Merge patch series "Add IPC support on MCU R5F cluster in Split Mode"

Beleswar Padhi <b-padhi@ti.com> says: This series adds remoteproc support on MCU R5F in Split mode. During boot, ROM can bring up the boot R5F cores in either lockstep or split mode based on X509 certificate flags. If booted in lockstep mode, the MCU R5F cores will run first the R5 SPL, and then once A72 comes up, will run the Device Manager (DM) firmware. But if booted in split mode, core 0 will run DM firmware and second core sits in WFI. Shut it down so that other firmwares can later be loaded on them. The shutdown of MCU R5 Core 1 is invoked at A72 SPL init, as by that time Device Manager (DM) is up and running on R5 Core 0. The shutdown of MCU R5 Core 1 is handled by Device Manager itself. Test logs: https://gist.github.com/3V3RYONE/ee8e3cb9aa5f4c5c00b059b9c14bfa98 Link: https://lore.kernel.org/r/20250609081429.1724643-1-b-padhi@ti.com
2026-06-13 15:03:58 +03:00 · 2025-06-18 12:16:50 -06:00
parent 009d7722ff 574321414f
commit 6226bfa41a
19 changed files with 136 additions and 34 deletions
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -31,6 +31,11 @@
 #include <dm/uclass-internal.h>
 #include <dm/device-internal.h>

+#define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT	0x00000001
+#define PROC_BOOT_STATUS_FLAG_R5_WFI		0x00000002
+#define PROC_ID_MCU_R5FSS0_CORE1		0x02
+#define PROC_BOOT_CFG_FLAG_R5_LOCKSTEP		0x00000100
+
 #include <asm/arch/k3-qos.h>

 struct ti_sci_handle *get_ti_sci_handle(void)
@@ -338,3 +343,67 @@ void setup_qos(void)
 		writel(qos_data[i].val, (uintptr_t)qos_data[i].reg);
 }
 #endif
+
+int __maybe_unused shutdown_mcu_r5_core1(void)
+{
+	struct ti_sci_handle *ti_sci = get_ti_sci_handle();
+	struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
+	struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
+	u32 dev_id_mcu_r5_core1 = put_core_ids[0];
+	u64 boot_vector;
+	u32 cfg, ctrl, sts, halted;
+	int cluster_mode_lockstep, ret;
+	bool r_state = false, c_state = false;
+
+	ret = proc_ops->proc_request(ti_sci, PROC_ID_MCU_R5FSS0_CORE1);
+	if (ret) {
+		printf("Unable to request processor control for MCU1_1 core, %d\n",
+		       ret);
+		return ret;
+	}
+
+	ret = dev_ops->is_on(ti_sci, dev_id_mcu_r5_core1, &r_state, &c_state);
+	if (ret) {
+		printf("Unable to get device status for MCU1_1 core, %d\n", ret);
+		return ret;
+	}
+
+	ret = proc_ops->get_proc_boot_status(ti_sci, PROC_ID_MCU_R5FSS0_CORE1,
+					     &boot_vector, &cfg, &ctrl, &sts);
+	if (ret) {
+		printf("Unable to get Processor boot status for MCU1_1 core, %d\n",
+		       ret);
+		goto release_proc_ctrl;
+	}
+
+	halted = !!(sts & PROC_BOOT_STATUS_FLAG_R5_WFI);
+	cluster_mode_lockstep = !!(cfg & PROC_BOOT_CFG_FLAG_R5_LOCKSTEP);
+
+	/*
+	 * Shutdown MCU R5F Core 1 only if:
+	 *	- cluster is booted in SplitMode
+	 *	- core is powered on
+	 *	- core is in WFI (halted)
+	 */
+	if (cluster_mode_lockstep || !c_state || !halted) {
+		ret = -EINVAL;
+		goto release_proc_ctrl;
+	}
+
+	ret = proc_ops->set_proc_boot_ctrl(ti_sci, PROC_ID_MCU_R5FSS0_CORE1,
+					   PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0);
+	if (ret) {
+		printf("Unable to Halt MCU1_1 core, %d\n", ret);
+		goto release_proc_ctrl;
+	}
+
+	ret = dev_ops->put_device(ti_sci, dev_id_mcu_r5_core1);
+	if (ret) {
+		printf("Unable to assert reset on MCU1_1 core, %d\n", ret);
+		return ret;
+	}
+
+release_proc_ctrl:
+	proc_ops->proc_release(ti_sci, PROC_ID_MCU_R5FSS0_CORE1);
+	return ret;
+}
--- a/arch/arm/mach-k3/common.h
+++ b/arch/arm/mach-k3/common.h
@@ -49,6 +49,7 @@ enum k3_device_type get_device_type(void);
 struct ti_sci_handle *get_ti_sci_handle(void);
 void do_board_detect(void);
 void ti_secure_image_check_binary(void **p_image, size_t *p_size);
+int shutdown_mcu_r5_core1(void);

 #if (IS_ENABLED(CONFIG_K3_QOS))
 void setup_qos(void);
--- a/arch/arm/mach-k3/include/mach/am62_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am62_hardware.h
@@ -177,8 +177,8 @@ static inline int k3_has_gpu(void)

 static const u32 put_device_ids[] = {};

-static const u32 put_core_ids[] = {};
-
 #endif

+static const u32 put_core_ids[] = {};
+
 #endif /* __ASM_ARCH_AM62_HARDWARE_H */
--- a/arch/arm/mach-k3/include/mach/am62a_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am62a_hardware.h
@@ -90,8 +90,8 @@

 static const u32 put_device_ids[] = {};

-static const u32 put_core_ids[] = {};
-
 #endif

+static const u32 put_core_ids[] = {};
+
 #endif /* __ASM_ARCH_AM62A_HARDWARE_H */
--- a/arch/arm/mach-k3/include/mach/am62p_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am62p_hardware.h
@@ -141,8 +141,8 @@ static inline int k3_get_a53_max_frequency(void)

 static const u32 put_device_ids[] = {};

-static const u32 put_core_ids[] = {};
-
 #endif

+static const u32 put_core_ids[] = {};
+
 #endif /* __ASM_ARCH_AM62P_HARDWARE_H */
--- a/arch/arm/mach-k3/include/mach/am64_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am64_hardware.h
@@ -50,19 +50,20 @@

 #define AM64X_DEV_RTI8			127
 #define AM64X_DEV_RTI9			128
-#define AM64X_DEV_R5FSS0_CORE0		121
-#define AM64X_DEV_R5FSS0_CORE1		122

 static const u32 put_device_ids[] = {
 	AM64X_DEV_RTI9,
 	AM64X_DEV_RTI8,
 };

+#endif
+
+#define AM64X_DEV_R5FSS0_CORE0		121
+#define AM64X_DEV_R5FSS0_CORE1		122
+
 static const u32 put_core_ids[] = {
 	AM64X_DEV_R5FSS0_CORE1,
 	AM64X_DEV_R5FSS0_CORE0, /* Handle CPU0 after CPU1 */
 };

-#endif
-
 #endif /* __ASM_ARCH_DRA8_HARDWARE_H */
--- a/arch/arm/mach-k3/include/mach/am6_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am6_hardware.h
@@ -43,19 +43,20 @@

 #define AM6_DEV_MCU_RTI0			134
 #define AM6_DEV_MCU_RTI1			135
-#define AM6_DEV_MCU_ARMSS0_CPU0			159
-#define AM6_DEV_MCU_ARMSS0_CPU1			245

 static const u32 put_device_ids[] = {
 	AM6_DEV_MCU_RTI0,
 	AM6_DEV_MCU_RTI1,
 };

+#endif
+
+#define AM6_DEV_MCU_ARMSS0_CPU0			159
+#define AM6_DEV_MCU_ARMSS0_CPU1			245
+
 static const u32 put_core_ids[] = {
 	AM6_DEV_MCU_ARMSS0_CPU1,
 	AM6_DEV_MCU_ARMSS0_CPU0,	/* Handle CPU0 after CPU1 */
 };

-#endif
-
 #endif /* __ASM_ARCH_AM6_HARDWARE_H */
--- a/arch/arm/mach-k3/include/mach/j721e_hardware.h
+++ b/arch/arm/mach-k3/include/mach/j721e_hardware.h
@@ -41,19 +41,20 @@

 #define J721E_DEV_MCU_RTI0			262
 #define J721E_DEV_MCU_RTI1			263
-#define J721E_DEV_MCU_ARMSS0_CPU0		250
-#define J721E_DEV_MCU_ARMSS0_CPU1		251

 static const u32 put_device_ids[] = {
 	J721E_DEV_MCU_RTI0,
 	J721E_DEV_MCU_RTI1,
 };

+#endif
+
+#define J721E_DEV_MCU_ARMSS0_CPU0		250
+#define J721E_DEV_MCU_ARMSS0_CPU1		251
+
 static const u32 put_core_ids[] = {
 	J721E_DEV_MCU_ARMSS0_CPU1,
 	J721E_DEV_MCU_ARMSS0_CPU0,	/* Handle CPU0 after CPU1 */
 };

-#endif
-
 #endif /* __ASM_ARCH_J721E_HARDWARE_H */
--- a/arch/arm/mach-k3/include/mach/j721s2_hardware.h
+++ b/arch/arm/mach-k3/include/mach/j721s2_hardware.h
@@ -41,19 +41,20 @@

 #define J721S2_DEV_MCU_RTI0			295
 #define J721S2_DEV_MCU_RTI1			296
-#define J721S2_DEV_MCU_ARMSS0_CPU0		284
-#define J721S2_DEV_MCU_ARMSS0_CPU1		285

 static const u32 put_device_ids[] = {
 	J721S2_DEV_MCU_RTI0,
 	J721S2_DEV_MCU_RTI1,
 };

+#endif
+
+#define J721S2_DEV_MCU_ARMSS0_CPU0		284
+#define J721S2_DEV_MCU_ARMSS0_CPU1		285
+
 static const u32 put_core_ids[] = {
 	J721S2_DEV_MCU_ARMSS0_CPU1,
 	J721S2_DEV_MCU_ARMSS0_CPU0,	/* Handle CPU0 after CPU1 */
 };

-#endif
-
 #endif /* __ASM_ARCH_J721S2_HARDWARE_H */
--- a/arch/arm/mach-k3/include/mach/j722s_hardware.h
+++ b/arch/arm/mach-k3/include/mach/j722s_hardware.h
@@ -76,8 +76,8 @@

 static const u32 put_device_ids[] = {};

-static const u32 put_core_ids[] = {};
-
 #endif

+static const u32 put_core_ids[] = {};
+
 #endif /* __ASM_ARCH_J722S_HARDWARE_H */
--- a/arch/arm/mach-k3/include/mach/j784s4_hardware.h
+++ b/arch/arm/mach-k3/include/mach/j784s4_hardware.h
@@ -41,19 +41,20 @@

 #define J784S4_DEV_MCU_RTI0			367
 #define J784S4_DEV_MCU_RTI1			368
-#define J784S4_DEV_MCU_ARMSS0_CPU0		346
-#define J784S4_DEV_MCU_ARMSS0_CPU1		347

 static const u32 put_device_ids[] = {
 	J784S4_DEV_MCU_RTI0,
 	J784S4_DEV_MCU_RTI1,
 };

+#endif
+
+#define J784S4_DEV_MCU_ARMSS0_CPU0		346
+#define J784S4_DEV_MCU_ARMSS0_CPU1		347
+
 static const u32 put_core_ids[] = {
 	J784S4_DEV_MCU_ARMSS0_CPU1,
 	J784S4_DEV_MCU_ARMSS0_CPU0,     /* Handle CPU0 after CPU1 */
 };

-#endif
-
 #endif /* __ASM_ARCH_J784S4_HARDWARE_H */
--- a/arch/arm/mach-k3/j721e/j721e_init.c
+++ b/arch/arm/mach-k3/j721e/j721e_init.c
@@ -296,9 +296,9 @@ void do_dt_magic(void)

 void board_init_f(ulong dummy)
 {
+	int ret;
 #if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW)
 	struct udevice *dev;
-	int ret;
 #endif
 	/*
 	 * Cannot delay this further as there is a chance that
@@ -371,6 +371,13 @@ void board_init_f(ulong dummy)
 	preloader_console_init();
 #endif

+	/* Shutdown MCU_R5 Core 1 in Split mode at A72 SPL Stage */
+	if (IS_ENABLED(CONFIG_ARM64)) {
+		ret = shutdown_mcu_r5_core1();
+		if (ret)
+			printf("Unable to shutdown MCU R5 core 1, %d\n", ret);
+	}
+
 	/* Output System Firmware version info */
 	k3_sysfw_print_ver();

--- a/arch/arm/mach-k3/j721s2/j721s2_init.c
+++ b/arch/arm/mach-k3/j721s2/j721s2_init.c
@@ -230,6 +230,13 @@ void k3_spl_init(void)
 		remove_fwl_configs(navss_cbass0_fwls, ARRAY_SIZE(navss_cbass0_fwls));
 	}

+	/* Shutdown MCU_R5 Core 1 in Split mode at A72 SPL Stage */
+	if (IS_ENABLED(CONFIG_ARM64)) {
+		ret = shutdown_mcu_r5_core1();
+		if (ret)
+			printf("Unable to shutdown MCU R5 core 1, %d\n", ret);
+	}
+
 	/* Output System Firmware version info */
 	k3_sysfw_print_ver();
 }
--- a/arch/arm/mach-k3/j784s4/j784s4_init.c
+++ b/arch/arm/mach-k3/j784s4/j784s4_init.c
@@ -206,6 +206,13 @@ void k3_spl_init(void)

 	writel(AUDIO_REFCLK1_DEFAULT, (uintptr_t)CTRL_MMR_CFG0_AUDIO_REFCLK1_CTRL);

+	/* Shutdown MCU_R5 Core 1 in Split mode at A72 SPL Stage */
+	if (IS_ENABLED(CONFIG_ARM64)) {
+		ret = shutdown_mcu_r5_core1();
+		if (ret)
+			printf("Unable to shutdown MCU R5 core 1, %d\n", ret);
+	}
+
 	/* Output System Firmware version info */
 	k3_sysfw_print_ver();
 }
--- a/board/ti/j7200/j7200.env
+++ b/board/ti/j7200/j7200.env
@@ -36,5 +36,5 @@ main_cpsw0_qsgmii_phyinit=
 #endif

 #if CONFIG_TARGET_J7200_A72_EVM
-rproc_fw_binaries=2 /lib/firmware/j7200-main-r5f0_0-fw 3 /lib/firmware/j7200-main-r5f0_1-fw
+rproc_fw_binaries= 1 /lib/firmware/j7200-mcu-r5f0_1-fw 2 /lib/firmware/j7200-main-r5f0_0-fw 3 /lib/firmware/j7200-main-r5f0_1-fw
 #endif
--- a/board/ti/j721e/j721e.env
+++ b/board/ti/j721e/j721e.env
@@ -38,5 +38,5 @@ main_cpsw0_qsgmii_phyinit=
 #endif

 #if CONFIG_TARGET_J721E_A72_EVM
-rproc_fw_binaries=2 /lib/firmware/j7-main-r5f0_0-fw 3 /lib/firmware/j7-main-r5f0_1-fw 4 /lib/firmware/j7-main-r5f1_0-fw 5 /lib/firmware/j7-main-r5f1_1-fw 6 /lib/firmware/j7-c66_0-fw 7 /lib/firmware/j7-c66_1-fw 8 /lib/firmware/j7-c71_0-fw
+rproc_fw_binaries= 1 /lib/firmware/j7-mcu-r5f0_1-fw 2 /lib/firmware/j7-main-r5f0_0-fw 3 /lib/firmware/j7-main-r5f0_1-fw 4 /lib/firmware/j7-main-r5f1_0-fw 5 /lib/firmware/j7-main-r5f1_1-fw 6 /lib/firmware/j7-c66_0-fw 7 /lib/firmware/j7-c66_1-fw 8 /lib/firmware/j7-c71_0-fw
 #endif
--- a/board/ti/j721s2/j721s2.env
+++ b/board/ti/j721s2/j721s2.env
@@ -24,6 +24,6 @@ name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw
 #endif
 rd_spec=-

-rproc_fw_binaries= 2 /lib/firmware/j721s2-main-r5f0_0-fw 3 /lib/firmware/j721s2-main-r5f0_1-fw 4 /lib/firmware/j721s2-main-r5f1_0-fw 5 /lib/firmware/j721s2-main-r5f1_1-fw 6 /lib/firmware/j721s2-c71_0-fw 7 /lib/firmware/j721s2-c71_1-fw
+rproc_fw_binaries= 1 /lib/firmware/j721s2-mcu-r5f0_1-fw 2 /lib/firmware/j721s2-main-r5f0_0-fw 3 /lib/firmware/j721s2-main-r5f0_1-fw 4 /lib/firmware/j721s2-main-r5f1_0-fw 5 /lib/firmware/j721s2-main-r5f1_1-fw 6 /lib/firmware/j721s2-c71_0-fw 7 /lib/firmware/j721s2-c71_1-fw


--- a/board/ti/j784s4/j784s4.env
+++ b/board/ti/j784s4/j784s4.env
@@ -21,7 +21,7 @@ bootdir=/boot
 rd_spec=-

 #if CONFIG_TARGET_J784S4_A72_EVM
-rproc_fw_binaries= 2 /lib/firmware/j784s4-main-r5f0_0-fw 3 /lib/firmware/j784s4-main-r5f0_1-fw 4 /lib/firmware/j784s4-main-r5f1_0-fw 5 /lib/firmware/j784s4-main-r5f1_1-fw 6 /lib/firmware/j784s4-main-r5f2_0-fw 7 /lib/firmware/j784s4-main-r5f2_1-fw 8 /lib/firmware/j784s4-c71_0-fw 9 /lib/firmware/j784s4-c71_1-fw 10 /lib/firmware/j784s4-c71_2-fw 11 /lib/firmware/j784s4-c71_3-fw
+rproc_fw_binaries= 1 /lib/firmware/j784s4-mcu-r5f0_1-fw 2 /lib/firmware/j784s4-main-r5f0_0-fw 3 /lib/firmware/j784s4-main-r5f0_1-fw 4 /lib/firmware/j784s4-main-r5f1_0-fw 5 /lib/firmware/j784s4-main-r5f1_1-fw 6 /lib/firmware/j784s4-main-r5f2_0-fw 7 /lib/firmware/j784s4-main-r5f2_1-fw 8 /lib/firmware/j784s4-c71_0-fw 9 /lib/firmware/j784s4-c71_1-fw 10 /lib/firmware/j784s4-c71_2-fw 11 /lib/firmware/j784s4-c71_3-fw
 #elif CONFIG_TARGET_J742S2_A72_EVM
-rproc_fw_binaries= 2 /lib/firmware/j742s2-main-r5f0_0-fw 3 /lib/firmware/j742s2-main-r5f0_1-fw 4 /lib/firmware/j742s2-main-r5f1_0-fw 5 /lib/firmware/j742s2-main-r5f1_1-fw 6 /lib/firmware/j742s2-main-r5f2_0-fw 7 /lib/firmware/j742s2-main-r5f2_1-fw 8 /lib/firmware/j742s2-c71_0-fw 9 /lib/firmware/j742s2-c71_1-fw 10 /lib/firmware/j742s2-c71_2-fw
+rproc_fw_binaries= 1 /lib/firmware/j742s2-mcu-r5f0_1-fw 2 /lib/firmware/j742s2-main-r5f0_0-fw 3 /lib/firmware/j742s2-main-r5f0_1-fw 4 /lib/firmware/j742s2-main-r5f1_0-fw 5 /lib/firmware/j742s2-main-r5f1_1-fw 6 /lib/firmware/j742s2-main-r5f2_0-fw 7 /lib/firmware/j742s2-main-r5f2_1-fw 8 /lib/firmware/j742s2-c71_0-fw 9 /lib/firmware/j742s2-c71_1-fw 10 /lib/firmware/j742s2-c71_2-fw
 #endif
--- a/drivers/remoteproc/ti_k3_r5f_rproc.c
+++ b/drivers/remoteproc/ti_k3_r5f_rproc.c
@@ -834,8 +834,14 @@ static int k3_r5f_probe(struct udevice *dev)
 			return 0;
 		}

+		ret = k3_r5f_proc_request(core);
+		if (ret)
+			return ret;
+
 		/* Make sure Local reset is asserted. Redundant? */
 		reset_assert(&core->reset);
+
+		ti_sci_proc_release(&core->tsp);
 	}

 	ret = k3_r5f_rproc_configure(core);