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clk: rockchip: rk3568: Fix mask for clk_cpll_div_25m_div

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The field for clk_cpll_div_25m_div in CRU_CLKSEL_CON81 is 6 bits wide,
not 5 bits wide as currently defined in CPLL_25M_DIV_MASK.

Fix this and the assert so that CPLL_25M can be assigned a 25 MHz rate.

Fixes: 4a262feba3 ("rockchip: rk3568: add clock driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Jonas Karlman
2023-08-04 09:33:59 +00:00
committed by Kever Yang
parent acb9812034
commit 6da8400d7a
2 changed files with 5 additions and 2 deletions
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2
arch/arm/include/asm/arch-rockchip/cru_rk3568.h
View File

@@ -495,7 +495,7 @@ enum {
/* CRU_CLK_SEL81_CON */
CPLL_25M_DIV_SHIFT = 8,
CPLL_25M_DIV_MASK = 0x1f << CPLL_25M_DIV_SHIFT,
CPLL_25M_DIV_MASK = 0x3f << CPLL_25M_DIV_SHIFT,
CPLL_50M_DIV_SHIFT = 0,
CPLL_50M_DIV_MASK = 0x1f << CPLL_50M_DIV_SHIFT,

5
drivers/clk/rockchip/clk_rk3568.c
View File

@@ -702,7 +702,10 @@ static ulong rk3568_cpll_div_set_rate(struct rk3568_clk_priv *priv,
}
div = DIV_ROUND_UP(priv->cpll_hz, rate);
assert(div - 1 <= 31);
if (clk_id == CPLL_25M)
assert(div - 1 <= 63);
else
assert(div - 1 <= 31);
rk_clrsetreg(&cru->clksel_con[con],
mask, (div - 1) << shift);
return rk3568_cpll_div_get_rate(priv, clk_id);