Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh

Fixes for newer revision of Retronix R-Car V4H Sparrow Hawk and fixes
for boards which enable POSITION_INDEPENDENT and also set non-zero
CONFIG_TEXT_BASE.

arch/arm/dts/r8a779g3-sparrow-hawk-u-boot.dtsi

@@ -7,6 +7,13 @@
 
 #include "r8a779g0-u-boot.dtsi"
 
+&avb0_pins {
+	pins-vddq18-25-avb {
+		pins = "PIN_VDDQ_AVB0", "PIN_VDDQ_AVB1", "PIN_VDDQ_AVB2", "PIN_VDDQ_TSN0";
+		power-source = <1800>;
+	};
+};
+
 /* Page 31 / FAN */
 &gpio1 {
 	pwm-fan-hog {
@@ -44,7 +51,16 @@
 
 &rpc {
 	flash@0 {
+		/*
+		 * EVTA1 is populated with Spansion S25FS512S
+		 * EVTB1 is populated with Winbond W77Q51NW
+		 */
+		compatible = "jedec,spi-nor";
 		spi-tx-bus-width = <1>;
 		spi-rx-bus-width = <1>;
 	};
 };
+
+&vcc_sdhi {
+	states = <1800000 0>, <3300000 1>;
+};

board/renesas/sparrowhawk/sparrowhawk.c

@@ -6,8 +6,12 @@
 #include <asm/io.h>
 #include <compiler.h>
 #include <dbsc5.h>
+#include <spi.h>
+#include <spi_flash.h>
 #include <spl.h>
 
+#include "../../../drivers/mtd/spi/sf_internal.h"
+
 #if defined(CONFIG_XPL_BUILD)
 
 static const struct renesas_dbsc5_board_config
@@ -112,12 +116,134 @@ dbsc5_get_board_data(struct udevice *dev, const u32 modemr0)
 	 * Use MD[19] setting to discern 8 GiB and 16 GiB DRAM Sparrow Hawk
 	 * board variants from each other automatically.
 	 */
-	if (modemr0 & BIT(19))
+	if ((renesas_get_cpu_rev_integer() >= 3) && (modemr0 & BIT(19)))
 		return &renesas_v4h_sparrowhawk_16g_5500_dbsc5_board_config;
 	else
 		return &renesas_v4h_sparrowhawk_8g_6400_dbsc5_board_config;
 }
 
+static bool renesas_v4h_sparrowhawk_is_evta1 = false;
+
+unsigned int spl_spi_get_uboot_offs(struct spi_flash *flash)
+{
+	const u8 sf_ids_evta1[6] = { 0x01, 0x02, 0x20, 0x4d, 0x00, 0x81 };
+
+	renesas_v4h_sparrowhawk_is_evta1 = !memcmp(sf_ids_evta1, flash->info->id,
+						   sizeof(sf_ids_evta1));
+
+	return CONFIG_SYS_SPI_U_BOOT_OFFS;
+}
+
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+	void *blob = spl_image_fdt_addr(spl_image);
+	int err, offs;
+	u32 size;
+
+	if (!renesas_v4h_sparrowhawk_is_evta1)
+		return;
+
+	printf("EVTA1 board detected\n");
+
+	/*
+	 * MicroSD voltage switch is not populated on Sparrow Hawk EVTA1,
+	 * rewrite MicroSD slot regulator to only support 3V3 and disable
+	 * UHS modes in MicroSD slot node.
+	 */
+	if (!blob)
+		return;
+
+	err = fdt_check_header(blob);
+	if (err < 0) {
+		printf("Invalid FDT header: %s\n", fdt_strerror(err));
+		return;
+	}
+
+	size = fdt_totalsize(blob);
+	err = fdt_open_into(blob, blob, size + 64);
+	if (err < 0) {
+		printf("Failed to expand DT\n");
+		return;
+	}
+
+	offs = fdt_path_offset(blob, "/regulator-vcc-sdhi");
+	if (offs < 0) {
+		printf("Failed to locate MicroSD regulator node: %d\n", offs);
+		return;
+	}
+
+	err = fdt_setprop_string(blob, offs, "compatible", "regulator-fixed");
+	if (err < 0) {
+		printf("Failed to set fixed MicroSD regulator: %d\n", err);
+		return;
+	}
+
+	err = fdt_setprop_u32(blob, offs, "regulator-min-microvolt", 3300000);
+	if (err < 0) {
+		printf("Failed to set MicroSD regulator minimum voltage: %d\n", err);
+		return;
+	}
+
+	err = fdt_nop_property(blob, offs, "gpios");
+	if (err < 0) {
+		printf("Failed to remove MicroSD regulator gpios: %d\n", err);
+		return;
+	}
+
+	err = fdt_nop_property(blob, offs, "gpios-states");
+	if (err < 0) {
+		printf("Failed to remove MicroSD regulator gpio states: %d\n", err);
+		return;
+	}
+
+	err = fdt_nop_property(blob, offs, "states");
+	if (err < 0) {
+		printf("Failed to remove MicroSD regulator states: %d\n", err);
+		return;
+	}
+
+	offs = fdt_path_offset(blob, "/soc/mmc@ee140000");
+	if (offs < 0) {
+		printf("Failed to locate MicroSD device node: %d\n", offs);
+		return;
+	}
+
+	err = fdt_nop_property(blob, offs, "sd-uhs-sdr50");
+	if (err < 0) {
+		printf("Failed to disable SDR50 mode in MicroSD node: %d\n", err);
+		return;
+	}
+
+	err = fdt_nop_property(blob, offs, "sd-uhs-sdr104");
+	if (err < 0) {
+		printf("Failed to disable SDR104 mode in MicroSD node: %d\n", err);
+		return;
+	}
+
+	err = fdt_setprop_string(blob, offs, "pinctrl-names", "default");
+	if (err < 0) {
+		printf("Failed to set fixed MicroSD pin names: %d\n", err);
+		return;
+	}
+
+	err = fdt_nop_property(blob, offs, "pinctrl-1");
+	if (err < 0) {
+		printf("Failed to disable UHS pins in MicroSD node: %d\n", err);
+		return;
+	}
+
+	offs = fdt_path_offset(blob, "/soc/pinctrl@e6050000/avb0/pins-vddq18-25-avb");
+	if (offs < 0) {
+		printf("Failed to locate AVB pinctrl node: %d\n", offs);
+		return;
+	}
+
+	err = fdt_setprop_u32(blob, offs, "power-source", 2500);
+	if (err < 0) {
+		printf("Failed to set AVB IO voltage: %d\n", err);
+		return;
+	}
+}
 #endif
 
 #define RST_MODEMR0			0xe6160000
@@ -130,7 +256,7 @@ void renesas_dram_init_banksize(void)
 	int bank;
 
 	/* 8 GiB device, do nothing. */
-	if (!(modemr0 & BIT(19)))
+	if (!((renesas_get_cpu_rev_integer() >= 3) && (modemr0 & BIT(19))))
 		return;
 
 	/* 16 GiB device, adjust memory map. */

configs/hihope_rzg2_defconfig

@@ -5,7 +5,6 @@ CONFIG_ARCH_RENESAS=y
 CONFIG_RCAR_GEN3=y
 CONFIG_COUNTER_FREQUENCY=16666666
 CONFIG_ARCH_CPU_INIT=y
-CONFIG_TEXT_BASE=0x50000000
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0xFFFE0000
 CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a774a1-hihope-rzg2m-ex"

configs/r8a77970_eagle_defconfig

@@ -5,7 +5,6 @@ CONFIG_ARCH_RENESAS=y
 CONFIG_RCAR_GEN3=y
 CONFIG_COUNTER_FREQUENCY=16666666
 CONFIG_ARCH_CPU_INIT=y
-CONFIG_TEXT_BASE=0x50000000
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x700000

configs/r8a77970_v3msk_defconfig

@@ -5,7 +5,6 @@ CONFIG_ARCH_RENESAS=y
 CONFIG_RCAR_GEN3=y
 CONFIG_COUNTER_FREQUENCY=16666666
 CONFIG_ARCH_CPU_INIT=y
-CONFIG_TEXT_BASE=0x50000000
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x700000

configs/r8a77990_ebisu_defconfig

@@ -5,7 +5,6 @@ CONFIG_ARCH_RENESAS=y
 CONFIG_RCAR_GEN3=y
 CONFIG_COUNTER_FREQUENCY=16666666
 CONFIG_ARCH_CPU_INIT=y
-CONFIG_TEXT_BASE=0x50000000
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0xFFFE0000

configs/r8a77995_draak_defconfig

@@ -5,7 +5,6 @@ CONFIG_ARCH_RENESAS=y
 CONFIG_RCAR_GEN3=y
 CONFIG_COUNTER_FREQUENCY=16666666
 CONFIG_ARCH_CPU_INIT=y
-CONFIG_TEXT_BASE=0x50000000
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0xFFFE0000

configs/r8a779a0_falcon_defconfig

@@ -4,7 +4,6 @@ CONFIG_ARM=y
 CONFIG_ARCH_RENESAS=y
 CONFIG_RCAR_GEN4=y
 CONFIG_COUNTER_FREQUENCY=16666666
-CONFIG_TEXT_BASE=0x50000000
 CONFIG_ENV_SIZE=0x40000
 CONFIG_ENV_OFFSET=0xC00000
 CONFIG_ENV_SECT_SIZE=0x40000

configs/r8a779g3_sparrowhawk_defconfig

@@ -25,6 +25,7 @@ CONFIG_GPIO_HOG=y
 CONFIG_REMOTEPROC_RENESAS_APMU=y
 CONFIG_BITBANGMII=y
 CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NVME_PCI=y
 CONFIG_PCI=y
@@ -34,6 +35,14 @@ CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_RENESAS_RAVB=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_XHCI_GENERIC=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
+# CONFIG_USB_XHCI_RCAR is not set
 
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_HAVE_INIT_STACK=y

configs/renesas_rzg2l_smarc_defconfig

@@ -3,7 +3,6 @@ CONFIG_COUNTER_FREQUENCY=16666666
 CONFIG_SYS_INIT_SP_BSS_OFFSET=1048576
 CONFIG_ARCH_CPU_INIT=y
 CONFIG_ARCH_RENESAS=y
-CONFIG_TEXT_BASE=0x50000000
 CONFIG_SYS_MALLOC_LEN=0x4000000
 CONFIG_SYS_MALLOC_F_LEN=0x80000
 CONFIG_ENV_SIZE=0x20000

configs/rzg2_beacon_defconfig

@@ -3,7 +3,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_RENESAS=y
 CONFIG_RCAR_GEN3=y
-CONFIG_TEXT_BASE=0x50000000
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFE000

configs/silinux_ek874_defconfig

@@ -5,7 +5,6 @@ CONFIG_ARCH_RENESAS=y
 CONFIG_RCAR_GEN3=y
 CONFIG_COUNTER_FREQUENCY=16666666
 CONFIG_ARCH_CPU_INIT=y
-CONFIG_TEXT_BASE=0x50000000
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x3F0000

drivers/pci/pci-rcar-gen4.c

@@ -235,7 +235,7 @@ static int rcar_gen4_pcie_ltssm_control(struct rcar_gen4_pcie *rcar, bool enable
 	clrsetbits_le32(rcar->phy_base + 0x148, GENMASK(23, 22), BIT(22));
 	clrsetbits_le32(rcar->phy_base + 0x148, GENMASK(18, 16), GENMASK(17, 16));
 	clrsetbits_le32(rcar->phy_base + 0x148, GENMASK(7, 6), BIT(6));
-	clrsetbits_le32(rcar->phy_base + 0x148, GENMASK(2, 0), GENMASK(11, 0));
+	clrsetbits_le32(rcar->phy_base + 0x148, GENMASK(2, 0), GENMASK(1, 0));
 	clrsetbits_le32(rcar->phy_base + 0x1d4, GENMASK(16, 15), GENMASK(16, 15));
 	clrsetbits_le32(rcar->phy_base + 0x514, BIT(26), BIT(26));
 	clrsetbits_le32(rcar->phy_base + 0x0f8, BIT(16), 0);