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Merge commit '3c9bb8fbdc77f6bd56e97597d875d8965db3b96c' of https://github.com/tienfong/uboot_mainline

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A few small SoCFPGA updates
This commit is contained in:
Tom Rini
2024-01-22 09:35:38 -05:00
parent 22aeab2d96 3c9bb8fbdc
commit 79a9697894
3 changed files with 20 additions and 5 deletions
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4
arch/arm/dts/socfpga_agilex.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019, Intel Corporation
* Copyright (C) 2019-2023 Intel Corporation <www.intel.com>
*/
/dts-v1/;
@@ -20,7 +20,7 @@
service_reserved: svcbuffer@0 {
compatible = "shared-dma-pool";
reg = <0x0 0x0 0x0 0x1000000>;
reg = <0x0 0x0 0x0 0x2000000>;
alignment = <0x1000>;
no-map;
};

17
arch/arm/mach-socfpga/clock_manager_s10.c
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@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
* Copyright (C) 2016-2023 Intel Corporation <www.intel.com>
*
*/
@@ -399,6 +399,21 @@ unsigned int cm_get_l4_sys_free_clk_hz(void)
return cm_get_l3_main_clk_hz() / 4;
}
/*
* Override weak dw_spi_get_clk implementation in designware_spi.c driver
*/
int dw_spi_get_clk(struct udevice *bus, ulong *rate)
{
*rate = cm_get_spi_controller_clk_hz();
if (!*rate) {
printf("SPI: clock rate is zero");
return -EINVAL;
}
return 0;
}
void cm_print_clock_quick_summary(void)
{
printf("MPU %d kHz\n", (u32)(cm_get_mpu_clk_hz() / 1000));

4
drivers/clk/altera/clk-mem-n5x.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
* Copyright (C) 2020-2022 Intel Corporation <www.intel.com>
* Copyright (C) 2020-2023 Intel Corporation <www.intel.com>
*/
#ifndef _CLK_MEM_N5X_
@@ -77,7 +77,7 @@
#define MEMCLKMGR_PLLOUTDIV_C0CNT_MASK GENMASK(4, 0)
#define MEMCLKMGR_PLLOUTDIV_C0CNT_OFFSET 0
#define MEMCLKMGR_EXTCNTRST_C0CNTRST BIT(7)
#define MEMCLKMGR_EXTCNTRST_C0CNTRST BIT(0)
#define MEMCLKMGR_EXTCNTRST_ALLCNTRST \
(MEMCLKMGR_EXTCNTRST_C0CNTRST)