Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh

This is Renesas R-Car X5H support for U-Boot on its RSIP Cortex-M33 core in addition to already support U-Boot on Cortex-A720AE core. The first two patches also switch X5H to OF_UPSTREAM.
2026-06-02 09:46:37 +03:00 · 2026-05-22 13:30:42 -06:00
parent 744cf5d4e3 9d47a5a4d5
commit 987c93fc68
25 changed files with 5146 additions and 1543 deletions
--- a/3
+++ b/3
@@ -1578,6 +1578,9 @@ spl/u-boot-spl.srec: spl/u-boot-spl FORCE
 %.scif: %.srec
 	$(Q)$(MAKE) $(build)=arch/arm/mach-renesas $@

+%.shdr: %.srec
+	$(Q)$(MAKE) $(build)=arch/arm/mach-renesas $@
+
 OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
 		$(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \
 		$(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),$(if $(CONFIG_OF_SEPARATE),-R .bootpg -R .resetvec))
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -900,11 +900,7 @@ dtb-$(CONFIG_RZA1) += \
 	r7s72100-gr-peach.dtb

 dtb-$(CONFIG_RCAR_GEN5) += \
-	r8a78000-ironhide.dtb
-
-ifdef CONFIG_RCAR_GEN5
-DTC_FLAGS += -R 4 -p 0x1000
-endif
+	r8a78000-ironhide-cm33.dtb

 dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb

--- a/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi
+++ b/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi
@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source extras for U-Boot for the Ironhide CM33 board
+ *
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ */
+
+#include "r8a78000-ironhide-u-boot.dtsi"
+
+/ {
+	model = "Renesas Ironhide board CM33 based on r8a78000";
+	compatible = "renesas,ironhide-cm33", "renesas,r8a78000-cm33";
+
+	aliases {
+		serial1 = &hscif1;
+	};
+
+	chosen {
+		stdout-path = "serial1:1843200n8";
+	};
+
+	/delete-node/ firmware;
+	/delete-node/ memory@40000000;
+	/delete-node/ memory@60600000;
+	/delete-node/ memory@1080000000;
+	/delete-node/ memory@1200000000;
+	/delete-node/ memory@1400000000;
+	/delete-node/ memory@1600000000;
+	/delete-node/ memory@1800000000;
+	/delete-node/ memory@1a00000000;
+	/delete-node/ memory@1c00000000;
+	/delete-node/ memory@1e00000000;
+	/delete-node/ reserved-memory;
+
+	memory@b8400000 {
+		device_type = "memory";
+		reg = <0x0 0xb8400000 0x0 0x00200000>;
+	};
+
+	dummy_clk_rclk: dummy-clk-rclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+	};
+
+	dummy_clk_sasyncd4_rt: dummy-clk-sasyncd4-rt {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <16660000>;
+	};
+
+	ctl: syscon@5fffd000 {
+		compatible = "renesas,r8a78000-ctl",
+			     "renesas,rcar-gen5-ctl",
+			     "syscon";
+		reg = <0 0x5fffd000 0 0xc4>;
+	};
+
+	watchdog@5fffd800 {
+		compatible = "renesas,r8a78000-wwdt",
+			     "renesas,rcar-gen5-wwdt";
+		clocks = <&dummy_clk_rclk>, <&dummy_clk_sasyncd4_rt>;
+		clock-names = "cnt", "bus";
+		reg = <0 0x5fffd800 0 0x10>;
+		syscon = <&ctl>;
+	};
+
+	scp@c1340000 {
+		compatible = "renesas,r8a78000-rproc";
+		reg = <0 0xc1340000 0 0x80000>;
+	};
+};
+
+&cpg {
+	/delete-property/ firmware;
+};
+
+&eth_pcs {
+	/* Stub clock */
+	clocks = <&dummy_clk_rclk>;
+};
+
+&hscif1 {
+	pinctrl-0 = <&hscif1_pins>;
+	pinctrl-names = "default";
+	uart-has-rtscts;
+	status = "okay";
+};
+
+&mdlc_hscn {
+	/delete-property/ firmware;
+};
+
+&mdlc_pere {
+	/delete-property/ firmware;
+};
+
+&mmc0 {
+	status = "disabled";
+};
+
+&mp_phy {
+	/* Stub clock */
+	clocks = <&dummy_clk_rclk>;
+};
+
+&pfc {
+	hscif1_pins: hscif1 {
+		groups = "hscif1_data", "hscif1_ctrl";
+		function = "hscif1";
+	};
+};
+
+&rswitch3 {
+	/* Stub clock */
+	clocks = <&dummy_clk_rclk>;
+};
+
+&soc {
+	dma-ranges = <0 0x00000000 0 0xa0000000 0 0x20000000>;
+};
+
+&ufs0 {
+	/delete-property/ power-domains;
+};
+
+&ufs1 {
+	/delete-property/ power-domains;
+	status = "disabled";
+};
--- a/arch/arm/dts/r8a78000-ironhide-cm33.dts
+++ b/arch/arm/dts/r8a78000-ironhide-cm33.dts
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the Ironhide CM33 board
+ *
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ */
+
+#include "../../../dts/upstream/src/arm64/renesas/r8a78000-ironhide.dts"
--- a/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi
+++ b/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi
@@ -5,4 +5,190 @@
 * Copyright (C) 2025 Renesas Electronics Corp.
 */

+#include <dt-bindings/net/ti-dp83869.h>
 #include "r8a78000-u-boot.dtsi"
+
+/ {
+	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		mmc0 = &mmc0;
+	};
+
+	reg_1p8v: regulator-1p8v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+};
+
+&cpg {
+	firmware = <&scmi>;
+};
+
+&eth_pcs {
+	phys = <&mp_phy 2 1>;
+	status = "okay";
+};
+
+&hscif0 {
+	pinctrl-0 = <&hscif0_pins>;
+	pinctrl-names = "default";
+};
+
+&i2c0 {
+	pinctrl-0 = <&i2c0_pins>;
+	pinctrl-names = "default";
+	clock-frequency = <400000>;
+	status = "okay";
+
+	eeprom@50 {
+		compatible = "rohm,br24g01", "atmel,24c01";
+		reg = <0x50>;
+		pagesize = <8>;
+	};
+};
+
+&i2c1 {
+	pinctrl-0 = <&i2c1_pins>;
+	pinctrl-names = "default";
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&mdlc_hscn {
+	firmware = <&scmi>;
+};
+
+&mdlc_pere {
+	firmware = <&scmi>;
+};
+
+&mmc0 {
+	pinctrl-0 = <&mmc0_pins>;
+	pinctrl-1 = <&mmc0_pins>;
+	pinctrl-names = "default", "state_uhs";
+
+	bus-width = <8>;
+	full-pwr-cycle-in-suspend;
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
+	no-sd;
+	no-sdio;
+	non-removable;
+
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_1p8v>;
+
+	status = "okay";
+};
+
+&mp_phy {
+	status = "okay";
+};
+
+&pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
+	eth25g2_pins: eth25g2 {
+		groups = "eth25g2_mdio", "eth25g2_link", "eth25g2_phyint";
+		function = "eth25g2";
+		drive-strength = <24>;
+	};
+
+	ethes0_pins: ethes0 {
+		groups = "ethes0_match", "ethes0_capture", "ethes0_pps";
+		function = "ethes0";
+		drive-strength = <24>;
+	};
+
+	hscif0_pins: hscif0 {
+		groups = "hscif0_data", "hscif0_ctrl";
+		function = "hscif0";
+	};
+
+	i2c0_pins: i2c0 {
+		groups = "i2c0";
+		function = "i2c0";
+	};
+
+	i2c1_pins: i2c1 {
+		groups = "i2c1";
+		function = "i2c1";
+	};
+
+	mmc0_pins: mmc0 {
+		groups = "mmc0_data8", "mmc0_ctrl", "mmc0_ds";
+		function = "mmc0";
+		drive-strength = <24>;
+	};
+
+	rsw3_pins: rsw3 {
+		groups = "rsw3_match", "rsw3_capture", "rsw3_pps";
+		function = "rsw3";
+		drive-strength = <24>;
+	};
+
+	scif_clk_pins: scif-clk {
+		groups = "scif_clk";
+		function = "scif_clk";
+	};
+};
+
+&rswitch3 {
+	pinctrl-0 = <&rsw3_pins>, <&eth25g2_pins>, <&ethes0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	ethernet-ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/*
+		 * NOTE: Only port@4 is configured for R-Car X5H board.
+		 * Other ports (0-3, 5-12) are currently unused or not
+		 * connected.
+		 */
+		port@4 {
+			reg = <4>;
+			renesas,connect_to_xpcs;
+			phy-handle = <&dp83869_phy>;
+			phy-mode = "sgmii";
+			phys = <&eth_pcs 5>;
+
+			mdio {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				dp83869_phy: ethernet-phy@2 {
+					reg = <2>;
+					ti,sgmii-interface;
+					ti,max-output-impedance;
+					ti,refclk-output-enable;
+					ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>;
+				};
+			};
+		};
+	};
+};
+
+&ufs0 {
+	status = "okay";
+};
+
+&ufs1 {
+	status = "okay";
+};
--- a/arch/arm/dts/r8a78000-ironhide.dts
+++ b/arch/arm/dts/r8a78000-ironhide.dts
@@ -1,257 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Device Tree Source for the Ironhide board
- *
- * Copyright (C) 2025 Renesas Electronics Corp.
- */
-
-/dts-v1/;
-#include "r8a78000.dtsi"
-#include <dt-bindings/net/ti-dp83869.h>
-
-/ {
-	model = "Renesas Ironhide board based on r8a78000";
-	compatible = "renesas,ironhide", "renesas,r8a78000";
-
-	aliases {
-		i2c0 = &i2c0;
-		i2c1 = &i2c1;
-		i2c2 = &i2c2;
-		i2c3 = &i2c3;
-		i2c4 = &i2c4;
-		i2c5 = &i2c5;
-		i2c6 = &i2c6;
-		i2c7 = &i2c7;
-		i2c8 = &i2c8;
-		mmc0 = &mmc0;
-		serial0 = &hscif0;
-	};
-
-	chosen {
-		stdout-path = "serial0:1843200n8";
-	};
-
-	memory@40000000 {
-		device_type = "memory";
-		reg = <0x0 0x40000000 0x0 0x80000000>;
-	};
-
-	memory@1080000000 {
-		device_type = "memory";
-		reg = <0x10 0x80000000 0x0 0x80000000>;
-	};
-
-	memory@1200000000 {
-		device_type = "memory";
-		reg = <0x12 0x00000000 0x1 0x00000000>;
-	};
-
-	memory@1400000000 {
-		device_type = "memory";
-		reg = <0x14 0x00000000 0x1 0x00000000>;
-	};
-
-	memory@1600000000 {
-		device_type = "memory";
-		reg = <0x16 0x00000000 0x1 0x00000000>;
-	};
-
-	memory@1800000000 {
-		device_type = "memory";
-		reg = <0x18 0x00000000 0x1 0x00000000>;
-	};
-
-	memory@1a00000000 {
-		device_type = "memory";
-		reg = <0x1a 0x00000000 0x1 0x00000000>;
-	};
-
-	memory@1c00000000 {
-		device_type = "memory";
-		reg = <0x1c 0x00000000 0x1 0x00000000>;
-	};
-
-	memory@1e00000000 {
-		device_type = "memory";
-		reg = <0x1e 0x00000000 0x1 0x00000000>;
-	};
-
-	reg_1p8v: regulator-1p8v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-1.8V";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-};
-
-&extal_clk {
-	clock-frequency = <16666600>;
-};
-
-&extalr_clk {
-	clock-frequency = <32768>;
-};
-
-&hscif0 {
-	pinctrl-0 = <&hscif0_pins>;
-	pinctrl-names = "default";
-	uart-has-rtscts;
-	status = "okay";
-};
-
-&i2c0 {
-	pinctrl-0 = <&i2c0_pins>;
-	pinctrl-names = "default";
-	clock-frequency = <400000>;
-	status = "okay";
-
-	eeprom@50 {
-		compatible = "rohm,br24g01", "atmel,24c01";
-		reg = <0x50>;
-		pagesize = <8>;
-	};
-};
-
-&i2c1 {
-	pinctrl-0 = <&i2c1_pins>;
-	pinctrl-names = "default";
-	clock-frequency = <400000>;
-	status = "okay";
-};
-
-&eth_pcs {
-	phys = <&mp_phy 2 1>;
-	status = "okay";
-};
-
-&mmc0 {
-	pinctrl-0 = <&mmc0_pins>;
-	pinctrl-1 = <&mmc0_pins>;
-	pinctrl-names = "default", "state_uhs";
-
-	bus-width = <8>;
-	full-pwr-cycle-in-suspend;
-	mmc-hs200-1_8v;
-	mmc-hs400-1_8v;
-	no-sd;
-	no-sdio;
-	non-removable;
-
-	vmmc-supply = <&reg_3p3v>;
-	vqmmc-supply = <&reg_1p8v>;
-
-	status = "okay";
-};
-
-&ufs0 {
-	status = "okay";
-};
-
-&ufs1 {
-	status = "okay";
-};
-
-&mp_phy {
-	status = "okay";
-};
-
-&pfc {
-	pinctrl-0 = <&scif_clk_pins>;
-	pinctrl-names = "default";
-
-	eth25g2_pins: eth25g2 {
-		groups = "eth25g2_mdio", "eth25g2_link", "eth25g2_phyint";
-		function = "eth25g2";
-		drive-strength = <24>;
-	};
-
-	ethes0_pins: ethes0 {
-		groups = "ethes0_match", "ethes0_capture", "ethes0_pps";
-		function = "ethes0";
-		drive-strength = <24>;
-	};
-
-	hscif0_pins: hscif0 {
-		groups = "hscif0_data", "hscif0_ctrl";
-		function = "hscif0";
-	};
-
-	i2c0_pins: i2c0 {
-		groups = "i2c0";
-		function = "i2c0";
-	};
-
-	i2c1_pins: i2c1 {
-		groups = "i2c1";
-		function = "i2c1";
-	};
-
-	mmc0_pins: mmc0 {
-		groups = "mmc0_data8", "mmc0_ctrl", "mmc0_ds";
-		function = "mmc0";
-		drive-strength = <24>;
-	};
-
-	rsw3_pins: rsw3 {
-		groups = "rsw3_match", "rsw3_capture", "rsw3_pps";
-		function = "rsw3";
-		drive-strength = <24>;
-	};
-
-	scif_clk_pins: scif-clk {
-		groups = "scif_clk";
-		function = "scif_clk";
-	};
-};
-
-&rswitch3 {
-	pinctrl-0 = <&rsw3_pins>, <&eth25g2_pins>, <&ethes0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	ethernet-ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		/*
-		 * NOTE: Only port@4 is configured for R-Car X5H board.
-		 * Other ports (0-3, 5-12) are currently unused or not
-		 * connected.
-		 */
-		port@4 {
-			reg = <4>;
-			renesas,connect_to_xpcs;
-			phy-handle = <&dp83869_phy>;
-			phy-mode = "sgmii";
-			phys = <&eth_pcs 5>;
-
-			mdio {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				dp83869_phy: ethernet-phy@2 {
-					reg = <2>;
-					ti,sgmii-interface;
-					ti,max-output-impedance;
-					ti,refclk-output-enable;
-					ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>;
-				};
-			};
-		};
-	};
-};
-
-&scif_clk {
-	clock-frequency = <26000000>;
-};
--- a/arch/arm/dts/r8a78000-u-boot.dtsi
+++ b/arch/arm/dts/r8a78000-u-boot.dtsi
@@ -5,9 +5,41 @@
 * Copyright (C) 2025 Renesas Electronics Corp.
 */

+#include <dt-bindings/clock/r8a78000-clock-scmi.h>
+#include <dt-bindings/power/r8a78000-power-scmi.h>
+#include <dt-bindings/reset/r8a78000-reset-scmi.h>
+
 / {
-	soc {
-		bootph-all;
+	firmware {
+		scmi: scmi {
+			compatible = "arm,scmi";
+			arm,poll-transport;
+			mbox-names = "tx", "rx";
+			mboxes = <&mailbox 0>, <&mailbox 1>;
+			shmem = <&cpu_scp_lpri0>, <&cpu_scp_hpri0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			protocol@11 {
+				reg = <0x11>;
+				#power-domain-cells = <1>;
+			};
+
+			protocol@14 {
+				reg = <0x14>;
+				#clock-cells = <1>;
+			};
+
+			protocol@16 {
+				reg = <0x16>;
+				#reset-cells = <1>;
+			};
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2";
+		method = "smc";
 	};

 	/* Placeholder clock until the clock provider is in place */
@@ -32,16 +64,12 @@
 	clk_stub_mmc: clk-stub-mmc {
 		compatible = "renesas,compound-clock";
 		#clock-cells = <0>;
-		clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_SDHI0>,
-			 <&scmi_clk 1691>;
+		clocks = <&cpg SCP_CLOCK_ID_MDLC_SDHI0>,
+			 <&cpg SCP_CLOCK_ID_CLK_S0D6_PERE_MAIN>;
 		clock-names = "mdlc", "per";
 	};
 };

-&cpg {
-	bootph-all;
-};
-
 &extal_clk {
 	bootph-all;
 };
@@ -50,90 +78,311 @@
 	bootph-all;
 };

-&gpio0 {
-	clocks = <&clk_stub_gpio>;
-};
-
-&gpio1 {
-	clocks = <&clk_stub_gpio>;
-};
-
-&gpio2 {
-	clocks = <&clk_stub_gpio>;
-};
-
-&gpio3 {
-	clocks = <&clk_stub_gpio>;
-};
-
-&gpio4 {
-	clocks = <&clk_stub_gpio>;
-};
-
-&gpio5 {
-	clocks = <&clk_stub_gpio>;
-};
-
-&gpio6 {
-	clocks = <&clk_stub_gpio>;
-};
-
-&gpio7 {
-	clocks = <&clk_stub_gpio>;
-};
-
-&gpio8 {
-	clocks = <&clk_stub_gpio>;
-};
-
-&gpio9 {
-	clocks = <&clk_stub_gpio>;
-};
-
-&gpio10 {
-	clocks = <&clk_stub_gpio>;
-};
-
-&i2c0 {
-	clocks = <&clk_stub_i2c0>;
-};
-
-&i2c1 {
-	clocks = <&clk_stub_i2c1>;
-};
-
-&i2c2 {
-	clocks = <&clk_stub_i2c1>;
-};
-
-&i2c3 {
-	clocks = <&clk_stub_i2c1>;
-};
-
-&i2c4 {
-	clocks = <&clk_stub_i2c1>;
-};
-
-&i2c5 {
-	clocks = <&clk_stub_i2c1>;
-};
-
-&i2c6 {
-	clocks = <&clk_stub_i2c1>;
-};
-
-&i2c7 {
-	clocks = <&clk_stub_i2c1>;
-};
-
-&i2c8 {
-	clocks = <&clk_stub_i2c1>;
-};
-
-&mmc0 {
-	clocks = <&clk_stub_mmc>;
-};
-
 &prr {
 	bootph-all;
 };
+
+&soc {
+	bootph-all;
+
+	mailbox: mfis_mbox@18842000 {
+		compatible = "renesas,mfis-mbox";
+		#mbox-cells = <1>;
+		reg = <0 0x18842004 0 0x8>;
+		interrupts = <GIC_SPI 4362 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	pfc: pinctrl@c0400000 {
+		compatible = "renesas,pfc-r8a78000";
+		reg = <0 0xc1080000 0 0x104>, <0 0xc1080800 0 0x104>,
+		      <0 0xc1081000 0 0x104>, <0 0xc0800000 0 0x104>,
+		      <0 0xc0800800 0 0x104>, <0 0xc0400000 0 0x104>,
+		      <0 0xc0400800 0 0x104>, <0 0xc0401000 0 0x104>,
+		      <0 0xc0401800 0 0x104>, <0 0xc9b00000 0 0x104>,
+		      <0 0xc9b00800 0 0x104>;
+	};
+
+	mmc0: mmc@c0880000 {
+		compatible = "renesas,rcar-gen5-sdhi";
+		reg = <0 0xc0880000 0 0x2000>;
+		clock-names = "core";
+		max-frequency = <200000000>;
+		clocks = <&clk_stub_mmc>;
+		status = "disabled";
+	};
+
+	mdlc_pere: system-controller@c08f0000 {
+		compatible = "renesas,r8a78000-mdlc";
+		reg = <0 0xc08f0000 0 0x1000>;
+		#power-domain-cells = <1>;
+		#reset-cells = <1>;
+		bootph-all;
+	};
+
+	ufs0: ufs@c0a80000 {
+		compatible = "renesas,r8a78000-ufs";
+		reg = <0 0xc0a80000 0 0x1100>, <0 0xc0a00000 0 0x40000>;
+		reg-names = "hcr", "phy";
+		interrupts = <GIC_SPI 4284 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&mdlc_pere X5H_POWER_DOMAIN_ID_UFS0>;
+		clocks = <&cpg SCP_CLOCK_ID_MDLC_UFS0>;
+		resets = <&mdlc_pere SCP_RESET_DOMAIN_ID_UFS0>;
+		freq-table-hz = <38400000 38400000>;
+		status = "disabled";
+	};
+
+	ufs1: ufs@c0a90000 {
+		compatible = "renesas,r8a78000-ufs";
+		reg = <0 0xc0a90000 0 0x1100>, <0 0xc0a40000 0 0x40000>;
+		reg-names = "hcr", "phy";
+		interrupts = <GIC_SPI 4285 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&mdlc_pere X5H_POWER_DOMAIN_ID_UFS1>;
+		clocks = <&cpg SCP_CLOCK_ID_MDLC_UFS1>;
+		resets = <&mdlc_pere SCP_RESET_DOMAIN_ID_UFS1>;
+		freq-table-hz = <38400000 38400000>;
+		status = "disabled";
+	};
+
+	scp: sram@c1000000 {
+		compatible = "arm,rcar-sram-ns", "mmio-sram";
+		reg = <0x0 0xc1000000 0x0 0x80000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x0 0xc1000000 0x80000>;
+
+		cpu_scp_lpri0: scp-shmem@60000 {
+			compatible = "arm,rcar-scp-shmem", "arm,scmi-shmem";
+			reg = <0x61200 0x0100>;
+		};
+
+		cpu_scp_hpri0: scp-shmem@60300 {
+			compatible = "arm,rcar-scp-shmem", "arm,scmi-shmem";
+			reg = <0x61300 0x100>;
+		};
+	};
+
+	cpg: clock-controller@c1320000 {
+		compatible = "renesas,r8a78000-cpg";
+		reg = <0 0xc1320000 0 0x10000>;
+		clocks = <&extal_clk>, <&extalr_clk>;
+		clock-names = "extal", "extalr";
+		#clock-cells = <1>;
+		bootph-all;
+	};
+
+	i2c0: i2c@c11d0000 {
+		compatible = "renesas,i2c-r8a78000",
+			     "renesas,rcar-gen5-i2c";
+		reg = <0 0xc11d0000 0 0x40>;
+		i2c-scl-internal-delay-ns = <110>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&clk_stub_i2c0>;
+		status = "disabled";
+	};
+
+	i2c1: i2c@c06c0000 {
+		compatible = "renesas,i2c-r8a78000",
+			     "renesas,rcar-gen5-i2c";
+		reg = <0 0xc06c0000 0 0x40>;
+		i2c-scl-internal-delay-ns = <110>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&clk_stub_i2c1>;
+		status = "disabled";
+	};
+
+	gpio0: gpio@c1080110 {
+		compatible = "renesas,gpio-r8a78000",
+			     "renesas,rcar-gen5-gpio";
+		reg = <0 0xc1080110 0 0xc0>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 0 28>;
+		clocks = <&clk_stub_gpio>;
+	};
+
+	gpio1: gpio@c1080910 {
+		compatible = "renesas,gpio-r8a78000",
+			     "renesas,rcar-gen5-gpio";
+		reg = <0 0xc1080910 0 0xc0>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 32 22>;
+		clocks = <&clk_stub_gpio>;
+	};
+
+	gpio2: gpio@c1081110 {
+		compatible = "renesas,gpio-r8a78000",
+			     "renesas,rcar-gen5-gpio";
+		reg = <0 0xc1081110 0 0xc0>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 64 29>;
+		clocks = <&clk_stub_gpio>;
+	};
+
+	gpio3: gpio@c0800110 {
+		compatible = "renesas,gpio-r8a78000",
+			     "renesas,rcar-gen5-gpio";
+		reg = <0 0xc0800110 0 0xc0>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 96 17>;
+		clocks = <&clk_stub_gpio>;
+	};
+
+	gpio4: gpio@c0800910 {
+		compatible = "renesas,gpio-r8a78000",
+			     "renesas,rcar-gen5-gpio";
+		reg = <0 0xc0800910 0 0xc0>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 128 16>;
+		clocks = <&clk_stub_gpio>;
+	};
+
+	gpio5: gpio@c0400110 {
+		compatible = "renesas,gpio-r8a78000",
+			     "renesas,rcar-gen5-gpio";
+		reg = <0 0xc0400110 0 0xc0>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 160 23>;
+		clocks = <&clk_stub_gpio>;
+	};
+
+	gpio6: gpio@c0400910 {
+		compatible = "renesas,gpio-r8a78000",
+			     "renesas,rcar-gen5-gpio";
+		reg = <0 0xc0400910 0 0xc0>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 192 31>;
+		clocks = <&clk_stub_gpio>;
+	};
+
+	gpio7: gpio@c0401110 {
+		compatible = "renesas,gpio-r8a78000",
+			     "renesas,rcar-gen5-gpio";
+		reg = <0 0xc0401110 0 0xc0>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 224 31>;
+		clocks = <&clk_stub_gpio>;
+	};
+
+	gpio8: gpio@c0401910 {
+		compatible = "renesas,gpio-r8a78000",
+			     "renesas,rcar-gen5-gpio";
+		reg = <0 0xc0401910 0 0xc0>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 256 32>;
+		gpio-reserved-ranges = <16 10>;
+		clocks = <&clk_stub_gpio>;
+	};
+
+	gpio9: gpio@c9b00110 {
+		compatible = "renesas,gpio-r8a78000",
+			     "renesas,rcar-gen5-gpio";
+		reg = <0 0xc9b00110 0 0xc0>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 288 17>;
+		clocks = <&clk_stub_gpio>;
+	};
+
+	gpio10: gpio@c9b00910 {
+		compatible = "renesas,gpio-r8a78000",
+			     "renesas,rcar-gen5-gpio";
+		reg = <0 0xc9b00910 0 0xc0>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 320 14>;
+		clocks = <&clk_stub_gpio>;
+	};
+
+	mp_phy: mp_phy@c9a00000 {
+		compatible = "renesas,r8a78000-multi-protocol-phy";
+		reg = <0 0xc9a00000 0 0x100000>;
+		#phy-cells = <2>;
+		clocks = <&cpg SCP_CLOCK_ID_MDLC_MPPHY01>,
+			 <&cpg SCP_CLOCK_ID_MDLC_MPPHY11>,
+			 <&cpg SCP_CLOCK_ID_MDLC_MPPHY21>,
+			 <&cpg SCP_CLOCK_ID_MDLC_MPPHY31>,
+			 <&cpg SCP_CLOCK_ID_MDLC_MPPHY02>;
+		clock-names = "mpphy01", "mpphy11", "mpphy21",
+			      "mpphy31", "mpphy02";
+		power-domains = <&mdlc_hscn X5H_POWER_DOMAIN_ID_MPP0>,
+				<&mdlc_hscn X5H_POWER_DOMAIN_ID_MPP1>,
+				<&mdlc_hscn X5H_POWER_DOMAIN_ID_MPP2>,
+				<&mdlc_hscn X5H_POWER_DOMAIN_ID_MPP3>;
+		resets = <&mdlc_hscn SCP_RESET_DOMAIN_ID_MPPHY01>,
+			 <&mdlc_hscn SCP_RESET_DOMAIN_ID_MPPHY11>,
+			 <&mdlc_hscn SCP_RESET_DOMAIN_ID_MPPHY21>,
+			 <&mdlc_hscn SCP_RESET_DOMAIN_ID_MPPHY31>,
+			 <&mdlc_hscn SCP_RESET_DOMAIN_ID_MPPHY02>;
+		status = "disabled";
+	};
+
+	rswitch3: ethernet@c9bc0000 {
+		compatible = "renesas,r8a78000-ether-switch3",
+				"renesas,etherswitch";
+		reg = <0 0xc9bc0000 0 0x40000>, <0 0xc9b80000 0 0x240000>;
+		reg-names = "base", "secure_base";
+		power-domains = <&mdlc_hscn X5H_POWER_DOMAIN_ID_RSW>;
+		clocks = <&cpg SCP_CLOCK_ID_MDLC_RSW3>,
+			 <&cpg SCP_CLOCK_ID_MDLC_RSW3TSN>,
+			 <&cpg SCP_CLOCK_ID_MDLC_RSW3AES>,
+			 <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES0>,
+			 <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES1>,
+			 <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES2>,
+			 <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES3>,
+			 <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES4>,
+			 <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES5>,
+			 <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES6>,
+			 <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES7>,
+			 <&cpg SCP_CLOCK_ID_MDLC_RSW3MFWD>;
+		clock-names = "rsw3", "rsw3tsn", "rsw3aes",
+			      "rsw3tsntes0", "rsw3tsntes1", "rsw3tsntes2",
+			      "rsw3tsntes3", "rsw3tsntes4", "rsw3tsntes5",
+			      "rsw3tsntes6", "rsw3tsntes7", "rsw3mfwd";
+		status = "disabled";
+	};
+
+	eth_pcs: phy@c9c50000 {
+		compatible = "renesas,r8a78000-ether-pcs";
+		reg = <0 0xc9c50000 0 0x4000>;
+		#phy-cells = <1>;
+		clocks = <&cpg SCP_CLOCK_ID_MDLC_XPCS0>,
+			 <&cpg SCP_CLOCK_ID_MDLC_XPCS1>,
+			 <&cpg SCP_CLOCK_ID_MDLC_XPCS2>,
+			 <&cpg SCP_CLOCK_ID_MDLC_XPCS3>,
+			 <&cpg SCP_CLOCK_ID_MDLC_XPCS4>,
+			 <&cpg SCP_CLOCK_ID_MDLC_XPCS5>,
+			 <&cpg SCP_CLOCK_ID_MDLC_XPCS6>,
+			 <&cpg SCP_CLOCK_ID_MDLC_XPCS7>;
+		clock-names = "xpcs0", "xpcs1", "xpcs2", "xpcs3",
+			      "xpcs4", "xpcs5", "xpcs6", "xpcs7";
+		resets = <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS0>,
+			 <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS1>,
+			 <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS2>,
+			 <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS3>,
+			 <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS4>,
+			 <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS5>,
+			 <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS6>,
+			 <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS7>;
+		reset-names = "xpcs0", "xpcs1", "xpcs2", "xpcs3",
+			      "xpcs4", "xpcs5", "xpcs6", "xpcs7";
+		status = "disabled";
+	};
+
+	mdlc_hscn: system-controller@c9c90000 {
+		compatible = "renesas,r8a78000-mdlc";
+		reg = <0 0xc9c90000 0 0x1000>;
+		#power-domain-cells = <1>;
+		#reset-cells = <1>;
+		bootph-all;
+	};
+};
--- a/arch/arm/dts/r8a78000.dtsi
+++ b/arch/arm/dts/r8a78000.dtsi
--- a/arch/arm/mach-renesas/Kconfig.rcar5
+++ b/arch/arm/mach-renesas/Kconfig.rcar5
@@ -13,7 +13,9 @@ menu "Select Target SoC"
 config R8A78000
 	bool "Renesas SoC R8A78000"
 	select GICV3
+	imply CLK_R8A78000
 	imply PINCTRL_PFC_R8A78000
+	imply RENESAS_R8A78000_POWER_DOMAIN

 endmenu

--- a/arch/arm/mach-renesas/Makefile
+++ b/arch/arm/mach-renesas/Makefile
@@ -40,6 +40,27 @@ else
 	srec_cat_le_cmd := "-l-e-constant"
 endif

+ifneq ($(CONFIG_RCAR_GEN5),)
+quiet_cmd_srec_cat = SRECCAT $@
+      cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \
+			-Output_Block_Size 16 \
+			-generate 0x18402010 0x18402014 $(srec_cat_le_cmd) $(CONFIG_SYS_UBOOT_START) 4 \
+			-generate 0x18402014 0x18402018 $(srec_cat_le_cmd) 0x1ef000 4
+
+quiet_cmd_srec_shdr_cat = SRECCAT $@
+      cmd_srec_shdr_cat = srec_cat -output $@ -M 8 \
+			-Output_Block_Size 16 \
+			-generate 0x18400000 0x18400004 $(srec_cat_le_cmd) 0x00000003 4 \
+			-generate 0x18400004 0x18400008 $(srec_cat_le_cmd) 0x0 4 \
+			-generate 0x18402000 0x18402004 $(srec_cat_le_cmd) 0x6b657963 4 \
+			-generate 0x18402004 0x18402008 $(srec_cat_le_cmd) 0x00010010 4 \
+			-generate 0x18402008 0x1840200c $(srec_cat_le_cmd) 0x0 4 \
+			-generate 0x1840200c 0x18402010 $(srec_cat_le_cmd) 0x34040000 4 \
+			-generate 0x18402010 0x18402014 $(srec_cat_le_cmd) $(CONFIG_SYS_UBOOT_START) 4 \
+			-generate 0x18402014 0x18402018 $(srec_cat_le_cmd) 0x1ef000 4 \
+			-generate 0x18402018 0x1840201c $(srec_cat_le_cmd) 0x0 4 \
+			-generate 0x1840201c 0x18402020 $(srec_cat_le_cmd) 0x0 4
+else
 ifneq ($(CONFIG_RCAR_GEN4),)
 quiet_cmd_srec_cat = SRECCAT $@
      cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \
@@ -106,10 +127,17 @@ quiet_cmd_srec_cat = SRECCAT $@
 			-generate 0xe6301264 0xe6301268 $(srec_cat_le_cmd) $2 4
 endif
 endif
+endif

 spl/u-boot-spl.scif: spl/u-boot-spl.srec spl/u-boot-spl.bin
 	$(call cmd,srec_cat,$(shell wc -c spl/u-boot-spl.bin | awk '{printf("0x%08x\n",$$1)}'))

+u-boot-elf.scif: u-boot-elf.srec u-boot.bin
+	$(call cmd,srec_cat,$(shell wc -c u-boot-dtb.bin | awk '{printf("0x%08x\n",$$1)}'))
+
+u-boot-elf.shdr: u-boot-elf.srec u-boot.bin
+	$(call cmd,srec_shdr_cat,$(shell wc -c u-boot-dtb.bin | awk '{printf("0x%08x\n",$$1)}'))
+
 # if srec_cat is present build u-boot-spl.scif by default
 has_srec_cat = $(call try-run,srec_cat -VERSion,y,n)
 INPUTS-$(has_srec_cat) += u-boot-spl.scif
--- a/arch/arm/mach-renesas/u-boot-rsip.lds
+++ b/arch/arm/mach-renesas/u-boot-rsip.lds
@@ -0,0 +1,203 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ */
+
+#include <config.h>
+#include <asm/psci.h>
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+#if defined(CONFIG_ARMV7_SECURE_BASE) && defined(CONFIG_ARMV7_NONSEC)
+	/*
+	 * If CONFIG_ARMV7_SECURE_BASE is true, secure code will not
+	 * bundle with u-boot, and code offsets are fixed. Secure zone
+	 * only needs to be copied from the loading address to
+	 * CONFIG_ARMV7_SECURE_BASE, which is the linking and running
+	 * address for secure code.
+	 *
+	 * If CONFIG_ARMV7_SECURE_BASE is undefined, the secure zone will
+	 * be included in u-boot address space, and some absolute address
+	 * were used in secure code. The absolute addresses of the secure
+	 * code also needs to be relocated along with the accompanying u-boot
+	 * code.
+	 *
+	 * So DISCARD is only for CONFIG_ARMV7_SECURE_BASE.
+	 */
+	/DISCARD/ : { *(.rel._secure*) }
+#endif
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	__image_copy_start = ADDR(.text);
+	.text :
+	{
+		CPUDIR/start.o (.text*)
+		*(.vectors)
+	}
+
+	/* This needs to come before *(.text*) */
+	.efi_runtime : {
+		__efi_runtime_start = .;
+		*(.text.efi_runtime*)
+		*(.rodata.efi_runtime*)
+		*(.data.efi_runtime*)
+		__efi_runtime_stop = .;
+	}
+
+	.text_rest :
+	{
+		*(.text*)
+	}
+
+#ifdef CONFIG_ARMV7_NONSEC
+
+	/* Align the secure section only if we're going to use it in situ */
+	.__secure_start
+#ifndef CONFIG_ARMV7_SECURE_BASE
+		ALIGN(CONSTANT(COMMONPAGESIZE))
+#endif
+	: {
+		KEEP(*(.__secure_start))
+	}
+
+#ifndef CONFIG_ARMV7_SECURE_BASE
+#define __ARMV7_SECURE_BASE
+#define __ARMV7_PSCI_STACK_IN_RAM
+#else
+#define __ARMV7_SECURE_BASE	CONFIG_ARMV7_SECURE_BASE
+#endif
+
+	.secure_text __ARMV7_SECURE_BASE :
+		AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
+	{
+		*(._secure.text)
+	}
+
+	.secure_data : AT(LOADADDR(.secure_text) + SIZEOF(.secure_text))
+	{
+		*(._secure.data)
+	}
+
+#ifdef CONFIG_ARMV7_PSCI
+	.secure_stack ALIGN(ADDR(.secure_data) + SIZEOF(.secure_data),
+			    CONSTANT(COMMONPAGESIZE)) (NOLOAD) :
+#ifdef __ARMV7_PSCI_STACK_IN_RAM
+		AT(ADDR(.secure_stack))
+#else
+		AT(LOADADDR(.secure_data) + SIZEOF(.secure_data))
+#endif
+	{
+		KEEP(*(.__secure_stack_start))
+
+		/* Skip addresses for stack */
+		. = . + CONFIG_ARMV7_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE;
+
+		/* Align end of stack section to page boundary */
+		. = ALIGN(CONSTANT(COMMONPAGESIZE));
+
+		KEEP(*(.__secure_stack_end))
+
+#ifdef CONFIG_ARMV7_SECURE_MAX_SIZE
+		/*
+		 * We are not checking (__secure_end - __secure_start) here,
+		 * as these are the load addresses, and do not include the
+		 * stack section. Instead, use the end of the stack section
+		 * and the start of the text section.
+		 */
+		ASSERT((. - ADDR(.secure_text)) <= CONFIG_ARMV7_SECURE_MAX_SIZE,
+		       "Error: secure section exceeds secure memory size");
+#endif
+	}
+
+#ifndef __ARMV7_PSCI_STACK_IN_RAM
+	/* Reset VMA but don't allocate space if we have secure SRAM */
+	. = LOADADDR(.secure_stack);
+#endif
+
+#endif
+
+	.__secure_end : AT(ADDR(.__secure_end)) {
+		*(.__secure_end)
+		LONG(0x1d1071c);	/* Must output something to reset LMA */
+	}
+#endif
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		__data_start = .;
+		*(.data*)
+		__data_end = .;
+	}
+
+	. = ALIGN(4);
+
+	. = .;
+
+	. = ALIGN(4);
+	__u_boot_list : {
+		KEEP(*(SORT(__u_boot_list*)));
+	}
+
+	.efi_runtime_rel : {
+		__efi_runtime_rel_start = .;
+		*(.rel*.efi_runtime)
+		*(.rel*.efi_runtime.*)
+		__efi_runtime_rel_stop = .;
+	}
+
+	. = ALIGN(8);
+	__image_copy_end = .;
+
+	/*
+	 * if CONFIG_USE_ARCH_MEMSET is not selected __bss_end - __bss_start
+	 * needs to be a multiple of 8 and we overlay .bss with .rel.dyn
+	 */
+	.rel.dyn ALIGN(8) : {
+		__rel_dyn_start = .;
+		*(.rel*)
+		__rel_dyn_end = .;
+		. = ALIGN(8);
+	}
+
+	_end = .;
+	_image_binary_end = .;
+
+/*
+ * These sections occupy the same memory, but their lifetimes do
+ * not overlap: U-Boot initializes .bss only after applying dynamic
+ * relocations and therefore after it doesn't need .rel.dyn any more.
+ */
+
+	/* BSS goes to special read-write offset below U-Boot entry point */
+	. = 0xb8400000;
+	.bss (OVERLAY): {
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end = .;
+	}
+
+	/DISCARD/ : { *(.dynsym) }
+	/DISCARD/ : { *(.dynbss) }
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu.hash) }
+	/DISCARD/ : { *(.gnu*) }
+	/DISCARD/ : { *(.ARM.exidx*) }
+	/DISCARD/ : { *(.gnu.linkonce.armexidx.*) }
+}
+
+ASSERT(_image_binary_end % 8 == 0, \
+       "_image_binary_end must be 8-byte aligned for device tree");
--- a/board/renesas/common/Makefile
+++ b/board/renesas/common/Makefile
@@ -45,9 +45,13 @@ endif
 endif

 ifdef CONFIG_RCAR_GEN5
+ifdef CONFIG_RCAR_64_RSIP
+obj-y	+= gen5-cm33.o
+else
 obj-y	+= gen5-common.o
 endif
 endif
+endif

 endif
 endif
--- a/board/renesas/common/gen5-cm33.c
+++ b/board/renesas/common/gen5-cm33.c
--- a/board/renesas/common/gen5-cm33.h
+++ b/board/renesas/common/gen5-cm33.h
--- a/configs/r8a78000_ironhide_cm33_defconfig
+++ b/configs/r8a78000_ironhide_cm33_defconfig
@@ -0,0 +1,80 @@
+#include <configs/renesas_rcar64.config>
+
+CONFIG_ARM=y
+CONFIG_ARCH_RENESAS=y
+CONFIG_RCAR_64_RSIP=y
+CONFIG_RCAR_GEN5=y
+CONFIG_TARGET_IRONHIDE=y
+CONFIG_DEFAULT_DEVICE_TREE="r8a78000-ironhide-cm33"
+CONFIG_DEFAULT_FDT_FILE="r8a78000-ironhide-cm33.dtb"
+
+CONFIG_TEXT_BASE=0x18410000
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x3fe10000
+CONFIG_SYS_CUSTOM_LDSCRIPT=y
+CONFIG_SYS_LDSCRIPT="arch/arm/mach-renesas/u-boot-rsip.lds"
+CONFIG_SKIP_RELOCATE_CODE=y
+CONFIG_SKIP_RELOCATE_CODE_DATA_OFFSET=0xa0000000
+
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_BAUDRATE=1843200
+CONFIG_BOOTCOMMAND=""
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_CMD_IMI=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_UFS=y
+CONFIG_DM_DMA=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DM_RESET=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_LAST_STAGE_INIT=y
+CONFIG_NET_LWIP=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_OF_LIVE=y
+CONFIG_PHY_R8A78000_ETHERNET_PCS=y
+CONFIG_PHY_R8A78000_MP_PHY=y
+CONFIG_PHY_TI_DP83869=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_RAM=y
+CONFIG_REMOTEPROC_RENESAS_RSIP=y
+CONFIG_RENESAS_ETHER_SWITCH=y
+CONFIG_RENESAS_R8A78000_POWER_DOMAIN=y
+CONFIG_SCSI=y
+CONFIG_SERIAL_PROBE_ALL=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SIMPLE_BUS_CORRECT_RANGE=y
+CONFIG_SKIP_RELOCATE=y
+CONFIG_SYS_ARCH_TIMER=y
+CONFIG_SYS_BARGSIZE=2048
+CONFIG_SYS_BOOT_GET_CMDLINE=y
+CONFIG_SYS_CLK_FREQ=16666666
+CONFIG_SYS_LOAD_ADDR=0xb8000000
+CONFIG_SYS_MALLOC_LEN=0x80000
+CONFIG_SYS_TIMER_COUNTS_DOWN=y
+CONFIG_UFS=y
+CONFIG_UFS_RENESAS_GEN5=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_WATCHDOG_TIMEOUT_MSECS=2000
+CONFIG_WDT=y
+CONFIG_WDT_RENESAS_WWDT=y
+# CONFIG_DM_THERMAL is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_BOOTFLOW is not set
+# CONFIG_CMD_BOOTZ is not set
+# CONFIG_PROT_TCP is not set
+# CONFIG_OF_UPSTREAM is not set
+# CONFIG_BOARD_EARLY_INIT_F is not set
+# CONFIG_OF_BOARD_SETUP is not set
+# CONFIG_SYS_ARCH_TIMER is not set
+
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_SCIF=y
+CONFIG_DEBUG_UART_BASE=0xc0714000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_DEBUG_UART_BOARD_INIT=y
--- a/configs/r8a78000_ironhide_defconfig
+++ b/configs/r8a78000_ironhide_defconfig
@@ -5,12 +5,11 @@ CONFIG_ARCH_RENESAS=y
 CONFIG_RCAR_GEN5=y
 CONFIG_TARGET_IRONHIDE=y

-# CONFIG_OF_UPSTREAM is not set
 CONFIG_ARMV8_PSCI=y
 CONFIG_ARM_SMCCC=y
 CONFIG_BAUDRATE=1843200
 CONFIG_BOOTCOMMAND="setexpr dloadaddr ${loadaddr} + 0x200000 && setexpr dloadaddr ${dloadaddr} \\\\& 0xffc00000 && setexpr kloadaddr ${dloadaddr} + 0x200000 && tftp ${dloadaddr} r8a78000-ironhide.dtb && tftp ${kloadaddr} Image && booti ${kloadaddr} - ${dloadaddr}"
-CONFIG_DEFAULT_DEVICE_TREE="r8a78000-ironhide"
+CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a78000-ironhide"
 CONFIG_CLK_CCF=y
 CONFIG_CLK_COMPOSITE_CCF=y
 CONFIG_CLK_SCMI=y
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -157,6 +157,12 @@ config CLK_R8A779H0
 	help
 	  Enable this to support the clocks on Renesas R8A779H0 SoC.

+config CLK_R8A78000
+	bool "Renesas R8A78000 clock driver"
+	depends on CLK_RENESAS
+	help
+	  Enable this to support the clocks on Renesas R8A78000 SoC.
+
 config CLK_R9A06G032
 	bool "Renesas R9A06G032 clock driver"
 	depends on CLK_RENESAS
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A779G0) += r8a779g0-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A779H0) += r8a779h0-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A78000) += r8a78000-cpg.o
 obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
 obj-$(CONFIG_CLK_RZG2L) += rzg2l-cpg.o
 obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
--- a/drivers/clk/renesas/r8a78000-cpg.c
+++ b/drivers/clk/renesas/r8a78000-cpg.c
@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Renesas R-Car Gen5 CPG driver
+ *
+ * Copyright (C) 2026 Marek Vasut <marek.vasut+renesas@mailbox.org>
+ */
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <linux/clk-provider.h>
+
+#include <scmi_agent.h>
+#include <scmi_agent-uclass.h>
+#include <scmi_protocols.h>
+
+#include <dt-bindings/clock/r8a78000-clock-scmi.h>
+
+#if IS_ENABLED(CONFIG_CLK_SCMI)
+struct gen5_clk_priv {
+	struct udevice	*clk;
+	u32		basever;
+};
+
+static struct clk *gen5_clk_get_by_scmi_id(struct clk *clk)
+{
+	struct gen5_clk_priv *priv = dev_get_priv(clk->dev);
+	struct udevice *sdev;
+	struct uclass *uc;
+
+	uclass_id_foreach_dev(UCLASS_CLK, sdev, uc)
+		if (sdev->seq_ == priv->clk->seq_ + clk->id + 1)
+			return dev_get_clk_ptr(sdev);
+
+	return NULL;
+}
+
+static ulong gen5_clk_round_rate(struct clk *clk, ulong rate)
+{
+	struct clk *scmi = gen5_clk_get_by_scmi_id(clk);
+
+	if (!scmi)
+		return -ENODEV;
+
+	return clk_round_rate(scmi, rate);
+}
+
+static ulong gen5_clk_get_rate(struct clk *clk)
+{
+	struct clk *scmi = gen5_clk_get_by_scmi_id(clk);
+
+	if (!scmi)
+		return -ENODEV;
+
+	return clk_get_rate(scmi);
+}
+
+static ulong gen5_clk_set_rate(struct clk *clk, ulong rate)
+{
+	struct clk *scmi = gen5_clk_get_by_scmi_id(clk);
+
+	if (!scmi)
+		return -ENODEV;
+
+	return clk_set_rate(scmi, rate);
+}
+
+static int gen5_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	struct clk *scmi = gen5_clk_get_by_scmi_id(clk);
+
+	if (!scmi)
+		return -ENODEV;
+
+	return clk_set_parent(scmi, parent);
+}
+
+static int gen5_clk_enable(struct clk *clk)
+{
+	struct clk *scmi = gen5_clk_get_by_scmi_id(clk);
+
+	if (!scmi)
+		return -ENODEV;
+
+	return clk_enable(scmi);
+}
+
+static int gen5_clk_disable(struct clk *clk)
+{
+	struct clk *scmi = gen5_clk_get_by_scmi_id(clk);
+
+	if (!scmi)
+		return -ENODEV;
+
+	return clk_disable(scmi);
+}
+
+struct clk_map_in {
+	u16 dt_id;	/* DT binding clock ID */
+	u16 fw_id;	/* SCMI firmware clock ID */
+};
+
+#define GEN5_SCMI_SDK_4_28		0x010a0000
+#define GEN5_SCMI_SDK_4_29		0x010b0000
+#define GEN5_SCMI_SDK_4_30		0x010c0000
+#define GEN5_SCMI_SDK_4_31		0x010d0000
+#define GEN5_SCMI_SDK_4_32		0x010e0000
+
+static const struct clk_map_in gen5_clk_map_dt_sdk_4_28[] = {
+	{ SCP_CLOCK_ID_MDLC_UFS0, 202 },
+	{ SCP_CLOCK_ID_MDLC_UFS1, 203 },
+	{ SCP_CLOCK_ID_MDLC_SDHI0, 204 },
+	{ SCP_CLOCK_ID_MDLC_XPCS0, 316 },
+	{ SCP_CLOCK_ID_MDLC_XPCS1, 317 },
+	{ SCP_CLOCK_ID_MDLC_XPCS2, 318 },
+	{ SCP_CLOCK_ID_MDLC_XPCS3, 319 },
+	{ SCP_CLOCK_ID_MDLC_XPCS4, 320 },
+	{ SCP_CLOCK_ID_MDLC_XPCS5, 321 },
+	{ SCP_CLOCK_ID_MDLC_XPCS6, 322 },
+	{ SCP_CLOCK_ID_MDLC_XPCS7, 323 },
+	{ SCP_CLOCK_ID_MDLC_RSW3, 324 },
+	{ SCP_CLOCK_ID_MDLC_RSW3TSN, 325 },
+	{ SCP_CLOCK_ID_MDLC_RSW3AES, 326 },
+	{ SCP_CLOCK_ID_MDLC_RSW3TSNTES0, 327 },
+	{ SCP_CLOCK_ID_MDLC_RSW3TSNTES1, 328 },
+	{ SCP_CLOCK_ID_MDLC_RSW3TSNTES2, 329 },
+	{ SCP_CLOCK_ID_MDLC_RSW3TSNTES3, 330 },
+	{ SCP_CLOCK_ID_MDLC_RSW3TSNTES4, 331 },
+	{ SCP_CLOCK_ID_MDLC_RSW3TSNTES5, 332 },
+	{ SCP_CLOCK_ID_MDLC_RSW3TSNTES6, 333 },
+	{ SCP_CLOCK_ID_MDLC_RSW3TSNTES7, 334 },
+	{ SCP_CLOCK_ID_MDLC_RSW3MFWD, 335 },
+	{ SCP_CLOCK_ID_MDLC_MPPHY01, 344 },
+	{ SCP_CLOCK_ID_MDLC_MPPHY11, 345 },
+	{ SCP_CLOCK_ID_MDLC_MPPHY21, 346 },
+	{ SCP_CLOCK_ID_MDLC_MPPHY31, 347 },
+	{ SCP_CLOCK_ID_MDLC_MPPHY02, 348 },
+	{ SCP_CLOCK_ID_CLK_S0D6_PERE_MAIN, 1691 },
+};
+
+static const struct clk_map_in gen5_clk_map_dt_sdk_4_31[] = {
+	{ SCP_CLOCK_ID_MDLC_UFS0, 198 },
+	{ SCP_CLOCK_ID_MDLC_UFS1, 199 },
+	{ SCP_CLOCK_ID_MDLC_SDHI0, 200 },
+	{ SCP_CLOCK_ID_MDLC_XPCS0, 312 },
+	{ SCP_CLOCK_ID_MDLC_XPCS1, 313 },
+	{ SCP_CLOCK_ID_MDLC_XPCS2, 314 },
+	{ SCP_CLOCK_ID_MDLC_XPCS3, 315 },
+	{ SCP_CLOCK_ID_MDLC_XPCS4, 316 },
+	{ SCP_CLOCK_ID_MDLC_XPCS5, 317 },
+	{ SCP_CLOCK_ID_MDLC_XPCS6, 318 },
+	{ SCP_CLOCK_ID_MDLC_XPCS7, 319 },
+	{ SCP_CLOCK_ID_MDLC_RSW3, 320 },
+	{ SCP_CLOCK_ID_MDLC_RSW3TSN, 321 },
+	{ SCP_CLOCK_ID_MDLC_RSW3AES, 322 },
+	{ SCP_CLOCK_ID_MDLC_RSW3TSNTES0, 323 },
+	{ SCP_CLOCK_ID_MDLC_RSW3TSNTES1, 324 },
+	{ SCP_CLOCK_ID_MDLC_RSW3TSNTES2, 325 },
+	{ SCP_CLOCK_ID_MDLC_RSW3TSNTES3, 326 },
+	{ SCP_CLOCK_ID_MDLC_RSW3TSNTES4, 327 },
+	{ SCP_CLOCK_ID_MDLC_RSW3TSNTES5, 328 },
+	{ SCP_CLOCK_ID_MDLC_RSW3TSNTES6, 329 },
+	{ SCP_CLOCK_ID_MDLC_RSW3TSNTES7, 330 },
+	{ SCP_CLOCK_ID_MDLC_RSW3MFWD, 331 },
+	{ SCP_CLOCK_ID_MDLC_MPPHY01, 340 },
+	{ SCP_CLOCK_ID_MDLC_MPPHY11, 341 },
+	{ SCP_CLOCK_ID_MDLC_MPPHY21, 342 },
+	{ SCP_CLOCK_ID_MDLC_MPPHY31, 343 },
+	{ SCP_CLOCK_ID_MDLC_MPPHY02, 344 },
+	{ SCP_CLOCK_ID_CLK_S0D6_PERE_MAIN, 1687 },
+};
+
+static int gen5_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
+{
+	struct gen5_clk_priv *priv = dev_get_priv(clk->dev);
+	const struct clk_map_in *map;
+	unsigned int map_size;
+	int i;
+
+	if (args->args_count != 1) {
+		debug("Invalid args_count: %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	if (priv->basever == GEN5_SCMI_SDK_4_28) {
+		map = gen5_clk_map_dt_sdk_4_28;
+		map_size = ARRAY_SIZE(gen5_clk_map_dt_sdk_4_28);
+	} else if (priv->basever == GEN5_SCMI_SDK_4_31 ||
+		   priv->basever == GEN5_SCMI_SDK_4_32) {
+		map = gen5_clk_map_dt_sdk_4_31;
+		map_size = ARRAY_SIZE(gen5_clk_map_dt_sdk_4_31);
+	} else {
+		printf("Unsupported SCMI base protocol version %x\n", priv->basever);
+		return -EINVAL;
+	}
+
+	clk->id = -1;
+	for (i = 0; i < map_size; i++) {
+		if (map[i].dt_id != args->args[0])
+			continue;
+		clk->id = map[i].fw_id;
+		break;
+	}
+
+	if (clk->id == -1)
+		return -EINVAL;
+
+	return 0;
+}
+
+static const struct clk_ops gen5_clk_ops = {
+	.round_rate	= gen5_clk_round_rate,
+	.get_rate	= gen5_clk_get_rate,
+	.set_rate	= gen5_clk_set_rate,
+	.set_parent	= gen5_clk_set_parent,
+	.enable		= gen5_clk_enable,
+	.disable	= gen5_clk_disable,
+	.of_xlate	= gen5_clk_of_xlate,
+};
+
+static int gen5_clk_probe(struct udevice *dev)
+{
+	struct gen5_clk_priv *priv = dev_get_priv(dev);
+	struct udevice *agent;
+	int ret;
+
+	ret = uclass_get_device(UCLASS_SCMI_AGENT, 0, &agent);
+	if (ret)
+		return ret;
+
+	if (!agent)
+		return -ENODEV;
+
+	priv->basever = scmi_impl_version(agent);
+
+	return uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(scmi_clock),
+					   &priv->clk);
+}
+#else
+static int gen5_clk_enable(struct clk *clk)
+{
+	return 0;
+}
+
+static int gen5_clk_disable(struct clk *clk)
+{
+	return 0;
+}
+
+static int gen5_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
+{
+	if (args->args_count != 1) {
+		debug("Invalid args_count: %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	clk->id = args->args[0];
+
+	return 0;
+}
+
+static const struct clk_ops gen5_clk_ops = {
+	.enable		= gen5_clk_enable,
+	.disable	= gen5_clk_disable,
+	.of_xlate	= gen5_clk_of_xlate,
+};
+#endif
+
+static const struct udevice_id r8a78000_mdlc_ids[] = {
+	{ .compatible = "renesas,r8a78000-cpg", },
+	{ }
+};
+
+U_BOOT_DRIVER(clk_gen5) = {
+	.name		= "clk_gen5",
+	.id		= UCLASS_CLK,
+	.of_match	= r8a78000_mdlc_ids,
+	.priv_auto	= CONFIG_IS_ENABLED(CLK_SCMI, (sizeof(struct gen5_clk_priv)), (0)),
+	.ops		= &gen5_clk_ops,
+	.probe		= CONFIG_IS_ENABLED(CLK_SCMI, (gen5_clk_probe), (NULL)),
+	.flags          = DM_FLAG_OS_PREPARE | DM_FLAG_VITAL,
+};
--- a/drivers/power/domain/Kconfig
+++ b/drivers/power/domain/Kconfig
@@ -98,6 +98,14 @@ config QCOM_RPMH_POWER_DOMAIN
 	  The RPMH power domain driver is responsible for managing power
 	  domains on Qualcomm SoCs.

+config RENESAS_R8A78000_POWER_DOMAIN
+	bool "Enable the Renesas R-Car MDLC Power domain and reset driver"
+	depends on POWER_DOMAIN && ARCH_RENESAS
+	help
+	  Enable support for Renesas R-Car R8A78000 X5H MDLC Power domain
+	  and reset driver. The MDLC is responsible for managing both
+	  power domains and resets on R-Car R8A78000 X5H SoC.
+
 config SANDBOX_POWER_DOMAIN
 	bool "Enable the sandbox power domain test driver"
 	depends on POWER_DOMAIN && SANDBOX
--- a/drivers/power/domain/Makefile
+++ b/drivers/power/domain/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_MTK_POWER_DOMAIN) += mtk-power-domain.o
 obj-$(CONFIG_MESON_GX_VPU_POWER_DOMAIN) += meson-gx-pwrc-vpu.o
 obj-$(CONFIG_MESON_EE_POWER_DOMAIN) += meson-ee-pwrc.o
 obj-$(CONFIG_MESON_SECURE_POWER_DOMAIN) += meson-secure-pwrc.o
+obj-$(CONFIG_RENESAS_R8A78000_POWER_DOMAIN) += renesas-r8a78000-power-domain.o
 obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o
 obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o
 obj-$(CONFIG_SCMI_POWER_DOMAIN) += scmi-power-domain.o
--- a/drivers/power/domain/renesas-r8a78000-power-domain.c
+++ b/drivers/power/domain/renesas-r8a78000-power-domain.c
@@ -0,0 +1,427 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas R-Car Gen5 MDLC driver
+ *
+ * Copyright (C) 2026 Marek Vasut <marek.vasut+renesas@mailbox.org>
+ */
+
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <power-domain-uclass.h>
+#include <reset-uclass.h>
+
+#include <scmi_agent.h>
+#include <scmi_agent-uclass.h>
+#include <scmi_protocols.h>
+
+#include <dt-bindings/power/r8a78000-power-scmi.h>
+#include <dt-bindings/reset/r8a78000-reset-scmi.h>
+
+#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
+#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
+
+#define PKC_PROT_LOCK			0xa5a5a500
+#define PKC_PROT_UNLOCK			0xa5a5a501
+
+#define MDLC_MSRESS_STANDBY		0
+#define MDLC_MSRESS_RESET		1
+#define MDLC_MSRESS_STOP		2
+#define MDLC_MSRESS_RUN			3
+
+#define MDLC_MSRES00			0x900
+#define MDLC_MSRESS00			0x960
+#define MDLC_PKCPROT1			0xcf4
+
+struct gen5_mdlc_priv {
+#if IS_ENABLED(CONFIG_SCMI_POWER_DOMAIN)
+	struct udevice	*pd;
+#endif
+#if IS_ENABLED(CONFIG_RESET_SCMI)
+	struct udevice	*rst;
+#endif
+#if IS_ENABLED(CONFIG_SCMI_POWER_DOMAIN) || IS_ENABLED(CONFIG_RESET_SCMI)
+	u32		basever;
+#endif
+#if !IS_ENABLED(CONFIG_SCMI_POWER_DOMAIN) && !IS_ENABLED(CONFIG_RESET_SCMI)
+	void __iomem	*base;
+#endif
+};
+
+static int gen5_pd_of_xlate(struct power_domain *power_domain,
+			    struct ofnode_phandle_args *args)
+{
+	/* Perform direct remap until the bindings stabilize. */
+	power_domain->id = args->args[0];
+
+	return 0;
+}
+
+#if IS_ENABLED(CONFIG_SCMI_POWER_DOMAIN)
+static int gen5_pd_on(struct power_domain *power_domain)
+{
+	struct gen5_mdlc_priv *priv = dev_get_priv(power_domain->dev->parent);
+	struct power_domain_ops *ops = (struct power_domain_ops *)priv->pd->driver->ops;
+	struct power_domain scmi = {
+		.dev = priv->pd,
+		.id = power_domain->id
+	};
+
+	return ops->on(&scmi);
+}
+
+static int gen5_pd_off(struct power_domain *power_domain)
+{
+	struct gen5_mdlc_priv *priv = dev_get_priv(power_domain->dev->parent);
+	struct power_domain_ops *ops = (struct power_domain_ops *)priv->pd->driver->ops;
+	struct power_domain scmi = {
+		.dev = priv->pd,
+		.id = power_domain->id
+	};
+
+	return ops->off(&scmi);
+}
+
+static const struct power_domain_ops pd_gen5_ops = {
+	.on = gen5_pd_on,
+	.off = gen5_pd_off,
+	.of_xlate = gen5_pd_of_xlate,
+};
+
+static int gen5_pd_probe(struct udevice *dev)
+{
+	struct gen5_mdlc_priv *priv = dev_get_priv(dev->parent);
+	struct udevice *agent;
+	int ret;
+
+	if (!priv->basever) {
+		ret = uclass_get_device(UCLASS_SCMI_AGENT, 0, &agent);
+		if (ret)
+			return ret;
+
+		if (!agent)
+			return -ENODEV;
+
+		priv->basever = scmi_impl_version(agent);
+	}
+
+	return uclass_get_device_by_driver(UCLASS_POWER_DOMAIN,
+					   DM_DRIVER_GET(scmi_power_domain),
+					   &priv->pd);
+}
+
+U_BOOT_DRIVER(pd_gen5) = {
+	.name		= "pd_gen5",
+	.id		= UCLASS_POWER_DOMAIN,
+	.ops		= &pd_gen5_ops,
+	.probe		= gen5_pd_probe,
+	.flags		= DM_FLAG_OS_PREPARE | DM_FLAG_VITAL,
+};
+#else
+static const struct power_domain_ops pd_gen5_ops = {
+	.of_xlate = gen5_pd_of_xlate,
+};
+
+U_BOOT_DRIVER(pd_gen5) = {
+	.name		= "pd_gen5",
+	.id		= UCLASS_POWER_DOMAIN,
+	.ops		= &pd_gen5_ops,
+	.flags		= DM_FLAG_OS_PREPARE | DM_FLAG_VITAL,
+};
+#endif
+
+#if IS_ENABLED(CONFIG_RESET_SCMI)
+static int gen5_reset_assert(struct reset_ctl *reset_ctl)
+{
+	struct gen5_mdlc_priv *priv = dev_get_priv(reset_ctl->dev->parent);
+	struct reset_ops *ops = (struct reset_ops *)priv->rst->driver->ops;
+	struct reset_ctl scmi = {
+		.dev = priv->rst,
+		.id = reset_ctl->id
+	};
+
+	return ops->rst_assert(&scmi);
+}
+
+static int gen5_reset_deassert(struct reset_ctl *reset_ctl)
+{
+	struct gen5_mdlc_priv *priv = dev_get_priv(reset_ctl->dev->parent);
+	struct reset_ops *ops = (struct reset_ops *)priv->rst->driver->ops;
+	struct reset_ctl scmi = {
+		.dev = priv->rst,
+		.id = reset_ctl->id
+	};
+
+	return ops->rst_deassert(&scmi);
+}
+
+struct rst_map_in {
+	u16 dt_id;	/* DT binding clock ID */
+	u16 fw_id;	/* SCMI firmware clock ID */
+};
+
+#define GEN5_SCMI_SDK_4_28		0x010a0000
+#define GEN5_SCMI_SDK_4_29		0x010b0000
+#define GEN5_SCMI_SDK_4_30		0x010c0000
+#define GEN5_SCMI_SDK_4_31		0x010d0000
+#define GEN5_SCMI_SDK_4_32		0x010e0000
+
+static const struct rst_map_in gen5_rst_map_dt_sdk_4_28[] = {
+	{ SCP_RESET_DOMAIN_ID_UFS0, 202 },
+	{ SCP_RESET_DOMAIN_ID_UFS1, 203 },
+	{ SCP_RESET_DOMAIN_ID_XPCS0, 316 },
+	{ SCP_RESET_DOMAIN_ID_XPCS1, 317 },
+	{ SCP_RESET_DOMAIN_ID_XPCS2, 318 },
+	{ SCP_RESET_DOMAIN_ID_XPCS3, 319 },
+	{ SCP_RESET_DOMAIN_ID_XPCS4, 320 },
+	{ SCP_RESET_DOMAIN_ID_XPCS5, 321 },
+	{ SCP_RESET_DOMAIN_ID_XPCS6, 322 },
+	{ SCP_RESET_DOMAIN_ID_XPCS7, 323 },
+	{ SCP_RESET_DOMAIN_ID_MPPHY01, 344 },
+	{ SCP_RESET_DOMAIN_ID_MPPHY11, 345 },
+	{ SCP_RESET_DOMAIN_ID_MPPHY21, 346 },
+	{ SCP_RESET_DOMAIN_ID_MPPHY31, 347 },
+	{ SCP_RESET_DOMAIN_ID_MPPHY02, 348 },
+};
+
+static const struct rst_map_in gen5_rst_map_dt_sdk_4_31[] = {
+	{ SCP_RESET_DOMAIN_ID_UFS0, 198 },
+	{ SCP_RESET_DOMAIN_ID_UFS1, 199 },
+	{ SCP_RESET_DOMAIN_ID_XPCS0, 312 },
+	{ SCP_RESET_DOMAIN_ID_XPCS1, 313 },
+	{ SCP_RESET_DOMAIN_ID_XPCS2, 314 },
+	{ SCP_RESET_DOMAIN_ID_XPCS3, 315 },
+	{ SCP_RESET_DOMAIN_ID_XPCS4, 316 },
+	{ SCP_RESET_DOMAIN_ID_XPCS5, 317 },
+	{ SCP_RESET_DOMAIN_ID_XPCS6, 318 },
+	{ SCP_RESET_DOMAIN_ID_XPCS7, 319 },
+	{ SCP_RESET_DOMAIN_ID_MPPHY01, 340 },
+	{ SCP_RESET_DOMAIN_ID_MPPHY11, 341 },
+	{ SCP_RESET_DOMAIN_ID_MPPHY21, 342 },
+	{ SCP_RESET_DOMAIN_ID_MPPHY31, 343 },
+	{ SCP_RESET_DOMAIN_ID_MPPHY02, 344 },
+};
+
+static int gen5_reset_of_xlate(struct reset_ctl *reset_ctl,
+			       struct ofnode_phandle_args *args)
+{
+	struct gen5_mdlc_priv *priv = dev_get_priv(reset_ctl->dev->parent);
+	const struct rst_map_in *map;
+	unsigned int map_size;
+	int i;
+
+	if (args->args_count != 1) {
+		debug("Invalid args_count: %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	if (priv->basever == GEN5_SCMI_SDK_4_28) {
+		map = gen5_rst_map_dt_sdk_4_28;
+		map_size = ARRAY_SIZE(gen5_rst_map_dt_sdk_4_28);
+	} else if (priv->basever == GEN5_SCMI_SDK_4_31 ||
+		   priv->basever == GEN5_SCMI_SDK_4_32) {
+		map = gen5_rst_map_dt_sdk_4_31;
+		map_size = ARRAY_SIZE(gen5_rst_map_dt_sdk_4_31);
+	} else {
+		printf("Unsupported SCMI base protocol version %x\n", priv->basever);
+		return -EINVAL;
+	}
+
+	reset_ctl->id = -1;
+	for (i = 0; i < map_size; i++) {
+		if (map[i].dt_id != args->args[0])
+			continue;
+		reset_ctl->id = map[i].fw_id;
+		break;
+	}
+
+	return 0;
+}
+
+static const struct reset_ops rst_gen5_ops = {
+	.rst_assert = gen5_reset_assert,
+	.rst_deassert = gen5_reset_deassert,
+	.of_xlate = gen5_reset_of_xlate,
+};
+
+static int gen5_rst_probe(struct udevice *dev)
+{
+	struct gen5_mdlc_priv *priv = dev_get_priv(dev->parent);
+	struct udevice *agent;
+	int ret = 0;
+
+	if (!priv->basever) {
+		ret = uclass_get_device(UCLASS_SCMI_AGENT, 0, &agent);
+		if (ret)
+			return ret;
+
+		if (!agent)
+			return -ENODEV;
+
+		priv->basever = scmi_impl_version(agent);
+	}
+
+	return uclass_get_device_by_driver(UCLASS_RESET,
+					   DM_DRIVER_GET(scmi_reset_domain),
+					   &priv->rst);
+}
+#else
+static int mdlc_wait_for_reset(struct reset_ctl *reset_ctl)
+{
+	struct gen5_mdlc_priv *priv = dev_get_priv(reset_ctl->dev->parent);
+	const u32 offset = (reset_ctl->id / 16) * 4;
+	void __iomem *res = priv->base + MDLC_MSRES00 + offset;
+	void __iomem *stat = priv->base + MDLC_MSRESS00 + offset;
+	u32 val;
+	int ret;
+
+	/* Wait 100ms for reset controller to synchronize. */
+	ret = readl_poll_timeout(res, val, val == readl(stat), 100000);
+	if (ret < 0)
+		dev_err(reset_ctl->dev, "Reset controller out of sync!\n");
+
+	return ret;
+}
+
+static void mdlc_rmw_msres(struct reset_ctl *reset_ctl, const int val)
+{
+	struct gen5_mdlc_priv *priv = dev_get_priv(reset_ctl->dev->parent);
+	const u32 offset = (reset_ctl->id / 16) * 4;
+	const u32 mask = 3 << ((reset_ctl->id % 16) * 2);
+	void __iomem *prot = priv->base + MDLC_PKCPROT1;
+	void __iomem *res = priv->base + MDLC_MSRES00 + offset;
+	u32 reg;
+
+	reg = readl(res);
+	reg &= ~mask;
+	reg |= field_prep(mask, val);
+
+	writel(PKC_PROT_UNLOCK, prot);
+	writel(reg, res);
+	writel(PKC_PROT_LOCK, prot);
+}
+
+static int gen5_reset_toggle(struct reset_ctl *reset_ctl, const u8 step1,
+			     const u8 step2, const u8 step3, const u8 step4)
+{
+	struct gen5_mdlc_priv *priv = dev_get_priv(reset_ctl->dev->parent);
+	const u32 offset = (reset_ctl->id / 16) * 4;
+	const u32 mask = 3 << ((reset_ctl->id % 16) * 2);
+	void __iomem *stat = priv->base + MDLC_MSRESS00 + offset;
+	u32 status;
+	int ret;
+
+	ret = mdlc_wait_for_reset(reset_ctl);
+	if (ret)
+		return ret;
+
+	status = field_get(mask, readl(stat));
+	if (status == step1) {
+		mdlc_rmw_msres(reset_ctl, step2);
+		ret = mdlc_wait_for_reset(reset_ctl);
+		if (ret)
+			return ret;
+		status = field_get(mask, readl(stat));
+	}
+
+	if (status == step2 || status == step3) {
+		mdlc_rmw_msres(reset_ctl, step4);
+		ret = mdlc_wait_for_reset(reset_ctl);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int gen5_reset_assert(struct reset_ctl *reset_ctl)
+{
+	return gen5_reset_toggle(reset_ctl,
+				 MDLC_MSRESS_STOP, MDLC_MSRESS_STANDBY,
+				 MDLC_MSRESS_RUN, MDLC_MSRESS_RESET);
+}
+
+static int gen5_reset_deassert(struct reset_ctl *reset_ctl)
+{
+	return gen5_reset_toggle(reset_ctl,
+				 MDLC_MSRESS_STANDBY, MDLC_MSRESS_RESET,
+				 MDLC_MSRESS_STOP, MDLC_MSRESS_RUN);
+}
+
+static int gen5_reset_of_xlate(struct reset_ctl *reset_ctl,
+			       struct ofnode_phandle_args *args)
+{
+	/* Perform direct remap until the bindings stabilize. */
+	reset_ctl->id = args->args[0];
+
+	return 0;
+}
+
+static const struct reset_ops rst_gen5_ops = {
+	.rst_assert = gen5_reset_assert,
+	.rst_deassert = gen5_reset_deassert,
+	.of_xlate = gen5_reset_of_xlate,
+};
+
+static int gen5_rst_probe(struct udevice *dev)
+{
+	struct gen5_mdlc_priv *priv = dev_get_priv(dev->parent);
+
+	priv->base = dev_read_addr_ptr(dev);
+	if (!priv->base)
+		return -EINVAL;
+
+	return 0;
+}
+#endif
+
+U_BOOT_DRIVER(rst_gen5) = {
+	.name		= "rst_gen5",
+	.id		= UCLASS_RESET,
+	.ops		= &rst_gen5_ops,
+	.probe		= gen5_rst_probe,
+	.flags		= DM_FLAG_OS_PREPARE | DM_FLAG_VITAL,
+};
+
+int gen5_mdlc_bind(struct udevice *parent)
+{
+	struct udevice *pdev, *rdev;
+	struct driver *pdrv, *rdrv;
+	int ret;
+
+	pdrv = lists_driver_lookup_name("pd_gen5");
+	if (!pdrv)
+		return -ENOENT;
+
+	rdrv = lists_driver_lookup_name("rst_gen5");
+	if (!rdrv)
+		return -ENOENT;
+
+	ret = device_bind_with_driver_data(parent, pdrv, "pd_gen5", 0,
+					   dev_ofnode(parent), &pdev);
+	if (ret)
+		return ret;
+
+	ret = device_bind_with_driver_data(parent, rdrv, "rst_gen5", (ulong)pdev,
+					   dev_ofnode(parent), &rdev);
+	if (ret)
+		device_unbind(pdev);
+
+	return ret;
+}
+
+static const struct udevice_id r8a78000_mdlc_ids[] = {
+	{ .compatible = "renesas,r8a78000-mdlc", },
+	{ }
+};
+
+U_BOOT_DRIVER(mdlc_gen5) = {
+	.name		= "mdlc_gen5",
+	.id		= UCLASS_NOP,
+	.of_match	= r8a78000_mdlc_ids,
+	.bind		= gen5_mdlc_bind,
+	.priv_auto	= sizeof(struct gen5_mdlc_priv),
+};
--- a/include/configs/rcar-gen5-common.h
+++ b/include/configs/rcar-gen5-common.h
@@ -10,10 +10,15 @@

 /* Console */
 #define CFG_SYS_BAUDRATE_TABLE		{ 38400, 115200, 921600, 1843200, 3250000 }
+#define CFG_HSCIF

 /* Memory */
-#define DRAM_RSV_SIZE			0x08000000
+#define DRAM_RSV_SIZE			0x20600000
+#ifdef CONFIG_RCAR_64_RSIP
+#define CFG_SYS_SDRAM_BASE		0xb8400000
+#else
 #define CFG_SYS_SDRAM_BASE		(0x40000000 + DRAM_RSV_SIZE)
+#endif
 #define CFG_SYS_SDRAM_SIZE		(0x80000000u - DRAM_RSV_SIZE)
 #define CFG_MAX_MEM_MAPPED		(0x80000000u - DRAM_RSV_SIZE)

--- a/include/dt-bindings/clock/r8a78000-clock-scmi.h
+++ b/include/dt-bindings/clock/r8a78000-clock-scmi.h
@@ -43,4 +43,6 @@
 #define SCP_CLOCK_ID_MDLC_MPPHY31	347
 #define SCP_CLOCK_ID_MDLC_MPPHY02	348

+#define SCP_CLOCK_ID_CLK_S0D6_PERE_MAIN	1691
+
 #endif /* __DT_BINDINGS_R8A78000_SCMI_CLOCK_H__ */
--- a/include/dt-bindings/reset/r8a78000-reset-scmi.h
+++ b/include/dt-bindings/reset/r8a78000-reset-scmi.h
@@ -1,33 +1,27 @@
 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
 /*
- * Copyright (C) 2025 Renesas Electronics Corp.
- *
- * IDs match SCP 4.27
+ * Copyright (C) 2025-2026 Renesas Electronics Corp.
 */

 #ifndef __DT_BINDINGS_R8A78000_SCMI_RESET_H__
 #define __DT_BINDINGS_R8A78000_SCMI_RESET_H__

-/*
- * These definition indices match the Reset ID defined by SCP FW 4.27.
- */
+#define SCP_RESET_DOMAIN_ID_UFS0	0x60
+#define SCP_RESET_DOMAIN_ID_UFS1	0x61

-#define SCP_RESET_DOMAIN_ID_UFS0	202
-#define SCP_RESET_DOMAIN_ID_UFS1	203
+#define SCP_RESET_DOMAIN_ID_XPCS0	0x30
+#define SCP_RESET_DOMAIN_ID_XPCS1	0x31
+#define SCP_RESET_DOMAIN_ID_XPCS2	0x32
+#define SCP_RESET_DOMAIN_ID_XPCS3	0x33
+#define SCP_RESET_DOMAIN_ID_XPCS4	0x34
+#define SCP_RESET_DOMAIN_ID_XPCS5	0x35
+#define SCP_RESET_DOMAIN_ID_XPCS6	0x36
+#define SCP_RESET_DOMAIN_ID_XPCS7	0x37

-#define SCP_RESET_DOMAIN_ID_XPCS0	316
-#define SCP_RESET_DOMAIN_ID_XPCS1	317
-#define SCP_RESET_DOMAIN_ID_XPCS2	318
-#define SCP_RESET_DOMAIN_ID_XPCS3	319
-#define SCP_RESET_DOMAIN_ID_XPCS4	320
-#define SCP_RESET_DOMAIN_ID_XPCS5	321
-#define SCP_RESET_DOMAIN_ID_XPCS6	322
-#define SCP_RESET_DOMAIN_ID_XPCS7	323
-
-#define SCP_RESET_DOMAIN_ID_MPPHY01	344
-#define SCP_RESET_DOMAIN_ID_MPPHY11	345
-#define SCP_RESET_DOMAIN_ID_MPPHY21	346
-#define SCP_RESET_DOMAIN_ID_MPPHY31	347
-#define SCP_RESET_DOMAIN_ID_MPPHY02	348
+#define SCP_RESET_DOMAIN_ID_MPPHY01	0x64
+#define SCP_RESET_DOMAIN_ID_MPPHY11	0x65
+#define SCP_RESET_DOMAIN_ID_MPPHY21	0x66
+#define SCP_RESET_DOMAIN_ID_MPPHY31	0x67
+#define SCP_RESET_DOMAIN_ID_MPPHY02	0x68

 #endif /* __DT_BINDINGS_R8A78000_SCMI_RESET_H__ */