Merge patch series "Fix speculative access to firewalled regions on AM62 SoCs"

Anshul Dalal <anshuld@ti.com> says:

This patch series fixes firewall exceptions observed on AM62 family of
devices due to speculative accesses made by the A53 core to secure DDR
regions.

Link: https://lore.kernel.org/r/20260520-am62_firewall_exception_fix-v3-0-9ca3dc40aea4@ti.com

arch/arm/cpu/armv8/cache_v8.c

@@ -810,8 +810,10 @@ __weak void mmu_setup(void)
 	el = current_el();
 	set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(NULL, NULL),
 			  MEMORY_ATTRIBUTES);
+}
 
-	/* enable the mmu */
+void mmu_enable(void)
+{
 	set_sctlr(get_sctlr() | CR_M);
 }
 
@@ -881,6 +883,7 @@ void dcache_enable(void)
 	if (!mmu_status()) {
 		__asm_invalidate_tlb_all();
 		mmu_setup();
+		mmu_enable();
 	}
 
 	/* Set up page tables only once (it is done also by mmu_setup()) */

arch/arm/include/asm/armv8/mmu.h

@@ -222,6 +222,11 @@ u64 get_tcr(u64 *pips, u64 *pva_bits);
  * mmu_setup() - Sets up the mmu page tables as per mem_map
  */
 void mmu_setup(void);
+
+/**
+ * mmu_enable() - Enable the MMU by setting 'M' bit in SCTLR register
+ */
+void mmu_enable(void);
 #endif
 
 #endif /* _ASM_ARMV8_MMU_H_ */

arch/arm/mach-k3/common.c

@@ -294,6 +294,7 @@ void enable_caches(void)
 			       __func__, ret);
 	}
 
+	mmu_enable();
 	icache_enable();
 	dcache_enable();
 }