Commit Graph

95116 Commits

Author SHA1 Message Date
Chia-Wei Wang
2db018d2ca configs: ibex-ast2700: Enable DRAM and timer driver
Enable the driver support for the DRAM and timer devices.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-09-11 20:35:04 +08:00
Chia-Wei Wang
a1ad11ce52 ram: ast2700: Add DRAM controller initialization
Add driver for AST2700 to initialize DRAM in SPL.

This patch also refactors the Kconfig dependency of
Aspeed DRAM drivers as some of them are shared among
the file structures of RV and ARM ISAs.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-09-11 20:35:03 +08:00
Chia-Wei Wang
73f802ac95 board: ibex_ast2700: Add FMC header support
Define and parse the header of the First Mutable Code (FMC)
of AST2700 SoCs at runtime phase.

The FMC header contains the information to load prebuilt binaries
required for device initialization such as DRAM and VGA.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-09-11 20:35:03 +08:00
Chia-Wei Wang
4b0129e810 timer: Add AST2700 IBEX timer support
Add the driver for the AST2700 Ibex timer, which uses CPU
cycles as the timer count running at 200MHz.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-09-11 20:35:03 +08:00
Chia-Wei Wang
9efcb10a09 riscv: Add AST2700 SoC initial platform support
AST2700 SoCs integrates a Ibex 32-bits RISC-V core as the boot MCU
for the first stage bootloader execution, namely SPL.

This patch implements the preliminary base to successfully run SPL
on this RV32-based MCU to the console banner message.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-09-11 20:35:03 +08:00
Chia-Wei Wang
717002f8ff riscv: u-boot-spl.lds: Remove _image_binary_end alignment
The _image_binary_end symbol was aligned to the 8-bytes boundary.
However, the SPL device tree (u-boot-spl.dtb) is concatenated right
after the binary (u-boot-spl-nodtb.bin) wihtout the consideration of
the 8-bytes alignment restriction.

After then, for the SPL_SEPARATE_BSS case, fdtdec_setup() searching
for the DTB by _image_binary_end will return the "Missing DTB" error.
As the real DTB starting point does not align to a 8-bytes address
like _image_binary_end does.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-09-11 20:35:03 +08:00
Chia-Wei Wang
248292f499 riscv: Make stack size shift configurable
Add prompt for STACK_SIZE_SHIFT to make it configurable.
The default value remains 14 as usual.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-09-11 20:35:03 +08:00
Chia-Wei Wang
9c0ed72142 riscv: Make A ISA extension selectable
Make the Atomic (A) ISA extension selectable. Thus CPUs such as
Ibex without the A extension can be supported.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-09-11 20:35:03 +08:00
Jacky Chou
db378b0f18 driver: net: Add Aspeed AST2700 MDIO support
The AST2700 is the 7th generation SoC from Aspeed.
And use the driver to support clause 22 access.

Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-09-11 20:34:48 +08:00
Jacky Chou
c724f3ed74 net: ftgmac100: Add Aspeed AST2700 support
Add support of Aspeed AST2700 SoC.  AST2700 is based on ARM64 so modify
the DMA address related code to fit both ARM and ARM64.  Besides, the
RMII/RGMII mode control register is moved from SCU500 to MAC50 so
initialize the register in ftgmac100_start correspondingly.

Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-09-11 20:34:43 +08:00
Jacky Chou
40c45a5797 net: ftgmac100: Modify desc. size to cache line
The TX/RX descriptor size is 16 byte.
When the cache line size is larger than 16 bytes, descriptors
flushed to RAM will flush more than one descriptor.
It is possible that it may mistakenly flush to other descriptor
that has been updated by MAC in RAM.

To avoid this issue, align the descriptors to cache line size.
Only one desc will be flushed or invalidated at a time.

Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-09-11 20:34:39 +08:00
Jacky Chou
a0f4e43c59 net: ftgmac100: Fixed NC-SI PHY device cannot get
The NC-SI interface does not need the MDIO bus and the
NC-SI PHY device cannot get from dm_eth_phy_connect.
Therefore, use phy_connect directly here.

Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-09-11 20:34:35 +08:00
Jacky Chou
21d5d5e55b net: ftgmac100: Fixed the cache coherency issues of rx memory
When executing TFTP, the ARP will be replied to after receiving
the ARP. U-boot's ARP routine modifies the data in the receive
packet in response to the ARP packet and then copies it
into the transmit packet.
At this point, the received packet cache is inconsistent.
It is possible that the cache will perform a writeback action to
affect the MAC receiving packets.

Avoid the same problem that occurs in other networking protocols.
In the free_pkt function, ensure cache and memory consistency.

Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-09-11 20:34:31 +08:00
Kongyang Liu
aa4a03f2e2 riscv: dts: sophgo: Replace device clocks with real clocks.
Replace device clocks with real clocks from the clock controller, and
remove dummy clocks.

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-09-11 20:32:06 +08:00
Kongyang Liu
78c04aea8c configs: milkv_duo: Enable clock controller
Add configs to enable clock controller for Sophgo Milk-V Duo board

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-09-11 20:32:06 +08:00
Kongyang Liu
5f364e072e clk: sophgo: cv1800b: Add clock controller driver for cv1800b SoC
Add clock controller driver for sophgo cv1800b SoC

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-09-11 20:32:06 +08:00
Kongyang Liu
bd2f42230e dt-bindings: clk: import header for clock controller of sophgo CV1800B
Import header file of sophgo cv1800b clock controller from kernel

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Link: https://lore.kernel.org/all/IA1PR20MB4953637E7A6C121D7A700F1CBB8BA@IA1PR20MB4953.namprd20.prod.outlook.com/
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-09-11 20:32:06 +08:00
Tom Rini
78d898eec0 Merge patch series "phycore-am62/4: Add more boot sources"
Daniel Schultz <d.schultz@phytec.de> says:

This patch stack extends the phyCORE-AM62x/AM64x U-Boot by following boot
sources:

  - Load U-Boot with USB DFU
  - Load a Linux and initramfs from OSPI/QSPI NOR flash
  - Load a Linux and rootfs from Network

Moreover, it adds required changes to the environment to boot an A/B
system with RAUC and includes some minor fixes.
2024-09-10 14:56:12 -06:00
Daniel Schultz
ef7a3f16a2 configs: phycore_am62x_*_defconfig: Set PHYTEC as Manufacturer
Commit 371b379edb ("configs: Make USB_GADGET_MANUFACTURER
consistent over all PHYTEC boards") made the USB_GADGET_MANUFACTURER
value consistent over all PHYTEC boards.

Update the phyCORE-AM62x defconfigs to make this config consistent
as well.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
2024-09-10 13:16:02 -06:00
Daniel Schultz
1bd194f1ff configs: phycore_am62x_a53_defconfig: Fix CONFIG_ENV_SIZE
The environment should have a size of 0x20000 instead 0x2000.
Update to have the same environment size for all PHYTEC K3 products.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
2024-09-10 13:16:02 -06:00
Daniel Schultz
4d197fab9b configs: Add phycore_am62x_r5_usbdfu_defconfig
This config includes the phycore_am62x_r5_defconfig file as well as
the am62x_r5_usbdfu.config fragment. We need another defconfig
because the AM62x has not enough internal SRAM to support all boot
sources. The normal phycore_am62x_r5_defconfig should allow to boot
from MMC and OSPI while this new defconfig allows to boot from USB.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
2024-09-10 13:16:01 -06:00
Daniel Schultz
529ddb6053 configs: phycore_am62x_a53_defconfig: Merge am62x_a53_usbdfu.config
Merge the am62x_a53_usbdfu.config into the phyCORE-AM62x A53 defconfig to
properly support USB DFU boot.

This config was made with the following command:

    make ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- \
        phycore_am62x_a53_defconfig am62x_a53_usbdfu.config

However, CONFIG_USB_GADGET_MANUFACTURER was not merged to keep Phytec
as manufacturer.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
2024-09-10 13:16:01 -06:00
Daniel Schultz
8b4a72f513 configs: phycore_am64x_a53_defconfig: Make BOOTCMD generic
The phyCORE-AM64x board code sets an environment variable 'boot'
with the device U-Boot booted from. Use this variable in
CONFIG_BOOTCOMMAND to boot Linux from the same boot device by
default.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
2024-09-10 13:16:01 -06:00
Daniel Schultz
9624465384 configs: phycore_am62x_a53_defconfig: Make BOOTCMD generic
The phyCORE-AM62x board code sets an environment variable 'boot'
with the device U-Boot booted from. Use this variable in
CONFIG_BOOTCOMMAND to boot Linux from the same boot device by
default.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
2024-09-10 13:16:01 -06:00
Daniel Schultz
11b8fa0095 board: phytec: phycore_am64x: Add Network/SPI Boot
Include the boot logic to boot via Network or from a OSPI/QSPI
NOR flash. Moreover, set all required variables to both boot
methods to the environment.

Note: The phyBOARD-Electra AM64x is not able to load the U-Boot
via Network. However, it's still possible to load the kernel.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
2024-09-10 13:16:01 -06:00
Daniel Schultz
a48cbaeecb board: phytec: phycore_am62x: Add Network/SPI Boot
Include the boot logic to boot via Network or from a OSPI/QSPI
NOR flash. Moreover, set all required variables to both boot
methods to the environment.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
2024-09-10 13:16:01 -06:00
Daniel Schultz
92ff68b298 include: env: phytec: Add K3 boot logic for OSPI/QSPI flashes
This boot logic allows to boot a Kernel image, Device-Tree blob
and a initramfs from an external OSPI/QSPI NOR flash.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
2024-09-10 13:16:01 -06:00
Daniel Schultz
d87842cd3d include: net: phytec: Add K3 network boot logic
This boot logic allows to boot a Kernel image, Device-Tree blob
and overlays via tftp/dhcp (configurable with 'net_fetch_cmd').
Additionally, it loads a rootfs via NFS.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
2024-09-10 13:16:01 -06:00
Daniel Schultz
8cafb21215 include: env: phytec: Add raucinit to k3_mmc environment
Initialize the environment for booting an RAUC image when
'doraucboot' is set to 1.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
2024-09-10 13:16:01 -06:00
Daniel Schultz
80c4f6f9f2 include: env: phytec: k3_mmc: Rename variables
Add a mmc prefix to 'loadimage' and 'loadfdt' because we need
similar variables for other boot sources. This will prevent
name clashes and allows to implement similar boot logic.

Also switch from loadaddr to kernel_addr_r.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
2024-09-10 13:16:01 -06:00
Wadim Egorov
d0bc2ac2bd configs: phycore_am64x_a53_defconfig: Enable CONFIG_OF_BOARD_SETUP
Enable CONFIG_OF_BOARD_SETUP to fixup kernel device tree with mtd
partitions.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
2024-09-10 13:16:01 -06:00
Daniel Palmer
c6eba28c46 spl: spl_load: fix comparison between negative error code and unsigned size
read could be a negative error value but size in spl_image is unsigned
so when they are compared read is used as if it's a unsigned value
and if it's negative it'll most likely be bigger than size and the
result will be true and _spl_load() will return 0 to the caller.

This results in the caller to _spl_load() not seeing that an error happened
as it should and continuing as if the load was completed when it might
not have been.

Check if read is negative and return it's value if it is before comparing
against size in spl_image.

Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-09-10 13:15:13 -06:00
Love Kumar
2349cc00d9 test/py: spi: Set the expected error message
If erase/write/read size is 0 then it throws the mentioned error message
when debug message ie enabled as per 899fb5aa8b ("cmd: sf/nand: Print
and return failure when 0 length is passed"), setting it to None as
debug message is not enabled by default for testing.

Signed-off-by: Love Kumar <love.kumar@amd.com>
2024-09-10 13:15:06 -06:00
Rasmus Villemoes
52ec7b7c89 treewide: drop redundant "type string" for SYS_SOC and friends
The Kconfig symbols SYS_ARCH, SYS_CPU, SYS_SOC, SYS_VENDOR and
SYS_BOARD are defined in arch/Kconfig as having type string, and most
board files simply amend those definition with suitable

  default "foo"

or

  default "foo" if BAR

stanzas. But some also include a redundant repetition of the type.

Homogenize the code base by removing those lines.

Generated by

  find arch/*/ board -name Kconfig | xargs perl -i -g -pe 's/(config SYS_(ARCH|CPU|SOC|VENDOR|BOARD)\n)\s*string\n/\1/gs'

with the trailing slash in arch/*/ ensuring that arch/Kconfig itself
is not found.

This does not change boards which add a prompt string, e.g.

  string "Board name"

because I think those change the semantics of the symbol into being
user-settable.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Tom Rini <trini@konsulko.com>
2024-09-10 13:14:59 -06:00
Tom Rini
2def0df217 arm: Remove ethernut5 board
As per the maintainers at egnite GmbH, they are no longer interested in
supporting this board. Go and remove the platform here. Furthermore,
this is the only AT91SAM9XE platform in-tree so remove supporting code
for that as well.

Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2024-09-10 13:12:32 -06:00
Jerome Forissier
278e9ac8aa net: guard call to tftp_start() with IS_ENABLED(CONFIG_CMD_TFTPBOOT)
net_auto_load() cannot call tftp_start() if CONFIG_CMD_TFTPBOOT is
disabled.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2024-09-10 13:08:24 -06:00
Tom Rini
ca55cf8104 Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-usb into next 2024-09-09 15:54:56 -06:00
Tom Rini
48038bfb4d Merge branch 'qcom-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-snapdragon into next
Various improvements to Snapdragon support:

* Bumped up the pagetable size to handle newer SoCs with much more RAM
* Made memory map parsing more robust, fixing chainloading on
  SM8550/SM8650
* Populate fdt_addr_r with U-Boot's FDT by default, and set $loadaddr to
  prevent
  crashes with some commands which expect it
* Added initial support for SC7280/QCM6490 and the new RB3 Gen 2 board
* Add debug config fragments to enable debug UART on some SoCs.
* Enable RPMh regulators on SM8550/SM8650
* Map the cmd-db memory explicitly since it may not be in the memory map

CI: https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/pipelines/22255
2024-09-09 10:52:55 -06:00
Marek Vasut
e72e683e36 phy: test: Implement sandbox PHY .set_mode and DM test
Implement trivial extension to the sandbox PHY, which makes it pretend
to support selecting USB Host mode and nothing else. Any other mode is
rejected with -EINVAL. Any submode except for default submode 0 is
rejected with -EOPNOTSUPP . The implementation behaves in this trivial
way to permit easy unit testing using test which is also added in this
commit.

To run the test, use e.g. sandbox64_defconfig and run U-Boot as follows:
$ ./u-boot -Tc 'ut dm phy_setup'

Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-09-09 17:18:04 +02:00
Marek Vasut
a1f841a33c phy: rcar: Split init and set_mode operations
The current init operation also sets the PHY into USB host mode.
Split the mode configuration into set_mode callback instead and
implement support for device and OTG modes as well.

The OTG mode performs auto-detection and selects either host or
device mode. In case the OTG mode is configured, submode field
can be used to select full PHY (re)initialization or only mode
auto-detection. The full (re)initialization is only necessary
once, on start up.

Since the OTG mode may enable IRQ generation in the PHY, disable
that IRQ generation in the exit callback again.

Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-09-09 17:18:04 +02:00
Marek Vasut
35941d3a96 phy: Extend generic_setup_phy() with PHY mode and submode
Extend generic_setup_phy() parameter list with PHY mode and submode and
call generic_phy_set_mode() in generic_setup_phy(), so the generic PHY
setup function can configure the PHY into correct mode before powering
the PHY up.

Update all call sites of generic_setup_phy() as well, all of which are
USB host related, except for DM test which now behaves as a USB host
test.

Note that if the PHY driver does not implement the .set_mode callback,
generic_phy_set_mode() call returns 0 and does not error out, so this
should not break any existing systems.

Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-09-09 17:18:04 +02:00
Simon Glass
d0f74bd417 buildman: Support building within a Python venv
The Python virtualenv tool sets up a few things in the environment,
putting its path first in the PATH environment variable and setting up
a sys.prefix different from the sys.base_prefix value.

At present buildman puts the toolchain path first in PATH so that it can
be found easily during the build. For sandbox this causes problems since
/usr/bin/gcc (for example) results in '/usr/bin' being prepended to the
PATH variable. As a result, the venv is partially disabled.

The result is that sandbox builds within a venv ignore the venv, e.g.
when looking for packages.

Correct this by detecting the venv and adding the toolchain path after
the venv path.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-09-06 12:45:54 -06:00
Caleb Connolly
41864bb2b6 board/qualcomm: add debug config fragments for some SoCs
We already have some documentation describing how to enable debug UART
for Qualcomm SoCs. However the UART address varies per-soc... Add some
config fragments to enable debug UART for few well supported SoCs.

These can be used like:

$ make qcom_defconfig debug-sdm845.config

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-09-06 11:59:51 +02:00
Caleb Connolly
224c90ede4 doc: board/qualcomm: document rb3gen2 building/flashing
The process here is almost identical to the Dragonboard 410c, we've come
full circle!

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-09-06 11:59:51 +02:00
Caleb Connolly
adc310c7af configs: add qcm6490_defconfig
Introduce a defconfig for the RB3 Gen 2 and other QCM6490 boards with a
dedicated uefi partition. These can replace EDK2 entirely with U-Boot.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-09-06 11:59:51 +02:00
Caleb Connolly
3176b5a2b2 qcom_defconfig: enable SC7280 clocks
Enable clocks on SC7280

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-09-06 10:47:47 +02:00
Caleb Connolly
2bb90ac29f iommu: qcom-smmu: add sc7280-smmu-500 compatible
This soc doesn't have the generic compatible.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-09-06 10:47:47 +02:00
Caleb Connolly
39e0e9fd19 dts: qcs6490-rb3gen2-u-boot: USB host mode
Adjust DTS so USB runs in host mode. The type-c port is the only
supported port (since the others need PCIe). Booting from USB is
possible with a powered type-c dock.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-09-06 10:47:47 +02:00
Caleb Connolly
259dba80dc dts: qcs6490-rb3gen2-u-boot: add override dtsi
For running U-Boot as primary bootloader we must define the memory
layout statically.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-09-06 10:47:47 +02:00
Caleb Connolly
f50e7be6bb clk/qcom: add initial clock driver for sc7280
We don't actually need any clocks to get UFS up and running, resets are
useful though.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-09-06 10:47:46 +02:00