The hardware only supports a specific console port, so remove the
option to change the console location in the environment.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
The address ariel.dalessandro@collabora.com is no longer working:
A message that you sent could not be delivered to one or more of its
recipients. This is a permanent error. The following address(es) failed:
ariel.dalessandro@collabora.com
host mx.collabora.co.uk [46.235.227.165]
SMTP error from remote mail server after RCPT TO:<ariel.dalessandro@collabora.com>:
550 5.1.1 <ariel.dalessandro@collabora.com>: Recipient address rejected:
undeliverable address: host mail.collabora.co.uk[46.235.227.172] said:
550 5.1.1 <ariel.dalessandro@collabora.com>: Recipient address rejected:
User unknown in local recipient table (in reply to RCPT TO command)
Remove this address from MAINTAINERS.
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
With DM enabled, there is no need for board code to initialize
the FEC interface.
The ethernet PHYs on the symphony carrier board have a dedicated
crystal/oscillator. If the SOM has the EC configuration option
(onboard ethernet PHY), it also has a dedicated crystal/oscillator.
So in all cases, there is no need to enable the RGMII TX clk output.
This follows a similar change introduced by Fabio Estevam:
Link: https://lore.kernel.org/u-boot/20231019170441.1610453-1-festevam@gmail.com/
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
I would like to help maintaining the imx8mn_var_som symphony board.
Add myself to MAINTAINERS.
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
When CONFIG_DWC_ETH_QOS_IMX=y and CONFIG_FEC_MXC is not selected, the
following warning is seen:
arch/arm/mach-imx/imx8m/clock_imx8mm.c: In function 'board_interface_eth_init':
arch/arm/mach-imx/imx8m/clock_imx8mm.c:914:24: warning: implicit declaration of function 'imx8mp_fec_interface_init; did you mean 'imx8mp_eqos_interface_init'? [-Wimplicit-function-declaration]
Fix it by adding a stub for imx8mp_fec_interface_init() to handle this
case.
This follows the same approach done on imx8mp_eqos_interface_init().
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
With DM enabled, there is no need for board code to initialize
the Ethernet interfaces.
The RTL8211FDI Ethernet PHYs have 25MHz oscillator, so there is no
need to enable the RGMII TX clk output.
Also, there is no need for describing the deprecated phy-reset FEC
properties, nor passing reset properties to the EQOS interface in
u-boot.dtsi.
Remove all these unneeded pieces.
Tested both Ethernet interfaces after these changes.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Currently, when running "ums 0 mmc 2" and breaking it via
CTRL + C, the following message is seen:
u-boot=> ums 0 mmc 1
UMS: LUN 0, dev mmc 1, hwpart 0, sector 0x0, count 0x1dacc00
CTRL+C - Operation aborted
clk usb_phy_root_clk already disabled
The USB PHY clock is disabled twice: first it gets disabled
inside imx8mq_usb_phy_power_off(), then it is disabled again
inside imx8mq_usb_phy_exit().
Let the USB PHY clock be disabled only once inside
imx8mq_usb_phy_power_off() by removing the .exit operation.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Sync imx8mm.dtsi with linux-next 20231019.
The motivation for doing this sync was a bug when doing "ums 0 mmc 1"
on imx8mm-evk. It worked well for the first time, but after doing
a CTRL+C and launching the ums again, the command did not work.
Adam Ford suggested to sync imx8mm.dtsi with the Linux dts, as there was
a recent USB power domain reorganization there.
After syncing the imx8mm.dtsi with Linux, the ums command works without
problem after a CTRL+C.
Suggested-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
I would like to help maintaining the imx8mp_evk board.
Add myself to MAINTAINERS.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Acked-by: Peng Fan <peng.fan@nxp.com>
Currently, the imx8mp_evk uses the non-DM code to initialize the PMIC.
Convert to DM_PMIC, which is the recommended way to access the PMIC.
While at it, fix multi-line comments style.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Add the TPM device found on the GW73xx revision F PCB.
This hangs off of SPI2, uses gpio1_10 as a CS and gpio1_11 as RST#.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Add the TPM device found on the GW73xx revision F PCB.
This hangs off of SPI2, uses gpio1_10 as a CS and gpio1_11 as RST#.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Add Variscite manufacturer to the IMX8MN_VAR_SOM target menu label as
the majority of targets include the manufacturer as part of their menu
description/label and it helps when looking for a particular
manufacturer/board.
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
The correct compatible string for i.MX93 variant of DWC EQoS MAC is now
"nxp,imx93-dwmac-eqos".
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Add a common board_interface_eth_init() called by the DWC MAC driver to
setup the MAC <-> PHY interface according to the PHY mode obtained from
DT.
Remove the board-side configuration in the i.MX93 EVK files.
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Change boot device logic to also allow environment stored in fat and
in ext4 when booting from SD or eMMC.
As the boot device check for SD and for eMMC was depending on
ENV_IS_IN_MMC being defined, change the ifdef blocks at
env_get_location to use IS_ENABLED instead for all modes, returning
NOWHERE when no valid mode is found.
Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Co-developed-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
The interrupt collector macro name for i.MX23 is MXS_ICOLL_BASE,
this is correct and matches the documentation of both i.MX23 and
i.MX28. Align the i.MX28 macro accordingly. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Sync the devicetree files used in the kernel for the imx8mm-phyboard-polis
with the corresponding devicetree files in U-Boot.
Replaced phycore-imx8mm.dts with kernel dts imx8mm-phyboard-polis-rdk.dts
Synced with kernel 6.5.0-rc1 commit
e752a4f9589c (arm64: dts: freescale: imx8mm-phyboard: Add I2C4 pinmuxing)
Signed-off-by: Cem Tenruh <c.tenruh@phytec.de>
Commit 0aea5dda29 ("ARM: dts: imx7d-sdb-u-boot: Fix usdhc1 UHS
operation") did a temporary workaround by addng the usdhc1 fix
inside the -u-boot.dtsi file.
The imx7d-sdb.dts from kernel 6.5-rc1 contains the proper UHS
fix, so sync the devicetree tree and remove the previous fix
from -u-boot.dtsi.
Also, adjust the PMIC node name inside pmic_get() to match
the devicetree update.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Add support for the Polyhex Debix Model A SBC board.
It is an industrial grade single board computer based on
NXP's i.MX 8M Plus.
Currently supported interfaces are:
- Serial console
- Micro SD
- eQOS and FEC Ethernet
imx8mp-debix-model-a.dts is taken from Linux 6.3.
Signed-off-by: Gilles Talis <gilles.talis@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Currently, building imx8qm_dmsse20a1_defconfig leads to the following
warning:
aarch64-linux-ld.bfd: invalid origin for memory region .sdram
Fix it by using the same SPL memory layout as done in the imx8mq_evk.
Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
Tested-by: Oliver Graute <oliver.graute@kococonnector.com>
Function ddr_load_train_firmware() is called 4 times in a loop by
ddr_cfg_phy(). The first 3 calls are all '1D' type and just loading the
same FWs. Let's add a type check and save 2 of them. This helps to
reduce DDRPHY training time from 269 ms down to 212 ms, and thus speed
up boot time ~ 50 ms.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Fabio Estevam <festevam@denx.de>
As of now only one mailbox agent is supported by mailbox driver.
On zynqmp platform there are about 7 mailbox agents which can communicate
over same IPI channel to U-Boot. This patch series introduces new
"zynqmp_ipi_dest" driver which adds one to multi-channel mailbox
support.
Following format in device-tree is expected as per latest bindings:
zynqmp-ipi {
compatible = "xlnx,zynqmp-ipi-mailbox";
mbox_1: mailbox@1 {
/* New compatible for child node */
compatible = "xlnx,zynqmp-ipi-dest-mailbox";
...
};
...
mbox_n: mailbox@n {
compatible = "xlnx,zynqmp-ipi-dest-mailbox";
...
}
};
Then mailbox client uses child mailbox node as following:
ipi-dest-1 {
...
mboxes = <mbox_1 0>, <mbox_1 1>;
mbox-names = "tx", "rx";
...
};
New "zynqmp_ipi_dest" driver is for devices with
"xlnx,zynqmp-ipi-dest-mailbox" compatible string. This driver will take care
of mailbox send recv ops and it replaces previous "zynqmp_ipi" driver.
Now "zynqmp_ipi" driver simply binds each child device with "zynqmp_ipi_dest"
driver.
However, its important to maintain backward comaptibility with previous
bindings where child node does not have compatible string. In such case, new
driver isn't probed by U-Boot during boot and system fails to boot. To
resolve this issue firmware-zynqmp.c driver probes all the IPI parent node
driver which binds each child node device with "zynqmp_ipi_dest" driver.
This makes sure corresponding child driver will be
probed when requested using mbox_get_by_name or mbox_get_by_idx
framework calls.
This way multiple mailbox agents are supported in device-tree without breaking
previous binding support.
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Link: https://lore.kernel.org/r/20231204215620.63334-4-tanmay.shah@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
In case of A/B update systems there should be an option to load the same
binary/binaries to different location and they should work.
Before this patch boot.bin with U-Boot SPL can be added to whatever 32k
offset in SPI and SPL finds u-boot.itb at CONFIG_SYS_SPI_U_BOOT_OFFS
offset. In case of A/B update systems that means that SPL is at different
locations but it still points to the same u-boot.itb which is not correct.
That's why include multiboot value to offset calculation to be able to
point to image from the same base.
It doesn't affect any current system which starts from 0 offset.
This patch also change Kria defconfig which uses A/B setup. Partition
A starts at multiboot 64, partition B at multiboot 496.
And also print message about used SPI offset which is useful for all cases.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/93903a53ad9358ae69991558b787f574797effbe.1699619666.git.michal.simek@amd.com
- Fix emmc detection on colibri_imx7
- Fix DDR configuration on tqma6 to improve Ethernet performance
- Fix aliases and chosen nodes indentation on imx7s-warp
- Convert pico-imx6ul to DM_SERIAL
- Convert pico-pi-imx7d to watchdog driver model to fix 'reset' command
- Select CONFIG_NET_RANDOM_ETHADDR on imx8mp_evk to fix networking on
older boards
- Add USBH_EN gpio hog to fix USB host interface not working on some
Apalis Toradex carrier boards with Apalis iMX8 SoM
- Add PCI fixup for GW73xx-F+
- Fix broken EEPROM read on imx8mn-var-som
Later versions of Colibri iMX7D V1.1B modules use a "new" SoC fusing. The
difference lies in whether we enable the boot ROM to use the eMMC reset
signal. Depending on the SoC fuse, the boot ROM configures this pin as a
GPIO output to drive the reset signal. Our eMMC vs NAND detection
currently only sets that signal to a GPIO without explicitly setting any
direction. Previously, by default, it was set as an input. As the boot ROM
now configures it as an output, we receive a value of zero instead of one,
indicating the absence of the pull-up on eMMC modules.
To fix this, set the SION bit, allowing the reading back of the value
even if it is configured as an output by the boot ROM. It's important to
note that with the new SoC fusing, we now read back what the boot ROM
drives rather than the real value caused by the pull-up resistor. However,
if it were ever driven low, the eMMC would permanently be reset.
In addition, remove hard-coded variant in the eMMC build case as since the
commit 0c39564d02 ("toradex: colibri_imx7: Enable nand/emmc detection
and set boot variant") will anyways always get overridden by the detection
routing in board code.
Fixes: 0c39564d ("toradex: colibri_imx7: Enable nand/emmc detection and set boot variant")
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Hiago De Franco <hiago.franco@toradex.com>
Initially investigating a Linux network issue causing a lot of drop and
poor network performances on a custom system based on a TQMA6A module
(based on an iMX6Q), [1st link below].
I eventually correlated my observations with a contention at the NIC
level when in concurrency with the graphics pipeline. Troubleshooting
this in the kernel lead to disabling DMA bursts accesses made by the IPU
in order to avoid triggering the QoS at the interconnect level, reducing
from 50 to 10% the drop rate on eth0, [2nd link below]. The solution
worked on my setup but not on others, which still suffered from
abnormally high drop rates even with this "fix".
After looking a while into TQ Systems BSP I figured out a number of
differences in recent U-Boot out-of-tree patches they had in their
repository [3rd link]. Parsing the differences one after the other lead
me to this final solution.
The reset pad of the DDR controller was apparently misconfigured, Bit
18-19 picturing the "DDR select field". The current value b11 is
reserved. The only defined value as of version 6 of the iMX6Q manual was
b00 "DDR3 and LPDDR2 mode". In practice no register difference has been
spotted after changing this configuration but all issues tracked thus
far just vanished. All previous fixes have been proven irrelevant. Just
clearing this field solved all our network issues and the drop rate as
measured by iperf3 felt back to 0%.
Link: https://lore.kernel.org/netdev/20231012193410.3d1812cf@xps-13/
Link: https://lists.freedesktop.org/archives/dri-devel/2023-October/428251.html
Link: 15eb6abbef
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
The aliases and chosen nodes are currently indented using spaces.
Fix them to use the standard tab indentation.
Signed-off-by: Fabio Estevam <festevam@denx.de>
