Commit Graph

102426 Commits

Author SHA1 Message Date
Marek Vasut
bc8d7288e3 net: designware: Reorder bb_miiphy functions
Move the bb_miiphy functions before MDIO registration. This is a
preparatory patch, the functions will be referenced around the MDIO
registration in the follow up patches. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2025-02-26 18:26:57 +01:00
Marek Vasut
90ef2549b7 arm: mvebu: a38x: Reorder bb_miiphy functions
Move the bb_miiphy functions before MDIO registration. This is a
preparatory patch, the functions will be referenced around the MDIO
registration in the follow up patches. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2025-02-26 18:26:57 +01:00
Marek Vasut
d8a1768eea net: sh_eth: Reorder bb_miiphy functions
Move the bb_miiphy functions before MDIO registration. This is a
preparatory patch, the functions will be referenced around the MDIO
registration in the follow up patches. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2025-02-26 18:26:57 +01:00
Marek Vasut
83064d5e3b net: ravb: Reorder bb_miiphy functions
Move the bb_miiphy functions before MDIO registration. This is a
preparatory patch, the functions will be referenced around the MDIO
registration in the follow up patches. No functional change.

Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-02-26 18:26:57 +01:00
Marek Vasut
165fba6c91 net: designware: Drop NULL priv assignment
This is unnecessary, the unset structure member is initialized to
NULL by default, drop the assignment.

Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-02-26 18:26:57 +01:00
Marek Vasut
4e984c1160 net: sh_eth: Drop empty init callback
The init function does nothing, the bb_miiphy_init() already checks
whether the .init callback is assigned, and if not, skips calling it.
Remove the empty init function. The entire init callback will be
removed in follow up patches.

Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-02-26 18:26:57 +01:00
Marek Vasut
c835f5c846 net: ravb: Drop empty init callback
The init function does nothing, the bb_miiphy_init() already checks
whether the .init callback is assigned, and if not, skips calling it.
Remove the empty init function. The entire init callback will be
removed in follow up patches.

Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-02-26 18:26:57 +01:00
Tom Rini
57bbc4de75 Merge tag 'qcom-fixes-2025.04-rc4' of https://source.denx.de/u-boot/custodians/u-boot-snapdragon
CI: https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/pipelines/24841

The clk_stub, regulator, and pinctrl fixes enable the sdcard on the RB5
dev board (and sm8250 devices broadly). clk_stub is only enabled in
qcom_defconfig and the others are qcom specific so these shouldn't
affect other platforms.

Lastly, a small ufetch fix from Sam which gets color rendering correctly
on U-Boots framebuffer video device.
2025-02-26 08:55:32 -06:00
Sam Day
6267ce5565 cmd: ufetch: use 3-bit colour ANSI codes
Currently, the 8-bit escapes are being used, which aren't supported by
vidconsole_escape_char. Since the current usage maps directly to the
3-bit equivalents anyway, let's use those instead.

With this change, the fetch output looks as fetching in the vidconsole
as it does over serial!

Signed-off-by: Sam Day <me@samcday.com>
Tested-by: Alexey Minnekhanov <alexeymin@postmarketos.org>
Tested-by: Ferass El Hafidi <funderscore@postmarketos.org>
2025-02-26 13:48:27 +00:00
Caleb Connolly
554562f7b5 pinctrl: qcom: sm8250: fix pin count
The pin count wasn't updated when the special pins were added, as a
result it was never possible to configure the special pins on SM8250
boards.

Fix the pin count and allow the special pins to be configured. This
fixes sdcard support on the RB5.

Fixes: 58fa520424 ("pinctr: qcom: sm8250: add special pins pins configuration data")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Amit Pundir <amit.pundir@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2025-02-26 13:48:27 +00:00
Caleb Connolly
e57b72abb7 power: regulator: add additional supported LDOs for pm8150l
Add the other LDOs that our rpmh driver can currently support. Some of
these are used on the RB5 to power the sdcard.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Amit Pundir <amit.pundir@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2025-02-26 13:48:27 +00:00
Julius Lehmann
506f6a384c clk: stub: add sm8150 compatible id
Add support for sm8150 clock controller to clk stub driver.

Signed-off-by: Julius Lehmann <lehmanju@devpi.de>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-02-26 13:16:40 +00:00
Caleb Connolly
b72d6a9d61 qcom_defconfig: enable stub clock
Enable the stub clock driver for rpmcc

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2025-02-26 13:16:40 +00:00
Caleb Connolly
d31a3bd08e clk: add stub clock driver
Add a stub clock driver which can be used to bind clock controllers
which aren't required for the platform to boot, but which are needed for
U-Boot drivers to work.

In addition, add a NOP parent driver to allow for binding the parent
nodes of the clock.

Initially this driver supports a Qualcomm platform where the MMC driver
tries to fetch the RPM clock controller, which is not actually required
for the device to work.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2025-02-26 13:16:40 +00:00
Svyatoslav Ryhel
892e97c0e1 ARM: tegra124: implement BCT patching
This function allows updating bootloader from u-boot
on production devices without need in host PC.

Be aware! It works only with re-crypt BCT and AES
encrypted devices.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-02-26 13:08:20 +02:00
Svyatoslav Ryhel
0298591857 video: panel: add Sharp LQ079L1SX01 MIPI DSI panel driver
This module is a color active matrix LCD module incorporating
Oxide TFT (Thin Film Transistor). It is composed of a color TFT-LCD
panel, driver ICs, a control circuit and power supply circuit, and
a backlight unit. Graphics and texts can be displayed on a 1536x2048
dots panel with (16,777,216) colors by using MIPI DUAL DSI interface,
supplying +3.3V DC supply voltage for TFT-LCD panel driving and
supplying DC supply voltage for LED Backlight.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-02-26 13:08:20 +02:00
Svyatoslav Ryhel
e503be022f video: add TI LP855x backlight driver
Add support for National Semiconductor/TI LP8550/1/2/3/5/6/7
LED Backlight. Driver is based on Linux version but is
reworked and optimised for U-Boot DM framework. Currently
only register driven backlight control is supported, PWM
driver backlight control may be added later if needed.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-02-26 13:08:20 +02:00
Svyatoslav Ryhel
f84ac08147 video: tegra20: mipi: add Tegra K1 support
Re-design MIPI calibration driver to fit T124.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-02-26 13:08:20 +02:00
Svyatoslav Ryhel
cd37937fc3 video: tegra20: dc: dsi: add Tegra K1 compatible
Tegra K1 is fully compatible with existing DC and DSI implementation
using Tegra 4 data.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-02-26 13:08:19 +02:00
Svyatoslav Ryhel
a237a20993 pinctrl: tegra: add Tegra K1 support
Tegra 124 is fully compatible with existing Tegra pincontrol
driver, but it needs a specific MIPI PAD control pinconfig.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-02-26 13:08:19 +02:00
Svyatoslav Ryhel
a6855d57ea ARM: tegra: endeavoru: adjust panel node
Bind panel in Linux-style, as DSI child.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-02-26 13:07:17 +02:00
Svyatoslav Ryhel
5325221186 video: tegra20: dsi: pass source on DSI configuration
Parametrize DSI configuration by passing DC source pipe. This
should resolve possible failure if second DC is used with DSI
for some reason.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-02-26 13:07:17 +02:00
Svyatoslav Ryhel
69d3ad1880 video: tegra20: dsi: calculate lanes for ganged mode
Use Linux DSI driver approach to calculate lanes for ganged mode.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-02-26 13:06:47 +02:00
Svyatoslav Ryhel
7d2004983e video: tegra20: dsi: calculate packet parameters for video mode
Calculate packet parameters for video mode same way it is done or
command mode, by halving timings plugged into equations.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-02-26 13:06:40 +02:00
Svyatoslav Ryhel
aa9fa8c1ad video: tegra20: dsi: make SOL delay calculation mode independent
Move SOL delay calculation outside of video mode conditions.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-02-26 13:06:02 +02:00
Svyatoslav Ryhel
785787b7f0 video: tegra20: dsi: align ganged mode implementation
Align U-Boot DSI ganged mode implementation with the Linux kernel's
implementation.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-02-26 13:06:02 +02:00
Svyatoslav Ryhel
239b7f1299 video: tegra20: dsi: switch to newer clk API
Switch to struct clk instead of working with plain clock id.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-02-26 13:06:02 +02:00
Svyatoslav Ryhel
eef35b8755 video: tegra20: dsi: check for panels among child nodes
Switch to Linux-like approach of DSI panel binding as a DSI
controllers child node.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-02-26 13:06:02 +02:00
Svyatoslav Ryhel
530ac53175 video: tegra20: dc: improve code quality
Mainly unification and improving of readability.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-02-26 13:06:02 +02:00
Svyatoslav Ryhel
8f1e56c9dd video: tegra20: dc: remove excessive headers
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-02-26 13:06:02 +02:00
Svyatoslav Ryhel
026a1ab2fa video: tegra20: dc: remove hardcoded Tegra 2 specific parts
Since pinmux driver now is available for Tegra 2, these parts may
be removed from here and defined either in device tree or in
the device board files.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-02-26 13:06:02 +02:00
Svyatoslav Ryhel
5643a85205 video: tegra20: dc: switch to newer clk API
Switch to struct clk instead of working with plain clock id.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-02-26 13:06:02 +02:00
Tom Rini
8dd7186ca7 Merge patch series "Remove "saveenv" functionality from am57xx evms"
Anurag Dutta <a-dutta@ti.com> says:

Previously saved environment introduce discrepancies and may lead to
incompatibilities without default settings. This series removes the saved
environment functionality on am57xx evms so that the default configuration
is always loaded

Test result: https://gist.github.com/anuragdutta731/b253ddb0a5538ab6588a3535d7bbecf7

Link: https://lore.kernel.org/r/20250208043938.52832-1-a-dutta@ti.com
2025-02-25 11:11:32 -06:00
Anurag Dutta
ff3db2ef29 configs: am57xx: Remove saved environments
Saved environments lead to inconsistencies leading to conflicts
with the default environment that U-boot should update during
development. Remove the previously saved environment so that
the default environment is always loaded.

Signed-off-by: Anurag Dutta <a-dutta@ti.com>
2025-02-25 11:11:29 -06:00
Anurag Dutta
940bf62a93 configs: am57xx_hs: Remove saved environments
Saved environments cause inconsistencies leading to conflicts
with the default environment that U-boot should update during
development. Remove the previously saved environment so that
the default environment is always loaded.

Signed-off-by: Anurag Dutta <a-dutta@ti.com>
2025-02-25 11:11:29 -06:00
Tom Rini
4da90796ca Merge tag 'u-boot-socfpga-next-20250225' of https://source.denx.de/u-boot/custodians/u-boot-socfpga into next
CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/24816

Please pull the SoCFPGA changes for next from u-boot-socfpga, containing
boot support for the  Altera SoCFPGA Agilex 5 platform in U-Boot. The
changes include:

1. Board-specific configurations and setup required to enable Agilex 5
   operation in U-Boot.
2. Integration of cache coherency unit (CCU) initialization routine,
   including CCU conguration in DT.
3. Clock, firewall (configured in DT), SMMU, low level initialization
   specific to Agilex 5.
4. Integration of memory initialization routine, including DDR setup.

This patch set has been tested on Agilex 5 devkit with QSPI boot
(UBI/UBIFS) and RAM boot (TFTP & ARM DS debugger).
2025-02-25 10:54:05 -06:00
Alif Zakuan Yuslaimi
7965e52e32 configs: agilex5: Enable watchdog autostart
Automatically start watchdog timer for Agilex5. This
configuration is enabled by default in the Kconfig,
hence removing this configuration from Agilex5 defconfig.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-02-25 10:54:05 -06:00
Alif Zakuan Yuslaimi
9f12a3265c configs: socfpga: soc64: agilex5: Enable QSPI boot with UBI / UBIFS
Add the required configuration in the U-Boot env to enable Linux QSPI
boot with UBI / UBIFS.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-02-25 10:54:04 -06:00
Tien Fong Chee
d1be524aac arm: socfpga: soc64: Add support for board_boot_order()
Add board_boot_order() to retrieve the list of boot devices from
spl-boot-order property in device tree. This board_boot_order()
would be used for all Intel SOC64 devices.

Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-02-25 10:54:04 -06:00
Tien Fong Chee
48e687cfea configs: socfpga: soc64: agilex5: Enable XGMAC
Enable XGMAC for SoCFPGA Agilex5 devkit.

Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-02-25 10:54:03 -06:00
Alif Zakuan Yuslaimi
e0d10e5105 configs: socfpga: soc64: agilex5: Use common ARMv8 linker script
Use default common ARMv8 linker script instead of a separate
SoC64 linker script

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
2025-02-25 10:54:02 -06:00
Alif Zakuan Yuslaimi
1c37e59bfb arm: armv8: Improve SPL data save and restore implementation
Introduce a new symbol in the beginning of .data section in
the common ARMv8 linker script and use that as a reference
for data save and restore.

Previously, the code would rely on calculating the start of
the .data section address via data size, however, we observed
that the data size does not really reflect the SPL mapped
addresses.

In our case, the binman_sym section size was not included in
the data size, which will result in a wrong address for the
.data start section, which prevents us from properly saving
and restoring SPL data.

This approach skips the calculation for the starting address
of the .data section, and instead just defines the beginning
address of the .data section and calling the symbol as needed,
in which we think as a simpler and much more robust method.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-02-25 10:54:02 -06:00
Tien Fong Chee
b005eca0c9 arm: socfpga: agilex5: Add SPL for Agilex5 SoCFPGA
Add SPL support for Agilex5 SoCFPGA.

Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-02-25 10:54:01 -06:00
Tingting Meng
04ea9147d5 ddr: altera: Add DDR driver for Agilex5 series
Adding DDR driver support for Agilex5 series.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
2025-02-25 10:54:01 -06:00
Alif Zakuan Yuslaimi
034ebe3302 arm: socfpga: smc: Add memory coherency support to mailbox command
As cache is enabled in U-Boot and disabled in ATF(BL31). We need to
perform cache flush of buffers that are shared between U-Boot and
ATF using secure monitor calls.

Signed-off-by: Mahesh Rao <mahesh.rao@altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-02-25 10:54:00 -06:00
Tien Fong Chee
19f20cfc49 configs: agilex5: Add configuration for malloc pool
Adding configuration for SPL malloc pool.

Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-02-25 10:54:00 -06:00
Alif Zakuan Yuslaimi
8c172a423c arm: socfpga: Export board ID as U-Boot environment
Board ID is exported as environment variable for use to boot Linux with FIT
configuration.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-02-25 10:53:59 -06:00
Alif Zakuan Yuslaimi
6ec6b75e9a arm: socfpga: agilex5: Update CPU info
Update the print info per Agilex5

Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-02-25 10:53:58 -06:00
Tien Fong Chee
0d2010faac arm: socfpga: agilex5: Add SMMU initialization
Allow non-secure accesses only with SMMU peripherals. This would protect
the content in DDR secure region from accidentally modified by SMMU
peripherals.

Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-02-25 10:53:57 -06:00
Tien Fong Chee
9bb68bff4e arm: socfpga: agilex5: Enable cache flush for system memory cache in CCU
set/way instructions "dc cisw" which is used by the "dcache flush" command
only flushing CPU data caches from L1 -> L2 -> L3 to system memory cache in
cache coherency unit, hence this patch enables data flush from system
memory cache of CCU into DDR memory.

Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-02-25 10:53:56 -06:00