Allow boards that use ti_spl_template to not use optee part in
configuration.
Vendor can have module with 256 Mb of memory and they try to optimize
the available memory just using the essential components.
This change allow to remove tee from configuration without binman
fail.
configurations {
default = "conf-0";
conf-0 {
description = "k3-am62_ccm_m3";
firmware = "atf";
loadables = "dm", "spl";
fdt = "fdt-0";
};
};
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
The phy calibration pattern partition isn't needed as the Cadence driver isn't
calibrating the phys.
Signed-off-by: Jonathan Humphreys <j-humphreys@ti.com>
Fixes: 58d61fb5a7 ("arm: dts: k3-j721e-sk: Add initial A72 specific dts support")
Add boot ROM XSPI bootmode, and set to BOOT_DEVICE_SPI if detected.
Signed-off-by: Jonathan Humphreys <j-humphreys@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Add bootph DT tags to enable OSPI in SPL.
Set OSPI regs for R5 SPL to address OSPI's boot region.
Signed-off-by: Jonathan Humphreys <j-humphreys@ti.com>
Clock names has been updated in kernel 5.19+ with the removal of
non-standard node names [1]. Due to this change, ft_opp_clock_fixups()
doesn't work anymore since ft_fixup_clocks() is looking to the clock
name and ft_opp_clock_fixups() error out with the following message:
ft_fixup_clocks failed for DSP voltage domain: <valid offset/length>
We can't use the new clock name since several clock are using the same
generic name "clock". ft_opp_clock_fixups() is looking at the clocks
node in cm_core_aon@0:
/sys/firmware/devicetree/base/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks
...
clock@120
clock@160
clock@1a0
clock@1e0
clock@210
clock@234
clock@284
clock@2a8
clock@2d8
When fdt_subnode_offset() fail, we can look at clock-output-names
property as fallback since it contain the previous clock name.
libfdt doesn't provide any support to replace fdt_subnode_offset() by
a new function looking for clock-output-names property instead of the
node name. So we have to implement it in arch/arm/mach-omap2/omap5/fdt.c
for now.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=e4920169e7a2a839836d3a0d8cda1bae8caa3056
Cc: Suman Anna <s-anna@ti.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Andrew Davis <afd@ti.com>
Signed-off-by: Romain Naour <romain.naour@skf.com>
The functions virtio_pci_get_config() and virtio_pci_set_config() don't
take the offset into account when reading the config space. For example
this manifests when U-Boot tries to read the MAC address of the VirtIO
networking device. It reads 6 equa bytes instead of the proper addess.
Fix those functions by taking the offset in the config space into
account.
Fixes: 4135e10732 ("virtio: Add virtio over pci transport driver")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Michał Barnaś <barnas@google.com> says:
Fix the driver to behave like the chip datasheet requires.
Improve wake up function to send low signal on SDA line for at least
60us as chip requires to wake up. Fix sleep function to move the chip
into sleep mode, not into idle mode. Remove unnecessary for loop,
which would never run for more than one iteration.
The ATSHA204A chip requires SDA line to go low for at least 60us to
wake up the chip. Previous implementation did not meet this requirement
due to the NAK received on bus and not sending the zeroes.
The function to ignore the NAK and send bytes regardless is not
supported in the u-boot making it impossible to wake up the chip
this way.
Instead, the bus speed, if needed, is set to lowest value and the
message is sent to the address 0x0. This way, the address of zero
makes the SDA line go low for about 80us, meeting the required time
to wake up the chip. The zero length packet is not sent by the i2c,
so the one byte is sent to the transfer function, but only the address
is sent anyway.
After sending the zero address, the bus speed is restored to the
previous value if it was slowed down to wake up the chip.
Signed-off-by: Michał Barnaś <barnas@google.com>
Some previous commit changed the continue statement to return,
making the for loop used to retry waking up the chip to always
return after one iteration. This commit removes the loop, cleaning
the code a little.
Signed-off-by: Michał Barnaś <barnas@google.com>
Apurva Nandan <a-nandan@ti.com> says:
Hello Everyone!
This series will introduce basic support (SD and UART) support for Texas
Instruments J784S4 EVM.
The J784S4 SoC device tree patches are taken from kernel patch submissions
and will be updated as they are accepted and merged to the kernel tree.
All other patches are specific to SPL and u-boot and do not have
dependency on other trees. Appreciate a review for acceptance to u-boot
tree.
Here are some of the salient features of the J784S4 automotive grade
application processor:
The J784S4 SoC belongs to the K3 Multicore SoC architecture
platform, providing advanced system integration in automotive,
ADAS and industrial applications requiring AI at the network edge.
This SoC extends the K3 Jacinto 7 family of SoCs with focus on
raising performance and integration while providing interfaces,
memory architecture and compute performance for multi-sensor, high
concurrency applications.
Some highlights of this SoC are:
* Up to 8 Cortex-A72s, four clusters of lockstep capable dual Cortex-R5F MCUs,
4 C7x floating point vector DSPs with Matrix Multiply Accelerator(MMA) for
deep learning and CNN.
* 3D GPU: Automotive grade IMG BXS-4-64 MC1
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Three CSI2.0 4L RX plus two CSI2.0 4L TX, two DSI Tx, one eDP/DP and one
DPI interface.
* Integrated gigabit ethernet switch, up to 8 ports (TDA4VH), two ports
support 10Gb USXGMII; Two 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role
device subsystems, Up to 20 MCANs, among other peripherals.
See J784S4 Technical Reference Manual (SPRUJ52 - JUNE 2022)
for further details: http://www.ti.com/lit/zip/spruj52
In addtion, the J784S4 EVM board is designed for TI J784S4 SoC. It
supports the following interfaces:
* 32 GB DDR4 RAM
* x2 Gigabit Ethernet interfaces capable of working in Switch and MAC mode
* x1 Input Audio Jack, x1 Output Audio Jack
* x1 USB2.0 Hub with two Type A host and x1 USB 3.1 Type-C Port
* x2 4L PCIe connector
* x1 UHS-1 capable micro-SD card slot
* 512 Mbit OSPI flash, 1 Gbit Octal NAND flash, 512 Mbit QSPI flash,
UFS flash.
* x6 UART through UART-USB bridge
* XDS110 for onboard JTAG debug using USB
* Temperature sensors, user push buttons and LEDs
* 40-pin User Expansion Connector
* x2 ENET Expansion Connector, x1 GESI expander, x2 Display connector
* x1 15-pin CSI header
* x6 MCAN instances
Schematics: https://www.ti.com/lit/zip/sprr458
AM69 SD mode bootlog: https://gist.githubusercontent.com/apurvanandan1997/1b2c55d0204ff0f5a47ebbc196a97e99/raw/
J784S4 SD mode bootlog: https://gist.githubusercontent.com/apurvanandan1997/5e2ef85ee4322798d22b57a60dc917db/raw/
eMMC UDA moode bootlog: https://gist.githubusercontent.com/apurvanandan1997/3cffada252d50a8aa0c00a91f1f2f856/raw/
ring_idx was not correctly assigned in case of tflow_id is zero.
Which leads to wrong pairing of DMA for drivers like OSPI.
Fixes: 4312a1dfca ("dma: ti: k3-udma: Use ring_idx to pair k3 nav rings")
Reviewed-by: Jai Luthra <j-luthra@ti.com>
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
TI K3 J784S4 and AM69 are new additions to the K3 SoC family.
Add documentation about the J784S4 EVM and AM69 SK.
Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
With the latest TIFS firmware, an additional virtual interrupt and
event is reserved for TIFS usage on am62x and am62ax devices.
Update the rm-cfg to reflect this new reservation.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
In udma_probe() the return value of setup_resources() is stored in the
u32 "ch_count" member of "struct udma_dev", due to which any negative
return value which indicates an error is masked.
Fix this by storing the return value of setup_resources() in the already
declared integer variable "ret", followed by assigning it to the "ch_count"
member of "struct udma_dev" in case of no error.
While at it, change the "return ret" at the end of udma_probe() to a
"return 0", to explicitly indicate that probe was successful.
Fixes: a8837cf438 ("dma: ti: k3-udma: Query DMA channels allocated from Resource Manager")
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Dan Carpenter <dan.carpenter@linaro.org>
With the default size the stack grows into the malloc, pool leading to
stack corruption and boot failure.
Signed-off-by: Thomas Weißschuh <thomas.weissschuh@linutronix.de>
Read the max temperature for the SoC temperature grade from the hardware
and change the critical trip nodes on each thermal zone of FDT at
runtime so they are correct with the hardware value for its grade.
Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
AM62x SoC is available in multiple temperature grade:
- Commercial: 0° to 95° C
- Industrial: -40° to 105° C
- Automotive: -40° to 125° C
Add a new function that returns the am62 max temperature value
accordingly to its temperature grade in Celsius.
Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Like we did with R5, move ARM64 code into a specific directory to make
it clear what code is only meant to run on each core type.
Signed-off-by: Andrew Davis <afd@ti.com>
The disable_linefill_optimization() function is only ever loaded by the
R5 core, move the code into the R5 directory.
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Loading ATF is only supported from the R5, move the Kconfig symbol
definition to match.
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Introduce the base dts files needed for u-boot or to augment the linux
dtbs for use in the u-boot-spl and u-boot binaries.
Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
Introduce the base dts files needed for u-boot or to augment the linux
dtbs for use in the u-boot-spl and u-boot binaries.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
[ add binman and ddr dtsi files ]
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
Add board files for J784S4 EVM.
SYS_DISABLE_DCACHE_OPS is selected in the Kconfig because
J784S4/AM69 are a coherent architecture at A72 level by
MSMC support.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
Add J784S4 initialization files for initial SPL boot.
config SYS_K3_MCU_SCRATCHPAD_BASE default value is same
for J721E, J721S2, J784S4. So combined them into a single
default.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
[ add firewall configurations and change the R5 MCU scratchpad ]
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
Nishanth Menon <nm@ti.com> says:
Hi,
Rev 2 of the series.
This is a follow up from [1] - Without the 32k crystal configuration,
wlan doesn't work. Debounce is needed for HDMI Hot plug detect(hpd)
gpio interrupt not storming.
At least the 32k configuration has been done for toradex and phytec
boards, follow similar model of programming.
Series is now based off master branch.
Bootlog: https://gist.github.com/nmenon/75df38bee907785d1d78d1ec4abd7304
Changes from V2:
- Removed depedency on [2] - depending on which way
the merge sequence goes, one of the series will need a rebase.
- Added a patch for a bug that Jan noticed
- Fixup for the fat finger missing 0x in 0x4080 :(
[1] https://lore.kernel.org/u-boot/20230725185253.2123433-4-nm@ti.com/
[2] https://lore.kernel.org/u-boot/20240212194726.1093771-1-nm@ti.com/
We had enabled USB and network pxe boot with the hope to get it all
merged on time. However, it has not panned out. Drop usb and pxe boot
else bootflow scan -l throws in:
a) Unknown uclass 'usb' in label
b) Crashes when attempting pxe - cpsw/mdio driver apparently has missing
error handling of what ever form. This is the one that Jan noticed in
his log.
We can enable these on a later date once things are working.
Cc: Roger Quadros <rogerq@kernel.org>
Reported-by: Jan Kiszka <jan.kiszka@siemens.com>
Closes: https://lore.kernel.org/all/782ea2c0-eef5-478d-a122-cc6e2d066762@siemens.com/
Signed-off-by: Nishanth Menon <nm@ti.com>
Add the Debounce configuration registers that need to be configured one
time for the platform for the entire SoC.
Signed-off-by: Nishanth Menon <nm@ti.com>
Enable the external 32k crystal similar to that found on other
production AM62X board. The trim settings for the crystal is board
dependent, so the sequences tend to be board specific. Since this is
a configuration that needs to be done prior to DM managing the system
and all other muxes get set, do the same from R5 context.
Tested-by: Robert Nelson <robertcnelson@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
- Assorted MediaTek, ASPEED, xenguest, s5p4418 and qemu-arm fixes
- Assorted test fixes/updates/additions.
- A few bootstd/related fixes.
- Remove common.h from some files
- Drop reiserfs
- A few other assorted fixes throughout the tree.
Add myself as maintainer for SynQuacer Developerbox,
as I'm currently working on it.
This commit also removes Jassi from maintainer since he
no longer has a Developerbox.
Cc: Jassi Brar <jassisinghbrar@gmail.com>
Signed-off-by: Masahisa Kojima <kojima.masahisa@socionext.com>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
