The Chameleon board is an OpenHardware devboard made by YuzukiTsuru.
The form factor resembles the Raspberry Pi Model A boards, though it
differs significantly in its features:
- Allwinner H618 SoC (4 * Arm Cortex-A53 cores, 1MB L2 cache, 1.4 GHz)
- between 512MiB and 2GiB DDR3 DRAM
- up to 128 GiB eMMC flash
- AXP313a PMIC
- 100 Mbit/s Ethernet pins on a header
- XR829 WIFI+Bluetooth chip
- 4 * USB 2.0 USB-C ports
- microSD card slot
- 3.5mm A/V port
Add the devicetree describing the board's peripherals and their
connections.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://patch.msgid.link/20250307005712.16828-16-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
[ upstream commit: f4a6b0f7200f8629f4138f1094ce654ab75df41e ]
(cherry picked from commit 3a879d878553d57057ce0a7096bfbf1eb077f6dc)
The H-A133L board is an industrial development board made by Liontron.
It contains a number of dedicated JST connectors, to connect external
peripherals. It features:
- Allwinner A133 SoC (4 * Arm Cortex-A53 cores at up to 1.6 GHz)
- 1 GiB, 2 GiB or 4 GiB of LPDDR4 DRAM
- between 16 and 128 GiB eMMC flash
- AXP707 PMIC (compatible to AXP803)
- 100 Mbit/s RJ45 Ethernet socket, using an JLSemi JL1101 PHY
- XR829 WIFI+Bluetooth chip
- 2 * USB 2.0 USB-A ports, plus three sets of USB pins on connectors
(connected via a USB hub connected to USB1 on the SoC)
- microSD card slot
- 3.5mm A/V port
- 12V power supply
- connectors for an LVDS or MIPI-DSI panel
Add the devicetree describing the board's peripherals and their
connections.
Despite being a devboard, the manufacturer does not publish a schematic
(I asked), so the PMIC rail assignments were bases on BSP dumps,
educated guesses and some experimentation. Dropping the always-on
property from any of the rails carrying it will make the board hang as
soon as the kernel turns off unused regulators.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Link: https://patch.msgid.link/20250505164729.18175-4-andre.przywara@arm.com
[wens@csie.org: fix property in &usbphy; fix comment typo in &usb_otg]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
[ upstream commit: a3cd12acb7b74d9b243cd893209972fc657d0bd3 ]
(cherry picked from commit 4062957c0797752dcf8b71f99c7aa47301c70aac)
The manual for the Allwinner A133 SoC mentions that the maximum
supported MMC frequency is 150 MHz, for all of the MMC devices.
Describe that in the DT entry, to help drivers setting the right
interface frequency.
Fixes: fcfbb8d9ec58 ("arm64: allwinner: a100: Add MMC related nodes")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Link: https://patch.msgid.link/20250505202416.23753-1-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
[ upstream commit: d8f10550448b03d3c5c6d9392119205c65ebfc89 ]
(cherry picked from commit 85e37e6a8a002eb231df8209478d7ff2b134a451)
This will allow arch(s) that use device tree blobs to pad the end of the
device tree so they can be modified by board files at run time. This will
help prevent errors such as FDT_ERR_NOSPACE from occurring.
Signed-off-by: Eric Schikschneit <eric.schikschneit@novatechautomation.com>
[trini: Change default order so that X86 && EFI_APP works correctly]
i.MX91 device tree still not landed in linux kernel, so drop OF_UPSTREAM
and move the device tree files to arch/arm/dts
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Add Retronix R-Car V4H Sparrow Hawk board based on Renesas R-Car V4H ES3.0
(R8A779G3) SoC. This is a single-board computer with single gigabit ethernet,
DSI-to-eDP bridge, DSI and two CSI2 interfaces, audio codec, two CANFD ports,
micro SD card slot, USB PD supply, USB 3.0 ports, M.2 Key-M slot for NVMe SSD,
debug UART and JTAG.
DT is imported from Linux next commit:
a719915e76f2 ("arm64: dts: renesas: r8a779g3: Add Retronix R-Car V4H Sparrow Hawk board support")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
As the name implies, it is built around the RK3576 SoC with 4x Cortex-A72
cores, four Cortex-A53 cores and Mali-G52 MC3 GPU.
Storage options are EMMC, SD-Card, a 2242 M.2 slot and the possibility to
use UFS 2.0 storage.
Video Output options are a HDMI port, a DSI connector as well as Display-
Port via the TypeC connector (all of them not yet supported).
Networking options are a Low-profile Gigabit Ethernet RJ45 port with
Motorcomm YT8531 PHY as well as WiFi via an AMPAK AP6256 module.
USB ports on the board are 1x USB 3.0 port, 1x USB 2.0 port, 1x USB Type-C
and it comes with 40-pin GPIO header
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250210205126.1173631-3-heiko@sntech.de
[ upstream commit: 887ff17cdd8f088a52e2b61e71f2b6c9b9678de6 ]
(cherry picked from commit 388e7272d092bd20e414cd408bac39d8fd02d765)
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Radxa E20C has two buttons, one SARADC maskrom button and one GPIO user
button.
Add support for the maskrom button using a adc-keys node, also add the
regulators used by SARADC controller.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250304201642.831218-5-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: 3a2819ee9c71d1c6388e456cc4eb042914d15d7e ]
(cherry picked from commit 460ef5b623e5fa69843305faf50f6b1a8e81e1cd)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Radxa E20C has three gpio controlled leds (sys, wan and lan).
Add led nodes and set default trigger to heartbeat for the sys led and
netdev for the lan and wan leds.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250304201642.831218-2-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: 6a709e003492e9878d5f1357be0b2e1162e1e6a6 ]
(cherry picked from commit a3556ede6b48c7760ac3608ad77601fca26d2ce0)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Radxa E20C route UART0 M0 pins (GPIO4_C7 and GPIO4_D0) to the onboard
CH340B for debug console use.
Add pinctrl for UART0 M0 pins used for serial console.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250228064024.3200000-6-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: 0d2312f0d3e4ce74af0977c1519a07dfc71a82ac ]
(cherry picked from commit 9bcf6ccdd87c3be48fe7d75150c6e403c5c0a42d)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The Quality-of-Service (QsS) node stores/restores specific
register contents when the power domains is turned off/on.
Add QoS node so that they can connect to the power domain.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://lore.kernel.org/r/20250306123809.273655-3-amadeus@jmu.edu.cn
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: 61a05d8ca3030a544175671f5fab7a8f29c24085 ]
(cherry picked from commit 9ee90dfd6957fcc42ea94c43d195b01d1b286713)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add pinctrl and gpio nodes for RK3528 and import rk3528-pinctrl.dtsi
from vendor linux-6.1-stan-rkr5 kernel with the hdmi-pins-idle node
removed due to missing label reference to pcfg_output_low_pull_down.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250228064024.3200000-5-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: a31fad19ae39ea27b5068e3b02bcbf30a905339b ]
(cherry picked from commit 89a24fa2e923b68a42ccc8cc9cb2d5bdf291ac40)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add dt node for RK3528 clock and reset unit. Clock "gmac0_clk" is
generated by internal Ethernet phy, a fixed clock node is added as a
placeholder to avoid orphans.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Link: https://lore.kernel.org/r/20250217061142.38480-9-ziyao@disroot.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: 858cdcdd11cf9913756297d3869e4de0f01329ea ]
(cherry picked from commit 60741472b42e92d2393327cb70669ab90e3b382f)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
There are two types of clocks in RK3528 SoC, CRU-managed and
SCMI-managed. Independent IDs are assigned to them.
For the reset part, differing from previous Rockchip SoCs and
downstream bindings which embeds register offsets into the IDs, gapless
numbers starting from zero are used.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250217061142.38480-6-ziyao@disroot.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: e0c0a97bc308f71b0934e3637ac545ce65195df0 ]
(cherry picked from commit 8768d063e732e64892e4d1d09aa583d1394c8388)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jiaxun Yang <jiaxun.yang@flygoat.com> says:
This is a huge series which promoted MIPS/Boston target into a
usable state, with fixes to drivers and general framework issues
I found in this process.
I also converted the target to OF_UPSTREAM.
This target is covered by QEMU, to test on QEMU:
```
make boston64r6el_defconfig
make
qemu-system-mips64el -M boston -cpu I6500 -bios ./u-boot.bin -nographic
```
Link: https://lore.kernel.org/r/20240517-boston-v3-0-1ea7d23f4a1d@flygoat.com
BootROM leave GPIO4_D6 configured as SDMMC_PWREN function and DW MCI
driver set PRWEN high on MMC_POWER_UP and low on MMC_POWER_OFF.
Similarly U-Boot also set PRWEN high before accessing mmc.
However, HW revision prior to v1.2 must pull GPIO4_D6 low to access
sdmmc. For HW revision v1.2 the state of GPIO4_D6 has no impact.
Model an always-on active low fixed regulator using GPIO4_D6 to fix
use of sdmmc on older HW revisions of the board.
Fixes: adeb5d2a4ba4 ("arm64: dts: rockchip: Add Radxa ROCK S0")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20241119230838.4137130-1-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: 26c100232b09ced0857306ac9831a4fa9c9aa231 ]
(cherry picked from commit ca8e0bedbc790b19b11efc223677d178b8eeb74e)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
QEMU always gets its devicetree from the OF_BOARD mechanism so we should
not depend on !BLOBLIST here.
It's not clear why we need to have any relationship with BLOBLIST so
let's remove the entire condition.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 2b71470628 dts: OF_HAS_PRIOR_STAGE should depend on !BLOBLIST
Reviewed-by: Tom Rini <trini@konsulko.com>
Radxa ROCK 5C is a 8K computer for everything[1] using the Rockchip
RK3588S2 chip:
- Rockchip RK3588S2
- Quad A76 and Quad A55 CPU
- 6 TOPS NPU
- up to 32GB LPDDR4x RAM
- eMMC / SPI flash connector
- Micro SD Card slot
- Gigabit ethernet port (supports PoE with add-on PoE HAT)
- WiFi6 / BT5.4
- 1x USB 3.0 Type-A HOST port
- 1x USB 3.0 Type-A OTG port
- 2x USB 2.0 Type-A HOST port
- 1x USB Type-C 5V power port
[1] https://radxa.com/products/rock5/5c
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://lore.kernel.org/r/20241021090548.1052-2-naoki@radxa.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: 3ddf5cdb77e6efd6fe9b70f36dec935e324a3cd2 ]
(cherry picked from commit f80689fcef4b9b07a97b629b4075cc1a4c21a68e)
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
These pinctrls manage the low-speed PCIe signals:
- CLKREQ#: An output on the RK3588 (both RC or EP modes), used to
request that external clock-generation circuitry provide a clock.
- PERST#: An input on the RK3588 in EP mode, used to detect a reset
signal from the RC. In RC mode, the hardware does not use this signal:
Linux itself generates it by putting the pin in GPIO mode.
- WAKE#: In EP mode, this is an output; in RC mode, this is an input.
Each of these signals serves a distinct purpose, and more importantly,
PERST# should not be muxed when the RK3588 is in the RC role. Bundling
them together in pinctrl groups prevents proper use: indeed, almost none
of the current board-specific .dts files make any use of them.
(Exception: Rock 5A recently had a patch land that misuses _pins; this
patch corrects that.)
However, on some RK3588 boards, the PCIe 3 controller will indefinitely
stall the boot if CLKREQ# is not muxed (details in the next patch).
This patch unbundles the signals to allow them to be used.
Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Link: https://lore.kernel.org/r/20240912025034.180233-2-CFSworks@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: 4294e32111781b3de4d73b944cbd1bc1662a9a7a ]
(cherry picked from commit 8713425fa162b61bcf5f7a6dcd171fddfb12be36)
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Typically any non-removable storage (emmc) is listed before removable
storage (sd-card) options. Also U-Boot will try to override and use
mmc0=sdhci and mmc1=sdmmc0 for all rk356x boards.
Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board")
Suggested-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Link: https://lore.kernel.org/r/20241022193537.1117919-6-cnsztl@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: b7cd1115456d312f8c5e60c80fdc35fd35ea6eab ]
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
