Adjust Kconfig and defconfig and add SPL initialization code for
Lichee Pi 4A. Then enable SPL support which we've added for TH1520 SoC
earlier. The board devicetree is changed to use TH1520 binman
configuration to generate bootable images.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Add binman configuration for TH1520 SoC, whose BROM loads the image
combined into SRAM and directly jumps to it. The configuration creates
u-boot-with-spl.bin where the SPL code locates at the start and the DDR
firmware is shipped.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Describe DRAM controller integrated in TH1520 SoC and preserve it in SPL
devicetree blob.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Memory node is necessary for TH1520 SPL to configure size and base
address of DRAM. Let's preserve it in SPL devicetree blob.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
SPL for TH1520 requires CPU and boot UART nodes to function. Preserve
them in SPL devicetree blob with bootph-pre-ram property.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Introduce the SoC-specific code and corresponding Kconfig entries for
TH1520 SoC. Following features are implemented for TH1520,
- Cache enable/disable through customized CSR
- Invalidation of customized PMP entries
- DRAM driver probing for SPL
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Designed before a standard set of cache management operations defined in
RISC-V, earlier T-Head cores like C906 and C910 provide CMO through the
customized extension XTheadCMO, which has been used in the CV1800B port
of U-Boot.
This patch splits XTheadCMO-related code into a generic module, allowing
SoCs shipping T-Head cores to share the code.
Link: https://github.com/XUANTIE-RV/thead-extension-spec
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
JH7110 drivers are missing support for CPU frequency scaling, so override
upstream device-tree to use default clock rates for syscrg. This override
duplicates a portion of jh7110-common-u-boot.dtsi file planned for removal.
Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Leo Liang <ycliang@andestech.com>
- use upstream alias name for cpu and timer nodes
- remove bootph-pre-ram hint from parent nodes
- drop S7 cpu core "okay" status
Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Move unnecessary clock frequency assignment out of device-tree and into the
board config header so that the ns16550 serial driver can successfully init
during SPL after failing to resolve the parent clock from upstream dts. The
serial driver will then resolve clock frequency from device-tree node parent
clock at init during Main app as it is expected by upstream.
Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Fix the erroneous header guard for insn-def.h to reflect the correct
header name.
Fixes: bfc8ca3f7f ("riscv: Add support for defining instructions")
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Similar to AArch64's case, Clang may wrongly fold accesses to gd pointer
which is defined with register qualifier into constants, breaking
various components.
This patch defines gd as a macro when building with Clang or LTO, which
expands to get_gd() that accesses gp pointer in assembly, making RISC-V
ports function properly and preparing for introduction of LTO in the
future. Board initialization code is also adapted for non-assignable gd.
Reported-by: Nathaniel Hourt <I@nathaniel.land>
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Drop filename property for proper U-Boot entry since binman takes
"u-boot-nodtb.bin" as the default filename for u-boot-nodtb entries.
This follows efe9c12322 ("riscv: dts: binman.dtsi: Switch to
u-boot-nodtb entry for proper U-Boot") to clean binman.dtsi up.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Unlike ARM and X86, booting 32-bit images on 64-bit CPUs is currently
not supported for Risc-V. Hence, for bootm, disallow booting a FIT
or a legacy image that was built for an arch type which is different
than the current arch and for booti, set the arch type to be the
same as the current arch.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Select between the 32-bit or 64-bit arch type for the image headers
depending on how the build is configured.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Enable DM_SERIAL for Marvell Kirkwood boards that have not been converted.
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
As the code is today, we get a warning about "select" statements on
"choice" options not doing anything. In this case, we move to having a
"default FSP_VERSION2 if INTEL_APOLLOLAKE" in order to get the desired
outcome.
Signed-off-by: Tom Rini <trini@konsulko.com>
This change adds `BOOT_DEVICE_NVME` to the `enum` list in
`arch/x86/include/asm/spl.h`,
enabling NVMe as a recognized boot device for SPL (Secondary Program
Loader).
Tested x86 hardware with coreboot + U-Boot payload.
Verified successful boot to NVMe drive.
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This file was using IS_ENABLED() to test for CONFIG flags but omitted
the CONFIG_ prefix and so did not work as expected.
Signed-off-by: Tom Rini <trini@konsulko.com>
This file was using IS_ENABLED() to test for CONFIG flags but omitted
the CONFIG_ prefix and so did not work as expected.
Signed-off-by: Tom Rini <trini@konsulko.com>
This was a temporary workaround for the Tegra210 Jetson Nano board. It is
not used by any device anymore, so let's remove it.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Since most boards now use the same generic device config header, move its
setup to SoC Kconfig instead of setting SYS_CONFIG_NAME in each board's
Kconfig.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
The LG Optimus 2X is a touchscreen-based, slate-sized smartphone designed
and manufactured by LG that runs the Android operating system. The
Optimus 2X features a 4" WVGA display, an Nvidia Tegra 2 dual-core chip,
512 MB of RAM and extendable 8 GB of internal storage. UART-B is default
debug port.
Tested-by: Ion Agorria <ion@agorria.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Add support for 8-bit CPU driven (primary and secondary) display signal
interface found in Tegra 2 and Tegra 3 SoC.
Tested-by: Ion Agorria <ion@agorria.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Update GMAC speed and flow control fields in GRF_SOC_CON1 to use
RK3288_GMAC_* prefix, ensuring a consistent naming convention. It also
shifts each mask/bit definition to match the actual hardware bits, which
makes future usage easier.
Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The LCKFB TaishanPi is a single-board computer based on the RK3566 SoC.
Specification:
- 1/2 Gib RAM
- Optinal EMMC
- SD-Card
- HDMI / MIPI CSI / MIPI DSI
- USB 2.0 Host (Type-A)
- USB 2.0 Host / OTG (Type-C)
- No Ethernet
This patch adds U-Boot support for the LCKFB TaishanPi RK3566 board, including:
- U-Boot device tree
- Default defconfig
- Board documentation
- MAINTAINERS entry
Changes in v2:
- Removed unused configs from `lckfb-tspi-rk3566_defconfig`
- Reordered TaishanPi entry in `doc/board/rockchip/rockchip.rst` alphabetically
Link to v1:
https://lore.kernel.org/u-boot/tencent_95ED0C0545D87B6A8C4B62EC045D53AD2406@qq.com/
Signed-off-by: Jiehui He <jiehui.he@foxmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The 5 Max is another board in the Orange Pi 5 family.
It's overall similar to the 5 Plus, but in a smaller form factor,
which leads to some I/O being reshuffled, but nothing relevant
to u-boot.
So, just reuse the config for the 5 Plus and adjust the DT names.
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Ilya Katsnelson <me@0upti.me>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
!A || (A && B) is equivalent to !A || B
Drop the unused middle expression to simplify the statement.
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Use of SHA256 checksum validation on ARMv7 SoCs can be very time
consuming compared to when used on a ARMv8 SoC with Crypto Extensions.
Add support for use of the much faster CRC32 hash algo when SHA256 is
not supported in SPL. Also use FIT_HASH_ALGO to simplify the ifdefs when
no known hash algo has been compiled.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Provide a compatible string in the config nodes that U-Boot can use to
help decide which configuration to use with SPL_LOAD_FIT_FULL=y and
FIT_BEST_MATCH=y.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Declare arch and compression at the top of the file to avoid needing
ifdefs in every usage.
Add a few comments to help with the remaining #ifdefs.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The U-Boot image is currently being identified as an invalid OS in
spl_fit_image_get_os() due to case sensitive compare.
Use the correct lower-case value to fix this.
Fixes: e0c0efff2a ("rockchip: Support building the all output files in binman")
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
This was only used on RK3288 Chromebooks and the EVB.
If it follows the same pattern as for RK3399 Chromebooks where their
maintainer (Simon) agreed[1] to removal of u-boot.rom on the basis that
the generic u-boot-rockchip-spi.bin is now enough, let's do the same for
RK3288 and remove the last Rockchip users of u-boot.rom (and HAS_ROM
symbol).
At the same time, remove HAS_ROM symbol from the RK3288 Chromebooks and
EVB configs since they were used only for that.
SYS_SPI_U_BOOT_OFFS offset in rockchip-u-boot.dtsi for the u-boot-img
node of simple-bin-spi binman image matches the one used in u-boot.rom
except for the EVB.
The EVB doesn't have ROCKCHIP_SPI_IMAGE symbol enabled, so HAS_ROM had
no effect anyway. Even if it had, this would not have been enough
considering that SPL_SPI_LOAD symbol is not set, so U-Boot proper could
not be loaded from SPI even if SPL/TPL does.
Make sure u-boot-rockchip-spi.bin has the same size of u-boot.rom for
Chromebooks as that seems to be important.
[1] https://lore.kernel.org/u-boot/CAFLszTh-SewFod8dEOF3+e-wCE1qFF0CyxxR8CbQwy3BRW3k6w@mail.gmail.com/
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Simon Glass <sjg@chromium.org> # chromebook-kevin
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
This was only used on RK3399 Gru Chromebooks and their maintainer
(Simon) agreed[1] to its removal on the basis that the generic
u-boot-rockchip-spi.bin is now enough, so let's do that.
At the same time, remove HAS_ROM symbol from the Gru Chromebooks config
since they were used only for that.
Make sure u-boot-rockchip-spi.bin has the same size of u-boot.rom for
Chromebooks as that seems to be important.
[1] https://lore.kernel.org/u-boot/CAFLszTh-SewFod8dEOF3+e-wCE1qFF0CyxxR8CbQwy3BRW3k6w@mail.gmail.com/
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Simon Glass <sjg@chromium.org> # chromebook-kevin
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
[backport from Linux commit db4fc2c79c533986795a7750e9a12caf9d620b48]
As reported in the section 8.3 (i. e. Board revision history) of document
UM2033 (i. e. Discovery kit with STM32F769NI MCU) these are the changes
related to the board revision addressed by the patch:
- Board MB1166 revision A-09:
- LCD FRIDA FRD397B25009-D-CTK replaced by FRIDA FRD400B25025-A-CTK
The patch adds the DTS support for the new display which belongs to the
the Novatek NT35510-based panel family.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
The Renesas R9A07G044L (RZ/G2L) SoC includes two Gigabit Ethernet
interfaces which can be supported using the ravb driver. Some RZ/G2L
specific steps need to be taken during initialization due to differences
between this SoC and previously supported SoCs. We also need to ensure
that the module reset is de-asserted after the module clock is enabled
but before any Ethernet register reads/writes take place.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
This patch adds i.MX95 19x19 EVK board basic support.
Messaging unit for EdgeLock Secure Enclave, messaging unit for System
Manager, uSDHC for SD Card, gpio, lpuart are supported now.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
This patch adds V2X container support for i.MX95. Since V2X container
may not be included in ahab-container.img of i.MX95, check if V2X
container exists in order to get the correct image end.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
i.MX95 only supports low power boot, which means A55 is kicked by M33.
There is no ROM runs on A55 in such case so that deselect IMX8_ROMAPI
for i.MX95.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
This patch adds i.MX95 Kconfig and Makefile. i.MX95 uses SCMI.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
When SPL loading image to secure region, for example, ATF and tee to
DDR secure region. Because the USDHC controller is non-secure master,
it can't access this region and will cause loading issue.
So use a trampoline buffer in non-secure region, then use CPU to copy the
image from trampoline buffer to destination secure region.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
