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Author SHA1 Message Date
Tom Rini
e7f7e2e1e2 Merge tag 'xilinx-for-v2023.10-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze 
Xilinx changes for v2023.10-rc1 v2

axi_emac:
- Change return value if RX packet is not ready

cadence_qspi:
- Enable flash reset for Versal NET

dt:
- Various DT syncups with Linux kernel
- SOM - reserved pmufw memory location

fpga:
- Add load event

mtd:
- Add missing dependency for FLASH_CFI_MTD

spi/nand:
- Minor cleanup in Xilinx drivers

versal-net:
- Prioritize boot device in boot_targets
- Wire mini ospi/qspi/emmc configurations

watchdog:
- Use new versal-wwdt property

xilinx:
- fix sparse warnings in various places ps7_init*
- add missing headers
- consolidate code around zynqmp_mmio_read/write
- switch to amd.com email

zynqmp_clk:
- Add handling for gem rx/tsu clocks

zynq_gem:
- Configure mdio clock at run time

zynq:
- Enable fdt overlay support

zynq_sdhci:
- Call dll reset only for ZynqMP SOCs
 2023-07-21 09:57:59 -04:00
Christian Taedcke
a1190b4d6a event: Add fpga load event 
This enables implementing custom logic after a bitstream was loaded
into the fpga.

Signed-off-by: Christian Taedcke <christian.taedcke@weidmueller.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Link: https://lore.kernel.org/r/20230720072724.11516-1-christian.taedcke-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
 2023-07-21 09:00:39 +02:00
Ashok Reddy Soma
2a907542c7 clk: zynqmp: Add gem rx and tsu clocks to return register 
Add gem_tsu and gem0_rx till gem3_rx to return proper register from
zynqmp_clk_get_register. Otherwise firmware won't be able to set clock
for these due to incorrect register address.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230720072859.3724-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
 2023-07-21 09:00:39 +02:00
Ashok Reddy Soma
7a480fd995 clk: zynqmp: Add set_rate support for gem rx and tsu clks 
gem0_rx till gem3_rx  and gem_tsu are missing from set rate function.
Add them, so that they can be set from pmu firmware via clock framework.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230719084912.30209-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
 2023-07-21 09:00:39 +02:00
Maksim Kiselev
3fb4ef7d39 net: axi_emac: Change return value to -EAGAIN if RX is not ready 
If there is no incoming package than axiemac_recv will return -1 which
in turn leads to printing `eth_rx: recv() returned error -1` error
message in eth_rx function. But missing a package is not an fatal error,
so return -EAGAIN in that case would be more suitable.

Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
Link: https://lore.kernel.org/r/20230719065337.69280-1-bigunclemax@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
 2023-07-21 09:00:39 +02:00
Michal Simek
c310c98201 arm64: zynqmp: Remove clock-names from pcap node 
Clock is not used in driver and also not described in binding.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/0a0fa0ba197fa4051a2c8a24e1451cefadce7517.1688992653.git.michal.simek@amd.com
 2023-07-21 09:00:39 +02:00
Michal Simek
4c360f6cfd arm64: zynqmp: Rename ams_ps/pl node names 
Fix child node names to be aligned with dt-binding available in the Linux
kernel which requires names as ams-ps@ and ams-pl@.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/8f1451d614f654cb0d0da1e799e876c078fbf2c9.1688992653.git.michal.simek@amd.com
 2023-07-21 09:00:39 +02:00
Michal Simek
20beff0ddb arm64: zynqmp: Remove interrupt/reg-names for AMS 
These two properties are not described in DT binding and also not used by
driver that's why remove them.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b123c7e537dcf70802e828bbcd484a761a264186.1688992653.git.michal.simek@amd.com
 2023-07-21 09:00:39 +02:00
Piyush Mehta
a876a5112e arm64: zynqmp: remove snps, enable_guctl1_resume_quirk quirk for usb 
To sync with the upstream code, removed 'snps,enable_guctl1_resume_quirk'
quirk for usb. This quirk is no more available in linux after the xilinx
release 2022.2.

This functionality is taken care of by the 'snps,resume-hs-terminations'
quirk.

Signed-off-by: Piyush Mehta <piyush.mehta@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/4b7a132116bf0248cdb558e04de3b06b412c4a0f.1688992653.git.michal.simek@amd.com
 2023-07-21 09:00:39 +02:00
Radhey Shyam Pandey
7cfddb4c07 arm64: zynqmp: add pmu interrupt-affinity 
Explicitly specify interrupt affinity to avoid HW perfevents
need to guess. This avoids the following error upon linux boot:
armv8-pmu pmu: hw perfevents: no interrupt-affinity property,
guessing.

Reported-by: John Toomey <john.toomey@amd.com>
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c2f55a10cf54c6004f5dfe2ea18bcb4cf04f5723.1688992653.git.michal.simek@amd.com
 2023-07-21 09:00:39 +02:00
Michal Simek
606121cdf4 arm64: zynqmp: Sync node name address with reg (mailbox) 
Address in node name should match with the first reg property in DT.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/47bea10bbc3c88727c1fe839ff20e15a0c79c339.1688992653.git.michal.simek@amd.com
 2023-07-21 09:00:39 +02:00
Radhey Shyam Pandey
a8d4b67000 arm64: zynqmp: Add L2 cache nodes 
Linux kernel throws "cacheinfo: Unable to detect cache hierarchy for
CPU 0" warning when booting on zu+ Soc. To fix it add the L2 cache
node and let each CPU point to it.

Reported-by: John Toomey <john.toomey@amd.com>
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c8dfabab12c97922aaad7fa91be0cbc7e4021528.1688992653.git.michal.simek@amd.com
 2023-07-21 09:00:39 +02:00
Michal Simek
1ea11e8138 arm64: zynqmp: Fix usb reset over bootmode pins on zcu100 
The commit a4180c3696 ("arm64: zynqmp: Add mode-pin GPIO controller DT
node") added usb phy reset over bootmode pins by default on usb0 only.
zcu100 is using usb0 as peripheral and usb1 as host. Unfortunately reset
line is shared for both usb ulpi phys but usb_rst_b is connected to usb5744
hub which is used only in host mode. Especially this chip requires reset to
operate properly that's why better assign gpio reset to usb1 instead of
usb0.
Without this change usb start crashed when runs.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1ca80ec5bf7a595c03822f3e4e3683298205067a.1688992653.git.michal.simek@amd.com
 2023-07-21 09:00:39 +02:00
Michal Simek
58601fbb8f arm64: zynqmp: Cover K24 revB/1 SOM 
Extend compatible versions for K24 SOM.
Changes are not affecting SW behavior that's why all versions are
compatible to each other.
Describing all revisions is done by purpose because user space SW is
reading compatible string for logic around DT overlays and bitstreams.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/92eba01ac316e58bd2d3508b0e63bbfafbedbb73.1688992653.git.michal.simek@amd.com
 2023-07-21 09:00:39 +02:00
Michal Simek
efa1ddea07 arm64: zynqmp: Record compatible string for kv260 rev2 
PCB rev2 compare to rev1 has some changes in PL side (IAS sensor AR1335
autofocus feature). PS side is completely unchanged.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/42f78dee8429eeac016d73de5c73af46fdaf4a98.1688992653.git.michal.simek@amd.com
 2023-07-21 09:00:39 +02:00
Harini Katakam
6a251f2488 arm64: zynqmp: Assign TSU clock frequency for KV and KD boards 
Set TSU clock frequency as 250MHz (minimum when running at 1G) on
KV and KD carrier cards to allow PTP functionality.

Signed-off-by: Harini Katakam <harini.katakam@amd.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/4b758d503ef545e4d25d3930b0eb0793f1c415d2.1688992653.git.michal.simek@amd.com
 2023-07-21 09:00:39 +02:00
Harini Katakam
414fc91f4e arm64: zynqmp: Increase reset assert time for TI SGMII PHY 
Increase reset assert time for TI SGMII PHY on KR260 CC starting
6.1 kernel. This PHY does not come out of reset with the existing
100us pulse width as per testing on multiple carrier cards. The reset
is driven via a PCA9570 I2C expander. The expander driver was updated
to an upstream version in 6.1 where gpio_chip _set was optimized.
Delays in earlier kernels may have masked this issue. This is a safe
workaround value for assert pulse width before the discussions are
resolved with TI.

Signed-off-by: Harini Katakam <harini.katakam@amd.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/8fb9f17d43a43ef504c9f29006cd686cce8ac98b.1688992653.git.michal.simek@amd.com
 2023-07-21 09:00:38 +02:00
Michal Simek
369d04d643 arm64: zynqmp: Fix gpio comment about No of gpios 
There are total 174 gpios but from 0 - 173 that's why fix comment to
reflect it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c7e94b334e7dd6297e0d3a36a6a3d04bd7e9e967.1688992653.git.michal.simek@amd.com
 2023-07-21 09:00:38 +02:00
Harini Katakam
f668961485 arm64: zynqmp: Assign TSU clock frequency for KR260 
Set TSU clock frequency as 250MHz (minimum when running at 1G) on
KR260 CC to allow PTP functionality.

Signed-off-by: Harini Katakam <harini.katakam@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d065b5c2c6450910bf57d104d65946111493caaa.1688992653.git.michal.simek@amd.com
 2023-07-21 09:00:38 +02:00
Parth Gajjar
d95fc99a74 arm64: zynqmp: Update MALI 400 interrupt and clock names 
Motivation for the commit is to utilize the upstream community
device tree so that the either modified ARM Mali 400 driver
or upstream lima driver can be used.

Signed-off-by: Parth Gajjar <parth.gajjar@amd.com>
Signed-off-by: Vishal Sagar <vishal.sagar@amd.com>
Link: https://lore.kernel.org/r/1678181001-2327-2-git-send-email-parth.gajjar@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/89d046a9da5638e8b4918f80f3245d73ea46f99f.1688992653.git.michal.simek@amd.com
 2023-07-21 09:00:38 +02:00
Manikanta Guntupalli
28dc356e66 xilinx: dts: Fix open drain warning on Zynq, ZynqMP and Versal 
Fix for below open drain warning on Zynq, ZynqMP and Versal reported by
Linux.
"enforced open drain please flag it properly in DT/ACPI DSDT/board
file."

Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/056b6f60f89fa2addb762669b80640cd5b31b001.1688992653.git.michal.simek@amd.com
 2023-07-21 09:00:38 +02:00
Varalaxmi Bingi
39bdb96498 arm: xilinx: Setting default i2c clock frequency to 400kHz 
Setting default i2c clock frequency for Zynq and ZynqMP to maximum rate of
400kHz. Current default value is 100kHz.

Signed-off-by: Varalaxmi Bingi <varalaxmi.bingi@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/fb46fe911a68b79c8e4d150ca90c4e94eb5fb9e1.1688992653.git.michal.simek@amd.com
 2023-07-21 09:00:38 +02:00
Michal Simek
ed4a0ccb6e mtd: Add missing MTD dependency for cfi_mtd 
cfi_mtd requires add_mtd_device() which is available only when MTD is
enabled that's why record this dependency.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/76ae01ce2b2c988758b69e0f0cdcc21bf301c01e.1688472227.git.michal.simek@amd.com
 2023-07-21 09:00:38 +02:00
Ashok Reddy Soma
752e4b6c8e mmc: zynq_sdhci: Dll reset only for ZynqMP platform 
Dll reset is needed only for ZynqMP platforms, add condition in tuning
to call arasan_zynqmp_dll_reset() just for ZynqMP platforms.

On other platforms like Versal NET, If this condition is not added, we
see PLM error messages when dll reset smc is called.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d673ff3bdc5c236a7f0403c920e719684abd6059.1688991117.git.michal.simek@amd.com
 2023-07-21 09:00:38 +02:00
Michal Simek
174d728471 arm64: zynqmp: Switch to amd.com emails 
Update my and DPs email address to match current setup.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
 2023-07-21 09:00:38 +02:00
Raju Kumar Pothuraju
378f4eef09 xilinx: zynq: Enable fdt apply utility for zynq 
Enables the FDT library (libfdt) overlay support for zynq platforms
to be able to use fdt apply command.

Signed-off-by: Raju Kumar Pothuraju <rajukumar.pothuraju@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ab26dd186fb752b3d607e6160ae5baf6661d5de7.1688990179.git.michal.simek@amd.com
 2023-07-21 09:00:38 +02:00
Michal Simek
5b90412cbf xilinx: Consolidate zynqmp_mmio_read/write in zynqmp_firmware.h 
zynqmp_mmio_read/write() are firmware provided hooks that's why use only
zynqmp_firmware.h for function declaration.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/e7489556f9e447c737a578c169d7e1e43586a273.1687524706.git.michal.simek@amd.com
 2023-07-21 09:00:38 +02:00
Ashok Reddy Soma
37688da586 xilinx: versal-net: Add mini eMMC 5.1 configuration 
Add support for Versal NET mini eMMC 5.1 configuration. Add device tree
and defconfig.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614121351.21521-4-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
 2023-07-21 09:00:38 +02:00
Ashok Reddy Soma
38e0fc06b2 xilinx: versal-net: Add mini ospi configuration 
Add support for Versal NET mini Octal SPI flash configuration. This runs
from onchip memory, so it has to be compact. Hence only Octal SPI
related settings are enabled.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614121351.21521-3-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
 2023-07-21 09:00:38 +02:00
Ashok Reddy Soma
96683d3436 xilinx: versal-net: Add mini qspi configuration 
Add support for Versal NET mini Quad SPI flash configuration. This runs
from onchip memory, so it has to be compact. Hence only Quad SPI
related settings are enabled.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614121351.21521-2-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
 2023-07-21 09:00:38 +02:00
Ashok Reddy Soma
34dec6a443 cadence_qspi: Enable flash reset for Versal NET platform 
Enable flash reset functionality for Versal NET platform.
In cadence_qspi.c there is weak function defined for reset, hence remove
the check for config, so that it will work for Versal and Versal NET
platforms.

Add register defines in Versal NET hardware.h for mini U-Boot flash
reset.

Add read_delay initialization for Versal NET also.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614120452.21019-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
 2023-07-21 09:00:38 +02:00
Venkatesh Yadav Abbarapu
22836f088d net: zynq_gem: Don't hardcode the MDC clock divisor 
As per spec MDC must not exceed 2.5MHz, read the pclk clock
from the device tree and update the MDC clock divisor.
GEM devices support larger clock divisors and have a different
range of divisors.  Program the MDIO clock divisors based on
the clock rate of the pclk clock.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20230619034922.24019-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
 2023-07-21 09:00:38 +02:00
Ashok Reddy Soma
9a45365ae9 arm64: versal-net: spi: Update boot sequence dynamically 
Currently xspi0 is used for all spi boot modes, it means it will use "sf
probe 0 0 0" for all spi's irrespective of which node it is wired.

Get boot sequence from dev_seq() and update boot command for xspi
dynamically.

As a result bootcmd for spi is updated as below when two instances of spi
are present in DT node.
bootcmd_xspi0=devnum_xspi=0; run xspi_boot
bootcmd_xspi1=devnum_xspi=1; run xspi_boot

xspi_boot=sf probe $devnum_xspi:0 0 0 && sf read $scriptaddr
$script_offset_f $script_size_f && echo XSPI: Trying to boot script at
${scriptaddr} && source ${scriptaddr}; echo XSPI: SCRIPT FAILED:
continuing...;

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614093058.30438-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
 2023-07-21 09:00:38 +02:00
Algapally Santosh Sagar
340760ec0f xilinx: zynq: Add the missing function prototypes 
Add the missing prototypes for the functions pointed by the below
sparse warnings
warning: no previous prototype for 'set_dfu_alt_info'
[-Wmissing-prototypes]
warning: no previous prototype for 'board_debug_uart_init'
[-Wmissing-prototypes]

Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614090359.10809-7-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
 2023-07-21 09:00:38 +02:00
Algapally Santosh Sagar
3bfc94ba9c arm: zynq: Pass the missing argument type in function definition 
Pass missing argument type in the function definition to fix the
sparse warning, warning: old-style function definition
[-Wold-style-definition]

Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614090359.10809-6-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
 2023-07-21 09:00:38 +02:00
Algapally Santosh Sagar
52279be25c mtd: nand: zynq_nand: Change datatype of status and ecc_status to int 
status and ecc_status are of unsigned type where they are compared for
negative value. This is pointed by below sparse warning. Change datatype
to int to fix this.
warning: comparison of unsigned expression in '< 0' is always false
[-Wtype-limits]

Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614090359.10809-5-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
 2023-07-21 09:00:38 +02:00
Algapally Santosh Sagar
0ebb68fb55 spi: zynq_qspi: Add missing prototype for zynq_qspi_mem_exec_op 
Add missing prototype to fix the sparse warning, warning: no
previous prototype for 'zynq_qspi_mem_exec_op' [-Wmissing-prototypes].

Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614090359.10809-4-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
 2023-07-21 09:00:38 +02:00
Algapally Santosh Sagar
fdae78b5f5 xilinx: zynq: Add missing prototype for zynqmp_mmio_write 
Add missing prototype to fix the sparse warning, warning: no
previous prototype for 'zynqmp_mmio_write' [-Wmissing-prototypes].

Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614090359.10809-3-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
 2023-07-21 09:00:38 +02:00
Algapally Santosh Sagar
583cebb9ec spi: xilinx_spi: Add missing prototype for xilinx_qspi_mem_exec_op 
Add missing prototype to fix the below sparse warning
warning: no previous prototype for 'xilinx_qspi_mem_exec_op'
[-Wmissing-prototypes]

Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614090359.10809-2-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
 2023-07-21 09:00:38 +02:00
Sharath Kumar Dasari
85a2d124cd arm64: zynqmp: Fix the memory node for k26/k24 kria som boards 
PMUFW requires top 1MB of the lower DDR memory reserved for its operation,
this is missing in k26/k24 sm static dts files because of which U-Boot
throws warning messages "efi_free_pool: illegal free" as EFI puts
some code to that space which shouldn't happen.

Signed-off-by: Sharath Kumar Dasari <sharath.kumar.dasari@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/57452d16df2d48593de206bebf877d2c2cfe7bf1.1685966389.git.michal.simek@amd.com
 2023-07-21 09:00:38 +02:00
Michal Simek
a24a1a19ef watchdog: versal: Use new compatible xlnx,versal-wwdt 
DT binding has been approved that's why use new compatible string.
The old one is mark as deprecated and should be removed after some
releases.

Link: https://lore.kernel.org/r/20230420104231.2243079-3-srinivas.neeli@amd.com/
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/6e78d0d2e21f2f9e7f8f448bb8e0d27ced4de7d3.1686655339.git.michal.simek@amd.com
 2023-07-21 09:00:38 +02:00
Tom Rini
e896279ac3 Merge tag 'dm-pull-20jul23' of https://source.denx.de/u-boot/custodians/u-boot-dm 
binman mkimage and template enhancements
misc fixes
 2023-07-20 21:31:31 -04:00
Tom Rini
7fe5accb45 Merge branch '2023-07-20-assorted-CI-updates' 
- Move to gcc-13.1 and QEMU 8.0.3 in CI.  This also lets us move to a
  kernel.org toolchain for arc as well.
 2023-07-20 21:28:59 -04:00
Simon Glass
24142ead21 binman: Reduce state.SetInt and bintool cmd to debug level 
These are not very important message. Change them to use the 'debug' level
instead of 'detail'.

Signed-off-by: Simon Glass <sjg@chromium.org>
 2023-07-20 14:10:58 -06:00
Simon Glass
23b96e920b binman: Support writing symbols inside a mkimage image 
Add support for writing symbols and determining the assumed position of
binaries inside a mkimage image. This is useful as an example for other
entry types which might want to do the same thing.

Signed-off-by: Simon Glass <sjg@chromium.org>
 2023-07-20 14:10:58 -06:00
Simon Glass
696f2b73d6 binman: Support templates at any level 
Allow templates to be used inside a section, not just in the top-level
/binman node.

Signed-off-by: Simon Glass <sjg@chromium.org>
 2023-07-20 14:10:58 -06:00
Simon Glass
db0e3f13b4 binman: Add a test for templating in a FIT 
Add this as a separate test case.

Signed-off-by: Simon Glass <sjg@chromium.org>
 2023-07-20 14:10:58 -06:00
Simon Glass
35f72fb55a binman: Support templating with multiple images 
Allow a template to appear in the top level description when using
multiple images.

Signed-off-by: Simon Glass <sjg@chromium.org>
 2023-07-20 14:10:58 -06:00
Simon Glass
f6abd5227a binman: Support simple templates 
Collections can used to collect the contents of other entries into a
single entry, but they result in a single entry, with the original entries
'left behind' in their old place.

It is useful to be able to specific a set of entries ones and have it used
in multiple images, or parts of an image.

Implement this mechanism.

Signed-off-by: Simon Glass <sjg@chromium.org>
 2023-07-20 14:10:58 -06:00
Simon Glass
55e1278d5e dtoc: Allow inserting a list of nodes into another 
Provide a way to specify a phandle list of nodes which are to be inserted
into an existing node.

Signed-off-by: Simon Glass <sjg@chromium.org>
 2023-07-20 14:10:58 -06:00