* Add support for IceCube board (with MGT5100 and MPC5200 CPUs)

* Add support for MGT5100 and MPC5200 processors

CHANGELOG

@@ -1,7 +1,81 @@
 ======================================================================
-Changes since U-Boot 0.4.0:
+Changes for U-Boot 0.4.4:
 ======================================================================
 
+* Add support for IceCube board (with MGT5100 and MPC5200 CPUs)
+
+* Add support for MGT5100 and MPC5200 processors
+
+* Patch by Lutz Dennig, 15 Jul 2003:
+  update for R360MPI board
+
+======================================================================
+Changes for U-Boot 0.4.3:
+======================================================================
+
+* Patches by Kshitij, 04 Jul 2003
+  - added support for arm925t cpu core
+  - added support for TI OMAP 1510 Innovator Board
+
+* Patches by Martin Krause, 14 Jul 2003:
+  - add I2C support for s3c2400 systems (trab board)
+  - (re-) add "ping" to command table
+
+* Fix handling of "slow" POST routines
+
+* Patches by Yuli Barcohen, 13 Jul 2003:
+  - Correct flash and JFFS2 support for MPC8260ADS
+  - fix PVR values and clock generation for PowerQUICC II family
+    (8270/8275/8280)
+
+* Patch by Bernhard Kuhn, 08 Jul 2003:
+  - add support for M68K targets
+
+* Patch by Ken Chou, 3 Jul:
+  - Fix PCI config table for A3000
+  - Fix iobase for natsemi.c
+    (PCI_BASE_ADDRESS_0 is the IO base register for DP83815)
+
+* Allow to enable "slow" POST routines by key press on power-on
+* Fix temperature dependend switching of LCD backlight on LWMON
+* Tweak output format for LWMON
+
+* Patch by Stefan Roese, 11 Jul 2003:
+  - Fix bug in CONFIG_VERSION_VARIABLE.
+  - AR405 config updated.
+  - OCRTC/ORSG: bsp command added.
+  - ASH405 bsp update.
+
+======================================================================
+Changes for U-Boot 0.4.2:
+======================================================================
+
+* Add support for NSCU board
+
+* Add support for TQM823M, TQM850M, TQM855M and TQM860M modules
+
+* Add support for Am29LV160ML, Am29LV320ML, and Am29LV640ML
+  mirror bit flash on TQM8xxM modules
+
+* Patch by Kenneth Johansson, 30 Jun 2003:
+  get rid of MK_CMD_ENTRY macro; update doc/README.command
+
+* Patch by Seb James, 30 Jun 2003:
+  Improve documentation of I2C configuration in README
+
+* Fix problems with previous log buffer "fixes"
+
+* Fix minor help text issues
+
+* "log append" did not append a newline
+
+======================================================================
+Changes for U-Boot 0.4.1:
+======================================================================
+
+* Fix some missing commands, cleanup header files
+  (autoscript, bmp, bsp, fat, mmc, nand, portio, ...)
+
 * Rewrite command lookup and help command (fix problems with bubble
   sort when sorting command name list). Minor cleanup here and there.
 

MAINTAINERS

@@ -52,6 +52,8 @@ Wolfgang Denk <wd@denx.de>
 	FPS850L			MPC850
 	FPS860L			MPC860
 	ICU862			MPC862
+	IceCube_5100		MGT5100
+	IceCube_5200		MPC5200
 	IP860			MPC860
 	IVML24			MPC860
 	IVML24_128		MPC860
@@ -72,7 +74,6 @@ Wolfgang Denk <wd@denx.de>
 	TQM855L			MPC855
 	TQM860L			MPC860
 	TQM860L_FEC		MPC860
-	TTTech			MPC823
 	c2mon			MPC855
 	hermes			MPC860
 	lwmon			MPC823
@@ -275,6 +276,9 @@ Gary Jennejohn <gj@denx.de>
 	smdk2400		ARM920T
 	trab			ARM920T
 
+Kshitij Gupta <kshitij@ti.com>
+	omap1510inn		ARM925T
+
 David Müller <d.mueller@elsoft.ch>
 
 	smdk2410		ARM920T

MAKEALL

@@ -18,6 +18,14 @@ LIST_5xx="	\
 	cmi_mpc5xx							\
 "
 
+#########################################################################
+## MPC5xxx Systems
+#########################################################################
+
+LIST_5xxx="	\
+	IceCube_5100	IceCube_5200					\
+"
+
 #########################################################################
 ## MPC8xx Systems
 #########################################################################
@@ -36,7 +44,7 @@ LIST_8xx="	\
 	rmu		RPXClassic	RPXlite		RRvision	\
 	SM850		SPD823TS	svm_sc8xx	SXNI855T	\
 	TOP860		TQM823L		TQM823L_LCD	TQM850L		\
-	TQM855L		TQM860L		TTTech		v37		\
+	TQM855L		TQM860L		v37				\
 "
 
 #########################################################################
@@ -45,9 +53,9 @@ LIST_8xx="	\
 
 LIST_4xx="	\
 	ADCIOP		AR405		ASH405          BUBINGA405EP    \
-        CANBT		CPCI405		CPCI4052 	CPCI405AB       \
+	CANBT		CPCI405		CPCI4052 	CPCI405AB       \
 	CPCI440         CPCIISER4	CRAYL1  	DASA_SIM	\
-        DU405    	EBONY           ERIC  		EXBITGEN	\
+	DU405    	EBONY           ERIC  		EXBITGEN	\
 	MIP405  	MIP405T		ML2		OCRTC		\
 	ORSG		PCI405		PIP405		PMC405          \
 	W7OLMC		W7OLMG          WALNUT405			\
@@ -87,7 +95,8 @@ LIST_7xx="	\
 	BAB7xx		ELPPC						\
 "
 
-LIST_ppc="${LIST_5xx}  ${LIST_8xx}  \
+LIST_ppc="${LIST_5xx}  ${LIST_5xxx} \
+	  ${LIST_8xx}  \
 	  ${LIST_824x} ${LIST_8260} \
 	  ${LIST_4xx}		    \
 	  ${LIST_74xx} ${LIST_7xx}"
@@ -108,7 +117,7 @@ LIST_ARM7="ep7312 impa7"
 ## ARM9 Systems
 #########################################################################
 
-LIST_ARM9="at91rm9200dk smdk2400 smdk2410 trab VCMA9"
+LIST_ARM9="at91rm9200dk omap1510inn smdk2400 smdk2410 trab VCMA9"
 
 #########################################################################
 ## Xscale Systems
@@ -159,7 +168,7 @@ build_target() {
 for arg in $@
 do
 	case "$arg" in
-	5xx|8xx|824x|8260|4xx|7xx|74xx|SA|ARM7|ARM9|ppc|arm|pxa|mips|I486|x86)
+	5xx|5xxx|8xx|824x|8260|4xx|7xx|74xx|SA|ARM7|ARM9|ppc|arm|pxa|mips|I486|x86)
 			for target in `eval echo '$LIST_'${arg}`
 			do
 				build_target ${target}

Makefile

@@ -181,6 +181,22 @@ unconfig:
 cmi_mpc5xx_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc5xx cmi
 
+#########################################################################
+## MPC5xxx Systems
+#########################################################################
+IceCube_5200_config	\
+IceCube_5100_config:		unconfig
+	@ >include/config.h
+	@[ -z "$(findstring _5200,$@)" ] || \
+		{ echo "#define CONFIG_MPC5200"		>>include/config.h ; \
+		  echo "... with MPC5200 processor" ; \
+		}
+	@[ -z "$(findstring _5100,$@)" ] || \
+		{ echo "#define CONFIG_MGT5100"		>>include/config.h ; \
+		  echo "... with MGT5100 processor" ; \
+		}
+	@./mkconfig -a IceCube ppc mpc5xxx icecube
+
 #########################################################################
 ## MPC8xx Systems
 #########################################################################
@@ -372,6 +388,7 @@ xtract_8xx = $(subst _66MHz,,$(subst _80MHz,,$(subst _100MHz,,$(subst _LCD,,$(su
 
 FPS850L_config		\
 FPS860L_config		\
+NSCU_config		\
 TQM823L_config		\
 TQM823L_66MHz_config	\
 TQM823L_80MHz_config	\
@@ -390,6 +407,15 @@ TQM860L_80MHz_config	\
 TQM862L_config		\
 TQM862L_66MHz_config	\
 TQM862L_80MHz_config	\
+TQM855M_config		\
+TQM855M_66MHz_config	\
+TQM855M_80MHz_config	\
+TQM860M_config		\
+TQM860M_66MHz_config	\
+TQM860M_80MHz_config	\
+TQM862M_config		\
+TQM862M_66MHz_config	\
+TQM862M_80MHz_config	\
 TQM862M_100MHz_config:	unconfig
 	@ >include/config.h
 	@[ -z "$(findstring _66MHz,$@)" ] || \
@@ -710,11 +736,14 @@ shannon_config	:	unconfig
 	@./mkconfig $(@:_config=) arm sa1100 shannon
 
 #########################################################################
-## ARM920T Systems
+## ARM92xT Systems
 #########################################################################
 
 xtract_trab = $(subst _big_flash,,$(subst _config,,$1))
 
+omap1510inn_config :	unconfig
+	@./mkconfig $(@:_config=) arm arm925t omap1510inn
+
 smdk2400_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm920t smdk2400
 

README

@@ -140,12 +140,14 @@ Directory Hierarchy:
 - tools		Tools to build S-Record or U-Boot images, etc.
 
 - cpu/74xx_7xx	Files specific to Motorola MPC74xx and 7xx CPUs
+- cpu/arm925t	Files specific to ARM	   925	   CPUs
 - cpu/mpc5xx	Files specific to Motorola MPC5xx  CPUs
 - cpu/mpc8xx	Files specific to Motorola MPC8xx  CPUs
 - cpu/mpc824x	Files specific to Motorola MPC824x CPUs
 - cpu/mpc8260	Files specific to Motorola MPC8260 CPU
 - cpu/ppc4xx	Files specific to IBM	   4xx	   CPUs
 
+
 - board/LEOX/   Files specific to boards manufactured by The LEOX team
 - board/LEOX/elpt860	Files specific to ELPT860 boards
 - board/RPXClassic
@@ -204,6 +206,8 @@ Directory Hierarchy:
 - board/mvs1	Files specific to MVS1       boards
 - board/nx823   Files specific to NX823      boards
 - board/oxc	Files specific to OXC        boards
+- board/omap1510inn
+		Files specific to OMAP 1510 Innovator boards
 - board/pcippc2	Files specific to PCIPPC2/PCIPPC6 boards
 - board/pm826	Files specific to PM826      boards
 - board/ppmc8260
@@ -353,6 +357,7 @@ The following options need to be configured:
 
 		CONFIG_HHP_CRADLE,  CONFIG_DNP1110,    CONFIG_EP7312,
 		CONFIG_IMPA7,       CONFIG_LART,       CONFIG_LUBBOCK,
+		CONFIG_INNOVATOROMAP1510,
 		CONFIG_SHANNON,     CONFIG_SMDK2400,   CONFIG_SMDK2410,
 		CONFIG_TRAB,	    CONFIG_AT91RM9200DK
 
@@ -653,6 +658,9 @@ The following options need to be configured:
 		CONFIG_RTC_DS1338	- use Maxim, Inc. DS1338 RTC
 		CONFIG_RTC_DS164x	- use Dallas DS164x RTC
 
+		Note that if the RTC uses I2C, then the I2C interface
+		must also be configured. See I2C Support, below.
+
 - Timestamp Support:
 
 		When CONFIG_TIMESTAMP is selected, the timestamp
@@ -904,29 +912,48 @@ The following options need to be configured:
 
 - I2C Support:	CONFIG_HARD_I2C | CONFIG_SOFT_I2C
 
-		Enables I2C serial bus commands.  If this is selected,
-		either CONFIG_HARD_I2C or CONFIG_SOFT_I2C must be defined
-		to include the appropriate I2C driver.
+		These enable I2C serial bus commands. Defining either of
+		(but not both of) CONFIG_HARD_I2C or CONFIG_SOFT_I2C will
+		include the appropriate I2C driver for the selected cpu.
 
-		See also: common/cmd_i2c.c for a description of the
+		This will allow you to use i2c commands at the u-boot
+		command line (as long as you set CFG_CMD_I2C in
+		CONFIG_COMMANDS) and communicate with i2c based realtime
+		clock chips. See common/cmd_i2c.c for a description of the
 		command line interface.
 
+		CONFIG_HARD_I2C	selects the CPM hardware driver for I2C.
 
-		CONFIG_HARD_I2C
+		CONFIG_SOFT_I2C configures u-boot to use a software (aka
+		bit-banging) driver instead of CPM or similar hardware
+		support for I2C.
 
-		Selects the CPM hardware driver for I2C.
+		There are several other quantities that must also be
+		defined when you define CONFIG_HARD_I2C or CONFIG_SOFT_I2C.
 
-		CONFIG_SOFT_I2C
+		In both cases you will need to define CFG_I2C_SPEED
+		to be the frequency (in Hz) at which you wish your i2c bus
+		to run and CFG_I2C_SLAVE to be the address of this node (ie
+		the cpu's i2c node address).
 
-		Use software (aka bit-banging) driver instead of CPM
-		or similar hardware support for I2C.  This is configured
-		via the following defines.
+		Now, the u-boot i2c code for the mpc8xx (cpu/mpc8xx/i2c.c)
+		sets the cpu up as a master node and so its address should
+		therefore be cleared to 0 (See, eg, MPC823e User's Manual
+		p.16-473). So, set CFG_I2C_SLAVE to 0.
+
+		That's all that's required for CONFIG_HARD_I2C.
+
+		If you use the software i2c interface (CONFIG_SOFT_I2C)
+		then the following macros need to be defined (examples are
+		from include/configs/lwmon.h):
 
 		I2C_INIT
 
-		(Optional). Any commands necessary to enable I2C
+		(Optional). Any commands necessary to enable the I2C
 		controller or configure ports.
 
+		eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |=  PB_SCL)
+
 		I2C_PORT
 
 		(Only for MPC8260 CPU). The I/O port to use (the code
@@ -939,32 +966,49 @@ The following options need to be configured:
 		(driven).  If the data line is open collector, this
 		define can be null.
 
+		eg: #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |=  PB_SDA)
+
 		I2C_TRISTATE
 
 		The code necessary to make the I2C data line tri-stated
 		(inactive).  If the data line is open collector, this
 		define can be null.
 
+		eg: #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
+
 		I2C_READ
 
 		Code that returns TRUE if the I2C data line is high,
 		FALSE if it is low.
 
+		eg: #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+
 		I2C_SDA(bit)
 
 		If <bit> is TRUE, sets the I2C data line high. If it
 		is FALSE, it clears it (low).
 
+		eg: #define I2C_SDA(bit) \
+		         if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+		         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+
 		I2C_SCL(bit)
 
 		If <bit> is TRUE, sets the I2C clock line high. If it
 		is FALSE, it clears it (low).
 
+		eg: #define I2C_SCL(bit) \
+		         if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+		         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+
 		I2C_DELAY
 
 		This delay is invoked four times per clock cycle so this
 		controls the rate of data transfer.  The data rate thus
-		is 1 / (I2C_DELAY * 4).
+		is 1 / (I2C_DELAY * 4). Often defined to be something
+		like:
+
+		#define I2C_DELAY  udelay(2)
 
 		CFG_I2C_INIT_BOARD
 
@@ -1442,6 +1486,16 @@ Configuration Settings:
 - CFG_FLASH_WRITE_TOUT:
 		Timeout for Flash write operations (in ms)
 
+- CFG_FLASH_LOCK_TOUT
+		Timeout for Flash set sector lock bit operation (in ms)
+
+- CFG_FLASH_UNLOCK_TOUT
+		Timeout for Flash clear lock bits operation (in ms)
+
+- CFG_FLASH_PROTECTION
+		If defined, hardware flash sectors protection is used
+		instead of U-Boot software protection.
+
 - CFG_DIRECT_FLASH_TFTP:
 
 		Enable TFTP transfers directly to flash memory;
@@ -1808,7 +1862,7 @@ configurations; the following names are supported:
     GENIETV_config	  TQM823L_config	PIP405_config
     GEN860T_config	  EBONY_config		FPS860L_config
     ELPT860_config	  cmi_mpc5xx_config	NETVIA_config
-    at91rm9200dk_config
+    at91rm9200dk_config	  omap1510inn_config
 
 Note: for some board special configuration names may exist; check  if
       additional  information is available from the board vendor; for
@@ -2999,6 +3053,11 @@ it:
   version of diff does not support these options, then get the latest
   version of GNU diff.
 
+  The current directory when running this command shall be the top
+  level directory of the U-Boot source tree, or it's parent directory
+  (i. e. please make sure that your patch includes sufficient
+  directory information for the affected files).
+
   We accept patches as plain text, MIME attachments or as uuencoded
   gzipped text.
 

board/MAI/AmigaOneG3SE/cmd_boota.c

@@ -121,8 +121,8 @@ int do_boota (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	return 0;
 }
 #if defined(CONFIG_AMIGAONEG3SE) && (CONFIG_COMMANDS & CFG_CMD_BSP)
-cmd_tbl_t U_BOOT_CMD(BOOTA) = MK_CMD_ENTRY(
-	"boota",   3,      1,      do_boota,
+U_BOOT_CMD(
+	boota,   3,      1,      do_boota,
 	"boota   - boot an Amiga kernel\n",
 	"address disk"
 );

board/MAI/menu/cmd_menu.c

@@ -8,8 +8,8 @@ int do_menu( cmd_tbl_t *cmdtp, /*bd_t *bd,*/ int flag, int argc, char *argv[] )
 }
 
 #if defined(CONFIG_AMIGAONEG3SE) && (CONFIG_COMMANDS & CFG_CMD_BSP)
-cmd_tbl_t U_BOOT_CMD(MENU) = MK_CMD_ENTRY(
-	"menu",   1,      1,      do_menu,
+U_BOOT_CMD(
+	menu,   1,      1,      do_menu,
 	"menu    - display BIOS setup menu\n",
 	""
 );

board/RRvision/video_ad7179.h

@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2003 Wolfgang Grandegger <wg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define VIDEO_ENCODER_NAME	"Analog Devices AD7179"
+
+#define VIDEO_ENCODER_I2C_RATE	100000	/* Max rate is 100Khz	*/
+#define VIDEO_ENCODER_CB_Y_CR_Y		/* Use CB Y CR Y format...	*/
+
+#define VIDEO_MODE_YUYV		/* The only mode supported by this encoder	*/
+#undef	VIDEO_MODE_RGB
+#define VIDEO_MODE_BPP		16
+
+#ifdef	VIDEO_MODE_PAL
+#define VIDEO_ACTIVE_COLS	720
+#define VIDEO_ACTIVE_ROWS	576
+#define VIDEO_VISIBLE_COLS	640
+#define VIDEO_VISIBLE_ROWS	480
+#else
+#error "NTSC mode is not supported"
+#endif
+
+static unsigned char video_encoder_data[] = {
+				0x05, /* Mode Register 0 */
+				0x11, /* Mode Register 1 */
+				0x20, /* Mode Register 2 */
+				0x0C, /* Mode Register 3 */
+				0x01, /* Mode Register 4 */
+				0x00, /* Reserved */
+				0x00, /* Reserved */
+				0x04, /* Timing Register 0 */
+				0x00, /* Timing Register 1 */
+				0xCB, /* Subcarrier Frequency Register 0 */
+				0x0A, /* Subcarrier Frequency Register 1 */
+				0x09, /* Subcarrier Frequency Register 2 */
+				0x2A, /* Subcarrier Frequency Register 3 */
+				0x00, /* Subcarrier Phase */
+				0x00, /* Closed Captioning Ext Reg 0 */
+				0x00, /* Closed Captioning Ext Reg 1 */
+				0x00, /* Closed Captioning Reg 0 */
+				0x00, /* Closed Captioning Reg 1 */
+				0x00, /* Pedestal Control Reg 0 */
+				0x00, /* Pedestal Control Reg 1 */
+				0x00, /* Pedestal Control Reg 2 */
+				0x00, /* Pedestal Control Reg 3 */
+				0x00, /* CGMS_WSS Reg 0 */
+				0x00, /* CGMS_WSS Reg 0 */
+				0x00, /* CGMS_WSS Reg 0 */
+				0x00  /* Teletext Req. Control Reg */
+} ;

board/a3000/a3000.c

@@ -2,6 +2,9 @@
  * (C) Copyright 2001
  * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
  *
+ * Modified during 2003 by
+ * Ken Chou, kchou@ieee.org
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -86,52 +89,42 @@ Done:
 /*
  * Initialize PCI Devices
  */
-#if 1
 #ifndef CONFIG_PCI_PNP
 static struct pci_config_table pci_a3000_config_table[] = {
-	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-	  0x0, 0x0, 0x0, /* unknown eth0 divice */
+	/* vendor, device, class */
+	/* bus, dev, func */
+	{ PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815, PCI_ANY_ID,
+	  PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,	/* dp83815 eth0 divice */
 	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
 				       PCI_ENET0_MEMADDR,
 				       PCI_COMMAND_IO |
 				       PCI_COMMAND_MEMORY |
 				       PCI_COMMAND_MASTER }},
 	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-	  0x0, 0x0, 0x0, /* unknown eth1 device */
+	  PCI_ANY_ID, 0x14, PCI_ANY_ID,		/* PCI slot1 */
 	  pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
 				       PCI_ENET1_MEMADDR,
 				       PCI_COMMAND_IO |
 				       PCI_COMMAND_MEMORY |
 				       PCI_COMMAND_MASTER }},
 	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-	  0x0, 0x0, 0x0, /* unknown eth1 device */
+	  PCI_ANY_ID, 0x15, PCI_ANY_ID, 	/* PCI slot2 */
 	  pci_cfgfunc_config_device, { PCI_ENET2_IOADDR,
 				       PCI_ENET2_MEMADDR,
 				       PCI_COMMAND_IO |
 				       PCI_COMMAND_MEMORY |
 				       PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	  PCI_ANY_ID, 0x16, PCI_ANY_ID,		/* PCI slot3 */
+	  pci_cfgfunc_config_device, { PCI_ENET3_IOADDR,
+				       PCI_ENET3_MEMADDR,
+				       PCI_COMMAND_IO |
+				       PCI_COMMAND_MEMORY |
+				       PCI_COMMAND_MASTER }},
 	{ }
 };
 #endif
 
-#else
-
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_a3000_config_table[] = {
-	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
-	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
-				       PCI_ENET0_MEMADDR,
-				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
-	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
-	  pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
-				       PCI_ENET1_MEMADDR,
-				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
-	{ }
-};
-#endif
-
-#endif
-
 struct pci_controller hose = {
 #ifndef CONFIG_PCI_PNP
 	config_table: pci_a3000_config_table,

board/esd/ar405/fpgadata.c

@@ -8,7 +8,7 @@
  0x03,0x07,0x02,0x09,0x04,0x04,0x04,0x04,0x0e,0x04,0x04,0x09,0x03,0x07,0x02,0x04,
  0x03,0x03,0x03,0x07,0xe5,0x01,0x0d,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,
  0x19,0x03,0x02,0x02,0x03,0x02,0x08,0x09,0x07,0x13,0x03,0x11,0x02,0x06,0x03,0x05,
- 0x03,0x05,0x11,0x1d,0x1f,0x13,0x10,0x01,0x01,0xe2,0x4c,0xe5,0x01,0x0a,0x04,0x01,
+ 0x03,0x05,0x11,0x1d,0x1f,0x13,0x10,0x01,0x01,0xe3,0x4c,0xe5,0x01,0x0a,0x04,0x01,
  0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x09,0x04,0x04,0x02,0x06,0x01,0xe5,0x05,
  0x01,0x02,0x04,0x04,0x04,0x09,0x09,0x09,0x09,0x04,0x06,0x01,0x07,0x09,0x04,0x04,
  0x09,0x06,0x02,0x09,0x09,0x04,0x01,0xe7,0x03,0x04,0x07,0xe6,0x08,0x09,0x09,0x0e,
@@ -16,7 +16,7 @@
  0x03,0x05,0xe5,0x07,0xe5,0x01,0x05,0x0b,0xe5,0x07,0xe5,0x07,0x09,0x03,0x05,0xe6,
  0xe5,0x04,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,0xe6,0x04,0x03,0x05,0xe5,0xe6,0x04,
  0xe5,0x07,0x03,0x05,0xe5,0x07,0x0b,0x01,0x0e,0x05,0x03,0x05,0x03,0x05,0x1d,0x03,
- 0x05,0x03,0x44,0xe5,0xe5,0x2e,0x1c,0x01,0x13,0x32,0x01,0xe2,0x4d,0xe5,0x0f,0x09,
+ 0x05,0x03,0x44,0xe5,0xe5,0x2e,0x1c,0x01,0x13,0x32,0x01,0xe3,0x4d,0xe5,0x0f,0x09,
  0x09,0x27,0x09,0x42,0x04,0x4a,0x44,0x01,0x01,0x01,0x12,0x09,0x09,0x01,0x06,0x01,
  0x12,0x09,0x0a,0x09,0x11,0x21,0x13,0x11,0x15,0x1d,0x1b,0x0c,0x0d,0x03,0x03,0x01,
  0x31,0x31,0x47,0x81,0xe5,0xe5,0xe5,0x77,0x3e,0xe5,0x19,0xe5,0x1b,0x3b,0xe5,0xe5,
@@ -2727,10 +2727,10 @@
  0x01,0x03,0x03,0x05,0x03,0x09,0xe5,0x07,0x09,0x09,0x01,0x07,0x09,0x07,0x01,0x09,
  0x09,0x0d,0x01,0x01,0x04,0x27,0x39,0x25,0x09,0x0b,0x09,0x09,0x02,0xe5,0x0e,0x02,
  0x07,0x0b,0x1d,0x2e,0xe5,0xe6,0x50,0xe5,0x1b,0x13,0x04,0x04,0x04,0x06,0x04,0x09,
- 0x04,0x04,0x13,0x0e,0x13,0x1d,0x27,0xe7,0x21,0xc6,0x40,0x03,0x03,0x07,0xe2,0x09,
+ 0x04,0x04,0x13,0x0e,0x13,0x1d,0x27,0xe7,0x21,0xc6,0x40,0x03,0x03,0x07,0xe3,0x09,
  0x3a,0x03,0x07,0x29,0x1f,0x25,0x0b,0x3b,0x15,0xe5,0x2d,0x01,0x27,0xe7,0x6e,0x16,
  0x05,0xe5,0x01,0x05,0x02,0x02,0x05,0x03,0x05,0xe5,0x01,0x05,0x0d,0x05,0x5c,0x06,
- 0x01,0x01,0x05,0x93,0x59,0x34,0x05,0xe5,0x01,0x04,0xe5,0xe2,0x34,0x10,0x02,0xe5,
+ 0x01,0x01,0x05,0x93,0x59,0x34,0x05,0xe5,0x01,0x04,0xe5,0xe3,0x34,0x10,0x02,0xe5,
  0x13,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0b,0x09,
  0x09,0x09,0x09,0x09,0x09,0x09,0x09,0xe6,0x06,0x09,0x09,0x09,0x03,0x05,0x0a,0xe5,
  0xe5,0x04,0x09,0x08,0xe5,0x07,0xe5,0x08,0x08,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
@@ -2747,4 +2747,4 @@
  0x05,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x01,0x07,0x03,0x02,0x02,0x02,0x04,
  0x02,0x01,0x04,0x02,0x01,0x02,0x01,0x02,0x01,0x01,0xe5,0x05,0x04,0x03,0x07,0xe5,
  0xe5,0x03,0x04,0x04,0x0b,0x02,0xe5,0x01,0xe5,0x01,0xe5,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

board/esd/ash405/ash405.c

@@ -67,7 +67,7 @@ int board_pre_init (void)
 	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
 	mtdcr(uicer, 0x00000000);       /* disable all ints */
 	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-	mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
+	mtdcr(uicpr, 0xFFFFFF9F);       /* set int polarities */
 	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
 	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
 	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */

board/esd/dasa_sim/cmd_dasa_sim.c

@@ -225,8 +225,8 @@ int do_pci9054 (cmd_tbl_t * cmdtp, int flag, int argc,
 
 }
 
-cmd_tbl_t U_BOOT_CMD (pci9054) = MK_CMD_ENTRY(
-	"pci9054", 3, 1, do_pci9054,
+U_BOOT_CMD(
+	pci9054, 3, 1, do_pci9054,
 	"pci9054 - PLX PCI9054 EEPROM access\n",
 	"pci9054 info - print EEPROM values\n"
 	"pci9054 update - updates EEPROM with default values\n"

board/esd/ocrtc/Makefile

@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= lib$(BOARD).a
 
-OBJS	= $(BOARD).o flash.o
+OBJS	= $(BOARD).o flash.o cmd_ocrtc.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS)

board/esd/ocrtc/cmd_ocrtc.c

@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <405gp_pci.h>
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+
+#define IBM_VENDOR_ID    0x1014
+#define PPC405_DEVICE_ID 0x0156
+
+
+/*
+ * Set device number on pci board
+ */
+int do_setdevice(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	int idx = 1;	  /* start at 1 (skip device 0) */
+	pci_dev_t bdf = 0;
+	u32 addr;
+
+	while (bdf >= 0) {
+		if ((bdf = pci_find_device(IBM_VENDOR_ID, PPC405_DEVICE_ID, idx++)) < 0) {
+			break;
+		}
+		printf("Found device nr %d at %x!\n", idx-1, bdf);
+		pci_read_config_dword(bdf, PCI_BASE_ADDRESS_1, &addr);
+		addr &= ~0xf;
+		*(u32 *)addr = (bdf & 0x0000f800) >> 11;
+		printf("Wrote %x at %x!\n", (bdf & 0x0000f800) >> 11, addr);
+	}
+
+	return 0;
+}
+U_BOOT_CMD(
+	setdevice,	1,	1,	do_setdevice,
+	"setdevice - Set device number on pci adapter boards\n",
+	NULL
+);
+
+
+/*
+ * Get device number on pci board
+ */
+int do_getdevice(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	u32 device;
+	char str[32];
+
+	device = *(u32 *)0x0;
+	device = 0x16 - device;      /* calculate vxworks bp slot id */
+	sprintf(str, "%d", device);
+	setenv("slot", str);
+	printf("Variabel slot set to %x\n", device);
+
+	return 0;
+}
+U_BOOT_CMD(
+	getdevice,	1,	1,	do_getdevice,
+	"getdevice - Get device number and set slot env variable\n",
+	NULL
+);
+
+#endif

board/evb64260/eth.c

@@ -22,7 +22,6 @@ Skeleton NIC driver for Etherboot
 
 #include <common.h>
 #include <malloc.h>
-#include <cmd_bsp.h>
 #include <galileo/gt64260R.h>
 #include <galileo/core.h>
 #include <asm/cache.h>

board/evb64260/zuma_pbb.c

@@ -198,20 +198,20 @@ do_zuma_init_mbox (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return 0;
 }
 
-cmd_tbl_t U_BOOT_CMD(zuma_init_pbb) = MK_CMD_ENTRY(
-	"zinit",	 1,	 0,	 do_zuma_init_pbb,
+U_BOOT_CMD(
+	zinit,	 1,	 0,	 do_zuma_init_pbb,
 	"zinit   - init zuma pbb\n",
 	"\n"
 	"    - init zuma pbb\n"
 );
-cmd_tbl_t U_BOOT_CMD(zuma_test_dma) = MK_CMD_ENTRY(
-	"zdtest",	  3,	  1,	  do_zuma_test_dma,
+U_BOOT_CMD(
+	zdtest,	  3,	  1,	  do_zuma_test_dma,
 	"zdtest  - run dma test\n",
 	"[cmd [count]]\n"
 	"    - run dma cmd (w=0,v=1,cp=2,cmp=3,wi=4,vi=5), count bytes\n"
 );
-cmd_tbl_t U_BOOT_CMD(zuma_init_mbox) = MK_CMD_ENTRY(
-	"zminit",	  1,	  0,	  do_zuma_init_mbox,
+U_BOOT_CMD(
+	zminit,	  1,	  0,	  do_zuma_init_mbox,
 	"zminit  - init zuma mbox\n",
 	"\n"
 	"    - init zuma mbox\n"

board/exbitgen/flash.c

@@ -217,7 +217,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 	short i;
 	FLASH_WORD_SIZE value;
 	ulong base = (ulong)addr;
-        volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
 
 	/* Write auto select command: read Manufacturer ID */
 	addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
@@ -247,7 +247,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 
 	switch (value) {
 	case (FLASH_WORD_SIZE)AMD_ID_F040B:
-	        info->flash_id += FLASH_AM040;
+		info->flash_id += FLASH_AM040;
 		info->sector_count = 8;
 		info->size = 0x0080000; /* => 512 ko */
 		break;
@@ -335,14 +335,14 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 	}
 
 	/* set up sector start address table */
-        if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
 		(info->flash_id  == FLASH_AM040) ||
 		(info->flash_id == FLASH_AMDLV033C) ||
 		(info->flash_id == FLASH_AMDLV065D)) {
 		ulong sectsize = info->size / info->sector_count;
 		for (i = 0; i < info->sector_count; i++)
 			info->start[i] = base + (i * sectsize);
-        } else {
+	} else {
 	    if (info->flash_id & FLASH_BTYPE) {
 		/* set sector offsets for bottom boot block type	*/
 		info->start[0] = base + 0x00000000;
@@ -370,9 +370,9 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		/* D0 = 1 if protected */
 
 		addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
-                if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
 			info->protect[i] = 0;
-                else
+		else
 			info->protect[i] = addr2[2] & 1;
 	}
 
@@ -450,7 +450,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
 			while ((addr2[0] & 0x00800080) !=
 				(FLASH_WORD_SIZE) 0x00800080) {
 				if ((now=get_timer(start)) >
-				           CFG_FLASH_ERASE_TOUT) {
+					   CFG_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					addr[0] = (FLASH_WORD_SIZE)0x00F000F0;
 					return 1;
@@ -551,12 +551,12 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
  */
 static int write_word (flash_info_t *info, ulong dest, ulong data)
 {
-        volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]);
-        volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest;
-        volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]);
+	volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
 	ulong start;
 	int flag;
-        int i;
+	int i;
 
 	/* Check if Flash is (sufficiently) erased */
 	if ((*((volatile ulong *)dest) & data) != data) {
@@ -565,7 +565,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
 		return 2;
 	}
 
-        for (i=0; i < 4/sizeof(FLASH_WORD_SIZE); i++) {
+	for (i=0; i < 4/sizeof(FLASH_WORD_SIZE); i++) {
 		/* Disable interrupts which might cause a timeout here */
 		flag = disable_interrupts();
 

board/exbitgen/init.S

@@ -34,7 +34,7 @@
 #include <asm/mmu.h>
 
 #include "exbitgen.h"
-		
+
 /* IIC declarations (This is an extract from 405gp_i2c.h, which also contains some */
 /* c-code declarations and consequently can't be included here). */
 /* (Possibly to be solved somehow else). */
@@ -100,25 +100,25 @@
 #define TIMEBASE_10PS (1000000000 / CONFIG_SYS_CLK_FREQ) * 100
 
 #define FLASH_8bit_AP   0x9B015480
-#define FLASH_8bit_CR   0xFFF18000 /* 1MB(min), 8bit, R/W */ 
+#define FLASH_8bit_CR   0xFFF18000 /* 1MB(min), 8bit, R/W */
 
 #define FLASH_32bit_AP  0x9B015480
 #define FLASH_32bit_CR  0xFFE3C000 /* 2MB, 32bit, R/W */
 
 
 #define WDCR_EBC(reg,val) addi    r4,0,reg;\
-        mtdcr   ebccfga,r4;\
-        addis   r4,0,val@h;\
-        ori     r4,r4,val@l;\
-        mtdcr   ebccfgd,r4
+	mtdcr   ebccfga,r4;\
+	addis   r4,0,val@h;\
+	ori     r4,r4,val@l;\
+	mtdcr   ebccfgd,r4
 
 /*---------------------------------------------------------------------
  * Function:     ext_bus_cntlr_init
- * Description:  Initializes the External Bus Controller for the external 
- *		peripherals. IMPORTANT: For pass1 this code must run from 
+ * Description:  Initializes the External Bus Controller for the external
+ *		peripherals. IMPORTANT: For pass1 this code must run from
  *		cache since you can not reliably change a peripheral banks
  *		timing register (pbxap) while running code from that bank.
- *		For ex., since we are running from ROM on bank 0, we can NOT 
+ *		For ex., since we are running from ROM on bank 0, we can NOT
  *		execute the code that modifies bank 0 timings from ROM, so
  *		we run it from cache.
  *	Bank 0 - Boot flash
@@ -126,63 +126,63 @@
  *	Bank 5 - CPLD
  *	Bank 6 - not used
  *	Bank 7 - Heathrow chip
- *---------------------------------------------------------------------	
+ *---------------------------------------------------------------------
  */
-     	.globl	ext_bus_cntlr_init
+	.globl	ext_bus_cntlr_init
 ext_bus_cntlr_init:
-        mflr    r4                      /* save link register */
-        bl      ..getAddr
+	mflr    r4                      /* save link register */
+	bl      ..getAddr
 ..getAddr:
-        mflr    r3                      /* get address of ..getAddr */
-        mtlr    r4                      /* restore link register */
-        addi    r4,0,14                 /* set ctr to 10; used to prefetch */
-        mtctr   r4                      /* 10 cache lines to fit this function */
-                                        /* in cache (gives us 8x10=80 instrctns) */
+	mflr    r3                      /* get address of ..getAddr */
+	mtlr    r4                      /* restore link register */
+	addi    r4,0,14                 /* set ctr to 10; used to prefetch */
+	mtctr   r4                      /* 10 cache lines to fit this function */
+					/* in cache (gives us 8x10=80 instrctns) */
 ..ebcloop:
-        icbt    r0,r3                   /* prefetch cache line for addr in r3 */
-        addi    r3,r3,32		/* move to next cache line */
-        bdnz    ..ebcloop               /* continue for 10 cache lines */
+	icbt    r0,r3                   /* prefetch cache line for addr in r3 */
+	addi    r3,r3,32		/* move to next cache line */
+	bdnz    ..ebcloop               /* continue for 10 cache lines */
 
 	mflr	r31			/* save link register */
-	
-        /*-----------------------------------------------------------
-         * Delay to ensure all accesses to ROM are complete before changing
+
+	/*-----------------------------------------------------------
+	 * Delay to ensure all accesses to ROM are complete before changing
 	 * bank 0 timings. 200usec should be enough.
-         *   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
-         *-----------------------------------------------------------
+	 *   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
+	 *-----------------------------------------------------------
 	 */
 
 	addis	r3,0,0x0
-        ori     r3,r3,0xA000          /* ensure 200usec have passed since reset */
-        mtctr   r3
+	ori     r3,r3,0xA000          /* ensure 200usec have passed since reset */
+	mtctr   r3
 ..spinlp:
-        bdnz    ..spinlp                /* spin loop */
+	bdnz    ..spinlp                /* spin loop */
 
-        /*---------------------------------------------------------------
-         * Memory Bank 0 (Boot Flash) initialization
-         *---------------------------------------------------------------
+	/*---------------------------------------------------------------
+	 * Memory Bank 0 (Boot Flash) initialization
+	 *---------------------------------------------------------------
 	 */
 	WDCR_EBC(pb0ap, FLASH_32bit_AP)
 	WDCR_EBC(pb0cr, 0xffe38000)
 /*pnc	WDCR_EBC(pb0cr, FLASH_32bit_CR) */
-	
-        /*---------------------------------------------------------------
-         * Memory Bank 5 (CPLD) initialization
-         *---------------------------------------------------------------
+
+	/*---------------------------------------------------------------
+	 * Memory Bank 5 (CPLD) initialization
+	 *---------------------------------------------------------------
 	 */
 	WDCR_EBC(pb5ap, 0x01010040)
 /*jsa recommendation:		WDCR_EBC(pb5ap, 0x00010040) */
 	WDCR_EBC(pb5cr, 0x10038000)
 
-        /*--------------------------------------------------------------- */
-        /* Memory Bank 6 (not used) initialization */
-        /*--------------------------------------------------------------- */
+	/*--------------------------------------------------------------- */
+	/* Memory Bank 6 (not used) initialization */
+	/*--------------------------------------------------------------- */
 	WDCR_EBC(pb6cr, 0x00000000)
 
 	/* Read HW ID to determine whether old H2 board or new generic CPU board */
 	addis	r3, 0,  HW_ID_ADDR@h
 	ori	r3, r3, HW_ID_ADDR@l
-        lbz     r3,0x0000(r3)
+	lbz     r3,0x0000(r3)
 	cmpi	0, r3, 1          /* if (HW_ID==1) */
 	beq 	setup_h2evalboard /* then jump */
 	cmpi	0, r3, 2          /* if (HW_ID==2) */
@@ -191,9 +191,9 @@ ext_bus_cntlr_init:
 	beq 	setup_genieboard  /* then jump */
 
 setup_genieboard:
-        /*--------------------------------------------------------------- */
-        /* Memory Bank 1 (Application Flash) initialization for generic CPU board */
-        /*--------------------------------------------------------------- */
+	/*--------------------------------------------------------------- */
+	/* Memory Bank 1 (Application Flash) initialization for generic CPU board */
+	/*--------------------------------------------------------------- */
 /*	WDCR_EBC(pb1ap, 0x7b015480)	/###* T.B.M. */
 /*	WDCR_EBC(pb1ap, 0x7F8FFE80)	/###* T.B.M. */
 	WDCR_EBC(pb1ap, 0x9b015480)	/* hlb-20020207: burst 8 bit 6 cycles  */
@@ -201,68 +201,68 @@ setup_genieboard:
 /*	WDCR_EBC(pb1cr, 0x20098000)	/###* 16 MB */
 	WDCR_EBC(pb1cr, 0x200B8000)	/* 32 MB */
 
-        /*--------------------------------------------------------------- */
-        /* Memory Bank 4 (Onboard FPGA) initialization for generic CPU board */
-        /*--------------------------------------------------------------- */
+	/*--------------------------------------------------------------- */
+	/* Memory Bank 4 (Onboard FPGA) initialization for generic CPU board */
+	/*--------------------------------------------------------------- */
 	WDCR_EBC(pb4ap, 0x01010000)	/*  */
 	WDCR_EBC(pb4cr, 0x1021c000)	/*  */
 
-        /*--------------------------------------------------------------- */
-        /* Memory Bank 7 (Heathrow chip on Reference board) initialization */
-        /*--------------------------------------------------------------- */
+	/*--------------------------------------------------------------- */
+	/* Memory Bank 7 (Heathrow chip on Reference board) initialization */
+	/*--------------------------------------------------------------- */
 	WDCR_EBC(pb7ap, 0x200ffe80)	/* No Ready, many wait states (let reflections die out) */
 	WDCR_EBC(pb7cr, 0X4001A000)
 
 	bl	setup_continue
 
-	
+
 setup_h2evalboard:
-        /*--------------------------------------------------------------- */
-        /* Memory Bank 1 (Application Flash) initialization */
-        /*--------------------------------------------------------------- */
+	/*--------------------------------------------------------------- */
+	/* Memory Bank 1 (Application Flash) initialization */
+	/*--------------------------------------------------------------- */
 	WDCR_EBC(pb1ap, 0x7b015480)	/* T.B.M. */
 /*3010	WDCR_EBC(pb1ap, 0x7F8FFE80)	/###* T.B.M. */
-	WDCR_EBC(pb1cr, 0x20058000) 
-
-        /*--------------------------------------------------------------- */
-        /* Memory Bank 2 (Application Flash) initialization */
-        /*--------------------------------------------------------------- */
-	WDCR_EBC(pb2ap, 0x7b015480)	/* T.B.M. */
-/*3010	WDCR_EBC(pb2ap, 0x7F8FFE80)	/###* T.B.M. */
-	WDCR_EBC(pb2cr, 0x20458000) 
+	WDCR_EBC(pb1cr, 0x20058000)
 
 	/*--------------------------------------------------------------- */
-        /* Memory Bank 3 (Application Flash) initialization */
-        /*--------------------------------------------------------------- */
+	/* Memory Bank 2 (Application Flash) initialization */
+	/*--------------------------------------------------------------- */
+	WDCR_EBC(pb2ap, 0x7b015480)	/* T.B.M. */
+/*3010	WDCR_EBC(pb2ap, 0x7F8FFE80)	/###* T.B.M. */
+	WDCR_EBC(pb2cr, 0x20458000)
+
+	/*--------------------------------------------------------------- */
+	/* Memory Bank 3 (Application Flash) initialization */
+	/*--------------------------------------------------------------- */
 	WDCR_EBC(pb3ap, 0x7b015480)	/* T.B.M. */
 /*3010	WDCR_EBC(pb3ap, 0x7F8FFE80)	/###* T.B.M. */
-	WDCR_EBC(pb3cr, 0x20858000) 
+	WDCR_EBC(pb3cr, 0x20858000)
 
-        /*--------------------------------------------------------------- */
-        /* Memory Bank 4 (Application Flash) initialization */
-        /*--------------------------------------------------------------- */
+	/*--------------------------------------------------------------- */
+	/* Memory Bank 4 (Application Flash) initialization */
+	/*--------------------------------------------------------------- */
 	WDCR_EBC(pb4ap, 0x7b015480)	/* T.B.M. */
 /*3010	WDCR_EBC(pb4ap, 0x7F8FFE80)	/###* T.B.M. */
 	WDCR_EBC(pb4cr, 0x20C58000)
 
-        /*--------------------------------------------------------------- */
-        /* Memory Bank 7 (Heathrow chip) initialization */
-        /*--------------------------------------------------------------- */
+	/*--------------------------------------------------------------- */
+	/* Memory Bank 7 (Heathrow chip) initialization */
+	/*--------------------------------------------------------------- */
 	WDCR_EBC(pb7ap, 0x02000280)	/* No Ready, 4 wait states */
 	WDCR_EBC(pb7cr, 0X4001A000)
 
 setup_continue:
 
-	
-        mtlr    r31                     /* restore lr	 */
+
+	mtlr    r31                     /* restore lr	 */
 	nop				/* pass2 DCR errata #8 */
-        blr
+	blr
 
 /*--------------------------------------------------------------------- */
 /* Function:     sdram_init */
 /* Description:  Configures SDRAM memory banks. */
 /*--------------------------------------------------------------------- */
-        .globl  sdram_init
+	.globl  sdram_init
 
 sdram_init:
 #if CFG_MONITOR_BASE < CFG_FLASH_BASE
@@ -377,12 +377,12 @@ sdram_init:
 	subf	r5, r6, r17
 	or	r4, r4, r5
 
-        /*----------------------------------------------------------- */
-        /* Set SDTR1  */
-        /*----------------------------------------------------------- */
-        addi    r5,0,mem_sdtr1
-        mtdcr   memcfga,r5
-        mtdcr   memcfgd,r4
+	/*----------------------------------------------------------- */
+	/* Set SDTR1  */
+	/*----------------------------------------------------------- */
+	addi    r5,0,mem_sdtr1
+	mtdcr   memcfga,r5
+	mtdcr   memcfgd,r4
 
 	/*----------------------------------------------------------- */
 	/* */
@@ -444,36 +444,36 @@ b1skip:	addi    r7,0,mem_mb2cf
 	addi    r7,0,mem_mb3cf
 	mtdcr   memcfga,r7
 	mtdcr   memcfgd,r6
-b3skip:	
+b3skip:
 
-        /*----------------------------------------------------------- */
-        /* Set RTR */
-        /*----------------------------------------------------------- */
+	/*----------------------------------------------------------- */
+	/* Set RTR */
+	/*----------------------------------------------------------- */
 	cmpi	0, r30, 1600
 	bge	rtr_1
-        addis   r7, 0, 0x05F0	/* RTR value for 100Mhz */
+	addis   r7, 0, 0x05F0	/* RTR value for 100Mhz */
 	bl	rtr_2
 rtr_1:	addis	r7, 0, 0x03F8
 rtr_2:	addi    r4,0,mem_rtr
 	mtdcr   memcfga,r4
 	mtdcr   memcfgd,r7
 
-        /*----------------------------------------------------------- */
-        /* Delay to ensure 200usec have elapsed since reset. Assume worst */
-        /* case that the core is running 200Mhz: */
-        /*   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
-        /*----------------------------------------------------------- */
-        addis   r3,0,0x0000
-        ori     r3,r3,0xA000          /* ensure 200usec have passed since reset */
-        mtctr   r3
+	/*----------------------------------------------------------- */
+	/* Delay to ensure 200usec have elapsed since reset. Assume worst */
+	/* case that the core is running 200Mhz: */
+	/*   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
+	/*----------------------------------------------------------- */
+	addis   r3,0,0x0000
+	ori     r3,r3,0xA000          /* ensure 200usec have passed since reset */
+	mtctr   r3
 ..spinlp2:
-        bdnz    ..spinlp2               /* spin loop */
+	bdnz    ..spinlp2               /* spin loop */
 
-        /*----------------------------------------------------------- */
-        /* Set memory controller options reg, MCOPT1. */
+	/*----------------------------------------------------------- */
+	/* Set memory controller options reg, MCOPT1. */
 	/* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst  */
 	/* read/prefetch. */
-        /*----------------------------------------------------------- */
+	/*----------------------------------------------------------- */
 	addi    r4,0,mem_mcopt1
 	mtdcr   memcfga,r4
 	addis   r4,0,0x80C0             /* set DC_EN=1 */
@@ -481,13 +481,13 @@ rtr_2:	addi    r4,0,mem_rtr
 	mtdcr   memcfgd,r4
 
 
-        /*----------------------------------------------------------- */
-        /* Delay to ensure 10msec have elapsed since reset. This is */
-        /* required for the MPC952 to stabalize. Assume worst */
-        /* case that the core is running 200Mhz: */
-        /*   200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles */
-        /* This delay should occur before accessing SDRAM. */
-        /*----------------------------------------------------------- */
+	/*----------------------------------------------------------- */
+	/* Delay to ensure 10msec have elapsed since reset. This is */
+	/* required for the MPC952 to stabalize. Assume worst */
+	/* case that the core is running 200Mhz: */
+	/*   200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles */
+	/* This delay should occur before accessing SDRAM. */
+	/*----------------------------------------------------------- */
 	addis   r3,0,0x001E
 	ori     r3,r3,0x8480          /* ensure 10msec have passed since reset */
 	mtctr   r3
@@ -501,8 +501,8 @@ rtr_2:	addi    r4,0,mem_rtr
 	stb	r4,0(r5)
 	eieio
 
-        mtlr    r31                     /* restore lr */
-        blr
+	mtlr    r31                     /* restore lr */
+	blr
 
 /*--------------------------------------------------------------------- */
 /* Function:    read_spd */
@@ -512,21 +512,21 @@ rtr_2:	addi    r4,0,mem_rtr
 
 #define WRITE_I2C(reg,val) \
 	addi    r3,0,val;\
-        addis   r4, 0, 0xef60;\
-        ori     r4, r4, 0x0500 + reg;\
-        stb     r3, 0(r4);\
-        eieio
+	addis   r4, 0, 0xef60;\
+	ori     r4, r4, 0x0500 + reg;\
+	stb     r3, 0(r4);\
+	eieio
 
 #define READ_I2C(reg) \
-        addis   r3, 0, 0xef60;\
-        ori     r3, r3, 0x0500 + reg;\
-        lbz     r3, 0x0000(r3);\
-        eieio
+	addis   r3, 0, 0xef60;\
+	ori     r3, r3, 0x0500 + reg;\
+	lbz     r3, 0x0000(r3);\
+	eieio
 
 read_spd:
 
 	mflr	r5
-	
+
 	/* Initialize i2c */
 	/*--------------- */
 	WRITE_I2C(IICLMADR, 0x00)	/* clear lo master address */
@@ -558,9 +558,9 @@ read_spd:
 
 	/* Wait a little */
 	/*-------------- */
-        addis   r3,0,0x0000
-        ori     r3,r3,0xA000
-        mtctr   r3
+	addis   r3,0,0x0000
+	ori     r3,r3,0xA000
+	mtctr   r3
 in02:	bdnz    in02
 
 	/* Issue write command */
@@ -572,12 +572,12 @@ in02:	bdnz    in02
 	/*--------------- */
 	addi	r7, 0, 0	/* byte counter in r7 */
 	addi	r8, 0, 0	/* checksum in r8 */
-rdlp:	
+rdlp:
 	/* issue read command */
 	/*------------------- */
 	cmpi	0, r7, 127
 	blt	rd01
-	WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_PT) 
+	WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_PT)
 	bl	rd02
 rd01:	WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_CHT | IIC_CNTL_PT)
 rd02:	bl	wait_i2c_transfer_done
@@ -585,46 +585,46 @@ rd02:	bl	wait_i2c_transfer_done
 	/* Fetch byte from buffer */
 	/*----------------------- */
 	READ_I2C(IICMDBUF)
-	
+
 	/* Retrieve parameters that are going to be used during configuration. */
 	/* Save them in dedicated registers. */
 	/*------------------------------------------------------------ */
 	cmpi	0, r7, 3	/* Save byte 3 in r10 */
 	bne	rd10
-	addi	r10, r3, 0	
+	addi	r10, r3, 0
 rd10:	cmpi	0, r7, 4	/* Save byte 4 in r11 */
 	bne	rd11
-	addi	r11, r3, 0	
+	addi	r11, r3, 0
 rd11:	cmpi	0, r7, 5	/* Save byte 5 in r12 */
 	bne	rd12
-	addi	r12, r3, 0	
+	addi	r12, r3, 0
 rd12:	cmpi	0, r7, 17	/* Save byte 17 in r13 */
 	bne	rd13
-	addi	r13, r3, 0	
+	addi	r13, r3, 0
 rd13:	cmpi	0, r7, 18	/* Save byte 18 in r14 */
 	bne	rd14
-	addi	r14, r3, 0	
+	addi	r14, r3, 0
 rd14:	cmpi	0, r7, 31	/* Save byte 31 in r15 */
 	bne	rd15
-	addi	r15, r3, 0	
+	addi	r15, r3, 0
 rd15:	cmpi	0, r7, 27	/* Save byte 27 in r16 */
 	bne	rd16
-	addi	r16, r3, 0	
+	addi	r16, r3, 0
 rd16:	cmpi	0, r7, 29	/* Save byte 29 in r17 */
 	bne	rd17
-	addi	r17, r3, 0	
+	addi	r17, r3, 0
 rd17:	cmpi	0, r7, 30	/* Save byte 30 in r18 */
 	bne	rd18
-	addi	r18, r3, 0	
+	addi	r18, r3, 0
 rd18:	cmpi	0, r7, 9	/* Save byte 9 in r19 */
 	bne	rd19
-	addi	r19, r3, 0	
+	addi	r19, r3, 0
 rd19:	cmpi	0, r7, 23	/* Save byte 23 in r20 */
 	bne	rd20
-	addi	r20, r3, 0	
+	addi	r20, r3, 0
 rd20:	cmpi	0, r7, 25	/* Save byte 25 in r21 */
 	bne	rd21
-	addi	r21, r3, 0	
+	addi	r21, r3, 0
 rd21:
 
 	/* Calculate checksum of the first 63 bytes */
@@ -647,16 +647,16 @@ rd30:	andi.	r8, r8, 0xff		/* use only 8 bits */
 	eieio
 rderr:	bl	rderr
 
-rd31:	
-	
+rd31:
+
 	/* Increment byte counter and check whether all bytes have been read. */
 	/*------------------------------------------------------------------- */
 	addi	r7, r7, 1
 	cmpi	0, r7, 127
 	bgt	rd05
 	bl	rdlp
-rd05:	
-        mtlr    r5                     /* restore lr */
+rd05:
+	mtlr    r5                     /* restore lr */
 	blr
 
 wait_i2c_transfer_done:
@@ -664,8 +664,8 @@ wait_i2c_transfer_done:
 wt01:	READ_I2C(IICSTS)
 	andi.	r4, r3, IIC_STS_PT
 	cmpi	0, r4, IIC_STS_PT
-	beq	wt01	
-        mtlr    r6                     /* restore lr */
+	beq	wt01
+	mtlr    r6                     /* restore lr */
 	blr
 
 /*--------------------------------------------------------------------- */
@@ -696,7 +696,7 @@ fm01:	cmpi	0, r10, 11
 	cmpi	0, r13, 2
 	bne	fm02
 	addi	r3, 0, 1
-	bl	fmfound	
+	bl	fmfound
 
 fm02:	cmpi	0, r10, 12
 	bne	fm03
@@ -815,7 +815,7 @@ fm14:	cmpi	0, r10, 13
 	addi	r3, 0, 7
 	bl	fmfound
 
-fm15:	
+fm15:
 	/* not found, error code to be issued on LEDs */
 	addi	r7, 0, LED_SDRAM_CODE_2
 	addis	r6, 0, 0x1000
@@ -827,7 +827,7 @@ fmerr:	bl	fmerr
 fmfound:addi	r6, 0, 1
 	subf	r3, r6, r3
 
-        mtlr    r5                     /* restore lr */
+	mtlr    r5                     /* restore lr */
 	blr
 
 /*--------------------------------------------------------------------- */
@@ -838,13 +838,13 @@ fmfound:addi	r6, 0, 1
 find_size_code:
 
 	mflr	r5
-	
+
 	addi	r3, r15, 0	/* density */
 	addi	r7, 0, 0
 fs01:	andi.	r6, r3, 0x01
 	cmpi	0, r6, 1
 	beq	fs04
-	
+
 	addi	r7, r7, 1
 	cmpi	0, r7, 7
 	bge	fs02
@@ -866,7 +866,7 @@ fs04:	addi	r3, r7, 0
 	addi	r6, 0, 1
 	subf	r3, r6, r3
 fs05:
-        mtlr    r5                     /* restore lr */
+	mtlr    r5                     /* restore lr */
 	blr
 
 /*--------------------------------------------------------------------- */
@@ -895,9 +895,9 @@ fc01:	srw	r6, r14, r4	/*  */
 	addi	r7, r19, 0	/* SDRAM cycle time for highest CAS latenty */
 
 	bl	fc03
-fc02:	
+fc02:
 	addi	r7, r20, 0	/* SDRAM cycle time for next-highest CAS latenty */
-fc03:	
+fc03:
 	addi	r8, r7, 0
 	addi	r9, 0, 4
 	srw	r7, r7, r9
@@ -910,7 +910,7 @@ fc03:
 	bgt	fc05
 	addi	r3, r2, 0
 	bl	fc05
-fc04:	
+fc04:
 	addi	r7, r21, 0	/* SDRAM cycle time for third-highest CAS latenty */
 	addi	r8, r7, 0
 	addi	r9, 0, 2
@@ -933,9 +933,9 @@ fc06:	addi	r6, 0, 1
 	cmpi	0, r4, 0
 	bne	fc01
 
-fc07:	
+fc07:
 
-        mtlr    r5		/* restore lr */
+	mtlr    r5		/* restore lr */
 	blr
 #endif
 
@@ -1000,7 +1000,7 @@ fc07:
 /* Size:	2 MB */
 /* Usage:	read/write */
 /* Width:	32 bit */
-	
+
 /* Walnut fpga pb7ap */
 /* 0      1      8         1         5         2         8            0 */
 /* 0 + 00000 + 011 + 000 + 00 + 01 + 01 + 01 + 001 + 0 + 1 + 0 + 0 + 00000 */

board/exbitgen/u-boot.lds

@@ -98,7 +98,7 @@ SECTIONS
   PROVIDE (erotext = .);
   .reloc   :
   {
-    *(.got) 
+    *(.got)
     _GOT2_TABLE_ = .;
     *(.got2)
     _FIXUP_TABLE_ = .;
@@ -119,6 +119,10 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
   __start___ex_table = .;
   __ex_table : { *(__ex_table) }
   __stop___ex_table = .;

board/gen860t/gen860t.c

@@ -302,4 +302,15 @@ board_poweroff(void)
     while (1);
 }
 
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+	return 0;	/* No hotkeys supported */
+}
+#endif
+
 /* vim: set ts=4 sw=4 tw=78 : */

board/hymod/bsp.c

@@ -27,7 +27,6 @@
 #include <command.h>
 #include <net.h>
 #include <asm/iopin_8260.h>
-#include <cmd_bsp.h>
 
 /*-----------------------------------------------------------------------
  * Board Special Commands: FPGA load/store, EEPROM erase
@@ -276,8 +275,8 @@ do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	printf ("Usage:\n%s\n", cmdtp->usage);
 	return 1;
 }
-cmd_tbl_t U_BOOT_CMD(fpga) = MK_CMD_ENTRY(
-	"fpga",	6,	1,	do_fpga,
+U_BOOT_CMD(
+	fpga,	6,	1,	do_fpga,
 	"fpga    - FPGA sub-system\n",
 	"load [type] addr size\n"
 	"  - write the configuration data at memory address `addr',\n"
@@ -335,8 +334,8 @@ do_eecl (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 
 	return 0;
 }
-cmd_tbl_t U_BOOT_CMD(eec) = MK_CMD_ENTRY(
-	"eeclear",	1,	0,	do_eecl,
+U_BOOT_CMD(
+	eeclear,	1,	0,	do_eecl,
 	"eeclear - Clear the eeprom on a Hymod board \n",
 	"[type]\n"
 	"  - write zeroes into the EEPROM on the board of type `type'\n"

board/icecube/Makefile

@@ -0,0 +1,47 @@
+
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/icecube/config.mk

@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# IceCube board
+#
+
+TEXT_BASE = 0xfff00000
+# TEXT_BASE = 0x00100000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board

board/icecube/flash.c

@@ -0,0 +1,480 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
+ *        has nothing to do with the flash chip being 8-bit or 16-bit.
+ */
+#ifdef CONFIG_FLASH_16BIT
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+#define	FLASH_ID_MASK	0xFFFF
+#else
+typedef unsigned char FLASH_PORT_WIDTH;
+typedef volatile unsigned char FLASH_PORT_WIDTHV;
+#define	FLASH_ID_MASK	0xFF
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define ORMASK(size) ((-size) & OR_AM_MSK)
+
+#define FLASH_CYCLE1	0x0555
+#define FLASH_CYCLE2	0x02aa
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPWV *addr, flash_info_t *info);
+static void flash_reset(flash_info_t *info);
+static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
+static flash_info_t *flash_get_info(ulong base);
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size = 0;
+	int i;
+	extern void flash_preinit(void);
+
+	flash_preinit();
+
+	/* Init: no FLASHes known */
+	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		ulong flashbase = CFG_FLASH_BASE;
+
+		memset(&flash_info[i], 0, sizeof(flash_info_t));
+
+		flash_info[i].size =
+			flash_get_size((FPW *)flashbase, &flash_info[i]);
+
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n",
+			i, flash_info[i].size);
+		}
+
+		size += flash_info[i].size;
+	}
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      flash_get_info(CFG_MONITOR_BASE));
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+		      flash_get_info(CFG_ENV_ADDR));
+#endif
+
+
+	return size ? size : 1;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t *info)
+{
+	FPWV *base = (FPWV *)(info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+		*base = (FPW)0x00FF00FF;	/* Intel Read Mode */
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+		*base = (FPW)0x00F000F0;	/* AMD Read Mode */
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static flash_info_t *flash_get_info(ulong base)
+{
+	int i;
+	flash_info_t * info;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
+		info = & flash_info[i];
+		if (info->start[0] <= base && base <= info->start[0] + info->size - 1)
+			break;
+	}
+
+	return i == CFG_MAX_FLASH_BANKS ? 0 : info;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+	uchar *boottype;
+	uchar *bootletter;
+	uchar *fmt;
+	uchar botbootletter[] = "B";
+	uchar topbootletter[] = "T";
+	uchar botboottype[] = "bottom boot sector";
+	uchar topboottype[] = "top boot sector";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	/* check for top or bottom boot, if it applies */
+	if (info->flash_id & FLASH_BTYPE) {
+		boottype = botboottype;
+		bootletter = botbootletter;
+	}
+	else {
+		boottype = topboottype;
+		bootletter = topbootletter;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMDLV065D:
+		fmt = "29LV065 (64 Mbit, uniform sectors)\n";
+		break;
+	default:
+		fmt = "Unknown Chip Type\n";
+		break;
+	}
+
+	printf (fmt, bootletter, boottype);
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20,
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size (FPWV *addr, flash_info_t *info)
+{
+	int i;
+	/* Write auto select command: read Manufacturer ID */
+	/* Write auto select command sequence and test FLASH answer */
+	addr[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE2] = (FPW)0x00550055;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE1] = (FPW)0x00900090;	/* selects Intel or AMD */
+
+	/* The manufacturer codes are only 1 byte, so just use 1 byte.
+	 * This works for any bus width and any FLASH device width.
+	 */
+	udelay(100);
+	switch (addr[0] & 0xff) {
+
+	case (uchar)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	case (uchar)INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
+	if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) {
+
+	case (FPW)AMD_ID_LV065D:
+		info->flash_id += FLASH_AMDLV065D;
+		info->sector_count = 128;
+		info->size = 0x00800000;
+		for( i = 0; i < info->sector_count; i++ )
+			info->start[i] = (ulong)addr + (i * 0x10000);
+		break;				/* => 8 or 16 MB	*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* => no or unknown flash */
+	}
+
+	/* Put FLASH back in read mode */
+	flash_reset(info);
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	FPWV *addr;
+	int flag, prot, sect;
+	int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMDLV065D:
+		break;
+	case FLASH_UNKNOWN:
+	default:
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	last  = get_timer(0);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
+
+		if (info->protect[sect] != 0)	/* protected, skip it */
+			continue;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr = (FPWV *)(info->start[sect]);
+		if (intel) {
+			*addr = (FPW)0x00500050; /* clear status register */
+			*addr = (FPW)0x00200020; /* erase setup */
+			*addr = (FPW)0x00D000D0; /* erase confirm */
+		}
+		else {
+			/* must be AMD style if not Intel */
+			FPWV *base;		/* first address in bank */
+
+			base = (FPWV *)(info->start[0]);
+			base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+			base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+			base[FLASH_CYCLE1] = (FPW)0x00800080;	/* erase mode */
+			base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+			base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+			*addr = (FPW)0x00300030;	/* erase sector */
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		start = get_timer(0);
+
+		/* wait at least 50us for AMD, 80us for Intel.
+		 * Let's wait 1 ms.
+		 */
+		udelay (1000);
+
+		while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
+			if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+
+				if (intel) {
+					/* suspend erase	*/
+					*addr = (FPW)0x00B000B0;
+				}
+
+				flash_reset(info);	/* reset to read mode */
+				rcode = 1;		/* failed */
+				break;
+			}
+
+			/* show that we're waiting */
+			if ((get_timer(last)) > CFG_HZ) {/* every second */
+				putc ('.');
+				last = get_timer(0);
+			}
+		}
+
+		/* show that we're waiting */
+		if ((get_timer(last)) > CFG_HZ) {	/* every second */
+			putc ('.');
+			last = get_timer(0);
+		}
+
+		flash_reset(info);	/* reset to read mode	*/
+	}
+
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
+	int bytes;	  /* number of bytes to program in current word		*/
+	int left;	  /* number of bytes left to program			*/
+	int i, res;
+
+	for (left = cnt, res = 0;
+		 left > 0 && res == 0;
+		 addr += sizeof(data), left -= sizeof(data) - bytes) {
+
+		bytes = addr & (sizeof(data) - 1);
+		addr &= ~(sizeof(data) - 1);
+
+		/* combine source and destination data so can program
+		 * an entire word of 16 or 32 bits
+		 */
+		for (i = 0; i < sizeof(data); i++) {
+			data <<= 8;
+			if (i < bytes || i - bytes >= left )
+				data += *((uchar *)addr + i);
+			else
+				data += *src++;
+		}
+
+		/* write one word to the flash */
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			res = write_word_amd(info, (FPWV *)addr, data);
+			break;
+		default:
+			/* unknown flash type, error! */
+			printf ("missing or unknown FLASH type\n");
+			res = 1;	/* not really a timeout, but gives error */
+			break;
+		}
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
+{
+	ulong start;
+	int flag;
+	int res = 0;	/* result, assume success	*/
+	FPWV *base;		/* first address in flash bank	*/
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+
+	base = (FPWV *)(info->start[0]);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+	base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+	base[FLASH_CYCLE1] = (FPW)0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data	*/
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer (0);
+
+	/* data polling for D7 */
+	while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*dest = (FPW)0x00F000F0;	/* reset bank */
+			res = 1;
+		}
+	}
+
+	return (res);
+}

board/icecube/icecube.c

@@ -0,0 +1,116 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+
+long int initdram (int board_type)
+{
+#ifndef CFG_RAMBOOT
+	/* configure SDRAM start/end */
+#if defined(CONFIG_MPC5200)
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x00000018;/* 32M at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x02000000;/* disabled */
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2233a00;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0000;
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002;
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = 0x408d0000;
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002;
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0004;
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0x504f0000;
+#elif defined(CONFIG_MGT5100)
+	*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
+	*(vu_long *)MPC5XXX_SDRAM_STOP = 0x000007ff;/* 64M */
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2222600;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004;
+
+	/* address select register */
+	*(vu_long *)MPC5XXX_SDRAM_XLBSEL = 0x03000000;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd14f0000;
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd14f0002;
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd14f0002;
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd14f0004;
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0x514f0000;
+#endif
+#else
+#ifdef CONFIG_MGT5100
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
+#endif
+#endif
+	/* return total ram size */
+#if defined(CONFIG_MGT5100)
+	return (64 * 1024 * 1024);
+#elif defined(CONFIG_MPC5200)
+	return (32 * 1024 * 1024);
+#endif
+}
+
+int checkboard (void)
+{
+#if defined(CONFIG_MPC5200)
+	puts ("Board: Motorola MPC5200 (IceCube)\n");
+#elif defined(CONFIG_MGT5100)
+	puts ("Board: Motorola MGT5100 (IceCube)\n");
+#endif
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+#if defined(CONFIG_MGT5100)
+	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
+#endif
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+}

board/icecube/u-boot.lds

@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc5xxx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/lwmon/lwmon.c

@@ -184,7 +184,7 @@ V* Verification: dzu@denx.de
  ***********************************************************************/
 int checkboard (void)
 {
-	puts ("Board: Litronic Monitor IV\n");
+	puts ("Board: LICCON Konsole LCD2\n");
 	return (0);
 }
 
@@ -851,8 +851,8 @@ int do_pic (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	printf ("Usage:\n%s\n", cmdtp->usage);
 	return 1;
 }
-cmd_tbl_t U_BOOT_CMD(pic) = MK_CMD_ENTRY(
-	"pic",	4,	1,	do_pic,
+U_BOOT_CMD(
+	pic,	4,	1,	do_pic,
 	"pic     - read and write PIC registers\n",
 	"read  reg      - read PIC register `reg'\n"
 	"pic write reg val  - write value `val' to PIC register `reg'\n"
@@ -910,8 +910,8 @@ int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return 0;
 }
 
-cmd_tbl_t U_BOOT_CMD(kdb) = MK_CMD_ENTRY(
-	"kbd",	1,	1,	do_kbd,
+U_BOOT_CMD(
+	kbd,	1,	1,	do_kbd,
 	"kbd     - read keyboard status\n",
 	NULL
 );
@@ -982,8 +982,8 @@ int do_lsb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return 1;
 }
 
-cmd_tbl_t U_BOOT_CMD(lsb) = MK_CMD_ENTRY(
-	"lsb",	2,	1,	do_lsb,
+U_BOOT_CMD(
+	lsb,	2,	1,	do_lsb,
 	"lsb     - check and set LSB switch\n",
 	"on  - switch LSB on\n"
 	"lsb off - switch LSB off\n"
@@ -1071,3 +1071,22 @@ static int key_pressed(void)
 	return (compare_magic(kbd_data, CONFIG_MODEM_KEY_MAGIC) == 0);
 }
 #endif	/* CONFIG_MODEM_SUPPORT */
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(gd_t *gd)
+{
+	uchar kbd_data[KEYBD_DATALEN];
+	uchar val;
+
+	/* Read keys */
+	val = KEYBD_CMD_READ_KEYS;
+	i2c_write (kbd_addr, 0, 0, &val, 1);
+	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+	return (compare_magic(kbd_data, CONFIG_POST_KEY_MAGIC) == 0);
+}
+#endif

board/mpc8260ads/flash.c

@@ -7,6 +7,11 @@
  * I started with board/ip860/flash.c and made changes I found in
  * the MTD project by David Schleef.
  *
+ * (C) Copyright 2003 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ * Re-written to support multi-bank flash SIMMs.
+ * Added support for real protection and JFFS2.
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -28,73 +33,119 @@
 
 #include <common.h>
 
+/* Intel-compatible flash ID */
+#define INTEL_COMPAT  0x89898989
+#define INTEL_ALT     0xB0B0B0B0
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+/* Intel-compatible flash commands */
+#define INTEL_PROGRAM 0x10101010
+#define INTEL_ERASE   0x20202020
+#define INTEL_CLEAR   0x50505050
+#define INTEL_LOCKBIT 0x60606060
+#define INTEL_PROTECT 0x01010101
+#define INTEL_STATUS  0x70707070
+#define INTEL_READID  0x90909090
+#define INTEL_CONFIRM 0xD0D0D0D0
+#define INTEL_RESET   0xFFFFFFFF
 
-#if defined(CFG_ENV_IS_IN_FLASH)
-# ifndef  CFG_ENV_ADDR
-#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
-# endif
-# ifndef  CFG_ENV_SIZE
-#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
-# endif
-# ifndef  CFG_ENV_SECT_SIZE
-#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
-# endif
-#endif
+/* Intel-compatible flash status bits */
+#define INTEL_FINISHED 0x80808080
+#define INTEL_OK       0x80808080
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
 /*-----------------------------------------------------------------------
- * Functions
+ * This board supports 32-bit wide flash SIMMs (4x8-bit configuration.)
+ * Up to 32MB of flash supported (up to 4 banks.)
+ * BCSR is used for flash presence detect (page 4-65 of the User's Manual)
+ *
+ * The following code can not run from flash!
  */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static int clear_block_lock_bit(vu_long * addr);
-
-/*-----------------------------------------------------------------------
- */
-
 unsigned long flash_init (void)
 {
-#ifndef CONFIG_MPC8260ADS
-	volatile immap_t	*immap  = (immap_t *)CFG_IMMR;
-	volatile memctl8xx_t	*memctl = &immap->im_memctl;
-	volatile ip860_bcsr_t	*bcsr   = (ip860_bcsr_t *)BCSR_BASE;
-#endif
-	unsigned long size;
-	int i;
+	ulong size = 0, sect_start, sect_size = 0, bank_size;
+	ushort sect_count = 0;
+	int i, j, nbanks;
+	vu_long *addr = (vu_long *)CFG_FLASH_BASE;
+	vu_long *bcsr = (vu_long *)CFG_BCSR;
 
-	/* Init: enable write,
-	 * or we cannot even write flash commands
-	 */
-#ifndef CONFIG_MPC8260ADS
-	bcsr->bd_ctrl |= BD_CTRL_FLWE;
-#endif
-
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-
-		/* set the default sector offset */
+	switch (bcsr[2] & 0xF) {
+	case 0:
+		nbanks = 4;
+		break;
+	case 1:
+		nbanks = 2;
+		break;
+	case 2:
+		nbanks = 1;
+		break;
+	default:		/* Unsupported configurations */
+		nbanks = CFG_MAX_FLASH_BANKS;
 	}
 
-	/* Static FLASH Bank configuration here - FIXME XXX */
+	if (nbanks > CFG_MAX_FLASH_BANKS)
+		nbanks = CFG_MAX_FLASH_BANKS;
 
-	size = flash_get_size((vu_long *)FLASH_BASE, &flash_info[0]);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-			size, size<<20);
+	for (i = 0; i < nbanks; i++) {
+		*addr = INTEL_READID;	/* Read Intelligent Identifier */
+		if ((addr[0] == INTEL_COMPAT) || (addr[0] == INTEL_ALT)) {
+			switch (addr[1]) {
+			case SHARP_ID_28F016SCL:
+			case SHARP_ID_28F016SCZ:
+				flash_info[i].flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
+				sect_count = 32;
+				sect_size = 0x40000;
+				break;
+			default:
+				flash_info[i].flash_id = FLASH_UNKNOWN;
+				sect_count = CFG_MAX_FLASH_SECT;
+				sect_size =
+				   CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS / CFG_MAX_FLASH_SECT;
+			}
+		}
+		else
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf("### Unknown flash ID %08lX %08lX at address %08lX ###\n",
+			       addr[0], addr[1], (ulong)addr);
+			size = 0;
+			*addr = INTEL_RESET; /* Reset bank to Read Array mode */
+			break;
+		}
+		flash_info[i].sector_count = sect_count;
+		flash_info[i].size = bank_size = sect_size * sect_count;
+		size += bank_size;
+		sect_start = (ulong)addr;
+		for (j = 0; j < sect_count; j++) {
+			addr = (vu_long *)sect_start;
+			flash_info[i].start[j]   = sect_start;
+			flash_info[i].protect[j] = (addr[2] == 0x01010101);
+			sect_start += sect_size;
+		}
+		*addr = INTEL_RESET; /* Reset bank to Read Array mode */
+		addr = (vu_long *)sect_start;
 	}
-#ifndef CONFIG_MPC8260ADS
-	/* Remap FLASH according to real size */
-	memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
-	memctl->memc_br1 = (CFG_FLASH_BASE & BR_BA_MSK) |
-				(memctl->memc_br1 & ~(BR_BA_MSK));
-#endif
 
-	/* Re-do sizing to get full correct info */
-	size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
-
-	flash_info[0].size = size;
+	if (size == 0) {	/* Unknown flash, fill with hard-coded values */
+		sect_start = CFG_FLASH_BASE;
+		for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+			flash_info[i].size = CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS;
+			flash_info[i].sector_count = sect_count;
+			for (j = 0; j < sect_count; j++) {
+				flash_info[i].start[j]   = sect_start;
+				flash_info[i].protect[j] = 0;
+				sect_start += sect_size;
+			}
+		}
+		size = CFG_FLASH_SIZE;
+	}
+	else
+		for (i = nbanks; i < CFG_MAX_FLASH_BANKS; i++) {
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+			flash_info[i].size = 0;
+			flash_info[i].sector_count = 0;
+		}
 
 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
 	/* monitor protection ON by default */
@@ -161,102 +212,6 @@ void flash_print_info  (flash_info_t *info)
 
 /*-----------------------------------------------------------------------
  */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
-	short i;
-	ulong value;
-	ulong base = (ulong)addr;
-	ulong sector_offset;
-
-	/* Write "Intelligent Identifier" command: read Manufacturer ID */
-	*addr = 0x90909090;
-
-	value = addr[0] & 0x00FF00FF;
-	switch (value) {
-	case MT_MANUFACT:	/* SHARP, MT or => Intel */
-	case INTEL_ALT_MANU:
-		info->flash_id = FLASH_MAN_INTEL;
-		break;
-	default:
-		printf("unknown manufacturer: %x\n", (unsigned int)value);
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		return (0);			/* no or unknown flash	*/
-	}
-
-	value = addr[1];			/* device ID		*/
-
-	switch (value) {
-	case (INTEL_ID_28F016S):
-		info->flash_id += FLASH_28F016SV;
-		info->sector_count = 32;
-		info->size = 0x00400000;
-		sector_offset = 0x20000;
-		break;				/* => 2x2 MB		*/
-
-	case (INTEL_ID_28F160S3):
-		info->flash_id += FLASH_28F160S3;
-		info->sector_count = 32;
-		info->size = 0x00400000;
-		sector_offset = 0x20000;
-		break;				/* => 2x2 MB		*/
-
-	case (INTEL_ID_28F320S3):
-		info->flash_id += FLASH_28F320S3;
-		info->sector_count = 64;
-		info->size = 0x00800000;
-		sector_offset = 0x20000;
-		break;				/* => 2x4 MB		*/
-
-	case SHARP_ID_28F016SCL:
-	case SHARP_ID_28F016SCZ:
-		info->flash_id      = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
-		info->sector_count  = 32;
-		info->size          = 0x00800000;
-		sector_offset = 0x40000;
-		break;				/* => 4x2 MB		*/
-
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		return (0);			/* => no or unknown flash */
-
-	}
-
-	/* set up sector start address table */
-	for (i = 0; i < info->sector_count; i++) {
-		info->start[i] = base;
-		base += sector_offset;
-		/* don't know how to check sector protection */
-		info->protect[i] = 0;
-	}
-
-	/*
-	 * Prevent writes to uninitialized FLASH.
-	 */
-	if (info->flash_id != FLASH_UNKNOWN) {
-		addr = (vu_long *)info->start[0];
-
-		*addr = 0xFFFFFF;	/* reset bank to read array mode */
-	}
-
-	return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
 int	flash_erase (flash_info_t *info, int s_first, int s_last)
 {
 	int flag, prot, sect;
@@ -292,12 +247,6 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 		printf ("\n");
 	}
 
-	/* Make Sure Block Lock Bit is not set. */
-	if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){
-		return 1;
-	}
-
-
 	/* Start erase on unprotected sectors */
 	for (sect = s_first; sect<=s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
@@ -308,36 +257,26 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 			/* Disable interrupts which might cause a timeout here */
 			flag = disable_interrupts();
 
-			/* Reset Array */
-			*addr = 0xffffffff;
 			/* Clear Status Register */
-			*addr = 0x50505050;
+			*addr = INTEL_CLEAR;
 			/* Single Block Erase Command */
-			*addr = 0x20202020;
+			*addr = INTEL_ERASE;
 			/* Confirm */
-			*addr = 0xD0D0D0D0;
+			*addr = INTEL_CONFIRM;
 
 			if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
 			    /* Resume Command, as per errata update */
-			    *addr = 0xD0D0D0D0;
+			    *addr = INTEL_CONFIRM;
 			}
 
 			/* re-enable interrupts if necessary */
 			if (flag)
 				enable_interrupts();
 
-			/* wait at least 80us - let's wait 1 ms */
-			udelay (1000);
-			while ((*addr & 0x80808080) != 0x80808080) {
-				if(*addr & 0x20202020){
-					printf("Error in Block Erase - Lock Bit may be set!\n");
-					printf("Status Register = 0x%X\n", (uint)*addr);
-					*addr = 0xFFFFFFFF;	/* reset bank */
-					return 1;
-				}
+			while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
 				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
-					*addr = 0xFFFFFFFF;	/* reset bank */
+					*addr = INTEL_RESET;	/* reset bank */
 					return 1;
 				}
 				/* show that we're waiting */
@@ -347,8 +286,15 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 				}
 			}
 
+			if (*addr != INTEL_OK) {
+				printf("Block erase failed at %08X, CSR=%08X\n",
+				       (uint)addr, (uint)*addr);
+				*addr = INTEL_RESET;	/* reset bank */
+				return 1;
+			}
+
 			/* reset to read mode */
-			*addr = 0xFFFFFFFF;
+			*addr = INTEL_RESET;
 		}
 	}
 
@@ -356,6 +302,58 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 	return 0;
 }
 
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	ulong start;
+	int rc = 0;
+	int flag;
+	vu_long *addr = (vu_long *)dest;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		return (2);
+	}
+
+	*addr = INTEL_CLEAR; /* Clear status register */
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Write Command */
+	*addr = INTEL_PROGRAM;
+
+	/* Write Data */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			printf("Write timed out\n");
+			rc = 1;
+			break;
+		}
+	}
+	if (*addr != INTEL_OK) {
+		printf ("Write failed at %08X, CSR=%08X\n", (uint)addr, (uint)*addr);
+		rc = 1;
+	}
+
+	*addr = INTEL_RESET; /* Reset to read array mode */
+
+	return rc;
+}
+
 /*-----------------------------------------------------------------------
  * Copy memory to flash, returns:
  * 0 - OK
@@ -370,6 +368,8 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 
 	wp = (addr & ~3);	/* get lower word aligned address */
 
+	*(vu_long *)wp = INTEL_RESET; /* Reset to read array mode */
+
 	/*
 	 * handle unaligned start bytes
 	 */
@@ -424,85 +424,125 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 		data = (data << 8) | (*(uchar *)cp);
 	}
 
-	return (write_word(info, wp, data));
+	rc = write_word(info, wp, data);
+
+	return rc;
 }
 
 /*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
+ * Set/Clear sector's lock bit, returns:
  * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
+ * 1 - Error (timeout, voltage problems, etc.)
  */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
+int flash_real_protect(flash_info_t *info, long sector, int prot)
 {
-	vu_long *addr = (vu_long *)dest;
-	ulong start, csr;
-	int flag;
+	ulong start;
+	int i;
+	int rc = 0;
+	vu_long *addr = (vu_long *)(info->start[sector]);
+	int flag = disable_interrupts();
 
-	/* Check if Flash is (sufficiently) erased */
-	if ((*addr & data) != data) {
-		return (2);
+	*addr = INTEL_CLEAR;	/* Clear status register */
+	if (prot) {			/* Set sector lock bit */
+		*addr = INTEL_LOCKBIT;	/* Sector lock bit */
+		*addr = INTEL_PROTECT;	/* set */
+	}
+	else {				/* Clear sector lock bit */
+		*addr = INTEL_LOCKBIT;	/* All sectors lock bits */
+		*addr = INTEL_CONFIRM;	/* clear */
 	}
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
 
-	/* Write Command */
-	*addr = 0x10101010;
-
-	/* Write Data */
-	*addr = data;
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* data polling for D7 */
-	start = get_timer (0);
-	flag  = 0;
-	while (((csr = *addr) & 0x80808080) != 0x80808080) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
-			flag = 1;
+	start = get_timer(0);
+	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
+		if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) {
+			printf("Flash lock bit operation timed out\n");
+			rc = 1;
 			break;
 		}
 	}
-	if (csr & 0x40404040) {
-		printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
-		flag = 1;
+
+	if (*addr != INTEL_OK) {
+		printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
+		       (uint)addr, (uint)*addr);
+		rc = 1;
 	}
 
-	/* Clear Status Registers Command */
-	*addr = 0x50505050;
-	/* Reset to read array mode */
-	*addr = 0xFFFFFFFF;
+	if (!rc)
+		info->protect[sector] = prot;
 
-	return (flag);
+	/*
+	 * Clear lock bit command clears all sectors lock bits, so
+	 * we have to restore lock bits of protected sectors.
+	 */
+	if (!prot)
+		for (i = 0; i < info->sector_count; i++)
+			if (info->protect[i]) {
+				addr = (vu_long *)(info->start[i]);
+				*addr = INTEL_LOCKBIT;	/* Sector lock bit */
+				*addr = INTEL_PROTECT;	/* set */
+				udelay(CFG_FLASH_LOCK_TOUT * 1000);
+			}
+
+	if (flag)
+		enable_interrupts();
+
+	*addr = INTEL_RESET;		/* Reset to read array mode */
+
+	return rc;
 }
 
 /*-----------------------------------------------------------------------
- * Clear Block Lock Bit, returns:
- * 0 - OK
- * 1 - Timeout
+ * Support for flash file system (JFFS2)
+ *
+ * We use custom partition info function because we have to fit the
+ * file system image between first sector (containing hard reset
+ * configuration word) and the sector containing U-Boot image. Standard
+ * partition info function does not allow for last sector specification
+ * and assumes that the file system occupies flash bank up to and
+ * including bank's last sector.
  */
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CFG_JFFS_CUSTOM_PART)
 
-static int clear_block_lock_bit(vu_long  * addr)
+#ifndef CFG_JFFS2_FIRST_SECTOR
+#define CFG_JFFS2_FIRST_SECTOR 0
+#endif
+#ifndef CFG_JFFS2_FIRST_BANK
+#define CFG_JFFS2_FIRST_BANK 0
+#endif
+#ifndef CFG_JFFS2_NUM_BANKS
+#define CFG_JFFS2_NUM_BANKS 1
+#endif
+#define CFG_JFFS2_LAST_BANK (CFG_JFFS2_FIRST_BANK + CFG_JFFS2_NUM_BANKS - 1)
+
+#include <jffs2/jffs2.h>
+
+static struct part_info partition;
+
+struct part_info *jffs2_part_info(int part_num)
 {
-	ulong start, now;
+	int i;
 
-	/* Reset Array */
-	*addr = 0xffffffff;
-	/* Clear Status Register */
-	*addr = 0x50505050;
+	if (part_num == 0) {
+		if (partition.usr_priv == 0) {
+			partition.offset =
+				(unsigned char *) flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR];
+			for (i = CFG_JFFS2_FIRST_BANK; i <= CFG_JFFS2_LAST_BANK; i++)
+				partition.size += flash_info[i].size;
+			partition.size -=
+				flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR] -
+				flash_info[CFG_JFFS2_FIRST_BANK].start[0];
+#ifdef CFG_JFFS2_LAST_SECTOR
+			i = flash_info[CFG_JFFS2_LAST_BANK].sector_count - 1;
+			partition.size -=
+				flash_info[CFG_JFFS2_LAST_BANK].start[i] -
+				flash_info[CFG_JFFS2_LAST_BANK].start[CFG_JFFS2_LAST_SECTOR];
+#endif
 
-	*addr = 0x60606060;
-	*addr = 0xd0d0d0d0;
-
-	start = get_timer (0);
-	while(*addr != 0x80808080){
-		if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
-			printf ("Timeout on clearing Block Lock Bit\n");
-			*addr = 0xFFFFFFFF;	/* reset bank */
-			return 1;
+			partition.usr_priv = (void *)1;
 		}
+		return &partition;
 	}
 	return 0;
 }
+
+#endif /* JFFS2 */

board/mpl/mip405/cmd_mip405.c

@@ -53,8 +53,8 @@ int do_mip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
    	}
 	return (do_mplcommon(cmdtp, flag, argc, argv));
 }
-cmd_tbl_t U_BOOT_CMD(mip405) = MK_CMD_ENTRY(
-	"mip405",	6,	1,	do_mip405,
+U_BOOT_CMD(
+	mip405,	6,	1,	do_mip405,
 	"mip405  - MIP405 specific Cmds\n",
 	"flash mem [SrcAddr] - updates U-Boot with image in memory\n"
 	"mip405 flash mps - updates U-Boot with image from MPS\n"

board/mpl/pip405/cmd_pip405.c

@@ -58,8 +58,8 @@ int do_pip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 	return (do_mplcommon(cmdtp, flag, argc, argv));
 }
-cmd_tbl_t U_BOOT_CMD(pip405) = MK_CMD_ENTRY(
-	"pip405",	6,	1,	do_pip405,
+U_BOOT_CMD(
+	pip405,	6,	1,	do_pip405,
 	"pip405  - PIP405 specific Cmds\n",
 	"flash mem [SrcAddr] - updates U-Boot with image in memory\n"
 	"pip405 flash floppy [SrcAddr] - updates U-Boot with image from floppy\n"

board/omap1510inn/Makefile

@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= omap1510innovator.o flash.o
+SOBJS	:= platform.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/omap1510inn/config.mk

@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2003
+# Texas Instruments, <www.ti.com>
+# Kshitij Gupta <Kshitij@ti.com>
+#
+# TI Innovator board with OMAP1510 (ARM925T) cpu
+# see http://www.ti.com/ for more information on Texas Insturments
+#
+# Innovator has 1 bank of 256 MB SDRAM
+# Physical Address:
+# 1000'0000 to 2000'0000
+#
+#
+# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000  (mem base + reserved)
+#
+# we load ourself to 1100'0000
+#
+#
+
+
+TEXT_BASE = 0x11000000

board/omap1510inn/flash.c

@@ -0,0 +1,428 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+#define PHYS_FLASH_SECT_SIZE    0x00020000	/* 256 KB sectors (x2) */
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH	ushort
+#define FLASH_PORT_WIDTHV	vu_short
+#define SWAP(x)			__swab16(x)
+#else
+#define FLASH_PORT_WIDTH	ulong
+#define FLASH_PORT_WIDTHV	vu_long
+#define SWAP(x)			__swab32(x)
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		default:
+			panic ("configured to many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0]);
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+			&flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);			/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];			/* device ID        */
+	switch (value) {
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x02000000;
+		break;				/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	/*start = get_timer (0); */
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+				if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = (FPW) 0x00B000B0;	/* suspend erase     */
+					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = (FPW) 0x00500050;	/* clear status register cmd.   */
+			*addr = (FPW) 0x00FF00FF;	/* resest to read mode          */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}

board/omap1510inn/omap1510innovator.c

@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+static void flash__init (void);
+static void ether__init (void);
+
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+			  "subs %0, %1, #1\n"
+			  "bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* arch number of OMAP 1510-Board */
+	gd->bd->bi_arch_number = 234;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x10000100;
+
+/* kk - this speeds up your boot a quite a bit.  However to make it
+ *  work, you need make sure your kernel startup flush bug is fixed.
+ *  ... rkw ...
+ */
+	icache_enable ();
+
+	flash__init ();
+	ether__init ();
+	return 0;
+}
+
+
+int misc_init_r (void)
+{
+	/* volatile ushort *gdir = (ushort *) (GPIO_DIR_CONTROL_REG); */
+	/* volatile ushort *mdir = (ushort *) (MPUIO_DIR_CONTROL_REG); */
+
+	/* setup gpio direction to match board (no floats!) */
+	/**gdir = 0xCFF9; */
+	/**mdir = 0x103F; */
+
+	return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+static void flash__init (void)
+{
+#define CS0_CHIP_SELECT_REG 0xfffecc10
+#define CS3_CHIP_SELECT_REG 0xfffecc1c
+#define EMIFS_GlB_Config_REG 0xfffecc0c
+
+	{
+		unsigned int regval;
+
+		regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
+		regval = regval | 0x0001;	/* Turn off write protection for flash devices. */
+		if (regval & 0x0002) {
+			regval = regval & 0xfffd;	/* Swap CS0 and CS3 so that flash is visible at 0x0 and eeprom at 0x0c000000. */
+			/* If, instead, you want to reference flash at 0x0c000000, then it seemed the following were necessary. */
+			/* *((volatile unsigned int *)CS0_CHIP_SELECT_REG) = 0x202090; / * Overrides head.S setting of 0x212090 */
+			/* *((volatile unsigned int *)CS3_CHIP_SELECT_REG) = 0x202090; / * Let's flash chips be fully functional. */
+		}
+		*((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
+	}
+}
+
+
+/******************************
+ Routine:
+ Description:
+******************************/
+static void ether__init (void)
+{
+#define ETH_CONTROL_REG 0x0800000b
+	/* take the Ethernet controller out of reset and wait
+	 * for the EEPROM load to complete.
+	 */
+	*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
+	udelay (3);
+}
+
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}

board/omap1510inn/platform.S

@@ -0,0 +1,386 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ *
+ * -- Some bits of code used from rrload's head_OMAP1510.s --
+ * Copyright (C) 2002 RidgeRun, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_OMAP1510)
+#include <./configs/omap1510.h>
+#endif
+
+#define OMAP1510_CLKS ((1<<EN_XORPCK)|(1<<EN_PERCK)|(1<<EN_TIMCK)|(1<<EN_GPIOCK))
+
+
+_TEXT_BASE:
+	.word	TEXT_BASE        /* sdram load addr from config.mk */
+
+.globl platformsetup
+platformsetup:
+
+	/*
+	 * Configure 1510 pins functions to match our board.
+	 */
+	ldr     r0, REG_PULL_DWN_CTRL_0
+	ldr     r1, VAL_PULL_DWN_CTRL_0
+	str     r1, [r0]
+	ldr     r0, REG_PULL_DWN_CTRL_1
+	ldr     r1, VAL_PULL_DWN_CTRL_1
+	str     r1, [r0]
+	ldr     r0, REG_PULL_DWN_CTRL_2
+	ldr     r1, VAL_PULL_DWN_CTRL_2
+	str     r1, [r0]
+	ldr     r0, REG_PULL_DWN_CTRL_3
+	ldr     r1, VAL_PULL_DWN_CTRL_3
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_4
+	ldr     r1, VAL_FUNC_MUX_CTRL_4
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_5
+	ldr     r1, VAL_FUNC_MUX_CTRL_5
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_6
+	ldr     r1, VAL_FUNC_MUX_CTRL_6
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_7
+	ldr     r1, VAL_FUNC_MUX_CTRL_7
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_8
+	ldr     r1, VAL_FUNC_MUX_CTRL_8
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_9
+	ldr     r1, VAL_FUNC_MUX_CTRL_9
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_A
+	ldr     r1, VAL_FUNC_MUX_CTRL_A
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_B
+	ldr     r1, VAL_FUNC_MUX_CTRL_B
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_C
+	ldr     r1, VAL_FUNC_MUX_CTRL_C
+	str     r1, [r0]
+	ldr     r0, REG_VOLTAGE_CTRL_0
+	ldr     r1, VAL_VOLTAGE_CTRL_0
+	str     r1, [r0]
+	ldr     r0, REG_TEST_DBG_CTRL_0
+	ldr     r1, VAL_TEST_DBG_CTRL_0
+	str     r1, [r0]
+	ldr     r0, REG_MOD_CONF_CTRL_0
+	ldr     r1, VAL_MOD_CONF_CTRL_0
+	str     r1, [r0]
+
+	/* Move to 1510 mode */
+	ldr     r0, REG_COMP_MODE_CTRL_0
+	ldr     r1, VAL_COMP_MODE_CTRL_0
+	str     r1, [r0]
+
+	/* Set up Traffic Ctlr*/
+	ldr r0, REG_TC_IMIF_PRIO
+	mov r1, #0x0
+	str r1, [r0]
+	ldr r0, REG_TC_EMIFS_PRIO
+	str r1, [r0]
+	ldr r0, REG_TC_EMIFF_PRIO
+	str r1, [r0]
+
+	ldr r0, REG_TC_EMIFS_CONFIG
+	ldr r1, [r0]
+	bic r1, r1, #0x08   /* clear the global power-down enable PDE bit */
+	bic r1, r1, #0x01   /* write protect flash by clearing the WP bit */
+	str r1, [r0]        /* EMIFS GlB Configuration. (value 0x12 most likely) */
+
+	/* Setup some clock domains */
+	ldr r1, =OMAP1510_CLKS
+	ldr r0, REG_ARM_IDLECT2
+	strh r1, [r0]  /* CLKM, Clock domain control. */
+
+	mov r1, #0x01  /* PER_EN bit */
+	ldr r0, REG_ARM_RSTCT2
+	strh r1, [r0]  /* CLKM; Peripheral reset. */
+
+	/* Set CLKM to Sync-Scalable  */
+	/* I supposidly need to enable the dsp clock before switching */
+	mov r1, #0x1000
+	ldr r0, REG_ARM_SYSST
+	strh r1, [r0]
+	mov r0, #0x400
+1:
+	subs r0, r0, #0x1   /* wait for any bubbles to finish */
+	bne 1b
+
+	ldr r1, VAL_ARM_CKCTL  /* use 12Mhz ref, PER must be <= 50Mhz so /2 */
+	ldr r0, REG_ARM_CKCTL
+	strh r1, [r0]
+
+	/* setup DPLL 1 */
+	ldr r1, VAL_DPLL1_CTL
+	ldr r0, REG_DPLL1_CTL
+	strh r1, [r0]
+	ands r1, r1, #0x10  /* Check if PLL is enabled. */
+	beq lock_end        /* Do not look for lock if BYPASS selected */
+2:
+	ldrh r1, [r0]
+	ands r1, r1, #0x01  /* Check the LOCK bit. */
+	beq 2b              /* ...loop until bit goes hi. */
+lock_end:
+
+	/* Set memory timings corresponding to the new clock speed */
+
+	/* Check execution location to determine current execution location
+	 * and branch to appropriate initialization code.
+	 */
+	mov r0, #0x10000000                 /* Load physical SDRAM base. */
+	mov r1, pc                          /* Get current execution location. */
+	cmp r1, r0                          /* Compare. */
+	bge skip_sdram                      /* Skip over EMIF-fast initialization if running from SDRAM. */
+
+	/*
+	 * Delay for SDRAM initialization.
+	 */
+	mov r3, #0x1800                        /* value should be checked */
+3:
+	subs r3, r3, #0x1                     /* Decrement count */
+	bne 3b
+
+	/*
+	 * Set SDRAM control values. Disable refresh before MRS command.
+	 */
+	ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG   /* get good value */
+	bic r3, r0, #0xC                    /* (BIT3|BIT2) ulConfig with auto-refresh disabled. */
+	orr r3, r3, #0x8000000              /* (BIT27) Disable CLK when Power down or Self-Refresh */
+	orr r3, r3, #0x4000000              /* BIT26 Power Down Enable */
+	ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
+	str r3, [r2]                        /* Store the passed value with AR disabled. */
+
+	ldr r1, VAL_TC_EMIFF_MRS            /* get MRS value */
+	ldr r2, REG_TC_EMIFF_MRS            /* Point to MRS register. */
+	str r1, [r2]                        /* Store the passed value.*/
+
+	ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
+	str r0, [r2]                        /* Store the passed value. */
+
+	/*
+	 * Delay for SDRAM initialization.
+	 */
+	mov r3, #0x1800
+4:
+	subs r3, r3, #1                     /* Decrement count. */
+	bne 4b
+
+skip_sdram:
+
+	/* slow interface */
+	ldr r1, VAL_TC_EMIFS_CS0_CONFIG
+	ldr r0, REG_TC_EMIFS_CS0_CONFIG
+	str r1, [r0] /* Chip Select 0 */
+	ldr r1, VAL_TC_EMIFS_CS1_CONFIG
+	ldr r0, REG_TC_EMIFS_CS1_CONFIG
+	str r1, [r0] /* Chip Select 1 */
+	ldr r1, VAL_TC_EMIFS_CS2_CONFIG
+	ldr r0, REG_TC_EMIFS_CS2_CONFIG
+	str r1, [r0] /* Chip Select 2 */
+	ldr r1, VAL_TC_EMIFS_CS3_CONFIG
+	ldr r0, REG_TC_EMIFS_CS3_CONFIG
+	str r1, [r0] /* Chip Select 3 */
+
+ /* Next, Enable the RS232 Line Drivers in the FPGA. */
+ /* Also, power on the audio CODEC's amplifier here, */
+ /* which will make a noise on the audio output. */
+ /* This is done here instead of in the kernel so there */
+ /* isn't a loud popping noise at the start of each */
+ /* song. */
+ /* Also, disable the CODEC's clocks. */
+ /* omap1510-HelenP1 [specific] */
+
+	ldr r0, REG_FPGA_POWER
+	mov r1, #0
+	ldr r2, REG_FPGA_DIP_SWITCH
+	ldrb r3, [r2]
+	cmp r3, #0x8
+	movne r1, #0x62     /* Enable the RS232 Line Drivers in the EPLD */
+	strb r1, [r0]
+	ldr r0, REG_FPGA_AUDIO
+	mov r1, #0x0     /* Disable sound driver (CODEC clocks) */
+	strb r1, [r0]
+
+	/* back to arch calling code */
+	mov	pc, lr
+
+/* the literal pools origin */
+	.ltorg
+
+/* OMAP configuration registers */
+REG_FUNC_MUX_CTRL_0:		/* 32 bits */
+	.word 0xfffe1000
+REG_FUNC_MUX_CTRL_1:		/* 32 bits */
+	.word 0xfffe1004
+REG_FUNC_MUX_CTRL_2:		/* 32 bits */
+	.word 0xfffe1008
+REG_COMP_MODE_CTRL_0:		/* 32 bits */
+	.word 0xfffe100c
+REG_FUNC_MUX_CTRL_3:		/* 32 bits */
+	.word 0xfffe1010
+REG_FUNC_MUX_CTRL_4:		/* 32 bits */
+	.word 0xfffe1014
+REG_FUNC_MUX_CTRL_5:		/* 32 bits */
+	.word 0xfffe1018
+REG_FUNC_MUX_CTRL_6:		/* 32 bits */
+	.word 0xfffe101c
+REG_FUNC_MUX_CTRL_7:		/* 32 bits */
+	.word 0xfffe1020
+REG_FUNC_MUX_CTRL_8:		/* 32 bits */
+	.word 0xfffe1024
+REG_FUNC_MUX_CTRL_9:		/* 32 bits */
+	.word 0xfffe1028
+REG_FUNC_MUX_CTRL_A:		/* 32 bits */
+	.word 0xfffe102C
+REG_FUNC_MUX_CTRL_B:		/* 32 bits */
+	.word 0xfffe1030
+REG_FUNC_MUX_CTRL_C:		/* 32 bits */
+	.word 0xfffe1034
+REG_FUNC_MUX_CTRL_D:		/* 32 bits */
+	.word 0xfffe1038
+REG_PULL_DWN_CTRL_0:		/* 32 bits */
+	.word 0xfffe1040
+REG_PULL_DWN_CTRL_1:		/* 32 bits */
+	.word 0xfffe1044
+REG_PULL_DWN_CTRL_2:		/* 32 bits */
+	.word 0xfffe1048
+REG_PULL_DWN_CTRL_3:		/* 32 bits */
+	.word 0xfffe104c
+REG_VOLTAGE_CTRL_0:		/* 32 bits */
+	.word 0xfffe1060
+REG_TEST_DBG_CTRL_0:		/* 32 bits */
+	.word 0xfffe1070
+REG_MOD_CONF_CTRL_0:		/* 32 bits */
+	.word 0xfffe1080
+REG_TC_IMIF_PRIO:		/* 32 bits */
+	.word 0xfffecc00
+REG_TC_EMIFS_PRIO:		/* 32 bits */
+	.word 0xfffecc04
+REG_TC_EMIFF_PRIO:		/* 32 bits */
+	.word 0xfffecc08
+REG_TC_EMIFS_CONFIG:		/* 32 bits */
+	.word 0xfffecc0c
+REG_TC_EMIFS_CS0_CONFIG:	/* 32 bits */
+	.word 0xfffecc10
+REG_TC_EMIFS_CS1_CONFIG:	/* 32 bits */
+	.word 0xfffecc14
+REG_TC_EMIFS_CS2_CONFIG:	/* 32 bits */
+	.word 0xfffecc18
+REG_TC_EMIFS_CS3_CONFIG:	/* 32 bits */
+	.word 0xfffecc1c
+REG_TC_EMIFF_SDRAM_CONFIG:	/* 32 bits */
+	.word 0xfffecc20
+REG_TC_EMIFF_MRS:		/* 32 bits */
+	.word 0xfffecc24
+/* MPU clock/reset/power mode control registers */
+REG_ARM_CKCTL:			/* 16 bits */
+	.word 0xfffece00
+REG_ARM_IDLECT2:		/* 16 bits */
+	.word 0xfffece08
+REG_ARM_RSTCT2:			/* 16 bits */
+	.word 0xfffece14
+REG_ARM_SYSST:			/* 16 bits */
+	.word 0xfffece18
+/* DPLL control registers */
+REG_DPLL1_CTL:			/* 16 bits */
+	.word 0xfffecf00
+/* identification code register */
+REG_IDCODE:			/* 32 bits */
+	.word 0xfffed404
+
+/* Innovator specific */
+REG_FPGA_LED_DIGIT:		/* 8 bits (not used on Innovator) */
+	.word 0x08000003
+REG_FPGA_POWER:			/* 8 bits */
+	.word 0x08000005
+REG_FPGA_AUDIO:			/* 8 bits (not used on Innovator) */
+	.word 0x0800000c
+REG_FPGA_DIP_SWITCH:		/* 8 bits (not used on Innovator) */
+	.word 0x0800000e
+
+VAL_COMP_MODE_CTRL_0:
+	.word 0x0000eaef
+VAL_FUNC_MUX_CTRL_4:
+	.word 0x00000000
+VAL_FUNC_MUX_CTRL_5:
+	.word 0x00000000
+VAL_FUNC_MUX_CTRL_6:
+	.word 0x00000001
+VAL_FUNC_MUX_CTRL_7:
+	.word 0x00000000
+VAL_FUNC_MUX_CTRL_8:
+	.word 0x10001200
+VAL_FUNC_MUX_CTRL_9:
+	.word 0x01201012
+VAL_FUNC_MUX_CTRL_A:
+	.word 0x00000248
+VAL_FUNC_MUX_CTRL_B:
+	.word 0x00000248
+VAL_FUNC_MUX_CTRL_C:
+	.word 0x09000000
+VAL_FUNC_MUX_CTRL_D:
+	.word 0x00000000
+VAL_PULL_DWN_CTRL_0:
+	.word 0x11a10000
+VAL_PULL_DWN_CTRL_1:
+	.word 0x2e047fff
+VAL_PULL_DWN_CTRL_2:
+	.word 0xffd7d3e6
+VAL_PULL_DWN_CTRL_3:
+	.word 0x00003f03
+VAL_VOLTAGE_CTRL_0:
+	.word 0x00000007
+VAL_TEST_DBG_CTRL_0:
+	/*  See Errata 4.13, This works around a SRAM bug, for chips below ES2.5 .
+	 *   This slows down internal SRAM accesses.
+	 */
+	.word 0x00000007
+VAL_MOD_CONF_CTRL_0:
+	.word 0x0b000008
+VAL_ARM_CKCTL:
+	.word 0x010f
+VAL_DPLL1_CTL:
+	.word 0x2710
+VAL_TC_EMIFS_CS1_CONFIG_PRELIM:
+	.word 0x00001149
+VAL_TC_EMIFS_CS2_CONFIG_PRELIM:
+	.word 0x00004158
+VAL_TC_EMIFS_CS0_CONFIG:
+	.word 0x002130b0
+VAL_TC_EMIFS_CS1_CONFIG:
+	.word 0x0000f559
+VAL_TC_EMIFS_CS2_CONFIG:
+	.word 0x000055f0
+VAL_TC_EMIFS_CS3_CONFIG:
+	.word 0x00003331
+VAL_TC_EMIFF_SDRAM_CONFIG:
+	.word 0x010290fc
+VAL_TC_EMIFF_MRS:
+	.word 0x00000027

board/omap1510inn/u-boot.lds

@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2001
- * Kyle Harris, kharris@nexus-tech.net
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -21,14 +21,38 @@
  * MA 02111-1307 USA
  */
 
-#ifndef	_CMD_AUTOSCRIPT_H_
-#define	_CMD_AUTOSCRIPT_H_
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
 
-#define AUTOSCRIPT_MAGIC	0x09011962
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm925t/start.o	(.text)
+	  *(.text)
+	}
 
-#if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT)
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
 
-int autoscript (ulong addr);
-#endif
+	. = ALIGN(4);
+	.data : { *(.data) }
 
-#endif	/* _CMD_AUTOSCRIPT_H_ */
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+	armboot_end_data = .;
+
+	. = ALIGN(4);
+	.bss : { *(.bss) }
+
+	armboot_end = .;
+}

board/pcippc2/pcippc2.c

@@ -233,8 +233,8 @@ int do_wd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return 1;
 }
 
-cmd_tbl_t U_BOOT_CMD(wd) = MK_CMD_ENTRY(
-	"wd",	2,	1,	do_wd,
+U_BOOT_CMD(
+	wd,	2,	1,	do_wd,
 	"wd      - check and set watchdog\n",
 	"on   - switch watchDog on\n"
 	"wd off  - switch watchdog off\n"

board/pn62/cmd_pn62.c

@@ -51,8 +51,8 @@ int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
     set_led (number, function);
     return 0;
 }
-cmd_tbl_t U_BOOT_CMD(led) = MK_CMD_ENTRY(
-	"led"    ,	3,	1,	do_led,
+U_BOOT_CMD(
+	led    ,	3,	1,	do_led,
 	"led     - set LED 0..11 on the PN62 board\n",
 	"i fun\n"
 	"    - set 'i'th LED to function 'fun'\n"
@@ -165,8 +165,8 @@ int do_loadpci (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
     return rcode;
 }
 
-cmd_tbl_t U_BOOT_CMD(loadpci) = MK_CMD_ENTRY(
-	"loadpci",	2,	1,	do_loadpci,
+U_BOOT_CMD(
+	loadpci,	2,	1,	do_loadpci,
 	"loadpci - load binary file over PCI\n",
 	"[addr]\n"
 	"    - load binary file over PCI to address 'addr'\n"

board/r360mpi/r360mpi.c

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2001
+ * (C) Copyright 2001-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -37,9 +37,9 @@
 /*
  *  Memory Controller Using
  *
- *  CS0 - Flash memory            (0x40000000)
- *  CS1 - SDRAM                   (0x00000000}
- *  CS2 -
+ *  CS0 - Flash memory		(0x40000000)
+ *  CS1 - FLASH memory		(0x????????)
+ *  CS2 - SDRAM			(0x00000000)
  *  CS3 -
  *  CS4 -
  *  CS5 -
@@ -148,7 +148,7 @@ long int initdram (int board_type)
 	udelay (1000);
 
 	/*
-	 * Check Bank 0 Memory Size for re-configuration
+	 * Check Bank 2 Memory Size for re-configuration
 	 *
 	 * try 8 column mode
 	 */
@@ -443,8 +443,8 @@ int do_kbd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	return 0;
 }
 
-cmd_tbl_t U_BOOT_CMD(kbd) = MK_CMD_ENTRY(
-	"kbd",	1,	1,	do_kbd,
+U_BOOT_CMD(
+	kbd,	1,	1,	do_kbd,
 	"kbd     - read keyboard status\n",
 	NULL
 );

board/sacsng/sacsng.c

@@ -816,3 +816,15 @@ int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
 #endif /* CFG_CMD_SPI */
 
 #endif /* CONFIG_MISC_INIT_R */
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+	return 0;	/* No hotkeys supported */
+}
+
+#endif

board/siemens/common/fpga.c

@@ -291,8 +291,8 @@ int do_fpga (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
     return 1;
 }
 
-cmd_tbl_t U_BOOT_CMD(fpga) = MK_CMD_ENTRY(
-	"fpga",	4,	1,	do_fpga,
+U_BOOT_CMD(
+	fpga,	4,	1,	do_fpga,
 	"fpga    - access FPGA(s)\n",
 	"fpga status [name] - print FPGA status\n"
 	"fpga reset  [name] - reset FPGA\n"

board/siemens/pcu_e/pcu_e.c

@@ -26,7 +26,6 @@
 #include <commproc.h>
 #include <i2c.h>
 #include <command.h>
-#include <cmd_bsp.h>
 
 /* ------------------------------------------------------------------------- */
 
@@ -433,8 +432,8 @@ int do_puma (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	printf ("Usage:\n%s\n", cmdtp->usage);
 	return 1;
 }
-cmd_tbl_t U_BOOT_CMD(puma) = MK_CMD_ENTRY(
-	"puma",	4,	1,	do_puma,
+U_BOOT_CMD(
+	puma,	4,	1,	do_puma,
 	"puma    - access PUMA FPGA\n",
 	"status - print PUMA status\n"
 	"puma load addr len - load PUMA configuration data\n"

board/sl8245/Makefile

@@ -28,7 +28,7 @@ LIB	= lib$(BOARD).a
 OBJS 	= $(BOARD).o flash.o
 
 $(LIB):	.depend $(OBJS)
-	$(AR) crv $@ $^
+	$(AR) crv $@ $(OBJS)
 
 #########################################################################
 

board/sl8245/u-boot.lds

@@ -102,6 +102,10 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
   __start___ex_table = .;
   __ex_table : { *(__ex_table) }
   __stop___ex_table = .;
@@ -125,4 +129,3 @@ SECTIONS
   _end = . ;
   PROVIDE (end = .);
 }
-

board/tqm8xx/flash.c

@@ -209,6 +209,10 @@ void flash_print_info  (flash_info_t *info)
 #ifdef CONFIG_TQM8xxM	/* mirror bit flash */
 	case FLASH_AMLV128U:	printf ("AM29LV128ML (128Mbit, uniform sector size)\n");
 				break;
+	case FLASH_AMLV320U:	printf ("AM29LV320ML (32Mbit, uniform sector size)\n");
+				break;
+	case FLASH_AMLV640U:	printf ("AM29LV640ML (64Mbit, uniform sector size)\n");
+				break;
 # else	/* ! TQM8xxM */
 	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
 				break;
@@ -218,15 +222,15 @@ void flash_print_info  (flash_info_t *info)
 				break;
 	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
 				break;
-	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
-				break;
 	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
 				break;
 	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
 				break;
 #endif	/* TQM8xxM */
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
 	default:		printf ("Unknown Chip Type\n");
 				break;
 	}
@@ -294,6 +298,14 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 	switch (value) {
 #ifdef CONFIG_TQM8xxM	/* mirror bit flash */
 	case AMD_ID_MIRROR:
+		/* Special case for AMLV320MH/L */
+		if ((addr[14] & 0x00ff00ff) == 0x001d001d &&
+			(addr[15] & 0x00ff00ff) == 0x00000000) {
+			info->flash_id += FLASH_AMLV320U;
+			info->sector_count = 64;
+			info->size = 0x00800000; /* => 8 MB */
+			break;
+		}
 		switch(addr[14]) {
 		case AMD_ID_LV128U_2:
 			if (addr[15] != AMD_ID_LV128U_3) {
@@ -305,6 +317,16 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 				info->size = 0x02000000;
 			}
 			break;				/* => 32 MB		*/
+		case AMD_ID_LV640U_2:
+			if (addr[15] != AMD_ID_LV640U_3) {
+				info->flash_id = FLASH_UNKNOWN;
+			}
+			else {
+				info->flash_id += FLASH_AMLV640U;
+				info->sector_count = 128;
+				info->size = 0x01000000;
+			}
+			break;				/* => 16 MB		*/
 		default:
 			info->flash_id = FLASH_UNKNOWN;
 			break;
@@ -335,18 +357,6 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		info->size = 0x00200000;
 		break;				/* => 2 MB		*/
 
-	case AMD_ID_LV160T:
-		info->flash_id += FLASH_AM160T;
-		info->sector_count = 35;
-		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
-
-	case AMD_ID_LV160B:
-		info->flash_id += FLASH_AM160B;
-		info->sector_count = 35;
-		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
-
 	case AMD_ID_LV320T:
 		info->flash_id += FLASH_AM320T;
 		info->sector_count = 71;
@@ -359,6 +369,19 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		info->size = 0x00800000;
 		break;				/* => 8 MB		*/
 #endif	/* TQM8xxM */
+
+	case AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
 	default:
 		info->flash_id = FLASH_UNKNOWN;
 		return (0);			/* => no or unknown flash */
@@ -371,6 +394,8 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		switch (info->flash_id & FLASH_TYPEMASK) {
 			/* only known types here - no default */
 		case FLASH_AMLV128U:
+		case FLASH_AMLV640U:
+		case FLASH_AMLV320U:
 			for (i = 0; i < info->sector_count; i++) {
 				info->start[i] = base;
 				base += 0x20000;
@@ -381,7 +406,6 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 # else	/* ! TQM8xxM */
 	case AMD_ID_LV400B:
 	case AMD_ID_LV800B:
-	case AMD_ID_LV160B:
 		/* set sector offsets for bottom boot block type	*/
 		info->start[0] = base + 0x00000000;
 		info->start[1] = base + 0x00008000;
@@ -393,7 +417,6 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		break;
 	case AMD_ID_LV400T:
 	case AMD_ID_LV800T:
-	case AMD_ID_LV160T:
 		/* set sector offsets for top boot block type		*/
 		i = info->sector_count - 1;
 		info->start[i--] = base + info->size - 0x00008000;
@@ -428,6 +451,26 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		}
 		break;
 #endif	/* TQM8xxM */
+	case AMD_ID_LV160B:
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+		break;
+	case AMD_ID_LV160T:
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+		break;
 	default:
 		return (0);
 		break;

board/trab/trab.c

@@ -130,6 +130,11 @@ int board_init ()
 	}
 #endif	/* CONFIG_MODEM_SUPPORT */
 
+#ifdef CONFIG_DRIVER_S3C24X0_I2C
+	/* Configure I/O ports PG5 und PG6 for I2C */
+ 	gpio->PGCON = (gpio->PGCON & 0x003c00) | 0x003c00;
+#endif /* CONFIG_DRIVER_S3C24X0_I2C */
+
 	return 0;
 }
 
@@ -298,8 +303,8 @@ int do_kbd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	return 0;
 }
 
-cmd_tbl_t U_BOOT_CMD(kbd) = MK_CMD_ENTRY(
- 	"kbd",	1,	1,	do_kbd,
+U_BOOT_CMD(
+ 	kbd,	1,	1,	do_kbd,
  	"kbd     - read keyboard status\n",
  	NULL
 );

board/w7o/cmd_vpd.c

@@ -27,7 +27,6 @@
 #if (CONFIG_COMMANDS & CFG_CMD_BSP)
 
 #include "vpd.h"
-#include "cmd_bsp.h"
 
 /* ======================================================================
  * Interpreter command to retrieve board specific Vital Product Data, "VPD"
@@ -57,8 +56,8 @@ int do_vpd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	return 1;
 }
 
-cmd_tbl_t U_BOOT_CMD(vpd) = MK_CMD_ENTRY(
-	  "vpd",	2,	1,	do_vpd,
+U_BOOT_CMD(
+	  vpd,	2,	1,	do_vpd,
 	  "vpd     - Read Vital Product Data\n",
 	  "[dev_addr]\n"
 	  "        - Read VPD Data from default address, or device address 'dev_addr'.\n"

common/cmd_autoscript.c

@@ -47,7 +47,6 @@
 #include <hush.h>
 #endif
 
-#define AUTOSCRIPT_MAGIC	0x09011962
 #if defined(CONFIG_AUTOSCRIPT) || \
 	 (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT )
 
@@ -172,8 +171,8 @@ do_autoscript (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 }
 
 #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT)
-cmd_tbl_t U_BOOT_CMD(AUTOSCRIPT) = MK_CMD_ENTRY(
-	"autoscr", 2, 0,	do_autoscript,
+U_BOOT_CMD(
+	autoscr, 2, 0,	do_autoscript,
 	"autoscr - run script from memory\n",
 	"[addr] - run script starting at addr"
 	" - A valid autoscr header must be present\n"

common/cmd_bdinfo.c

@@ -172,10 +172,9 @@ static void print_str(const char *name, const char *str)
 
 /* -------------------------------------------------------------------- */
 
-cmd_tbl_t U_BOOT_CMD(BDINFO) =  MK_CMD_ENTRY(
-	"bdinfo",	1,	1,	do_bdinfo,
+U_BOOT_CMD(
+	bdinfo,	1,	1,	do_bdinfo,
 	"bdinfo  - print Board Info structure\n",
 	NULL
 );
 #endif	/* CFG_CMD_BDI */
-

common/cmd_bedbug.c

@@ -108,8 +108,8 @@ int do_bedbug_dis (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
   dis_last_len = len;
   return 0;
 } /* do_bedbug_dis */
-cmd_tbl_t U_BOOT_CMD(DIS) = MK_CMD_ENTRY(
-	"ds",      3,      1,      do_bedbug_dis,
+U_BOOT_CMD(
+	ds,      3,      1,      do_bedbug_dis,
 	"ds      - disassemble memory\n",
 	"ds <address> [# instructions]\n"
 );
@@ -165,8 +165,8 @@ int do_bedbug_asm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
   }
   return rcode;
 } /* do_bedbug_asm */
-cmd_tbl_t U_BOOT_CMD(ASM) = MK_CMD_ENTRY(
-	"as",      2,      0,      do_bedbug_asm,
+U_BOOT_CMD(
+	as,      2,      0,      do_bedbug_asm,
 	"as      - assemble memory\n",
 	"as <address>\n"
 );
@@ -184,8 +184,8 @@ int do_bedbug_break (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
     return 0;
 
 } /* do_bedbug_break */
-cmd_tbl_t U_BOOT_CMD(BREAK) = MK_CMD_ENTRY(
-	"break",      3,      0,      do_bedbug_break,
+U_BOOT_CMD(
+	break,      3,      0,      do_bedbug_break,
 	"break   - set or clear a breakpoint\n",
 	" - Set or clear a breakpoint\n"
 	"break <address> - Break at an address\n"
@@ -288,8 +288,8 @@ int do_bedbug_continue (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
   bug_ctx.stopped = 0;
   return 0;
 } /* do_bedbug_continue */
-cmd_tbl_t U_BOOT_CMD(CONTINUE) = MK_CMD_ENTRY(
-	"continue",      1,      0,      do_bedbug_continue,
+U_BOOT_CMD(
+	continue,      1,      0,      do_bedbug_continue,
 	"continue- continue from a breakpoint\n",
 	" - continue from a breakpoint.\n"
 );
@@ -320,8 +320,8 @@ int do_bedbug_step (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
   bug_ctx.stopped = 0;
   return 0;
 } /* do_bedbug_step */
-cmd_tbl_t U_BOOT_CMD(STEP) = MK_CMD_ENTRY(
-	"step",      1,      1,      do_bedbug_step,
+U_BOOT_CMD(
+	step,      1,      1,      do_bedbug_step,
 	"step    - single step execution.\n",
 	" - single step execution.\n"
 );
@@ -352,8 +352,8 @@ int do_bedbug_next (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
   bug_ctx.stopped = 0;
   return 0;
 } /* do_bedbug_next */
-cmd_tbl_t U_BOOT_CMD(NEXT) = MK_CMD_ENTRY(
-	"next",      1,      1,      do_bedbug_next,
+U_BOOT_CMD(
+	next,      1,      1,      do_bedbug_next,
 	"next    - single step execution, stepping over subroutines.\n",
 	" - single step execution, stepping over subroutines.\n"
 );
@@ -401,8 +401,8 @@ int do_bedbug_stack (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
   }
   return 0;
 } /* do_bedbug_stack */
-cmd_tbl_t U_BOOT_CMD(STACK) = MK_CMD_ENTRY(
-	"where",     1,      1,      do_bedbug_stack,
+U_BOOT_CMD(
+	where,     1,      1,      do_bedbug_stack,
 	"where   - Print the running stack.\n",
 	" - Print the running stack.\n"
 );
@@ -424,8 +424,8 @@ int do_bedbug_rdump (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
   show_regs( bug_ctx.regs );
   return 0;
 } /* do_bedbug_rdump */
-cmd_tbl_t U_BOOT_CMD(RDUMP) = MK_CMD_ENTRY(
-	"rdump",     1,      1,      do_bedbug_rdump,
+U_BOOT_CMD(
+	rdump,     1,      1,      do_bedbug_rdump,
 	"rdump   - Show registers.\n",
 	" - Show registers.\n"
 );

common/cmd_bmp.c

@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2002
- * Dtlev Zundel, DENX Software Engineering, dzu@denx.de.
+ * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -73,6 +73,13 @@ int do_bmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	}
 }
 
+U_BOOT_CMD(
+	bmp,	3,	1,	do_bmp,
+	"bmp     - manipulate BMP image data\n",
+	"info <imageAddr>    - display image info\n"
+	"bmp display <imageAddr> - display image\n"
+);
+
 /*
  * Subroutine:  bmp_info
  *

common/cmd_boot.c

@@ -26,7 +26,6 @@
  */
 #include <common.h>
 #include <command.h>
-#include <cmd_autoscript.h>
 #include <net.h>
 #include <syscall.h>
 
@@ -60,8 +59,8 @@ int do_go (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 /* -------------------------------------------------------------------- */
 
-cmd_tbl_t U_BOOT_CMD(GO) = MK_CMD_ENTRY(
-	"go", CFG_MAXARGS, 1,	do_go,
+U_BOOT_CMD(
+	go, CFG_MAXARGS, 1,	do_go,
 	"go      - start application at address 'addr'\n",
 	"addr [arg ...]\n    - start application at address 'addr'\n"
 	"      passing 'arg' as arguments\n"
@@ -69,8 +68,8 @@ cmd_tbl_t U_BOOT_CMD(GO) = MK_CMD_ENTRY(
 
 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 
-cmd_tbl_t U_BOOT_CMD(RESET) = MK_CMD_ENTRY(
-	"reset", 1, 0,	do_reset,
+U_BOOT_CMD(
+	reset, 1, 0,	do_reset,
 	"reset   - Perform RESET of the CPU\n",
 	NULL
 );

common/cmd_bootm.c

@@ -381,8 +381,8 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return 1;
 }
 
-cmd_tbl_t U_BOOT_CMD(BOOTM) =  MK_CMD_ENTRY(
- 	"bootm",	CFG_MAXARGS,	1,	do_bootm,
+U_BOOT_CMD(
+ 	bootm,	CFG_MAXARGS,	1,	do_bootm,
  	"bootm   - boot application image from memory\n",
  	"[addr [arg ...]]\n    - boot application image stored in memory\n"
  	"        passing arguments 'arg ...'; when booting a Linux kernel,\n"
@@ -481,6 +481,10 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
 		kbd->bi_sccfreq /= 1000000L;
 		kbd->bi_vco     /= 1000000L;
 #endif /* CONFIG_8260 */
+#if defined(CONFIG_MPC5XXXX)
+		kbd->bi_ipbfreq /= 1000000L;
+		kbd->bi_pcifreq /= 1000000L;
+#endif /* CONFIG_MPC5XXXX */
 	}
 
 	kernel = (void (*)(bd_t *, ulong, ulong, ulong, ulong))hdr->ih_ep;
@@ -872,15 +876,15 @@ int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return rcode;
 }
 
-cmd_tbl_t U_BOOT_CMD(BOOT) = MK_CMD_ENTRY(
- 	"boot",	1,	1,	do_bootd,
+U_BOOT_CMD(
+ 	boot,	1,	1,	do_bootd,
  	"boot    - boot default, i.e., run 'bootcmd'\n",
 	NULL
 );
 
 /* keep old command name "bootd" for backward compatibility */
-cmd_tbl_t U_BOOT_CMD(BOOTD) = MK_CMD_ENTRY(
- 	"bootd", 1,	1,	do_bootd,
+U_BOOT_CMD(
+ 	bootd, 1,	1,	do_bootd,
  	"bootd   - boot default, i.e., run 'bootcmd'\n",
 	NULL
 );
@@ -945,8 +949,9 @@ static int image_info (ulong addr)
 	printf ("OK\n");
 	return 0;
 }
-cmd_tbl_t U_BOOT_CMD(IMINFO) = MK_CMD_ENTRY(
-	"iminfo",	CFG_MAXARGS,	1,	do_iminfo,
+
+U_BOOT_CMD(
+	iminfo,	CFG_MAXARGS,	1,	do_iminfo,
 	"iminfo  - print header information for application image\n",
 	"addr [addr ...]\n"
 	"    - print header information for application image starting at\n"
@@ -1023,6 +1028,7 @@ print_type (image_header_t *hdr)
 	case IH_CPU_SH:		arch = "SuperH";		break;
 	case IH_CPU_SPARC:	arch = "SPARC";			break;
 	case IH_CPU_SPARC64:	arch = "SPARC 64 Bit";		break;
+	case IH_CPU_M68K:	arch = "M68K"; 			break;
 	default:		arch = "Unknown Architecture";	break;
 	}
 

common/cmd_cache.c

@@ -95,15 +95,15 @@ static int on_off (const char *s)
 }
 
 
-cmd_tbl_t U_BOOT_CMD(ICACHE) = MK_CMD_ENTRY(
-	"icache",   2,   1,     do_icache,
+U_BOOT_CMD(
+	icache,   2,   1,     do_icache,
 	"icache  - enable or disable instruction cache\n",
 	"[on, off]\n"
 	"    - enable or disable instruction cache\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(DCACHE) = MK_CMD_ENTRY(
-	"dcache",   2,   1,     do_dcache,
+U_BOOT_CMD(
+	dcache,   2,   1,     do_dcache,
 	"dcache  - enable or disable data cache\n",
 	"[on, off]\n"
 	"    - enable or disable data (writethrough) cache\n"

common/cmd_console.c

@@ -62,8 +62,8 @@ int do_coninfo (cmd_tbl_t * cmd, int flag, int argc, char *argv[])
 
 /***************************************************/
 
-cmd_tbl_t U_BOOT_CMD(CONINFO) = MK_CMD_ENTRY(
-	"coninfo",	3,	1,	do_coninfo,
+U_BOOT_CMD(
+	coninfo,	3,	1,	do_coninfo,
 	"coninfo - print console devices and informations\n",
 	""
 );

common/cmd_date.c

@@ -191,8 +191,8 @@ int mk_date (char *datestr, struct rtc_time *tmp)
 
 /***************************************************/
 
-cmd_tbl_t U_BOOT_CMD(DATE) = MK_CMD_ENTRY(
-	"date",	2,	1,	do_date,
+U_BOOT_CMD(
+	date,	2,	1,	do_date,
 	"date    - get/set/reset date & time\n",
 	"[MMDDhhmm[[CC]YY][.ss]]\ndate reset\n"
 	"  - without arguments: print date & time\n"

common/cmd_dcr.c

@@ -106,13 +106,13 @@ int do_setdcr ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 /***************************************************/
 
-cmd_tbl_t U_BOOT_CMD(GETDCR) = MK_CMD_ENTRY(
-	"getdcr",	2,	1,	do_getdcr,
+U_BOOT_CMD(
+	getdcr,	2,	1,	do_getdcr,
 	"getdcr  - Get an IBM PPC 4xx DCR's value\n",
 	"dcrn - return a DCR's value.\n"
 );
-cmd_tbl_t U_BOOT_CMD(SETDCR) = MK_CMD_ENTRY(
-	"setdcr",	2,	1,	do_setdcr,
+U_BOOT_CMD(
+	setdcr,	2,	1,	do_setdcr,
 	"setdcr  - Set an IBM PPC 4xx DCR's value\n",
 	"dcrn - set a DCR's value.\n"
 );

common/cmd_diag.c

@@ -66,8 +66,8 @@ int do_diag (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 }
 /***************************************************/
 
-cmd_tbl_t U_BOOT_CMD(DIAG) = MK_CMD_ENTRY(
-	"diag",	CFG_MAXARGS,	0,	do_diag,
+U_BOOT_CMD(
+	diag,	CFG_MAXARGS,	0,	do_diag,
 	"diag    - perform board diagnostics\n",
 	     "    - print list of available tests\n"
 	"diag [test1 [test2]]\n"

common/cmd_doc.c

@@ -170,8 +170,8 @@ int do_doc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return rcode;
     }
 }
-cmd_tbl_t U_BOOT_CMD(DOC) = MK_CMD_ENTRY(
-	"doc",	5,	1,	do_doc,
+U_BOOT_CMD(
+	doc,	5,	1,	do_doc,
 	"doc     - Disk-On-Chip sub-system\n",
 	"info  - show available DOC devices\n"
 	"doc device [dev] - show or set current device\n"
@@ -284,8 +284,8 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return rcode;
 }
 
-cmd_tbl_t U_BOOT_CMD(DOCBOOT) = MK_CMD_ENTRY(
-	"docboot",	4,	1,	do_docboot,
+U_BOOT_CMD(
+	docboot,	4,	1,	do_docboot,
 	"docboot - boot from DOC device\n",
 	"loadAddr dev\n"
 );

common/cmd_dtt.c

@@ -47,8 +47,8 @@ int do_dtt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 
 /***************************************************/
 
-cmd_tbl_t U_BOOT_CMD(DTT) = MK_CMD_ENTRY(
-	  "dtt",	1,	1,	do_dtt,
+U_BOOT_CMD(
+	  dtt,	1,	1,	do_dtt,
 	  "dtt     - Digital Thermometer and Themostat\n",
 	  "        - Read temperature from digital thermometer and thermostat.\n"
 );

common/cmd_eeprom.c

@@ -376,16 +376,16 @@ void eeprom_init  (void)
 #if (CONFIG_COMMANDS & CFG_CMD_EEPROM)
 
 #ifdef CFG_I2C_MULTI_EEPROMS
-cmd_tbl_t U_BOOT_CMD(EEPROM) = MK_CMD_ENTRY(
-	"eeprom",	6,	1,	do_eeprom,
+U_BOOT_CMD(
+	eeprom,	6,	1,	do_eeprom,
 	"eeprom  - EEPROM sub-system\n",
 	"read  devaddr addr off cnt\n"
 	"eeprom write devaddr addr off cnt\n"
 	"       - read/write `cnt' bytes from `devaddr` EEPROM at offset `off'\n"
 );
 #else /* One EEPROM */
-cmd_tbl_t U_BOOT_CMD(EEPROM) = MK_CMD_ENTRY(
-	"eeprom",	5,	1,	do_eeprom,
+U_BOOT_CMD(
+	eeprom,	5,	1,	do_eeprom,
 	"eeprom  - EEPROM sub-system\n",
 	"read  addr off cnt\n"
 	"eeprom write addr off cnt\n"

common/cmd_elf.c

@@ -321,14 +321,14 @@ unsigned long load_elf_image (unsigned long addr)
 }
 
 /* ====================================================================== */
-cmd_tbl_t U_BOOT_CMD(BOOTELF) = MK_CMD_ENTRY(
-	"bootelf",      2,      0,      do_bootelf,
+U_BOOT_CMD(
+	bootelf,      2,      0,      do_bootelf,
 	"bootelf - Boot from an ELF image in memory\n",
 	" [address] - load address of ELF image.\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(BOOTVX) = MK_CMD_ENTRY(
-	"bootvx",      2,      0,      do_bootvx,
+U_BOOT_CMD(
+	bootvx,      2,      0,      do_bootvx,
 	"bootvx  - Boot vxWorks from an ELF image\n",
 	" [address] - load address of vxWorks ELF image.\n"
 );

common/cmd_fat.c

@@ -26,7 +26,6 @@
  */
 #include <common.h>
 #include <command.h>
-#include <cmd_autoscript.h>
 #include <s_record.h>
 #include <net.h>
 #include <ata.h>
@@ -63,6 +62,14 @@ int do_fat_fsload (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return size;
 }
 
+U_BOOT_CMD(
+	fatload,	4,	0,	do_fat_fsload,
+	"fatload - load binary file from a dos filesystem\n",
+	"[ off ] [ filename ]\n"
+	"    - load binary file from dos filesystem\n"
+	"      with offset 'off'\n"
+);
+
 int do_fat_ls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	char *filename = "/";
@@ -76,6 +83,13 @@ int do_fat_ls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return (ret);
 }
 
+U_BOOT_CMD(
+	fatls,	2,	1,	do_fat_ls,
+	"fatls   - list files in a directory (default /)\n",
+	"[ directory ]\n"
+	"    - list files in a directory\n"
+);
+
 int do_fat_fsinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	int ret;
@@ -87,6 +101,13 @@ int do_fat_fsinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return (ret);
 }
 
+U_BOOT_CMD(
+	fatinfo,	1,	1,	do_fat_fsinfo,
+	"fatinfo - print information about filesystem\n",
+	"\n"
+	"    - print information about filesystem\n"
+);
+
 #ifdef NOT_IMPLEMENTED_YET
 /* find first device whose first partition is a DOS filesystem */
 int find_fat_partition (void)

common/cmd_fdc.c

@@ -888,8 +888,8 @@ int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 #if (CONFIG_COMMANDS & CFG_CMD_FDC)
 
-cmd_tbl_t U_BOOT_CMD(FDC) = MK_CMD_ENTRY(
-	"fdcboot",	3,	1,	do_fdcboot,
+U_BOOT_CMD(
+	fdcboot,	3,	1,	do_fdcboot,
 	"fdcboot - boot from floppy device\n",
 	"loadAddr drive\n"
 );

common/cmd_fdos.c

@@ -142,14 +142,14 @@ int do_fdosls(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
     return (dos_dir ());
 }
 
-cmd_tbl_t U_BOOT_CMD(FDOS_BOOT) = MK_CMD_ENTRY(
-	"fdosboot",	3,	0,	do_fdosboot,
+U_BOOT_CMD(
+	fdosboot,	3,	0,	do_fdosboot,
 	"fdosboot- boot from a dos floppy file\n",
 	"[loadAddr] [filename]\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(FDOS_LS) = MK_CMD_ENTRY(
-	"fdosls",	2,	0,	do_fdosls,
+U_BOOT_CMD(
+	fdosls,	2,	0,	do_fdosls,
 	"fdosls  - list files in a directory\n",
 	"[directory]\n"
 );

common/cmd_flash.c

@@ -440,15 +440,15 @@ int flash_sect_protect (int p, ulong addr_first, ulong addr_last)
 
 /**************************************************/
 
-cmd_tbl_t U_BOOT_CMD(FLINFO) = MK_CMD_ENTRY(
-	"flinfo",    2,    1,    do_flinfo,
+U_BOOT_CMD(
+	flinfo,    2,    1,    do_flinfo,
 	"flinfo  - print FLASH memory information\n",
 	"\n    - print information for all FLASH memory banks\n"
 	"flinfo N\n    - print information for FLASH memory bank # N\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(ERASE) = MK_CMD_ENTRY(
-	"erase",   3,   1,  do_flerase,
+U_BOOT_CMD(
+	erase,   3,   1,  do_flerase,
 	"erase   - erase FLASH memory\n",
 	"start end\n"
 	"    - erase FLASH from addr 'start' to addr 'end'\n"
@@ -457,8 +457,8 @@ cmd_tbl_t U_BOOT_CMD(ERASE) = MK_CMD_ENTRY(
 	"erase all\n    - erase all FLASH banks\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(PROTECT) = MK_CMD_ENTRY(
-	"protect",  4,  1,   do_protect,
+U_BOOT_CMD(
+	protect,  4,  1,   do_protect,
 	"protect - enable or disable FLASH write protection\n",
 	"on  start end\n"
 	"    - protect FLASH from addr 'start' to addr 'end'\n"

common/cmd_fpga.c

@@ -27,7 +27,6 @@
  */
 #include <common.h>
 #include <command.h>
-#include <cmd_bsp.h>
 #if (CONFIG_COMMANDS & CFG_CMD_NET)
 #include <net.h>
 #endif
@@ -155,8 +154,8 @@ static int fpga_get_op( char *opstr )
 	return op;
 }
 
-cmd_tbl_t U_BOOT_CMD(FPGA) = MK_CMD_ENTRY(
-	"fpga",    6,     1,     do_fpga,
+U_BOOT_CMD(
+	fpga,    6,     1,     do_fpga,
 	"fpga   - loadable FPGA image support\n",
 	"fpga [operation type] [device number] [image address] [image size]\n"
 	"fpga operations:\n"

common/cmd_i2c.c

@@ -867,38 +867,38 @@ int do_sdram  ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 /***************************************************/
 
-cmd_tbl_t U_BOOT_CMD(IMD) = MK_CMD_ENTRY(
-	"imd",	4,	1,	do_i2c_md,		\
+U_BOOT_CMD(
+	imd,	4,	1,	do_i2c_md,		\
 	"imd     - i2c memory display\n",				\
 	"chip address[.0, .1, .2] [# of objects]\n    - i2c memory display\n" \
 );
 
-cmd_tbl_t U_BOOT_CMD(IMM) = MK_CMD_ENTRY(
- 	"imm",	3,	1,	do_i2c_mm,
+U_BOOT_CMD(
+ 	imm,	3,	1,	do_i2c_mm,
 	"imm     - i2c memory modify (auto-incrementing)\n",
 	"chip address[.0, .1, .2]\n"
 	"    - memory modify, auto increment address\n"
 );
-cmd_tbl_t U_BOOT_CMD(INM) = MK_CMD_ENTRY(
-	"inm",	3,	1,	do_i2c_nm,
+U_BOOT_CMD(
+	inm,	3,	1,	do_i2c_nm,
 	"inm     - memory modify (constant address)\n",
 	"chip address[.0, .1, .2]\n    - memory modify, read and keep address\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(IMW) = MK_CMD_ENTRY(
-	"imw",	5,	1,	do_i2c_mw,
+U_BOOT_CMD(
+	imw,	5,	1,	do_i2c_mw,
 	"imw     - memory write (fill)\n",
 	"chip address[.0, .1, .2] value [count]\n    - memory write (fill)\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(ICRC) = MK_CMD_ENTRY(
-	"icrc32",	5,	1,	do_i2c_crc,
+U_BOOT_CMD(
+	icrc32,	5,	1,	do_i2c_crc,
 	"icrc32  - checksum calculation\n",
 	"chip address[.0, .1, .2] count\n    - compute CRC32 checksum\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(IPROBE) = MK_CMD_ENTRY(
-	"iprobe",	1,	1,	do_i2c_probe,
+U_BOOT_CMD(
+	iprobe,	1,	1,	do_i2c_probe,
 	"iprobe  - probe to discover valid I2C chip addresses\n",
 	"\n    -discover valid I2C chip addresses\n"
 );
@@ -906,16 +906,16 @@ cmd_tbl_t U_BOOT_CMD(IPROBE) = MK_CMD_ENTRY(
 /*
  * Require full name for "iloop" because it is an infinite loop!
  */
-cmd_tbl_t U_BOOT_CMD(ILOOP) = MK_CMD_ENTRY(
-	"iloop",	5,	1,	do_i2c_loop,
+U_BOOT_CMD(
+	iloop,	5,	1,	do_i2c_loop,
 	"iloop   - infinite loop on address range\n",
 	"chip address[.0, .1, .2] [# of objects]\n"
 	"    - loop, reading a set of addresses\n"
 );
 
 #if (CONFIG_COMMANDS & CFG_CMD_SDRAM)
-cmd_tbl_t U_BOOT_CMD(ISDRAM) = MK_CMD_ENTRY(
-	"isdram",	2,	1,	do_sdram,
+U_BOOT_CMD(
+	isdram,	2,	1,	do_sdram,
 	"isdram  - print SDRAM configuration information\n",
 	"chip\n    - print SDRAM configuration information\n"
 	"      (valid chip values 50..57)\n"

common/cmd_ide.c

@@ -39,7 +39,6 @@
 #endif
 #include <ide.h>
 #include <ata.h>
-#include <cmd_disk.h>
 #ifdef CONFIG_STATUS_LED
 # include <status_led.h>
 #endif
@@ -1811,8 +1810,8 @@ ulong atapi_read (int device, ulong blknr, ulong blkcnt, ulong *buffer)
 
 #endif /* CONFIG_ATAPI */
 
-cmd_tbl_t U_BOOT_CMD(IDE) = MK_CMD_ENTRY(
-	"ide",  5,  1,  do_ide,
+U_BOOT_CMD(
+	ide,  5,  1,  do_ide,
 	"ide     - IDE sub-system\n",
 	"reset - reset IDE controller\n"
 	"ide info  - show available IDE devices\n"
@@ -1824,8 +1823,8 @@ cmd_tbl_t U_BOOT_CMD(IDE) = MK_CMD_ENTRY(
 	"    to/from memory address `addr'\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(DISK) = MK_CMD_ENTRY(
-	"diskboot",	3,	1,	do_diskboot,
+U_BOOT_CMD(
+	diskboot,	3,	1,	do_diskboot,
 	"diskboot- boot from IDE device\n",
 	"loadAddr dev:part\n"
 );

common/cmd_immap.c

@@ -594,106 +594,106 @@ do_mccinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 /***************************************************/
 
-cmd_tbl_t U_BOOT_CMD(SIUINFO) = MK_CMD_ENTRY(
-	"siuinfo",	1,	1,	do_siuinfo,
+U_BOOT_CMD(
+	siuinfo,	1,	1,	do_siuinfo,
 	"siuinfo - print System Interface Unit (SIU) registers\n",
 	NULL
 );
 
-cmd_tbl_t U_BOOT_CMD(MEMCINFO) = MK_CMD_ENTRY(
-	"memcinfo",	1,	1,	do_memcinfo,
+U_BOOT_CMD(
+	memcinfo,	1,	1,	do_memcinfo,
 	"memcinfo- print Memory Controller registers\n",
 	NULL
 );
 
-cmd_tbl_t U_BOOT_CMD(SITINFO) = MK_CMD_ENTRY(
-	"sitinfo",	1,	1,	do_sitinfo,
+U_BOOT_CMD(
+	sitinfo,	1,	1,	do_sitinfo,
 	"sitinfo - print System Integration Timers (SIT) registers\n",
 	NULL
 );
 
 #ifdef CONFIG_8260
-cmd_tbl_t U_BOOT_CMD(ICINFO) = MK_CMD_ENTRY(
-	"icinfo",	1,	1,	do_icinfo,
+U_BOOT_CMD(
+	icinfo,	1,	1,	do_icinfo,
 	"icinfo  - print Interrupt Controller registers\n",
 	NULL
 );
 #endif
 
-cmd_tbl_t U_BOOT_CMD(CARINFO) = MK_CMD_ENTRY(
-	"carinfo",	1,	1,	do_carinfo,
+U_BOOT_CMD(
+	carinfo,	1,	1,	do_carinfo,
 	"carinfo - print Clocks and Reset registers\n",
 	NULL
 );
 
-cmd_tbl_t U_BOOT_CMD(IOPINFO) = MK_CMD_ENTRY(
-	"iopinfo",	1,	1,	do_iopinfo,
+U_BOOT_CMD(
+	iopinfo,	1,	1,	do_iopinfo,
 	"iopinfo - print I/O Port registers\n",
 	NULL
 );
 
-cmd_tbl_t U_BOOT_CMD(IOPSET) = 	MK_CMD_ENTRY(
-	"iopset",	5,	0,	do_iopset,
+U_BOOT_CMD(
+	iopset,	5,	0,	do_iopset,
 	"iopset - set I/O Port registers\n",
 	"PORT PIN CMD VALUE\nPORT: A-D, PIN: 0-31, CMD: [dat|dir|odr|sor], VALUE: 0|1"
 );
 
-cmd_tbl_t U_BOOT_CMD(DMAINFO) = MK_CMD_ENTRY(
-	"dmainfo",	1,	1,	do_dmainfo,
+U_BOOT_CMD(
+	dmainfo,	1,	1,	do_dmainfo,
 	"dmainfo - print SDMA/IDMA registers\n",
 	NULL
 );
 
-cmd_tbl_t U_BOOT_CMD(FCCINFO) = MK_CMD_ENTRY(
-	"fccinfo",	1,	1,	do_fccinfo,
+U_BOOT_CMD(
+	fccinfo,	1,	1,	do_fccinfo,
 	"fccinfo - print FCC registers\n",
 	NULL
 );
 
-cmd_tbl_t U_BOOT_CMD(BRGINFO) = MK_CMD_ENTRY(
-	"brginfo",	1,	1,	do_brginfo,
+U_BOOT_CMD(
+	brginfo,	1,	1,	do_brginfo,
 	"brginfo - print Baud Rate Generator (BRG) registers\n",
 	NULL
 );
 
-cmd_tbl_t U_BOOT_CMD(I2CINFO) = MK_CMD_ENTRY(
-	"i2cinfo",	1,	1,	do_i2cinfo,
+U_BOOT_CMD(
+	i2cinfo,	1,	1,	do_i2cinfo,
 	"i2cinfo - print I2C registers\n",
 	NULL
 );
 
-cmd_tbl_t U_BOOT_CMD(SCCINFO) = MK_CMD_ENTRY(
-	"sccinfo",	1,	1,	do_sccinfo,
+U_BOOT_CMD(
+	sccinfo,	1,	1,	do_sccinfo,
 	"sccinfo - print SCC registers\n",
 	NULL
 );
 
-cmd_tbl_t U_BOOT_CMD(SMCINFO) = MK_CMD_ENTRY(
-	"smcinfo",	1,	1,	do_smcinfo,
+U_BOOT_CMD(
+	smcinfo,	1,	1,	do_smcinfo,
 	"smcinfo - print SMC registers\n",
 	NULL
 );
 
-cmd_tbl_t U_BOOT_CMD(SPIINFO) = MK_CMD_ENTRY(
-	"spiinfo",	1,	1,	do_spiinfo,
+U_BOOT_CMD(
+	spiinfo,	1,	1,	do_spiinfo,
 	"spiinfo - print Serial Peripheral Interface (SPI) registers\n",
 	NULL
 );
 
-cmd_tbl_t U_BOOT_CMD(MUXINFO) = MK_CMD_ENTRY(
-	"muxinfo",	1,	1,	do_muxinfo,
+U_BOOT_CMD(
+	muxinfo,	1,	1,	do_muxinfo,
 	"muxinfo - print CPM Multiplexing registers\n",
 	NULL
 );
 
-cmd_tbl_t U_BOOT_CMD(SIINFO) = MK_CMD_ENTRY(
-	"siinfo",	1,	1,	do_siinfo,
+U_BOOT_CMD(
+	siinfo,	1,	1,	do_siinfo,
 	"siinfo  - print Serial Interface (SI) registers\n",
 	NULL
 );
 
-cmd_tbl_t U_BOOT_CMD(MCCINFO) = MK_CMD_ENTRY(
-	"mccinfo",	1,	1,	do_mccinfo,
+U_BOOT_CMD(
+	mccinfo,	1,	1,	do_mccinfo,
 	"mccinfo - print MCC registers\n",
 	NULL
 );

common/cmd_jffs2.c

@@ -186,29 +186,29 @@ do_jffs2_chpart(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 /***************************************************/
 
-cmd_tbl_t U_BOOT_CMD(JFFS2_FSLOAD) = MK_CMD_ENTRY(
-	"fsload",	3,	0,	do_jffs2_fsload,
+U_BOOT_CMD(
+	fsload,	3,	0,	do_jffs2_fsload,
 	"fsload  - load binary file from a filesystem image\n",
 	"[ off ] [ filename ]\n"
 	"    - load binary file from flash bank\n"
 	"      with offset 'off'\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(JFFS2_FSINFO) = MK_CMD_ENTRY(
-	"fsinfo",	1,	1,	do_jffs2_fsinfo,
+U_BOOT_CMD(
+	fsinfo,	1,	1,	do_jffs2_fsinfo,
 	"fsinfo  - print information about filesystems\n",
 	"    - print information about filesystems\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(JFFS2_LS) = MK_CMD_ENTRY(
-	"ls",	2,	1,	do_jffs2_ls,
+U_BOOT_CMD(
+	ls,	2,	1,	do_jffs2_ls,
 	"ls      - list files in a directory (default /)\n",
 	"[ directory ]\n"
 	"    - list files in a directory.\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(JFFS2_CHPART) = MK_CMD_ENTRY(
-	"chpart",	2,	0,	do_jffs2_chpart,
+U_BOOT_CMD(
+	chpart,	2,	0,	do_jffs2_chpart,
 	"chpart  - change active partition\n",
 	"    - change active partition\n"
 );

common/cmd_load.c

@@ -26,7 +26,6 @@
  */
 #include <common.h>
 #include <command.h>
-#include <cmd_autoscript.h>
 #include <s_record.h>
 #include <net.h>
 #include <syscall.h>
@@ -972,8 +971,8 @@ START:
 #if (CONFIG_COMMANDS & CFG_CMD_LOADS)
 
 #ifdef	CFG_LOADS_BAUD_CHANGE
-cmd_tbl_t U_BOOT_CMD(LOADS) =  MK_CMD_ENTRY(
-	"loads", 3, 0,	do_load_serial,
+U_BOOT_CMD(
+	loads, 3, 0,	do_load_serial,
 	"loads   - load S-Record file over serial line\n",
 	"[ off ] [ baud ]\n"
 	"    - load S-Record file over serial line"
@@ -981,8 +980,8 @@ cmd_tbl_t U_BOOT_CMD(LOADS) =  MK_CMD_ENTRY(
 );
 
 #else	/* ! CFG_LOADS_BAUD_CHANGE */
-cmd_tbl_t U_BOOT_CMD(LOADS) =  MK_CMD_ENTRY(
-	"loads", 2, 0,	do_load_serial,
+U_BOOT_CMD(
+	loads, 2, 0,	do_load_serial,
 	"loads   - load S-Record file over serial line\n",
 	"[ off ]\n"
 	"    - load S-Record file over serial line with offset 'off'\n"
@@ -996,16 +995,16 @@ cmd_tbl_t U_BOOT_CMD(LOADS) =  MK_CMD_ENTRY(
 
 #if (CONFIG_COMMANDS & CFG_CMD_SAVES)
 #ifdef	CFG_LOADS_BAUD_CHANGE
-cmd_tbl_t U_BOOT_CMD(SAVES) = MK_CMD_ENTRY(
-	"saves", 4, 0,	do_save_serial,
+U_BOOT_CMD(
+	saves, 4, 0,	do_save_serial,
 	"saves   - save S-Record file over serial line\n",
 	"[ off ] [size] [ baud ]\n"
 	"    - save S-Record file over serial line"
 	" with offset 'off', size 'size' and baudrate 'baud'\n"
 );
 #else	/* ! CFG_LOADS_BAUD_CHANGE */
-cmd_tbl_t U_BOOT_CMD(SAVES) = MK_CMD_ENTRY(
-	"saves", 3, 0,	do_save_serial,
+U_BOOT_CMD(
+	saves, 3, 0,	do_save_serial,
 	"saves   - save S-Record file over serial line\n",
 	"[ off ] [size]\n"
 	"    - save S-Record file over serial line with offset 'off' and size 'size'\n"
@@ -1016,8 +1015,8 @@ cmd_tbl_t U_BOOT_CMD(SAVES) = MK_CMD_ENTRY(
 
 
 #if (CONFIG_COMMANDS & CFG_CMD_LOADB)
-cmd_tbl_t U_BOOT_CMD(LOADB) = MK_CMD_ENTRY(
-	"loadb", 3, 0,	do_load_serial_bin,
+U_BOOT_CMD(
+	loadb, 3, 0,	do_load_serial_bin,
 	"loadb   - load binary file over serial line (kermit mode)\n",
 	"[ off ] [ baud ]\n"
 	"    - load binary file over serial line"
@@ -1048,10 +1047,10 @@ int do_hwflow (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 /* -------------------------------------------------------------------- */
 
-cmd_tbl_t U_BOOT_CMD(HWFLOW) = MK_CMD_ENTRY(
-	"hwflow [on|off]", 2, 0,	do_hwflow,
+U_BOOT_CMD(
+	hwflow, 2, 0,	do_hwflow,
 	"hwflow  - turn the harwdare flow control on/off\n",
-	"\n - change RTS/CTS hardware flow control over serial line\n"
+	"[on|off]\n - change RTS/CTS hardware flow control over serial line\n"
 );
 
 #endif /* CFG_CMD_HWFLOW */

common/cmd_log.c

@@ -74,22 +74,29 @@ static unsigned long *ext_logged_chars;
 void logbuff_init_ptrs (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
+	unsigned long *ext_tag;
+	unsigned long post_word;
 	char *s;
 
 	log_buf = (unsigned char *)(gd->bd->bi_memsize-LOGBUFF_LEN);
-	ext_log_start = (unsigned long *)(log_buf)-3;
+	ext_tag = (unsigned long *)(log_buf)-4;
+ 	ext_log_start = (unsigned long *)(log_buf)-3;
 	ext_log_size = (unsigned long *)(log_buf)-2;
 	ext_logged_chars = (unsigned long *)(log_buf)-1;
+	post_word = post_word_load();
 #ifdef CONFIG_POST
 	/* The post routines have setup the word so we can simply test it */
- 	if (post_word_load () & POST_POWERON) {
+ 	if (((post_word & 0xffff) == POST_POWERON) ||
+	    ((post_word & 0xffff) == POST_SLOWTEST)) {
  		logged_chars = log_size = log_start = 0;
+		*ext_tag = LOGBUFF_MAGIC;
  	}
 #else
 	/* No post routines, so we do our own checking                    */
- 	if (post_word_load () != LOGBUFF_MAGIC) {
+ 	if (post_word != LOGBUFF_MAGIC) {
  		logged_chars = log_size = log_start = 0;
 		post_word_store (LOGBUFF_MAGIC);
+		*ext_tag = LOGBUFF_MAGIC;
  	}
 #endif
 	/* Initialize default loglevel if present */
@@ -162,12 +169,8 @@ int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	if (strcmp(argv[1],"append") == 0) {
 		/* Log concatenation of all arguments separated by spaces */
 		for (i=2; i<argc; i++) {
-			if (i<argc-1) {
-				logbuff_printk (argv[i]);
-				logbuff_putc (' ');
-			} else {
-				logbuff_puts (argv[i]);
-			}
+			logbuff_printk (argv[i]);
+			logbuff_putc ((i<argc-1) ? ' ' : '\n');
 		}
 		return 0;
 	}
@@ -202,10 +205,10 @@ int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	}
 }
 #if defined(CONFIG_LOGBUFFER)
-cmd_tbl_t U_BOOT_CMD(LOG) = MK_CMD_ENTRY(
-	"log",     255,	1,	do_log,
+U_BOOT_CMD(
+	log,     255,	1,	do_log,
 	"log     - manipulate logbuffer\n",
-	"log info   - show pointer details\n"
+	"info   - show pointer details\n"
 	"log reset  - clear contents\n"
 	"log show   - show contents\n"
 	"log append <msg> - append <msg> to the logbuffer\n"

common/cmd_mem.c

@@ -963,66 +963,66 @@ int do_mem_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 /**************************************************/
 #if (CONFIG_COMMANDS & CFG_CMD_MEMORY)
-cmd_tbl_t U_BOOT_CMD(MD) = MK_CMD_ENTRY(
-	"md",     3,     1,      do_mem_md,
+U_BOOT_CMD(
+	md,     3,     1,      do_mem_md,
 	"md      - memory display\n",
 	"[.b, .w, .l] address [# of objects]\n    - memory display\n"
 );
 
 
-cmd_tbl_t U_BOOT_CMD(MM) = MK_CMD_ENTRY(
-	"mm",     2,      1,       do_mem_mm,
+U_BOOT_CMD(
+	mm,     2,      1,       do_mem_mm,
 	"mm      - memory modify (auto-incrementing)\n",
 	"[.b, .w, .l] address\n" "    - memory modify, auto increment address\n"
 );
 
 
-cmd_tbl_t U_BOOT_CMD(NM) = MK_CMD_ENTRY(
-	"nm",     2,	    1,     	do_mem_nm,
+U_BOOT_CMD(
+	nm,     2,	    1,     	do_mem_nm,
 	"nm      - memory modify (constant address)\n",
 	"[.b, .w, .l] address\n    - memory modify, read and keep address\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(MW) = MK_CMD_ENTRY(
-	"mw",    4,    1,     do_mem_mw,
+U_BOOT_CMD(
+	mw,    4,    1,     do_mem_mw,
 	"mw      - memory write (fill)\n",
 	"[.b, .w, .l] address value [count]\n    - write memory\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(CP) = MK_CMD_ENTRY(
-	"cp",    4,    1,    do_mem_cp,
+U_BOOT_CMD(
+	cp,    4,    1,    do_mem_cp,
 	"cp      - memory copy\n",
 	"[.b, .w, .l] source target count\n    - copy memory\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(CMP) = MK_CMD_ENTRY(
-	"cmp",    4,     1,     do_mem_cmp,
+U_BOOT_CMD(
+	cmp,    4,     1,     do_mem_cmp,
 	"cmp     - memory compare\n",
 	"[.b, .w, .l] addr1 addr2 count\n    - compare memory\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(CRC32) = MK_CMD_ENTRY(
-	"crc32",    4,    1,     do_mem_crc,
+U_BOOT_CMD(
+	crc32,    4,    1,     do_mem_crc,
 	"crc32   - checksum calculation\n",
 	"address count [addr]\n    - compute CRC32 checksum [save at addr]\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(BASE) = MK_CMD_ENTRY(
-	"base",    2,    1,     do_mem_base,
+U_BOOT_CMD(
+	base,    2,    1,     do_mem_base,
 	"base    - print or set address offset\n",
 	"\n    - print address offset for memory commands\n"
 	"base off\n    - set address offset for memory commands to 'off'\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(LOOP) = MK_CMD_ENTRY(
-	"loop",    3,    1,    do_mem_loop,
+U_BOOT_CMD(
+	loop,    3,    1,    do_mem_loop,
 	"loop    - infinite loop on address range\n",
 	"[.b, .w, .l] address number_of_objects\n"
 	"    - loop on a set of addresses\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(MTEST) = MK_CMD_ENTRY(
-	"mtest",    4,    1,     do_mem_mtest,
+U_BOOT_CMD(
+	mtest,    4,    1,     do_mem_mtest,
 	"mtest   - simple RAM test\n",
 	"[start [end [pattern]]]\n"
 	"    - simple RAM read/write test\n"

common/cmd_mii.c

@@ -129,8 +129,8 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 
 /***************************************************/
 
-cmd_tbl_t U_BOOT_CMD(MII) = MK_CMD_ENTRY(
-	"mii",	5,	1,	do_mii,
+U_BOOT_CMD(
+	mii,	5,	1,	do_mii,
 	"mii     - MII utility commands\n",
 	"info  <addr>              - display MII PHY info\n"
 	"mii read  <addr> <reg>        - read  MII PHY <addr> register <reg>\n"

common/cmd_misc.c

@@ -56,15 +56,15 @@ int do_sleep (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #if (CONFIG_COMMANDS & CFG_CMD_IRQ)
 int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 
-cmd_tbl_t U_BOOT_CMD(IRQINFO) = MK_CMD_ENTRY(
-	"irqinfo",    1,    1,     do_irqinfo,
+U_BOOT_CMD(
+	irqinfo,    1,    1,     do_irqinfo,
 	"irqinfo - print information about IRQs\n",
 	NULL
 );
 #endif  /* CONFIG_COMMANDS & CFG_CMD_IRQ */
 
-cmd_tbl_t U_BOOT_CMD(MISC) = MK_CMD_ENTRY(
-	"sleep" ,    2,    2,     do_sleep,
+U_BOOT_CMD(
+	sleep ,    2,    2,     do_sleep,
 	"sleep   - delay execution for some time\n",
 	"N\n"
 	"    - delay execution for N seconds (N is _decimal_ !!!)\n"

common/cmd_mmc.c

@@ -37,4 +37,10 @@ int do_mmc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return 0;
 }
 
+U_BOOT_CMD(
+	mmcinit,	1,	0,	do_mmc,
+	"mmcinit - init mmc card\n",
+	NULL
+);
+
 #endif	/* CFG_CMD_MMC */

common/cmd_nand.c

@@ -247,6 +247,21 @@ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
     }
 }
 
+U_BOOT_CMD(
+	nand,	5,	1,	do_nand,
+	"nand    - NAND sub-system\n",
+	"info  - show available NAND devices\n"
+	"nand device [dev] - show or set current device\n"
+	"nand read[.jffs2]  addr off size\n"
+	"nand write[.jffs2] addr off size - read/write `size' bytes starting\n"
+	"    at offset `off' to/from memory address `addr'\n"
+	"nand erase [clean] [off size] - erase `size' bytes from\n"
+	"    offset `off' (entire device if not specified)\n"
+	"nand bad - show bad blocks\n"
+	"nand read.oob addr off size - read out-of-band data\n"
+	"nand write.oob addr off size - read out-of-band data\n"
+);
+
 int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	char *boot_device = NULL;
@@ -348,6 +363,12 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return rcode;
 }
 
+U_BOOT_CMD(
+	nboot,	4,	1,	do_nandboot,
+	"nboot   - boot from NAND device\n",
+	"loadAddr dev\n"
+);
+
 /* returns 0 if block containing pos is OK:
  *		valid erase block and
  *		not marked bad, or no bad mark position is specified

common/cmd_net.c

@@ -26,7 +26,6 @@
  */
 #include <common.h>
 #include <command.h>
-#include <cmd_autoscript.h>
 #include <net.h>
 
 #if (CONFIG_COMMANDS & CFG_CMD_NET)
@@ -41,8 +40,8 @@ int do_bootp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return netboot_common (BOOTP, cmdtp, argc, argv);
 }
 
-cmd_tbl_t U_BOOT_CMD(BOOTP) = MK_CMD_ENTRY(
-	"bootp",	3,	1,	do_bootp,
+U_BOOT_CMD(
+	bootp,	3,	1,	do_bootp,
 	"bootp   - boot image via network using BootP/TFTP protocol\n",
 	"[loadAddress] [bootfilename]\n"
 );
@@ -52,8 +51,8 @@ int do_tftpb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return netboot_common (TFTP, cmdtp, argc, argv);
 }
 
-cmd_tbl_t U_BOOT_CMD(TFTPB) = MK_CMD_ENTRY(
-	"tftpboot",	3,	1,	do_tftpb,
+U_BOOT_CMD(
+	tftpboot,	3,	1,	do_tftpb,
 	"tftpboot- boot image via network using TFTP protocol\n",
 	"[loadAddress] [bootfilename]\n"
 );
@@ -63,8 +62,8 @@ int do_rarpb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return netboot_common (RARP, cmdtp, argc, argv);
 }
 
-cmd_tbl_t U_BOOT_CMD(RARPB) = MK_CMD_ENTRY(
-	"rarpboot",	3,	1,	do_rarpb,
+U_BOOT_CMD(
+	rarpboot,	3,	1,	do_rarpb,
 	"rarpboot- boot image via network using RARP/TFTP protocol\n",
 	"[loadAddress] [bootfilename]\n"
 );
@@ -75,8 +74,8 @@ int do_dhcp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return netboot_common(DHCP, cmdtp, argc, argv);
 }
 
-cmd_tbl_t U_BOOT_CMD(DHCP) = MK_CMD_ENTRY(
-	"dhcp",	3,	1,	do_dhcp,
+U_BOOT_CMD(
+	dhcp,	3,	1,	do_dhcp,
 	"dhcp    - invoke DHCP client to obtain IP/boot params\n",
 	"\n"
 );
@@ -211,6 +210,12 @@ int do_ping (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 	return 0;
 }
+
+U_BOOT_CMD(
+	ping,	2,	1,	do_ping,
+	"ping    - send ICMP ECHO_REQUEST to network host\n",
+	"pingAddress\n"
+);
 #endif	/* CFG_CMD_PING */
 
 #endif	/* CFG_CMD_NET */

common/cmd_nvedit.c

@@ -183,9 +183,6 @@ int _do_setenv (int flag, int argc, char *argv[])
 		 * ver is readonly.
 		 */
 		if ( (strcmp (name, "serial#") == 0) ||
-#if defined(CONFIG_VERSION_VARIABLE)
-		     (strcmp (name, "ver") == 0) ||
-#endif /* CONFIG_VERSION_VARIABLE */
 		    ((strcmp (name, "ethaddr") == 0)
 #if defined(CONFIG_OVERWRITE_ETHADDR_ONCE) && defined(CONFIG_ETHADDR)
 		     && (strcmp (env_get_addr(oldval),MK_STR(CONFIG_ETHADDR)) != 0)
@@ -561,16 +558,16 @@ envmatch (uchar *s1, int i2)
 
 /**************************************************/
 
-cmd_tbl_t U_BOOT_CMD(PRINTENV) = MK_CMD_ENTRY(
-	"printenv", CFG_MAXARGS, 1,	do_printenv,
+U_BOOT_CMD(
+	printenv, CFG_MAXARGS, 1,	do_printenv,
 	"printenv- print environment variables\n",
 	"\n    - print values of all environment variables\n"
 	"printenv name ...\n"
 	"    - print value of environment variable 'name'\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(SETENV) = MK_CMD_ENTRY(
-	"setenv", CFG_MAXARGS, 0,	do_setenv,
+U_BOOT_CMD(
+	setenv, CFG_MAXARGS, 0,	do_setenv,
 	"setenv  - set environment variables\n",
 	"name value ...\n"
 	"    - set environment variable 'name' to 'value ...'\n"
@@ -580,8 +577,8 @@ cmd_tbl_t U_BOOT_CMD(SETENV) = MK_CMD_ENTRY(
 
 #if ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_FLASH)) == (CFG_CMD_ENV|CFG_CMD_FLASH))
 
-cmd_tbl_t U_BOOT_CMD(SAVEENV) = MK_CMD_ENTRY(
-	"saveenv", 1, 0,	do_saveenv,
+U_BOOT_CMD(
+	saveenv, 1, 0,	do_saveenv,
 	"saveenv - save environment variables to persistent storage\n",
 	NULL
 );
@@ -590,8 +587,8 @@ cmd_tbl_t U_BOOT_CMD(SAVEENV) = MK_CMD_ENTRY(
 
 #if (CONFIG_COMMANDS & CFG_CMD_ASKENV)
 
-cmd_tbl_t U_BOOT_CMD(ASKENV) = MK_CMD_ENTRY(
-	"askenv",	CFG_MAXARGS,	1,	do_askenv,
+U_BOOT_CMD(
+	askenv,	CFG_MAXARGS,	1,	do_askenv,
 	"askenv  - get environment variables from stdin\n",
 	"name [message] [size]\n"
 	"    - get environment variable 'name' from stdin (max 'size' chars)\n"
@@ -607,8 +604,8 @@ cmd_tbl_t U_BOOT_CMD(ASKENV) = MK_CMD_ENTRY(
 
 #if (CONFIG_COMMANDS & CFG_CMD_RUN)
 int do_run (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
-cmd_tbl_t U_BOOT_CMD(RUN) = MK_CMD_ENTRY(
-	"run",	CFG_MAXARGS,	1,	do_run,
+U_BOOT_CMD(
+	run,	CFG_MAXARGS,	1,	do_run,
 	"run     - run commands in an environment variable\n",
 	"var [...]\n"
 	"    - run the commands in the environment variable(s) 'var'\n"

common/cmd_pci.c

@@ -548,8 +548,8 @@ int do_pci (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 /***************************************************/
 
 
-cmd_tbl_t U_BOOT_CMD(PCI) = MK_CMD_ENTRY(
-	"pci",	5,	1,	do_pci,
+U_BOOT_CMD(
+	pci,	5,	1,	do_pci,
 	"pci     - list and access PCI Configuraton Space\n",
 	"[bus] [long]\n"
 	"    - short or long list of PCI devices on bus 'bus'\n"

common/cmd_pcmcia.c

@@ -2487,8 +2487,8 @@ static int identify  (volatile uchar *p)
 /**************************************************/
 
 #if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
-cmd_tbl_t U_BOOT_CMD(PINIT) = MK_CMD_ENTRY(
-	"pinit",	2,	1,	do_pinit,
+U_BOOT_CMD(
+	pinit,	2,	1,	do_pinit,
 	"pinit   - PCMCIA sub-system\n",
 	"on  - power on PCMCIA socket\n"
 	"pinit off - power off PCMCIA socket\n"

common/cmd_portio.c

@@ -29,7 +29,6 @@
 
 #include <common.h>
 #include <command.h>
-#include <cmd_portio.h>
 
 #if (CONFIG_COMMANDS & CFG_CMD_PORTIO)
 
@@ -96,6 +95,12 @@ int do_portio_out (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	return 0;
 }
 
+U_BOOT_CMD(
+	out,	3,	1,	do_portio_out,
+	"out     - write datum to IO port\n",
+	"[.b, .w, .l] port value\n    - output to IO port\n"
+);
+
 int do_portio_in (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
 	uint addr = in_last_addr;
@@ -154,4 +159,11 @@ int do_portio_in (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	return 0;
 }
 
+U_BOOT_CMD(
+	in,	2,	1,	do_portio_in,
+	"in      - read data from an IO port\n",
+	"[.b, .w, .l] port\n"
+	"    - read datum from IO port\n"
+);
+
 #endif	/* CFG_CMD_PORTIO */

common/cmd_reginfo.c

@@ -219,8 +219,8 @@ mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) );
 #if (defined(CONFIG_8xx) || defined(CONFIG_405GP)) && \
      (CONFIG_COMMANDS & CFG_CMD_REGINFO)
 
-cmd_tbl_t U_BOOT_CMD(REGINFO) =	MK_CMD_ENTRY(
- 	"reginfo",	2,	1,	do_reginfo,
+U_BOOT_CMD(
+ 	reginfo,	2,	1,	do_reginfo,
 	"reginfo - print register information\n",
 );
 #endif

common/cmd_scsi.c

@@ -33,7 +33,6 @@
 #include <asm/processor.h>
 #include <scsi.h>
 #include <image.h>
-#include <cmd_disk.h>
 #include <pci.h>
 
 

common/cmd_spi.c

@@ -131,8 +131,8 @@ int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 /***************************************************/
 
-cmd_tbl_t U_BOOT_CMD(SPI) = MK_CMD_ENTRY(
-	"sspi",	5,	1,	do_spi,
+U_BOOT_CMD(
+	sspi,	5,	1,	do_spi,
 	"sspi     - SPI utility commands\n",
 	"<device> <bit_len> <dout> - Send <bit_len> bits from <dout> out the SPI\n"
 	"<device>  - Identifies the chip select of the device\n"

common/cmd_usb.c

@@ -31,7 +31,6 @@
 #if (CONFIG_COMMANDS & CFG_CMD_USB)
 
 #include <usb.h>
-#include <cmd_disk.h>
 
 #undef	CMD_USB_DEBUG
 
@@ -595,8 +594,8 @@ int do_usb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #if (CONFIG_COMMANDS & CFG_CMD_USB)
 
 #ifdef CONFIG_USB_STORAGE
-cmd_tbl_t U_BOOT_CMD(USB) = MK_CMD_ENTRY(
-	"usb",	5,	1,	do_usb,
+U_BOOT_CMD(
+	usb,	5,	1,	do_usb,
 	"usb     - USB sub-system\n",
 	"reset - reset (rescan) USB controller\n"
 	"usb  stop [f]  - stop USB [f]=force stop\n"
@@ -610,15 +609,15 @@ cmd_tbl_t U_BOOT_CMD(USB) = MK_CMD_ENTRY(
 );
 
 
-cmd_tbl_t U_BOOT_CMD(USBBOOT) = MK_CMD_ENTRY(
-	"usbboot",	3,	1,	do_usbboot,
+U_BOOT_CMD(
+	usbboot,	3,	1,	do_usbboot,
 	"usbboot - boot from USB device\n",
 	"loadAddr dev:part\n"
 );
 
 #else
-cmd_tbl_t U_BOOT_CMD(USB) = MK_CMD_ENTRY(
-	"usb",	5,	1,	do_usb,
+U_BOOT_CMD(
+	usb,	5,	1,	do_usb,
 	"usb     - USB sub-system\n",
 	"reset - reset (rescan) USB controller\n"
 	"usb  tree  - show USB device tree\n"

common/cmd_vfd.c

@@ -65,8 +65,8 @@ int do_vfd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return 0;
 }
 
-cmd_tbl_t U_BOOT_CMD(VFD) = MK_CMD_ENTRY(
- 	"vfd",	2,	0,	do_vfd,
+U_BOOT_CMD(
+ 	vfd,	2,	0,	do_vfd,
  	"vfd     - load a bitmap to the VFDs on TRAB\n",
  	"N\n"
  	"    - load bitmap N to the VFDs (N is _decimal_ !!!)\n"

common/command.c

@@ -36,6 +36,12 @@ do_version (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return 0;
 }
 
+U_BOOT_CMD(
+	version,	1,		1,	do_version,
+ 	"version - print monitor version\n",
+	NULL
+);
+
 int
 do_echo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
@@ -61,6 +67,13 @@ do_echo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return 0;
 }
 
+U_BOOT_CMD(
+	echo,	CFG_MAXARGS,	1,	do_echo,
+ 	"echo    - echo args to console\n",
+ 	"[args..]\n"
+	"    - echo args to console; \\c suppresses newline\n"
+);
+
 /*
  * Use puts() instead of printf() to avoid printf buffer overflow
  * for long help messages
@@ -145,8 +158,8 @@ int do_help (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 }
 
 
-cmd_tbl_t U_BOOT_CMD(HELP) = MK_CMD_ENTRY(
-	"help",	CFG_MAXARGS,	1,	do_help,
+U_BOOT_CMD(
+	help,	CFG_MAXARGS,	1,	do_help,
  	"help    - print online help\n",
  	"[command ...]\n"
  	"    - show help information (for 'command')\n"
@@ -156,24 +169,19 @@ cmd_tbl_t U_BOOT_CMD(HELP) = MK_CMD_ENTRY(
   "'help' with one or more command names as arguments.\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(QUES) = MK_CMD_ENTRY(
+/* This do not ust the U_BOOT_CMD macro as ? can't be used in symbol names */
+#ifdef  CFG_LONGHELP
+cmd_tbl_t __u_boot_cmd_question_mark Struct_Section = {
 	"?",	CFG_MAXARGS,	1,	do_help,
  	"?       - alias for 'help'\n",
 	NULL
-);
-
-cmd_tbl_t U_BOOT_CMD(VERS) = MK_CMD_ENTRY(
-	"version",	1,		1,	do_version,
- 	"version - print monitor version\n",
-	NULL
-);
-
-cmd_tbl_t U_BOOT_CMD(ECHO) = MK_CMD_ENTRY(
-	"echo",	CFG_MAXARGS,	1,	do_echo,
- 	"echo    - echo args to console\n",
- 	"[args..]\n"
-	"    - echo args to console; \\c suppresses newline\n"
-);
+};
+#else
+cmd_tbl_t __u_boot_cmd_question_mark Struct_Section = {
+	"?",	CFG_MAXARGS,	1,	do_help,
+ 	"?       - alias for 'help'\n"
+};
+#endif /* CFG_LONGHELP */
 
 /***************************************************************************
  * find command table entry for a command

common/kgdb.c

@@ -573,8 +573,8 @@ do_kgdb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
     return 0;
 }
 
-cmd_tbl_t U_BOOT_CMD(KGDB) = MK_CMD_ENTRY(
-	"kgdb", CFG_MAXARGS, 1,	do_kgdb,
+U_BOOT_CMD(
+	kgdb, CFG_MAXARGS, 1,	do_kgdb,
 	"kgdb    - enter gdb remote debug mode\n",
 	"[arg0 arg1 .. argN]\n"
 	"    - executes a breakpoint so that kgdb mode is\n"

common/main.c

@@ -284,10 +284,8 @@ void main_loop (void)
 #ifdef CONFIG_VERSION_VARIABLE
 	{
 		extern char version_string[];
-		char *str = getenv("ver");
 
-		if (!str)
-			setenv ("ver", version_string);  /* set version variable */
+		setenv ("ver", version_string);  /* set version variable */
 	}
 #endif /* CONFIG_VERSION_VARIABLE */
 

cpu/arm925t/Makefile

@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(CPU).a
+
+START	= start.o
+OBJS	= interrupts.o cpu.o omap925.o
+
+all:	.depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(START:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

cpu/arm925t/config.mk

@@ -0,0 +1,27 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
+	-mshort-load-bytes -msoft-float
+
+PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4

cpu/arm925t/cpu.c

@@ -0,0 +1,159 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * CPU specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <arm925t.h>
+
+/* read co-processor 15, register #1 (control register) */
+static unsigned long read_p15_c1 (void)
+{
+	unsigned long value;
+
+	__asm__ __volatile__(
+		"mrc	p15, 0, %0, c1, c0, 0   @ read control reg\n"
+		: "=r" (value)
+		:
+		: "memory");
+
+#ifdef MMU_DEBUG
+	printf ("p15/c1 is = %08lx\n", value);
+#endif
+	return value;
+}
+
+/* write to co-processor 15, register #1 (control register) */
+static void write_p15_c1 (unsigned long value)
+{
+#ifdef MMU_DEBUG
+	printf ("write %08lx to p15/c1\n", value);
+#endif
+	__asm__ __volatile__(
+		"mcr	p15, 0, %0, c1, c0, 0   @ write it back\n"
+		:
+		: "r" (value)
+		: "memory");
+
+	read_p15_c1 ();
+}
+
+static void cp_delay (void)
+{
+	volatile int i;
+
+	/* Many OMAP regs need at least 2 nops  */
+	for (i = 0; i < 100; i++);
+}
+
+/* See also ARM Ref. Man. */
+#define C1_MMU		(1<<0)		/* mmu off/on */
+#define C1_ALIGN	(1<<1)		/* alignment faults off/on */
+#define C1_DC		(1<<2)		/* dcache off/on */
+#define C1_WB		(1<<3)		/* merging write buffer on/off */
+#define C1_BIG_ENDIAN	(1<<7)	/* big endian off/on */
+#define C1_SYS_PROT	(1<<8)		/* system protection */
+#define C1_ROM_PROT	(1<<9)		/* ROM protection */
+#define C1_IC		(1<<12)		/* icache off/on */
+#define C1_HIGH_VECTORS	(1<<13)	/* location of vectors: low/high addresses */
+#define RESERVED_1	(0xf << 3)	/* must be 111b for R/W */
+
+int cpu_init (void)
+{
+	/*
+	 * setup up stack if necessary
+	 */
+#ifdef CONFIG_USE_IRQ
+	IRQ_STACK_START = _armboot_end +
+			CONFIG_STACKSIZE + CONFIG_STACKSIZE_IRQ - 4;
+	FIQ_STACK_START = IRQ_STACK_START + CONFIG_STACKSIZE_FIQ;
+	_armboot_real_end = FIQ_STACK_START + 4;
+#else
+	_armboot_real_end = _armboot_end + CONFIG_STACKSIZE;
+#endif	/* CONFIG_USE_IRQ */
+	return (0);
+}
+
+int cleanup_before_linux (void)
+{
+	/*
+	 * this function is called just before we call linux
+	 * it prepares the processor for linux
+	 *
+	 * we turn off caches etc ...
+	 */
+
+	unsigned long i;
+
+	disable_interrupts ();
+
+	/* turn off I/D-cache */
+	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	i &= ~(C1_DC | C1_IC);
+	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+
+	/* flush I/D-cache */
+	i = 0;
+	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
+	return (0);
+}
+
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	extern void reset_cpu (ulong addr);
+
+	disable_interrupts ();
+	reset_cpu (0);
+	/*NOTREACHED*/
+	return (0);
+}
+
+void icache_enable (void)
+{
+	ulong reg;
+
+	reg = read_p15_c1 ();		/* get control reg. */
+	cp_delay ();
+	write_p15_c1 (reg | C1_IC);
+}
+
+void icache_disable (void)
+{
+	ulong reg;
+
+	reg = read_p15_c1 ();
+	cp_delay ();
+	write_p15_c1 (reg & ~C1_IC);
+}
+
+int icache_status (void)
+{
+	return (read_p15_c1 () & C1_IC) != 0;
+}

cpu/arm925t/interrupts.c

@@ -0,0 +1,300 @@
+/*
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <arm925t.h>
+#include <configs/omap1510.h>
+
+#include <asm/proc-armv/ptrace.h>
+
+extern void reset_cpu(ulong addr);
+#define TIMER_LOAD_VAL 0xffffffff
+
+/* macro to read the 32 bit timer */
+#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8))
+
+#ifdef CONFIG_USE_IRQ
+/* enable IRQ interrupts */
+void enable_interrupts (void)
+{
+	unsigned long temp;
+	__asm__ __volatile__("mrs %0, cpsr\n"
+			     "bic %0, %0, #0x80\n"
+			     "msr cpsr_c, %0"
+			     : "=r" (temp)
+			     :
+			     : "memory");
+}
+
+
+/*
+ * disable IRQ/FIQ interrupts
+ * returns true if interrupts had been enabled before we disabled them
+ */
+int disable_interrupts (void)
+{
+	unsigned long old,temp;
+	__asm__ __volatile__("mrs %0, cpsr\n"
+			     "orr %1, %0, #0xc0\n"
+			     "msr cpsr_c, %1"
+			     : "=r" (old), "=r" (temp)
+			     :
+			     : "memory");
+	return (old & 0x80) == 0;
+}
+#else
+void enable_interrupts (void)
+{
+	return;
+}
+int disable_interrupts (void)
+{
+	return 0;
+}
+#endif
+
+
+void bad_mode (void)
+{
+	panic ("Resetting CPU ...\n");
+	reset_cpu (0);
+}
+
+void show_regs (struct pt_regs *regs)
+{
+	unsigned long flags;
+	const char *processor_modes[] = {
+	"USER_26",	"FIQ_26",	"IRQ_26",	"SVC_26",
+	"UK4_26",	"UK5_26",	"UK6_26",	"UK7_26",
+	"UK8_26",	"UK9_26",	"UK10_26",	"UK11_26",
+	"UK12_26",	"UK13_26",	"UK14_26",	"UK15_26",
+	"USER_32",	"FIQ_32",	"IRQ_32",	"SVC_32",
+	"UK4_32",	"UK5_32",	"UK6_32",	"ABT_32",
+	"UK8_32",	"UK9_32",	"UK10_32",	"UND_32",
+	"UK12_32",	"UK13_32",	"UK14_32",	"SYS_32",
+	};
+
+	flags = condition_codes (regs);
+
+	printf ("pc : [<%08lx>]    lr : [<%08lx>]\n"
+		"sp : %08lx  ip : %08lx  fp : %08lx\n",
+		instruction_pointer (regs),
+		regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
+	printf ("r10: %08lx  r9 : %08lx  r8 : %08lx\n",
+		regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
+	printf ("r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
+		regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
+	printf ("r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
+		regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
+	printf ("Flags: %c%c%c%c",
+		flags & CC_N_BIT ? 'N' : 'n',
+		flags & CC_Z_BIT ? 'Z' : 'z',
+		flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
+	printf ("  IRQs %s  FIQs %s  Mode %s%s\n",
+		interrupts_enabled (regs) ? "on" : "off",
+		fast_interrupts_enabled (regs) ? "on" : "off",
+		processor_modes[processor_mode (regs)],
+		thumb_mode (regs) ? " (T)" : "");
+}
+
+void do_undefined_instruction (struct pt_regs *pt_regs)
+{
+	printf ("undefined instruction\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_software_interrupt (struct pt_regs *pt_regs)
+{
+	printf ("software interrupt\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_prefetch_abort (struct pt_regs *pt_regs)
+{
+	printf ("prefetch abort\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_data_abort (struct pt_regs *pt_regs)
+{
+	printf ("data abort\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_not_used (struct pt_regs *pt_regs)
+{
+	printf ("not used\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_fiq (struct pt_regs *pt_regs)
+{
+	printf ("fast interrupt request\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_irq (struct pt_regs *pt_regs)
+{
+	printf ("interrupt request\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+static ulong timestamp;
+static ulong lastdec;
+
+/* nothing really to do with interrupts, just starts up a counter. */
+int interrupt_init (void)
+{
+	int32_t val;
+
+	*((int32_t *) (CFG_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
+	val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CFG_PVT << MPUTIM_PTV_BIT);
+	*((int32_t *) (CFG_TIMERBASE + CNTL_TIMER)) = val;
+	return (0);
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer (void)
+{
+	reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+	return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+	timestamp = t;
+}
+
+/* very rough timer... */
+void udelay (unsigned long usec)
+{
+#ifdef CONFIG_INNOVATOROMAP1510
+#define LOOPS_PER_MSEC 60		/* tuned on omap1510 */
+	volatile int i, time_remaining = LOOPS_PER_MSEC * usec;
+
+	for (i = time_remaining; i > 0; i--) {
+	}
+#else
+
+	ulong tmo;
+
+	tmo = usec / 1000;
+	tmo *= CFG_HZ;
+	tmo /= 1000;
+
+	tmo += get_timer (0);
+
+	while (get_timer_masked () < tmo)
+		/*NOP*/;
+#endif
+}
+
+void reset_timer_masked (void)
+{
+	/* reset time */
+	lastdec = READ_TIMER;
+	timestamp = 0;
+}
+
+ulong get_timer_masked (void)
+{
+	ulong now = READ_TIMER;           /* current tick value */
+
+	if (lastdec >= now) {             /* did I roll (rem decrementer) */
+		/* normal mode */
+		timestamp += lastdec - now;   /* record amount of time since last check */
+	} else {
+		/* we have an overflow ... */
+		timestamp += lastdec + TIMER_LOAD_VAL - now;
+	}
+	lastdec = now;
+
+	return timestamp;
+}
+
+void udelay_masked (unsigned long usec)
+{
+#ifdef CONFIG_INNOVATOROMAP1510
+	#define LOOPS_PER_MSEC 60 /* tuned on omap1510 */
+	volatile int i, time_remaining = LOOPS_PER_MSEC*usec;
+    for (i=time_remaining; i>0; i--) { }
+#else
+
+	ulong tmo;
+
+	tmo = usec / 1000;
+	tmo *= CFG_HZ;
+	tmo /= 1000;
+
+	reset_timer_masked ();
+
+	while (get_timer_masked () < tmo)
+		/*NOP*/;
+#endif
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{	/* poor timer, may need to improve especiall for bootp. */
+	ulong tbclk;
+
+	tbclk = CFG_HZ;
+	return tbclk;
+}

cpu/arm925t/omap925.c

@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2003
+ * Texas Instruments <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <arm925t.h>
+
+ushort gpioreserved;
+
+void gpioreserve(ushort mask)
+{
+	gpioreserved |= mask;
+}
+
+void gpiosetdir(ushort mask, ushort in)
+{
+	*(ushort *)GPIO_DIR_CONTROL_REG = (*(ushort *)GPIO_DIR_CONTROL_REG & ~mask) | (in & mask);
+}
+
+
+void gpiosetout(ushort mask, ushort out)
+{
+	ushort *r_ptr, r_val;
+
+	r_ptr = (ushort *)GPIO_DATA_OUTPUT_REG;	/* set pointer */
+	r_val = *r_ptr & ~mask;		/* get previous val, clear bits we want to change */
+	r_val |= (out & mask);		/* set specified bits in value + plus origional ones */
+	*r_ptr = r_val;			/* write it out */
+/*
+ * gcc screwed this one up :(.
+ *
+ * *(ushort *)GPIO_DATA_OUTPUT_REG = (*(ushort *)GPIO_DATA_OUTPUT_REG & ~mask) | (out & mask);
+ */
+
+}
+
+void gpioinit(void)
+{
+}
+
+
+#define MIF_CONFIG_REG 0xFFFECC0C
+#define FLASH_GLOBAL_CTRL_NWP 1
+
+void archflashwp (void *archdata, int wp)
+{
+	ulong *fgc = (ulong *) MIF_CONFIG_REG;
+
+	if (wp == 1)
+		*fgc &= ~FLASH_GLOBAL_CTRL_NWP;
+	else
+		*fgc |= FLASH_GLOBAL_CTRL_NWP;
+}

cpu/arm925t/start.S

@@ -0,0 +1,423 @@
+/*
+ *  armboot - Startup Code for ARM925 CPU-core
+ *
+ *  Copyright (c) 2003  Texas Instruments
+ *
+ *  ----- Adapted for OMAP1510 from ARM920 code ------
+ *
+ *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
+ *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
+ *  Copyright (c) 2002	Gary Jennejohn <gj@denx.de>
+ *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
+ *  Copyright (c) 2003	Kshitij 	 <kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_OMAP1510)
+#include <./configs/omap1510.h>
+#endif
+
+/*
+ *************************************************************************
+ *
+ * Jump vector table as in table 3.1 in [1]
+ *
+ *************************************************************************
+ */
+
+
+.globl _start
+_start:	b       reset
+	ldr	pc, _undefined_instruction
+	ldr	pc, _software_interrupt
+	ldr	pc, _prefetch_abort
+	ldr	pc, _data_abort
+	ldr	pc, _not_used
+	ldr	pc, _irq
+	ldr	pc, _fiq
+
+_undefined_instruction:	.word undefined_instruction
+_software_interrupt:	.word software_interrupt
+_prefetch_abort:	.word prefetch_abort
+_data_abort:		.word data_abort
+_not_used:		.word not_used
+_irq:			.word irq
+_fiq:			.word fiq
+
+	.balignl 16,0xdeadbeef
+
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * setup Memory and board specific bits prior to relocation.
+ * relocate armboot to ram
+ * setup stack
+ *
+ *************************************************************************
+ */
+
+/*
+ * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
+ */
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+.globl _armboot_start
+_armboot_start:
+	.word _start
+
+/*
+ * Note: _armboot_end_data and _armboot_end are defined
+ * by the (board-dependent) linker script.
+ * _armboot_end_data is the first usable FLASH address after armboot
+ */
+.globl _armboot_end_data
+_armboot_end_data:
+	.word armboot_end_data
+.globl _armboot_end
+_armboot_end:
+	.word armboot_end
+
+/*
+ * _armboot_real_end is the first usable RAM address behind armboot
+ * and the various stacks
+ */
+.globl _armboot_real_end
+_armboot_real_end:
+	.word 0x0badc0de
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+	.word	0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+	.word 0x0badc0de
+#endif
+
+
+/*
+ * the actual reset code
+ */
+
+reset:
+	/*
+	 * set the cpu to SVC32 mode
+	 */
+	mrs	r0,cpsr
+	bic	r0,r0,#0x1f
+	orr	r0,r0,#0xd3
+	msr	cpsr,r0
+
+	/*
+	 * Set up 925T mode
+	 */
+	mov r1, #0x81               /* Set ARM925T configuration. */
+	mcr p15, 0, r1, c15, c1, 0  /* Write ARM925T configuration register. */
+
+	/*
+	 * turn off the watchdog, unlock/diable sequence
+	 */
+	mov  r1, #0xF5
+	ldr  r0, =WDTIM_MODE
+	strh r1, [r0]
+	mov  r1, #0xA0
+	strh r1, [r0]
+
+	/*
+	 * mask all IRQs by setting all bits in the INTMR - default
+	 */
+	mov r1, #0xffffffff
+	ldr r0, =REG_IHL1_MIR
+	str r1, [r0]
+	ldr r0, =REG_IHL2_MIR
+	str r1, [r0]
+
+	/*
+	 * wait for dpll to lock
+	 */
+	ldr  r0, =CK_DPLL1
+	mov  r1, #0x10
+	strh r1, [r0]
+poll1:
+	ldrh r1, [r0]
+	ands r1, r1, #0x01
+	beq poll1
+	bl  cpu_init_crit
+
+relocate:
+	/*
+	 * relocate armboot to RAM
+	 */
+	adr	r0, _start		/* r0 <- current position of code */
+	ldr	r2, _armboot_start
+	ldr	r3, _armboot_end
+	sub	r2, r3, r2		/* r2 <- size of armboot */
+	ldr	r1, _TEXT_BASE		/* r1 <- destination address */
+	add	r2, r0, r2		/* r2 <- source end address */
+
+	/*
+	 * r0 = source address
+	 * r1 = target address
+	 * r2 = source end address
+	 */
+copy_loop:
+	ldmia	r0!, {r3-r10}
+	stmia	r1!, {r3-r10}
+	cmp	r0, r2
+	ble	copy_loop
+
+	/* set up the stack */
+	ldr	r0, _armboot_end
+	add	r0, r0, #CONFIG_STACKSIZE
+	sub	sp, r0, #12		/* leave 3 words for abort-stack */
+
+	ldr	pc, _start_armboot
+
+_start_armboot:	.word start_armboot
+
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+
+
+cpu_init_crit:
+	/*
+	 * flush v4 I/D caches
+	 */
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
+	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+
+	/*
+	 * disable MMU stuff and caches
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
+	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
+	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
+	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
+	mcr	p15, 0, r0, c1, c0, 0
+
+	/*
+	 * Go setup Memory and board specific bits prior to relocation.
+	 */
+	mov	ip, lr          /* perserve link reg across call */
+	bl	platformsetup   /* go setup pll,mux,memory */
+	mov	lr, ip          /* restore link */
+	mov	pc, lr          /* back to my caller */
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+
+@
+@ IRQ stack frame.
+@
+#define S_FRAME_SIZE	72
+
+#define S_OLD_R0	68
+#define S_PSR		64
+#define S_PC		60
+#define S_LR		56
+#define S_SP		52
+
+#define S_IP		48
+#define S_FP		44
+#define S_R10		40
+#define S_R9		36
+#define S_R8		32
+#define S_R7		28
+#define S_R6		24
+#define S_R5		20
+#define S_R4		16
+#define S_R3		12
+#define S_R2		8
+#define S_R1		4
+#define S_R0		0
+
+#define MODE_SVC 0x13
+#define I_BIT	 0x80
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
+ */
+
+	.macro	bad_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE           @ carve out a frame on current user stack
+	stmia	sp, {r0 - r12}			@ Save user registers (now in svc mode) r0-r12
+
+	ldr	r2, _armboot_end                @ find top of stack
+	add	r2, r2, #CONFIG_STACKSIZE       @ find base of normal stack
+	sub	r2, r2, #8                      @ set base 2 words into abort stack
+	ldmia	r2, {r2 - r3}                   @ get values for "aborted" pc and cpsr (into parm regs)
+	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
+
+	add	r5, sp, #S_SP
+	mov	r1, lr
+	stmia	r5, {r0 - r3}                   @ save sp_SVC, lr_SVC, pc, cpsr
+	mov	r0, sp                          @ save current stack into r0 (param register)
+	.endm
+
+	.macro	irq_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE
+	stmia	sp, {r0 - r12}			@ Calling r0-r12
+	add     r8, sp, #S_PC                   @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
+	stmdb   r8, {sp, lr}^                   @ Calling SP, LR
+	str     lr, [r8, #0]                    @ Save calling PC
+	mrs     r6, spsr
+	str     r6, [r8, #4]                    @ Save CPSR
+	str     r0, [r8, #8]                    @ Save OLD_R0
+	mov	r0, sp
+	.endm
+
+	.macro	irq_restore_user_regs
+	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
+	mov	r0, r0
+	ldr	lr, [sp, #S_PC]			@ Get PC
+	add	sp, sp, #S_FRAME_SIZE
+	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
+	.endm
+
+	.macro get_bad_stack
+	ldr	r13, _armboot_end		@ get bottom of stack (into sp by by user stack pointer).
+	add	r13, r13, #CONFIG_STACKSIZE	@ head to reserved words at the top of the stack
+	sub	r13, r13, #8                    @ reserved a couple spots in abort stack
+
+	str	lr, [r13]			@ save caller lr in position 0 of saved stack
+	mrs	lr, spsr                        @ get the spsr
+	str     lr, [r13, #4]                   @ save spsr in position 1 of saved stack
+
+	mov	r13, #MODE_SVC			@ prepare SVC-Mode
+	@ msr	spsr_c, r13
+	msr	spsr, r13                       @ switch modes, make sure moves will execute
+	mov	lr, pc                          @ capture return pc
+	movs	pc, lr                          @ jump to next instruction & switch modes.
+	.endm
+
+	.macro get_irq_stack			@ setup IRQ stack
+	ldr	sp, IRQ_STACK_START
+	.endm
+
+	.macro get_fiq_stack			@ setup FIQ stack
+	ldr	sp, FIQ_STACK_START
+	.endm
+
+/*
+ * exception handlers
+ */
+	.align  5
+undefined_instruction:
+	get_bad_stack
+	bad_save_user_regs
+	bl 	do_undefined_instruction
+
+	.align	5
+software_interrupt:
+	get_bad_stack
+	bad_save_user_regs
+	bl 	do_software_interrupt
+
+	.align	5
+prefetch_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl 	do_prefetch_abort
+
+	.align	5
+data_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl 	do_data_abort
+
+	.align	5
+not_used:
+	get_bad_stack
+	bad_save_user_regs
+	bl 	do_not_used
+
+#ifdef CONFIG_USE_IRQ
+
+	.align	5
+irq:
+	get_irq_stack
+	irq_save_user_regs
+	bl 	do_irq
+	irq_restore_user_regs
+
+	.align	5
+fiq:
+	get_fiq_stack
+	/* someone ought to write a more effiction fiq_save_user_regs */
+	irq_save_user_regs
+	bl 	do_fiq
+	irq_restore_user_regs
+
+#else
+
+	.align	5
+irq:
+	get_bad_stack
+	bad_save_user_regs
+	bl 	do_irq
+
+	.align	5
+fiq:
+	get_bad_stack
+	bad_save_user_regs
+	bl 	do_fiq
+
+#endif
+
+	.align	5
+.globl reset_cpu
+reset_cpu:
+	ldr	r1, rstctl1     /* get clkm1 reset ctl */
+	mov     r3, #0x0
+	strh	r3, [r1]        /* clear it */
+	mov     r3, #0x8
+	strh    r3, [r1]        /* force dsp+arm reset */
+_loop_forever:
+	b	_loop_forever
+rstctl1:
+	.word	0xfffece10

cpu/mpc5xxx/Makefile

@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(CPU).a
+
+START	= start.o
+ASOBJS	= io.o firmware_sc_task_bestcomm.impl.o firmware_sc_task.impl.o
+OBJS	= traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o \
+	  loadtask.o fec.o
+
+all:	.depend $(START) $(ASOBJS) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) crv $@ $(ASOBJS) $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(START:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(START:.o=.S) $(ASOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

cpu/mpc5xxx/config.mk

@@ -0,0 +1,27 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -mrelocatable -ffixed-r14 -meabi
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC5XXX -ffixed-r2 -ffixed-r29 \
+		     -mstring -mcpu=603e -mmultiple