* Fix "cls" command when used with splash screen

* Increase NFS download timeout (now 1 min - 10 sec is to short for a
  slow download of a big image)

CHANGELOG

@@ -1,10 +1,840 @@
 ======================================================================
-Changes since U-Boot 1.0.1:
+Changes since U-Boot 1.1.1:
 ======================================================================
 
+* Fix "cls" command when used with splash screen
+
+* Increase NFS download timeout (now 1 min - 10 sec is to short for a
+  slow download of a big image)
+
+* Add "cls" function to MPC823 LCD driver so we can reinitialize the
+  display even after showing a bitmap
+
+* Patch by Josef Wagner, 04 Jun 2004:
+  - DDR Ram support for PM520 (MPC5200)
+  - support for different flash types (PM520)
+  - USB / IDE / CF-Card / DiskOnChip support for PM520
+  - 8 bit boot rom support for PM520/CE520
+  - Add auto SDRAM module detection for MicroSys CPC45 board (MPC8245)
+  - I2C and RTC support for CPC45
+  - support of new flash type (28F160C3T) for CPC45
+
+* Fix flash parameters passed to Linux for PPChameleon board
+
+* Remove eth_init() from lib_arm/board.c; it's done in net.net.c.
+
+* Patch by Paul Ruhland, 10 Jun 2004:
+  fix support for Logic SDK-LH7A404 board and clean up the
+  LH7A404 register macros.
+
+* Patch by Matthew McClintock, 10 Jun 2004:
+  Modify code to select correct serial clock on Sandpoint8245
+
+* Patch by Robert Schwebel, 10 Jun 2004:
+  Add support for Intel K3 strata flash.
+
+* Patch by Thomas Brand, 10 Jun 2004:
+  Fix "loads" command on DK1S10 board
+
+* Patch by Yuli Barcohen, 09 Jun 2004:
+  Add support for 8MB flash SIMM and JFFS2 file system on
+  Motorola FADS board and its derivatives (MPC86xADS, MPC885ADS).
+
+* Patch by Yuli Barcohen, 09 Jun 2004:
+  Add support for Analogue&Micro Adder87x and the older AdderII board.
+
+* Patch by Ming-Len Wu, 09 Jun 2004:
+  Add suppport for MC9328 (Dargonball) CPU and Motorola MX1ADS board
+
+* Patch by Sam Song, 09 Jun 2004:
+  - Add support for RPXlite_DW board
+  - Update FLASH driver for 4*AM29DL323DB90VI
+  - Add option configuration of CFG_ENV_IS_IN_NVRAM on RPXlite_DW board
+
+* Patch by Mark Jonas, 08 June 2004:
+  - Make MPC5200 boards evaluate the SVR to print processor name and
+    version in checkcpu() (cpu/mpc5xxx/cpu.c).
+
+* Patch by Kai-Uwe Bloem, 06 May 2004:
+  Fix endianess problem in cramfs code
+
+* Patch by Tom Armistead, 04 Jun 2004:
+  Add support for MAX6900 RTC
+
+* Patches by Ladislav Michl, 03 Jun 2004:
+  - fix cfi_flash.c on LE systems
+  - let 'make mrproper' delete u-boot.img as well
+  - turn printf into debug in cfi_flash.c
+
+* Patch by Kurt Stremerch, 28 May 2004:
+  Add support for Exys XSEngine board
+
+* Patch by Martin Krause, 27 May 2004:
+  Fix a MPC5xxx I2C timing issue in i2c_probe().
+
+* Patch by Leif Lindholm, 27 May 2004:
+  Fix board_init_f() for dbau1x00 board.
+
+* Patch by Imre Deak, 26 May 2004:
+  On OMAP1610 platforms check if booting from RAM(CS0) or flash(CS3).
+  Set flash base accordingly, and decide whether to do or skip board
+  specific setup steps.
+
+* Patch by Josef Baumgartner, 26 May 2004:
+  Add missing define in include/asm-m68k/global_data.h
+
+* Patch by Josef Baumgartner, 25 May 2004:
+  Add missing functions get_ticks() and get_tbclk() in lib_m68k/time.c
+
+* Patch by Paul Ruhland, 24 May 2004:
+  fix SDRAM initialization for LPD7A400 board.
+
+* Patch by Jian Zhang, 20 May 2004:
+  add support for environment in NAND flash
+
+* Patch by Yuli Barcohen, 20 May 2004:
+  Add support for Interphase iSPAN boards.
+
+* Patches by Paul Ruhland, 17 May 2004:
+  - Add I/O functions to the smc91111 ethernet driver to support the
+    Logic LPD7A40x boards.
+  - Add support for the Logic Zoom LH7A40x based SDK board(s),
+    specifically the LPD7A400.
+
+* Patches by Robert Schwebel, 15 May 2004:
+  - call MAC address reading code also for SMSC91C111;
+  - make SMSC91C111 timeout configurable, remove duplicate code
+  - fix get_timer() for PXA
+  - update doc/README.JFFS2
+  - use "bootfile" env variable also for jffs2
+
+* Patch by Tolunay Orkun, 14 May 2004:
+  Add support for Cogent CSB472 board (8MB Flash Rev)
+
+* Patch by Thomas Viehweger, 14 May 2004:
+  - flash.h: more flash types added
+  - immap_8260.h: some bits added (useful for RMII)
+  - cmd_coninfo.c: typo corrected, printf -> puts
+  - reduced size by replacing spaces with tab
+
+* Patch by Robert Schwebel, 13 May 2004:
+  Add 'imgextract' command: extract one part of a multi file image.
+
+* Patches by Jon Loeliger, 11 May 2004:
+  Dynamically handle REV1 and REV2 MPC85xx parts.
+    (Jon Loeliger, 10-May-2004).
+  New consistent memory map and Local Access Window across MPC85xx line.
+  New CCSRBAR at 0xE000_0000 now.
+  Add RAPID I/O memory map.
+  New memory map in README.MPC85xxads
+    (Kumar Gala, 10-May-2004)
+  Better board and CPU identification on MPC85xx boards at boot.
+    (Jon Loeliger, 10-May-2004)
+  SDRAM clock control fixes on MPC8540ADS & MPC8560 boards.
+  Some configuration options for MPC8540ADS & MPC8560ADS cleaned up.
+    (Jim Robertson, 10-May-2004)
+  Rewrite of the MPC85xx Three Speed Ethernet Controller (TSEC) driver.
+  Supports multiple PHYs.
+    (Andy Fleming, 10-May-2004)
+  Some README.MPC85xxads updates.
+    (Kumar Gala, 10-May-2004)
+  Copyright updates for "Freescale"
+    (Andy Fleming, 10-May-2004)
+
+* Patch by Stephen Williams, 11 May 2004:
+  Add flash support for ST M29W040B
+  Reduce JSE specific flash.c to remove dead code.
+
+* Patch by Markus Pietrek, 04 May 2004:
+  Fix clear_bss code for ARM systems (all except s3c44b0 which
+  doesn't clear BSS at all?)
+
+* Fix "ping" problem on INC-IP board. Strange problem:
+  Sometimes the store word instruction hangs while writing to one of
+  the Switch registers, but only if the next instruction is 16-byte
+  aligned. Moving the instruction into a separate function somehow
+  makes the problem go away.
+
+* Patch by Rishi Bhattacharya, 08 May 2004:
+  Add support for TI OMAP5912 OSK Board
+
+* Patch by Sam Song May, 07 May 2004:
+  Fix typo of UPM table for rmu board
+
+* Patch by Pantelis Antoniou, 05 May 2004:
+  - Intracom board update.
+  - Add Codec POST.
+
+* Add support for the second Ethernet interface for the 'PPChameleon'
+  board.
+
+* Patch by Dave Peverley, 30 Apr 2004:
+  Add support for OMAP730 Perseus2 Development board
+
+* Patch by Alan J. Luse, 29 Apr 2004:
+  Fix flash chip-select (OR0) option register setting on FADS boards.
+
+* Patch by Alan J. Luse, 29 Apr 2004:
+  Report MII network speed and duplex setting properly when
+  auto-negotiate is not enabled.
+
+* Patch by Jarrett Redd, 29 Apr 2004:
+  Fix hang on reset on Ocotea board due to flash in wrong mode.
+
+* Patch by Dave Peverley, 29 Apr 2004:
+  add MAC address detection to smc91111 driver
+
+* Patch by David Müller, 28 Apr 2004:
+  fix typo in lib_arm/board.c
+
+* Patch by Tolunay Orkun, 20 Apr 2004:
+  - README update: add CONFIG_CSB272 and csb272_config
+  - add descriptions for some MII/PHY options, CONFIG_I2CFAST, and
+    i2cfast environment variable
+
+* Patch by Yuli Barcohen, 19 Apr 2004:
+  - Rename DUET_ADS to MPC885ADS
+  - Rename CONFIG_DUET to CONFIG_MPC885_FAMILY
+  - Rename CONFIG_866_et_al to CONFIG_MPC866_FAMILY
+  - Clean up FADS family port to use the new defines
+
+* Fix PCI support on CPC45 board
+
+* Patch by Scott McNutt, 25 Apr 2004:
+  Add Nios GDB/JTAG Console support:
+  - Add stubs to support gdb via JTAG.
+  - Add support for console over JTAG.
+  - Minor cleanup.
+
+* Add support for CATcenter board (based on PPChameleon ME module)
+
+* Patch by Klaus Heydeck, 12 May 2004:
+  Using external watchdog for KUP4 boards in mpc8xx/cpu.c;
+  load_sernum_ethaddr() for KUP4 boards in lib_ppc/board.c;
+  various changes to KUP4 board specific files
+
+* Fix minor network problem on MPC5200: need some delay between
+  resetting the PHY and sending the first packet. Implemented in a
+  "natural" way by invoking the PHY reset and initialization code
+  only once after power on vs. each time the interface is brought up.
+
+* Add some limited support for low-speed devices to SL811 USB controller
+  (at least "usb reset" now passes successfully and "usb info" displays
+  correct information)
+
+* Change init sequence for multiple network interfaces: initialize
+  on-chip interfaces before external cards.
+
+* Fix memory leak in the NAND-specific JFFS2 code
+
+* Fix SL811 USB controller when attached to a USB hub
+
+* Fix config option spelling in PM520 config file
+
+* Fix PHY discovery problem in cpu/mpc8xx/fec.c (introduced by
+  patches by Pantelis Antoniou, 30 Mar 2004)
+
+* Fix minor NAND JFFS2 related issue
+
+* Fixes for SL811 USB controller:
+  - implement workaround for broken memory stick
+  - improve error handling
+
+* Increase packet send timeout to 1 ms in cpu/mpc8xx/scc.c to better
+  cope with congested networks.
+
+======================================================================
+Changes for U-Boot 1.1.1:
+======================================================================
+
+* Patch by Travis Sawyer, 23 Apr 2004:
+  Fix VSC/CIS 8201 phy descrambler interoperability timing due to
+  errata from Vitesse Semiconductor.
+
+* Patch by Philippe Robin, 22 Apr 2004:
+  Fix ethernet configuration for "versatile" board
+
+* Patch by Kshitij Gupta, 21 Apr 2004:
+  Remove busy loop and use MPU timer fr usleep() on OMAP1510/1610 boards
+
+* Patch by Steven Scholz, 24 Feb 2004:
+  Fix a bug in AT91RM9200 ethernet driver:
+  The MII interface is now initialized before accessing the PHY.
+
+* Patch by John Kerl, 19 Apr 2004:
+  Use U-boot's miiphy.h for PHY register names, rather than
+  introducing a new header file.
+
+* Update pci_ids.h from linux-2.4.26
+
+* Patch by Masami Komiya, 19 Apr 2004:
+  Fix problem cause by VLAN function on little endian architecture
+  without VLAN environment
+
+* Clean up the TQM8xx_YYMHz configurations; allow to use the same
+  binary image for all clock frequencies. Implement run-time
+  optimization of flash access timing based on the actual bus
+  frequency.
+
+* Modify KUP4X board configuration to use SL811 driver for USB memory
+  sticks (including FAT / VFAT filesystem support)
+
+* Add SL811 Host Controller Interface driver for USB
+
+* Add CFG_I2C_EEPROM_ADDR_OVERFLOW desription to README
+
+* Patch by Pantelis Antoniou, 19 Apr 2004:
+  Allow to use shell style syntax (i. e. ${var} ) with standard parser.
+  Minor patches for Intracom boards.
+
+* Patch by Christian Pell, 19 Apr 2004:
+  cleanup support for CF/IDE on PCMCIA for PXA25X
+
+* Temporarily disabled John Kerl's extended MII command code because
+  "miivals.h" is missing
+
+* Patches by Mark Jonas, 13 Apr 2004:
+  - Remove CS0 chip select timing setting from cpu/mpc5xxx/start.S
+  - Add sync instructions to IceCube SDRAM init code
+  - Move SDRAM chip constants into seperate include files
+  - Unify DDR and SDR initialization code
+  - Unify all IceCube (Lite5xxx) target names
+
+* Patch by John Kerl, 16 Apr 2004:
+  Enable ranges in mii command, e.g. mii read 0-1f 0 or
+  mii read 4-7 18-1a.  Also add mii dump subcommand for
+  pretty-printing standard regs 0-5.
+
+* Patch by  Stephen Williams, 16 April 2004:
+  fix typo in JSE.h; update MAINTAINERS
+
+* Patch by Matthew S. McClintock, 14 Apr 2004:
+  fix initdram function for utx8245 board
+
+* Patch by Markus Pietrek, 14 Apr 2004:
+  use ATAG_INITRD2 instead of deprecated ATAG_INITRD tag
+
+* Patch by Reinhard Meyer, 18 Apr 2004:
+  provide the IDE Reset Function for EMK 5200 boards
+
+* Patch by Masami Komiya, 12 Apr 2004:
+  fix pci_hose_write_config_{byte,word}_via_dword problems
+
+* Patch by Sangmoon Kim, 12 Apr 2004:
+  Update max RAM size for debris board
+
+* Patch by Travis Sawyer, 08 Apr 2004:
+  Add TLB entry for second DIMM slot on ocotea
+
+* Patch by Masami Komiya, 08 Apr 2004:
+  add RTL8169 network driver
+
+* Patch by Dan Malek, 07 Apr 2004:
+  - Add support for RPC/STx GP3, Motorola 8560 board
+  - Update 85xx TSEC driver so it searches MII for first available PHY
+    and uses that one.
+  - Add functions to support console MII commands.
+
+* Patch by Tolunay Orkun, 07 Apr 2004:
+  Move initialization of bi_iic_fast[]
+  from board_init_f() to board_init_r()
+
+* Patch by Yasushi Shoji, 07 Apr 2004:
+  Cleanup microblaze port
+
+* Patch by Sangmoon Kim, 07 Apr 2004:
+  Add auto SDRAM module detection for Debris board
+
+* Patch by Rune Torgersen, 06 Apr 2004:
+  - Fix some PCI problems on the MPC8266ADS board
+  - Fix the location of some PCI entries in the immap structure
+
+* Patch by Yasushi Shoji, 07 Apr 2004:
+  - add support for microblaze processors
+  - add support for AtmarkTechno "suzaku" board
+
+* Configure PPChameleon board to use redundand environment in flash
+
+* Configure PPChameleon board to use JFFS2 NAND support.
+
+* Added support for JFFS2 filesystem (read-only) on top of NAND flash
+
+* Patch by Rune Torgersen, 16 Apr 2004:
+  LBA48 fixes
+
+* Patches by Pantelis Antoniou, 16 Apr 2004:
+  - add support for a new version of an Intracom board and fix
+    various other things on others.
+  - add verify support to the crc32 command (define
+    CONFIG_CRC32_VERIFY to enable it)
+  - fix FEC driver for MPC8xx systems:
+    1. fix compilation problems for boards that use dynamic
+       allocation of DPRAM
+    2. shut down FEC after network transfers
+  - HUSH parser fixes:
+    1. A new test command was added. This is a simplified version of
+       the one in the bourne shell.
+    2. A new exit command was added which terminates the current
+       executing script.
+    3. Fixed handing of $? (exit code of last executed command)
+  - Fix some compile problems;
+    add "once" functionality for the netretry variable
+
+* Patch by George G. Davis, 02 Apr 2004:
+  add support for Intel Assabet board
+
+* Patch by Stephen Williams, 01 Apr 2004:
+  Add support for Picture Elements JSE board
+
+* Patch by Christian Pell, 01 Apr 2004:
+  Add CompactFlash support for PXA systems.
+
+* Patches by Pantelis Antoniou, 30 Mar 2004:
+  - add auto-complete support to the U-Boot CLI
+  - add support for NETTA and NETPHONE boards; fix NETVIA board
+  - add support for the Epson 156x series of graphical displays
+    (These displays are serial and not suitable for using a normal
+    framebuffer console on them)
+  - add infrastructure needed in order to POST any DSPs in a board
+  - improve and fix various things in the MPC8xx FEC driver:
+    1. The new 87x and 88x series of processors have two FECs,
+       and the new driver supports them both.
+    2. Another change in the 87x/88x series is support for
+       the RMII (Reduced MII) interface. However numerous
+       changes are needed to make it work since the PHYs
+       are connected to the same lines. That means that
+       you have to address them correctly over the MII
+       interface.
+    3. We now correctly match the MII/RMII interface
+       configuration to what the PHY reports.
+  - Fix problem when readingthe MII status register. Due to the
+    internal design of many PHYs you have to read the register
+    twice. The problem is more apparent in 10Mbit mode.
+  - add new mode ".jffs2s" for reading from a NAND device: it just
+    skips over bad blocks.
+  - add networking support for VLANs (802.1q), and CDP (Cisco
+    Discovery Protocol)
+  - some minor patches / cleanup
+
+* Patch by Yuli Barcohen, 28 Mar 2004:
+  - Add support for MPC8272 family including MPC8247/8248/8271/8272
+  - Add support for MPC8272ADS evaluation board (another flavour of MPC8260ADS)
+  - Change configuration method for MPC8260ADS family
+
+* add startup code to clear the BSS of standalone applications
+
+* Fix if / elif handling bug in HUSH shell
+
+======================================================================
+Changes for U-Boot 1.1.0:
+======================================================================
+
+* Patch by Mark Jonas: Remove config.tmp files only when
+  unconfiguring the board
+
+* Adapt RMU board for bigger flash memory
+
+* Patch by Klaus Heydeck, 13 Mar 2003:
+  Add support for KUP4X Board
+
+* Patch by Pavel Bartusek, 21 Mar 2004
+  Add Reiserfs support
+
+* Patch by Hinko Kocevar, 20 Mar 2004
+  - Add auto-release for SMSC LAN91c111 driver
+  - Add save/restore of PTR and PNR regs as suggested in datasheet
+
+* Patch by Stephen Williams, 19 March 2004
+  Increase speed of sector reads from SystemACE,
+  shorten poll timeout and remove a useless reset
+
+* Patch by Tolunay Orkun, 19 Mar 2004:
+  Make GigE PHY 1000Mbps Speed/Duplex detection conditional
+  (CONFIG_PHY_GIGE)
+
+* Patch by Brad Kemp, 18 Mar 2004:
+  prevent machine checks during a PCI scan
+
+* Patch by Pierre Aubert, 18 Mar 2004:
+  Fix string cleaning in IDE identification
+
+* Patch by Pierre Aubert, 18 Mar 2004:
+  - Unify video mode handling for Chips & Technologies 69000 Video
+    chip and Silicon Motion SMI 712/710/810 Video chip
+  - Add selection of the video output (CRT or LCD) via 'videoout'
+    environment variable for the Silicon Motion
+  - README update
+
+* Patch by Pierre Aubert, 18 Mar 2004:
+  include/common.h typo fix
+
+* Patches by Tolunay Orkun, 17 Mar 2004:
+  - Add support for bd->bi_iic_fast[] initialization via environment
+    variable "i2cfast" (CONFIG_I2CFAST)
+  - Add "i2cfast" u-boot environment variable support for csb272
+
+* Patch by Carl Riechers, 17 Mar 2004:
+  Ignore '\0' characters in console input for use with telnet and
+  telco pads.
+
+* Patch by Leon Kukovec, 17 Mar 2004:
+  typo fix for strswab prototype #ifdef
+
+* Patches by Thomas Viehweger, 16 Mar 2004:
+  - show PCI clock frequency on MPC8260 systems
+  - add FCC_PSMR_RMII flag for HiP7 processors
+  - in do_jffs2_fsload(), take load address from load_addr if not set
+    explicit, update load_addr otherwise
+  - replaced printf by putc/puts when no formatting is needed
+    (smaller code size, faster execution)
+
+* Patch by Phillippe Robin, 16 Mar 2004:
+  avoid dereferencing NULL pointer in lib_arm/armlinux.c
+
+* Patch by Stephen Williams, 15 Mar 2004:
+  Fix CONFIG_SERIAL_SOFTWARE_FIFO documentation
+
+* Patch by Tolunay Orkun, 15 Mar 2004:
+  Initialize bi_opbfreq to real OPB frequency via get_OPB_freq()
+
+* Patch by Travis Sawyer, 15 Mar 2004:
+  Update CREDITS & MAINTAINERS files for PPC440GX & Ocotea port
+
+* Add start-up delay to make sure power has stabilized before
+  attempting to switch on USB on SX1 board.
+
+* Patch by Josef Wagner, 18 Mar 2004:
+  - Add support for MicroSys XM250 board (PXA255)
+  - Add support for MicroSys PM828 board (MPC8280)
+  - Add support for 32 MB Flash on PM825/826
+  - new SDRAM refresh rate for PM825/PM826
+  - added support for MicroSys PM520 (MPC5200)
+  - replaced Query by Identify command in CPU86/flash.c
+    to support 28F160F3B
+
+* Fix wrap around problem with udelay() on ARM920T
+
+* Add support for Macronix flash on TRAB board
+
+* Patch by Pierre Aubert, 15 Mar 2004:
+  Fix buffer overflow in IDE identification
+
+* Fix power-off of LCD for out-of-band temperatures on LWMON board
+
+* Remove redundand #define in IceCube.h
+
+* Patch by Steven Scholz, 27 Feb 2004:
+  - Adding get_ticks() and get_tbclk() for AT91RM9200
+  - Many white space fixes in cpu/at91rm9200/interrupts.c
+
+* Patches by Steven Scholz, 20 Feb 2004:
+  some cleanup in AT91RM9200 related code
+
+* Patches by Travis Sawyer, 12 Mar 2004:
+  - Fix Gigabit Ethernet support for 440GX
+  - Add Gigabit Ethernet Support to MII PHY utilities
+
+* Patch by Brad Kemp, 12 Mar 2004:
+  Fixes for drivers/cfi_flash.c:
+  - Better support for x8/x16 implementations
+  - Added failure for AMD chips attempting to use CFG_FLASH_USE_BUFFER_WRITE
+  - Added defines for AMD command and address constants
+
+* Patch by Leon Kukovec, 12 Mar 2004:
+  Fix get_dentfromdir() to correctly handle deleted dentries
+
+* Patch by George G. Davis, 11 Mar 2004:
+  Remove hard coded network settings in TI OMAP1610 H2
+  default board config
+
+* Patch by George G. Davis, 11 Mar 2004:
+  add support for ADS GraphicsClient+ board.
+
+* Patch by Pierre Aubert, 11 Mar 2004:
+  - add bitmap command and splash screen support in cfb console
+  - add [optional] origin in the bitmap display command
+
+* Patch by Travis Sawyer, 11 Mar 2004:
+  Fix ocotea board early init interrupt setup.
+
+* Patch by Thomas Viehweger, 11 Mar 2004:
+  Remove redundand code; add  PCI-specific bits to include/mpc8260.h
+
+* Patch by Stephan Linz, 09 Mar 2004
+  - Add support for the SSV ADNP/ESC1 (Nios Softcore)
+
+* Patch by George G. Davis, 9 Mar 2004:
+  fix recent build failure for SA1100 target
+
+* Patch by Travis Sawyer, 09 Mar 2004:
+  Support native interrupt mode for the IBM440GX.
+  Previously it was running in 440GP compatibility mode.
+
+* Patch by Philippe Robin, 09 Mar 2004:
+  Added ARM Integrator AP, CP and Versatile PB926EJ-S Reference
+  Platform support.
+
+* Patch by Masami Komiya, 08 Mar 2004:
+  Don't overwrite server IP address or boot file name
+  when the boot server does not return values
+
+* Patch by Tolunay Orkun, 5 Mar 2004:
+  Removed compile time restriction on CFG_I2C_SPEED for DS1338 RTC
+
+* Patch by Tolunay Orkun, 5 Mar 2004:
+  Fix early board initialization for Cogent CSB272 board
+
+* Patch by Ed Okerson, 3 Mar 2004:
+  fix CFI flash writes for little endian systems
+
+* Patch by Reinhard Meyer, 01 Mar 2004:
+  generalize USB and IDE support for MPC5200 with according
+  changes to IceCube.h and TOP5200.h
+  add Am29LV256 256 MBit FLASH support for TOP5200 boards
+  add info about USB and IDE to README
+
+* Patch by Yuli Barcohen, 4 Mar 2004:
+  Fix problems with GCC 3.3.x which changed handling of global
+  variables explicitly initialized to zero (now in .bss instead of
+  .data as before).
+
+* Patch by Leon Kukovec, 02 Mar 2004:
+  add strswab() to fix IDE LBA capacity, firmware and model numbers
+  on little endian machines
+
+* Patch by Masami Komiya, 02 Mar 2004:
+  - Remove get_ticks() from NFS code
+  - Add verification of RPC transaction ID
+
+* Patch by Pierre Aubert, 02 Mar 2004:
+  cleanup for IDE and USB drivers for MPC5200
+
+* Patch by Travis Sawyer, 01 Mar 2004:
+  Ocotea:
+  - Add IBM PPC440GX Ref Platform support (Ocotea)
+    Original code by Paul Reynolds <PaulReynolds@lhsolutions.com>
+    Adapted to U-Boot and 440GX port
+  440gx_enet.c:
+  - Add gracious handling of all Ethernet Pin Selections for 440GX
+  - Add RGMII selection for Cicada CIS8201 Gigabit PHY
+  ppc440.h:
+  - Add needed bit definitions
+  - Fix formatting
+
+* Patch by Carl Riechers, 1 Mar 2004:
+  Add PPC440GX prbdv0 divider to fix memory clock calculation.
+
+* Patch by Stephan Linz, 27 Feb 2004
+  - avoid problems for targets without NFS download support
+
+* Patch by Rune Torgersen, 27 Feb 2004:
+  - Added LBA48 support (CONFIG_LBA48 & CFG_64BIT_LBA)
+  - Added support for 64bit printing in vsprintf (CFG_64BIT_VSPRINTF)
+  - Added support for 64bit strtoul (CFG_64BIT_STRTOUL)
+
+* Patch by Masami Komiya, 27 Feb 2004:
+  Fix rarpboot: add autoload by NFS
+
+* Patch by Dan Eisenhut, 26 Feb 2004:
+  fix flash_write return value in saveenv
+
+* Patch by Stephan Linz, 11 Dec 2003
+  expand config.mk to avoid trigraph warnings on NIOS
+
+* Rename "BMS2003" board into "HMI10"
+
+* SX1 patches: use "serial#" for USB serial #; use redundand environment
+  storage; auto-set console on USB port (using preboot command)
+
+* Add support for SX1 mobile phone; add support for USB-based console
+  (enable with "setenv stdout usbtty; setenv stdin usbtty")
+
+* Fix LOWBOOT configuration for MPC5200 with DDR memory
+
+* Fix SDRAM timings for LITE5200 / IceCube board
+
+* Handle Auti-MDIX / connection status for INCA-IP
+
+* Fix USB problems when attempting to read 0 bytes
+
+* Patch by Travis Sawyer, 26 Feb 2004:
+  Fix broken compile for XPEDITE1K target.
+
+* Patch by Stephan Linz, 26 Feb 2004:
+  Bug fix for NFS code on NIOS targets
+
+* Patch by Stephen Williams, 26 Feb 2004:
+  Break up SystemACE reads of large block counts
+
+* Patch by Pierre Aubert, 26 Feb 2004
+  add IDE support for MPC5200
+
+* Patch by Masami Komiya, 26 Feb 2004:
+  add autoload via NFS
+
+* Patch by Stephen Williams
+  Use of CONFIG_SERIAL_SOFTWARE_FIFO in board.c consistent with uses
+  elsewhere in the source.
+
+* Patch by Steven Scholz, 25 Feb 2004:
+  - Timeouts in FPGA code should be based on CFG_HZ
+  - Minor cleanup in code for Altera FPGA ACEX1K
+
+* Patch by Steven Scholz, 25 Feb 2004:
+  Changed "Directory Hierarchy" section in README
+
+* Patch by Masami Komiya, 25 Feb 2004:
+  Reduce copy count in nfs_read_reply() of NFS code
+
+* Patch by Markus Pietrek, 24 Feb 2004:
+  NS9750 DevBoard added
+
+* Patch by Pierre Aubert, 24 Feb 2004
+  add USB support for MPC5200
+
+* Patch by Steven Scholz, 24 Feb 2004:
+  - fix MII commands to use values from last command
+
+* Patch by Torsten Demke, 24 Feb 2004:
+  Add support for the eXalion platform (SPSW-8240, F-30, F-300)
+
+* Patch by Rahul Shanbhag, 19 Feb 2004:
+  Fixes for for OMAP1610 board:
+  - shift some IRQ specific code to platform.S file
+  - remove duplicatewatchdog reset code from start.S
+
+* Make Auto-MDIX Support configurable on INCA-IP board
+
+* Fix license for mkimage tool
+
+* Patch by Masami Komiya, 24 Feb 2004:
+  Update NetBootFileXferSize in NFS code
+
+* Patch by Scott McNutt, 24 Feb 2004:
+  fix packet length in NFS code
+
+* Patch by Masami Komiy, 22 Feb 2004:
+  Add support for NFS for file download
+
+* Patch by Andrea Scian, 17 Feb 2004:
+  Add support for S3C44B0 processor and DAVE B2 board
+
+* Patch by Steven Scholz, 20 Feb 2004:
+  - Add support for MII commands on AT91RM9200 boards
+  - some cleanup in AT91RM9200 ethernet code
+
+* Patch by Peter Ryser, 20 Feb 2004:
+  Add support for the Xilinx ML300 platform
+
+* Patch by Stephan Linz, 17 Feb 2004:
+  Fix watchdog support for NIOS
+
+* Patch by Josh Fryman, 16 Feb 2004:
+  Fix byte-swapping for cfi_flash.c for different bus widths
+
+* Patch by Jon Diekema, 14 Jeb 2004:
+  Remove duplicate "FPGA Support" notes from the README file
+
+* Patches by Reinhard Meyer, 14 Feb 2004:
+  - update board/emk tree; use common flash driver
+  - Corrected tested bits in machine check exception in cpu/mpc5xxx/traps.c
+    [adapted for other PPC CPUs -- wd]
+  - Added support for the M48T08 on the EVAL5200 board in rtc/mk48t59.c
+
+* Patch by Jon Diekema, 13 Feb 2004:
+  Call show_boot_progress() whenever POST "FAILED" is printed.
+
+* Patch by Nishant Kamat, 13 Feb 2004:
+  Add support for TI OMAP1610 H2 Board
+  Fixes for cpu/arm926ejs/interrupt.c
+	(based on Richard Woodruff's patch for arm925, 16 Oct 03)
+  Fix for a timer bug in OMAP1610 Innovator
+  Add support for CS0 (ROM)/CS3 (Flash) boot in OMAP1610 Innovator and H2
+
+* Patches by Stephan Linz, 12 Feb 2004:
+  - add support for NIOS timer with variable period preload counter value
+  - prepare POST framework support for NIOS targets
+
+* Patch by Denis Peter, 11 Feb 2004:
+  add POST support for the MIP405 board
+
+* Patch by Laurent Mohin, 10 Feb 2004:
+  Fix buffer overflow in common/usb.c
+
+* Patch by Tolunay Orkun, 10 Feb 2004:
+  Add support for Cogent CSB272 board
+
+* Patch by Thomas Elste, 10 Feb 2004:
+  Add support for NET+50 CPU and ModNET50 board
+
+* Patch by Sam Song, 10 Feb 2004:
+  Fix typos in cfi_flash.c
+
+* Patch by Leon Kukovec, 10 Feb 2004
+  Fixed long dir entry slot id calculation in get_vfatname
+
+* Patch by Robin Gilks, 10 Feb 2004:
+  add "itest" command (operators: -eq, -ne, -lt, -gt, -le, -ge, ==,
+  !=, <>, <, >, <=, >=)
+
+* Fix problem with side effects in macros in include/usb.h
+
+* Patch by David Benson, 13 Nov 2003:
+  bug 841358 - fix TFTP download size limit
+
+* Fixing bug 850768:
+  improper flush_cache() in load_serial()
+
+* Fixing bug 834943:
+  MPC8540 - missing volatile declarations
+
+* Patch by Stephen Williams, 09 Feb 2004:
+  Add support for Xilinx SystemACE chip:
+  - New files common/cmd_ace.c and include/systemace.h
+  - Hook systemace support into cmd_fat and the partition manager
+
+* Patch by Travis Sawyer, 09 Feb 2004:
+  Add bi_opbfreq & bi_iic_fast to 440GX bd_info as needed for Linux
+
+* Patch by Travis Sawyer, 09 Feb 2004:
+  o 440GX:
+    - Fix PCI Indirect access for type 1 config cycles with ppc440.
+    - Add phymode for 440 enet
+    - fix pci pre init
+  o XPedite1K:
+    - Change board_pre_init to board_early_init_f
+    - Add user flash to bus controller setup
+    - Fix pci pre init
+    - Fix is_pci_host to check GPIO for monarch bit
+    - Force xpedite1k to pci conventional mode (via #define option)
+
+* Patch by Brad Kemp, 4 Feb 2004:
+  - handle the machine check that is generated during the PCI scans
+    on 82xx processors.
+  - define the registers used in the IMMR by the PCI subsystem.
+
+* Patch by Pierre Aubert, 03 Feb 2004:
+  cpu/mpc5xxx/start.S: copy MBAR into SPR311
+
+* Patch by Jeff Angielski, 03 Feb 2004:
+  Fix copy & paste error in cpu/mpc8260/pci.c
+
+* Patch by Reinhard Meyer, 24 Jan 2004:
+  Fix typo in cpu/mpc5xxx/pci_mpc5200.c
+
+* Add Auto-MDIX support for INCA-IP
+
+* Some code cleanup
+
+* Patch by Josef Baumgartner, 10 Feb 2004:
+  Fixes for Coldfire port
+
+* Patch by Brad Kemp, 11 Feb 2004:
+  Fix CFI flash driver problems
+
 * Make sure to use a bus clock divider of 2 only when running TQM8xxM
   modules at CPU clock frequencies above 66 MHz.
-  
+
 * Optimize flash programming speed for LWMON (by another 100% :-)
 
 * Patch by Jian Zhang, 3 Feb 2004:

CREDITS

@@ -28,16 +28,29 @@ D: ERIC Support
 
 N: Pantelis Antoniou
 E: panto@intracom.gr
-D: NETVIA board support, ARTOS support.
+D: NETVIA & NETPHONE board support, ARTOS support.
 
 N: Pierre Aubert
 E: <p.aubert@staubli.com>
 D: Support for RPXClassic board
 
+N: Yuli Barcohen
+E: yuli@arabellasw.com
+D: Unified support for Motorola MPC826xADS/MPC8272ADS/PQ2FADS boards.
+D: Support for Zephyr Engineering ZPC.1900 board.
+D: Support for Interphase iSPAN boards.
+D: Support for Analogue&Micro Adder boards.
+W: http://www.arabellasw.com
+
 N: Jerry van Baren
 E: <vanbaren@cideas.com>
 D: BedBug port to 603e core (MPC82xx). Code for enhanced memory test.
 
+N: Pavel Bartusek
+E: <pba@sysgo.com>
+D: Reiserfs support
+W: http://www.elinos.com
+
 N: Andre Beaudin
 E: <andre.beaudin@colubris.com>
 D: PCMCIA, Ethernet, TFTP
@@ -78,6 +91,10 @@ N: Magnus Damm
 E: damm@opensource.se
 D: 8xxrom
 
+N: George G. Davis
+E: gdavis@mvista.com
+D: Board ports for ADS GraphicsClient+ and Intel Assabet
+
 N: Arun Dharankar
 E: ADharankar@ATTBI.Com
 D: threads / scheduler example code
@@ -103,6 +120,11 @@ N: Dave Ellis
 E: DGE@sixnetio.com
 D: EEPROM Speedup, SXNI855T port
 
+N: Thomas Elste
+E: info@elste.org
+D: Port for the ModNET50 Board, NET+50 CPU Port
+W: http://www.imms.de
+
 N: Daniel Engström
 E: daniel@omicron.se
 D: x86 port, Support for sc520_cdp board
@@ -178,6 +200,10 @@ N: Yoo. Jonghoon
 E: yooth@ipone.co.kr
 D: Added port to the RPXlite board
 
+N: Sam Song
+E: samsongshu@yahoo.com.cn
+D: Port to the RPXlite_DW board
+
 N: Brad Kemp
 E: Brad.Kemp@seranoa.com
 D: Port to Windriver ppmc8260 board
@@ -211,6 +237,7 @@ W: http://www.leox.org
 N: Stephan Linz
 E: linz@li-pro.net
 D: Support for Nios Stratix Development Kit (DK-1S10)
+D: Support for SSV ADNP/ESC1 (Nios Cyclone)
 W: http://www.li-pro.net
 
 N: Raymond Lo
@@ -246,6 +273,10 @@ E: rof@sysgo.de
 D: Initial support for SSV-DNP1110, SMC91111 driver
 W: www.elinos.com
 
+N: Tolunay Orkun
+E: torkun@nextio.com
+D: Support for Cogent CSB272 & CSB472 boards
+
 N: Keith Outwater
 E: keith_outwater@mvis.com
 D: Support for generic/custom MPC860T boards (GEN860T, GEN860T_SC)
@@ -260,6 +291,11 @@ D: Support for 4xx SCSI, floppy, CDROM, CT69000 video, ...
 D: Support for PIP405 board
 D: Support for MIP405 board
 
+N: Dave Peverley
+E: dpeverley@mpc-data.co.uk
+W: http://www.mpc-data.co.uk
+D: OMAP730 P2 board support
+
 N: Bill Pitts
 E: wlp@mindspring.com
 D: BedBug embedded debugger code
@@ -272,13 +308,17 @@ N: Erwin Rol
 E: erwin@muffin.org
 D: boot support for RTEMS
 
+N: Paul Ruhland
+E: pruhland@rochester.rr.com
+D: Port to Logic Zoom LH7A40x SDK board(s)
+
 N: Neil Russell
 E: caret@c-side.com
 D: Author of LiMon-1.4.2, which contributed some ideas
 
 N: Travis B. Sawyer
 E: travis.sawyer@sandburst.com
-D: Support for IBM PPC440GX, XES XPedite1000 440GX PrPMC board.
+D: Support for IBM PPC440GX, XES XPedite1000 440GX PrPMC board.  IBM 440gx Ref Platform (Ocotea)
 
 N: Paolo Scaffardi
 E: arsenio@tin.it
@@ -288,6 +328,10 @@ N: Robert Schwebel
 E: r.schwebel@pengutronix.de
 D: Support for csb226, logodl and innokom boards (PXA2xx)
 
+N: Kurt Stremerch
+E: kurt@exys.be
+D: Support for Exys XSEngine board
+
 N: Rob Taylor
 E: robt@flyingpig.com
 D: Port to MBX860T and Sandpoint8240
@@ -308,13 +352,22 @@ N: David Updegraff
 E: dave@cray.com
 D: Port to Cray L1 board; DHCP vendor extensions
 
+N: Christian Vejlbo
+E: christian.vejlbo@tellabs.com
+D: FADS860T ethernet support
+
 N: Martin Winistoerfer
 E: martinwinistoerfer@gmx.ch
 D: Port to MPC555/556 microcontrollers and support for cmi board
 
-N: Christian Vejlbo
-E: christian.vejlbo@tellabs.com
-D: FADS860T ethernet support
+N: Ming-Len Wu
+E: minglen_wu@techware.com.tw
+D: Motorola MX1ADS board support
+W: http://www.techware.com.tw/
+
+N: Xianghua Xiao
+E: x.xiao@motorola.com
+D: Support for Motorola 85xx(PowerQUICC III) chip, MPC8540ADS and MPC8560ADS boards.
 
 N: John Zhan
 E: zhanz@sinovee.com
@@ -324,7 +377,3 @@ N: Alex Zuepke
 E: azu@sysgo.de
 D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
 W: www.elinos.com
-
-N: Xianghua Xiao
-E: x.xiao@motorola.com
-D: Support for Motorola 85xx(PowerQUICC III) chip, MPC8540ADS and MPC8560ADS boards.

MAINTAINERS

@@ -27,6 +27,9 @@ Pantelis Antoniou <panto@intracom.gr>
 
 Yuli Barcohen <yuli@arabellasw.com>
 
+	Adder			MPC87x/MPC852T
+	ISPAN			MPC8260
+	MPC8260ADS		MPC826x/MPC827x/MPC8280
 	ZPC1900			MPC8265
 
 Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
@@ -49,6 +52,10 @@ K
 
 	FLAGADM			MPC823
 
+Torsten Demke <torsten.demke@fci.com>
+
+	eXalion			MPC824x
+
 Wolfgang Denk <wd@denx.de>
 
 	AMX860			MPC860
@@ -93,7 +100,6 @@ Wolfgang Denk <wd@denx.de>
 	TQM8255			MPC8255
 
 	CPU86			MPC8260
-	PM825			MPC8250
 	PM826			MPC8260
 	TQM8260			MPC8260
 
@@ -142,6 +148,7 @@ Bill Hargen <Bill_Hargen@Jabil.com>
 Klaus Heydeck <heydeck@kieback-peter.de>
 
 	KUP4K			MPC855
+	KUP4X			MPC859
 
 Murray Jensen <Murray.Jensen@cmst.csiro.au>
 
@@ -187,6 +194,10 @@ Scott McNutt <smcnutt@artesyncp.com>
 
 	EBONY			PPC440GP
 
+Tolunay Orkun <torkun@nextio.com>
+	csb272			PPC405GP
+	csb472			PPC405GP
+
 Keith Outwater <Keith_Outwater@mvis.com>
 
 	GEN860T			MPC860T
@@ -223,6 +234,11 @@ Stefan Roese <stefan.roese@esd-electronics.com>
 	PMC405			PPC405GP
 	VOH405			PPC405EP
 
+Travis Sawyer (travis.sawyer@sandburst.com>
+
+	XPEDITE1K		PPC440GX
+	OCOTEA			PPC440GX
+
 Peter De Schrijver <p2@mind.be>
 
 	ML2			PPC4xx
@@ -241,6 +257,15 @@ Rune Torgersen <runet@innovsys.com>
 
 	MPC8266ADS		MPC8266
 
+Josef Wagner <Wagner@Microsys.de>
+
+	CPC45			MPC8245
+	PM520			MPC5200
+
+Stephen Williams <steve@icarus.com>
+
+	JSE			PPC405GPr
+
 John Zhan <zhanz@sinovee.com>
 
 	svm_sc8xx		MPC8xx
@@ -250,6 +275,10 @@ Xianghua Xiao <x.xiao@motorola.com>
 	MPC8540ADS		MPC8540
 	MPC8560ADS		MPC8560
 
+Dan Malek <dan@embeddededge.com>
+
+	STxGP3			MPC85xx
+
 -------------------------------------------------------------------------
 
 Unknown / orphaned boards:
@@ -272,7 +301,6 @@ Unknown / orphaned boards:
 
 	MOUSSE			MPC824x
 
-	MPC8260ADS		MPC8260
 	RPXsuper		MPC8260
 	rsdproto		MPC8260
 
@@ -286,6 +314,15 @@ Unknown / orphaned boards:
 #	Board			CPU					#
 #########################################################################
 
+George G. Davis <gdavis@mvista.com>
+
+	assabet			SA1100
+	gcplus			SA1100
+
+Thomas Elste <info@elste.org>
+
+	modnet50		ARM720T (NET+50)
+
 Peter Figuli <peposh@etc.sk>
 
 	wepep250		xscale
@@ -307,9 +344,21 @@ Gary Jennejohn <gj@denx.de>
 	trab			ARM920T
 
 Kshitij Gupta <kshitij@ti.com>
+
 	omap1510inn		ARM925T
 	omap1610inn		ARM926EJS
 
+Dave Peverley <dpeverley@mpc-data.co.uk>
+	omap730p2		ARM926EJS
+
+Nishant Kamat <nskamat@ti.com>
+
+	omap1610h2		ARM926EJS
+
+Rishi Bhattacharya <rishi@ti.com>
+
+	omap5912osk		ARM926EJS
+
 David Müller <d.mueller@elsoft.ch>
 
 	smdk2410		ARM920T
@@ -365,6 +414,7 @@ Thomas Lange <thomas@corelatus.se>
 Stephan Linz <linz@li-pro.net>
 
 	DK1S10			Nios-32
+	ADNPESC1		Nios-32
 
 Scott McNutt <smcnutt@psyent.com>
 

MAKEALL

@@ -25,7 +25,7 @@ LIST_5xx="	\
 #########################################################################
 
 LIST_5xxx="	\
-	IceCube_5100	IceCube_5200	EVAL5200	\
+	icecube_5100	icecube_5200	EVAL5200	PM520		\
 "
 
 #########################################################################
@@ -33,22 +33,23 @@ LIST_5xxx="	\
 #########################################################################
 
 LIST_8xx="	\
-	AdderII		ADS860		AMX860		c2mon		\
-	CCM		cogent_mpc8xx	DUET_ADS	ESTEEM192E	\
-	ETX094		ELPT860		FADS823		FADS850SAR	\
-	FADS860T	FLAGADM		FPS850L		GEN860T		\
-	GEN860T_SC	GENIETV		GTH		hermes		\
-	IAD210		ICU862_100MHz	IP860		IVML24		\
-	IVML24_128	IVML24_256	IVMS8		IVMS8_128	\
-	IVMS8_256	KUP4K           LANTEC	        lwmon   	\
-	MBX		MBX860T		MHPC		MPC86xADS	\
-	MVS1		NETVIA		NETVIA_V2	NX823		\
-	pcu_e		QS823		QS850		QS860T		\
-	R360MPI		RBC823		rmu		RPXClassic	\
-	RPXlite		RRvision	SM850		SPD823TS	\
-	svm_sc8xx	SXNI855T	TOP860		TQM823L		\
-	TQM823L_LCD	TQM850L		TQM855L		TQM860L		\
-	v37								\
+	Adder		GENIETV		MBX860T		RBC823		\
+	AdderII		GTH		MHPC		rmu		\
+	ADS860		hermes		MPC86xADS	RPXClassic	\
+	AMX860		IAD210		MPC885ADS	RPXlite		\
+	c2mon		ICU862_100MHz	MVS1		RPXlite_DW	\
+	CCM		IP860		NETPHONE	RRvision	\
+	cogent_mpc8xx	IVML24		NETTA		SM850		\
+	ELPT860		IVML24_128	NETTA2		SPD823TS	\
+	ESTEEM192E	IVML24_256	NETTA_ISDN	svm_sc8xx	\
+	ETX094		IVMS8		NETVIA		SXNI855T	\
+	FADS823		IVMS8_128	NETVIA_V2	TOP860		\
+	FADS850SAR	IVMS8_256	NX823		TQM823L		\
+	FADS860T	KUP4K		pcu_e		TQM823L_LCD	\
+	FLAGADM		KUP4X		QS823		TQM850L		\
+	FPS850L		LANTEC		QS850		TQM855L		\
+	GEN860T		lwmon		QS860T		TQM860L		\
+	GEN860T_SC	MBX		R360MPI		v37		\
 "
 
 #########################################################################
@@ -56,15 +57,16 @@ LIST_8xx="	\
 #########################################################################
 
 LIST_4xx="	\
-	ADCIOP		AR405		ASH405          BUBINGA405EP    \
-	CANBT		CPCI405		CPCI4052 	CPCI405AB       \
-	CPCI440         CPCIISER4	CRAYL1  	DASA_SIM	\
-	DP405           DU405    	EBONY           ERIC  		\
-	EXBITGEN	HUB405          MIP405  	MIP405T		\
-	ML2		OCRTC		ORSG		PCI405		\
-	PIP405		PLU405          PMC405          PPChameleonEVB	\
-	VOH405          W7OLMC		W7OLMG          WALNUT405	\
-	XPEDITE1K							\
+	ADCIOP		AR405		ASH405		BUBINGA405EP	\
+	CANBT		CPCI405		CPCI4052	CPCI405AB	\
+	CPCI440		CPCIISER4	CRAYL1		csb272		\
+	csb472		DASA_SIM	DP405		DU405		\
+	EBONY		ERIC		EXBITGEN	HUB405		\
+	JSE		MIP405		MIP405T		ML2		\
+	ml300		OCOTEA		OCRTC		ORSG		\
+	PCI405		PIP405		PLU405		PMC405		\
+	PPChameleonEVB	VOH405		W7OLMC		W7OLMG		\
+	WALNUT405	XPEDITE1K					\
 "
 
 #########################################################################
@@ -72,10 +74,10 @@ LIST_4xx="	\
 #########################################################################
 
 LIST_824x="	\
-	A3000           BMW		CPC45		CU824		\
-	debris		MOUSSE          MUSENKI    	MVBLUE		\
-	OXC		PN62		Sandpoint8240   Sandpoint8245	\
-	SL8245		utx8245						\
+	A3000		BMW		CPC45		CU824		\
+	debris		eXalion		MOUSSE		MUSENKI		\
+	MVBLUE		OXC		PN62		Sandpoint8240	\
+	Sandpoint8245	SL8245		utx8245				\
 "
 
 #########################################################################
@@ -84,8 +86,9 @@ LIST_824x="	\
 
 LIST_8260="	\
 	atc		cogent_mpc8260	CPU86		ep8260		\
-	gw8260		hymod		IPHASE4539	MPC8260ADS	\
-	MPC8266ADS	PM826		ppmc8260	RPXsuper	\
+	gw8260		hymod		IPHASE4539	ISPAN		\
+	MPC8260ADS	MPC8266ADS	MPC8272ADS	PM826		\
+	PM828		ppmc8260	PQ2FADS		RPXsuper	\
 	rsdproto	sacsng		sbc8260		SCM		\
 	TQM8260_AC	TQM8260_AD	TQM8260_AE	ZPC1900		\
 "
@@ -95,7 +98,7 @@ LIST_8260="	\
 #########################################################################
 
 LIST_85xx="	\
-	MPC8540ADS	MPC8560ADS					\
+	MPC8540ADS	MPC8560ADS	stxgp3				\
 "
 
 #########################################################################
@@ -122,29 +125,31 @@ LIST_ppc="${LIST_5xx}  ${LIST_5xxx} \
 ## StrongARM Systems
 #########################################################################
 
-LIST_SA="dnp1110 lart shannon"
+LIST_SA="assabet dnp1110 gcplus lart shannon"
 
 #########################################################################
 ## ARM7 Systems
 #########################################################################
 
-LIST_ARM7="ep7312 impa7"
+LIST_ARM7="B2 ep7312 impa7"
 
 #########################################################################
 ## ARM9 Systems
 #########################################################################
 
 LIST_ARM9="	\
-	at91rm9200dk	omap1510inn	omap1610inn			\
+	at91rm9200dk	integratorcp	integratorap			\
+	lpd7a400	mx1ads		omap1510inn			\
+	omap1610h2	omap1610inn	omap730p2			\
 	smdk2400	smdk2410	trab				\
-	VCMA9								\
+	VCMA9		versatile					\
 "
 
 #########################################################################
 ## Xscale Systems
 #########################################################################
 
-LIST_pxa="cradle csb226 innokom lubbock wepep250"
+LIST_pxa="cradle csb226 innokom lubbock wepep250 xm250 xsengine"
 
 LIST_ixp="ixdp425"
 
@@ -176,6 +181,8 @@ LIST_x86="${LIST_I486}"
 #########################################################################
 
 LIST_nios="	\
+	ADNPESC1 ADNPESC1_base_32					\
+	ADNPESC1_DNPEVA2_base_32					\
 	DK1C20 DK1C20_standard_32					\
 	DK1S10 DK1S10_standard_32 DK1S10_mtx_ldk_20			\
 "

Makefile

@@ -75,6 +75,9 @@ endif
 ifeq ($(ARCH),m68k)
 CROSS_COMPILE = m68k-elf-
 endif
+ifeq ($(ARCH),microblaze)
+CROSS_COMPILE = mb-
+endif
 endif
 endif
 
@@ -99,7 +102,8 @@ LIBS  = lib_generic/libgeneric.a
 LIBS += board/$(BOARDDIR)/lib$(BOARD).a
 LIBS += cpu/$(CPU)/lib$(CPU).a
 LIBS += lib_$(ARCH)/lib$(ARCH).a
-LIBS += fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a fs/jffs2/libjffs2.a
+LIBS += fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a fs/jffs2/libjffs2.a \
+	fs/reiserfs/libreiserfs.a
 LIBS += net/libnet.a
 LIBS += disk/libdisk.a
 LIBS += rtc/librtc.a
@@ -111,7 +115,8 @@ LIBS += common/libcommon.a
 .PHONY : $(LIBS)
 
 # Add GCC lib
-PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
+PLATFORM_LIBS += --no-warn-mismatch -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
+
 
 # The "tools" are needed early, so put this first
 # Don't include stuff already done in $(LIBS)
@@ -164,6 +169,9 @@ depend dep:
 
 tags:
 		ctags -w `find $(SUBDIRS) include \
+				lib_generic board/$(BOARDDIR) cpu/$(CPU) lib_$(ARCH) \
+				fs/cramfs fs/fat fs/fdos fs/jffs2 \
+				net disk rtc dtt drivers drivers/sk98lin common \
 			\( -name CVS -prune \) -o \( -name '*.[ch]' -print \)`
 
 etags:
@@ -185,7 +193,7 @@ endif
 #########################################################################
 
 unconfig:
-	rm -f include/config.h include/config.mk
+	@rm -f include/config.h include/config.mk board/*/config.tmp
 
 #========================================================================
 # PowerPC
@@ -198,29 +206,34 @@ unconfig:
 cmi_mpc5xx_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc5xx cmi
 
-PATI_config:unconfig
+PATI_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc5xx pati mpl
 
 #########################################################################
 ## MPC5xxx Systems
 #########################################################################
-MPC5200LITE_config		\
-MPC5200LITE_LOWBOOT_config	\
-MPC5200LITE_LOWBOOT08_config	\
-icecube_5200_DDR_LOWBOOT_config	\
-icecube_5200_DDR_config		\
-IceCube_5200_DDR_config		\
-icecube_5200_config		\
-IceCube_5200_config		\
-IceCube_5100_config:		unconfig
+Lite5200_config				\
+Lite5200_LOWBOOT_config			\
+Lite5200_LOWBOOT08_config		\
+icecube_5200_config			\
+icecube_5200_LOWBOOT_config		\
+icecube_5200_LOWBOOT08_config		\
+icecube_5200_DDR_config 		\
+icecube_5200_DDR_LOWBOOT_config 	\
+icecube_5200_DDR_LOWBOOT08_config	\
+icecube_5100_config:			unconfig
 	@ >include/config.h
-	@[ -z "$(findstring LOWBOOT,$@)" ] || \
-		{ echo "TEXT_BASE = 0xFF000000" >board/icecube/config.tmp ; \
+	@[ -z "$(findstring LOWBOOT_,$@)" ] || \
+		{ if [ "$(findstring DDR,$@)" ] ; \
+			then echo "TEXT_BASE = 0xFF800000" >board/icecube/config.tmp ; \
+			else echo "TEXT_BASE = 0xFF000000" >board/icecube/config.tmp ; \
+		  fi ; \
 		  echo "... with LOWBOOT configuration" ; \
 		}
 	@[ -z "$(findstring LOWBOOT08,$@)" ] || \
 		{ echo "TEXT_BASE = 0xFF800000" >board/icecube/config.tmp ; \
 		  echo "... with 8 MB flash only" ; \
+		  echo "... with LOWBOOT configuration" ; \
 		}
 	@[ -z "$(findstring DDR,$@)" ] || \
 		{ echo "#define CONFIG_MPC5200_DDR"	>>include/config.h ; \
@@ -242,27 +255,47 @@ TOP5200_config:	unconfig
 	@ echo "#define CONFIG_$(@:_config=) 1"	>include/config.h
 	@./mkconfig -a TOP5200 ppc mpc5xxx top5200 emk
 
+PM520_config \
+PM520_DDR_config \
+PM520_ROMBOOT_config \
+PM520_ROMBOOT_DDR_config:	unconfig
+	@ >include/config.h
+	@[ -z "$(findstring DDR,$@)" ] || \
+		{ echo "#define CONFIG_MPC5200_DDR"	>>include/config.h ; \
+		  echo "... DDR memory revision" ; \
+		}
+	@[ -z "$(findstring ROMBOOT,$@)" ] || \
+		{ echo "#define CONFIG_BOOT_ROM" >>include/config.h ; \
+		  echo "... booting from 8-bit flash" ; \
+		}
+	@./mkconfig -a PM520 ppc mpc5xxx pm520
+
 #########################################################################
 ## MPC8xx Systems
 #########################################################################
 
+Adder_config    \
+Adder87x_config \
+Adder852_config \
+	:		unconfig
+	$(if $(findstring 852,$@), \
+	@echo "#define CONFIG_MPC852T" > include/config.h)
+	@./mkconfig -a Adder ppc mpc8xx adder
+
 AdderII_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx adderII
 
 ADS860_config     \
-DUET_ADS_config   \
 FADS823_config    \
 FADS850SAR_config \
 MPC86xADS_config  \
+MPC885ADS_config  \
 FADS860T_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx fads
 
 AMX860_config	:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx amx860 westel
 
-bms2003_config	:	unconfig
-	@./mkconfig $(@:_config=) ppc mpc8xx tqm8xx
-
 c2mon_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx c2mon
 
@@ -304,6 +337,9 @@ GTH_config:	unconfig
 hermes_config	:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx hermes
 
+HMI10_config	:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc8xx tqm8xx
+
 IAD210_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx IAD210 siemens
 
@@ -352,7 +388,10 @@ IVMS8_config:	unconfig
 	@./mkconfig -a IVMS8 ppc mpc8xx ivm
 
 KUP4K_config	:	unconfig
-	@./mkconfig $(@:_config=) ppc mpc8xx kup4k
+	@./mkconfig $(@:_config=) ppc mpc8xx kup4k kup
+
+KUP4X_config    :       unconfig
+	@./mkconfig $(@:_config=) ppc mpc8xx kup4x kup
 
 LANTEC_config	:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx lantec
@@ -385,6 +424,63 @@ NETVIA_config:		unconfig
 		 }
 	@./mkconfig -a $(call xtract_NETVIA,$@) ppc mpc8xx netvia
 
+xtract_NETPHONE = $(subst _V2,,$(subst _config,,$1))
+
+NETPHONE_V2_config \
+NETPHONE_config:	unconfig
+	@ >include/config.h
+	@[ -z "$(findstring NETPHONE_config,$@)" ] || \
+		 { echo "#define CONFIG_NETPHONE_VERSION 1" >>include/config.h ; \
+		 }
+	@[ -z "$(findstring NETPHONE_V2_config,$@)" ] || \
+		 { echo "#define CONFIG_NETPHONE_VERSION 2" >>include/config.h ; \
+		 }
+	@./mkconfig -a $(call xtract_NETPHONE,$@) ppc mpc8xx netphone
+
+xtract_NETTA = $(subst _SWAPHOOK,,$(subst _6412,,$(subst _ISDN,,$(subst _config,,$1))))
+
+NETTA_ISDN_6412_SWAPHOOK_config \
+NETTA_ISDN_SWAPHOOK_config \
+NETTA_6412_SWAPHOOK_config \
+NETTA_SWAPHOOK_config \
+NETTA_ISDN_6412_config \
+NETTA_ISDN_config \
+NETTA_6412_config \
+NETTA_config:		unconfig
+	@ >include/config.h
+	@[ -z "$(findstring ISDN_,$@)" ] || \
+		 { echo "#define CONFIG_NETTA_ISDN 1" >>include/config.h ; \
+		 }
+	@[ -n "$(findstring ISDN_,$@)" ] || \
+		 { echo "#undef CONFIG_NETTA_ISDN" >>include/config.h ; \
+		 }
+	@[ -z "$(findstring 6412_,$@)" ] || \
+		 { echo "#define CONFIG_NETTA_6412 1" >>include/config.h ; \
+		 }
+	@[ -n "$(findstring 6412_,$@)" ] || \
+		 { echo "#undef CONFIG_NETTA_6412" >>include/config.h ; \
+		 }
+	@[ -z "$(findstring SWAPHOOK_,$@)" ] || \
+		 { echo "#define CONFIG_NETTA_SWAPHOOK 1" >>include/config.h ; \
+		 }
+	@[ -n "$(findstring SWAPHOOK_,$@)" ] || \
+		 { echo "#undef CONFIG_NETTA_SWAPHOOK" >>include/config.h ; \
+		 }
+	@./mkconfig -a $(call xtract_NETTA,$@) ppc mpc8xx netta
+
+xtract_NETTA2 = $(subst _V2,,$(subst _config,,$1))
+
+NETTA2_V2_config \
+NETTA2_config:		unconfig
+	@ >include/config.h
+	@[ -z "$(findstring NETTA2_config,$@)" ] || \
+		 { echo "#define CONFIG_NETTA2_VERSION 1" >>include/config.h ; \
+		 }
+	@[ -z "$(findstring NETTA2_V2_config,$@)" ] || \
+		 { echo "#define CONFIG_NETTA2_VERSION 2" >>include/config.h ; \
+		 }
+	@./mkconfig -a $(call xtract_NETTA2,$@) ppc mpc8xx netta2
+
 NX823_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx nx823
 
@@ -412,6 +508,30 @@ RPXClassic_config:	unconfig
 RPXlite_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx RPXlite
 
+RPXlite_DW_64_config  		\
+RPXlite_DW_LCD_config 		\
+RPXlite_DW_64_LCD_config 	\
+RPXlite_DW_NVRAM_config		\
+RPXlite_DW_NVRAM_64_config      \
+RPXlite_DW_NVRAM_LCD_config	\
+RPXlite_DW_NVRAM_64_LCD_config  \
+RPXlite_DW_config:         unconfig
+	@ >include/config.h
+	@[ -z "$(findstring _64,$@)" ] || \
+		{ echo "#define RPXlite_64MHz"		>>include/config.h ; \
+		  echo "... with 64MHz system clock ..."; \
+		}
+	@[ -z "$(findstring _LCD,$@)" ] || \
+		{ echo "#define CONFIG_LCD"          	>>include/config.h ; \
+		  echo "#define CONFIG_NEC_NL6448BC20"	>>include/config.h ; \
+		  echo "... with LCD display ..."; \
+		}
+	@[ -z "$(findstring _NVRAM,$@)" ] || \
+		{ echo "#define  CFG_ENV_IS_IN_NVRAM" 	>>include/config.h ; \
+		  echo "... with ENV in NVRAM ..."; \
+		}
+	@./mkconfig -a RPXlite_DW ppc mpc8xx RPXlite_dw
+
 rmu_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx rmu
 
@@ -441,66 +561,26 @@ TOP860_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx top860 emk
 
 # Play some tricks for configuration selection
-# All boards can come with 50 MHz (default), 66MHz, 80MHz or 100 MHz clock,
-# but only 855 and 860 boards may come with FEC
-# and 823 boards may have LCD support
-xtract_8xx = $(subst _66MHz,,$(subst _80MHz,,$(subst _100MHz,,$(subst _133MHz,,$(subst _LCD,,$(subst _config,,$1))))))
+# Only 855 and 860 boards may come with FEC
+# and only 823 boards may have LCD support
+xtract_8xx = $(subst _LCD,,$(subst _config,,$1))
 
 FPS850L_config		\
 FPS860L_config		\
 NSCU_config		\
 TQM823L_config		\
-TQM823L_66MHz_config	\
-TQM823L_80MHz_config	\
 TQM823L_LCD_config	\
-TQM823L_LCD_66MHz_config \
-TQM823L_LCD_80MHz_config \
 TQM850L_config		\
-TQM850L_66MHz_config	\
-TQM850L_80MHz_config	\
 TQM855L_config		\
-TQM855L_66MHz_config	\
-TQM855L_80MHz_config	\
 TQM860L_config		\
-TQM860L_66MHz_config	\
-TQM860L_80MHz_config	\
 TQM862L_config		\
-TQM862L_66MHz_config	\
-TQM862L_80MHz_config	\
 TQM823M_config		\
-TQM823M_66MHz_config	\
-TQM823M_80MHz_config	\
 TQM850M_config		\
-TQM850M_66MHz_config	\
-TQM850M_80MHz_config	\
 TQM855M_config		\
-TQM855M_66MHz_config	\
-TQM855M_80MHz_config	\
 TQM860M_config		\
-TQM860M_66MHz_config	\
-TQM860M_80MHz_config	\
 TQM862M_config		\
-TQM862M_66MHz_config	\
-TQM862M_80MHz_config	\
-TQM862M_100MHz_config	\
 TQM866M_config:		unconfig
 	@ >include/config.h
-	@[ -z "$(findstring _66MHz,$@)" ] || \
-		{ echo "#define CONFIG_66MHz"		>>include/config.h ; \
-		  echo "... with 66MHz system clock" ; \
-		}
-	@[ -z "$(findstring _80MHz,$@)" ] || \
-		{ echo "#define CONFIG_80MHz"		>>include/config.h ; \
-		  echo "... with 80MHz system clock" ; \
-		}
-	@[ -z "$(findstring _100MHz,$@)" ] || \
-		{ echo "#define CONFIG_100MHz"		>>include/config.h ; \
-		  echo "... with 100MHz system clock" ; \
-		}
-	@[ -z "$(findstring _133MHz,$@)" ] || \
-		{ echo "#define CONFIG_133MHz"		>>include/config.h ; \
-		  echo "... with 133MHz system clock" ; \
-		}
 	@[ -z "$(findstring _LCD,$@)" ] || \
 		{ echo "#define CONFIG_LCD"		>>include/config.h ; \
 		  echo "#define CONFIG_NEC_NL6448BC20"	>>include/config.h ; \
@@ -537,12 +617,17 @@ AR405_config:	unconfig
 ASH405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx ash405 esd
 
-BUBINGA405EP_config:unconfig
+BUBINGA405EP_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx bubinga405ep
 
 CANBT_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx canbt esd
 
+CATcenter_config:	unconfig
+	@ echo "/* CATcenter uses PPChameleon Model ME */"  > include/config.h
+	@ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 1" >> include/config.h
+	@./mkconfig -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave
+
 CPCI405_config	\
 CPCI4052_config	\
 CPCI405AB_config:	unconfig
@@ -555,9 +640,15 @@ CPCI440_config:	unconfig
 CPCIISER4_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx cpciiser4 esd
 
-CRAYL1_config:unconfig
+CRAYL1_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx L1 cray
 
+csb272_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx csb272
+
+csb472_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx csb472
+
 DASA_SIM_config: unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx dasa_sim esd
 
@@ -567,29 +658,38 @@ DP405_config:	unconfig
 DU405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx du405 esd
 
-EBONY_config:unconfig
+EBONY_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx ebony
 
-ERIC_config:unconfig
+ERIC_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx eric
 
-EXBITGEN_config:unconfig
+EXBITGEN_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx exbitgen
 
 HUB405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx hub405 esd
 
-MIP405_config:unconfig
+JSE_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx jse
+
+MIP405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx mip405 mpl
 
-MIP405T_config:unconfig
+MIP405T_config:	unconfig
 	@echo "#define CONFIG_MIP405T" >include/config.h
 	@echo "Enable subset config for MIP405T"
 	@./mkconfig -a MIP405 ppc ppc4xx mip405 mpl
 
-ML2_config:unconfig
+ML2_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx ml2
 
+ml300_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx ml300 xilinx
+
+OCOTEA_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx ocotea
+
 OCRTC_config		\
 ORSG_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx ocrtc esd
@@ -597,7 +697,7 @@ ORSG_config:	unconfig
 PCI405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx pci405 esd
 
-PIP405_config:unconfig
+PIP405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx pip405 mpl
 
 PLU405_config:	unconfig
@@ -632,16 +732,16 @@ W7OLMC_config	\
 W7OLMG_config: unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx w7o
 
-WALNUT405_config:unconfig
+WALNUT405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx walnut405
 
-XPEDITE1K_config:unconfig
+XPEDITE1K_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx xpedite1k
 
 #########################################################################
 ## MPC824x Systems
 #########################################################################
-xtract_82xx = $(subst _ROMBOOT,,$(subst _L2,,$(subst _266MHz,,$(subst _300MHz,,$(subst _config,,$1)))))
+xtract_82xx = $(subst _BIGFLASH,,$(subst _ROMBOOT,,$(subst _L2,,$(subst _266MHz,,$(subst _300MHz,,$(subst _config,,$1))))))
 
 A3000_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x a3000
@@ -665,6 +765,12 @@ CPC45_ROMBOOT_config:	unconfig
 CU824_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x cu824
 
+debris_config: unconfig
+	@./mkconfig $(@:_config=) ppc mpc824x debris etin
+
+eXalion_config: unconfig
+	@./mkconfig $(@:_config=) ppc mpc824x eXalion
+
 MOUSSE_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x mousse
 
@@ -727,38 +833,84 @@ hymod_config:	unconfig
 IPHASE4539_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 iphase4539
 
-MPC8260ADS_config:	unconfig
-	@./mkconfig $(@:_config=) ppc mpc8260 mpc8260ads
+ISPAN_config		\
+ISPAN_REVB_config:	unconfig
+	@if [ "$(findstring _REVB_,$@)" ] ; then \
+		echo "#define CFG_REV_B" > include/config.h ; \
+	fi
+	@./mkconfig -a ISPAN ppc mpc8260 ispan
+
+MPC8260ADS_config	\
+MPC8260ADS_33MHz_config	\
+MPC8260ADS_40MHz_config	\
+MPC8272ADS_config	\
+PQ2FADS_config		\
+PQ2FADS-VR_config	\
+PQ2FADS-ZU_config	\
+PQ2FADS-ZU_66MHz_config	\
+	:		unconfig
+	$(if $(findstring PQ2FADS,$@), \
+	@echo "#define CONFIG_ADSTYPE CFG_PQ2FADS" > include/config.h, \
+	@echo "#define CONFIG_ADSTYPE CFG_"$(subst MPC,,$(word 1,$(subst _, ,$@))) > include/config.h)
+	$(if $(findstring MHz,$@), \
+	@echo "#define CONFIG_8260_CLKIN" $(subst MHz,,$(word 2,$(subst _, ,$@)))"000000" >> include/config.h, \
+	$(if $(findstring VR,$@), \
+	@echo "#define CONFIG_8260_CLKIN 66000000" >> include/config.h))
+	@./mkconfig -a MPC8260ADS ppc mpc8260 mpc8260ads
 
 MPC8266ADS_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 mpc8266ads
 
+# PM825/PM826 default configuration:  small (= 8 MB) Flash / boot from 64-bit flash
 PM825_config	\
-PM825_ROMBOOT_config: unconfig
-	@echo "#define CONFIG_PCI"	>include/config.h
-	@./mkconfig -a PM826 ppc mpc8260 pm826
-	@cd ./include ;				\
-	if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
-		echo "CONFIG_BOOT_ROM = y" >> config.mk ; \
-		echo "... booting from 8-bit flash" ; \
-	else \
-		echo "CONFIG_BOOT_ROM = n" >> config.mk ; \
-		echo "... booting from 64-bit flash" ; \
-	fi; \
-	echo "export CONFIG_BOOT_ROM" >> config.mk; \
-
+PM825_ROMBOOT_config	\
+PM825_BIGFLASH_config	\
+PM825_ROMBOOT_BIGFLASH_config	\
 PM826_config	\
-PM826_ROMBOOT_config: unconfig
-	@./mkconfig $(call xtract_82xx,$@) ppc mpc8260 pm826
-	@cd ./include ;				\
-	if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
-		echo "CONFIG_BOOT_ROM = y" >> config.mk ; \
-		echo "... booting from 8-bit flash" ; \
+PM826_ROMBOOT_config	\
+PM826_BIGFLASH_config	\
+PM826_ROMBOOT_BIGFLASH_config:	unconfig
+	@if [ "$(findstring PM825_,$@)" ] ; then \
+		echo "#define CONFIG_PCI"	>include/config.h ; \
+	else \
+		>include/config.h ; \
+	fi
+	@if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
+		echo "... booting from 8-bit flash" ; \
+		echo "#define CONFIG_BOOT_ROM" >>include/config.h ; \
+		echo "TEXT_BASE = 0xFF800000" >board/pm826/config.tmp ; \
+		if [ "$(findstring _BIGFLASH_,$@)" ] ; then \
+			echo "... with 32 MB Flash" ; \
+			echo "#define CONFIG_FLASH_32MB" >>include/config.h ; \
+		fi; \
 	else \
-		echo "CONFIG_BOOT_ROM = n" >> config.mk ; \
 		echo "... booting from 64-bit flash" ; \
-	fi; \
-	echo "export CONFIG_BOOT_ROM" >> config.mk; \
+		if [ "$(findstring _BIGFLASH_,$@)" ] ; then \
+			echo "... with 32 MB Flash" ; \
+			echo "#define CONFIG_FLASH_32MB" >>include/config.h ; \
+			echo "TEXT_BASE = 0x40000000" >board/pm826/config.tmp ; \
+		else \
+			echo "TEXT_BASE = 0xFF000000" >board/pm826/config.tmp ; \
+		fi; \
+	fi
+	@./mkconfig -a PM826 ppc mpc8260 pm826
+
+PM828_config	\
+PM828_PCI_config	\
+PM828_ROMBOOT_config	\
+PM828_ROMBOOT_PCI_config:	unconfig
+	@if [ -z "$(findstring _PCI_,$@)" ] ; then \
+		echo "#define CONFIG_PCI"  >>include/config.h ; \
+		echo "... with PCI enabled" ; \
+	else \
+		>include/config.h ; \
+	fi
+	@if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
+		echo "... booting from 8-bit flash" ; \
+		echo "#define CONFIG_BOOT_ROM" >>include/config.h ; \
+		echo "TEXT_BASE = 0xFF800000" >board/pm826/config.tmp ; \
+	fi
+	@./mkconfig -a PM828 ppc mpc8260 pm828
 
 ppmc8260_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 ppmc8260
@@ -833,10 +985,10 @@ ZPC1900_config: unconfig
 #########################################################################
 
 M5272C3_config :		unconfig
-	@./mkconfig $(@:_config=) m68k coldfire m5272c3
+	@./mkconfig $(@:_config=) m68k mcf52x2 m5272c3
 
 M5282EVB_config :		unconfig
-	@./mkconfig $(@:_config=) m68k coldfire m5282evb
+	@./mkconfig $(@:_config=) m68k mcf52x2 m5282evb
 
 #########################################################################
 ## MPC85xx Systems
@@ -848,6 +1000,9 @@ MPC8540ADS_config:      unconfig
 MPC8560ADS_config:      unconfig
 	@./mkconfig $(@:_config=) ppc mpc85xx mpc8560ads
 
+stxgp3_config:      unconfig
+	@./mkconfig $(@:_config=) ppc mpc85xx stxgp3
+
 #########################################################################
 ## 74xx/7xx Systems
 #########################################################################
@@ -864,9 +1019,6 @@ DB64360_config:  unconfig
 DB64460_config:  unconfig
 	@./mkconfig DB64460 ppc 74xx_7xx db64460 Marvell
 
-debris_config: unconfig
-	@./mkconfig $(@:_config=) ppc mpc824x debris etin
-
 ELPPC_config: unconfig
 	@./mkconfig $(@:_config=) ppc 74xx_7xx elppc eltec
 
@@ -891,15 +1043,18 @@ ZUMA_config:	unconfig
 ## StrongARM Systems
 #########################################################################
 
-at91rm9200dk_config	:	unconfig
-	@./mkconfig $(@:_config=) arm at91rm9200 at91rm9200dk
-
-lart_config	:	unconfig
-	@./mkconfig $(@:_config=) arm sa1100 lart
+assabet_config	:	unconfig
+	@./mkconfig $(@:_config=) arm sa1100 assabet
 
 dnp1110_config	:	unconfig
 	@./mkconfig $(@:_config=) arm sa1100 dnp1110
 
+gcplus_config	:	unconfig
+	@./mkconfig $(@:_config=) arm sa1100 gcplus
+
+lart_config	:	unconfig
+	@./mkconfig $(@:_config=) arm sa1100 lart
+
 shannon_config	:	unconfig
 	@./mkconfig $(@:_config=) arm sa1100 shannon
 
@@ -909,11 +1064,57 @@ shannon_config	:	unconfig
 
 xtract_trab = $(subst _bigram,,$(subst _bigflash,,$(subst _old,,$(subst _config,,$1))))
 
+xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,,$(subst _cs_autoboot,,$(subst _config,,$1))))
+
+xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))
+
+integratorcp_config :	unconfig
+	@./mkconfig $(@:_config=) arm arm926ejs integratorcp
+
+integratorap_config :	unconfig
+	@./mkconfig $(@:_config=) arm arm926ejs integratorap
+
+lpd7a400_config \
+lpd7a404_config:	unconfig
+	@./mkconfig $(@:_config=) arm lh7a40x lpd7a40x
+
 omap1510inn_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm925t omap1510inn
 
-omap1610inn_config :	unconfig
-	@./mkconfig $(@:_config=) arm arm926ejs omap1610inn
+omap5912osk_config :	unconfig
+	@./mkconfig $(@:_config=) arm arm926ejs omap5912osk
+
+omap1610inn_config \
+omap1610inn_cs0boot_config \
+omap1610inn_cs3boot_config \
+omap1610inn_cs_autoboot_config \
+omap1610h2_config \
+omap1610h2_cs0boot_config \
+omap1610h2_cs3boot_config \
+omap1610h2_cs_autoboot_config:	unconfig
+	@if [ "$(findstring _cs0boot_, $@)" ] ; then \
+		echo "#define CONFIG_CS0_BOOT" >> ./include/config.h ; \
+		echo "... configured for CS0 boot"; \
+	elif [ "$(findstring _cs_autoboot_, $@)" ] ; then \
+		echo "#define CONFIG_CS_AUTOBOOT" >> ./include/config.h ; \
+		echo "... configured for CS_AUTO boot"; \
+	else \
+		echo "#define CONFIG_CS3_BOOT" >> ./include/config.h ; \
+		echo "... configured for CS3 boot"; \
+	fi;
+	@./mkconfig -a $(call xtract_omap1610xxx,$@) arm arm926ejs omap1610inn
+
+omap730p2_config \
+omap730p2_cs0boot_config \
+omap730p2_cs3boot_config :	unconfig
+	@if [ "$(findstring _cs0boot_, $@)" ] ; then \
+		echo "#define CONFIG_CS0_BOOT" >> ./include/config.h ; \
+		echo "... configured for CS0 boot"; \
+	else \
+		echo "#define CONFIG_CS3_BOOT" >> ./include/config.h ; \
+		echo "... configured for CS3 boot"; \
+	fi;
+	@./mkconfig -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2
 
 smdk2400_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm920t smdk2400
@@ -921,6 +1122,9 @@ smdk2400_config	:	unconfig
 smdk2410_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm920t smdk2410
 
+SX1_config :		unconfig
+	@./mkconfig $(@:_config=) arm arm925t sx1
+
 # TRAB default configuration:	8 MB Flash, 32 MB RAM
 trab_config \
 trab_bigram_config \
@@ -949,15 +1153,42 @@ trab_old_config:	unconfig
 VCMA9_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm920t vcma9 mpl
 
+versatile_config :	unconfig
+	@./mkconfig $(@:_config=) arm arm926ejs versatile
+
+#########################################################################
+## S3C44B0 Systems
+#########################################################################
+
+B2_config	:	unconfig
+	@./mkconfig $(@:_config=) arm s3c44b0 B2 dave
+
+#########################################################################
+## MC9328 (Dragonball) Systems
+#########################################################################
+
+mx1ads_config	:	unconfig
+	@./mkconfig $(@:_config=) arm mc9328 mx1ads
+
 #########################################################################
 ## ARM720T Systems
 #########################################################################
 
+ep7312_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm720t ep7312
+
 impa7_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm720t impa7
 
-ep7312_config	:	unconfig
-	@./mkconfig $(@:_config=) arm arm720t ep7312
+modnet50_config :	unconfig
+	@./mkconfig $(@:_config=) arm arm720t modnet50
+
+#########################################################################
+## AT91RM9200 Systems
+#########################################################################
+
+at91rm9200dk_config	:	unconfig
+	@./mkconfig $(@:_config=) arm at91rm9200 at91rm9200dk
 
 #########################################################################
 ## XScale Systems
@@ -984,6 +1215,12 @@ logodl_config	:	unconfig
 wepep250_config	:	unconfig
 	@./mkconfig $(@:_config=) arm pxa wepep250
 
+xm250_config	:	unconfig
+	@./mkconfig $(@:_config=) arm pxa xm250
+
+xsengine_config :	unconfig
+	@./mkconfig $(@:_config=) arm pxa xsengine
+
 #========================================================================
 # i386
 #========================================================================
@@ -1030,6 +1267,24 @@ incaip_config: unconfig
 tb0229_config: unconfig
 	@./mkconfig $(@:_config=) mips mips tb0229
 
+#########################################################################
+## MIPS32 AU1X00
+#########################################################################
+dbau1000_config		: 	unconfig
+	@ >include/config.h
+	@echo "#define CONFIG_DBAU1000 1" >>include/config.h
+	@./mkconfig -a dbau1x00 mips mips dbau1x00
+
+dbau1100_config		: 	unconfig
+	@ >include/config.h
+	@echo "#define CONFIG_DBAU1100 1" >>include/config.h
+	@./mkconfig -a dbau1x00 mips mips dbau1x00
+
+dbau1500_config		: 	unconfig
+	@ >include/config.h
+	@echo "#define CONFIG_DBAU1500 1" >>include/config.h
+	@./mkconfig -a dbau1x00 mips mips dbau1x00
+
 #########################################################################
 ## MIPS64 5Kc
 #########################################################################
@@ -1085,24 +1340,35 @@ DK1S10_config:	unconfig
 		}
 	@./mkconfig -a DK1S10 nios nios dk1s10 altera
 
+ADNPESC1_DNPEVA2_base_32_config	\
+ADNPESC1_base_32_config		\
+ADNPESC1_config: unconfig
+	@ >include/config.h
+	@[ -z "$(findstring _DNPEVA2,$@)" ] || \
+		{ echo "#define CONFIG_DNPEVA2 1" >>include/config.h ; \
+		  echo "... DNP/EVA2 configuration" ; \
+		}
+	@[ -z "$(findstring _base_32,$@)" ] || \
+		{ echo "#define CONFIG_NIOS_BASE_32 1" >>include/config.h ; \
+		  echo "... NIOS 'base_32' configuration" ; \
+		}
+	@[ -z "$(findstring ADNPESC1_config,$@)" ] || \
+		{ echo "#define CONFIG_NIOS_BASE_32 1" >>include/config.h ; \
+		  echo "... NIOS 'base_32' configuration (DEFAULT)" ; \
+		}
+	@./mkconfig -a ADNPESC1 nios nios adnpesc1 ssv
 
+
+#========================================================================
+# MicroBlaze
+#========================================================================
 #########################################################################
-## MIPS32 AU1X00
+## Microblaze
 #########################################################################
-dbau1000_config		: 	unconfig
+suzaku_config:	unconfig
 	@ >include/config.h
-	@echo "#define CONFIG_DBAU1000 1" >>include/config.h
-	@./mkconfig -a dbau1x00 mips mips dbau1x00
-
-dbau1100_config		: 	unconfig
-	@ >include/config.h
-	@echo "#define CONFIG_DBAU1100 1" >>include/config.h
-	@./mkconfig -a dbau1x00 mips mips dbau1x00
-
-dbau1500_config		: 	unconfig
-	@ >include/config.h
-	@echo "#define CONFIG_DBAU1500 1" >>include/config.h
-	@./mkconfig -a dbau1x00 mips mips dbau1x00
+	@echo "#define CONFIG_SUZAKU 1" >> include/config.h
+	@./mkconfig -a $(@:_config=) microblaze microblaze suzaku AtmarkTechno
 
 #########################################################################
 #########################################################################
@@ -1115,19 +1381,19 @@ clean:
 	rm -f examples/hello_world examples/timer \
 	      examples/eepro100_eeprom examples/sched \
 	      examples/mem_to_mem_idma2intr examples/82559_eeprom
-
 	rm -f tools/img2srec tools/mkimage tools/envcrc tools/gen_eth_addr
+	rm -f tools/mpc86x_clk
 	rm -f tools/easylogo/easylogo tools/bmp_logo
 	rm -f tools/gdb/astest tools/gdb/gdbcont tools/gdb/gdbsend
 	rm -f tools/env/fw_printenv tools/env/fw_setenv
 	rm -f board/cray/L1/bootscript.c board/cray/L1/bootscript.image
-	rm -f board/trab/trab_fkt board/*/config.tmp
+	rm -f board/trab/trab_fkt
 
 clobber:	clean
-	find . -type f \
-		\( -name .depend -o -name '*.srec' -o -name '*.bin' \) \
-		-print \
-		| xargs rm -f
+	find . -type f \( -name .depend \
+		-o -name '*.srec' -o -name '*.bin' -o -name u-boot.img \) \
+		-print0 \
+		| xargs -0 rm -f
 	rm -f $(OBJS) *.bak tags TAGS
 	rm -fr *.*~
 	rm -f u-boot u-boot.map $(ALL)

README

@@ -122,135 +122,45 @@ Directory Hierarchy:
 - board		Board dependent files
 - common	Misc architecture independent functions
 - cpu		CPU specific files
+  - 74xx_7xx	Files specific to Motorola MPC74xx and 7xx CPUs
+  - arm720t	Files specific to ARM 720 CPUs
+  - arm920t	Files specific to ARM 920 CPUs
+  - arm925t	Files specific to ARM 925 CPUs
+  - arm926ejs	Files specific to ARM 926 CPUs
+  - at91rm9200	Files specific to Atmel AT91RM9200 CPUs
+  - i386	Files specific to i386 CPUs
+  - ixp		Files specific to Intel XScale IXP CPUs
+  - mcf52x2	Files specific to Motorola ColdFire MCF52x2 CPUs
+  - mips	Files specific to MIPS CPUs
+  - mpc5xx	Files specific to Motorola MPC5xx  CPUs
+  - mpc5xxx	Files specific to Motorola MPC5xxx CPUs
+  - mpc8xx	Files specific to Motorola MPC8xx  CPUs
+  - mpc824x	Files specific to Motorola MPC824x CPUs
+  - mpc8260	Files specific to Motorola MPC8260 CPUs
+  - mpc85xx	Files specific to Motorola MPC85xx CPUs
+  - nios	Files specific to Altera NIOS CPUs
+  - ppc4xx	Files specific to IBM PowerPC 4xx CPUs
+  - pxa		Files specific to Intel XScale PXA CPUs
+  - s3c44b0	Files specific to Samsung S3C44B0 CPUs
+  - sa1100	Files specific to Intel StrongARM SA1100 CPUs
 - disk		Code for disk drive partition handling
 - doc		Documentation (don't expect too much)
 - drivers	Commonly used device drivers
 - dtt		Digital Thermometer and Thermostat drivers
 - examples	Example code for standalone applications, etc.
 - include	Header Files
-- disk		Harddisk interface code
+- lib_arm	Files generic to ARM	 architecture
+- lib_generic	Files generic to all	 architectures
+- lib_i386	Files generic to i386	 architecture
+- lib_m68k	Files generic to m68k	 architecture
+- lib_mips	Files generic to MIPS	 architecture
+- lib_nios	Files generic to NIOS	 architecture
+- lib_ppc	Files generic to PowerPC architecture
 - net		Networking code
-- ppc		Files generic to PowerPC architecture
 - post		Power On Self Test
-- post/arch		Symlink to architecture specific Power On Self Test
-- post/arch-ppc		PowerPC architecture specific Power On Self Test
-- post/cpu/mpc8260	MPC8260 CPU specific Power On Self Test
-- post/cpu/mpc8xx	MPC8xx CPU specific Power On Self Test
 - rtc		Real Time Clock drivers
 - tools		Tools to build S-Record or U-Boot images, etc.
 
-- cpu/74xx_7xx	Files specific to Motorola MPC74xx and 7xx CPUs
-- cpu/arm925t	Files specific to ARM	   925	   CPUs
-- cpu/arm926ejs Files specific to ARM	926	CPUs
-- cpu/mpc5xx	Files specific to Motorola MPC5xx  CPUs
-- cpu/mpc8xx	Files specific to Motorola MPC8xx  CPUs
-- cpu/mpc824x	Files specific to Motorola MPC824x CPUs
-- cpu/mpc8260	Files specific to Motorola MPC8260 CPU
-- cpu/mpc85xx	Files specific to Motorola MPC85xx CPUs
-- cpu/ppc4xx	Files specific to IBM	   4xx	   CPUs
-
-
-- board/LEOX/	Files specific to boards manufactured by The LEOX team
-- board/LEOX/elpt860	Files specific to ELPT860 boards
-- board/RPXClassic
-		Files specific to RPXClassic boards
-- board/RPXlite Files specific to RPXlite    boards
-- board/at91rm9200dk Files specific to AT91RM9200DK boards
-- board/c2mon	Files specific to c2mon	     boards
-- board/cmi	Files specific to cmi	     boards
-- board/cogent	Files specific to Cogent     boards
-		(need further configuration)
-		Files specific to CPCIISER4  boards
-- board/cpu86	Files specific to CPU86	     boards
-- board/cray/	Files specific to boards manufactured by Cray
-- board/cray/L1		Files specific to L1	     boards
-- board/cu824	Files specific to CU824	     boards
-- board/ebony	Files specific to IBM Ebony board
-- board/eric	Files specific to ERIC	     boards
-- board/esd/	Files specific to boards manufactured by ESD
-- board/esd/adciop	Files specific to ADCIOP     boards
-- board/esd/ar405	Files specific to AR405	     boards
-- board/esd/canbt	Files specific to CANBT	     boards
-- board/esd/cpci405	Files specific to CPCI405    boards
-- board/esd/cpciiser4	Files specific to CPCIISER4  boards
-- board/esd/common	Common files for ESD boards
-- board/esd/dasa_sim	Files specific to DASA_SIM   boards
-- board/esd/du405	Files specific to DU405	     boards
-- board/esd/ocrtc	Files specific to OCRTC	     boards
-- board/esd/pci405	Files specific to PCI405     boards
-- board/esteem192e
-		Files specific to ESTEEM192E boards
-- board/etx094	Files specific to ETX_094    boards
-- board/evb64260
-		Files specific to EVB64260   boards
-- board/fads	Files specific to FADS	     boards
-- board/flagadm Files specific to FLAGADM    boards
-- board/gen860t Files specific to GEN860T and GEN860T_SC    boards
-- board/genietv Files specific to GENIETV    boards
-- board/gth	Files specific to GTH	     boards
-- board/hermes	Files specific to HERMES     boards
-- board/hymod	Files specific to HYMOD	     boards
-- board/icu862	Files specific to ICU862     boards
-- board/ip860	Files specific to IP860	     boards
-- board/iphase4539
-		Files specific to Interphase4539 boards
-- board/ivm	Files specific to IVMS8/IVML24 boards
-- board/lantec	Files specific to LANTEC     boards
-- board/lwmon	Files specific to LWMON	     boards
-- board/Marvell Files specific to Marvell development boards
-- board/Marvell/db64360 Files specific to db64360 board
-- board/Marvell/db64460 Files specific to db64460 board
-- board/mbx8xx	Files specific to MBX	     boards
-- board/mpc8260ads
-		Files specific to MPC826xADS and PQ2FADS-ZU/VR boards
-- board/mpc8540ads
-		Files specific to MPC8540ADS boards
-- board/mpc8560ads
-		Files specific to MPC8560ADS boards
-- board/mpl/	Files specific to boards manufactured by MPL
-- board/mpl/common	Common files for MPL boards
-- board/mpl/pip405	Files specific to PIP405     boards
-- board/mpl/mip405	Files specific to MIP405     boards
-- board/mpl/vcma9	Files specific to VCMA9	     boards
-- board/musenki Files specific to MUSEKNI    boards
-- board/mvs1	Files specific to MVS1	     boards
-- board/nx823	Files specific to NX823	     boards
-- board/oxc	Files specific to OXC	     boards
-- board/omap1510inn
-		Files specific to OMAP 1510 Innovator boards
-- board/omap1610inn
-		Files specific to OMAP 1610 Innovator boards
-- board/pcippc2 Files specific to PCIPPC2/PCIPPC6 boards
-- board/pm826	Files specific to PM826	     boards
-- board/ppmc8260
-		Files specific to PPMC8260   boards
-- board/snmc/qs850	Files specific to QS850/823  boards
-- board/snmc/qs860t	Files specific to QS860T     boards
-- board/rpxsuper
-		Files specific to RPXsuper   boards
-- board/rsdproto
-		Files specific to RSDproto   boards
-- board/sandpoint
-		Files specific to Sandpoint  boards
-- board/sbc8260 Files specific to SBC8260    boards
-- board/sacsng	Files specific to SACSng     boards
-- board/siemens Files specific to boards manufactured by Siemens AG
-- board/siemens/CCM	Files specific to CCM	     boards
-- board/siemens/IAD210	Files specific to IAD210     boards
-- board/siemens/SCM	Files specific to SCM	     boards
-- board/siemens/pcu_e	Files specific to PCU_E	     boards
-- board/sixnet	Files specific to SIXNET     boards
-- board/spd8xx	Files specific to SPD8xxTS   boards
-- board/tqm8260 Files specific to TQM8260    boards
-- board/tqm8xx	Files specific to TQM8xxL    boards
-- board/w7o	Files specific to W7O	     boards
-- board/walnut405
-		Files specific to Walnut405  boards
-- board/westel/ Files specific to boards manufactured by Westel Wireless
-- board/westel/amx860	Files specific to AMX860     boards
-- board/utx8245 Files specific to UTX8245   boards
-- board/zpc1900 Files specific to Zephyr Engineering ZPC.1900 board
-
 Software Configuration:
 =======================
 
@@ -330,56 +240,68 @@ The following options need to be configured:
 		CONFIG_ARM7
 		CONFIG_PXA250
 
+		MicroBlaze based CPUs:
+		----------------------
+		CONFIG_MICROBLZE
+
 
 - Board Type:	Define exactly one of
 
 		PowerPC based boards:
 		---------------------
 
-		CONFIG_ADCIOP,	   CONFIG_ICU862      CONFIG_RPXsuper,
-		CONFIG_ADS860,	   CONFIG_IP860,      CONFIG_SM850,
-		CONFIG_AMX860,	   CONFIG_IPHASE4539, CONFIG_SPD823TS,
-		CONFIG_AR405,	   CONFIG_IVML24,     CONFIG_SXNI855T,
-		CONFIG_BAB7xx,	   CONFIG_IVML24_128, CONFIG_Sandpoint8240,
-		CONFIG_CANBT,	   CONFIG_IVML24_256, CONFIG_Sandpoint8245,
-		CONFIG_CCM,	   CONFIG_IVMS8,      CONFIG_TQM823L,
-		CONFIG_CPCI405,	   CONFIG_IVMS8_128,  CONFIG_TQM850L,
-		CONFIG_CPCI4052,   CONFIG_IVMS8_256,  CONFIG_TQM855L,
-		CONFIG_CPCIISER4,  CONFIG_LANTEC,     CONFIG_TQM860L,
-		CONFIG_CPU86,	   CONFIG_MBX,	      CONFIG_TQM8260,
-		CONFIG_CRAYL1,	   CONFIG_MBX860T,    CONFIG_TTTech,
-		CONFIG_CU824,	   CONFIG_MHPC,	      CONFIG_UTX8245,
-		CONFIG_DASA_SIM,   CONFIG_MIP405,     CONFIG_W7OLMC,
-		CONFIG_DU405,	   CONFIG_MOUSSE,     CONFIG_W7OLMG,
-		CONFIG_ELPPC,	   CONFIG_MPC8260ADS, CONFIG_WALNUT405,
-		CONFIG_ERIC,	   CONFIG_MUSENKI,    CONFIG_ZUMA,
-		CONFIG_ESTEEM192E, CONFIG_MVS1,	      CONFIG_c2mon,
-		CONFIG_ETX094,	   CONFIG_NX823,      CONFIG_cogent_mpc8260,
-		CONFIG_EVB64260,   CONFIG_OCRTC,      CONFIG_cogent_mpc8xx,
-		CONFIG_FADS823,	   CONFIG_ORSG,	      CONFIG_ep8260,
-		CONFIG_FADS850SAR, CONFIG_OXC,	      CONFIG_gw8260,
-		CONFIG_FADS860T,   CONFIG_PCI405,     CONFIG_hermes,
-		CONFIG_FLAGADM,	   CONFIG_PCIPPC2,    CONFIG_hymod,
-		CONFIG_FPS850L,	   CONFIG_PCIPPC6,    CONFIG_lwmon,
-		CONFIG_GEN860T,	   CONFIG_PIP405,     CONFIG_pcu_e,
-		CONFIG_GENIETV,	   CONFIG_PM826,      CONFIG_ppmc8260,
-		CONFIG_GTH,	   CONFIG_RPXClassic, CONFIG_rsdproto,
-		CONFIG_IAD210,	   CONFIG_RPXlite,    CONFIG_sbc8260,
-		CONFIG_EBONY,	   CONFIG_sacsng,     CONFIG_FPS860L,
-		CONFIG_V37,	   CONFIG_ELPT860,    CONFIG_CMI,
-		CONFIG_NETVIA,	   CONFIG_RBC823,     CONFIG_ZPC1900,
-		CONFIG_MPC8540ADS, CONFIG_MPC8560ADS, CONFIG_QS850,
-		CONFIG_QS823,	   CONFIG_QS860T,     CONFIG_DB64360,
-		CONFIG_DB64460,	   CONFIG_DUET_ADS
+		CONFIG_ADCIOP		CONFIG_GEN860T		CONFIG_PCI405
+		CONFIG_ADS860		CONFIG_GENIETV		CONFIG_PCIPPC2
+		CONFIG_AMX860		CONFIG_GTH		CONFIG_PCIPPC6
+		CONFIG_AR405		CONFIG_gw8260		CONFIG_pcu_e
+		CONFIG_BAB7xx		CONFIG_hermes		CONFIG_PIP405
+		CONFIG_c2mon		CONFIG_hymod		CONFIG_PM826
+		CONFIG_CANBT		CONFIG_IAD210		CONFIG_ppmc8260
+		CONFIG_CCM		CONFIG_ICU862		CONFIG_QS823
+		CONFIG_CMI		CONFIG_IP860		CONFIG_QS850
+		CONFIG_cogent_mpc8260	CONFIG_IPHASE4539	CONFIG_QS860T
+		CONFIG_cogent_mpc8xx	CONFIG_IVML24		CONFIG_RBC823
+		CONFIG_CPCI405		CONFIG_IVML24_128	CONFIG_RPXClassic
+		CONFIG_CPCI4052		CONFIG_IVML24_256	CONFIG_RPXlite
+		CONFIG_CPCIISER4	CONFIG_IVMS8		CONFIG_RPXsuper
+		CONFIG_CPU86		CONFIG_IVMS8_128	CONFIG_rsdproto
+		CONFIG_CRAYL1		CONFIG_IVMS8_256	CONFIG_sacsng
+		CONFIG_CSB272		CONFIG_JSE		CONFIG_Sandpoint8240
+		CONFIG_CU824		CONFIG_LANTEC		CONFIG_Sandpoint8245
+		CONFIG_DASA_SIM		CONFIG_lwmon		CONFIG_sbc8260
+		CONFIG_DB64360		CONFIG_MBX		CONFIG_SM850
+		CONFIG_DB64460		CONFIG_MBX860T		CONFIG_SPD823TS
+		CONFIG_DU405		CONFIG_MHPC		CONFIG_STXGP3
+		CONFIG_DUET_ADS		CONFIG_MIP405		CONFIG_SXNI855T
+		CONFIG_EBONY		CONFIG_MOUSSE		CONFIG_TQM823L
+		CONFIG_ELPPC		CONFIG_MPC8260ADS	CONFIG_TQM8260
+		CONFIG_ELPT860		CONFIG_MPC8540ADS	CONFIG_TQM850L
+		CONFIG_ep8260		CONFIG_MPC8560ADS	CONFIG_TQM855L
+		CONFIG_ERIC		CONFIG_MUSENKI		CONFIG_TQM860L
+		CONFIG_ESTEEM192E	CONFIG_MVS1		CONFIG_TTTech
+		CONFIG_ETX094		CONFIG_NETPHONE		CONFIG_UTX8245
+		CONFIG_EVB64260		CONFIG_NETTA		CONFIG_V37
+		CONFIG_FADS823		CONFIG_NETVIA		CONFIG_W7OLMC
+		CONFIG_FADS850SAR	CONFIG_NX823		CONFIG_W7OLMG
+		CONFIG_FADS860T		CONFIG_OCRTC		CONFIG_WALNUT405
+		CONFIG_FLAGADM		CONFIG_ORSG		CONFIG_ZPC1900
+		CONFIG_FPS850L		CONFIG_OXC		CONFIG_ZUMA
+		CONFIG_FPS860L
 
 		ARM based boards:
 		-----------------
 
-		CONFIG_HHP_CRADLE,  CONFIG_DNP1110,    CONFIG_EP7312,
-		CONFIG_IMPA7,	    CONFIG_LART,       CONFIG_LUBBOCK,
-		CONFIG_INNOVATOROMAP1510,	CONFIG_INNOVATOROMAP1610
-		CONFIG_SHANNON,	    CONFIG_SMDK2400,   CONFIG_SMDK2410,
-		CONFIG_TRAB,	    CONFIG_VCMA9,      CONFIG_AT91RM9200DK
+		CONFIG_AT91RM9200DK,		CONFIG_DNP1110,		CONFIG_EP7312,
+		CONFIG_H2_OMAP1610,		CONFIG_HHP_CRADLE,	CONFIG_IMPA7,
+		CONFIG_INNOVATOROMAP1510,   CONFIG_INNOVATOROMAP1610,	CONFIG_LART,
+		CONFIG_LPD7A400			CONFIG_LUBBOCK,		CONFIG_OSK_OMAP5912,
+		CONFIG_SHANNON,			CONFIG_P2_OMAP730,	CONFIG_SMDK2400,
+		CONFIG_SMDK2410,		CONFIG_TRAB,		CONFIG_VCMA9
+
+		MicroBlaze based boards:
+		------------------------
+
+		CONFIG_SUZAKU
 
 
 - CPU Module Type: (if CONFIG_COGENT is defined)
@@ -409,7 +331,7 @@ The following options need to be configured:
 			CFG_8260ADS	- original MPC8260ADS
 			CFG_8266ADS	- MPC8266ADS
 			CFG_PQ2FADS	- PQ2FADS-ZU or PQ2FADS-VR
-
+			CFG_8272ADS	- MPC8272ADS
 
 - MPC824X Family Member (if CONFIG_MPC824X is defined)
 		Define exactly one of
@@ -530,8 +452,8 @@ The following options need to be configured:
 		(RTS/CTS) and UART's built-in FIFO. Set the number of
 		bytes the interrupt driven input buffer should have.
 
-		Set to 0 to disable this feature (this is the default).
-		This will also disable hardware handshake.
+		Leave undefined to disable this feature, including
+		disable the buffer and hardware handshake.
 
 - Console UART Number:
 		CONFIG_UART1_CONSOLE
@@ -644,6 +566,7 @@ The following options need to be configured:
 		CFG_CMD_IMLS	  List all found images
 		CFG_CMD_IMMAP	* IMMR dump support
 		CFG_CMD_IRQ	* irqinfo
+		CFG_CMD_ITEST	* Integer/string test of 2 values
 		CFG_CMD_JFFS2	* JFFS2 Support
 		CFG_CMD_KGDB	* kgdb
 		CFG_CMD_LOADB	  loadb
@@ -669,6 +592,7 @@ The following options need to be configured:
 		CFG_CMD_USB	* USB support
 		CFG_CMD_VFD	* VFD support (TRAB)
 		CFG_CMD_BSP	* Board SPecific functions
+		CFG_CMD_CDP	* Cisco Discover Protocol support
 		-----------------------------------------------
 		CFG_CMD_ALL	all
 
@@ -728,6 +652,7 @@ The following options need to be configured:
 		CONFIG_RTC_DS1337	- use Maxim, Inc. DS1337 RTC
 		CONFIG_RTC_DS1338	- use Maxim, Inc. DS1338 RTC
 		CONFIG_RTC_DS164x	- use Dallas DS164x RTC
+		CONFIG_RTC_MAX6900	- use Maxim, Inc. MAX6900 RTC
 
 		Note that if the RTC uses I2C, then the I2C interface
 		must also be configured. See I2C Support, below.
@@ -748,16 +673,31 @@ The following options need to be configured:
 		one partition type as well.
 
 - IDE Reset method:
-		CONFIG_IDE_RESET_ROUTINE
+		CONFIG_IDE_RESET_ROUTINE - this is defined in several
+		board configurations files but used nowhere!
 
-		Set this to define that instead of a reset Pin, the
-		routine ide_set_reset(int idereset) will be used.
+		CONFIG_IDE_RESET - is this is defined, IDE Reset will
+		be performed by calling the function
+			ide_set_reset(int reset)
+		which has to be defined in a board specific file
 
 - ATAPI Support:
 		CONFIG_ATAPI
 
 		Set this to enable ATAPI support.
 
+- LBA48 Support
+		CONFIG_LBA48
+
+		Set this to enable support for disks larger than 137GB
+		Also look at CFG_64BIT_LBA ,CFG_64BIT_VSPRINTF and CFG_64BIT_STRTOUL
+		Whithout these , LBA48 support uses 32bit variables and will 'only'
+		support disks up to 2.1TB.
+
+		CFG_64BIT_LBA:
+			When enabled, makes the IDE subsystem use 64bit sector addresses.
+			Default is 32bit.
+
 - SCSI Support:
 		At the moment only there is only support for the
 		SYM53C8XX SCSI controller; define
@@ -802,9 +742,23 @@ The following options need to be configured:
 			CONFIG_LAN91C96_USE_32_BIT
 			Define this to enable 32 bit addressing
 
+		CONFIG_DRIVER_SMC91111
+		Support for SMSC's LAN91C111 chip
+
+			CONFIG_SMC91111_BASE
+			Define this to hold the physical address
+			of the device (I/O space)
+
+			CONFIG_SMC_USE_32_BIT
+			Define this if data bus is 32 bits
+
+			CONFIG_SMC_USE_IOFUNCS
+			Define this to use i/o functions instead of macros
+			(some hardware wont work with macros)
+
 - USB Support:
 		At the moment only the UHCI host controller is
-		supported (PIP405, MIP405); define
+		supported (PIP405, MIP405, MPC5200); define
 		CONFIG_USB_UHCI to enable it.
 		define CONFIG_USB_KEYBOARD to enable the USB Keyboard
 		end define CONFIG_USB_STORAGE to enable the USB
@@ -812,6 +766,13 @@ The following options need to be configured:
 		Note:
 		Supported are USB Keyboards and USB Floppy drives
 		(TEAC FD-05PUB).
+		MPC5200 USB requires additional defines:
+			CONFIG_USB_CLOCK
+				for 528 MHz Clock: 0x0001bbbb
+			CONFIG_USB_CONFIG
+				for differential drivers: 0x00001000
+				for single ended drivers: 0x00005000
+
 
 - MMC Support:
 		The MMC controller on the Intel PXA is supported. To
@@ -844,17 +805,30 @@ The following options need to be configured:
 		Enable Chips & Technologies 69000 Video chip
 
 		CONFIG_VIDEO_SMI_LYNXEM
-		Enable Silicon Motion SMI 712/710/810 Video chip
-		Videomode are selected via environment 'videomode' with
-		standard LiLo mode numbers.
-		Following modes are supported  (* is default):
+		Enable Silicon Motion SMI 712/710/810 Video chip. The
+		video output is selected via environment 'videoout'
+		(1 = LCD and 2 = CRT). If videoout is undefined, CRT is
+		assumed.
 
-			    800x600  1024x768  1280x1024
-	      256  (8bit)     303*	305	  307
-	    65536 (16bit)     314	317	  31a
-	16,7 Mill (24bit)     315	318	  31b
+		For the CT69000 and SMI_LYNXEM drivers, videomode is
+		selected via environment 'videomode'. Two diferent ways
+		are possible:
+		- "videomode=num"   'num' is a standard LiLo mode numbers.
+		Following standard modes are supported	(* is default):
+
+		      Colors	640x480 800x600 1024x768 1152x864 1280x1024
+		-------------+---------------------------------------------
+		      8 bits |	0x301*	0x303	 0x305	  0x161	    0x307
+		     15 bits |	0x310	0x313	 0x316	  0x162	    0x319
+		     16 bits |	0x311	0x314	 0x317	  0x163	    0x31A
+		     24 bits |	0x312	0x315	 0x318	    ?	    0x31B
+		-------------+---------------------------------------------
 		(i.e. setenv videomode 317; saveenv; reset;)
 
+		- "videomode=bootargs" all the video parameters are parsed
+		from the bootargs. (See drivers/videomodes.c)
+
+
 		CONFIG_VIDEO_SED13806
 		Enable Epson SED13806 driver. This driver supports 8bpp
 		and 16bpp modes defined by CONFIG_VIDEO_SED13806_8BPP
@@ -921,7 +895,7 @@ The following options need to be configured:
 		If this option is set, the environment is checked for
 		a variable "splashimage". If found, the usual display
 		of logo, copyright and system information on the LCD
-		is supressed and the BMP image at the address
+		is suppressed and the BMP image at the address
 		specified in "splashimage" is loaded instead. The
 		console is redirected to the "nulldev", too. This
 		allows for a "silent" boot where a splash screen is
@@ -938,6 +912,32 @@ The following options need to be configured:
 		the malloc area (as defined by CFG_MALLOC_LEN) should
 		be at least 4MB.
 
+- MII/PHY support:
+		CONFIG_PHY_ADDR
+
+		The address of PHY on MII bus.
+
+		CONFIG_PHY_CLOCK_FREQ (ppc4xx)
+
+		The clock frequency of the MII bus
+
+		CONFIG_PHY_GIGE
+
+		If this option is set, support for speed/duplex
+		detection of Gigabit PHY is included.
+
+		CONFIG_PHY_RESET_DELAY
+
+		Some PHY like Intel LXT971A need extra delay after
+		reset before any MII register access is possible.
+		For such PHY, set this option to the usec delay
+		required. (minimum 300usec for LXT971A)
+
+		CONFIG_PHY_CMD_DELAY (ppc4xx)
+
+		Some PHY like Intel LXT971A need extra delay after
+		command issued before MII status register can be read
+
 - Ethernet address:
 		CONFIG_ETHADDR
 		CONFIG_ETH2ADDR
@@ -1002,6 +1002,48 @@ The following options need to be configured:
 		environment variable is passed as option 12 to
 		the DHCP server.
 
+ - CDP Options:
+		CONFIG_CDP_DEVICE_ID
+
+		The device id used in CDP trigger frames.
+
+		CONFIG_CDP_DEVICE_ID_PREFIX
+
+		A two character string which is prefixed to the MAC address
+		of the device.
+
+		CONFIG_CDP_PORT_ID
+
+		A printf format string which contains the ascii name of
+		the port. Normally is set to "eth%d" which sets
+		eth0 for the first ethernet, eth1 for the second etc.
+
+		CONFIG_CDP_CAPABILITIES
+
+		A 32bit integer which indicates the device capabilities;
+		0x00000010 for a normal host which does not forwards.
+
+		CONFIG_CDP_VERSION
+
+		An ascii string containing the version of the software.
+
+		CONFIG_CDP_PLATFORM
+
+		An ascii string containing the name of the platform.
+
+		CONFIG_CDP_TRIGGER
+
+		A 32bit integer sent on the trigger.
+
+		CONFIG_CDP_POWER_CONSUMPTION
+
+		A 16bit integer containing the power consumption of the
+		device in .1 of milliwatts.
+
+		CONFIG_CDP_APPLIANCE_VLAN_TYPE
+
+		A byte containing the id of the VLAN.
+
 - Status LED:	CONFIG_STATUS_LED
 
 		Several configurations allow to display the current
@@ -1130,6 +1172,12 @@ The following options need to be configured:
 		custom i2c_init_board() routine in boards/xxx/board.c
 		is run early in the boot sequence.
 
+		CONFIG_I2CFAST (PPC405GP|PPC405EP only)
+
+		This option enables configuration of bi_iic_fast[] flags
+		in u-boot bd_info structure based on u-boot environment
+		variable "i2cfast". (see also i2cfast)
+
 - SPI Support:	CONFIG_SPI
 
 		Enables SPI driver (so far only tested with
@@ -1151,60 +1199,6 @@ The following options need to be configured:
 		SPI configuration items (port pins to use, etc). For
 		an example, see include/configs/sacsng.h.
 
-- FPGA Support: CONFIG_FPGA_COUNT
-
-		Specify the number of FPGA devices to support.
-
-		CONFIG_FPGA
-
-		Used to specify the types of FPGA devices. For
-		example,
-		#define CONFIG_FPGA  CFG_XILINX_VIRTEX2
-
-		CFG_FPGA_PROG_FEEDBACK
-
-		Enable printing of hash marks during FPGA
-		configuration.
-
-		CFG_FPGA_CHECK_BUSY
-
-		Enable checks on FPGA configuration interface busy
-		status by the configuration function. This option
-		will require a board or device specific function to
-		be written.
-
-		CONFIG_FPGA_DELAY
-
-		If defined, a function that provides delays in the
-		FPGA configuration driver.
-
-		CFG_FPGA_CHECK_CTRLC
-
-		Allow Control-C to interrupt FPGA configuration
-
-		CFG_FPGA_CHECK_ERROR
-
-		Check for configuration errors during FPGA bitfile
-		loading. For example, abort during Virtex II
-		configuration if the INIT_B line goes low (which
-		indicated a CRC error).
-
-		CFG_FPGA_WAIT_INIT
-
-		Maximum time to wait for the INIT_B line to deassert
-		after PROB_B has been deasserted during a Virtex II
-		FPGA configuration sequence. The default time is 500 mS.
-
-		CFG_FPGA_WAIT_BUSY
-
-		Maximum time to wait for BUSY to deassert during
-		Virtex II FPGA configuration. The default is 5 mS.
-
-		CFG_FPGA_WAIT_CONFIG
-
-		Time to wait after FPGA configuration. The default is
-		200 mS.
-
 - FPGA Support: CONFIG_FPGA_COUNT
 
 		Specify the number of FPGA devices to support.
@@ -1338,6 +1332,10 @@ The following options need to be configured:
 		default value of 5 is used.
 
 - Command Interpreter:
+		CFG_AUTO_COMPLETE
+
+		Enable auto completion of commands using TAB.
+
 		CFG_HUSH_PARSER
 
 		Define this variable to enable the "hush" shell (from
@@ -1410,6 +1408,20 @@ The following options need to be configured:
 		allows to read/write in Dataflash via the standard
 		commands cp, md...
 
+- SystemACE Support:
+		CONFIG_SYSTEMACE
+
+		Adding this option adds support for Xilinx SystemACE
+		chips attached via some sort of local bus. The address
+		of the chip must alsh be defined in the
+		CFG_SYSTEMACE_BASE macro. For example:
+
+		#define CONFIG_SYSTEMACE
+		#define CFG_SYSTEMACE_BASE 0xf0000000
+
+		When SystemACE support is added, the "ace" device type
+		becomes available to the fat commands, i.e. fatls.
+
 - Show boot progress:
 		CONFIG_SHOW_BOOT_PROGRESS
 
@@ -1450,6 +1462,10 @@ The following options need to be configured:
    14	common/cmd_bootm.c	No initial ramdisk, no multifile, continue.
    15	common/cmd_bootm.c	All preparation done, transferring control to OS
 
+  -30	lib_ppc/board.c		Fatal error, hang the system
+  -31	post/post.c		POST test failed, detected by post_output_backlog()
+  -32	post/post.c		POST test failed, detected by post_run_single()
+
    -1	common/cmd_doc.c	Bad usage of "doc" command
    -1	common/cmd_doc.c	No boot device
    -1	common/cmd_doc.c	Unknown Chip ID on boot device
@@ -1784,6 +1800,17 @@ to save the current settings.
 	  The length in bytes of the EEPROM memory array address.  Note
 	  that this is NOT the chip address length!
 
+	- CFG_I2C_EEPROM_ADDR_OVERFLOW:
+	  EEPROM chips that implement "address overflow" are ones
+	  like Catalyst 24WC04/08/16 which has 9/10/11 bits of
+	  address and the extra bits end up in the "chip address" bit
+	  slots. This makes a 24WC08 (1Kbyte) chip look like four 256
+	  byte chips.
+
+	  Note that we consider the length of the address field to
+	  still be one byte because the extra address bits are hidden
+	  in the chip address.
+
 	- CFG_EEPROM_SIZE:
 	  The size in bytes of the EEPROM device.
 
@@ -1801,6 +1828,16 @@ to save the current settings.
 	  environment area within the total memory of your DataFlash placed
 	  at the specified address.
 
+- CFG_ENV_IS_IN_NAND:
+
+	Define this if you have a NAND device which you want to use
+	for the environment.
+
+	- CFG_ENV_OFFSET:
+	- CFG_ENV_SIZE:
+
+	  These two #defines specify the offset and size of the environment
+	  area within the first NAND device.
 
 - CFG_SPI_INIT_OFFSET
 
@@ -1837,6 +1874,13 @@ use the "saveenv" command to store a valid environment.
 - CFG_FAULT_MII_ADDR:
 		MII address of the PHY to check for the Ethernet link state.
 
+- CFG_64BIT_VSPRINTF:
+		Makes vsprintf (and all *printf functions) support printing
+		of 64bit values by using the L quantifier
+
+- CFG_64BIT_STRTOUL:
+		Adds simple_strtoull that returns a 64bit value
+
 Low Level (hardware related) configuration options:
 ---------------------------------------------------
 
@@ -1978,6 +2022,36 @@ Low Level (hardware related) configuration options:
   CFG_POCMR2_MASK_ATTRIB: (MPC826x only)
 		Overrides the default PCI memory map in cpu/mpc8260/pci.c if set.
 
+- CONFIG_ETHER_ON_FEC[12]
+		Define to enable FEC[12] on a 8xx series processor.
+
+- CONFIG_FEC[12]_PHY
+		Define to the hardcoded PHY address which corresponds
+		to the given FEC; i. e.
+			#define CONFIG_FEC1_PHY 4
+		means that the PHY with address 4 is connected to FEC1
+
+		When set to -1, means to probe for first available.
+
+- CONFIG_FEC[12]_PHY_NORXERR
+		The PHY does not have a RXERR line (RMII only).
+		(so program the FEC to ignore it).
+
+- CONFIG_RMII
+		Enable RMII mode for all FECs.
+		Note that this is a global option, we can't
+		have one FEC in standard MII mode and another in RMII mode.
+
+- CONFIG_CRC32_VERIFY
+		Add a verify option to the crc32 command.
+		The syntax is:
+
+		=> crc32 -v <address> <count> <crc32>
+
+		Where address/count indicate a memory area
+		and crc32 is the correct crc32 which the
+		area should have.
+
 Building the Software:
 ======================
 
@@ -2005,54 +2079,41 @@ is done by typing:
 where "NAME_config" is the name of one of the existing
 configurations; the following names are supported:
 
-    ADCIOP_config	  GTH_config		TQM850L_config
-    ADS860_config	  IP860_config		TQM855L_config
-    AR405_config	  IVML24_config		TQM860L_config
-    CANBT_config	  IVMS8_config		WALNUT405_config
-    CPCI405_config	  LANTEC_config		cogent_common_config
-    CPCIISER4_config	  MBX_config		cogent_mpc8260_config
-    CU824_config	  MBX860T_config	cogent_mpc8xx_config
-    ESTEEM192E_config	  RPXlite_config	hermes_config
-    ETX094_config	  RPXsuper_config	hymod_config
-    FADS823_config	  SM850_config		lwmon_config
-    FADS850SAR_config	  SPD823TS_config	pcu_e_config
-    FADS860T_config	  SXNI855T_config	rsdproto_config
-    FPS850L_config	  Sandpoint8240_config	sbc8260_config
-    GENIETV_config	  TQM823L_config	PIP405_config
-    GEN860T_config	  EBONY_config		FPS860L_config
-    ELPT860_config	  cmi_mpc5xx_config	NETVIA_config
-    at91rm9200dk_config	  omap1510inn_config	MPC8260ADS_config
-    omap1610inn_config	  ZPC1900_config	MPC8540ADS_config
-    MPC8560ADS_config	  QS850_config		QS823_config
-    QS860T_config	  DUET_ADS_config
+	ADCIOP_config		FPS860L_config		omap730p2_config
+	ADS860_config		GEN860T_config		pcu_e_config
+	AR405_config		GENIETV_config		PIP405_config
+	at91rm9200dk_config	GTH_config		QS823_config
+	CANBT_config		hermes_config		QS850_config
+	cmi_mpc5xx_config	hymod_config		QS860T_config
+	cogent_common_config	IP860_config		RPXlite_config
+	cogent_mpc8260_config	IVML24_config		RPXlite_DW_config
+	cogent_mpc8xx_config	IVMS8_config		RPXsuper_config
+	CPCI405_config		JSE_config		rsdproto_config
+	CPCIISER4_config	LANTEC_config		Sandpoint8240_config
+	csb272_config		lwmon_config		sbc8260_config
+	CU824_config		MBX860T_config		SM850_config
+	DUET_ADS_config		MBX_config		SPD823TS_config
+	EBONY_config		MPC8260ADS_config	stxgp3_config
+	ELPT860_config		MPC8540ADS_config	SXNI855T_config
+	ESTEEM192E_config	MPC8560ADS_config	TQM823L_config
+	ETX094_config		NETVIA_config		TQM850L_config
+	FADS823_config		omap1510inn_config	TQM855L_config
+	FADS850SAR_config	omap1610h2_config	TQM860L_config
+	FADS860T_config		omap1610inn_config	WALNUT405_config
+	FPS850L_config		omap5912osk_config	ZPC1900_config
 
-Note: for some board special configuration names may exist; check  if
-      additional  information is available from the board vendor; for
-      instance, the TQM8xxL systems run normally at 50 MHz and use  a
-      SCC  for	10baseT	 ethernet; there are also systems with 80 MHz
-      CPU clock, and an optional Fast Ethernet	module	is  available
-      for  CPU's  with FEC. You can select such additional "features"
+Note: for some board special configuration names may exist; check if
+      additional information is available from the board vendor; for
+      instance, the TQM823L systems are available without (standard)
+      or with LCD support. You can select such additional "features"
       when chosing the configuration, i. e.
 
-      make TQM860L_config
-	- will configure for a plain TQM860L, i. e. 50MHz, no FEC
-
-      make TQM860L_FEC_config
-	- will configure for a TQM860L at 50MHz with FEC for ethernet
-
-      make TQM860L_80MHz_config
-	- will configure for a TQM860L at 80 MHz, with normal 10baseT
-	  interface
-
-      make TQM860L_FEC_80MHz_config
-	- will configure for a TQM860L at 80 MHz with FEC for ethernet
+      make TQM823L_config
+	- will configure for a plain TQM823L, i. e. no LCD support
 
       make TQM823L_LCD_config
 	- will configure for a TQM823L with U-Boot console on LCD
 
-      make TQM823L_LCD_80MHz_config
-	- will configure for a TQM823L at 80 MHz with U-Boot console on LCD
-
       etc.
 
 
@@ -2220,6 +2281,12 @@ Some configuration options can be set using Environment Variables:
 		  This can be used to load and uncompress arbitrary
 		  data.
 
+  i2cfast	- (PPC405GP|PPC405EP only)
+		  if set to 'y' configures Linux I2C driver for fast
+		  mode (400kHZ). This environment variable is used in
+		  initialization code. So, for changes to be effective
+		  it must be saved and board must be reset.
+
   initrd_high	- restrict positioning of initrd images:
 		  If this variable is not set, initrd images will be
 		  copied to the highest possible address in RAM; this
@@ -2264,6 +2331,29 @@ Some configuration options can be set using Environment Variables:
 
   bootstopkey	- see CONFIG_AUTOBOOT_STOP_STR
 
+  ethprime	- When CONFIG_NET_MULTI is enabled controls which
+		  interface is used first.
+
+  ethact	- When CONFIG_NET_MULTI is enabled controls which
+		  interface is currently active. For example you
+		  can do the following
+
+		  => setenv ethact FEC ETHERNET
+		  => ping 192.168.0.1 # traffic sent on FEC ETHERNET
+		  => setenv ethact SCC ETHERNET
+		  => ping 10.0.0.1 # traffic sent on SCC ETHERNET
+
+   netretry	- When set to "no" each network operation will
+		  either succeed or fail without retrying.
+		  When set to "once" the network operation will
+		  fail when all the available network interfaces
+		  are tried once without success.
+		  Useful on scripts which control the retry operation
+		  themselves.
+
+   vlan		- When set to a value < 4095 the traffic over
+		  ethernet is encapsulated/received over 802.1q
+		  VLAN tagged frames.
 
 The following environment variables may be used and automatically
 updated by the network boot commands ("bootp" and "rarpboot"),
@@ -2530,8 +2620,9 @@ from a "data file" which is used as image payload:
 	  -n ==> set image name to 'name'
 	  -d ==> use image data from 'datafile'
 
-Right now, all Linux kernels use the same load address	(0x00000000),
-but the entry point address depends on the kernel version:
+Right now, all Linux kernels for PowerPC systems use the same load
+address (0x00000000), but the entry point address depends on the
+kernel version:
 
 - 2.2.x kernels have the entry point at 0x0000000C,
 - 2.3.x and later kernels have the entry point at 0x00000000.

board/AtmarkTechno/suzaku/Makefile

@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000-2002
+# (C) Copyright 2003
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this

board/AtmarkTechno/suzaku/config.mk

@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2004 Atmark Techno, Inc.
+#
+# Yasushi SHOJI <yashi@atmark-techno.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x80F00000
+
+PLATFORM_CPPFLAGS += -mno-xl-soft-mul
+PLATFORM_CPPFLAGS += -mno-xl-soft-div
+PLATFORM_CPPFLAGS += -mxl-barrel-shift

board/AtmarkTechno/suzaku/flash.c

@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2004 Atmark Techno, Inc.
+ *
+ * Yasushi SHOJI <yashi@atmark-techno.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+unsigned long flash_init(void)
+{
+	return 0;
+}
+
+void flash_print_info(flash_info_t *info)
+{
+}
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	return 0;
+}
+
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	return 0;
+}

board/AtmarkTechno/suzaku/suzaku.c

@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2004 Atmark Techno, Inc.
+ *
+ * Yasushi SHOJI <yashi@atmark-techno.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+void do_reset(void)
+{
+}

board/AtmarkTechno/suzaku/u-boot.lds

@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2004 Atmark Techno, Inc.
+ *
+ * Yasushi SHOJI <yashi@atmark-techno.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(microblaze)
+ENTRY(_start)
+
+SECTIONS
+{
+	.text ALIGN(0x4):
+	{
+		__text_start = .;
+		cpu/microblaze/start.o (.text)
+		*(.text)
+		__text_end = .;
+	}
+
+	.rodata ALIGN(0x4):
+	{
+		__rodata_start = .;
+		*(.rodata)
+		__rodata_end = .;
+	}
+
+	.data ALIGN(0x4):
+	{
+		__data_start = .;
+		*(.data)
+		__data_end = .;
+	}
+
+	.u_boot_cmd ALIGN(0x4):
+	{
+		__u_boot_cmd_start = .;
+		*(.u_boot_cmd)
+		__u_boot_cmd_end = .;
+	}
+
+	.bss ALIGN(0x4):
+	{
+		__bss_start = .;
+		*(.bss)
+		__bss_start = .;
+	}
+}

board/RPXlite_dw/Makefile

@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/RPXlite_dw/README

@@ -0,0 +1,96 @@
+
+After following the step of Yoo. Jonghoon and Wolfgang Denk,
+I ported u-boot on RPXlite DW version board: RPXlite_DW or LITE_DW.
+
+There are three differences between the Yoo-ported RPXlite and the RPXlite_DW.
+
+Board(in U-BOOT)	version(in EmbeddedPlanet)	CPU	SDRAM	FLASH
+RPXlite				RPXlite CW		850	16MB	4MB
+RPXlite_DW			RPXlite DW		823e	64MB	16MB
+
+This fireware is specially coded for EmbeddedPlanet Co. Software Development
+Platform(RPXlite DW),which has a NEC NL6448BC20-08 LCD panel.
+
+It has the following three features:
+
+1. 64MHz/48MHz system frequence setting options.
+The default setting is 48MHz.To get a 64MHz u-boot,just add
+'64' in make command,like
+
+make RPXlite_DW_64_config
+make all
+
+2. CFG_ENV_IS_IN_FLASH/CFG_ENV_IS_IN_NVRAM
+
+The default environment parameter is stored in FLASH because it is a common choice for
+environment parameter.So I make NVRAM as backup parameter storeage.The reason why I
+didn't use EEPROM for ENV is that PlanetCore V2.0 use EEPROM as environment parameter
+home.Because of the possibility of using two firewares on this board,I didn't
+'disturb' EEPROM.To get NVRAM support,you may use the following build command:
+
+make RPXlite_DW_NVRAM_config
+make all
+
+3. LCD panel support
+
+To support the Platform better,I added LCD panel(NL6448BC20-08) function.But bewear of
+the fact that once you build this support and program it to FLASH,you should make sure
+you put workable kernel and ramdisk at the right place in FLASH or through NFS.
+Otherwise, you must erase this fireware manually via BDI2000 or ICE tools.So this
+function is used for deployment and demo only.Pls look before you leap.
+
+To get a LCD support u-boot,you can do the following:
+
+make RPXlite_DW_LCD_config
+make all
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+The basic make commands could be:
+
+make RPXlite_DW_config
+make RPXlite_DW_64_config
+make RPXlite_DW_LCD_config
+make RPXlite_DW_NVRAM_config
+
+BTW,you can combine the above features together and get a workable u-boot to meet your need.
+For example,to get a 64MHZ && ENV_IS_IN_FLASH && LCD panel support u-boot,you can type:
+
+make RPXlite_DW_NVRAM_64_LCD_config
+make all
+
+So other combining make commands could be:
+
+make RPXlite_DW_NVRAM_64_config
+make RPXlite_DW_NVRAM_LCD_config
+make RPXlite_DW_64_LCD_config
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The boot process by "make RPXlite_DW_config" could be:
+
+U-Boot 1.1.1 (Jun  8 2004 - 11:16:30)
+
+CPU:   PPC823EZTnnB2 at 48 MHz: 16 kB I-Cache 8 kB D-Cache
+Board: RPXlite_DW
+DRAM:  64 MB
+FLASH: 16 MB
+*** Warning - bad CRC, using default environment
+
+In:    serial
+Out:   serial
+Err:   serial
+Net:   SCC ETHERNET
+u-boot>
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+I'd like to extend my heartfelt gratitute to kind people for helping me work it out.
+I would particually thank Wolfgang Denk for his nice help.
+
+Enjoy,
+
+Sam Song, samsongshu@yahoo.com.cn
+Institute of Electrical Machinery and Controls
+Shanghai University
+
+June 8,2004

board/RPXlite_dw/RPXlite_dw.c

@@ -0,0 +1,180 @@
+/*
+ * (C) Copyright 2004
+ * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Sam Song
+ * U-Boot port on RPXlite DW board : RPXlite_DW or LITE_DW
+ * Tested on working at 64MHz(CPU)/32MHz(BUS),48MHz/24MHz
+ * with 64MB, 2 SDRAM Micron chips,MT48LC16M16A2-75.
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+static long int dram_size (long int, long int *, long int);
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFCC25
+
+const uint sdram_table[] =
+{
+	/*
+	 * Single Read. (Offset 00h in UPMA RAM)
+	 */
+	0x0F03CC04, 0x00ACCC24, 0x1FF74C20, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_,
+
+	/*
+	 * Burst Read. (Offset 08h in UPMA RAM)
+	 */
+	0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20,
+	0x01FFCC20, 0x1FF74C20, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Single Write. (Offset 18h in UPMA RAM)
+	 */
+	0x0F03CC02, 0x00AC0C24, 0x1FF74C25, /* last */
+	_NOT_USED_, _NOT_USED_, 0x0FA00C34,0x0FFFCC35,
+	_NOT_USED_,
+
+	/*
+	 * Burst Write. (Offset 20h in UPMA RAM)
+	 */
+	0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22,
+	0x01FFFC24, 0x1FF74C25, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Refresh. (Offset 30h in UPMA RAM)
+	 */
+	0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34,
+	0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34, 0x0FFFCCB4,
+	/* INIT sequence RAM WORDS
+	 * SDRAM Initialization (offset 0x36 in UPMA RAM)
+	 * The above definition uses the remaining space
+	 * to establish an initialization sequence,
+	 * which is executed by a RUN command.
+	 * The sequence is COMMAND INHIBIT(NOP),Precharge,
+	 * Load Mode Register,NOP,Auto Refresh.
+	 */
+
+	/*
+	 * Exception. (Offset 3Ch in UPMA RAM)
+	 */
+	0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_
+};
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	puts ("Board: RPXlite_DW\n") ;
+	return (0) ;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size9;
+
+	upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+	/* Refresh clock prescalar */
+	memctl->memc_mptpr = CFG_MPTPR ;
+
+	memctl->memc_mar  = 0x00000088;
+
+	/* Map controller banks 1 to the SDRAM bank */
+	memctl->memc_or1 = CFG_OR1_PRELIM;
+	memctl->memc_br1 = CFG_BR1_PRELIM;
+
+	memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
+	/*Disable Periodic timer A. */
+
+ 	udelay(200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr  = 0x80002236; /* SDRAM bank 0 - refresh twice */
+
+	udelay(1);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	/*Enable Periodic timer A */
+
+	udelay (1000);
+
+	 /* Check Bank 0 Memory Size
+	  * try 9 column mode
+	  */
+
+	size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
+
+	/*
+	 * Final mapping:
+	 */
+
+	memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+
+	udelay (1000);
+
+	return (size9);
+}
+
+void rpxlite_init (void)
+{
+	/* Enable NVRAM */
+	*((uchar *) BCSR0) |= BCSR0_ENNVRAM;
+}
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+static long int dram_size (long int mamr_value, long int *base,
+			   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size (base, maxsize));
+}

board/RPXlite_dw/config.mk

@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# RPXlite dw boards : lite_dw
+#
+
+TEXT_BASE = 0xff000000

board/RPXlite_dw/flash.c

@@ -0,0 +1,490 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Yoo. Jonghoon, IPone, yooth@ipone.co.kr
+ * U-Boot port on RPXlite board
+ *
+ * Some of flash control words are modified. (from 2x16bit device
+ * to 4x8bit device)
+ * RPXLite board I tested has only 4 AM29LV800BB devices. Other devices
+ * are not tested.
+ *
+ * (?) Does an RPXLite board which
+ * 	does not use AM29LV800 flash memory exist ?
+ *	I don't know...
+ */
+
+/* Yes,Yoo.They do use other FLASH for the board.
+ *
+ * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
+ * U-Boot port on RPXlite DW version board
+ *
+ * By now,it uses 4 AM29DL323DB90VI devices(4x8bit).
+ * The total FLASH has 16MB(4x4MB).
+ * I just made some necessary changes on the basis of Wolfgang and Yoo's job.
+ *
+ * June 8, 2004 */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions   vu_long : volatile unsigned long IN include/common.h
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0 ;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* If Monitor is in the cope of FLASH,then
+	 * protect this area by default in case for
+	 * other occupation. [SAM] */
+
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      &flash_info[0]);
+#endif
+	flash_info[0].size = size_b0;
+	return (size_b0);
+}
+
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x00010000;
+		info->start[3] = base + 0x00018000;
+		info->start[4] = base + 0x00020000;
+		info->start[5] = base + 0x00028000;
+		info->start[6] = base + 0x00030000;
+		info->start[7] = base + 0x00038000;
+
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + ((i-7) * 0x00040000);
+		}
+	} else {
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00010000;
+		info->start[i--] = base + info->size - 0x00018000;
+		info->start[i--] = base + info->size - 0x00020000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00040000;
+		}
+	}
+
+}
+
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AMDL323B:    printf ("AM29DL323B (32 Mbit, bottom boot sector)\n");
+				break;
+	/* I just add the FLASH_AMDL323B for RPXlite_DW BOARD. [SAM]  */
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+	printf ("  Size: %ld MB in %d Sectors\n",info->size >> 20, info->sector_count);
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",info->start[i],info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0xAAA] = 0x00AA00AA ;
+	addr[0x555] = 0x00550055 ;
+	addr[0xAAA] = 0x00900090 ;
+
+	value = addr[0] ;
+	switch (value & 0x00FF00FF) {
+	case AMD_MANUFACT:             		/* AMD_MANUFACT=0x00010001 in flash.h. */
+		info->flash_id = FLASH_MAN_AMD; /* FLASH_MAN_AMD=0x00000000 in flash.h.*/
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[2] ;			/* device ID		*/
+	switch (value & 0x00FF00FF) {
+	case (AMD_ID_LV400T & 0x00FF00FF):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+	case (AMD_ID_LV400B & 0x00FF00FF):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+	case (AMD_ID_LV800T & 0x00FF00FF):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+	case (AMD_ID_LV800B & 0x00FF00FF):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00400000;	/* Size doubled by yooth */
+		break;				/* => 4 MB		 */
+	case (AMD_ID_LV160T & 0x00FF00FF):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+	case (AMD_ID_LV160B & 0x00FF00FF):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+	case (AMD_ID_DL323B & 0x00FF00FF):
+		info->flash_id += FLASH_AMDL323B;
+		info->sector_count = 71;
+		info->size = 0x01000000;
+		break;                          /* => 16 MB(4x4MB)  */
+	/* AMD_ID_DL323B= 0x22532253  FLASH_AMDL323B= 0x0013
+	 * AMD_ID_DL323B could be found in <flash.h>.[SAM]
+	 * So we could get : flash_id = 0x00000013.
+	 * The first four-bit represents VEDOR ID,leaving others for FLASH ID. */
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+	/* FLASH_BTYPE=0x0001 mask for bottom boot sector type.If the last bit equals 1,
+	 * it means bottom boot flash. GOOD IDEA! [SAM]
+	 */
+
+	/* set sector offsets for bottom boot block type        */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x00010000;
+		info->start[3] = base + 0x00018000;
+		info->start[4] = base + 0x00020000;
+		info->start[5] = base + 0x00028000;
+		info->start[6] = base + 0x00030000;
+		info->start[7] = base + 0x00038000;
+
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + ((i-7) * 0x00040000) ;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00010000;
+		info->start[i--] = base + info->size - 0x00018000;
+		info->start[i--] = base + info->size - 0x00020000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00040000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned long *)(info->start[i]);
+		/* info->protect[i] = addr[4] & 1 ; */
+		/* Mask it for disorder FLASH protection **[Sam]** */
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *)info->start[0];
+
+		*addr = 0xF0F0F0F0;	/* reset bank */
+	}
+	return (info->size);
+}
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+	addr[0xAAA] = 0x80808080;
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long *)(info->start[sect]) ;
+			addr[0] = 0x30303030 ;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long *)(info->start[l_sect]);
+	while ((addr[0] & 0x80808080) != 0x80808080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (vu_long *)info->start[0];
+	addr[0] = 0xF0F0F0F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+	addr[0xAAA] = 0xA0A0A0A0;
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}

board/RPXlite_dw/u-boot.lds

@@ -0,0 +1,139 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+/* XXX ?
+    . = env_offset;
+*/
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/RPXlite_dw/u-boot.lds.debug

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2002
+ * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this

board/adder/Makefile

@@ -0,0 +1,46 @@
+#
+# Copyright (C) 2004 Arabella Software Ltd.
+# Yuli Barcohen <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/adder/adder.c

@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * Support for Analogue&Micro Adder boards family.
+ * Tested on AdderII and Adder87x.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/*
+ * SDRAM is single Samsung K4S643232F-T70 chip.
+ * Minimal CPU frequency is 40MHz.
+ */
+static uint sdram_table[] = {
+	/* Single read	(offset 0x00 in UPM RAM) */
+	0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00,
+	0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04,
+
+	/* Burst read	(offset 0x08 in UPM RAM) */
+	0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00,
+	0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44,
+	0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35,
+	0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35,
+
+	/* Single write (offset 0x18 in UPM RAM) */
+	0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47,
+	0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+	/* Burst write	(offset 0x20 in UPM RAM) */
+	0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+	0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+	/* Refresh	(offset 0x30 in UPM RAM) */
+	0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+	/* Exception	(offset 0x3C in UPM RAM) */
+	0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04
+};
+
+long int initdram (int board_type)
+{
+	long int msize = CFG_SDRAM_SIZE;
+	volatile immap_t     *immap  = (volatile immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
+
+	/* Configure SDRAM refresh */
+	memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */
+
+	memctl->memc_mamr = (94 << 24) | CFG_MAMR;
+	memctl->memc_mar  = 0x0;
+	udelay(200);
+
+	/* Run precharge from location 0x15 */
+	memctl->memc_mcr = 0x80002115;
+	udelay(200);
+
+	/* Run 8 refresh cycles */
+	memctl->memc_mcr = 0x80002830;
+	udelay(200);
+
+	memctl->memc_mar = 0x88;
+	udelay(200);
+
+	/* Run MRS pattern from location 0x16 */
+	memctl->memc_mcr = 0x80002116;
+	udelay(200);
+
+	return msize;
+}
+
+int checkboard( void )
+{
+	puts("Board: Adder");
+#if defined(CONFIG_MPC885_FAMILY)
+	puts("87x\n");
+#elif defined(CONFIG_MPC866_FAMILY)
+	puts("II\n");
+#endif
+
+	return 0;
+}

board/adder/config.mk

@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2004 Arabella Software Ltd.
+# Yuli Barcohen <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Analogue&Micro Adder boards family
+#
+TEXT_BASE = 0xFE000000

board/adder/u-boot.lds

@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp        : { *(.interp)		}
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt           : { *(.plt)		}
+  .text          :
+  {
+    cpu/mpc8xx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)

board/altera/dk1c20/vectors.S

@@ -38,6 +38,8 @@
  *	_cwp_lolimit	-Handles register window underflows.
  *	_cwp_hilimit	-Handles register window overflows.
  *	_timebase_int	-Increments the timebase.
+ *	_brkpt_hw_int	-Hardware breakpoint handler.
+ *	_brkpt_sw_int	-Software breakpoint handler.
  *	_def_xhandler	-Default exception handler.
  *
  * _timebase_int handles a Nios Timer interrupt and increments the
@@ -58,9 +60,8 @@ _vectors:
 	.long	_def_xhandler@h		/* Vector 0  - NMI */
 	.long	_cwp_lolimit@h		/* Vector 1  -  underflow */
 	.long	_cwp_hilimit@h		/* Vector 2  - overflow	*/
-
-	.long	_def_xhandler@h		/* Vector 3 - GNUPro debug */
-	.long	_def_xhandler@h		/* Vector 4 - GNUPro debug */
+	.long	_brkpt_hw_int@h		/* Vector 3 - Breakpoint */
+	.long	_brkpt_sw_int@h		/* Vector 4 - Single step*/
 	.long	_def_xhandler@h		/* Vector 5 - GNUPro debug */
 	.long	_def_xhandler@h		/* Vector 6 - future reserved */
 	.long	_def_xhandler@h		/* Vector 7 - future reserved */

board/assabet/Makefile

@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# 2004 (c) MontaVista Software, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= assabet.o
+SOBJS	:= setup.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/assabet/assabet.c

@@ -0,0 +1,121 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <SA-1100.h>
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Board dependent initialisation
+ */
+
+#define ECOR			0x8000
+#define ECOR_RESET		0x80
+#define ECOR_LEVEL_IRQ		0x40
+#define ECOR_WR_ATTRIB		0x04
+#define ECOR_ENABLE		0x01
+
+#define ECSR			0x8002
+#define ECSR_IOIS8		0x20
+#define ECSR_PWRDWN		0x04
+#define ECSR_INT		0x02
+#define SMC_IO_SHIFT		2
+#define NCR_0           	(*((volatile u_char *)(0x100000a0)))
+#define NCR_ENET_OSC_EN		(1<<3)
+
+static inline u8
+readb(volatile u8 * p)
+{
+	return *p;
+}
+
+static inline void
+writeb(u8 v, volatile u8 * p)
+{
+	*p = v;
+}
+
+static void
+smc_init(void)
+{
+	u8 ecor;
+	u8 ecsr;
+	volatile u8 *addr = (volatile u8 *)(0x18000000 + (1 << 25));
+
+	NCR_0 |= NCR_ENET_OSC_EN;
+	udelay(100);
+
+	ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET;
+	writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT));
+	udelay(100);
+
+	/*
+	 * The device will ignore all writes to the enable bit while
+	 * reset is asserted, even if the reset bit is cleared in the
+	 * same write.  Must clear reset first, then enable the device.
+	 */
+	writeb(ecor, addr + (ECOR << SMC_IO_SHIFT));
+	writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT));
+
+	/*
+	 * Set the appropriate byte/word mode.
+	 */
+	ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8;
+	ecsr |= ECSR_IOIS8;
+	writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT));
+	udelay(100);
+}
+
+static void
+neponset_init(void)
+{
+	smc_init();
+}
+
+int
+board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_arch_number = 25;	/* Intel Assabet Board */
+	gd->bd->bi_boot_params = 0xc0000100;
+
+	neponset_init();
+
+	return 0;
+}
+
+int
+dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}

board/assabet/config.mk

@@ -0,0 +1,7 @@
+#
+# SA-1110 based Intel Assabet board
+#
+# The Intel Assabet 1 bank of 32 MiB SDRAM
+#
+
+TEXT_BASE = 0xc1f00000

board/assabet/setup.S

@@ -0,0 +1,136 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *		       Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include "config.h"
+#include "version.h"
+
+
+/*-----------------------------------------------------------------------
+ * Board defines:
+ */
+
+#define MDCNFG		0x00
+#define MDCAS00		0x04
+#define MDCAS01		0x08
+#define MDCAS02		0x0C
+#define MSC0		0x10
+#define MSC1		0x14
+#define MECR		0x18
+#define MDREFR		0x1C
+#define MDCAS20		0x20
+#define MDCAS21		0x24
+#define MDCAS22		0x28
+#define MSC2		0x2C
+#define SMCNFG		0x30
+
+#define ASSABET_BCR		(0x12000000)
+#define ASSABET_BCR_DB1110	(0x00a07490 | (0<<16) | (0<<17))
+#define ASSABET_SCR_nNEPONSET	(1 << 9)
+#define NEPONSET_LEDS		(0x10000010)
+
+
+/*-----------------------------------------------------------------------
+ * Setup parameters for the board:
+ */
+
+
+MEM_BASE:	.long	0xa0000000
+MEM_START:	.long	0xc0000000
+
+mdcnfg:		.long	0x72547254
+mdcas00:	.long	0xaaaaaa7f
+mdcas01:	.long	0xaaaaaaaa
+mdcas02:	.long	0xaaaaaaaa
+msc0:		.long	0x4b384370
+msc1:		.long	0x22212419
+mecr:		.long	0x994a994a
+mdrefr:		.long	0x04340327
+mdcas20:	.long	0xaaaaaa7f
+mdcas21:	.long	0xaaaaaaaa
+mdcas22:	.long	0xaaaaaaaa
+msc2:		.long	0x42196669
+smcnfg:		.long	0x00000000
+
+BCR:		.long	ASSABET_BCR
+BCR_DB1110:	.long	ASSABET_BCR_DB1110
+LEDS:		.long	NEPONSET_LEDS
+
+
+	.globl memsetup
+memsetup:
+
+	/* Setting up the memory and stuff */
+
+	ldr	r0, MEM_BASE
+	ldr	r1, mdcas00
+	str	r1, [r0, #MDCAS00]
+	ldr	r1, mdcas01
+	str	r1, [r0, #MDCAS01]
+	ldr	r1, mdcas02
+	str	r1, [r0, #MDCAS02]
+	ldr	r1, mdcas20
+	str	r1, [r0, #MDCAS20]
+	ldr	r1, mdcas21
+	str	r1, [r0, #MDCAS21]
+	ldr	r1, mdcas22
+	str	r1, [r0, #MDCAS22]
+	ldr	r1, mdrefr
+	str	r1, [r0, #MDREFR]
+	ldr	r1, mecr
+	str	r1, [r0, #MECR]
+	ldr	r1, msc0
+	str	r1, [r0, #MSC0]
+	ldr	r1, msc1
+	str	r1, [r0, #MSC1]
+	ldr	r1, msc2
+	str	r1, [r0, #MSC2]
+	ldr	r1, smcnfg
+	str	r1, [r0, #SMCNFG]
+
+	ldr	r1, mdcnfg
+	str	r1, [r0, #MDCNFG]
+
+	/* Load something to activate bank */
+	ldr	r2, MEM_START
+.rept	8
+	ldr	r3, [r2]
+.endr
+
+	/* Enable SDRAM */
+	orr	r1, r1, #0x00000001
+	str	r1, [r0, #MDCNFG]
+
+	ldr	r1, BCR
+	ldr	r2, BCR_DB1110
+	str	r2, [r1]
+
+	ldr	r1, LEDS
+	mov	r0, #0x3
+	str	r0, [r1]
+
+	/* All done... */
+	mov	pc, lr

board/assabet/u-boot.lds

@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+		cpu/sa1100/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/bmw/ns16550.c

@@ -9,49 +9,49 @@
 
 typedef struct NS16550 *NS16550_t;
 
-const NS16550_t COM_PORTS[] = { (NS16550_t) ((CFG_EUMB_ADDR) + 0x4500), (NS16550_t) ((CFG_EUMB_ADDR) + 0x4600)};
+const NS16550_t COM_PORTS[] =
+	{ (NS16550_t) ((CFG_EUMB_ADDR) + 0x4500),
+(NS16550_t) ((CFG_EUMB_ADDR) + 0x4600) };
 
-volatile struct NS16550 *
-NS16550_init(int chan, int baud_divisor)
+volatile struct NS16550 *NS16550_init (int chan, int baud_divisor)
 {
- volatile struct NS16550 *com_port;
- com_port = (struct NS16550 *) COM_PORTS[chan];
- com_port->ier = 0x00;
- com_port->lcr = LCR_BKSE;              /* Access baud rate */
- com_port->dll = baud_divisor & 0xff;   /* 9600 baud */
- com_port->dlm = (baud_divisor >> 8) & 0xff;
- com_port->lcr = LCR_8N1;               /* 8 data, 1 stop, no parity */
- com_port->mcr = MCR_RTS;     /* RTS/DTR */
- com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;                  /* Clear & enable FIFOs */
-return (com_port);
+	volatile struct NS16550 *com_port;
+
+	com_port = (struct NS16550 *) COM_PORTS[chan];
+	com_port->ier = 0x00;
+	com_port->lcr = LCR_BKSE;	/* Access baud rate */
+	com_port->dll = baud_divisor & 0xff;	/* 9600 baud */
+	com_port->dlm = (baud_divisor >> 8) & 0xff;
+	com_port->lcr = LCR_8N1;	/* 8 data, 1 stop, no parity */
+	com_port->mcr = MCR_RTS;	/* RTS/DTR */
+	com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;	/* Clear & enable FIFOs */
+	return (com_port);
 }
 
-void
-NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor)
+void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor)
 {
- com_port->ier = 0x00;
- com_port->lcr = LCR_BKSE;              /* Access baud rate */
- com_port->dll = baud_divisor & 0xff;   /* 9600 baud */
- com_port->dlm = (baud_divisor >> 8) & 0xff;
- com_port->lcr = LCR_8N1;               /* 8 data, 1 stop, no parity */
- com_port->mcr = MCR_RTS;     /* RTS/DTR */
- com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;                  /* Clear & enable FIFOs */
+	com_port->ier = 0x00;
+	com_port->lcr = LCR_BKSE;	/* Access baud rate */
+	com_port->dll = baud_divisor & 0xff;	/* 9600 baud */
+	com_port->dlm = (baud_divisor >> 8) & 0xff;
+	com_port->lcr = LCR_8N1;	/* 8 data, 1 stop, no parity */
+	com_port->mcr = MCR_RTS;	/* RTS/DTR */
+	com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;	/* Clear & enable FIFOs */
 }
 
-void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c)
+void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c)
 {
- while ((com_port->lsr & LSR_THRE) == 0) ;
- com_port->thr = c;
+	while ((com_port->lsr & LSR_THRE) == 0);
+	com_port->thr = c;
 }
 
-unsigned char
-NS16550_getc(volatile struct NS16550 *com_port)
+unsigned char NS16550_getc (volatile struct NS16550 *com_port)
 {
- while ((com_port->lsr & LSR_DR) == 0) ;
- return (com_port->rbr);
+	while ((com_port->lsr & LSR_DR) == 0);
+	return (com_port->rbr);
 }
 
-int NS16550_tstc(volatile struct NS16550 *com_port)
+int NS16550_tstc (volatile struct NS16550 *com_port)
 {
- return ((com_port->lsr & LSR_DR) != 0);
+	return ((com_port->lsr & LSR_DR) != 0);
 }

board/bmw/ns16550.h

@@ -12,20 +12,19 @@
  */
 
 
-struct NS16550
- {
-  unsigned char rbrthrdlb;  /* 0 */
-  unsigned char ierdmb;     /* 1 */
-  unsigned char iirfcrafr;  /* 2 */
-  unsigned char lcr;         /* 3 */
-  unsigned char mcr;         /* 4 */
-  unsigned char lsr;         /* 5 */
-  unsigned char msr;         /* 6 */
-  unsigned char scr;         /* 7 */
-  unsigned char reserved[2]; /* 8 & 9 */
-  unsigned char dsr;         /* 10 */
-  unsigned char dcr;         /* 11 */
- };
+struct NS16550 {
+	unsigned char rbrthrdlb;	/* 0 */
+	unsigned char ierdmb;		/* 1 */
+	unsigned char iirfcrafr;	/* 2 */
+	unsigned char lcr;		/* 3 */
+	unsigned char mcr;		/* 4 */
+	unsigned char lsr;		/* 5 */
+	unsigned char msr;		/* 6 */
+	unsigned char scr;		/* 7 */
+	unsigned char reserved[2];	/* 8 & 9 */
+	unsigned char dsr;		/* 10 */
+	unsigned char dcr;		/* 11 */
+};
 
 
 #define rbr rbrthrdlb
@@ -37,44 +36,44 @@ struct NS16550
 #define fcr iirfcrafr
 #define afr iirfcrafr
 
-#define FCR_FIFO_EN     0x01    /*fifo enable*/
-#define FCR_RXSR        0x02    /*reciever soft reset*/
-#define FCR_TXSR        0x04    /*transmitter soft reset*/
-#define FCR_DMS		0x08    /* DMA Mode Select */
+#define FCR_FIFO_EN     0x01	/*fifo enable */
+#define FCR_RXSR        0x02	/*reciever soft reset */
+#define FCR_TXSR        0x04	/*transmitter soft reset */
+#define FCR_DMS		0x08	/* DMA Mode Select */
 
-#define MCR_RTS         0x02    /* Readyu to Send */
+#define MCR_RTS         0x02	/* Readyu to Send */
 #define MCR_LOOP	0x10	/* Local loopback mode enable */
 /* #define MCR_DTR         0x01    noton 8245 duart */
 /* #define MCR_DMA_EN      0x04    noton 8245 duart */
 /* #define MCR_TX_DFR      0x08    noton 8245 duart */
 
-#define LCR_WLS_MSK 0x03    /* character length slect mask*/
-#define LCR_WLS_5   0x00    /* 5 bit character length */
-#define LCR_WLS_6   0x01    /* 6 bit character length */
-#define LCR_WLS_7   0x02    /* 7 bit character length */
-#define LCR_WLS_8   0x03    /* 8 bit character length */
-#define LCR_STB     0x04    /* Number of stop Bits, off = 1, on = 1.5 or 2) */
-#define LCR_PEN     0x08    /* Parity eneble*/
-#define LCR_EPS     0x10    /* Even Parity Select*/
-#define LCR_STKP    0x20    /* Stick Parity*/
-#define LCR_SBRK    0x40    /* Set Break*/
-#define LCR_BKSE    0x80    /* Bank select enable - aka DLAB on 8245 */
+#define LCR_WLS_MSK 0x03	/* character length slect mask */
+#define LCR_WLS_5   0x00	/* 5 bit character length */
+#define LCR_WLS_6   0x01	/* 6 bit character length */
+#define LCR_WLS_7   0x02	/* 7 bit character length */
+#define LCR_WLS_8   0x03	/* 8 bit character length */
+#define LCR_STB     0x04	/* Number of stop Bits, off = 1, on = 1.5 or 2) */
+#define LCR_PEN     0x08	/* Parity eneble */
+#define LCR_EPS     0x10	/* Even Parity Select */
+#define LCR_STKP    0x20	/* Stick Parity */
+#define LCR_SBRK    0x40	/* Set Break */
+#define LCR_BKSE    0x80	/* Bank select enable - aka DLAB on 8245 */
 
-#define LSR_DR      0x01    /* Data ready */
-#define LSR_OE      0x02    /* Overrun */
-#define LSR_PE      0x04    /* Parity error */
-#define LSR_FE      0x08    /* Framing error */
-#define LSR_BI      0x10    /* Break */
-#define LSR_THRE    0x20    /* Xmit holding register empty */
-#define LSR_TEMT    0x40    /* Xmitter empty */
-#define LSR_ERR     0x80    /* Error */
+#define LSR_DR      0x01	/* Data ready */
+#define LSR_OE      0x02	/* Overrun */
+#define LSR_PE      0x04	/* Parity error */
+#define LSR_FE      0x08	/* Framing error */
+#define LSR_BI      0x10	/* Break */
+#define LSR_THRE    0x20	/* Xmit holding register empty */
+#define LSR_TEMT    0x40	/* Xmitter empty */
+#define LSR_ERR     0x80	/* Error */
 
 /* useful defaults for LCR*/
 #define LCR_8N1     0x03
 
 
-volatile struct NS16550 * NS16550_init(int chan, int baud_divisor);
-void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c);
-unsigned char NS16550_getc(volatile struct NS16550 *com_port);
-int NS16550_tstc(volatile struct NS16550 *com_port);
-void NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor);
+volatile struct NS16550 *NS16550_init (int chan, int baud_divisor);
+void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c);
+unsigned char NS16550_getc (volatile struct NS16550 *com_port);
+int NS16550_tstc (volatile struct NS16550 *com_port);
+void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor);

board/cogent/mb.c

@@ -43,152 +43,166 @@
 
 const iop_conf_t iop_conf_tab[4][32] = {
 
-    /* Port A configuration */
-    {	/*	      conf ppar psor pdir podr pdat */
-	/* PA31 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA30 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA29 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA28 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA27 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA26 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA25 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA24 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA23 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA22 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA21 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA20 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA19 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA18 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA17 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA16 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA15 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA14 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA13 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA12 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA11 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA10 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA9  */ {   1,   1,   0,   1,   0,   0   },	/* SMC2 TXD */
-	/* PA8  */ {   1,   1,   0,   0,   0,   0   },	/* SMC2 RXD */
-	/* PA7  */ {   0,   0,   0,   0,   0,   0   },
-	/* PA6  */ {   0,   0,   0,   0,   0,   0   },
-	/* PA5  */ {   0,   0,   0,   0,   0,   0   },
-	/* PA4  */ {   0,   0,   0,   0,   0,   0   },
-	/* PA3  */ {   0,   0,   0,   0,   0,   0   },
-	/* PA2  */ {   0,   0,   0,   0,   0,   0   },
-	/* PA1  */ {   0,   0,   0,   0,   0,   0   },
-	/* PA0  */ {   0,   0,   0,   0,   0,   0   }
-    },
+	/* Port A configuration */
+	{			/*            conf ppar psor pdir podr pdat */
+	 /* PA31 */ {0, 0, 0, 0, 0, 0},
+	 /* PA30 */ {0, 0, 0, 0, 0, 0},
+	 /* PA29 */ {0, 0, 0, 0, 0, 0},
+	 /* PA28 */ {0, 0, 0, 0, 0, 0},
+	 /* PA27 */ {0, 0, 0, 0, 0, 0},
+	 /* PA26 */ {0, 0, 0, 0, 0, 0},
+	 /* PA25 */ {0, 0, 0, 0, 0, 0},
+	 /* PA24 */ {0, 0, 0, 0, 0, 0},
+	 /* PA23 */ {0, 0, 0, 0, 0, 0},
+	 /* PA22 */ {0, 0, 0, 0, 0, 0},
+	 /* PA21 */ {0, 0, 0, 0, 0, 0},
+	 /* PA20 */ {0, 0, 0, 0, 0, 0},
+	 /* PA19 */ {0, 0, 0, 0, 0, 0},
+	 /* PA18 */ {0, 0, 0, 0, 0, 0},
+	 /* PA17 */ {0, 0, 0, 0, 0, 0},
+	 /* PA16 */ {0, 0, 0, 0, 0, 0},
+	 /* PA15 */ {0, 0, 0, 0, 0, 0},
+	 /* PA14 */ {0, 0, 0, 0, 0, 0},
+	 /* PA13 */ {0, 0, 0, 0, 0, 0},
+	 /* PA12 */ {0, 0, 0, 0, 0, 0},
+	 /* PA11 */ {0, 0, 0, 0, 0, 0},
+	 /* PA10 */ {0, 0, 0, 0, 0, 0},
+					/* PA9  */ {1, 1, 0, 1, 0, 0},
+					/* SMC2 TXD */
+					/* PA8  */ {1, 1, 0, 0, 0, 0},
+					/* SMC2 RXD */
+	 /* PA7  */ {0, 0, 0, 0, 0, 0},
+	 /* PA6  */ {0, 0, 0, 0, 0, 0},
+	 /* PA5  */ {0, 0, 0, 0, 0, 0},
+	 /* PA4  */ {0, 0, 0, 0, 0, 0},
+	 /* PA3  */ {0, 0, 0, 0, 0, 0},
+	 /* PA2  */ {0, 0, 0, 0, 0, 0},
+	 /* PA1  */ {0, 0, 0, 0, 0, 0},
+	 /* PA0  */ {0, 0, 0, 0, 0, 0}
+	 },
 
 
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PB31 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB30 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB29 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB28 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB27 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB26 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB25 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB24 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB23 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB22 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB21 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB20 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB19 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB18 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB17 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB16 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB15 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB14 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB13 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB12 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB11 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB10 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB9  */ {   0,   0,   0,   0,   0,   0   },
-	/* PB8  */ {   0,   0,   0,   0,   0,   0   },
-	/* PB7  */ {   0,   0,   0,   0,   0,   0   },
-	/* PB6  */ {   0,   0,   0,   0,   0,   0   },
-	/* PB5  */ {   0,   0,   0,   0,   0,   0   },
-	/* PB4  */ {   0,   0,   0,   0,   0,   0   },
-	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
-    },
+	{			/*            conf ppar psor pdir podr pdat */
+	 /* PB31 */ {0, 0, 0, 0, 0, 0},
+	 /* PB30 */ {0, 0, 0, 0, 0, 0},
+	 /* PB29 */ {0, 0, 0, 0, 0, 0},
+	 /* PB28 */ {0, 0, 0, 0, 0, 0},
+	 /* PB27 */ {0, 0, 0, 0, 0, 0},
+	 /* PB26 */ {0, 0, 0, 0, 0, 0},
+	 /* PB25 */ {0, 0, 0, 0, 0, 0},
+	 /* PB24 */ {0, 0, 0, 0, 0, 0},
+	 /* PB23 */ {0, 0, 0, 0, 0, 0},
+	 /* PB22 */ {0, 0, 0, 0, 0, 0},
+	 /* PB21 */ {0, 0, 0, 0, 0, 0},
+	 /* PB20 */ {0, 0, 0, 0, 0, 0},
+	 /* PB19 */ {0, 0, 0, 0, 0, 0},
+	 /* PB18 */ {0, 0, 0, 0, 0, 0},
+	 /* PB17 */ {0, 0, 0, 0, 0, 0},
+	 /* PB16 */ {0, 0, 0, 0, 0, 0},
+	 /* PB15 */ {0, 0, 0, 0, 0, 0},
+	 /* PB14 */ {0, 0, 0, 0, 0, 0},
+	 /* PB13 */ {0, 0, 0, 0, 0, 0},
+	 /* PB12 */ {0, 0, 0, 0, 0, 0},
+	 /* PB11 */ {0, 0, 0, 0, 0, 0},
+	 /* PB10 */ {0, 0, 0, 0, 0, 0},
+	 /* PB9  */ {0, 0, 0, 0, 0, 0},
+	 /* PB8  */ {0, 0, 0, 0, 0, 0},
+	 /* PB7  */ {0, 0, 0, 0, 0, 0},
+	 /* PB6  */ {0, 0, 0, 0, 0, 0},
+	 /* PB5  */ {0, 0, 0, 0, 0, 0},
+	 /* PB4  */ {0, 0, 0, 0, 0, 0},
+					/* PB3  */ {0, 0, 0, 0, 0, 0},
+					/* pin doesn't exist */
+					/* PB2  */ {0, 0, 0, 0, 0, 0},
+					/* pin doesn't exist */
+					/* PB1  */ {0, 0, 0, 0, 0, 0},
+					/* pin doesn't exist */
+					/* PB0  */ {0, 0, 0, 0, 0, 0}
+					/* pin doesn't exist */
+	 },
 
 
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PC31 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC30 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC29 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC28 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC27 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC26 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC25 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC24 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC23 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC22 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC21 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC20 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC19 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC18 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC17 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC16 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC15 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC14 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC13 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC12 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC11 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC10 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC9  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC8  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC7  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC6  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC5  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC4  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC3  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC2  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC1  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC0  */ {   0,   0,   0,   0,   0,   0   }
-    },
+	{			/*            conf ppar psor pdir podr pdat */
+	 /* PC31 */ {0, 0, 0, 0, 0, 0},
+	 /* PC30 */ {0, 0, 0, 0, 0, 0},
+	 /* PC29 */ {0, 0, 0, 0, 0, 0},
+	 /* PC28 */ {0, 0, 0, 0, 0, 0},
+	 /* PC27 */ {0, 0, 0, 0, 0, 0},
+	 /* PC26 */ {0, 0, 0, 0, 0, 0},
+	 /* PC25 */ {0, 0, 0, 0, 0, 0},
+	 /* PC24 */ {0, 0, 0, 0, 0, 0},
+	 /* PC23 */ {0, 0, 0, 0, 0, 0},
+	 /* PC22 */ {0, 0, 0, 0, 0, 0},
+	 /* PC21 */ {0, 0, 0, 0, 0, 0},
+	 /* PC20 */ {0, 0, 0, 0, 0, 0},
+	 /* PC19 */ {0, 0, 0, 0, 0, 0},
+	 /* PC18 */ {0, 0, 0, 0, 0, 0},
+	 /* PC17 */ {0, 0, 0, 0, 0, 0},
+	 /* PC16 */ {0, 0, 0, 0, 0, 0},
+	 /* PC15 */ {0, 0, 0, 0, 0, 0},
+	 /* PC14 */ {0, 0, 0, 0, 0, 0},
+	 /* PC13 */ {0, 0, 0, 0, 0, 0},
+	 /* PC12 */ {0, 0, 0, 0, 0, 0},
+	 /* PC11 */ {0, 0, 0, 0, 0, 0},
+	 /* PC10 */ {0, 0, 0, 0, 0, 0},
+	 /* PC9  */ {0, 0, 0, 0, 0, 0},
+	 /* PC8  */ {0, 0, 0, 0, 0, 0},
+	 /* PC7  */ {0, 0, 0, 0, 0, 0},
+	 /* PC6  */ {0, 0, 0, 0, 0, 0},
+	 /* PC5  */ {0, 0, 0, 0, 0, 0},
+	 /* PC4  */ {0, 0, 0, 0, 0, 0},
+	 /* PC3  */ {0, 0, 0, 0, 0, 0},
+	 /* PC2  */ {0, 0, 0, 0, 0, 0},
+	 /* PC1  */ {0, 0, 0, 0, 0, 0},
+	 /* PC0  */ {0, 0, 0, 0, 0, 0}
+	 },
 
 
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PD31 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD30 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD29 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD28 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD27 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD26 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD25 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD24 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD23 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD22 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD21 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD20 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD19 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD18 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD17 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD16 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD15 */ {   1,   1,   1,   0,   0,   0   },	/* I2C SDA */
-	/* PD14 */ {   1,   1,   1,   0,   0,   0   },	/* I2C SCL */
-	/* PD13 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD12 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD11 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD10 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD9  */ {   1,   1,   0,   1,   0,   0   },	/* SMC1 TXD */
-	/* PD8  */ {   1,   1,   0,   0,   0,   0   },	/* SMC1 RXD */
-	/* PD7  */ {   0,   0,   0,   0,   0,   0   },
-	/* PD6  */ {   0,   0,   0,   0,   0,   0   },
-	/* PD5  */ {   0,   0,   0,   0,   0,   0   },
-	/* PD4  */ {   0,   0,   0,   0,   0,   0   },
-	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
-    }
+	{			/*            conf ppar psor pdir podr pdat */
+	 /* PD31 */ {0, 0, 0, 0, 0, 0},
+	 /* PD30 */ {0, 0, 0, 0, 0, 0},
+	 /* PD29 */ {0, 0, 0, 0, 0, 0},
+	 /* PD28 */ {0, 0, 0, 0, 0, 0},
+	 /* PD27 */ {0, 0, 0, 0, 0, 0},
+	 /* PD26 */ {0, 0, 0, 0, 0, 0},
+	 /* PD25 */ {0, 0, 0, 0, 0, 0},
+	 /* PD24 */ {0, 0, 0, 0, 0, 0},
+	 /* PD23 */ {0, 0, 0, 0, 0, 0},
+	 /* PD22 */ {0, 0, 0, 0, 0, 0},
+	 /* PD21 */ {0, 0, 0, 0, 0, 0},
+	 /* PD20 */ {0, 0, 0, 0, 0, 0},
+	 /* PD19 */ {0, 0, 0, 0, 0, 0},
+	 /* PD18 */ {0, 0, 0, 0, 0, 0},
+	 /* PD17 */ {0, 0, 0, 0, 0, 0},
+	 /* PD16 */ {0, 0, 0, 0, 0, 0},
+					/* PD15 */ {1, 1, 1, 0, 0, 0},
+					/* I2C SDA */
+					/* PD14 */ {1, 1, 1, 0, 0, 0},
+					/* I2C SCL */
+	 /* PD13 */ {0, 0, 0, 0, 0, 0},
+	 /* PD12 */ {0, 0, 0, 0, 0, 0},
+	 /* PD11 */ {0, 0, 0, 0, 0, 0},
+	 /* PD10 */ {0, 0, 0, 0, 0, 0},
+					/* PD9  */ {1, 1, 0, 1, 0, 0},
+					/* SMC1 TXD */
+					/* PD8  */ {1, 1, 0, 0, 0, 0},
+					/* SMC1 RXD */
+	 /* PD7  */ {0, 0, 0, 0, 0, 0},
+	 /* PD6  */ {0, 0, 0, 0, 0, 0},
+	 /* PD5  */ {0, 0, 0, 0, 0, 0},
+	 /* PD4  */ {0, 0, 0, 0, 0, 0},
+					/* PD3  */ {0, 0, 0, 0, 0, 0},
+					/* pin doesn't exist */
+					/* PD2  */ {0, 0, 0, 0, 0, 0},
+					/* pin doesn't exist */
+					/* PD1  */ {0, 0, 0, 0, 0, 0},
+					/* pin doesn't exist */
+					/* PD0  */ {0, 0, 0, 0, 0, 0}
+					/* pin doesn't exist */
+	 }
 };
 
-#endif	/* CONFIG_8260 */
+#endif /* CONFIG_8260 */
 
 /* ------------------------------------------------------------------------- */
 
@@ -196,12 +210,11 @@ const iop_conf_t iop_conf_tab[4][32] = {
  * Check Board Identity:
  */
 
-int
-checkboard(void)
+int checkboard (void)
 {
-    puts ("Board: Cogent " COGENT_MOTHERBOARD " motherboard with a "
-	COGENT_CPU_MODULE " CPU Module\n");
-    return (0);
+	puts ("Board: Cogent " COGENT_MOTHERBOARD " motherboard with a "
+	      COGENT_CPU_MODULE " CPU Module\n");
+	return (0);
 }
 
 /* ------------------------------------------------------------------------- */
@@ -213,46 +226,44 @@ checkboard(void)
 
 int misc_init_f (void)
 {
-    printf ("DIPSW: ");
-    dipsw_init();
-    return (0);
+	printf ("DIPSW: ");
+	dipsw_init ();
+	return (0);
 }
 
 /* ------------------------------------------------------------------------- */
 
-long int
-initdram(int board_type)
+long int initdram (int board_type)
 {
-#if CONFIG_CMA111
-    return (32L * 1024L * 1024L);
+#ifdef CONFIG_CMA111
+	return (32L * 1024L * 1024L);
 #else
-    unsigned char dipsw_val;
-    int dual, size0, size1;
-    long int memsize;
+	unsigned char dipsw_val;
+	int dual, size0, size1;
+	long int memsize;
 
-    dipsw_val = dipsw_cooked();
+	dipsw_val = dipsw_cooked ();
 
-    dual = dipsw_val & 0x01;
-    size0 = (dipsw_val & 0x08) >> 3;
-    size1 = (dipsw_val & 0x04) >> 2;
+	dual = dipsw_val & 0x01;
+	size0 = (dipsw_val & 0x08) >> 3;
+	size1 = (dipsw_val & 0x04) >> 2;
 
-    if (size0)
-	if (size1)
-	    memsize = 16L * 1024L * 1024L;
-	else
-	    memsize =  1L * 1024L * 1024L;
-    else
-	if (size1)
-	    memsize =  4L * 1024L * 1024L;
+	if (size0)
+		if (size1)
+			memsize = 16L * 1024L * 1024L;
+		else
+			memsize = 1L * 1024L * 1024L;
+	else if (size1)
+		memsize = 4L * 1024L * 1024L;
 	else {
-	    printf("[Illegal dip switch settings - assuming 16Mbyte SIMMs] ");
-	    memsize = 16L * 1024L * 1024L; /* shouldn't happen - guess 16M */
+		printf ("[Illegal dip switch settings - assuming 16Mbyte SIMMs] ");
+		memsize = 16L * 1024L * 1024L;	/* shouldn't happen - guess 16M */
 	}
 
-    if (dual)
-	memsize *= 2L;
+	if (dual)
+		memsize *= 2L;
 
-    return (memsize);
+	return (memsize);
 #endif
 }
 
@@ -265,21 +276,21 @@ initdram(int board_type)
 
 int misc_init_r (void)
 {
-    printf ("LCD:   ");
-    lcd_init();
+	printf ("LCD:   ");
+	lcd_init ();
 
 #if 0
-    printf ("RTC:   ");
-    rtc_init();
+	printf ("RTC:   ");
+	rtc_init ();
 
-    printf ("PAR:   ");
-    par_init();
+	printf ("PAR:   ");
+	par_init ();
 
-    printf ("KBM:   ");
-    kbm_init();
+	printf ("KBM:   ");
+	kbm_init ();
 
-    printf ("PCI:   ");
-    pci_init();
+	printf ("PCI:   ");
+	pci_init ();
 #endif
-    return (0);
+	return (0);
 }

board/cpc45/cpc45.c

@@ -25,6 +25,7 @@
 #include <mpc824x.h>
 #include <asm/processor.h>
 #include <pci.h>
+#include <i2c.h>
 
 int sysControlDisplay(int digit, uchar ascii_code);
 extern void Plx9030Init(void);
@@ -49,7 +50,7 @@ int checkboard(void)
 	ulong busfreq  = get_bus_freq(0);
 	char  buf[32];
 
-	printf("CPC45 ");
+	puts ("CPC45  ");
 /*
 	printf("Revision %d ", revision);
 */
@@ -58,46 +59,134 @@ int checkboard(void)
 	return 0;
 }
 
-long int initdram(int board_type)
+long int initdram (int board_type)
 {
-	long size;
-	long new_bank0_end;
-	long mear1;
-	long emear1;
+	int m, row, col, bank, i, ref;
+	unsigned long start, end;
+	uint32_t mccr1, mccr2;
+	uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
+	uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
+	uint8_t mber = 0;
+	unsigned int tmp;
 
-	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
 
-	new_bank0_end = size - 1;
-	mear1 = mpc824x_mpc107_getreg(MEAR1);
-	emear1 = mpc824x_mpc107_getreg(EMEAR1);
-	mear1 = (mear1  & 0xFFFFFF00) |
-		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
-	emear1 = (emear1 & 0xFFFFFF00) |
-		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
-	mpc824x_mpc107_setreg(MEAR1, mear1);
-	mpc824x_mpc107_setreg(EMEAR1, emear1);
+	if (i2c_reg_read (0x50, 2) != 0x04)
+		return 0;	/* Memory type */
 
-	return (size);
+	m = i2c_reg_read (0x50, 5);	/* # of physical banks */
+	row = i2c_reg_read (0x50, 3);	/* # of rows */
+	col = i2c_reg_read (0x50, 4);	/* # of columns */
+	bank = i2c_reg_read (0x50, 17);	/* # of logical banks */
+	ref  = i2c_reg_read (0x50, 12);	/* refresh rate / type */
+
+	CONFIG_READ_WORD(MCCR1, mccr1);
+	mccr1 &= 0xffff0000;
+
+	CONFIG_READ_WORD(MCCR2, mccr2);
+	mccr2 &= 0xffff0000;
+
+	start = CFG_SDRAM_BASE;
+	end = start + (1 << (col + row + 3) ) * bank - 1;
+
+	for (i = 0; i < m; i++) {
+		mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
+		if (i < 4) {
+			msar1  |= ((start >> 20) & 0xff) << i * 8;
+			emsar1 |= ((start >> 28) & 0xff) << i * 8;
+			mear1  |= ((end >> 20) & 0xff) << i * 8;
+			emear1 |= ((end >> 28) & 0xff) << i * 8;
+		} else {
+			msar2  |= ((start >> 20) & 0xff) << (i-4) * 8;
+			emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
+			mear2  |= ((end >> 20) & 0xff) << (i-4) * 8;
+			emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
+		}
+		mber |= 1 << i;
+		start += (1 << (col + row + 3) ) * bank;
+		end += (1 << (col + row + 3) ) * bank;
+	}
+	for (; i < 8; i++) {
+		if (i < 4) {
+			msar1  |= 0xff << i * 8;
+			emsar1 |= 0x30 << i * 8;
+			mear1  |= 0xff << i * 8;
+			emear1 |= 0x30 << i * 8;
+		} else {
+			msar2  |= 0xff << (i-4) * 8;
+			emsar2 |= 0x30 << (i-4) * 8;
+			mear2  |= 0xff << (i-4) * 8;
+			emear2 |= 0x30 << (i-4) * 8;
+		}
+	}
+
+	switch(ref) {
+		case 0x00:
+		case 0x80:
+			tmp = get_bus_freq(0) / 1000000 * 15625 / 1000 - 22;
+			break;
+		case 0x01:
+		case 0x81:
+			tmp = get_bus_freq(0) / 1000000 * 3900 / 1000 - 22;
+			break;
+		case 0x02:
+		case 0x82:
+			tmp = get_bus_freq(0) / 1000000 * 7800 / 1000 - 22;
+			break;
+		case 0x03:
+		case 0x83:
+			tmp = get_bus_freq(0) / 1000000 * 31300 / 1000 - 22;
+			break;
+		case 0x04:
+		case 0x84:
+			tmp = get_bus_freq(0) / 1000000 * 62500 / 1000 - 22;
+			break;
+		case 0x05:
+		case 0x85:
+			tmp = get_bus_freq(0) / 1000000 * 125000 / 1000 - 22;
+			break;
+		default:
+			tmp = 0x512;
+			break;
+	}
+
+	CONFIG_WRITE_WORD(MCCR1, mccr1);
+	CONFIG_WRITE_WORD(MCCR2, tmp << MCCR2_REFINT_SHIFT);
+	CONFIG_WRITE_WORD(MSAR1, msar1);
+	CONFIG_WRITE_WORD(EMSAR1, emsar1);
+	CONFIG_WRITE_WORD(MEAR1, mear1);
+	CONFIG_WRITE_WORD(EMEAR1, emear1);
+	CONFIG_WRITE_WORD(MSAR2, msar2);
+	CONFIG_WRITE_WORD(EMSAR2, emsar2);
+	CONFIG_WRITE_WORD(MEAR2, mear2);
+	CONFIG_WRITE_WORD(EMEAR2, emear2);
+	CONFIG_WRITE_BYTE(MBER, mber);
+
+	return (1 << (col + row + 3) ) * bank * m;
 }
 
+
 /*
  * Initialize PCI Devices, report devices found.
  */
-#ifndef CONFIG_PCI_PNP
 
-static struct pci_config_table pci_sandpoint_config_table[] = {
-	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
+static struct pci_config_table pci_cpc45_config_table[] = {
+#ifndef CONFIG_PCI_PNP
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0F, PCI_ANY_ID,
 	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
 				       PCI_ENET0_MEMADDR,
 				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0D, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_PLX9030_IOADDR,
+				       PCI_PLX9030_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+#endif /*CONFIG_PCI_PNP*/
 	{ }
 };
-#endif
-
 
 struct pci_controller hose = {
 #ifndef CONFIG_PCI_PNP
-	config_table: pci_sandpoint_config_table,
+	config_table: pci_cpc45_config_table,
 #endif
 };
 
@@ -108,6 +197,9 @@ void pci_init_board(void)
 	/* init PCI_to_LOCAL Bus BRIDGE */
 	Plx9030Init();
 
+	/* Clear Display */
+	DISP_CWORD = 0x0;
+
 	sysControlDisplay(0,' ');
 	sysControlDisplay(1,'C');
 	sysControlDisplay(2,'P');
@@ -130,16 +222,14 @@ void pci_init_board(void)
 * RETURNS: NA
 */
 
-int sysControlDisplay
-    (
-    int digit, 			/* number of digit 0..7 */
-    uchar ascii_code		/* ASCII code */
-    )
+int sysControlDisplay (int digit,	/* number of digit 0..7 */
+		       uchar ascii_code	/* ASCII code */
+		      )
 {
 	if ((digit < 0) || (digit > 7))
 		return (-1);
 
-	*((volatile uchar*)(DISP_CHR_RAM + digit)) = ascii_code;
+	*((volatile uchar *) (DISP_CHR_RAM + digit)) = ascii_code;
 
 	return (0);
 }

board/cpc45/flash.c

@@ -41,12 +41,12 @@
 #define MAIN_SECT_SIZE  0x40000
 #define PARAM_SECT_SIZE 0x8000
 
-flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
 
-static int write_data (flash_info_t *info, ulong dest, ulong *data);
-static void write_via_fpu(vu_long *addr, ulong *data);
-static __inline__ unsigned long get_msr(void);
-static __inline__ void set_msr(unsigned long msr);
+static int write_data (flash_info_t * info, ulong dest, ulong * data);
+static void write_via_fpu (vu_long * addr, ulong * data);
+static __inline__ unsigned long get_msr (void);
+static __inline__ void set_msr (unsigned long msr);
 
 /*---------------------------------------------------------------------*/
 #undef	DEBUG_FLASH
@@ -62,102 +62,132 @@ static __inline__ void set_msr(unsigned long msr);
 /*-----------------------------------------------------------------------
  */
 
-unsigned long flash_init(void)
+unsigned long flash_init (void)
 {
-    int i, j;
-    ulong size = 0;
-    uchar tempChar;
+	int i, j;
+	ulong size = 0;
+	uchar tempChar;
+	vu_long *tmpaddr;
 
-   /* Enable flash writes on CPC45 */
+	/* Enable flash writes on CPC45 */
 
-    tempChar = BOARD_CTRL;
+	tempChar = BOARD_CTRL;
 
-    tempChar |= (B_CTRL_FWPT_1 | B_CTRL_FWRE_1);
+	tempChar |= (B_CTRL_FWPT_1 | B_CTRL_FWRE_1);
 
-    tempChar &= ~(B_CTRL_FWPT_0 | B_CTRL_FWRE_0);
+	tempChar &= ~(B_CTRL_FWPT_0 | B_CTRL_FWRE_0);
 
-    BOARD_CTRL = tempChar;
+	BOARD_CTRL = tempChar;
+
+	__asm__ volatile ("sync\n eieio");
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		vu_long *addr = (vu_long *) (CFG_FLASH_BASE + i * FLASH_BANK_SIZE);
+
+		addr[0] = 0x00900090;
+
+		__asm__ volatile ("sync\n eieio");
+
+		udelay (100);
+
+		DEBUGF ("Flash bank # %d:\n"
+			"\tManuf. ID @ 0x%08lX: 0x%08lX\n"
+			"\tDevice ID @ 0x%08lX: 0x%08lX\n",
+			i,
+			(ulong) (&addr[0]), addr[0],
+			(ulong) (&addr[2]), addr[2]);
 
 
-    for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
-	vu_long *addr = (vu_long *)(CFG_FLASH_BASE + i * FLASH_BANK_SIZE);
+		if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) &&
+		    (addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3T)) {
 
-	addr[0] = 0x00900090;
+			flash_info[i].flash_id =
+				(FLASH_MAN_INTEL & FLASH_VENDMASK) |
+				(INTEL_ID_28F160F3T & FLASH_TYPEMASK);
 
-	DEBUGF ("Flash bank # %d:\n"
-		"\tManuf. ID @ 0x%08lX: 0x%08lX\n"
-		"\tDevice ID @ 0x%08lX: 0x%08lX\n",
-		i,
-		(ulong)(&addr[0]), addr[0],
-		(ulong)(&addr[2]), addr[2]);
+		} else if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT)
+			 && (addr[2] == addr[3])
+			 && (addr[2] == INTEL_ID_28F160C3T)) {
 
+			flash_info[i].flash_id =
+				(FLASH_MAN_INTEL & FLASH_VENDMASK) |
+				(INTEL_ID_28F160C3T & FLASH_TYPEMASK);
 
-	if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) &&
-	    (addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3T))
-	{
-
-	    flash_info[i].flash_id = (FLASH_MAN_INTEL & FLASH_VENDMASK) |
-				     (INTEL_ID_28F160F3T & FLASH_TYPEMASK);
-
-	} else {
-	    flash_info[i].flash_id = FLASH_UNKNOWN;
-	    addr[0] = 0xFFFFFFFF;
-	    goto Done;
-	}
-
-	DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id);
-
-	addr[0] = 0xFFFFFFFF;
-
-	flash_info[i].size = FLASH_BANK_SIZE;
-	flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-	memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
-	for (j = 0; j < flash_info[i].sector_count; j++) {
-		if (j > 30) {
-			flash_info[i].start[j] = CFG_FLASH_BASE +
-						 i * FLASH_BANK_SIZE +
-						 (MAIN_SECT_SIZE * 31) + (j - 31) * PARAM_SECT_SIZE;
 		} else {
-			flash_info[i].start[j] = CFG_FLASH_BASE +
-						 i * FLASH_BANK_SIZE +
-						 j * MAIN_SECT_SIZE;
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+			addr[0] = 0xFFFFFFFF;
+			goto Done;
 		}
-	}
-	size += flash_info[i].size;
-    }
 
-    /* Protect monitor and environment sectors
-     */
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+		DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id);
+
+		addr[0] = 0xFFFFFFFF;
+
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			if (j > 30) {
+				flash_info[i].start[j] = CFG_FLASH_BASE +
+					i * FLASH_BANK_SIZE +
+					(MAIN_SECT_SIZE * 31) + (j -
+								 31) *
+					PARAM_SECT_SIZE;
+			} else {
+				flash_info[i].start[j] = CFG_FLASH_BASE +
+					i * FLASH_BANK_SIZE +
+					j * MAIN_SECT_SIZE;
+			}
+		}
+
+		/* unlock sectors, if 160C3T */
+
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			tmpaddr = (vu_long *) flash_info[i].start[j];
+
+			if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
+			    (INTEL_ID_28F160C3T & FLASH_TYPEMASK)) {
+				tmpaddr[0] = 0x00600060;
+				tmpaddr[0] = 0x00D000D0;
+				tmpaddr[1] = 0x00600060;
+				tmpaddr[1] = 0x00D000D0;
+			}
+		}
+
+		size += flash_info[i].size;
+
+		addr[0] = 0x00FF00FF;
+		addr[1] = 0x00FF00FF;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE
-    flash_protect(FLAG_PROTECT_SET,
-	      CFG_MONITOR_BASE,
-	      CFG_MONITOR_BASE + monitor_flash_len - 1,
-	      &flash_info[1]);
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_MONITOR_BASE,
+		       CFG_MONITOR_BASE + monitor_flash_len - 1,
+		       &flash_info[1]);
 #else
-    flash_protect(FLAG_PROTECT_SET,
-	      CFG_MONITOR_BASE,
-	      CFG_MONITOR_BASE + monitor_flash_len - 1,
-	      &flash_info[0]);
-#endif
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_MONITOR_BASE,
+		       CFG_MONITOR_BASE + monitor_flash_len - 1,
+		       &flash_info[0]);
 #endif
 
 #if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
 #if CFG_ENV_ADDR >= CFG_FLASH_BASE + FLASH_BANK_SIZE
-    flash_protect(FLAG_PROTECT_SET,
-	      CFG_ENV_ADDR,
-	      CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
-	      &flash_info[1]);
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[1]);
 #else
-    flash_protect(FLAG_PROTECT_SET,
-	      CFG_ENV_ADDR,
-	      CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
-	      &flash_info[0]);
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
 #endif
 #endif
 
 Done:
-    return size;
+	return size;
 }
 
 /*-----------------------------------------------------------------------
@@ -179,6 +209,11 @@ void flash_print_info (flash_info_t * info)
 	case (INTEL_ID_28F160F3T & FLASH_TYPEMASK):
 		printf ("28F160F3T (16Mbit)\n");
 		break;
+
+	case (INTEL_ID_28F160C3T & FLASH_TYPEMASK):
+		printf ("28F160C3T (16Mbit)\n");
+		break;
+
 	default:
 		printf ("Unknown Chip Type 0x%04x\n", i);
 		goto Done;
@@ -186,7 +221,7 @@ void flash_print_info (flash_info_t * info)
 	}
 
 	printf ("  Size: %ld MB in %d Sectors\n",
-			info->size >> 20, info->sector_count);
+		info->size >> 20, info->sector_count);
 
 	printf ("  Sector Start Addresses:");
 	for (i = 0; i < info->sector_count; i++) {
@@ -194,7 +229,7 @@ void flash_print_info (flash_info_t * info)
 			printf ("\n   ");
 		}
 		printf (" %08lX%s", info->start[i],
-				info->protect[i] ? " (RO)" : "     ");
+			info->protect[i] ? " (RO)" : "     ");
 	}
 	printf ("\n");
 
@@ -205,7 +240,7 @@ Done:
 /*-----------------------------------------------------------------------
  */
 
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
+int flash_erase (flash_info_t * info, int s_first, int s_last)
 {
 	int flag, prot, sect;
 	ulong start, now, last;
@@ -229,33 +264,32 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 	}
 
 	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
+	for (sect = s_first; sect <= s_last; ++sect) {
 		if (info->protect[sect]) {
 			prot++;
 		}
 	}
 
 	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
 	} else {
 		printf ("\n");
 	}
 
 	start = get_timer (0);
-	last  = start;
+	last = start;
 	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last; sect++) {
+	for (sect = s_first; sect <= s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
-			vu_long *addr = (vu_long *)(info->start[sect]);
+			vu_long *addr = (vu_long *) (info->start[sect]);
 
 			DEBUGF ("Erase sect %d @ 0x%08lX\n",
-				sect, (ulong)addr);
+				sect, (ulong) addr);
 
 			/* Disable interrupts which might cause a timeout
 			 * here.
 			 */
-			flag = disable_interrupts();
+			flag = disable_interrupts ();
 
 			addr[0] = 0x00500050;	/* clear status register */
 			addr[0] = 0x00200020;	/* erase setup */
@@ -267,23 +301,23 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 
 			/* re-enable interrupts if necessary */
 			if (flag)
-				enable_interrupts();
+				enable_interrupts ();
 
 			/* wait at least 80us - let's wait 1 ms */
 			udelay (1000);
 
 			while (((addr[0] & 0x00800080) != 0x00800080) ||
-			       ((addr[1] & 0x00800080) != 0x00800080) ) {
-				if ((now=get_timer(start)) >
-					   CFG_FLASH_ERASE_TOUT) {
+			       ((addr[1] & 0x00800080) != 0x00800080)) {
+				if ((now = get_timer (start)) >
+				    CFG_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
-					addr[0] = 0x00B000B0; /* suspend erase */
-					addr[0] = 0x00FF00FF; /* to read mode  */
+					addr[0] = 0x00B000B0;	/* suspend erase */
+					addr[0] = 0x00FF00FF;	/* to read mode  */
 					return 1;
 				}
 
 				/* show that we're waiting */
-				if ((now - last) > 1000) {  /* every second  */
+				if ((now - last) > 1000) {	/* every second  */
 					putc ('.');
 					last = now;
 				}
@@ -306,7 +340,7 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 
 #define	FLASH_WIDTH	8	/* flash bus width in bytes */
 
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 {
 	ulong wp, cp, msr;
 	int l, rc, i;
@@ -315,16 +349,16 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	ulong *datal = &data[1];
 
 	DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n",
-		addr, (ulong)src, cnt);
+		addr, (ulong) src, cnt);
 
 	if (info->flash_id == FLASH_UNKNOWN) {
 		return 4;
 	}
 
-	msr = get_msr();
-	set_msr(msr | MSR_FP);
+	msr = get_msr ();
+	set_msr (msr | MSR_FP);
 
-	wp = (addr & ~(FLASH_WIDTH-1));	/* get lower aligned address */
+	wp = (addr & ~(FLASH_WIDTH - 1));	/* get lower aligned address */
 
 	/*
 	 * handle unaligned start bytes
@@ -335,39 +369,35 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 		for (i = 0, cp = wp; i < l; i++, cp++) {
 			if (i >= 4) {
 				*datah = (*datah << 8) |
-						((*datal & 0xFF000000) >> 24);
+					((*datal & 0xFF000000) >> 24);
 			}
 
-			*datal = (*datal << 8) | (*(uchar *)cp);
+			*datal = (*datal << 8) | (*(uchar *) cp);
 		}
 		for (; i < FLASH_WIDTH && cnt > 0; ++i) {
-			char tmp;
-
-			tmp = *src;
-
-			src++;
+			char tmp = *src++;
 
 			if (i >= 4) {
 				*datah = (*datah << 8) |
-						((*datal & 0xFF000000) >> 24);
+					((*datal & 0xFF000000) >> 24);
 			}
 
 			*datal = (*datal << 8) | tmp;
-
-			--cnt; ++cp;
+			--cnt;
+			++cp;
 		}
 
 		for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) {
 			if (i >= 4) {
 				*datah = (*datah << 8) |
-						((*datal & 0xFF000000) >> 24);
+					((*datal & 0xFF000000) >> 24);
 			}
 
-			*datal = (*datah << 8) | (*(uchar *)cp);
+			*datal = (*datah << 8) | (*(uchar *) cp);
 		}
 
-		if ((rc = write_data(info, wp, data)) != 0) {
-			set_msr(msr);
+		if ((rc = write_data (info, wp, data)) != 0) {
+			set_msr (msr);
 			return (rc);
 		}
 
@@ -378,19 +408,19 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	 * handle FLASH_WIDTH aligned part
 	 */
 	while (cnt >= FLASH_WIDTH) {
-		*datah = *(ulong *)src;
-		*datal = *(ulong *)(src + 4);
-		if ((rc = write_data(info, wp, data)) != 0) {
-			set_msr(msr);
+		*datah = *(ulong *) src;
+		*datal = *(ulong *) (src + 4);
+		if ((rc = write_data (info, wp, data)) != 0) {
+			set_msr (msr);
 			return (rc);
 		}
-		wp  += FLASH_WIDTH;
+		wp += FLASH_WIDTH;
 		cnt -= FLASH_WIDTH;
 		src += FLASH_WIDTH;
 	}
 
 	if (cnt == 0) {
-		set_msr(msr);
+		set_msr (msr);
 		return (0);
 	}
 
@@ -399,31 +429,28 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	 */
 	*datah = *datal = 0;
 	for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) {
-		char tmp;
-
-		tmp = *src;
-
-		src++;
+		char tmp = *src++;
 
 		if (i >= 4) {
-			*datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
+			*datah = (*datah << 8) | ((*datal & 0xFF000000) >>
+						  24);
 		}
 
 		*datal = (*datal << 8) | tmp;
-
 		--cnt;
 	}
 
 	for (; i < FLASH_WIDTH; ++i, ++cp) {
 		if (i >= 4) {
-			*datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
+			*datah = (*datah << 8) | ((*datal & 0xFF000000) >>
+						  24);
 		}
 
-		*datal = (*datal << 8) | (*(uchar *)cp);
+		*datal = (*datal << 8) | (*(uchar *) cp);
 	}
 
-	rc = write_data(info, wp, data);
-	set_msr(msr);
+	rc = write_data (info, wp, data);
+	set_msr (msr);
 
 	return (rc);
 }
@@ -434,32 +461,32 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
  * 1 - write timeout
  * 2 - Flash not erased
  */
-static int write_data (flash_info_t *info, ulong dest, ulong *data)
+static int write_data (flash_info_t * info, ulong dest, ulong * data)
 {
-	vu_long *addr = (vu_long *)dest;
+	vu_long *addr = (vu_long *) dest;
 	ulong start;
 	int flag;
 
 	/* Check if Flash is (sufficiently) erased */
 	if (((addr[0] & data[0]) != data[0]) ||
-	    ((addr[1] & data[1]) != data[1]) ) {
+	    ((addr[1] & data[1]) != data[1])) {
 		return (2);
 	}
 	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
+	flag = disable_interrupts ();
 
-	addr[0] = 0x00400040;		/* write setup */
-	write_via_fpu(addr, data);
+	addr[0] = 0x00400040;	/* write setup */
+	write_via_fpu (addr, data);
 
 	/* re-enable interrupts if necessary */
 	if (flag)
-		enable_interrupts();
+		enable_interrupts ();
 
 	start = get_timer (0);
 
 	while (((addr[0] & 0x00800080) != 0x00800080) ||
-	       ((addr[1] & 0x00800080) != 0x00800080) ) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	       ((addr[1] & 0x00800080) != 0x00800080)) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
 			addr[0] = 0x00FF00FF;	/* restore read mode */
 			return (1);
 		}
@@ -472,22 +499,24 @@ static int write_data (flash_info_t *info, ulong dest, ulong *data)
 
 /*-----------------------------------------------------------------------
  */
-static void write_via_fpu(vu_long *addr, ulong *data)
+static void write_via_fpu (vu_long * addr, ulong * data)
 {
-	__asm__ __volatile__ ("lfd  1, 0(%0)" : : "r" (data));
-	__asm__ __volatile__ ("stfd 1, 0(%0)" : : "r" (addr));
+	__asm__ __volatile__ ("lfd  1, 0(%0)"::"r" (data));
+	__asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr));
 }
+
 /*-----------------------------------------------------------------------
  */
-static __inline__ unsigned long get_msr(void)
+static __inline__ unsigned long get_msr (void)
 {
-    unsigned long msr;
+	unsigned long msr;
 
-    __asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :);
-    return msr;
+	__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
+
+	return msr;
 }
 
-static __inline__ void set_msr(unsigned long msr)
+static __inline__ void set_msr (unsigned long msr)
 {
-    __asm__ __volatile__ ("mtmsr %0" : : "r" (msr));
+	__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
 }

board/cpu86/flash.c

@@ -41,10 +41,10 @@ ulong flash_int_get_size (volatile unsigned long *baseaddr,
 	info->sector_count = info->size = 0;
 	info->flash_id = FLASH_UNKNOWN;
 
-	/* Write query command sequence and test FLASH answer
+	/* Write identify command sequence and test FLASH answer
 	 */
-	baseaddr[0] = 0x00980098;
-	baseaddr[1] = 0x00980098;
+	baseaddr[0] = 0x00900090;
+	baseaddr[1] = 0x00900090;
 
 	flashtest_h = baseaddr[0];	/* manufacturer ID	*/
 	flashtest_l = baseaddr[1];

board/csb272/Makefile

@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+#OBJS	= $(BOARD).o flash.o
+#OBJS	= $(BOARD).o strataflash.o
+OBJS	= $(BOARD).o
+
+SOBJS	= init.o
+
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/csb272/config.mk

@@ -0,0 +1,36 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004
+# Tolunay Orkun, NextIO Inc., torkun@nextio.com.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Cogent CSB272 board
+#
+
+LDFLAGS += $(LINKER_UNDEFS)
+
+TEXT_BASE := 0xFFFC0000
+#TEXT_BASE := 0x00100000
+
+PLATFORM_RELFLAGS := $(PLATFORM_RELFLAGS)

board/csb272/csb272.c

@@ -0,0 +1,173 @@
+/*
+ * (C) Copyright 2004
+ * Tolunay Orkun, Nextio Inc., torkun@nextio.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <405gp_enet.h>
+
+/*
+ * Configuration data for AMIS FS6377-01 Programmable 3-PLL Clock Generator
+ *
+ * CLKA output => Epson LCD Controller
+ * CLKB output => Not Connected
+ * CLKC output => Ethernet
+ * CLKD output => UART external clock
+ *
+ * Note: these values are obtained from device after init by micromonitor
+*/
+uchar pll_fs6377_regs[16] = {
+	0x28, 0xef, 0x53, 0x03, 0x4b, 0x80, 0x32, 0x80,
+	0x94, 0x32, 0x80, 0xd4, 0x56, 0xf6, 0xf6, 0xe0 };
+
+/*
+ * pll_init: Initialize AMIS IC FS6377-01 PLL
+ *
+ * PLL supplies Epson LCD Clock, Ethernet Clock and UART external clock
+ *
+ */
+int pll_init(void)
+{
+	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+	return  i2c_write(CFG_I2C_PLL_ADDR, 0, 1,
+		(uchar *) pll_fs6377_regs, sizeof(pll_fs6377_regs));
+}
+
+/*
+ * board_early_init_f: do early board initialization
+ *
+ */
+int board_early_init_f(void)
+{
+	/* initialize PLL so UART, LCD, Ethernet clocked at correctly */
+	(void) get_clocks();
+	pll_init();
+
+   /*-------------------------------------------------------------------------+
+   | Interrupt controller setup for the Walnut board.
+   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
+   |       IRQ 16    405GP internally generated; active low; level sensitive
+   |       IRQ 17-24 RESERVED
+   |       IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
+   |       IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
+   |       IRQ 27 (EXT IRQ 2) Not Used
+   |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
+   |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+   |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
+   |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
+   | Note for Walnut board:
+   |       An interrupt taken for the FPGA (IRQ 25) indicates that either
+   |       the Mouse, Keyboard, IRDA, or External Expansion caused the
+   |       interrupt. The FPGA must be read to determine which device
+   |       caused the interrupt. The default setting of the FPGA clears
+   |
+   +-------------------------------------------------------------------------*/
+
+	mtdcr (uicsr, 0xFFFFFFFF);   /* clear all ints */
+	mtdcr (uicer, 0x00000000);   /* disable all ints */
+	mtdcr (uiccr, 0x00000000);   /* set all to be non-critical */
+	mtdcr (uicpr, 0xFFFFFF83);   /* set int polarities */
+	mtdcr (uictr, 0x10000000);   /* set int trigger levels */
+	mtdcr (uicvcr, 0x00000001);  /* set vect base=0,INT0 highest priority */
+	mtdcr (uicsr, 0xFFFFFFFF);   /* clear all ints */
+
+	mtebc (epcr, 0xa8400000);   /* EBC always driven */
+
+	return 0; /* success */
+}
+
+/*
+ * checkboard: identify/verify the board we are running
+ *
+ * Remark: we just assume it is correct board here!
+ *
+ */
+int checkboard(void)
+{
+	printf("BOARD: Cogent CSB272\n");
+
+	return 0; /* success */
+}
+
+/*
+ * initram: Determine the size of mounted DRAM
+ *
+ * Size is determined by reading SDRAM configuration registers as
+ * configured by initialization code
+ *
+ */
+long initdram (int board_type)
+{
+	ulong tot_size;
+	ulong bank_size;
+	ulong tmp;
+
+	tot_size = 0;
+
+	mtdcr (memcfga, mem_mb0cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	mtdcr (memcfga, mem_mb1cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	mtdcr (memcfga, mem_mb2cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	mtdcr (memcfga, mem_mb3cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	return tot_size;
+}
+
+/*
+ * last_stage_init: final configurations (such as PHY etc)
+ *
+ */
+int last_stage_init(void)
+{
+	/* initialize the PHY */
+	miiphy_reset(CONFIG_PHY_ADDR);
+	miiphy_write(CONFIG_PHY_ADDR, PHY_BMCR,
+			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);	/* AUTO neg */
+	miiphy_write(CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08);	/* LEDs     */
+
+	return 0; /* success */
+}

board/csb272/init.S

@@ -0,0 +1,216 @@
+/******************************************************************************
+ *
+ *	 This source code has been made available to you by IBM on an AS-IS
+ *	 basis.	 Anyone receiving this source is licensed under IBM
+ *	 copyrights to use it in any way he or she deems fit, including
+ *	 copying it, modifying it, compiling it, and redistributing it either
+ *	 with or without modifications.	 No license under IBM patents or
+ *	 patent applications is to be implied by the copyright license.
+ *
+ *	 Any user of this software should understand that IBM cannot provide
+ *	 technical support for this software and will not be responsible for
+ *	 any consequences resulting from the use of this software.
+ *
+ *	 Any person who transfers this source code or any derivative work
+ *	 must include the IBM copyright notice, this paragraph, and the
+ *	 preceding two paragraphs in the transferred software.
+ *
+ *	 COPYRIGHT   I B M   CORPORATION 1995
+ *	 LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+ *
+ *****************************************************************************/
+#include <config.h>
+#include <ppc4xx.h>
+
+#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#define LI32(reg,val) \
+	addis   reg,0,val@h;\
+	ori     reg,reg,val@l
+
+#define WDCR_EBC(reg,val) \
+	addi    r4,0,reg;\
+	mtdcr   ebccfga,r4;\
+	addis   r4,0,val@h;\
+	ori     r4,r4,val@l;\
+	mtdcr   ebccfgd,r4
+
+#define WDCR_SDRAM(reg,val) \
+	addi    r4,0,reg;\
+	mtdcr   memcfga,r4;\
+	addis   r4,0,val@h;\
+	ori     r4,r4,val@l;\
+	mtdcr   memcfgd,r4
+
+/******************************************************************************
+ * Function:	ext_bus_cntlr_init
+ *
+ * Description:	Configures EBC Controller and a few basic chip selects.
+ *
+ *		CS0 is setup to get the Boot Flash out of the addresss range
+ *		so that we may setup a stack.  CS7 is setup so that we can
+ *		access and reset the hardware watchdog.
+ *
+ *		IMPORTANT: For pass1 this code must run from
+ *		cache since you can not reliably change a peripheral banks
+ *		timing register (pbxap) while running code from that bank.
+ *		For ex., since we are running from ROM on bank 0, we can NOT
+ *		execute the code that modifies bank 0 timings from ROM, so
+ *		we run it from cache.
+ *
+ * Notes:	Does NOT use the stack.
+ *****************************************************************************/
+	.section ".text"
+	.align	2
+	.globl	ext_bus_cntlr_init
+	.type	ext_bus_cntlr_init, @function
+ext_bus_cntlr_init:
+	mflr	r0
+	/********************************************************************
+	 * Prefetch entire ext_bus_cntrl_init function into the icache.
+	 * This is necessary because we are going to change the same CS we
+	 * are executing from.  Otherwise a CPU lockup may occur.
+	 *******************************************************************/
+	bl	..getAddr
+..getAddr:
+	mflr	r3			/* get address of ..getAddr */
+
+	/* Calculate number of cache lines for this function */
+	addi	r4, 0, (((.Lfe0 - ..getAddr) / CFG_CACHELINE_SIZE) + 2)
+	mtctr	r4
+..ebcloop:
+	icbt	r0, r3			/* prefetch cache line for addr in r3*/
+	addi	r3, r3, CFG_CACHELINE_SIZE /* move to next cache line */
+	bdnz	..ebcloop		/* continue for $CTR cache lines */
+
+	/********************************************************************
+	 * Delay to ensure all accesses to ROM are complete before changing
+	 * bank 0 timings. 200usec should be enough.
+	 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
+	 *******************************************************************/
+	addis	r3, 0, 0x0
+	ori	r3, r3, 0xA000		/* wait 200us from reset */
+	mtctr	r3
+..spinlp:
+	bdnz	..spinlp		/* spin loop */
+
+	/********************************************************************
+	 * SETUP CPC0_CR0
+	 *******************************************************************/
+	LI32(r4, 0x007000c0)
+	mtdcr	cntrl0, r4
+
+	/********************************************************************
+	 * Setup CPC0_CR1: Change PCIINT signal to PerWE
+	 *******************************************************************/
+	mfdcr	r4, cntrl1
+	ori	r4, r4, 0x4000
+	mtdcr	cntrl1, r4
+
+	/********************************************************************
+	 * Setup External Bus Controller (EBC).
+	 *******************************************************************/
+	WDCR_EBC(epcr, 0xd84c0000)
+	/********************************************************************
+	 * Memory Bank 0 (Intel 28F128J3 Flash) initialization
+	 *******************************************************************/
+	/*WDCR_EBC(pb0ap, 0x02869200)*/
+	WDCR_EBC(pb0ap, 0x07869200)
+	WDCR_EBC(pb0cr, 0xfe0bc000)
+	/********************************************************************
+	 * Memory Bank 1 (Holtek HT6542B PS/2) initialization
+	 *******************************************************************/
+	WDCR_EBC(pb1ap, 0x1f869200)
+	WDCR_EBC(pb1cr, 0xf0818000)
+	/********************************************************************
+	 * Memory Bank 2 (Epson S1D13506) initialization
+	 *******************************************************************/
+	WDCR_EBC(pb2ap, 0x05860300)
+	WDCR_EBC(pb2cr, 0xf045a000)
+	/********************************************************************
+	 * Memory Bank 3 (Philips SJA1000 CAN Controllers) initialization
+	 *******************************************************************/
+	WDCR_EBC(pb3ap, 0x0387d200)
+	WDCR_EBC(pb3cr, 0xf021c000)
+	/********************************************************************
+	 * Memory Bank 4-7 (Unused) initialization
+	 *******************************************************************/
+	WDCR_EBC(pb4ap, 0)
+	WDCR_EBC(pb4cr, 0)
+	WDCR_EBC(pb5ap, 0)
+	WDCR_EBC(pb5cr, 0)
+	WDCR_EBC(pb6ap, 0)
+	WDCR_EBC(pb6cr, 0)
+	WDCR_EBC(pb7ap, 0)
+	WDCR_EBC(pb7cr, 0)
+
+	/* We are all done */
+	mtlr	r0			/* Restore link register */
+	blr				/* Return to calling function */
+.Lfe0:	.size	ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
+/* end ext_bus_cntlr_init() */
+
+/******************************************************************************
+ * Function:	sdram_init
+ *
+ * Description:	Configures SDRAM memory banks.
+ *
+ * Notes:	Does NOT use the stack.
+ *****************************************************************************/
+	.section ".text"
+	.align	2
+	.globl	sdram_init
+	.type	sdram_init, @function
+sdram_init:
+
+	/*
+	 * Disable memory controller to allow
+	 * values to be changed.
+	 */
+	WDCR_SDRAM(mem_mcopt1, 0x00000000)
+
+	/*
+	 * Configure Memory Banks
+	 */
+	WDCR_SDRAM(mem_mb0cf, 0x00084001)
+	WDCR_SDRAM(mem_mb1cf, 0x00000000)
+	WDCR_SDRAM(mem_mb2cf, 0x00000000)
+	WDCR_SDRAM(mem_mb3cf, 0x00000000)
+
+	/*
+	 * Set up SDTR1 (SDRAM Timing Register)
+	 */
+	WDCR_SDRAM(mem_sdtr1, 0x00854009)
+
+	/*
+	 * Set RTR (Refresh Timing Register)
+	 */
+	WDCR_SDRAM(mem_rtr,   0x10000000)
+	/* WDCR_SDRAM(mem_rtr,   0x05f00000) */
+
+	/********************************************************************
+	 * Delay to ensure 200usec have elapsed since reset. Assume worst
+	 * case that the core is running 200Mhz:
+	 *	  200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
+	 *******************************************************************/
+	addis   r3, 0, 0x0000
+	ori     r3, r3, 0xA000		/* Wait >200us from reset */
+	mtctr   r3
+..spinlp2:
+	bdnz    ..spinlp2		/* spin loop */
+
+	/********************************************************************
+	 * Set memory controller options reg, MCOPT1.
+	 *******************************************************************/
+	WDCR_SDRAM(mem_mcopt1,0x80800000)
+
+..sdri_done:
+	blr				/* Return to calling function */
+.Lfe1:	.size	sdram_init,.Lfe1-sdram_init
+/* end sdram_init() */

board/csb272/u-boot.lds

@@ -0,0 +1,151 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/csb272/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/405gp_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    lib_ppc/extable.o	(.text)
+    lib_ppc/board.o	(.text)
+    lib_generic/zlib.o	(.text)
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/csb472/Makefile

@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+#OBJS	= $(BOARD).o flash.o
+#OBJS	= $(BOARD).o strataflash.o
+OBJS	= $(BOARD).o
+
+SOBJS	= init.o
+
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/csb472/config.mk

@@ -0,0 +1,36 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004
+# Tolunay Orkun, NextIO Inc., torkun@nextio.com.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Cogent CSB472 board
+#
+
+LDFLAGS += $(LINKER_UNDEFS)
+
+TEXT_BASE := 0xFFFC0000
+#TEXT_BASE := 0x00100000
+
+PLATFORM_RELFLAGS := $(PLATFORM_RELFLAGS)

board/csb472/csb472.c

@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2004
+ * Tolunay Orkun, Nextio Inc., torkun@nextio.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <405gp_enet.h>
+
+/*
+ * board_early_init_f: do early board initialization
+ *
+ */
+int board_early_init_f(void)
+{
+   /*-------------------------------------------------------------------------+
+   | Interrupt controller setup for the Walnut board.
+   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
+   |       IRQ 16    405GP internally generated; active low; level sensitive
+   |       IRQ 17-24 RESERVED
+   |       IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
+   |       IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
+   |       IRQ 27 (EXT IRQ 2) Not Used
+   |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
+   |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+   |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
+   |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
+   | Note for Walnut board:
+   |       An interrupt taken for the FPGA (IRQ 25) indicates that either
+   |       the Mouse, Keyboard, IRDA, or External Expansion caused the
+   |       interrupt. The FPGA must be read to determine which device
+   |       caused the interrupt. The default setting of the FPGA clears
+   |
+   +-------------------------------------------------------------------------*/
+
+	mtdcr (uicsr, 0xFFFFFFFF);   /* clear all ints */
+	mtdcr (uicer, 0x00000000);   /* disable all ints */
+	mtdcr (uiccr, 0x00000000);   /* set all to be non-critical */
+	mtdcr (uicpr, 0xFFFFFF83);   /* set int polarities */
+	mtdcr (uictr, 0x10000000);   /* set int trigger levels */
+	mtdcr (uicvcr, 0x00000001);  /* set vect base=0,INT0 highest priority */
+	mtdcr (uicsr, 0xFFFFFFFF);   /* clear all ints */
+
+	mtebc (epcr, 0xa8400000);   /* EBC always driven */
+
+	return 0; /* success */
+}
+
+/*
+ * checkboard: identify/verify the board we are running
+ *
+ * Remark: we just assume it is correct board here!
+ *
+ */
+int checkboard(void)
+{
+	printf("BOARD: Cogent CSB472\n");
+
+	return 0; /* success */
+}
+
+/*
+ * initram: Determine the size of mounted DRAM
+ *
+ * Size is determined by reading SDRAM configuration registers as
+ * configured by initialization code
+ *
+ */
+long initdram (int board_type)
+{
+	ulong tot_size;
+	ulong bank_size;
+	ulong tmp;
+
+	tot_size = 0;
+
+	mtdcr (memcfga, mem_mb0cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	mtdcr (memcfga, mem_mb1cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	mtdcr (memcfga, mem_mb2cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	mtdcr (memcfga, mem_mb3cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	return tot_size;
+}
+
+/*
+ * last_stage_init: final configurations (such as PHY etc)
+ *
+ */
+int last_stage_init(void)
+{
+	/* initialize the PHY */
+	miiphy_reset(CONFIG_PHY_ADDR);
+	miiphy_write(CONFIG_PHY_ADDR, PHY_BMCR,
+			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);	/* AUTO neg */
+	miiphy_write(CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08);	/* LEDs     */
+
+	return 0; /* success */
+}

board/csb472/init.S

@@ -0,0 +1,212 @@
+/******************************************************************************
+ *
+ *	 This source code has been made available to you by IBM on an AS-IS
+ *	 basis.	 Anyone receiving this source is licensed under IBM
+ *	 copyrights to use it in any way he or she deems fit, including
+ *	 copying it, modifying it, compiling it, and redistributing it either
+ *	 with or without modifications.	 No license under IBM patents or
+ *	 patent applications is to be implied by the copyright license.
+ *
+ *	 Any user of this software should understand that IBM cannot provide
+ *	 technical support for this software and will not be responsible for
+ *	 any consequences resulting from the use of this software.
+ *
+ *	 Any person who transfers this source code or any derivative work
+ *	 must include the IBM copyright notice, this paragraph, and the
+ *	 preceding two paragraphs in the transferred software.
+ *
+ *	 COPYRIGHT   I B M   CORPORATION 1995
+ *	 LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+ *
+ *****************************************************************************/
+#include <config.h>
+#include <ppc4xx.h>
+
+#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#define LI32(reg,val) \
+	addis   reg,0,val@h;\
+	ori     reg,reg,val@l
+
+#define WDCR_EBC(reg,val) \
+	addi    r4,0,reg;\
+	mtdcr   ebccfga,r4;\
+	addis   r4,0,val@h;\
+	ori     r4,r4,val@l;\
+	mtdcr   ebccfgd,r4
+
+#define WDCR_SDRAM(reg,val) \
+	addi    r4,0,reg;\
+	mtdcr   memcfga,r4;\
+	addis   r4,0,val@h;\
+	ori     r4,r4,val@l;\
+	mtdcr   memcfgd,r4
+
+/******************************************************************************
+ * Function:	ext_bus_cntlr_init
+ *
+ * Description:	Configures EBC Controller and a few basic chip selects.
+ *
+ *		CS0 is setup to get the Boot Flash out of the addresss range
+ *		so that we may setup a stack.  CS7 is setup so that we can
+ *		access and reset the hardware watchdog.
+ *
+ *		IMPORTANT: For pass1 this code must run from
+ *		cache since you can not reliably change a peripheral banks
+ *		timing register (pbxap) while running code from that bank.
+ *		For ex., since we are running from ROM on bank 0, we can NOT
+ *		execute the code that modifies bank 0 timings from ROM, so
+ *		we run it from cache.
+ *
+ * Notes:	Does NOT use the stack.
+ *****************************************************************************/
+	.section ".text"
+	.align	2
+	.globl	ext_bus_cntlr_init
+	.type	ext_bus_cntlr_init, @function
+ext_bus_cntlr_init:
+	mflr	r0
+	/********************************************************************
+	 * Prefetch entire ext_bus_cntrl_init function into the icache.
+	 * This is necessary because we are going to change the same CS we
+	 * are executing from.  Otherwise a CPU lockup may occur.
+	 *******************************************************************/
+	bl	..getAddr
+..getAddr:
+	mflr	r3			/* get address of ..getAddr */
+
+	/* Calculate number of cache lines for this function */
+	addi	r4, 0, (((.Lfe0 - ..getAddr) / CFG_CACHELINE_SIZE) + 2)
+	mtctr	r4
+..ebcloop:
+	icbt	r0, r3			/* prefetch cache line for addr in r3*/
+	addi	r3, r3, CFG_CACHELINE_SIZE /* move to next cache line */
+	bdnz	..ebcloop		/* continue for $CTR cache lines */
+
+	/********************************************************************
+	 * Delay to ensure all accesses to ROM are complete before changing
+	 * bank 0 timings. 200usec should be enough.
+	 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
+	 *******************************************************************/
+	addis	r3, 0, 0x0
+	ori	r3, r3, 0xA000		/* wait 200us from reset */
+	mtctr	r3
+..spinlp:
+	bdnz	..spinlp		/* spin loop */
+
+	/********************************************************************
+	 * SETUP CPC0_CR0
+	 *******************************************************************/
+	LI32(r4, 0x00c01030)
+	mtdcr	cntrl0, r4
+
+	/********************************************************************
+	 * Setup CPC0_CR1: Change PCIINT signal to PerWE
+	 *******************************************************************/
+	mfdcr	r4, cntrl1
+	ori	r4, r4, 0x4000
+	mtdcr	cntrl1, r4
+
+	/********************************************************************
+	 * Setup External Bus Controller (EBC).
+	 *******************************************************************/
+	WDCR_EBC(epcr, 0xd84c0000)
+	/********************************************************************
+	 * Memory Bank 0 (Intel 28F640J3 Flash) initialization
+	 *******************************************************************/
+	/*WDCR_EBC(pb0ap, 0x03055200)*/
+	/*WDCR_EBC(pb0ap, 0x04055200)*/
+	WDCR_EBC(pb0ap, 0x08055200)
+	WDCR_EBC(pb0cr, 0xff87a000)
+	/********************************************************************
+	 * Memory Bank 3 (Xilinx XC95144 CPLD) initialization
+	 *******************************************************************/
+	/*WDCR_EBC(pb3ap, 0x07869200)*/
+	WDCR_EBC(pb3ap, 0x04055200)
+	WDCR_EBC(pb3cr, 0xff01c000)
+	/********************************************************************
+	 * Memory Bank 1,2,4-7 (Unused) initialization
+	 *******************************************************************/
+	WDCR_EBC(pb1ap, 0)
+	WDCR_EBC(pb1cr, 0)
+	WDCR_EBC(pb2ap, 0)
+	WDCR_EBC(pb2cr, 0)
+	WDCR_EBC(pb4ap, 0)
+	WDCR_EBC(pb4cr, 0)
+	WDCR_EBC(pb5ap, 0)
+	WDCR_EBC(pb5cr, 0)
+	WDCR_EBC(pb6ap, 0)
+	WDCR_EBC(pb6cr, 0)
+	WDCR_EBC(pb7ap, 0)
+	WDCR_EBC(pb7cr, 0)
+
+	/* We are all done */
+	mtlr	r0			/* Restore link register */
+	blr				/* Return to calling function */
+.Lfe0:	.size	ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
+/* end ext_bus_cntlr_init() */
+
+/******************************************************************************
+ * Function:	sdram_init
+ *
+ * Description:	Configures SDRAM memory banks.
+ *
+ * Notes:	Does NOT use the stack.
+ *****************************************************************************/
+	.section ".text"
+	.align	2
+	.globl	sdram_init
+	.type	sdram_init, @function
+sdram_init:
+
+	/*
+	 * Disable memory controller to allow
+	 * values to be changed.
+	 */
+	WDCR_SDRAM(mem_mcopt1, 0x00000000)
+
+	/*
+	 * Configure Memory Banks
+	 */
+	WDCR_SDRAM(mem_mb0cf, 0x00062001)
+	WDCR_SDRAM(mem_mb1cf, 0x00000000)
+	WDCR_SDRAM(mem_mb2cf, 0x00000000)
+	WDCR_SDRAM(mem_mb3cf, 0x00000000)
+
+	/*
+	 * Set up SDTR1 (SDRAM Timing Register)
+	 */
+	WDCR_SDRAM(mem_sdtr1, 0x00854009)
+
+	/*
+	 * Set RTR (Refresh Timing Register)
+	 */
+	WDCR_SDRAM(mem_rtr,   0x10000000)
+	/* WDCR_SDRAM(mem_rtr,   0x05f00000) */
+
+	/********************************************************************
+	 * Delay to ensure 200usec have elapsed since reset. Assume worst
+	 * case that the core is running 200Mhz:
+	 *	  200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
+	 *******************************************************************/
+	addis   r3, 0, 0x0000
+	ori     r3, r3, 0xA000		/* Wait >200us from reset */
+	mtctr   r3
+..spinlp2:
+	bdnz    ..spinlp2		/* spin loop */
+
+	/********************************************************************
+	 * Set memory controller options reg, MCOPT1.
+	 *******************************************************************/
+	WDCR_SDRAM(mem_mcopt1,0x80800000)
+
+..sdri_done:
+	blr				/* Return to calling function */
+.Lfe1:	.size	sdram_init,.Lfe1-sdram_init
+/* end sdram_init() */

board/csb472/u-boot.lds

@@ -0,0 +1,151 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/csb472/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/405gp_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    lib_ppc/extable.o	(.text)
+    lib_ppc/board.o	(.text)
+    lib_generic/zlib.o	(.text)
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/dave/B2/B2.c

@@ -0,0 +1,128 @@
+/*
+ * (C) Copyright 2004
+ * DAVE Srl
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/hardware.h>
+
+/*
+ * Miscelaneous platform dependent initialization
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	u32 temp;
+
+	/* Configuration Port Control Register*/
+	/* Port A */
+	PCONA = 0x3ff;
+
+	/* Port B */
+	PCONB = 0xff;
+	PDATB = 0xFFFF;
+
+	/* Port C */
+	/*
+	PCONC = 0xff55ff15;
+	PDATC = 0x0;
+	PUPC = 0xffff;
+	*/
+
+	/* Port D */
+	/*
+	PCOND = 0xaaaa;
+	PUPD = 0xff;
+	*/
+
+	/* Port E */
+	PCONE = 0x0001aaa9;
+	PDATE = 0x0;
+	PUPE = 0xff;
+
+	/* Port F */
+	PCONF = 0x124955;
+	PDATF  = 0xff; /* B2-eth_reset tied high level */
+	/*
+	PUPF = 0x1e3;
+	*/
+
+	/* Port G */
+	PUPG = 0x1;
+	PCONG = 0x3; /*PG0= EINT0= ETH_INT prepared for linux kernel*/
+
+	INTMSK = 0x03fffeff;
+	INTCON = 0x05;
+
+    /*
+    	Configure chip ethernet interrupt as High level
+    	Port G EINT 0-7 EINT0 -> CHIP ETHERNET
+    */
+	temp = EXTINT;
+   	temp &= ~0x7;
+    temp |= 0x1; /*LEVEL_HIGH*/
+	EXTINT = temp;
+
+    /*
+    	Reset SMSC LAN91C96 chip
+    */
+    temp= PCONF;
+    temp |= 0x00000040;
+    PCONF = temp;
+
+	/* Reset high */
+    temp = PDATF;
+    temp |= (1 << 3);
+    PDATF = temp;
+
+    /* Short delay */
+    for (temp=0;temp<10;temp++)
+    {
+		/* NOP */
+    }
+
+    /* Reset low */
+    temp = PDATF;
+    temp &= ~(1 << 3);
+    PDATF = temp;
+
+	/* arch number MACH_TYPE_MBA44B0 */
+	gd->bd->bi_arch_number = 178;
+
+	/* location of boot parameters */
+	gd->bd->bi_boot_params = 0x0c000100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}

board/dave/B2/Makefile

@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2002
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= B2.o flash.o
+SOBJS	:= memsetup.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/dave/B2/config.mk

@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x0C100000
+
+PLATFORM_CPPFLAGS += -Uarm

board/dave/B2/flash.c

@@ -0,0 +1,76 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/hardware.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+#ifdef __DEBUG_START_FROM_SRAM__
+	return CFG_DUMMY_FLASH_SIZE;
+#else
+	unsigned long size_b0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (0, &flash_info[0]);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+#endif
+}

board/dave/B2/memsetup.S

@@ -0,0 +1,167 @@
+/*
+ * (C) Copyright 2004
+ * DAVE Srl
+ *
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
+ *
+ * memsetup-sa1110.S (blob): memory setup for various SA1110 architectures
+ * Modified By MATTO
+ *
+ * Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+/*
+ * Documentation:
+ * Intel Corporation, "Intel StrongARM SA-1110 Microprocessor
+ *     Advanced Developer's manual, December 1999
+ *
+ * Intel has a very hard to find SDRAM configurator on their web site:
+ *   http://appzone.intel.com/hcd/sa1110/memory/index.asp
+ *
+ * NOTE: This code assumes that an SA1110 CPU *always* uses SDRAM. This
+ * appears to be true, but it might be possible that somebody designs a
+ * board with mixed EDODRAM/SDRAM memory (which is a bad idea). -- Erik
+ *
+ * 04-10-2001:  SELETZ
+ * - separated memory config for multiple platform support
+ * - perform SA1110 Hardware Reset Procedure
+ *
+ */
+
+.equ    B0_Tacs,      0x0 /* 0clk */
+.equ    B0_Tcos,      0x0 /* 0clk */
+.equ    B0_Tacc,      0x4 /* 6clk */
+.equ    B0_Tcoh,      0x0 /* 0clk */
+.equ    B0_Tah,       0x0 /* 0clk */
+.equ    B0_Tacp,      0x0 /* 0clk */
+.equ    B0_PMC,       0x0 /* normal(1data) */
+/* Bank 1 parameter */
+.equ    B1_Tacs,      0x3 /* 4clk */
+.equ    B1_Tcos,      0x3 /* 4clk */
+.equ    B1_Tacc,      0x7 /* 14clkv */
+.equ    B1_Tcoh,      0x3 /* 4clk */
+.equ    B1_Tah,       0x3 /* 4clk */
+.equ    B1_Tacp,      0x3 /* 6clk */
+.equ    B1_PMC,       0x0 /* normal(1data) */
+
+/* Bank 2 parameter - LAN91C96 */
+.equ    B2_Tacs,      0x3 /* 4clk */
+.equ    B2_Tcos,      0x3 /* 4clk */
+.equ    B2_Tacc,      0x7 /* 14clk */
+.equ    B2_Tcoh,      0x3 /* 4clk */
+.equ    B2_Tah,       0x3 /* 4clk */
+.equ    B2_Tacp,      0x3 /* 6clk */
+.equ    B2_PMC,       0x0 /* normal(1data) */
+
+/* Bank 3 parameter */
+.equ    B3_Tacs,      0x3 /* 4clk */
+.equ    B3_Tcos,      0x3 /* 4clk */
+.equ    B3_Tacc,      0x7 /* 14clk */
+.equ    B3_Tcoh,      0x3 /* 4clk */
+.equ    B3_Tah,       0x3 /* 4clk */
+.equ    B3_Tacp,      0x3 /* 6clk */
+.equ    B3_PMC,       0x0 /* normal(1data) */
+
+/* Bank 4 parameter */
+.equ    B4_Tacs,      0x3 /* 4clk */
+.equ    B4_Tcos,      0x3 /* 4clk */
+.equ    B4_Tacc,      0x7 /* 14clk */
+.equ    B4_Tcoh,      0x3 /* 4clk */
+.equ    B4_Tah,       0x3 /* 4clk */
+.equ    B4_Tacp,      0x3 /* 6clk */
+.equ    B4_PMC,       0x0 /* normal(1data) */
+
+/* Bank 5 parameter */
+.equ    B5_Tacs,      0x3 /* 4clk */
+.equ    B5_Tcos,      0x3 /* 4clk */
+.equ    B5_Tacc,      0x7 /* 14clk */
+.equ    B5_Tcoh,      0x3 /* 4clk */
+.equ    B5_Tah,       0x3 /* 4clk */
+.equ    B5_Tacp,      0x3 /* 6clk */
+.equ    B5_PMC,       0x0 /* normal(1data) */
+
+/* Bank 6(if SROM) parameter */
+.equ    B6_Tacs,      0x3 /* 4clk */
+.equ    B6_Tcos,      0x3 /* 4clk */
+.equ    B6_Tacc,      0x7 /* 14clk */
+.equ    B6_Tcoh,      0x3 /* 4clk */
+.equ    B6_Tah,       0x3 /* 4clk */
+.equ    B6_Tacp,      0x3 /* 6clk */
+.equ    B6_PMC,       0x0 /* normal(1data) */
+
+/* Bank 7(if SROM) parameter */
+.equ    B7_Tacs,      0x3 /* 4clk */
+.equ    B7_Tcos,      0x3 /* 4clk */
+.equ    B7_Tacc,      0x7 /* 14clk */
+.equ    B7_Tcoh,      0x3 /* 4clk */
+.equ    B7_Tah,       0x3 /* 4clk */
+.equ    B7_Tacp,      0x3 /* 6clk */
+.equ    B7_PMC,       0x0 /* normal(1data) */
+
+/* Bank 6 parameter */
+.equ    B6_MT,        0x3 /* SDRAM */
+.equ    B6_Trcd,      0x0 /* 2clk */
+.equ    B6_SCAN,      0x0 /* 10bit */
+
+.equ    B7_MT,        0x3 /* SDRAM */
+.equ    B7_Trcd,      0x0 /* 2clk */
+.equ    B7_SCAN,      0x0 /* 10bit */
+
+
+/* REFRESH parameter */
+.equ    REFEN,        0x1 /* Refresh enable */
+.equ    TREFMD,       0x0 /* CBR(CAS before RAS)/Auto refresh */
+.equ    Trp,        0x0 /* 2clk */
+.equ    Trc,        0x3 /* 0x1=5clk 0x3=11clk*/
+.equ    Tchr,       0x0 /* 0x2=3clk 0x0=0clks  */
+.equ    REFCNT,       879
+
+MEMORY_CONFIG:
+  .long   0x12111900 /* Bank0 = OM[1:0] , Bank1-7 16bit, Bank2=Nowait,UB/LB*/
+  .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /*GCS0*/
+  .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /*GCS1*/
+  .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /*GCS2*/
+  .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /*GCS3*/
+  .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /*GCS4*/
+  .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /*GCS5*/
+  .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))  /*GCS6*/
+  .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))  /*GCS7*/
+  .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)  /*REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019*/
+  .word 0x17      /*SCLK power down mode, BANKSIZE 16M/16M*/
+  .word 0x20      /*MRSR6 CL=2clk*/
+  .word 0x20      /*MRSR7*/
+
+
+.globl memsetup
+memsetup:
+
+	/*
+		the next instruction fail due memory relocation...
+		we'll find the right MEMORY_CONFIG address with the next 3 lines...
+	*/
+	/*ldr r0, =MEMORY_CONFIG*/
+	mov r0, pc
+	ldr r1, =(0x38+4)
+	sub r0, r0, r1
+
+	ldmia r0, {r1-r13}
+	ldr   r0, =0x01c80000
+	stmia r0, {r1-r13}
+	mov pc, lr

board/dave/B2/u-boot.lds

@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/s3c44b0/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+	armboot_end_data = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/dave/PPChameleonEVB/PPChameleonEVB.c

@@ -96,11 +96,15 @@ int misc_init_f (void)
 	return 0;  /* dummy implementation */
 }
 
+extern flash_info_t flash_info[];	/* info for FLASH chips */
 
 int misc_init_r (void)
 {
-#if 0 /* test-only */
 	DECLARE_GLOBAL_DATA_PTR;
+
+	/* adjust flash start and size as well as the offset */
+	gd->bd->bi_flashstart = 0 - flash_info[0].size;
+	gd->bd->bi_flashoffset= flash_info[0].size - CFG_MONITOR_LEN;
 #if 0
 	volatile unsigned short *fpga_mode =
 		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
@@ -192,8 +196,6 @@ int misc_init_r (void)
 	*duart0_mcr = 0x08;
 	*duart1_mcr = 0x08;
 #endif
-#endif
-
 	return (0);
 }
 

board/dave/PPChameleonEVB/flash.c

@@ -44,10 +44,10 @@ unsigned long flash_init (void)
 #ifdef __DEBUG_START_FROM_SRAM__
 	return CFG_DUMMY_FLASH_SIZE;
 #else
-	unsigned long size_b0;
+	unsigned long size;
 	int i;
 	uint pbcr;
-	unsigned long base_b0;
+	unsigned long base;
 	int size_val = 0;
 
 	/* Init: no FLASHes known */
@@ -57,22 +57,22 @@ unsigned long flash_init (void)
 
 	/* Static FLASH Bank configuration here - FIXME XXX */
 
-	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+	size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
 
 	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
 		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-			size_b0, size_b0<<20);
+			size, size<<20);
 	}
 
 	/* Setup offsets */
-	flash_get_offsets (-size_b0, &flash_info[0]);
+	flash_get_offsets (-size, &flash_info[0]);
 
 	/* Re-do sizing to get full correct info */
 	mtdcr(ebccfga, pb0cr);
 	pbcr = mfdcr(ebccfgd);
 	mtdcr(ebccfga, pb0cr);
-	base_b0 = -size_b0;
-	switch (size_b0) {
+	base = -size;
+	switch (size) {
 	case 1 << 20:
 		size_val = 0;
 		break;
@@ -89,7 +89,7 @@ unsigned long flash_init (void)
 		size_val = 4;
 		break;
 	}
-	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	pbcr = (pbcr & 0x0001ffff) | base | (size_val << 17);
 	mtdcr(ebccfgd, pbcr);
 
 	/* Monitor protection ON by default */
@@ -98,8 +98,8 @@ unsigned long flash_init (void)
 			    0xffffffff,
 			    &flash_info[0]);
 
-	flash_info[0].size = size_b0;
+	flash_info[0].size  = size;
 
-	return (size_b0);
+	return (size);
 #endif
 }

board/dave/PPChameleonEVB/u-boot.lds

@@ -73,9 +73,6 @@ SECTIONS
     lib_ppc/extable.o	(.text)
     lib_generic/zlib.o		(.text)
 
-/*    . = env_offset;*/
-/*    common/environment.o(.text)*/
-
     *(.text)
     *(.fixup)
     *(.got1)
@@ -142,6 +139,13 @@ SECTIONS
    *(.bss)
    *(COMMON)
   }
+
+  . = 0xFFFF8000;
+  .ppcenv :
+  {
+    common/environment.o(.ppcenv);
+  }
+
   _end = . ;
   PROVIDE (end = .);
 }

board/dave/common/flash.c

@@ -22,7 +22,6 @@
  */
 
 #include <common.h>
-#include <ppc4xx.h>
 #include <asm/processor.h>
 
 flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
@@ -578,15 +577,27 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	if ((l = addr - wp) != 0) {
 		data = 0;
 		for (i=0, cp=wp; i<l; ++i, ++cp) {
+#ifdef CONFIG_B2
+			data = data | ((*(uchar *)cp)<<(8*i));
+#else
 			data = (data << 8) | (*(uchar *)cp);
+#endif
 		}
 		for (; i<4 && cnt>0; ++i) {
+#ifdef CONFIG_B2
+			data = data  | ((*src++)<<(8*i));
+#else
 			data = (data << 8) | *src++;
+#endif
 			--cnt;
 			++cp;
 		}
 		for (; cnt==0 && i<4; ++i, ++cp) {
+#ifdef CONFIG_B2
+			data = data | ((*(uchar *)cp)<<(8*i));
+#else
 			data = (data << 8) | (*(uchar *)cp);
+#endif
 		}
 
 		if ((rc = write_word(info, wp, data)) != 0) {
@@ -600,9 +611,14 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	 */
 	while (cnt >= 4) {
 		data = 0;
+#ifdef CONFIG_B2
+		data = (*(ulong*)src);
+		src += 4;
+#else
 		for (i=0; i<4; ++i) {
 			data = (data << 8) | *src++;
 		}
+#endif
 		if ((rc = write_word(info, wp, data)) != 0) {
 			return (rc);
 		}
@@ -619,11 +635,19 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	 */
 	data = 0;
 	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+#ifdef CONFIG_B2
+		data = data  | ((*src++)<<(8*i));
+#else
 		data = (data << 8) | *src++;
+#endif
 		--cnt;
 	}
 	for (; i<4; ++i, ++cp) {
+#ifdef CONFIG_B2
+		data = data | ((*(uchar *)cp)<<(8*i));
+#else
 		data = (data << 8) | (*(uchar *)cp);
+#endif
 	}
 
 	return (write_word(info, wp, data));
@@ -645,8 +669,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
 	int i;
 
 	/* Check if Flash is (sufficiently) erased */
-	if ((*((volatile CFG_FLASH_WORD_SIZE *)dest) &
-	     (CFG_FLASH_WORD_SIZE)data) != (CFG_FLASH_WORD_SIZE)data) {
+	if ((*((volatile ulong *)dest) & data) != data) {
 		return (2);
 	}
 	/* Disable interrupts which might cause a timeout here */

board/dbau1x00/dbau1x00.c

@@ -104,17 +104,17 @@ int checkboard (void)
 		      CFG_PCMCIA_ATTR_BASE, /* Hi */
 		      0x3D000017,           /* Lo0 */
 		      0x3D200017);          /* Lo1 */
-#endif
+#endif	/* 0 */
 	write_one_tlb(22,                   /* index */
 		      0x01ffe000,           /* Pagemask, 16 MB pages */
 		      CFG_PCMCIA_MEM_ADDR,  /* Hi */
 		      0x3E000017,           /* Lo0 */
 		      0x3E200017);          /* Lo1 */
+#endif	/* CONFIG_IDE_PCMCIA */
 
 	/* Release reset of ethernet PHY chips */
 	/* Always do this, because linux does not know about it */
 	*phy = 3;
 
 	return 0;
-#endif
 }

board/eXalion/Makefile

@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o
+SOBJS	=
+
+$(LIB):	.depend $(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/eXalion/config.mk

@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Sandpoint boards
+#
+
+#TEXT_BASE = 0x00090000
+TEXT_BASE = 0xFFF00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)

board/eXalion/eXalion.c

@@ -0,0 +1,292 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * Torsten Demke, FORCE Computers GmbH. torsten.demke@fci.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <pci.h>
+#include <ide.h>
+#include "piix_pci.h"
+#include "eXalion.h"
+
+int checkboard (void)
+{
+	ulong busfreq = get_bus_freq (0);
+	char buf[32];
+
+	printf ("Board: eXalion MPC824x - CHRP (MAP B)\n");
+	printf ("Built: %s at %s\n", __DATE__, __TIME__);
+	printf ("Local Bus:  %s MHz\n", strmhz (buf, busfreq));
+
+	return 0;
+}
+
+int checkflash (void)
+{
+	printf ("checkflash\n");
+	flash_init ();
+	return (0);
+}
+
+long int initdram (int board_type)
+{
+	int i, cnt;
+	volatile uchar *base = CFG_SDRAM_BASE;
+	volatile ulong *addr;
+	ulong save[32];
+	ulong val, ret = 0;
+
+	for (i = 0, cnt = (CFG_MAX_RAM_SIZE / sizeof (long)) >> 1; cnt > 0;
+	     cnt >>= 1) {
+		addr = (volatile ulong *) base + cnt;
+		save[i++] = *addr;
+		*addr = ~cnt;
+	}
+
+	addr = (volatile ulong *) base;
+	save[i] = *addr;
+	*addr = 0;
+
+	if (*addr != 0) {
+		*addr = save[i];
+		goto Done;
+	}
+
+	for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof (long); cnt <<= 1) {
+		addr = (volatile ulong *) base + cnt;
+		val = *addr;
+		*addr = save[--i];
+		if (val != ~cnt) {
+			ulong new_bank0_end = cnt * sizeof (long) - 1;
+			ulong mear1 = mpc824x_mpc107_getreg (MEAR1);
+			ulong emear1 = mpc824x_mpc107_getreg (EMEAR1);
+
+			mear1 = (mear1 & 0xFFFFFF00) |
+				((new_bank0_end & MICR_ADDR_MASK) >>
+				 MICR_ADDR_SHIFT);
+			emear1 = (emear1 & 0xFFFFFF00) |
+				((new_bank0_end & MICR_ADDR_MASK) >>
+				 MICR_EADDR_SHIFT);
+			mpc824x_mpc107_setreg (MEAR1, mear1);
+			mpc824x_mpc107_setreg (EMEAR1, emear1);
+
+			ret = cnt * sizeof (long);
+			goto Done;
+		}
+	}
+
+	ret = CFG_MAX_RAM_SIZE;
+      Done:
+	return ret;
+}
+
+int misc_init_r (void)
+{
+	pci_dev_t bdf;
+	u32 val32;
+	u8 val8;
+
+	puts ("ISA:   ");
+	bdf = pci_find_device (PIIX4_VENDOR_ID, PIIX4_ISA_DEV_ID, 0);
+	if (bdf == -1) {
+		puts ("Unable to find PIIX4 ISA bridge !\n");
+		hang ();
+	}
+
+	/* set device for normal ISA instead EIO */
+	pci_read_config_dword (bdf, PCI_CFG_PIIX4_GENCFG, &val32);
+	val32 |= 0x00000001;
+	pci_write_config_dword (bdf, PCI_CFG_PIIX4_GENCFG, val32);
+	printf ("PIIX4 ISA bridge (%d,%d,%d)\n", PCI_BUS (bdf),
+		PCI_DEV (bdf), PCI_FUNC (bdf));
+
+	puts ("ISA:   ");
+	bdf = pci_find_device (PIIX4_VENDOR_ID, PIIX4_IDE_DEV_ID, 0);
+	if (bdf == -1) {
+		puts ("Unable to find PIIX4 IDE controller !\n");
+		hang ();
+	}
+
+	/* Init BMIBA register  */
+	/* pci_read_config_dword(bdf, PCI_CFG_PIIX4_BMIBA, &val32); */
+	/* val32 |= 0x1000; */
+	/* pci_write_config_dword(bdf, PCI_CFG_PIIX4_BMIBA, val32); */
+
+	/* Enable BUS master and IO access  */
+	val32 = PCI_COMMAND_MASTER | PCI_COMMAND_IO;
+	pci_write_config_dword (bdf, PCI_COMMAND, val32);
+
+	/* Set latency  */
+	pci_read_config_byte (bdf, PCI_LATENCY_TIMER, &val8);
+	val8 = 0x40;
+	pci_write_config_byte (bdf, PCI_LATENCY_TIMER, val8);
+
+	/* Enable Primary ATA/IDE  */
+	pci_read_config_dword (bdf, PCI_CFG_PIIX4_IDETIM, &val32);
+	/* val32 = 0xa307a307; */
+	val32 = 0x00008000;
+	pci_write_config_dword (bdf, PCI_CFG_PIIX4_IDETIM, val32);
+
+
+	printf ("PIIX4 IDE controller (%d,%d,%d)\n", PCI_BUS (bdf),
+		PCI_DEV (bdf), PCI_FUNC (bdf));
+
+	/* Try to get FAT working... */
+	/* fat_register_read(ide_read); */
+
+
+	return (0);
+}
+
+/*
+ * Show/Init PCI devices on the specified bus number.
+ */
+
+void pci_eXalion_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned char line;
+
+	switch (PCI_DEV (dev)) {
+	case 16:
+		line = PCI_INT_A;
+		break;
+	case 17:
+		line = PCI_INT_B;
+		break;
+	case 18:
+		line = PCI_INT_C;
+		break;
+	case 19:
+		line = PCI_INT_D;
+		break;
+#if defined (CONFIG_MPC8245)
+	case 20:
+		line = PCI_INT_A;
+		break;
+	case 21:
+		line = PCI_INT_B;
+		break;
+	case 22:
+		line = PCI_INT_NA;
+		break;
+#endif
+	default:
+		line = PCI_INT_A;
+		break;
+	}
+	pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, line);
+}
+
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+#ifndef CONFIG_PCI_PNP
+#if defined (CONFIG_MPC8240)
+static struct pci_config_table pci_eXalion_config_table[] = {
+	{
+	 /* Intel 82559ER ethernet controller */
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 18, 0x00,
+	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+				     PCI_ENET0_MEMADDR,
+				     PCI_COMMAND_MEMORY |
+				     PCI_COMMAND_MASTER}},
+	{
+	 /* Intel 82371AB PIIX4 PCI to ISA bridge */
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x00,
+	 pci_cfgfunc_config_device, {0,
+				     0,
+				     PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
+	{
+	 /* Intel 82371AB PIIX4 IDE controller */
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x01,
+	 pci_cfgfunc_config_device, {0,
+				     0,
+				     PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
+	{}
+};
+#elif defined (CONFIG_MPC8245)
+static struct pci_config_table pci_eXalion_config_table[] = {
+	{
+	 /* Intel 82559ER ethernet controller */
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 17, 0x00,
+	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+				     PCI_ENET0_MEMADDR,
+				     PCI_COMMAND_MEMORY |
+				     PCI_COMMAND_MASTER}},
+	{
+	 /* Intel 82559ER ethernet controller */
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 18, 0x00,
+	 pci_cfgfunc_config_device, {PCI_ENET1_IOADDR,
+				     PCI_ENET1_MEMADDR,
+				     PCI_COMMAND_MEMORY |
+				     PCI_COMMAND_MASTER}},
+	{
+	 /* Broadcom BCM5690 Gigabit switch */
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x00,
+	 pci_cfgfunc_config_device, {PCI_ENET2_IOADDR,
+				     PCI_ENET2_MEMADDR,
+				     PCI_COMMAND_MEMORY |
+				     PCI_COMMAND_MASTER}},
+	{
+	 /* Broadcom BCM5690 Gigabit switch */
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 21, 0x00,
+	 pci_cfgfunc_config_device, {PCI_ENET3_IOADDR,
+				     PCI_ENET3_MEMADDR,
+				     PCI_COMMAND_MEMORY |
+				     PCI_COMMAND_MASTER}},
+	{
+	 /* Intel 82371AB PIIX4 PCI to ISA bridge */
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 22, 0x00,
+	 pci_cfgfunc_config_device, {0,
+				     0,
+				     PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
+	{
+	 /* Intel 82371AB PIIX4 IDE controller */
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 22, 0x01,
+	 pci_cfgfunc_config_device, {0,
+				     0,
+				     PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
+	{}
+};
+#else
+#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
+#endif
+
+#endif /* #ifndef CONFIG_PCI_PNP */
+
+struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table:pci_eXalion_config_table,
+	fixup_irq:pci_eXalion_fixup_irq,
+#endif
+};
+
+void pci_init_board (void)
+{
+	pci_mpc824x_init (&hose);
+}

board/eXalion/eXalion.h

@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2002
+ * Torsten Demke, FORCE Computers GmbH. torsten.demke@fci.com
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * James Dougherty (jfd@broadcom.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __EXALION_H
+#define __EXALION_H
+
+/* IRQ settings */
+#define  PCI_INT_NA (0xff)   /* PCI Intr. not used */
+#define  PCI_INT_A  (0x09)   /* PCI Intr. A Interrupt Request Line Nr. */
+#define  PCI_INT_B  (0x0a)   /* PCI Intr. B Interrupt Request Line Nr. */
+#define  PCI_INT_C  (0x0b)   /* PCI Intr. C Interrupt Request Line Nr. */
+#define  PCI_INT_D  (0x0c)   /* PCI Intr. D Interrupt Request Line Nr. */
+#if defined (CPU_MPC8245)
+#define  LN_1_INT     PCI_INT_B  /* ethernet interrupt level */
+#define  LN_2_INT     PCI_INT_C  /* ethernet interrupt level */
+#define  BCM_1_INT    PCI_INT_A  /* BCM5690 interrupt level */
+#define  BCM_2_INT    PCI_INT_B  /* BCM5690 interrupt level */
+#elif defined (CPU_MPC8240)
+#define  BCM_INT      PCI_INT_B  /* BCM5600 interrupt level */
+#define  LN_INT       PCI_INT_C  /* ethernet interrupt level */
+#endif
+
+#ifndef __ASSEMBLY__
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __EXALION_H */

board/eXalion/piix_pci.h

@@ -0,0 +1,172 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * Torsten Demke, FORCE Computers GmbH. torsten.demke@fci.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _PIIX4_PCI_H
+#define _PIIX4_PCI_H
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <pci.h>
+
+#define PIIX4_VENDOR_ID         0x8086
+#define PIIX4_ISA_DEV_ID        0x7110
+#define PIIX4_IDE_DEV_ID        0x7111
+
+/* Function 0 ISA Bridge */
+#define PCI_CFG_PIIX4_IORT      0x4C    /* 8 bit ISA Recovery Timer Reg (default 0x4D) */
+#define PCI_CFG_PIIX4_XBCS      0x4E    /* 16 bit XBus Chip select reg (default 0x0003) */
+#define PCI_CFG_PIIX4_PIRQC     0x60    /* PCI IRQ Route Register 4 x 8bit (default )*/
+#define PCI_CFG_PIIX4_SERIRQ    0x64
+#define PCI_CFG_PIIX4_TOM       0x69
+#define PCI_CFG_PIIX4_MSTAT     0x6A
+#define PCI_CFG_PIIX4_MBDMA     0x76
+#define PCI_CFG_PIIX4_APICBS    0x80
+#define PCI_CFG_PIIX4_DLC       0x82
+#define PCI_CFG_PIIX4_PDMACFG   0x90
+#define PCI_CFG_PIIX4_DDMABS    0x92
+#define PCI_CFG_PIIX4_GENCFG    0xB0
+#define PCI_CFG_PIIX4_RTCCFG    0xCB
+
+/* IO Addresses */
+#define PIIX4_ISA_DMA1_CH0BA    0x00
+#define PIIX4_ISA_DMA1_CH0CA    0x01
+#define PIIX4_ISA_DMA1_CH1BA    0x02
+#define PIIX4_ISA_DMA1_CH1CA    0x03
+#define PIIX4_ISA_DMA1_CH2BA    0x04
+#define PIIX4_ISA_DMA1_CH2CA    0x05
+#define PIIX4_ISA_DMA1_CH3BA    0x06
+#define PIIX4_ISA_DMA1_CH3CA    0x07
+#define PIIX4_ISA_DMA1_CMDST    0x08
+#define PIIX4_ISA_DMA1_REQ      0x09
+#define PIIX4_ISA_DMA1_WSBM     0x0A
+#define PIIX4_ISA_DMA1_CH_MOD   0x0B
+#define PIIX4_ISA_DMA1_CLR_PT   0x0C
+#define PIIX4_ISA_DMA1_M_CLR    0x0D
+#define PIIX4_ISA_DMA1_CLR_M    0x0E
+#define PIIX4_ISA_DMA1_RWAMB    0x0F
+
+#define PIIX4_ISA_DMA2_CH0BA    0xC0
+#define PIIX4_ISA_DMA2_CH0CA    0xC1
+#define PIIX4_ISA_DMA2_CH1BA    0xC2
+#define PIIX4_ISA_DMA2_CH1CA    0xC3
+#define PIIX4_ISA_DMA2_CH2BA    0xC4
+#define PIIX4_ISA_DMA2_CH2CA    0xC5
+#define PIIX4_ISA_DMA2_CH3BA    0xC6
+#define PIIX4_ISA_DMA2_CH3CA    0xC7
+#define PIIX4_ISA_DMA2_CMDST    0xD0
+#define PIIX4_ISA_DMA2_REQ      0xD2
+#define PIIX4_ISA_DMA2_WSBM     0xD4
+#define PIIX4_ISA_DMA2_CH_MOD   0xD6
+#define PIIX4_ISA_DMA2_CLR_PT   0xD8
+#define PIIX4_ISA_DMA2_M_CLR    0xDA
+#define PIIX4_ISA_DMA2_CLR_M    0xDC
+#define PIIX4_ISA_DMA2_RWAMB    0xDE
+
+#define PIIX4_ISA_INT1_ICW1     0x20
+#define PIIX4_ISA_INT1_OCW2     0x20
+#define PIIX4_ISA_INT1_OCW3     0x20
+#define PIIX4_ISA_INT1_ICW2     0x21
+#define PIIX4_ISA_INT1_ICW3     0x21
+#define PIIX4_ISA_INT1_ICW4     0x21
+#define PIIX4_ISA_INT1_OCW1     0x21
+
+#define PIIX4_ISA_INT1_ELCR     0x4D0
+
+#define PIIX4_ISA_INT2_ICW1     0xA0
+#define PIIX4_ISA_INT2_OCW2     0xA0
+#define PIIX4_ISA_INT2_OCW3     0xA0
+#define PIIX4_ISA_INT2_ICW2     0xA1
+#define PIIX4_ISA_INT2_ICW3     0xA1
+#define PIIX4_ISA_INT2_ICW4     0xA1
+#define PIIX4_ISA_INT2_OCW1     0xA1
+#define PIIX4_ISA_INT2_IMR      0xA1 /* read only */
+
+#define PIIX4_ISA_INT2_ELCR     0x4D1
+
+#define PIIX4_ISA_TMR0_CNT_ST   0x40
+#define PIIX4_ISA_TMR1_CNT_ST   0x41
+#define PIIX4_ISA_TMR2_CNT_ST   0x42
+#define PIIX4_ISA_TMR_TCW       0x43
+
+#define PIIX4_ISA_RST_XBUS      0x60
+
+#define PIIX4_ISA_NMI_CNT_ST    0x61
+#define PIIX4_ISA_NMI_ENABLE    0x70
+
+#define PIIX4_ISA_RTC_INDEX     0x70
+#define PIIX4_ISA_RTC_DATA      0x71
+#define PIIX4_ISA_RTCEXT_IND    0x70
+#define PIIX4_ISA_RTCEXT_DATA   0x71
+
+#define PIIX4_ISA_DMA1_CH2LPG   0x81
+#define PIIX4_ISA_DMA1_CH3LPG   0x82
+#define PIIX4_ISA_DMA1_CH1LPG   0x83
+#define PIIX4_ISA_DMA1_CH0LPG   0x87
+#define PIIX4_ISA_DMA2_CH2LPG   0x89
+#define PIIX4_ISA_DMA2_CH3LPG   0x8A
+#define PIIX4_ISA_DMA2_CH1LPG   0x8B
+#define PIIX4_ISA_DMA2_LPGRFR   0x8F
+
+#define PIIX4_ISA_PORT_92       0x92
+
+#define PIIX4_ISA_APM_CONTRL    0xB2
+#define PIIX4_ISA_APM_STATUS    0xB3
+
+#define PIIX4_ISA_COCPU_ERROR   0xF0
+
+/* Function 1 IDE Controller */
+#define PCI_CFG_PIIX4_BMIBA     0x20
+#define PCI_CFG_PIIX4_IDETIM    0x40
+#define PCI_CFG_PIIX4_SIDETIM   0x44
+#define PCI_CFG_PIIX4_UDMACTL   0x48
+#define PCI_CFG_PIIX4_UDMATIM   0x4A
+
+/* Function 2 USB Controller */
+#define PCI_CFG_PIIX4_SBRNUM    0x60
+#define PCI_CFG_PIIX4_LEGSUP    0xC0
+
+/* Function 3 Power Management */
+#define PCI_CFG_PIIX4_PMAB      0x40
+#define PCI_CFG_PIIX4_CNTA      0x44
+#define PCI_CFG_PIIX4_CNTB      0x48
+#define PCI_CFG_PIIX4_GPICTL    0x4C
+#define PCI_CFG_PIIX4_DEVRESD   0x50
+#define PCI_CFG_PIIX4_DEVACTA   0x54
+#define PCI_CFG_PIIX4_DEVACTB   0x58
+#define PCI_CFG_PIIX4_DEVRESA   0x5C
+#define PCI_CFG_PIIX4_DEVRESB   0x60
+#define PCI_CFG_PIIX4_DEVRESC   0x64
+#define PCI_CFG_PIIX4_DEVRESE   0x68
+#define PCI_CFG_PIIX4_DEVRESF   0x6C
+#define PCI_CFG_PIIX4_DEVRESG   0x70
+#define PCI_CFG_PIIX4_DEVRESH   0x74
+#define PCI_CFG_PIIX4_DEVRESI   0x78
+#define PCI_CFG_PIIX4_PMMISC    0x80
+#define PCI_CFG_PIIX4_SMBBA     0x90
+
+
+#endif  /* _PIIX4_PCI_H */

board/eXalion/u-boot.lds

@@ -0,0 +1,133 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc824x/start.o		(.text)
+    lib_ppc/board.o		(.text)
+    lib_ppc/ppcstring.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+	. = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o (.text)
+
+	*(.text)
+
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}

board/eltec/bab7xx/bab7xx.c

@@ -37,17 +37,18 @@
  */
 ulong bab7xx_get_bus_freq (void)
 {
-    /*
-     * The GPIO Port 1 on BAB7xx reflects the bus speed.
-     */
-    volatile struct GPIO *gpio = (struct GPIO *)(CFG_ISA_IO + CFG_NS87308_GPIO_BASE);
+	/*
+	 * The GPIO Port 1 on BAB7xx reflects the bus speed.
+	 */
+	volatile struct GPIO *gpio =
+		(struct GPIO *) (CFG_ISA_IO + CFG_NS87308_GPIO_BASE);
 
-    unsigned char data = gpio->dta1;
+	unsigned char data = gpio->dta1;
 
-    if (data & 0x02)
-	return 66666666;
+	if (data & 0x02)
+		return 66666666;
 
-    return 83333333;
+	return 83333333;
 }
 
 /*---------------------------------------------------------------------------*/
@@ -57,24 +58,26 @@ ulong bab7xx_get_bus_freq (void)
  */
 ulong bab7xx_get_gclk_freq (void)
 {
-    static const int pllratio_to_factor[] = {
-	00, 75, 70, 00, 20, 65, 100, 45, 30, 55, 40, 50, 80, 60, 35, 00,
-    };
+	static const int pllratio_to_factor[] = {
+		00, 75, 70, 00, 20, 65, 100, 45, 30, 55, 40, 50, 80, 60, 35,
+			00,
+	};
 
-    return pllratio_to_factor[get_hid1 () >> 28] * (bab7xx_get_bus_freq() / 10);
+	return pllratio_to_factor[get_hid1 () >> 28] *
+		(bab7xx_get_bus_freq () / 10);
 }
 
 /*----------------------------------------------------------------------------*/
 
 int checkcpu (void)
 {
-    uint pvr  = get_pvr();
+	uint pvr = get_pvr ();
 
-    printf ("MPC7xx V%d.%d",(pvr >> 8) & 0xFF, pvr & 0xFF);
-    printf (" at %ld / %ld MHz\n",  bab7xx_get_gclk_freq()/1000000,
-	    bab7xx_get_bus_freq()/1000000);
+	printf ("MPC7xx V%d.%d", (pvr >> 8) & 0xFF, pvr & 0xFF);
+	printf (" at %ld / %ld MHz\n", bab7xx_get_gclk_freq () / 1000000,
+		bab7xx_get_bus_freq () / 1000000);
 
-    return (0);
+	return (0);
 }
 
 /* ------------------------------------------------------------------------- */
@@ -82,20 +85,20 @@ int checkcpu (void)
 int checkboard (void)
 {
 #ifdef CFG_ADDRESS_MAP_A
-    puts ("Board: ELTEC BAB7xx PReP\n");
+	puts ("Board: ELTEC BAB7xx PReP\n");
 #else
-    puts ("Board: ELTEC BAB7xx CHRP\n");
+	puts ("Board: ELTEC BAB7xx CHRP\n");
 #endif
-    return (0);
+	return (0);
 }
 
 /* ------------------------------------------------------------------------- */
 
 int checkflash (void)
 {
-    /* TODO: XXX XXX XXX */
-    printf ("2 MB ## Test not implemented yet ##\n");
-    return (0);
+	/* TODO: XXX XXX XXX */
+	printf ("2 MB ## Test not implemented yet ##\n");
+	return (0);
 }
 
 /* ------------------------------------------------------------------------- */
@@ -103,77 +106,75 @@ int checkflash (void)
 
 static unsigned int mpc106_read_cfg_dword (unsigned int reg)
 {
-    unsigned int reg_addr = MPC106_REG | (reg & 0xFFFFFFFC);
+	unsigned int reg_addr = MPC106_REG | (reg & 0xFFFFFFFC);
 
-    out32r(MPC106_REG_ADDR, reg_addr);
+	out32r (MPC106_REG_ADDR, reg_addr);
 
-    return (in32r(MPC106_REG_DATA | (reg & 0x3)));
+	return (in32r (MPC106_REG_DATA | (reg & 0x3)));
 }
 
 /* ------------------------------------------------------------------------- */
 
 long int dram_size (int board_type)
 {
-    /* No actual initialisation to do - done when setting up
-     * PICRs MCCRs ME/SARs etc in ram_init.S.
-     */
+	/* No actual initialisation to do - done when setting up
+	 * PICRs MCCRs ME/SARs etc in ram_init.S.
+	 */
 
-    register unsigned long i, msar1, mear1, memSize;
+	register unsigned long i, msar1, mear1, memSize;
 
 #if defined(CFG_MEMTEST)
-    register unsigned long reg;
+	register unsigned long reg;
 
-    printf("Testing DRAM\n");
+	printf ("Testing DRAM\n");
 
-    /* write each mem addr with it's address */
-    for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg+=4)
-    *reg = reg;
+	/* write each mem addr with it's address */
+	for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4)
+		*reg = reg;
 
-    for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg+=4)
-    {
-	if (*reg != reg)
-	    return -1;
-    }
+	for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4) {
+		if (*reg != reg)
+			return -1;
+	}
 #endif
 
-    /*
-    * Since MPC106 memory controller chip has already been set to
-    * control all memory, just read and interpret its memory boundery register.
-    */
-    memSize = 0;
-    msar1 = mpc106_read_cfg_dword(MPC106_MSAR1);
-    mear1 = mpc106_read_cfg_dword(MPC106_MEAR1);
-    i     = mpc106_read_cfg_dword(MPC106_MBER) & 0xf;
+	/*
+	 * Since MPC106 memory controller chip has already been set to
+	 * control all memory, just read and interpret its memory boundery register.
+	 */
+	memSize = 0;
+	msar1 = mpc106_read_cfg_dword (MPC106_MSAR1);
+	mear1 = mpc106_read_cfg_dword (MPC106_MEAR1);
+	i = mpc106_read_cfg_dword (MPC106_MBER) & 0xf;
 
-    do
-    {
-	if (i & 0x01)   /* is bank enabled ? */
-	    memSize += (mear1 & 0xff) - (msar1 & 0xff) + 1;
-	msar1 >>= 8;
-	mear1 >>= 8;
-	i     >>= 1;
-    } while (i);
+	do {
+		if (i & 0x01)	/* is bank enabled ? */
+			memSize += (mear1 & 0xff) - (msar1 & 0xff) + 1;
+		msar1 >>= 8;
+		mear1 >>= 8;
+		i >>= 1;
+	} while (i);
 
-    return (memSize * 0x100000);
+	return (memSize * 0x100000);
 }
 
 /* ------------------------------------------------------------------------- */
 
-long int initdram(int board_type)
+long int initdram (int board_type)
 {
-    return dram_size(board_type);
+	return dram_size (board_type);
 }
 
 /* ------------------------------------------------------------------------- */
 
 void after_reloc (ulong dest_addr)
 {
-    DECLARE_GLOBAL_DATA_PTR;
+	DECLARE_GLOBAL_DATA_PTR;
 
-    /*
-     * Jump to the main U-Boot board init code
-     */
-    board_init_r((gd_t *)gd, dest_addr);
+	/*
+	 * Jump to the main U-Boot board init code
+	 */
+	board_init_r ((gd_t *) gd, dest_addr);
 }
 
 /* ------------------------------------------------------------------------- */
@@ -182,14 +183,13 @@ void after_reloc (ulong dest_addr)
  * do_reset is done here because in this case it is board specific, since the
  * 7xx CPUs can only be reset by external HW (the RTC in this case).
  */
-void
-do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+void do_reset (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
 {
 #if defined(CONFIG_RTC_MK48T59)
-    /* trigger watchdog immediately */
-    rtc_set_watchdog(1, RTC_WD_RB_16TH);
+	/* trigger watchdog immediately */
+	rtc_set_watchdog (1, RTC_WD_RB_16TH);
 #else
-    #error "You must define the macro CONFIG_RTC_MK48T59."
+#error "You must define the macro CONFIG_RTC_MK48T59."
 #endif
 }
 
@@ -200,16 +200,16 @@ do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
  * Since the 7xx CPUs don't have an internal watchdog, this function is
  * board specific.  We use the RTC here.
  */
-void watchdog_reset(void)
+void watchdog_reset (void)
 {
 #if defined(CONFIG_RTC_MK48T59)
-    /* we use a 32 sec watchdog timer */
-    rtc_set_watchdog(8, RTC_WD_RB_4);
+	/* we use a 32 sec watchdog timer */
+	rtc_set_watchdog (8, RTC_WD_RB_4);
 #else
-    #error "You must define the macro CONFIG_RTC_MK48T59."
+#error "You must define the macro CONFIG_RTC_MK48T59."
 #endif
 }
-#endif    /* CONFIG_WATCHDOG */
+#endif /* CONFIG_WATCHDOG */
 
 /* ------------------------------------------------------------------------- */
 
@@ -218,29 +218,28 @@ extern GraphicDevice smi;
 
 void video_get_info_str (int line_number, char *info)
 {
-    /* init video info strings for graphic console */
-    switch (line_number)
-    {
-    case 1:
-	sprintf (info," MPC7xx V%d.%d at %ld / %ld MHz",
-	    (get_pvr() >> 8) & 0xFF,
-	    get_pvr() & 0xFF,
-	    bab7xx_get_gclk_freq()/1000000,
-	    bab7xx_get_bus_freq()/1000000);
-	return;
-    case 2:
-	sprintf (info, " ELTEC BAB7xx with %ld MB DRAM and %ld MB FLASH",
-	    dram_size(0)/0x100000,
-	    flash_init()/0x100000);
-	return;
-    case 3:
-	sprintf (info, " %s", smi.modeIdent);
-	return;
-    }
+	/* init video info strings for graphic console */
+	switch (line_number) {
+	case 1:
+		sprintf (info, " MPC7xx V%d.%d at %ld / %ld MHz",
+			 (get_pvr () >> 8) & 0xFF,
+			 get_pvr () & 0xFF,
+			 bab7xx_get_gclk_freq () / 1000000,
+			 bab7xx_get_bus_freq () / 1000000);
+		return;
+	case 2:
+		sprintf (info,
+			 " ELTEC BAB7xx with %ld MB DRAM and %ld MB FLASH",
+			 dram_size (0) / 0x100000, flash_init () / 0x100000);
+		return;
+	case 3:
+		sprintf (info, " %s", smi.modeIdent);
+		return;
+	}
 
-    /* no more info lines */
-    *info = 0;
-    return;
+	/* no more info lines */
+	*info = 0;
+	return;
 }
 #endif
 

board/eltec/elppc/misc.c

@@ -31,32 +31,32 @@
 /* imports  */
 extern char console_buffer[CFG_CBSIZE];
 extern int l2_cache_enable (int l2control);
-extern int eepro100_write_eeprom (struct eth_device* dev, int location,
-		 int addr_len, unsigned short data);
-extern int read_eeprom (struct eth_device* dev, int location, int addr_len);
+extern int eepro100_write_eeprom (struct eth_device *dev, int location,
+				  int addr_len, unsigned short data);
+extern int read_eeprom (struct eth_device *dev, int location, int addr_len);
 
 /*----------------------------------------------------------------------------*/
 /*
  * read/write to nvram is only byte access
  */
-void *nvram_read(void *dest, const long src, size_t count)
+void *nvram_read (void *dest, const long src, size_t count)
 {
-    uchar *d = (uchar *) dest;
-    uchar *s = (uchar *) (CFG_ENV_MAP_ADRS + src);
+	uchar *d = (uchar *) dest;
+	uchar *s = (uchar *) (CFG_ENV_MAP_ADRS + src);
 
-    while (count--)
-	*d++ = *s++;
+	while (count--)
+		*d++ = *s++;
 
-    return dest;
+	return dest;
 }
 
-void nvram_write(long dest, const void *src, size_t count)
+void nvram_write (long dest, const void *src, size_t count)
 {
-    uchar *d = (uchar *) (CFG_ENV_MAP_ADRS + dest);
-    uchar *s = (uchar *) src;
+	uchar *d = (uchar *) (CFG_ENV_MAP_ADRS + dest);
+	uchar *s = (uchar *) src;
 
-    while (count--)
-	*d++ = *s++;
+	while (count--)
+		*d++ = *s++;
 }
 
 /*----------------------------------------------------------------------------*/
@@ -67,192 +67,199 @@ void nvram_write(long dest, const void *src, size_t count)
  */
 int misc_init_r (void)
 {
-    revinfo eerev;
-    u_char *ptr;
-    u_int  i, l, initSrom, copyNv;
-    char buf[256];
-    char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
-		     0, 0, 0, 0, 10, 11, 12, 13, 14, 15 };
+	revinfo eerev;
+	u_char *ptr;
+	u_int i, l, initSrom, copyNv;
+	char buf[256];
+	char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
+		0, 0, 0, 0, 10, 11, 12, 13, 14, 15
+	};
 
-    /* Clock setting for MPC107 i2c */
-    mpc107_i2c_init (MPC107_EUMB_ADDR, 0x2b);
+	/* Clock setting for MPC107 i2c */
+	mpc107_i2c_init (MPC107_EUMB_ADDR, 0x2b);
 
-    /* Reset the EPIC */
-    out32r (MPC107_EUMB_GCR, 0xa0000000);
-    while (in32r (MPC107_EUMB_GCR) & 0x80000000);   /* Wait for reset to complete */
-    out32r (MPC107_EUMB_GCR, 0x20000000);           /* Put into into mixed mode */
-    while (in32r (MPC107_EUMB_IACKR) != 0xff);      /* Clear all pending interrupts */
+	/* Reset the EPIC */
+	out32r (MPC107_EUMB_GCR, 0xa0000000);
+	while (in32r (MPC107_EUMB_GCR) & 0x80000000);	/* Wait for reset to complete */
+	out32r (MPC107_EUMB_GCR, 0x20000000);	/* Put into into mixed mode */
+	while (in32r (MPC107_EUMB_IACKR) != 0xff);	/* Clear all pending interrupts */
 
-    /*
-     * Check/Remake revision info
-     */
-    initSrom = 0;
-    copyNv   = 0;
+	/*
+	 * Check/Remake revision info
+	 */
+	initSrom = 0;
+	copyNv = 0;
 
-    /* read out current revision srom contens */
-    mpc107_srom_load (0x0000, (u_char*)&eerev, sizeof(revinfo),
-		SECOND_DEVICE, FIRST_BLOCK);
+	/* read out current revision srom contens */
+	mpc107_srom_load (0x0000, (u_char *) & eerev, sizeof (revinfo),
+			  SECOND_DEVICE, FIRST_BLOCK);
 
-    /* read out current nvram shadow image */
-    nvram_read (buf, CFG_NV_SROM_COPY_ADDR, CFG_SROM_SIZE);
+	/* read out current nvram shadow image */
+	nvram_read (buf, CFG_NV_SROM_COPY_ADDR, CFG_SROM_SIZE);
 
-    if (strcmp (eerev.magic, "ELTEC") != 0)
-    {
-	/* srom is not initialized -> create a default revision info */
-	for (i = 0, ptr = (u_char *)&eerev; i < sizeof(revinfo); i++)
-	    *ptr++ = 0x00;
-	strcpy(eerev.magic, "ELTEC");
-	eerev.revrev[0] = 1;
-	eerev.revrev[1] = 0;
-	eerev.size = 0x00E0;
-	eerev.category[0] = 0x01;
+	if (strcmp (eerev.magic, "ELTEC") != 0) {
+		/* srom is not initialized -> create a default revision info */
+		for (i = 0, ptr = (u_char *) & eerev; i < sizeof (revinfo);
+		     i++)
+			*ptr++ = 0x00;
+		strcpy (eerev.magic, "ELTEC");
+		eerev.revrev[0] = 1;
+		eerev.revrev[1] = 0;
+		eerev.size = 0x00E0;
+		eerev.category[0] = 0x01;
 
-	/* node id from dead e128 as default */
-	eerev.etheraddr[0] = 0x00;
-	eerev.etheraddr[1] = 0x00;
-	eerev.etheraddr[2] = 0x5B;
-	eerev.etheraddr[3] = 0x00;
-	eerev.etheraddr[4] = 0x2E;
-	eerev.etheraddr[5] = 0x4D;
+		/* node id from dead e128 as default */
+		eerev.etheraddr[0] = 0x00;
+		eerev.etheraddr[1] = 0x00;
+		eerev.etheraddr[2] = 0x5B;
+		eerev.etheraddr[3] = 0x00;
+		eerev.etheraddr[4] = 0x2E;
+		eerev.etheraddr[5] = 0x4D;
 
-	/* cache config word for ELPPC */
-	*(int*)&eerev.res[0] = 0;
+		/* cache config word for ELPPC */
+		*(int *) &eerev.res[0] = 0;
 
-	initSrom = 1;  /* force dialog */
-	copyNv   = 1;  /* copy to nvram */
-    }
-
-    if ((copyNv == 0) &&   (el_srom_checksum((u_char*)&eerev, CFG_SROM_SIZE) !=
-		el_srom_checksum((u_char*)buf, CFG_SROM_SIZE)))
-    {
-	printf ("Invalid revision info copy in nvram !\n");
-	printf ("Press key:\n  <c> to copy current revision info to nvram.\n");
-	printf ("  <r> to reenter revision info.\n");
-	printf ("=> ");
-	if (0 != readline (NULL))
-	{
-	    switch ((char)toupper(console_buffer[0]))
-	    {
-	    case 'C':
-		copyNv = 1;
-		break;
-	    case 'R':
-		copyNv = 1;
-		initSrom = 1;
-		break;
-	    }
-	}
-    }
-
-    if (initSrom)
-    {
-	memcpy (buf, &eerev.revision[0][0], 14);     /* save all revision info */
-	printf ("Enter revision number (0-9): %c  ", eerev.revision[0][0]);
-	if (0 != readline (NULL))
-	{
-	    eerev.revision[0][0] = (char)toupper(console_buffer[0]);
-	    memcpy (&eerev.revision[1][0], buf, 12); /* shift rest of rev info */
+		initSrom = 1;	/* force dialog */
+		copyNv = 1;	/* copy to nvram */
 	}
 
-	printf ("Enter revision character (A-Z): %c  ", eerev.revision[0][1]);
-	if (1 == readline (NULL))
-	{
-	    eerev.revision[0][1] = (char)toupper(console_buffer[0]);
+	if ((copyNv == 0)
+	    && (el_srom_checksum ((u_char *) & eerev, CFG_SROM_SIZE) !=
+		el_srom_checksum ((u_char *) buf, CFG_SROM_SIZE))) {
+		printf ("Invalid revision info copy in nvram !\n");
+		printf ("Press key:\n  <c> to copy current revision info to nvram.\n");
+		printf ("  <r> to reenter revision info.\n");
+		printf ("=> ");
+		if (0 != readline (NULL)) {
+			switch ((char) toupper (console_buffer[0])) {
+			case 'C':
+				copyNv = 1;
+				break;
+			case 'R':
+				copyNv = 1;
+				initSrom = 1;
+				break;
+			}
+		}
 	}
 
-	printf ("Enter board name (V-XXXX-XXXX): %s  ", (char *)&eerev.board);
-	if (11 == readline (NULL))
-	{
-	    for (i=0; i<11; i++)
-		eerev.board[i] =  (char)toupper(console_buffer[i]);
-	    eerev.board[11] = '\0';
+	if (initSrom) {
+		memcpy (buf, &eerev.revision[0][0], 14);	/* save all revision info */
+		printf ("Enter revision number (0-9): %c  ",
+			eerev.revision[0][0]);
+		if (0 != readline (NULL)) {
+			eerev.revision[0][0] =
+				(char) toupper (console_buffer[0]);
+			memcpy (&eerev.revision[1][0], buf, 12);	/* shift rest of rev info */
+		}
+
+		printf ("Enter revision character (A-Z): %c  ",
+			eerev.revision[0][1]);
+		if (1 == readline (NULL)) {
+			eerev.revision[0][1] =
+				(char) toupper (console_buffer[0]);
+		}
+
+		printf ("Enter board name (V-XXXX-XXXX): %s  ",
+			(char *) &eerev.board);
+		if (11 == readline (NULL)) {
+			for (i = 0; i < 11; i++)
+				eerev.board[i] =
+					(char) toupper (console_buffer[i]);
+			eerev.board[11] = '\0';
+		}
+
+		printf ("Enter serial number: %s ", (char *) &eerev.serial);
+		if (6 == readline (NULL)) {
+			for (i = 0; i < 6; i++)
+				eerev.serial[i] = console_buffer[i];
+			eerev.serial[6] = '\0';
+		}
+
+		printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x  ", eerev.etheraddr[0], eerev.etheraddr[1], eerev.etheraddr[2], eerev.etheraddr[3], eerev.etheraddr[4], eerev.etheraddr[5]);
+		if (12 == readline (NULL)) {
+			for (i = 0; i < 12; i += 2)
+				eerev.etheraddr[i >> 1] =
+					(char) (16 *
+						hex[toupper
+						    (console_buffer[i]) -
+						    '0'] +
+						hex[toupper
+						    (console_buffer[i + 1]) -
+						    '0']);
+		}
+
+		l = strlen ((char *) &eerev.text);
+		printf ("Add to text section (max 64 chr): %s ",
+			(char *) &eerev.text);
+		if (0 != readline (NULL)) {
+			for (i = l; i < 63; i++)
+				eerev.text[i] = console_buffer[i - l];
+			eerev.text[63] = '\0';
+		}
+
+		/* prepare network eeprom */
+		memset (buf, 0, 128);
+
+		buf[0] = eerev.etheraddr[1];
+		buf[1] = eerev.etheraddr[0];
+		buf[2] = eerev.etheraddr[3];
+		buf[3] = eerev.etheraddr[2];
+		buf[4] = eerev.etheraddr[5];
+		buf[5] = eerev.etheraddr[4];
+
+		*(unsigned short *) &buf[20] = 0x48B2;
+		*(unsigned short *) &buf[22] = 0x0004;
+		*(unsigned short *) &buf[24] = 0x1433;
+
+		printf ("\nSRom:  Writing i82559 info ........ ");
+		if (eepro100_srom_store ((unsigned short *) buf) == -1)
+			printf ("FAILED\n");
+		else
+			printf ("OK\n");
+
+		/* update CRC */
+		eerev.crc =
+			el_srom_checksum ((u_char *) eerev.board, eerev.size);
+
+		/* write new values */
+		printf ("\nSRom:  Writing revision info ...... ");
+		if (mpc107_srom_store
+		    ((BLOCK_SIZE - sizeof (revinfo)), (u_char *) & eerev,
+		     sizeof (revinfo), SECOND_DEVICE, FIRST_BLOCK) == -1)
+			printf ("FAILED\n\n");
+		else
+			printf ("OK\n\n");
+
+		/* write new values as shadow image to nvram */
+		nvram_write (CFG_NV_SROM_COPY_ADDR, (void *) &eerev,
+			     CFG_SROM_SIZE);
+
 	}
 
-	printf ("Enter serial number: %s ", (char *)&eerev.serial );
-	if (6 == readline (NULL))
-	{
-	    for (i=0; i<6; i++)
-		eerev.serial[i] = console_buffer[i];
-	    eerev.serial[6] = '\0';
-	}
+	/*if (initSrom) */
+	/* copy current values as shadow image to nvram */
+	if (initSrom == 0 && copyNv == 1)
+		nvram_write (CFG_NV_SROM_COPY_ADDR, (void *) &eerev,
+			     CFG_SROM_SIZE);
 
-	printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x  ",
-	    eerev.etheraddr[0], eerev.etheraddr[1],
-	    eerev.etheraddr[2], eerev.etheraddr[3],
-	    eerev.etheraddr[4], eerev.etheraddr[5]);
-	if (12 == readline (NULL))
-	{
-	    for (i=0; i<12; i+=2)
-	    eerev.etheraddr[i>>1] = (char)(16*hex[toupper(console_buffer[i])-'0'] +
-			       hex[toupper(console_buffer[i+1])-'0']);
-	}
+	/* update environment */
+	sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
+		 eerev.etheraddr[0], eerev.etheraddr[1],
+		 eerev.etheraddr[2], eerev.etheraddr[3],
+		 eerev.etheraddr[4], eerev.etheraddr[5]);
+	setenv ("ethaddr", buf);
 
-	l = strlen ((char *)&eerev.text);
-	printf("Add to text section (max 64 chr): %s ", (char *)&eerev.text );
-	if (0 != readline (NULL))
-	{
-	    for (i = l; i<63; i++)
-		eerev.text[i] = console_buffer[i-l];
-	    eerev.text[63] = '\0';
-	}
+	/* set serial console as default */
+	if ((ptr = getenv ("console")) == NULL)
+		setenv ("console", "serial");
 
-	/* prepare network eeprom */
-	memset (buf, 0, 128);
+	/* print actual board identification */
+	printf ("Ident: %s  Ser %s  Rev %c%c\n",
+		eerev.board, (char *) &eerev.serial,
+		eerev.revision[0][0], eerev.revision[0][1]);
 
-	buf[0] = eerev.etheraddr[1];
-	buf[1] = eerev.etheraddr[0];
-	buf[2] = eerev.etheraddr[3];
-	buf[3] = eerev.etheraddr[2];
-	buf[4] = eerev.etheraddr[5];
-	buf[5] = eerev.etheraddr[4];
-
-	*(unsigned short *)&buf[20] = 0x48B2;
-	*(unsigned short *)&buf[22] = 0x0004;
-	*(unsigned short *)&buf[24] = 0x1433;
-
-	printf("\nSRom:  Writing i82559 info ........ ");
-	if (eepro100_srom_store ((unsigned short *)buf) == -1)
-	    printf("FAILED\n");
-	else
-	    printf("OK\n");
-
-	/* update CRC */
-	eerev.crc = el_srom_checksum((u_char *)eerev.board, eerev.size);
-
-	/* write new values */
-	printf("\nSRom:  Writing revision info ...... ");
-	if (mpc107_srom_store((BLOCK_SIZE-sizeof(revinfo)), (u_char *)&eerev,
-			    sizeof(revinfo), SECOND_DEVICE, FIRST_BLOCK) == -1)
-	    printf("FAILED\n\n");
-	else
-	    printf("OK\n\n");
-
-	/* write new values as shadow image to nvram */
-	nvram_write (CFG_NV_SROM_COPY_ADDR, (void *)&eerev, CFG_SROM_SIZE);
-
-    } /*if (initSrom) */
-
-    /* copy current values as shadow image to nvram */
-    if (initSrom == 0 && copyNv == 1)
-	nvram_write (CFG_NV_SROM_COPY_ADDR, (void *)&eerev, CFG_SROM_SIZE);
-
-    /* update environment */
-    sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
-	    eerev.etheraddr[0], eerev.etheraddr[1],
-	    eerev.etheraddr[2], eerev.etheraddr[3],
-	    eerev.etheraddr[4], eerev.etheraddr[5]);
-    setenv ("ethaddr", buf);
-
-    /* set serial console as default */
-    if ((ptr = getenv ("console")) == NULL)
-	setenv ("console", "serial");
-
-    /* print actual board identification */
-    printf("Ident: %s  Ser %s  Rev %c%c\n",
-	    eerev.board, (char *)&eerev.serial,
-	    eerev.revision[0][0], eerev.revision[0][1]);
-
-    return (0);
+	return (0);
 }
 
 /*----------------------------------------------------------------------------*/

board/eltec/mhpc/mhpc.c

@@ -38,19 +38,19 @@
 /* imports from common/main.c */
 extern char console_buffer[CFG_CBSIZE];
 
-extern void eeprom_init  (void);
-extern int  eeprom_read  (unsigned dev_addr, unsigned offset,
-			  unsigned char *buffer, unsigned cnt);
-extern int  eeprom_write (unsigned dev_addr, unsigned offset,
-			  unsigned char *buffer, unsigned cnt);
+extern void eeprom_init (void);
+extern int eeprom_read (unsigned dev_addr, unsigned offset,
+			unsigned char *buffer, unsigned cnt);
+extern int eeprom_write (unsigned dev_addr, unsigned offset,
+			 unsigned char *buffer, unsigned cnt);
 
 /* globals */
-void *video_hw_init(void);
-void video_set_lut (unsigned int index,     /* color number */
-		    unsigned char r,        /* red */
-		    unsigned char g,        /* green */
-		    unsigned char b         /* blue */
-		    );
+void *video_hw_init (void);
+void video_set_lut (unsigned int index,	/* color number */
+		    unsigned char r,	/* red */
+		    unsigned char g,	/* green */
+		    unsigned char b	/* blue */
+	);
 
 GraphicDevice gdev;
 
@@ -60,79 +60,78 @@ static void video_test_image (void);
 static void video_default_lut (unsigned int clut_type);
 
 /* revision info foer MHPC EEPROM offset 480 */
-typedef struct  {
-    char    board[12];      /* 000 - Board Revision information */
-    char    sensor;         /* 012 - Sensor Type information */
-    char    serial[8];      /* 013 - Board serial number */
-    char    etheraddr[6];   /* 021 - Ethernet node addresse */
-    char    revision[2];    /* 027 - Revision code */
-    char    option[3];      /* 029 - resevered for options */
+typedef struct {
+	char board[12];		/* 000 - Board Revision information */
+	char sensor;		/* 012 - Sensor Type information */
+	char serial[8];		/* 013 - Board serial number */
+	char etheraddr[6];	/* 021 - Ethernet node addresse */
+	char revision[2];	/* 027 - Revision code */
+	char option[3];		/* 029 - resevered for options */
 } revinfo;
 
 /* ------------------------------------------------------------------------- */
 
-static const unsigned int sdram_table[] =
-{
-    /* read single beat cycle */
-    0xef0efc04, 0x0e2dac04, 0x01ba5c04, 0x1ff5fc00,
-    0xfffffc05, 0xeffafc34, 0x0ff0bc34, 0x1ff57c35,
+static const unsigned int sdram_table[] = {
+	/* read single beat cycle */
+	0xef0efc04, 0x0e2dac04, 0x01ba5c04, 0x1ff5fc00,
+	0xfffffc05, 0xeffafc34, 0x0ff0bc34, 0x1ff57c35,
 
-    /* read burst cycle */
-    0xef0efc04, 0x0e3dac04, 0x10ff5c04, 0xf0fffc00,
-    0xf0fffc00, 0xf1fffc00, 0xfffffc00, 0xfffffc05,
-    0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-    0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	/* read burst cycle */
+	0xef0efc04, 0x0e3dac04, 0x10ff5c04, 0xf0fffc00,
+	0xf0fffc00, 0xf1fffc00, 0xfffffc00, 0xfffffc05,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
 
-    /* write single beat cycle */
-    0xef0efc04, 0x0e29ac00, 0x01b25c04, 0x1ff5fc05,
-    0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	/* write single beat cycle */
+	0xef0efc04, 0x0e29ac00, 0x01b25c04, 0x1ff5fc05,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
 
-    /* write burst cycle */
-    0xef0ef804, 0x0e39a000, 0x10f75000, 0xf0fff440,
-    0xf0fffc40, 0xf1fffc04, 0xfffffc05, 0xfffffc04,
-    0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-    0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	/* write burst cycle */
+	0xef0ef804, 0x0e39a000, 0x10f75000, 0xf0fff440,
+	0xf0fffc40, 0xf1fffc04, 0xfffffc05, 0xfffffc04,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
 
-    /* periodic timer expired */
-    0xeffebc84, 0x1ffd7c04, 0xfffffc04, 0xfffffc84,
-    0xeffebc04, 0x1ffd7c04, 0xfffffc04, 0xfffffc05,
-    0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	/* periodic timer expired */
+	0xeffebc84, 0x1ffd7c04, 0xfffffc04, 0xfffffc84,
+	0xeffebc04, 0x1ffd7c04, 0xfffffc04, 0xfffffc05,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
 
-    /* exception */
-    0xfffffc04, 0xfffffc05, 0xfffffc04, 0xfffffc04
+	/* exception */
+	0xfffffc04, 0xfffffc05, 0xfffffc04, 0xfffffc04
 };
 
 /* ------------------------------------------------------------------------- */
 
 int board_early_init_f (void)
 {
-    volatile immap_t  *im = (immap_t *)CFG_IMMR;
-    volatile cpm8xx_t *cp = &(im->im_cpm);
-    volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
+	volatile immap_t *im = (immap_t *) CFG_IMMR;
+	volatile cpm8xx_t *cp = &(im->im_cpm);
+	volatile iop8xx_t *ip = (iop8xx_t *) & (im->im_ioport);
 
-    /* reset the port A s.a. cpm-routines */
-    ip->iop_padat = 0x0000;
-    ip->iop_papar = 0x0000;
-    ip->iop_padir = 0x0800;
-    ip->iop_paodr = 0x0000;
+	/* reset the port A s.a. cpm-routines */
+	ip->iop_padat = 0x0000;
+	ip->iop_papar = 0x0000;
+	ip->iop_padir = 0x0800;
+	ip->iop_paodr = 0x0000;
 
-    /* reset the port B for digital and LCD output */
-    cp->cp_pbdat  = 0x0300;
-    cp->cp_pbpar  = 0x5001;
-    cp->cp_pbdir  = 0x5301;
-    cp->cp_pbodr  = 0x0000;
+	/* reset the port B for digital and LCD output */
+	cp->cp_pbdat = 0x0300;
+	cp->cp_pbpar = 0x5001;
+	cp->cp_pbdir = 0x5301;
+	cp->cp_pbodr = 0x0000;
 
-    /* reset the port C configured for SMC1 serial port and aqc. control */
-    ip->iop_pcdat = 0x0800;
-    ip->iop_pcpar = 0x0000;
-    ip->iop_pcdir = 0x0e30;
-    ip->iop_pcso  = 0x0000;
+	/* reset the port C configured for SMC1 serial port and aqc. control */
+	ip->iop_pcdat = 0x0800;
+	ip->iop_pcpar = 0x0000;
+	ip->iop_pcdir = 0x0e30;
+	ip->iop_pcso = 0x0000;
 
-    /* Config port D for LCD output */
-    ip->iop_pdpar = 0x1fff;
-    ip->iop_pddir = 0x1fff;
+	/* Config port D for LCD output */
+	ip->iop_pdpar = 0x1fff;
+	ip->iop_pddir = 0x1fff;
 
-    return (0);
+	return (0);
 }
 
 /* ------------------------------------------------------------------------- */
@@ -142,322 +141,327 @@ int board_early_init_f (void)
  */
 int checkboard (void)
 {
-    puts ("Board: ELTEC miniHiperCam\n");
-    return(0);
+	puts ("Board: ELTEC miniHiperCam\n");
+	return (0);
 }
 
 /* ------------------------------------------------------------------------- */
 
-int misc_init_r(void)
+int misc_init_r (void)
 {
-    revinfo  mhpcRevInfo;
-    char     nid[32];
-    char     *mhpcSensorTypes[] = { "OMNIVISON OV7610/7620 color",
-				    "OMNIVISON OV7110 b&w", NULL };
-    char     hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
-			 0, 0, 0, 0, 10, 11, 12, 13, 14, 15 };
-    int      i;
+	revinfo mhpcRevInfo;
+	char nid[32];
+	char *mhpcSensorTypes[] = { "OMNIVISON OV7610/7620 color",
+		"OMNIVISON OV7110 b&w", NULL
+	};
+	char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
+		0, 0, 0, 0, 10, 11, 12, 13, 14, 15
+	};
+	int i;
 
-    /* check revision data */
-    eeprom_read (CFG_I2C_EEPROM_ADDR, 480, (char*)&mhpcRevInfo, 32);
+	/* check revision data */
+	eeprom_read (CFG_I2C_EEPROM_ADDR, 480, (char *) &mhpcRevInfo, 32);
 
-    if (strncmp((char *)&mhpcRevInfo.board[2], "MHPC", 4) != 0)
-    {
-    printf ("Enter revision number (0-9): %c  ", mhpcRevInfo.revision[0]);
-    if (0 != readline (NULL))
-    {
-	mhpcRevInfo.revision[0] = (char)toupper(console_buffer[0]);
-    }
+	if (strncmp ((char *) &mhpcRevInfo.board[2], "MHPC", 4) != 0) {
+		printf ("Enter revision number (0-9): %c  ",
+			mhpcRevInfo.revision[0]);
+		if (0 != readline (NULL)) {
+			mhpcRevInfo.revision[0] =
+				(char) toupper (console_buffer[0]);
+		}
 
-    printf ("Enter revision character (A-Z): %c  ", mhpcRevInfo.revision[1]);
-    if (1 == readline (NULL))
-    {
-	mhpcRevInfo.revision[1] = (char)toupper(console_buffer[0]);
-    }
+		printf ("Enter revision character (A-Z): %c  ",
+			mhpcRevInfo.revision[1]);
+		if (1 == readline (NULL)) {
+			mhpcRevInfo.revision[1] =
+				(char) toupper (console_buffer[0]);
+		}
 
-    printf("Enter board name (V-XXXX-XXXX): %s  ", (char *)&mhpcRevInfo.board);
-    if (11 == readline (NULL))
-    {
-	for (i=0; i<11; i++)
-	{
-	    mhpcRevInfo.board[i] =  (char)toupper(console_buffer[i]);
-	    mhpcRevInfo.board[11] = '\0';
+		printf ("Enter board name (V-XXXX-XXXX): %s  ",
+			(char *) &mhpcRevInfo.board);
+		if (11 == readline (NULL)) {
+			for (i = 0; i < 11; i++) {
+				mhpcRevInfo.board[i] =
+					(char) toupper (console_buffer[i]);
+				mhpcRevInfo.board[11] = '\0';
+			}
+		}
+
+		printf ("Supported sensor types:\n");
+		i = 0;
+		do {
+			printf ("\n    \'%d\' : %s\n", i, mhpcSensorTypes[i]);
+		} while (mhpcSensorTypes[++i] != NULL);
+
+		do {
+			printf ("\nEnter sensor number (0-255): %d  ",
+				(int) mhpcRevInfo.sensor);
+			if (0 != readline (NULL)) {
+				mhpcRevInfo.sensor =
+					(unsigned char)
+					simple_strtoul (console_buffer, NULL,
+							10);
+			}
+		} while (mhpcRevInfo.sensor >= i);
+
+		printf ("Enter serial number: %s ",
+			(char *) &mhpcRevInfo.serial);
+		if (6 == readline (NULL)) {
+			for (i = 0; i < 6; i++) {
+				mhpcRevInfo.serial[i] = console_buffer[i];
+			}
+			mhpcRevInfo.serial[6] = '\0';
+		}
+
+		printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x  ", mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1], mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3], mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]);
+		if (12 == readline (NULL)) {
+			for (i = 0; i < 12; i += 2) {
+				mhpcRevInfo.etheraddr[i >> 1] =
+					(char) (16 *
+						hex[toupper
+						    (console_buffer[i]) -
+						    '0'] +
+						hex[toupper
+						    (console_buffer[i + 1]) -
+						    '0']);
+			}
+		}
+
+		/* setup new revision data */
+		eeprom_write (CFG_I2C_EEPROM_ADDR, 480, (char *) &mhpcRevInfo,
+			      32);
 	}
-    }
 
-    printf("Supported sensor types:\n");
-    i=0;
-    do
-    {
-	printf("\n    \'%d\' : %s\n", i, mhpcSensorTypes[i]);
-    } while ( mhpcSensorTypes[++i] != NULL );
+	/* set environment */
+	sprintf (nid, "%02x:%02x:%02x:%02x:%02x:%02x",
+		 mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1],
+		 mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3],
+		 mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]);
+	setenv ("ethaddr", nid);
 
-    do
-    {
-	printf("\nEnter sensor number (0-255): %d  ", (int)mhpcRevInfo.sensor );
-	if (0 != readline (NULL))
-	{
-	mhpcRevInfo.sensor = (unsigned char)simple_strtoul(console_buffer, NULL, 10);
-	}
-    } while ( mhpcRevInfo.sensor >= i );
+	/* print actual board identification */
+	printf ("Ident: %s %s Ser %s Rev %c%c\n",
+		mhpcRevInfo.board,
+		(mhpcRevInfo.sensor == 0 ? "color" : "b&w"),
+		(char *) &mhpcRevInfo.serial, mhpcRevInfo.revision[0],
+		mhpcRevInfo.revision[1]);
 
-    printf("Enter serial number: %s ", (char *)&mhpcRevInfo.serial );
-    if (6 == readline (NULL))
-    {
-	for (i=0; i<6; i++)
-	{
-	mhpcRevInfo.serial[i] = console_buffer[i];
-	}
-	mhpcRevInfo.serial[6] = '\0';
-    }
-
-    printf("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x  ",
-	      mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1],
-	      mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3],
-	      mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]  );
-    if (12 == readline (NULL))
-    {
-	for (i=0; i<12; i+=2)
-	{
-	mhpcRevInfo.etheraddr[i>>1] = (char)(16*hex[toupper(console_buffer[i])-'0'] +
-			     hex[toupper(console_buffer[i+1])-'0']);
-	}
-    }
-
-    /* setup new revision data */
-    eeprom_write (CFG_I2C_EEPROM_ADDR, 480, (char*)&mhpcRevInfo, 32);
-    }
-
-    /* set environment */
-    sprintf( nid, "%02x:%02x:%02x:%02x:%02x:%02x",
-		  mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1],
-		  mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3],
-		  mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]);
-    setenv("ethaddr", nid);
-
-    /* print actual board identification */
-    printf("Ident: %s %s Ser %s Rev %c%c\n",
-	    mhpcRevInfo.board, (mhpcRevInfo.sensor==0?"color":"b&w"),
-	    (char *)&mhpcRevInfo.serial,
-	    mhpcRevInfo.revision[0], mhpcRevInfo.revision[1]);
-
-    return (0);
+	return (0);
 }
 
 /* ------------------------------------------------------------------------- */
 
 long int initdram (int board_type)
 {
-    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
-    volatile memctl8xx_t *memctl = &immap->im_memctl;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
-    upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
 
-    memctl->memc_mamr  = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
-    memctl->memc_mbmr  = MBMR_GPL_B4DIS;	/* should this be mamr? - NTL */
-    memctl->memc_mptpr = MPTPR_PTP_DIV64;
-    memctl->memc_mar   = 0x00008800;
+	memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_mbmr = MBMR_GPL_B4DIS;	/* should this be mamr? - NTL */
+	memctl->memc_mptpr = MPTPR_PTP_DIV64;
+	memctl->memc_mar = 0x00008800;
 
-    /*
-     * Map controller SDRAM bank 0
-     */
-    memctl->memc_or1 = CFG_OR1_PRELIM;
-    memctl->memc_br1 = CFG_BR1_PRELIM;
-    udelay(200);
+	/*
+	 * Map controller SDRAM bank 0
+	 */
+	memctl->memc_or1 = CFG_OR1_PRELIM;
+	memctl->memc_br1 = CFG_BR1_PRELIM;
+	udelay (200);
 
-    /*
-     * Map controller SDRAM bank 1
-     */
-    memctl->memc_or2 = CFG_OR2;
-    memctl->memc_br2 = CFG_BR2;
+	/*
+	 * Map controller SDRAM bank 1
+	 */
+	memctl->memc_or2 = CFG_OR2;
+	memctl->memc_br2 = CFG_BR2;
 
-    /*
-     * Perform SDRAM initializsation sequence
-     */
-    memctl->memc_mcr  = 0x80002105;    /* SDRAM bank 0 */
-    udelay(1);
-    memctl->memc_mcr  = 0x80002730;    /* SDRAM bank 0 - execute twice */
-    udelay(1);
-    memctl->memc_mamr |= MAMR_PTAE;    /* enable refresh */
+	/*
+	 * Perform SDRAM initializsation sequence
+	 */
+	memctl->memc_mcr = 0x80002105;	/* SDRAM bank 0 */
+	udelay (1);
+	memctl->memc_mcr = 0x80002730;	/* SDRAM bank 0 - execute twice */
+	udelay (1);
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
 
-    udelay(10000);
+	udelay (10000);
 
-    /* leave place for framebuffers */
-    return (SDRAM_MAX_SIZE-SDRAM_RES_SIZE);
+	/* leave place for framebuffers */
+	return (SDRAM_MAX_SIZE - SDRAM_RES_SIZE);
 }
 
 /* ------------------------------------------------------------------------- */
 
 static void video_circle (char *center, int radius, int color, int pitch)
 {
-    int x,y,d,dE,dSE;
+	int x, y, d, dE, dSE;
 
-    x   = 0;
-    y   = radius;
-    d   = 1-radius;
-    dE  = 3;
-    dSE = -2*radius+5;
+	x = 0;
+	y = radius;
+	d = 1 - radius;
+	dE = 3;
+	dSE = -2 * radius + 5;
 
-    *(center+x+y*pitch) = color;
-    *(center+y+x*pitch) = color;
-    *(center+y-x*pitch) = color;
-    *(center+x-y*pitch) = color;
-    *(center-x-y*pitch) = color;
-    *(center-y-x*pitch) = color;
-    *(center-y+x*pitch) = color;
-    *(center-x+y*pitch) = color;
-    while(y>x)
-    {
-	if (d<0)
-	{
-	    d   += dE;
-	    dE  += 2;
-	    dSE += 2;
-	    x++;
+	*(center + x + y * pitch) = color;
+	*(center + y + x * pitch) = color;
+	*(center + y - x * pitch) = color;
+	*(center + x - y * pitch) = color;
+	*(center - x - y * pitch) = color;
+	*(center - y - x * pitch) = color;
+	*(center - y + x * pitch) = color;
+	*(center - x + y * pitch) = color;
+	while (y > x) {
+		if (d < 0) {
+			d += dE;
+			dE += 2;
+			dSE += 2;
+			x++;
+		} else {
+			d += dSE;
+			dE += 2;
+			dSE += 4;
+			x++;
+			y--;
+		}
+		*(center + x + y * pitch) = color;
+		*(center + y + x * pitch) = color;
+		*(center + y - x * pitch) = color;
+		*(center + x - y * pitch) = color;
+		*(center - x - y * pitch) = color;
+		*(center - y - x * pitch) = color;
+		*(center - y + x * pitch) = color;
+		*(center - x + y * pitch) = color;
 	}
-	else
-	{
-	    d   += dSE;
-	    dE  += 2;
-	    dSE += 4;
-	    x++;
-	    y--;
-	}
-	*(center+x+y*pitch) = color;
-	*(center+y+x*pitch) = color;
-	*(center+y-x*pitch) = color;
-	*(center+x-y*pitch) = color;
-	*(center-x-y*pitch) = color;
-	*(center-y-x*pitch) = color;
-	*(center-y+x*pitch) = color;
-	*(center-x+y*pitch) = color;
-    }
 }
 
 /* ------------------------------------------------------------------------- */
 
-static void video_test_image(void)
+static void video_test_image (void)
 {
-    char *di;
-    int i, n;
+	char *di;
+	int i, n;
 
-    /* draw raster */
-    for (i=0; i<LCD_VIDEO_ROWS; i+=32)
-    {
-	memset((char*)(LCD_VIDEO_ADDR+i*LCD_VIDEO_COLS), LCD_VIDEO_FG, LCD_VIDEO_COLS);
-	for (n=i+1;n<i+32;n++)
-	    memset((char*)(LCD_VIDEO_ADDR+n*LCD_VIDEO_COLS), LCD_VIDEO_BG, LCD_VIDEO_COLS);
-    }
-
-    for (i=0; i<LCD_VIDEO_COLS; i+=32)
-    {
-	for (n=0; n<LCD_VIDEO_ROWS; n++)
-	    *(char*)(LCD_VIDEO_ADDR+n*LCD_VIDEO_COLS+i) = LCD_VIDEO_FG;
-    }
-
-    /* draw gray bar */
-    di = (char *)(LCD_VIDEO_ADDR + (LCD_VIDEO_COLS-256)/64*32 + 97*LCD_VIDEO_COLS);
-    for (n=0; n<63; n++)
-    {
-	for (i=0; i<256; i++)
-	{
-	    *di++ = (char)i;
-	    *(di+LCD_VIDEO_COLS*64) = (i&1)*255;
+	/* draw raster */
+	for (i = 0; i < LCD_VIDEO_ROWS; i += 32) {
+		memset ((char *) (LCD_VIDEO_ADDR + i * LCD_VIDEO_COLS),
+			LCD_VIDEO_FG, LCD_VIDEO_COLS);
+		for (n = i + 1; n < i + 32; n++)
+			memset ((char *) (LCD_VIDEO_ADDR +
+					  n * LCD_VIDEO_COLS), LCD_VIDEO_BG,
+				LCD_VIDEO_COLS);
 	}
-	di += LCD_VIDEO_COLS-256;
-    }
 
-    video_circle ((char*)LCD_VIDEO_ADDR+LCD_VIDEO_COLS/2+LCD_VIDEO_ROWS/2*LCD_VIDEO_COLS,
-		  LCD_VIDEO_ROWS/2,LCD_VIDEO_FG, LCD_VIDEO_COLS);
+	for (i = 0; i < LCD_VIDEO_COLS; i += 32) {
+		for (n = 0; n < LCD_VIDEO_ROWS; n++)
+			*(char *) (LCD_VIDEO_ADDR + n * LCD_VIDEO_COLS + i) =
+				LCD_VIDEO_FG;
+	}
+
+	/* draw gray bar */
+	di = (char *) (LCD_VIDEO_ADDR + (LCD_VIDEO_COLS - 256) / 64 * 32 +
+		       97 * LCD_VIDEO_COLS);
+	for (n = 0; n < 63; n++) {
+		for (i = 0; i < 256; i++) {
+			*di++ = (char) i;
+			*(di + LCD_VIDEO_COLS * 64) = (i & 1) * 255;
+		}
+		di += LCD_VIDEO_COLS - 256;
+	}
+
+	video_circle ((char *) LCD_VIDEO_ADDR + LCD_VIDEO_COLS / 2 +
+		      LCD_VIDEO_ROWS / 2 * LCD_VIDEO_COLS, LCD_VIDEO_ROWS / 2,
+		      LCD_VIDEO_FG, LCD_VIDEO_COLS);
 }
 
 /* ------------------------------------------------------------------------- */
 
 static void video_default_lut (unsigned int clut_type)
 {
-    unsigned int i;
-    unsigned char RGB[] =
-	{
-	0x00, 0x00, 0x00,   /* black */
-	0x80, 0x80, 0x80,   /* gray */
-	0xff, 0x00, 0x00,   /* red */
-	0x00, 0xff, 0x00,   /* green */
-	0x00, 0x00, 0xff,   /* blue */
-	0x00, 0xff, 0xff,   /* cyan */
-	0xff, 0x00, 0xff,   /* magenta */
-	0xff, 0xff, 0x00,   /* yellow */
-	0x80, 0x00, 0x00,   /* dark red */
-	0x00, 0x80, 0x00,   /* dark green */
-	0x00, 0x00, 0x80,   /* dark blue */
-	0x00, 0x80, 0x80,   /* dark cyan */
-	0x80, 0x00, 0x80,   /* dark magenta */
-	0x80, 0x80, 0x00,   /* dark yellow */
-	0xc0, 0xc0, 0xc0,   /* light gray */
-	0xff, 0xff, 0xff,   /* white */
+	unsigned int i;
+	unsigned char RGB[] = {
+		0x00, 0x00, 0x00,	/* black */
+		0x80, 0x80, 0x80,	/* gray */
+		0xff, 0x00, 0x00,	/* red */
+		0x00, 0xff, 0x00,	/* green */
+		0x00, 0x00, 0xff,	/* blue */
+		0x00, 0xff, 0xff,	/* cyan */
+		0xff, 0x00, 0xff,	/* magenta */
+		0xff, 0xff, 0x00,	/* yellow */
+		0x80, 0x00, 0x00,	/* dark red */
+		0x00, 0x80, 0x00,	/* dark green */
+		0x00, 0x00, 0x80,	/* dark blue */
+		0x00, 0x80, 0x80,	/* dark cyan */
+		0x80, 0x00, 0x80,	/* dark magenta */
+		0x80, 0x80, 0x00,	/* dark yellow */
+		0xc0, 0xc0, 0xc0,	/* light gray */
+		0xff, 0xff, 0xff,	/* white */
 	};
 
-    switch (clut_type)
-    {
-    case 1:
-	for (i=0; i<240; i++)
-	    video_set_lut (i, i, i, i);
-	for (i=0; i<16; i++)
-	    video_set_lut (i+240, RGB[i*3], RGB[i*3+1], RGB[i*3+2]);
-	break;
-    default:
-	for (i=0; i<256; i++)
-	    video_set_lut (i, i, i, i);
-    }
+	switch (clut_type) {
+	case 1:
+		for (i = 0; i < 240; i++)
+			video_set_lut (i, i, i, i);
+		for (i = 0; i < 16; i++)
+			video_set_lut (i + 240, RGB[i * 3], RGB[i * 3 + 1],
+				       RGB[i * 3 + 2]);
+		break;
+	default:
+		for (i = 0; i < 256; i++)
+			video_set_lut (i, i, i, i);
+	}
 }
 
 /* ------------------------------------------------------------------------- */
 
 void *video_hw_init (void)
 {
-    unsigned int clut = 0;
-    unsigned char *penv;
-    immap_t *immr = (immap_t *) CFG_IMMR;
+	unsigned int clut = 0;
+	unsigned char *penv;
+	immap_t *immr = (immap_t *) CFG_IMMR;
 
-    /* enable video only on CLUT value */
-    if ((penv = getenv ("clut")) != NULL)
-	clut = (u_int)simple_strtoul (penv, NULL, 10);
-    else
-	return NULL;
+	/* enable video only on CLUT value */
+	if ((penv = getenv ("clut")) != NULL)
+		clut = (u_int) simple_strtoul (penv, NULL, 10);
+	else
+		return NULL;
 
-    /* disable graphic before write LCD regs. */
-    immr->im_lcd.lcd_lccr = 0x96000866;
+	/* disable graphic before write LCD regs. */
+	immr->im_lcd.lcd_lccr = 0x96000866;
 
-    /* config LCD regs. */
-    immr->im_lcd.lcd_lcfaa = LCD_VIDEO_ADDR;
-    immr->im_lcd.lcd_lchcr = 0x010a0093;
-    immr->im_lcd.lcd_lcvcr = 0x900f0024;
+	/* config LCD regs. */
+	immr->im_lcd.lcd_lcfaa = LCD_VIDEO_ADDR;
+	immr->im_lcd.lcd_lchcr = 0x010a0093;
+	immr->im_lcd.lcd_lcvcr = 0x900f0024;
 
-    printf ("Video: 640x480 8Bit Index Lut %s\n",
-	    (clut==1?"240/16 (gray/vga)":"256(gray)"));
+	printf ("Video: 640x480 8Bit Index Lut %s\n",
+		(clut == 1 ? "240/16 (gray/vga)" : "256(gray)"));
 
-    video_default_lut (clut);
+	video_default_lut (clut);
 
-    /* clear framebuffer */
-    memset ( (char*)(LCD_VIDEO_ADDR), LCD_VIDEO_BG, LCD_VIDEO_ROWS*LCD_VIDEO_COLS );
+	/* clear framebuffer */
+	memset ((char *) (LCD_VIDEO_ADDR), LCD_VIDEO_BG,
+		LCD_VIDEO_ROWS * LCD_VIDEO_COLS);
 
-    /* enable graphic */
-    immr->im_lcd.lcd_lccr = 0x96000867;
+	/* enable graphic */
+	immr->im_lcd.lcd_lccr = 0x96000867;
 
-    /* fill in Graphic Device */
-    gdev.frameAdrs = LCD_VIDEO_ADDR;
-    gdev.winSizeX = LCD_VIDEO_COLS;
-    gdev.winSizeY = LCD_VIDEO_ROWS;
-    gdev.gdfBytesPP = 1;
-    gdev.gdfIndex = GDF__8BIT_INDEX;
+	/* fill in Graphic Device */
+	gdev.frameAdrs = LCD_VIDEO_ADDR;
+	gdev.winSizeX = LCD_VIDEO_COLS;
+	gdev.winSizeY = LCD_VIDEO_ROWS;
+	gdev.gdfBytesPP = 1;
+	gdev.gdfIndex = GDF__8BIT_INDEX;
 
-    if (clut > 1)
-	/* return Graphic Device for console */
-	return (void *)&gdev;
-    else
-	/* just graphic enabled - draw something beautiful */
-	video_test_image();
+	if (clut > 1)
+		/* return Graphic Device for console */
+		return (void *) &gdev;
+	else
+		/* just graphic enabled - draw something beautiful */
+		video_test_image ();
 
-    return NULL;            /* this disabels cfb - console */
+	return NULL;		/* this disabels cfb - console */
 }
 
 /* ------------------------------------------------------------------------- */
@@ -465,13 +469,15 @@ void *video_hw_init (void)
 void video_set_lut (unsigned int index,
 		    unsigned char r, unsigned char g, unsigned char b)
 {
-    unsigned int lum;
-    unsigned short *pLut = (unsigned short *)(CFG_IMMR + 0x0e00);
+	unsigned int lum;
+	unsigned short *pLut = (unsigned short *) (CFG_IMMR + 0x0e00);
 
-    /* 16 bit lut values, 12 bit used, xxxx BBGG RRii iiii */
-    /* y = 0.299*R + 0.587*G + 0.114*B */
-    lum = (2990*r + 5870*g + 1140*b)/10000;
-    pLut[index] = ((b & 0xc0)<<4) | ((g & 0xc0)<<2) | (r & 0xc0) | (lum & 0x3f);
+	/* 16 bit lut values, 12 bit used, xxxx BBGG RRii iiii */
+	/* y = 0.299*R + 0.587*G + 0.114*B */
+	lum = (2990 * r + 5870 * g + 1140 * b) / 10000;
+	pLut[index] =
+		((b & 0xc0) << 4) | ((g & 0xc0) << 2) | (r & 0xc0) | (lum &
+								      0x3f);
 }
 
 /* ------------------------------------------------------------------------- */

board/emk/common/flash.c

@@ -28,15 +28,53 @@
 
 flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
-typedef unsigned char FLASH_PORT_WIDTH;
-typedef volatile unsigned char FLASH_PORT_WIDTHV;
-#define	FLASH_ID_MASK	0xFF
+#if defined (CONFIG_TOP860)
+  typedef unsigned short FLASH_PORT_WIDTH;
+  typedef volatile unsigned short FLASH_PORT_WIDTHV;
+  #define	FLASH_ID_MASK	0xFF
 
-#define FPW	FLASH_PORT_WIDTH
-#define FPWV	FLASH_PORT_WIDTHV
+  #define FPW	FLASH_PORT_WIDTH
+  #define FPWV	FLASH_PORT_WIDTHV
 
-#define FLASH_CYCLE1	0x0aaa
-#define FLASH_CYCLE2	0x0555
+  #define FLASH_CYCLE1	0x0555
+  #define FLASH_CYCLE2	0x02aa
+  #define FLASH_ID1		0
+  #define FLASH_ID2		1
+  #define FLASH_ID3		0x0e
+  #define FLASH_ID4		0x0F
+#endif
+
+#if defined (CONFIG_TOP5200) && !defined (CONFIG_LITE5200)
+  typedef unsigned char FLASH_PORT_WIDTH;
+  typedef volatile unsigned char FLASH_PORT_WIDTHV;
+  #define	FLASH_ID_MASK	0xFF
+
+  #define FPW	FLASH_PORT_WIDTH
+  #define FPWV	FLASH_PORT_WIDTHV
+
+  #define FLASH_CYCLE1	0x0aaa
+  #define FLASH_CYCLE2	0x0555
+  #define FLASH_ID1		0
+  #define FLASH_ID2		2
+  #define FLASH_ID3		0x1c
+  #define FLASH_ID4		0x1E
+#endif
+
+#if defined (CONFIG_TOP5200) && defined (CONFIG_LITE5200)
+  typedef unsigned char FLASH_PORT_WIDTH;
+  typedef volatile unsigned char FLASH_PORT_WIDTHV;
+  #define	FLASH_ID_MASK	0xFF
+
+  #define FPW	FLASH_PORT_WIDTH
+  #define FPWV	FLASH_PORT_WIDTHV
+
+  #define FLASH_CYCLE1	0x0555
+  #define FLASH_CYCLE2	0x02aa
+  #define FLASH_ID1		0
+  #define FLASH_ID2		1
+  #define FLASH_ID3		0x0E
+  #define FLASH_ID4		0x0F
+#endif
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -165,6 +203,15 @@ void flash_print_info (flash_info_t *info)
 	case FLASH_AM160B:
 		fmt = "29LV160%s (16 Mbit, %s)\n";
 		break;
+	case FLASH_AMLV640U:
+		fmt = "29LV640M (64 Mbit)\n";
+		break;
+	case FLASH_AMDLV065D:
+		fmt = "29LV065D (64 Mbit)\n";
+		break;
+	case FLASH_AMLV256U:
+		fmt = "29LV256M (256 Mbit)\n";
+		break;
 	default:
 		fmt = "Unknown Chip Type\n";
 		break;
@@ -179,12 +226,33 @@ void flash_print_info (flash_info_t *info)
 	printf ("  Sector Start Addresses:");
 
 	for (i=0; i<info->sector_count; ++i) {
+		ulong	size;
+		int		erased;
+		ulong	*flash = (unsigned long *) info->start[i];
+
 		if ((i % 5) == 0) {
 			printf ("\n   ");
 		}
 
-		printf (" %08lX%s", info->start[i],
-			info->protect[i] ? " (RO)" : "     ");
+		/*
+		 * Check if whole sector is erased
+		 */
+		size =
+			(i != (info->sector_count - 1)) ?
+			(info->start[i + 1] - info->start[i]) >> 2 :
+		(info->start[0] + info->size - info->start[i]) >> 2;
+
+		for (
+			flash = (unsigned long *) info->start[i], erased = 1;
+				(flash != (unsigned long *) info->start[i] + size) && erased;
+					flash++
+			)
+			erased = *flash == ~0x0UL;
+
+		printf (" %08lX %s %s",
+			info->start[i],
+			erased ? "E": " ",
+			info->protect[i] ? "(RO)" : "    ");
 	}
 
 	printf ("\n");
@@ -200,7 +268,6 @@ void flash_print_info (flash_info_t *info)
 ulong flash_get_size (FPWV *addr, flash_info_t *info)
 {
 	int		i;
-	ulong	offset;
 
 	/* Write auto select command: read Manufacturer ID */
 	/* Write auto select command sequence and test FLASH answer */
@@ -212,7 +279,7 @@ ulong flash_get_size (FPWV *addr, flash_info_t *info)
 	 * This works for any bus width and any FLASH device width.
 	 */
 	udelay(100);
-	switch (addr[0] & 0xff) {
+	switch (addr[FLASH_ID1] & 0xff) {
 
 	case (uchar)AMD_MANUFACT:
 		info->flash_id = FLASH_MAN_AMD;
@@ -225,7 +292,7 @@ ulong flash_get_size (FPWV *addr, flash_info_t *info)
 #endif
 
 	default:
-		printf ("unknown vendor=%x ", addr[0] & 0xff);
+		printf ("unknown vendor=%x ", addr[FLASH_ID1] & 0xff);
 		info->flash_id = FLASH_UNKNOWN;
 		info->sector_count = 0;
 		info->size = 0;
@@ -233,33 +300,70 @@ ulong flash_get_size (FPWV *addr, flash_info_t *info)
 	}
 
 	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
-	if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[2]) {
+	if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[FLASH_ID2]) {
 
 	case (FPW)AMD_ID_LV160B:
 		info->flash_id += FLASH_AM160B;
 		info->sector_count = 35;
 		info->size = 0x00200000;
-#ifdef CFG_LOWBOOT
-		offset = 0;
-#else
-		offset = 0x00e00000;
-#endif
-		info->start[0] = (ulong)addr + offset;
-		info->start[1] = (ulong)addr + offset + 0x4000;
-		info->start[2] = (ulong)addr + offset + 0x6000;
-		info->start[3] = (ulong)addr + offset + 0x8000;
+		info->start[0] = (ulong)addr;
+		info->start[1] = (ulong)addr + 0x4000;
+		info->start[2] = (ulong)addr + 0x6000;
+		info->start[3] = (ulong)addr + 0x8000;
 		for (i = 4; i < info->sector_count; i++)
 		{
-			info->start[i] = (ulong)addr + offset + 0x10000 * (i-3);
+			info->start[i] = (ulong)addr + 0x10000 * (i-3);
 		}
 		break;
 
+	case (FPW)AMD_ID_LV065D:
+		info->flash_id += FLASH_AMDLV065D;
+		info->sector_count = 128;
+		info->size = 0x00800000;
+		for (i = 0; i < info->sector_count; i++)
+		{
+			info->start[i] = (ulong)addr + 0x10000 * i;
+		}
+		break;
+
+	case (FPW)AMD_ID_MIRROR:
+		/* MIRROR BIT FLASH, read more ID bytes */
+		if ((FPW)addr[FLASH_ID3] == (FPW)AMD_ID_LV640U_2 &&
+			(FPW)addr[FLASH_ID4] == (FPW)AMD_ID_LV640U_3)
+		{
+			info->flash_id += FLASH_AMLV640U;
+			info->sector_count = 128;
+			info->size = 0x00800000;
+			for (i = 0; i < info->sector_count; i++)
+			{
+				info->start[i] = (ulong)addr + 0x10000 * i;
+			}
+			break;
+		}
+		if ((FPW)addr[FLASH_ID3] == (FPW)AMD_ID_LV256U_2 &&
+			(FPW)addr[FLASH_ID4] == (FPW)AMD_ID_LV256U_3)
+		{
+			/* attention: only the first 16 MB will be used in u-boot */
+			info->flash_id += FLASH_AMLV256U;
+			info->sector_count = 256;
+			info->size = 0x01000000;
+			for (i = 0; i < info->sector_count; i++)
+			{
+				info->start[i] = (ulong)addr + 0x10000 * i;
+			}
+			break;
+		}
+
+		/* fall thru to here ! */
 	default:
-		printf ("unknown AMD device=%x ", (FPW)addr[2]);
+		printf ("unknown AMD device=%x %x %x",
+			(FPW)addr[FLASH_ID2],
+			(FPW)addr[FLASH_ID3],
+			(FPW)addr[FLASH_ID4]);
 		info->flash_id = FLASH_UNKNOWN;
 		info->sector_count = 0;
-		info->size = 0;
-		return (0);			/* => no or unknown flash */
+		info->size = 0x800000;
+		break;
 	}
 
 	/* Put FLASH back in read mode */
@@ -290,6 +394,7 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 
 	switch (info->flash_id & FLASH_TYPEMASK) {
 	case FLASH_AM160B:
+	case FLASH_AMLV640U:
 		break;
 	case FLASH_UNKNOWN:
 	default:

board/emk/top5200/Makefile

@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= lib$(BOARD).a
 
-OBJS	:= $(BOARD).o flash.o
+OBJS	:= $(BOARD).o ../common/flash.o ../common/vpd.o ../common/am79c874.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS)

board/emk/top5200/flash.c

@@ -1,502 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2003
- * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
-
-typedef unsigned char FLASH_PORT_WIDTH;
-typedef volatile unsigned char FLASH_PORT_WIDTHV;
-#define	FLASH_ID_MASK	0xFF
-
-#define FPW	FLASH_PORT_WIDTH
-#define FPWV	FLASH_PORT_WIDTHV
-
-#define FLASH_CYCLE1	0x0aaa
-#define FLASH_CYCLE2	0x0555
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(FPWV *addr, flash_info_t *info);
-static void flash_reset(flash_info_t *info);
-static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
-static flash_info_t *flash_get_info(ulong base);
-
-/*-----------------------------------------------------------------------
- * flash_init()
- *
- * sets up flash_info and returns size of FLASH (bytes)
- */
-unsigned long flash_init (void)
-{
-	unsigned long size = 0;
-	int i = 0;
-	extern void flash_preinit(void);
-	extern void flash_afterinit(uint, ulong, ulong);
-	ulong flashbase = CFG_FLASH_BASE;
-
-	flash_preinit();
-
-	/* There is only ONE FLASH device */
-	memset(&flash_info[i], 0, sizeof(flash_info_t));
-	flash_info[i].size =
-			flash_get_size((FPW *)flashbase, &flash_info[i]);
-	size += flash_info[i].size;
-
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
-	/* monitor protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
-		      flash_get_info(CFG_MONITOR_BASE));
-#endif
-
-#ifdef	CFG_ENV_IS_IN_FLASH
-	/* ENV protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CFG_ENV_ADDR,
-		      CFG_ENV_ADDR+CFG_ENV_SIZE-1,
-		      flash_get_info(CFG_ENV_ADDR));
-#endif
-
-
-	flash_afterinit(i, flash_info[i].start[0], flash_info[i].size);
-	return size ? size : 1;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_reset(flash_info_t *info)
-{
-	FPWV *base = (FPWV *)(info->start[0]);
-
-	/* Put FLASH back in read mode */
-	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
-		*base = (FPW)0x00FF00FF;	/* Intel Read Mode */
-	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
-		*base = (FPW)0x00F000F0;	/* AMD Read Mode */
-}
-
-/*-----------------------------------------------------------------------
- */
-
-static flash_info_t *flash_get_info(ulong base)
-{
-	int i;
-	flash_info_t * info;
-
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
-		info = & flash_info[i];
-		if (info->size &&
-			info->start[0] <= base && base <= info->start[0] + info->size - 1)
-			break;
-	}
-
-	return i == CFG_MAX_FLASH_BANKS ? 0 : info;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-void flash_print_info (flash_info_t *info)
-{
-	int i;
-	uchar *boottype;
-	uchar *bootletter;
-	uchar *fmt;
-	uchar botbootletter[] = "B";
-	uchar topbootletter[] = "T";
-	uchar botboottype[] = "bottom boot sector";
-	uchar topboottype[] = "top boot sector";
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:	printf ("AMD ");		break;
-#if 0
-	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
-	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
-	case FLASH_MAN_SST:	printf ("SST ");		break;
-	case FLASH_MAN_STM:	printf ("STM ");		break;
-	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
-#endif
-	default:		printf ("Unknown Vendor ");	break;
-	}
-
-	/* check for top or bottom boot, if it applies */
-	if (info->flash_id & FLASH_BTYPE) {
-		boottype = botboottype;
-		bootletter = botbootletter;
-	}
-	else {
-		boottype = topboottype;
-		bootletter = topbootletter;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AM160T:
-	case FLASH_AM160B:
-		fmt = "29LV160%s (16 Mbit, %s)\n";
-		break;
-	case FLASH_AMDLV065D:
-		fmt = "29LV065 (64 Mbit, uniform sectors)\n";
-		break;
-	default:
-		fmt = "Unknown Chip Type\n";
-		break;
-	}
-
-	printf (fmt, bootletter, boottype);
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20,
-		info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-
-	for (i=0; i<info->sector_count; ++i) {
-		if ((i % 5) == 0) {
-			printf ("\n   ");
-		}
-
-		printf (" %08lX%s", info->start[i],
-			info->protect[i] ? " (RO)" : "     ");
-	}
-
-	printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-ulong flash_get_size (FPWV *addr, flash_info_t *info)
-{
-	int		i;
-	ulong	offset;
-
-	/* Write auto select command: read Manufacturer ID */
-	/* Write auto select command sequence and test FLASH answer */
-	addr[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* for AMD, Intel ignores this */
-	addr[FLASH_CYCLE2] = (FPW)0x00550055;	/* for AMD, Intel ignores this */
-	addr[FLASH_CYCLE1] = (FPW)0x00900090;	/* selects Intel or AMD */
-
-	/* The manufacturer codes are only 1 byte, so just use 1 byte.
-	 * This works for any bus width and any FLASH device width.
-	 */
-	udelay(100);
-	switch (addr[0] & 0xff) {
-
-	case (uchar)AMD_MANUFACT:
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-
-#if 0
-	case (uchar)INTEL_MANUFACT:
-		info->flash_id = FLASH_MAN_INTEL;
-		break;
-#endif
-
-	default:
-		printf ("unknown vendor=%x ", addr[0] & 0xff);
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		break;
-	}
-
-	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
-	if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[2]) {
-
-	case (FPW)AMD_ID_LV160B:
-		info->flash_id += FLASH_AM160B;
-		info->sector_count = 35;
-		info->size = 0x00200000;
-#ifdef CFG_LOWBOOT
-		offset = 0;
-#else
-		offset = 0x00e00000;
-#endif
-		info->start[0] = (ulong)addr + offset;
-		info->start[1] = (ulong)addr + offset + 0x4000;
-		info->start[2] = (ulong)addr + offset + 0x6000;
-		info->start[3] = (ulong)addr + offset + 0x8000;
-		for (i = 4; i < info->sector_count; i++)
-		{
-			info->start[i] = (ulong)addr + offset + 0x10000 * (i-3);
-		}
-		break;
-
-	case (FPW)AMD_ID_LV065D:
-		info->flash_id += FLASH_AMDLV065D;
-		info->sector_count = 128;
-		info->size = 0x00800000;
-#ifdef CFG_LOWBOOT
-		offset = 0;
-#else
-		offset = 0x00800000;
-#endif
-		for( i = 0; i < info->sector_count; i++ )
-			info->start[i] = (ulong)addr + offset + (i * 0x10000);
-		break;				/* => 8 or 16 MB	*/
-
-	default:
-		printf ("unknown AMD device=%x ", (FPW)addr[2]);
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		return (0);			/* => no or unknown flash */
-	}
-
-	/* Put FLASH back in read mode */
-	flash_reset(info);
-
-	return (info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-	FPWV *addr;
-	int flag, prot, sect;
-	int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
-	ulong start, now, last;
-	int rcode = 0;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AMDLV065D:
-		break;
-	case FLASH_UNKNOWN:
-	default:
-		printf ("Can't erase unknown flash type %08lx - aborted\n",
-			info->flash_id);
-		return 1;
-	}
-
-	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-	last  = get_timer(0);
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
-
-		if (info->protect[sect] != 0)	/* protected, skip it */
-			continue;
-
-		/* Disable interrupts which might cause a timeout here */
-		flag = disable_interrupts();
-
-		addr = (FPWV *)(info->start[sect]);
-		if (intel) {
-			*addr = (FPW)0x00500050; /* clear status register */
-			*addr = (FPW)0x00200020; /* erase setup */
-			*addr = (FPW)0x00D000D0; /* erase confirm */
-		}
-		else {
-			/* must be AMD style if not Intel */
-			FPWV *base;		/* first address in bank */
-
-			base = (FPWV *)(info->start[0]);
-			base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
-			base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
-			base[FLASH_CYCLE1] = (FPW)0x00800080;	/* erase mode */
-			base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
-			base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
-			*addr = (FPW)0x00300030;	/* erase sector */
-		}
-
-		/* re-enable interrupts if necessary */
-		if (flag)
-			enable_interrupts();
-
-		start = get_timer(0);
-
-		/* wait at least 50us for AMD, 80us for Intel.
-		 * Let's wait 1 ms.
-		 */
-		udelay (1000);
-
-		while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
-			if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
-				printf ("Timeout\n");
-
-				if (intel) {
-					/* suspend erase	*/
-					*addr = (FPW)0x00B000B0;
-				}
-
-				flash_reset(info);	/* reset to read mode */
-				rcode = 1;		/* failed */
-				break;
-			}
-
-			/* show that we're waiting */
-			if ((get_timer(last)) > CFG_HZ) {/* every second */
-				putc ('.');
-				last = get_timer(0);
-			}
-		}
-
-		/* show that we're waiting */
-		if ((get_timer(last)) > CFG_HZ) {	/* every second */
-			putc ('.');
-			last = get_timer(0);
-		}
-
-		flash_reset(info);	/* reset to read mode	*/
-	}
-
-	printf (" done\n");
-	return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
-	int bytes;	  /* number of bytes to program in current word		*/
-	int left;	  /* number of bytes left to program			*/
-	int i, res;
-
-	for (left = cnt, res = 0;
-		 left > 0 && res == 0;
-		 addr += sizeof(data), left -= sizeof(data) - bytes) {
-
-		bytes = addr & (sizeof(data) - 1);
-		addr &= ~(sizeof(data) - 1);
-
-		/* combine source and destination data so can program
-		 * an entire word of 16 or 32 bits
-		 */
-		for (i = 0; i < sizeof(data); i++) {
-			data <<= 8;
-			if (i < bytes || i - bytes >= left )
-				data += *((uchar *)addr + i);
-			else
-				data += *src++;
-		}
-
-		/* write one word to the flash */
-		switch (info->flash_id & FLASH_VENDMASK) {
-		case FLASH_MAN_AMD:
-			res = write_word_amd(info, (FPWV *)addr, data);
-			break;
-		default:
-			/* unknown flash type, error! */
-			printf ("missing or unknown FLASH type\n");
-			res = 1;	/* not really a timeout, but gives error */
-			break;
-		}
-	}
-
-	return (res);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash for AMD FLASH
- * A word is 16 or 32 bits, whichever the bus width of the flash bank
- * (not an individual chip) is.
- *
- * returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
-{
-	ulong start;
-	int flag;
-	int res = 0;	/* result, assume success	*/
-	FPWV *base;		/* first address in flash bank	*/
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*dest & data) != data) {
-		return (2);
-	}
-
-
-	base = (FPWV *)(info->start[0]);
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
-	base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
-	base[FLASH_CYCLE1] = (FPW)0x00A000A0;	/* selects program mode */
-
-	*dest = data;		/* start programming the data	*/
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	start = get_timer (0);
-
-	/* data polling for D7 */
-	while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
-			*dest = (FPW)0x00F000F0;	/* reset bank */
-			res = 1;
-		}
-	}
-
-	return (res);
-}

board/emk/top5200/top5200.c

@@ -57,7 +57,7 @@ long int initdram (int board_type)
 	*(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN;
 	/* precharge all banks */
 	*(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_PRE;
-#if CFG_DRAM_DDR
+#ifdef CFG_DRAM_DDR
 	/* set extended mode register */
 	*(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_EMODE;
 #endif
@@ -113,11 +113,15 @@ int checkboard (void)
 #if defined (CONFIG_EVAL5200)
 	puts ("Board: EMK TOP5200 on EVAL5200\n");
 #else
+#if defined (CONFIG_LITE5200)
+	puts ("Board: LITE5200\n");
+#else
 #if defined (CONFIG_MINI5200)
 	puts ("Board: EMK TOP5200 on MINI5200\n");
 #else
 	puts ("Board: EMK TOP5200\n");
 #endif
+#endif
 #endif
 	return 0;
 }
@@ -155,54 +159,11 @@ void flash_afterinit(uint bank, ulong start, ulong size)
  *****************************************************************************/
 int misc_init_r (void)
 {
+#if !defined (CONFIG_LITE5200)
 	/* read 'factory' part of EEPROM */
-	uchar buf[81];
-	uchar *p;
-	uint length;
-	uint addr;
-	uint len;
-
-	/* get length first */
-	addr = CFG_FACT_OFFSET;
-	if (eeprom_read (CFG_I2C_FACT_ADDR, addr, buf, 2)) {
-bailout:
-		printf ("cannot read factory configuration\n");
-		printf ("be sure to set ethaddr	yourself!\n");
-		return 0;
-	}
-	length = buf[0] + (buf[1] << 8);
-	addr += 2;
-
-	/* sanity check */
-	if (length < 20 || length > CFG_FACT_SIZE - 2)
-		goto bailout;
-
-	/* read lines */
-	while (length > 0) {
-		/* read one line */
-		len = length > 80 ? 80 : length;
-		if (eeprom_read (CFG_I2C_FACT_ADDR, addr, buf, len))
-			goto bailout;
-		/* mark end of buffer */
-		buf[len] = 0;
-		/* search end of line */
-		for (p = buf; *p && *p != 0x0a; p++);
-		if (!*p)
-			goto bailout;
-		*p++ = 0;
-		/* advance to next line start */
-		length -= p - buf;
-		addr += p - buf;
-		/*printf ("%s\n", buf); */
-		/* search for our specific entry */
-		if (!strncmp ((char *) buf, "[RLA/lan/Ethernet] ", 19)) {
-			setenv ("ethaddr", buf + 19);
-		} else if (!strncmp ((char *) buf, "[BOARD/SERIAL] ", 15)) {
-			setenv ("serial#", buf + 15);
-		} else if (!strncmp ((char *) buf, "[BOARD/TYPE] ", 13)) {
-			setenv ("board_id", buf + 13);
-		}
-	}
+	extern void read_factory_r (void);
+	read_factory_r ();
+#endif
 	return (0);
 }
 
@@ -219,3 +180,31 @@ void pci_init_board(void)
 	pci_mpc5xxx_init(&hose);
 }
 #endif
+
+/*****************************************************************************
+ * provide the IDE Reset Function
+ *****************************************************************************/
+#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+
+#define GPIO_PSC1_4	0x01000000UL
+
+void init_ide_reset (void)
+{
+	debug ("init_ide_reset\n");
+
+    	/* Configure PSC1_4 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
+}
+
+void ide_set_reset (int idereset)
+{
+	debug ("ide_reset(%d)\n", idereset);
+
+	if (idereset) {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
+	} else {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA |=  GPIO_PSC1_4;
+	}
+}
+#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */

board/emk/top860/Makefile

@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= lib$(BOARD).a
 
-OBJS	= $(BOARD).o flash.o
+OBJS	= $(BOARD).o ../common/flash.o ../common/vpd.o ../common/am79c874.o
 
 $(LIB):	.depend $(OBJS)
 	$(AR) crv $@ $(OBJS)

board/emk/top860/flash.c

@@ -1,489 +0,0 @@
-/*
- * (C) Copyright 2003
- * EMK Elektronik GmbH <www.emk-elektronik.de>
- * Reinhard Meyer <r.meyer@emk-elektronik.de>
- *
- * copied from the BMW Port - seems that its similiar enough
- * to be easily adaped ;) --- Well, it turned out to become a
- * merger between parts of the EMKstax Flash routines and the
- * BMW funtion frames...
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-#define	FLASH_WORD_SIZE		unsigned short
-#define FLASH_WORD_WIDTH	(sizeof (FLASH_WORD_SIZE))
-
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips    */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-
-
-/*****************************************************************************
- * software product ID entry/exit
- *****************************************************************************/
-static void FlashProductIdMode (
-	volatile FLASH_WORD_SIZE *b,
-	int on_off)
-{
-	b[0x5555] = 0xaa;
-	b[0x2aaa] = 0x55;
-	b[0x5555] = on_off ? 0x90 : 0xf0;
-}
-
-/*****************************************************************************
- * sector erase start
- *****************************************************************************/
-static void FlashSectorErase (
-	volatile FLASH_WORD_SIZE *b,
-	volatile FLASH_WORD_SIZE *a)
-{
-	b[0x5555] = 0xaa;
-	b[0x2aaa] = 0x55;
-	b[0x5555] = 0x80;
-	b[0x5555] = 0xaa;
-	b[0x2aaa] = 0x55;
-	a[0] = 0x30;
-}
-
-/*****************************************************************************
- * program a word
- *****************************************************************************/
-static void FlashProgWord (
-	volatile FLASH_WORD_SIZE *b,
-	volatile FLASH_WORD_SIZE *a,
-	FLASH_WORD_SIZE v)
-{
-	b[0x5555] = 0xaa;
-	b[0x2aaa] = 0x55;
-	b[0x5555] = 0xa0;
-	a[0] = v;
-}
-
-/*****************************************************************************
- * reset bank, back to read mode
- *****************************************************************************/
-static void FlashReset (volatile FLASH_WORD_SIZE *b)
-{
-	b[0] = 0xf0;
-}
-
-/*****************************************************************************
- * identify FLASH chip
- * this code is a stripped version of the FlashGetType() function in EMKstax
- *****************************************************************************/
-unsigned long flash_init (void)
-{
-	volatile FLASH_WORD_SIZE * const flash = (volatile FLASH_WORD_SIZE *) CFG_FLASH_BASE;
-	FLASH_WORD_SIZE	manu, dev;
-	flash_info_t * const pflinfo = &flash_info[0];
-	int j;
-
-	/* get Id Bytes */
-	FlashProductIdMode (flash, 1);
-	manu = flash[0];
-	dev  = flash[1];
-	FlashProductIdMode (flash, 0);
-
-	pflinfo->size = 0;
-	pflinfo->sector_count = 0;
-	pflinfo->flash_id = 0xffffffff;
-	pflinfo->portwidth = FLASH_CFI_16BIT;
-	pflinfo->chipwidth = FLASH_CFI_BY16;
-
-	switch (manu&0xff)
-	{
-	case 0x01:	/* AMD */
-		pflinfo->flash_id = FLASH_MAN_AMD;
-		switch (dev&0xff)
-		{
-		case 0x49:
-			pflinfo->size = 0x00200000;
-			pflinfo->sector_count = 35;
-			pflinfo->flash_id |= FLASH_AM160B;
-			pflinfo->start[0] = CFG_FLASH_BASE;
-			pflinfo->start[1] = CFG_FLASH_BASE + 0x4000;
-			pflinfo->start[2] = CFG_FLASH_BASE + 0x6000;
-			pflinfo->start[3] = CFG_FLASH_BASE + 0x8000;
-			for (j = 4; j < 35; j++)
-			{
-				pflinfo->start[j] = CFG_FLASH_BASE + 0x00010000 * (j-3);
-			}
-			break;
-
-		case 0xf9:
-			pflinfo->size = 0x00400000;
-			pflinfo->sector_count = 71;
-			pflinfo->flash_id |= FLASH_AM320B;
-			pflinfo->start[0] = CFG_FLASH_BASE;
-			pflinfo->start[1] = CFG_FLASH_BASE + 0x4000;
-			pflinfo->start[2] = CFG_FLASH_BASE + 0x6000;
-			pflinfo->start[3] = CFG_FLASH_BASE + 0x8000;
-			for (j = 0; j < 8; j++)
-			{
-				pflinfo->start[j] = CFG_FLASH_BASE + 0x00002000 * (j);
-			}
-			for (j = 8; j < 71; j++)
-			{
-				pflinfo->start[j] = CFG_FLASH_BASE + 0x00010000 * (j-7);
-			}
-			break;
-
-		default:
-			printf ("unknown AMD dev=%x ", dev);
-			pflinfo->flash_id |= FLASH_UNKNOWN;
-		}
-		break;
-
-	default:
-		printf ("unknown manu=%x ", manu);
-	}
-	return pflinfo->size;
-}
-
-/*****************************************************************************
- * print info about a FLASH
- *****************************************************************************/
-void flash_print_info (flash_info_t *info)
-{
-	static const char	unk[] = "Unknown";
-	unsigned int		i;
-	const char			*mfct=unk,
-						*type=unk;
-
-	if(info->flash_id != FLASH_UNKNOWN)
-	{
-		switch (info->flash_id & FLASH_VENDMASK)
-		{
-		case FLASH_MAN_AMD:
-			mfct = "AMD";
-			break;
-		}
-
-		switch (info->flash_id & FLASH_TYPEMASK)
-		{
-		case FLASH_AM160B:
-			type = "AM29LV160B (16 Mbit, bottom boot sect)";
-			break;
-		case FLASH_AM320B:
-			type = "AM29LV320B (32 Mbit, bottom boot sect)";
-			break;
-		}
-	}
-
-	printf (
-		"\n  Brand: %s Type: %s\n"
-		"  Size: %lu KB in %d Sectors\n",
-		mfct,
-		type,
-		info->size >> 10,
-		info->sector_count
-		);
-
-	printf ("  Sector Start Addresses:");
-
-	for (i = 0; i < info->sector_count; i++)
-	{
-		unsigned long	size;
-		unsigned int	erased;
-		unsigned long	*flash = (unsigned long *) info->start[i];
-
-		/*
-		 * Check if whole sector is erased
-		 */
-		size =
-			(i != (info->sector_count - 1)) ?
-			(info->start[i + 1] - info->start[i]) >> 2 :
-		(info->start[0] + info->size - info->start[i]) >> 2;
-
-		for (
-			flash = (unsigned long *) info->start[i], erased = 1;
-				(flash != (unsigned long *) info->start[i] + size) && erased;
-					flash++
-			)
-			erased = *flash == ~0x0UL;
-
-		printf (
-			"%s %08lX %s %s",
-			(i % 5) ? "" : "\n   ",
-			info->start[i],
-			erased ? "E" : " ",
-			info->protect[i] ? "RO" : "  "
-			);
-	}
-
-	puts ("\n");
-	return;
-}
-
-/*****************************************************************************
- * erase one or more sectors
- *****************************************************************************/
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-	volatile FLASH_WORD_SIZE	*addr = (FLASH_WORD_SIZE *)(info->start[0]);
-	int							flag,
-								prot,
-								sect,
-								l_sect;
-	ulong						start,
-								now,
-								last;
-
-	if ((s_first < 0) || (s_first > s_last))
-	{
-		if (info->flash_id == FLASH_UNKNOWN)
-		{
-			printf ("- missing\n");
-		}
-		else
-		{
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	if ((info->flash_id == FLASH_UNKNOWN) ||
-		(info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP)))
-	{
-		printf ("Can't erase unknown flash type - aborted\n");
-		return 1;
-	}
-
-	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect)
-	{
-		if (info->protect[sect])
-		{
-			prot++;
-		}
-	}
-
-	if (prot)
-	{
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	}
-	else
-	{
-		printf ("\n");
-	}
-
-	l_sect = -1;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last; sect++)
-	{
-		if (info->protect[sect] == 0)
-		{ /* not protected */
-			FlashSectorErase ((FLASH_WORD_SIZE *)info->start[0], (FLASH_WORD_SIZE *)info->start[sect]);
-			l_sect = sect;
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay (1000);
-
-	/*
-	* We wait for the last triggered sector
-	*/
-	if (l_sect < 0)
-		goto DONE;
-
-	start = get_timer (0);
-	last  = start;
-	addr = (FLASH_WORD_SIZE *)info->start[l_sect];
-	while ((addr[0] & 0x0080) != 0x0080)
-	{
-		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT)
-		{
-			printf ("Timeout\n");
-			return 1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000)
-		{  /* every second */
-			serial_putc ('.');
-			last = now;
-		}
-	}
-
-	DONE:
-	/* reset to read mode */
-	FlashReset ((FLASH_WORD_SIZE *)info->start[0]);
-
-	printf (" done\n");
-	return 0;
-}
-
-/*****************************************************************************
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- *****************************************************************************/
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	ulong		cp,
-				wp,
-				data;
-	int			i,
-				l,
-				rc;
-
-	wp = (addr & ~(FLASH_WORD_WIDTH-1));   /* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes, if there are...
-	 */
-	if ((l = addr - wp) != 0)
-	{
-		data = 0;
-
-		/* get the current before the new data into our data word */
-		for (i=0, cp=wp; i<l; ++i, ++cp)
-		{
-			data = (data << 8) | (*(uchar *)cp);
-		}
-
-		/* now merge the to be programmed values */
-		for (; i<4 && cnt>0; ++i, ++cp, --cnt)
-		{
-			data = (data << 8) | *src++;
-		}
-
-		/* get the current after the new data into our data word */
-		for (; cnt==0 && i<FLASH_WORD_WIDTH; ++i, ++cp)
-		{
-			data = (data << 8) | (*(uchar *)cp);
-		}
-
-		/* now write the combined word */
-		if ((rc = write_word (info, wp, data)) != 0)
-		{
-			return (rc);
-		}
-		wp += FLASH_WORD_WIDTH;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= FLASH_WORD_WIDTH)
-	{
-		data = 0;
-		for (i=0; i<FLASH_WORD_WIDTH; ++i)
-		{
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_word (info, wp, data)) != 0)
-		{
-			return (rc);
-		}
-		wp  += FLASH_WORD_WIDTH;
-		cnt -= FLASH_WORD_WIDTH;
-	}
-
-	if (cnt == 0)
-	{
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes, if there are...
-	 */
-	data = 0;
-
-	/* now merge the to be programmed values */
-	for (i=0, cp=wp; i<FLASH_WORD_WIDTH && cnt>0; ++i, ++cp)
-	{
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-
-	/* get the current after the new data into our data word */
-	for (; i<FLASH_WORD_WIDTH; ++i, ++cp)
-	{
-		data = (data << 8) | (*(uchar *)cp);
-	}
-
-	/* now write the combined word */
-	return (write_word (info, wp, data));
-}
-
-/*****************************************************************************
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- *****************************************************************************/
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
-	volatile FLASH_WORD_SIZE	*addr2 = (FLASH_WORD_SIZE *)info->start[0];
-	volatile FLASH_WORD_SIZE	*dest2 = (FLASH_WORD_SIZE *)dest;
-	FLASH_WORD_SIZE				data2 = data;
-	ulong						start;
-	int							flag;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*dest2 & data2) != data2)
-	{
-		return (2);
-	}
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	FlashProgWord (addr2, dest2, data2);
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts ();
-
-	/* data polling for D7 */
-	start = get_timer (0);
-	while ((*dest2 & 0x0080) != (data2 & 0x0080))
-	{
-		if (get_timer (start) > CFG_FLASH_WRITE_TOUT)
-		{
-			return (1);
-		}
-	}
-
-	return (0);
-}
-
-/*-----------------------------------------------------------------------
- */

board/emk/top860/top860.c

@@ -119,6 +119,20 @@ long int initdram (int board_type)
 	return -(memctl->memc_or2 & 0xffff0000);
 }
 
+/*****************************************************************************
+ * prepare for FLASH detection
+ *****************************************************************************/
+void flash_preinit(void)
+{
+}
+
+/*****************************************************************************
+ * finalize FLASH setup
+ *****************************************************************************/
+void flash_afterinit(uint bank, ulong start, ulong size)
+{
+}
+
 /*****************************************************************************
  * otherinits after RAM is there and we are relocated to RAM
  * note: though this is an int function, nobody cares for the result!
@@ -126,52 +140,8 @@ long int initdram (int board_type)
 int misc_init_r (void)
 {
 	/* read 'factory' part of EEPROM */
-	uchar buf[81];
-	uchar *p;
-	uint length;
-	uint addr;
-	uint len;
+	extern void read_factory_r (void);
+	read_factory_r ();
 
-	/* get length first */
-	addr = CFG_FACT_OFFSET;
-	if (eeprom_read (CFG_I2C_FACT_ADDR, addr, buf, 2)) {
-	  bailout:
-		printf ("cannot read factory configuration\n");
-		printf ("be sure to set ethaddr	yourself!\n");
-		return 0;
-	}
-	length = buf[0] + (buf[1] << 8);
-	addr += 2;
-
-	/* sanity check */
-	if (length < 20 || length > CFG_FACT_SIZE - 2)
-		goto bailout;
-
-	/* read lines */
-	while (length > 0) {
-		/* read one line */
-		len = length > 80 ? 80 : length;
-		if (eeprom_read (CFG_I2C_FACT_ADDR, addr, buf, len))
-			goto bailout;
-		/* mark end of buffer */
-		buf[len] = 0;
-		/* search end of line */
-		for (p = buf; *p && *p != 0x0a; p++);
-		if (!*p)
-			goto bailout;
-		*p++ = 0;
-		/* advance to next line start */
-		length -= p - buf;
-		addr += p - buf;
-		/*printf ("%s\n", buf); */
-		/* search for our specific entry */
-		if (!strncmp ((char *) buf, "[RLA/lan/Ethernet] ", 19)) {
-			setenv ("ethaddr", buf + 19);
-		} else if (!strncmp ((char *) buf, "[BOARD/SERIAL] ", 15)) {
-			setenv ("serial#", buf + 15);
-		} else if (!strncmp ((char *) buf, "[BOARD/TYPE] ", 13)) {
-			setenv ("board_id", buf + 13);
-		}
-	}
 	return (0);
 }

board/ep8260/ep8260.c

@@ -190,21 +190,22 @@ const iop_conf_t iop_conf_tab[4][32] = {
 */
 int board_early_init_f (void)
 {
-    volatile t_ep_regs *regs = (t_ep_regs*)CFG_REGS_BASE;
-    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
-    volatile memctl8260_t *memctl = &immap->im_memctl;
-    memctl->memc_br4 = CFG_BR4_PRELIM;
-    memctl->memc_or4 = CFG_OR4_PRELIM;
-    regs->bcsr1 = 0x62; /* to enable terminal on SMC1 */
-    regs->bcsr2 = 0x30;	/* enable NVRAM and writing FLASH */
-    return 0;
+	volatile t_ep_regs *regs = (t_ep_regs *) CFG_REGS_BASE;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+	memctl->memc_br4 = CFG_BR4_PRELIM;
+	memctl->memc_or4 = CFG_OR4_PRELIM;
+	regs->bcsr1 = 0x62;	/* to enable terminal on SMC1 */
+	regs->bcsr2 = 0x30;	/* enable NVRAM and writing FLASH */
+	return 0;
 }
 
-void
-reset_phy(void)
+void reset_phy (void)
 {
-    volatile t_ep_regs *regs = (t_ep_regs*)CFG_REGS_BASE;
-    regs->bcsr4 = 0xC0;
+	volatile t_ep_regs *regs = (t_ep_regs *) CFG_REGS_BASE;
+
+	regs->bcsr4 = 0xC0;
 }
 
 /*
@@ -213,15 +214,21 @@ reset_phy(void)
  * Thats why its a static interpretation ...
 */
 
-int
-checkboard(void)
+int checkboard (void)
 {
-	volatile t_ep_regs *regs = (t_ep_regs*)CFG_REGS_BASE;
-	uint major=0, minor=0;
+	volatile t_ep_regs *regs = (t_ep_regs *) CFG_REGS_BASE;
+	uint major = 0, minor = 0;
+
 	switch (regs->bcsr0) {
-		case 0x02: major = 1; break;
-		case 0x03: major = 1; minor = 1; break;
-		default: break;
+	case 0x02:
+		major = 1;
+		break;
+	case 0x03:
+		major = 1;
+		minor = 1;
+		break;
+	default:
+		break;
 	}
 	printf ("Board: Embedded Planet EP8260, Revision %d.%d\n",
 		major, minor);
@@ -232,13 +239,13 @@ checkboard(void)
 /* ------------------------------------------------------------------------- */
 
 
-long int
-initdram(int board_type)
+long int initdram (int board_type)
 {
-	volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 	volatile uchar c = 0;
-	volatile uchar *ramaddr = (uchar *)(CFG_SDRAM_BASE) + 0x110;
+	volatile uchar *ramaddr = (uchar *) (CFG_SDRAM_BASE) + 0x110;
+
 /*
 	ulong psdmr = CFG_PSDMR;
 #ifdef CFG_LSDRAM
@@ -288,7 +295,7 @@ initdram(int board_type)
 #ifndef CFG_RAMBOOT
 #ifdef CFG_LSDRAM
 	size += CFG_SDRAM1_SIZE;
-	ramaddr = (uchar *)(CFG_SDRAM1_BASE) + 0x8c;
+	ramaddr = (uchar *) (CFG_SDRAM1_BASE) + 0x8c;
 	memctl->memc_lsrt = CFG_LSRT;
 
 	memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_PREA;

board/esd/ar405/fpgadata.c

@@ -2747,4 +2747,4 @@
  0x05,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x01,0x07,0x03,0x02,0x02,0x02,0x04,
  0x02,0x01,0x04,0x02,0x01,0x02,0x01,0x02,0x01,0x01,0xe5,0x05,0x04,0x03,0x07,0xe5,
  0xe5,0x03,0x04,0x04,0x0b,0x02,0xe5,0x01,0xe5,0x01,0xe5,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

board/etin/debris/debris.c

@@ -24,6 +24,7 @@
 #include <common.h>
 #include <mpc824x.h>
 #include <pci.h>
+#include <i2c.h>
 
 int checkboard (void)
 {
@@ -52,28 +53,70 @@ int checkflash (void)
 
 long int initdram (int board_type)
 {
-	long size;
-#if 0
-	long new_bank0_end;
-	long mear1;
-	long emear1;
-#endif
+	int m, row, col, bank, i;
+	unsigned long start, end;
+	uint32_t mccr1;
+	uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
+	uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
+	uint8_t mber = 0;
 
-	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
 
-#if 0
-	new_bank0_end = size - 1;
-	mear1 = mpc824x_mpc107_getreg(MEAR1);
-	emear1 = mpc824x_mpc107_getreg(EMEAR1);
-	mear1 = (mear1  & 0xFFFFFF00) |
-		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
-	emear1 = (emear1 & 0xFFFFFF00) |
-		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
-	mpc824x_mpc107_setreg(MEAR1, mear1);
-	mpc824x_mpc107_setreg(EMEAR1, emear1);
-#endif
+	if (i2c_reg_read (0x50, 2) != 0x04) return 0;	/* Memory type */
+	m = i2c_reg_read (0x50, 5);	/* # of physical banks */
+	row = i2c_reg_read (0x50, 3);	/* # of rows */
+	col = i2c_reg_read (0x50, 4);	/* # of columns */
+	bank = i2c_reg_read (0x50, 17);	/* # of logical banks */
 
-	return (size);
+	CONFIG_READ_WORD(MCCR1, mccr1);
+	mccr1 &= 0xffff0000;
+
+	start = CFG_SDRAM_BASE;
+	end = start + (1 << (col + row + 3) ) * bank - 1;
+
+	for (i = 0; i < m; i++) {
+		mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
+		if (i < 4) {
+			msar1  |= ((start >> 20) & 0xff) << i * 8;
+			emsar1 |= ((start >> 28) & 0xff) << i * 8;
+			mear1  |= ((end >> 20) & 0xff) << i * 8;
+			emear1 |= ((end >> 28) & 0xff) << i * 8;
+		} else {
+			msar2  |= ((start >> 20) & 0xff) << (i-4) * 8;
+			emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
+			mear2  |= ((end >> 20) & 0xff) << (i-4) * 8;
+			emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
+		}
+		mber |= 1 << i;
+		start += (1 << (col + row + 3) ) * bank;
+		end += (1 << (col + row + 3) ) * bank;
+	}
+	for (; i < 8; i++) {
+		if (i < 4) {
+			msar1  |= 0xff << i * 8;
+			emsar1 |= 0x30 << i * 8;
+			mear1  |= 0xff << i * 8;
+			emear1 |= 0x30 << i * 8;
+		} else {
+			msar2  |= 0xff << (i-4) * 8;
+			emsar2 |= 0x30 << (i-4) * 8;
+			mear2  |= 0xff << (i-4) * 8;
+			emear2 |= 0x30 << (i-4) * 8;
+		}
+	}
+
+	CONFIG_WRITE_WORD(MCCR1, mccr1);
+	CONFIG_WRITE_WORD(MSAR1, msar1);
+	CONFIG_WRITE_WORD(EMSAR1, emsar1);
+	CONFIG_WRITE_WORD(MEAR1, mear1);
+	CONFIG_WRITE_WORD(EMEAR1, emear1);
+	CONFIG_WRITE_WORD(MSAR2, msar2);
+	CONFIG_WRITE_WORD(EMSAR2, emsar2);
+	CONFIG_WRITE_WORD(MEAR2, mear2);
+	CONFIG_WRITE_WORD(EMEAR2, emear2);
+	CONFIG_WRITE_BYTE(MBER, mber);
+
+	return (1 << (col + row + 3) ) * bank * m;
 }
 
 /*

board/evb64260/ecctest.c

@@ -1,91 +1,111 @@
+indent: Standard input:27: Warning:old style assignment ambiguity in "=*".  Assuming "= *"
+
 #ifdef ECC_TEST
-static inline void ecc_off(void)
+static inline void ecc_off (void)
 {
-	*(volatile int *)(INTERNAL_REG_BASE_ADDR+0x4b4) &= ~0x00200000;
+	*(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) &= ~0x00200000;
 }
 
-static inline void ecc_on(void)
+static inline void ecc_on (void)
 {
-	*(volatile int *)(INTERNAL_REG_BASE_ADDR+0x4b4) |= 0x00200000;
+	*(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) |= 0x00200000;
 }
 
-static int putshex(const char *buf, int len)
+static int putshex (const char *buf, int len)
 {
-    int i;
-    for (i=0;i<len;i++) {
-	printf("%02x", buf[i]);
-    }
-    return 0;
-}
+	int i;
 
-static int char_memcpy(void *d, const void *s, int len)
-{
-    int i;
-    char *cd=d;
-    const char *cs=s;
-    for(i=0;i<len;i++) {
-	*(cd++)=*(cs++);
-    }
-    return 0;
-}
-
-static int memory_test(char *buf)
-{
-    const char src[][16]={
-	{   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0},
-	{0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01},
-	{0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02},
-	{0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04},
-	{0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08},
-	{0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10},
-	{0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20},
-	{0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
-	{0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80},
-	{0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55},
-	{0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa},
-	{0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff}
-    };
-    const int foo[] = {0};
-    int i,j,a;
-
-    printf("\ntest @ %d %p\n", foo[0], buf);
-    for(i=0;i<12;i++) {
-	for(a=0;a<8;a++) {
-	    const char *s=src[i]+a;
-	    int align=(unsigned)(s)&0x7;
-	    /* ecc_off(); */
-	    memcpy(buf,s,8);
-	    /* ecc_on(); */
-	    putshex(s,8);
-	    if(memcmp(buf,s,8)) {
-		putc('\n');
-		putshex(buf,8);
-		printf(" [FAIL] (%p) align=%d\n", s, align);
-		for(j=0;j<8;j++) {
-		    s[j]==buf[j]?puts("  "):printf("%02x", (s[j])^(buf[j]));
-		}
-		putc('\n');
-	    } else {
-		printf(" [PASS] (%p) align=%d\n", s, align);
-	    }
-	    /* ecc_off(); */
-	    char_memcpy(buf,s,8);
-	    /* ecc_on(); */
-	    putshex(s,8);
-	    if(memcmp(buf,s,8)) {
-		putc('\n');
-		putshex(buf,8);
-		printf(" [FAIL] (%p) align=%d\n", s, align);
-		for(j=0;j<8;j++) {
-		    s[j]==buf[j]?puts("  "):printf("%02x", (s[j])^(buf[j]));
-		}
-		putc('\n');
-	    } else {
-		printf(" [PASS] (%p) align=%d\n", s, align);
-	    }
+	for (i = 0; i < len; i++) {
+		printf ("%02x", buf[i]);
 	}
-    }
+	return 0;
+}
 
-    return 0;
+static int char_memcpy (void *d, const void *s, int len)
+{
+	int i;
+	char *cd = d;
+	const char *cs = s;
+
+	for (i = 0; i < len; i++) {
+		*(cd++) = *(cs++);
+	}
+	return 0;
+}
+
+static int memory_test (char *buf)
+{
+	const char src[][16] = {
+		{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+		{0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+		 0x01, 0x01, 0x01, 0x01, 0x01, 0x01},
+		{0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
+		 0x02, 0x02, 0x02, 0x02, 0x02, 0x02},
+		{0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04,
+		 0x04, 0x04, 0x04, 0x04, 0x04, 0x04},
+		{0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+		 0x08, 0x08, 0x08, 0x08, 0x08, 0x08},
+		{0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+		 0x10, 0x10, 0x10, 0x10, 0x10, 0x10},
+		{0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+		 0x20, 0x20, 0x20, 0x20, 0x20, 0x20},
+		{0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
+		 0x40, 0x40, 0x40, 0x40, 0x40, 0x40},
+		{0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+		 0x80, 0x80, 0x80, 0x80, 0x80, 0x80},
+		{0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55,
+		 0x55, 0x55, 0x55, 0x55, 0x55, 0x55},
+		{0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+		 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa},
+		{0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+	};
+	const int foo[] = { 0 };
+	int i, j, a;
+
+	printf ("\ntest @ %d %p\n", foo[0], buf);
+	for (i = 0; i < 12; i++) {
+		for (a = 0; a < 8; a++) {
+			const char *s = src[i] + a;
+			int align = (unsigned) (s) & 0x7;
+
+			/* ecc_off(); */
+			memcpy (buf, s, 8);
+			/* ecc_on(); */
+			putshex (s, 8);
+			if (memcmp (buf, s, 8)) {
+				putc ('\n');
+				putshex (buf, 8);
+				printf (" [FAIL] (%p) align=%d\n", s, align);
+				for (j = 0; j < 8; j++) {
+					s[j] == buf[j] ? puts ("  ") :
+						printf ("%02x",
+							(s[j]) ^ (buf[j]));
+				}
+				putc ('\n');
+			} else {
+				printf (" [PASS] (%p) align=%d\n", s, align);
+			}
+			/* ecc_off(); */
+			char_memcpy (buf, s, 8);
+			/* ecc_on(); */
+			putshex (s, 8);
+			if (memcmp (buf, s, 8)) {
+				putc ('\n');
+				putshex (buf, 8);
+				printf (" [FAIL] (%p) align=%d\n", s, align);
+				for (j = 0; j < 8; j++) {
+					s[j] == buf[j] ? puts ("  ") :
+						printf ("%02x",
+							(s[j]) ^ (buf[j]));
+				}
+				putc ('\n');
+			} else {
+				printf (" [PASS] (%p) align=%d\n", s, align);
+			}
+		}
+	}
+
+	return 0;
 }
 #endif

board/evb64260/eth_addrtbl.c

@@ -13,66 +13,68 @@
 
 #ifdef CONFIG_GT_USE_MAC_HASH_TABLE
 
-static u32           addressTableHashMode[ GAL_ETH_DEVS ] = { 0, };
-static u32           addressTableHashSize[ GAL_ETH_DEVS ] = { 0, };
-static addrTblEntry *addressTableBase[     GAL_ETH_DEVS ] = { 0, };
-static void         *realAddrTableBase[    GAL_ETH_DEVS ] = { 0, };
+static u32 addressTableHashMode[GAL_ETH_DEVS] = { 0, };
+static u32 addressTableHashSize[GAL_ETH_DEVS] = { 0, };
+static addrTblEntry *addressTableBase[GAL_ETH_DEVS] = { 0, };
+static void *realAddrTableBase[GAL_ETH_DEVS] = { 0, };
 
-static const u32 hashLength[ 2 ] = {
-    (0x8000),             /* 8K * 4 entries */
-    (0x8000/16),          /* 512 * 4 entries */
+static const u32 hashLength[2] = {
+	(0x8000),		/* 8K * 4 entries */
+	(0x8000 / 16),		/* 512 * 4 entries */
 };
 
 /* Initialize the address table for a port, if needed */
-unsigned int initAddressTable( u32 port, u32 hashMode, u32 hashSizeSelector)
+unsigned int initAddressTable (u32 port, u32 hashMode, u32 hashSizeSelector)
 {
-    unsigned int tableBase;
+	unsigned int tableBase;
 
-    if( port < 0 || port >= GAL_ETH_DEVS ) {
-		printf("%s: Invalid port number %d\n", __FUNCTION__, port );
+	if (port < 0 || port >= GAL_ETH_DEVS) {
+		printf ("%s: Invalid port number %d\n", __FUNCTION__, port);
 		return 0;
 	}
 
 	if (hashMode > 1) {
-		printf("%s: Invalid Hash Mode %d\n", __FUNCTION__, port );
+		printf ("%s: Invalid Hash Mode %d\n", __FUNCTION__, port);
 		return 0;
 	}
 
-	if ( realAddrTableBase[port] &&
-		( addressTableHashSize[port] != hashSizeSelector )) {
+	if (realAddrTableBase[port] &&
+	    (addressTableHashSize[port] != hashSizeSelector)) {
 		/* we have been here before,
 		 * but now we want a different sized table
 		 */
-		free( realAddrTableBase[port] );
+		free (realAddrTableBase[port]);
 		realAddrTableBase[port] = 0;
 		addressTableBase[port] = 0;
 
 	}
 
-	tableBase = (unsigned int)addressTableBase[port];
+	tableBase = (unsigned int) addressTableBase[port];
 	/* we get called for every probe, so only do this once */
-	if ( !tableBase ) {
-	int bytes = hashLength[hashSizeSelector] * sizeof(addrTblEntry);
+	if (!tableBase) {
+		int bytes =
+			hashLength[hashSizeSelector] * sizeof (addrTblEntry);
 
-		tableBase = (unsigned int)realAddrTableBase[port] = malloc(bytes+64);
+		tableBase = (unsigned int) realAddrTableBase[port] =
+			malloc (bytes + 64);
 
-	    if(!tableBase)
-		{
-			printf("%s: alloc memory failed \n", __FUNCTION__);
+		if (!tableBase) {
+			printf ("%s: alloc memory failed \n", __FUNCTION__);
 			return 0;
 		}
 
-	/* align to octal byte */
-	    if(tableBase&63) tableBase=(tableBase+63) & ~63;
+		/* align to octal byte */
+		if (tableBase & 63)
+			tableBase = (tableBase + 63) & ~63;
 
-	addressTableHashMode[port] = hashMode;
-	    addressTableHashSize[port] = hashSizeSelector;
-	addressTableBase[port] = (addrTblEntry *)tableBase;
+		addressTableHashMode[port] = hashMode;
+		addressTableHashSize[port] = hashSizeSelector;
+		addressTableBase[port] = (addrTblEntry *) tableBase;
 
-	    memset((void *)tableBase,0,bytes);
+		memset ((void *) tableBase, 0, bytes);
 	}
 
-    return tableBase;
+	return tableBase;
 }
 
 /*
@@ -87,61 +89,61 @@ unsigned int initAddressTable( u32 port, u32 hashMode, u32 hashSizeSelector)
  * Outputs
  * return the calculated entry.
  */
-u32
-hashTableFunction( u32 macH, u32 macL, u32 HashSize, u32 hash_mode)
+u32 hashTableFunction (u32 macH, u32 macL, u32 HashSize, u32 hash_mode)
 {
-    u32 hashResult;
-    u32 addrH;
-    u32 addrL;
-    u32 addr0;
-    u32 addr1;
-    u32 addr2;
-    u32 addr3;
-    u32 addrHSwapped;
-    u32 addrLSwapped;
+	u32 hashResult;
+	u32 addrH;
+	u32 addrL;
+	u32 addr0;
+	u32 addr1;
+	u32 addr2;
+	u32 addr3;
+	u32 addrHSwapped;
+	u32 addrLSwapped;
 
 
-    addrH = NIBBLE_SWAPPING_16_BIT( macH );
-    addrL = NIBBLE_SWAPPING_32_BIT( macL );
+	addrH = NIBBLE_SWAPPING_16_BIT (macH);
+	addrL = NIBBLE_SWAPPING_32_BIT (macL);
 
-    addrHSwapped =   FLIP_4_BITS(  addrH        & 0xf )
-		 + ((FLIP_4_BITS( (addrH >>  4) & 0xf)) <<  4)
-		 + ((FLIP_4_BITS( (addrH >>  8) & 0xf)) <<  8)
-		 + ((FLIP_4_BITS( (addrH >> 12) & 0xf)) << 12);
+	addrHSwapped = FLIP_4_BITS (addrH & 0xf)
+		+ ((FLIP_4_BITS ((addrH >> 4) & 0xf)) << 4)
+		+ ((FLIP_4_BITS ((addrH >> 8) & 0xf)) << 8)
+		+ ((FLIP_4_BITS ((addrH >> 12) & 0xf)) << 12);
 
-    addrLSwapped =   FLIP_4_BITS(  addrL        & 0xf )
-		 + ((FLIP_4_BITS( (addrL >>  4) & 0xf)) <<  4)
-		 + ((FLIP_4_BITS( (addrL >>  8) & 0xf)) <<  8)
-		 + ((FLIP_4_BITS( (addrL >> 12) & 0xf)) << 12)
-		 + ((FLIP_4_BITS( (addrL >> 16) & 0xf)) << 16)
-		 + ((FLIP_4_BITS( (addrL >> 20) & 0xf)) << 20)
-		 + ((FLIP_4_BITS( (addrL >> 24) & 0xf)) << 24)
-		 + ((FLIP_4_BITS( (addrL >> 28) & 0xf)) << 28);
+	addrLSwapped = FLIP_4_BITS (addrL & 0xf)
+		+ ((FLIP_4_BITS ((addrL >> 4) & 0xf)) << 4)
+		+ ((FLIP_4_BITS ((addrL >> 8) & 0xf)) << 8)
+		+ ((FLIP_4_BITS ((addrL >> 12) & 0xf)) << 12)
+		+ ((FLIP_4_BITS ((addrL >> 16) & 0xf)) << 16)
+		+ ((FLIP_4_BITS ((addrL >> 20) & 0xf)) << 20)
+		+ ((FLIP_4_BITS ((addrL >> 24) & 0xf)) << 24)
+		+ ((FLIP_4_BITS ((addrL >> 28) & 0xf)) << 28);
 
-    addrH = addrHSwapped;
-    addrL = addrLSwapped;
+	addrH = addrHSwapped;
+	addrL = addrLSwapped;
 
-    if( hash_mode == 0 )  {
-	addr0 =  (addrL >>  2) & 0x03f;
-	addr1 =  (addrL        & 0x003) | ((addrL >> 8) & 0x7f) << 2;
-	addr2 =  (addrL >> 15) & 0x1ff;
-	addr3 = ((addrL >> 24) & 0x0ff) | ((addrH &  1)         << 8);
-    } else  {
-	addr0 = FLIP_6_BITS(    addrL        & 0x03f );
-	addr1 = FLIP_9_BITS(  ((addrL >>  6) & 0x1ff));
-	addr2 = FLIP_9_BITS(   (addrL >> 15) & 0x1ff);
-	addr3 = FLIP_9_BITS( (((addrL >> 24) & 0x0ff) | ((addrH & 0x1) << 8)));
-    }
+	if (hash_mode == 0) {
+		addr0 = (addrL >> 2) & 0x03f;
+		addr1 = (addrL & 0x003) | ((addrL >> 8) & 0x7f) << 2;
+		addr2 = (addrL >> 15) & 0x1ff;
+		addr3 = ((addrL >> 24) & 0x0ff) | ((addrH & 1) << 8);
+	} else {
+		addr0 = FLIP_6_BITS (addrL & 0x03f);
+		addr1 = FLIP_9_BITS (((addrL >> 6) & 0x1ff));
+		addr2 = FLIP_9_BITS ((addrL >> 15) & 0x1ff);
+		addr3 = FLIP_9_BITS ((((addrL >> 24) & 0x0ff) |
+				      ((addrH & 0x1) << 8)));
+	}
 
-    hashResult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
+	hashResult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
 
-    if( HashSize == _8K_TABLE )  {
-	hashResult = hashResult & 0xffff;
-    } else  {
-	hashResult = hashResult & 0x07ff;
-    }
+	if (HashSize == _8K_TABLE) {
+		hashResult = hashResult & 0xffff;
+	} else {
+		hashResult = hashResult & 0x07ff;
+	}
 
-    return( hashResult );
+	return (hashResult);
 }
 
 
@@ -160,66 +162,59 @@ hashTableFunction( u32 macH, u32 macL, u32 HashSize, u32 hash_mode)
  * TRUE if success.
  * FALSE if table full
  */
-int
-addAddressTableEntry(
-    u32           port,
-    u32           macH,
-    u32           macL,
-    u32           rd,
-    u32           skip         )
+int addAddressTableEntry (u32 port, u32 macH, u32 macL, u32 rd, u32 skip)
 {
-    addrTblEntry *entry;
-    u32           newHi;
-    u32           newLo;
-    u32           i;
+	addrTblEntry *entry;
+	u32 newHi;
+	u32 newLo;
+	u32 i;
 
-    newLo = (((macH >>  4) & 0xf) << 15)
-	  | (((macH >>  0) & 0xf) << 11)
-	  | (((macH >> 12) & 0xf) <<  7)
-	  | (((macH >>  8) & 0xf) <<  3)
-	  | (((macL >> 20) & 0x1) << 31)
-	  | (((macL >> 16) & 0xf) << 27)
-	  | (((macL >> 28) & 0xf) << 23)
-	  | (((macL >> 24) & 0xf) << 19)
-	  |   (skip << SKIP_BIT)  |  (rd << 2) | VALID;
+	newLo = (((macH >> 4) & 0xf) << 15)
+		| (((macH >> 0) & 0xf) << 11)
+		| (((macH >> 12) & 0xf) << 7)
+		| (((macH >> 8) & 0xf) << 3)
+		| (((macL >> 20) & 0x1) << 31)
+		| (((macL >> 16) & 0xf) << 27)
+		| (((macL >> 28) & 0xf) << 23)
+		| (((macL >> 24) & 0xf) << 19)
+		| (skip << SKIP_BIT) | (rd << 2) | VALID;
 
-    newHi = (((macL >>  4) & 0xf) << 15)
-	  | (((macL >>  0) & 0xf) << 11)
-	  | (((macL >> 12) & 0xf) <<  7)
-	  | (((macL >>  8) & 0xf) <<  3)
-	  | (((macL >> 21) & 0x7) <<  0);
+	newHi = (((macL >> 4) & 0xf) << 15)
+		| (((macL >> 0) & 0xf) << 11)
+		| (((macL >> 12) & 0xf) << 7)
+		| (((macL >> 8) & 0xf) << 3)
+		| (((macL >> 21) & 0x7) << 0);
 
-    /*
-     * Pick the appropriate table, start scanning for free/reusable
-     * entries at the index obtained by hashing the specified MAC address
-     */
-    entry  = addressTableBase[port];
-    entry += hashTableFunction( macH, macL, addressTableHashSize[port],
-					    addressTableHashMode[port]  );
-    for( i = 0;  i < HOP_NUMBER;  i++, entry++ )  {
-	if( !(entry->lo & VALID)   /*|| (entry->lo & SKIP)*/   )  {
-	    break;
-	} else  {                    /* if same address put in same position */
-	    if(   ((entry->lo & 0xfffffff8) == (newLo & 0xfffffff8))
-		&& (entry->hi               ==  newHi) )
-	    {
-		    break;
-	    }
+	/*
+	 * Pick the appropriate table, start scanning for free/reusable
+	 * entries at the index obtained by hashing the specified MAC address
+	 */
+	entry = addressTableBase[port];
+	entry += hashTableFunction (macH, macL, addressTableHashSize[port],
+				    addressTableHashMode[port]);
+	for (i = 0; i < HOP_NUMBER; i++, entry++) {
+		if (!(entry->lo & VALID) /*|| (entry->lo & SKIP) */ ) {
+			break;
+		} else {	/* if same address put in same position */
+			if (((entry->lo & 0xfffffff8) == (newLo & 0xfffffff8))
+			    && (entry->hi == newHi)) {
+				break;
+			}
+		}
 	}
-    }
 
-    if( i == HOP_NUMBER )  {
-	PRINTF( "addGT64260addressTableEntry: table section is full\n" );
-	return( FALSE );
-    }
+	if (i == HOP_NUMBER) {
+		PRINTF ("addGT64260addressTableEntry: table section is full\n");
+		return (FALSE);
+	}
 
-    /*
-     * Update the selected entry
-     */
-    entry->hi = newHi;
-    entry->lo = newLo;
-    DCACHE_FLUSH_N_SYNC( (u32)entry, MAC_ENTRY_SIZE );
-    return( TRUE );
+	/*
+	 * Update the selected entry
+	 */
+	entry->hi = newHi;
+	entry->lo = newLo;
+	DCACHE_FLUSH_N_SYNC ((u32) entry, MAC_ENTRY_SIZE);
+	return (TRUE);
 }
 
 #endif /* CONFIG_GT_USE_MAC_HASH_TABLE */

board/evb64260/sdram_init.c

@@ -54,65 +54,64 @@ typedef struct sdram_info {
 	uchar tras_clocks;
 	uchar burst_len;
 	uchar banks, slot;
-	int size;	/* detected size, not from I2C but from dram_size() */
+	int size;		/* detected size, not from I2C but from dram_size() */
 } sdram_info_t;
 
 #ifdef DEBUG
-void dump_dimm_info(struct sdram_info *d)
+void dump_dimm_info (struct sdram_info *d)
 {
-    static const char *ecc_legend[]={""," Parity"," ECC"};
-    printf("dimm%s %sDRAM: %dMibytes:\n",
-	    ecc_legend[d->ecc],
-	    d->registered?"R":"",
-	    (d->size>>20));
-    printf("  drb=%d tpar=%d tras=%d burstlen=%d banks=%d slot=%d\n",
-	    d->drb_size, d->tpar, d->tras_clocks, d->burst_len,
-	    d->banks, d->slot);
+	static const char *ecc_legend[] = { "", " Parity", " ECC" };
+
+	printf ("dimm%s %sDRAM: %dMibytes:\n",
+		ecc_legend[d->ecc],
+		d->registered ? "R" : "", (d->size >> 20));
+	printf ("  drb=%d tpar=%d tras=%d burstlen=%d banks=%d slot=%d\n",
+		d->drb_size, d->tpar, d->tras_clocks, d->burst_len,
+		d->banks, d->slot);
 }
 #endif
 
 static int
-memory_map_bank(unsigned int bankNo,
-		unsigned int bankBase,
-		unsigned int bankLength)
+memory_map_bank (unsigned int bankNo,
+		 unsigned int bankBase, unsigned int bankLength)
 {
 #ifdef DEBUG
 	if (bankLength > 0) {
-		printf("mapping bank %d at %08x - %08x\n",
-		       bankNo, bankBase, bankBase + bankLength - 1);
+		printf ("mapping bank %d at %08x - %08x\n",
+			bankNo, bankBase, bankBase + bankLength - 1);
 	} else {
-		printf("unmapping bank %d\n", bankNo);
+		printf ("unmapping bank %d\n", bankNo);
 	}
 #endif
 
-	memoryMapBank(bankNo, bankBase, bankLength);
+	memoryMapBank (bankNo, bankBase, bankLength);
 
 	return 0;
 }
 
 #ifdef MAP_PCI
 static int
-memory_map_bank_pci(unsigned int bankNo,
-		unsigned int bankBase,
-		unsigned int bankLength)
+memory_map_bank_pci (unsigned int bankNo,
+		     unsigned int bankBase, unsigned int bankLength)
 {
 	PCI_HOST host;
-	for (host=PCI_HOST0;host<=PCI_HOST1;host++) {
-		const int features=
+
+	for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
+		const int features =
 			PREFETCH_ENABLE |
 			DELAYED_READ_ENABLE |
 			AGGRESSIVE_PREFETCH |
 			READ_LINE_AGGRESSIVE_PREFETCH |
 			READ_MULTI_AGGRESSIVE_PREFETCH |
-			MAX_BURST_4 |
-			PCI_NO_SWAP;
+			MAX_BURST_4 | PCI_NO_SWAP;
 
-		pciMapMemoryBank(host, bankNo, bankBase, bankLength);
+		pciMapMemoryBank (host, bankNo, bankBase, bankLength);
 
-		pciSetRegionSnoopMode(host, bankNo, PCI_SNOOP_WB, bankBase,
-				bankLength);
+		pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
+				       bankLength);
 
-		pciSetRegionFeatures(host, bankNo, features, bankBase, bankLength);
+		pciSetRegionFeatures (host, bankNo, features, bankBase,
+				      bankLength);
 	}
 	return 0;
 }
@@ -128,8 +127,7 @@ memory_map_bank_pci(unsigned int bankNo,
  * translate ns.ns/10 coding of SPD timing values
  * into 10 ps unit values
  */
-static inline unsigned short
-NS10to10PS(unsigned char spd_byte)
+static inline unsigned short NS10to10PS (unsigned char spd_byte)
 {
 	unsigned short ns, ns10;
 
@@ -138,37 +136,35 @@ NS10to10PS(unsigned char spd_byte)
 	/* isolate lower nibble */
 	ns10 = (spd_byte & 0x0F);
 
-	return(ns*100 + ns10*10);
+	return (ns * 100 + ns10 * 10);
 }
 
 /*
  * translate ns coding of SPD timing values
  * into 10 ps unit values
  */
-static inline unsigned short
-NSto10PS(unsigned char spd_byte)
+static inline unsigned short NSto10PS (unsigned char spd_byte)
 {
-	return(spd_byte*100);
+	return (spd_byte * 100);
 }
 
 #ifdef CONFIG_ZUMA_V2
-static int
-check_dimm(uchar slot, sdram_info_t *info)
+static int check_dimm (uchar slot, sdram_info_t * info)
 {
 	/* assume 2 dimms, 2 banks each 256M - we dont have an
 	 * dimm i2c so rely on the detection routines later */
 
-	memset(info, 0, sizeof(*info));
+	memset (info, 0, sizeof (*info));
 
 	info->slot = slot;
 	info->banks = 2;	/* Detect later */
-	    info->registered = 0;
+	info->registered = 0;
 	info->drb_size = 32;	/* 16 - 256MBit, 32 - 512MBit
 				   but doesn't matter, both do same
 				   thing in setup_sdram() */
-	    info->tpar = 3;
-	    info->tras_clocks = 5;
-	    info->burst_len = 4;
+	info->tpar = 3;
+	info->tras_clocks = 5;
+	info->burst_len = 4;
 #ifdef CONFIG_ECC
 	info->ecc = 0;		/* Detect later */
 #endif /* CONFIG_ECC */
@@ -177,10 +173,9 @@ check_dimm(uchar slot, sdram_info_t *info)
 
 #elif defined(CONFIG_P3G4)
 
-static int
-check_dimm(uchar slot, sdram_info_t *info)
+static int check_dimm (uchar slot, sdram_info_t * info)
 {
-	memset(info, 0, sizeof(*info));
+	memset (info, 0, sizeof (*info));
 
 	if (slot)
 		return 0;
@@ -198,12 +193,11 @@ check_dimm(uchar slot, sdram_info_t *info)
 	return 0;
 }
 
-#else /* ! CONFIG_ZUMA_V2 && ! CONFIG_P3G4*/
+#else  /* ! CONFIG_ZUMA_V2 && ! CONFIG_P3G4 */
 
 /* This code reads the SPD chip on the sdram and populates
  * the array which is passed in with the relevant information */
-static int
-check_dimm(uchar slot, sdram_info_t *info)
+static int check_dimm (uchar slot, sdram_info_t * info)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 	uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
@@ -215,32 +209,32 @@ check_dimm(uchar slot, sdram_info_t *info)
 
 	get_clocks ();
 
-	tmemclk = 1000000000 / (gd->bus_clk / 100);  /* in 10 ps units */
+	tmemclk = 1000000000 / (gd->bus_clk / 100);	/* in 10 ps units */
 
 #ifdef CONFIG_EVB64260_750CX
 	if (0 != slot) {
-		printf("check_dimm: The EVB-64260-750CX only has 1 DIMM,");
-		printf("            called with slot=%d insetad!\n", slot);
+		printf ("check_dimm: The EVB-64260-750CX only has 1 DIMM,");
+		printf ("            called with slot=%d insetad!\n", slot);
 		return 0;
 	}
 #endif
-	DP(puts("before i2c read\n"));
+	DP (puts ("before i2c read\n"));
 
-	ret = i2c_read(addr, 0, 128, data, 0);
+	ret = i2c_read (addr, 0, 128, data, 0);
 
-	DP(puts("after i2c read\n"));
+	DP (puts ("after i2c read\n"));
 
 	/* zero all the values */
-	memset(info, 0, sizeof(*info));
+	memset (info, 0, sizeof (*info));
 
 	if (ret) {
-		DP(printf("No DIMM in slot %d [err = %x]\n", slot, ret));
+		DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret));
 		return 0;
 	}
 
 	/* first, do some sanity checks */
 	if (data[2] != 0x4) {
-		printf("Not SDRAM in slot %d\n", slot);
+		printf ("Not SDRAM in slot %d\n", slot);
 		return 0;
 	}
 
@@ -251,7 +245,8 @@ check_dimm(uchar slot, sdram_info_t *info)
 	sdram_banks = data[17];
 	width = data[13] & 0x7f;
 
-	DP(printf("sdram_banks: %d, banks: %d\n", sdram_banks, info->banks));
+	DP (printf
+	    ("sdram_banks: %d, banks: %d\n", sdram_banks, info->banks));
 
 	/* check if the memory is registered */
 	if (data[21] & (BIT1 | BIT4))
@@ -266,31 +261,31 @@ check_dimm(uchar slot, sdram_info_t *info)
 	supp_cal = (data[18] & 0x6) >> 1;
 
 	/* compute the relevant clock values */
-	trp_clocks = (NSto10PS(data[27])+(tmemclk-1)) / tmemclk;
-	trcd_clocks = (NSto10PS(data[29])+(tmemclk-1)) / tmemclk;
-	info->tras_clocks = (NSto10PS(data[30])+(tmemclk-1)) / tmemclk;
+	trp_clocks = (NSto10PS (data[27]) + (tmemclk - 1)) / tmemclk;
+	trcd_clocks = (NSto10PS (data[29]) + (tmemclk - 1)) / tmemclk;
+	info->tras_clocks = (NSto10PS (data[30]) + (tmemclk - 1)) / tmemclk;
 
-	DP(printf("trp = %d\ntrcd_clocks = %d\ntras_clocks = %d\n",
-		  trp_clocks, trcd_clocks, info->tras_clocks));
+	DP (printf ("trp = %d\ntrcd_clocks = %d\ntras_clocks = %d\n",
+		    trp_clocks, trcd_clocks, info->tras_clocks));
 
 	/* try a CAS latency of 3 first... */
 	cal_val = 0;
 	if (supp_cal & 3) {
-		if (NS10to10PS(data[9]) <= tmemclk)
+		if (NS10to10PS (data[9]) <= tmemclk)
 			cal_val = 3;
 	}
 
 	/* then 2... */
 	if (supp_cal & 2) {
-		if (NS10to10PS(data[23]) <= tmemclk)
+		if (NS10to10PS (data[23]) <= tmemclk)
 			cal_val = 2;
 	}
 
-	DP(printf("cal_val = %d\n", cal_val));
+	DP (printf ("cal_val = %d\n", cal_val));
 
 	/* bummer, did't work... */
 	if (cal_val == 0) {
-		DP(printf("Couldn't find a good CAS latency\n"));
+		DP (printf ("Couldn't find a good CAS latency\n"));
 		return 0;
 	}
 
@@ -302,18 +297,19 @@ check_dimm(uchar slot, sdram_info_t *info)
 	if (trcd_clocks > info->tpar)
 		info->tpar = trcd_clocks;
 
-	DP(printf("tpar set to: %d\n", info->tpar));
+	DP (printf ("tpar set to: %d\n", info->tpar));
 
 #ifdef CFG_BROKEN_CL2
-	if (info->tpar == 2){
+	if (info->tpar == 2) {
 		info->tpar = 3;
-		DP(printf("tpar fixed-up to: %d\n", info->tpar));
+		DP (printf ("tpar fixed-up to: %d\n", info->tpar));
 	}
 #endif
 	/* compute the module DRB size */
-	info->drb_size = (((1 << (rows + cols)) * sdram_banks) * width) / _16M;
+	info->drb_size =
+		(((1 << (rows + cols)) * sdram_banks) * width) / _16M;
 
-	DP(printf("drb_size set to: %d\n", info->drb_size));
+	DP (printf ("drb_size set to: %d\n", info->drb_size));
 
 	/* find the burst len */
 	info->burst_len = data[16] & 0xf;
@@ -330,40 +326,48 @@ check_dimm(uchar slot, sdram_info_t *info)
 }
 #endif /* ! CONFIG_ZUMA_V2 */
 
-static int
-setup_sdram_common(sdram_info_t info[2])
+static int setup_sdram_common (sdram_info_t info[2])
 {
 	ulong tmp;
-	int tpar=2, tras_clocks=5, registered=1, ecc=2;
+	int tpar = 2, tras_clocks = 5, registered = 1, ecc = 2;
 
-	if(!info[0].banks && !info[1].banks) return 0;
+	if (!info[0].banks && !info[1].banks)
+		return 0;
 
-	if(info[0].banks) {
-	    if(info[0].tpar>tpar) tpar=info[0].tpar;
-	    if(info[0].tras_clocks>tras_clocks) tras_clocks=info[0].tras_clocks;
-	    if(!info[0].registered) registered=0;
-	    if(info[0].ecc!=2) ecc=0;
+	if (info[0].banks) {
+		if (info[0].tpar > tpar)
+			tpar = info[0].tpar;
+		if (info[0].tras_clocks > tras_clocks)
+			tras_clocks = info[0].tras_clocks;
+		if (!info[0].registered)
+			registered = 0;
+		if (info[0].ecc != 2)
+			ecc = 0;
 	}
 
-	if(info[1].banks) {
-	    if(info[1].tpar>tpar) tpar=info[1].tpar;
-	    if(info[1].tras_clocks>tras_clocks) tras_clocks=info[1].tras_clocks;
-	    if(!info[1].registered) registered=0;
-	    if(info[1].ecc!=2) ecc=0;
+	if (info[1].banks) {
+		if (info[1].tpar > tpar)
+			tpar = info[1].tpar;
+		if (info[1].tras_clocks > tras_clocks)
+			tras_clocks = info[1].tras_clocks;
+		if (!info[1].registered)
+			registered = 0;
+		if (info[1].ecc != 2)
+			ecc = 0;
 	}
 
 	/* SDRAM configuration */
-	tmp = GTREGREAD(SDRAM_CONFIGURATION);
+	tmp = GTREGREAD (SDRAM_CONFIGURATION);
 
 	/* Turn on physical interleave if both DIMMs
 	 * have even numbers of banks. */
-	if( (info[0].banks == 0 || info[0].banks == 2) &&
-	    (info[1].banks == 0 || info[1].banks == 2) ) {
-	    /* physical interleave on */
-	    tmp &= ~(1 << 15);
+	if ((info[0].banks == 0 || info[0].banks == 2) &&
+	    (info[1].banks == 0 || info[1].banks == 2)) {
+		/* physical interleave on */
+		tmp &= ~(1 << 15);
 	} else {
-	    /* physical interleave off */
-	    tmp |= (1 << 15);
+		/* physical interleave off */
+		tmp |= (1 << 15);
 	}
 
 	tmp |= (registered << 17);
@@ -372,52 +376,51 @@ setup_sdram_common(sdram_info_t info[2])
 	 * See Res #12 */
 	tmp |= (1 << 26);
 
-	GT_REG_WRITE(SDRAM_CONFIGURATION, tmp);
-	DP(printf("SDRAM config: %08x\n",
-		GTREGREAD(SDRAM_CONFIGURATION)));
+	GT_REG_WRITE (SDRAM_CONFIGURATION, tmp);
+	DP (printf ("SDRAM config: %08x\n", GTREGREAD (SDRAM_CONFIGURATION)));
 
 	/* SDRAM timing */
 	tmp = (((tpar == 3) ? 2 : 1) |
 	       (((tpar == 3) ? 2 : 1) << 2) |
-	       (((tpar == 3) ? 2 : 1) << 4) |
-	       (tras_clocks << 8));
+	       (((tpar == 3) ? 2 : 1) << 4) | (tras_clocks << 8));
 
 #ifdef CONFIG_ECC
 	/* Setup ECC */
-	if (ecc == 2) tmp |= 1<<13;
+	if (ecc == 2)
+		tmp |= 1 << 13;
 #endif /* CONFIG_ECC */
 
-	GT_REG_WRITE(SDRAM_TIMING, tmp);
-	DP(printf("SDRAM timing: %08x (%d,%d,%d,%d)\n",
-		GTREGREAD(SDRAM_TIMING), tpar,tpar,tpar,tras_clocks));
+	GT_REG_WRITE (SDRAM_TIMING, tmp);
+	DP (printf ("SDRAM timing: %08x (%d,%d,%d,%d)\n",
+		    GTREGREAD (SDRAM_TIMING), tpar, tpar, tpar, tras_clocks));
 
 	/* SDRAM address decode register */
 	/* program this with the default value */
-	GT_REG_WRITE(SDRAM_ADDRESS_DECODE, 0x2);
-	DP(printf("SDRAM decode: %08x\n",
-		GTREGREAD(SDRAM_ADDRESS_DECODE)));
+	GT_REG_WRITE (SDRAM_ADDRESS_DECODE, 0x2);
+	DP (printf ("SDRAM decode: %08x\n",
+		    GTREGREAD (SDRAM_ADDRESS_DECODE)));
 
 	return 0;
 }
 
 /* sets up the GT properly with information passed in */
-static int
-setup_sdram(sdram_info_t *info)
+static int setup_sdram (sdram_info_t * info)
 {
 	ulong tmp, check;
 	ulong *addr = 0;
 	int i;
 
 	/* sanity checking */
-	if (! info->banks) return 0;
+	if (!info->banks)
+		return 0;
 
 	/* ---------------------------- */
 	/* Program the GT with the discovered data */
 
 	/* bank parameters */
-	tmp = (0xf<<16);	/* leave all virt bank pages open */
+	tmp = (0xf << 16);	/* leave all virt bank pages open */
 
-	DP(printf("drb_size: %d\n", info->drb_size));
+	DP (printf ("drb_size: %d\n", info->drb_size));
 	switch (info->drb_size) {
 	case 1:
 		tmp |= (1 << 14);
@@ -431,41 +434,42 @@ setup_sdram(sdram_info_t *info)
 		tmp |= (3 << 14);
 		break;
 	default:
-		printf("Error in dram size calculation\n");
+		printf ("Error in dram size calculation\n");
 		return 1;
 	}
 
 	/* SDRAM bank parameters */
 	/* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
-	GT_REG_WRITE(SDRAM_BANK0PARAMETERS + (info->slot * 0x8), tmp);
-	GT_REG_WRITE(SDRAM_BANK1PARAMETERS + (info->slot * 0x8), tmp);
-	DP(printf("SDRAM bankparam slot %d (bank %d+%d): %08lx\n", info->slot, info->slot*2, (info->slot*2)+1, tmp));
+	GT_REG_WRITE (SDRAM_BANK0PARAMETERS + (info->slot * 0x8), tmp);
+	GT_REG_WRITE (SDRAM_BANK1PARAMETERS + (info->slot * 0x8), tmp);
+	DP (printf
+	    ("SDRAM bankparam slot %d (bank %d+%d): %08lx\n", info->slot,
+	     info->slot * 2, (info->slot * 2) + 1, tmp));
 
 	/* set the SDRAM configuration for each bank */
 	for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) {
-		DP(printf("*** Running a MRS cycle for bank %d ***\n", i));
+		DP (printf ("*** Running a MRS cycle for bank %d ***\n", i));
 
 		/* map the bank */
-		memory_map_bank(i, 0, GB/4);
+		memory_map_bank (i, 0, GB / 4);
 
 		/* set SDRAM mode */
-		GT_REG_WRITE(SDRAM_OPERATION_MODE, 0x3);
-		check = GTREGREAD(SDRAM_OPERATION_MODE);
+		GT_REG_WRITE (SDRAM_OPERATION_MODE, 0x3);
+		check = GTREGREAD (SDRAM_OPERATION_MODE);
 
 		/* dummy write */
 		*addr = 0;
 
 		/* wait for the command to complete */
-		while ((GTREGREAD(SDRAM_OPERATION_MODE) & (1 << 31)) == 0)
-			;
+		while ((GTREGREAD (SDRAM_OPERATION_MODE) & (1 << 31)) == 0);
 
 		/* switch back to normal operation mode */
-		GT_REG_WRITE(SDRAM_OPERATION_MODE, 0);
-		check = GTREGREAD(SDRAM_OPERATION_MODE);
+		GT_REG_WRITE (SDRAM_OPERATION_MODE, 0);
+		check = GTREGREAD (SDRAM_OPERATION_MODE);
 
 		/* unmap the bank */
-		memory_map_bank(i, 0, 0);
-		DP(printf("*** MRS cycle for bank %d done ***\n", i));
+		memory_map_bank (i, 0, 0);
+		DP (printf ("*** MRS cycle for bank %d done ***\n", i));
 	}
 
 	return 0;
@@ -478,50 +482,50 @@ setup_sdram(sdram_info_t *info)
  * - short between address lines
  * - short between data lines
  */
-static long int
-dram_size(long int *base, long int maxsize)
+static long int dram_size (long int *base, long int maxsize)
 {
-    volatile long int	 *addr, *b=base;
-    long int	 cnt, val, save1, save2;
+	volatile long int *addr, *b = base;
+	long int cnt, val, save1, save2;
 
 #define STARTVAL (1<<20)	/* start test at 1M */
-    for (cnt = STARTVAL/sizeof(long); cnt < maxsize/sizeof(long); cnt <<= 1) {
-	    addr = base + cnt;	/* pointer arith! */
+	for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
+	     cnt <<= 1) {
+		addr = base + cnt;	/* pointer arith! */
 
-	    save1=*addr;	/* save contents of addr */
-	    save2=*b;		/* save contents of base */
+		save1 = *addr;	/* save contents of addr */
+		save2 = *b;	/* save contents of base */
 
-	    *addr=cnt;		/* write cnt to addr */
-	    *b=0;		/* put null at base */
+		*addr = cnt;	/* write cnt to addr */
+		*b = 0;		/* put null at base */
 
-	    /* check at base address */
-	    if ((*b) != 0) {
-		*addr=save1;	/* restore *addr */
-		*b=save2;	/* restore *b */
-		return (0);
-	    }
-	    val = *addr;	/* read *addr */
+		/* check at base address */
+		if ((*b) != 0) {
+			*addr = save1;	/* restore *addr */
+			*b = save2;	/* restore *b */
+			return (0);
+		}
+		val = *addr;	/* read *addr */
 
-	    *addr=save1;
-	    *b=save2;
+		*addr = save1;
+		*b = save2;
 
-	    if (val != cnt) {
-		    /* fix boundary condition.. STARTVAL means zero */
-		    if(cnt==STARTVAL/sizeof(long)) cnt=0;
-		    return (cnt * sizeof(long));
-	    }
-    }
-    return maxsize;
+		if (val != cnt) {
+			/* fix boundary condition.. STARTVAL means zero */
+			if (cnt == STARTVAL / sizeof (long))
+				cnt = 0;
+			return (cnt * sizeof (long));
+		}
+	}
+	return maxsize;
 }
 
 /* ------------------------------------------------------------------------- */
 
 /* U-Boot interface function to SDRAM init - this is where all the
  * controlling logic happens */
-long int
-initdram(int board_type)
+long int initdram (int board_type)
 {
-	ulong checkbank[4] = { [0 ... 3] = 0 };
+	ulong checkbank[4] = {[0 ... 3] = 0 };
 	int bank_no;
 	ulong total;
 	int nhr;
@@ -531,92 +535,97 @@ initdram(int board_type)
 	/* first, use the SPD to get info about the SDRAM */
 
 	/* check the NHR bit and skip mem init if it's already done */
-	nhr = get_hid0() & (1 << 16);
+	nhr = get_hid0 () & (1 << 16);
 
 	if (nhr) {
-		printf("Skipping SDRAM setup due to NHR bit being set\n");
+		printf ("Skipping SDRAM setup due to NHR bit being set\n");
 	} else {
 		/* DIMM0 */
-		check_dimm(0, &dimm_info[0]);
+		check_dimm (0, &dimm_info[0]);
 
 		/* DIMM1 */
-#ifndef CONFIG_EVB64260_750CX /* EVB64260_750CX has only 1 DIMM */
-		check_dimm(1, &dimm_info[1]);
-#else /* CONFIG_EVB64260_750CX */
-		memset(&dimm_info[1], 0, sizeof(sdram_info_t));
+#ifndef CONFIG_EVB64260_750CX	/* EVB64260_750CX has only 1 DIMM */
+		check_dimm (1, &dimm_info[1]);
+#else  /* CONFIG_EVB64260_750CX */
+		memset (&dimm_info[1], 0, sizeof (sdram_info_t));
 #endif
 
 		/* unmap all banks */
-		memory_map_bank(0, 0, 0);
-		memory_map_bank(1, 0, 0);
-		memory_map_bank(2, 0, 0);
-		memory_map_bank(3, 0, 0);
+		memory_map_bank (0, 0, 0);
+		memory_map_bank (1, 0, 0);
+		memory_map_bank (2, 0, 0);
+		memory_map_bank (3, 0, 0);
 
 		/* Now, program the GT with the correct values */
-		if (setup_sdram_common(dimm_info)) {
-			printf("Setup common failed.\n");
+		if (setup_sdram_common (dimm_info)) {
+			printf ("Setup common failed.\n");
 		}
 
-		if (setup_sdram(&dimm_info[0])) {
-			printf("Setup for DIMM1 failed.\n");
+		if (setup_sdram (&dimm_info[0])) {
+			printf ("Setup for DIMM1 failed.\n");
 		}
 
-		if (setup_sdram(&dimm_info[1])) {
-			printf("Setup for DIMM2 failed.\n");
+		if (setup_sdram (&dimm_info[1])) {
+			printf ("Setup for DIMM2 failed.\n");
 		}
 
 		/* set the NHR bit */
-		set_hid0(get_hid0() | (1 << 16));
+		set_hid0 (get_hid0 () | (1 << 16));
 	}
 	/* next, size the SDRAM banks */
 
 	total = 0;
-	if (dimm_info[0].banks > 0) checkbank[0] = 1;
-	if (dimm_info[0].banks > 1) checkbank[1] = 1;
+	if (dimm_info[0].banks > 0)
+		checkbank[0] = 1;
+	if (dimm_info[0].banks > 1)
+		checkbank[1] = 1;
 	if (dimm_info[0].banks > 2)
-		printf("Error, SPD claims DIMM1 has >2 banks\n");
+		printf ("Error, SPD claims DIMM1 has >2 banks\n");
 
-	if (dimm_info[1].banks > 0) checkbank[2] = 1;
-	if (dimm_info[1].banks > 1) checkbank[3] = 1;
+	if (dimm_info[1].banks > 0)
+		checkbank[2] = 1;
+	if (dimm_info[1].banks > 1)
+		checkbank[3] = 1;
 	if (dimm_info[1].banks > 2)
-		printf("Error, SPD claims DIMM2 has >2 banks\n");
+		printf ("Error, SPD claims DIMM2 has >2 banks\n");
 
 	/* Generic dram sizer: works even if we don't have i2c DIMMs,
 	 * as long as the timing settings are more or less correct */
 
 	/*
 	 * pass 1: size all the banks, using first bat (0-256M)
-	 * 	   limitation: we only support 256M per bank due to
-	 *  	   us only having 1 BAT for all DRAM
+	 *         limitation: we only support 256M per bank due to
+	 *         us only having 1 BAT for all DRAM
 	 */
 	for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
 		/* skip over banks that are not populated */
-		if (! checkbank[bank_no])
+		if (!checkbank[bank_no])
 			continue;
 
-		DP(printf("checking bank %d\n", bank_no));
+		DP (printf ("checking bank %d\n", bank_no));
 
-		memory_map_bank(bank_no, 0, GB/4);
-		checkbank[bank_no] = dram_size(NULL, GB/4);
-		memory_map_bank(bank_no, 0, 0);
+		memory_map_bank (bank_no, 0, GB / 4);
+		checkbank[bank_no] = dram_size (NULL, GB / 4);
+		memory_map_bank (bank_no, 0, 0);
 
-		DP(printf("bank %d %08lx\n", bank_no, checkbank[bank_no]));
+		DP (printf ("bank %d %08lx\n", bank_no, checkbank[bank_no]));
 	}
 
 	/*
 	 * pass 2: contiguously map each bank into physical address
-	 * 	   space.
+	 *         space.
 	 */
-	dimm_info[0].banks=dimm_info[1].banks=0;
+	dimm_info[0].banks = dimm_info[1].banks = 0;
 	for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
-		if(!checkbank[bank_no]) continue;
+		if (!checkbank[bank_no])
+			continue;
 
-		dimm_info[bank_no/2].banks++;
-		dimm_info[bank_no/2].size+=checkbank[bank_no];
+		dimm_info[bank_no / 2].banks++;
+		dimm_info[bank_no / 2].size += checkbank[bank_no];
 
-		memory_map_bank(bank_no, total, checkbank[bank_no]);
+		memory_map_bank (bank_no, total, checkbank[bank_no]);
 #ifdef MAP_PCI
-		memory_map_bank_pci(bank_no, total, checkbank[bank_no]);
+		memory_map_bank_pci (bank_no, total, checkbank[bank_no]);
 #endif
 		total += checkbank[bank_no];
 	}
@@ -630,21 +639,22 @@ initdram(int board_type)
 	 * in that configuration, ECC chips are mounted, even for stacked
 	 * chips)
 	 */
-	if (checkbank[2]==0 && checkbank[3]==0) {
-		dimm_info[0].ecc=2;
-		GT_REG_WRITE(SDRAM_TIMING, GTREGREAD(SDRAM_TIMING) | (1 << 13));
+	if (checkbank[2] == 0 && checkbank[3] == 0) {
+		dimm_info[0].ecc = 2;
+		GT_REG_WRITE (SDRAM_TIMING,
+			      GTREGREAD (SDRAM_TIMING) | (1 << 13));
 		/* TODO: do we have to run MRS cycles again? */
 	}
 #endif /* CONFIG_ZUMA_V2 */
 
-	if (GTREGREAD(SDRAM_TIMING) & (1 << 13)) {
-		puts("[ECC] ");
+	if (GTREGREAD (SDRAM_TIMING) & (1 << 13)) {
+		puts ("[ECC] ");
 	}
 #endif /* CONFIG_ECC */
 
 #ifdef DEBUG
-	dump_dimm_info(&dimm_info[0]);
-	dump_dimm_info(&dimm_info[1]);
+	dump_dimm_info (&dimm_info[0]);
+	dump_dimm_info (&dimm_info[1]);
 #endif
 	/* TODO: return at MOST 256M? */
 	/* return total > GB/4 ? GB/4 : total; */

board/evb64260/zuma_pbb_mbox.h

@@ -2,33 +2,33 @@
 #define OUT_PENDING 2
 
 enum {
-    ZUMA_MBOXMSG_DONE,
-    ZUMA_MBOXMSG_MACL,
-    ZUMA_MBOXMSG_MACH,
-    ZUMA_MBOXMSG_IP,
-    ZUMA_MBOXMSG_SLOT,
-    ZUMA_MBOXMSG_RESET,
-    ZUMA_MBOXMSG_BAUD,
-    ZUMA_MBOXMSG_START,
-    ZUMA_MBOXMSG_ENG_PRV_MACL,
-    ZUMA_MBOXMSG_ENG_PRV_MACH,
+	ZUMA_MBOXMSG_DONE,
+	ZUMA_MBOXMSG_MACL,
+	ZUMA_MBOXMSG_MACH,
+	ZUMA_MBOXMSG_IP,
+	ZUMA_MBOXMSG_SLOT,
+	ZUMA_MBOXMSG_RESET,
+	ZUMA_MBOXMSG_BAUD,
+	ZUMA_MBOXMSG_START,
+	ZUMA_MBOXMSG_ENG_PRV_MACL,
+	ZUMA_MBOXMSG_ENG_PRV_MACH,
 
-    MBOXMSG_LAST
+	MBOXMSG_LAST
 };
 
 struct zuma_mailbox_info {
-  unsigned char acc_mac[6];
-  unsigned char prv_mac[6];
-  unsigned int ip;
-  unsigned int slot_bac;
-  unsigned int console_baud;
-  unsigned int debug_baud;
+	unsigned char acc_mac[6];
+	unsigned char prv_mac[6];
+	unsigned int ip;
+	unsigned int slot_bac;
+	unsigned int console_baud;
+	unsigned int debug_baud;
 };
 
 struct _zuma_mbox_dev {
-  pci_dev_t dev;
-  PBB_DMA_REG_MAP *sip;
-  struct zuma_mailbox_info mailbox;
+	pci_dev_t dev;
+	PBB_DMA_REG_MAP *sip;
+	struct zuma_mailbox_info mailbox;
 };
 
 #define zuma_prv_mac		zuma_mbox_dev.mailbox.prv_mac
@@ -40,4 +40,4 @@ struct _zuma_mbox_dev {
 
 
 extern struct _zuma_mbox_dev zuma_mbox_dev;
-extern int zuma_mbox_init(void);
+extern int zuma_mbox_init (void);

board/fads/config.mk

@@ -24,8 +24,8 @@
 #
 
 #
-# Motorola old MPC821/860ADS, MPC8xxFADS, new MPC866ADS, and DUET
-# (MPC87x/88x) ADS boards
+# Motorola old MPC821/860ADS, MPC8xxFADS, new MPC866ADS, and
+# MPC885ADS boards
 #
 
 TEXT_BASE = 0xFE000000

board/fads/fads.c

@@ -26,12 +26,13 @@
 #include <config.h>
 #include <common.h>
 #include <mpc8xx.h>
+#include <pcmcia.h>
 
 #define	_NOT_USED_	0xFFFFFFFF
 
 /* ========================================================================= */
 
-#ifndef CONFIG_DUET_ADS /* No old DRAM on Duet */
+#ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */
 
 #if defined(CONFIG_DRAM_50MHZ)
 /* 50MHz tables */
@@ -290,7 +291,7 @@ static void _dramdisable(void)
 
 	/* maybe we should turn off upma here or something */
 }
-#endif /* !CONFIG_DUET_ADS */
+#endif /* !CONFIG_MPC885ADS */
 
 /* ========================================================================= */
 
@@ -604,7 +605,7 @@ long int initdram (int board_type)
 	uint sdramsz = 0;	/* size of sdram in Mbytes */
 	uint base = 0;		/* base of dram in bytes */
 	uint m = 0;		/* size of dram in Mbytes */
-#ifndef CONFIG_DUET_ADS
+#ifndef CONFIG_MPC885ADS
 	uint k, s;
 #endif
 
@@ -614,7 +615,7 @@ long int initdram (int board_type)
 		printf ("(%u MB SDRAM) ", sdramsz);
 	}
 #endif
-#ifndef CONFIG_DUET_ADS /* No old DRAM on Duet */
+#ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */
 	k = (*((uint *) BCSR2) >> 23) & 0x0f;
 
 	switch (k & 0x3) {
@@ -665,7 +666,7 @@ long int initdram (int board_type)
 		_dramdisable ();
 		m = 0;
 	}
-#endif /* !CONFIG_DUET_ADS */
+#endif /* !CONFIG_MPC885ADS */
 	m += sdramsz;				/* add sdram size to total */
 
 	return (m << 20);
@@ -734,8 +735,8 @@ int checkboard (void)
 
 #if defined(CONFIG_MPC86xADS)
 	puts ("MPC86xADS");
-#elif defined(CONFIG_DUET_ADS)
-	puts ("DUET ADS");
+#elif defined(CONFIG_MPC885ADS)
+	puts ("MPC885ADS");
 	r = 0; /* I've got NR (No Revision) board */
 #elif defined(CONFIG_FADS)
 	puts ("FADS");
@@ -759,7 +760,7 @@ int checkboard (void)
 	case 0x03:
 		puts ("B \n");
 		break;
-#elif defined(CONFIG_DUET_ADS)
+#elif defined(CONFIG_MPC885ADS)
 	case 0x00:
 		puts ("NR\n");
 		break;
@@ -790,7 +791,7 @@ volatile unsigned char *pcmcia_mem = (unsigned char*)CFG_PCMCIA_MEM_ADDR;
 int pcmcia_init(void)
 {
 	volatile pcmconf8xx_t	*pcmp;
-	uint v, slota, slotb;
+	uint v, slota = 0, slotb = 0;
 
 	/*
 	** Enable the PCMCIA for a Flash card.
@@ -805,10 +806,10 @@ int pcmcia_init(void)
 	/* Set all slots to zero by default. */
 	pcmp->pcmc_pgcra = 0;
 	pcmp->pcmc_pgcrb = 0;
-#ifdef PCMCIA_SLOT_A
+#ifdef CONFIG_PCMCIA_SLOT_A
 	pcmp->pcmc_pgcra = 0x40;
 #endif
-#ifdef PCMCIA_SLOT_B
+#ifdef CONFIG_PCMCIA_SLOT_B
 	pcmp->pcmc_pgcrb = 0x40;
 #endif
 
@@ -817,17 +818,17 @@ int pcmcia_init(void)
 
 	/* Check if any PCMCIA card is plugged in. */
 
+#ifdef CONFIG_PCMCIA_SLOT_A
 	slota = (pcmp->pcmc_pipr & 0x18000000) == 0 ;
+#endif
+#ifdef CONFIG_PCMCIA_SLOT_B
 	slotb = (pcmp->pcmc_pipr & 0x00001800) == 0 ;
+#endif
 
 	if (!(slota || slotb)) {
 		printf("No card present\n");
-#ifdef PCMCIA_SLOT_A
 		pcmp->pcmc_pgcra = 0;
-#endif
-#ifdef PCMCIA_SLOT_B
 		pcmp->pcmc_pgcrb = 0;
-#endif
 		return -1;
 	}
 	else
@@ -908,9 +909,10 @@ int pcmcia_init(void)
 
 	udelay(20);
 
-#ifdef PCMCIA_SLOT_A
+#ifdef CONFIG_PCMCIA_SLOT_A
 	pcmp->pcmc_pgcra = 0;
-#elif PCMCIA_SLOT_B
+#endif
+#ifdef CONFIG_PCMCIA_SLOT_B
 	pcmp->pcmc_pgcrb = 0;
 #endif
 

board/fads/fads.h

@@ -48,9 +48,6 @@
  * | ...                   |                                 v
  *
  *****************************************************************************/
-/* should ALWAYS define this, measure_gclk in speed.c is unreliable */
-/* in general, we always know this for FADS+new ADS anyway */
-#define CONFIG_8xx_GCLK_FREQ     ((CFG_8XX_XIN) * (CFG_8XX_FACT))
 
 #if 0
 #define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
@@ -66,6 +63,7 @@
     "bootm"
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#define CONFIG_BZIP2	 /* include support for bzip2 compressed images */
 
 /*
  * New MPC86xADS and Duet provide two Ethernet connectivity options:
@@ -90,11 +88,13 @@
 #endif
 
 #ifndef CONFIG_COMMANDS
-#define CONFIG_COMMANDS	(CONFIG_CMD_DFL  \
-			 | CFG_CMD_DHCP  \
-			 | CFG_CMD_IMMAP \
-			 | CFG_CMD_MII   \
-			 | CFG_CMD_PING  \
+#define CONFIG_COMMANDS	(CONFIG_CMD_DFL   \
+			 | CFG_CMD_DHCP   \
+			 | CFG_CMD_IMMAP  \
+			 | CFG_CMD_JFFS2  \
+			 | CFG_CMD_MII    \
+			 | CFG_CMD_PCMCIA \
+			 | CFG_CMD_PING   \
 			)
 #endif /* !CONFIG_COMMANDS */
 
@@ -146,7 +146,7 @@
  * Please note that CFG_SDRAM_BASE _must_ start at 0
  */
 #define	CFG_SDRAM_BASE		0x00000000
-#if defined(CONFIG_MPC86xADS) || defined(CONFIG_DUET_ADS) /* New ADS or Duet */
+#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */
 #define	CFG_SDRAM_SIZE		0x00800000      	/* 8 Mbyte */
 #elif defined(CONFIG_FADS)				/* Old/new FADS */
 #define	CFG_SDRAM_SIZE		0x00400000		/* 4 Mbyte */
@@ -167,14 +167,24 @@
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 KB for monitor	*/
+
+#ifdef CONFIG_BZIP2
+#define	CFG_MALLOC_LEN		(2500 << 10)	/* Reserve ~2.5 MB for malloc()	*/
+#else
+#define	CFG_MALLOC_LEN		(384 << 10)	/* Reserve 384 kB for malloc()	*/
+#endif /* CONFIG_BZIP2 */
+
 /*-----------------------------------------------------------------------
  * Flash organization
  */
-#define CFG_FLASH_BASE		TEXT_BASE
-#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
+#define CFG_FLASH_BASE		CFG_MONITOR_BASE
+#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte	*/
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	16      /* max number of sectors on one chip	*/
+#define CFG_MAX_FLASH_BANKS	4	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
 
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
@@ -184,9 +194,14 @@
 #define CFG_ENV_OFFSET		CFG_ENV_SECT_SIZE
 #define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment		*/
 
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 KB for monitor	*/
-#define	CFG_MALLOC_LEN		(384 << 10)	/* Reserve 384 kB for malloc()	*/
+#define	CFG_DIRECT_FLASH_TFTP
+
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+#define CFG_JFFS2_FIRST_BANK	0
+#define CFG_JFFS2_NUM_BANKS	CFG_MAX_FLASH_BANKS
+#define CFG_JFFS2_FIRST_SECTOR  4
+#define CFG_JFFS2_SORT_FRAGMENTS
+#endif /* CFG_CMD_JFFS2 */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
@@ -248,7 +263,16 @@
 #define SCCR_MASK	SCCR_EBDF11
 #define CFG_SCCR	(SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
 
- /*-----------------------------------------------------------------------
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		14-22
+ *-----------------------------------------------------------------------
+ * set the PLL, the low-power modes and the reset control
+ */
+#ifndef CFG_PLPRCR
+#define CFG_PLPRCR	PLPRCR_TEXPS
+#endif
+
+/*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
@@ -339,6 +363,7 @@
 #define BCSR1_PCCVCCON		 BCSR1_PCCVCC0
 
 #define BCSR2_FLASH_PD_MASK      ((uint)0xF0000000)
+#define BCSR2_FLASH_PD_SHIFT     28
 #define BCSR2_DRAM_PD_MASK       ((uint)0x07800000)
 #define BCSR2_DRAM_PD_SHIFT      23
 #define BCSR2_EXTTOLI_MASK       ((uint)0x00780000)
@@ -407,6 +432,20 @@
 #define BCSR4_DATA_VOICE         ((uint)0x00080000)
 #endif /* CONFIG_MPC850 */
 
+/* BSCR5 exists on MPC86xADS and Duet ADS only */
+
+#define CFG_PHYDEV_ADDR		(BCSR_ADDR + 0x20000)
+
+#define BCSR5			(CFG_PHYDEV_ADDR + 0x300)
+
+#define BCSR5_MII2_EN		0x40
+#define BCSR5_MII2_RST		0x20
+#define BCSR5_T1_RST		0x10
+#define BCSR5_ATM155_RST	0x08
+#define BCSR5_ATM25_RST		0x04
+#define BCSR5_MII1_EN		0x02
+#define BCSR5_MII1_RST		0x01
+
 /* We don't use the 8259.
 */
 #define NR_8259_INTS	0
@@ -419,10 +458,6 @@
  * PCMCIA stuff
  *-----------------------------------------------------------------------
  */
-#if !defined(CONFIG_MPC823) && !defined(CONFIG_MPC850)
-#define PCMCIA_SLOT_A 1
-#endif
-
 #define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
 #define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
 #define CFG_PCMCIA_DMA_ADDR	(0xE4000000)

board/fads/flash.c

@@ -24,7 +24,7 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
 
 #if defined(CFG_ENV_IS_IN_FLASH)
 # ifndef  CFG_ENV_ADDR
@@ -38,312 +38,283 @@ flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 # endif
 #endif
 
+#define QUAD_ID(id)	((((ulong)(id) & 0xFF) << 24) | \
+			 (((ulong)(id) & 0xFF) << 16) | \
+			 (((ulong)(id) & 0xFF) << 8)  | \
+			 (((ulong)(id) & 0xFF) << 0)    \
+			)
+
 /*-----------------------------------------------------------------------
  * Functions
  */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static int write_word (flash_info_t * info, ulong dest, ulong data);
 
 /*-----------------------------------------------------------------------
  */
-
 unsigned long flash_init (void)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	unsigned long total_size;
-	unsigned long size_b0, size_b1;
+	vu_long *bcsr = (vu_long *)BCSR_ADDR;
+	unsigned long pd_size, total_size, bsize, or_am;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i)
-	{
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].size = 0;
+		flash_info[i].sector_count = 0;
+		flash_info[i].start[0] = 0xFFFFFFFF; /* For TFTP */
+	}
+
+	switch ((bcsr[2] & BCSR2_FLASH_PD_MASK) >> BCSR2_FLASH_PD_SHIFT) {
+	case 2:
+	case 4:
+	case 6:
+		pd_size = 0x800000;
+		or_am = 0xFF800000;
+		break;
+
+	case 5:
+	case 7:
+		pd_size = 0x400000;
+		or_am = 0xFFC00000;
+		break;
+
+	case 8:
+		pd_size = 0x200000;
+		or_am = 0xFFE00000;
+		break;
+
+	default:
+		pd_size = 0;
+		or_am = 0xFFE00000;
+		printf("## Unsupported flash detected by BCSR: 0x%08X\n", bcsr[2]);
 	}
 
 	total_size = 0;
-	size_b0 = 0xffffffff;
+	for (i = 0; i < CFG_MAX_FLASH_BANKS && total_size < pd_size; ++i) {
+		bsize = flash_get_size((vu_long *)(CFG_FLASH_BASE + total_size),
+				       &flash_info[i]);
 
-	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i)
-	{
-		size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + total_size), &flash_info[i]);
-
-		if (flash_info[i].flash_id == FLASH_UNKNOWN)
-		{
-			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", i, size_b1, size_b1>>20);
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+				i, bsize, bsize >> 20);
 		}
 
-		/* Is this really needed ? - LP */
-		if (size_b1 > size_b0) {
-			printf ("## ERROR: Bank %d (0x%08lx = %ld MB) > Bank %d (0x%08lx = %ld MB)\n",
-			        i, size_b1, size_b1>>20, i-1, size_b0, size_b0>>20);
-			goto out_error;
-		}
-		size_b0 = size_b1;
-		total_size += size_b1;
+		total_size += bsize;
 	}
 
-	/* Compute the Address Mask */
-	for (i=0; (total_size >> i) != 0; ++i) {};
-	i--;
-
-	if (total_size != (1 << i)) {
-		printf ("## WARNING: Total FLASH size (0x%08lx = %ld MB) is not a power of 2\n",
-			total_size, total_size>>20);
+	if (total_size != pd_size) {
+		printf("## Detected flash size %lu conflicts with PD data %lu\n",
+		       total_size, pd_size);
 	}
 
 	/* Remap FLASH according to real size */
-	memctl->memc_or0 = ((((unsigned long)~1) << i) & OR_AM_MSK) | CFG_OR_TIMING_FLASH;
-	memctl->memc_br0 = CFG_BR0_PRELIM;
-
-	total_size = 0;
-
-	for (i=0; i < CFG_MAX_FLASH_BANKS && flash_info[i].size != 0; ++i)
-	{
-		/* Re-do sizing to get full correct info */
-		/* Why ? - LP */
-		size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + total_size), &flash_info[i]);
-
-		/* This is done by flash_get_size - LP */
-		/* flash_get_offsets (CFG_FLASH_BASE + total_size, &flash_info[i]); */
+	memctl->memc_or0 = or_am | CFG_OR_TIMING_FLASH;
 
+	for (i = 0; i < CFG_MAX_FLASH_BANKS && flash_info[i].size != 0; ++i) {
 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
 		/* monitor protection ON by default */
-		flash_protect(FLAG_PROTECT_SET,
-			      CFG_MONITOR_BASE,
-			      CFG_MONITOR_BASE+monitor_flash_len-1,
-			      &flash_info[i]);
+		if (CFG_MONITOR_BASE >= flash_info[i].start[0])
+			flash_protect (FLAG_PROTECT_SET,
+				       CFG_MONITOR_BASE,
+				       CFG_MONITOR_BASE + monitor_flash_len - 1,
+				       &flash_info[i]);
 #endif
 
 #ifdef	CFG_ENV_IS_IN_FLASH
 		/* ENV protection ON by default */
-		flash_protect(FLAG_PROTECT_SET,
-			      CFG_ENV_ADDR,
-			      CFG_ENV_ADDR+CFG_ENV_SIZE-1,
-			      &flash_info[i]);
+		if (CFG_ENV_ADDR >= flash_info[i].start[0])
+			flash_protect (FLAG_PROTECT_SET,
+				       CFG_ENV_ADDR,
+				       CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+				       &flash_info[i]);
 #endif
-
-		total_size += size_b1;
 	}
 
-	return (total_size);
-
-out_error:
-	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i)
-	{
-		flash_info[i].flash_id		= FLASH_UNKNOWN;
-		flash_info[i].sector_count	= -1;
-		flash_info[i].size		= 0;
-	}
-
-	return (0);
+	return total_size;
 }
 
 /*-----------------------------------------------------------------------
  */
-static void flash_get_offsets (ulong base, flash_info_t *info)
+void flash_print_info (flash_info_t * info)
 {
 	int i;
 
-	/* set up sector start address table */
-	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040 || (info->flash_id & FLASH_TYPEMASK) == FLASH_AM080 ) {
-		/* set sector offsets for uniform sector type	*/
-		for (i = 0; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00040000);
-		}
-	}
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info  (flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN)
-	{
+	if (info->flash_id == FLASH_UNKNOWN) {
 		printf ("missing or unknown FLASH type\n");
 		return;
 	}
 
-	switch (info->flash_id & FLASH_VENDMASK)
-	{
-		case FLASH_MAN_AMD:	printf ("AMD ");		break;
-		case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
-		case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
-		default:		printf ("Unknown Vendor ");	break;
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf ("FUJITSU ");
+		break;
+	case FLASH_MAN_BM:
+		printf ("BRIGHT MICRO ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
 	}
 
-	switch (info->flash_id & FLASH_TYPEMASK)
-	{
-		case FLASH_AM040:	printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
-			break;
-		case FLASH_AM080:	printf ("29F080 or 29LV080 (8 Mbit, uniform sectors)\n");
-		                	break;
-		case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
-					break;
-		case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
-					break;
-		case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
-					break;
-		case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
-					break;
-		case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
-					break;
-		case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
-					break;
-		case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
-					break;
-		case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
-					break;
-		default:		printf ("Unknown Chip Type\n");
-					break;
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+		printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
+		break;
+	case FLASH_AM080:
+		printf ("29F080 or 29LV080 (8 Mbit, uniform sectors)\n");
+		break;
+	case FLASH_AM400B:
+		printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:
+		printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:
+		printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:
+		printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:
+		printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
 	}
 
-	printf ("  Size: %ld MB in %d Sectors\n",info->size >> 20, info->sector_count);
+	printf ("  Size: %ld MB in %d Sectors\n", info->size >> 20,
+		info->sector_count);
 
 	printf ("  Sector Start Addresses:");
 
-	for (i=0; i<info->sector_count; ++i)
-	{
-		if ((i % 5) == 0)
-		{
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0) {
 			printf ("\n   ");
 		}
 
 		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     ");
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
 	}
 
 	printf ("\n");
-	return;
 }
 
 /*-----------------------------------------------------------------------
+ * The following code can not run from flash!
  */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+static ulong flash_get_size (vu_long * addr, flash_info_t * info)
 {
 	short i;
-#if 0
-	ulong base = (ulong)addr;
-#endif
-	uchar value;
 
 	/* Write auto select command: read Manufacturer ID */
-#if 0
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00900090;
-#else
 	addr[0x0555] = 0xAAAAAAAA;
 	addr[0x02AA] = 0x55555555;
 	addr[0x0555] = 0x90909090;
-#endif
 
-	value = addr[0];
+	switch (addr[0]) {
+	case QUAD_ID(AMD_MANUFACT):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
 
-	switch (value + (value << 16))
-	{
-		case AMD_MANUFACT:
-			info->flash_id = FLASH_MAN_AMD;
-			break;
+	case QUAD_ID(FUJ_MANUFACT):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
 
-		case FUJ_MANUFACT:
-			info->flash_id = FLASH_MAN_FUJ;
-			break;
-
-		default:
-			info->flash_id = FLASH_UNKNOWN;
-			info->sector_count = 0;
-			info->size = 0;
-			break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
 	}
 
-	value = addr[1];			/* device ID		*/
+	switch (addr[1]) {	/* device ID            */
+	case QUAD_ID(AMD_ID_F040B):
+	case QUAD_ID(AMD_ID_LV040B):
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
 
-	switch (value)
-	{
-		case AMD_ID_F040B:
-			info->flash_id += FLASH_AM040;
-			info->sector_count = 8;
-			info->size = 0x00200000;
-			break;				/* => 2 MB		*/
+	case QUAD_ID(AMD_ID_F080B):
+		info->flash_id += FLASH_AM080;
+		info->sector_count = 16;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+#if 0
+	case AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */
 
-		case AMD_ID_F080B:
-			info->flash_id += FLASH_AM080;
-			info->sector_count =16;
-			info->size = 0x00400000;
-			break;				/* => 4 MB		*/
+	case AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */
 
-		case AMD_ID_LV400T:
-			info->flash_id += FLASH_AM400T;
-			info->sector_count = 11;
-			info->size = 0x00100000;
-			break;				/* => 1 MB		*/
+	case AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
 
-		case AMD_ID_LV400B:
-			info->flash_id += FLASH_AM400B;
-			info->sector_count = 11;
-			info->size = 0x00100000;
-			break;				/* => 1 MB		*/
+	case AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
 
-		case AMD_ID_LV800T:
-			info->flash_id += FLASH_AM800T;
-			info->sector_count = 19;
-			info->size = 0x00200000;
-			break;				/* => 2 MB		*/
+	case AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
 
-		case AMD_ID_LV800B:
-			info->flash_id += FLASH_AM800B;
-			info->sector_count = 19;
-			info->size = 0x00200000;
-			break;				/* => 2 MB		*/
+	case AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
 
-		case AMD_ID_LV160T:
-			info->flash_id += FLASH_AM160T;
-			info->sector_count = 35;
-			info->size = 0x00400000;
-			break;				/* => 4 MB		*/
-
-		case AMD_ID_LV160B:
-			info->flash_id += FLASH_AM160B;
-			info->sector_count = 35;
-			info->size = 0x00400000;
-			break;				/* => 4 MB		*/
-#if 0	/* enable when device IDs are available */
-		case AMD_ID_LV320T:
-			info->flash_id += FLASH_AM320T;
-			info->sector_count = 67;
-			info->size = 0x00800000;
-			break;				/* => 8 MB		*/
-
-		case AMD_ID_LV320B:
-			info->flash_id += FLASH_AM320B;
-			info->sector_count = 67;
-			info->size = 0x00800000;
-			break;				/* => 8 MB		*/
-#endif
-		default:
-			info->flash_id = FLASH_UNKNOWN;
-			return (0);			/* => no or unknown flash */
+	case AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;		/* => 8 MB              */
 
+	case AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;		/* => 8 MB              */
+#endif /* 0 */
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);	/* => no or unknown flash */
 	}
 
 #if 0
 	/* set up sector start address table */
 	if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type	*/
+		/* set sector offsets for bottom boot block type        */
 		info->start[0] = base + 0x00000000;
 		info->start[1] = base + 0x00008000;
 		info->start[2] = base + 0x0000C000;
@@ -352,7 +323,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 			info->start[i] = base + (i * 0x00020000) - 0x00060000;
 		}
 	} else {
-		/* set sector offsets for top boot block type		*/
+		/* set sector offsets for top boot block type           */
 		i = info->sector_count - 1;
 		info->start[i--] = base + info->size - 0x00008000;
 		info->start[i--] = base + info->size - 0x0000C000;
@@ -362,41 +333,32 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		}
 	}
 #else
-	flash_get_offsets ((ulong)addr, info);
+	/* set sector offsets for uniform sector type */
+	for (i = 0; i < info->sector_count; i++)
+		info->start[i] = (ulong)addr + (i * 0x00040000);
 #endif
 
 	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++)
-	{
+	for (i = 0; i < info->sector_count; i++) {
 		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
 		/* D0 = 1 if protected */
-		addr = (volatile unsigned long *)(info->start[i]);
+		addr = (volatile unsigned long *) (info->start[i]);
 		info->protect[i] = addr[2] & 1;
 	}
 
-	/*
-	 * Prevent writes to uninitialized FLASH.
-	 */
-	if (info->flash_id != FLASH_UNKNOWN)
-	{
-		addr = (volatile unsigned long *)info->start[0];
-#if 0
-		*addr = 0x00F000F0;	/* reset bank */
-#else
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *) info->start[0];
 		*addr = 0xF0F0F0F0;	/* reset bank */
-#endif
 	}
 
 	return (info->size);
 }
 
-
 /*-----------------------------------------------------------------------
  */
-
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
+int flash_erase (flash_info_t * info, int s_first, int s_last)
 {
-	vu_long *addr = (vu_long*)(info->start[0]);
+	vu_long *addr = (vu_long *) (info->start[0]);
 	int flag, prot, sect, l_sect;
 	ulong start, now, last;
 
@@ -406,25 +368,24 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 		} else {
 			printf ("- no sectors to erase\n");
 		}
-		return 1;
+		return ERR_INVAL;
 	}
 
 	if ((info->flash_id == FLASH_UNKNOWN) ||
 	    (info->flash_id > FLASH_AMD_COMP)) {
 		printf ("Can't erase unknown flash type - aborted\n");
-		return 1;
+		return ERR_UNKNOWN_FLASH_TYPE;
 	}
 
 	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
+	for (sect = s_first; sect <= s_last; ++sect) {
 		if (info->protect[sect]) {
 			prot++;
 		}
 	}
 
 	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
 	} else {
 		printf ("\n");
 	}
@@ -432,38 +393,26 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 	l_sect = -1;
 
 	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
+	flag = disable_interrupts ();
 
-#if 0
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00800080;
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-#else
 	addr[0x0555] = 0xAAAAAAAA;
 	addr[0x02AA] = 0x55555555;
 	addr[0x0555] = 0x80808080;
 	addr[0x0555] = 0xAAAAAAAA;
 	addr[0x02AA] = 0x55555555;
-#endif
 
 	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last; sect++) {
+	for (sect = s_first; sect <= s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
-			addr = (vu_long*)(info->start[sect]);
-#if 0
-			addr[0] = 0x00300030;
-#else
+			addr = (vu_long *) (info->start[sect]);
 			addr[0] = 0x30303030;
-#endif
 			l_sect = sect;
 		}
 	}
 
 	/* re-enable interrupts if necessary */
 	if (flag)
-		enable_interrupts();
+		enable_interrupts ();
 
 	/* wait at least 80us - let's wait 1 ms */
 	udelay (1000);
@@ -475,17 +424,13 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 		goto DONE;
 
 	start = get_timer (0);
-	last  = start;
-	addr = (vu_long*)(info->start[l_sect]);
-#if 0
-	while ((addr[0] & 0x00800080) != 0x00800080)
-#else
+	last = start;
+	addr = (vu_long *) (info->start[l_sect]);
 	while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF)
-#endif
 	{
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
-			return 1;
+			return ERR_TIMOUT;
 		}
 		/* show that we're waiting */
 		if ((now - last) > 1000) {	/* every second */
@@ -494,16 +439,13 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 		}
 	}
 
-DONE:
+      DONE:
 	/* reset to read mode */
-	addr = (volatile unsigned long *)info->start[0];
-#if 0
-	addr[0] = 0x00F000F0;	/* reset bank */
-#else
+	addr = (volatile unsigned long *) info->start[0];
 	addr[0] = 0xF0F0F0F0;	/* reset bank */
-#endif
 
 	printf (" done\n");
+
 	return 0;
 }
 
@@ -513,8 +455,7 @@ DONE:
  * 1 - write timeout
  * 2 - Flash not erased
  */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 {
 	ulong cp, wp, data;
 	int i, l, rc;
@@ -526,19 +467,19 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	 */
 	if ((l = addr - wp) != 0) {
 		data = 0;
-		for (i=0, cp=wp; i<l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
 		}
-		for (; i<4 && cnt>0; ++i) {
+		for (; i < 4 && cnt > 0; ++i) {
 			data = (data << 8) | *src++;
 			--cnt;
 			++cp;
 		}
-		for (; cnt==0 && i<4; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
 		}
 
-		if ((rc = write_word(info, wp, data)) != 0) {
+		if ((rc = write_word (info, wp, data)) != 0) {
 			return (rc);
 		}
 		wp += 4;
@@ -549,13 +490,13 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	 */
 	while (cnt >= 4) {
 		data = 0;
-		for (i=0; i<4; ++i) {
+		for (i = 0; i < 4; ++i) {
 			data = (data << 8) | *src++;
 		}
-		if ((rc = write_word(info, wp, data)) != 0) {
+		if ((rc = write_word (info, wp, data)) != 0) {
 			return (rc);
 		}
-		wp  += 4;
+		wp += 4;
 		cnt -= 4;
 	}
 
@@ -567,15 +508,15 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	 * handle unaligned tail bytes
 	 */
 	data = 0;
-	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
 		data = (data << 8) | *src++;
 		--cnt;
 	}
-	for (; i<4; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *)cp);
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
 	}
 
-	return (write_word(info, wp, data));
+	return (write_word (info, wp, data));
 }
 
 /*-----------------------------------------------------------------------
@@ -584,49 +525,36 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
  * 1 - write timeout
  * 2 - Flash not erased
  */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
+static int write_word (flash_info_t * info, ulong dest, ulong data)
 {
-	vu_long *addr = (vu_long*)(info->start[0]);
+	vu_long *addr = (vu_long *) (info->start[0]);
 	ulong start;
 	int flag;
 
 	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_long *)dest) & data) != data) {
-		return (2);
+	if ((*((vu_long *) dest) & data) != data) {
+		return ERR_NOT_ERASED;
 	}
 	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
+	flag = disable_interrupts ();
 
-#if 0
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00A000A0;
-#else
 	addr[0x0555] = 0xAAAAAAAA;
 	addr[0x02AA] = 0x55555555;
 	addr[0x0555] = 0xA0A0A0A0;
-#endif
 
-	*((vu_long *)dest) = data;
+	*((vu_long *) dest) = data;
 
 	/* re-enable interrupts if necessary */
 	if (flag)
-		enable_interrupts();
+		enable_interrupts ();
 
 	/* data polling for D7 */
 	start = get_timer (0);
-#if 0
-	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080))
-#else
-	while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080))
-#endif
+	while ((*((vu_long *) dest) & 0x80808080) != (data & 0x80808080))
 	{
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
-			return (1);
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			return ERR_TIMOUT;
 		}
 	}
 	return (0);
 }
-
-/*-----------------------------------------------------------------------
- */

board/fads/u-boot.lds

@@ -52,7 +52,7 @@ SECTIONS
   {
     cpu/mpc8xx/start.o		(.text)
 
-    . = DEFINED(env_offset) ? env_offset : .;
+    /*. = DEFINED(env_offset) ? env_offset : .;*/
     common/environment.o	(.ppcenv)
 
     *(.text)

board/gcplus/Makefile

@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# 2003 (c) MontaVista Software, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= gcplus.o flash.o
+SOBJS	:= memsetup.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/gcplus/config.mk

@@ -0,0 +1,13 @@
+#
+# ADS GCPlus board with SA1110 cpu
+#
+# The ADS GCPlus has 2 banks of 16 MiB SDRAM
+#
+# We use the ADS GCPlus Linux boot ROM to load U-Boot into SDRAM
+# at c020'0000 and then move ourself to c8f0'0000. Basically, just
+# install the U-Boot binary as you would the Linux zImage and then
+# reap the benfits of more convenient Linux development cycles, i.e.
+# bootp;tftp;bootm, repeat, etc.,.
+#
+
+TEXT_BASE = 0xc8f00000

board/gcplus/flash.c

@@ -0,0 +1,440 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * 2003 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)				__swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)				__swab32(x)
+#endif
+
+#define FPW				FLASH_PORT_WIDTH
+#define FPWV				FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPW * addr, flash_info_t * info);
+static int write_data(flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+void inline spin_wheel(void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long
+flash_init(void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets(PHYS_FLASH_1, &flash_info[i]);
+			break;
+		default:
+			panic("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_FLASH_BASE,
+		      CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
+
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void
+flash_get_offsets(ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void
+flash_print_info(flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf("INTEL ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf("28F128J3A\n");
+		break;
+	case FLASH_28F640J5:
+		printf("28F640J5\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		break;
+	}
+
+	printf("  Size: %ld MB in %d Sectors\n",
+	       info->size >> 20, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s",
+		       info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong
+flash_get_size(FPW * addr, flash_info_t * info)
+{
+	volatile FPW value;
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);	/* no or unknown flash  */
+	}
+
+	mb();
+	value = addr[1];	/* device ID            */
+	switch (value) {
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x02000000;
+		break;		/* => 16 MB     */
+	case (FPW) INTEL_ID_28F640J5:
+		info->flash_id += FLASH_28F640J5;
+		info->sector_count = 64;
+		info->size = 0x01000000;
+		break;		/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf("** ERROR: sector count %d > max (%d) **\n",
+		       info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int
+flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf("Can't erase unknown flash type %08lx - aborted\n",
+		       info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	} else {
+		printf("\n");
+	}
+
+	start = get_timer(0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked();
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			while (((status =
+				 *addr) & (FPW) 0x00800080) !=
+			       (FPW) 0x00800080) {
+				if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) {
+					printf("Timeout\n");
+					*addr = (FPW) 0x00B000B0;	/* suspend erase         */
+					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = (FPW) 0x00500050;	/* clear status register cmd.   */
+			*addr = (FPW) 0x00FF00FF;	/* resest to read mode          */
+
+			printf(" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int
+write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data(info, wp, SWAP(data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data(info, wp, SWAP(data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data(info, wp, SWAP(data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int
+write_data(flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf("not erased at %08lX (%lX)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline
+spin_wheel(void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}

board/gcplus/gcplus.c

@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * 2003-2004 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <SA-1100.h>
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int
+board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_arch_number = 29;	/* ADS GraphicsClientPlus Board */
+
+	gd->bd->bi_boot_params = 0xc000003c; /* Weird address? */
+
+	/* Most of the ADS GCPlus I/O is connected to Static nCS2.
+	 * So I'm brute forcing nCS2 timiming here for worst case.
+	 */
+	MSC1 &= ~0xFFFF;
+	MSC1 |= 0x8649;
+
+	/* Nothing is connected to Static nCS4 or nCS5. But I'm using
+	 * nCS4 as a paranoia safe guard to force nCS2, nOE; nWE high
+	 * after accessing I/O via (non-VLIO) nCS2. What can I say, I'm
+	 * paranoid and lack decent tools to alleviate my fear. I sure
+	 * do wish I had a logic analyzer. : (
+	 */
+
+	MSC2 =  0xfff9fff9;
+
+	return 0;
+}
+
+int
+dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+	return (0);
+}

board/gcplus/memsetup.S

@@ -0,0 +1,77 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ * 2003-2004 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include "config.h"
+#include "version.h"
+
+
+	.globl	memsetup
+memsetup:
+	/* The ADS GC+ for Linux Boot Rom Ver. 1.73 does memory init for us.
+	 * However the darn thing leaves the MMU enabled before handing control
+	 * over to us. So we need to disable the MMU and we use memsetup
+	 * to do it.
+	 */
+
+@ The following code segment was borrowed with gratitude from:
+@	linux-2.4.19-rmk7/arch/arm/boot/compressed/head-sa1100.S
+
+	@ Data cache might be active.
+	@ Be sure to flush kernel binary out of the cache,
+	@ whatever state it is, before it is turned off.
+	@ This is done by fetching through currently executed
+	@ memory to be sure we hit the same cache.
+	bic	r2, pc, #0x1f
+	add	r3, r2, #0x4000		@ 16 kb is quite enough...
+1:	ldr	r0, [r2], #32
+	teq	r2, r3
+	bne	1b
+	mcr	p15, 0, r0, c7, c10, 4	@ drain WB
+	mcr	p15, 0, r0, c7, c7, 0	@ flush I & D caches
+
+	@ disabling MMU and caches
+	mrc	p15, 0, r0, c1, c0, 0	@ read control reg
+	bic	r0, r0, #0x0d		@ clear WB, DC, MMU
+	bic	r0, r0, #0x1000		@ clear Icache
+	mcr	p15, 0, r0, c1, c0, 0
+
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	b	2f
+2:
+	nop
+	nop
+	nop
+	nop
+	nop
+
+
+	mov	pc, lr

board/gcplus/u-boot.lds

@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * 2003 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+		cpu/sa1100/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/gen860t/fpga.c

@@ -72,30 +72,27 @@ Xilinx_Virtex2_Slave_SelectMap_fns fpga_fns = {
 };
 
 Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
-	{ Xilinx_Virtex2,
-	  slave_selectmap,
-	  XILINX_XC2V3000_SIZE,
-	  (void *)&fpga_fns,
-	  0
-	}
+	{Xilinx_Virtex2,
+	 slave_selectmap,
+	 XILINX_XC2V3000_SIZE,
+	 (void *) &fpga_fns,
+	 0}
 };
 
 /*
  * Display FPGA revision information
  */
-void
-print_fpga_revision(void)
+void print_fpga_revision (void)
 {
-	vu_long *rev_p = (vu_long *)0x60000008;
+	vu_long *rev_p = (vu_long *) 0x60000008;
 
-	printf("FPGA Revision 0x%.8lx"
-		   " (Date %.2lx/%.2lx/%.2lx, Status \"%.1lx\", Version %.3lu)\n",
-		   *rev_p,
-		   ((*rev_p >> 28) & 0xf),
-		   ((*rev_p >> 20) & 0xff),
-		   ((*rev_p >> 12) & 0xff),
-		   ((*rev_p >> 8) & 0xf),
-		   (*rev_p & 0xff));
+	printf ("FPGA Revision 0x%.8lx"
+		" (Date %.2lx/%.2lx/%.2lx, Status \"%.1lx\", Version %.3lu)\n",
+		*rev_p,
+		((*rev_p >> 28) & 0xf),
+		((*rev_p >> 20) & 0xff),
+		((*rev_p >> 12) & 0xff),
+		((*rev_p >> 8) & 0xf), (*rev_p & 0xff));
 }
 
 
@@ -106,10 +103,9 @@ print_fpga_revision(void)
  * problems with bus charging.
  * Return 0 on failure, 1 on success.
  */
-int
-test_fpga_ibtr(void)
+int test_fpga_ibtr (void)
 {
-	vu_long *ibtr_p = (vu_long *)0x60000010;
+	vu_long *ibtr_p = (vu_long *) 0x60000010;
 	vu_long readback;
 	vu_long compare;
 	int i;
@@ -118,40 +114,41 @@ test_fpga_ibtr(void)
 	int pass = 1;
 
 	static const ulong bitpattern[] = {
-		0xdeadbeef,	/* magic ID pattern for debug	*/
-		0x00000001,	/* single bit					*/
-		0x00000003,	/* two adjacent bits			*/
-		0x00000007,	/* three adjacent bits			*/
-		0x0000000F,	/* four adjacent bits			*/
-		0x00000005,	/* two non-adjacent bits		*/
-		0x00000015,	/* three non-adjacent bits		*/
-		0x00000055,	/* four non-adjacent bits		*/
-		0xaaaaaaaa,	/* alternating 1/0				*/
+		0xdeadbeef,	/* magic ID pattern for debug   */
+		0x00000001,	/* single bit                                   */
+		0x00000003,	/* two adjacent bits                    */
+		0x00000007,	/* three adjacent bits                  */
+		0x0000000F,	/* four adjacent bits                   */
+		0x00000005,	/* two non-adjacent bits                */
+		0x00000015,	/* three non-adjacent bits              */
+		0x00000055,	/* four non-adjacent bits               */
+		0xaaaaaaaa,	/* alternating 1/0                              */
 	};
 
 	for (i = 0; i < 1024; i++) {
 		for (j = 0; j < 31; j++) {
-			for (k = 0; k < sizeof(bitpattern)/sizeof(bitpattern[0]); k++) {
+			for (k = 0;
+			     k < sizeof (bitpattern) / sizeof (bitpattern[0]);
+			     k++) {
 				*ibtr_p = compare = (bitpattern[k] << j);
 				readback = *ibtr_p;
 				if (readback != ~compare) {
-					printf("%s:%d: FPGA test fail: expected 0x%.8lx"
-						   " actual 0x%.8lx\n",
-						   __FUNCTION__, __LINE__, ~compare, readback);
+					printf ("%s:%d: FPGA test fail: expected 0x%.8lx" " actual 0x%.8lx\n", __FUNCTION__, __LINE__, ~compare, readback);
 					pass = 0;
 					break;
 				}
 			}
-			if (!pass) break;
+			if (!pass)
+				break;
 		}
-		if (!pass) break;
+		if (!pass)
+			break;
 	}
 	if (pass) {
-		printf("FPGA inverting bus test passed\n");
-		print_fpga_revision();
-	}
-	else {
-		printf("** FPGA inverting bus test failed\n");
+		printf ("FPGA inverting bus test passed\n");
+		print_fpga_revision ();
+	} else {
+		printf ("** FPGA inverting bus test failed\n");
 	}
 	return pass;
 }
@@ -160,19 +157,17 @@ test_fpga_ibtr(void)
 /*
  * Set the active-low FPGA reset signal.
  */
-void
-fpga_reset(int assert)
+void fpga_reset (int assert)
 {
-    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 
-	PRINTF("%s:%d: RESET ", __FUNCTION__, __LINE__);
+	PRINTF ("%s:%d: RESET ", __FUNCTION__, __LINE__);
 	if (assert) {
 		immap->im_ioport.iop_pcdat &= ~(0x8000 >> FPGA_RESET_BIT_NUM);
-		PRINTF("asserted\n");
-	}
-	else {
+		PRINTF ("asserted\n");
+	} else {
 		immap->im_ioport.iop_pcdat |= (0x8000 >> FPGA_RESET_BIT_NUM);
-		PRINTF("deasserted\n");
+		PRINTF ("deasserted\n");
 	}
 }
 
@@ -181,54 +176,52 @@ fpga_reset(int assert)
  * Initialize the SelectMap interface.  We assume that the mode and the
  * initial state of all of the port pins have already been set!
  */
-void
-fpga_selectmap_init(void)
+void fpga_selectmap_init (void)
 {
-	PRINTF("%s:%d: Initialize SelectMap interface\n", __FUNCTION__, __LINE__);
-	fpga_pgm_fn(FALSE, FALSE, 0);   /* make sure program pin is inactive */
+	PRINTF ("%s:%d: Initialize SelectMap interface\n", __FUNCTION__,
+		__LINE__);
+	fpga_pgm_fn (FALSE, FALSE, 0);	/* make sure program pin is inactive */
 }
 
 
 /*
  * Initialize the fpga.  Return 1 on success, 0 on failure.
  */
-int
-gen860t_init_fpga(void)
+int gen860t_init_fpga (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 
 	int i;
 
-	PRINTF("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n",
-			__FUNCTION__, __LINE__, gd->reloc_off);
-	fpga_init(gd->reloc_off);
-	fpga_selectmap_init();
+	PRINTF ("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n", __FUNCTION__, __LINE__, gd->reloc_off);
+	fpga_init (gd->reloc_off);
+	fpga_selectmap_init ();
 
-	for(i=0; i < CONFIG_FPGA_COUNT; i++) {
-		PRINTF("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
-		fpga_add(fpga_xilinx, &fpga[i]);
+	for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
+		PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
+		fpga_add (fpga_xilinx, &fpga[i]);
 	}
- 	return 1;
+	return 1;
 }
 
 
 /*
  * Set the FPGA's active-low SelectMap program line to the specified level
  */
-int
-fpga_pgm_fn(int assert, int flush, int cookie)
+int fpga_pgm_fn (int assert, int flush, int cookie)
 {
-    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 
-	PRINTF("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__);
+	PRINTF ("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__);
 
 	if (assert) {
-		immap->im_ioport.iop_padat &= ~(0x8000 >> FPGA_PROGRAM_BIT_NUM);
-		PRINTF("asserted\n");
-	}
-	else {
-		immap->im_ioport.iop_padat |= (0x8000 >> FPGA_PROGRAM_BIT_NUM);
-		PRINTF("deasserted\n");
+		immap->im_ioport.iop_padat &=
+			~(0x8000 >> FPGA_PROGRAM_BIT_NUM);
+		PRINTF ("asserted\n");
+	} else {
+		immap->im_ioport.iop_padat |=
+			(0x8000 >> FPGA_PROGRAM_BIT_NUM);
+		PRINTF ("deasserted\n");
 	}
 	return assert;
 }
@@ -238,18 +231,16 @@ fpga_pgm_fn(int assert, int flush, int cookie)
  * Test the state of the active-low FPGA INIT line.  Return 1 on INIT
  * asserted (low).
  */
-int
-fpga_init_fn(int cookie)
+int fpga_init_fn (int cookie)
 {
-    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 
-	PRINTF("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
-	if(immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_INIT_BIT_NUM)) {
-		PRINTF("high\n");
+	PRINTF ("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
+	if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_INIT_BIT_NUM)) {
+		PRINTF ("high\n");
 		return 0;
-	}
-	else {
-		PRINTF("low\n");
+	} else {
+		PRINTF ("low\n");
 		return 1;
 	}
 }
@@ -258,18 +249,16 @@ fpga_init_fn(int cookie)
 /*
  * Test the state of the active-high FPGA DONE pin
  */
-int
-fpga_done_fn(int cookie)
+int fpga_done_fn (int cookie)
 {
-    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 
-	PRINTF("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
+	PRINTF ("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
 	if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_DONE_BIT_NUM)) {
-		PRINTF("high\n");
+		PRINTF ("high\n");
 		return FPGA_SUCCESS;
-	}
-	else {
-		PRINTF("low\n");
+	} else {
+		PRINTF ("low\n");
 		return FPGA_FAIL;
 	}
 }
@@ -278,43 +267,40 @@ fpga_done_fn(int cookie)
 /*
  * Read FPGA SelectMap data.
  */
-int
-fpga_read_data_fn(unsigned char *data, int cookie)
+int fpga_read_data_fn (unsigned char *data, int cookie)
 {
-	vu_char *p = (vu_char *)SELECTMAP_BASE;
+	vu_char *p = (vu_char *) SELECTMAP_BASE;
 
 	*data = *p;
 #if 0
-	PRINTF("%s: Read 0x%x into 0x%p\n", __FUNCTION__, (int)data, data);
+	PRINTF ("%s: Read 0x%x into 0x%p\n", __FUNCTION__, (int) data, data);
 #endif
-	return (int)data;
+	return (int) data;
 }
 
 
 /*
  * Write data to the FPGA SelectMap port
  */
-int
-fpga_write_data_fn(unsigned char data, int flush, int cookie)
+int fpga_write_data_fn (unsigned char data, int flush, int cookie)
 {
-	vu_char *p = (vu_char *)SELECTMAP_BASE;
+	vu_char *p = (vu_char *) SELECTMAP_BASE;
 
 #if 0
-	PRINTF("%s: Write Data 0x%x\n", __FUNCTION__, (int)data);
+	PRINTF ("%s: Write Data 0x%x\n", __FUNCTION__, (int) data);
 #endif
 	*p = data;
-	return (int)data;
+	return (int) data;
 }
 
 
 /*
  * Abort and FPGA operation
  */
-int
-fpga_abort_fn(int cookie)
+int fpga_abort_fn (int cookie)
 {
-	PRINTF("%s:%d: FPGA program sequence aborted\n",
-		   __FUNCTION__, __LINE__);
+	PRINTF ("%s:%d: FPGA program sequence aborted\n",
+		__FUNCTION__, __LINE__);
 	return FPGA_FAIL;
 }
 
@@ -324,11 +310,10 @@ fpga_abort_fn(int cookie)
  * FPGA reset is asserted to keep the FPGA from starting up after
  * configuration.
  */
-int
-fpga_pre_config_fn(int cookie)
+int fpga_pre_config_fn (int cookie)
 {
-	PRINTF("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
-	fpga_reset(TRUE);
+	PRINTF ("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
+	fpga_reset (TRUE);
 	return 0;
 }
 
@@ -337,22 +322,21 @@ fpga_pre_config_fn(int cookie)
  * FPGA post configuration function. Blip the FPGA reset line and then see if
  * the FPGA appears to be running.
  */
-int
-fpga_post_config_fn(int cookie)
+int fpga_post_config_fn (int cookie)
 {
 	int rc;
 
-	PRINTF("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__);
-	fpga_reset(TRUE);
-	udelay(1000);
-	fpga_reset(FALSE);
+	PRINTF ("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__);
+	fpga_reset (TRUE);
+	udelay (1000);
+	fpga_reset (FALSE);
 	udelay (1000);
 
 	/*
 	 * Use the FPGA,s inverting bus test register to do a simple test of the
 	 * processor interface.
 	 */
-	rc = test_fpga_ibtr();
+	rc = test_fpga_ibtr ();
 	return rc;
 }
 
@@ -367,32 +351,27 @@ fpga_post_config_fn(int cookie)
  * going low during configuration, so there is no need for a separate error
  * function.
  */
-int
-fpga_clk_fn(int assert_clk, int flush, int cookie)
+int fpga_clk_fn (int assert_clk, int flush, int cookie)
 {
 	return assert_clk;
 }
 
-int
-fpga_cs_fn(int assert_cs, int flush, int cookie)
+int fpga_cs_fn (int assert_cs, int flush, int cookie)
 {
 	return assert_cs;
 }
 
-int
-fpga_wr_fn(int assert_write, int flush, int cookie)
+int fpga_wr_fn (int assert_write, int flush, int cookie)
 {
 	return assert_write;
 }
 
-int
-fpga_err_fn(int cookie)
+int fpga_err_fn (int cookie)
 {
 	return 0;
 }
 
-int
-fpga_busy_fn(int cookie)
+int fpga_busy_fn (int cookie)
 {
 	return 0;
 }

board/gen860t/gen860t.c

@@ -94,7 +94,7 @@ const uint sdram_upm_table[] = {
 	0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff,
 	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
 	/* exception     (offset 0x3C in upm ram) */
-   };
+};
 
 const uint selectmap_upm_table[] = {
 	/* single read   (offset 0x00 in upm ram) */
@@ -124,63 +124,61 @@ const uint selectmap_upm_table[] = {
 /*
  * Check board identity.  Always successful (gives information only)
  */
-int
-checkboard(void)
+int checkboard (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 
-    unsigned char *s;
-    unsigned char buf[64];
-    int i;
+	unsigned char *s;
+	unsigned char buf[64];
+	int i;
 
-    i = getenv_r("board_id", buf, sizeof(buf));
-    s = (i>0) ? buf : NULL;
+	i = getenv_r ("board_id", buf, sizeof (buf));
+	s = (i > 0) ? buf : NULL;
 
 	if (s) {
-		printf("%s ", s);
+		printf ("%s ", s);
 	} else {
-		printf("<unknown> ");
+		printf ("<unknown> ");
 	}
 
-    i = getenv_r("serial#", buf, sizeof(buf));
-    s = (i>0) ? buf : NULL;
+	i = getenv_r ("serial#", buf, sizeof (buf));
+	s = (i > 0) ? buf : NULL;
 
 	if (s) {
-		printf("S/N %s\n", s);
+		printf ("S/N %s\n", s);
 	} else {
-		printf("S/N <unknown>\n");
+		printf ("S/N <unknown>\n");
 	}
 
-    printf("CPU at %s MHz, ",strmhz(buf, gd->cpu_clk));
-	printf("local bus at %s MHz\n", strmhz(buf, gd->bus_clk));
-    return (0);
+	printf ("CPU at %s MHz, ", strmhz (buf, gd->cpu_clk));
+	printf ("local bus at %s MHz\n", strmhz (buf, gd->bus_clk));
+	return (0);
 }
 
 /*
  * Initialize SDRAM
  */
-long int
-initdram(int board_type)
+long int initdram (int board_type)
 {
-    volatile immap_t     *immr  = (immap_t *)CFG_IMMR;
-    volatile memctl8xx_t *memctl = &immr->im_memctl;
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immr->im_memctl;
 
-    upmconfig(UPMA,
-			  (uint *)sdram_upm_table,
-			  sizeof(sdram_upm_table) / sizeof(uint)
-			 );
+	upmconfig (UPMA,
+		   (uint *) sdram_upm_table,
+		   sizeof (sdram_upm_table) / sizeof (uint)
+		);
 
-    /*
-     * Setup MAMR register
-     */
-    memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
-    memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
+	/*
+	 * Setup MAMR register
+	 */
+	memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
+	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
 
-    /*
-     * Map CS1* to SDRAM bank
-     */
-    memctl->memc_or1 = CFG_OR1;
-    memctl->memc_br1 = CFG_BR1;
+	/*
+	 * Map CS1* to SDRAM bank
+	 */
+	memctl->memc_or1 = CFG_OR1;
+	memctl->memc_br1 = CFG_BR1;
 
 	/*
 	 * Perform SDRAM initialization sequence:
@@ -193,31 +191,31 @@ initdram(int board_type)
 	 * Program SDRAM for standard operation, sequential burst, burst length
 	 * of 4, CAS latency of 2.
 	 */
-    memctl->memc_mar = 0x00000000;
+	memctl->memc_mar = 0x00000000;
 	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
-					   MCR_MLCF(0) | UPMA_NOP_ADDR;
-	udelay(200);
-    memctl->memc_mar = 0x00000000;
+		MCR_MLCF (0) | UPMA_NOP_ADDR;
+	udelay (200);
+	memctl->memc_mar = 0x00000000;
 	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
-					   MCR_MLCF(4) | UPMA_PRECHARGE_ADDR;
+		MCR_MLCF (4) | UPMA_PRECHARGE_ADDR;
 
-    memctl->memc_mar = 0x00000000;
+	memctl->memc_mar = 0x00000000;
 	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
-					   MCR_MLCF(2) | UPM_REFRESH_ADDR;
+		MCR_MLCF (2) | UPM_REFRESH_ADDR;
 
-    memctl->memc_mar = 0x00000088;
+	memctl->memc_mar = 0x00000088;
 	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
-					   MCR_MLCF(1) | UPMA_MRS_ADDR;
+		MCR_MLCF (1) | UPMA_MRS_ADDR;
 
-    memctl->memc_mar = 0x00000000;
+	memctl->memc_mar = 0x00000000;
 	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
-					   MCR_MLCF(0) | UPMA_NOP_ADDR;
+		MCR_MLCF (0) | UPMA_NOP_ADDR;
 	/*
 	 * Enable refresh
 	 */
-    memctl->memc_mamr |= MAMR_PTAE;
+	memctl->memc_mamr |= MAMR_PTAE;
 
-    return (SDRAM_SIZE);
+	return (SDRAM_SIZE);
 }
 
 /*
@@ -225,42 +223,39 @@ initdram(int board_type)
  * The DOC lives in the CS2* space
  */
 #if (CONFIG_COMMANDS & CFG_CMD_DOC)
-extern void
-doc_probe(ulong physadr);
+extern void doc_probe (ulong physadr);
 
-void
-doc_init(void)
+void doc_init (void)
 {
-	printf("Probing at 0x%.8x: ", DOC_BASE);
-	doc_probe(DOC_BASE);
+	printf ("Probing at 0x%.8x: ", DOC_BASE);
+	doc_probe (DOC_BASE);
 }
 #endif
 
 /*
  * Miscellaneous intialization
  */
-int
-misc_init_r (void)
+int misc_init_r (void)
 {
-    volatile immap_t     *immr  = (immap_t *)CFG_IMMR;
-    volatile memctl8xx_t *memctl = &immr->im_memctl;
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immr->im_memctl;
 
 	/*
 	 * Set up UPMB to handle the Virtex FPGA SelectMap interface
 	 */
-	upmconfig(UPMB, (uint *)selectmap_upm_table,
-			  sizeof(selectmap_upm_table) / sizeof(uint));
+	upmconfig (UPMB, (uint *) selectmap_upm_table,
+		   sizeof (selectmap_upm_table) / sizeof (uint));
 
-    memctl->memc_mbmr = 0x0;
+	memctl->memc_mbmr = 0x0;
 
-	config_mpc8xx_ioports(immr);
+	config_mpc8xx_ioports (immr);
 
 #if (CONFIG_COMMANDS & CFG_CMD_MII)
-	mii_init();
+	mii_init ();
 #endif
 
 #if (CONFIG_FPGA)
-	gen860t_init_fpga();
+	gen860t_init_fpga ();
 #endif
 	return 0;
 }
@@ -268,8 +263,7 @@ misc_init_r (void)
 /*
  * Final init hook before entering command loop.
  */
-int
-last_stage_init(void)
+int last_stage_init (void)
 {
 #if !defined(CONFIG_SC)
 	unsigned char buf[256];
@@ -278,15 +272,15 @@ last_stage_init(void)
 	/*
 	 * Turn the beeper volume all the way down in case this is a warm boot.
 	 */
-	set_beeper_volume(-64);
-	init_beeper();
+	set_beeper_volume (-64);
+	init_beeper ();
 
 	/*
 	 * Read the environment to see what to do with the beeper
 	 */
-    i = getenv_r("beeper", buf, sizeof(buf));
+	i = getenv_r ("beeper", buf, sizeof (buf));
 	if (i > 0) {
-		do_beeper(buf);
+		do_beeper (buf);
 	}
 #endif
 	return 0;
@@ -295,11 +289,10 @@ last_stage_init(void)
 /*
  * Stub to make POST code happy.  Can't self-poweroff, so just hang.
  */
-void
-board_poweroff(void)
+void board_poweroff (void)
 {
-	puts("### Please power off the board ###\n");
-    while (1);
+	puts ("### Please power off the board ###\n");
+	while (1);
 }
 
 #ifdef CONFIG_POST
@@ -307,9 +300,9 @@ board_poweroff(void)
  * Returns 1 if keys pressed to start the power-on long-running tests
  * Called from board_init_f().
  */
-int post_hotkeys_pressed(void)
+int post_hotkeys_pressed (void)
 {
-	return 0;	/* No hotkeys supported */
+	return 0;		/* No hotkeys supported */
 }
 #endif
 

board/gen860t/ioport.c

@@ -199,16 +199,16 @@ const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = {
  * Configure the MPC8XX I/O ports per the ioport configuration table
  * (taken from ./cpu/mpc8260/cpu_init.c)
  */
-void
-config_mpc8xx_ioports(volatile immap_t *immr)
+void config_mpc8xx_ioports (volatile immap_t * immr)
 {
-    int portnum;
+	int portnum;
 
-    for (portnum = 0; portnum < NUM_PORTS; portnum++) {
+	for (portnum = 0; portnum < NUM_PORTS; portnum++) {
 		uint pmsk = 0, ppar = 0, psor = 0, pdir = 0;
 		uint podr = 0, pdat = 0, pint = 0;
 		uint msk = 1;
-		mpc8xx_iop_conf_t *iopc = (mpc8xx_iop_conf_t *)&iop_conf_tab[portnum][0];
+		mpc8xx_iop_conf_t *iopc =
+			(mpc8xx_iop_conf_t *) & iop_conf_tab[portnum][0];
 		mpc8xx_iop_conf_t *eiopc = iopc + PORT_BITS;
 
 		/*
@@ -216,104 +216,132 @@ config_mpc8xx_ioports(volatile immap_t *immr)
 		 * in the configuration tables.
 		 */
 		if (portnum != 1) {
-			iopc = (mpc8xx_iop_conf_t *)&iop_conf_tab[portnum][2];
+			iopc = (mpc8xx_iop_conf_t *) &
+				iop_conf_tab[portnum][2];
 		}
 
 		/*
 		 * NOTE: index 0 refers to pin 17, index 17 refers to pin 0
 		 */
 		while (iopc < eiopc) {
-	    	if (iopc->conf) {
+			if (iopc->conf) {
 				pmsk |= msk;
-				if (iopc->ppar) ppar |= msk;
-				if (iopc->psor) psor |= msk;
-				if (iopc->pdir) pdir |= msk;
-				if (iopc->podr) podr |= msk;
-				if (iopc->pdat) pdat |= msk;
-				if (iopc->pint) pint |= msk;
-		    }
-		    msk <<= 1;
-	  	  iopc++;
+				if (iopc->ppar)
+					ppar |= msk;
+				if (iopc->psor)
+					psor |= msk;
+				if (iopc->pdir)
+					pdir |= msk;
+				if (iopc->podr)
+					podr |= msk;
+				if (iopc->pdat)
+					pdat |= msk;
+				if (iopc->pint)
+					pint |= msk;
+			}
+			msk <<= 1;
+			iopc++;
 		}
 
-		PRINTF("%s:%d:\n  portnum=%d ", __FUNCTION__, __LINE__, portnum);
+		PRINTF ("%s:%d:\n  portnum=%d ", __FUNCTION__, __LINE__,
+			portnum);
 #ifdef IOPORT_DEBUG
-		switch(portnum) {
-			case 0: printf("(A)\n"); break;
-			case 1: printf("(B)\n"); break;
-			case 2: printf("(C)\n"); break;
-			case 3: printf("(D)\n"); break;
-			default: printf("(?)\n"); break;
+		switch (portnum) {
+		case 0:
+			printf ("(A)\n");
+			break;
+		case 1:
+			printf ("(B)\n");
+			break;
+		case 2:
+			printf ("(C)\n");
+			break;
+		case 3:
+			printf ("(D)\n");
+			break;
+		default:
+			printf ("(?)\n");
+			break;
 		}
 #endif
-		PRINTF("  ppar=0x%.8x  pdir=0x%.8x  podr=0x%.8x\n"
-			   "  pdat=0x%.8x  psor=0x%.8x  pint=0x%.8x  pmsk=0x%.8x\n",
-			   ppar, pdir, podr, pdat, psor, pint, pmsk);
+		PRINTF ("  ppar=0x%.8x  pdir=0x%.8x  podr=0x%.8x\n"
+			"  pdat=0x%.8x  psor=0x%.8x  pint=0x%.8x  pmsk=0x%.8x\n",
+			ppar, pdir, podr, pdat, psor, pint, pmsk);
 
 		/*
 		 * Have to handle the ioports on a port-by-port basis since there
 		 * are three different flavors.
 		 */
 		if (pmsk != 0) {
-		    uint tpmsk = ~pmsk;
+			uint tpmsk = ~pmsk;
 
-			if (0 == portnum) { /* port A */
-		    	immr->im_ioport.iop_papar &= tpmsk;
-		    	immr->im_ioport.iop_padat =
-					(immr->im_ioport.iop_padat & tpmsk) | pdat;
-		    	immr->im_ioport.iop_padir =
-					(immr->im_ioport.iop_padir & tpmsk) | pdir;
-		    	immr->im_ioport.iop_paodr =
-					(immr->im_ioport.iop_paodr & tpmsk) | podr;
-		    	immr->im_ioport.iop_papar |= ppar;
-			}
-			else if (1 == portnum) { /* port B */
-		    	immr->im_cpm.cp_pbpar &= tpmsk;
-		    	immr->im_cpm.cp_pbdat = (immr->im_cpm.cp_pbdat & tpmsk) | pdat;
-		    	immr->im_cpm.cp_pbdir = (immr->im_cpm.cp_pbdir & tpmsk) | pdir;
-		    	immr->im_cpm.cp_pbodr = (immr->im_cpm.cp_pbodr & tpmsk) | podr;
-		    	immr->im_cpm.cp_pbpar |= ppar;
-			}
-			else if (2 == portnum) { /* port C */
-		    	immr->im_ioport.iop_pcpar &= tpmsk;
-		    	immr->im_ioport.iop_pcdat =
-					(immr->im_ioport.iop_pcdat & tpmsk) | pdat;
-		    	immr->im_ioport.iop_pcdir =
-					(immr->im_ioport.iop_pcdir & tpmsk) | pdir;
-		    	immr->im_ioport.iop_pcint =
-					(immr->im_ioport.iop_pcint & tpmsk) | pint;
-		    	immr->im_ioport.iop_pcso =
-					(immr->im_ioport.iop_pcso & tpmsk) | psor;
-		    	immr->im_ioport.iop_pcpar |= ppar;
-			}
-			else if (3 == portnum) { /* port D */
-		    	immr->im_ioport.iop_pdpar &= tpmsk;
-		    	immr->im_ioport.iop_pddat =
-					(immr->im_ioport.iop_pddat & tpmsk) | pdat;
-		    	immr->im_ioport.iop_pddir =
-					(immr->im_ioport.iop_pddir & tpmsk) | pdir;
-		    	immr->im_ioport.iop_pdpar |= ppar;
+			if (0 == portnum) {	/* port A */
+				immr->im_ioport.iop_papar &= tpmsk;
+				immr->im_ioport.iop_padat =
+					(immr->im_ioport.
+					 iop_padat & tpmsk) | pdat;
+				immr->im_ioport.iop_padir =
+					(immr->im_ioport.
+					 iop_padir & tpmsk) | pdir;
+				immr->im_ioport.iop_paodr =
+					(immr->im_ioport.
+					 iop_paodr & tpmsk) | podr;
+				immr->im_ioport.iop_papar |= ppar;
+			} else if (1 == portnum) {	/* port B */
+				immr->im_cpm.cp_pbpar &= tpmsk;
+				immr->im_cpm.cp_pbdat =
+					(immr->im_cpm.
+					 cp_pbdat & tpmsk) | pdat;
+				immr->im_cpm.cp_pbdir =
+					(immr->im_cpm.
+					 cp_pbdir & tpmsk) | pdir;
+				immr->im_cpm.cp_pbodr =
+					(immr->im_cpm.
+					 cp_pbodr & tpmsk) | podr;
+				immr->im_cpm.cp_pbpar |= ppar;
+			} else if (2 == portnum) {	/* port C */
+				immr->im_ioport.iop_pcpar &= tpmsk;
+				immr->im_ioport.iop_pcdat =
+					(immr->im_ioport.
+					 iop_pcdat & tpmsk) | pdat;
+				immr->im_ioport.iop_pcdir =
+					(immr->im_ioport.
+					 iop_pcdir & tpmsk) | pdir;
+				immr->im_ioport.iop_pcint =
+					(immr->im_ioport.
+					 iop_pcint & tpmsk) | pint;
+				immr->im_ioport.iop_pcso =
+					(immr->im_ioport.
+					 iop_pcso & tpmsk) | psor;
+				immr->im_ioport.iop_pcpar |= ppar;
+			} else if (3 == portnum) {	/* port D */
+				immr->im_ioport.iop_pdpar &= tpmsk;
+				immr->im_ioport.iop_pddat =
+					(immr->im_ioport.
+					 iop_pddat & tpmsk) | pdat;
+				immr->im_ioport.iop_pddir =
+					(immr->im_ioport.
+					 iop_pddir & tpmsk) | pdir;
+				immr->im_ioport.iop_pdpar |= ppar;
 			}
 		}
-    }
+	}
 
-	PRINTF("%s:%d: Port A:\n  papar=0x%.4x  padir=0x%.4x"
-		   "  paodr=0x%.4x\n  padat=0x%.4x\n", __FUNCTION__, __LINE__,
-		   immr->im_ioport.iop_papar, immr->im_ioport.iop_padir,
-		   immr->im_ioport.iop_paodr, immr->im_ioport.iop_padat);
-	PRINTF("%s:%d: Port B:\n  pbpar=0x%.8x  pbdir=0x%.8x"
-		   "  pbodr=0x%.8x\n  pbdat=0x%.8x\n", __FUNCTION__, __LINE__,
-		   immr->im_cpm.cp_pbpar, immr->im_cpm.cp_pbdir,
-		   immr->im_cpm.cp_pbodr, immr->im_cpm.cp_pbdat);
-	PRINTF("%s:%d: Port C:\n  pcpar=0x%.4x  pcdir=0x%.4x"
-		   "  pcdat=0x%.4x\n  pcso=0x%.4x  pcint=0x%.4x\n  ",
-		   __FUNCTION__, __LINE__, immr->im_ioport.iop_pcpar,
-		   immr->im_ioport.iop_pcdir, immr->im_ioport.iop_pcdat,
-		   immr->im_ioport.iop_pcso, immr->im_ioport.iop_pcint);
-	PRINTF("%s:%d: Port D:\n  pdpar=0x%.4x  pddir=0x%.4x"
-		   "  pddat=0x%.4x\n", __FUNCTION__, __LINE__,
-		   immr->im_ioport.iop_pdpar, immr->im_ioport.iop_pddir,
-		   immr->im_ioport.iop_pddat);
+	PRINTF ("%s:%d: Port A:\n  papar=0x%.4x  padir=0x%.4x"
+		"  paodr=0x%.4x\n  padat=0x%.4x\n", __FUNCTION__, __LINE__,
+		immr->im_ioport.iop_papar, immr->im_ioport.iop_padir,
+		immr->im_ioport.iop_paodr, immr->im_ioport.iop_padat);
+	PRINTF ("%s:%d: Port B:\n  pbpar=0x%.8x  pbdir=0x%.8x"
+		"  pbodr=0x%.8x\n  pbdat=0x%.8x\n", __FUNCTION__, __LINE__,
+		immr->im_cpm.cp_pbpar, immr->im_cpm.cp_pbdir,
+		immr->im_cpm.cp_pbodr, immr->im_cpm.cp_pbdat);
+	PRINTF ("%s:%d: Port C:\n  pcpar=0x%.4x  pcdir=0x%.4x"
+		"  pcdat=0x%.4x\n  pcso=0x%.4x  pcint=0x%.4x\n  ",
+		__FUNCTION__, __LINE__, immr->im_ioport.iop_pcpar,
+		immr->im_ioport.iop_pcdir, immr->im_ioport.iop_pcdat,
+		immr->im_ioport.iop_pcso, immr->im_ioport.iop_pcint);
+	PRINTF ("%s:%d: Port D:\n  pdpar=0x%.4x  pddir=0x%.4x"
+		"  pddat=0x%.4x\n", __FUNCTION__, __LINE__,
+		immr->im_ioport.iop_pdpar, immr->im_ioport.iop_pddir,
+		immr->im_ioport.iop_pddat);
 }
-
-/* vim: set ts=4 sw=4 tw=78: */

board/gw8260/gw8260.c

@@ -212,16 +212,17 @@ const iop_conf_t iop_conf_tab[4][32] = {
 /*								     */
 /*								     */
 /*********************************************************************/
-int checkboard(void)
+int checkboard (void)
 {
-    char *str;
-    puts ("Board: Advent Networks gw8260\n");
+	char *str;
 
-    str = getenv("serial#");
-    if (str != NULL) {
-	printf("SN:    %s\n", str);
-    }
-    return 0;
+	puts ("Board: Advent Networks gw8260\n");
+
+	str = getenv ("serial#");
+	if (str != NULL) {
+		printf ("SN:    %s\n", str);
+	}
+	return 0;
 }
 
 
@@ -246,30 +247,31 @@ int checkboard(void)
 /*   May cloober fr0.						     */
 /*								     */
 /*********************************************************************/
-static void move64(unsigned long long *src, unsigned long long *dest)
+static void move64 (unsigned long long *src, unsigned long long *dest)
 {
-	asm ("lfd  0, 0(3)\n\t" /* fpr0	  =  *scr	*/
-	 "stfd 0, 0(4)"		/* *dest  =  fpr0	*/
-	 : : : "fr0" );		/* Clobbers fr0		*/
-    return;
+	asm ("lfd  0, 0(3)\n\t"	/* fpr0   =  *scr       */
+	     "stfd 0, 0(4)"	/* *dest  =  fpr0       */
+      : : : "fr0");		/* Clobbers fr0         */
+	return;
 }
 
 
 #if defined (CFG_DRAM_TEST_DATA)
 
-unsigned long long pattern[]= {
-    0xaaaaaaaaaaaaaaaa,
-    0xcccccccccccccccc,
-    0xf0f0f0f0f0f0f0f0,
-    0xff00ff00ff00ff00,
-    0xffff0000ffff0000,
-    0xffffffff00000000,
-    0x00000000ffffffff,
-    0x0000ffff0000ffff,
-    0x00ff00ff00ff00ff,
-    0x0f0f0f0f0f0f0f0f,
-    0x3333333333333333,
-    0x5555555555555555};
+unsigned long long pattern[] = {
+	0xaaaaaaaaaaaaaaaa,
+	0xcccccccccccccccc,
+	0xf0f0f0f0f0f0f0f0,
+	0xff00ff00ff00ff00,
+	0xffff0000ffff0000,
+	0xffffffff00000000,
+	0x00000000ffffffff,
+	0x0000ffff0000ffff,
+	0x00ff00ff00ff00ff,
+	0x0f0f0f0f0f0f0f0f,
+	0x3333333333333333,
+	0x5555555555555555
+};
 
 /*********************************************************************/
 /* NAME:  mem_test_data() -  test data lines for shorts and opens    */
@@ -315,34 +317,34 @@ unsigned long long pattern[]= {
 /*  Assumes only one one SDRAM bank				     */
 /*								     */
 /*********************************************************************/
-int mem_test_data(void)
+int mem_test_data (void)
 {
-    unsigned long long * pmem =
-	(unsigned long long *)CFG_SDRAM_BASE ;
-    unsigned long long temp64;
-    int num_patterns = sizeof(pattern)/ sizeof(pattern[0]);
-    int i;
-    unsigned int hi, lo;
+	unsigned long long *pmem = (unsigned long long *) CFG_SDRAM_BASE;
+	unsigned long long temp64;
+	int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
+	int i;
+	unsigned int hi, lo;
 
-    for ( i = 0; i < num_patterns; i++) {
-	move64(&(pattern[i]), pmem);
-	move64(pmem, &temp64);
+	for (i = 0; i < num_patterns; i++) {
+		move64 (&(pattern[i]), pmem);
+		move64 (pmem, &temp64);
 
-	/* hi = (temp64>>32) & 0xffffffff;	    */
-	/* lo = temp64 & 0xffffffff;		    */
-	/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
+		/* hi = (temp64>>32) & 0xffffffff;          */
+		/* lo = temp64 & 0xffffffff;                */
+		/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
 
-	hi = (pattern[i]>>32) & 0xffffffff;
-	lo = pattern[i] & 0xffffffff;
-	/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo);  */
+		hi = (pattern[i] >> 32) & 0xffffffff;
+		lo = pattern[i] & 0xffffffff;
+		/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo);  */
 
-	if (temp64 != pattern[i]){
-	    printf ("\n   Data Test Failed, pattern 0x%08x%08x", hi, lo);
-	    return 1;
+		if (temp64 != pattern[i]) {
+			printf ("\n   Data Test Failed, pattern 0x%08x%08x",
+				hi, lo);
+			return 1;
+		}
 	}
-    }
 
-    return 0;
+	return 0;
 }
 #endif /* CFG_DRAM_TEST_DATA */
 
@@ -368,25 +370,26 @@ int mem_test_data(void)
 /*								     */
 /*								     */
 /*********************************************************************/
-int mem_test_address(void)
+int mem_test_address (void)
 {
-    volatile unsigned int * pmem = (volatile unsigned int *)CFG_SDRAM_BASE ;
-    const unsigned int size = (CFG_SDRAM_SIZE * 1024 * 1024)/4;
-    unsigned int i;
+	volatile unsigned int *pmem =
+		(volatile unsigned int *) CFG_SDRAM_BASE;
+	const unsigned int size = (CFG_SDRAM_SIZE * 1024 * 1024) / 4;
+	unsigned int i;
 
-    /* write address to each location */
-    for ( i = 0; i < size; i++) {
-	pmem[i] = i;
-    }
-
-    /* verify each loaction */
-    for ( i = 0; i < size; i++) {
-	if (pmem[i] != i) {
-	    printf("\n   Address Test Failed at 0x%x", i);
-	    return 1;
+	/* write address to each location */
+	for (i = 0; i < size; i++) {
+		pmem[i] = i;
 	}
-    }
-    return 0;
+
+	/* verify each loaction */
+	for (i = 0; i < size; i++) {
+		if (pmem[i] != i) {
+			printf ("\n   Address Test Failed at 0x%x", i);
+			return 1;
+		}
+	}
+	return 0;
 }
 #endif /* CFG_DRAM_TEST_ADDRESS */
 
@@ -418,39 +421,35 @@ int mem_test_address(void)
 /*								     */
 /*								     */
 /*********************************************************************/
-int mem_march(volatile unsigned long long * base,
-	      unsigned int size,
-	      unsigned long long rmask,
-	      unsigned long long wmask,
-	      short read,
-	      short write)
+int mem_march (volatile unsigned long long *base,
+	       unsigned int size,
+	       unsigned long long rmask,
+	       unsigned long long wmask, short read, short write)
 {
-    unsigned int i;
-    unsigned long long temp;
-    unsigned int hitemp, lotemp, himask, lomask;
+	unsigned int i;
+	unsigned long long temp;
+	unsigned int hitemp, lotemp, himask, lomask;
 
-    for (i = 0 ; i < size ; i++) {
-	if (read != 0) {
-	    /* temp = base[i]; */
-	    move64 ((unsigned long long *)&(base[i]), &temp);
-	    if (rmask != temp) {
-		hitemp = (temp>>32) & 0xffffffff;
-		lotemp = temp & 0xffffffff;
-		himask = (rmask>>32) & 0xffffffff;
-		lomask = rmask & 0xffffffff;
+	for (i = 0; i < size; i++) {
+		if (read != 0) {
+			/* temp = base[i]; */
+			move64 ((unsigned long long *) &(base[i]), &temp);
+			if (rmask != temp) {
+				hitemp = (temp >> 32) & 0xffffffff;
+				lotemp = temp & 0xffffffff;
+				himask = (rmask >> 32) & 0xffffffff;
+				lomask = rmask & 0xffffffff;
 
-		printf("\n Walking one's test failed: address = 0x%08x,"
-		       "\n\texpected 0x%08x%08x, found 0x%08x%08x",
-		       i<<3, himask, lomask, hitemp, lotemp);
-		return 1;
-	    }
+				printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
+				return 1;
+			}
+		}
+		if (write != 0) {
+			/*  base[i] = wmask; */
+			move64 (&wmask, (unsigned long long *) &(base[i]));
+		}
 	}
-	if ( write != 0 ) {
-	   /*  base[i] = wmask; */
-	    move64 (&wmask, (unsigned long long *)&(base[i]));
-	}
-    }
-    return 0;
+	return 0;
 }
 #endif /* CFG_DRAM_TEST_WALK */
 
@@ -480,43 +479,44 @@ int mem_march(volatile unsigned long long * base,
 /*								     */
 /*								     */
 /*********************************************************************/
-int mem_test_walk(void)
+int mem_test_walk (void)
 {
-    unsigned long long mask;
-    volatile unsigned long long * pmem =
-	(volatile unsigned long long *)CFG_SDRAM_BASE ;
-    const unsigned long size = (CFG_SDRAM_SIZE * 1024 * 1024)/8;
+	unsigned long long mask;
+	volatile unsigned long long *pmem =
+		(volatile unsigned long long *) CFG_SDRAM_BASE;
+	const unsigned long size = (CFG_SDRAM_SIZE * 1024 * 1024) / 8;
 
-    unsigned int i;
-    mask = 0x01;
+	unsigned int i;
 
-    printf("Initial Pass");
-    mem_march(pmem,size,0x0,0x1,0,1);
+	mask = 0x01;
 
-    printf("\b\b\b\b\b\b\b\b\b\b\b\b");
-    printf("		");
-    printf("\b\b\b\b\b\b\b\b\b\b\b\b");
+	printf ("Initial Pass");
+	mem_march (pmem, size, 0x0, 0x1, 0, 1);
 
-    for (i = 0 ; i < 63 ; i++) {
-	printf("Pass %2d", i+2);
-	if ( mem_march(pmem,size, mask,mask << 1, 1, 1) != 0 ){
-	    /*printf("mask: 0x%x, pass: %d, ", mask, i);*/
-	    return 1;
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+	printf ("		");
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+
+	for (i = 0; i < 63; i++) {
+		printf ("Pass %2d", i + 2);
+		if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
+			/*printf("mask: 0x%x, pass: %d, ", mask, i); */
+			return 1;
+		}
+		mask = mask << 1;
+		printf ("\b\b\b\b\b\b\b");
 	}
-	mask = mask<<1;
-	printf("\b\b\b\b\b\b\b");
-    }
 
-    printf("Last Pass");
-    if (mem_march(pmem, size, 0, mask, 0, 1) != 0) {
-	/* printf("mask: 0x%x", mask); */
-	return 1;
-    }
-    printf("\b\b\b\b\b\b\b\b\b");
-    printf("	     ");
-    printf("\b\b\b\b\b\b\b\b\b");
+	printf ("Last Pass");
+	if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
+		/* printf("mask: 0x%x", mask); */
+		return 1;
+	}
+	printf ("\b\b\b\b\b\b\b\b\b");
+	printf ("	     ");
+	printf ("\b\b\b\b\b\b\b\b\b");
 
-    return 0;
+	return 0;
 }
 
 /*********************************************************************/
@@ -542,46 +542,46 @@ int mem_test_walk(void)
 /*								     */
 /*								     */
 /*********************************************************************/
-int testdram(void)
+int testdram (void)
 {
-    char *s;
-    int rundata, runaddress, runwalk;
+	char *s;
+	int rundata, runaddress, runwalk;
 
-    s = getenv ("testdramdata");
-    rundata = (s && (*s == 'y')) ? 1 : 0;
-    s = getenv ("testdramaddress");
-    runaddress = (s && (*s == 'y')) ? 1 : 0;
-    s = getenv ("testdramwalk");
-    runwalk = (s && (*s == 'y')) ? 1 : 0;
+	s = getenv ("testdramdata");
+	rundata = (s && (*s == 'y')) ? 1 : 0;
+	s = getenv ("testdramaddress");
+	runaddress = (s && (*s == 'y')) ? 1 : 0;
+	s = getenv ("testdramwalk");
+	runwalk = (s && (*s == 'y')) ? 1 : 0;
 
-    if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
-	printf("Testing RAM ... ");
-    }
-#ifdef CFG_DRAM_TEST_DATA
-    if (rundata == 1) {
-	if (mem_test_data() == 1){
-	    return 1;
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
+		printf ("Testing RAM ... ");
+	}
+#ifdef CFG_DRAM_TEST_DATA
+	if (rundata == 1) {
+		if (mem_test_data () == 1) {
+			return 1;
+		}
 	}
-    }
 #endif
 #ifdef CFG_DRAM_TEST_ADDRESS
-    if (runaddress == 1) {
-	if (mem_test_address() == 1){
-	    return 1;
+	if (runaddress == 1) {
+		if (mem_test_address () == 1) {
+			return 1;
+		}
 	}
-    }
 #endif
 #ifdef CFG_DRAM_TEST_WALK
-    if (runwalk == 1) {
-	if (mem_test_walk() == 1){
-	    return 1;
+	if (runwalk == 1) {
+		if (mem_test_walk () == 1) {
+			return 1;
+		}
 	}
-    }
 #endif
-    if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
-	printf("passed");
-    }
-    return 0;
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
+		printf ("passed");
+	}
+	return 0;
 
 }
 #endif /* CFG_DRAM_TEST */
@@ -606,52 +606,52 @@ int testdram(void)
 /*								     */
 /*								     */
 /*********************************************************************/
-long int initdram(int board_type)
+long int initdram (int board_type)
 {
-    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
-    volatile memctl8260_t *memctl = &immap->im_memctl;
-    volatile uchar c = 0, *ramaddr = (uchar *)(CFG_SDRAM_BASE + 0x8);
-    ulong psdmr = CFG_PSDMR;
-    int i;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	volatile uchar c = 0, *ramaddr = (uchar *) (CFG_SDRAM_BASE + 0x8);
+	ulong psdmr = CFG_PSDMR;
+	int i;
 
-    /*
-     * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
-     *
-     * "At system reset, initialization software must set up the
-     *	programmable parameters in the memory controller banks registers
-     *	(ORx, BRx, P/LSDMR). After all memory parameters are configured,
-     *	system software should execute the following initialization sequence
-     *	for each SDRAM device.
-     *
-     *	1. Issue a PRECHARGE-ALL-BANKS command
-     *	2. Issue eight CBR REFRESH commands
-     *	3. Issue a MODE-SET command to initialize the mode register
-     *
-     *	The initial commands are executed by setting P/LSDMR[OP] and
-     *	accessing the SDRAM with a single-byte transaction."
-     *
-     * The appropriate BRx/ORx registers have already been set when we
-     * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
-     */
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 */
 
-    memctl->memc_psrt = CFG_PSRT;
-    memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_mptpr = CFG_MPTPR;
 
-    memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
-    *ramaddr = c;
-
-    memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
-    for (i = 0; i < 8; i++){
+	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
 	*ramaddr = c;
-    }
-    memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
-    *ramaddr = c;
 
-    memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
-    *ramaddr = c;
+	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++) {
+		*ramaddr = c;
+	}
+	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
+	*ramaddr = c;
 
-    /* return total ram size */
-    return (CFG_SDRAM0_SIZE * 1024 * 1024);
+	memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*ramaddr = c;
+
+	/* return total ram size */
+	return (CFG_SDRAM0_SIZE * 1024 * 1024);
 }
 
 /*********************************************************************/

board/icecube/icecube.c

@@ -2,6 +2,9 @@
  * (C) Copyright 2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -25,90 +28,84 @@
 #include <mpc5xxx.h>
 #include <pci.h>
 
+#if defined(CONFIG_MPC5200_DDR)
+#include "mt46v16m16-75.h"
+#else
+#include "mt48lc16m16a2-75.h"
+#endif
+
 #ifndef CFG_RAMBOOT
 static void sdram_start (int hi_addr)
 {
 	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
 
-#ifdef CONFIG_MPC5200_DDR
 	/* unlock mode register */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f00 | hi_addr_bit;
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
 	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f02 | hi_addr_bit;
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
 	/* set mode register: extended mode */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = 0x40090000;
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
 	/* set mode register: reset DLL */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = 0x058d0000;
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f02 | hi_addr_bit;
-	/* auto refresh */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f04 | hi_addr_bit;
-	/* set mode register */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = 0x018d0000;
-	/* normal operation */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0x705f0f00 | hi_addr_bit;
-#else
-	/* unlock mode register */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0000 | hi_addr_bit;
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002 | hi_addr_bit;
-	/* set mode register */
-#if defined(CONFIG_MPC5200)
-	*(vu_long *)MPC5XXX_SDRAM_MODE = 0x408d0000;
-#elif defined(CONFIG_MGT5100)
-	*(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
 #endif
+
 	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002 | hi_addr_bit;
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
 	/* auto refresh */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0004 | hi_addr_bit;
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
 	/* set mode register */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
 	/* normal operation */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0x504f0000 | hi_addr_bit;
-#endif
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
 }
 #endif
 
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+#if defined(CONFIG_MPC5200)
 long int initdram (int board_type)
 {
 	ulong dramsize = 0;
-#ifdef CONFIG_MPC5200_DDR
 	ulong dramsize2 = 0;
-#endif
 #ifndef CFG_RAMBOOT
 	ulong test1, test2;
 
-	/* configure SDRAM start/end */
-#if defined(CONFIG_MPC5200)
+	/* setup SDRAM chip selects */
 	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
 	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+	__asm__ volatile ("sync");
 
-#ifdef CONFIG_MPC5200_DDR
 	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0x73722930;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x47770000;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
 
-	/* set tap delay to 0x10 */
-	*(vu_long *)MPC5XXX_CDM_PORCFG = 0x10000000;
-#else
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2233a00;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004;
+#if SDRAM_DDR
+	/* set tap delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
 #endif
 
-#elif defined(CONFIG_MGT5100)
-	*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
-	*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
-	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2222600;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004;
-
-	/* address select register */
-	*(vu_long *)MPC5XXX_SDRAM_XLBSEL = 0x03000000;
-#endif
+	/* find RAM size using SDRAM CS0 only */
 	sdram_start(0);
 	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
 	sdram_start(1);
@@ -119,11 +116,23 @@ long int initdram (int board_type)
 	} else {
 		dramsize = test2;
 	}
-#if defined(CONFIG_MPC5200)
-	*(vu_long *)MPC5XXX_SDRAM_CS0CFG =
-		(0x13 + __builtin_ffs(dramsize >> 20) - 1);
-#ifdef CONFIG_MPC5200_DDR
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	/* let SDRAM CS1 start right after CS0 */
 	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+	/* find RAM size using SDRAM CS1 only */
 	sdram_start(0);
 	test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
 	sdram_start(1);
@@ -134,34 +143,94 @@ long int initdram (int board_type)
 	} else {
 		dramsize2 = test2;
 	}
-	*(vu_long *)MPC5XXX_SDRAM_CS1CFG =
-		dramsize + (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
-#else
-	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-#endif
-#elif defined(CONFIG_MGT5100)
-	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
-#endif
 
-#else	/* CFG_RAMBOOT */
-#ifdef CONFIG_MGT5100
-	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
-	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
-#else
-	dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20);
-#ifdef CONFIG_MPC5200_DDR
-	dramsize2 = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS1CFG - 0x13)) << 20);
-#endif
-#endif
+	/* memory smaller than 1MB is impossible */
+	if (dramsize2 < (1 << 20)) {
+		dramsize2 = 0;
+	}
+
+	/* set SDRAM CS1 size according to the amount of RAM found */
+	if (dramsize2 > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+	}
+
+#else /* CFG_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CFG_RAMBOOT */
+
+	return dramsize + dramsize2;
+}
+
+#elif defined(CONFIG_MGT5100)
+
+long int initdram (int board_type)
+{
+	ulong dramsize = 0;
+#ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
+	/* setup and enable SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
+	*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+
+	/* address select register */
+	*(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
+	__asm__ volatile ("sync");
+
+	/* find RAM size */
+	sdram_start(0);
+	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* set SDRAM end address according to size */
+	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
+
+#else /* CFG_RAMBOOT */
+
+	/* Retrieve amount of SDRAM available */
+	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
+
 #endif /* CFG_RAMBOOT */
 
-#ifdef CONFIG_MPC5200_DDR
-	dramsize += dramsize2;
-#endif
-	/* return total ram size */
 	return dramsize;
 }
 
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif
+
 int checkboard (void)
 {
 #if defined(CONFIG_MPC5200)
@@ -207,3 +276,28 @@ void pci_init_board(void)
 	pci_mpc5xxx_init(&hose);
 }
 #endif
+
+#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+
+#define GPIO_PSC1_4	0x01000000UL
+
+void init_ide_reset (void)
+{
+	debug ("init_ide_reset\n");
+
+    	/* Configure PSC1_4 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
+}
+
+void ide_set_reset (int idereset)
+{
+	debug ("ide_reset(%d)\n", idereset);
+
+	if (idereset) {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
+	} else {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA |=  GPIO_PSC1_4;
+	}
+}
+#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */

board/icecube/mt46v16m16-75.h

@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1		/* is DDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x705f0f00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+#define SDRAM_TAPDELAY	0x10000000
+
+#else
+#error CONFIG_MPC5200 not defined
+#endif

board/icecube/mt48lc16m16a2-75.h

@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	0		/* is SDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+#define SDRAM_CONFIG2	0x8AD70000
+
+#elif defined(CONFIG_MGT5100)
+/* Settings for XLB = 66 MHz */
+#define SDRAM_MODE	0x008D0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xC2222600
+#define SDRAM_CONFIG2	0x88B70004
+#define SDRAM_ADDRSEL	0x02000000
+
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif

board/incaip/memsetup.S

@@ -185,8 +185,10 @@ sdram_init:
 
 	li	t1, MC_MODUL_BASE
 
+#if 0
 	/* Disable memory controller before changing any of its registers */
 	sw	zero, MC_CTRLENA(t1)
+#endif
 
 	li	t2, 100000000
 	beq	a0, t2, 1f

board/integratorap/Makefile

@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004
+# ARM Ltd.
+# Philippe Robin, <philippe.robin@arm.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= integratorap.o flash.o
+SOBJS	:= platform.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################