* Fix "cls" command when used with splash screen

* Increase NFS download timeout (now 1 min - 10 sec is to short for a
  slow download of a big image)

CHANGELOG

@@ -2,6 +2,14 @@
 Changes since U-Boot 1.1.1:
 ======================================================================
 
+* Fix "cls" command when used with splash screen
+
+* Increase NFS download timeout (now 1 min - 10 sec is to short for a
+  slow download of a big image)
+
+* Add "cls" function to MPC823 LCD driver so we can reinitialize the
+  display even after showing a bitmap
+
 * Patch by Josef Wagner, 04 Jun 2004:
   - DDR Ram support for PM520 (MPC5200)
   - support for different flash types (PM520)

README

@@ -895,7 +895,7 @@ The following options need to be configured:
 		If this option is set, the environment is checked for
 		a variable "splashimage". If found, the usual display
 		of logo, copyright and system information on the LCD
-		is supressed and the BMP image at the address
+		is suppressed and the BMP image at the address
 		specified in "splashimage" is loaded instead. The
 		console is redirected to the "nulldev", too. This
 		allows for a "silent" boot where a splash screen is

cpu/mpc8xx/lcd.c

@@ -29,6 +29,7 @@
 
 #include <config.h>
 #include <common.h>
+#include <command.h>
 #include <watchdog.h>
 #include <version.h>
 #include <stdarg.h>
@@ -434,8 +435,9 @@ static void	lcd_drawchars  (ushort x, ushort y, uchar *str, int count);
 static inline void lcd_puts_xy (ushort x, ushort y, uchar *s);
 static inline void lcd_putc_xy (ushort x, ushort y, uchar  c);
 
-int	lcd_init (void *lcdbase);
+static int	lcd_init (void *lcdbase);
 
+static int	lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]);
 static void	lcd_ctrl_init (void *lcdbase);
 static void	lcd_enable (void);
 static void    *lcd_logo (void);
@@ -718,13 +720,8 @@ int drv_lcd_init (void)
 
 /*----------------------------------------------------------------------*/
 
-int lcd_init (void *lcdbase)
+static int lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
-	/* Initialize the lcd controller */
-	debug ("[LCD] Initializing LCD frambuffer at %p\n", lcdbase);
-
-	lcd_ctrl_init (lcdbase);
-
 #if LCD_BPP == LCD_MONOCHROME
 	/* Setting the palette */
 	lcd_initcolregs();
@@ -758,13 +755,33 @@ int lcd_init (void *lcdbase)
 		COLOR_MASK(lcd_getbgcolor()),
 		lcd_line_length*panel_info.vl_row);
 #endif
-
-	lcd_enable ();
-
 	/* Paint the logo and retrieve LCD base address */
 	debug ("[LCD] Drawing the logo...\n");
 	lcd_console_address = lcd_logo ();
 
+	console_col = 0;
+	console_row = 0;
+
+	return (0);
+}
+
+U_BOOT_CMD(
+	cls,	1,	1,	lcd_clear,
+	"cls     - clear screen\n",
+	NULL
+);
+
+/*----------------------------------------------------------------------*/
+
+static int lcd_init (void *lcdbase)
+{
+	/* Initialize the lcd controller */
+	debug ("[LCD] Initializing LCD frambuffer at %p\n", lcdbase);
+
+	lcd_ctrl_init (lcdbase);
+	lcd_clear (NULL, 1, 1, NULL);	/* dummy args */
+	lcd_enable ();
+
 	/* Initialize the console */
 	console_col = 0;
 #ifdef LCD_INFO_BELOW_LOGO
@@ -1316,9 +1333,11 @@ static void *lcd_logo (void)
 #ifdef CONFIG_SPLASH_SCREEN
 	char *s;
 	ulong addr;
+	static int do_splash = 1;
 
-	if ((s = getenv("splashimage")) != NULL) {
+	if (do_splash && (s = getenv("splashimage")) != NULL) {
 		addr = simple_strtoul(s, NULL, 16);
+		do_splash = 0;
 
 		if (lcd_display_bitmap (addr, 0, 0) == 0) {
 			return ((void *)lcd_base);

include/configs/HMI10.h

@@ -297,12 +297,7 @@
  *
  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
  */
-#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_PLPRCR							\
-		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-#else			/* up to 66 MHz we use a 1:1 clock */
 #define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-#endif	/* CONFIG_80MHz */
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -311,33 +306,15 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_SCCR	(/* SCCR_TBS  | */ \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
-#else			/* up to 66 MHz we use a 1:1 clock */
-#define CFG_SCCR	(SCCR_TBS     | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-#endif	/* CONFIG_80MHz */
 
 /*-----------------------------------------------------------------------
  * PCMCIA stuff
  *-----------------------------------------------------------------------
  *
  */
-#ifndef CONFIG_HMI10
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
-#else	/* CONFIG_HMI10 */
 #define CFG_PCMCIA_MEM_ADDR	(0xE0100000)
 #define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
 #define CFG_PCMCIA_DMA_ADDR	(0xE4100000)
@@ -348,7 +325,6 @@
 #define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
 #define PCMCIA_MEM_WIN_NO	5
 #define NSCU_OE_INV		1		/* PCMCIA_GCRX_CXOE is inverted */
-#endif
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
@@ -405,19 +381,8 @@
 /*
  * FLASH timing:
  */
-#if   defined(CONFIG_80MHz)
-/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | 0	| OR_CSNT_SAM | \
-				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
-#elif defined(CONFIG_66MHz)
-/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
 #define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
-#else		/*   50 MHz */
-/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
-				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
-#endif	/*CONFIG_??MHz */
 
 #define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 #define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
@@ -478,13 +443,9 @@
  * 66 Mhz => 66.000.000 / Divider = 129
  * 80 Mhz => 80.000.000 / Divider = 156
  */
-#if   defined(CONFIG_80MHz)
-#define CFG_MAMR_PTA		156
-#elif defined(CONFIG_66MHz)
-#define CFG_MAMR_PTA		129
-#else		/*   50 MHz */
-#define CFG_MAMR_PTA		 98
-#endif	/*CONFIG_??MHz */
+
+#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CFG_MAMR_PTA	98
 
 /*
  * For 16 MBit, refresh rates could be 31.3 us

include/lcd.h

@@ -37,7 +37,7 @@ extern char lcd_is_enabled;
 
 /* Video functions */
 
-int	lcd_init	(void *lcdbase);
+/* int	lcd_init	(void *lcdbase); */
 void	lcd_putc	(const char c);
 void	lcd_puts	(const char *s);
 void	lcd_printf	(const char *fmt, ...);

net/nfs.c

@@ -34,7 +34,7 @@
 #if ((CONFIG_COMMANDS & CFG_CMD_NET) && (CONFIG_COMMANDS & CFG_CMD_NFS))
 
 #define HASHES_PER_LINE 65	/* Number of "loading" hashes per line	*/
-#define NFS_TIMEOUT 10
+#define NFS_TIMEOUT 60
 
 static int fs_mounted = 0;
 static unsigned long rpc_id = 0;