Merge patch series "clk: support arbitrary clk_register() sequence"

Yang Xiwen <forbidden405@outlook.com> says: Currently, the U-Boot clk framework mandates that clock registration begins at the root and proceeds to children. This creates an additional requirement that does not exist in the Linux kernel, making the porting of clk drivers more difficult. This series handles the dependency entirely within the clk framework, allowing drivers the freedom to register clocks in any order. This is achieved by assigning the parent "lazily". The framework caches the parent name in the core clk struct and attempts to resolve the actual parent when clk consumers call clk_get_parent(). The process is transparent to clk consumers as long as they use standard clk framework APIs. I've run `ut dm clk*` and verified these commits do not break any existing test cases. It also passes the new test case. This feature is disabled for xPLs by default. I have not found a clean way to enable this separately for xPLs without introducing a repetitive Kconfig entry (e.g., xPL_CLK_LAZY_REPARENT), which looks very ugly. Link: https://lore.kernel.org/r/20260120-clk-reparent-v3-0-0d43d4b362ac@outlook.com
test: clk: add test for CLK_LAZY_REPARENT
2026-06-13 15:03:58 +03:00 · 2026-02-02 13:40:50 -06:00 · 2026-02-02 13:40:41 -06:00 · 2026-02-02 13:40:41 -06:00 · 2026-02-02 13:40:41 -06:00 · 2026-02-02 13:40:41 -06:00
6039 changed files with 72658 additions and 240567 deletions
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -524,9 +524,6 @@ stages:
          TEST_PY_ID: "--id qemu"
          TEST_PY_TEST_SPEC: "not sleep and not efi"
          OVERRIDE: "-a CONFIG_M68K_QEMU=y -a ~CONFIG_MCFTMR"
-        qemu_m68k_virt:
-          TEST_PY_BD: "qemu-m68k"
-          TEST_PY_TEST_SPEC: "not sleep"
        qemu_malta:
          TEST_PY_BD: "malta"
          TEST_PY_ID: "--id qemu"
--- a/.clang-format
+++ b/.clang-format
@@ -748,57 +748,6 @@ ForEachMacros:
  - 'ynl_attr_for_each_nested'
  - 'ynl_attr_for_each_payload'
  - 'zorro_for_each_dev'
-  # U-Boot specific
-  - '__for_each_child_of_node'
-  - '__usbhs_for_each_pipe'
-  - '__usbhsg_for_each_uep'
-  - '_for_each_zynqmp_part'
-  - 'alist_for_each'
-  - 'alist_for_each_filter'
-  - 'cvmx_coremask_for_each_core'
-  - 'cvmx_coremask_for_each_node'
-  - 'dev_for_each_property'
-  - 'dev_for_each_subnode'
-  - 'expr_list_for_each_sym'
-  - 'fdt_for_each_node_by_compatible'
-  - 'fdt_for_each_property_offset'
-  - 'fdt_for_each_subnode'
-  - 'for_each_bin_hdr_v0'
-  - 'for_each_bl_params_node'
-  - 'for_each_child_withdel'
-  - 'for_each_console_dev'
-  - 'for_each_ext_hdr_v0'
-  - 'for_each_label'
-  - 'for_each_label_withdel'
-  - 'for_each_marker'
-  - 'for_each_marker_of_type'
-  - 'for_each_memory_map_entry_reversed'
-  - 'for_each_mmc_mode_by_pref'
-  - 'for_each_opt_hdr_v1'
-  - 'for_each_property_withdel'
-  - 'for_each_sd_mode_by_pref'
-  - 'for_each_supported_width'
-  - 'for_each_tpm_device'
-  - 'for_each_w1_device'
-  - 'for_each_zynqmp_image'
-  - 'for_each_zynqmp_part'
-  - 'for_each_zynqmp_part_in_image'
-  - 'mtd_for_each_device'
-  - 'ofnode_for_each_compatible_node'
-  - 'ofnode_for_each_prop'
-  - 'ofnode_for_each_subnode'
-  - 'pko_for_each_port'
-  - 'sfi_for_each_mentry'
-  - 'ubi_for_each_free_peb'
-  - 'ubi_for_each_protected_peb'
-  - 'ubi_for_each_scrub_peb'
-  - 'ubi_for_each_used_peb'
-  - 'ubi_rb_for_each_entry'
-  - 'usbhs_for_each_dfifo'
-  - 'usbhs_for_each_pipe'
-  - 'usbhs_for_each_pipe_with_dcp'
-  - 'usbhsg_for_each_uep'
-  - 'usbhsg_for_each_uep_with_dcp'

 IncludeBlocks: Preserve
 IncludeCategories:
--- a/.gitignore
+++ b/.gitignore
@@ -80,7 +80,7 @@ fit-dtb.blob*
 /*imx8mimage*
 /*imx8mcst*
 /*rcar4-sa0*
-/drivers/video/u_boot_logo.bmp.S
+/drivers/video/u_boot_logo.S
 /test/fdt_overlay/test-fdt-overlay-stacked.dtbo.S
 /test/fdt_overlay/test-fdt-overlay.dtbo.S
 capsule_esl_file
--- a/.gitlab-ci-sage-lab.yml
+++ b/.gitlab-ci-sage-lab.yml
@@ -26,7 +26,7 @@
      . /tmp/venv/bin/activate;
      pip install -r test/py/requirements.txt -r tools/binman/requirements.txt
        -r tools/buildman/requirements.txt -r tools/u_boot_pylib/requirements.txt
-        labgrid==25.0.1 setuptools
+        labgrid setuptools
    # Acquire and turn on the exporter.
    - labgrid-client reserve --wait board=${LABGRID_EXPORTER} &&
      labgrid-client -p ${LABGRID_EXPORTER} acquire &&
@@ -153,13 +153,20 @@ Raspberry Pi 4 (rpi_arm64):
    LABGRID_EXPORTER: "sage-exporter-rpi4-1"
    LG_PLACE: "rpi4-1"
    TEST_PY_BD: "rpi_arm64"
-    # DHCP is not being run first, needs to be investigated.
-    TEST_PY_TEST_SPEC: "not test_efi_helloworld_net_http"
-    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
+    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a CMD_TFTPPUT -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
+
+Raspberry Pi 4 (rpi_arm64, lwIP):
+  <<: *sage_lab_dfn
+  needs: [ "Raspberry Pi 4 (rpi_arm64)" ]
+  variables:
+    LABGRID_EXPORTER: "sage-exporter-rpi4-1"
+    LG_PLACE: "rpi4-1"
+    TEST_PY_BD: "rpi_arm64"
+    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000 -a NET_LWIP"

 Raspberry Pi 4 (rpi_4_32b):
  <<: *sage_lab_dfn
-  needs: [ "Raspberry Pi 4 (rpi_arm64)" ]
+  needs: [ "Raspberry Pi 4 (rpi_arm64, lwIP)" ]
  variables:
    LABGRID_EXPORTER: "sage-exporter-rpi4-1"
    LG_PLACE: "rpi4-1"
@@ -190,13 +197,20 @@ Raspberry Pi 3 (rpi_arm64):
    LABGRID_EXPORTER: "sage-exporter-rpi3-1"
    LG_PLACE: "rpi3-1"
    TEST_PY_BD: "rpi_arm64"
-    # DHCP is not being run first, needs to be investigated.
-    TEST_PY_TEST_SPEC: "not test_efi_helloworld_net_http"
-    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
+    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a CMD_TFTPPUT -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
+
+Raspberry Pi 3 (rpi_arm64, lwIP):
+  <<: *sage_lab_dfn
+  needs: [ "Raspberry Pi 3 (rpi_arm64)" ]
+  variables:
+    LABGRID_EXPORTER: "sage-exporter-rpi3-1"
+    LG_PLACE: "rpi3-1"
+    TEST_PY_BD: "rpi_arm64"
+    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000 -a NET_LWIP"

 Raspberry Pi 3 (rpi_3_32b):
  <<: *sage_lab_dfn
-  needs: [ "Raspberry Pi 3 (rpi_arm64)" ]
+  needs: [ "Raspberry Pi 3 (rpi_arm64, lwIP)" ]
  variables:
    LABGRID_EXPORTER: "sage-exporter-rpi3-1"
    LG_PLACE: "rpi3-1"
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -421,12 +421,6 @@ qemu_m68k test.py:
    OVERRIDE: "-a CONFIG_M68K_QEMU=y -a ~CONFIG_MCFTMR"
  <<: *buildman_and_testpy_dfn

-qemu_m68k_virt test.py:
-  variables:
-    TEST_PY_BD: "qemu-m68k"
-    TEST_PY_TEST_SPEC: "not sleep"
-  <<: *buildman_and_testpy_dfn
-
 qemu_malta test.py:
  variables:
    TEST_PY_BD: "malta"
@@ -795,5 +789,5 @@ vf2:
 qemu-x86_64:
  variables:
    ROLE: qemu-x86_64
-    TEST_PY_TEST_SPEC: "not sleep"
+    TEST_PY_TEST_SPEC: "and not sleep"
  <<: *sjg_lab_dfn
--- a/.mailmap
+++ b/.mailmap
@@ -43,9 +43,8 @@ Christopher Obbard <christopher.obbard@linaro.org> <chris.obbard@collabora.com>
 Dirk Behme <dirk.behme@googlemail.com>
 <duje@dujemihanovic.xyz> <duje.mihanovic@skole.hr>
 Durga Challa <durga.challa@amd.com> <vnsl.durga.challa@xilinx.com>
-Eugen Hristev <ehristev@kernel.org> <eugen.hristev@microchip.com>
-Eugen Hristev <ehristev@kernel.org> <eugen.hristev@linaro.org>
-Eugen Hristev <ehristev@kernel.org> <eugen.hristev@collabora.com>
+Eugen Hristev <eugen.hristev@linaro.org> <eugen.hristev@microchip.com>
+Eugen Hristev <eugen.hristev@linaro.org> <eugen.hristev@collabora.com>
 Fabio Estevam <fabio.estevam@nxp.com>
 Greg Malysa <malysagreg@gmail.com> <greg.malysa@timesys.com>
 Harini Katakam <harini.katakam@amd.com> <harini.katakam@xilinx.com>
@@ -68,11 +67,9 @@ Jagan Teki <jaganna@xilinx.com>
 Jagan Teki <jagannadh.teki@gmail.com>
 Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com>
 Jakob Unterwurzacher <jakob.unterwurzacher@cherry.de> <jakob.unterwurzacher@theobroma-systems.com>
-Javier Tia <floss@jetm.me> <javier.tia@linaro.org>
 Jay Buddhabhatti <jay.buddhabhatti@amd.com> <jay.buddhabhatti@xilinx.com>
 Jernej Skrabec <jernej.skrabec@gmail.com> <jernej.skrabec@siol.net>
-Jerome Forissier <jerome.forissier@arm.com> <jerome@forissier.org>
-Jerome Forissier <jerome.forissier@arm.com> <jerome.forissier@linaro.org>
+Jerome Forissier <jerome@forissier.org> <jerome.forissier@linaro.org>
 John Linn <john.linn@amd.com> <john.linn@xilinx.com>
 Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyothee@xilinx.com>
 Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyotheeswar.reddy.mutthareddyvari@xilinx.com>
@@ -133,11 +130,9 @@ Sam Protsenko <semen.protsenko@linaro.org> <joe.skb7@gmail.com>
 Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com> <sandeep.gundlupet-raju@xilinx.com>
 Sandeep Paulraj <s-paulraj@ti.com>
 Sandeep Reddy Ghanapuram <sandeep.reddy-ghanapuram@amd.com> <sandeep.reddy-ghanapuram@xilinx.com>
-Sean Anderson <sean.anderson@linux.dev> <sean.anderson@seco.com>
 Shaohui Xie <Shaohui.Xie@freescale.com>
 Shravya Kumbham <shravya.kumbham@amd.com> <shravya.kumbham@xilinx.com>
 Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> <shubhrajyoti.datta@xilinx.com>
-Simon Glass <sjg@chromium.org> <simon.glass@canonical.com>
 Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> <siva.durga.paladugu@xilinx.com>
 Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> <sivadur@xilinx.com>
 Srinivas Goud <srinivas.goud@amd.com> <srinivas.goud@xilinx.com>
@@ -145,7 +140,6 @@ Srinivas Neeli <srinivas.neeli@amd.com> <srinivas.neeli@xilinx.com>
 Stefan Roese <stefan.roese@mailbox.org> <stroese>
 Stefano Babic <sbabic@nabladev.com>
 Stefano Stabellini <stefano.stabellini@amd.com> <stefano.stabellini@xilinx.com>
-Sughosh Ganu <sughosh.ganu@arm.com> <sughosh.ganu@linaro.org>
 No generic patch CC mail please <noreply@example.com> <swarren@wwwdotorg.org>
 No generic patch CC mail please <noreply@example.com> <swarren@nvidia.com>
 Sumit Garg <sumit.garg@kernel.org> <sumit.garg@linaro.org>
--- a/77
+++ b/77
@@ -468,41 +468,12 @@ config TOOLS_DEBUG
 	  it is possible to set breakpoints on particular lines, single-step
 	  debug through the source code, etc.

-config SKIP_EARLY_DM
-	bool "Skips initialising device model pre-relocation"
-	help
-	  Enable this option to skip scanning and probing devices prior to
-	  U-Boot relocation (during board_f). Unless console support is disabled
-	  a serial port is still required, however this can be found through
-	  /chosen/stdout-path in FDT. If the serial port relies on other devices
-	  like clocks these will also be bound and probed on demand.
-
-	  This can speed up time to interactive console by about 50%, particularly
-	  when combined with OF_LIVE.
-
 config SKIP_RELOCATE
 	bool "Skips relocation of U-Boot to end of RAM"
 	help
 	  Skips relocation of U-Boot allowing for systems that have extremely
 	  limited RAM to run U-Boot.

-config SKIP_RELOCATE_CODE
-	bool
-	help
-	  Skips relocation of U-Boot code to the end of RAM, but still does
-	  relocate data to the end of RAM. This is mainly meant to relocate
-	  data to read-write portion of the RAM, while the code remains in
-	  read-only portion of the RAM from which it is allowed to execute.
-	  This split configuration is present on various secure cores.
-
-config SKIP_RELOCATE_CODE_DATA_OFFSET
-	hex
-	default 0x0
-	depends on SKIP_RELOCATE_CODE
-	help
-	  Offset of the read-write memory which contains data, from read-only
-	  memory which contains executable text.
-
 endif # EXPERT

 config PHYS_64BIT
@@ -551,10 +522,10 @@ config BUILD_TARGET
 	default "u-boot-elf.srec" if RCAR_64
 	default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
 	default "u-boot-with-spl.bin" if MPC85xx && !E500MC && !E5500 && !E6500 && SPL
-	default "u-boot-with-spl.imx" if (ARCH_MX6 || ARCH_MX7) && SPL
+	default "u-boot-with-spl.imx" if ARCH_MX6 && SPL
 	default "u-boot-with-spl.kwb" if ARMADA_32BIT && SPL
-	default "u-boot-with-spl.sfp" if ARCH_SOCFPGA_ARRIA10
-	default "u-boot-with-spl.sfp" if ARCH_SOCFPGA_GEN5
+	default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_ARRIA10
+	default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_GEN5
 	default "u-boot.itb" if !BINMAN && SPL_LOAD_FIT && (ARCH_ROCKCHIP || \
 				RISCV || ARCH_ZYNQMP)
 	default "u-boot.kwb" if (ARCH_KIRKWOOD || ARMADA_32BIT) && !SPL
@@ -644,11 +615,9 @@ config STACK_SIZE
 	default 0x4000 if ARCH_STM32
 	default 0x1000000
 	help
-	  Define Max stack size that can be used by U-Boot. The UEFI sub-system
-	  considers this value when setting up the memory map. The UEFI
-	  specification requires 128 KiB or more of available stack space. On
-	  some boards initrd_high is calculated as base stack pointer minus this
-	  stack size.
+	  Define Max stack size that can be used by U-Boot. This value is used
+	  by the UEFI sub-system. On some boards initrd_high is calculated as
+	  base stack pointer minus this stack size.

 config SYS_MEM_TOP_HIDE
 	hex "Exclude some memory from U-Boot / OS information"
@@ -803,8 +772,42 @@ source "dts/Kconfig"

 source "env/Kconfig"

+menu "Networking"
+
+choice
+	prompt "Networking stack"
+	default NET
+
+config NO_NET
+	bool "No networking support"
+	help
+	  Do not include networking support
+
+config NET
+	bool "Legacy U-Boot networking stack"
+	imply NETDEVICES
+	help
+	  Include networking support with U-Boot's internal implementation of
+	  the TCP/IP protocol stack.
+
+config NET_LWIP
+	bool "Use lwIP for networking stack"
+	imply NETDEVICES
+	help
+	  Include networking support based on the lwIP (lightweight IP)
+	  TCP/IP stack (https://nongnu.org/lwip). This is a replacement for
+	  the default U-Boot network stack and applications located in net/
+	  and enabled via CONFIG_NET as well as other pieces of code that
+	  depend on CONFIG_NET (such as cmd/net.c enabled via CONFIG_CMD_NET).
+	  Therefore the two symbols CONFIG_NET and CONFIG_NET_LWIP are mutually
+	  exclusive.
+
+endchoice
+
 source "net/Kconfig"

+endmenu
+
 source "drivers/Kconfig"

 source "fs/Kconfig"
--- a/154
+++ b/154
@@ -65,11 +65,6 @@ F:	include/alist.h
 F:	lib/alist.c
 F:	test/lib/alist.c

-AMD VERSAL2 PCIE DRIVER
-M:	Pranav Sanwal <pranav.sanwal@amd.com>
-S:	Maintained
-F:	drivers/pci/pcie_dw_amd.c
-
 ANDROID AB
 M:	Mattijs Korpershoek <mkorpershoek@kernel.org>
 R:	Igor Opaniuk <igor.opaniuk@gmail.com>
@@ -133,22 +128,15 @@ F:	drivers/mmc/snps_dw_mmc.c

 APPLE M1 SOC SUPPORT
 M:	Mark Kettenis <kettenis@openbsd.org>
-R:	Janne Grunau <j@jannau.net>
 S:	Maintained
 F:	arch/arm/include/asm/arch-apple/
 F:	arch/arm/mach-apple/
-F:	board/apple/
 F:	configs/apple_m1_defconfig
-F:	doc/board/apple/
-F:	drivers/input/apple_spi_kbd.c
 F:	drivers/iommu/apple_dart.c
-F:	drivers/mailbox/apple-mbox.c
 F:	drivers/nvme/nvme_apple.c
 F:	drivers/pci/pcie_apple.c
 F:	drivers/phy/phy-apple-atc.c
 F:	drivers/pinctrl/pinctrl-apple.c
-F:	drivers/power/domain/apple-pmgr.c
-F:	drivers/spi/apple_spi.c
 F:	drivers/watchdog/apple_wdt.c
 F:	include/configs/apple.h

@@ -335,7 +323,6 @@ F:	doc/imx/
 F:	drivers/mailbox/imx-mailbox.c
 F:	drivers/remoteproc/imx*
 F:	drivers/serial/serial_mxc.c
-F:	drivers/spi/nxp_xspi.c
 F:	include/imx_container.h

 ARM HISILICON
@@ -373,7 +360,7 @@ F:	drivers/rng/msm_rng.c
 F:	drivers/pinctrl/qcom/pinctrl-ipq4019.c

 ARM LAYERSCAPE SFP
-M:	Sean Anderson <sean.anderson@linux.dev>
+M:	Sean Anderson <sean.anderson@seco.com>
 S:	Maintained
 F:	drivers/misc/ls2_sfp.c

@@ -427,10 +414,7 @@ M:	Ryder Lee <ryder.lee@mediatek.com>
 M:	Weijie Gao <weijie.gao@mediatek.com>
 M:	Chunfeng Yun <chunfeng.yun@mediatek.com>
 M:	Igor Belwon <igor.belwon@mentallysanemainliners.org>
-M:	David Lechner <dlechner@baylibre.com>
-M:	Julien Stephan <jstephan@baylibre.com>
 R:	GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>
-T:	git https://source.denx.de/u-boot/custodians/u-boot-mediatek.git
 S:	Maintained
 F:	arch/arm/dts/mt*
 F:	arch/arm/mach-mediatek/
@@ -448,8 +432,6 @@ F:	drivers/net/phy/mediatek/
 F:	drivers/phy/phy-mtk-*
 F:	drivers/pinctrl/mediatek/
 F:	drivers/power/domain/mtk-power-domain.c
-F:	drivers/power/pmic/mtk-pwrap.c
-F:	drivers/power/regulator/mt*.c
 F:	drivers/pci/pcie_mediatek_gen3.c
 F:	drivers/pci/pcie_mediatek.c
 F:	drivers/pwm/pwm-mtk.c
@@ -466,7 +448,6 @@ F:	drivers/reset/reset-mediatek.c
 F:	drivers/serial/serial_mtk.c
 F:	include/dt-bindings/clock/mediatek,*
 F:	include/dt-bindings/power/mediatek,*
-F:	include/power/mt*.h
 F:	tools/mtk_image.c
 F:	tools/mtk_image.h
 F:	tools/mtk_nand_headers.c
@@ -482,7 +463,7 @@ F:	configs/eDPU_defconfig
 F:	configs/uDPU_defconfig

 ARM MICROCHIP/ATMEL AT91
-M:	Eugen Hristev <ehristev@kernel.org>
+M:	Eugen Hristev <eugen.hristev@microchip.com>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-at91.git
 F:	arch/arm/dts/at91*
@@ -645,14 +626,17 @@ S:	Supported
 F:	arch/arm/dts/am335x-sancloud*

 ARM SC5XX
+M:	Nathan Barrett-Morrison <nathan.morrison@timesys.com>
 M:	Greg Malysa <malysagreg@gmail.com>
+M:	Ian Roberts <ian.roberts@timesys.com>
 M:	Vasileios Bimpikas <vasileios.bimpikas@analog.com>
+M:	Utsav Agarwal <utsav.agarwal@analog.com>
 M:	Arturs Artamonovs <arturs.artamonovs@analog.com>
-L:	linux@analog.com
+L:	adsp-linux@analog.com
 S:	Supported
-T:	git https://github.com/analogdevicesinc/u-boot
+T:	git https://github.com/analogdevicesinc/lnxdsp-u-boot
 F:	arch/arm/dts/sc5*
-F:	arch/arm/include/asm/arch-sc5xx/
+F:	arch/arm/include/asm/arch-adi/
 F:	arch/arm/mach-sc5xx/
 F:	board/adi/
 F:	configs/sc5*
@@ -692,7 +676,6 @@ F:	drivers/*/*/pm8???-*
 F:	drivers/gpio/msm_gpio.c
 F:	drivers/mmc/msm_sdhci.c
 F:	drivers/phy/msm8916-usbh-phy.c
-F:	drivers/phy/qcom/
 F:	drivers/serial/serial_msm.c
 F:	drivers/serial/serial_msm_geni.c
 F:	drivers/smem/msm_smem.c
@@ -768,6 +751,7 @@ N:	stm
 N:	stm32

 ARM SUNXI
+M:	Jagan Teki <jagan@amarulasolutions.com>
 M:	Andre Przywara <andre.przywara@arm.com>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-sunxi.git
@@ -1064,6 +1048,15 @@ T:	git https://source.denx.de/u-boot/custodians/u-boot-clk.git
 F:	drivers/clk/
 F:	drivers/clk/imx/

+COLDFIRE
+M:	Huan Wang <alison.wang@nxp.com>
+M:	Angelo Dureghello <angelo@kernel-space.org>
+S:	Maintained
+T:	git https://source.denx.de/u-boot/custodians/u-boot-coldfire.git
+F:	arch/m68k/
+F:	doc/arch/m68k.rst
+F:	drivers/watchdog/mcf_wdt.c
+
 CPU
 M:	Simon Glass <sjg@chromium.org>
 M:	Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
@@ -1116,7 +1109,7 @@ EFI CLIENT
 M:	Simon Glass <sjg@chromium.org>
 M:	Heinrich Schuchardt <xypron.glpk@gmx.de>
 S:	Maintained
-W:	https://docs.u-boot-project.org/en/latest/develop/uefi/u-boot_on_efi.html
+W:	https://docs.u-boot.org/en/latest/develop/uefi/u-boot_on_efi.html
 F:	board/efi/efi-x86_app
 F:	configs/efi-x86_app*
 F:	doc/develop/uefi/u-boot_on_efi.rst
@@ -1163,7 +1156,8 @@ F:	tools/file2include.c
 F:	tools/mkeficapsule.c

 ENVIRONMENT
-S:	Orphaned
+M:	Joe Hershberger <joe.hershberger@ni.com>
+S:	Maintained
 F:	env/
 F:	include/env/
 F:	include/env*
@@ -1256,17 +1250,12 @@ F:	drivers/watchdog/sp805_wdt.c
 F:	drivers/watchdog/sbsa_gwdt.c

 FWU Multi Bank Update
-M:	Sughosh Ganu <sughosh.ganu@arm.com>
-M:	Kory Maincent <kory.maincent@bootlin.com>
+M:	Sughosh Ganu <sughosh.ganu@linaro.org>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-efi.git
-F:	doc/fwumdata.1
-F:	doc/mkfwumdata.1
 F:	lib/fwu_updates/*
 F:	drivers/fwu-mdata/*
-F:	tools/fwumdata_src/fwumdata.c
-F:	tools/fwumdata_src/fwumdata.h
-F:	tools/fwumdata_src/mkfwumdata.c
+F:	tools/mkfwumdata.c

 GATEWORKS_SC
 M:	Tim Harvey <tharvey@gateworks.com>
@@ -1274,18 +1263,6 @@ S:	Maintained
 F:	drivers/misc/gsc.c
 F:	include/gsc.h

-GOLDFISH SERIAL DRIVER
-M:	Kuan-Wei Chiu <visitorckw@gmail.com>
-S:	Maintained
-F:	drivers/serial/serial_goldfish.c
-F:	include/goldfish_tty.h
-
-GOLDFISH TIMER DRIVER
-M:	Kuan-Wei Chiu <visitorckw@gmail.com>
-S:	Maintained
-F:	drivers/timer/goldfish_timer.c
-F:	include/goldfish_timer.h
-
 INTERCONNECT:
 M:	Neil Armstrong <neil.armstrong@linaro.org>
 S:	Maintained
@@ -1320,6 +1297,12 @@ F:	doc/README.kwbimage
 F:	doc/kwboot.1
 F:	tools/kwb*

+LED
+M:	Ivan Vozvakhov <i.vozvakhov@vk.team>
+S:	Supported
+F:	doc/device-tree-bindings/leds/leds-pwm.txt
+F:	drivers/led/led_pwm.c
+
 LOGGING
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
@@ -1332,21 +1315,6 @@ F:	lib/getopt.c
 F:	test/log/
 F:	test/py/tests/test_log.py

-M680X0 ARCHITECTURE
-M:	Kuan-Wei Chiu <visitorckw@gmail.com>
-S:	Maintained
-F:	arch/m68k/cpu/m680x0/
-F:	arch/m68k/include/asm/bootinfo.h
-
-M68K
-M:	Angelo Dureghello <angelo@kernel-space.org>
-M:	Kuan-Wei Chiu <visitorckw@gmail.com>
-S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-coldfire.git
-F:	arch/m68k/
-F:	doc/arch/m68k.rst
-F:	drivers/watchdog/mcf_wdt.c
-
 MALI DISPLAY PROCESSORS
 M:	Liviu Dudau <liviu.dudau@foss.arm.com>
 S:	Supported
@@ -1406,10 +1374,7 @@ F:	drivers/net/phy/ca_phy.c

 MIPS MEDIATEK
 M:	Weijie Gao <weijie.gao@mediatek.com>
-M:	David Lechner <dlechner@baylibre.com>
-M:	Julien Stephan <jstephan@baylibre.com>
 R:	GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>
-T:	git https://source.denx.de/u-boot/custodians/u-boot-mediatek.git
 S:	Maintained
 F:	arch/mips/mach-mtmips/
 F:	arch/mips/dts/mt7620.dtsi
@@ -1479,7 +1444,9 @@ F:	drivers/mmc/
 N:	mmc

 NETWORK
-M:	Jerome Forissier <jerome.forissier@arm.com>
+M:	Joe Hershberger <joe.hershberger@ni.com>
+M:	Ramon Fried <rfried.dev@gmail.com>
+M:	Jerome Forissier <jerome@forissier.org>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-net.git
 F:	drivers/net/
@@ -1487,7 +1454,7 @@ F:	include/net.h
 F:	net/

 NETWORK (LWIP)
-M:	Jerome Forissier <jerome.forissier@arm.com>
+M:	Jerome Forissier <jerome@forissier.org>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-net.git
 F:	cmd/lwip/
@@ -1506,7 +1473,6 @@ T:	git https://source.denx.de/u-boot/custodians/u-boot-nios.git
 F:	arch/nios2/

 NVMe
-M:	Neil Armstrong <neil.armstrong@linaro.org>
 M:	Bin Meng <bmeng.cn@gmail.com>
 S:	Maintained
 F:	drivers/nvme/
@@ -1565,7 +1531,8 @@ F:	drivers/pci/pcie_dw_imx.c
 F:	drivers/phy/phy-imx8m-pcie.c

 PCI Endpoint
-S:	Orphaned
+M:	Ramon Fried <rfried.dev@gmail.com>
+S:	Maintained
 F:	drivers/pci_endpoint/
 F:  include/pci_ep.h

@@ -1622,17 +1589,6 @@ S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-mpc85xx.git
 F:	arch/powerpc/cpu/mpc85xx/

-PWM LED
-S:	Orphan
-F:	doc/device-tree-bindings/leds/leds-pwm.txt
-F:	drivers/led/led_pwm.c
-
-QEMU VIRTUAL SYSTEM CONTROLLER
-M:	Kuan-Wei Chiu <visitorckw@gmail.com>
-S:	Maintained
-F:	drivers/sysreset/sysreset_qemu_virt_ctrl.c
-F:	include/qemu_virt_ctrl.h
-
 RAW NAND
 M:	Dario Binacchi <dario.binacchi@amarulasolutions.com>
 M:	Michael Trimarchi <michael@amarulasolutions.com>
@@ -1673,7 +1629,7 @@ F:	drivers/pinctrl/pinctrl-th1520.c
 F:	drivers/ram/thead/th1520_ddr.c

 RNG
-M:	Sughosh Ganu <sughosh.ganu@arm.com>
+M:	Sughosh Ganu <sughosh.ganu@linaro.org>
 R:	Heinrich Schuchardt <xypron.glpk@gmx.de>
 S:	Maintained
 F:	cmd/rng.c
@@ -1714,7 +1670,7 @@ F:	doc/usage/cmd/seama.rst
 F:	test/cmd/seama.c

 SEMIHOSTING
-R:	Sean Anderson <sean.anderson@linux.dev>
+R:	Sean Anderson <sean.anderson@seco.com>
 S:	Orphaned
 N:	semihosting

@@ -1752,22 +1708,14 @@ F:	cmd/sm3sum.c
 F:	include/u-boot/sm3.h
 F:	lib/sm3.c

-SMBIOS
-M:	Raymond Mao <raymondmaoca@gmail.com>
-S:	Maintained
-F:	arch/arm/dts/smbios_generic.dtsi
-F:	cmd/smbios.c
-F:	drivers/sysinfo/smbios.c
-F:	include/smbios*
-F:	lib/smbios.c
-
 SMCCC TRNG
 M:	Etienne Carriere <etienne.carriere@linaro.org>
 S:	Maintained
 F:	drivers/rng/smccc_trng.c

 SPI
-S:	Orphaned
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-spi.git
 F:	drivers/spi/
 F:	include/spi*
@@ -1781,8 +1729,9 @@ T:	git https://source.denx.de/u-boot/custodians/u-boot-nand-flash.git
 F:	drivers/mtd/nand/spi/

 SPI-NOR
+M:	Jagan Teki <jagan@amarulasolutions.com>
 M:	Vignesh R <vigneshr@ti.com>
-R:	Takahiro Kuwano <takahiro.kuwano@infineon.com>
+R:	Tudor Ambarus <tudor.ambarus@linaro.org>
 S:	Maintained
 F:	drivers/mtd/spi/
 F:	include/spi_flash.h
@@ -1796,15 +1745,13 @@ F:	drivers/spmi/
 F:	include/spmi/

 SQUASHFS
-M:	Joao Marcos Costa <joaomarcos.costa@bootlin.com>
-M:	Richard Genoud <richard.genoud@bootlin.com>
+M:	Joao Marcos Costa <jmcosta944@gmail.com>
 R:	Thomas Petazzoni <thomas.petazzoni@bootlin.com>
 R:	Miquel Raynal <miquel.raynal@bootlin.com>
 S:	Maintained
-F:	cmd/sqfs.c
-F:	common/spl/spl_squashfs.c
 F:	fs/squashfs/
 F:	include/sqfs.h
+F:	cmd/sqfs.c
 F:	test/py/tests/test_fs/test_squashfs/

 STACKPROTECTOR
@@ -1872,14 +1819,10 @@ F:	drivers/tpm/
 F:	include/tpm*
 F:	lib/tpm*

-TQ-SYSTEMS
-L:	u-boot@ew.tq-group.com
-S:	Maintained
-W:	https://www.tq-group.com/en/products/tq-embedded/
-F:	board/tq/*
-F:	doc/board/tq/*
-F:	include/configs/tq*.h
-F:	include/env/tq/*
+TQ GROUP
+#M:	Martin Krause <martin.krause@tq-systems.de>
+S:	Orphaned (Since 2016-02)
+T:	git git://git.denx.de/u-boot-tq-group.git

 TEE
 M:	Jens Wiklander <jens.wiklander@linaro.org>
@@ -1921,7 +1864,6 @@ M:	Neil Armstrong <neil.armstrong@linaro.org>
 M:	Bhupesh Sharma <bhupesh.linux@gmail.com>
 M:	Neha Malcom Francis <n-francis@ti.com>
 S:	Maintained
-F:	common/spl/spl_ufs.c
 F:	drivers/ufs/

 UPL
@@ -1964,7 +1906,7 @@ F:	drivers/usb/host/xhci*
 F:	include/usb/xhci.h

 UTHREAD
-M:	Jerome Forissier <jerome.forissier@arm.com>
+M:	Jerome Forissier <jerome@forissier.org>
 S:	Maintained
 F:	cmd/spawn.c
 F:	include/uthread.h
--- a/55
+++ b/55
@@ -1,9 +1,9 @@
 # SPDX-License-Identifier: GPL-2.0+

 VERSION = 2026
-PATCHLEVEL = 07
+PATCHLEVEL = 04
 SUBLEVEL =
-EXTRAVERSION = -rc4
+EXTRAVERSION = -rc1
 NAME =

 # *DOCUMENTATION*
@@ -531,7 +531,7 @@ UBOOTINCLUDE    := \
 		-I$(srctree)/lib/mbedtls/external/mbedtls/include) \
 	$(if $(CONFIG_$(PHASE_)SYS_THUMB_BUILD), \
 		$(if $(CONFIG_HAS_THUMB2), \
-			$(if $(CONFIG_CPU_V7M_V8M), \
+			$(if $(CONFIG_CPU_V7M), \
 				-I$(srctree)/arch/arm/thumb1/include), \
 			-I$(srctree)/arch/arm/thumb1/include)) \
 	-I$(srctree)/arch/$(ARCH)/include \
@@ -920,7 +920,7 @@ endif
 ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE
 KBUILD_CFLAGS	+= -Os
 else ifdef CONFIG_CC_OPTIMIZE_FOR_DEBUG
-KBUILD_CFLAGS  += -Og
+-KBUILD_CFLAGS  += -Og
 # Avoid false positives -Wmaybe-uninitialized
 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78394
 KBUILD_CFLAGS  += -Wno-maybe-uninitialized
@@ -1050,7 +1050,7 @@ UBOOTINCLUDE    := \
 		-I$(srctree)/lib/mbedtls/external/mbedtls/include) \
 	$(if $(CONFIG_$(PHASE_)SYS_THUMB_BUILD), \
 		$(if $(CONFIG_HAS_THUMB2), \
-			$(if $(CONFIG_CPU_V7M_V8M), \
+			$(if $(CONFIG_CPU_V7M), \
 				-I$(srctree)/arch/arm/thumb1/include), \
 			-I$(srctree)/arch/arm/thumb1/include)) \
 	-I$(srctree)/arch/$(ARCH)/include \
@@ -1081,7 +1081,7 @@ libs-$(CONFIG_OF_EMBED) += dts/
 libs-y += env/
 libs-y += lib/
 libs-y += fs/
-libs-$(CONFIG_NET) += net/
+libs-$(filter y,$(CONFIG_NET) $(CONFIG_NET_LWIP)) += net/
 libs-y += disk/
 libs-y += drivers/
 libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
@@ -1231,7 +1231,6 @@ ifneq ($(CONFIG_SPL_TARGET),)
 INPUTS-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%)
 endif
 INPUTS-$(CONFIG_REMAKE_ELF) += u-boot.elf
-INPUTS-$(CONFIG_SPL_REMAKE_ELF) += spl/u-boot-spl.elf
 INPUTS-$(CONFIG_EFI_APP) += u-boot-app.efi
 INPUTS-$(CONFIG_EFI_STUB) += u-boot-payload.efi

@@ -1373,7 +1372,7 @@ expect = $(foreach cfg,$(1),y)
 # 1: List of options to migrate to (e.g. "CONFIG_DM_MMC CONFIG_BLK")
 # 2: Name of component (e.g . "Ethernet drivers")
 # 3: Release deadline (e.g. "v202.07")
-# 4: Condition to require before checking (e.g. "$(CONFIG_NET_LEGACY)")
+# 4: Condition to require before checking (e.g. "$(CONFIG_NET)")
 # Note: Script avoids bash construct, hence the strange double 'if'
 # (patches welcome!)
 define deprecated
@@ -1423,6 +1422,7 @@ endif

 PHONY += dtbs dtbs_check
 dtbs: dts/dt.dtb
+	@:
 dts/dt.dtb: dtbs_prepare u-boot
 	$(Q)$(MAKE) $(build)=dts dtbs

@@ -1446,15 +1446,11 @@ quiet_cmd_copy = COPY    $@
      cmd_copy = cp $< $@

 ifeq ($(CONFIG_OF_UPSTREAM),y)
-ifeq ($(CONFIG_CPU_V8M),y)
-dt_dir := dts/upstream/src/arm64
-else
 ifeq ($(CONFIG_ARM64),y)
 dt_dir := dts/upstream/src/arm64
 else
 dt_dir := dts/upstream/src/$(ARCH)
 endif
-endif
 else
 dt_dir := arch/$(ARCH)/dts
 endif
@@ -1578,9 +1574,6 @@ spl/u-boot-spl.srec: spl/u-boot-spl FORCE
 %.scif: %.srec
 	$(Q)$(MAKE) $(build)=arch/arm/mach-renesas $@

-%.shdr: %.srec
-	$(Q)$(MAKE) $(build)=arch/arm/mach-renesas $@
-
 OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
 		$(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \
 		$(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),$(if $(CONFIG_OF_SEPARATE),-R .bootpg -R .resetvec))
@@ -1685,7 +1678,7 @@ cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
 		build -u -d $(binman_dtb) -O . -m \
 		--allow-missing --fake-ext-blobs \
 		$(if $(BINMAN_ALLOW_MISSING),--ignore-missing) \
-		-I . -I $(srctree)/board/$(BOARDDIR) -I $(srctree) \
+		-I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \
 		$(foreach f,$(of_list_dirs),-I $(f)) -a of-list=$(of_list) \
 		$(foreach f,$(BINMAN_INDIRS),-I $(f)) \
 		-a atf-bl1-path=${BL1} \
@@ -2008,15 +2001,6 @@ u-boot.elf: u-boot.bin u-boot-elf.lds FORCE
 	$(Q)$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< u-boot-elf.o
 	$(call if_changed,u-boot-elf)

-quiet_cmd_u-boot-spl-elf ?= LD      $@
-	cmd_u-boot-spl-elf ?= $(LD) spl/u-boot-spl-elf.o -o $@ \
-	$(if $(CONFIG_SYS_BIG_ENDIAN),-EB,-EL) \
-	-T u-boot-elf.lds --defsym=$(CONFIG_PLATFORM_ELFENTRY)=$(CONFIG_SPL_TEXT_BASE) \
-	-Ttext=$(CONFIG_SPL_TEXT_BASE)
-spl/u-boot-spl.elf: spl/u-boot-spl.bin u-boot-elf.lds
-	$(Q)$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< spl/u-boot-spl-elf.o
-	$(call if_changed,u-boot-spl-elf)
-
 u-boot-elf.lds: arch/u-boot-elf.lds prepare FORCE
 	$(call if_changed_dep,cpp_lds)

@@ -2150,12 +2134,10 @@ ENV_FILE := $(if $(ENV_SOURCE_FILE),$(ENV_FILE_CFG),$(wildcard $(ENV_FILE_BOARD)
 quiet_cmd_gen_envp = ENVP    $@
      cmd_gen_envp = \
 	if [ -s "$(ENV_FILE)" ]; then \
-		$(CPP) -P $(KBUILD_CPPFLAGS) $(UBOOTINCLUDE) \
-			-x assembler-with-cpp -undef \
+		$(CPP) -P $(cpp_flags) -x assembler-with-cpp -undef \
 			-D__ASSEMBLY__ \
 			-D__UBOOT_CONFIG__ \
 			-DDEFAULT_DEVICE_TREE=$(subst ",,$(CONFIG_DEFAULT_DEVICE_TREE)) \
-			-DDEFAULT_FDT_FILE=$(subst ",,$(CONFIG_DEFAULT_FDT_FILE)) \
 			-I . -I include -I $(srctree)/include \
 			-include linux/kconfig.h -include include/config.h \
 			-I$(srctree)/arch/$(ARCH)/include \
@@ -2544,7 +2526,7 @@ CLEAN_FILES  += $(MODVERDIR) \
 			$(filter-out include, $(shell ls -1 $d 2>/dev/null))))

 CLEAN_FILES += include/autoconf.mk* include/bmp_logo.h include/bmp_logo_data.h \
-	       include/config.h include/generated/env.* drivers/video/u_boot_logo.bmp.S \
+	       include/config.h include/generated/env.* drivers/video/u_boot_logo.S \
 	       tools/version.h u-boot* MLO* SPL System.map fit-dtb.blob* \
 	       u-boot-ivt.img.log u-boot-dtb.imx.log SPL.log u-boot.imx.log \
 	       lpc32xx-* bl31.c bl31.elf bl31_*.bin image.map tispl.bin* \
@@ -2755,19 +2737,21 @@ help:
 	@echo  'Execute "make" or "make all" to build all targets marked with [*] '
 	@echo  'For further info see the ./README file'

-run_tests = $(Q)env -u sub_make_done $(srctree)/test/run
+ifneq ($(filter tests pcheck qcheck tcheck,$(MAKECMDGOALS)),)
+export sub_make_done := 0
+endif

 tests check:
-	$(run_tests)
+	$(srctree)/test/run

 pcheck:
-	$(run_tests) parallel
+	$(srctree)/test/run parallel

 qcheck:
-	$(run_tests) quick
+	$(srctree)/test/run quick

 tcheck:
-	$(run_tests) tools
+	$(srctree)/test/run tools

 # Documentation targets
 # ---------------------------------------------------------------------------
@@ -2775,7 +2759,8 @@ DOC_TARGETS := xmldocs latexdocs pdfdocs htmldocs epubdocs cleandocs \
 	       linkcheckdocs dochelp refcheckdocs texinfodocs infodocs
 PHONY += $(DOC_TARGETS)
 $(DOC_TARGETS): scripts_basic FORCE
-	$(Q)$(MAKE) $(build)=doc $@
+	$(Q)PYTHONPATH=$(srctree)/test/py/tests:$(srctree)/test/py \
+	$(MAKE) $(build)=doc $@

 PHONY += checkstack ubootrelease ubootversion

--- a/122
+++ b/122
@@ -597,6 +597,32 @@ The following options need to be configured:

 		A byte containing the id of the VLAN.

+- Status LED:	CONFIG_LED_STATUS
+
+		Several configurations allow to display the current
+		status using a LED. For instance, the LED will blink
+		fast while running U-Boot code, stop blinking as
+		soon as a reply to a BOOTP request was received, and
+		start blinking slow once the Linux kernel is running
+		(supported by a status LED driver in the Linux
+		kernel). Defining CONFIG_LED_STATUS enables this
+		feature in U-Boot.
+
+		Additional options:
+
+		CONFIG_LED_STATUS_GPIO
+		The status LED can be connected to a GPIO pin.
+		In such cases, the gpio_led driver can be used as a
+		status LED backend implementation. Define CONFIG_LED_STATUS_GPIO
+		to include the gpio_led driver in the U-Boot binary.
+
+		CFG_GPIO_LED_INVERTED_TABLE
+		Some GPIO connected LEDs may have inverted polarity in which
+		case the GPIO high value corresponds to LED off state and
+		GPIO low value corresponds to LED on state.
+		In such cases CFG_GPIO_LED_INVERTED_TABLE may be defined
+		with a list of GPIO LEDs that have inverted polarity.
+
 - I2C Support:
 		CFG_SYS_NUM_I2C_BUSES
 		Hold the number of i2c buses you want to use.
@@ -628,6 +654,98 @@ The following options need to be configured:

 		If you do not have i2c muxes on your board, omit this define.

+- Legacy I2C Support:
+		If you use the software i2c interface (CONFIG_SYS_I2C_SOFT)
+		then the following macros need to be defined (examples are
+		from include/configs/lwmon.h):
+
+		I2C_INIT
+
+		(Optional). Any commands necessary to enable the I2C
+		controller or configure ports.
+
+		eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |=	PB_SCL)
+
+		I2C_ACTIVE
+
+		The code necessary to make the I2C data line active
+		(driven).  If the data line is open collector, this
+		define can be null.
+
+		eg: #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |=  PB_SDA)
+
+		I2C_TRISTATE
+
+		The code necessary to make the I2C data line tri-stated
+		(inactive).  If the data line is open collector, this
+		define can be null.
+
+		eg: #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
+
+		I2C_READ
+
+		Code that returns true if the I2C data line is high,
+		false if it is low.
+
+		eg: #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+
+		I2C_SDA(bit)
+
+		If <bit> is true, sets the I2C data line high. If it
+		is false, it clears it (low).
+
+		eg: #define I2C_SDA(bit) \
+			if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else	immr->im_cpm.cp_pbdat &= ~PB_SDA
+
+		I2C_SCL(bit)
+
+		If <bit> is true, sets the I2C clock line high. If it
+		is false, it clears it (low).
+
+		eg: #define I2C_SCL(bit) \
+			if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else	immr->im_cpm.cp_pbdat &= ~PB_SCL
+
+		I2C_DELAY
+
+		This delay is invoked four times per clock cycle so this
+		controls the rate of data transfer.  The data rate thus
+		is 1 / (I2C_DELAY * 4). Often defined to be something
+		like:
+
+		#define I2C_DELAY  udelay(2)
+
+		CONFIG_SOFT_I2C_GPIO_SCL / CONFIG_SOFT_I2C_GPIO_SDA
+
+		If your arch supports the generic GPIO framework (asm/gpio.h),
+		then you may alternatively define the two GPIOs that are to be
+		used as SCL / SDA.  Any of the previous I2C_xxx macros will
+		have GPIO-based defaults assigned to them as appropriate.
+
+		You should define these to the GPIO value as given directly to
+		the generic GPIO functions.
+
+		CFG_SYS_I2C_NOPROBES
+
+		This option specifies a list of I2C devices that will be skipped
+		when the 'i2c probe' command is issued.
+
+		e.g.
+			#define CFG_SYS_I2C_NOPROBES {0x50,0x68}
+
+		will skip addresses 0x50 and 0x68 on a board with one I2C bus
+
+		CONFIG_SOFT_I2C_READ_REPEATED_START
+
+		defining this will force the i2c_read() function in
+		the soft_i2c driver to perform an I2C repeated start
+		between writing the address pointer and reading the
+		data.  If this define is omitted the default behaviour
+		of doing a stop-start sequence will be used.  Most I2C
+		devices can use either method, but some require one or
+		the other.
+
 - SPI Support:	CONFIG_SPI

 		Enables SPI driver (so far only tested with
@@ -1544,7 +1662,7 @@ New uImage format (FIT)
 Flexible and powerful format based on Flattened Image Tree -- FIT (similar
 to Flattened Device Tree). It allows the use of images with multiple
 components (several kernels, ramdisks, etc.), with contents protected by
-SHA1, MD5 or CRC32. More details are found in the doc/usage/fit directory.
+SHA1, MD5 or CRC32. More details are found in the doc/uImage.FIT directory.


 Old uImage format
@@ -2281,5 +2399,5 @@ Contributing

 The U-Boot projects depends on contributions from the user community.
 If you want to participate, please, have a look at the 'General'
-section of https://docs.u-boot-project.org/en/latest/develop/index.html
+section of https://docs.u-boot.org/en/latest/develop/index.html
 where we describe coding standards and the patch submission process.
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -190,7 +190,6 @@ config SANDBOX
 	select HAVE_SETJMP
 	select HAVE_INITJMP
 	select ARCH_SUPPORTS_LTO
-	select AXI
 	select BOARD_LATE_INIT
 	select BZIP2
 	select CMD_POWEROFF if CMDLINE
@@ -200,37 +199,24 @@ config SANDBOX
 	select DM_GPIO
 	select DM_I2C
 	select DM_KEYBOARD
-	select DM_MAILBOX
-	select DM_RESET
 	select DM_SERIAL
 	select DM_SPI
 	select DM_SPI_FLASH
-	select GPIO
 	select GZIP_COMPRESSED
-	select I2C
 	select LZO
 	select MMC
 	select MTD
 	select OF_BOARD_SETUP
-	select OF_CONTROL
 	select PCI_ENDPOINT
-	select SANDBOX_RESET
 	select SPI
-	select SERIAL
 	select SUPPORT_OF_CONTROL
 	select SUPPORT_BIG_ENDIAN
 	select SUPPORT_LITTLE_ENDIAN
-	select SYSRESET
-	select SYSRESET_CMD_RESET
-	select SYSRESET_CMD_POWEROFF if SYSRESET && CMD_POWEROFF
+	select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
 	select SYS_CACHE_SHIFT_4
 	select IRQ
 	select SUPPORT_EXTENSION_SCAN if CMDLINE
 	select SUPPORT_ACPI
-	select TIMER
-	select SPL_TIMER if SPL
-	select TPL_TIMER if TPL
-	select VPL_TIMER if VPL
 	imply BITREVERSE
 	select BLOBLIST
 	imply LTO
@@ -254,7 +240,7 @@ config SANDBOX
 	imply AVB_VERIFY
 	imply LIBAVB
 	imply CMD_AVB
-	imply PARTITION_TYPE_GUID if EFI_PARTITION
+	imply PARTITION_TYPE_GUID
 	imply SCP03
 	imply CMD_SCP03
 	imply UDP_FUNCTION_FASTBOOT
@@ -264,7 +250,7 @@ config SANDBOX
 	# Re-enable this when fully implemented
 	# imply VIRTIO_BLK
 	imply VIRTIO_NET
-	imply SOUND
+	imply DM_SOUND
 	imply PCI_SANDBOX_EP
 	imply PCH
 	imply PHYLIB
@@ -280,6 +266,7 @@ config SANDBOX
 	imply PHY_FIXED
 	imply DM_DSA
 	imply CMD_EXTENSION
+	imply KEYBOARD
 	imply PHYSMEM
 	imply GENERATE_ACPI_TABLE
 	imply BINMAN
@@ -297,7 +284,6 @@ config SH

 config X86
 	bool "x86 architecture"
-	select AHCI
 	select HAVE_SETJMP
 	select SUPPORT_SPL
 	select SUPPORT_TPL
@@ -306,7 +292,6 @@ config X86
 	select DM
 	select HAVE_ARCH_IOMAP
 	select HAVE_PRIVATE_LIBGCC
-	select LMB_ARCH_MEM_MAP
 	select OF_CONTROL
 	select PCI
 	select SUPPORT_ACPI
--- a/arch/arc/lib/bootm.c
+++ b/arch/arc/lib/bootm.c
@@ -10,6 +10,9 @@
 #include <irq_func.h>
 #include <log.h>
 #include <asm/cache.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;

 static int cleanup_before_linux(void)
 {
@@ -50,13 +53,17 @@ static void boot_jump_linux(struct bootm_headers *images, int flag)
 {
 	ulong kernel_entry;
 	unsigned int r0, r2;
+	int fake = (flag & BOOTM_STATE_OS_FAKE_GO);
+
 	kernel_entry = images->ep;

 	debug("## Transferring control to Linux (at address %08lx)...\n",
 	      kernel_entry);
 	bootstage_mark(BOOTSTAGE_ID_RUN_OS);

-	bootm_final(flag);
+	printf("\nStarting kernel ...%s\n\n", fake ?
+	       "(fake run for tracing)" : "");
+	bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");

 	if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
 		r0 = 2;
@@ -68,7 +75,7 @@ static void boot_jump_linux(struct bootm_headers *images, int flag)

 	cleanup_before_linux();

-	if (!(flag & BOOTM_STATE_OS_FAKE_GO))
+	if (!fake)
 		board_jump_and_run(kernel_entry, r0, 0, r2);
 }

--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -30,7 +30,7 @@ config COUNTER_FREQUENCY
 			ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036
 	default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A
 	default 100000000 if ARCH_ZYNQMP
-	default 200000000 if ARCH_SOCFPGA_AGILEX5 || ARCH_SOCFPGA_AGILEX7M
+	default 200000000 if TARGET_SOCFPGA_AGILEX5 || TARGET_SOCFPGA_AGILEX7M
 	default 0
 	help
 	  For platforms with ARMv8-A and ARMv7-A which features a system
@@ -363,8 +363,7 @@ config CPU_V7A
 	select SYS_CACHE_SHIFT_6
 	imply SYS_ARM_MMU

-# ARMv7-M/ARMv8-M
-config CPU_V7M_V8M
+config CPU_V7M
 	bool
 	select HAS_THUMB2
 	select SYS_ARM_MPU
@@ -373,10 +372,6 @@ config CPU_V7M_V8M
 	select THUMB2_KERNEL
 	select NVIC

-config CPU_V7M
-	bool
-	select CPU_V7M_V8M
-
 config CPU_V7R
 	bool
 	select HAS_THUMB2
@@ -384,10 +379,6 @@ config CPU_V7R
 	select SYS_ARM_MPU
 	select SYS_CACHE_SHIFT_6

-config CPU_V8M
-	bool
-	select CPU_V7M_V8M
-
 config SYS_CPU
 	default "arm720t" if CPU_ARM720T
 	default "arm920t" if CPU_ARM920T
@@ -398,7 +389,6 @@ config SYS_CPU
 	default "armv7" if CPU_V7A
 	default "armv7" if CPU_V7R
 	default "armv7m" if CPU_V7M
-	default "armv7m" if CPU_V8M
 	default "armv8" if ARM64

 config SYS_ARM_ARCH
@@ -412,7 +402,6 @@ config SYS_ARM_ARCH
 	default 7 if CPU_V7A
 	default 7 if CPU_V7M
 	default 7 if CPU_V7R
-	default 7 if CPU_V8M
 	default 8 if ARM64

 choice
@@ -456,7 +445,7 @@ config ARCH_CPU_INIT

 config SYS_ARCH_TIMER
 	bool "ARM Generic Timer support"
-	depends on CPU_V7A || CPU_V7M_V8M || ARM64
+	depends on CPU_V7A || CPU_V7M || ARM64
 	default y if ARM64
 	help
 	  The ARM Generic Timer (aka arch-timer) provides an architected
@@ -845,9 +834,6 @@ config ARCH_K3
 	imply DM_RNG if ARM64
 	imply TEE if ARM64
 	imply OPTEE if ARM64
-	imply TPM if ARM64 && MMC
-	imply TPM2_FTPM_TEE if ARM64 && MMC
-	imply SUPPORT_EMMC_RPMB if ARM64 && MMC

 config ARCH_OMAP2PLUS
 	bool "TI OMAP2+"
@@ -1082,7 +1068,6 @@ config ARCH_APPLE
 	imply CMD_GPT
 	imply BOOTSTD_FULL
 	imply OF_HAS_PRIOR_STAGE
-	imply OF_UPSTREAM

 config ARCH_OWL
 	bool "Actions Semi OWL SoCs"
@@ -1160,35 +1145,35 @@ config ARCH_SNAPDRAGON
 config ARCH_SOCFPGA
 	bool "Altera SOCFPGA family"
 	select ARCH_EARLY_INIT_R
-	select ARCH_MISC_INIT if !ARCH_SOCFPGA_ARRIA10
-	select ARM64 if ARCH_SOCFPGA_SOC64
-	select CPU_V7A if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10
+	select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
+	select ARM64 if TARGET_SOCFPGA_SOC64
+	select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
 	select DM
 	select DM_SERIAL
 	select GPIO_EXTRA_HEADER
-	select ENABLE_ARM_SOC_BOOT0_HOOK if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10
-	select LMB_ARCH_MEM_MAP if ARCH_SOCFPGA_SOC64
+	select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
+	select LMB_ARCH_MEM_MAP if TARGET_SOCFPGA_SOC64
 	select OF_CONTROL
 	select SPL_DM_RESET if DM_RESET
 	select SPL_DM_SERIAL
 	select SPL_LIBCOMMON_SUPPORT
 	select SPL_LIBGENERIC_SUPPORT
 	select SPL_OF_CONTROL
-	select SPL_SEPARATE_BSS if ARCH_SOCFPGA_SOC64
-	select SPL_DRIVERS_MISC if ARCH_SOCFPGA_SOC64
-	select SPL_SOCFPGA_DT_REG if ARCH_SOCFPGA_SOC64
+	select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
+	select SPL_DRIVERS_MISC if TARGET_SOCFPGA_SOC64
+	select SPL_SOCFPGA_DT_REG if TARGET_SOCFPGA_SOC64
 	select SPL_SERIAL
 	select SPL_SYSRESET
 	select SPL_WATCHDOG
 	select SUPPORT_SPL
 	select SYS_NS16550
-	select SYS_THUMB_BUILD if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10
+	select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
 	select SYSRESET
-	select SYSRESET_SOCFPGA if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10
-	select SYSRESET_SOCFPGA_SOC64 if !ARCH_SOCFPGA_AGILEX5 && \
-           ARCH_SOCFPGA_SOC64
-	select SYSRESET_PSCI if ARCH_SOCFPGA_AGILEX5
-	select USE_BOOTFILE if SPL_ATF && ARCH_SOCFPGA_SOC64
+	select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
+	select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && \
+           TARGET_SOCFPGA_SOC64
+	select SYSRESET_PSCI if TARGET_SOCFPGA_AGILEX5
+	select USE_BOOTFILE if SPL_ATF && TARGET_SOCFPGA_SOC64
 	imply CMD_DM
 	imply CMD_MTDPARTS
 	imply CRC32_VERIFY
@@ -2169,6 +2154,7 @@ config TARGET_POMELO
 	select SCSI_AHCI
 	select AHCI_PCI
 	select PCI
+	select DM_PCI
 	select SCSI
 	select DM_SERIAL
 	imply CMD_PCI
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -16,7 +16,6 @@ arch-$(CONFIG_CPU_V7A)		=$(call cc-option, -march=armv7-a, \
 				 $(call cc-option, -march=armv7))
 arch-$(CONFIG_CPU_V7M)		=-march=armv7-m
 arch-$(CONFIG_CPU_V7R)		=-march=armv7-r
-arch-$(CONFIG_CPU_V8M)		=-march=armv8-m.main
 ifeq ($(CONFIG_ARM64_CRC32),y)
 arch-$(CONFIG_ARM64)		=-march=armv8-a+crc
 else
@@ -43,7 +42,6 @@ tune-$(CONFIG_CPU_ARM1136)	=
 tune-$(CONFIG_CPU_ARM1176)	=
 tune-$(CONFIG_CPU_V7A)		=-mtune=generic-armv7-a
 tune-$(CONFIG_CPU_V7R)		=
-tune-$(CONFIG_CPU_V8M)		=
 tune-$(CONFIG_ARM64)		=

 # Evaluate tune cc-option calls now
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -112,14 +112,6 @@ endif
 # needed for relocation
 LDFLAGS_u-boot += -pie

-ifeq ($(CONFIG_ARM64),y)
-# U-Boot uses fixed 4K granules, so we force the linker to match.
-# Otherwise, we're subject to toolchain preferences, (e.g Fedora's
-# aarch64-linux-none toolchain selects 64K granules) and we end up wasting
-# a lot of space in ELFs with MMU_PGPROT enabled.
-LDFLAGS_u-boot += -z common-page-size=0x1000 -z max-page-size=0x1000
-endif
-
 #
 # FIXME: binutils versions < 2.22 have a bug in the assembler where
 # branches to weak symbols can be incorrectly optimized in thumb mode
--- a/arch/arm/cpu/armv7/s5p4418/cpu.c
+++ b/arch/arm/cpu/armv7/s5p4418/cpu.c
@@ -7,6 +7,7 @@
 #include <command.h>
 #include <asm/system.h>
 #include <asm/cache.h>
+#include <asm/global_data.h>
 #include <asm/sections.h>
 #include <asm/io.h>
 #include <asm/arch/nexell.h>
@@ -14,6 +15,8 @@
 #include <asm/arch/tieoff.h>
 #include <cpu_func.h>

+DECLARE_GLOBAL_DATA_PTR;
+
 #ifndef	CONFIG_ARCH_CPU_INIT
 #error must be define the macro "CONFIG_ARCH_CPU_INIT"
 #endif
--- a/arch/arm/cpu/armv7m/cpu.c
+++ b/arch/arm/cpu/armv7m/cpu.c
@@ -19,9 +19,6 @@
 */
 int cleanup_before_linux(void)
 {
-	if (!CONFIG_IS_ENABLED(LIB_BOOTM) && !CONFIG_IS_ENABLED(LIB_BOOTZ))
-		return 0;
-
 	/*
 	 * this function is called just before we call linux
 	 * it prepares the processor for linux
@@ -48,9 +45,8 @@ int cleanup_before_linux(void)
 }

 /*
- * Perform the low-level reset. ARMv7M only.
+ * Perform the low-level reset.
 */
-#if IS_ENABLED(CONFIG_CPU_V7M)
 void reset_cpu(void)
 {
 	/*
@@ -60,10 +56,8 @@ void reset_cpu(void)
 		| (V7M_SCB->aircr & V7M_AIRCR_PRIGROUP_MSK)
 		| V7M_AIRCR_SYSRESET, &V7M_SCB->aircr);
 }
-#endif

 void spl_perform_arch_fixups(struct spl_image_info *spl_image)
 {
-	if (IS_ENABLED(CONFIG_XPL_BUILD))
-		spl_image->entry_point |= 0x1;
+	spl_image->entry_point |= 0x1;
 }
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -810,10 +810,8 @@ __weak void mmu_setup(void)
 	el = current_el();
 	set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(NULL, NULL),
 			  MEMORY_ATTRIBUTES);
-}

-void mmu_enable(void)
-{
+	/* enable the mmu */
 	set_sctlr(get_sctlr() | CR_M);
 }

@@ -880,17 +878,15 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
 void dcache_enable(void)
 {
 	/* The data cache is not active unless the mmu is enabled */
-	if (!mmu_status()) {
-		__asm_invalidate_tlb_all();
+	if (!mmu_status())
 		mmu_setup();
-		mmu_enable();
-	}

 	/* Set up page tables only once (it is done also by mmu_setup()) */
 	if (!gd->arch.tlb_fillptr)
 		setup_all_pgtables();

 	invalidate_dcache_all();
+	__asm_invalidate_tlb_all();
 	set_sctlr(get_sctlr() | CR_C);
 }

--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -382,7 +382,6 @@ menu "Layerscape architecture"
 config FSL_LAYERSCAPE
 	bool
 	select ARM_SMCCC
-	select LMB_ARCH_MEM_MAP

 config HAS_FEATURE_GIC64K_ALIGN
 	bool
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1143,7 +1143,7 @@ int arch_early_init_r(void)
 #ifdef CONFIG_SYS_HAS_SERDES
 	fsl_serdes_init();
 #endif
-#if defined(CONFIG_SYS_FSL_HAS_RGMII) && defined(CONFIG_FSL_MC_ENET)
+#ifdef CONFIG_SYS_FSL_HAS_RGMII
 	/* some dpmacs in armv8a based freescale layerscape SOCs can be
 	 * configured via both serdes(sgmii, 10gbase-r, xlaui etc) bits and via
 	 * EC*_PMUX(rgmii) bits in RCW.
@@ -1158,10 +1158,6 @@ int arch_early_init_r(void)
 	 * function of SOC, the dpmac will be enabled as RGMII even if it was
 	 * also enabled before as SGMII. If ECx_PMUX is not configured for
 	 * RGMII, DPMAC will remain configured as SGMII from fsl_serdes_init().
-	 *
-	 * fsl_rgmii_init() itself is only built under CONFIG_FSL_MC_ENET
-	 * (drivers/net/ldpaa_eth/); gate the call the same way so builds
-	 * without MC-ENET still link.
 	 */
 	fsl_rgmii_init();
 #endif
@@ -1553,8 +1549,7 @@ void lmb_arch_add_memory(void)
 		    gd->arch.resv_ram < ram_start + ram_size)
 			ram_size = gd->arch.resv_ram - ram_start;
 #endif
-		if (ram_size > 0)
-			lmb_add(ram_start, ram_size);
+		lmb_add(ram_start, ram_size);
 	}
 }
 #endif
--- a/arch/arm/cpu/armv8/fwcall.c
+++ b/arch/arm/cpu/armv8/fwcall.c
@@ -129,18 +129,3 @@ void __noreturn psci_system_off(void)
 	while (1)
 		;
 }
-
-int psci_features(u32 psci_func_id)
-{
-	struct pt_regs regs;
-
-	regs.regs[0] = ARM_PSCI_1_0_FN_PSCI_FEATURES;
-	regs.regs[1] = psci_func_id;
-
-	if (use_smc_for_psci)
-		smc_call(&regs);
-	else
-		hvc_call(&regs);
-
-	return regs.regs[0];
-}
--- a/arch/arm/cpu/armv8/u-boot-spl.lds
+++ b/arch/arm/cpu/armv8/u-boot-spl.lds
@@ -49,6 +49,12 @@ SECTIONS
 	} >.sram
 #endif

+	__u_boot_list : {
+		. = ALIGN(8);
+		KEEP(*(SORT(__u_boot_list*)));
+		. = ALIGN(8);
+	} >.sram
+
 	.binman_sym_table : {
 		. = ALIGN(8);
 		__binman_sym_start = .;
@@ -57,12 +63,6 @@ SECTIONS
 		. = ALIGN(8);
 	} > .sram

-	__u_boot_list : {
-		. = ALIGN(8);
-		KEEP(*(SORT(__u_boot_list*)));
-		. = ALIGN(8);
-	} >.sram
-
 	__image_copy_end = .;
 	_end = .;
 	_image_binary_end = .;
@@ -75,7 +75,7 @@ SECTIONS
 		__bss_end = .;
 	} >.sdram
 #else
-	.bss _image_binary_end (OVERLAY) : {
+	.bss (NOLOAD) : {
 		__bss_start = .;
 		*(.bss*)
 		 . = ALIGN(8);
@@ -99,6 +99,5 @@ SECTIONS

 ASSERT(_image_binary_end % 8 == 0, \
       "_image_binary_end must be 8-byte aligned for device tree");
-
 ASSERT(ADDR(.bss) % 8 == 0, \
       ".bss must be 8-byte aligned");
--- a/arch/arm/cpu/u-boot-spl.lds
+++ b/arch/arm/cpu/u-boot-spl.lds
@@ -31,16 +31,16 @@ SECTIONS
 		*(.data*)
 	}

+	. = ALIGN(4);
+	__u_boot_list : {
+		KEEP(*(SORT(__u_boot_list*)));
+	}
+
 	. = ALIGN(4);
 	.binman_sym_table : {
 		__binman_sym_start = .;
 		KEEP(*(SORT(.binman_sym*)));
 		__binman_sym_end = .;
-	}
-
-	. = ALIGN(4);
-	__u_boot_list : {
-		KEEP(*(SORT(__u_boot_list*)));
 		. = ALIGN(8);
 	}

@@ -48,7 +48,7 @@ SECTIONS
 	_image_binary_end = .;
 	_end = .;

-	.bss _image_binary_end (OVERLAY) : {
+	.bss : {
 		__bss_start = .;
 		*(.bss*)
 		 . = ALIGN(8);
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -32,6 +32,13 @@ dtb-$(CONFIG_TARGET_A5Y17LTE) += exynos78x0-axy17lte.dtb
 dtb-$(CONFIG_TARGET_A3Y17LTE) += exynos78x0-axy17lte.dtb
 dtb-$(CONFIG_TARGET_A7Y17LTE) += exynos78x0-axy17lte.dtb

+dtb-$(CONFIG_ARCH_APPLE) += \
+	t8103-j274.dtb \
+	t8103-j293.dtb \
+	t8103-j313.dtb \
+	t8103-j456.dtb \
+	t8103-j457.dtb
+
 dtb-$(CONFIG_ARCH_DAVINCI) += \
 	da850-lcdk.dtb \
 	da850-lego-ev3.dtb
@@ -45,6 +52,23 @@ dtb-$(CONFIG_MACH_S900) += \
 dtb-$(CONFIG_MACH_S700) += \
 	s700-cubieboard7.dtb

+dtb-$(CONFIG_ROCKCHIP_RK3128) += \
+	rk3128-evb.dtb
+
+dtb-$(CONFIG_ROCKCHIP_RK322X) += \
+	rk3229-evb.dtb
+
+dtb-$(CONFIG_ROCKCHIP_RK3288) += \
+	rk3288-evb.dtb \
+	rk3288-popmetal.dtb \
+	rk3288-rock2-square.dtb \
+	rk3288-rock-pi-n8.dtb \
+	rk3288-veyron-jerry.dtb \
+	rk3288-veyron-mickey.dtb \
+	rk3288-veyron-minnie.dtb \
+	rk3288-veyron-speedy.dtb \
+	rk3288-vyasa.dtb
+
 dtb-$(CONFIG_ROCKCHIP_RK3368) += \
 	rk3368-sheep.dtb \
 	rk3368-geekbox.dtb \
@@ -445,8 +469,6 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_cyclone5_socrates.dtb			\
 	socfpga_cyclone5_sr1500.dtb			\
 	socfpga_cyclone5_vining_fpga.dtb		\
-	socfpga_cyclone5_ac501soc.dtb			\
-	socfpga_cyclone5_ac550soc.dtb			\
 	socfpga_n5x_socdk.dtb				\
 	socfpga_stratix10_socdk.dtb

@@ -866,6 +888,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
 	imx8mm-mx8menlo.dtb \
 	imx8mm-phg.dtb \
 	imx8mq-cm.dtb \
+	imx8mn-var-som-symphony.dtb \
 	imx8mq-mnt-reform2.dtb \
 	imx8mq-phanbell.dtb \
 	imx8mp-data-modul-edm-sbc.dtb \
@@ -893,11 +916,12 @@ dtb-$(CONFIG_RZA1) += \
 	r7s72100-genmai.dtb \
 	r7s72100-gr-peach.dtb

-dtb-$(CONFIG_RCAR_GEN3) += \
-	r8a779md-geist.dtb
-
 dtb-$(CONFIG_RCAR_GEN5) += \
-	r8a78000-ironhide-cm33.dtb
+	r8a78000-ironhide.dtb
+
+ifdef CONFIG_RCAR_GEN5
+DTC_FLAGS += -R 4 -p 0x1000
+endif

 dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb

@@ -1065,7 +1089,8 @@ dtb-$(CONFIG_SOC_K3_J7200) += k3-j7200-r5-common-proc-board.dtb
 dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-r5-base-board.dtb\
 			       k3-j721s2-r5-common-proc-board.dtb

-dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-r5-aquila-dev.dtb \
+dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-aquila-dev.dtb \
+			       k3-am69-r5-aquila-dev.dtb \
 			       k3-am69-r5-sk.dtb \
 			       k3-j784s4-r5-evm.dtb

@@ -1090,9 +1115,6 @@ dtb-$(CONFIG_SOC_K3_AM62D2) += k3-am62d2-r5-evm.dtb
 dtb-$(CONFIG_SOC_K3_AM62P5) += k3-am62p5-r5-sk.dtb \
 			       k3-am62p5-verdin-r5.dtb

-mt8371-genio-520-evk-ufs-dtbs := mt8371-genio-520-evk.dtb mt8371-genio-common-ufs.dtbo
-mt8391-genio-720-evk-ufs-dtbs := mt8391-genio-720-evk.dtb mt8371-genio-common-ufs.dtbo
-
 dtb-$(CONFIG_ARCH_MEDIATEK) += \
 	mt7622-rfb.dtb \
 	mt7623a-unielec-u7623-02-emmc.dtb \
@@ -1112,10 +1134,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
 	mt7988-rfb.dtb \
 	mt7988-sd-rfb.dtb \
 	mt8183-pumpkin.dtb \
-	mt8371-genio-520-evk.dtb \
-	mt8371-genio-520-evk-ufs.dtb \
-	mt8391-genio-720-evk.dtb \
-	mt8391-genio-720-evk-ufs.dtb \
 	mt8512-bm1-emmc.dtb \
 	mt8516-pumpkin.dtb \
 	mt8518-ap1-emmc.dtb
--- a/arch/arm/dts/an7581-u-boot.dtsi
+++ b/arch/arm/dts/an7581-u-boot.dtsi
@@ -35,48 +35,6 @@
 			reg = <0x0 0x1fa20000 0x0 0x388>;
 		};

-		pon_pcs: pcs@1fa08000 {
-			compatible = "airoha,an7581-pcs-pon";
-			reg = <0x0 0x1fa08000 0x0 0x1000>,
-			      <0x0 0x1fa80000 0x0 0x60>,
-			      <0x0 0x1fa80a00 0x0 0x164>,
-			      <0x0 0x1fa84000 0x0 0x450>,
-			      <0x0 0x1fa85900 0x0 0x338>,
-			      <0x0 0x1fa86000 0x0 0x300>,
-			      <0x0 0x1fa8a000 0x0 0x1000>,
-			      <0x0 0x1fa8b000 0x0 0x1000>;
-			reg-names = "xfi_mac", "hsgmii_an", "hsgmii_pcs",
-				    "multi_sgmii", "usxgmii",
-				    "hsgmii_rate_adp", "xfi_ana", "xfi_pma";
-
-			resets = <&scuclk EN7581_XPON_MAC_RST>,
-				 <&scuclk EN7581_XPON_PHY_RST>;
-			reset-names = "mac", "phy";
-
-			airoha,scu = <&scuclk>;
-		};
-
-		eth_pcs: pcs@1fa09000 {
-			compatible = "airoha,an7581-pcs-eth";
-			reg = <0x0 0x1fa09000 0x0 0x1000>,
-			      <0x0 0x1fa70000 0x0 0x60>,
-			      <0x0 0x1fa70a00 0x0 0x164>,
-			      <0x0 0x1fa74000 0x0 0x450>,
-			      <0x0 0x1fa75900 0x0 0x338>,
-			      <0x0 0x1fa76000 0x0 0x300>,
-			      <0x0 0x1fa7a000 0x0 0x1000>,
-			      <0x0 0x1fa7b000 0x0 0x1000>;
-			reg-names = "xfi_mac", "hsgmii_an", "hsgmii_pcs",
-				    "multi_sgmii", "usxgmii",
-				    "hsgmii_rate_adp", "xfi_ana", "xfi_pma";
-
-			resets = <&scuclk EN7581_XSI_MAC_RST>,
-				 <&scuclk EN7581_XSI_PHY_RST>;
-			reset-names = "mac", "phy";
-
-			airoha,scu = <&scuclk>;
-		};
-
 		eth: ethernet@1fb50000 {
 			compatible = "airoha,en7581-eth";
 			reg = <0 0x1fb50000 0 0x2600>,
@@ -94,45 +52,11 @@
 			reset-names = "fe", "pdma", "qdma",
 				      "hsi0-mac", "hsi1-mac", "hsi-mac",
 				      "xfp-mac";
-
-			gdm1: ethernet@1 {
-				compatible = "airoha,eth-mac";
-				reg = <1>;
-				phy-mode = "internal";
-				status = "disabled";
-
-				fixed-link {
-					speed = <10000>;
-					full-duplex;
-					pause;
-				};
-			};
-
-			gdm2: ethernet@2 {
-				compatible = "airoha,eth-mac";
-				reg = <2>;
-				pcs = <&pon_pcs>;
-
-				status = "disabled";
-			};
-
-			gdm4: ethernet@4 {
-				compatible = "airoha,eth-mac";
-				reg = <4>;
-				pcs = <&eth_pcs>;
-
-				status = "disabled";
-			};
 		};

 		switch: switch@1fb58000 {
 			compatible = "airoha,en7581-switch";
 			reg = <0 0x1fb58000 0 0x8000>;
-
-			mdio: mdio {
-				#address-cells = <1>;
-				#size-cells = <0>;
-			};
 		};

 		snfi: spi@1fa10000 {
--- a/arch/arm/dts/cros-ec-sbs.dtsi
+++ b/arch/arm/dts/cros-ec-sbs.dtsi
@@ -0,0 +1,52 @@
+/*
+ * Smart battery dts fragment for devices that use cros-ec-sbs
+ *
+ * Copyright (c) 2015 Google, Inc
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+&i2c_tunnel {
+	battery: sbs-battery@b {
+		compatible = "sbs,sbs-battery";
+		reg = <0xb>;
+		sbs,i2c-retry-count = <2>;
+		sbs,poll-retry-count = <1>;
+	};
+};
--- a/arch/arm/dts/en7523-evb-u-boot.dtsi
+++ b/arch/arm/dts/en7523-evb-u-boot.dtsi
@@ -9,7 +9,3 @@
 };

 #include "en7523-u-boot.dtsi"
-
-&gdm1 {
-	status = "okay";
-};
--- a/arch/arm/dts/en7523-u-boot.dtsi
+++ b/arch/arm/dts/en7523-u-boot.dtsi
@@ -37,29 +37,11 @@
 			 <&scu EN7523_HSI_MAC_RST>;
 		reset-names = "fe", "pdma", "qdma",
 			      "hsi0-mac", "hsi1-mac", "hsi-mac";
-
-		gdm1: ethernet@1 {
-			compatible = "airoha,eth-mac";
-			reg = <1>;
-			phy-mode = "internal";
-			status = "disabled";
-
-			fixed-link {
-				speed = <10000>;
-				full-duplex;
-				pause;
-			};
-		};
 	};

 	switch: switch@1fb58000 {
 		compatible = "airoha,en7523-switch";
 		reg = <0x1fb58000 0x8000>;
-
-		mdio: mdio {
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
 	};

 	snfi: spi@1fa10000 {
--- a/arch/arm/dts/en7581-evb-u-boot.dtsi
+++ b/arch/arm/dts/en7581-evb-u-boot.dtsi
@@ -9,21 +9,3 @@
 };

 #include "an7581-u-boot.dtsi"
-
-&gdm1 {
-	status = "okay";
-};
-
-&gdm2 {
-	status = "okay";
-
-	managed = "in-band-status";
-	phy-mode = "10gbase-r";
-};
-
-&gdm4 {
-	status = "okay";
-
-	managed = "in-band-status";
-	phy-mode = "usxgmii";
-};
--- a/arch/arm/dts/exynos7870-a2corelte-u-boot.dtsi
+++ b/arch/arm/dts/exynos7870-a2corelte-u-boot.dtsi
@@ -1,26 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2026 Kaustabh Chakraborty <kauschluss@disroot.org>
- */
-
-/ {
-	/* These properties are required by S-BOOT. */
-	model_info-chip = <7870>;
-	model_info-hw_rev = <0>;
-	model_info-hw_rev_end = <255>;
-
-	chosen {
-		#address-cells = <2>;
-		#size-cells = <1>;
-		ranges;
-
-		framebuffer@67000000 {
-			compatible = "simple-framebuffer";
-			reg = <0x0 0x67000000 (540 * 960 * 4)>;
-			width = <540>;
-			height = <960>;
-			stride = <(540 * 4)>;
-			format = "a8r8g8b8";
-		};
-	};
-};
--- a/arch/arm/dts/exynos7870-j6lte-u-boot.dtsi
+++ b/arch/arm/dts/exynos7870-j6lte-u-boot.dtsi
@@ -1,46 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) Kaustabh Chakraborty <kauschluss@disroot.org>
- */
-
-/ {
-	/* These properties are required by S-BOOT. */
-	model_info-chip = <7870>;
-	model_info-hw_rev = <0>;
-	model_info-hw_rev_end = <255>;
-
-	chosen {
-		#address-cells = <2>;
-		#size-cells = <1>;
-		ranges;
-
-		framebuffer@67000000 {
-			compatible = "simple-framebuffer";
-			reg = <0x0 0x67000000 (720 * 1480 * 4)>;
-			width = <720>;
-			height = <1480>;
-			stride = <(720 * 4)>;
-			format = "a8r8g8b8";
-		};
-	};
-
-	/*
-	 * S-BOOT will populate the memory nodes stated below. Existing
-	 * values redefine the safe memory requirements as stated in upstream
-	 * device tree, in separate nodes for each bank.
-	 */
-	memory@40000000 {
-		device_type = "memory";
-		reg = <0x0 0x40000000 0x3d800000>;
-	};
-
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0x0 0x80000000 0x40000000>;
-	};
-
-	memory@100000000 {
-		device_type = "memory";
-		reg = <0x1 0x00000000 0x00000000>;
-	};
-};
--- a/arch/arm/dts/exynos7870-on7xelte-u-boot.dtsi
+++ b/arch/arm/dts/exynos7870-on7xelte-u-boot.dtsi
@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2026 Kaustabh Chakraborty <kauschluss@disroot.org>
- */
-
-/ {
-	/* These properties are required by S-BOOT. */
-	model_info-chip = <7870>;
-	model_info-hw_rev = <0>;
-	model_info-hw_rev_end = <255>;
-
-	chosen {
-		#address-cells = <2>;
-		#size-cells = <1>;
-		ranges;
-
-		framebuffer@67000000 {
-			compatible = "simple-framebuffer";
-			reg = <0x0 0x67000000 (1080 * 1920 * 4)>;
-			width = <1080>;
-			height = <1920>;
-			stride = <(1080 * 4)>;
-			format = "a8r8g8b8";
-		};
-	};
-
-	/*
-	 * S-BOOT will populate the memory nodes stated below. Existing
-	 * values redefine the safe memory requirements as stated in upstream
-	 * device tree, in separate nodes for each bank.
-	 */
-	memory@40000000 {
-		device_type = "memory";
-		reg = <0x0 0x40000000 0x3e400000>;
-	};
-
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0x0 0x80000000 0x80000000>;
-	};
-};
--- a/arch/arm/dts/fsl-ls1012a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1012a-qds.dtsi
@@ -17,7 +17,7 @@
 	bus-num = <0>;
 	status = "okay";

-	dflash0: n25q128a@0 {
+	dflash0: n25q128a {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "jedec,spi-nor";
@@ -25,7 +25,7 @@
 		spi-max-frequency = <1000000>; /* input clock */
 	};

-	dflash1: sst25wf040b@1 {
+	dflash1: sst25wf040b {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "jedec,spi-nor";
@@ -33,7 +33,7 @@
 		reg = <1>;
 	};

-	dflash2: en25s64@2 {
+	dflash2: en25s64 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "jedec,spi-nor";
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -48,7 +48,7 @@
 			clocks = <&sysclk>;
 		};

-		dspi0: spi@2100000 {
+		dspi0: dspi@2100000 {
 			compatible = "fsl,vf610-dspi";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -178,7 +178,7 @@
 			clocks = <&clockgen 4 0>;
 		};

-		qspi: spi@1550000 {
+		qspi: quadspi@1550000 {
 			compatible = "fsl,ls1021a-qspi";
 			#address-cells = <1>;
 			#size-cells = <0>;
--- a/arch/arm/dts/fsl-ls1028a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds.dtsi
@@ -26,29 +26,29 @@
 	bus-num = <0>;
 	status = "okay";

-	dflash0: sst25wf040b@0 {
+	dflash0: sst25wf040b {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
+		compatible = "spi-flash";
 		spi-max-frequency = <3000000>;
 		spi-cpol;
 		spi-cpha;
 		reg = <0>;
 	};

-	dflash1: en25s64@1 {
+	dflash1: en25s64 {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
+		compatible = "spi-flash";
 		spi-max-frequency = <3000000>;
 		spi-cpol;
 		spi-cpha;
 		reg = <1>;
 	};
-	dflash2: n25q128a@2 {
+	dflash2: n25q128a {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
+		compatible = "spi-flash";
 		spi-max-frequency = <3000000>;
 		spi-cpol;
 		spi-cpha;
@@ -60,29 +60,29 @@
 	bus-num = <0>;
 	status = "okay";

-	dflash3: sst25wf040b@0 {
+	dflash3: sst25wf040b {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
+		compatible = "spi-flash";
 		spi-max-frequency = <3000000>;
 		spi-cpol;
 		spi-cpha;
 		reg = <0>;
 	};

-	dflash4: en25s64@1 {
+	dflash4: en25s64 {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
+		compatible = "spi-flash";
 		spi-max-frequency = <3000000>;
 		spi-cpol;
 		spi-cpha;
 		reg = <1>;
 	};
-	dflash5: n25q128a@2 {
+	dflash5: n25q128a {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
+		compatible = "spi-flash";
 		spi-max-frequency = <3000000>;
 		spi-cpol;
 		spi-cpha;
@@ -94,10 +94,10 @@
 	bus-num = <0>;
 	status = "okay";

-	dflash8: en25s64@0 {
+	dflash8: en25s64 {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
+		compatible = "spi-flash";
 		spi-max-frequency = <3000000>;
 		spi-cpol;
 		spi-cpha;
--- a/arch/arm/dts/fsl-ls1043a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1043a-qds.dtsi
@@ -21,7 +21,7 @@
 	bus-num = <0>;
 	status = "okay";

-	dflash0: n25q128a@0 {
+	dflash0: n25q128a {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "jedec,spi-nor";
@@ -31,7 +31,7 @@
 		reg = <0>;
 	};

-	dflash1: sst25wf040b@1 {
+	dflash1: sst25wf040b {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "jedec,spi-nor";
@@ -41,7 +41,7 @@
 		reg = <1>;
 	};

-	dflash2: en25s64@2 {
+	dflash2: en25s64 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "jedec,spi-nor";
--- a/arch/arm/dts/fsl-ls1043a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1043a-rdb.dts
@@ -28,7 +28,7 @@
 	bus-num = <0>;
 	status = "okay";

-	dspiflash: n25q12a@0 {
+	dspiflash: n25q12a {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "jedec,spi-nor";
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -54,7 +54,7 @@
 			clocks = <&sysclk>;
 		};

-		dspi0: spi@2100000 {
+		dspi0: dspi@2100000 {
 			compatible = "fsl,vf610-dspi";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -67,7 +67,7 @@
 			status = "disabled";
 		};

-		dspi1: spi@2110000 {
+		dspi1: dspi@2110000 {
 			compatible = "fsl,vf610-dspi";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -306,7 +306,7 @@
 			clock-names = "ipg";
 			status = "disabled";
 		};
-		qspi: spi@1550000 {
+		qspi: quadspi@1550000 {
 			compatible = "fsl,ls1021a-qspi";
 			#address-cells = <1>;
 			#size-cells = <0>;
--- a/arch/arm/dts/fsl-ls1046a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1046a-qds.dtsi
@@ -21,7 +21,7 @@
 	bus-num = <0>;
 	status = "okay";

-	dflash0: n25q128a@0 {
+	dflash0: n25q128a {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "jedec,spi-nor";
@@ -31,7 +31,7 @@
 		reg = <0>;
 	};

-	dflash1: sst25wf040b@1 {
+	dflash1: sst25wf040b {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "jedec,spi-nor";
@@ -41,7 +41,7 @@
 		reg = <1>;
 	};

-	dflash2: en25s64@2 {
+	dflash2: en25s64 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "jedec,spi-nor";
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -54,7 +54,7 @@
 			clocks = <&sysclk>;
 		};

-		dspi0: spi@2100000 {
+		dspi0: dspi@2100000 {
 			compatible = "fsl,vf610-dspi";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -67,7 +67,7 @@
 			status = "disabled";
 		};

-		dspi1: spi@2110000 {
+		dspi1: dspi@2110000 {
 			compatible = "fsl,vf610-dspi";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -311,7 +311,7 @@
 			status = "disabled";
 		};

-		qspi: spi@1550000 {
+		qspi: quadspi@1550000 {
 			compatible = "fsl,ls1021a-qspi";
 			#address-cells = <1>;
 			#size-cells = <0>;
--- a/arch/arm/dts/fsl-ls1088a-qds-21-x-u-boot.dtsi
+++ b/arch/arm/dts/fsl-ls1088a-qds-21-x-u-boot.dtsi
@@ -1,9 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2024 NXP
- *
- */
-
-#include <config.h>
-
-#include "fsl-ls1088a-qds-u-boot.dtsi"
--- a/arch/arm/dts/fsl-ls1088a-qds-29-x-u-boot.dtsi
+++ b/arch/arm/dts/fsl-ls1088a-qds-29-x-u-boot.dtsi
@@ -1,9 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2024 NXP
- *
- */
-
-#include <config.h>
-
-#include "fsl-ls1088a-qds-u-boot.dtsi"
--- a/arch/arm/dts/fsl-ls1088a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1088a-qds.dtsi
@@ -144,7 +144,7 @@
 	bus-num = <0>;
 	status = "okay";

-	dflash0: n25q128a@0 {
+	dflash0: n25q128a {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "jedec,spi-nor";
@@ -152,7 +152,7 @@
 		spi-max-frequency = <1000000>; /* input clock */
 	};

-	dflash1: sst25wf040b@1 {
+	dflash1: sst25wf040b {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "jedec,spi-nor";
@@ -160,7 +160,7 @@
 		reg = <1>;
 	};

-	dflash2: en25s64@2 {
+	dflash2: en25s64 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "jedec,spi-nor";
--- a/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi
+++ b/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi
@@ -18,3 +18,11 @@
 		ethernet9 = &dpmac1;
 	};
 };
+
+&i2c0 {
+	uc: board-controller@7e {
+		compatible = "traverse,ten64-controller";
+		reg = <0x7e>;
+	};
+};
+
--- a/arch/arm/dts/fsl-ls1088a-ten64.dts
+++ b/arch/arm/dts/fsl-ls1088a-ten64.dts
@@ -0,0 +1,388 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree file for Traverse Technologies Ten64
+ * (LS1088A) board
+ * Based on fsl-ls1088a-rdb.dts
+ * Copyright 2017-2020 NXP
+ * Copyright 2019-2023 Traverse Technologies
+ *
+ * Author: Mathew McBride <matt@traverse.com.au>
+ */
+
+/dts-v1/;
+
+#include "fsl-ls1088a.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "Traverse Ten64";
+	compatible = "traverse,ten64", "fsl,ls1088a";
+
+	aliases {
+		serial0 = &duart0;
+		serial1 = &duart1;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		/* Fired by system controller when
+		 * external power off (e.g ATX Power Button)
+		 * asserted
+		 */
+		button-powerdn {
+			label = "External Power Down";
+			gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_POWER>;
+		};
+
+		/* Rear Panel 'ADMIN' button (GPIO_H) */
+		button-admin {
+			label = "ADMIN button";
+			gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
+			linux,code = <KEY_WPS_BUTTON>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-0 {
+			label = "ten64:green:sfp1:down";
+			gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-1 {
+			label = "ten64:green:sfp2:up";
+			gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-2 {
+			label = "ten64:admin";
+			gpios = <&sfpgpio 12 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	sfp_xg0: dpmac2-sfp {
+		compatible = "sff,sfp";
+		i2c-bus = <&sfplower_i2c>;
+		tx-fault-gpios = <&sfpgpio 0 GPIO_ACTIVE_HIGH>;
+		tx-disable-gpios = <&sfpgpio 1 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sfpgpio 2 GPIO_ACTIVE_LOW>;
+		los-gpios = <&sfpgpio 3 GPIO_ACTIVE_HIGH>;
+		maximum-power-milliwatt = <2000>;
+	};
+
+	sfp_xg1: dpmac1-sfp {
+		compatible = "sff,sfp";
+		i2c-bus = <&sfpupper_i2c>;
+		tx-fault-gpios = <&sfpgpio 4 GPIO_ACTIVE_HIGH>;
+		tx-disable-gpios = <&sfpgpio 5 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sfpgpio 6 GPIO_ACTIVE_LOW>;
+		los-gpios = <&sfpgpio 7 GPIO_ACTIVE_HIGH>;
+		maximum-power-milliwatt = <2000>;
+	};
+};
+
+/* XG1 - Upper SFP */
+&dpmac1 {
+	sfp = <&sfp_xg1>;
+	pcs-handle = <&pcs1>;
+	phy-connection-type = "10gbase-r";
+	managed = "in-band-status";
+};
+
+/* XG0 - Lower SFP */
+&dpmac2 {
+	sfp = <&sfp_xg0>;
+	pcs-handle = <&pcs2>;
+	phy-connection-type = "10gbase-r";
+	managed = "in-band-status";
+};
+
+/* DPMAC3..6 is GE4 to GE8 */
+&dpmac3 {
+	phy-handle = <&mdio1_phy5>;
+	phy-connection-type = "qsgmii";
+	managed = "in-band-status";
+	pcs-handle = <&pcs3_0>;
+};
+
+&dpmac4 {
+	phy-handle = <&mdio1_phy6>;
+	phy-connection-type = "qsgmii";
+	managed = "in-band-status";
+	pcs-handle = <&pcs3_1>;
+};
+
+&dpmac5 {
+	phy-handle = <&mdio1_phy7>;
+	phy-connection-type = "qsgmii";
+	managed = "in-band-status";
+	pcs-handle = <&pcs3_2>;
+};
+
+&dpmac6 {
+	phy-handle = <&mdio1_phy8>;
+	phy-connection-type = "qsgmii";
+	managed = "in-band-status";
+	pcs-handle = <&pcs3_3>;
+};
+
+/* DPMAC7..10 is GE0 to GE3 */
+&dpmac7 {
+	phy-handle = <&mdio1_phy1>;
+	phy-connection-type = "qsgmii";
+	managed = "in-band-status";
+	pcs-handle = <&pcs7_0>;
+};
+
+&dpmac8 {
+	phy-handle = <&mdio1_phy2>;
+	phy-connection-type = "qsgmii";
+	managed = "in-band-status";
+	pcs-handle = <&pcs7_1>;
+};
+
+&dpmac9 {
+	phy-handle = <&mdio1_phy3>;
+	phy-connection-type = "qsgmii";
+	managed = "in-band-status";
+	pcs-handle = <&pcs7_2>;
+};
+
+&dpmac10 {
+	phy-handle = <&mdio1_phy4>;
+	phy-connection-type = "qsgmii";
+	managed = "in-band-status";
+	pcs-handle = <&pcs7_3>;
+};
+
+&duart0 {
+	status = "okay";
+};
+
+&duart1 {
+	status = "okay";
+};
+
+&emdio1 {
+	status = "okay";
+
+	mdio1_phy5: ethernet-phy@c {
+		reg = <0xc>;
+	};
+
+	mdio1_phy6: ethernet-phy@d {
+		reg = <0xd>;
+	};
+
+	mdio1_phy7: ethernet-phy@e {
+		reg = <0xe>;
+	};
+
+	mdio1_phy8: ethernet-phy@f {
+		reg = <0xf>;
+	};
+
+	mdio1_phy1: ethernet-phy@1c {
+		reg = <0x1c>;
+	};
+
+	mdio1_phy2: ethernet-phy@1d {
+		reg = <0x1d>;
+	};
+
+	mdio1_phy3: ethernet-phy@1e {
+		reg = <0x1e>;
+	};
+
+	mdio1_phy4: ethernet-phy@1f {
+		reg = <0x1f>;
+	};
+};
+
+&esdhc {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	sfpgpio: gpio@76 {
+		compatible = "ti,tca9539";
+		reg = <0x76>;
+		#gpio-cells = <2>;
+		gpio-controller;
+
+		admin_led_lower {
+			gpio-hog;
+			gpios = <13 GPIO_ACTIVE_HIGH>;
+			output-low;
+		};
+	};
+
+	at97sc: tpm@29 {
+		compatible = "atmel,at97sc3204t";
+		reg = <0x29>;
+	};
+};
+
+&i2c2 {
+	status = "okay";
+
+	rx8035: rtc@32 {
+		compatible = "epson,rx8035";
+		reg = <0x32>;
+	};
+};
+
+&i2c3 {
+	status = "okay";
+
+	i2c-mux@70 {
+		compatible = "nxp,pca9540";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x70>;
+
+		sfpupper_i2c: i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+		};
+
+		sfplower_i2c: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+		};
+	};
+};
+
+&pcs_mdio1 {
+	status = "okay";
+};
+
+&pcs_mdio2 {
+	status = "okay";
+};
+
+&pcs_mdio3 {
+	status = "okay";
+};
+
+&pcs_mdio7 {
+	status = "okay";
+};
+
+&qspi {
+	status = "okay";
+
+	en25s64: flash@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <20000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "bl2";
+				reg = <0 0x100000>;
+			};
+
+			partition@100000 {
+				label = "bl3";
+				reg = <0x100000 0x200000>;
+			};
+
+			partition@300000 {
+				label = "mcfirmware";
+				reg = <0x300000 0x200000>;
+			};
+
+			partition@500000 {
+				label = "ubootenv";
+				reg = <0x500000 0x80000>;
+			};
+
+			partition@580000 {
+				label = "dpl";
+				reg = <0x580000 0x40000>;
+			};
+
+			partition@5C0000 {
+				label = "dpc";
+				reg = <0x5C0000 0x40000>;
+			};
+
+			partition@600000 {
+				label = "devicetree";
+				reg = <0x600000 0x40000>;
+			};
+		};
+	};
+
+	nand: flash@1 {
+		compatible = "spi-nand";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <1>;
+		spi-max-frequency = <20000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			/* reserved for future boot direct from NAND flash
+			 * (this would use the same layout as the 8MiB NOR flash)
+			 */
+			partition@0 {
+				label = "nand-boot-reserved";
+				reg = <0 0x800000>;
+			};
+
+			/* recovery / install environment */
+			partition@800000 {
+				label = "recovery";
+				reg = <0x800000 0x2000000>;
+			};
+
+			/* ubia (first OpenWrt) - a/b names to prevent confusion with ubi0/1/etc. */
+			partition@2800000 {
+				label = "ubia";
+				reg = <0x2800000 0x6C00000>;
+			};
+
+			/* ubib (second OpenWrt) */
+			partition@9400000 {
+				label = "ubib";
+				reg = <0x9400000 0x6C00000>;
+			};
+		};
+	};
+};
+
+&usb0 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};
--- a/arch/arm/dts/fsl-ls1088a-u-boot.dtsi
+++ b/arch/arm/dts/fsl-ls1088a-u-boot.dtsi
@@ -55,14 +55,9 @@

 &usb0 {
 	compatible = "fsl,layerscape-dwc3", "snps,dwc3";
-	status = "okay";
 };

 &usb1 {
 	compatible = "fsl,layerscape-dwc3", "snps,dwc3";
-	status = "okay";
 };

-&esdhc {
-	status = "okay";
-};
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -978,61 +978,51 @@
 				dpmac1: ethernet@1 {
 					compatible = "fsl,qoriq-mc-dpmac";
 					reg = <1>;
-					status = "disabled";
 				};

 				dpmac2: ethernet@2 {
 					compatible = "fsl,qoriq-mc-dpmac";
 					reg = <2>;
-					status = "disabled";
 				};

 				dpmac3: ethernet@3 {
 					compatible = "fsl,qoriq-mc-dpmac";
 					reg = <3>;
-					status = "disabled";
 				};

 				dpmac4: ethernet@4 {
 					compatible = "fsl,qoriq-mc-dpmac";
 					reg = <4>;
-					status = "disabled";
 				};

 				dpmac5: ethernet@5 {
 					compatible = "fsl,qoriq-mc-dpmac";
 					reg = <5>;
-					status = "disabled";
 				};

 				dpmac6: ethernet@6 {
 					compatible = "fsl,qoriq-mc-dpmac";
 					reg = <6>;
-					status = "disabled";
 				};

 				dpmac7: ethernet@7 {
 					compatible = "fsl,qoriq-mc-dpmac";
 					reg = <7>;
-					status = "disabled";
 				};

 				dpmac8: ethernet@8 {
 					compatible = "fsl,qoriq-mc-dpmac";
 					reg = <8>;
-					status = "disabled";
 				};

 				dpmac9: ethernet@9 {
 					compatible = "fsl,qoriq-mc-dpmac";
 					reg = <9>;
-					status = "disabled";
 				};

 				dpmac10: ethernet@a {
 					compatible = "fsl,qoriq-mc-dpmac";
 					reg = <0xa>;
-					status = "disabled";
 				};
 			};
 		};
--- a/arch/arm/dts/fsl-ls2080a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls2080a-qds.dtsi
@@ -31,7 +31,7 @@
 	bus-num = <0>;
 	status = "okay";

-	dflash0: n25q128a@0 {
+	dflash0: n25q128a {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "jedec,spi-nor";
@@ -40,7 +40,7 @@
 		spi-cpha;
 		reg = <0>;
 	};
-	dflash1: sst25wf040b@1 {
+	dflash1: sst25wf040b {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "jedec,spi-nor";
@@ -49,7 +49,7 @@
 		spi-cpha;
 		reg = <1>;
 	};
-	dflash2: en25s64@2 {
+	dflash2: en25s64 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "jedec,spi-nor";
--- a/arch/arm/dts/fsl-ls2080a-rdb.dts
+++ b/arch/arm/dts/fsl-ls2080a-rdb.dts
@@ -22,7 +22,7 @@
 	bus-num = <0>;
 	status = "okay";

-	dflash0: n25q512a@0 {
+	dflash0: n25q512a {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "jedec,spi-nor";
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -118,7 +118,7 @@
 		interrupts = <0 35 0x4>; /* Level high type */
 	};

-	dspi: spi@2100000 {
+	dspi: dspi@2100000 {
 		compatible = "fsl,vf610-dspi";
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -127,7 +127,7 @@
 		spi-num-chipselects = <6>;
 	};

-	qspi: spi@1550000 {
+	qspi: quadspi@1550000 {
 		compatible = "fsl,ls2080a-qspi";
 		#address-cells = <1>;
 		#size-cells = <0>;
--- a/arch/arm/dts/fsl-ls2081a-rdb.dts
+++ b/arch/arm/dts/fsl-ls2081a-rdb.dts
@@ -25,7 +25,7 @@
 	bus-num = <0>;
 	status = "okay";

-	dflash0: n25q512a@0 {
+	dflash0: n25q512a {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "jedec,spi-nor";
--- a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
+++ b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
@@ -113,7 +113,7 @@
 	bus-num = <0>;
 	status = "okay";

-	dflash0: n25q512a@0 {
+	dflash0: n25q512a {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "jedec,spi-nor";
--- a/arch/arm/dts/fsl-lx2160a-qds.dtsi
+++ b/arch/arm/dts/fsl-lx2160a-qds.dtsi
@@ -31,28 +31,28 @@
 	bus-num = <0>;
 	status = "okay";

-	dflash0: n25q128a@0 {
+	dflash0: n25q128a {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
+		compatible = "spi-flash";
 		spi-max-frequency = <3000000>;
 		spi-cpol;
 		spi-cpha;
 		reg = <0>;
 	};
-	dflash1: sst25wf040b@1 {
+	dflash1: sst25wf040b {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
+		compatible = "spi-flash";
 		spi-max-frequency = <3000000>;
 		spi-cpol;
 		spi-cpha;
 		reg = <1>;
 	};
-	dflash2: en25s64@2 {
+	dflash2: en25s64 {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
+		compatible = "spi-flash";
 		spi-max-frequency = <3000000>;
 		spi-cpol;
 		spi-cpha;
@@ -64,28 +64,28 @@
 	bus-num = <0>;
 	status = "okay";

-	dflash3: n25q128a@0 {
+	dflash3: n25q128a {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
+		compatible = "spi-flash";
 		spi-max-frequency = <3000000>;
 		spi-cpol;
 		spi-cpha;
 		reg = <0>;
 	};
-	dflash4: sst25wf040b@1 {
+	dflash4: sst25wf040b {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
+		compatible = "spi-flash";
 		spi-max-frequency = <3000000>;
 		spi-cpol;
 		spi-cpha;
 		reg = <1>;
 	};
-	dflash5: en25s64@2 {
+	dflash5: en25s64 {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
+		compatible = "spi-flash";
 		spi-max-frequency = <3000000>;
 		spi-cpol;
 		spi-cpha;
@@ -97,28 +97,28 @@
 	bus-num = <0>;
 	status = "okay";

-	dflash6: n25q128a@0 {
+	dflash6: n25q128a {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
+		compatible = "spi-flash";
 		spi-max-frequency = <3000000>;
 		spi-cpol;
 		spi-cpha;
 		reg = <0>;
 	};
-	dflash7: sst25wf040b@1 {
+	dflash7: sst25wf040b {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
+		compatible = "spi-flash";
 		spi-max-frequency = <3000000>;
 		spi-cpol;
 		spi-cpha;
 		reg = <1>;
 	};
-	dflash8: en25s64@2 {
+	dflash8: en25s64 {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
+		compatible = "spi-flash";
 		spi-max-frequency = <3000000>;
 		spi-cpol;
 		spi-cpha;
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -134,7 +134,7 @@
 			     <1 10 0x8>; /* Hypervisor PPI, active-low */
 	};

-	fspi: spi@20c0000 {
+	fspi: flexspi@20c0000 {
 		compatible = "nxp,lx2160a-fspi";
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -221,7 +221,7 @@
 		status = "disabled";
 	};

-	dspi0: spi@2100000 {
+	dspi0: dspi@2100000 {
 		compatible = "fsl,vf610-dspi";
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -230,7 +230,7 @@
 		spi-num-chipselects = <6>;
 	};

-	dspi1: spi@2110000 {
+	dspi1: dspi@2110000 {
 		compatible = "fsl,vf610-dspi";
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -239,7 +239,7 @@
 		spi-num-chipselects = <6>;
 	};

-	dspi2: spi@2120000 {
+	dspi2: dspi@2120000 {
 		compatible = "fsl,vf610-dspi";
 		#address-cells = <1>;
 		#size-cells = <0>;
--- a/arch/arm/dts/fsl-lx2162a-qds.dts
+++ b/arch/arm/dts/fsl-lx2162a-qds.dts
@@ -41,28 +41,28 @@
 	bus-num = <0>;
 	status = "okay";

-	dflash0: n25q128a@0 {
+	dflash0: n25q128a {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
+		compatible = "spi-flash";
 		spi-max-frequency = <3000000>;
 		spi-cpol;
 		spi-cpha;
 		reg = <0>;
 	};
-	dflash1: sst25wf040b@1 {
+	dflash1: sst25wf040b {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
+		compatible = "spi-flash";
 		spi-max-frequency = <3000000>;
 		spi-cpol;
 		spi-cpha;
 		reg = <1>;
 	};
-	dflash2: en25s64@2 {
+	dflash2: en25s64 {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
+		compatible = "spi-flash";
 		spi-max-frequency = <3000000>;
 		spi-cpol;
 		spi-cpha;
@@ -74,28 +74,28 @@
 	bus-num = <0>;
 	status = "okay";

-	dflash3: n25q128a@0 {
+	dflash3: n25q128a {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
+		compatible = "spi-flash";
 		spi-max-frequency = <3000000>;
 		spi-cpol;
 		spi-cpha;
 		reg = <0>;
 	};
-	dflash4: sst25wf040b@1 {
+	dflash4: sst25wf040b {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
+		compatible = "spi-flash";
 		spi-max-frequency = <3000000>;
 		spi-cpol;
 		spi-cpha;
 		reg = <1>;
 	};
-	dflash5: en25s64@2 {
+	dflash5: en25s64 {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
+		compatible = "spi-flash";
 		spi-max-frequency = <3000000>;
 		spi-cpol;
 		spi-cpha;
@@ -107,28 +107,28 @@
 	bus-num = <0>;
 	status = "okay";

-	dflash6: n25q128a@0 {
+	dflash6: n25q128a {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
+		compatible = "spi-flash";
 		spi-max-frequency = <3000000>;
 		spi-cpol;
 		spi-cpha;
 		reg = <0>;
 	};
-	dflash7: sst25wf040b@1 {
+	dflash7: sst25wf040b {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
+		compatible = "spi-flash";
 		spi-max-frequency = <3000000>;
 		spi-cpol;
 		spi-cpha;
 		reg = <1>;
 	};
-	dflash8: en25s64@2 {
+	dflash8: en25s64 {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
+		compatible = "spi-flash";
 		spi-max-frequency = <3000000>;
 		spi-cpol;
 		spi-cpha;
--- a/arch/arm/dts/imx23-olinuxino-u-boot.dtsi
+++ b/arch/arm/dts/imx23-olinuxino-u-boot.dtsi
@@ -1,20 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0+

-/ {
-	leds {
-		user_led: user {
-			default-state = "on";
-		};
-	};
-
-	options {
-		u-boot {
-			compatible = "u-boot,config";
-			boot-led = <&user_led>;
-		};
-	};
-};
-
 &ssp0 {
 	non-removable;
 };
--- a/arch/arm/dts/imx7d-mba7-u-boot.dtsi
+++ b/arch/arm/dts/imx7d-mba7-u-boot.dtsi
@@ -1,10 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/*
- * Device Tree Source for TQ-Systems TQMa7D board on MBa7x carrier board.
- *
- * Copyright (C) 2024-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
- * D-82229 Seefeld, Germany
- * Author: Steffen Doster
- */
-
-#include "imx7s-mba7-u-boot.dtsi"
--- a/arch/arm/dts/imx7s-mba7-u-boot.dtsi
+++ b/arch/arm/dts/imx7s-mba7-u-boot.dtsi
@@ -1,48 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/*
- * Device Tree Source for TQ-Systems TQMa7S board on MBa7x carrier board.
- *
- * Copyright (C) 2025-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
- * D-82229 Seefeld, Germany
- * Author: Steffen Doster
- */
-
-#include "imx7s-tqma7-u-boot.dtsi"
-
-/ {
-	config {
-		u-boot,mmc-env-offset = <0x100000>;
-		u-boot,mmc-env-offset-redundant = <0x110000>;
-	};
-
-	wdt-reboot {
-		compatible = "wdt-reboot";
-		wdt = <&wdog1>;
-	};
-};
-
-&gpio4 {
-	/* Deassert BOOT_EN after boot to separate BOOT_CFG circuits from LCD signals */
-	boot-en-hog {
-		gpio-hog;
-		gpios = <3 GPIO_ACTIVE_LOW>;
-		output-low;
-	};
-};
-
-&wdog1 {
-	u-boot,noautostart;
-	timeout-sec = <60>;
-};
-
-&iomuxc {
-	bootph-pre-ram;
-};
-
-&pinctrl_uart6 {
-	bootph-pre-ram;
-};
-
-&uart6 {
-	bootph-pre-ram;
-};
--- a/arch/arm/dts/imx7s-tqma7-u-boot.dtsi
+++ b/arch/arm/dts/imx7s-tqma7-u-boot.dtsi
@@ -1,22 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/*
- * Device Tree Source for TQ-Systems TQMa7S module.
- *
- * Copyright (C) 2024-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
- * D-82229 Seefeld, Germany
- * Author: Steffen Doster
- */
-
-#include "imx7s-u-boot.dtsi"
-
-&soc {
-	bootph-pre-ram;
-};
-
-&aips1 {
-	bootph-pre-ram;
-};
-
-&aips3 {
-	bootph-pre-ram;
-};
--- a/arch/arm/dts/imx8-capricorn-cxg3.dts
+++ b/arch/arm/dts/imx8-capricorn-cxg3.dts
@@ -102,26 +102,6 @@
 	pinctrl-0 = <&pinctrl_gpio_keys>;

 	muxcgrp: imx8qxp-som {
-		pinctrl_fec2: fec2grp {
-			fsl,pins = <
-				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD	0x000014a0
-				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD	0x000014a0
-				SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD		0x000514a0
-
-				SC_P_ENET0_MDC_CONN_ENET1_MDC			0x00000060
-				SC_P_ENET0_MDIO_CONN_ENET1_MDIO			0x00000060
-
-				SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN		0x00000060
-				SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0		0x00000060
-				SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1	0x00000060
-				SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER	0x00000060
-				SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL		0x00000060
-				SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0	0x00000060
-				SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1	0x00000060
-				SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL		0x00000060
-			>;
-		};
-
 		pinctrl_gpio_leds: gpioledsgrp {
 			fsl,pins = <
 			SC_P_ESAI0_FST_LSIO_GPIO0_IO01		0x06000021
@@ -147,27 +127,3 @@
 		>;
 	};
 };
-
-&fec2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_fec2>;
-	phy-mode = "rmii";
-
-	phy-handle = <&ethphy1>;
-	fsl,magic-packet;
-	status = "okay";
-
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		ethphy0: ethernet-phy@0 {
-			compatible = "ethernet-phy-ieee802.3-c22";
-			reg = <0>;
-		};
-		ethphy1: ethernet-phy@1 {
-			compatible = "ethernet-phy-ieee802.3-c22";
-			reg = <1>;
-		};
-	};
-};
--- a/arch/arm/dts/imx8-capricorn.dtsi
+++ b/arch/arm/dts/imx8-capricorn.dtsi
@@ -63,6 +63,41 @@
 				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
 				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000041
 				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
+				SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29	0x06000021
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK	0x06000041
+				SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD	0x00000021
+				SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021
+				SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021
+				SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021
+				SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021
+				SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B	0x06000021
+				//SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x06000021
+				SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30	0x06000021
+			>;
+		};
+
+		pinctrl_fec2: fec2grp {
+			fsl,pins = <
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD	0x000014a0
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD	0x000014a0
+				SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD		0x000514a0
+
+				SC_P_ENET0_MDC_CONN_ENET1_MDC                   0x00000060
+				SC_P_ENET0_MDIO_CONN_ENET1_MDIO                 0x00000060
+
+				SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN            0x00000060
+				SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0            0x00000060
+				SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1        0x00000060
+				SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER        0x00000060
+				SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL          0x00000060
+				SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0        0x00000060
+				SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1        0x00000060
+				SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL         0x00000060	/* ERST: Reset pin */
 			>;
 		};
 	};
@@ -91,7 +126,6 @@
 &usdhc1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usdhc1>;
-	max-frequency = <52000000>;
 	clock-frequency=<52000000>;
 	no-1-8-v;
 	bus-width = <8>;
@@ -126,3 +160,27 @@
 &fec1 {
 	status ="disabled";
 };
+
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec2>;
+	phy-mode = "rmii";
+
+	phy-handle = <&ethphy1>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+		};
+		ethphy1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+		};
+	};
+};
--- a/arch/arm/dts/imx8mm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-u-boot.dtsi
@@ -50,6 +50,14 @@
 	section {
 		pad-byte = <0x00>;

+#ifdef CONFIG_FSPI_CONF_HEADER
+		fspi_conf_block {
+			filename = CONFIG_FSPI_CONF_FILE;
+			type = "blob-ext";
+			size = <0x1000>;
+		};
+#endif
+
 #ifdef CONFIG_IMX_HAB
 		nxp-imx8mcst@0 {
 			filename = "u-boot-spl-mkimage.signed.bin";
@@ -60,12 +68,7 @@

 			binman_imx_spl: nxp-imx8mimage {
 				filename = "u-boot-spl-mkimage.bin";
-#ifdef CONFIG_FSPI_CONF_HEADER
-				nxp,boot-from = "fspi";
-				nxp,fspi-header-filename = CONFIG_FSPI_CONF_FILE;
-#else
 				nxp,boot-from = "sd";
-#endif
 				nxp,rom-version = <1>;
 				nxp,loader-address = <CONFIG_SPL_TEXT_BASE>;
 				args;	/* Needed by mkimage etype superclass */
--- a/arch/arm/dts/imx8mn-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-u-boot.dtsi
@@ -104,6 +104,14 @@
 	section {
 		pad-byte = <0x00>;

+#ifdef CONFIG_FSPI_CONF_HEADER
+		fspi_conf_block {
+			filename = CONFIG_FSPI_CONF_FILE;
+			type = "blob-ext";
+			offset = <0x400>;
+		};
+#endif
+
 #ifdef CONFIG_IMX_HAB
 		nxp-imx8mcst@0 {
 			filename = "u-boot-spl-mkimage.signed.bin";
@@ -114,12 +122,7 @@

 			binman_imx_spl: nxp-imx8mimage {
 				filename = "u-boot-spl-mkimage.bin";
-#ifdef CONFIG_FSPI_CONF_HEADER
-				nxp,boot-from = "fspi";
-				nxp,fspi-header-filename = CONFIG_FSPI_CONF_FILE;
-#else
 				nxp,boot-from = "sd";
-#endif
 				nxp,rom-version = <2>;
 				nxp,loader-address = <CONFIG_SPL_TEXT_BASE>;
 				args;	/* Needed by mkimage etype superclass */
--- a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
@@ -3,7 +3,52 @@
 * Copyright 2021 Collabora Ltd.
 */

-#include "imx8mn-var-som-u-boot.dtsi"
+#include "imx8mn-u-boot.dtsi"
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
+	bootph-pre-ram;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
+	bootph-pre-ram;
+};
+
+&eeprom_som {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	eth_mac_address: eth-mac-address@19 {
+		reg = <0x19 0x06>;
+	};
+};
+
+&fec1 {
+	nvmem-cells = <&eth_mac_address>;
+	nvmem-cell-names = "mac-address";
+};
+
+&gpio1 {
+	bootph-pre-ram;
+};
+
+&gpio2 {
+	bootph-pre-ram;
+};
+
+&gpio4 {
+	bootph-pre-ram;
+};
+
+&i2c1 {
+	bootph-all;
+};
+
+&pinctrl_i2c1 {
+	bootph-all;
+};
+
+&pinctrl_pmic {
+	bootph-pre-ram;
+};

 &pinctrl_reg_usdhc2_vmmc {
 	bootph-pre-ram;
@@ -17,6 +62,14 @@
 	bootph-pre-ram;
 };

+&pinctrl_usdhc3 {
+	bootph-pre-ram;
+};
+
+&pinctrl_wdog {
+	bootph-pre-ram;
+};
+
 &uart4 {
 	bootph-pre-ram;
 };
@@ -24,3 +77,11 @@
 &usdhc2 {
 	bootph-pre-ram;
 };
+
+&usdhc3 {
+	bootph-pre-ram;
+};
+
+&eeprom_som {
+	bootph-all;
+};
--- a/arch/arm/dts/imx8mn-var-som-symphony.dts
+++ b/arch/arm/dts/imx8mn-var-som-symphony.dts
@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019-2020 Variscite Ltd.
+ * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+/dts-v1/;
+
+#include "imx8mn-var-som.dtsi"
+
+/ {
+	model = "Variscite VAR-SOM-MX8MN Symphony evaluation board";
+	compatible = "variscite,var-som-mx8mn-symphony", "variscite,var-som-mx8mn", "fsl,imx8mn";
+
+	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+		regulator-name = "VSD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		key-back {
+			label = "Back";
+			gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_BACK>;
+		};
+
+		key-home {
+			label = "Home";
+			gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_HOME>;
+		};
+
+		key-menu {
+			label = "Menu";
+			gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_MENU>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led {
+			label = "Heartbeat";
+			gpios = <&pca9534 0 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+
+	pca9534: gpio@20 {
+		compatible = "nxp,pca9534";
+		reg = <0x20>;
+		gpio-controller;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pca9534>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
+		#gpio-cells = <2>;
+		wakeup-source;
+
+		/* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */
+		usb3-sata-sel-hog {
+			gpio-hog;
+			gpios = <4 GPIO_ACTIVE_HIGH>;
+			output-low;
+			line-name = "usb3_sata_sel";
+		};
+
+		som-vselect-hog {
+			gpio-hog;
+			gpios = <6 GPIO_ACTIVE_HIGH>;
+			output-low;
+			line-name = "som_vselect";
+		};
+
+		enet-sel-hog {
+			gpio-hog;
+			gpios = <7 GPIO_ACTIVE_HIGH>;
+			output-low;
+			line-name = "enet_sel";
+		};
+	};
+
+	extcon_usbotg1: typec@3d {
+		compatible = "nxp,ptn5150";
+		reg = <0x3d>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_ptn5150>;
+		status = "okay";
+	};
+};
+
+&i2c3 {
+	/* Capacitive touch controller */
+	ft5x06_ts: touchscreen@38 {
+		compatible = "edt,edt-ft5406";
+		reg = <0x38>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_captouch>;
+		interrupt-parent = <&gpio5>;
+		interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+
+		touchscreen-size-x = <800>;
+		touchscreen-size-y = <480>;
+		touchscreen-inverted-x;
+		touchscreen-inverted-y;
+	};
+
+	rtc@68 {
+		compatible = "dallas,ds1337";
+		reg = <0x68>;
+	};
+};
+
+/* Header */
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+/* Header */
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	status = "okay";
+};
+
+&usbotg1 {
+	disable-over-current;
+	extcon = <&extcon_usbotg1>, <&extcon_usbotg1>;
+};
+
+&pinctrl_fec1 {
+	fsl,pins = <
+		MX8MN_IOMUXC_ENET_MDC_ENET1_MDC			0x3
+		MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
+		MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
+		MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
+		MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
+		MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
+		MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
+		MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
+		MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
+		MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
+		MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
+		MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
+		MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
+		MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
+		/* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */
+	>;
+};
+
+&pinctrl_fec1_sleep {
+	fsl,pins = <
+		MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16		0x120
+		MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17		0x120
+		MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18		0x120
+		MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19		0x120
+		MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20		0x120
+		MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21		0x120
+		MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29		0x120
+		MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28		0x120
+		MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27		0x120
+		MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26		0x120
+		MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23		0x120
+		MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25		0x120
+		MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24		0x120
+		MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22		0x120
+		/* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */
+	>;
+};
+
+&iomuxc {
+	pinctrl_captouch: captouchgrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4		0x16
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
+			MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
+		>;
+	};
+
+	pinctrl_pca9534: pca9534grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x16
+		>;
+	};
+
+	pinctrl_ptn5150: ptn5150grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11	0x16
+		>;
+	};
+
+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22	0x41
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
+			MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
+		>;
+	};
+
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140
+			MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140
+		>;
+	};
+};
--- a/arch/arm/dts/imx8mn-var-som-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-var-som-u-boot.dtsi
@@ -1,70 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2025 Dimonoff
- */
-
-#include "imx8mn-u-boot.dtsi"
-
-/ {
-	aliases {
-		eeprom-som = &eeprom_som;
-	};
-};
-
-&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
-	bootph-pre-ram;
-};
-
-&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
-	bootph-pre-ram;
-};
-
-&eeprom_som {
-	bootph-all;
-	#address-cells = <1>;
-	#size-cells = <1>;
-	eth_mac_address: eth-mac-address@19 {
-		reg = <0x19 0x06>;
-	};
-};
-
-&fec1 {
-	nvmem-cells = <&eth_mac_address>;
-	nvmem-cell-names = "mac-address";
-};
-
-&gpio1 {
-	bootph-pre-ram;
-};
-
-&gpio2 {
-	bootph-pre-ram;
-};
-
-&gpio4 {
-	bootph-pre-ram;
-};
-
-&i2c1 {
-	bootph-all;
-};
-
-&usdhc3 {
-	bootph-pre-ram;
-};
-
-&pinctrl_i2c1 {
-	bootph-all;
-};
-
-&pinctrl_wdog {
-	bootph-pre-ram;
-};
-
-&pinctrl_pmic {
-	bootph-pre-ram;
-};
-
-&pinctrl_usdhc3 {
-	bootph-pre-ram;
-};
--- a/arch/arm/dts/imx8mn-var-som.dtsi
+++ b/arch/arm/dts/imx8mn-var-som.dtsi
@@ -0,0 +1,564 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ * Copyright 2019-2020 Variscite Ltd.
+ * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+#include "imx8mn.dtsi"
+
+/ {
+	model = "Variscite VAR-SOM-MX8MN module";
+	compatible = "variscite,var-som-mx8mn", "fsl,imx8mn";
+
+	aliases {
+		eeprom-som = &eeprom_som;
+	};
+
+	chosen {
+		stdout-path = &uart4;
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x0 0x40000000 0 0x40000000>;
+	};
+
+	reg_eth_phy: regulator-eth-phy {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_eth_phy>;
+		regulator-name = "eth_phy_pwr";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+&A53_0 {
+	cpu-supply = <&buck2_reg>;
+};
+
+&A53_1 {
+	cpu-supply = <&buck2_reg>;
+};
+
+&A53_2 {
+	cpu-supply = <&buck2_reg>;
+};
+
+&A53_3 {
+	cpu-supply = <&buck2_reg>;
+};
+
+&ecspi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1>;
+	cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>,
+		   <&gpio1  0 GPIO_ACTIVE_LOW>;
+	/delete-property/ dmas;
+	/delete-property/ dma-names;
+	status = "okay";
+
+	/* Resistive touch controller */
+	touchscreen@0 {
+		reg = <0>;
+		compatible = "ti,ads7846";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_restouch>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+
+		spi-max-frequency = <1500000>;
+		pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+
+		ti,x-min = /bits/ 16 <125>;
+		touchscreen-size-x = <4008>;
+		ti,y-min = /bits/ 16 <282>;
+		touchscreen-size-y = <3864>;
+		ti,x-plate-ohms = /bits/ 16 <180>;
+		touchscreen-max-pressure = <255>;
+		touchscreen-average-samples = <10>;
+		ti,debounce-tol = /bits/ 16 <3>;
+		ti,debounce-rep = /bits/ 16 <1>;
+		ti,settle-delay-usec = /bits/ 16 <150>;
+		ti,keep-vref-on;
+		wakeup-source;
+	};
+};
+
+&fec1 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_fec1>;
+	pinctrl-1 = <&pinctrl_fec1_sleep>;
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy>;
+	phy-supply = <&reg_eth_phy>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy: ethernet-phy@4 { /* AR8033 or ADIN1300 */
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <4>;
+			reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <10000>;
+			/*
+			 * Deassert delay:
+			 * ADIN1300 requires 5ms.
+			 * AR8033   requires 1ms.
+			 */
+			reset-deassert-us = <20000>;
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+
+	pmic@4b {
+		compatible = "rohm,bd71847";
+		reg = <0x4b>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pmic>;
+		interrupt-parent = <&gpio2>;
+		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+		rohm,reset-snvs-powered;
+
+		regulators {
+			buck1_reg: BUCK1 {
+				regulator-name = "buck1";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <1250>;
+			};
+
+			buck2_reg: BUCK2 {
+				regulator-name = "buck2";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <1250>;
+				rohm,dvs-run-voltage = <1000000>;
+				rohm,dvs-idle-voltage = <900000>;
+			};
+
+			buck3_reg: BUCK3 {
+				regulator-name = "buck3";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck4_reg: BUCK4 {
+				regulator-name = "buck4";
+				regulator-min-microvolt = <2600000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck5_reg: BUCK5 {
+				regulator-name = "buck5";
+				regulator-min-microvolt = <1605000>;
+				regulator-max-microvolt = <1995000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck6_reg: BUCK6 {
+				regulator-name = "buck6";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1_reg: LDO1 {
+				regulator-name = "ldo1";
+				regulator-min-microvolt = <1600000>;
+				regulator-max-microvolt = <1900000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo2_reg: LDO2 {
+				regulator-name = "ldo2";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <900000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo3_reg: LDO3 {
+				regulator-name = "ldo3";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4_reg: LDO4 {
+				regulator-name = "ldo4";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+
+			ldo5_reg: LDO5 {
+				regulator-compatible = "ldo5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+
+			ldo6_reg: LDO6 {
+				regulator-name = "ldo6";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+
+	eeprom_som: eeprom@52 {
+		compatible = "atmel,24c04";
+		reg = <0x52>;
+		pagesize = <16>;
+	};
+};
+
+&i2c3 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+
+	/* TODO: configure audio, as of now just put a placeholder */
+	wm8904: codec@1a {
+		compatible = "wlf,wm8904";
+		reg = <0x1a>;
+		status = "disabled";
+	};
+};
+
+&snvs_pwrkey {
+	status = "okay";
+};
+
+/* Bluetooth */
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	assigned-clocks = <&clk IMX8MN_CLK_UART2>;
+	assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
+	uart-has-rtscts;
+	status = "okay";
+};
+
+/* Console */
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4>;
+	status = "okay";
+};
+
+&usbotg1 {
+	dr_mode = "otg";
+	usb-role-switch;
+	status = "okay";
+};
+
+/* WIFI */
+&usdhc1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	bus-width = <4>;
+	non-removable;
+	keep-power-in-suspend;
+	status = "okay";
+
+	brcmf: bcrmf@1 {
+		reg = <1>;
+		compatible = "brcm,bcm4329-fmac";
+	};
+};
+
+/* SD */
+&usdhc2 {
+	assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
+	assigned-clock-rates = <200000000>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+	bus-width = <4>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+	assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
+	assigned-clock-rates = <400000000>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_ecspi1: ecspi1grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x13
+			MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x13
+			MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x13
+			MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14		0x13
+			MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x13
+		>;
+	};
+
+	pinctrl_fec1: fec1grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_ENET_MDC_ENET1_MDC			0x3
+			MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
+			MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
+			MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
+			MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
+			MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
+			MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
+			MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
+			MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
+			MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
+			MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
+			MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
+			MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
+			MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
+			MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
+		>;
+	};
+
+	pinctrl_fec1_sleep: fec1sleepgrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16		0x120
+			MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17		0x120
+			MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18		0x120
+			MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19		0x120
+			MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20		0x120
+			MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21		0x120
+			MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29		0x120
+			MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28		0x120
+			MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27		0x120
+			MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26		0x120
+			MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23		0x120
+			MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25		0x120
+			MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24		0x120
+			MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22		0x120
+			MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x120
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
+			MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
+			MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
+		>;
+	};
+
+	pinctrl_pmic: pmicirqgrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8	0x141
+		>;
+	};
+
+	pinctrl_reg_eth_phy: regethphygrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9	0x41
+		>;
+	};
+
+	pinctrl_restouch: restouchgrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x1c0
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX	0x140
+			MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX	0x140
+			MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B	0x140
+			MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B	0x140
+		>;
+	};
+
+	pinctrl_uart4: uart4grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140
+			MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
+			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
+			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
+			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
+			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
+			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
+		>;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK		0x194
+			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4
+			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4
+			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4
+			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4
+			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4
+		>;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK		0x196
+			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6
+			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6
+			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6
+			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6
+			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6
+		>;
+	};
+
+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10	0x41
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
+			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
+			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
+			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
+			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
+			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
+			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+		>;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
+			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
+			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
+			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
+			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
+			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
+			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
+			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
+			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
+			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
+			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
+			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
+			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190
+			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0
+			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0
+			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0
+			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0
+			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0
+			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0
+			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0
+			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0
+			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0
+			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190
+		>;
+	};
+
+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194
+			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4
+			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4
+			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4
+			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4
+			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4
+			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4
+			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4
+			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4
+			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4
+			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194
+		>;
+	};
+
+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196
+			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6
+			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6
+			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6
+			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6
+			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6
+			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6
+			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6
+			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6
+			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6
+			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196
+		>;
+	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0x166
+		>;
+	};
+};
--- a/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi
@@ -22,18 +22,6 @@
 	bootph-pre-ram;
 };

-&pca9450 {
-	bootph-all;
-};
-
-&pinctrl_i2c1 {
-	bootph-all;
-};
-
-&pinctrl_pmic {
-	bootph-all;
-};
-
 &pinctrl_uart2 {
 	bootph-pre-ram;
 };
@@ -75,7 +63,7 @@
 };

 &i2c1 {
-	bootph-all;
+	bootph-pre-ram;
 };

 &i2c2 {
@@ -130,7 +118,3 @@
 	phy-reset-duration = <15>;
 	phy-reset-post-delay = <100>;
 };
-
-&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
-	bootph-all;
-};
--- a/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi
@@ -33,18 +33,6 @@
 	};
 };

-&pinctrl_i2c1 {
-	bootph-all;
-};
-
-&pinctrl_pmic {
-	bootph-all;
-};
-
-&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
-	bootph-all;
-};
-
 &reg_usdhc2_vmmc {
 	bootph-pre-ram;
 };
@@ -90,11 +78,11 @@
 };

 &i2c1 {
-	bootph-all;
+	bootph-pre-ram;
 };

 &pmic {
-	bootph-all;
+	bootph-pre-ram;
 };

 /* USB1 Type-C */
@@ -132,12 +120,6 @@

 &usdhc2 {
 	bootph-pre-ram;
-	/*
-	 * LDO5 output depends on SD2_VSEL, but no way to read back SD2_VSEL
-	 * when using SDHC controller VSELECT to control SD2_VSEL. So drop
-	 * vqmmc-supply to avoid fsl_esdhc_imx read back wrong voltage.
-	 */
-	 /delete-property/ vqmmc-supply;
 };

 &usdhc3 {
--- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
@@ -34,18 +34,6 @@
 	};
 };

-&pinctrl_i2c1 {
-	bootph-all;
-};
-
-&pinctrl_pmic {
-	bootph-all;
-};
-
-&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
-	bootph-all;
-};
-
 &reg_usdhc2_vmmc {
 	bootph-pre-ram;
 };
@@ -95,11 +83,11 @@
 };

 &i2c1 {
-	bootph-all;
+	bootph-pre-ram;
 };

 &pmic {
-	bootph-all;
+	bootph-pre-ram;
 };

 &usb_dwc3_0 {
@@ -108,12 +96,6 @@

 &usdhc2 {
 	bootph-pre-ram;
-	/*
-	 * LDO5 output depends on SD2_VSEL, but no way to read back SD2_VSEL
-	 * when using SDHC controller VSELECT to control SD2_VSEL. So drop
-	 * vqmmc-supply to avoid fsl_esdhc_imx read back wrong voltage.
-	 */
-	/delete-property/ vqmmc-supply;
 };

 &usdhc3 {
--- a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi
@@ -70,7 +70,7 @@
 };

 &i2c1 {
-	bootph-all;
+	bootph-pre-ram;

 	eeprom_module: eeprom@50 {
 		compatible = "i2c-eeprom";
@@ -104,7 +104,7 @@
 };

 &pca9450 {
-	bootph-all;
+	bootph-pre-ram;
 };

 &pinctrl_ctrl_sleep_moci {
@@ -112,11 +112,7 @@
 };

 &pinctrl_i2c1 {
-	bootph-all;
-};
-
-&pinctrl_pmic {
-	bootph-all;
+	bootph-pre-ram;
 };

 &pinctrl_usdhc2_pwr_en {
@@ -163,12 +159,6 @@
 	sd-uhs-ddr50;
 	sd-uhs-sdr104;
 	bootph-pre-ram;
-	/*
-	 * LDO5 output depends on SD2_VSEL, but no way to read back SD2_VSEL
-	 * when using SDHC controller VSELECT to control SD2_VSEL. So drop
-	 * vqmmc-supply to avoid fsl_esdhc_imx read back wrong voltage.
-	 */
-	 /delete-property/ vqmmc-supply;
 };

 &usdhc3 {
@@ -183,7 +173,3 @@
 &wdog1 {
 	bootph-pre-ram;
 };
-
-&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
-	bootph-all;
-};
--- a/arch/arm/dts/imx8mq-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi
@@ -2,105 +2,19 @@

 #include "imx8mq-u-boot.dtsi"

-&aips1 {
-	bootph-all;
-};
-
-&gpio2 {
-	bootph-pre-ram;
-};
-
-&pinctrl_i2c1 {
-	bootph-all;
-};
-
-&i2c1 {
-	bootph-all;
-};
-
-&soc {
-	bootph-all;
-	bootph-pre-ram;
-};
-
-&{/soc@0/bus@30800000/i2c@30a20000/pmic@8} {
-	bootph-all;
-};
-
-&{/soc@0/bus@30800000/i2c@30a20000/pmic@8/regulators} {
-	bootph-all;
-};
-
 &pinctrl_uart1 {
 	bootph-pre-ram;
 };

-&uart1 {
-	bootph-pre-ram;
-};
-
 &usdhc1 {
-	bootph-pre-ram;
 	mmc-hs400-1_8v;
-	/delete-property/ vqmmc-supply;
-};
-
-&pinctrl_usdhc1 {
-	bootph-pre-ram;
-};
-
-&pinctrl_usdhc1_100mhz {
-	bootph-pre-ram;
-};
-
-&pinctrl_usdhc1_200mhz {
-	bootph-pre-ram;
 };

 &usdhc2 {
-	bootph-pre-ram;
 	sd-uhs-sdr104;
 	sd-uhs-ddr50;
 };

-&pinctrl_usdhc2 {
+&uart1 {
 	bootph-pre-ram;
 };
-
-&pinctrl_usdhc2_100mhz {
-	bootph-pre-ram;
-};
-
-&pinctrl_usdhc2_200mhz {
-	bootph-pre-ram;
-};
-
-&pinctrl_usdhc2_gpio {
-	bootph-pre-ram;
-};
-
-&pinctrl_reg_usdhc2 {
-	bootph-pre-ram;
-};
-
-&reg_usdhc2_vmmc {
-	bootph-pre-ram;
-};
-
-#ifdef CONFIG_FSL_CAAM
-&crypto {
-	bootph-pre-ram;
-};
-
-&sec_jr0 {
-	bootph-pre-ram;
-};
-
-&sec_jr1 {
-	bootph-pre-ram;
-};
-
-&sec_jr2 {
-	bootph-pre-ram;
-};
-#endif
--- a/arch/arm/dts/imx8mq-kontron-pitx-imx8m-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-kontron-pitx-imx8m-u-boot.dtsi
@@ -2,90 +2,26 @@

 #include "imx8mq-u-boot.dtsi"

-&aips1 {
-	bootph-all;
-};
-
-&gpio2 {
-	bootph-pre-ram;
-};
-
-&pinctrl_i2c1 {
-	bootph-all;
-};
-
-&i2c1 {
-	bootph-all;
-};
-
-&soc {
-	bootph-all;
-	bootph-pre-ram;
-};
-
-&{/soc@0/bus@30800000/i2c@30a20000/pmic@8} {
-	bootph-all;
-};
-
-&{/soc@0/bus@30800000/i2c@30a20000/pmic@8/regulators} {
-	bootph-all;
-};
-
-&pinctrl_uart1 {
-	bootph-pre-ram;
-};
-
-&uart1 {
-	bootph-pre-ram;
-};
-
 &usdhc1 {
-	bootph-pre-ram;
 	mmc-hs400-1_8v;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc1>;
-};
-
-&pinctrl_usdhc1 {
-	bootph-pre-ram;
 };

 &usdhc2 {
-	bootph-pre-ram;
 	sd-uhs-sdr104;
 	sd-uhs-ddr50;
 };

-&pinctrl_usdhc2 {
-	bootph-pre-ram;
-};
-
-&pinctrl_usdhc2_gpio {
-	bootph-pre-ram;
-};
-
-&pinctrl_reg_usdhc2 {
-	bootph-pre-ram;
-};
-
-&reg_usdhc2_vmmc {
-	bootph-pre-ram;
-};
-
 &uart1 {
-	bootph-pre-ram;
 	/delete-property/ assigned-clocks;
 	/delete-property/ assigned-clock-parents;
 };

 &uart2 {
-	bootph-pre-ram;
 	/delete-property/ assigned-clocks;
 	/delete-property/ assigned-clock-parents;
 };

 &uart3 {
-	bootph-pre-ram;
 	/delete-property/ assigned-clocks;
 	/delete-property/ assigned-clock-parents;
 };
--- a/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
@@ -10,7 +10,7 @@
 	bootph-pre-ram;
 };

-&binman {
+&binman_imx_spl {
 	section {
 		signed-hdmi-imx8m {
 			filename = "signed_dp_imx8m.bin";
--- a/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi
@@ -2,12 +2,7 @@

 #include "imx8mq-u-boot.dtsi"

-&gpio2 {
-	bootph-pre-ram;
-};
-
 &reg_usdhc2_vmmc {
-	bootph-pre-ram;
 	u-boot,off-on-delay-us = <20000>;
 };

@@ -18,39 +13,3 @@
 &pinctrl_uart1 {
 	bootph-pre-ram;
 };
-
-&usdhc1 {
-	bootph-pre-ram;
-};
-
-&pinctrl_usdhc1 {
-	bootph-pre-ram;
-};
-
-&pinctrl_usdhc1_100mhz {
-	bootph-pre-ram;
-};
-
-&pinctrl_usdhc1_200mhz {
-	bootph-pre-ram;
-};
-
-&usdhc2 {
-	bootph-pre-ram;
-};
-
-&pinctrl_usdhc2 {
-	bootph-pre-ram;
-};
-
-&pinctrl_usdhc2_100mhz {
-	bootph-pre-ram;
-};
-
-&pinctrl_usdhc2_200mhz {
-	bootph-pre-ram;
-};
-
-&pinctrl_usdhc2_gpio {
-	bootph-pre-ram;
-};
--- a/arch/arm/dts/imx8mq-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-u-boot.dtsi
@@ -41,33 +41,6 @@
 	filename = "flash.bin";
 	section {
 		pad-byte = <0x00>;
-		/*
-		 * signed_hdmi_imx8m.bin contains a 1KB zero-filled padding at
-		 * its beginning. This padding has no functional purpose, but
-		 * the firmware is provided and signed by NXP, so the head
-		 * must be preserved and should not be removed.
-		 *
-		 * When the signed HDMI firmware is placed at the beginning of
-		 * flash.bin, the IVT header of u-boot-spl must still reside at
-		 * a 4KB-aligned address. Since flash.bin starts with the HDMI
-		 * firmware (including its 1KB padding), there is already a 1KB
-		 * empty region at the head of flash.bin.
-		 *
-		 * The required 4KB alignment is therefore calculated relative
-		 * to the location after this 1KB padding. To achieve this, we
-		 * explicitly set align and align-size to 0x1000, and add an
-		 * additional 0x400 (1KB) fill to account for the padding.
-		 */
-		signed-hdmi-imx8m {
-			filename = "signed_hdmi_imx8m.bin";
-			type = "blob-ext";
-			align = <0x1000>;
-			align-size = <0x1000>;
-		};
-
-		fill {
-			size = <0x400>;
-		};

 #ifdef CONFIG_IMX_HAB
 		nxp-imx8mcst@0 {
@@ -78,142 +51,145 @@
 #endif

 			binman_imx_spl: nxp-imx8mimage {
-			filename = "u-boot-spl-mkimage.bin";
-			nxp,boot-from = "sd";
-			nxp,rom-version = <1>;
-			nxp,loader-address = <CONFIG_SPL_TEXT_BASE>;
-			args;	/* Needed by mkimage etype superclass */
+				filename = "u-boot-spl-mkimage.bin";
+				nxp,boot-from = "sd";
+				nxp,rom-version = <1>;
+				nxp,loader-address = <CONFIG_SPL_TEXT_BASE>;
+				args;	/* Needed by mkimage etype superclass */

-			section {
-				align = <4>;
-				align-size = <4>;
-				filename = "u-boot-spl-ddr.bin";
-				pad-byte = <0xff>;
+				section {
+					align = <4>;
+					align-size = <4>;
+					filename = "u-boot-spl-ddr.bin";
+					pad-byte = <0xff>;

-				u-boot-spl {
-					align-end = <4>;
-					filename = "u-boot-spl.bin";
-				};
+					u-boot-spl {
+						align-end = <4>;
+						filename = "u-boot-spl.bin";
+					};

-				ddr-1d-imem-fw {
-					filename = "lpddr4_pmu_train_1d_imem.bin";
-					align-end = <4>;
-					type = "blob-ext";
-				};
+					ddr-1d-imem-fw {
+						filename = "lpddr4_pmu_train_1d_imem.bin";
+						align-end = <4>;
+						type = "blob-ext";
+					};

-				ddr-1d-dmem-fw {
-					filename = "lpddr4_pmu_train_1d_dmem.bin";
-					align-end = <4>;
-					type = "blob-ext";
-				};
+					ddr-1d-dmem-fw {
+						filename = "lpddr4_pmu_train_1d_dmem.bin";
+						align-end = <4>;
+						type = "blob-ext";
+					};

-				ddr-2d-imem-fw {
-					filename = "lpddr4_pmu_train_2d_imem.bin";
-					align-end = <4>;
-					type = "blob-ext";
-				};
+					ddr-2d-imem-fw {
+						filename = "lpddr4_pmu_train_2d_imem.bin";
+						align-end = <4>;
+						type = "blob-ext";
+					};

-				ddr-2d-dmem-fw {
-					filename = "lpddr4_pmu_train_2d_dmem.bin";
-					align-end = <4>;
-					type = "blob-ext";
+					ddr-2d-dmem-fw {
+						filename = "lpddr4_pmu_train_2d_dmem.bin";
+						align-end = <4>;
+						type = "blob-ext";
+					};
+
+					signed-hdmi-imx8m {
+						filename = "signed_hdmi_imx8m.bin";
+						type = "blob-ext";
+					};
 				};
 			};
-		};
 #ifdef CONFIG_IMX_HAB
 		};
-#endif
-	};
-
-#ifdef CONFIG_IMX_HAB
-	nxp-imx8mcst@1 {
-		filename = "u-boot-fit.signed.bin";
-		nxp,loader-address = <CONFIG_SPL_LOAD_FIT_ADDRESS>;
-		offset = <0x58400>;
-		args;	/* Needed by mkimage etype superclass */
-#endif
-
-		binman_imx_fit: fit {
-			description = "Configuration to load ATF before U-Boot";
-			filename = "u-boot.itb";
-#ifndef CONFIG_IMX_HAB
-			fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
-#endif
-			#address-cells = <1>;

+		nxp-imx8mcst@1 {
+			filename = "u-boot-fit.signed.bin";
+			nxp,loader-address = <CONFIG_SPL_LOAD_FIT_ADDRESS>;
 			offset = <0x58000>;
-
-			images {
-				uboot {
-					arch = "arm64";
-					compression = "none";
-					description = "U-Boot (64-bit)";
-					load = <CONFIG_TEXT_BASE>;
-					type = "standalone";
-
-					uboot-blob {
-						filename = "u-boot-nodtb.bin";
-						type = "blob-ext";
-					};
-				};
-
-#ifndef CONFIG_ARMV8_PSCI
-				atf {
-					arch = "arm64";
-					compression = "none";
-					description = "ARM Trusted Firmware";
-					entry = <0x910000>;
-					load = <0x910000>;
-					type = "firmware";
-
-					atf-blob {
-						filename = "bl31.bin";
-						type = "blob-ext";
-					};
-				};
+			args;	/* Needed by mkimage etype superclass */
 #endif

-				tee: tee {
-					description = "OP-TEE";
-					type = "tee";
-					arch = "arm64";
-					compression = "none";
-					os = "tee";
-					load = <CONFIG_IMX8M_OPTEE_LOAD_ADDR>;
-					entry = <CONFIG_IMX8M_OPTEE_LOAD_ADDR>;
+			binman_imx_fit: fit {
+				description = "Configuration to load ATF before U-Boot";
+				filename = "u-boot.itb";
+#ifndef CONFIG_IMX_HAB
+				fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+#endif
+				#address-cells = <1>;

-					tee-os {
-						filename = "tee.bin";
-						optional;
+				offset = <0x57c00>;
+
+				images {
+					uboot {
+						arch = "arm64";
+						compression = "none";
+						description = "U-Boot (64-bit)";
+						load = <CONFIG_TEXT_BASE>;
+						type = "standalone";
+
+						uboot-blob {
+							filename = "u-boot-nodtb.bin";
+							type = "blob-ext";
+						};
+					};
+
+#ifndef CONFIG_ARMV8_PSCI
+					atf {
+						arch = "arm64";
+						compression = "none";
+						description = "ARM Trusted Firmware";
+						entry = <0x910000>;
+						load = <0x910000>;
+						type = "firmware";
+
+						atf-blob {
+							filename = "bl31.bin";
+							type = "blob-ext";
+						};
+					};
+#endif
+
+					tee: tee {
+						description = "OP-TEE";
+						type = "tee";
+						arch = "arm64";
+						compression = "none";
+						os = "tee";
+						load = <CONFIG_IMX8M_OPTEE_LOAD_ADDR>;
+						entry = <CONFIG_IMX8M_OPTEE_LOAD_ADDR>;
+
+						tee-os {
+							filename = "tee.bin";
+							optional;
+						};
+					};
+
+					fdt {
+						compression = "none";
+						description = "NAME";
+						type = "flat_dt";
+
+						uboot-fdt-blob {
+							filename = "u-boot.dtb";
+							type = "blob-ext";
+						};
 					};
 				};

-				fdt {
-					compression = "none";
-					description = "NAME";
-					type = "flat_dt";
+				configurations {
+					default = "conf";

-					uboot-fdt-blob {
-						filename = "u-boot.dtb";
-						type = "blob-ext";
+					conf {
+						description = "NAME";
+						fdt = "fdt";
+						firmware = "uboot";
+#ifndef CONFIG_ARMV8_PSCI
+						loadables = "atf", "tee";
+#endif
 					};
 				};
 			};
-
-			configurations {
-				default = "conf";
-
-				conf {
-					description = "NAME";
-					fdt = "fdt";
-					firmware = "uboot";
-#ifndef CONFIG_ARMV8_PSCI
-					loadables = "atf", "tee";
-#endif
-				};
-			};
-		};
 #ifdef CONFIG_IMX_HAB
-	};
+		};
 #endif
+	};
 };
--- a/arch/arm/dts/imx91-93-phyboard-segin-common-u-boot.dtsi
+++ b/arch/arm/dts/imx91-93-phyboard-segin-common-u-boot.dtsi
@@ -1,228 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2026 PHYTEC Messtechnik GmbH
- * Author: Primoz Fiser <primoz.fiser@norik.com>
- *
- */
-
-/ {
-	wdt-reboot {
-		compatible = "wdt-reboot";
-		wdt = <&wdog3>;
-		bootph-pre-ram;
-		bootph-some-ram;
-	};
-
-	aliases {
-		ethernet0 = &fec;
-		ethernet1 = &eqos;
-	};
-
-	bootstd {
-		bootph-verify;
-		compatible = "u-boot,boot-std";
-
-		filename-prefixes = "/", "/boot/";
-		bootdev-order = "mmc0", "mmc1", "ethernet";
-
-		rauc {
-			compatible = "u-boot,distro-rauc";
-		};
-
-		script {
-			compatible = "u-boot,script";
-		};
-	};
-
-	firmware {
-		optee {
-			compatible = "linaro,optee-tz";
-			method = "smc";
-		};
-	};
-};
-
-&{/soc@0} {
-	bootph-all;
-	bootph-pre-ram;
-};
-
-&aips1 {
-	bootph-pre-ram;
-	bootph-all;
-};
-
-&aips2 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&aips3 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&iomuxc {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&reg_usdhc2_vmmc {
-	u-boot,off-on-delay-us = <20000>;
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_lpi2c3 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_pmic {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_reg_usdhc2_vmmc {
-	bootph-pre-ram;
-};
-
-&pinctrl_uart1 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_usdhc1 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_usdhc1_100mhz {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_usdhc1_200mhz {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_usdhc2_cd {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_usdhc2_default {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_usdhc2_100mhz {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_usdhc2_200mhz {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&gpio1 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&gpio2 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&gpio3 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&gpio4 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&lpuart1 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&usdhc1 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&usdhc2 {
-	bootph-pre-ram;
-	bootph-some-ram;
-	fsl,signal-voltage-switch-extra-delay-ms = <8>;
-};
-
-&lpi2c1 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&lpi2c2 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&lpi2c3 {
-	bootph-pre-ram;
-	bootph-some-ram;
-
-	pmic@25 {
-		bootph-pre-ram;
-		bootph-some-ram;
-
-		regulators {
-			bootph-pre-ram;
-			bootph-some-ram;
-		};
-	};
-
-	eeprom@50 {
-		bootph-pre-ram;
-		bootph-some-ram;
-	};
-};
-
-&s4muap {
-	bootph-pre-ram;
-	bootph-some-ram;
-	status = "okay";
-};
-
-&clk {
-	bootph-all;
-	bootph-pre-ram;
-	/delete-property/ assigned-clocks;
-	/delete-property/ assigned-clock-rates;
-	/delete-property/ assigned-clock-parents;
-};
-
-&osc_32k {
-	bootph-all;
-	bootph-pre-ram;
-};
-
-&osc_24m {
-	bootph-all;
-	bootph-pre-ram;
-};
-
-&clk_ext1 {
-	bootph-all;
-	bootph-pre-ram;
-};
-
-&wdog3 {
-	bootph-all;
-	bootph-pre-ram;
-};
--- a/arch/arm/dts/imx91-phyboard-segin-u-boot.dtsi
+++ b/arch/arm/dts/imx91-phyboard-segin-u-boot.dtsi
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2026 PHYTEC Messtechnik GmbH
- * Author: Primoz Fiser <primoz.fiser@norik.com>
- *
- */
-
-#include "imx91-u-boot.dtsi"
-#include "imx91-93-phyboard-segin-common-u-boot.dtsi"
-
-/ {
-	/*
-	 * The phyCORE-i.MX91 u-boot uses the imx91-phyboard-segin.dts as
-	 * reference, but does only make use of its SoM (phyCORE) contained
-	 * periphery.
-	 */
-	model = "PHYTEC phyCORE-i.MX91";
-};
--- a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
+++ b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
@@ -9,7 +9,6 @@
 */

 #include "imx93-u-boot.dtsi"
-#include "imx91-93-phyboard-segin-common-u-boot.dtsi"

 / {
 	/*
@@ -18,4 +17,224 @@
 	 * periphery.
 	 */
 	model = "PHYTEC phyCORE-i.MX93";
+
+	wdt-reboot {
+		compatible = "wdt-reboot";
+		wdt = <&wdog3>;
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+
+	aliases {
+		ethernet0 = &fec;
+		ethernet1 = &eqos;
+	};
+
+	bootstd {
+		bootph-verify;
+		compatible = "u-boot,boot-std";
+
+		filename-prefixes = "/", "/boot/";
+		bootdev-order = "mmc0", "mmc1", "ethernet";
+
+		rauc {
+			compatible = "u-boot,distro-rauc";
+		};
+
+		script {
+			compatible = "u-boot,script";
+		};
+	};
+
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
+};
+
+&{/soc@0} {
+	bootph-all;
+	bootph-pre-ram;
+};
+
+&aips1 {
+	bootph-pre-ram;
+	bootph-all;
+};
+
+&aips2 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&aips3 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&iomuxc {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&reg_usdhc2_vmmc {
+	u-boot,off-on-delay-us = <20000>;
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_lpi2c3 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_pmic {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_reg_usdhc2_vmmc {
+	bootph-pre-ram;
+};
+
+&pinctrl_uart1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc1_100mhz {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc1_200mhz {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc2_cd {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc2_default {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc2_100mhz {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc2_200mhz {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&gpio1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&gpio2 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&gpio3 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&gpio4 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&lpuart1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&usdhc1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&usdhc2 {
+	bootph-pre-ram;
+	bootph-some-ram;
+	fsl,signal-voltage-switch-extra-delay-ms = <8>;
+};
+
+&lpi2c1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&lpi2c2 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&lpi2c3 {
+	bootph-pre-ram;
+	bootph-some-ram;
+
+	pmic@25 {
+		bootph-pre-ram;
+		bootph-some-ram;
+
+		regulators {
+			bootph-pre-ram;
+			bootph-some-ram;
+		};
+	};
+
+	eeprom@50 {
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+};
+
+&s4muap {
+	bootph-pre-ram;
+	bootph-some-ram;
+	status = "okay";
+};
+
+&clk {
+	bootph-all;
+	bootph-pre-ram;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-rates;
+	/delete-property/ assigned-clock-parents;
+};
+
+&osc_32k {
+	bootph-all;
+	bootph-pre-ram;
+};
+
+&osc_24m {
+	bootph-all;
+	bootph-pre-ram;
+};
+
+&clk_ext1 {
+	bootph-all;
+	bootph-pre-ram;
+};
+
+&wdog3 {
+	bootph-all;
+	bootph-pre-ram;
 };
--- a/arch/arm/dts/imx943-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx943-evk-u-boot.dtsi
@@ -157,24 +157,6 @@
 	status = "disabled";
 };

-&xspi1 {
-	bootph-pre-ram;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_xspi1>;
-	status = "okay";
-
-	mt35xu512aba: flash@0 {
-		bootph-pre-ram;
-		reg = <0>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <200000000>;
-		spi-tx-bus-width = <8>;
-		spi-rx-bus-width = <8>;
-	};
-};
-
 &scmi_iomuxc {
 	pinctrl_emdio: emdiogrp {
 		fsl,pins = <
@@ -223,22 +205,6 @@
 			IMX94_PAD_GPIO_IO17__LPI2C3_SCL		0x40000b9e
 		>;
 	};
-
-	pinctrl_xspi1: xspi1grp {
-		fsl,pins = <
-			IMX94_PAD_XSPI1_SCLK__XSPI1_A_SCLK	0x3fe
-			IMX94_PAD_XSPI1_SS0_B__XSPI1_A_SS0_B	0x3fe
-			IMX94_PAD_XSPI1_DATA0__XSPI1_A_DATA0	0x3fe
-			IMX94_PAD_XSPI1_DATA1__XSPI1_A_DATA1	0x3fe
-			IMX94_PAD_XSPI1_DATA2__XSPI1_A_DATA2	0x3fe
-			IMX94_PAD_XSPI1_DATA3__XSPI1_A_DATA3	0x3fe
-			IMX94_PAD_XSPI1_DATA4__XSPI1_A_DATA4	0x3fe
-			IMX94_PAD_XSPI1_DATA5__XSPI1_A_DATA5	0x3fe
-			IMX94_PAD_XSPI1_DATA6__XSPI1_A_DATA6	0x3fe
-			IMX94_PAD_XSPI1_DATA7__XSPI1_A_DATA7	0x3fe
-			IMX94_PAD_XSPI1_DQS__XSPI1_A_DQS	0x3fe
-		>;
-	};
 };

 &pinctrl_reg_usdhc2_vmmc {
--- a/arch/arm/dts/imx943-u-boot.dtsi
+++ b/arch/arm/dts/imx943-u-boot.dtsi
@@ -141,22 +141,6 @@

 &aips3 {
 	bootph-all;
-
-	xspi1: spi@42b90000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "nxp,imx94-xspi";
-		reg = <0x42b90000 0x50000>, <0x28000000 0x08000000>;
-		reg-names = "xspi_base", "xspi_mmap";
-		interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,       // EENV0
-			     <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,	      // EENV1
-			     <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,       // EENV2
-			     <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,       // EENV3
-			     <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;       // EENV4
-		clocks = <&scmi_clk IMX94_CLK_XSPI1>;
-		clock-names = "xspi";
-		status = "disabled";
-	};
 };

 &clk_ext1 {
@@ -339,6 +323,12 @@
 				};
 			};

+			netc_timer0: ethernet@0,1 {
+				compatible = "pci1131,ee02";
+				reg = <0x100 0 0 0 0>;
+				status = "disabled";
+			};
+
 			netc_switch: ethernet-switch@0,2 {
 				compatible = "pci1131,eef2", "nxp,imx943-netc-switch";
 				reg = <0x200 0 0 0 0>;
@@ -402,6 +392,12 @@
 				status = "disabled";
 			};

+			netc_timer1: ethernet@0,1 {
+				compatible = "pci1131,ee02";
+				reg = <0x10100 0 0 0 0>;
+				status = "disabled";
+			};
+
 			enetc1: ethernet@8,0 {
 				compatible = "pci1131,e101";
 				reg = <0x14000 0 0 0 0>;
@@ -414,6 +410,12 @@
 				status = "disabled";
 			};

+			netc_timer2: ethernet@10,1 {
+				compatible = "pci1131,ee02";
+				reg = <0x18100 0 0 0 0>;
+				status = "disabled";
+			};
+
 			netc_emdio: mdio@18,0 {
 				compatible = "pci1131,ee00";
 				reg = <0x1c000 0 0 0 0>;
--- a/dts/upstream/src/arm64/freescale/imx95-toradex-smarc-dev.dts
+++ b/dts/upstream/src/arm64/freescale/imx95-toradex-smarc-dev.dts
--- a/dts/upstream/src/arm64/freescale/imx95-toradex-smarc.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx95-toradex-smarc.dtsi
@@ -112,8 +112,8 @@
 		compatible = "regulator-fixed";
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
-		gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
 		enable-active-high;
+		gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
 		off-on-delay-us = <100000>;
 		regulator-max-microvolt = <3300000>;
 		regulator-min-microvolt = <3300000>;
@@ -153,7 +153,7 @@
 			compatible = "shared-dma-pool";
 			reusable;
 			size = <0 0x3c000000>;
-			alloc-ranges = <0 0x80000000 0 0x7f000000>;
+			alloc-ranges = <0 0x80000000 0 0x7F000000>;
 			linux,cma-default;
 		};
 	};
@@ -406,6 +406,8 @@
 			"",
 			"",
 			"",
+			"",
+			"",
 			"SMARC_SDIO_WP";
 	};

@@ -451,14 +453,12 @@

 			port@0 {
 				reg = <0>;
-
 				sn65dsi86_in: endpoint {
 				};
 			};

 			port@1 {
 				reg = <1>;
-
 				sn65dsi86_out: endpoint {
 					data-lanes = <3 2 1 0>;
 				};
@@ -580,7 +580,7 @@
 	ethphy1: ethernet-phy@1 {
 		reg = <1>;
 		interrupt-parent = <&som_gpio_expander_1>;
-		interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
+		interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
 		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 		ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 	};
--- a/arch/arm/dts/imx95-u-boot.dtsi
+++ b/arch/arm/dts/imx95-u-boot.dtsi
@@ -96,10 +96,6 @@
 			};
 		};
 	};
-
-	imx95-cm7 {
-		compatible = "fsl,imx95-cm7";
-	};
 };

 &A55_0 {
--- a/arch/arm/dts/imx95-verdin-dev.dtsi
+++ b/arch/arm/dts/imx95-verdin-dev.dtsi
@@ -1,239 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/*
- * Copyright (c) Toradex
- *
- * Common dtsi for Verdin iMX95 SoM on development carrier board
- *
- * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
- * https://www.toradex.com/products/carrier-board/verdin-development-board-kit
- */
-
-/ {
-	aliases {
-		eeprom1 = &carrier_eeprom;
-	};
-
-	sound {
-		compatible = "simple-audio-card";
-		simple-audio-card,bitclock-master = <&codec_dai>;
-		simple-audio-card,format = "i2s";
-		simple-audio-card,frame-master = <&codec_dai>;
-		simple-audio-card,mclk-fs = <256>;
-		simple-audio-card,name = "verdin-nau8822";
-		simple-audio-card,routing =
-			"Headphones", "LHP",
-			"Headphones", "RHP",
-			"Speaker", "LSPK",
-			"Speaker", "RSPK",
-			"Line Out", "AUXOUT1",
-			"Line Out", "AUXOUT2",
-			"LAUX", "Line In",
-			"RAUX", "Line In",
-			"LMICP", "Mic In",
-			"RMICP", "Mic In";
-		simple-audio-card,widgets =
-			"Headphones", "Headphones",
-			"Line Out", "Line Out",
-			"Speaker", "Speaker",
-			"Microphone", "Mic In",
-			"Line", "Line In";
-
-		codec_dai: simple-audio-card,codec {
-			clocks = <&scmi_clk IMX95_CLK_SAI3>;
-			sound-dai = <&nau8822_1a>;
-		};
-
-		simple-audio-card,cpu {
-			sound-dai = <&sai3>;
-		};
-	};
-};
-
-/* Verdin ADC_1, ADC_2, ADC_3 and ADC_4 */
-&adc1 {
-	status = "okay";
-};
-
-/* Verdin ETH_1 (On-module PHY) */
-&enetc_port0 {
-	status = "okay";
-};
-
-/* Verdin ETH_2_RGMII */
-&enetc_port1 {
-	phy-handle = <&ethphy2>;
-	phy-mode = "rgmii-id";
-	status = "okay";
-};
-
-/* Verdin QSPI_1 */
-&flexspi1 {
-	status = "okay";
-};
-
-&gpio1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
-};
-
-&gpio2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_gpio1>,
-		    <&pinctrl_gpio2>,
-		    <&pinctrl_gpio3>;
-};
-
-&gpio3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_gpio6>;
-};
-
-&gpio4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_gpio5>;
-};
-
-&gpio5 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_gpio4>;
-};
-
-/* Verdin I2C_3_HDMI */
-&i3c2 {
-	status = "okay";
-};
-
-/* Verdin I2C_2_DSI */
-&lpi2c3 {
-	status = "okay";
-};
-
-/* Verdin I2C_1 */
-&lpi2c4 {
-	status = "okay";
-
-	nau8822_1a: audio-codec@1a {
-		compatible = "nuvoton,nau8822";
-		reg = <0x1a>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_sai3_mclk>;
-		#sound-dai-cells = <0>;
-	};
-
-	carrier_gpio_expander: gpio@21 {
-		compatible = "nxp,pcal6416";
-		reg = <0x21>;
-		#gpio-cells = <2>;
-		gpio-controller;
-	};
-
-	/* Current measurement into module VCC */
-	hwmon@40 {
-		compatible = "ti,ina219";
-		reg = <0x40>;
-		shunt-resistor = <10000>;
-	};
-
-	temperature-sensor@4f {
-		compatible = "ti,tmp75c";
-		reg = <0x4f>;
-	};
-
-	carrier_eeprom: eeprom@57 {
-		compatible = "st,24c02", "atmel,24c02";
-		reg = <0x57>;
-		pagesize = <16>;
-	};
-};
-
-/* Verdin I2C_4_CSI */
-&lpi2c5 {
-	status = "okay";
-};
-
-/* Verdin UART_3, used as the Linux console */
-&lpuart1 {
-	status = "okay";
-};
-
-/* Verdin UART_4 */
-&lpuart2 {
-	status = "okay";
-};
-
-/* Verdin UART_1, connector X50 through RS485 transceiver */
-&lpuart7 {
-	rs485-rts-active-low;
-	rs485-rx-during-tx;
-	linux,rs485-enabled-at-boot-time;
-
-	status = "okay";
-};
-
-/* Verdin UART_2 */
-&lpuart8 {
-	status = "okay";
-};
-
-&netc_emdio {
-	ethphy2: ethernet-phy@7 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <7>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_eth2_rgmii_int>;
-		interrupt-parent = <&gpio1>;
-		interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
-		micrel,led-mode = <0>;
-	};
-};
-
-/* Verdin PCIE_1 */
-&pcie0 {
-	status = "okay";
-};
-
-/* Verdin I2S_1 */
-&sai3 {
-	status = "okay";
-};
-
-/* Verdin PWM_1 */
-&tpm4 {
-	status = "okay";
-};
-
-/* Verdin PWM_2 */
-&tpm5 {
-	status = "okay";
-};
-
-/* Verdin PWM_3_DSI */
-&tpm6 {
-	status = "okay";
-};
-
-/* Verdin USB_1 */
-&usb2 {
-	status = "okay";
-};
-
-/* Verdin USB_2 */
-&usb3 {
-	fsl,permanently-attached;
-
-	status = "okay";
-};
-
-&usb3_phy {
-	status = "okay";
-};
-
-/* Verdin SD_1 */
-&usdhc2 {
-	status = "okay";
-};
-
-/* Verdin CTRL_WAKE1_MICO# */
-&verdin_gpio_keys {
-	status = "okay";
-};
--- a/arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi
+++ b/arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi
@@ -1,112 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) Toradex */
-
-#include "imx95-u-boot.dtsi"
-
-/ {
-	sysinfo {
-		compatible = "toradex,sysinfo";
-	};
-};
-
-&{/binman/m33-oei-ddrfw/imx-lpddr/imx-lpddr-imem} {
-	filename = "lpddr4x_imem_v202409.bin";
-};
-
-&{/binman/m33-oei-ddrfw/imx-lpddr/imx-lpddr-dmem} {
-	filename = "lpddr4x_dmem_v202409.bin";
-};
-
-&{/binman/m33-oei-ddrfw/imx-lpddr-qb/imx-lpddr-imem-qb} {
-	filename = "lpddr4x_imem_qb_v202409.bin";
-};
-
-&{/binman/m33-oei-ddrfw/imx-lpddr-qb/imx-lpddr-dmem-qb} {
-	filename = "lpddr4x_dmem_qb_v202409.bin";
-};
-
-&gpio1 {
-	reg = <0 0x47400000 0 0x1000>, <0 0x47400000 0 0x40>;
-	bootph-pre-ram;
-
-	ctrl-sleep-moci-hog {
-		bootph-pre-ram;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
-		gpio-hog;
-		/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
-		gpios = <14 GPIO_ACTIVE_HIGH>;
-		line-name = "CTRL_SLEEP_MOCI#";
-		output-high;
-	};
-};
-
-&som_gpio_expander {
-	bootph-pre-ram;
-};
-
-&lpi2c2 {
-	bootph-pre-ram;
-};
-
-&lpuart1 {
-	clocks = <&scmi_clk IMX95_CLK_LPUART1>, <&scmi_clk IMX95_CLK_LPUART1>;
-	clock-names = "ipg", "per";
-	bootph-pre-ram;
-};
-
-&pinctrl_ctrl_sleep_moci {
-	bootph-pre-ram;
-};
-
-&pinctrl_io_exp_int {
-	bootph-pre-ram;
-};
-
-&pinctrl_lpi2c2 {
-	bootph-pre-ram;
-};
-
-&pinctrl_lpi2c2_gpio {
-	bootph-pre-ram;
-};
-
-&pinctrl_uart1 {
-	bootph-pre-ram;
-};
-
-&pinctrl_usdhc1 {
-	bootph-pre-ram;
-};
-
-&pinctrl_usdhc1_200mhz {
-	bootph-pre-ram;
-};
-
-&som_gpio_expander {
-	bootph-pre-ram;
-};
-
-&usb2 {
-	/delete-property/power-domains;
-};
-
-&usb3 {
-	status = "disabled";
-};
-
-&usb3_dwc3 {
-	status = "disabled";
-};
-
-&usb_recov_ctrl {
-	bootph-pre-ram;
-};
-
-&usdhc1 {
-	bootph-pre-ram;
-};
-
-&wdog3 {
-	status = "disabled";
-};
--- a/arch/arm/dts/imx95-verdin-wifi-dev.dts
+++ b/arch/arm/dts/imx95-verdin-wifi-dev.dts
@@ -1,21 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/*
- * Copyright (c) Toradex
- *
- * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
- * https://www.toradex.com/products/carrier-board/verdin-development-board-kit
- */
-
-/dts-v1/;
-
-#include "imx95-verdin.dtsi"
-#include "imx95-verdin-wifi.dtsi"
-#include "imx95-verdin-dev.dtsi"
-
-/ {
-	model = "Toradex Verdin iMX95 WB on Verdin Development Board";
-	compatible = "toradex,verdin-imx95-wifi-dev",
-		     "toradex,verdin-imx95-wifi",
-		     "toradex,verdin-imx95",
-		     "fsl,imx95";
-};
--- a/arch/arm/dts/imx95-verdin-wifi.dtsi
+++ b/arch/arm/dts/imx95-verdin-wifi.dtsi
@@ -1,50 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/*
- * Copyright (c) Toradex
- *
- * Common dtsi for Verdin iMX95 SoM WB variant
- *
- * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
- */
-
-/ {
-	reg_wifi_en: regulator-wifi-en {
-		compatible = "regulator-fixed";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_wifi_pwr_en>;
-		/* PMIC_EN_WIFI */
-		gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-		regulator-max-microvolt = <3300000>;
-		regulator-min-microvolt = <3300000>;
-		regulator-name = "PDn_MAYA-W260";
-		startup-delay-us = <2000>;
-	};
-};
-
-/* On-module Bluetooth */
-&lpuart6 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_bt_uart>;
-	uart-has-rtscts;
-
-	status = "okay";
-
-	som_bt: bluetooth {
-		compatible = "nxp,88w8987-bt";
-		fw-init-baudrate = <3000000>;
-	};
-};
-
-/* On-module Wi-Fi */
-&usdhc3 {
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc3>;
-	pinctrl-1 = <&pinctrl_usdhc3>;
-	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
-	keep-power-in-suspend;
-	non-removable;
-	vmmc-supply = <&reg_wifi_en>;
-
-	status = "okay";
-};
--- a/arch/arm/dts/imx95-verdin.dtsi
+++ b/arch/arm/dts/imx95-verdin.dtsi
--- a/arch/arm/dts/imx952-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx952-evk-u-boot.dtsi
@@ -1,10 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2026 NXP
- */
-
-#include "imx952-u-boot.dtsi"
-
-&wdog3 {
-	status = "disabled";
-};
--- a/arch/arm/dts/imx952-u-boot.dtsi
+++ b/arch/arm/dts/imx952-u-boot.dtsi
@@ -1,290 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2026 NXP
- */
-
-/ {
-	binman {
-		multiple-images;
-
-		m33-oei-ddrfw {
-			pad-byte = <0x00>;
-			align-size = <0x8>;
-			filename = "m33-oei-ddrfw.bin";
-
-			oei-m33-ddr {
-				align-size = <0x4>;
-				filename = "oei-m33-ddr.bin";
-				type = "blob-ext";
-			};
-
-			imx-lpddr {
-				type = "nxp-header-ddrfw";
-
-				imx-lpddr-imem {
-					filename = "lpddr4x_imem_v202409.bin";
-					type = "blob-ext";
-				};
-
-				imx-lpddr-dmem {
-					filename = "lpddr4x_dmem_v202409.bin";
-					type = "blob-ext";
-				};
-			};
-
-			imx-lpddr-qb {
-				type = "nxp-header-ddrfw";
-
-				imx-lpddr-imem-qb {
-					filename = "lpddr4x_imem_qb_v202409.bin";
-					type = "blob-ext";
-				};
-
-				imx-lpddr-dmem-qb {
-					filename = "lpddr4x_dmem_qb_v202409.bin";
-					type = "blob-ext";
-				};
-			};
-		};
-
-		imx-boot {
-			filename = "flash.bin";
-			pad-byte = <0x00>;
-
-			spl {
-				type = "nxp-imx9image";
-				cfg-path = "spl/u-boot-spl.cfgout";
-				args;
-
-				cntr-version = <2>;
-				boot-from = "sd";
-				soc-type = "IMX9";
-				append = "mx952a0-ahab-container.img";
-				container;
-				dummy-ddr;
-				image0 = "oei", "m33-oei-ddrfw.bin", "0x1ffc0000";
-				hold = <0x10000>;
-				image1 = "m33", "m33_image.bin", "0x1ffc0000";
-				image2 = "a55", "spl/u-boot-spl.bin", "0x20480000";
-				dummy-v2x = <0x8b000000>;
-			};
-
-			u-boot {
-				type = "nxp-imx9image";
-				cfg-path = "u-boot-container.cfgout";
-				args;
-
-				cntr-version = <2>;
-				boot-from = "sd";
-				soc-type = "IMX9";
-				container;
-				image0 = "a55", "bl31.bin", "0x8a200000";
-				image1 = "a55", "u-boot.bin", "0x90200000";
-			};
-		};
-	};
-
-	chosen {
-		bootargs = "console=ttyLP0,115200 earlycon";
-	};
-};
-
-&A55_0 {
-	clocks = <&scmi_clk IMX952_CLK_ARMPLL_PFD0>;
-	/delete-property/ power-domains;
-};
-
-&A55_1 {
-	clocks = <&scmi_clk IMX952_CLK_ARMPLL_PFD0>;
-	/delete-property/ power-domains;
-};
-
-&A55_2 {
-	clocks = <&scmi_clk IMX952_CLK_ARMPLL_PFD0>;
-	/delete-property/ power-domains;
-};
-
-&A55_3 {
-	clocks = <&scmi_clk IMX952_CLK_ARMPLL_PFD0>;
-	/delete-property/ power-domains;
-};
-
-&aips1 {
-	bootph-all;
-};
-
-&aips2 {
-	bootph-all;
-};
-
-&aips3 {
-	bootph-all;
-};
-
-&clk_ext1 {
-	bootph-all;
-};
-
-&clk_dummy {
-	bootph-all;
-};
-
-&clk_osc_24m {
-	bootph-all;
-};
-
-&elemu1 {
-	status = "okay";
-	bootph-all;
-};
-
-&elemu3 {
-	status = "okay";
-	bootph-all;
-};
-
-&{/firmware} {
-	bootph-all;
-};
-
-&{/firmware/scmi} {
-	bootph-all;
-};
-
-&{/firmware/scmi/protocol@11} {
-	bootph-all;
-};
-
-&{/firmware/scmi/protocol@13} {
-	bootph-all;
-};
-
-&{/firmware/scmi/protocol@14} {
-	bootph-all;
-};
-
-&{/firmware/scmi/protocol@15} {
-	bootph-all;
-};
-
-&{/firmware/scmi/protocol@19} {
-	bootph-all;
-};
-
-&gpio1 {
-	reg = <0 0x47400000 0 0x1000>, <0 0x47400040 0 0x40>;
-};
-
-&gpio2 {
-	reg = <0 0x43810000 0 0x1000>, <0 0x43810040 0 0x40>;
-	bootph-pre-ram;
-	/*
-	 * Use one SPL/U-Boot for mx952evk and mx952evkrpmsg, since GPIO2
-	 * is assigned to M7, disable gpio2 here
-	 */
-	status = "disabled";
-};
-
-&gpio3 {
-	reg = <0 0x43820000 0 0x1000>, <0 0x43820040 0 0x40>;
-	bootph-pre-ram;
-};
-
-&gpio4 {
-	reg = <0 0x43840000 0 0x1000>, <0 0x43840040 0 0x40>;
-	bootph-pre-ram;
-};
-
-&gpio5 {
-	reg = <0 0x43850000 0 0x1000>, <0 0x43850040 0 0x40>;
-	bootph-pre-ram;
-};
-
-&lpuart1 {
-	bootph-pre-ram;
-};
-
-&mu2 {
-	bootph-all;
-};
-
-&reg_usdhc2_vmmc {
-	bootph-pre-ram;
-};
-
-&scmi_buf0 {
-	reg = <0x0 0x400>;
-	bootph-all;
-};
-
-&scmi_buf1 {
-	bootph-all;
-};
-
-&{/soc} {
-	bootph-all;
-};
-
-&sram0 {
-	bootph-all;
-};
-
-&usdhc1 {
-	bootph-pre-ram;
-};
-
-&usdhc2 {
-	bootph-pre-ram;
-};
-
-&scmi_iomuxc {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_hog>;
-
-	pinctrl_hog: hoggrp {
-		bootph-pre-ram;
-
-		fsl,pins = <
-			IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_GPIO5_IO_11	0x3fe
-			IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_TPM3_CH2		0x51e
-			IMX952_PAD_CCM_CLKO1__WAKEUPMIX_TOP_GPIO3_IO_26		0x3fe
-			IMX952_PAD_CCM_CLKO2__WAKEUPMIX_TOP_GPIO3_IO_27		0x3fe
-		>;
-	};
-};
-
-&pinctrl_uart1 {
-	bootph-pre-ram;
-};
-
-&pinctrl_usdhc1 {
-	bootph-pre-ram;
-};
-
-&pinctrl_usdhc1_100mhz {
-	bootph-pre-ram;
-};
-
-&pinctrl_usdhc1_200mhz {
-	bootph-pre-ram;
-};
-
-&pinctrl_usdhc2 {
-	bootph-pre-ram;
-};
-
-&pinctrl_usdhc2_100mhz {
-	bootph-pre-ram;
-};
-
-&pinctrl_usdhc2_200mhz {
-	bootph-pre-ram;
-};
-
-&pinctrl_usdhc2_gpio {
-	bootph-pre-ram;
-};
-
-&pinctrl_reg_usdhc2_vmmc {
-	bootph-pre-ram;
-};
--- a/arch/arm/dts/ipq5424-rdp466-u-boot.dtsi
+++ b/arch/arm/dts/ipq5424-rdp466-u-boot.dtsi
@@ -12,9 +12,6 @@
 		reg = <0x0 0x80000000 0x0 0x20000000>;
 	};

-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
 };

 	&sdhc {
--- a/arch/arm/dts/k3-am62-lp4-50-800-800.dtsi
+++ b/arch/arm/dts/k3-am62-lp4-50-800-800.dtsi
@@ -1,21 +1,20 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
 * This file was generated with the
- * AM623/AM625 SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px, AM62Dx, AM62Lx v0.10.32
- * Fri Jan 30 2026 13:45:31 GMT+0530 (India Standard Time)
+ * AM623/AM625 SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
+ * Tue Sep 17 2024 13:07:19 GMT+0530 (India Standard Time)
 * DDR Type: LPDDR4
 * F0 = 50MHz    F1 = NA     F2 = 800MHz
 * Density (per channel): 16Gb
 * Write DBI: Enable
 * Number of Ranks: 1
-*/
+ */

 #define DDRSS_PLL_FHS_CNT 3
 #define DDRSS_PLL_FREQUENCY_1 400000000
 #define DDRSS_PLL_FREQUENCY_2 400000000
 #define DDRSS_SDRAM_IDX 15
-#define DDRSS_REGION_IDX 15
-#define DDRSS_TOOL_VERSION "0.10.32"
+#define DDRSS_REGION_IDX 16

 #define DDRSS_CTL_0_DATA 0x00000B00
 #define DDRSS_CTL_1_DATA 0x00000000
@@ -647,8 +646,8 @@
 #define DDRSS_PI_204_DATA 0x00C90100
 #define DDRSS_PI_205_DATA 0x010000C9
 #define DDRSS_PI_206_DATA 0x00C900C9
-#define DDRSS_PI_207_DATA 0x321E3200
-#define DDRSS_PI_208_DATA 0x0101321E
+#define DDRSS_PI_207_DATA 0x32103200
+#define DDRSS_PI_208_DATA 0x01013210
 #define DDRSS_PI_209_DATA 0x0A070601
 #define DDRSS_PI_210_DATA 0x0D09070D
 #define DDRSS_PI_211_DATA 0x0D09070D
--- a/arch/arm/dts/k3-am62-r5-lp-sk.dts
+++ b/arch/arm/dts/k3-am62-r5-lp-sk.dts
@@ -9,4 +9,84 @@
 #include "k3-am62-ddr.dtsi"

 #include "k3-am62-lp-sk-u-boot.dtsi"
-#include "k3-am625-r5.dtsi"
+
+/ {
+	aliases {
+		tick-timer = &main_timer0;
+		remoteproc0 = &sysctrler;
+		remoteproc1 = &a53_0;
+		serial0 = &wkup_uart0;
+		serial3 = &main_uart1;
+	};
+
+	a53_0: a53@0 {
+		compatible = "ti,am654-rproc";
+		reg = <0x00 0x00a90000 0x00 0x10>;
+		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
+		resets = <&k3_reset 135 0>;
+		clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+		clock-names = "gtc", "core";
+		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+		assigned-clock-parents = <&k3_clks 61 2>;
+		assigned-clock-rates = <200000000>, <1200000000>;
+		ti,sci = <&dmsc>;
+		ti,sci-proc-id = <32>;
+		ti,sci-host-id = <10>;
+		bootph-pre-ram;
+	};
+
+	dm_tifs: dm-tifs {
+		compatible = "ti,j721e-dm-sci";
+		ti,host-id = <36>;
+		ti,secure-host;
+		mbox-names = "rx", "tx";
+		mboxes= <&secure_proxy_main 22>,
+			<&secure_proxy_main 23>;
+		bootph-pre-ram;
+	};
+};
+
+&dmsc {
+	mboxes= <&secure_proxy_main 0>,
+		<&secure_proxy_main 1>,
+		<&secure_proxy_main 0>;
+	mbox-names = "rx", "tx", "notify";
+	ti,host-id = <35>;
+	ti,secure-host;
+};
+
+&secure_proxy_sa3 {
+	/* We require this for boot handshake */
+	status = "okay";
+};
+
+&cbass_main {
+	sysctrler: sysctrler {
+		compatible = "ti,am654-tisci-rproc-r5";
+		mboxes= <&secure_proxy_main 1>,
+			<&secure_proxy_main 0>,
+			<&secure_proxy_sa3 0>;
+		mbox-names = "tx", "rx", "boot_notify";
+		bootph-pre-ram;
+	};
+};
+
+&main_timer0 {
+	/delete-property/ clocks;
+	/delete-property/ clocks-names;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	clock-frequency = <25000000>;
+};
+
+/* WKUP UART0 is used for DM firmware logs */
+&wkup_uart0 {
+	status = "okay";
+};
+
+/* Main UART1 is used for TIFS firmware logs */
+&main_uart1 {
+	status = "okay";
+};
--- a/arch/arm/dts/k3-am625-phycore-som-binman.dtsi
+++ b/arch/arm/dts/k3-am625-phycore-som-binman.dtsi
@@ -215,36 +215,6 @@
 		fit {

 			images {
-				atf {
-					ti-secure {
-						auth-in-place = <0xa02>;
-
-						firewall-1-0 {
-							insert-template = <&firewall_bg_3>;
-							id = <1>;
-							region = <0>;
-						};
-
-						firewall-1-1 {
-							insert-template = <&firewall_armv8_atf_fg>;
-							id = <1>;
-							region = <1>;
-						};
-					};
-				};
-
-				tee {
-					ti-secure {
-						auth-in-place = <0xa02>;
-
-						firewall-1-2 {
-							insert-template = <&firewall_armv8_optee_fg>;
-							id = <1>;
-							region = <2>;
-						};
-					};
-				};
-
 				tifsstub-hs {
 					description = "TIFSSTUB";
 					type = "firmware";
--- a/arch/arm/dts/k3-am625-r5-beagleplay.dts
+++ b/arch/arm/dts/k3-am625-r5-beagleplay.dts
@@ -11,14 +11,70 @@
 #include "k3-am62-ddr.dtsi"

 #include "k3-am625-beagleplay-u-boot.dtsi"
-#include "k3-am625-r5.dtsi"

-&a53_0 {
-	power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-			<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
-	assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
-	assigned-clock-parents = <&k3_clks 61 2>;
-	assigned-clock-rates = <200000000>, <1250000000>;
+/ {
+	aliases {
+		remoteproc0 = &sysctrler;
+		remoteproc1 = &a53_0;
+	};
+
+	a53_0: a53@0 {
+		compatible = "ti,am654-rproc";
+		reg = <0x00 0x00a90000 0x00 0x10>;
+		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
+		resets = <&k3_reset 135 0>;
+		clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+		clock-names = "gtc", "core";
+		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+		assigned-clock-parents = <&k3_clks 61 2>;
+		assigned-clock-rates = <200000000>, <1250000000>;
+		ti,sci = <&dmsc>;
+		ti,sci-proc-id = <32>;
+		ti,sci-host-id = <10>;
+		bootph-pre-ram;
+	};
+
+	dm_tifs: dm-tifs {
+		compatible = "ti,j721e-dm-sci";
+		ti,host-id = <36>;
+		ti,secure-host;
+		mbox-names = "rx", "tx";
+		mboxes= <&secure_proxy_main 22>,
+			<&secure_proxy_main 23>;
+		bootph-pre-ram;
+	};
+};
+
+&main_timer0 {
+	/delete-property/ clocks;
+	/delete-property/ clocks-names;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	clock-frequency = <25000000>;
+};
+
+&dmsc {
+	mboxes= <&secure_proxy_main 0>,
+		<&secure_proxy_main 1>,
+		<&secure_proxy_main 0>;
+	mbox-names = "rx", "tx", "notify";
+	ti,host-id = <35>;
+	ti,secure-host;
+};
+
+&secure_proxy_sa3 {
+	/* We require this for boot handshake */
+	status = "okay";
+};
+
+&cbass_main {
+	sysctrler: sysctrler {
+		compatible = "ti,am654-tisci-rproc-r5";
+		mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
+		mbox-names = "tx", "rx", "boot_notify";
+		bootph-pre-ram;
+	};
 };

 &main_pktdma {
--- a/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts
+++ b/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts
@@ -10,9 +10,42 @@
 #include "k3-am62-ddr.dtsi"

 #include "k3-am625-phyboard-lyra-rdk-u-boot.dtsi"
-#include "k3-am625-r5.dtsi"

 / {
+	aliases {
+		remoteproc0 = &sysctrler;
+		remoteproc1 = &a53_0;
+		serial0 = &wkup_uart0;
+		serial3 = &main_uart1;
+	};
+
+	a53_0: a53@0 {
+		compatible = "ti,am654-rproc";
+		reg = <0x00 0x00a90000 0x00 0x10>;
+		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
+		resets = <&k3_reset 135 0>;
+		clocks = <&k3_clks 61 0>;
+		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+		assigned-clock-parents = <&k3_clks 61 2>;
+		assigned-clock-rates = <200000000>, <1200000000>;
+		ti,sci = <&dmsc>;
+		ti,sci-proc-id = <32>;
+		ti,sci-host-id = <10>;
+		bootph-pre-ram;
+	};
+
+	dm_tifs: dm-tifs {
+		compatible = "ti,j721e-dm-sci";
+		ti,host-id = <36>;
+		ti,secure-host;
+		mbox-names = "rx", "tx";
+		mboxes= <&secure_proxy_main 22>,
+			<&secure_proxy_main 23>;
+		bootph-pre-ram;
+	};
+
 	memory@80000000 {
 		device_type = "memory";
 		/* 2G RAM */
@@ -21,14 +54,45 @@
 	};
 };

-&main_pktdma {
-	ti,sci = <&dm_tifs>;
+&main_timer0 {
+	/delete-property/ clocks;
+	/delete-property/ clocks-names;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	clock-frequency = <25000000>;
+};
+
+&secure_proxy_sa3 {
+	/* We require this for boot handshake */
+	status = "okay";
+};
+
+&cbass_main {
+	sysctrler: sysctrler {
+		compatible = "ti,am654-tisci-rproc-r5";
+		mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
+		mbox-names = "tx", "rx", "boot_notify";
+		bootph-pre-ram;
+	};
+};
+
+&dmsc {
+	mboxes= <&secure_proxy_main 0>,
+		<&secure_proxy_main 1>,
+		<&secure_proxy_main 0>;
+	mbox-names = "rx", "tx", "notify";
+	ti,host-id = <35>;
+	ti,secure-host;
 };

 &main_bcdma {
 	ti,sci = <&dm_tifs>;
 };

+&main_pktdma {
+	ti,sci = <&dm_tifs>;
+};
+
 &mcu_pmx0 {
 	wkup_uart0_pins_default: wkup-uart0-pins-default {
 		pinctrl-single,pins = <
@@ -41,6 +105,11 @@
 	};
 };

+&ospi0 {
+	reg = <0x00 0x0fc40000 0x00 0x100>,
+	      <0x00 0x60000000 0x00 0x08000000>;
+};
+
 /* WKUP UART0 is used for DM firmware logs */
 &wkup_uart0 {
 	pinctrl-names = "default";
--- a/arch/arm/dts/k3-am625-r5-sk.dts
+++ b/arch/arm/dts/k3-am625-r5-sk.dts
@@ -9,8 +9,92 @@
 #include "k3-am62-ddr.dtsi"

 #include "k3-am625-sk-u-boot.dtsi"
-#include "k3-am625-r5.dtsi"
+
+/ {
+	aliases {
+		tick-timer = &main_timer0;
+		remoteproc0 = &sysctrler;
+		remoteproc1 = &a53_0;
+		serial0 = &wkup_uart0;
+		serial3 = &main_uart1;
+	};
+
+	a53_0: a53@0 {
+		compatible = "ti,am654-rproc";
+		reg = <0x00 0x00a90000 0x00 0x10>;
+		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
+		resets = <&k3_reset 135 0>;
+		clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+		clock-names = "gtc", "core";
+		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+		assigned-clock-parents = <&k3_clks 61 2>;
+		assigned-clock-rates = <200000000>, <1200000000>;
+		ti,sci = <&dmsc>;
+		ti,sci-proc-id = <32>;
+		ti,sci-host-id = <10>;
+		bootph-pre-ram;
+	};
+
+	dm_tifs: dm-tifs {
+		compatible = "ti,j721e-dm-sci";
+		ti,host-id = <36>;
+		ti,secure-host;
+		mbox-names = "rx", "tx";
+		mboxes= <&secure_proxy_main 22>,
+			<&secure_proxy_main 23>;
+		bootph-pre-ram;
+	};
+};
+
+&dmsc {
+	mboxes= <&secure_proxy_main 0>,
+		<&secure_proxy_main 1>,
+		<&secure_proxy_main 0>;
+	mbox-names = "rx", "tx", "notify";
+	ti,host-id = <35>;
+	ti,secure-host;
+};
+
+&secure_proxy_sa3 {
+	/* We require this for boot handshake */
+	status = "okay";
+};
+
+&cbass_main {
+	sysctrler: sysctrler {
+		compatible = "ti,am654-tisci-rproc-r5";
+		mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
+		mbox-names = "tx", "rx", "boot_notify";
+		bootph-pre-ram;
+	};
+};
+
+&main_timer0 {
+	/delete-property/ clocks;
+	/delete-property/ clocks-names;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	clock-frequency = <25000000>;
+};
+
+/* WKUP UART0 is used for DM firmware logs */
+&wkup_uart0 {
+	status = "okay";
+};
+
+/* Main UART1 is used for TIFS firmware logs */
+&main_uart1 {
+	status = "okay";
+};
+
+&ospi0 {
+	reg = <0x00 0x0fc40000 0x00 0x100>,
+	      <0x00 0x60000000 0x00 0x08000000>;
+};

 &main_pktdma {
 	ti,sci = <&dm_tifs>;
+	bootph-all;
 };
--- a/arch/arm/dts/k3-am625-r5.dtsi
+++ b/arch/arm/dts/k3-am625-r5.dtsi
@@ -1,88 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/ {
-	aliases {
-		tick-timer = &main_timer0;
-		remoteproc0 = &sysctrler;
-		remoteproc1 = &a53_0;
-		serial0 = &wkup_uart0;
-		serial3 = &main_uart1;
-	};
-
-	a53_0: a53@0 {
-		compatible = "ti,am654-rproc";
-		reg = <0x00 0x00a90000 0x00 0x10>;
-		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
-		resets = <&k3_reset 135 0>;
-		clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
-		clock-names = "gtc", "core";
-		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
-		assigned-clock-parents = <&k3_clks 61 2>;
-		assigned-clock-rates = <200000000>, <1200000000>;
-		ti,sci = <&dmsc>;
-		ti,sci-proc-id = <32>;
-		ti,sci-host-id = <10>;
-		bootph-pre-ram;
-	};
-
-	dm_tifs: dm-tifs {
-		compatible = "ti,j721e-dm-sci";
-		ti,host-id = <36>;
-		ti,secure-host;
-		mbox-names = "rx", "tx";
-		mboxes= <&secure_proxy_main 22>,
-			<&secure_proxy_main 23>;
-		bootph-pre-ram;
-	};
-};
-
-&dmsc {
-	mboxes= <&secure_proxy_main 0>,
-		<&secure_proxy_main 1>,
-		<&secure_proxy_main 0>;
-	mbox-names = "rx", "tx", "notify";
-	ti,host-id = <35>;
-	ti,secure-host;
-};
-
-&secure_proxy_sa3 {
-	/* We require this for boot handshake */
-	status = "okay";
-};
-
-&cbass_main {
-	sysctrler: sysctrler {
-		compatible = "ti,am654-tisci-rproc-r5";
-		mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
-		mbox-names = "tx", "rx", "boot_notify";
-		bootph-pre-ram;
-	};
-};
-
-&main_timer0 {
-	/delete-property/ clocks;
-	/delete-property/ clocks-names;
-	/delete-property/ assigned-clocks;
-	/delete-property/ assigned-clock-parents;
-	clock-frequency = <25000000>;
-};
-
-/* WKUP UART0 is used for DM firmware logs */
-&wkup_uart0 {
-	status = "okay";
-};
-
-/* Main UART1 is used for TIFS firmware logs */
-&main_uart1 {
-	status = "okay";
-};
-
-&ospi0 {
-	reg = <0x00 0x0fc40000 0x00 0x100>,
-	      <0x00 0x60000000 0x00 0x08000000>;
-};
--- a/arch/arm/dts/k3-am625-sk-binman.dtsi
+++ b/arch/arm/dts/k3-am625-sk-binman.dtsi
@@ -7,10 +7,6 @@

 #ifdef CONFIG_TARGET_AM625_R5_EVM

-&rcfg_yaml_tifs {
-	config = "tifs-rm-cfg.yaml";
-};
-
 &binman {
 	tiboot3-am62x-hs-evm.bin {
 		filename = "tiboot3-am62x-hs-evm.bin";
@@ -279,35 +275,6 @@

 		fit {
 			images {
-				atf {
-					ti-secure {
-						auth-in-place = <0xa02>;
-
-						firewall-1-0 {
-							insert-template = <&firewall_bg_3>;
-							id = <1>;
-							region = <0>;
-						};
-
-						firewall-1-1 {
-							insert-template = <&firewall_armv8_atf_fg>;
-							id = <1>;
-							region = <1>;
-						};
-					};
-				};
-
-				tee {
-					ti-secure {
-						auth-in-place = <0xa02>;
-
-						firewall-1-2 {
-							insert-template = <&firewall_armv8_optee_fg>;
-							id = <1>;
-							region = <2>;
-						};
-					};
-				};

 				tifsstub-hs {
 					description = "TIFSSTUB";
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
Tom Rini	fd070b0e71	Merge patch series "clk: support arbitrary clk_register() sequence" Yang Xiwen <forbidden405@outlook.com> says: Currently, the U-Boot clk framework mandates that clock registration begins at the root and proceeds to children. This creates an additional requirement that does not exist in the Linux kernel, making the porting of clk drivers more difficult. This series handles the dependency entirely within the clk framework, allowing drivers the freedom to register clocks in any order. This is achieved by assigning the parent "lazily". The framework caches the parent name in the core clk struct and attempts to resolve the actual parent when clk consumers call clk_get_parent(). The process is transparent to clk consumers as long as they use standard clk framework APIs. I've run `ut dm clk*` and verified these commits do not break any existing test cases. It also passes the new test case. This feature is disabled for xPLs by default. I have not found a clean way to enable this separately for xPLs without introducing a repetitive Kconfig entry (e.g., xPL_CLK_LAZY_REPARENT), which looks very ugly. Link: https://lore.kernel.org/r/20260120-clk-reparent-v3-0-0d43d4b362ac@outlook.com	2026-02-02 13:40:50 -06:00
Yang Xiwen	90cd316b5a	test: clk: add test for CLK_LAZY_REPARENT Add a test for the newly introduced CLK_LAZY_REPARENT feature. Modify clk_sandbox_ccf driver to register two clocks(i2s and i2s_root) in reversed order. The test function then try to acquire the clocks and asserts that their internal states are maintained correctly. Ensure clk->parent_name is NULL in all "normal" cases so existing drivers are not broken by this feature. Signed-off-by: Yang Xiwen <forbidden405@outlook.com>	2026-02-02 13:40:41 -06:00
Yang Xiwen	8f230323e4	clk: allow assigning parent lazily Don't mandate the parent device exists when registering a clock. Instead, cache the parent name in the core clk struct and resolve the parent in clk_get_parent(), which is called lazily upon real use. Disable this feature for xPLs by default to save size. Reviewed-by: Simon Glass <simon.glass@canonical.com> Signed-off-by: Yang Xiwen <forbidden405@outlook.com>	2026-02-02 13:40:41 -06:00
Yang Xiwen	5fc1388141	clk: use clk_get_parent() helper in clk_en(dis)able() Update clk_enable() and clk_disable() to use clk_get_parent() instead of manually accessing clk->dev->parent. Reviewed-by: Simon Glass <simon.glass@canonical.com> Signed-off-by: Yang Xiwen <forbidden405@outlook.com>	2026-02-02 13:40:41 -06:00
Yang Xiwen	d18343651c	clk: add uclass id check to clk_get_parent() Check the uclass id in clk_get_parent() before casting dev->priv to struct clk *. This sanity check can be also found in some other places and should be enforced. Reviewed-by: Simon Glass <simon.glass@canonical.com> Signed-off-by: Yang Xiwen <forbidden405@outlook.com>	2026-02-02 13:40:41 -06:00
Yang Xiwen	74720cb082	test: dm: core: add some assertions for device_reparent() The original tests only assert the return value of device_reparent(), but does not check the actual relation between the new parent and the child. Add some assertions to check this behavior. It also lacks the logic to test orphan/root devices. Add tests for that. Signed-off-by: Yang Xiwen <forbidden405@outlook.com>	2026-02-02 13:40:41 -06:00
Yang Xiwen	d7aea17d2e	drivers: core: device: set new parent when old parent is NULL The current logic does not update the new parent in device_reparent() if old parent is NULL. The behavior is not desired. Fix it by setting the parent in this case. Fixes: `cfecbaf4e7` ("dm: core: add support for device re-parenting") Signed-off-by: Yang Xiwen <forbidden405@outlook.com>	2026-02-02 13:40:41 -06:00