Prepare v2023.07.02

Take the v2023.07 tag, which reported to be v2023.07-rc6 still, and
change this to be v2023.07.02 (as I made a v2023.07.01 incorrectly).

Signed-off-by: Tom Rini <trini@konsulko.com>

.azure-pipelines.yml

@@ -1,45 +1,13 @@
 variables:
-  windows_vm: windows-2022
-  ubuntu_vm: ubuntu-24.04
-  macos_vm: macOS-14
-  ci_runner_image: trini/u-boot-gitlab-ci-runner:noble-20251013-23Jan2026
-  # Ensure we do a shallow clone
-  Agent.Source.Git.ShallowFetchDepth: 1
+  windows_vm: windows-2019
+  ubuntu_vm: ubuntu-22.04
+  macos_vm: macOS-12
+  ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20230308-04Apr2023
   # Add '-u 0' options for Azure pipelines, otherwise we get "permission
   # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
   # since our $(ci_runner_image) user is not root.
   container_option: -u 0
   work_dir: /u
-  # We define all of these as variables so we can easily reference them twice
-  am33xx_kirkwood: "am33xx kirkwood"
-  amd: "amd xilinx zynq"
-  amlogic_bcm: "amlogic bcm -x mips"
-  atmel: "atmel"
-  engicam_renesas: "engicam renesas"
-  k3_32b: "k3 -x aarch64,phytec,toradex"
-  k3_64b: "k3 -x armv7,phytec,toradex"
-  kirkwood_mvebu: "kirkwood mvebu"
-  layerscape_vf610: "ls1 ls2 lx2 vf610 -x phytec,toradex"
-  m68k_remaining_mx_xtensa: "m68k imxrt mx xtensa -x mx6,aarch64"
-  mips_x86: "mips x86 -x mediatek"
-  mx6: "mx6 -x engicam,phytec,toradex"
-  imx8: "imx8 -x engicam,phytec,toradex"
-  imx9_arc_nios2_socfpga: "imx9 arc nios2 socfpga -x phytec,toradex"
-  phytec_toradex: "phytec toradex"
-  powerpc: "powerpc"
-  riscv_stm32: "riscv stm32 -x engicam,xilinx"
-  rk3399: "rk3399"
-  rk352x_rk358x: "rk352 rk358"
-  rk356x_rk357x: "rk356 rk357"
-  rk3xxx_rest: "rk30 rk31 rk32 rk33 -x rk3399,phytec"
-  sandbox_tegra: "tegra sandbox -x toradex"
-  samsung_omap_mediatek: "samsung omap mediatek"
-  sun4i_5i: "sun4i sun5i"
-  sun6i_sun7i: "sun6i sun7i"
-  sun8i: "sun8i"
-  sunxi_rest: "sunxi -x sun4i,sun5i,sun6i,sun7i,sun8i"
-  arm_catch_all: "arm -x aarch64,am33xx,atmel,bcm,ls,lx,imx,k3,kirkwood,mvebu,mx,omap,renesas,rk,samsung,socfpga,stm32,sunxi,tegra,vf610,xilinx,zynq"
-  aarch64_catch_all: "aarch64 -x amd,amlogic,bcm,engicam,imx,k3,ls,lx,mediatek,mvebu,renesas,rk,samsung,socfpga,stm32,sunxi,tegra,xilinx,zynq"
 
 stages:
 - stage: testsuites
@@ -97,9 +65,17 @@ stages:
       # have no matches.
       - script: git grep -E '^#[[:blank:]]*(define|undef)[[:blank:]]*CONFIG_'
                   :^doc/ :^arch/arm/dts/ :^scripts/kconfig/lkc.h
-                  :^include/linux/kconfig.h :^tools/ :^dts/upstream/
-                  :^lib/mbedtls/external :^lib/mbedtls/mbedtls_def_config.h &&
-                  exit 1 || exit 0
+                  :^include/linux/kconfig.h :^tools/ && exit 1 || exit 0
+
+  - job: cppcheck
+    displayName: 'Static code analysis with cppcheck'
+    pool:
+      vmImage: $(ubuntu_vm)
+    container:
+      image: $(ci_runner_image)
+      options: $(container_option)
+    steps:
+      - script: cppcheck -j$(nproc) --force --quiet --inline-suppr .
 
   - job: docs
     displayName: 'Build documentation'
@@ -110,13 +86,34 @@ stages:
       options: $(container_option)
     steps:
       - script: |
-          set -e
-          python3 -m venv /tmp/venvhtml
+          virtualenv -p /usr/bin/python3 /tmp/venvhtml
           . /tmp/venvhtml/bin/activate
-          pip install -r doc/sphinx/requirements.txt -r test/py/requirements.txt
+          pip install -r doc/sphinx/requirements.txt
           make htmldocs KDOC_WERROR=1
           make infodocs
 
+  - job: todo
+    displayName: 'Search for TODO within source tree'
+    pool:
+      vmImage: $(ubuntu_vm)
+    container:
+      image: $(ci_runner_image)
+      options: $(container_option)
+    steps:
+      - script: grep -r TODO .
+      - script: grep -r FIXME .
+      - script: grep -r HACK . | grep -v HACKKIT
+
+  - job: sloccount
+    displayName: 'Some statistics about the code base'
+    pool:
+      vmImage: $(ubuntu_vm)
+    container:
+      image: $(ci_runner_image)
+      options: $(container_option)
+    steps:
+      - script: sloccount .
+
   - job: maintainers
     displayName: 'Ensure all configs have MAINTAINERS entries'
     pool:
@@ -126,10 +123,10 @@ stages:
       options: $(container_option)
     steps:
       - script: |
-          ./tools/buildman/buildman --maintainer-check
+          ./tools/buildman/buildman -R
 
-  - job: allyesconfig_and_tools
-    displayName: 'Ensure allyesconfig, tools-only and envtools build'
+  - job: tools_only
+    displayName: 'Ensure host tools build'
     pool:
       vmImage: $(ubuntu_vm)
     container:
@@ -137,16 +134,52 @@ stages:
       options: $(container_option)
     steps:
       - script: |
-          # Allow pipefail because of how we use 'yes' here.
-          set +o pipefail;
-          yes 0 | make allyesconfig oldconfig all -j$(nproc)
-          make mrproper
           make tools-only_config tools-only -j$(nproc)
-          make mrproper
+
+  - job: envtools
+    displayName: 'Ensure env tools build'
+    pool:
+      vmImage: $(ubuntu_vm)
+    container:
+      image: $(ci_runner_image)
+      options: $(container_option)
+    steps:
+      - script: |
           make tools-only_config envtools -j$(nproc)
 
   - job: utils
     displayName: 'Run binman, buildman, dtoc, Kconfig and patman testsuites'
+    pool:
+      vmImage: $(ubuntu_vm)
+    steps:
+      - script: |
+          cat << "EOF" > build.sh
+          cd $(work_dir)
+          git config --global user.name "Azure Pipelines"
+          git config --global user.email bmeng.cn@gmail.com
+          git config --global --add safe.directory $(work_dir)
+          export USER=azure
+          virtualenv -p /usr/bin/python3 /tmp/venv
+          . /tmp/venv/bin/activate
+          pip install -r test/py/requirements.txt
+          export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl
+          export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt
+          export PATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}
+          ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w --board sandbox_spl
+          set -ex
+          ./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test
+          ./tools/buildman/buildman -t
+          ./tools/dtoc/dtoc -t
+          ./tools/patman/patman test
+          make O=${UBOOT_TRAVIS_BUILD_DIR} testconfig
+          EOF
+          cat build.sh
+          # We cannot use "container" like other jobs above, as buildman
+          # seems to hang forever with pre-configured "container" environment
+          docker run -v $PWD:$(work_dir) $(ci_runner_image) /bin/bash $(work_dir)/build.sh
+
+  - job: nokia_rx51_test
+    displayName: 'Run tests for Nokia RX-51 (aka N900)'
     pool:
       vmImage: $(ubuntu_vm)
     container:
@@ -154,31 +187,15 @@ stages:
       options: $(container_option)
     steps:
       - script: |
-          # Configure git
-          git config --global user.name "Azure Pipelines"
-          git config --global user.email bmeng.cn@gmail.com
-          export USER=azure
-          python3 -m venv /tmp/venv
-          . /tmp/venv/bin/activate
-          pip install -r test/py/requirements.txt \
-            -r tools/binman/requirements.txt \
-            -r tools/buildman/requirements.txt \
-            -r tools/patman/requirements.txt \
-            -r tools/u_boot_pylib/requirements.txt
-          export UBOOT_TRAVIS_BUILD_DIR=/tmp/tools-only
-          export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt
-          export PATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}
-          ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w --board tools-only
-          set -ex
-          export TOOLPATH="--toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools --toolpath /opt/coreboot"
-          ./tools/binman/binman ${TOOLPATH} tool -f missing
-          ./tools/binman/binman ${TOOLPATH} test
-          # Avoid "Permission denied: 'cov'" error by using a temporary file
-          COVERAGE_FILE=/tmp/.coverage ./tools/binman/binman ${TOOLPATH} test -T
-          ./tools/buildman/buildman -t
-          ./tools/dtoc/dtoc -t
-          ./tools/patman/patman test
-          make O=${UBOOT_TRAVIS_BUILD_DIR} testconfig
+          mkdir nokia_rx51_tmp
+          ln -s /opt/nokia/u-boot-gen-combined nokia_rx51_tmp/
+          ln -s /opt/nokia/qemu-n900.tar.gz nokia_rx51_tmp/
+          ln -s /opt/nokia/kernel_2.6.28-20103103+0m5_armel.deb nokia_rx51_tmp/
+          ln -s /opt/nokia/libc6_2.5.1-1eglibc27+0m5_armel.deb nokia_rx51_tmp/
+          ln -s /opt/nokia/busybox_1.10.2.legal-1osso30+0m5_armel.deb nokia_rx51_tmp/
+          ln -s /opt/nokia/qemu-system-arm nokia_rx51_tmp/
+          export PATH=/opt/gcc-12.2.0-nolibc/arm-linux-gnueabi/bin:$PATH
+          test/nokia_rx51_test.sh
 
   - job: pylint
     displayName: Check for any pylint regressions
@@ -191,24 +208,30 @@ stages:
       - script: |
           git config --global --add safe.directory $(work_dir)
           export USER=azure
-          python3 -m venv /tmp/venv
-          . /tmp/venv/bin/activate
-          pip install -r test/py/requirements.txt \
-            -r tools/binman/requirements.txt \
-            -r tools/buildman/requirements.txt \
-            -r tools/patman/requirements.txt \
-            -r tools/u_boot_pylib/requirements.txt \
-            asteval pylint==3.3.4 pyopenssl
+          pip install -r test/py/requirements.txt
+          pip install asteval pylint==2.12.2 pyopenssl
           export PATH=${PATH}:~/.local/bin
           echo "[MASTER]" >> .pylintrc
           echo "load-plugins=pylint.extensions.docparams" >> .pylintrc
-          export UBOOT_TRAVIS_BUILD_DIR=/tmp/tools-only
-          ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w --board tools-only
+          export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl
+          ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w --board sandbox_spl
           set -ex
           pylint --version
           export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt
           make pylint_err
 
+  - job: check_for_pre_schema_tags
+    displayName: 'Check for pre-schema driver model tags'
+    pool:
+      vmImage: $(ubuntu_vm)
+    container:
+      image: $(ci_runner_image)
+      options: $(container_option)
+    steps:
+      # If grep succeeds and finds a match the test fails as we should
+      # have no matches.
+      - script: git grep u-boot,dm- -- '*.dts*' && exit 1 || exit 0
+
   - job: check_packing_of_python_tools
     displayName: 'Check we can package the Python tools'
     pool:
@@ -219,201 +242,22 @@ stages:
     steps:
       - script: make pip
 
-  - job: count_built_machines
-    displayName: 'Ensure we build all possible machines'
-    pool:
-      vmImage: $(ubuntu_vm)
-    container:
-      image: $(ci_runner_image)
-      options: $(container_option)
-    steps:
-      - script: |
-          BMANARGS="-o /tmp --dry-run -v"
-          # First get the total number of boards
-          total=$(tools/buildman/buildman ${BMANARGS} | grep "Total boards to build for each commit" | cut -d ' ' -f 8)
-          # Now build up the list of what each job built.
-          built="$(tools/buildman/buildman ${BMANARGS} $(am33xx_kirkwood) | grep '^   ')"
-          built="$built $(tools/buildman/buildman ${BMANARGS} $(amd) | grep '^   ')"
-          built="$built $(tools/buildman/buildman ${BMANARGS} $(amlogic_bcm) | grep '^   ')"
-          built="$built $(tools/buildman/buildman ${BMANARGS} $(atmel) | grep '^   ')"
-          built="$built $(tools/buildman/buildman ${BMANARGS} $(engicam_renesas) | grep '^   ')"
-          built="$built $(tools/buildman/buildman ${BMANARGS} $(k3_32b) | grep '^   ')"
-          built="$built $(tools/buildman/buildman ${BMANARGS} $(k3_64b) | grep '^   ')"
-          built="$built $(tools/buildman/buildman ${BMANARGS} $(kirkwood_mvebu) | grep '^   ')"
-          built="$built $(tools/buildman/buildman ${BMANARGS} $(layerscape_vf610) | grep '^   ')"
-          built="$built $(tools/buildman/buildman ${BMANARGS} $(m68k_remaining_mx_xtensa) | grep '^   ')"
-          built="$built $(tools/buildman/buildman ${BMANARGS} $(mips_x86) | grep '^   ')"
-          built="$built $(tools/buildman/buildman ${BMANARGS} $(mx6) | grep '^   ')"
-          built="$built $(tools/buildman/buildman ${BMANARGS} $(imx8) | grep '^   ')"
-          built="$built $(tools/buildman/buildman ${BMANARGS} $(imx9_arc_nios2_socfpga) | grep '^   ')"
-          built="$built $(tools/buildman/buildman ${BMANARGS} $(phytec_toradex) | grep '^   ')"
-          built="$built $(tools/buildman/buildman ${BMANARGS} $(powerpc) | grep '^   ')"
-          built="$built $(tools/buildman/buildman ${BMANARGS} $(riscv_stm32) | grep '^   ')"
-          built="$built $(tools/buildman/buildman ${BMANARGS} $(rk3399) | grep '^   ')"
-          built="$built $(tools/buildman/buildman ${BMANARGS} $(rk352x_rk358x) | grep '^   ')"
-          built="$built $(tools/buildman/buildman ${BMANARGS} $(rk356x_rk357x) | grep '^   ')"
-          built="$built $(tools/buildman/buildman ${BMANARGS} $(rk3xxx_rest) | grep '^   ')"
-          built="$built $(tools/buildman/buildman ${BMANARGS} $(sandbox_tegra) | grep '^   ')"
-          built="$built $(tools/buildman/buildman ${BMANARGS} $(samsung_omap_mediatek) | grep '^   ')"
-          built="$built $(tools/buildman/buildman ${BMANARGS} $(sun4i_5i) | grep '^   ')"
-          built="$built $(tools/buildman/buildman ${BMANARGS} $(sun6i_sun7i) | grep '^   ')"
-          built="$built $(tools/buildman/buildman ${BMANARGS} $(sun8i) | grep '^   ')"
-          built="$built $(tools/buildman/buildman ${BMANARGS} $(sunxi_rest) | grep '^   ')"
-          built="$built $(tools/buildman/buildman ${BMANARGS} $(arm_catch_all) | grep '^   ')"
-          built="$built $(tools/buildman/buildman ${BMANARGS} $(aarch64_catch_all) | grep '^   ')"
-
-          # Finally see how many machines that is.
-          actual=$(tools/buildman/buildman ${BMANARGS} $built | grep "Total boards to build for each commit" | cut -d ' ' -f 8)
-          echo We would build a total of $actual out of $total platforms this CI run
-          [ $actual -eq $total ] && exit 0 || exit 1
-
-  - job: create_test_py_wrapper_script
-    displayName: 'Create and stage a wrapper for test.py runs'
-    pool:
-      vmImage: $(ubuntu_vm)
-    steps:
-      - checkout: none
-      - script: |
-          cat << EOF > test.sh
-          #!/bin/bash
-          set -ex
-          # the below corresponds to .gitlab-ci.yml "before_script"
-          cd \${WORK_DIR}
-          git config --global --add safe.directory \${WORK_DIR}
-          git clone --depth=1 https://github.com/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks
-          # qemu_arm64_lwip_defconfig is the same as qemu_arm64 but with NET_LWIP enabled.
-          # The test config and the boardenv file from qemu_arm64 can be re-used so create symlinks
-          ln -s conf.qemu_arm64 /tmp/uboot-test-hooks/bin/travis-ci/conf.qemu_arm64_lwip_na
-          ln -s u_boot_boardenv_qemu_arm64_na.py /tmp/uboot-test-hooks/py/travis-ci/u_boot_boardenv_qemu_arm64_lwip_na.py
-          ln -s travis-ci /tmp/uboot-test-hooks/bin/\`hostname\`
-          ln -s travis-ci /tmp/uboot-test-hooks/py/\`hostname\`
-          if [[ "\${TEST_PY_BD}" == "qemu-riscv32_spl" ]] || [[ "\${TEST_PY_BD}" == "xilinx_mbv32_smode" ]]; then
-              wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
-              export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
-          fi
-          if [[ "\${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "\${TEST_PY_BD}" == "sifive_unleashed" ]] || [[ "\${TEST_PY_BD}" == "xilinx_mbv64_smode" ]]; then
-              wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
-              export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
-          fi
-          if [[ "\${TEST_PY_BD}" == "qemu-arm-sbsa" ]]; then
-              wget -O /tmp/bl1.bin https://artifacts.codelinaro.org/artifactory/linaro-419-sbsa-ref/latest/tf-a/bl1.bin;
-              wget -O /tmp/fip.bin https://artifacts.codelinaro.org/artifactory/linaro-419-sbsa-ref/latest/tf-a/fip.bin;
-              export BINMAN_INDIRS=/tmp
-          fi
-          # the below corresponds to .gitlab-ci.yml "script"
-          cd \${WORK_DIR}
-          export UBOOT_TRAVIS_BUILD_DIR=/tmp/\${TEST_PY_BD}
-          if [ -n "\${BUILD_ENV}" ]; then
-              export \${BUILD_ENV};
-          fi
-          python3 -m venv /tmp/venv
-          . /tmp/venv/bin/activate
-          pip install -r tools/binman/requirements.txt \
-            -r tools/buildman/requirements.txt \
-            -r test/py/requirements.txt \
-            -r tools/u_boot_pylib/requirements.txt \
-            setuptools \
-            pytest-azurepipelines
-          tools/buildman/buildman -o \${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e --board \${TEST_PY_BD} \${OVERRIDE}
-          cp /opt/grub/grub_x86.efi \${UBOOT_TRAVIS_BUILD_DIR}/
-          cp /opt/grub/grub_x64.efi \${UBOOT_TRAVIS_BUILD_DIR}/
-          cp /opt/grub/grubriscv64.efi \${UBOOT_TRAVIS_BUILD_DIR}/grub_riscv64.efi
-          cp /opt/grub/grubaa64.efi \${UBOOT_TRAVIS_BUILD_DIR}/grub_arm64.efi
-          cp /opt/grub/grubarm.efi \${UBOOT_TRAVIS_BUILD_DIR}/grub_arm.efi
-          # create sdcard / spi-nor images for sifive unleashed using genimage
-          if [[ "\${TEST_PY_BD}" == "sifive_unleashed" ]]; then
-              mkdir -p root;
-              cp \${UBOOT_TRAVIS_BUILD_DIR}/spl/u-boot-spl.bin .;
-              cp \${UBOOT_TRAVIS_BUILD_DIR}/u-boot.itb .;
-              rm -rf tmp;
-              genimage --inputpath . --config board/sifive/unleashed/genimage_sdcard.cfg;
-              cp images/sdcard.img \${UBOOT_TRAVIS_BUILD_DIR}/;
-              rm -rf tmp;
-              genimage --inputpath . --config board/sifive/unleashed/genimage_spi-nor.cfg;
-              cp images/spi-nor.img \${UBOOT_TRAVIS_BUILD_DIR}/;
-          fi
-          if [[ "\${TEST_PY_BD}" == "coreboot" ]]; then
-              cp /opt/coreboot/coreboot.rom \${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom;
-              /opt/coreboot/cbfstool \${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom remove -n fallback/payload;
-              /opt/coreboot/cbfstool \${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f \${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
-          fi
-          # If we have TF-A binaries, we need to use them.
-          tfa_dir=""
-          rm -f /tmp/fip.bin
-          rm -f /tmp/bl1.bin
-          if [[ -d /opt/tf-a/"\${TEST_PY_BD}\${TEST_PY_ID//--id /_}" ]]; then
-            tfa_dir="/opt/tf-a/\${TEST_PY_BD}\${TEST_PY_ID//--id /_}";
-          elif [[ -d /opt/tf-a/"\${TEST_PY_BD}" ]]; then
-            tfa_dir="/opt/tf-a/\${TEST_PY_BD}";
-          fi
-          if [[ -n "\$tfa_dir" ]]; then
-            cp "\$tfa_dir"/fip.bin "\$tfa_dir"/bl1.bin /tmp/;
-          fi
-          if [ -f /tmp/fip.bin ] && [ -f /tmp/bl1.bin ]; then
-            export fip=/tmp/fip.bin;
-            export bl1=/tmp/bl1.bin;
-            export PATH=/opt/Base_RevC_AEMvA_pkg/models/Linux64_GCC-9.3:\${PATH};
-          fi
-          export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:\${PATH}
-          export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci
-          python3 -m http.server 80 --directory "\${UBOOT_TRAVIS_BUILD_DIR}" > /dev/null 2>&1 &
-          HTTP_PID=\$!
-          sleep 1  # Give the server a moment to start
-          if ps -p \${HTTP_PID} > /dev/null; then
-            export HTTP_PID
-          else
-            unset HTTP_PID
-          fi
-          # "\${var:+"-k \$var"}" expands to "" if \$var is empty, "-k \$var" if not
-          ./test/py/test.py -ra -o cache_dir="\$UBOOT_TRAVIS_BUILD_DIR"/.pytest_cache --bd \${TEST_PY_BD} \${TEST_PY_ID} \${TEST_PY_EXTRA} \${TEST_PY_TEST_SPEC:+"-k \${TEST_PY_TEST_SPEC}"} --build-dir "\$UBOOT_TRAVIS_BUILD_DIR" --report-dir "\$UBOOT_TRAVIS_BUILD_DIR" --junitxml=\$(System.DefaultWorkingDirectory)/results.xml
-          # the below corresponds to .gitlab-ci.yml "after_script"
-          if [[ -n "\${HTTP_PID}" ]]; then
-            kill \${HTTP_PID};
-          fi
-          rm -rf /tmp/uboot-test-hooks /tmp/venv
-          EOF
-      - task: CopyFiles@2
-        displayName: 'Copy test.sh for later usage'
-        inputs:
-          contents: 'test.sh'
-          targetFolder: '$(Build.ArtifactStagingDirectory)'
-      - publish: '$(Build.ArtifactStagingDirectory)/test.sh'
-        displayName: 'Publish test.sh'
-        artifact: testsh
-
-- stage: test_py_sandbox
+- stage: test_py
   jobs:
-  - job: test_py_sandbox
-    displayName: 'test.py for sandbox'
+  - job: test_py
+    displayName: 'test.py'
     pool:
       vmImage: $(ubuntu_vm)
     strategy:
       matrix:
         sandbox:
           TEST_PY_BD: "sandbox"
-          TEST_PY_EXTRA: "--timing"
-          # addr2line in Ubuntu 'Noble' and later are broken.
-          TEST_PY_TEST_SPEC: "not event_dump"
-        sandbox_asan:
-          TEST_PY_BD: "sandbox"
-          OVERRIDE: "-a ASAN"
-          TEST_PY_TEST_SPEC: "version"
         sandbox_clang:
           TEST_PY_BD: "sandbox"
-          OVERRIDE: "-O clang-20"
-          # addr2line in Ubuntu 'Noble' and later are broken.
-          TEST_PY_TEST_SPEC: "not event_dump"
-        sandbox_clang_asan:
+          OVERRIDE: "-O clang-16"
+        sandbox_nolto:
           TEST_PY_BD: "sandbox"
-          OVERRIDE: "-O clang-20 -a ASAN"
-          TEST_PY_TEST_SPEC: "version"
-        sandbox64:
-          TEST_PY_BD: "sandbox64"
-        sandbox64_clang:
-          TEST_PY_BD: "sandbox64"
-          OVERRIDE: "-O clang-20"
-        sandbox64_lwip:
-          TEST_PY_BD: "sandbox64_lwip"
+          BUILD_ENV: "NO_LTO=1"
         sandbox_spl:
           TEST_PY_BD: "sandbox_spl"
           TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
@@ -423,63 +267,13 @@ stages:
         sandbox_noinst:
           TEST_PY_BD: "sandbox_noinst"
           TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
-        sandbox_noinst_load_fit_full:
-          TEST_PY_BD: "sandbox_noinst"
-          TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
-          OVERRIDE: "-a CONFIG_SPL_LOAD_FIT_FULL=y"
         sandbox_flattree:
           TEST_PY_BD: "sandbox_flattree"
         sandbox_trace:
           TEST_PY_BD: "sandbox"
           BUILD_ENV: "FTRACE=1 NO_LTO=1"
           TEST_PY_TEST_SPEC: "trace"
-          OVERRIDE: "-a CONFIG_TRACE=y -a CONFIG_TRACE_EARLY=y -a CONFIG_TRACE_EARLY_SIZE=0x01000000 -a CONFIG_TRACE_BUFFER_SIZE=0x02000000"
-    steps:
-      - download: current
-        artifact: testsh
-      - script: |
-          # make current directory writeable to uboot user inside the container
-          # as sandbox testing need create files like spi flash images, etc.
-          # (TODO: clean up this in the future)
-          chmod 777 .
-          chmod 755 $(Pipeline.Workspace)/testsh/test.sh
-          # Filesystem tests need extra docker args to run
-          set --
-          # mount -o loop needs the loop devices
-          if modprobe loop; then
-              for d in $(find /dev -maxdepth 1 -name 'loop*'); do
-                  set -- "$@" --device $d:$d
-              done
-          fi
-          # Needed for mount syscall (for guestmount as well)
-          set -- "$@" --cap-add SYS_ADMIN
-          # Default apparmor profile denies mounts
-          set -- "$@" --security-opt apparmor=unconfined
-          # Some tests using libguestfs-tools need the fuse device to run
-          docker run "$@" --device /dev/fuse:/dev/fuse \
-                         -v $PWD:$(work_dir) \
-                         -v $(Pipeline.Workspace):$(Pipeline.Workspace) \
-                         -v $(System.DefaultWorkingDirectory):$(System.DefaultWorkingDirectory) \
-                         -e WORK_DIR="${WORK_DIR}" \
-                         -e TEST_PY_BD="${TEST_PY_BD}" \
-                         -e TEST_PY_ID="${TEST_PY_ID}" \
-                         -e TEST_PY_TEST_SPEC="${TEST_PY_TEST_SPEC}" \
-                         -e OVERRIDE="${OVERRIDE}" \
-                         -e BUILD_ENV="${BUILD_ENV}" $(ci_runner_image) \
-                         $(Pipeline.Workspace)/testsh/test.sh
-      - task: PublishTestResults@2
-        inputs:
-          testResultsFormat: 'JUnit'
-          testResultsFiles: 'results.xml'
-
-- stage: test_py_qemu
-  jobs:
-  - job: test_py_qemu
-    displayName: 'test.py for QEMU platforms'
-    pool:
-      vmImage: $(ubuntu_vm)
-    strategy:
-      matrix:
+          OVERRIDE: "-a CONFIG_TRACE=y -a CONFIG_TRACE_EARLY=y -a CONFIG_TRACE_EARLY_SIZE=0x01000000"
         coreboot:
           TEST_PY_BD: "coreboot"
           TEST_PY_ID: "--id qemu"
@@ -487,17 +281,12 @@ stages:
         evb_ast2500:
           TEST_PY_BD: "evb-ast2500"
           TEST_PY_ID: "--id qemu"
-          TEST_PY_TEST_SPEC: "not sleep"
+        evb_ast2600:
+          TEST_PY_BD: "evb-ast2600"
+          TEST_PY_ID: "--id qemu"
         vexpress_ca9x4:
           TEST_PY_BD: "vexpress_ca9x4"
           TEST_PY_ID: "--id qemu"
-          TEST_PY_TEST_SPEC: "not sleep"
-        vexpress_fvp:
-          TEST_PY_BD: "vexpress_fvp"
-          TEST_PY_TEST_SPEC: "not sleep and not hostfs"
-        vexpress_fvp_bloblist:
-          TEST_PY_BD: "vexpress_fvp_bloblist"
-          TEST_PY_TEST_SPEC: "not sleep and not hostfs"
         integratorcp_cm926ejs:
           TEST_PY_BD: "integratorcp_cm926ejs"
           TEST_PY_ID: "--id qemu"
@@ -508,25 +297,11 @@ stages:
         qemu_arm64:
           TEST_PY_BD: "qemu_arm64"
           TEST_PY_TEST_SPEC: "not sleep"
-          OVERRIDE: "-a CONFIG_SEMIHOSTING=y"
-        qemu_arm64_lwip:
-          TEST_PY_BD: "qemu_arm64_lwip"
-          TEST_PY_TEST_SPEC: "test_net_dhcp or test_net_ping or test_net_tftpboot"
-        qemu_arm64_tfa_fw_handoff:
-          TEST_PY_BD: "qemu_arm64"
-          TEST_PY_ID: "--id fw_handoff_tfa_optee"
-          TEST_PY_TEST_SPEC: "test_fw_handoff"
-        qemu_arm_sbsa_ref:
-          TEST_PY_BD: "qemu-arm-sbsa"
-          TEST_PY_TEST_SPEC: "not sleep"
         qemu_m68k:
           TEST_PY_BD: "M5208EVBE"
           TEST_PY_ID: "--id qemu"
           TEST_PY_TEST_SPEC: "not sleep and not efi"
           OVERRIDE: "-a CONFIG_M68K_QEMU=y -a ~CONFIG_MCFTMR"
-        qemu_m68k_virt:
-          TEST_PY_BD: "qemu-m68k"
-          TEST_PY_TEST_SPEC: "not sleep"
         qemu_malta:
           TEST_PY_BD: "malta"
           TEST_PY_ID: "--id qemu"
@@ -558,62 +333,30 @@ stages:
         qemu_riscv64_spl:
           TEST_PY_BD: "qemu-riscv64_spl"
           TEST_PY_TEST_SPEC: "not sleep"
-        qemu_riscv64_smode:
-          TEST_PY_BD: "qemu-riscv64_smode"
-          TEST_PY_TEST_SPEC: "not sleep"
-        qemu_riscv64_smode_acpi:
-          TEST_PY_BD: "qemu-riscv64_smode_acpi"
-          TEST_PY_TEST_SPEC: "not sleep"
         qemu_x86:
           TEST_PY_BD: "qemu-x86"
           TEST_PY_TEST_SPEC: "not sleep"
         qemu_x86_64:
           TEST_PY_BD: "qemu-x86_64"
           TEST_PY_TEST_SPEC: "not sleep"
-        qemu_xtensa_dc233c:
-          TEST_PY_BD: "qemu-xtensa-dc233c"
-          TEST_PY_TEST_SPEC: "not sleep and not efi"
         r2dplus_i82557c:
           TEST_PY_BD: "r2dplus"
           TEST_PY_ID: "--id i82557c_qemu"
-          TEST_PY_TEST_SPEC: "not sleep"
         r2dplus_pcnet:
           TEST_PY_BD: "r2dplus"
           TEST_PY_ID: "--id pcnet_qemu"
-          TEST_PY_TEST_SPEC: "not sleep"
         r2dplus_rtl8139:
           TEST_PY_BD: "r2dplus"
           TEST_PY_ID: "--id rtl8139_qemu"
-          TEST_PY_TEST_SPEC: "not sleep"
         r2dplus_tulip:
           TEST_PY_BD: "r2dplus"
           TEST_PY_ID: "--id tulip_qemu"
-          TEST_PY_TEST_SPEC: "not sleep"
-# This is broken upsteam: https://gitlab.com/qemu-project/qemu/-/issues/2945
-#        sifive_unleashed_sdcard:
-#          TEST_PY_BD: "sifive_unleashed"
-#          TEST_PY_ID: "--id sdcard_qemu"
-#          TEST_PY_TEST_SPEC: "not sleep"
+        sifive_unleashed_sdcard:
+          TEST_PY_BD: "sifive_unleashed"
+          TEST_PY_ID: "--id sdcard_qemu"
         sifive_unleashed_spi-nor:
           TEST_PY_BD: "sifive_unleashed"
           TEST_PY_ID: "--id spi-nor_qemu"
-          TEST_PY_TEST_SPEC: "not sleep"
-        xilinx_mbv32:
-          TEST_PY_BD: "xilinx_mbv32"
-          TEST_PY_ID: "--id qemu"
-          TEST_PY_TEST_SPEC: "not sleep"
-        xilinx_mbv32_smode test.py:
-          TEST_PY_BD: "xilinx_mbv32_smode"
-          TEST_PY_ID: "--id qemu"
-          TEST_PY_TEST_SPEC: "not sleep"
-        xilinx_mbv64 test.py:
-          TEST_PY_BD: "xilinx_mbv64"
-          TEST_PY_ID: "--id qemu"
-          TEST_PY_TEST_SPEC: "not sleep"
-        xilinx_mbv64_smode test.py:
-          TEST_PY_BD: "xilinx_mbv64_smode"
-          TEST_PY_ID: "--id qemu"
-          TEST_PY_TEST_SPEC: "not sleep"
         xilinx_zynq_virt:
           TEST_PY_BD: "xilinx_zynq_virt"
           TEST_PY_ID: "--id qemu"
@@ -622,119 +365,226 @@ stages:
           TEST_PY_BD: "xilinx_versal_virt"
           TEST_PY_ID: "--id qemu"
           TEST_PY_TEST_SPEC: "not sleep"
-          OVERRIDE: "-a ~CONFIG_USB_DWC3"
         xtfpga:
           TEST_PY_BD: "xtfpga"
           TEST_PY_ID: "--id qemu"
           TEST_PY_TEST_SPEC: "not sleep"
     steps:
-      - download: current
-        artifact: testsh
       - script: |
+          cat << EOF > test.sh
+          set -ex
+          # make environment variables available as tests are running inside a container
+          export WORK_DIR="${WORK_DIR}"
+          export TEST_PY_BD="${TEST_PY_BD}"
+          export TEST_PY_ID="${TEST_PY_ID}"
+          export TEST_PY_TEST_SPEC="${TEST_PY_TEST_SPEC}"
+          export OVERRIDE="${OVERRIDE}"
+          export BUILD_ENV="${BUILD_ENV}"
+          EOF
+          cat << "EOF" >> test.sh
+          # the below corresponds to .gitlab-ci.yml "before_script"
+          cd ${WORK_DIR}
+          git config --global --add safe.directory ${WORK_DIR}
+          git clone --depth=1 https://source.denx.de/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks
+          ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
+          ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
+          grub-mkimage --prefix=\"\" -o ~/grub_x86.efi -O i386-efi normal  echo lsefimmap lsefi lsefisystab efinet tftp minicmd
+          grub-mkimage --prefix=\"\" -o ~/grub_x64.efi -O x86_64-efi normal  echo lsefimmap lsefi lsefisystab efinet tftp minicmd
+          if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
+              wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
+              export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
+          fi
+          if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
+              wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
+              export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
+          fi
+          # the below corresponds to .gitlab-ci.yml "script"
+          cd ${WORK_DIR}
+          export UBOOT_TRAVIS_BUILD_DIR=/tmp/${TEST_PY_BD};
+          if [ -n "${BUILD_ENV}" ]; then
+              export ${BUILD_ENV};
+          fi
+          tools/buildman/buildman -o ${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e --board ${TEST_PY_BD} ${OVERRIDE}
+          cp ~/grub_x86.efi ${UBOOT_TRAVIS_BUILD_DIR}/
+          cp ~/grub_x64.efi ${UBOOT_TRAVIS_BUILD_DIR}/
+          cp /opt/grub/grubriscv64.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_riscv64.efi
+          cp /opt/grub/grubaa64.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_arm64.efi
+          cp /opt/grub/grubarm.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_arm.efi
+          # create sdcard / spi-nor images for sifive unleashed using genimage
+          if [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
+              mkdir -p root;
+              cp ${UBOOT_TRAVIS_BUILD_DIR}/spl/u-boot-spl.bin .;
+              cp ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.itb .;
+              rm -rf tmp;
+              genimage --inputpath . --config board/sifive/unleashed/genimage_sdcard.cfg;
+              cp images/sdcard.img ${UBOOT_TRAVIS_BUILD_DIR}/;
+              rm -rf tmp;
+              genimage --inputpath . --config board/sifive/unleashed/genimage_spi-nor.cfg;
+              cp images/spi-nor.img ${UBOOT_TRAVIS_BUILD_DIR}/;
+          fi
+          if [[ "${TEST_PY_BD}" == "coreboot" ]]; then
+              wget -O - "https://drive.google.com/uc?id=1x6nrtWIyIRPLS2cQBwYTnT2TbOI8UjmM&export=download" |xz -dc >${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom;
+              wget -O - "https://drive.google.com/uc?id=149Cz-5SZXHNKpi9xg6R_5XITWohu348y&export=download" >cbfstool;
+              chmod a+x cbfstool;
+              ./cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
+          fi
+          virtualenv -p /usr/bin/python3 /tmp/venv
+          . /tmp/venv/bin/activate
+          pip install -r test/py/requirements.txt
+          pip install pytest-azurepipelines
+          export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:${PATH};
+          export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci;
+          # "${var:+"-k $var"}" expands to "" if $var is empty, "-k $var" if not
+          ./test/py/test.py -ra -o cache_dir="$UBOOT_TRAVIS_BUILD_DIR"/.pytest_cache --bd ${TEST_PY_BD} ${TEST_PY_ID} ${TEST_PY_TEST_SPEC:+"-k ${TEST_PY_TEST_SPEC}"} --build-dir "$UBOOT_TRAVIS_BUILD_DIR" --report-dir "$UBOOT_TRAVIS_BUILD_DIR";
+          # the below corresponds to .gitlab-ci.yml "after_script"
+          rm -rf /tmp/uboot-test-hooks /tmp/venv
+          EOF
+          cat test.sh
           # make current directory writeable to uboot user inside the container
           # as sandbox testing need create files like spi flash images, etc.
           # (TODO: clean up this in the future)
           chmod 777 .
-          chmod 755 $(Pipeline.Workspace)/testsh/test.sh
+          # Filesystem tests need extra docker args to run
+          set --
+          if [[ "${TEST_PY_BD}" == "sandbox" ]]; then
+              # mount -o loop needs the loop devices
+              if modprobe loop; then
+                  for d in $(find /dev -maxdepth 1 -name 'loop*'); do
+                      set -- "$@" --device $d:$d
+                  done
+              fi
+              # Needed for mount syscall (for guestmount as well)
+              set -- "$@" --cap-add SYS_ADMIN
+              # Default apparmor profile denies mounts
+              set -- "$@" --security-opt apparmor=unconfined
+          fi
           # Some tests using libguestfs-tools need the fuse device to run
-          docker run "$@" --device /dev/fuse:/dev/fuse \
-                         -v $PWD:$(work_dir) \
-                         -v $(Pipeline.Workspace):$(Pipeline.Workspace) \
-                         -v $(System.DefaultWorkingDirectory):$(System.DefaultWorkingDirectory) \
-                         -e WORK_DIR="${WORK_DIR}" \
-                         -e TEST_PY_BD="${TEST_PY_BD}" \
-                         -e TEST_PY_ID="${TEST_PY_ID}" \
-                         -e TEST_PY_TEST_SPEC="${TEST_PY_TEST_SPEC}" \
-                         -e OVERRIDE="${OVERRIDE}" \
-                         -e BUILD_ENV="${BUILD_ENV}" $(ci_runner_image) \
-                         $(Pipeline.Workspace)/testsh/test.sh
-        retryCountOnTaskFailure: 2 # QEMU may be too slow, etc.
-      - task: PublishTestResults@2
-        inputs:
-          testResultsFormat: 'JUnit'
-          testResultsFiles: 'results.xml'
+          docker run "$@" --device /dev/fuse:/dev/fuse -v $PWD:$(work_dir) $(ci_runner_image) /bin/bash $(work_dir)/test.sh
 
 - stage: world_build
   jobs:
   - job: build_the_world
-    timeoutInMinutes: 0 # Use the maximum allowed
     displayName: 'Build the World'
     pool:
       vmImage: $(ubuntu_vm)
-    container:
-      image: $(ci_runner_image)
-      options: $(container_option)
     strategy:
-      # We split the world up in to 10 jobs as we can have at most 10
-      # parallel jobs going on the free tier of Azure.
+      # Use almost the same target division in .travis.yml, only merged
+      # 3 small build jobs (arc/microblaze/xtensa) into one.
       matrix:
-        am33xx_kirkwood:
-          BUILDMAN: $(am33xx_kirkwood)
-        amd:
-          BUILDMAN: $(amd)
-        amlogic_bcm:
-          BUILDMAN: $(amlogic_bcm)
-        atmel:
-          BUILDMAN: $(atmel)
-        engicam_renesas:
-          BUILDMAN: $(engicam_renesas)
-        k3_32b:
-          BUILDMAN: $(k3_32b)
-        k3_64b:
-          BUILDMAN: $(k3_64b)
-        kirkwood_mvebu:
-          BUILDMAN: $(kirkwood_mvebu)
-        layerscape_vf610:
-          BUILDMAN: $(layerscape_vf610)
-        m68k_remaining_mx_xtensa:
-          BUILDMAN: $(m68k_remaining_mx_xtensa)
-        mips_x86:
-          BUILDMAN: $(mips_x86)
-        mx6:
-          BUILDMAN: $(mx6)
-        imx8:
-          BUILDMAN: $(imx8)
-        imx9_arc_nios2_socfpga:
-          BUILDMAN: $(imx9_arc_nios2_socfpga)
-        phytec_toradex:
-          BUILDMAN: $(phytec_toradex)
-        powerpc:
-          BUILDMAN: $(powerpc)
-        riscv_stm32:
-          BUILDMAN: $(riscv_stm32)
-        rk3399:
-          BUILDMAN: $(rk3399)
-        rk352x_rk358x:
-          BUILDMAN: $(rk352x_rk358x)
-        rk356x_rk357x:
-          BUILDMAN: $(rk356x_rk357x)
-        rk3xxx_rest:
-          BUILDMAN: $(rk3xxx_rest)
-        sandbox_tegra:
-          BUILDMAN: $(sandbox_tegra)
-        samsung_omap_mediatek:
-          BUILDMAN: $(samsung_omap_mediatek)
-        sun4i_5i:
-          BUILDMAN: $(sun4i_5i)
-        sun6i_sun7i:
-          BUILDMAN: $(sun6i_sun7i)
-        sun8i:
-          BUILDMAN: $(sun8i)
-        sunxi_rest:
-          BUILDMAN: $(sunxi_rest)
+        arc_microblaze_xtensa:
+          BUILDMAN: "arc microblaze xtensa"
+        amlogic:
+          BUILDMAN: "amlogic"
+        arm11_arm7_arm920t_arm946es:
+          BUILDMAN: "arm11 arm7 arm920t arm946es"
+        arm926ejs:
+          BUILDMAN: "arm926ejs -x freescale,siemens,at91,kirkwood,omap"
+        at91_non_armv7:
+          BUILDMAN: "at91 -x armv7"
+        at91_non_arm926ejs:
+          BUILDMAN: "at91 -x arm926ejs"
+        boundary_engicam_toradex:
+          BUILDMAN: "boundary engicam toradex"
+        arm_bcm:
+          BUILDMAN: "bcm -x mips"
+        nxp_arm32:
+          BUILDMAN: "freescale -x powerpc,m68k,aarch64,ls101,ls102,ls104,ls108,ls20,lx216"
+        nxp_ls101x:
+          BUILDMAN: "freescale&ls101"
+        nxp_ls102x:
+          BUILDMAN: "freescale&ls102 -x keymile"
+        nxp_ls104x:
+          BUILDMAN: "freescale&ls104"
+        nxp_ls108x:
+          BUILDMAN: "freescale&ls108"
+        nxp_ls20xx:
+          BUILDMAN: "freescale&ls20"
+        nxp_lx216x:
+          BUILDMAN: "freescale&lx216"
+        imx6:
+          BUILDMAN: "mx6 -x boundary,engicam,freescale,technexion,toradex"
+        imx:
+          BUILDMAN: "mx -x mx6,imx8,freescale,technexion,toradex"
+        imx8_imx9:
+          BUILDMAN: "imx8 imx9"
+        keymile:
+          BUILDMAN: "keymile"
+        keystone2_keystone3:
+          BUILDMAN: "k2 k3"
+        sandbox_asan:
+          BUILDMAN: "sandbox"
+          OVERRIDE: "-a ASAN"
+        sandbox_clang_asan:
+          BUILDMAN: "sandbox"
+          OVERRIDE: "-O clang-16 -a ASAN"
+        samsung_socfpga:
+          BUILDMAN: "samsung socfpga"
+        sun4i:
+          BUILDMAN: "sun4i"
+        sun5i:
+          BUILDMAN: "sun5i"
+        sun6i:
+          BUILDMAN: "sun6i"
+        sun7i:
+          BUILDMAN: "sun7i"
+        sun8i_32bit:
+          BUILDMAN: "sun8i&armv7"
+        sun8i_64bit:
+          BUILDMAN: "sun8i&aarch64"
+        sun9i:
+          BUILDMAN: "sun9i"
+        sun50i:
+          BUILDMAN: "sun50i"
         arm_catch_all:
-          BUILDMAN: $(arm_catch_all)
+          BUILDMAN: "arm -x arm11,arm7,arm9,aarch64,at91,bcm,freescale,kirkwood,mvebu,renesas,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap,rk,toradex,socfpga,k2,k3,zynq"
+        sandbox_x86:
+          BUILDMAN: "sandbox x86"
+        technexion:
+          BUILDMAN: "technexion"
+        kirkwood:
+          BUILDMAN: "kirkwood"
+        mvebu:
+          BUILDMAN: "mvebu"
+        m68k:
+          BUILDMAN: "m68k"
+        mips:
+          BUILDMAN: "mips"
+        powerpc:
+          BUILDMAN: "powerpc -x keymile"
+        siemens:
+          BUILDMAN: "siemens"
+        tegra:
+          BUILDMAN: "tegra -x toradex"
+        am33xx_no_siemens:
+          BUILDMAN: "am33xx -x siemens"
+        omap:
+          BUILDMAN: "omap"
+        uniphier:
+          BUILDMAN: "uniphier"
         aarch64_catch_all:
-          BUILDMAN: $(aarch64_catch_all)
+          BUILDMAN: "aarch64 -x amlogic,bcm,imx8,imx9,k3,tegra,ls1,ls2,lx216,mvebu,uniphier,renesas,sunxi,samsung,socfpga,rk,versal,zynq"
+        rockchip_32bit:
+          BUILDMAN: "rk -x aarch64"
+        rockchip_64bit:
+          BUILDMAN: "rk&aarch64"
+        renesas:
+          BUILDMAN: "renesas"
+        zynq:
+          BUILDMAN: "zynq&armv7"
+        zynqmp_versal:
+          BUILDMAN: "versal|zynqmp&aarch64"
+        riscv:
+          BUILDMAN: "riscv"
     steps:
       - script: |
+          cat << EOF > build.sh
           set -ex
-          # Setup venv, perform build
-          python3 -m venv /tmp/venv
-          . /tmp/venv/bin/activate
-          pip install -r tools/binman/requirements.txt \
-            -r tools/buildman/requirements.txt \
-            setuptools
+          cd ${WORK_DIR}
+          # make environment variables available as tests are running inside a container
+          export BUILDMAN="${BUILDMAN}"
+          git config --global --add safe.directory ${WORK_DIR}
+          EOF
+          cat << "EOF" >> build.sh
           if [[ "${BUILDMAN}" != "" ]]; then
               ret=0;
               tools/buildman/buildman -o /tmp -PEWM ${BUILDMAN} ${OVERRIDE} || ret=$?;
@@ -743,3 +593,6 @@ stages:
                   exit $ret;
               fi;
           fi
+          EOF
+          cat build.sh
+          docker run -v $PWD:$(work_dir) $(ci_runner_image) /bin/bash $(work_dir)/build.sh

.b4-config

@@ -1,11 +0,0 @@
-# Configuration for the `b4` tool
-# See https://b4.docs.kernel.org/en/latest/config.html
-
-[b4]
-    send-auto-to-cmd = scripts/get_maintainer.pl --nogit --nogit-fallback --nogit-chief-penguins --norolestats --nom
-    send-auto-cc-cmd = scripts/get_maintainer.pl --nogit-fallback --nogit-chief-penguins --norolestats --nol
-    # Patchwork integration. You still need to set pw-key to your API key
-    pw-url = https://patchwork.ozlabs.org/
-    pw-project = uboot
-    pw-review-state = under-review
-    pw-accept-state = accepted

.checkpatch.conf

@@ -19,9 +19,6 @@
 # Not Linux, so we don't recommend usleep_range() over udelay()
 --ignore USLEEP_RANGE
 
-# We also do not have a functionally different mdelay() and udelay()
---ignore LONG_UDELAY
-
 # Ignore networking block comment style
 --ignore NETWORKING_BLOCK_COMMENT_STYLE
 

.clang-format

@@ -1,855 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# clang-format configuration file. Intended for clang-format >= 11.
-#
-# For more information, see:
-#
-#   Documentation/dev-tools/clang-format.rst
-#   https://clang.llvm.org/docs/ClangFormat.html
-#   https://clang.llvm.org/docs/ClangFormatStyleOptions.html
-#
----
-AccessModifierOffset: -4
-AlignAfterOpenBracket: Align
-AlignConsecutiveAssignments: false
-AlignConsecutiveDeclarations: false
-AlignEscapedNewlines: Left
-AlignOperands: true
-AlignTrailingComments: false
-AllowAllParametersOfDeclarationOnNextLine: false
-AllowShortBlocksOnASingleLine: false
-AllowShortCaseLabelsOnASingleLine: false
-AllowShortFunctionsOnASingleLine: None
-AllowShortIfStatementsOnASingleLine: false
-AllowShortLoopsOnASingleLine: false
-AlwaysBreakAfterDefinitionReturnType: None
-AlwaysBreakAfterReturnType: None
-AlwaysBreakBeforeMultilineStrings: false
-AlwaysBreakTemplateDeclarations: false
-BinPackArguments: true
-BinPackParameters: true
-BraceWrapping:
-  AfterClass: false
-  AfterControlStatement: false
-  AfterEnum: false
-  AfterFunction: true
-  AfterNamespace: true
-  AfterObjCDeclaration: false
-  AfterStruct: false
-  AfterUnion: false
-  AfterExternBlock: false
-  BeforeCatch: false
-  BeforeElse: false
-  IndentBraces: false
-  SplitEmptyFunction: true
-  SplitEmptyRecord: true
-  SplitEmptyNamespace: true
-BreakBeforeBinaryOperators: None
-BreakBeforeBraces: Custom
-BreakBeforeInheritanceComma: false
-BreakBeforeTernaryOperators: false
-BreakConstructorInitializersBeforeComma: false
-BreakConstructorInitializers: BeforeComma
-BreakAfterJavaFieldAnnotations: false
-BreakStringLiterals: false
-ColumnLimit: 80
-CommentPragmas: '^ IWYU pragma:'
-CompactNamespaces: false
-ConstructorInitializerAllOnOneLineOrOnePerLine: false
-ConstructorInitializerIndentWidth: 8
-ContinuationIndentWidth: 8
-Cpp11BracedListStyle: false
-DerivePointerAlignment: false
-DisableFormat: false
-ExperimentalAutoDetectBinPacking: false
-FixNamespaceComments: false
-
-# Taken from:
-#   git grep -h '^#define [^[:space:]]*for_each[^[:space:]]*(' include/ tools/ \
-#   | sed "s,^#define \([^[:space:]]*for_each[^[:space:]]*\)(.*$,  - '\1'," \
-#   | LC_ALL=C sort -u
-ForEachMacros:
-  - '__ata_qc_for_each'
-  - '__bio_for_each_bvec'
-  - '__bio_for_each_segment'
-  - '__evlist__for_each_entry'
-  - '__evlist__for_each_entry_continue'
-  - '__evlist__for_each_entry_from'
-  - '__evlist__for_each_entry_reverse'
-  - '__evlist__for_each_entry_safe'
-  - '__for_each_mem_range'
-  - '__for_each_mem_range_rev'
-  - '__for_each_thread'
-  - '__hlist_for_each_rcu'
-  - '__map__for_each_symbol_by_name'
-  - '__pci_bus_for_each_res0'
-  - '__pci_bus_for_each_res1'
-  - '__pci_dev_for_each_res0'
-  - '__pci_dev_for_each_res1'
-  - '__perf_evlist__for_each_entry'
-  - '__perf_evlist__for_each_entry_reverse'
-  - '__perf_evlist__for_each_entry_safe'
-  - '__rq_for_each_bio'
-  - '__shost_for_each_device'
-  - '__sym_for_each'
-  - '_for_each_counter'
-  - 'apei_estatus_for_each_section'
-  - 'ata_for_each_dev'
-  - 'ata_for_each_link'
-  - 'ata_qc_for_each'
-  - 'ata_qc_for_each_raw'
-  - 'ata_qc_for_each_with_internal'
-  - 'ax25_for_each'
-  - 'ax25_uid_for_each'
-  - 'bio_for_each_bvec'
-  - 'bio_for_each_bvec_all'
-  - 'bio_for_each_folio_all'
-  - 'bio_for_each_integrity_vec'
-  - 'bio_for_each_segment'
-  - 'bio_for_each_segment_all'
-  - 'bio_list_for_each'
-  - 'bip_for_each_vec'
-  - 'bond_for_each_slave'
-  - 'bond_for_each_slave_rcu'
-  - 'bpf_for_each'
-  - 'bpf_for_each_reg_in_vstate'
-  - 'bpf_for_each_reg_in_vstate_mask'
-  - 'bpf_for_each_spilled_reg'
-  - 'bpf_object__for_each_map'
-  - 'bpf_object__for_each_program'
-  - 'btree_for_each_safe128'
-  - 'btree_for_each_safe32'
-  - 'btree_for_each_safe64'
-  - 'btree_for_each_safel'
-  - 'card_for_each_dev'
-  - 'cgroup_taskset_for_each'
-  - 'cgroup_taskset_for_each_leader'
-  - 'cpu_aggr_map__for_each_idx'
-  - 'cpufreq_for_each_efficient_entry_idx'
-  - 'cpufreq_for_each_entry'
-  - 'cpufreq_for_each_entry_idx'
-  - 'cpufreq_for_each_valid_entry'
-  - 'cpufreq_for_each_valid_entry_idx'
-  - 'css_for_each_child'
-  - 'css_for_each_descendant_post'
-  - 'css_for_each_descendant_pre'
-  - 'damon_for_each_region'
-  - 'damon_for_each_region_from'
-  - 'damon_for_each_region_safe'
-  - 'damon_for_each_scheme'
-  - 'damon_for_each_scheme_safe'
-  - 'damon_for_each_target'
-  - 'damon_for_each_target_safe'
-  - 'damos_for_each_filter'
-  - 'damos_for_each_filter_safe'
-  - 'damos_for_each_ops_filter'
-  - 'damos_for_each_ops_filter_safe'
-  - 'damos_for_each_quota_goal'
-  - 'damos_for_each_quota_goal_safe'
-  - 'data__for_each_file'
-  - 'data__for_each_file_new'
-  - 'data__for_each_file_start'
-  - 'def_for_each_cpu'
-  - 'device_for_each_child_node'
-  - 'device_for_each_child_node_scoped'
-  - 'dma_fence_array_for_each'
-  - 'dma_fence_chain_for_each'
-  - 'dma_fence_unwrap_for_each'
-  - 'dma_resv_for_each_fence'
-  - 'dma_resv_for_each_fence_unlocked'
-  - 'do_for_each_ftrace_op'
-  - 'drm_atomic_crtc_for_each_plane'
-  - 'drm_atomic_crtc_state_for_each_plane'
-  - 'drm_atomic_crtc_state_for_each_plane_state'
-  - 'drm_atomic_for_each_plane_damage'
-  - 'drm_client_for_each_connector_iter'
-  - 'drm_client_for_each_modeset'
-  - 'drm_connector_for_each_possible_encoder'
-  - 'drm_exec_for_each_locked_object'
-  - 'drm_exec_for_each_locked_object_reverse'
-  - 'drm_for_each_bridge_in_chain'
-  - 'drm_for_each_connector_iter'
-  - 'drm_for_each_crtc'
-  - 'drm_for_each_crtc_reverse'
-  - 'drm_for_each_encoder'
-  - 'drm_for_each_encoder_mask'
-  - 'drm_for_each_fb'
-  - 'drm_for_each_legacy_plane'
-  - 'drm_for_each_plane'
-  - 'drm_for_each_plane_mask'
-  - 'drm_for_each_privobj'
-  - 'drm_gem_for_each_gpuvm_bo'
-  - 'drm_gem_for_each_gpuvm_bo_safe'
-  - 'drm_gpusvm_for_each_range'
-  - 'drm_gpuva_for_each_op'
-  - 'drm_gpuva_for_each_op_from_reverse'
-  - 'drm_gpuva_for_each_op_reverse'
-  - 'drm_gpuva_for_each_op_safe'
-  - 'drm_gpuvm_bo_for_each_va'
-  - 'drm_gpuvm_bo_for_each_va_safe'
-  - 'drm_gpuvm_for_each_va'
-  - 'drm_gpuvm_for_each_va_range'
-  - 'drm_gpuvm_for_each_va_range_safe'
-  - 'drm_gpuvm_for_each_va_safe'
-  - 'drm_mm_for_each_hole'
-  - 'drm_mm_for_each_node'
-  - 'drm_mm_for_each_node_in_range'
-  - 'drm_mm_for_each_node_safe'
-  - 'dsa_switch_for_each_available_port'
-  - 'dsa_switch_for_each_cpu_port'
-  - 'dsa_switch_for_each_cpu_port_continue_reverse'
-  - 'dsa_switch_for_each_port'
-  - 'dsa_switch_for_each_port_continue_reverse'
-  - 'dsa_switch_for_each_port_safe'
-  - 'dsa_switch_for_each_user_port'
-  - 'dsa_switch_for_each_user_port_continue_reverse'
-  - 'dsa_tree_for_each_cpu_port'
-  - 'dsa_tree_for_each_user_port'
-  - 'dsa_tree_for_each_user_port_continue_reverse'
-  - 'dso__for_each_symbol'
-  - 'elf_hash_for_each_possible'
-  - 'elf_symtab__for_each_symbol'
-  - 'evlist__for_each_cpu'
-  - 'evlist__for_each_entry'
-  - 'evlist__for_each_entry_continue'
-  - 'evlist__for_each_entry_from'
-  - 'evlist__for_each_entry_reverse'
-  - 'evlist__for_each_entry_safe'
-  - 'flow_action_for_each'
-  - 'for_each_acpi_consumer_dev'
-  - 'for_each_acpi_dev_match'
-  - 'for_each_active_dev_scope'
-  - 'for_each_active_drhd_unit'
-  - 'for_each_active_iommu'
-  - 'for_each_active_irq'
-  - 'for_each_active_route'
-  - 'for_each_aggr_pgid'
-  - 'for_each_alloc_capable_rdt_resource'
-  - 'for_each_and_bit'
-  - 'for_each_andnot_bit'
-  - 'for_each_available_child_of_node'
-  - 'for_each_available_child_of_node_scoped'
-  - 'for_each_bench'
-  - 'for_each_bio'
-  - 'for_each_board_func_rsrc'
-  - 'for_each_btf_ext_rec'
-  - 'for_each_btf_ext_sec'
-  - 'for_each_bvec'
-  - 'for_each_capable_rdt_resource'
-  - 'for_each_card_auxs'
-  - 'for_each_card_auxs_safe'
-  - 'for_each_card_components'
-  - 'for_each_card_dapms'
-  - 'for_each_card_pre_auxs'
-  - 'for_each_card_prelinks'
-  - 'for_each_card_rtds'
-  - 'for_each_card_rtds_safe'
-  - 'for_each_card_widgets'
-  - 'for_each_card_widgets_safe'
-  - 'for_each_cgroup_storage_type'
-  - 'for_each_child_of_node'
-  - 'for_each_child_of_node_scoped'
-  - 'for_each_child_of_node_with_prefix'
-  - 'for_each_clear_bit'
-  - 'for_each_clear_bit_from'
-  - 'for_each_clear_bitrange'
-  - 'for_each_clear_bitrange_from'
-  - 'for_each_cmd'
-  - 'for_each_cmsghdr'
-  - 'for_each_collection'
-  - 'for_each_comp_order'
-  - 'for_each_compatible_node'
-  - 'for_each_component_dais'
-  - 'for_each_component_dais_safe'
-  - 'for_each_conduit'
-  - 'for_each_console'
-  - 'for_each_console_srcu'
-  - 'for_each_cpu'
-  - 'for_each_cpu_and'
-  - 'for_each_cpu_andnot'
-  - 'for_each_cpu_from'
-  - 'for_each_cpu_or'
-  - 'for_each_cpu_wrap'
-  - 'for_each_dapm_widgets'
-  - 'for_each_dedup_cand'
-  - 'for_each_dev_addr'
-  - 'for_each_dev_scope'
-  - 'for_each_dma_cap_mask'
-  - 'for_each_dpcm_be'
-  - 'for_each_dpcm_be_rollback'
-  - 'for_each_dpcm_be_safe'
-  - 'for_each_dpcm_fe'
-  - 'for_each_drhd_unit'
-  - 'for_each_dss_dev'
-  - 'for_each_efi_memory_desc'
-  - 'for_each_efi_memory_desc_in_map'
-  - 'for_each_element'
-  - 'for_each_element_extid'
-  - 'for_each_element_id'
-  - 'for_each_enabled_cpu'
-  - 'for_each_endpoint_of_node'
-  - 'for_each_event'
-  - 'for_each_event_tps'
-  - 'for_each_evictable_lru'
-  - 'for_each_fib6_node_rt_rcu'
-  - 'for_each_fib6_walker_rt'
-  - 'for_each_file_lock'
-  - 'for_each_free_mem_pfn_range_in_zone_from'
-  - 'for_each_free_mem_range'
-  - 'for_each_free_mem_range_reverse'
-  - 'for_each_func_rsrc'
-  - 'for_each_gpiochip_node'
-  - 'for_each_group_evsel'
-  - 'for_each_group_evsel_head'
-  - 'for_each_group_member'
-  - 'for_each_group_member_head'
-  - 'for_each_hstate'
-  - 'for_each_hwgpio'
-  - 'for_each_hwgpio_in_range'
-  - 'for_each_if'
-  - 'for_each_inject_fn'
-  - 'for_each_insn'
-  - 'for_each_insn_op_loc'
-  - 'for_each_insn_prefix'
-  - 'for_each_intid'
-  - 'for_each_iommu'
-  - 'for_each_ip_tunnel_rcu'
-  - 'for_each_irq_desc'
-  - 'for_each_irq_nr'
-  - 'for_each_lang'
-  - 'for_each_link_ch_maps'
-  - 'for_each_link_codecs'
-  - 'for_each_link_cpus'
-  - 'for_each_link_platforms'
-  - 'for_each_lru'
-  - 'for_each_matching_node'
-  - 'for_each_matching_node_and_match'
-  - 'for_each_media_entity_data_link'
-  - 'for_each_mem_pfn_range'
-  - 'for_each_mem_range'
-  - 'for_each_mem_range_rev'
-  - 'for_each_mem_region'
-  - 'for_each_member'
-  - 'for_each_memory'
-  - 'for_each_migratetype_order'
-  - 'for_each_missing_reg'
-  - 'for_each_mle_subelement'
-  - 'for_each_mod_mem_type'
-  - 'for_each_mon_capable_rdt_resource'
-  - 'for_each_mp_bvec'
-  - 'for_each_net'
-  - 'for_each_net_continue_reverse'
-  - 'for_each_net_rcu'
-  - 'for_each_netdev'
-  - 'for_each_netdev_continue'
-  - 'for_each_netdev_continue_rcu'
-  - 'for_each_netdev_continue_reverse'
-  - 'for_each_netdev_dump'
-  - 'for_each_netdev_feature'
-  - 'for_each_netdev_in_bond_rcu'
-  - 'for_each_netdev_rcu'
-  - 'for_each_netdev_reverse'
-  - 'for_each_netdev_safe'
-  - 'for_each_new_connector_in_state'
-  - 'for_each_new_crtc_in_state'
-  - 'for_each_new_mst_mgr_in_state'
-  - 'for_each_new_plane_in_state'
-  - 'for_each_new_plane_in_state_reverse'
-  - 'for_each_new_private_obj_in_state'
-  - 'for_each_new_reg'
-  - 'for_each_nhlt_endpoint'
-  - 'for_each_nhlt_endpoint_fmtcfg'
-  - 'for_each_nhlt_fmtcfg'
-  - 'for_each_node'
-  - 'for_each_node_by_name'
-  - 'for_each_node_by_type'
-  - 'for_each_node_mask'
-  - 'for_each_node_numadist'
-  - 'for_each_node_state'
-  - 'for_each_node_with_cpus'
-  - 'for_each_node_with_property'
-  - 'for_each_nonreserved_multicast_dest_pgid'
-  - 'for_each_numa_hop_mask'
-  - 'for_each_of_allnodes'
-  - 'for_each_of_allnodes_from'
-  - 'for_each_of_cpu_node'
-  - 'for_each_of_graph_port'
-  - 'for_each_of_graph_port_endpoint'
-  - 'for_each_of_pci_range'
-  - 'for_each_old_connector_in_state'
-  - 'for_each_old_crtc_in_state'
-  - 'for_each_old_mst_mgr_in_state'
-  - 'for_each_old_plane_in_state'
-  - 'for_each_old_private_obj_in_state'
-  - 'for_each_oldnew_connector_in_state'
-  - 'for_each_oldnew_crtc_in_state'
-  - 'for_each_oldnew_mst_mgr_in_state'
-  - 'for_each_oldnew_plane_in_state'
-  - 'for_each_oldnew_plane_in_state_reverse'
-  - 'for_each_oldnew_private_obj_in_state'
-  - 'for_each_online_cpu'
-  - 'for_each_online_cpu_wrap'
-  - 'for_each_online_node'
-  - 'for_each_online_pgdat'
-  - 'for_each_or_bit'
-  - 'for_each_page_ext'
-  - 'for_each_path'
-  - 'for_each_pci_bridge'
-  - 'for_each_pci_dev'
-  - 'for_each_pcm_streams'
-  - 'for_each_physmem_range'
-  - 'for_each_populated_zone'
-  - 'for_each_possible_cpu'
-  - 'for_each_possible_cpu_wrap'
-  - 'for_each_present_blessed_reg'
-  - 'for_each_present_cpu'
-  - 'for_each_present_section_nr'
-  - 'for_each_prime_number'
-  - 'for_each_prime_number_from'
-  - 'for_each_probe_cache_entry'
-  - 'for_each_process'
-  - 'for_each_process_thread'
-  - 'for_each_prop_codec_conf'
-  - 'for_each_prop_dai_codec'
-  - 'for_each_prop_dai_cpu'
-  - 'for_each_prop_dlc_codecs'
-  - 'for_each_prop_dlc_cpus'
-  - 'for_each_prop_dlc_platforms'
-  - 'for_each_property_of_node'
-  - 'for_each_rdt_resource'
-  - 'for_each_reg'
-  - 'for_each_reg_filtered'
-  - 'for_each_reloc'
-  - 'for_each_reloc_from'
-  - 'for_each_requested_gpio'
-  - 'for_each_requested_gpio_in_range'
-  - 'for_each_reserved_child_of_node'
-  - 'for_each_reserved_mem_range'
-  - 'for_each_reserved_mem_region'
-  - 'for_each_rtd_ch_maps'
-  - 'for_each_rtd_codec_dais'
-  - 'for_each_rtd_components'
-  - 'for_each_rtd_cpu_dais'
-  - 'for_each_rtd_dais'
-  - 'for_each_rtd_dais_reverse'
-  - 'for_each_sband_iftype_data'
-  - 'for_each_script'
-  - 'for_each_sec'
-  - 'for_each_set_bit'
-  - 'for_each_set_bit_from'
-  - 'for_each_set_bit_wrap'
-  - 'for_each_set_bitrange'
-  - 'for_each_set_bitrange_from'
-  - 'for_each_set_clump8'
-  - 'for_each_sg'
-  - 'for_each_sg_dma_page'
-  - 'for_each_sg_page'
-  - 'for_each_sgtable_dma_page'
-  - 'for_each_sgtable_dma_sg'
-  - 'for_each_sgtable_page'
-  - 'for_each_sgtable_sg'
-  - 'for_each_sibling_event'
-  - 'for_each_sta_active_link'
-  - 'for_each_subelement'
-  - 'for_each_subelement_extid'
-  - 'for_each_subelement_id'
-  - 'for_each_sublist'
-  - 'for_each_subsystem'
-  - 'for_each_suite'
-  - 'for_each_supported_activate_fn'
-  - 'for_each_supported_inject_fn'
-  - 'for_each_sym'
-  - 'for_each_thread'
-  - 'for_each_token'
-  - 'for_each_unicast_dest_pgid'
-  - 'for_each_valid_link'
-  - 'for_each_vif_active_link'
-  - 'for_each_vma'
-  - 'for_each_vma_range'
-  - 'for_each_vsi'
-  - 'for_each_wakeup_source'
-  - 'for_each_zone'
-  - 'for_each_zone_zonelist'
-  - 'for_each_zone_zonelist_nodemask'
-  - 'func_for_each_insn'
-  - 'fwnode_for_each_available_child_node'
-  - 'fwnode_for_each_child_node'
-  - 'fwnode_for_each_parent_node'
-  - 'fwnode_graph_for_each_endpoint'
-  - 'gadget_for_each_ep'
-  - 'genradix_for_each'
-  - 'genradix_for_each_from'
-  - 'genradix_for_each_reverse'
-  - 'hash_for_each'
-  - 'hash_for_each_possible'
-  - 'hash_for_each_possible_rcu'
-  - 'hash_for_each_possible_rcu_notrace'
-  - 'hash_for_each_possible_safe'
-  - 'hash_for_each_rcu'
-  - 'hash_for_each_safe'
-  - 'hashmap__for_each_entry'
-  - 'hashmap__for_each_entry_safe'
-  - 'hashmap__for_each_key_entry'
-  - 'hashmap__for_each_key_entry_safe'
-  - 'hctx_for_each_ctx'
-  - 'hists__for_each_format'
-  - 'hists__for_each_sort_list'
-  - 'hlist_bl_for_each_entry'
-  - 'hlist_bl_for_each_entry_rcu'
-  - 'hlist_bl_for_each_entry_safe'
-  - 'hlist_for_each'
-  - 'hlist_for_each_entry'
-  - 'hlist_for_each_entry_continue'
-  - 'hlist_for_each_entry_continue_rcu'
-  - 'hlist_for_each_entry_continue_rcu_bh'
-  - 'hlist_for_each_entry_from'
-  - 'hlist_for_each_entry_from_rcu'
-  - 'hlist_for_each_entry_rcu'
-  - 'hlist_for_each_entry_rcu_bh'
-  - 'hlist_for_each_entry_rcu_notrace'
-  - 'hlist_for_each_entry_safe'
-  - 'hlist_for_each_entry_srcu'
-  - 'hlist_for_each_safe'
-  - 'hlist_nulls_for_each_entry'
-  - 'hlist_nulls_for_each_entry_from'
-  - 'hlist_nulls_for_each_entry_rcu'
-  - 'hlist_nulls_for_each_entry_safe'
-  - 'i3c_bus_for_each_i2cdev'
-  - 'i3c_bus_for_each_i3cdev'
-  - 'idr_for_each_entry'
-  - 'idr_for_each_entry_continue'
-  - 'idr_for_each_entry_continue_ul'
-  - 'idr_for_each_entry_ul'
-  - 'iio_for_each_active_channel'
-  - 'in_dev_for_each_ifa_rcu'
-  - 'in_dev_for_each_ifa_rtnl'
-  - 'in_dev_for_each_ifa_rtnl_net'
-  - 'inet_bind_bucket_for_each'
-  - 'interval_tree_for_each_span'
-  - 'intlist__for_each_entry'
-  - 'intlist__for_each_entry_safe'
-  - 'kcore_copy__for_each_phdr'
-  - 'key_for_each'
-  - 'key_for_each_safe'
-  - 'klp_for_each_func'
-  - 'klp_for_each_func_safe'
-  - 'klp_for_each_func_static'
-  - 'klp_for_each_object'
-  - 'klp_for_each_object_safe'
-  - 'klp_for_each_object_static'
-  - 'kunit_suite_for_each_test_case'
-  - 'kvm_for_each_memslot'
-  - 'kvm_for_each_memslot_in_gfn_range'
-  - 'kvm_for_each_vcpu'
-  - 'libbpf_nla_for_each_attr'
-  - 'list_for_each'
-  - 'list_for_each_codec'
-  - 'list_for_each_codec_safe'
-  - 'list_for_each_continue'
-  - 'list_for_each_entry'
-  - 'list_for_each_entry_continue'
-  - 'list_for_each_entry_continue_rcu'
-  - 'list_for_each_entry_continue_reverse'
-  - 'list_for_each_entry_from'
-  - 'list_for_each_entry_from_rcu'
-  - 'list_for_each_entry_from_reverse'
-  - 'list_for_each_entry_lockless'
-  - 'list_for_each_entry_rcu'
-  - 'list_for_each_entry_reverse'
-  - 'list_for_each_entry_safe'
-  - 'list_for_each_entry_safe_continue'
-  - 'list_for_each_entry_safe_from'
-  - 'list_for_each_entry_safe_reverse'
-  - 'list_for_each_entry_srcu'
-  - 'list_for_each_from'
-  - 'list_for_each_prev'
-  - 'list_for_each_prev_safe'
-  - 'list_for_each_rcu'
-  - 'list_for_each_safe'
-  - 'llist_for_each'
-  - 'llist_for_each_entry'
-  - 'llist_for_each_entry_safe'
-  - 'llist_for_each_safe'
-  - 'lwq_for_each_safe'
-  - 'map__for_each_symbol'
-  - 'map__for_each_symbol_by_name'
-  - 'mas_for_each'
-  - 'mas_for_each_rev'
-  - 'mci_for_each_dimm'
-  - 'media_device_for_each_entity'
-  - 'media_device_for_each_intf'
-  - 'media_device_for_each_link'
-  - 'media_device_for_each_pad'
-  - 'media_entity_for_each_pad'
-  - 'media_pipeline_for_each_entity'
-  - 'media_pipeline_for_each_pad'
-  - 'mlx5_lag_for_each_peer_mdev'
-  - 'mptcp_for_each_subflow'
-  - 'msi_domain_for_each_desc'
-  - 'msi_for_each_desc'
-  - 'mt_for_each'
-  - 'nanddev_io_for_each_block'
-  - 'nanddev_io_for_each_page'
-  - 'neigh_for_each_in_bucket'
-  - 'neigh_for_each_in_bucket_rcu'
-  - 'neigh_for_each_in_bucket_safe'
-  - 'netdev_for_each_lower_dev'
-  - 'netdev_for_each_lower_private'
-  - 'netdev_for_each_lower_private_rcu'
-  - 'netdev_for_each_mc_addr'
-  - 'netdev_for_each_synced_mc_addr'
-  - 'netdev_for_each_synced_uc_addr'
-  - 'netdev_for_each_uc_addr'
-  - 'netdev_for_each_upper_dev_rcu'
-  - 'netdev_hw_addr_list_for_each'
-  - 'nft_rule_for_each_expr'
-  - 'nla_for_each_attr'
-  - 'nla_for_each_attr_type'
-  - 'nla_for_each_nested'
-  - 'nla_for_each_nested_type'
-  - 'nlmsg_for_each_attr'
-  - 'nlmsg_for_each_msg'
-  - 'nr_neigh_for_each'
-  - 'nr_neigh_for_each_safe'
-  - 'nr_node_for_each'
-  - 'nr_node_for_each_safe'
-  - 'of_for_each_phandle'
-  - 'of_property_for_each_string'
-  - 'of_property_for_each_u32'
-  - 'pci_bus_for_each_resource'
-  - 'pci_dev_for_each_resource'
-  - 'pcl_for_each_chunk'
-  - 'pcl_for_each_segment'
-  - 'pcm_for_each_format'
-  - 'perf_config_items__for_each_entry'
-  - 'perf_config_sections__for_each_entry'
-  - 'perf_config_set__for_each_entry'
-  - 'perf_cpu_map__for_each_cpu'
-  - 'perf_cpu_map__for_each_cpu_skip_any'
-  - 'perf_cpu_map__for_each_idx'
-  - 'perf_evlist__for_each_entry'
-  - 'perf_evlist__for_each_entry_reverse'
-  - 'perf_evlist__for_each_entry_safe'
-  - 'perf_evlist__for_each_evsel'
-  - 'perf_evlist__for_each_mmap'
-  - 'perf_evsel_for_each_per_thread_period_safe'
-  - 'perf_hpp_list__for_each_format'
-  - 'perf_hpp_list__for_each_format_safe'
-  - 'perf_hpp_list__for_each_sort_list'
-  - 'perf_hpp_list__for_each_sort_list_safe'
-  - 'plist_for_each'
-  - 'plist_for_each_continue'
-  - 'plist_for_each_entry'
-  - 'plist_for_each_entry_continue'
-  - 'plist_for_each_entry_safe'
-  - 'plist_for_each_safe'
-  - 'pnp_for_each_card'
-  - 'pnp_for_each_dev'
-  - 'protocol_for_each_card'
-  - 'protocol_for_each_dev'
-  - 'queue_for_each_hw_ctx'
-  - 'radix_tree_for_each_slot'
-  - 'radix_tree_for_each_tagged'
-  - 'rb_for_each'
-  - 'rbtree_postorder_for_each_entry_safe'
-  - 'rdma_for_each_block'
-  - 'rdma_for_each_port'
-  - 'rdma_umem_for_each_dma_block'
-  - 'resource_list_for_each_entry'
-  - 'resource_list_for_each_entry_safe'
-  - 'rhl_for_each_entry_rcu'
-  - 'rhl_for_each_rcu'
-  - 'rht_for_each'
-  - 'rht_for_each_entry'
-  - 'rht_for_each_entry_from'
-  - 'rht_for_each_entry_rcu'
-  - 'rht_for_each_entry_rcu_from'
-  - 'rht_for_each_entry_safe'
-  - 'rht_for_each_from'
-  - 'rht_for_each_rcu'
-  - 'rht_for_each_rcu_from'
-  - 'rq_for_each_bvec'
-  - 'rq_for_each_segment'
-  - 'rq_list_for_each'
-  - 'rq_list_for_each_safe'
-  - 'sample_read_group__for_each'
-  - 'scsi_for_each_prot_sg'
-  - 'scsi_for_each_sg'
-  - 'sctp_for_each_hentry'
-  - 'sctp_skb_for_each'
-  - 'sec_for_each_insn'
-  - 'sec_for_each_insn_continue'
-  - 'sec_for_each_insn_from'
-  - 'sec_for_each_sym'
-  - 'shdma_for_each_chan'
-  - 'shost_for_each_device'
-  - 'sk_for_each'
-  - 'sk_for_each_bound'
-  - 'sk_for_each_bound_safe'
-  - 'sk_for_each_entry_offset_rcu'
-  - 'sk_for_each_from'
-  - 'sk_for_each_rcu'
-  - 'sk_for_each_safe'
-  - 'sk_nulls_for_each'
-  - 'sk_nulls_for_each_from'
-  - 'sk_nulls_for_each_rcu'
-  - 'snd_array_for_each'
-  - 'snd_pcm_group_for_each_entry'
-  - 'snd_soc_dapm_widget_for_each_path'
-  - 'snd_soc_dapm_widget_for_each_path_safe'
-  - 'snd_soc_dapm_widget_for_each_sink_path'
-  - 'snd_soc_dapm_widget_for_each_source_path'
-  - 'sparsebit_for_each_set_range'
-  - 'strlist__for_each_entry'
-  - 'strlist__for_each_entry_safe'
-  - 'sym_for_each_insn'
-  - 'sym_for_each_insn_continue_reverse'
-  - 'symbols__for_each_entry'
-  - 'tb_property_for_each'
-  - 'tcf_act_for_each_action'
-  - 'tcf_exts_for_each_action'
-  - 'test_suite__for_each_test_case'
-  - 'tool_pmu__for_each_event'
-  - 'ttm_bo_lru_for_each_reserved_guarded'
-  - 'ttm_resource_manager_for_each_res'
-  - 'udp_lrpa_for_each_entry_rcu'
-  - 'udp_portaddr_for_each_entry'
-  - 'udp_portaddr_for_each_entry_rcu'
-  - 'usb_hub_for_each_child'
-  - 'v4l2_device_for_each_subdev'
-  - 'v4l2_m2m_for_each_dst_buf'
-  - 'v4l2_m2m_for_each_dst_buf_safe'
-  - 'v4l2_m2m_for_each_src_buf'
-  - 'v4l2_m2m_for_each_src_buf_safe'
-  - 'virtio_device_for_each_vq'
-  - 'vkms_config_for_each_connector'
-  - 'vkms_config_for_each_crtc'
-  - 'vkms_config_for_each_encoder'
-  - 'vkms_config_for_each_plane'
-  - 'vkms_config_connector_for_each_possible_encoder'
-  - 'vkms_config_encoder_for_each_possible_crtc'
-  - 'vkms_config_plane_for_each_possible_crtc'
-  - 'while_for_each_ftrace_op'
-  - 'workloads__for_each'
-  - 'xa_for_each'
-  - 'xa_for_each_marked'
-  - 'xa_for_each_range'
-  - 'xa_for_each_start'
-  - 'xas_for_each'
-  - 'xas_for_each_conflict'
-  - 'xas_for_each_marked'
-  - 'xbc_array_for_each_value'
-  - 'xbc_for_each_key_value'
-  - 'xbc_node_for_each_array_value'
-  - 'xbc_node_for_each_child'
-  - 'xbc_node_for_each_key_value'
-  - 'xbc_node_for_each_subkey'
-  - 'ynl_attr_for_each'
-  - 'ynl_attr_for_each_nested'
-  - 'ynl_attr_for_each_payload'
-  - 'zorro_for_each_dev'
-  # U-Boot specific
-  - '__for_each_child_of_node'
-  - '__usbhs_for_each_pipe'
-  - '__usbhsg_for_each_uep'
-  - '_for_each_zynqmp_part'
-  - 'alist_for_each'
-  - 'alist_for_each_filter'
-  - 'cvmx_coremask_for_each_core'
-  - 'cvmx_coremask_for_each_node'
-  - 'dev_for_each_property'
-  - 'dev_for_each_subnode'
-  - 'expr_list_for_each_sym'
-  - 'fdt_for_each_node_by_compatible'
-  - 'fdt_for_each_property_offset'
-  - 'fdt_for_each_subnode'
-  - 'for_each_bin_hdr_v0'
-  - 'for_each_bl_params_node'
-  - 'for_each_child_withdel'
-  - 'for_each_console_dev'
-  - 'for_each_ext_hdr_v0'
-  - 'for_each_label'
-  - 'for_each_label_withdel'
-  - 'for_each_marker'
-  - 'for_each_marker_of_type'
-  - 'for_each_memory_map_entry_reversed'
-  - 'for_each_mmc_mode_by_pref'
-  - 'for_each_opt_hdr_v1'
-  - 'for_each_property_withdel'
-  - 'for_each_sd_mode_by_pref'
-  - 'for_each_supported_width'
-  - 'for_each_tpm_device'
-  - 'for_each_w1_device'
-  - 'for_each_zynqmp_image'
-  - 'for_each_zynqmp_part'
-  - 'for_each_zynqmp_part_in_image'
-  - 'mtd_for_each_device'
-  - 'ofnode_for_each_compatible_node'
-  - 'ofnode_for_each_prop'
-  - 'ofnode_for_each_subnode'
-  - 'pko_for_each_port'
-  - 'sfi_for_each_mentry'
-  - 'ubi_for_each_free_peb'
-  - 'ubi_for_each_protected_peb'
-  - 'ubi_for_each_scrub_peb'
-  - 'ubi_for_each_used_peb'
-  - 'ubi_rb_for_each_entry'
-  - 'usbhs_for_each_dfifo'
-  - 'usbhs_for_each_pipe'
-  - 'usbhs_for_each_pipe_with_dcp'
-  - 'usbhsg_for_each_uep'
-  - 'usbhsg_for_each_uep_with_dcp'
-
-IncludeBlocks: Preserve
-IncludeCategories:
-  - Regex: '.*'
-    Priority: 1
-IncludeIsMainRegex: '(Test)?$'
-IndentCaseLabels: false
-IndentGotoLabels: false
-IndentPPDirectives: None
-IndentWidth: 8
-IndentWrappedFunctionNames: false
-JavaScriptQuotes: Leave
-JavaScriptWrapImports: true
-KeepEmptyLinesAtTheStartOfBlocks: false
-MacroBlockBegin: ''
-MacroBlockEnd: ''
-MaxEmptyLinesToKeep: 1
-NamespaceIndentation: None
-ObjCBinPackProtocolList: Auto
-ObjCBlockIndentWidth: 8
-ObjCSpaceAfterProperty: true
-ObjCSpaceBeforeProtocolList: true
-
-# Taken from git's rules
-PenaltyBreakAssignment: 10
-PenaltyBreakBeforeFirstCallParameter: 30
-PenaltyBreakComment: 10
-PenaltyBreakFirstLessLess: 0
-PenaltyBreakString: 10
-PenaltyExcessCharacter: 100
-PenaltyReturnTypeOnItsOwnLine: 60
-
-PointerAlignment: Right
-ReflowComments: false
-SortIncludes: false
-SortUsingDeclarations: false
-SpaceAfterCStyleCast: false
-SpaceAfterTemplateKeyword: true
-SpaceBeforeAssignmentOperators: true
-SpaceBeforeCtorInitializerColon: true
-SpaceBeforeInheritanceColon: true
-SpaceBeforeParens: ControlStatementsExceptForEachMacros
-SpaceBeforeRangeBasedForLoopColon: true
-SpaceInEmptyParentheses: false
-SpacesBeforeTrailingComments: 1
-SpacesInAngles: false
-SpacesInContainerLiterals: false
-SpacesInCStyleCastParentheses: false
-SpacesInParentheses: false
-SpacesInSquareBrackets: false
-Standard: Cpp03
-TabWidth: 8
-UseTab: Always
-...

.get_maintainer.conf

@@ -1 +1 @@
---find-maintainer-files --git --maintainer-path=.
+--find-maintainer-files --maintainer-path=.

.get_maintainer.ignore

@@ -1 +0,0 @@
-"Pali Rohár" <pali@kernel.org>

.gitignore

@@ -10,7 +10,6 @@
 *.a
 *.asn1.[ch]
 *.bin
-*.bin[_.]*
 *.cfgout
 *.cover
 *.dtb
@@ -18,29 +17,25 @@
 *.dtb.S
 *.elf
 *.exe
-*.fit
 *.gcda
 *.gcno
 *.i
 *.img
-*.itb
 *.lex.c
 *.lst
-*.map
 *.mod.c
 *.mbx
 *.o
 *.o.*
 *.order
 *.patch
-*.pem
 *.s
 *.su
 *.swp
 *.tab.[ch]
-*.ti-*
+
 # Build tree
-/build*
+/build-*
 
 #
 # Top-level generic files
@@ -49,19 +44,13 @@ fit-dtb.blob*
 /MLO*
 /SPL*
 /System.map
-/boards.cfg
-/mkimage*mkimage
-/mkimage-in-simple-bin*
-/simple-bin*
 /u-boot*
+/boards.cfg
 /*.log
 
 #
-# We don't want to ignore the following even if they are dot-files
+# git files that we don't want to ignore even it they are dot-files
 #
-!.clang-format
-!.get_maintainer.*
-!.gitattributes
 !.gitignore
 !.mailmap
 
@@ -70,30 +59,13 @@ fit-dtb.blob*
 #
 /spl/
 /tpl/
-/vpl/
 /defconfig
-/generated_defconfig
-/Test*
-/capsule*.efi-capsule
-/capsule*.map
-/keep-syms-lto.*
-/*imx8mimage*
-/*imx8mcst*
-/*rcar4-sa0*
-/drivers/video/u_boot_logo.bmp.S
-/test/fdt_overlay/test-fdt-overlay-stacked.dtbo.S
-/test/fdt_overlay/test-fdt-overlay.dtbo.S
-capsule_esl_file
 
 #
 # Generated include files
 #
-/include/autoconf.mk*
-/include/config.h
 /include/config/
 /include/generated/
-/include/bmp_logo.h
-/include/bmp_logo_data.h
 
 # stgit generated dirs
 patches-*
@@ -134,8 +106,5 @@ __pycache__
 /pylint.cur
 /pylint.out/
 
-# qconfig database
-/qconfig.db
-
-# Clang's compilation database file
-/compile_commands.json
+# moveconfig database
+/moveconfig.db

.gitlab-ci-sage-lab.yml

@@ -1,213 +0,0 @@
-# Definition for the lab connected to the "sage" host and managed with labgrid
-
-.sage_lab_template: &sage_lab_dfn
-  stage: sage-lab
-  rules:
-    - if: $SAGE_LAB == "1"
-      when: always
-    - if: $SAGE_LAB != "1"
-      when: manual
-      allow_failure: true
-  # USB can be unreliable.
-  retry: 2
-  dependencies: []
-  needs: [ "sandbox test.py" ]
-  tags: [ 'konsulko-sage-labgrid' ]
-  before_script:
-    # Clone uboot-test-hooks
-    - git config --global --add safe.directory "${CI_PROJECT_DIR}"
-    - git clone --depth=1 https://source.denx.de/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks
-    - ln -s sage /tmp/uboot-test-hooks/bin/`hostname`
-    - ln -s sage /tmp/uboot-test-hooks/py/`hostname`
-    - export LG_ENV="/tmp/uboot-test-hooks/bin/sage/labgrid-sage-env.yaml";
-      export LG_COORDINATOR=172.17.0.1:20408
-    # Prepare python environment
-    - python3 -m venv /tmp/venv;
-      . /tmp/venv/bin/activate;
-      pip install -r test/py/requirements.txt -r tools/binman/requirements.txt
-        -r tools/buildman/requirements.txt -r tools/u_boot_pylib/requirements.txt
-        labgrid setuptools
-    # Acquire and turn on the exporter.
-    - labgrid-client reserve --wait board=${LABGRID_EXPORTER} &&
-      labgrid-client -p ${LABGRID_EXPORTER} acquire &&
-      labgrid-client -p ${LABGRID_EXPORTER} power on
-    # Prepare ssh
-    - mkdir --mode=0700 ~/.ssh;
-      printf 'Host sage-exporter-*\n\tUser labgrid\n' > ~/.ssh/config
-    # If we have TF-A binaries, we need to use them.
-    - if [[ -d /opt/tf-a/${TEST_PY_BD}${TEST_PY_ID//--id /_} ]]; then
-        cp /opt/tf-a/${TEST_PY_BD}${TEST_PY_ID//--id /_}/* /tmp/;
-      elif [[ -d /opt/tf-a/${TEST_PY_BD} ]]; then
-        cp /opt/tf-a/${TEST_PY_BD}/* /tmp/;
-      fi;
-      export BINMAN_INDIRS=/tmp;
-  script:
-    - export UBOOT_TRAVIS_BUILD_DIR=/tmp/${TEST_PY_BD}
-    # Don't stop on non-zero exit codes now, to provide as much chance as
-    # possible to ensure we don't leave lab resources acquired.
-    - set +e;
-    # Sage is 16 threads and has 4 devices attached, so 4 builder threads.
-    - tools/buildman/buildman -o ${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e
-        --board ${TEST_PY_BD} ${OVERRIDE} -T 4;
-      RC=`echo $?`;
-    # Wait for the exporter to have the device ready
-    - while test `labgrid-client resources |
-        grep -q ${LABGRID_EXPORTER}/${LG_PLACE}/; echo $?` -ne 0; do sleep 1;
-      done
-    # Fingerprint the exporter
-    - ssh-keyscan ${LABGRID_EXPORTER} > ~/.ssh/known_hosts 2>/dev/null
-    # If we built, run the tests and save the results.
-    - export PATH=/tmp/uboot-test-hooks/bin:${PATH};
-      export PYTHONPATH=/tmp/uboot-test-hooks/py/sage;
-      test $RC -eq 0 && labgrid-client reserve --wait board=${LG_PLACE} &&
-      labgrid-client -p ${LG_PLACE} acquire &&
-      ./test/py/test.py -ra --bd ${TEST_PY_BD} ${TEST_PY_ID}
-        ${TEST_PY_EXTRA:-"--capture=tee-sys"}
-        ${TEST_PY_TEST_SPEC:+"-k ${TEST_PY_TEST_SPEC}"}
-        --build-dir "$UBOOT_TRAVIS_BUILD_DIR"
-        --junitxml=/tmp/${TEST_PY_BD}/results.xml;
-      RC=`echo $?`;
-      cp -v /tmp/${TEST_PY_BD}/*.{html,css,xml} .;
-    # Release and power off everything.
-    - labgrid-client -p ${LG_PLACE} power off
-    - labgrid-client -p ${LG_PLACE} release
-    - labgrid-client -p ${LABGRID_EXPORTER} ssh sudo poweroff && sleep 15 &&
-      labgrid-client -p ${LABGRID_EXPORTER} power off
-    - labgrid-client -p ${LABGRID_EXPORTER} release
-    - exit $RC
-  artifacts:
-    when: always
-    paths:
-      - "*.html"
-      - "*.css"
-      - results.xml
-    reports:
-      junit: results.xml
-    expire_in: 1 week
-
-BeagleBone Black:
-  <<: *sage_lab_dfn
-  variables:
-    LABGRID_EXPORTER: "sage-exporter-bbb-1"
-    LG_PLACE: "bbb-1"
-    TEST_PY_BD: "am335x_evm"
-    OVERRIDE: "-a CMD_BOOTMENU -a CMD_LOG -a CMD_BOOTEFI_HELLO -a CMD_BOOTEFI_SELFTEST"
-
-BeagleBone Black (lwIP):
-  <<: *sage_lab_dfn
-  needs: [ "BeagleBone Black" ]
-  variables:
-    LABGRID_EXPORTER: "sage-exporter-bbb-1"
-    LG_PLACE: "bbb-1"
-    TEST_PY_BD: "am335x_evm"
-    OVERRIDE: "-a CMD_BOOTMENU -a CMD_LOG -a CMD_BOOTEFI_HELLO -a CMD_BOOTEFI_SELFTEST -a NET_LWIP"
-
-Pine64+:
-  <<: *sage_lab_dfn
-  variables:
-    LABGRID_EXPORTER: "sage-exporter-pine64-1"
-    LG_PLACE: "pine64-1"
-    TEST_PY_BD: "pine64_plus"
-    OVERRIDE: "-a CMD_BOOTMENU -a CMD_LOG"
-
-Pine64+ (lwIP):
-  <<: *sage_lab_dfn
-  needs: [ "Pine64+" ]
-  variables:
-    LABGRID_EXPORTER: "sage-exporter-pine64-1"
-    LG_PLACE: "pine64-1"
-    TEST_PY_BD: "pine64_plus"
-    # Leads to crash on lwIP, needs investigation.
-    TEST_PY_TEST_SPEC: "not test_net_pxe_boot_config"
-    OVERRIDE: "-a CMD_BOOTMENU -a CMD_LOG -a NET_LWIP"
-
-SolidRun Hummingboard 2:
-  <<: *sage_lab_dfn
-  variables:
-    LABGRID_EXPORTER: "sage-exporter-hb-1"
-    LG_PLACE: "hb-1"
-    TEST_PY_BD: "mx6cuboxi"
-    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG"
-
-SolidRun Hummingboard 2 (lwIP):
-  <<: *sage_lab_dfn
-  needs: [ "SolidRun Hummingboard 2" ]
-  variables:
-    LABGRID_EXPORTER: "sage-exporter-hb-1"
-    LG_PLACE: "hb-1"
-    TEST_PY_BD: "mx6cuboxi"
-    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a NET_LWIP"
-
-Raspberry Pi 4:
-  <<: *sage_lab_dfn
-  variables:
-    LABGRID_EXPORTER: "sage-exporter-rpi4-1"
-    LG_PLACE: "rpi4-1"
-    TEST_PY_BD: "rpi_4"
-    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a CMD_TFTPPUT -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
-
-Raspberry Pi 4 (rpi_arm64):
-  <<: *sage_lab_dfn
-  needs: [ "Raspberry Pi 4" ]
-  variables:
-    LABGRID_EXPORTER: "sage-exporter-rpi4-1"
-    LG_PLACE: "rpi4-1"
-    TEST_PY_BD: "rpi_arm64"
-    # DHCP is not being run first, needs to be investigated.
-    TEST_PY_TEST_SPEC: "not test_efi_helloworld_net_http"
-    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
-
-Raspberry Pi 4 (rpi_4_32b):
-  <<: *sage_lab_dfn
-  needs: [ "Raspberry Pi 4 (rpi_arm64)" ]
-  variables:
-    LABGRID_EXPORTER: "sage-exporter-rpi4-1"
-    LG_PLACE: "rpi4-1"
-    TEST_PY_BD: "rpi_4_32b"
-    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a CMD_BOOTEFI_SELFTEST -a CMD_TFTPPUT -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
-
-Raspberry Pi 4 (rpi_4_32b, lwIP):
-  <<: *sage_lab_dfn
-  needs: [ "Raspberry Pi 4 (rpi_4_32b)" ]
-  variables:
-    LABGRID_EXPORTER: "sage-exporter-rpi4-1"
-    LG_PLACE: "rpi4-1"
-    TEST_PY_BD: "rpi_4_32b"
-    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a CMD_BOOTEFI_SELFTEST -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000 -a NET_LWIP"
-
-Raspberry Pi 3:
-  <<: *sage_lab_dfn
-  variables:
-    LABGRID_EXPORTER: "sage-exporter-rpi3-1"
-    LG_PLACE: "rpi3-1"
-    TEST_PY_BD: "rpi_3"
-    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a CMD_BOOTEFI_SELFTEST -a CMD_TFTPPUT -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
-
-Raspberry Pi 3 (rpi_arm64):
-  <<: *sage_lab_dfn
-  needs: [ "Raspberry Pi 3" ]
-  variables:
-    LABGRID_EXPORTER: "sage-exporter-rpi3-1"
-    LG_PLACE: "rpi3-1"
-    TEST_PY_BD: "rpi_arm64"
-    # DHCP is not being run first, needs to be investigated.
-    TEST_PY_TEST_SPEC: "not test_efi_helloworld_net_http"
-    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
-
-Raspberry Pi 3 (rpi_3_32b):
-  <<: *sage_lab_dfn
-  needs: [ "Raspberry Pi 3 (rpi_arm64)" ]
-  variables:
-    LABGRID_EXPORTER: "sage-exporter-rpi3-1"
-    LG_PLACE: "rpi3-1"
-    TEST_PY_BD: "rpi_3_32b"
-    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a CMD_BOOTEFI_SELFTEST -a CMD_TFTPPUT -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
-
-Raspberry Pi 3 (rpi_3_32b, lwIP):
-  <<: *sage_lab_dfn
-  needs: [ "Raspberry Pi 3 (rpi_3_32b)" ]
-  variables:
-    LABGRID_EXPORTER: "sage-exporter-rpi3-1"
-    LG_PLACE: "rpi3-1"
-    TEST_PY_BD: "rpi_3_32b"
-    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a CMD_BOOTEFI_SELFTEST -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000 -a NET_LWIP"

.gitlab-ci.yml

@@ -1,70 +1,44 @@
 # SPDX-License-Identifier: GPL-2.0+
 
 variables:
-  DEFAULT_ALL_TAG: "all"
-  DEFAULT_AMD64_TAG: "amd64"
-  DEFAULT_FAST_TAG: "fast"
+  DEFAULT_TAG: ""
   MIRROR_DOCKER: docker.io
-  SAGE_LAB: ""
-  SJG_LAB: ""
-  PLATFORM: linux/amd64,linux/arm64
 
 default:
   tags:
-    - ${DEFAULT_ALL_TAG}
-
-workflow:
-  rules:
-    - when: always
+    - ${DEFAULT_TAG}
 
 # Grab our configured image.  The source for this is found
 # in the u-boot tree at tools/docker/Dockerfile
-image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:noble-20251013-23Jan2026
+image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20230308-04Apr2023
 
 # We run some tests in different order, to catch some failures quicker.
 stages:
   - testsuites
   - test.py
-  - sage-lab
-  - sjg-lab
   - world build
 
 .buildman_and_testpy_template: &buildman_and_testpy_dfn
   stage: test.py
-  retry: 2 # QEMU may be too slow, etc.
-  needs: [ "Build allyesconfig, tools-only and envtools" ]
   before_script:
     # Clone uboot-test-hooks
     - git config --global --add safe.directory "${CI_PROJECT_DIR}"
     - git clone --depth=1 https://source.denx.de/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks
-    # qemu_arm64_lwip_defconfig is the same as qemu_arm64 but with NET_LWIP enabled.
-    # The test config and the boardenv file from qemu_arm64 can be re-used so create symlinks
-    - ln -s conf.qemu_arm64 /tmp/uboot-test-hooks/bin/travis-ci/conf.qemu_arm64_lwip_na
-    - ln -s u_boot_boardenv_qemu_arm64_na.py /tmp/uboot-test-hooks/py/travis-ci/u_boot_boardenv_qemu_arm64_lwip_na.py
     - ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
     - ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
-    - if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]] || [[ "${TEST_PY_BD}" == "xilinx_mbv32_smode" ]]; then
-        wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
-        export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
+    - grub-mkimage --prefix="" -o ~/grub_x86.efi -O i386-efi normal  echo lsefimmap lsefi lsefisystab efinet tftp minicmd
+    - grub-mkimage --prefix="" -o ~/grub_x64.efi -O x86_64-efi normal  echo lsefimmap lsefi lsefisystab efinet tftp minicmd
+    - if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
+        wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
+        export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
       fi
-    - if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]] || [[ "${TEST_PY_BD}" == "xilinx_mbv64_smode" ]]; then
-        wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
-        export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
+    - if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
+        wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
+        export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
       fi
-    - if [[ "${TEST_PY_BD}" == "qemu-arm-sbsa" ]]; then
-        wget -O /tmp/bl1.bin https://artifacts.codelinaro.org/artifactory/linaro-419-sbsa-ref/latest/tf-a/bl1.bin;
-        wget -O /tmp/fip.bin https://artifacts.codelinaro.org/artifactory/linaro-419-sbsa-ref/latest/tf-a/fip.bin;
-        export BINMAN_INDIRS=/tmp;
-      fi
-    # Prepare python environment
-    - python3 -m venv /tmp/venv;
-      . /tmp/venv/bin/activate;
-      pip install -r test/py/requirements.txt -r tools/binman/requirements.txt
-        -r tools/buildman/requirements.txt -r tools/u_boot_pylib/requirements.txt
-        setuptools
 
   after_script:
-    - cp -v /tmp/${TEST_PY_BD}/*.{html,css,xml} .
+    - cp -v /tmp/${TEST_PY_BD}/*.{html,css} .
     - rm -rf /tmp/uboot-test-hooks /tmp/venv
   script:
     # If we've been asked to use clang only do one configuration.
@@ -75,8 +49,8 @@ stages:
       fi
     - tools/buildman/buildman -o ${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e
         --board ${TEST_PY_BD} ${OVERRIDE}
-    - cp /opt/grub/grub_x86.efi $UBOOT_TRAVIS_BUILD_DIR/
-    - cp /opt/grub/grub_x64.efi $UBOOT_TRAVIS_BUILD_DIR/
+    - cp ~/grub_x86.efi $UBOOT_TRAVIS_BUILD_DIR/
+    - cp ~/grub_x64.efi $UBOOT_TRAVIS_BUILD_DIR/
     - cp /opt/grub/grubriscv64.efi $UBOOT_TRAVIS_BUILD_DIR/grub_riscv64.efi
     - cp /opt/grub/grubaa64.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm64.efi
     - cp /opt/grub/grubarm.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm.efi
@@ -93,232 +67,223 @@ stages:
         cp images/spi-nor.img ${UBOOT_TRAVIS_BUILD_DIR}/;
       fi
     - if [[ "${TEST_PY_BD}" == "coreboot" ]]; then
-        cp /opt/coreboot/coreboot.rom ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom;
-        /opt/coreboot/cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom remove -n fallback/payload;
-        /opt/coreboot/cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
-      fi
-    # If we have TF-A binaries, we need to use them.
-    - tfa_dir=""
-    - rm -f /tmp/fip.bin
-    - rm -f /tmp/bl1.bin
-    - if [[ -d /opt/tf-a/"${TEST_PY_BD}${TEST_PY_ID//--id /_}" ]]; then
-        tfa_dir="/opt/tf-a/${TEST_PY_BD}${TEST_PY_ID//--id /_}";
-      elif [[ -d /opt/tf-a/"${TEST_PY_BD}" ]]; then
-        tfa_dir="/opt/tf-a/${TEST_PY_BD}";
-      fi
-    - if [[ -n "$tfa_dir" ]]; then
-        cp "$tfa_dir"/fip.bin "$tfa_dir"/bl1.bin /tmp/;
-      fi
-    - if [ -f /tmp/fip.bin ] && [ -f /tmp/bl1.bin ]; then
-        export fip=/tmp/fip.bin;
-        export bl1=/tmp/bl1.bin;
-        export PATH=/opt/Base_RevC_AEMvA_pkg/models/Linux64_GCC-9.3:${PATH};
+        wget -O -
+          "https://drive.google.com/uc?id=1x6nrtWIyIRPLS2cQBwYTnT2TbOI8UjmM&export=download" |
+          xz -dc >${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom;
+        wget -O -
+          "https://drive.google.com/uc?id=149Cz-5SZXHNKpi9xg6R_5XITWohu348y&export=download" >
+          cbfstool;
+        chmod a+x cbfstool;
+        ./cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
       fi
+    - virtualenv -p /usr/bin/python3 /tmp/venv
+    - . /tmp/venv/bin/activate
+    - pip install -r test/py/requirements.txt
     # "${var:+"-k $var"}" expands to "" if $var is empty, "-k $var" if not
     - export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:${PATH};
       export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci;
-      python3 -m http.server 80 --directory "${UBOOT_TRAVIS_BUILD_DIR}" > /dev/null 2>&1 &
-      HTTP_PID=$!;
-      sleep 1;
-      if ps -p ${HTTP_PID} > /dev/null; then
-        export HTTP_PID;
-      else
-        unset HTTP_PID;
-      fi;
-      ./test/py/test.py -ra --bd ${TEST_PY_BD} ${TEST_PY_ID} ${TEST_PY_EXTRA}
+      ./test/py/test.py -ra --bd ${TEST_PY_BD} ${TEST_PY_ID}
         ${TEST_PY_TEST_SPEC:+"-k ${TEST_PY_TEST_SPEC}"}
         --build-dir "$UBOOT_TRAVIS_BUILD_DIR"
-        --junitxml=/tmp/${TEST_PY_BD}/results.xml;
-      if [[ -n "${HTTP_PID}" ]]; then
-        kill ${HTTP_PID};
-      fi
   artifacts:
     when: always
     paths:
       - "*.html"
       - "*.css"
-      - results.xml
-    reports:
-      junit: results.xml
     expire_in: 1 week
 
-build all platforms in a single job:
+build all 32bit ARM platforms:
   stage: world build
-  dependencies: []
-  needs: [ "sandbox test.py" ]
-  tags:
-    - ${DEFAULT_FAST_TAG}
   script:
-    # Prepare python environment
-    - python3 -m venv /tmp/venv;
-      . /tmp/venv/bin/activate;
-      pip install -r tools/binman/requirements.txt
-        -r tools/buildman/requirements.txt
-        setuptools
     - ret=0;
       git config --global --add safe.directory "${CI_PROJECT_DIR}";
-      ./tools/buildman/buildman -o /tmp -PEWM -x xtensa || ret=$?;
+      ./tools/buildman/buildman -o /tmp -PEWM arm -x aarch64 || ret=$?;
       if [[ $ret -ne 0 ]]; then
         ./tools/buildman/buildman -o /tmp -seP;
         exit $ret;
       fi;
 
-.testsuites:
-  stage: testsuites
+build all 64bit ARM platforms:
+  stage: world build
+  script:
+    - virtualenv -p /usr/bin/python3 /tmp/venv
+    - . /tmp/venv/bin/activate
+    - ret=0;
+      git config --global --add safe.directory "${CI_PROJECT_DIR}";
+      ./tools/buildman/buildman -o /tmp -PEWM aarch64 || ret=$?;
+      if [[ $ret -ne 0 ]]; then
+        ./tools/buildman/buildman -o /tmp -seP;
+        exit $ret;
+      fi;
+
+build all PowerPC platforms:
+  stage: world build
+  script:
+    - ret=0;
+      git config --global --add safe.directory "${CI_PROJECT_DIR}";
+      ./tools/buildman/buildman -o /tmp -P -E -W powerpc || ret=$?;
+      if [[ $ret -ne 0 ]]; then
+        ./tools/buildman/buildman -o /tmp -seP;
+        exit $ret;
+      fi;
+
+build all other platforms:
+  stage: world build
+  script:
+    - ret=0;
+      git config --global --add safe.directory "${CI_PROJECT_DIR}";
+      ./tools/buildman/buildman -o /tmp -PEWM -x arm,powerpc || ret=$?;
+      if [[ $ret -ne 0 ]]; then
+        ./tools/buildman/buildman -o /tmp -seP;
+        exit $ret;
+      fi;
 
 check for new CONFIG symbols outside Kconfig:
-  extends: .testsuites
+  stage: testsuites
   script:
     - git config --global --add safe.directory "${CI_PROJECT_DIR}"
     # If grep succeeds and finds a match the test fails as we should
     # have no matches.
     - git grep -E '^#[[:blank:]]*(define|undef)[[:blank:]]*CONFIG_'
         :^doc/ :^arch/arm/dts/ :^scripts/kconfig/lkc.h
-        :^include/linux/kconfig.h :^tools/ :^dts/upstream/
-        :^lib/mbedtls/external :^lib/mbedtls/mbedtls_def_config.h &&
-        exit 1 || exit 0
+        :^include/linux/kconfig.h :^tools/ && exit 1 || exit 0
+
+# QA jobs for code analytics
+# static code analysis with cppcheck (we can add --enable=all later)
+cppcheck:
+  stage: testsuites
+  script:
+    - cppcheck -j$(nproc) --force --quiet --inline-suppr .
+
+# search for TODO within source tree
+grep TODO/FIXME/HACK:
+  stage: testsuites
+  script:
+    - grep -r TODO .
+    - grep -r FIXME .
+    # search for HACK within source tree and ignore HACKKIT board
+    - grep -r HACK . | grep -v HACKKIT
 
 # build documentation
 docs:
-  extends: .testsuites
+  stage: testsuites
   script:
-    - python3 -m venv /tmp/venvhtml
+    - virtualenv -p /usr/bin/python3 /tmp/venvhtml
     - . /tmp/venvhtml/bin/activate
-    - pip install -r doc/sphinx/requirements.txt -r test/py/requirements.txt
+    - pip install -r doc/sphinx/requirements.txt
     - make htmldocs KDOC_WERROR=1
     - make infodocs
 
+# some statistics about the code base
+sloccount:
+  stage: testsuites
+  script:
+    - sloccount .
+
 # ensure all configs have MAINTAINERS entries
 Check for configs without MAINTAINERS entry:
-  extends: .testsuites
+  stage: testsuites
   script:
-    - ./tools/buildman/buildman --maintainer-check
+    - ./tools/buildman/buildman -R
 
 # Ensure host tools build
-Build allyesconfig, tools-only and envtools:
-  extends: .testsuites
+Build tools-only:
+  stage: testsuites
   script:
-    # Allow pipefail because of how we use 'yes' here.
-    - set +o pipefail;
-      yes 0 | make allyesconfig oldconfig all -j$(nproc);
-      make mrproper;
-      make tools-only_config tools-only -j$(nproc);
-      make mrproper;
-      make tools-only_config envtools -j$(nproc)
+    - make tools-only_config tools-only -j$(nproc)
+
+# Ensure env tools build
+Build envtools:
+  stage: testsuites
+  script:
+    - make tools-only_config envtools -j$(nproc)
 
 Run binman, buildman, dtoc, Kconfig and patman testsuites:
-  extends: .testsuites
-  tags:
-    - ${DEFAULT_AMD64_TAG}
+  stage: testsuites
   script:
     - git config --global user.name "GitLab CI Runner";
       git config --global user.email trini@konsulko.com;
       git config --global --add safe.directory "${CI_PROJECT_DIR}";
       export USER=gitlab;
-      python3 -m venv /tmp/venv;
+      virtualenv -p /usr/bin/python3 /tmp/venv;
       . /tmp/venv/bin/activate;
-      pip install -r test/py/requirements.txt -r tools/binman/requirements.txt
-        -r tools/buildman/requirements.txt -r tools/patman/requirements.txt
-        -r tools/u_boot_pylib/requirements.txt;
-      export UBOOT_TRAVIS_BUILD_DIR=/tmp/tools-only;
+      pip install -r test/py/requirements.txt;
+      export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl;
       export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt";
       export PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}";
       set +e;
       ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w
-        --board tools-only;
+        --board sandbox_spl;
       set -e;
-      export TOOLPATH="--toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools --toolpath /opt/coreboot";
-      ./tools/binman/binman ${TOOLPATH} tool -f missing;
-      ./tools/binman/binman ${TOOLPATH} test;
-      ./tools/binman/binman ${TOOLPATH} test -T;
+      ./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test;
       ./tools/buildman/buildman -t;
       ./tools/dtoc/dtoc -t;
       ./tools/patman/patman test;
       make testconfig
 
+Run tests for Nokia RX-51 (aka N900):
+  stage: testsuites
+  script:
+    - mkdir nokia_rx51_tmp;
+      ln -s /opt/nokia/u-boot-gen-combined nokia_rx51_tmp/;
+      ln -s /opt/nokia/qemu-n900.tar.gz nokia_rx51_tmp/;
+      ln -s /opt/nokia/kernel_2.6.28-20103103+0m5_armel.deb nokia_rx51_tmp/;
+      ln -s /opt/nokia/libc6_2.5.1-1eglibc27+0m5_armel.deb nokia_rx51_tmp/;
+      ln -s /opt/nokia/busybox_1.10.2.legal-1osso30+0m5_armel.deb nokia_rx51_tmp/;
+      ln -s /opt/nokia/qemu-system-arm nokia_rx51_tmp/;
+      export PATH=/opt/gcc-12.2.0-nolibc/arm-linux-gnueabi/bin:$PATH;
+      test/nokia_rx51_test.sh
+
 # Check for any pylint regressions
 Run pylint:
-  extends: .testsuites
+  stage: testsuites
   script:
     - git config --global --add safe.directory "${CI_PROJECT_DIR}"
-    - python3 -m venv /tmp/venv
-    - . /tmp/venv/bin/activate
-    - pip install -r test/py/requirements.txt -r tools/binman/requirements.txt
-        -r tools/buildman/requirements.txt -r tools/patman/requirements.txt
-        -r tools/u_boot_pylib/requirements.txt asteval pylint==3.3.4 pyopenssl
+    - pip install -r test/py/requirements.txt
+    - pip install asteval pylint==2.12.2 pyopenssl
     - export PATH=${PATH}:~/.local/bin
     - echo "[MASTER]" >> .pylintrc
     - echo "load-plugins=pylint.extensions.docparams" >> .pylintrc
-    - export UBOOT_TRAVIS_BUILD_DIR=/tmp/tools-only
+    - export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl
     - set +e
     - ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w
-        --board tools-only
+        --board sandbox_spl
     - set -e
     - pylint --version
     - export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt"
     - make pylint_err
 
+# Check for pre-schema driver model tags
+Check for pre-schema tags:
+  stage: testsuites
+  script:
+    - git config --global --add safe.directory "${CI_PROJECT_DIR}";
+    # If grep succeeds and finds a match the test fails as we should
+    # have no matches.
+    - git grep u-boot,dm- -- '*.dts*' && exit 1 || exit 0
+
 # Check we can package the Python tools
 Check packing of Python tools:
-  extends: .testsuites
+  stage: testsuites
   script:
     - make pip
 
 # Test sandbox with test.py
 sandbox test.py:
-  parallel:
-    matrix:
-      - HOST: "arm64"
-      - HOST: "amd64"
-  tags:
-    - ${HOST}
   variables:
     TEST_PY_BD: "sandbox"
-    TEST_PY_EXTRA: "--timing"
-    # addr2line in Ubuntu 'Noble' and later are broken.
-    TEST_PY_TEST_SPEC: "not event_dump"
   <<: *buildman_and_testpy_dfn
 
 sandbox with clang test.py:
-  parallel:
-    matrix:
-      - HOST: "arm64"
-      - HOST: "amd64"
-  tags:
-    - ${HOST}
   variables:
     TEST_PY_BD: "sandbox"
-    OVERRIDE: "-O clang-20"
-    # addr2line in Ubuntu 'Noble' and later are broken.
-    TEST_PY_TEST_SPEC: "not event_dump"
+    OVERRIDE: "-O clang-16"
   <<: *buildman_and_testpy_dfn
 
-sandbox64 test.py:
-  parallel:
-    matrix:
-      - HOST: "arm64"
-      - HOST: "amd64"
-  tags:
-    - ${HOST}
+sandbox without LTO test.py:
   variables:
-    TEST_PY_BD: "sandbox64"
-  <<: *buildman_and_testpy_dfn
-
-sandbox64 with clang test.py:
-  parallel:
-    matrix:
-      - HOST: "arm64"
-      - HOST: "amd64"
-  tags:
-    - ${HOST}
-  variables:
-    TEST_PY_BD: "sandbox64"
-    OVERRIDE: "-O clang-20"
-  <<: *buildman_and_testpy_dfn
-
-sandbox64_lwip test.py:
-  variables:
-    TEST_PY_BD: "sandbox64_lwip"
+    TEST_PY_BD: "sandbox"
+    BUILD_ENV: "NO_LTO=1"
   <<: *buildman_and_testpy_dfn
 
 sandbox_spl test.py:
@@ -333,13 +298,6 @@ sandbox_noinst_test.py:
     TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
   <<: *buildman_and_testpy_dfn
 
-sandbox_noinst with LOAD_FIT_FULL test.py:
-  variables:
-    TEST_PY_BD: "sandbox_noinst"
-    TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
-    OVERRIDE: "-a CONFIG_SPL_LOAD_FIT_FULL=y"
-  <<: *buildman_and_testpy_dfn
-
 sandbox_vpl test.py:
   variables:
     TEST_PY_BD: "sandbox_vpl"
@@ -352,13 +310,18 @@ sandbox trace_test.py:
     TEST_PY_BD: "sandbox"
     BUILD_ENV: "FTRACE=1 NO_LTO=1"
     TEST_PY_TEST_SPEC: "trace"
-    OVERRIDE: "-a CONFIG_TRACE=y -a CONFIG_TRACE_EARLY=y -a CONFIG_TRACE_EARLY_SIZE=0x01000000 -a CONFIG_TRACE_BUFFER_SIZE=0x02000000"
+    OVERRIDE: "-a CONFIG_TRACE=y -a CONFIG_TRACE_EARLY=y -a CONFIG_TRACE_EARLY_SIZE=0x01000000"
   <<: *buildman_and_testpy_dfn
 
 evb-ast2500 test.py:
   variables:
     TEST_PY_BD: "evb-ast2500"
-    TEST_PY_TEST_SPEC: "not sleep"
+    TEST_PY_ID: "--id qemu"
+  <<: *buildman_and_testpy_dfn
+
+evb-ast2600 test.py:
+  variables:
+    TEST_PY_BD: "evb-ast2600"
     TEST_PY_ID: "--id qemu"
   <<: *buildman_and_testpy_dfn
 
@@ -370,7 +333,6 @@ sandbox_flattree test.py:
 vexpress_ca9x4 test.py:
   variables:
     TEST_PY_BD: "vexpress_ca9x4"
-    TEST_PY_TEST_SPEC: "not sleep"
     TEST_PY_ID: "--id qemu"
   <<: *buildman_and_testpy_dfn
 
@@ -391,26 +353,6 @@ qemu_arm64 test.py:
   variables:
     TEST_PY_BD: "qemu_arm64"
     TEST_PY_TEST_SPEC: "not sleep"
-    OVERRIDE: "-a CONFIG_SEMIHOSTING=y"
-  <<: *buildman_and_testpy_dfn
-
-qemu_arm64_lwip test.py:
-  variables:
-    TEST_PY_BD: "qemu_arm64_lwip"
-    TEST_PY_TEST_SPEC: "test_net_dhcp or test_net_ping or test_net_tftpboot"
-  <<: *buildman_and_testpy_dfn
-
-qemu_arm64_tfa_fw_handoff test.py:
-  variables:
-    TEST_PY_BD: "qemu_arm64"
-    TEST_PY_ID: "--id fw_handoff_tfa_optee"
-    TEST_PY_TEST_SPEC: "test_fw_handoff"
-  <<: *buildman_and_testpy_dfn
-
-qemu_arm_sbsa test.py:
-  variables:
-    TEST_PY_BD: "qemu-arm-sbsa"
-    TEST_PY_TEST_SPEC: "not sleep"
   <<: *buildman_and_testpy_dfn
 
 qemu_m68k test.py:
@@ -421,12 +363,6 @@ qemu_m68k test.py:
     OVERRIDE: "-a CONFIG_M68K_QEMU=y -a ~CONFIG_MCFTMR"
   <<: *buildman_and_testpy_dfn
 
-qemu_m68k_virt test.py:
-  variables:
-    TEST_PY_BD: "qemu-m68k"
-    TEST_PY_TEST_SPEC: "not sleep"
-  <<: *buildman_and_testpy_dfn
-
 qemu_malta test.py:
   variables:
     TEST_PY_BD: "malta"
@@ -485,18 +421,6 @@ qemu-riscv64_spl test.py:
     TEST_PY_TEST_SPEC: "not sleep"
   <<: *buildman_and_testpy_dfn
 
-qemu-riscv64_smode test.py:
-  variables:
-    TEST_PY_BD: "qemu-riscv64_smode"
-    TEST_PY_TEST_SPEC: "not sleep"
-  <<: *buildman_and_testpy_dfn
-
-qemu-riscv64_smode_acpi test.py:
-  variables:
-    TEST_PY_BD: "qemu-riscv64_smode_acpi"
-    TEST_PY_TEST_SPEC: "not sleep"
-  <<: *buildman_and_testpy_dfn
-
 qemu-x86 test.py:
   variables:
     TEST_PY_BD: "qemu-x86"
@@ -509,85 +433,42 @@ qemu-x86_64 test.py:
     TEST_PY_TEST_SPEC: "not sleep"
   <<: *buildman_and_testpy_dfn
 
-qemu-xtensa-dc233c test.py:
-  variables:
-    TEST_PY_BD: "qemu-xtensa-dc233c"
-    TEST_PY_TEST_SPEC: "not sleep and not efi"
-  tags:
-    - ${DEFAULT_AMD64_TAG}
-  <<: *buildman_and_testpy_dfn
-
 r2dplus_i82557c test.py:
   variables:
     TEST_PY_BD: "r2dplus"
-    TEST_PY_TEST_SPEC: "not sleep"
     TEST_PY_ID: "--id i82557c_qemu"
   <<: *buildman_and_testpy_dfn
 
 r2dplus_pcnet test.py:
   variables:
     TEST_PY_BD: "r2dplus"
-    TEST_PY_TEST_SPEC: "not sleep"
     TEST_PY_ID: "--id pcnet_qemu"
   <<: *buildman_and_testpy_dfn
 
 r2dplus_rtl8139 test.py:
   variables:
     TEST_PY_BD: "r2dplus"
-    TEST_PY_TEST_SPEC: "not sleep"
     TEST_PY_ID: "--id rtl8139_qemu"
   <<: *buildman_and_testpy_dfn
 
 r2dplus_tulip test.py:
   variables:
     TEST_PY_BD: "r2dplus"
-    TEST_PY_TEST_SPEC: "not sleep"
     TEST_PY_ID: "--id tulip_qemu"
   <<: *buildman_and_testpy_dfn
 
-# This is broken upsteam: https://gitlab.com/qemu-project/qemu/-/issues/2945
-#sifive_unleashed_sdcard test.py:
-#  variables:
-#    TEST_PY_BD: "sifive_unleashed"
-#    TEST_PY_TEST_SPEC: "not sleep"
-#    TEST_PY_ID: "--id sdcard_qemu"
-#  <<: *buildman_and_testpy_dfn
+sifive_unleashed_sdcard test.py:
+  variables:
+    TEST_PY_BD: "sifive_unleashed"
+    TEST_PY_ID: "--id sdcard_qemu"
+  <<: *buildman_and_testpy_dfn
 
 sifive_unleashed_spi-nor test.py:
   variables:
     TEST_PY_BD: "sifive_unleashed"
-    TEST_PY_TEST_SPEC: "not sleep"
     TEST_PY_ID: "--id spi-nor_qemu"
   <<: *buildman_and_testpy_dfn
 
-xilinx_mbv32 test.py:
-  variables:
-    TEST_PY_BD: "xilinx_mbv32"
-    TEST_PY_TEST_SPEC: "not sleep"
-    TEST_PY_ID: "--id qemu"
-  <<: *buildman_and_testpy_dfn
-
-xilinx_mbv32_smode test.py:
-  variables:
-    TEST_PY_BD: "xilinx_mbv32_smode"
-    TEST_PY_TEST_SPEC: "not sleep"
-    TEST_PY_ID: "--id qemu"
-  <<: *buildman_and_testpy_dfn
-
-xilinx_mbv64 test.py:
-  variables:
-    TEST_PY_BD: "xilinx_mbv64"
-    TEST_PY_TEST_SPEC: "not sleep"
-    TEST_PY_ID: "--id qemu"
-  <<: *buildman_and_testpy_dfn
-
-xilinx_mbv64_smode test.py:
-  variables:
-    TEST_PY_BD: "xilinx_mbv64_smode"
-    TEST_PY_TEST_SPEC: "not sleep"
-    TEST_PY_ID: "--id qemu"
-  <<: *buildman_and_testpy_dfn
-
 xilinx_zynq_virt test.py:
   variables:
     TEST_PY_BD: "xilinx_zynq_virt"
@@ -600,7 +481,6 @@ xilinx_versal_virt test.py:
     TEST_PY_BD: "xilinx_versal_virt"
     TEST_PY_TEST_SPEC: "not sleep"
     TEST_PY_ID: "--id qemu"
-    OVERRIDE: "-a ~CONFIG_USB_DWC3"
   <<: *buildman_and_testpy_dfn
 
 xtfpga test.py:
@@ -608,8 +488,6 @@ xtfpga test.py:
     TEST_PY_BD: "xtfpga"
     TEST_PY_TEST_SPEC: "not sleep"
     TEST_PY_ID: "--id qemu"
-  tags:
-    - ${DEFAULT_AMD64_TAG}
   <<: *buildman_and_testpy_dfn
 
 coreboot test.py:
@@ -618,182 +496,3 @@ coreboot test.py:
     TEST_PY_TEST_SPEC: "not sleep"
     TEST_PY_ID: "--id qemu"
   <<: *buildman_and_testpy_dfn
-
-# Add sage-lab stage
-include: .gitlab-ci-sage-lab.yml
-
-.sjg_lab_template: &sjg_lab_dfn
-  stage: sjg-lab
-  rules:
-    - if: $SJG_LAB == "1"
-      when: always
-    - if: $SJG_LAB != "1"
-      when: manual
-      allow_failure: true
-  dependencies: []
-  needs: [ "sandbox test.py" ]
-  tags: [ 'lab' ]
-  script:
-    # Environment:
-    #   SRC  - source tree
-    #   OUT  - output directory for builds
-    - export SRC="$(pwd)"
-    - export OUT="${SRC}/build/${BOARD}"
-    - export PATH=$PATH:~/bin
-    - export PATH=$PATH:/vid/software/devel/ubtest/u-boot-test-hooks/bin
-
-    # Load it on the device
-    - ret=0
-    - echo "role ${ROLE}"
-    - export strategy="-s uboot -e off"
-    - export USE_LABGRID_SJG=1
-    # export verbose="-v"
-    - ${SRC}/test/py/test.py -ra --role ${ROLE} ${TEST_PY_EXTRA:-"--capture=tee-sys"}
-        --build-dir "${OUT}"
-        ${TEST_PY_TEST_SPEC:+"-k ${TEST_PY_TEST_SPEC}"}
-        --junitxml=${OUT}/results.xml || ret=$?
-    - U_BOOT_BOARD_IDENTITY="${ROLE}" u-boot-test-release || true
-    - if [[ $ret -ne 0 ]]; then
-        exit $ret;
-      fi
-  artifacts:
-    when: always
-    paths:
-      - "build/${BOARD}/test-log.html"
-      - "build/${BOARD}/multiplexed_log.css"
-      - "build/${BOARD}/results.xml"
-    reports:
-      junit: "build/${BOARD}/results.xml"
-    expire_in: 1 week
-
-rpi3:
-  variables:
-    ROLE: rpi3
-  <<: *sjg_lab_dfn
-
-opi_pc:
-  variables:
-    ROLE: opi_pc
-  <<: *sjg_lab_dfn
-
-pcduino3_nano:
-  variables:
-    ROLE: pcduino3_nano
-  <<: *sjg_lab_dfn
-
-samus:
-  variables:
-    ROLE: samus
-  <<: *sjg_lab_dfn
-
-link:
-  variables:
-    ROLE: link
-  <<: *sjg_lab_dfn
-
-jerry:
-  variables:
-    ROLE: jerry
-  <<: *sjg_lab_dfn
-
-minnowmax:
-  variables:
-    ROLE: minnowmax
-  <<: *sjg_lab_dfn
-
-opi_pc2:
-  variables:
-    ROLE: opi_pc2
-  <<: *sjg_lab_dfn
-
-bpi:
-  variables:
-    ROLE: bpi
-  <<: *sjg_lab_dfn
-
-rpi2:
-  variables:
-    ROLE: rpi2
-  <<: *sjg_lab_dfn
-
-bob:
-  variables:
-    ROLE: bob
-  <<: *sjg_lab_dfn
-
-ff3399:
-  variables:
-    ROLE: ff3399
-  <<: *sjg_lab_dfn
-
-coral:
-  variables:
-    ROLE: coral
-  <<: *sjg_lab_dfn
-
-rpi3z:
-  variables:
-    ROLE: rpi3z
-  <<: *sjg_lab_dfn
-
-bbb:
-  variables:
-    ROLE: bbb
-  <<: *sjg_lab_dfn
-
-kevin:
-  variables:
-    ROLE: kevin
-  <<: *sjg_lab_dfn
-
-pine64:
-  variables:
-    ROLE: pine64
-  <<: *sjg_lab_dfn
-
-c4:
-  variables:
-    ROLE: c4
-  <<: *sjg_lab_dfn
-
-rpi4:
-  variables:
-    ROLE: rpi4
-  <<: *sjg_lab_dfn
-
-rpi0:
-  variables:
-    ROLE: rpi0
-  <<: *sjg_lab_dfn
-
-snow:
-  variables:
-    ROLE: snow
-  <<: *sjg_lab_dfn
-
-pcduino3:
-  variables:
-    ROLE: pcduino3
-  <<: *sjg_lab_dfn
-
-nyan-big:
-  variables:
-    ROLE: nyan-big
-  <<: *sjg_lab_dfn
-
-rpi:
-  variables:
-    ROLE: rpi
-  <<: *sjg_lab_dfn
-
-# StarFive VisionFive 2
-vf2:
-  variables:
-    ROLE: vf2
-  <<: *sjg_lab_dfn
-
-qemu-x86_64:
-  variables:
-    ROLE: qemu-x86_64
-    TEST_PY_TEST_SPEC: "not sleep"
-  <<: *sjg_lab_dfn

.mailmap

@@ -15,7 +15,6 @@
 # Proper Name <proper@email.xx> <commit@email.xx>
 # Proper Name <proper@email.xx> Commit Name <commit@email.xx>
 
-AKASHI Takahiro <akashi.tkhro@gmail.com> <takahiro.akashi@linaro.org>
 Alexander Graf <agraf@csgraf.de> <agraf@suse.de>
 Allen Martin <amartin@nvidia.com>
 Amanda Baze <amanda.baze@amd.com> <nicole.baze@xilinx.com>
@@ -28,34 +27,19 @@ Anurag Kumar Vulisha <AnuragKumar.Vulisha@amd.com> <anurag.kumar.vulisha@xilinx.
 Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com> <appana.durga.rao@xilinx.com>
 Ashok Reddy Soma <ashok.reddy.soma@amd.com> <ashok.reddy.soma@xilinx.com>
 Atish Patra <atishp@atishpatra.org> <atish.patra@wdc.com>
-Bernhard Messerklinger <bernhard.messerklinger@at.abb.com> <bernhard.messerklinger@br-automation.com>
 Bharat Kumar Gogada <bharat.kumar.gogada@amd.com> <bharat.kumar.gogada@xilinx.com>
 Bharat Kumar Gogada <bharat.kumar.gogada@amd.com> <bharatku@xilinx.com>
 Bhargava Sreekantappa Gayathri <bhargava.sreekantappa-gayathri@amd.com> <bhargava.sreekantappa-gayathri@xilinx.com>
-Bhupesh Sharma <bhupesh.linux@gmail.com> <bhupesh.sharma@linaro.org>
 Bin Meng <bmeng.cn@gmail.com> <bin.meng@windriver.com>
 Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@bootlin.com>
 Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@free-electrons.com>
-Casey Connolly <casey.connolly@linaro.org> <caleb.connolly@linaro.org>
-Chen-Yu Tsai <wens@kernel.org> <wens@csie.org>
 Christian Kohn <chris.kohn@amd.com> <christian.kohn@xilinx.com>
-Christopher Obbard <christopher.obbard@linaro.org> <chris.obbard@collabora.com>
 Dirk Behme <dirk.behme@googlemail.com>
-<duje@dujemihanovic.xyz> <duje.mihanovic@skole.hr>
 Durga Challa <durga.challa@amd.com> <vnsl.durga.challa@xilinx.com>
-Eugen Hristev <ehristev@kernel.org> <eugen.hristev@microchip.com>
-Eugen Hristev <ehristev@kernel.org> <eugen.hristev@linaro.org>
-Eugen Hristev <ehristev@kernel.org> <eugen.hristev@collabora.com>
+Eugen Hristev <eugen.hristev@collabora.com> <eugen.hristev@microchip.com>
 Fabio Estevam <fabio.estevam@nxp.com>
-Greg Malysa <malysagreg@gmail.com> <greg.malysa@timesys.com>
 Harini Katakam <harini.katakam@amd.com> <harini.katakam@xilinx.com>
 Harsha <harsha.harsha@amd.com> <harsha.harsha@xilinx.com>
-Heiko Stuebner <heiko.stuebner@cherry.de> <heiko.stuebner@theobroma-systems.com>
-Heiko Schocher <hs@nabladev.com> <hs@denx.de>
-Heiko Schocher <hs@nabladev.com> <hs@pollux.denx.de>
-Heiko Schocher <hs@nabladev.com> <heiko.schocher@invitel.hu>
-Heiko Schocher <hs@nabladev.com> <[hs@denx.de]>
-Heiko Schocher <hs@nabladev.com> <hs@pollux.(none)>
 Heinrich Schuchardt <xypron.glpk@gmx.de> <heinrich.schuchardt@canonical.com>
 Heinrich Schuchardt <xypron.glpk@gmx.de> xypron.glpk@gmx.de <xypron.glpk@gmx.de>
 Ibai Erkiaga <ibai.erkiaga-elorza@amd.com> <ibai.erkiaga-elorza@xilinx.com>
@@ -67,19 +51,12 @@ Jagan Teki <jaganna@gmail.com>
 Jagan Teki <jaganna@xilinx.com>
 Jagan Teki <jagannadh.teki@gmail.com>
 Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com>
-Jakob Unterwurzacher <jakob.unterwurzacher@cherry.de> <jakob.unterwurzacher@theobroma-systems.com>
-Javier Tia <floss@jetm.me> <javier.tia@linaro.org>
 Jay Buddhabhatti <jay.buddhabhatti@amd.com> <jay.buddhabhatti@xilinx.com>
 Jernej Skrabec <jernej.skrabec@gmail.com> <jernej.skrabec@siol.net>
-Jerome Forissier <jerome.forissier@arm.com> <jerome@forissier.org>
-Jerome Forissier <jerome.forissier@arm.com> <jerome.forissier@linaro.org>
 John Linn <john.linn@amd.com> <john.linn@xilinx.com>
 Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyothee@xilinx.com>
 Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyotheeswar.reddy.mutthareddyvari@xilinx.com>
 Kalyani Akula <kalyani.akula@amd.com> <kalyani.akula@xilinx.com>
-Klaus Goger <klaus.goger@cherry.de> <klaus.goger@theobroma-systems.com>
-Masahisa Kojima <kojima.masahisa@socionext.com> <masahisa.kojima@linaro.org>
-Linus Walleij <linusw@kernel.org> <linus.walleij@linaro.org>
 Love Kumar <love.kumar@amd.com> <love.kumar@xilinx.com>
 Lukasz Majewski <lukma@denx.de>
 Marek Behún <kabel@kernel.org> <marek.behun@nic.cz>
@@ -88,9 +65,8 @@ Marek Vasut <marex@denx.de> <marek.vasut+renesas@gmail.com>
 Marek Vasut <marex@denx.de> <marek.vasut@gmail.com>
 Marek Vasut <marex@denx.de> <marex at denx.de>
 Markus Klotzbuecher <mk@denx.de>
-Masahiro Yamada <masahiroy@kernel.org> <yamada.masahiro@socionext.com>
-Masahiro Yamada <masahiroy@kernel.org> <yamada.m@jp.panasonic.com>
-Mattijs Korpershoek <mkorpershoek@kernel.org> <mkorpershoek@baylibre.com>
+Masahiro Yamada <yamada.masahiro@socionext.com> <masahiroy@kernel.org>
+Masahiro Yamada <yamada.masahiro@socionext.com> <yamada.m@jp.panasonic.com>
 Michal Simek <michal.simek@amd.com> <Monstr@seznam.cz>
 Michal Simek <michal.simek@amd.com> <michal.simek@xilinx.com>
 Michal Simek <michal.simek@amd.com> <monstr@monstr.eu>
@@ -104,23 +80,16 @@ Nava kishore Manne <nava.kishore.manne@amd.com> <nava.manne@xilinx.com>
 Neal Frager <neal.frager@amd.com> <neal.frager@xilinx.com>
 Neil Armstrong <neil.armstrong@linaro.org> <narmstrong@baylibre.com>
 Nicolas Saenz Julienne <nsaenz@kernel.org> <nsaenzjulienne@suse.de>
-This contributor prefers not to receive mails <noreply@example.com> <pali@kernel.org>
-This contributor prefers not to receive mails <noreply@example.com> <pali.rohar@gmail.com>
-Padmarao Begari <padmarao.begari@amd.com> <padmarao.begari@microchip.com>
 Patrice Chotard <patrice.chotard@foss.st.com> <patrice.chotard@st.com>
 Patrick Delaunay <patrick.delaunay@foss.st.com> <patrick.delaunay@st.com>
-Paul Burton <paulburton@kernel.org> <paul.burton@imgtec.com>
-Paul Burton <paulburton@kernel.org> <paul.burton@mips.com>
-Philipp Tomsich <philipp.tomsich@vrull.eu> <philipp.tomsich@theobroma-systems.com>
+Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
 Piyush Mehta <piyush.mehta@amd.com> <piyush.mehta@xilinx.com>
 Prabhakar Kushwaha <prabhakar@freescale.com>
 Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@amd.com> <punnaiah.choudary.kalluri@xilinx.com>
-Quentin Schulz <quentin.schulz@cherry.de> <quentin.schulz@theobroma-systems.com>
 Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> <radhey.shyam.pandey@xilinx.com>
 Rajeshwari Shinde <rajeshwari.s@samsung.com>
 Raju Kumar Pothuraju <rajukumar.pothuraju@amd.com> <raju.kumar-pothuraju@xilinx.com>
 Ravi Patel <ravi.patel@amd.com> <ravi.patel@xilinx.com>
-Raymond Mao <raymondmaoca@gmail.com> <raymond.mao@linaro.org>
 Ricardo Ribalda <ricardo@ribalda.com> <ricardo.ribalda@gmail.com>
 Ricardo Ribalda <ricardo@ribalda.com> <ricardo.ribalda@uam.es>
 Rohit Visavalia <rohit.visavalia@amd.com> <rohit.visavalia@xilinx.com>
@@ -128,32 +97,24 @@ Ruchika Gupta <ruchika.gupta@nxp.com> <ruchika.gupta@freescale.com>
 Saeed Nowshadi <saeed.nowshadi@amd.com> <saeed.nowshadi@xilinx.com>
 Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> <lakshmi.sai.krishna.potthuri@xilinx.com>
 Sai Pavan Boddu <sai.pavan.boddu@amd.com> <sai.pavan.boddu@xilinx.com>
-Sam Protsenko <semen.protsenko@linaro.org>
-Sam Protsenko <semen.protsenko@linaro.org> <joe.skb7@gmail.com>
 Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com> <sandeep.gundlupet-raju@xilinx.com>
 Sandeep Paulraj <s-paulraj@ti.com>
 Sandeep Reddy Ghanapuram <sandeep.reddy-ghanapuram@amd.com> <sandeep.reddy-ghanapuram@xilinx.com>
-Sean Anderson <sean.anderson@linux.dev> <sean.anderson@seco.com>
 Shaohui Xie <Shaohui.Xie@freescale.com>
 Shravya Kumbham <shravya.kumbham@amd.com> <shravya.kumbham@xilinx.com>
 Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> <shubhrajyoti.datta@xilinx.com>
-Simon Glass <sjg@chromium.org> <simon.glass@canonical.com>
 Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> <siva.durga.paladugu@xilinx.com>
 Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> <sivadur@xilinx.com>
 Srinivas Goud <srinivas.goud@amd.com> <srinivas.goud@xilinx.com>
 Srinivas Neeli <srinivas.neeli@amd.com> <srinivas.neeli@xilinx.com>
-Stefan Roese <stefan.roese@mailbox.org> <stroese>
-Stefano Babic <sbabic@nabladev.com>
+Stefan Roese <sr@denx.de> <stroese>
+Stefano Babic <sbabic@denx.de>
 Stefano Stabellini <stefano.stabellini@amd.com> <stefano.stabellini@xilinx.com>
-Sughosh Ganu <sughosh.ganu@arm.com> <sughosh.ganu@linaro.org>
-No generic patch CC mail please <noreply@example.com> <swarren@wwwdotorg.org>
-No generic patch CC mail please <noreply@example.com> <swarren@nvidia.com>
-Sumit Garg <sumit.garg@kernel.org> <sumit.garg@linaro.org>
 Tom Rini <trini@konsulko.com> <trini@ti.com>
 Tomas Thoresen <tomas.thoresen@amd.com> <tomast@xilinx.com>
 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Varalaxmi Bingi <varalaxmi.bingi@amd.com> <varalaxmi.bingi@xilinx.com>
-Abbarapu Venkatesh Yadav <venkyada@qti.qualcomm.com>
+Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> <venkatesh.abbarapu@xilinx.com>
 Vikhyat Goyal <vikhyat.goyal@amd.com> <vikhyat.goyal@xilinx.com>
 Vishal Patel <vishal.patel@amd.com> <vishal.patel@xilinx.com>
 Wolfgang Denk <wd@denx.de> <wd@atlas.denx.de>
@@ -165,8 +126,6 @@ Wolfgang Denk <wd@denx.de> <wd@pollux.(none)>
 Wolfgang Denk <wd@denx.de> <wd@pollux.denx.de>
 Wolfgang Denk <wd@denx.de> <wd@xpert.denx.de>
 Wolfgang Denk <wd@denx.de> <wdenk>
-Wolfgang Wallner <wolfgang.wallner@at.abb.com> <wolfgang.wallner@br-automation.com>
-Yao Zi <me@ziyao.cc> <ziyao@disroot.org>
 York Sun <york.sun@nxp.com>
 York Sun <yorksun@freescale.com>
 Łukasz Majewski <l.majewski@samsung.com>

.readthedocs.yml

@@ -6,11 +6,11 @@
 version: 2
 
 build:
-  os: "ubuntu-24.04"
+  os: "ubuntu-20.04"
   apt_packages:
     - python3-six
   tools:
-    python: "3.12"
+    python: "3.9"
 
 # Build documentation in the docs/ directory with Sphinx
 sphinx:
@@ -22,4 +22,3 @@ formats: []
 python:
   install:
     - requirements: doc/sphinx/requirements.txt
-    - requirements: test/py/requirements.txt

COPYING

@@ -1 +0,0 @@
-Licenses/gpl-2.0.txt

Kbuild

@@ -7,11 +7,10 @@
 
 generic-offsets-file := include/generated/generic-asm-offsets.h
 
-always-y  := $(generic-offsets-file)
+always  := $(generic-offsets-file)
 targets := lib/asm-offsets.s
 
-CFLAGS_REMOVE_lib/asm-offsets.o := $(LTO_CFLAGS)
-CFLAGS_REMOVE_arch/$(ARCH)/lib/asm-offsets.o := $(LTO_CFLAGS)
+CFLAGS_REMOVE_asm-offsets.o := $(LTO_CFLAGS)
 
 $(obj)/$(generic-offsets-file): $(obj)/lib/asm-offsets.s FORCE
 	$(call filechk,offsets,__GENERIC_ASM_OFFSETS_H__)
@@ -23,11 +22,10 @@ ifneq ($(wildcard $(srctree)/arch/$(ARCH)/lib/asm-offsets.c),)
 offsets-file := include/generated/asm-offsets.h
 endif
 
-always-y  += $(offsets-file)
+always  += $(offsets-file)
 targets += arch/$(ARCH)/lib/asm-offsets.s
 
-CFLAGS_lib/asm-offsets.o := -DDO_DEPS_ONLY
-CFLAGS_arch/$(ARCH)/lib/asm-offsets.o := -DDO_DEPS_ONLY
+CFLAGS_asm-offsets.o := -DDO_DEPS_ONLY
 
 $(obj)/$(offsets-file): $(obj)/arch/$(ARCH)/lib/asm-offsets.s FORCE
 	$(call filechk,offsets,__ASM_OFFSETS_H__)

Kconfig

@@ -1,6 +1,6 @@
 #
 # For a description of the syntax of this configuration file,
-# see the file Documentation/kbuild/kconfig-language.rst in the
+# see the file Documentation/kbuild/kconfig-language.txt in the
 # Linux kernel source tree.
 #
 mainmenu "U-Boot $(UBOOTVERSION) Configuration"
@@ -27,31 +27,6 @@ config DEPRECATED
 	  code that relies on deprecated features that will be removed and
 	  the conversion deadline has passed.
 
-config COMPILE_TEST
-	bool "Compile also drivers which will not load"
-	help
-	  Some drivers can be compiled on a different platform than they are
-	  intended to be run on. Despite they cannot be loaded there (or even
-	  when they load they cannot be used due to missing HW support),
-	  developers still, opposing to distributors, might want to build such
-	  drivers to compile-test them.
-
-	  If you are a developer and want to build everything available, say Y
-	  here. If you are a user/distributor, say N here to exclude useless
-	  drivers to be distributed.
-
-config WERROR
-	bool "Compile U-Boot with warnings as errors"
-	default COMPILE_TEST
-	help
-	  A U-Boot build should not cause any compiler warnings, and this
-	  enables the '-Werror' flag to enforce that rule.
-
-	  However, if you have a new (or very old) compiler or linker with odd
-	  and unusual warnings, or you have some architecture with problems,
-	  you may need to disable this config option in order to
-	  successfully build U-Boot.
-
 config LOCALVERSION
 	string "Local version - append to U-Boot release"
 	help
@@ -140,15 +115,6 @@ config SPL_OPTIMIZE_INLINING
 	  do what it thinks is best, which is desirable in some cases for size
 	  reasons.
 
-config TPL_OPTIMIZE_INLINING
-	bool "Allow compiler to uninline functions marked 'inline' in TPL"
-	depends on TPL
-	help
-	  This option determines if U-Boot forces gcc to inline the functions
-	  developers have marked 'inline'. Doing so takes away freedom from gcc to
-	  do what it thinks is best, which is desirable in some cases for size
-	  reasons.
-
 config ARCH_SUPPORTS_LTO
 	bool
 
@@ -172,6 +138,15 @@ config LTO
 
 	  If unsure, say n.
 
+config TPL_OPTIMIZE_INLINING
+	bool "Allow compiler to uninline functions marked 'inline' in TPL"
+	depends on TPL
+	help
+	  This option determines if U-Boot forces gcc to inline the functions
+	  developers have marked 'inline'. Doing so takes away freedom from gcc to
+	  do what it thinks is best, which is desirable in some cases for size
+	  reasons.
+
 config CC_COVERAGE
 	bool "Enable code coverage analysis"
 	depends on SANDBOX
@@ -233,8 +208,7 @@ config ENV_VARS_UBOOT_CONFIG
 
 config NR_DRAM_BANKS
 	int "Number of DRAM banks"
-	default 1 if ARCH_SC5XX || ARCH_SUNXI || ARCH_OWL
-	default 2 if OMAP34XX
+	default 1 if ARCH_SUNXI || ARCH_OWL
 	default 4
 	help
 	  This defines the number of DRAM banks.
@@ -262,7 +236,6 @@ config SYS_BOOT_GET_KBD
 config HAS_CUSTOM_SYS_INIT_SP_ADDR
 	bool "Use a custom location for the initial stack pointer address"
 	depends on ARC || (ARM && !INIT_SP_RELATIVE) || MIPS || PPC || RISCV
-	default y if OMAP34XX || AM33XX || AM43XX || DRA7XX
 	default y if TFABOOT
 	help
 	  Typically, we use an initial stack pointer address that is calculated
@@ -276,10 +249,6 @@ config HAS_CUSTOM_SYS_INIT_SP_ADDR
 config CUSTOM_SYS_INIT_SP_ADDR
 	hex "Static location for the initial stack pointer"
 	depends on HAS_CUSTOM_SYS_INIT_SP_ADDR
-	default 0x4020ff00 if OMAP34XX
-	default 0x4030ff00 if AM33XX
-	default 0x4033ff00 if AM43XX
-	default 0x4037ff00 if DRA7XX
 	default TEXT_BASE if TFABOOT
 
 config SYS_MALLOC_F
@@ -296,11 +265,11 @@ config SYS_MALLOC_F_LEN
 	hex "Size of malloc() pool before relocation"
 	depends on SYS_MALLOC_F
 	default 0x400 if M68K || PPC || ROCKCHIP_PX30 || ROCKCHIP_RK3036 || \
-			 ROCKCHIP_RV1108
+			 ROCKCHIP_RK3308 || ROCKCHIP_RV1108
 	default 0x600 if ARCH_ZYNQMP_R5 || ARCH_ZYNQMP
 	default 0x800 if ARCH_ZYNQ || ROCKCHIP_RK3128 || ROCKCHIP_RK3188 || \
-			 ROCKCHIP_RK322X
-	default 0x1000 if ARCH_MESON || ARCH_BMIPS || ARCH_MTMIPS || X86
+			 ROCKCHIP_RK322X || X86
+	default 0x1000 if ARCH_MESON || ARCH_BMIPS || ARCH_MTMIPS
 	default 0x1800 if ARCH_TEGRA
 	default 0x4000 if SANDBOX || RISCV || ARCH_APPLE || ROCKCHIP_RK3368 || \
 			  ROCKCHIP_RK3399
@@ -308,22 +277,15 @@ config SYS_MALLOC_F_LEN
 	default 0x10000 if ARCH_IMX8 || ARCH_IMX8M
 	default 0x2000
 	help
-		Size of the malloc() pool for use before relocation. If
-		this is defined, then a very simple malloc() implementation
-		will become available before relocation. The address is just
-		below the global data, and the stack is moved down to make
-		space.
-
-		This feature allocates regions with increasing addresses
-		within the region. calloc() is supported, but realloc()
-		is not available. free() is supported but does nothing.
-		The memory will be freed (or in fact just forgotten) when
-		U-Boot relocates itself.
+	  Before relocation, memory is very limited on many platforms. Still,
+	  we can provide a small malloc() pool if needed. Driver model in
+	  particular needs this to operate, so that it can allocate the
+	  initial serial device and any others that are needed.
 
 config SYS_MALLOC_LEN
 	hex "Define memory for Dynamic allocation"
 	default 0x4000000 if SANDBOX
-	default 0x2000000 if ARCH_ROCKCHIP || ARCH_OMAP2PLUS || ARCH_MESON || ARCH_K3
+	default 0x2000000 if ARCH_ROCKCHIP || ARCH_OMAP2PLUS || ARCH_MESON
 	default 0x200000 if ARCH_BMIPS || X86
 	default 0x4020000 if SUNXI_MINIMUM_DRAM_MB >= 256
 	default 0x220000 if SUNXI_MINIMUM_DRAM_MB >= 64
@@ -333,49 +295,32 @@ config SYS_MALLOC_LEN
 	  This defines memory to be allocated for Dynamic allocation
 	  TODO: Use for other architectures
 
-config SPL_SYS_MALLOC_F
-	bool "Enable malloc() pool in SPL"
-	depends on SPL_FRAMEWORK && SYS_MALLOC_F && SPL
-	default y
+config SPL_SYS_MALLOC_F_LEN
+	hex "Size of malloc() pool in SPL"
+	depends on SYS_MALLOC_F && SPL
+	default 0 if !SPL_FRAMEWORK
+	default 0x2800 if RCAR_GEN3
+	default 0x2000 if IMX8MQ
+	default SYS_MALLOC_F_LEN
 	help
 	  In SPL memory is very limited on many platforms. Still,
 	  we can provide a small malloc() pool if needed. Driver model in
 	  particular needs this to operate, so that it can allocate the
 	  initial serial device and any others that are needed.
 
-config SPL_SYS_MALLOC_F_LEN
-	hex "Size of malloc() pool in SPL"
-	depends on SPL_SYS_MALLOC_F
-	default 0x2800 if RCAR_GEN3
-	default 0x2000 if IMX8MQ
-	default SYS_MALLOC_F_LEN
-	help
-	  Sets the size of the malloc() pool in SPL. This is used for
-	  driver model and other features, which must allocate memory for
-	  data structures.
-
-	  It is possible to enable CFG_SPL_SYS_MALLOC_START to start a new
+	  It is possible to enable CFG_SYS_SPL_MALLOC_START to start a new
 	  malloc() region in SDRAM once it is inited.
 
-config TPL_SYS_MALLOC_F
-	bool "Enable malloc() pool in TPL"
+config TPL_SYS_MALLOC_F_LEN
+	hex "Size of malloc() pool in TPL"
 	depends on SYS_MALLOC_F && TPL
-	default y if SPL_SYS_MALLOC_F
+	default SPL_SYS_MALLOC_F_LEN
 	help
 	  In TPL memory is very limited on many platforms. Still,
 	  we can provide a small malloc() pool if needed. Driver model in
 	  particular needs this to operate, so that it can allocate the
 	  initial serial device and any others that are needed.
 
-config TPL_SYS_MALLOC_F_LEN
-	hex "Size of malloc() pool in TPL"
-	depends on TPL_SYS_MALLOC_F
-	default SPL_SYS_MALLOC_F_LEN
-	help
-	  Sets the size of the malloc() pool in TPL. This is used for
-	  driver model and other features, which must allocate memory for
-	  data structures.
-
 config VALGRIND
 	bool "Inform valgrind about memory allocations"
 	depends on !RISCV
@@ -391,25 +336,16 @@ config VALGRIND
 	  it can be handled accurately by Valgrind. If you aren't planning on
 	  using valgrind to debug U-Boot, say 'n'.
 
-config VPL_SYS_MALLOC_F
-	bool "Enable malloc() pool in VPL"
+config VPL_SYS_MALLOC_F_LEN
+	hex "Size of malloc() pool in VPL before relocation"
 	depends on SYS_MALLOC_F && VPL
-	default y if SPL_SYS_MALLOC_F
+	default SYS_MALLOC_F_LEN
 	help
-	  In VPL memory is very limited on many platforms. Still,
+	  Before relocation, memory is very limited on many platforms. Still,
 	  we can provide a small malloc() pool if needed. Driver model in
 	  particular needs this to operate, so that it can allocate the
 	  initial serial device and any others that are needed.
 
-config VPL_SYS_MALLOC_F_LEN
-	hex "Size of malloc() pool in VPL before relocation"
-	depends on VPL_SYS_MALLOC_F
-	default SPL_SYS_MALLOC_F_LEN
-	help
-	  Sets the size of the malloc() pool in VPL. This is used for
-	  driver model and other features, which must allocate memory for
-	  data structures.
-
 menuconfig EXPERT
 	bool "Configure standard U-Boot features (expert users)"
 	default y
@@ -436,17 +372,6 @@ if EXPERT
 	  When disabling this, please check if malloc calls, maybe
 	  should be replaced by calloc - if one expects zeroed memory.
 
-config SPL_SYS_MALLOC_CLEAR_ON_INIT
-	bool "Init with zeros the memory reserved for malloc (slow) in SPL"
-	depends on SPL
-	default SYS_MALLOC_CLEAR_ON_INIT
-	help
-	  Same as SYS_MALLOC_CLEAR_ON_INIT, but for SPL. It's possible to
-	  Enable it without SYS_MALLOC_CLEAR_ON_INIT. It's useful for boards
-	  that must have particular memory regions zero'ed before first use.
-	  If SYS_SPL_MALLOC_START is configured to be in such region, this
-	  option should be enabled.
-
 config SYS_MALLOC_DEFAULT_TO_INIT
 	bool "Default malloc to init while reserving the memory for it"
 	help
@@ -468,41 +393,6 @@ config TOOLS_DEBUG
 	  it is possible to set breakpoints on particular lines, single-step
 	  debug through the source code, etc.
 
-config SKIP_EARLY_DM
-	bool "Skips initialising device model pre-relocation"
-	help
-	  Enable this option to skip scanning and probing devices prior to
-	  U-Boot relocation (during board_f). Unless console support is disabled
-	  a serial port is still required, however this can be found through
-	  /chosen/stdout-path in FDT. If the serial port relies on other devices
-	  like clocks these will also be bound and probed on demand.
-
-	  This can speed up time to interactive console by about 50%, particularly
-	  when combined with OF_LIVE.
-
-config SKIP_RELOCATE
-	bool "Skips relocation of U-Boot to end of RAM"
-	help
-	  Skips relocation of U-Boot allowing for systems that have extremely
-	  limited RAM to run U-Boot.
-
-config SKIP_RELOCATE_CODE
-	bool
-	help
-	  Skips relocation of U-Boot code to the end of RAM, but still does
-	  relocate data to the end of RAM. This is mainly meant to relocate
-	  data to read-write portion of the RAM, while the code remains in
-	  read-only portion of the RAM from which it is allowed to execute.
-	  This split configuration is present on various secure cores.
-
-config SKIP_RELOCATE_CODE_DATA_OFFSET
-	hex
-	default 0x0
-	depends on SKIP_RELOCATE_CODE
-	help
-	  Offset of the read-write memory which contains data, from read-only
-	  memory which contains executable text.
-
 endif # EXPERT
 
 config PHYS_64BIT
@@ -540,7 +430,6 @@ config SPL_IMAGE
 
 config REMAKE_ELF
 	bool "Recreate an ELF image from raw U-Boot binary"
-	depends on !COMPILE_TEST
 	help
 	  Enable this to recreate an ELF image (u-boot.elf) from the raw
 	  U-Boot binary (u-boot.bin), which may already have been statically
@@ -551,10 +440,10 @@ config BUILD_TARGET
 	default "u-boot-elf.srec" if RCAR_64
 	default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
 	default "u-boot-with-spl.bin" if MPC85xx && !E500MC && !E5500 && !E6500 && SPL
-	default "u-boot-with-spl.imx" if (ARCH_MX6 || ARCH_MX7) && SPL
+	default "u-boot-with-spl.imx" if ARCH_MX6 && SPL
 	default "u-boot-with-spl.kwb" if ARMADA_32BIT && SPL
-	default "u-boot-with-spl.sfp" if ARCH_SOCFPGA_ARRIA10
-	default "u-boot-with-spl.sfp" if ARCH_SOCFPGA_GEN5
+	default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_ARRIA10
+	default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_GEN5
 	default "u-boot.itb" if !BINMAN && SPL_LOAD_FIT && (ARCH_ROCKCHIP || \
 				RISCV || ARCH_ZYNQMP)
 	default "u-boot.kwb" if (ARCH_KIRKWOOD || ARMADA_32BIT) && !SPL
@@ -567,26 +456,23 @@ config BUILD_TARGET
 
 config HAS_BOARD_SIZE_LIMIT
 	bool "Define a maximum size for the U-Boot image"
-	depends on !COMPILE_TEST
-	default y if RCAR_32 || RCAR_64
+	default y if RCAR_64
 	help
 	  In some cases, we need to enforce a hard limit on how big the U-Boot
 	  image itself can be.
 
 config BOARD_SIZE_LIMIT
 	int "Maximum size of the U-Boot image in bytes"
-	default 524288 if RCAR_32
 	default 1048576 if RCAR_64
 	depends on HAS_BOARD_SIZE_LIMIT
 	help
 	  Maximum size of the U-Boot image. When defined, the build system
 	  checks that the actual size does not exceed it.  This does not
 	  include SPL nor TPL, on platforms that use that functionality, they
-	  have separate options to restrict size.
+	  have a separate option to restict size.
 
 config SYS_CUSTOM_LDSCRIPT
 	bool "Use a custom location for the U-Boot linker script"
-	depends on !COMPILE_TEST
 	help
 	  Normally when linking U-Boot we will look in the board directory,
 	  the CPU directory and finally the "cpu" directory of the architecture
@@ -614,7 +500,6 @@ config SYS_LOAD_ADDR
 	default 0x12000000 if ARCH_MX6 && !(MX6SL || MX6SLL  || MX6SX || MX6UL || MX6ULL)
 	default 0x80800000 if ARCH_MX7
 	default 0x90000000 if FSL_LSCH2 || FSL_LSCH3
-	default 0x0 if ARCH_SC5XX
 	help
 	  Address in memory to use as the default safe load address.
 
@@ -641,14 +526,11 @@ config STACK_SIZE
 	hex "Define max stack size that can be used by U-Boot"
 	default 0x4000000 if ARCH_VERSAL_NET || ARCH_VERSAL || ARCH_ZYNQMP
 	default 0x200000 if MICROBLAZE
-	default 0x4000 if ARCH_STM32
 	default 0x1000000
 	help
-	  Define Max stack size that can be used by U-Boot. The UEFI sub-system
-	  considers this value when setting up the memory map. The UEFI
-	  specification requires 128 KiB or more of available stack space. On
-	  some boards initrd_high is calculated as base stack pointer minus this
-	  stack size.
+	  Define Max stack size that can be used by U-Boot. This value is used
+	  by the UEFI sub-system. On some boards initrd_high is calculated as
+	  base stack pointer minus this stack size.
 
 config SYS_MEM_TOP_HIDE
 	hex "Exclude some memory from U-Boot / OS information"
@@ -661,10 +543,33 @@ config SYS_MEM_TOP_HIDE
 	  WARNING: Please make sure that this value is a multiple of the OS
 	  page size.
 
+config SYS_HAS_SRAM
+	bool
+	default y if TARGET_PIC32MZDASK
+	default y if TARGET_DEVKIT8000
+	default y if TARGET_TRICORDER
+	help
+	  Enable this to allow support for the on board SRAM.
+	  SRAM base address is controlled by CONFIG_SYS_SRAM_BASE.
+	  SRAM size is controlled by CONFIG_SYS_SRAM_SIZE.
+
+config SYS_SRAM_BASE
+	hex
+	default 0x80000000 if TARGET_PIC32MZDASK
+	default 0x40200000 if TARGET_DEVKIT8000
+	default 0x40200000 if TARGET_TRICORDER
+	default 0x0
+
+config SYS_SRAM_SIZE
+	hex
+	default 0x00080000 if TARGET_PIC32MZDASK
+	default 0x10000 if TARGET_DEVKIT8000
+	default 0x10000 if TARGET_TRICORDER
+	default 0x0
+
 config SYS_MONITOR_LEN
 	int "Maximum size in bytes reserved for U-Boot in memory"
 	default 1048576 if X86
-	default 262144 if OMAP34XX
 	default 786432 if ARCH_SUNXI
 	default 0
 	help
@@ -680,117 +585,10 @@ config MP
 	  This provides an option to bringup different processors
 	  in multiprocessor cases.
 
-config HAVE_TEXT_BASE
-	bool
-	depends on !NIOS2 && !XTENSA
-	depends on !EFI_APP
-	default y
-
-config TEXT_BASE
-	depends on HAVE_TEXT_BASE
-	default 0x0 if POSITION_INDEPENDENT
-	default 0x17800000 if ARCH_MX6
-	default 0x87800000 if ARCH_MX7
-	default 0x80800000 if ARCH_OMAP2PLUS || ARCH_K3
-	default 0x81700000 if MACH_SUNIV
-	default 0x2a000000 if MACH_SUN9I
-	default 0x4a000000 if SUNXI_MINIMUM_DRAM_MB >= 256
-	default 0x42e00000 if SUNXI_MINIMUM_DRAM_MB >= 64
-	default 0x96000000 if ARCH_SC5XX && SC59X_64
-	default 0xB2200000 if ARCH_SC5XX && SC59X
-	default 0x89200000 if ARCH_SC5XX && TARGET_SC584_EZKIT
-	default 0xC2200000 if ARCH_SC5XX && (TARGET_SC589_EZKIT || TARGET_SC589_MINI)
-	default 0x82200000 if ARCH_SC5XX && SC57X
-	hex "Text Base"
-	help
-	  The address in memory that U-Boot will be copied and executed from
-	  initially.
-
-config HAVE_SYS_UBOOT_START
-	bool "Use custom U-Boot Start"
-	depends on HAVE_TEXT_BASE
-	help
-	  By default, the address in memory that U-Boot will be copied from
-	  (TEXT_BASE) and the entry point are the same. Select this to start the
-	  execution of U-Boot from a different address.
-	  This may be required if a header or vector table needs to be copied
-	  but not executed.
-
-config SYS_UBOOT_START
-	hex
-	depends on HAVE_TEXT_BASE
-	default TEXT_BASE
-	prompt "U-Boot entry" if HAVE_SYS_UBOOT_START
-	help
-	  If TEXT_BASE differs from the start of execution, this sets the
-	  address in memory that U-Boot will start execution from initially.
-
-config HAVE_SYS_MONITOR_BASE
-	bool
-	depends on ARC || MIPS || M68K || NIOS2 || PPC || XTENSA || X86 \
-		|| ENV_IS_IN_FLASH || MTD_NOR_FLASH
-	depends on !EFI_APP
-	default y
-
-config SYS_MONITOR_BASE
-	depends on HAVE_SYS_MONITOR_BASE
-	hex "Physical start address of boot monitor code"
-	default TEXT_BASE
-	help
-	  The physical start address of boot monitor code (which is the same as
-	  CONFIG_TEXT_BASE when linking) and the same as CFG_SYS_FLASH_BASE
-	  when booting from flash.
-
-config SPL_SYS_MONITOR_BASE
-	depends on MPC85xx && SPL && HAVE_SYS_MONITOR_BASE
-	hex "Physical start address of SPL monitor code"
-	default SPL_TEXT_BASE
-
-config TPL_SYS_MONITOR_BASE
-	depends on MPC85xx && TPL && HAVE_SYS_MONITOR_BASE
-	hex "Physical start address of TPL monitor code"
-
-config DYNAMIC_SYS_CLK_FREQ
-	bool "Determine CPU clock frequency at run-time"
-	depends on !COMPILE_TEST
-	help
-	  Implement a get_board_sys_clk function that will determine the CPU
-	  clock frequency at run time, rather than define it statically.
-
-config SYS_CLK_FREQ
-	depends on !DYNAMIC_SYS_CLK_FREQ
-	int "CPU clock frequency"
-	default 125000000 if ARCH_LS1012A
-	default 100000000 if ARCH_P2020 || ARCH_T1024 || ARCH_T1042 || \
-			     ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
-	default 66666666 if ARCH_P1010 || ARCH_P1020 || ARCH_T4240
-	default 66660000 if ARCH_T2080
-	default 33333333 if RCAR_GEN3
-	default 24000000 if ARCH_EXYNOS
-	default 20000000 if RCAR_GEN2
-	default 0
-	help
-	  A static value for the CPU frequency.  Note that if not required
-	  for a given SoC, this can be left at 0.
-
-config HAS_LDR
-	bool
-	help
-	  Enables building .ldr targets for U-Boot and SPL. This does not
-	  automatically build any additional targets with make or buildman.
-
-config LDR_CPU
-	string "CPU name to be passed to LDR utility."
-	depends on HAS_LDR
-	help
-	  Set the CPU name for the -T parameter in the LDR utility.  This is
-	  generally used on processors from Analog Devices, but may be also
-	  be useful for other vendors.
+endmenu		# General setup
 
 source "api/Kconfig"
 
-endmenu		# General setup
-
 source "boot/Kconfig"
 
 source "common/Kconfig"

README

@@ -1,4 +1,4 @@
- # SPDX-License-Identifier: GPL-2.0+
+# SPDX-License-Identifier: GPL-2.0+
 #
 # (C) Copyright 2000 - 2013
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -133,6 +133,96 @@ run some of U-Boot's tests.
 
 See doc/arch/sandbox/sandbox.rst for more details.
 
+
+Board Initialisation Flow:
+--------------------------
+
+This is the intended start-up flow for boards. This should apply for both
+SPL and U-Boot proper (i.e. they both follow the same rules).
+
+Note: "SPL" stands for "Secondary Program Loader," which is explained in
+more detail later in this file.
+
+At present, SPL mostly uses a separate code path, but the function names
+and roles of each function are the same. Some boards or architectures
+may not conform to this.  At least most ARM boards which use
+CONFIG_SPL_FRAMEWORK conform to this.
+
+Execution typically starts with an architecture-specific (and possibly
+CPU-specific) start.S file, such as:
+
+	- arch/arm/cpu/armv7/start.S
+	- arch/powerpc/cpu/mpc83xx/start.S
+	- arch/mips/cpu/start.S
+
+and so on. From there, three functions are called; the purpose and
+limitations of each of these functions are described below.
+
+lowlevel_init():
+	- purpose: essential init to permit execution to reach board_init_f()
+	- no global_data or BSS
+	- there is no stack (ARMv7 may have one but it will soon be removed)
+	- must not set up SDRAM or use console
+	- must only do the bare minimum to allow execution to continue to
+		board_init_f()
+	- this is almost never needed
+	- return normally from this function
+
+board_init_f():
+	- purpose: set up the machine ready for running board_init_r():
+		i.e. SDRAM and serial UART
+	- global_data is available
+	- stack is in SRAM
+	- BSS is not available, so you cannot use global/static variables,
+		only stack variables and global_data
+
+	Non-SPL-specific notes:
+	- dram_init() is called to set up DRAM. If already done in SPL this
+		can do nothing
+
+	SPL-specific notes:
+	- you can override the entire board_init_f() function with your own
+		version as needed.
+	- preloader_console_init() can be called here in extremis
+	- should set up SDRAM, and anything needed to make the UART work
+	- there is no need to clear BSS, it will be done by crt0.S
+	- for specific scenarios on certain architectures an early BSS *can*
+	  be made available (via CONFIG_SPL_EARLY_BSS by moving the clearing
+	  of BSS prior to entering board_init_f()) but doing so is discouraged.
+	  Instead it is strongly recommended to architect any code changes
+	  or additions such to not depend on the availability of BSS during
+	  board_init_f() as indicated in other sections of this README to
+	  maintain compatibility and consistency across the entire code base.
+	- must return normally from this function (don't call board_init_r()
+		directly)
+
+Here the BSS is cleared. For SPL, if CONFIG_SPL_STACK_R is defined, then at
+this point the stack and global_data are relocated to below
+CONFIG_SPL_STACK_R_ADDR. For non-SPL, U-Boot is relocated to run at the top of
+memory.
+
+board_init_r():
+	- purpose: main execution, common code
+	- global_data is available
+	- SDRAM is available
+	- BSS is available, all static/global variables can be used
+	- execution eventually continues to main_loop()
+
+	Non-SPL-specific notes:
+	- U-Boot is relocated to the top of memory and is now running from
+		there.
+
+	SPL-specific notes:
+	- stack is optionally in SDRAM, if CONFIG_SPL_STACK_R is defined and
+		CONFIG_SYS_FSL_HAS_CCI400
+
+		Defined For SoC that has cache coherent interconnect
+		CCN-400
+
+		CONFIG_SYS_FSL_HAS_CCN504
+
+		Defined for SoC that has cache coherent interconnect CCN-504
+
 The following options need to be configured:
 
 - CPU Type:	Define exactly one, e.g. CONFIG_MPC85XX.
@@ -210,6 +300,13 @@ The following options need to be configured:
 		different from COUNTER_FREQUENCY, and can only be determined
 		at run time.
 
+- Tegra SoC options:
+		CONFIG_TEGRA_SUPPORT_NON_SECURE
+
+		Support executing U-Boot in non-secure (NS) mode. Certain
+		impossible actions will be skipped if the CPU is in NS mode,
+		such as ARM architectural timer initialization.
+
 - Linux Kernel Interface:
 		CONFIG_OF_LIBFDT
 
@@ -300,6 +397,28 @@ The following options need to be configured:
 		Note that if the GPIO device uses I2C, then the I2C interface
 		must also be configured. See I2C Support, below.
 
+- I/O tracing:
+		When CONFIG_IO_TRACE is selected, U-Boot intercepts all I/O
+		accesses and can checksum them or write a list of them out
+		to memory. See the 'iotrace' command for details. This is
+		useful for testing device drivers since it can confirm that
+		the driver behaves the same way before and after a code
+		change. Currently this is supported on sandbox and arm. To
+		add support for your architecture, add '#include <iotrace.h>'
+		to the bottom of arch/<arch>/include/asm/io.h and test.
+
+		Example output from the 'iotrace stats' command is below.
+		Note that if the trace buffer is exhausted, the checksum will
+		still continue to operate.
+
+			iotrace is enabled
+			Start:  10000000	(buffer start address)
+			Size:   00010000	(buffer size)
+			Offset: 00000120	(current buffer offset)
+			Output: 10000120	(start + offset)
+			Count:  00000018	(number of trace records)
+			CRC32:  9526fb66	(CRC32 of all trace records)
+
 - Timestamp Support:
 
 		When CONFIG_TIMESTAMP is selected, the timestamp
@@ -357,6 +476,15 @@ The following options need to be configured:
 		CONFIG_SH_ETHER
 		Support for Renesas on-chip Ethernet controller
 
+			CFG_SH_ETHER_USE_PORT
+			Define the number of ports to be used
+
+			CFG_SH_ETHER_PHY_ADDR
+			Define the ETH PHY's address
+
+			CFG_SH_ETHER_CACHE_WRITEBACK
+			If this option is set, the driver enables cache flush.
+
 - TPM Support:
 		CONFIG_TPM
 		Support TPM devices.
@@ -368,6 +496,17 @@ The following options need to be configured:
 			CONFIG_TPM_TIS_I2C_BURST_LIMITATION
 			Define the burst count bytes upper limit
 
+		CONFIG_TPM_ST33ZP24
+		Support for STMicroelectronics TPM devices. Requires DM_TPM support.
+
+			CONFIG_TPM_ST33ZP24_I2C
+			Support for STMicroelectronics ST33ZP24 I2C devices.
+			Requires TPM_ST33ZP24 and I2C.
+
+			CONFIG_TPM_ST33ZP24_SPI
+			Support for STMicroelectronics ST33ZP24 SPI devices.
+			Requires TPM_ST33ZP24 and SPI.
+
 		CONFIG_TPM_ATMEL_TWI
 		Support for Atmel TWI TPM device. Requires I2C support.
 
@@ -440,6 +579,18 @@ The following options need to be configured:
 			for your device
 			- CONFIG_USBD_PRODUCTID 0xFFFF
 
+- ULPI Layer Support:
+		The ULPI (UTMI Low Pin (count) Interface) PHYs are supported via
+		the generic ULPI layer. The generic layer accesses the ULPI PHY
+		via the platform viewport, so you need both the genric layer and
+		the viewport enabled. Currently only Chipidea/ARC based
+		viewport is supported.
+		To enable the ULPI layer support, define CONFIG_USB_ULPI and
+		CONFIG_USB_ULPI_VIEWPORT in your board configuration file.
+		If your ULPI phy needs a different reference clock than the
+		standard 24 MHz then you have to define CFG_ULPI_REF_CLK to
+		the appropriate value in Hz.
+
 - MMC Support:
 		CONFIG_SH_MMCIF
 		Support for Renesas on-chip MMCIF controller
@@ -597,12 +748,51 @@ The following options need to be configured:
 
 		A byte containing the id of the VLAN.
 
+- Status LED:	CONFIG_LED_STATUS
+
+		Several configurations allow to display the current
+		status using a LED. For instance, the LED will blink
+		fast while running U-Boot code, stop blinking as
+		soon as a reply to a BOOTP request was received, and
+		start blinking slow once the Linux kernel is running
+		(supported by a status LED driver in the Linux
+		kernel). Defining CONFIG_LED_STATUS enables this
+		feature in U-Boot.
+
+		Additional options:
+
+		CONFIG_LED_STATUS_GPIO
+		The status LED can be connected to a GPIO pin.
+		In such cases, the gpio_led driver can be used as a
+		status LED backend implementation. Define CONFIG_LED_STATUS_GPIO
+		to include the gpio_led driver in the U-Boot binary.
+
+		CFG_GPIO_LED_INVERTED_TABLE
+		Some GPIO connected LEDs may have inverted polarity in which
+		case the GPIO high value corresponds to LED off state and
+		GPIO low value corresponds to LED on state.
+		In such cases CFG_GPIO_LED_INVERTED_TABLE may be defined
+		with a list of GPIO LEDs that have inverted polarity.
+
 - I2C Support:
 		CFG_SYS_NUM_I2C_BUSES
 		Hold the number of i2c buses you want to use.
 
+		CFG_SYS_I2C_DIRECT_BUS
+		define this, if you don't use i2c muxes on your hardware.
+		if CFG_SYS_I2C_MAX_HOPS is not defined or == 0 you can
+		omit this define.
+
+		CFG_SYS_I2C_MAX_HOPS
+		define how many muxes are maximal consecutively connected
+		on one i2c bus. If you not use i2c muxes, omit this
+		define.
+
 		CFG_SYS_I2C_BUSES
-		hold a list of buses you want to use
+		hold a list of buses you want to use, only used if
+		CFG_SYS_I2C_DIRECT_BUS is not defined, for example
+		a board with CFG_SYS_I2C_MAX_HOPS = 1 and
+		CFG_SYS_NUM_I2C_BUSES = 9:
 
 		 CFG_SYS_I2C_BUSES	{{0, {I2C_NULL_HOP}}, \
 					{0, {{I2C_MUX_PCA9547, 0x70, 1}}}, \
@@ -628,6 +818,110 @@ The following options need to be configured:
 
 		If you do not have i2c muxes on your board, omit this define.
 
+- Legacy I2C Support:
+		If you use the software i2c interface (CONFIG_SYS_I2C_SOFT)
+		then the following macros need to be defined (examples are
+		from include/configs/lwmon.h):
+
+		I2C_INIT
+
+		(Optional). Any commands necessary to enable the I2C
+		controller or configure ports.
+
+		eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |=	PB_SCL)
+
+		I2C_ACTIVE
+
+		The code necessary to make the I2C data line active
+		(driven).  If the data line is open collector, this
+		define can be null.
+
+		eg: #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |=  PB_SDA)
+
+		I2C_TRISTATE
+
+		The code necessary to make the I2C data line tri-stated
+		(inactive).  If the data line is open collector, this
+		define can be null.
+
+		eg: #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
+
+		I2C_READ
+
+		Code that returns true if the I2C data line is high,
+		false if it is low.
+
+		eg: #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+
+		I2C_SDA(bit)
+
+		If <bit> is true, sets the I2C data line high. If it
+		is false, it clears it (low).
+
+		eg: #define I2C_SDA(bit) \
+			if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else	immr->im_cpm.cp_pbdat &= ~PB_SDA
+
+		I2C_SCL(bit)
+
+		If <bit> is true, sets the I2C clock line high. If it
+		is false, it clears it (low).
+
+		eg: #define I2C_SCL(bit) \
+			if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else	immr->im_cpm.cp_pbdat &= ~PB_SCL
+
+		I2C_DELAY
+
+		This delay is invoked four times per clock cycle so this
+		controls the rate of data transfer.  The data rate thus
+		is 1 / (I2C_DELAY * 4). Often defined to be something
+		like:
+
+		#define I2C_DELAY  udelay(2)
+
+		CONFIG_SOFT_I2C_GPIO_SCL / CONFIG_SOFT_I2C_GPIO_SDA
+
+		If your arch supports the generic GPIO framework (asm/gpio.h),
+		then you may alternatively define the two GPIOs that are to be
+		used as SCL / SDA.  Any of the previous I2C_xxx macros will
+		have GPIO-based defaults assigned to them as appropriate.
+
+		You should define these to the GPIO value as given directly to
+		the generic GPIO functions.
+
+		CFG_I2C_MULTI_BUS
+
+		This option allows the use of multiple I2C buses, each of which
+		must have a controller.	 At any point in time, only one bus is
+		active.	 To switch to a different bus, use the 'i2c dev' command.
+		Note that bus numbering is zero-based.
+
+		CFG_SYS_I2C_NOPROBES
+
+		This option specifies a list of I2C devices that will be skipped
+		when the 'i2c probe' command is issued.
+
+		e.g.
+			#define CFG_SYS_I2C_NOPROBES {0x50,0x68}
+
+		will skip addresses 0x50 and 0x68 on a board with one I2C bus
+
+		CFG_SYS_RTC_BUS_NUM
+
+		If defined, then this indicates the I2C bus number for the RTC.
+		If not defined, then U-Boot assumes that RTC is on I2C bus 0.
+
+		CONFIG_SOFT_I2C_READ_REPEATED_START
+
+		defining this will force the i2c_read() function in
+		the soft_i2c driver to perform an I2C repeated start
+		between writing the address pointer and reading the
+		data.  If this define is omitted the default behaviour
+		of doing a stop-start sequence will be used.  Most I2C
+		devices can use either method, but some require one or
+		the other.
+
 - SPI Support:	CONFIG_SPI
 
 		Enables SPI driver (so far only tested with
@@ -790,6 +1084,15 @@ The following options need to be configured:
 		the environment like the "source" command or the
 		boot command first.
 
+		CONFIG_DELAY_ENVIRONMENT
+
+		Normally the environment is loaded when the board is
+		initialised so that it is available to U-Boot. This inhibits
+		that so that the environment is not available until
+		explicitly loaded later by U-Boot code. With CONFIG_OF_CONTROL
+		this is instead controlled by the value of
+		/config/load-environment.
+
 - Automatic software updates via TFTP server
 		CONFIG_UPDATE_TFTP
 		CONFIG_UPDATE_TFTP_CNT_MAX
@@ -888,10 +1191,11 @@ The following options need to be configured:
 		Support for a lightweight UBI (fastmap) scanner and
 		loader
 
-		CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_SIZE,
-		CONFIG_SYS_NAND_OOBSIZE, CONFIG_SYS_NAND_BLOCK_SIZE,
-		CONFIG_SYS_NAND_BAD_BLOCK_POS, CFG_SYS_NAND_ECCPOS,
-		CFG_SYS_NAND_ECCSIZE, CFG_SYS_NAND_ECCBYTES
+		CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
+		CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
+		CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
+		CFG_SYS_NAND_ECCPOS, CFG_SYS_NAND_ECCSIZE,
+		CFG_SYS_NAND_ECCBYTES
 		Defines the size and behavior of the NAND that SPL uses
 		to read U-Boot
 
@@ -944,6 +1248,9 @@ typically in board_init_f() and board_init_r().
 Configuration Settings:
 -----------------------
 
+- MEM_SUPPORT_64BIT_DATA: Defined automatically if compiled as 64-bit.
+		Optionally it can be defined to support 64-bit memory commands.
+
 - CONFIG_SYS_LONGHELP: Defined when you want long help messages included;
 		undefine this when you're short of memory.
 
@@ -974,6 +1281,24 @@ Configuration Settings:
 - CONFIG_SYS_MALLOC_LEN:
 		Size of DRAM reserved for malloc() use.
 
+- CONFIG_SYS_MALLOC_F_LEN
+		Size of the malloc() pool for use before relocation. If
+		this is defined, then a very simple malloc() implementation
+		will become available before relocation. The address is just
+		below the global data, and the stack is moved down to make
+		space.
+
+		This feature allocates regions with increasing addresses
+		within the region. calloc() is supported, but realloc()
+		is not available. free() is supported but does nothing.
+		The memory will be freed (or in fact just forgotten) when
+		U-Boot relocates itself.
+
+- CONFIG_SYS_MALLOC_SIMPLE
+		Provides a simple and small malloc() and calloc() for those
+		boards which do not use the full malloc in SPL (which is
+		enabled with CONFIG_SYS_SPL_MALLOC).
+
 - CFG_SYS_BOOTMAPSZ:
 		Maximum size of memory mapped by the startup code of
 		the Linux kernel; all data that must be processed by
@@ -1098,6 +1423,9 @@ Note: once the monitor has been relocated, then it will complain if
 the default environment is used; a new CRC is computed as soon as you
 use the "saveenv" command to store a valid environment.
 
+- CONFIG_SYS_FAULT_MII_ADDR:
+		MII address of the PHY to check for the Ethernet link state.
+
 - CONFIG_DISPLAY_BOARDINFO
 		Display information about the board that U-Boot is running on
 		when U-Boot starts up. The board function checkboard() is called
@@ -1234,23 +1562,17 @@ Low Level (hardware related) configuration options:
 		This only takes effect if the memory commands are activated
 		globally (CONFIG_CMD_MEMORY).
 
-- CONFIG_XPL_BUILD
-		Set when the currently running compilation is for an artifact
-		that will end up in one of the 'xPL' builds, i.e. SPL, TPL or
-		VPL. Code that needs phase-specific behaviour can check this,
-		or (where possible) use xpl_phase() instead.
+- CONFIG_SPL_BUILD
+		Set when the currently-running compilation is for an artifact
+		that will end up in the SPL (as opposed to the TPL or U-Boot
+		proper). Code that needs stage-specific behavior should check
+		this.
 
 - CONFIG_TPL_BUILD
-		Set when the currently running compilation is for an artifact
-		that will end up in the TPL build (as opposed to SPL, VPL or
-		U-Boot proper). Code that needs phase-specific behaviour can
-		check this, or (where possible) use xpl_phase() instead.
-
-- CONFIG_VPL_BUILD
-		Set when the currently running compilation is for an artifact
-		that will end up in the VPL build (as opposed to the SPL, TPL
-		or U-Boot proper). Code that needs phase-specific behaviour can
-		check this, or (where possible) use xpl_phase() instead.
+		Set when the currently-running compilation is for an artifact
+		that will end up in the TPL (as opposed to the SPL or U-Boot
+		proper). Code that needs stage-specific behavior should check
+		this.
 
 - CONFIG_ARCH_MAP_SYSMEM
 		Generally U-Boot (and in particular the md command) uses
@@ -1381,6 +1703,26 @@ images ready for download to / installation on your system:
 - "u-boot" is an image in ELF binary format
 - "u-boot.srec" is in Motorola S-Record format
 
+By default the build is performed locally and the objects are saved
+in the source directory. One of the two methods can be used to change
+this behavior and build U-Boot to some external directory:
+
+1. Add O= to the make command line invocations:
+
+	make O=/tmp/build distclean
+	make O=/tmp/build NAME_defconfig
+	make O=/tmp/build all
+
+2. Set environment variable KBUILD_OUTPUT to point to the desired location:
+
+	export KBUILD_OUTPUT=/tmp/build
+	make distclean
+	make NAME_defconfig
+	make all
+
+Note that the command line "O=" setting overrides the KBUILD_OUTPUT environment
+variable.
+
 User specific CPPFLAGS, AFLAGS and CFLAGS can be passed to the compiler by
 setting the according environment variables KCPPFLAGS, KAFLAGS and KCFLAGS.
 For example to treat all compiler warnings as errors:
@@ -1544,7 +1886,7 @@ New uImage format (FIT)
 Flexible and powerful format based on Flattened Image Tree -- FIT (similar
 to Flattened Device Tree). It allows the use of images with multiple
 components (several kernels, ramdisks, etc.), with contents protected by
-SHA1, MD5 or CRC32. More details are found in the doc/usage/fit directory.
+SHA1, MD5 or CRC32. More details are found in the doc/uImage.FIT directory.
 
 
 Old uImage format
@@ -2088,6 +2430,27 @@ Hit 'q':
 	[q, b, e, ?] ## Application terminated, rc = 0x0
 
 
+Minicom warning:
+================
+
+Over time, many people have reported problems when trying to use the
+"minicom" terminal emulation program for serial download. I (wd)
+consider minicom to be broken, and recommend not to use it. Under
+Unix, I recommend to use C-Kermit for general purpose use (and
+especially for kermit binary protocol download ("loadb" command), and
+use "cu" for S-Record download ("loads" command).  See
+https://www.denx.de/wiki/view/DULG/SystemSetup#Section_4.3.
+for help with kermit.
+
+
+Nevertheless, if you absolutely want to use it try adding this
+configuration to your "File transfer protocols" section:
+
+	   Name	   Program			Name U/D FullScr IO-Red. Multi
+	X  kermit  /usr/bin/kermit -i -l %l -s	 Y    U	   Y	   N	  N
+	Y  kermit  /usr/bin/kermit -i -l %l -r	 N    D	   Y	   N	  N
+
+
 Implementation Internals:
 =========================
 
@@ -2238,6 +2601,51 @@ On RISC-V, the following registers are used:
 
     ==> U-Boot will use gp to hold a pointer to the global data
 
+Memory Management:
+------------------
+
+U-Boot runs in system state and uses physical addresses, i.e. the
+MMU is not used either for address mapping nor for memory protection.
+
+The available memory is mapped to fixed addresses using the memory
+controller. In this process, a contiguous block is formed for each
+memory type (Flash, SDRAM, SRAM), even when it consists of several
+physical memory banks.
+
+U-Boot is installed in the first 128 kB of the first Flash bank (on
+TQM8xxL modules this is the range 0x40000000 ... 0x4001FFFF). After
+booting and sizing and initializing DRAM, the code relocates itself
+to the upper end of DRAM. Immediately below the U-Boot code some
+memory is reserved for use by malloc() [see CONFIG_SYS_MALLOC_LEN
+configuration setting]. Below that, a structure with global Board
+Info data is placed, followed by the stack (growing downward).
+
+Additionally, some exception handler code is copied to the low 8 kB
+of DRAM (0x00000000 ... 0x00001FFF).
+
+So a typical memory configuration with 16 MB of DRAM could look like
+this:
+
+	0x0000 0000	Exception Vector code
+	      :
+	0x0000 1FFF
+	0x0000 2000	Free for Application Use
+	      :
+	      :
+
+	      :
+	      :
+	0x00FB FF20	Monitor Stack (Growing downward)
+	0x00FB FFAC	Board Info Data and permanent copy of global data
+	0x00FC 0000	Malloc Arena
+	      :
+	0x00FD FFFF
+	0x00FE 0000	RAM Copy of Monitor Code
+	...		eventually: LCD or video framebuffer
+	...		eventually: pRAM (Protected RAM - unchanged by reset)
+	0x00FF FFFF	[End of RAM]
+
+
 System Initialization:
 ----------------------
 
@@ -2281,5 +2689,5 @@ Contributing
 
 The U-Boot projects depends on contributions from the user community.
 If you want to participate, please, have a look at the 'General'
-section of https://docs.u-boot-project.org/en/latest/develop/index.html
+section of https://u-boot.readthedocs.io/en/latest/develop/index.html
 where we describe coding standards and the patch submission process.

api/Kconfig

@@ -19,4 +19,24 @@ config EXAMPLES
 	  U-Boot provides an API for standalone applications. Examples are
 	  provided in directory examples/.
 
+config STANDALONE_LOAD_ADDR
+	depends on EXAMPLES
+	hex "Address in memory to link standalone applications to"
+	default 0xffffffff80200000 if MIPS && 64BIT
+	default 0x8c000000 if SH
+	default 0x82000000 if ARC
+	default 0x80f00000 if MICROBLAZE
+	default 0x80300000 if ARCH_OMAP2PLUS || FSL_LSCH2 || FSL_LSCH3
+	default 0x80200000 if MIPS && 32BIT
+	default 0x0c100000 if ARM
+	default 0x02000000 if NIOS2
+	default 0x00040000 if PPC || X86
+	default 0x00020000 if M68K
+	default 0x0 if RISCV
+	default SYS_LOAD_ADDR
+	help
+	  This option defines a board specific value for the address where
+	  standalone program gets loaded, thus overwriting the architecture
+	  dependent default settings.
+
 endmenu

api/Makefile

@@ -1,11 +1,8 @@
-# SPDX-License-Identifier: GPL-2.0-or-later
+# SPDX-License-Identifier: GPL-2.0+
 #
 # (C) Copyright 2007 Semihalf
 
 obj-y += api.o api_display.o api_net.o api_storage.o
-
-ifeq (CONFIG_PPC,y)
+obj-$(CONFIG_ARM) += api_platform-arm.o
 obj-$(CONFIG_PPC) += api_platform-powerpc.o
-else
-obj-y += api_platform.o
-endif
+obj-$(CONFIG_MIPS) += api_platform-mips.o

api/api.c

@@ -7,13 +7,11 @@
 
 #include <config.h>
 #include <command.h>
+#include <common.h>
 #include <env.h>
 #include <malloc.h>
-#include <time.h>
 #include <env_internal.h>
-#include <vsprintf.h>
 #include <linux/delay.h>
-#include <linux/errno.h>
 #include <linux/types.h>
 #include <api_public.h>
 #include <u-boot/crc.h>
@@ -180,6 +178,7 @@ static int API_get_timer(va_list ap)
 	return 0;
 }
 
+
 /*****************************************************************************
  *
  * pseudo signature:
@@ -229,6 +228,7 @@ static int API_dev_enum(va_list ap)
 	return 0;
 }
 
+
 static int API_dev_open(va_list ap)
 {
 	struct device_info *di;
@@ -260,6 +260,7 @@ static int API_dev_open(va_list ap)
 	return err;
 }
 
+
 static int API_dev_close(va_list ap)
 {
 	struct device_info *di;
@@ -294,6 +295,7 @@ static int API_dev_close(va_list ap)
 	return err;
 }
 
+
 /*
  * pseudo signature:
  *
@@ -372,6 +374,7 @@ static int API_dev_write(va_list ap)
 	return err;
 }
 
+
 /*
  * pseudo signature:
  *
@@ -457,6 +460,7 @@ static int API_dev_read(va_list ap)
 	return 0;
 }
 
+
 /*
  * pseudo signature:
  *

api/api_display.c

@@ -3,9 +3,9 @@
  * Copyright (c) 2011 The Chromium OS Authors.
  */
 
+#include <common.h>
 #include <api_public.h>
 #include <log.h>
-#include <linux/types.h>
 
 /* TODO(clchiou): add support of video device */
 

api/api_net.c

@@ -6,6 +6,7 @@
  */
 
 #include <config.h>
+#include <common.h>
 #include <net.h>
 #include <linux/types.h>
 #include <api_public.h>

api/api_platform-arm.c

@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007 Semihalf
+ *
+ * Written by: Rafal Jaworowski <raj@semihalf.com>
+ *
+ * This file contains routines that fetch data from ARM-dependent sources
+ * (bd_info etc.)
+ */
+
+#include <config.h>
+#include <linux/types.h>
+#include <api_public.h>
+
+#include <asm/u-boot.h>
+#include <asm/global_data.h>
+
+#include "api_private.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Important notice: handling of individual fields MUST be kept in sync with
+ * include/asm-arm/u-boot.h and include/asm-arm/global_data.h, so any changes
+ * need to reflect their current state and layout of structures involved!
+ */
+int platform_sys_info(struct sys_info *si)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		platform_set_mr(si, gd->bd->bi_dram[i].start,
+				gd->bd->bi_dram[i].size, MR_ATTR_DRAM);
+
+	return 1;
+}

api/api_platform-mips.c

@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007 Stanislav Galabov <sgalabov@gmail.com>
+ *
+ * This file contains routines that fetch data from bd_info sources
+ */
+
+#include <config.h>
+#include <linux/types.h>
+#include <api_public.h>
+
+#include <asm/u-boot.h>
+#include <asm/global_data.h>
+
+#include "api_private.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Important notice: handling of individual fields MUST be kept in sync with
+ * include/asm-generic/u-boot.h, so any changes
+ * need to reflect their current state and layout of structures involved!
+ */
+int platform_sys_info(struct sys_info *si)
+{
+
+	platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM);
+
+	return 1;
+}

api/api_platform-powerpc.c

@@ -12,6 +12,7 @@
 #include <linux/types.h>
 #include <api_public.h>
 
+#include <asm/u-boot.h>
 #include <asm/global_data.h>
 
 #include "api_private.h"
@@ -43,6 +44,7 @@ int platform_sys_info(struct sys_info *si)
 
 	platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM);
 	platform_set_mr(si, gd->bd->bi_flashstart, gd->bd->bi_flashsize, MR_ATTR_FLASH);
+	platform_set_mr(si, gd->bd->bi_sramstart, gd->bd->bi_sramsize, MR_ATTR_SRAM);
 
 	return 1;
 }

api/api_platform.c

@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * (C) Copyright 2007 Semihalf
- *
- * Written by: Rafal Jaworowski <raj@semihalf.com>
- *
- * This file contains a routine to fetch data from the global_data structure.
- */
-
-#include <api_public.h>
-#include <asm/global_data.h>
-#include "api_private.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int platform_sys_info(struct sys_info *si)
-{
-	int i;
-
-	si->clk_bus = gd->bus_clk;
-	si->clk_cpu = gd->cpu_clk;
-
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
-		platform_set_mr(si, gd->bd->bi_dram[i].start,
-				gd->bd->bi_dram[i].size, MR_ATTR_DRAM);
-
-	platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM);
-	platform_set_mr(si, gd->bd->bi_flashstart, gd->bd->bi_flashsize, MR_ATTR_FLASH);
-
-	return 1;
-}

api/api_storage.c

@@ -6,10 +6,10 @@
  */
 
 #include <config.h>
+#include <common.h>
 #include <api_public.h>
 #include <part.h>
 #include <scsi.h>
-#include <linux/types.h>
 
 #if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)
 #include <usb.h>
@@ -26,6 +26,7 @@
 
 #define errf(fmt, args...) do { printf("ERROR @ %s(): ", __func__); printf(fmt, ##args); } while (0)
 
+
 #define ENUM_IDE	0
 #define ENUM_USB	1
 #define ENUM_SCSI	2
@@ -66,6 +67,13 @@ void dev_stor_init(void)
 	specs[ENUM_SATA].type = DEV_TYP_STOR | DT_STOR_SATA;
 	specs[ENUM_SATA].name = "sata";
 #endif
+#if defined(CONFIG_SCSI)
+	specs[ENUM_SCSI].max_dev = SCSI_MAX_DEVICE;
+	specs[ENUM_SCSI].enum_started = 0;
+	specs[ENUM_SCSI].enum_ended = 0;
+	specs[ENUM_SCSI].type = DEV_TYP_STOR | DT_STOR_SCSI;
+	specs[ENUM_SCSI].name = "scsi";
+#endif
 #if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)
 	specs[ENUM_USB].max_dev = USB_MAX_STOR_DEV;
 	specs[ENUM_USB].enum_started = 0;
@@ -143,6 +151,7 @@ static int dev_stor_get(int type, int *more, struct device_info *di)
 	return found;
 }
 
+
 /* returns: ENUM_IDE, ENUM_USB etc. based on struct blk_desc */
 
 static int dev_stor_type(struct blk_desc *dd)
@@ -157,6 +166,7 @@ static int dev_stor_type(struct blk_desc *dd)
 	return ENUM_MAX;
 }
 
+
 /* returns: 0/1 whether cookie points to some device in this group */
 
 static int dev_is_stor(int type, struct device_info *di)
@@ -164,6 +174,7 @@ static int dev_is_stor(int type, struct device_info *di)
 	return (dev_stor_type(di->cookie) == type) ? 1 : 0;
 }
 
+
 static int dev_enum_stor(int type, struct device_info *di)
 {
 	int found = 0, more = 0;
@@ -289,6 +300,7 @@ static int dev_stor_is_valid(int type, struct blk_desc *dd)
 	return 0;
 }
 
+
 int dev_open_stor(void *cookie)
 {
 	int type = dev_stor_type(cookie);
@@ -302,6 +314,7 @@ int dev_open_stor(void *cookie)
 	return API_ENODEV;
 }
 
+
 int dev_close_stor(void *cookie)
 {
 	/*
@@ -311,6 +324,7 @@ int dev_close_stor(void *cookie)
 	return 0;
 }
 
+
 lbasize_t dev_read_stor(void *cookie, void *buf, lbasize_t len, lbastart_t start)
 {
 	int type;
@@ -334,6 +348,7 @@ lbasize_t dev_read_stor(void *cookie, void *buf, lbasize_t len, lbastart_t start
 #endif	/* defined(CONFIG_BLK) */
 }
 
+
 lbasize_t dev_write_stor(void *cookie, void *buf, lbasize_t len, lbastart_t start)
 {
 	struct blk_desc *dd = (struct blk_desc *)cookie;

arch/Kconfig

@@ -8,25 +8,6 @@ config CREATE_ARCH_SYMLINK
 config HAVE_ARCH_IOREMAP
 	bool
 
-config HAVE_SETJMP
-	bool
-	help
-	 The architecture supports setjmp() and longjmp().
-
-config HAVE_INITJMP
-	bool
-	depends on HAVE_SETJMP
-	help
-	 The architecture supports initjmp(), a non-standard companion to
-	 setjmp() and longjmp().
-
-config SUPPORT_BIG_ENDIAN
-	bool
-
-config SUPPORT_LITTLE_ENDIAN
-	bool
-	default y if !SUPPORT_BIG_ENDIAN
-
 config SYS_CACHE_SHIFT_4
 	bool
 
@@ -39,37 +20,15 @@ config SYS_CACHE_SHIFT_6
 config SYS_CACHE_SHIFT_7
 	bool
 
-config 32BIT
-	bool
-
-config 64BIT
-	bool
-	help
-	  Indicates that U-Boot proper will be built for a 64 bit
-	  architecture.
-
-config SPL_64BIT
-	bool
-	help
-	  Indicates that SPL will be built for a 64 bit architecture.
-
 config SYS_CACHELINE_SIZE
 	int
 	default 128 if SYS_CACHE_SHIFT_7
 	default 64 if SYS_CACHE_SHIFT_6
 	default 32 if SYS_CACHE_SHIFT_5
 	default 16 if SYS_CACHE_SHIFT_4
-	# Fall-back for MIPS and RISC-V
-	default 64 if RISCV
+	# Fall-back for MIPS
 	default 32 if MIPS
 
-config SYS_DTC_PAD_BYTES
-	int "Size in bytes to pad device tree blob"
-	default 32768 if X86 && EFI_APP
-	default 4096 if ARC || ARM64 || M68K || MICROBLAZE || NIOS2 \
-		|| RISCV || SANDBOX || X86
-	default 0
-
 config LINKER_LIST_ALIGN
 	int
 	default 32 if SANDBOX
@@ -94,36 +53,29 @@ config ARC
 	select SUPPORT_OF_CONTROL
 	select SYS_CACHE_SHIFT_7
 	select TIMER
-	select SUPPORT_BIG_ENDIAN
-	select SUPPORT_LITTLE_ENDIAN
 	select SYS_BIG_ENDIAN if CPU_BIG_ENDIAN
 	select SYS_LITTLE_ENDIAN if !CPU_BIG_ENDIAN
 
 config ARM
 	bool "ARM architecture"
-	select HAVE_SETJMP
-	select HAVE_INITJMP
 	select ARCH_SUPPORTS_LTO
 	select CREATE_ARCH_SYMLINK
 	select HAVE_PRIVATE_LIBGCC if !ARM64
 	select SUPPORT_ACPI
-	select SUPPORT_LITTLE_ENDIAN
 	select SUPPORT_OF_CONTROL
 
 config M68K
 	bool "M68000 architecture"
 	select HAVE_PRIVATE_LIBGCC
 	select USE_PRIVATE_LIBGCC
+	select NEEDS_MANUAL_RELOC
 	select SYS_BOOT_GET_CMDLINE
 	select SYS_BOOT_GET_KBD
 	select SYS_CACHE_SHIFT_4
-	select SUPPORT_BIG_ENDIAN
 	select SUPPORT_OF_CONTROL
 
 config MICROBLAZE
 	bool "MicroBlaze architecture"
-	select SUPPORT_BIG_ENDIAN
-	select SUPPORT_LITTLE_ENDIAN
 	select SUPPORT_OF_CONTROL
 	imply CMD_TIMER
 	imply SPL_REGMAP if SPL
@@ -144,14 +96,12 @@ config NIOS2
 	select DM
 	select DM_EVENT
 	select OF_CONTROL
-	select SUPPORT_LITTLE_ENDIAN
 	select SUPPORT_OF_CONTROL
 	imply CMD_DM
 
 config PPC
 	bool "PowerPC architecture"
 	select HAVE_PRIVATE_LIBGCC
-	select SUPPORT_BIG_ENDIAN
 	select SUPPORT_OF_CONTROL
 	select SYS_BOOT_GET_CMDLINE
 	select SYS_BOOT_GET_KBD
@@ -159,11 +109,6 @@ config PPC
 config RISCV
 	bool "RISC-V architecture"
 	select CREATE_ARCH_SYMLINK
-	select HAVE_PRIVATE_LIBGCC if 64BIT
-	select HAVE_SETJMP
-	select HAVE_INITJMP
-	select SUPPORT_ACPI
-	select SUPPORT_LITTLE_ENDIAN
 	select SUPPORT_OF_CONTROL
 	select OF_CONTROL
 	select DM
@@ -187,54 +132,35 @@ config RISCV
 
 config SANDBOX
 	bool "Sandbox"
-	select HAVE_SETJMP
-	select HAVE_INITJMP
 	select ARCH_SUPPORTS_LTO
-	select AXI
 	select BOARD_LATE_INIT
 	select BZIP2
-	select CMD_POWEROFF if CMDLINE
+	select CMD_POWEROFF
 	select DM
 	select DM_EVENT
 	select DM_FUZZING_ENGINE
 	select DM_GPIO
 	select DM_I2C
 	select DM_KEYBOARD
-	select DM_MAILBOX
-	select DM_RESET
+	select DM_MMC
 	select DM_SERIAL
 	select DM_SPI
 	select DM_SPI_FLASH
-	select GPIO
 	select GZIP_COMPRESSED
-	select I2C
+	select IO_TRACE
 	select LZO
-	select MMC
-	select MTD
 	select OF_BOARD_SETUP
-	select OF_CONTROL
 	select PCI_ENDPOINT
-	select SANDBOX_RESET
 	select SPI
-	select SERIAL
 	select SUPPORT_OF_CONTROL
-	select SUPPORT_BIG_ENDIAN
-	select SUPPORT_LITTLE_ENDIAN
-	select SYSRESET
-	select SYSRESET_CMD_RESET
-	select SYSRESET_CMD_POWEROFF if SYSRESET && CMD_POWEROFF
+	select SYSRESET_CMD_POWEROFF
 	select SYS_CACHE_SHIFT_4
 	select IRQ
-	select SUPPORT_EXTENSION_SCAN if CMDLINE
+	select SUPPORT_EXTENSION_SCAN
 	select SUPPORT_ACPI
-	select TIMER
-	select SPL_TIMER if SPL
-	select TPL_TIMER if TPL
-	select VPL_TIMER if VPL
 	imply BITREVERSE
 	select BLOBLIST
 	imply LTO
-	imply CMD_BOOTEFI_SELFTEST
 	imply CMD_DM
 	imply CMD_EXCEPTION
 	imply CMD_GETTIME
@@ -254,17 +180,16 @@ config SANDBOX
 	imply AVB_VERIFY
 	imply LIBAVB
 	imply CMD_AVB
-	imply PARTITION_TYPE_GUID if EFI_PARTITION
+	imply PARTITION_TYPE_GUID
 	imply SCP03
 	imply CMD_SCP03
 	imply UDP_FUNCTION_FASTBOOT
 	imply VIRTIO_MMIO
 	imply VIRTIO_PCI
 	imply VIRTIO_SANDBOX
-	# Re-enable this when fully implemented
-	# imply VIRTIO_BLK
+	imply VIRTIO_BLK
 	imply VIRTIO_NET
-	imply SOUND
+	imply DM_SOUND
 	imply PCI_SANDBOX_EP
 	imply PCH
 	imply PHYLIB
@@ -280,33 +205,24 @@ config SANDBOX
 	imply PHY_FIXED
 	imply DM_DSA
 	imply CMD_EXTENSION
+	imply KEYBOARD
 	imply PHYSMEM
 	imply GENERATE_ACPI_TABLE
 	imply BINMAN
-	imply CMD_MBR
-	imply CMD_MMC
-	imply BOOTSTD_DEFAULTS if BOOTSTD_FULL && CMDLINE
-	imply BOOTMETH_DISTRO if BOOTSTD_FULL && CMDLINE
-	imply CMD_SYSBOOT if BOOTSTD_FULL
 
 config SH
 	bool "SuperH architecture"
-	select SUPPORT_LITTLE_ENDIAN
 	select HAVE_PRIVATE_LIBGCC
 	select SUPPORT_OF_CONTROL
 
 config X86
 	bool "x86 architecture"
-	select AHCI
-	select HAVE_SETJMP
 	select SUPPORT_SPL
 	select SUPPORT_TPL
-	select SUPPORT_LITTLE_ENDIAN
 	select CREATE_ARCH_SYMLINK
 	select DM
 	select HAVE_ARCH_IOMAP
 	select HAVE_PRIVATE_LIBGCC
-	select LMB_ARCH_MEM_MAP
 	select OF_CONTROL
 	select PCI
 	select SUPPORT_ACPI
@@ -326,17 +242,16 @@ config X86
 	imply CMD_PCI
 	imply CMD_SF
 	imply CMD_SF_TEST
+	imply CMD_ZBOOT
 	imply DM_GPIO
 	imply DM_KEYBOARD
 	imply DM_MMC
 	imply DM_RTC
-	imply SCSI
+	imply DM_SCSI
 	imply DM_SERIAL
-	imply MTD
 	imply DM_SPI
 	imply DM_SPI_FLASH
 	imply DM_USB
-	imply LAST_STAGE_INIT
 	imply VIDEO
 	imply SYSRESET
 	imply SPL_SYSRESET
@@ -384,7 +299,6 @@ config X86
 config XTENSA
 	bool "Xtensa architecture"
 	select CREATE_ARCH_SYMLINK
-	select SUPPORT_LITTLE_ENDIAN
 	select SUPPORT_OF_CONTROL
 
 endchoice
@@ -439,16 +353,7 @@ config SYS_BOARD
 	  leave this option empty.
 
 config SYS_CONFIG_NAME
-	string "Board header file" if ARCH_MESON || ARCH_VERSAL || \
-		ARCH_VERSAL_NET || ARCH_ZYNQ || ARCH_ZYNQMP || \
-		ARCH_ZYNQMP_R5 || MICROBLAZE || NIOS2
-	default "meson64" if ARCH_MESON
-	default "microblaze-generic" if MICROBLAZE
-	default "xilinx_versal" if ARCH_VERSAL
-	default "xilinx_versal_net" if ARCH_VERSAL_NET
-	default "xilinx_zynqmp" if ARCH_ZYNQMP
-	default "xilinx_zynqmp_r5" if ARCH_ZYNQMP_R5
-	default "zynq-common" if ARCH_ZYNQ
+	string
 	help
 	  This option should contain the base name of board header file.
 	  The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
@@ -588,21 +493,24 @@ endif
 
 source "board/keymile/Kconfig"
 
+if MIPS || MICROBLAZE
+
 choice
 	prompt "Endianness selection"
-	default SYS_BIG_ENDIAN if MIPS || MICROBLAZE
-	default SYS_LITTLE_ENDIAN
 	help
-	  Some boards can be configured for either little or big endian
+	  Some MIPS boards can be configured for either little or big endian
 	  byte order. These modes require different U-Boot images. In general there
 	  is one preferred byteorder for a particular system but some systems are
 	  just as commonly used in the one or the other endianness.
 
 config SYS_BIG_ENDIAN
 	bool "Big endian"
-	depends on SUPPORT_BIG_ENDIAN
+	depends on (SUPPORTS_BIG_ENDIAN && MIPS) || MICROBLAZE
 
 config SYS_LITTLE_ENDIAN
 	bool "Little endian"
-	depends on SUPPORT_LITTLE_ENDIAN
+	depends on (SUPPORTS_LITTLE_ENDIAN && MIPS) || MICROBLAZE
+
 endchoice
+
+endif

arch/Kconfig.nxp

@@ -45,7 +45,7 @@ config ESBC_HDR_LS
 
 config ESBC_ADDR_64BIT
 	def_bool y
-	depends on FSL_LAYERSCAPE
+	depends on ESBC_HDR_LS && FSL_LAYERSCAPE
 	help
 	  For Layerscape based platforms, ESBC image Address in Header is 64bit.
 
@@ -84,35 +84,13 @@ config SYS_FSL_SFP_VER_3_4
 
 endchoice
 
-config FSL_SEC_MON
-	bool
-	help
-	  Freescale Security Monitor block is responsible for monitoring
-	  system states.
-	  Security Monitor can be transitioned on any security failures,
-	  like software violations or hardware security violations.
-
-choice
-	prompt "Security monitor interaction endianess"
-	depends on FSL_SEC_MON
-	default SYS_FSL_SEC_MON_BE if PPC
-	default SYS_FSL_SEC_MON_LE
-
-config SYS_FSL_SEC_MON_LE
-	bool "Security monitor interactions are little endian"
-
-config SYS_FSL_SEC_MON_BE
-	bool "Security monitor interactions are big endian"
-
-endchoice
-
 config SPL_UBOOT_KEY_HASH
 	string "Non-SRK key hash for U-Boot public/private key pair"
 	depends on SPL
 	default ""
 	help
 	  Set the key hash for U-Boot here if public/private key pair used to
-	  sign U-Boot are different from the SRK hash put in the fuse.  Example
+	  sign U-boot are different from the SRK hash put in the fuse.  Example
 	  of a key hash is
 	  41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b.
 	  Otherwise leave this empty.

arch/arc/dts/Makefile

@@ -10,5 +10,12 @@ dtb-$(CONFIG_TARGET_IOT_DEVKIT) +=  iot_devkit.dtb
 
 include $(srctree)/scripts/Makefile.dts
 
-# Add any required device tree compiler flags here
-DTC_FLAGS += -R 4
+targets += $(dtb-y)
+
+DTC_FLAGS += -R 4 -p 0x1000
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+	@:
+
+clean-files := *.dtb

arch/arc/include/asm/arc-bcr.h

@@ -13,9 +13,11 @@
 #define __ARC_BCR_H
 #ifndef __ASSEMBLY__
 
+#include <config.h>
+
 union bcr_di_cache {
 	struct {
-#ifdef CONFIG_SYS_BIG_ENDIAN
+#ifdef CONFIG_CPU_BIG_ENDIAN
 		unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
 #else
 		unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
@@ -26,7 +28,7 @@ union bcr_di_cache {
 
 union bcr_slc_cfg {
 	struct {
-#ifdef CONFIG_SYS_BIG_ENDIAN
+#ifdef CONFIG_CPU_BIG_ENDIAN
 		unsigned int pad:24, way:2, lsz:2, sz:4;
 #else
 		unsigned int sz:4, lsz:2, way:2, pad:24;
@@ -37,7 +39,7 @@ union bcr_slc_cfg {
 
 union bcr_generic {
 	struct {
-#ifdef CONFIG_SYS_BIG_ENDIAN
+#ifdef CONFIG_CPU_BIG_ENDIAN
 		unsigned int pad:24, ver:8;
 #else
 		unsigned int ver:8, pad:24;
@@ -48,7 +50,7 @@ union bcr_generic {
 
 union bcr_clust_cfg {
 	struct {
-#ifdef CONFIG_SYS_BIG_ENDIAN
+#ifdef CONFIG_CPU_BIG_ENDIAN
 		unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8;
 #else
 		unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7;
@@ -59,7 +61,7 @@ union bcr_clust_cfg {
 
 union bcr_mmu_4 {
 	struct {
-#ifdef CONFIG_SYS_BIG_ENDIAN
+#ifdef CONFIG_CPU_BIG_ENDIAN
 	unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1,
 		     n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3;
 #else

arch/arc/include/asm/arcregs.h

@@ -7,6 +7,7 @@
 #define _ASM_ARC_ARCREGS_H
 
 #include <asm/cache.h>
+#include <config.h>
 
 /*
  * ARC architecture has additional address space - auxiliary registers.

arch/arc/include/asm/cache.h

@@ -6,6 +6,8 @@
 #ifndef __ASM_ARC_CACHE_H
 #define __ASM_ARC_CACHE_H
 
+#include <config.h>
+
 /*
  * As of today we may handle any L1 cache line length right in software.
  * For that essentially cache line length is a variable not constant.

arch/arc/include/asm/global_data.h

@@ -6,8 +6,6 @@
 #ifndef	__ASM_ARC_GLOBAL_DATA_H
 #define __ASM_ARC_GLOBAL_DATA_H
 
-#include <asm/u-boot.h>
-
 #ifndef __ASSEMBLY__
 /* Architecture-specific global data */
 struct arch_global_data {
@@ -20,6 +18,6 @@ struct arch_global_data {
 
 #include <asm-generic/global_data.h>
 
-#define DECLARE_GLOBAL_DATA_PTR		register gd_t *gd asm ("r25")
+#define DECLARE_GLOBAL_DATA_PTR		register volatile gd_t *gd asm ("r25")
 
 #endif /* __ASM_ARC_GLOBAL_DATA_H */

arch/arc/include/asm/io.h

@@ -77,9 +77,10 @@ static inline void sync(void)
 #define __arch_putl(v, a)	({ __comp_b(); *(volatile u32 *)(a) = (v); __comp_b(); })
 #define __arch_putq(v, a)	({ __comp_b(); *(volatile u64 *)(a) = (v); __comp_b(); })
 
+
 /*
  * We add memory barriers for __raw_readX / __raw_writeX accessors same way as
- * it is done for readX and writeX accessors as lots of U-Boot driver uses
+ * it is done for readX and writeX accessors as lots of U-boot driver uses
  * __raw_readX / __raw_writeX instead of proper accessor with barrier.
  */
 #define __raw_writeb(v, c)	({ __iowmb(); __arch_putb(v, c); })
@@ -92,6 +93,7 @@ static inline void sync(void)
 #define __raw_readl(c)		({ u32 __v = __arch_getl(c); __iormb(); __v; })
 #define __raw_readq(c)		({ u64 __v = __arch_getq(c); __iormb(); __v; })
 
+
 static inline void __raw_writesb(unsigned long addr, const void *data,
 				 int bytelen)
 {

arch/arc/include/asm/sections.h

@@ -8,8 +8,7 @@
 
 #include <asm-generic/sections.h>
 
-extern char __ivt_start[];
-extern char __ivt_end[];
-extern char __text_end[];
+extern ulong __ivt_start;
+extern ulong __ivt_end;
 
 #endif /* __ASM_ARC_SECTIONS_H */

arch/arc/lib/bootm.c

@@ -3,13 +3,16 @@
  * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
  */
 
-#include <bootm.h>
+#include <common.h>
 #include <bootstage.h>
 #include <env.h>
 #include <image.h>
 #include <irq_func.h>
 #include <log.h>
 #include <asm/cache.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 static int cleanup_before_linux(void)
 {
@@ -50,13 +53,17 @@ static void boot_jump_linux(struct bootm_headers *images, int flag)
 {
 	ulong kernel_entry;
 	unsigned int r0, r2;
+	int fake = (flag & BOOTM_STATE_OS_FAKE_GO);
+
 	kernel_entry = images->ep;
 
 	debug("## Transferring control to Linux (at address %08lx)...\n",
 	      kernel_entry);
 	bootstage_mark(BOOTSTAGE_ID_RUN_OS);
 
-	bootm_final(flag);
+	printf("\nStarting kernel ...%s\n\n", fake ?
+	       "(fake run for tracing)" : "");
+	bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
 
 	if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
 		r0 = 2;
@@ -68,14 +75,12 @@ static void boot_jump_linux(struct bootm_headers *images, int flag)
 
 	cleanup_before_linux();
 
-	if (!(flag & BOOTM_STATE_OS_FAKE_GO))
+	if (!fake)
 		board_jump_and_run(kernel_entry, r0, 0, r2);
 }
 
-int do_bootm_linux(int flag, struct bootm_info *bmi)
+int do_bootm_linux(int flag, int argc, char *argv[], struct bootm_headers *images)
 {
-	struct bootm_headers *images = bmi->images;
-
 	/* No need for those on ARC */
 	if ((flag & BOOTM_STATE_OS_BD_T) || (flag & BOOTM_STATE_OS_CMDLINE))
 		return -1;

arch/arc/lib/cache.c

@@ -4,13 +4,14 @@
  */
 
 #include <config.h>
+#include <common.h>
 #include <cpu_func.h>
 #include <asm/global_data.h>
 #include <linux/bitops.h>
 #include <linux/compiler.h>
-#include <linux/errno.h>
 #include <linux/kernel.h>
 #include <linux/log2.h>
+#include <lmb.h>
 #include <asm/arcregs.h>
 #include <asm/arc-bcr.h>
 #include <asm/cache.h>
@@ -821,7 +822,15 @@ void sync_n_cleanup_cache_all(void)
 	__ic_entire_invalidate();
 }
 
-int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm)
+static ulong get_sp(void)
 {
-	return -ENOSYS;
+	ulong ret;
+
+	asm("mov %0, sp" : "=r"(ret) : );
+	return ret;
+}
+
+void arch_lmb_reserve(struct lmb *lmb)
+{
+	arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
 }

arch/arc/lib/cpu.c

@@ -3,11 +3,11 @@
  * Copyright (C) 2013-2014, 2018 Synopsys, Inc. All rights reserved.
  */
 
-#include <config.h>
+#include <common.h>
 #include <clock_legacy.h>
 #include <init.h>
 #include <malloc.h>
-#include <stdio.h>
+#include <vsprintf.h>
 #include <asm/arcregs.h>
 #include <asm/cache.h>
 #include <asm/global_data.h>

arch/arc/lib/init_helpers.c

@@ -5,6 +5,7 @@
 
 #include <init.h>
 #include <asm/cache.h>
+#include <common.h>
 
 int init_cache_f_r(void)
 {

arch/arc/lib/interrupts.c

@@ -3,8 +3,8 @@
  * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
  */
 
+#include <common.h>
 #include <irq_func.h>
-#include <vsprintf.h>
 #include <asm/arcregs.h>
 #include <asm/ptrace.h>
 

arch/arc/lib/relocate.c

@@ -3,29 +3,35 @@
  * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
  */
 
+#include <common.h>
 #include <elf.h>
 #include <log.h>
-#include <asm/sections.h>
+#include <asm-generic/sections.h>
 #include <asm/global_data.h>
 
+extern ulong __image_copy_start;
+extern ulong __ivt_start;
+extern ulong __ivt_end;
+extern ulong __text_end;
+
 DECLARE_GLOBAL_DATA_PTR;
 
 int copy_uboot_to_ram(void)
 {
-	size_t len = (size_t)__image_copy_end - (size_t)__image_copy_start;
+	size_t len = (size_t)&__image_copy_end - (size_t)&__image_copy_start;
 
 	if (gd->flags & GD_FLG_SKIP_RELOC)
 		return 0;
 
-	memcpy((void *)gd->relocaddr, (void *)__image_copy_start, len);
+	memcpy((void *)gd->relocaddr, (void *)&__image_copy_start, len);
 
 	return 0;
 }
 
 int clear_bss(void)
 {
-	ulong dst_addr = (ulong)__bss_start + gd->reloc_off;
-	size_t len = (size_t)__bss_end - (size_t)__bss_start;
+	ulong dst_addr = (ulong)&__bss_start + gd->reloc_off;
+	size_t len = (size_t)&__bss_end - (size_t)&__bss_start;
 
 	memset((void *)dst_addr, 0x00, len);
 
@@ -37,8 +43,8 @@ int clear_bss(void)
  */
 int do_elf_reloc_fixups(void)
 {
-	Elf32_Rela *re_src = (Elf32_Rela *)__rel_dyn_start;
-	Elf32_Rela *re_end = (Elf32_Rela *)__rel_dyn_end;
+	Elf32_Rela *re_src = (Elf32_Rela *)(&__rel_dyn_start);
+	Elf32_Rela *re_end = (Elf32_Rela *)(&__rel_dyn_end);
 
 	if (gd->flags & GD_FLG_SKIP_RELOC)
 		return 0;
@@ -54,8 +60,8 @@ int do_elf_reloc_fixups(void)
 		offset_ptr_rom = (Elf32_Addr *)re_src->r_offset;
 
 		/* Check that the location of the relocation is in .text */
-		if (offset_ptr_rom >= (Elf32_Addr *)__image_copy_start &&
-		    offset_ptr_rom < (Elf32_Addr *)__image_copy_end) {
+		if (offset_ptr_rom >= (Elf32_Addr *)&__image_copy_start &&
+		    offset_ptr_rom < (Elf32_Addr *)&__image_copy_end) {
 			unsigned int val, do_swap = 0;
 			/* Switch to the in-RAM version */
 			offset_ptr_ram = (Elf32_Addr *)((ulong)offset_ptr_rom +
@@ -63,11 +69,11 @@ int do_elf_reloc_fixups(void)
 
 #ifdef __LITTLE_ENDIAN__
 			/* If location in ".text" section swap value */
-			if (((u32)offset_ptr_rom >= (u32)__text_start &&
-			     (u32)offset_ptr_rom <= (u32)__text_end)
+			if (((u32)offset_ptr_rom >= (u32)&__text_start &&
+			     (u32)offset_ptr_rom <= (u32)&__text_end)
 #if defined(__ARC700__) || defined(__ARC600__)
-			    || ((u32)offset_ptr_rom >= (u32)__ivt_start &&
-				(u32)offset_ptr_rom <= (u32)__ivt_end)
+			    || ((u32)offset_ptr_rom >= (u32)&__ivt_start &&
+				(u32)offset_ptr_rom <= (u32)&__ivt_end)
 #endif
 			   )
 				do_swap = 1;
@@ -90,8 +96,8 @@ int do_elf_reloc_fixups(void)
 				val = (val << 16) | (val >> 16);
 
 			/* Check that the target points into executable */
-			if (val < (unsigned int)__image_copy_start ||
-			    val > (unsigned int)__image_copy_end) {
+			if (val < (unsigned int)&__image_copy_start ||
+			    val > (unsigned int)&__image_copy_end) {
 				/* TODO: Use panic() instead of debug()
 				 *
 				 * For some reason GCC might generate
@@ -100,7 +106,7 @@ int do_elf_reloc_fixups(void)
 				 * ----------------------->8--------------------
 				 * static int setup_mon_len(void)
 				 * {
-				 *         gd->mon_len = (ulong)__bss_end - CONFIG_SYS_MONITOR_BASE;
+				 *         gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
 				 *         return 0;
 				 * }
 				 * ----------------------->8--------------------

arch/arc/lib/reset.c

@@ -4,6 +4,7 @@
  */
 
 #include <command.h>
+#include <common.h>
 #include <cpu_func.h>
 
 __weak void reset_cpu(void)

arch/arm/Makefile

@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0+
 
-ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_ARCH_TEGRA),yy)
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_ARCH_TEGRA),yy)
 CONFIG_CPU_V7A=
 CONFIG_CPU_ARM720T=y
 endif
@@ -16,7 +16,6 @@ arch-$(CONFIG_CPU_V7A)		=$(call cc-option, -march=armv7-a, \
 				 $(call cc-option, -march=armv7))
 arch-$(CONFIG_CPU_V7M)		=-march=armv7-m
 arch-$(CONFIG_CPU_V7R)		=-march=armv7-r
-arch-$(CONFIG_CPU_V8M)		=-march=armv8-m.main
 ifeq ($(CONFIG_ARM64_CRC32),y)
 arch-$(CONFIG_ARM64)		=-march=armv8-a+crc
 else
@@ -25,7 +24,7 @@ endif
 
 # On Tegra systems we must build SPL for the armv4 core on the device
 # but otherwise we can use the value in CONFIG_SYS_ARM_ARCH
-ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_ARCH_TEGRA),yy)
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_ARCH_TEGRA),yy)
 arch-y += -D__LINUX_ARM_ARCH__=4
 else
 arch-y += -D__LINUX_ARM_ARCH__=$(CONFIG_SYS_ARM_ARCH)
@@ -43,7 +42,6 @@ tune-$(CONFIG_CPU_ARM1136)	=
 tune-$(CONFIG_CPU_ARM1176)	=
 tune-$(CONFIG_CPU_V7A)		=-mtune=generic-armv7-a
 tune-$(CONFIG_CPU_V7R)		=
-tune-$(CONFIG_CPU_V8M)		=
 tune-$(CONFIG_ARM64)		=
 
 # Evaluate tune cc-option calls now
@@ -53,7 +51,6 @@ PLATFORM_CPPFLAGS += $(arch-y) $(tune-y)
 
 # Machine directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
-machine-$(CONFIG_ARCH_AIROHA)		+= airoha
 machine-$(CONFIG_ARCH_APPLE)		+= apple
 machine-$(CONFIG_ARCH_ASPEED)		+= aspeed
 machine-$(CONFIG_ARCH_AT91)		+= at91
@@ -72,16 +69,15 @@ machine-$(CONFIG_ARCH_KIRKWOOD)		+= kirkwood
 machine-$(CONFIG_ARCH_LPC32XX)		+= lpc32xx
 machine-$(CONFIG_ARCH_MEDIATEK)		+= mediatek
 machine-$(CONFIG_ARCH_MESON)		+= meson
-machine-$(CONFIG_ARCH_MMP)		+= mmp
 machine-$(CONFIG_ARCH_MVEBU)		+= mvebu
 machine-$(CONFIG_ARCH_NEXELL)		+= nexell
 machine-$(CONFIG_ARCH_NPCM)             += npcm
 machine-$(CONFIG_ARCH_OMAP2PLUS)	+= omap2
+machine-$(CONFIG_ARCH_ORION5X)		+= orion5x
 machine-$(CONFIG_ARCH_OWL)		+= owl
-machine-$(CONFIG_ARCH_RENESAS)		+= renesas
+machine-$(CONFIG_ARCH_RMOBILE)		+= rmobile
 machine-$(CONFIG_ARCH_ROCKCHIP)		+= rockchip
 machine-$(CONFIG_ARCH_S5PC1XX)		+= s5pc1xx
-machine-$(CONFIG_ARCH_SC5XX)		+= sc5xx
 machine-$(CONFIG_ARCH_SNAPDRAGON)	+= snapdragon
 machine-$(CONFIG_ARCH_SOCFPGA)		+= socfpga
 machine-$(CONFIG_ARCH_STM32)		+= stm32
@@ -93,7 +89,6 @@ machine-$(CONFIG_ARCH_OCTEONTX)		+= octeontx
 machine-$(CONFIG_ARCH_OCTEONTX2)	+= octeontx2
 machine-$(CONFIG_ARCH_UNIPHIER)		+= uniphier
 machine-$(CONFIG_ARCH_VERSAL)		+= versal
-machine-$(CONFIG_ARCH_VERSAL2)		+= versal2
 machine-$(CONFIG_ARCH_VERSAL_NET)	+= versal-net
 machine-$(CONFIG_ARCH_ZYNQ)		+= zynq
 machine-$(CONFIG_ARCH_ZYNQMP)		+= zynqmp
@@ -109,7 +104,7 @@ libs-y += $(machdirs)
 
 head-y := arch/arm/cpu/$(CPU)/start.o
 
-ifeq ($(CONFIG_XPL_BUILD),y)
+ifeq ($(CONFIG_SPL_BUILD),y)
 ifeq ($(CONFIG_SYS_SOC)$(CONFIG_SPL_FRAMEWORK),"mxs")
 head-y := arch/arm/cpu/arm926ejs/mxs/start.o
 endif

arch/arm/config.mk

@@ -23,42 +23,38 @@ endif
 
 PLATFORM_RELFLAGS += -fno-common $(FIXED_REG)
 PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \
+		     $(call cc-option,-mgeneral-regs-only) \
       $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
 
-ifeq ($(CONFIG_ARM64),y)
-PLATFORM_RELFLAGS += $(call cc-option,-mgeneral-regs-only)
-endif
-
 # LLVM support
-LLVM_RELFLAGS		:= $(call cc-option,-mllvm,)
+LLVM_RELFLAGS		:= $(call cc-option,-mllvm,) \
+			$(call cc-option,-mno-movt,)
+PLATFORM_RELFLAGS	+= $(LLVM_RELFLAGS)
+
 PLATFORM_CPPFLAGS += -D__ARM__
 
 ifdef CONFIG_ARM64
 PLATFORM_ELFFLAGS += -B aarch64 -O elf64-littleaarch64
 else
 PLATFORM_ELFFLAGS += -B arm -O elf32-littlearm
-# no-movt is only available when targeting AArch32
-LLVM_RELFLAGS	+= $(call cc-option,-mno-movt,)
 endif
 
-PLATFORM_RELFLAGS	+= $(LLVM_RELFLAGS)
-
 # Choose between ARM/Thumb instruction sets
-ifeq ($(CONFIG_$(PHASE_)SYS_THUMB_BUILD),y)
+ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y)
 AFLAGS_IMPLICIT_IT	:= $(call as-option,-Wa$(comma)-mimplicit-it=always)
 PF_CPPFLAGS_ARM		:= $(AFLAGS_IMPLICIT_IT) \
 			$(call cc-option, -mthumb -mthumb-interwork,\
 			$(call cc-option,-marm,)\
 			$(call cc-option,-mno-thumb-interwork,)\
 		)
-else ifneq ($(CONFIG_ARM64),y)
+else
 PF_CPPFLAGS_ARM := $(call cc-option,-marm,) \
 		$(call cc-option,-mno-thumb-interwork,)
 endif
 
 # Only test once
-ifeq ($(CONFIG_$(PHASE_)SYS_THUMB_BUILD),y)
-archprepare: checkthumb checkgcc10
+ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y)
+archprepare: checkthumb checkgcc6
 
 checkthumb:
 	@if test "$(call cc-name)" = "gcc" -a \
@@ -69,13 +65,13 @@ checkthumb:
 		false; \
 	fi
 else
-archprepare: checkgcc10
+archprepare: checkgcc6
 endif
 
-checkgcc10:
+checkgcc6:
 	@if test "$(call cc-name)" = "gcc" -a \
-			"$(call cc-version)" -lt "1000"; then \
-		echo '*** Your GCC is older than 10.0 and is not supported'; \
+			"$(call cc-version)" -lt "0600"; then \
+		echo '*** Your GCC is older than 6.0 and is not supported'; \
 		false; \
 	fi
 
@@ -103,7 +99,7 @@ PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARM) $(PF_CPPFLAGS_ABI)
 ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
 # This file is parsed many times, so the string may get added multiple
 # times. Also, the prefix needs to be different based on whether
-# CONFIG_XPL_BUILD is defined or not. 'filter-out' the existing entry
+# CONFIG_SPL_BUILD is defined or not. 'filter-out' the existing entry
 # before adding the correct one.
 PLATFORM_LIBS := arch/arm/lib/eabi_compat.o \
 	$(filter-out arch/arm/lib/eabi_compat.o, $(PLATFORM_LIBS))
@@ -120,7 +116,7 @@ LDFLAGS_u-boot += -pie
 #
 # http://sourceware.org/bugzilla/show_bug.cgi?id=12532
 #
-ifeq ($(CONFIG_$(PHASE_)SYS_THUMB_BUILD),y)
+ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y)
 ifeq ($(GAS_BUG_12532),)
 export GAS_BUG_12532:=$(shell if [ $(call binutils-version) -lt 0222 ] ; \
 	then echo y; else echo n; fi)
@@ -130,7 +126,7 @@ PLATFORM_RELFLAGS += -fno-optimize-sibling-calls
 endif
 endif
 
-ifneq ($(CONFIG_XPL_BUILD),y)
+ifneq ($(CONFIG_SPL_BUILD),y)
 # Check that only R_ARM_RELATIVE relocations are generated.
 INPUTS-y += checkarmreloc
 # The movt / movw can hardcode 16 bit parts of the addresses in the
@@ -164,7 +160,7 @@ endif
 ifdef CONFIG_MACH_IMX
 ifneq ($(CONFIG_IMX_CONFIG),"")
 ifdef CONFIG_SPL
-ifndef CONFIG_XPL_BUILD
+ifndef CONFIG_SPL_BUILD
 INPUTS-y += SPL
 endif
 else

arch/arm/cpu/arm11/Makefile

@@ -5,6 +5,6 @@
 
 obj-y	= cpu.o
 
-ifneq ($(CONFIG_XPL_BUILD),y)
+ifneq ($(CONFIG_SPL_BUILD),y)
 obj-$(CONFIG_EFI_LOADER) += sctlr.o
 endif

arch/arm/cpu/arm11/cpu.c

@@ -14,6 +14,7 @@
  * CPU specific code
  */
 
+#include <common.h>
 #include <command.h>
 #include <cpu_func.h>
 #include <irq_func.h>
@@ -116,15 +117,3 @@ void enable_caches(void)
 #endif
 }
 #endif
-
-#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
-/* Invalidate entire I-cache */
-void invalidate_icache_all(void)
-{
-	unsigned long i = 0;
-
-	asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i));
-}
-#else
-void invalidate_icache_all(void) {}
-#endif

arch/arm/cpu/arm1136/mx31/devices.c

@@ -6,6 +6,7 @@
  * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  */
 
+#include <common.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
 

arch/arm/cpu/arm1136/mx31/generic.c

@@ -4,6 +4,7 @@
  * Sascha Hauer, Pengutronix
  */
 
+#include <common.h>
 #include <div64.h>
 #include <init.h>
 #include <asm/arch/imx-regs.h>

arch/arm/cpu/arm1136/mx31/timer.c

@@ -4,6 +4,7 @@
  * Sascha Hauer, Pengutronix
  */
 
+#include <common.h>
 #include <init.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/io.h>

arch/arm/cpu/arm1136/u-boot-spl.lds

@@ -30,12 +30,14 @@ SECTIONS
 	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
 
 	. = ALIGN(4);
-	.data : {
-		*(SORT_BY_ALIGNMENT(.data*))
-		. = ALIGN(8);
-	} >.sram
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+	. = ALIGN(4);
 	__image_copy_end = .;
-	_end = .;
+
+	.end :
+	{
+		*(.__end)
+	}
 
 	.bss :
 	{
@@ -46,5 +48,3 @@ SECTIONS
 		__bss_end = .;
 	} >.sdram
 }
-
-ASSERT(_end % 8 == 0, "_end must be 8-byte aligned for device tree");

arch/arm/cpu/arm1176/start.S

@@ -65,7 +65,7 @@ cpu_init_crit:
 	 * When booting from NAND - it has definitely been a reset, so, no need
 	 * to flush caches and disable the MMU
 	 */
-#ifndef CONFIG_XPL_BUILD
+#ifndef CONFIG_SPL_BUILD
 	/*
 	 * flush v4 I/D caches
 	 */

arch/arm/cpu/arm720t/interrupts.c

@@ -9,7 +9,7 @@
  * Alex Zuepke <azu@sysgo.de>
  */
 
-#include <linux/types.h>
+#include <common.h>
 
 #if defined(CONFIG_ARCH_TEGRA)
 static ulong timestamp;

arch/arm/cpu/arm920t/Makefile

@@ -9,6 +9,6 @@ obj-y	+= cpu.o
 
 # some files can only build in ARM mode
 
-ifdef CONFIG_$(PHASE_)SYS_THUMB_BUILD
+ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD
 CFLAGS_cpu.o := -marm
 endif

arch/arm/cpu/arm920t/cpu.c

@@ -12,6 +12,7 @@
  * CPU specific code
  */
 
+#include <common.h>
 #include <command.h>
 #include <cpu_func.h>
 #include <irq_func.h>

arch/arm/cpu/arm920t/start.S

@@ -8,6 +8,7 @@
  */
 
 #include <asm-offsets.h>
+#include <common.h>
 #include <config.h>
 
 /*

arch/arm/cpu/arm926ejs/Makefile

@@ -6,7 +6,7 @@
 extra-y	= start.o
 obj-y	= cpu.o cache.o
 
-ifdef	CONFIG_XPL_BUILD
+ifdef	CONFIG_SPL_BUILD
 ifdef	CONFIG_SPL_NO_CPU_SUPPORT
 extra-y	:=
 endif
@@ -17,7 +17,7 @@ obj-$(CONFIG_ARCH_SUNXI) += sunxi/
 
 # some files can only build in ARM or THUMB2, not THUMB1
 
-ifdef CONFIG_$(PHASE_)SYS_THUMB_BUILD
+ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD
 ifndef CONFIG_HAS_THUMB2
 
 CFLAGS_cpu.o := -marm

arch/arm/cpu/arm926ejs/cache.c

@@ -5,8 +5,8 @@
  */
 #include <cpu_func.h>
 #include <asm/cache.h>
-#include <linux/errno.h>
 #include <linux/types.h>
+#include <common.h>
 
 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void invalidate_dcache_all(void)
@@ -89,8 +89,3 @@ void enable_caches(void)
 	dcache_enable();
 #endif
 }
-
-int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm)
-{
-	return -ENOSYS;
-}

arch/arm/cpu/arm926ejs/cpu.c

@@ -12,6 +12,7 @@
  * CPU specific code
  */
 
+#include <common.h>
 #include <command.h>
 #include <cpu_func.h>
 #include <irq_func.h>
@@ -44,6 +45,7 @@ int cleanup_before_linux (void)
 
 	disable_interrupts();
 
+
 	/* turn off I/D-cache */
 	icache_disable();
 	dcache_disable();

arch/arm/cpu/arm926ejs/mxs/Makefile

@@ -3,11 +3,11 @@
 # (C) Copyright 2000-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 
-extra-$(CONFIG_XPL_BUILD) := start.o
+extra-$(CONFIG_SPL_BUILD) := start.o
 
 obj-y	= clock.o mxs.o iomux.o timer.o
 
-ifdef	CONFIG_XPL_BUILD
+ifdef	CONFIG_SPL_BUILD
 obj-y	+= spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o
 endif
 
@@ -53,23 +53,23 @@ quiet_cmd_mkcst_mxs = MXSCST  $@
 cmd_mkcst_mxs = cst -o $@ < $^						\
 	$(if $(KBUILD_VERBOSE:1=), >/dev/null)
 
-spl/u-boot-spl.ivt: spl/u-boot-spl.bin FORCE
+spl/u-boot-spl.ivt: spl/u-boot-spl.bin
 	$(call if_changed,mkalign_mxs)
 	$(call if_changed,mkivt_mxs,$(CONFIG_SPL_TEXT_BASE),\
 		0x00008000,0x00008040)
 
-u-boot.ivt: u-boot.bin FORCE
+u-boot.ivt: u-boot.bin
 	$(call if_changed,mkalign_mxs)
 	$(call if_changed,mkivt_mxs,$(CONFIG_TEXT_BASE),\
 		0x40001000,0x40001040)
 
-spl/u-boot-spl.csf: spl/u-boot-spl.ivt spl/u-boot-spl.bin board/$(VENDOR)/$(BOARD)/sign/u-boot-spl.csf FORCE
+spl/u-boot-spl.csf: spl/u-boot-spl.ivt spl/u-boot-spl.bin board/$(VENDOR)/$(BOARD)/sign/u-boot-spl.csf
 	$(call if_changed,mkcsfreq_mxs,$(CONFIG_SPL_TEXT_BASE),0x8000)
 
-u-boot.csf: u-boot.ivt u-boot.bin board/$(VENDOR)/$(BOARD)/sign/u-boot.csf FORCE
+u-boot.csf: u-boot.ivt u-boot.bin board/$(VENDOR)/$(BOARD)/sign/u-boot.csf
 	$(call if_changed,mkcsfreq_mxs,$(CONFIG_TEXT_BASE),0x40001000)
 
-%.sig: %.csf FORCE
+%.sig: %.csf
 	$(call if_changed,mkcst_mxs)
 
 MKIMAGEFLAGS_u-boot.sb = -n $< -T mxsimage

arch/arm/cpu/arm926ejs/mxs/clock.c

@@ -9,6 +9,7 @@
  * Copyright (C) 2010 Freescale Semiconductor, Inc.
  */
 
+#include <common.h>
 #include <log.h>
 #include <linux/errno.h>
 #include <asm/io.h>

arch/arm/cpu/arm926ejs/mxs/iomux.c

@@ -6,6 +6,7 @@
  *                       <armlinux@phytec.de>
  */
 
+#include <common.h>
 #include <linux/errno.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>

arch/arm/cpu/arm926ejs/mxs/mxs.c

@@ -9,6 +9,7 @@
  * Copyright (C) 2010 Freescale Semiconductor, Inc.
  */
 
+#include <common.h>
 #include <command.h>
 #include <cpu_func.h>
 #include <hang.h>
@@ -70,7 +71,6 @@ void reset_cpu(void)
  * actually 0x20, this the associated <destination address>. Loading the PC
  * register with an address performs a jump to that address.
  */
-noinline __attribute__((target("arm")))
 void mx28_fixup_vt(uint32_t start_addr)
 {
 	/* ldr pc, [pc, #0x18] */
@@ -85,9 +85,6 @@ void mx28_fixup_vt(uint32_t start_addr)
 		/* cppcheck-suppress nullPointer */
 		vt[i + 8] = start_addr + (4 * i);
 	}
-
-	/* Make sure ARM core points to low vectors */
-	set_cr(get_cr() & ~CR_V);
 }
 
 #ifdef	CONFIG_ARCH_MISC_INIT
@@ -103,7 +100,7 @@ int arch_cpu_init(void)
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
-	mx28_fixup_vt((uint32_t)_start);
+	mx28_fixup_vt((uint32_t)&_start);
 
 	/*
 	 * Enable NAND clock

arch/arm/cpu/arm926ejs/mxs/spl_boot.c

@@ -6,6 +6,7 @@
  * on behalf of DENX Software Engineering GmbH
  */
 
+#include <common.h>
 #include <config.h>
 #include <init.h>
 #include <log.h>
@@ -16,7 +17,6 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/sections.h>
-#include <asm/system.h>
 #include <linux/compiler.h>
 
 #include "mxs_init.h"
@@ -93,9 +93,7 @@ static uint8_t mxs_get_bootmode_index(void)
 	return i;
 }
 
-static noinline
-__attribute__((target("arm")))
-void mxs_spl_fixup_vectors(void)
+static void mxs_spl_fixup_vectors(void)
 {
 	/*
 	 * Copy our vector table to 0x0, since due to HAB, we cannot
@@ -105,10 +103,7 @@ void mxs_spl_fixup_vectors(void)
 	 */
 
 	/* cppcheck-suppress nullPointer */
-	memcpy(0x0, _start, 0x60);
-
-	/* Make sure ARM core points to low vectors */
-	set_cr(get_cr() & ~CR_V);
+	memcpy(0x0, &_start, 0x60);
 }
 
 static void mxs_spl_console_init(void)
@@ -117,7 +112,7 @@ static void mxs_spl_console_init(void)
 	gd->bd = &bdata;
 	gd->baudrate = CONFIG_BAUDRATE;
 	serial_init();
-	gd->flags |= GD_FLG_HAVE_CONSOLE;
+	gd->have_console = 1;
 #endif
 }
 
@@ -133,10 +128,8 @@ void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
 
 	mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size);
 
-	if (!CONFIG_IS_ENABLED(DM_SERIAL)) {
-		mxs_spl_console_init();
-		debug("SPL: Serial Console Initialised\n");
-	}
+	mxs_spl_console_init();
+	debug("SPL: Serial Console Initialised\n");
 
 	mxs_power_init();
 

arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c

@@ -6,6 +6,7 @@
  * on behalf of DENX Software Engineering GmbH
  */
 
+#include <common.h>
 #include <config.h>
 #include <log.h>
 #include <asm/io.h>

arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c

@@ -6,6 +6,7 @@
  * on behalf of DENX Software Engineering GmbH
  */
 
+#include <common.h>
 #include <config.h>
 #include <init.h>
 #include <log.h>

arch/arm/cpu/arm926ejs/mxs/spl_power_init.c

@@ -6,6 +6,7 @@
  * on behalf of DENX Software Engineering GmbH
  */
 
+#include <common.h>
 #include <config.h>
 #include <hang.h>
 #include <log.h>
@@ -40,29 +41,6 @@ static void mxs_power_clock2xtal(void)
 		&clkctrl_regs->hw_clkctrl_clkseq_set);
 }
 
-static void mxs_power_regs_dump(void)
-{
-	struct mxs_power_regs *power_regs =
-		(struct mxs_power_regs *)MXS_POWER_BASE;
-
-	debug("ctrl:\t\t 0x%x\n", readl(&power_regs->hw_power_ctrl));
-	debug("5vctrl:\t\t 0x%x\n", readl(&power_regs->hw_power_5vctrl));
-	debug("minpwr:\t\t 0x%x\n", readl(&power_regs->hw_power_minpwr));
-	debug("charge:\t\t 0x%x\n", readl(&power_regs->hw_power_charge));
-	debug("vddctrl:\t 0x%x\n", readl(&power_regs->hw_power_vdddctrl));
-	debug("vddactrl:\t 0x%x\n", readl(&power_regs->hw_power_vddactrl));
-	debug("vddioctrl:\t 0x%x\n", readl(&power_regs->hw_power_vddioctrl));
-	debug("vddmemctrl:\t 0x%x\n", readl(&power_regs->hw_power_vddmemctrl));
-	debug("dcdc4p2:\t 0x%x\n", readl(&power_regs->hw_power_dcdc4p2));
-	debug("misc:\t\t 0x%x\n", readl(&power_regs->hw_power_misc));
-	debug("dclimits:\t 0x%x\n", readl(&power_regs->hw_power_dclimits));
-	debug("loopctrl:\t 0x%x\n", readl(&power_regs->hw_power_loopctrl));
-	debug("sts:\t\t 0x%x\n", readl(&power_regs->hw_power_sts));
-	debug("speed:\t\t 0x%x\n", readl(&power_regs->hw_power_speed));
-	debug("battmonitor:\t 0x%x\n",
-	      readl(&power_regs->hw_power_battmonitor));
-}
-
 /**
  * mxs_power_clock2pll() - Switch CPU core clock source to PLL
  *
@@ -774,19 +752,7 @@ static void mxs_batt_boot(void)
 		POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
 		0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 
-	if (CONFIG_IS_ENABLED(MXS_PMU_MINIMAL_VDD5V_CURRENT))
-		setbits_le32(&power_regs->hw_power_5vctrl,
-			     POWER_5VCTRL_ILIMIT_EQ_ZERO);
-
-	if (CONFIG_IS_ENABLED(MXS_PMU_DISABLE_BATT_CHARGE)) {
-		writel(POWER_CHARGE_PWD_BATTCHRG,
-		       &power_regs->hw_power_charge_set);
-		writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
-		       &power_regs->hw_power_5vctrl_set);
-	}
-
-	if (CONFIG_IS_ENABLED(MXS_PMU_ENABLE_4P2_LINEAR_REGULATOR))
-		mxs_power_enable_4p2();
+	mxs_power_enable_4p2();
 }
 
 /**
@@ -1176,9 +1142,8 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
 
 	if (adjust_up && cfg->bo_irq) {
 		if (powered_by_linreg) {
-			bo_int = readl(&power_regs->hw_power_ctrl);
-			clrbits_le32(&power_regs->hw_power_ctrl,
-				cfg->bo_enirq);
+			bo_int = readl(cfg->reg);
+			clrbits_le32(cfg->reg, cfg->bo_enirq);
 		}
 		setbits_le32(cfg->reg, cfg->bo_offset_mask);
 	}
@@ -1220,8 +1185,7 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
 		if (adjust_up && powered_by_linreg) {
 			writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
 			if (bo_int & cfg->bo_enirq)
-				setbits_le32(&power_regs->hw_power_ctrl,
-					cfg->bo_enirq);
+				setbits_le32(cfg->reg, cfg->bo_enirq);
 		}
 
 		clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
@@ -1304,7 +1268,6 @@ void mxs_power_init(void)
 		POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
 
 	writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set);
-	mxs_power_regs_dump();
 
 	early_delay(1000);
 }

arch/arm/cpu/arm926ejs/mxs/start.S

@@ -20,6 +20,7 @@
 
 #include <asm-offsets.h>
 #include <config.h>
+#include <common.h>
 #include <system-constants.h>
 
 /*

arch/arm/cpu/arm926ejs/mxs/timer.c

@@ -9,6 +9,7 @@
  * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
  */
 
+#include <common.h>
 #include <init.h>
 #include <time.h>
 #include <asm/global_data.h>

arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds

@@ -33,15 +33,27 @@ SECTIONS
 		*(.data*)
 	}
 
+	. = ALIGN(4);
+
+	.rel.dyn : {
+		__rel_dyn_start = .;
+		*(.rel*)
+		__rel_dyn_end = .;
+	}
+
 	.bss : {
 		. = ALIGN(4);
 		__bss_start = .;
 		*(.bss*)
-		. = ALIGN(8);
+		. = ALIGN(4);
 		__bss_end = .;
 	}
 
-	_end = .;
+	.end :
+	{
+		*(.__end)
+	}
+
 	_image_binary_end = .;
 
 	.dynsym _image_binary_end : { *(.dynsym) }
@@ -54,6 +66,3 @@ SECTIONS
 	.gnu : { *(.gnu*) }
 	.ARM.exidx : { *(.ARM.exidx*) }
 }
-
-ASSERT(_image_binary_end % 8 == 0, \
-       "_image_binary_end must be 8-byte aligned for device tree");

arch/arm/cpu/arm926ejs/start.S

@@ -16,6 +16,7 @@
 
 #include <asm-offsets.h>
 #include <config.h>
+#include <common.h>
 #include <linux/linkage.h>
 
 /*

arch/arm/cpu/arm926ejs/sunxi/config.mk

@@ -1,6 +1,6 @@
 # Build a combined spl + u-boot image
 ifdef CONFIG_SPL
-ifndef CONFIG_XPL_BUILD
+ifndef CONFIG_SPL_BUILD
 ALL-y += u-boot-sunxi-with-spl.bin
 endif
 endif

arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds

@@ -31,9 +31,9 @@ SECTIONS
 	. = ALIGN(4);
 	__u_boot_list : {
 		KEEP(*(SORT(__u_boot_list*)));
-		. = ALIGN(8);
 	} > .sram
 
+	. = ALIGN(4);
 	__image_copy_end = .;
 	_end = .;
 	_image_binary_end = .;
@@ -47,6 +47,3 @@ SECTIONS
 		__bss_end = .;
 	} > .sdram
 }
-
-ASSERT(_image_binary_end % 8 == 0, \
-       "_image_binary_end must be 8-byte aligned for device tree");

arch/arm/cpu/arm946es/cpu.c

@@ -12,6 +12,7 @@
  * CPU specific code
  */
 
+#include <common.h>
 #include <command.h>
 #include <cpu_func.h>
 #include <irq_func.h>

arch/arm/cpu/armv7/Kconfig

@@ -28,7 +28,7 @@ config ARMV7_BOOT_SEC_DEFAULT
 	variable to "sec" or "nonsec".
 
 config HAS_ARMV7_SECURE_BASE
-	bool "Enable support for a hardware secure memory area"
+	bool "Enable support for a ahardware secure memory area"
 	default y if ARCH_LS1021A || ARCH_MX7 || ARCH_MX7ULP || ARCH_STM32MP \
 			|| MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || TEGRA124
 
@@ -36,8 +36,7 @@ config ARMV7_SECURE_BASE
 	hex "Base address for secure mode memory"
 	depends on HAS_ARMV7_SECURE_BASE
 	default 0xfff00000 if TEGRA124
-	default 0x2ffe0000 if STM32MP13X
-	default 0x2ffc0000 if STM32MP15X
+	default 0x2ffc0000 if ARCH_STM32MP
 	default 0x2f000000 if ARCH_MX7ULP
 	default 0x10010000 if ARCH_LS1021A
 	default 0x00900000 if ARCH_MX7
@@ -59,17 +58,6 @@ config ARMV7_SECURE_MAX_SIZE
 	default 0x3c00 if MACH_SUN8I && MACH_SUN8I_H3
 	default 0x10000
 
-config ARM_GIC_BASE_ADDRESS
-	hex
-	depends on ARMV7_NONSEC
-	depends on ARCH_EXYNOS5 || MACH_SUN8I_R528
-	default 0x10480000 if ARCH_EXYNOS5
-	default 0x03020000 if MACH_SUN8I_R528
-	help
-	  Override the GIC base address if the Arm Cortex defined
-	  CBAR/PERIPHBASE system register holds the wrong value.
-	  Used by the PSCI code to configure the secure side of the GIC.
-
 config ARMV7_VIRT
 	bool "Enable support for hardware virtualization" if EXPERT
 	depends on CPU_V7_HAS_VIRT && ARMV7_NONSEC
@@ -122,7 +110,7 @@ config ARMV7_LPAE
 config ARMV7_SET_CORTEX_SMPEN
 	bool
 	help
-	  Enable the ARM Cortex ACTLR.SMP enable bit in U-Boot.
+	  Enable the ARM Cortex ACTLR.SMP enable bit in U-boot.
 
 config SPL_ARMV7_SET_CORTEX_SMPEN
 	bool

arch/arm/cpu/armv7/Makefile

@@ -12,12 +12,12 @@ obj-y	+= syslib.o
 
 obj-$(CONFIG_SYS_ARM_MPU) += mpu_v7r.o
 
-ifneq ($(CONFIG_XPL_BUILD),y)
+ifneq ($(CONFIG_SPL_BUILD),y)
 obj-$(CONFIG_EFI_LOADER) += sctlr.o
 obj-$(CONFIG_ARMV7_NONSEC) += exception_level.o
 endif
 
-ifneq ($(CONFIG_$(PHASE_)SKIP_LOWLEVEL_INIT),y)
+ifneq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),y)
 obj-y	+= lowlevel_init.o
 endif
 
@@ -32,10 +32,12 @@ ifneq (,$(filter s5pc1xx exynos,$(SOC)))
 obj-y += s5p-common/
 endif
 
+obj-$(if $(filter bcm235xx,$(SOC)),y) += bcm235xx/
 obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
 obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
 obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
 obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/
+obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
 obj-$(CONFIG_ARCH_SUNXI) += sunxi/
 obj-$(CONFIG_VF610) += vf610/
 obj-$(CONFIG_ARCH_S5P4418) += s5p4418/

arch/arm/cpu/armv7/arch_timer.c

@@ -4,7 +4,7 @@
  *     Texas Instruments Incorporated, <www.ti.com>
  */
 
-#include <config.h>
+#include <common.h>
 #include <init.h>
 #include <time.h>
 #include <asm/global_data.h>
@@ -49,6 +49,7 @@ unsigned long long get_ticks(void)
 	return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
 }
 
+
 ulong timer_get_boot_us(void)
 {
 	if (!gd->arch.timer_rate_hz)

arch/arm/cpu/armv7/bcm235xx/Makefile

@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2013 Broadcom Corporation.
+
+obj-y	+= clk-core.o
+obj-y	+= clk-bcm235xx.o
+obj-y	+= clk-sdio.o
+obj-y	+= clk-bsc.o
+obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
+obj-y	+= clk-usb-otg.o

arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c

@@ -0,0 +1,568 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013 Broadcom Corporation.
+ */
+
+/*
+ *
+ * bcm235xx-specific clock tables
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+#define CLOCK_1K		1000
+#define CLOCK_1M		(CLOCK_1K * 1000)
+
+/* declare a reference clock */
+#define DECLARE_REF_CLK(clk_name, clk_parent, clk_rate, clk_div) \
+static struct refclk clk_name = { \
+	.clk	=	{ \
+		.name	=	#clk_name, \
+		.parent =	clk_parent, \
+		.rate	=	clk_rate, \
+		.div	=	clk_div, \
+		.ops	=	&ref_clk_ops, \
+	}, \
+}
+
+/*
+ * Reference clocks
+ */
+
+/* Declare a list of reference clocks */
+DECLARE_REF_CLK(ref_crystal,	0,		26  * CLOCK_1M,	1);
+DECLARE_REF_CLK(var_96m,	0,		96  * CLOCK_1M,	1);
+DECLARE_REF_CLK(ref_96m,	0,		96  * CLOCK_1M,	1);
+DECLARE_REF_CLK(ref_312m,	0,		312 * CLOCK_1M,	0);
+DECLARE_REF_CLK(ref_104m,	&ref_312m.clk,	104 * CLOCK_1M,	3);
+DECLARE_REF_CLK(ref_52m,	&ref_104m.clk,	52  * CLOCK_1M,	2);
+DECLARE_REF_CLK(ref_13m,	&ref_52m.clk,	13  * CLOCK_1M,	4);
+DECLARE_REF_CLK(var_312m,	0,		312 * CLOCK_1M,	0);
+DECLARE_REF_CLK(var_104m,	&var_312m.clk,	104 * CLOCK_1M,	3);
+DECLARE_REF_CLK(var_52m,	&var_104m.clk,	52  * CLOCK_1M,	2);
+DECLARE_REF_CLK(var_13m,	&var_52m.clk,	13  * CLOCK_1M,	4);
+
+struct refclk_lkup {
+	struct refclk *procclk;
+	const char *name;
+};
+
+/* Lookup table for string to clk tranlation */
+#define MKSTR(x) {&x, #x}
+static struct refclk_lkup refclk_str_tbl[] = {
+	MKSTR(ref_crystal), MKSTR(var_96m), MKSTR(ref_96m),
+	MKSTR(ref_312m), MKSTR(ref_104m), MKSTR(ref_52m),
+	MKSTR(ref_13m), MKSTR(var_312m), MKSTR(var_104m),
+	MKSTR(var_52m), MKSTR(var_13m),
+};
+
+int refclk_entries = sizeof(refclk_str_tbl)/sizeof(refclk_str_tbl[0]);
+
+/* convert ref clock string to clock structure pointer */
+struct refclk *refclk_str_to_clk(const char *name)
+{
+	int i;
+	struct refclk_lkup *tblp = refclk_str_tbl;
+	for (i = 0; i < refclk_entries; i++, tblp++) {
+		if (!(strcmp(name, tblp->name)))
+			return tblp->procclk;
+	}
+	return NULL;
+}
+
+/* frequency tables indexed by freq_id */
+unsigned long master_axi_freq_tbl[8] = {
+	26 * CLOCK_1M,
+	52 * CLOCK_1M,
+	104 * CLOCK_1M,
+	156 * CLOCK_1M,
+	156 * CLOCK_1M,
+	208 * CLOCK_1M,
+	312 * CLOCK_1M,
+	312 * CLOCK_1M
+};
+
+unsigned long master_ahb_freq_tbl[8] = {
+	26 * CLOCK_1M,
+	52 * CLOCK_1M,
+	52 * CLOCK_1M,
+	52 * CLOCK_1M,
+	78 * CLOCK_1M,
+	104 * CLOCK_1M,
+	104 * CLOCK_1M,
+	156 * CLOCK_1M
+};
+
+unsigned long slave_axi_freq_tbl[8] = {
+	26 * CLOCK_1M,
+	52 * CLOCK_1M,
+	78 * CLOCK_1M,
+	104 * CLOCK_1M,
+	156 * CLOCK_1M,
+	156 * CLOCK_1M
+};
+
+unsigned long slave_apb_freq_tbl[8] = {
+	26 * CLOCK_1M,
+	26 * CLOCK_1M,
+	39 * CLOCK_1M,
+	52 * CLOCK_1M,
+	52 * CLOCK_1M,
+	78 * CLOCK_1M
+};
+
+unsigned long esub_freq_tbl[8] = {
+	78 * CLOCK_1M,
+	156 * CLOCK_1M,
+	156 * CLOCK_1M,
+	156 * CLOCK_1M,
+	208 * CLOCK_1M,
+	208 * CLOCK_1M,
+	208 * CLOCK_1M
+};
+
+static struct bus_clk_data bsc1_apb_data = {
+	.gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1),
+};
+
+static struct bus_clk_data bsc2_apb_data = {
+	.gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1),
+};
+
+static struct bus_clk_data bsc3_apb_data = {
+	.gate = HW_SW_GATE_AUTO(0x0484, 16, 0, 1),
+};
+
+/* * Master CCU clocks */
+static struct peri_clk_data sdio1_data = {
+	.gate		= HW_SW_GATE(0x0358, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_52m",
+				 "ref_52m",
+				 "var_96m",
+				 "ref_96m"),
+	.sel		= SELECTOR(0x0a28, 0, 3),
+	.div		= DIVIDER(0x0a28, 4, 14),
+	.trig		= TRIGGER(0x0afc, 9),
+};
+
+static struct peri_clk_data sdio2_data = {
+	.gate		= HW_SW_GATE(0x035c, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_52m",
+				 "ref_52m",
+				 "var_96m",
+				 "ref_96m"),
+	.sel		= SELECTOR(0x0a2c, 0, 3),
+	.div		= DIVIDER(0x0a2c, 4, 14),
+	.trig		= TRIGGER(0x0afc, 10),
+};
+
+static struct peri_clk_data sdio3_data = {
+	.gate		= HW_SW_GATE(0x0364, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_52m",
+				 "ref_52m",
+				 "var_96m",
+				 "ref_96m"),
+	.sel		= SELECTOR(0x0a34, 0, 3),
+	.div		= DIVIDER(0x0a34, 4, 14),
+	.trig		= TRIGGER(0x0afc, 12),
+};
+
+static struct peri_clk_data sdio4_data = {
+	.gate		= HW_SW_GATE(0x0360, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_52m",
+				 "ref_52m",
+				 "var_96m",
+				 "ref_96m"),
+	.sel		= SELECTOR(0x0a30, 0, 3),
+	.div		= DIVIDER(0x0a30, 4, 14),
+	.trig		= TRIGGER(0x0afc, 11),
+};
+
+static struct peri_clk_data sdio1_sleep_data = {
+	.clocks		= CLOCKS("ref_32k"),
+	.gate		= SW_ONLY_GATE(0x0358, 20, 4),
+};
+
+static struct peri_clk_data sdio2_sleep_data = {
+	.clocks		= CLOCKS("ref_32k"),
+	.gate		= SW_ONLY_GATE(0x035c, 20, 4),
+};
+
+static struct peri_clk_data sdio3_sleep_data = {
+	.clocks		= CLOCKS("ref_32k"),
+	.gate		= SW_ONLY_GATE(0x0364, 20, 4),
+};
+
+static struct peri_clk_data sdio4_sleep_data = {
+	.clocks		= CLOCKS("ref_32k"),
+	.gate		= SW_ONLY_GATE(0x0360, 20, 4),
+};
+
+static struct bus_clk_data usb_otg_ahb_data = {
+	.gate		= HW_SW_GATE_AUTO(0x0348, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio1_ahb_data = {
+	.gate		= HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio2_ahb_data = {
+	.gate		= HW_SW_GATE_AUTO(0x035c, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio3_ahb_data = {
+	.gate		= HW_SW_GATE_AUTO(0x0364, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio4_ahb_data = {
+	.gate		= HW_SW_GATE_AUTO(0x0360, 16, 0, 1),
+};
+
+/* * Slave CCU clocks */
+static struct peri_clk_data bsc1_data = {
+	.gate		= HW_SW_GATE(0x0458, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_104m",
+				 "ref_104m",
+				 "var_13m",
+				 "ref_13m"),
+	.sel		= SELECTOR(0x0a64, 0, 3),
+	.trig		= TRIGGER(0x0afc, 23),
+};
+
+static struct peri_clk_data bsc2_data = {
+	.gate		= HW_SW_GATE(0x045c, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_104m",
+				 "ref_104m",
+				 "var_13m",
+				 "ref_13m"),
+	.sel		= SELECTOR(0x0a68, 0, 3),
+	.trig		= TRIGGER(0x0afc, 24),
+};
+
+static struct peri_clk_data bsc3_data = {
+	.gate		= HW_SW_GATE(0x0484, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_104m",
+				 "ref_104m",
+				 "var_13m",
+				 "ref_13m"),
+	.sel		= SELECTOR(0x0a84, 0, 3),
+	.trig		= TRIGGER(0x0b00, 2),
+};
+
+/*
+ * CCU clocks
+ */
+
+static struct ccu_clock kpm_ccu_clk = {
+	.clk = {
+		.name = "kpm_ccu_clk",
+		.ops = &ccu_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.num_policy_masks = 1,
+	.policy_freq_offset = 0x00000008,
+	.freq_bit_shift = 8,
+	.policy_ctl_offset = 0x0000000c,
+	.policy0_mask_offset = 0x00000010,
+	.policy1_mask_offset = 0x00000014,
+	.policy2_mask_offset = 0x00000018,
+	.policy3_mask_offset = 0x0000001c,
+	.lvm_en_offset = 0x00000034,
+	.freq_id = 2,
+	.freq_tbl = master_axi_freq_tbl,
+};
+
+static struct ccu_clock kps_ccu_clk = {
+	.clk = {
+		.name = "kps_ccu_clk",
+		.ops = &ccu_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+	},
+	.num_policy_masks = 1,
+	.policy_freq_offset = 0x00000008,
+	.freq_bit_shift = 8,
+	.policy_ctl_offset = 0x0000000c,
+	.policy0_mask_offset = 0x00000010,
+	.policy1_mask_offset = 0x00000014,
+	.policy2_mask_offset = 0x00000018,
+	.policy3_mask_offset = 0x0000001c,
+	.lvm_en_offset = 0x00000034,
+	.freq_id = 2,
+	.freq_tbl = slave_axi_freq_tbl,
+};
+
+#ifdef CONFIG_BCM_SF2_ETH
+static struct ccu_clock esub_ccu_clk = {
+	.clk = {
+		.name = "esub_ccu_clk",
+		.ops = &ccu_clk_ops,
+		.ccu_clk_mgr_base = ESUB_CLK_BASE_ADDR,
+	},
+	.num_policy_masks = 1,
+	.policy_freq_offset = 0x00000008,
+	.freq_bit_shift = 8,
+	.policy_ctl_offset = 0x0000000c,
+	.policy0_mask_offset = 0x00000010,
+	.policy1_mask_offset = 0x00000014,
+	.policy2_mask_offset = 0x00000018,
+	.policy3_mask_offset = 0x0000001c,
+	.lvm_en_offset = 0x00000034,
+	.freq_id = 2,
+	.freq_tbl = esub_freq_tbl,
+};
+#endif
+
+/*
+ * Bus clocks
+ */
+
+/* KPM bus clocks */
+static struct bus_clock usb_otg_ahb_clk = {
+	.clk = {
+		.name = "usb_otg_ahb_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.freq_tbl = master_ahb_freq_tbl,
+	.data = &usb_otg_ahb_data,
+};
+
+static struct bus_clock sdio1_ahb_clk = {
+	.clk = {
+		.name = "sdio1_ahb_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.freq_tbl = master_ahb_freq_tbl,
+	.data = &sdio1_ahb_data,
+};
+
+static struct bus_clock sdio2_ahb_clk = {
+	.clk = {
+		.name = "sdio2_ahb_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.freq_tbl = master_ahb_freq_tbl,
+	.data = &sdio2_ahb_data,
+};
+
+static struct bus_clock sdio3_ahb_clk = {
+	.clk = {
+		.name = "sdio3_ahb_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.freq_tbl = master_ahb_freq_tbl,
+	.data = &sdio3_ahb_data,
+};
+
+static struct bus_clock sdio4_ahb_clk = {
+	.clk = {
+		.name = "sdio4_ahb_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.freq_tbl = master_ahb_freq_tbl,
+	.data = &sdio4_ahb_data,
+};
+
+static struct bus_clock bsc1_apb_clk = {
+	.clk = {
+		.name = "bsc1_apb_clk",
+		.parent = &kps_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+	},
+	.freq_tbl = slave_apb_freq_tbl,
+	.data = &bsc1_apb_data,
+};
+
+static struct bus_clock bsc2_apb_clk = {
+	.clk = {
+		.name = "bsc2_apb_clk",
+		.parent = &kps_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+		},
+	.freq_tbl = slave_apb_freq_tbl,
+	.data = &bsc2_apb_data,
+};
+
+static struct bus_clock bsc3_apb_clk = {
+	.clk = {
+		.name = "bsc3_apb_clk",
+		.parent = &kps_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+		},
+	.freq_tbl = slave_apb_freq_tbl,
+	.data = &bsc3_apb_data,
+};
+
+/* KPM peripheral */
+static struct peri_clock sdio1_clk = {
+	.clk = {
+		.name = "sdio1_clk",
+		.parent = &ref_52m.clk,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio1_data,
+};
+
+static struct peri_clock sdio2_clk = {
+	.clk = {
+		.name = "sdio2_clk",
+		.parent = &ref_52m.clk,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio2_data,
+};
+
+static struct peri_clock sdio3_clk = {
+	.clk = {
+		.name = "sdio3_clk",
+		.parent = &ref_52m.clk,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio3_data,
+};
+
+static struct peri_clock sdio4_clk = {
+	.clk = {
+		.name = "sdio4_clk",
+		.parent = &ref_52m.clk,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio4_data,
+};
+
+static struct peri_clock sdio1_sleep_clk = {
+	.clk = {
+		.name = "sdio1_sleep_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio1_sleep_data,
+};
+
+static struct peri_clock sdio2_sleep_clk = {
+	.clk = {
+		.name = "sdio2_sleep_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio2_sleep_data,
+};
+
+static struct peri_clock sdio3_sleep_clk = {
+	.clk = {
+		.name = "sdio3_sleep_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio3_sleep_data,
+};
+
+static struct peri_clock sdio4_sleep_clk = {
+	.clk = {
+		.name = "sdio4_sleep_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio4_sleep_data,
+};
+
+/* KPS peripheral clock */
+static struct peri_clock bsc1_clk = {
+	.clk = {
+		.name = "bsc1_clk",
+		.parent = &ref_13m.clk,
+		.rate = 13 * CLOCK_1M,
+		.div = 1,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+	},
+	.data = &bsc1_data,
+};
+
+static struct peri_clock bsc2_clk = {
+	.clk = {
+		.name = "bsc2_clk",
+		.parent = &ref_13m.clk,
+		.rate = 13 * CLOCK_1M,
+		.div = 1,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+	},
+	.data = &bsc2_data,
+};
+
+static struct peri_clock bsc3_clk = {
+	.clk = {
+		.name = "bsc3_clk",
+		.parent = &ref_13m.clk,
+		.rate = 13 * CLOCK_1M,
+		.div = 1,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+	},
+	.data = &bsc3_data,
+};
+
+/* public table for registering clocks */
+struct clk_lookup arch_clk_tbl[] = {
+	/* Peripheral clocks */
+	CLK_LK(sdio1),
+	CLK_LK(sdio2),
+	CLK_LK(sdio3),
+	CLK_LK(sdio4),
+	CLK_LK(sdio1_sleep),
+	CLK_LK(sdio2_sleep),
+	CLK_LK(sdio3_sleep),
+	CLK_LK(sdio4_sleep),
+	CLK_LK(bsc1),
+	CLK_LK(bsc2),
+	CLK_LK(bsc3),
+	/* Bus clocks */
+	CLK_LK(usb_otg_ahb),
+	CLK_LK(sdio1_ahb),
+	CLK_LK(sdio2_ahb),
+	CLK_LK(sdio3_ahb),
+	CLK_LK(sdio4_ahb),
+	CLK_LK(bsc1_apb),
+	CLK_LK(bsc2_apb),
+	CLK_LK(bsc3_apb),
+#ifdef CONFIG_BCM_SF2_ETH
+	CLK_LK(esub_ccu),
+#endif
+};
+
+/* public array size */
+unsigned int arch_clk_tbl_array_size = ARRAY_SIZE(arch_clk_tbl);

arch/arm/cpu/armv7/bcm235xx/clk-bsc.c

@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013 Broadcom Corporation.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+/* Enable appropriate clocks for a BSC/I2C port */
+int clk_bsc_enable(void *base)
+{
+	int ret;
+	char *bscstr, *apbstr;
+
+	switch ((u32) base) {
+	case PMU_BSC_BASE_ADDR:
+		/* PMU clock is always enabled */
+		return 0;
+	case BSC1_BASE_ADDR:
+		bscstr = "bsc1_clk";
+		apbstr = "bsc1_apb_clk";
+		break;
+	case BSC2_BASE_ADDR:
+		bscstr = "bsc2_clk";
+		apbstr = "bsc2_apb_clk";
+		break;
+	case BSC3_BASE_ADDR:
+		bscstr = "bsc3_clk";
+		apbstr = "bsc3_apb_clk";
+		break;
+	default:
+		printf("%s: base 0x%p not found\n", __func__, base);
+		return -EINVAL;
+	}
+
+	/* Note that the bus clock must be enabled first */
+
+	ret = clk_get_and_enable(apbstr);
+	if (ret)
+		return ret;
+
+	ret = clk_get_and_enable(bscstr);
+	if (ret)
+		return ret;
+
+	return 0;
+}

arch/arm/cpu/armv7/bcm235xx/clk-core.c

@@ -0,0 +1,514 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013 Broadcom Corporation.
+ */
+
+/*
+ *
+ * bcm235xx architecture clock framework
+ *
+ */
+
+#include <common.h>
+#include <log.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <bitfield.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+#define CLK_WR_ACCESS_PASSWORD	0x00a5a501
+#define WR_ACCESS_OFFSET	0	/* common to all clock blocks */
+#define POLICY_CTL_GO		1	/* Load and refresh policy masks */
+#define POLICY_CTL_GO_ATL	4	/* Active Load */
+
+/* Helper function */
+int clk_get_and_enable(char *clkstr)
+{
+	int ret = 0;
+	struct clk *c;
+
+	debug("%s: %s\n", __func__, clkstr);
+
+	c = clk_get(clkstr);
+	if (c) {
+		ret = clk_enable(c);
+		if (ret)
+			return ret;
+	} else {
+		printf("%s: Couldn't find %s\n", __func__, clkstr);
+		return -EINVAL;
+	}
+	return ret;
+}
+
+/*
+ * Poll a register in a CCU's address space, returning when the
+ * specified bit in that register's value is set (or clear). Delay
+ * a microsecond after each read of the register. Returns true if
+ * successful, or false if we gave up trying.
+ *
+ * Caller must ensure the CCU lock is held.
+ */
+#define CLK_GATE_DELAY_USEC 2000
+static inline int wait_bit(void *base, u32 offset, u32 bit, bool want)
+{
+	unsigned int tries;
+	u32 bit_mask = 1 << bit;
+
+	for (tries = 0; tries < CLK_GATE_DELAY_USEC; tries++) {
+		u32 val;
+		bool bit_val;
+
+		val = readl(base + offset);
+		bit_val = (val & bit_mask) ? 1 : 0;
+		if (bit_val == want)
+			return 0;	/* success */
+		udelay(1);
+	}
+
+	debug("%s: timeout on addr 0x%p, waiting for bit %d to go to %d\n",
+	      __func__, base + offset, bit, want);
+
+	return -ETIMEDOUT;
+}
+
+/* Enable a peripheral clock */
+static int peri_clk_enable(struct clk *c, int enable)
+{
+	int ret = 0;
+	u32 reg;
+	struct peri_clock *peri_clk = to_peri_clk(c);
+	struct peri_clk_data *cd = peri_clk->data;
+	struct bcm_clk_gate *gate = &cd->gate;
+	void *base = (void *)c->ccu_clk_mgr_base;
+
+
+	debug("%s: %s\n", __func__, c->name);
+
+	clk_get_rate(c);	/* Make sure rate and sel are filled in */
+
+	/* enable access */
+	writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
+
+	if (enable) {
+		debug("%s %s set rate %lu div %lu sel %d parent %lu\n",
+		      __func__, c->name, c->rate, c->div, c->sel,
+		      c->parent->rate);
+
+		/*
+		 * clkgate - only software controllable gates are
+		 * supported by u-boot which includes all clocks
+		 * that matter. This avoids bringing in a lot of extra
+		 * complexity as done in the kernel framework.
+		 */
+		if (gate_exists(gate)) {
+			reg = readl(base + cd->gate.offset);
+			reg |= (1 << cd->gate.en_bit);
+			writel(reg, base + cd->gate.offset);
+		}
+
+		/* div and pll select */
+		if (divider_exists(&cd->div)) {
+			reg = readl(base + cd->div.offset);
+			bitfield_replace(reg, cd->div.shift, cd->div.width,
+					 c->div - 1);
+			writel(reg, base + cd->div.offset);
+		}
+
+		/* frequency selector */
+		if (selector_exists(&cd->sel)) {
+			reg = readl(base + cd->sel.offset);
+			bitfield_replace(reg, cd->sel.shift, cd->sel.width,
+					 c->sel);
+			writel(reg, base + cd->sel.offset);
+		}
+
+		/* trigger */
+		if (trigger_exists(&cd->trig)) {
+			writel((1 << cd->trig.bit), base + cd->trig.offset);
+
+			/* wait for trigger status bit to go to 0 */
+			ret = wait_bit(base, cd->trig.offset, cd->trig.bit, 0);
+			if (ret)
+				return ret;
+		}
+
+		/* wait for running (status_bit = 1) */
+		ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1);
+		if (ret)
+			return ret;
+	} else {
+		debug("%s disable clock %s\n", __func__, c->name);
+
+		/* clkgate */
+		reg = readl(base + cd->gate.offset);
+		reg &= ~(1 << cd->gate.en_bit);
+		writel(reg, base + cd->gate.offset);
+
+		/* wait for stop (status_bit = 0) */
+		ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0);
+	}
+
+	/* disable access */
+	writel(0, base + WR_ACCESS_OFFSET);
+
+	return ret;
+}
+
+/* Set the rate of a peripheral clock */
+static int peri_clk_set_rate(struct clk *c, unsigned long rate)
+{
+	int ret = 0;
+	int i;
+	unsigned long diff;
+	unsigned long new_rate = 0, div = 1;
+	struct peri_clock *peri_clk = to_peri_clk(c);
+	struct peri_clk_data *cd = peri_clk->data;
+	const char **clock;
+
+	debug("%s: %s\n", __func__, c->name);
+	diff = rate;
+
+	i = 0;
+	for (clock = cd->clocks; *clock; clock++, i++) {
+		struct refclk *ref = refclk_str_to_clk(*clock);
+		if (!ref) {
+			printf("%s: Lookup of %s failed\n", __func__, *clock);
+			return -EINVAL;
+		}
+
+		/* round to the new rate */
+		div = ref->clk.rate / rate;
+		if (div == 0)
+			div = 1;
+
+		new_rate = ref->clk.rate / div;
+
+		/* get the min diff */
+		if (abs(new_rate - rate) < diff) {
+			diff = abs(new_rate - rate);
+			c->sel = i;
+			c->parent = &ref->clk;
+			c->rate = new_rate;
+			c->div = div;
+		}
+	}
+
+	debug("%s %s set rate %lu div %lu sel %d parent %lu\n", __func__,
+	      c->name, c->rate, c->div, c->sel, c->parent->rate);
+	return ret;
+}
+
+/* Get the rate of a peripheral clock */
+static unsigned long peri_clk_get_rate(struct clk *c)
+{
+	struct peri_clock *peri_clk = to_peri_clk(c);
+	struct peri_clk_data *cd = peri_clk->data;
+	void *base = (void *)c->ccu_clk_mgr_base;
+	int div = 1;
+	const char **clock;
+	struct refclk *ref;
+	u32 reg;
+
+	debug("%s: %s\n", __func__, c->name);
+	if (selector_exists(&cd->sel)) {
+		reg = readl(base + cd->sel.offset);
+		c->sel = bitfield_extract(reg, cd->sel.shift, cd->sel.width);
+	} else {
+		/*
+		 * For peri clocks that don't have a selector, the single
+		 * reference clock will always exist at index 0.
+		 */
+		c->sel = 0;
+	}
+
+	if (divider_exists(&cd->div)) {
+		reg = readl(base + cd->div.offset);
+		div = bitfield_extract(reg, cd->div.shift, cd->div.width);
+		div += 1;
+	}
+
+	clock = cd->clocks;
+	ref = refclk_str_to_clk(clock[c->sel]);
+	if (!ref) {
+		printf("%s: Can't lookup %s\n", __func__, clock[c->sel]);
+		return 0;
+	}
+
+	c->parent = &ref->clk;
+	c->div = div;
+	c->rate = c->parent->rate / c->div;
+	debug("%s parent rate %lu div %d sel %d rate %lu\n", __func__,
+	      c->parent->rate, div, c->sel, c->rate);
+
+	return c->rate;
+}
+
+/* Peripheral clock operations */
+struct clk_ops peri_clk_ops = {
+	.enable = peri_clk_enable,
+	.set_rate = peri_clk_set_rate,
+	.get_rate = peri_clk_get_rate,
+};
+
+/* Enable a CCU clock */
+static int ccu_clk_enable(struct clk *c, int enable)
+{
+	struct ccu_clock *ccu_clk = to_ccu_clk(c);
+	void *base = (void *)c->ccu_clk_mgr_base;
+	int ret = 0;
+	u32 reg;
+
+	debug("%s: %s\n", __func__, c->name);
+	if (!enable)
+		return -EINVAL;	/* CCU clock cannot shutdown */
+
+	/* enable access */
+	writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
+
+	/* config enable for policy engine */
+	writel(1, base + ccu_clk->lvm_en_offset);
+
+	/* wait for bit to go to 0 */
+	ret = wait_bit(base, ccu_clk->lvm_en_offset, 0, 0);
+	if (ret)
+		return ret;
+
+	/* freq ID */
+	if (!ccu_clk->freq_bit_shift)
+		ccu_clk->freq_bit_shift = 8;
+
+	/* Set frequency id for each of the 4 policies */
+	reg = ccu_clk->freq_id |
+	    (ccu_clk->freq_id << (ccu_clk->freq_bit_shift)) |
+	    (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 2)) |
+	    (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 3));
+	writel(reg, base + ccu_clk->policy_freq_offset);
+
+	/* enable all clock mask */
+	writel(0x7fffffff, base + ccu_clk->policy0_mask_offset);
+	writel(0x7fffffff, base + ccu_clk->policy1_mask_offset);
+	writel(0x7fffffff, base + ccu_clk->policy2_mask_offset);
+	writel(0x7fffffff, base + ccu_clk->policy3_mask_offset);
+
+	if (ccu_clk->num_policy_masks == 2) {
+		writel(0x7fffffff, base + ccu_clk->policy0_mask2_offset);
+		writel(0x7fffffff, base + ccu_clk->policy1_mask2_offset);
+		writel(0x7fffffff, base + ccu_clk->policy2_mask2_offset);
+		writel(0x7fffffff, base + ccu_clk->policy3_mask2_offset);
+	}
+
+	/* start policy engine */
+	reg = readl(base + ccu_clk->policy_ctl_offset);
+	reg |= (POLICY_CTL_GO + POLICY_CTL_GO_ATL);
+	writel(reg, base + ccu_clk->policy_ctl_offset);
+
+	/* wait till started */
+	ret = wait_bit(base, ccu_clk->policy_ctl_offset, 0, 0);
+	if (ret)
+		return ret;
+
+	/* disable access */
+	writel(0, base + WR_ACCESS_OFFSET);
+
+	return ret;
+}
+
+/* Get the CCU clock rate */
+static unsigned long ccu_clk_get_rate(struct clk *c)
+{
+	struct ccu_clock *ccu_clk = to_ccu_clk(c);
+	debug("%s: %s\n", __func__, c->name);
+	c->rate = ccu_clk->freq_tbl[ccu_clk->freq_id];
+	return c->rate;
+}
+
+/* CCU clock operations */
+struct clk_ops ccu_clk_ops = {
+	.enable = ccu_clk_enable,
+	.get_rate = ccu_clk_get_rate,
+};
+
+/* Enable a bus clock */
+static int bus_clk_enable(struct clk *c, int enable)
+{
+	struct bus_clock *bus_clk = to_bus_clk(c);
+	struct bus_clk_data *cd = bus_clk->data;
+	void *base = (void *)c->ccu_clk_mgr_base;
+	int ret = 0;
+	u32 reg;
+
+	debug("%s: %s\n", __func__, c->name);
+	/* enable access */
+	writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
+
+	/* enable gating */
+	reg = readl(base + cd->gate.offset);
+	if (!!(reg & (1 << cd->gate.status_bit)) == !!enable)
+		debug("%s already %s\n", c->name,
+		      enable ? "enabled" : "disabled");
+	else {
+		int want = (enable) ? 1 : 0;
+		reg |= (1 << cd->gate.hw_sw_sel_bit);
+
+		if (enable)
+			reg |= (1 << cd->gate.en_bit);
+		else
+			reg &= ~(1 << cd->gate.en_bit);
+
+		writel(reg, base + cd->gate.offset);
+		ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit,
+			       want);
+		if (ret)
+			return ret;
+	}
+
+	/* disable access */
+	writel(0, base + WR_ACCESS_OFFSET);
+
+	return ret;
+}
+
+/* Get the rate of a bus clock */
+static unsigned long bus_clk_get_rate(struct clk *c)
+{
+	struct bus_clock *bus_clk = to_bus_clk(c);
+	struct ccu_clock *ccu_clk;
+
+	debug("%s: %s\n", __func__, c->name);
+	ccu_clk = to_ccu_clk(c->parent);
+
+	c->rate = bus_clk->freq_tbl[ccu_clk->freq_id];
+	c->div = ccu_clk->freq_tbl[ccu_clk->freq_id] / c->rate;
+	return c->rate;
+}
+
+/* Bus clock operations */
+struct clk_ops bus_clk_ops = {
+	.enable = bus_clk_enable,
+	.get_rate = bus_clk_get_rate,
+};
+
+/* Enable a reference clock */
+static int ref_clk_enable(struct clk *c, int enable)
+{
+	debug("%s: %s\n", __func__, c->name);
+	return 0;
+}
+
+/* Reference clock operations */
+struct clk_ops ref_clk_ops = {
+	.enable = ref_clk_enable,
+};
+
+/*
+ * clk.h implementation follows
+ */
+
+/* Initialize the clock framework */
+int clk_init(void)
+{
+	debug("%s:\n", __func__);
+	return 0;
+}
+
+/* Get a clock handle, give a name string */
+struct clk *clk_get(const char *con_id)
+{
+	int i;
+	struct clk_lookup *clk_tblp;
+
+	debug("%s: %s\n", __func__, con_id);
+
+	clk_tblp = arch_clk_tbl;
+	for (i = 0; i < arch_clk_tbl_array_size; i++, clk_tblp++) {
+		if (clk_tblp->con_id) {
+			if (!con_id || strcmp(clk_tblp->con_id, con_id))
+				continue;
+			return clk_tblp->clk;
+		}
+	}
+	return NULL;
+}
+
+/* Enable a clock */
+int clk_enable(struct clk *c)
+{
+	int ret = 0;
+
+	debug("%s: %s\n", __func__, c->name);
+	if (!c->ops || !c->ops->enable)
+		return -1;
+
+	/* enable parent clock first */
+	if (c->parent)
+		ret = clk_enable(c->parent);
+
+	if (ret)
+		return ret;
+
+	if (!c->use_cnt)
+		ret = c->ops->enable(c, 1);
+	c->use_cnt++;
+
+	return ret;
+}
+
+/* Disable a clock */
+void clk_disable(struct clk *c)
+{
+	debug("%s: %s\n", __func__, c->name);
+	if (!c->ops || !c->ops->enable)
+		return;
+
+	if (c->use_cnt > 0) {
+		c->use_cnt--;
+		if (c->use_cnt == 0)
+			c->ops->enable(c, 0);
+	}
+
+	/* disable parent */
+	if (c->parent)
+		clk_disable(c->parent);
+}
+
+/* Get the clock rate */
+unsigned long clk_get_rate(struct clk *c)
+{
+	unsigned long rate;
+
+	if (!c || !c->ops || !c->ops->get_rate)
+		return 0;
+	debug("%s: %s\n", __func__, c->name);
+
+	rate = c->ops->get_rate(c);
+	debug("%s: rate = %ld\n", __func__, rate);
+	return rate;
+}
+
+/* Set the clock rate */
+int clk_set_rate(struct clk *c, unsigned long rate)
+{
+	int ret;
+
+	if (!c || !c->ops || !c->ops->set_rate)
+		return -EINVAL;
+	debug("%s: %s rate=%ld\n", __func__, c->name, rate);
+
+	if (c->use_cnt)
+		return -EINVAL;
+
+	ret = c->ops->set_rate(c, rate);
+
+	return ret;
+}
+
+/* Not required for this arch */
+/*
+long clk_round_rate(struct clk *clk, unsigned long rate);
+int clk_set_parent(struct clk *clk, struct clk *parent);
+struct clk *clk_get_parent(struct clk *clk);
+*/

arch/arm/cpu/armv7/bcm235xx/clk-core.h

@@ -0,0 +1,491 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013 Broadcom Corporation.
+ */
+
+#include <linux/stddef.h>
+#include <linux/stringify.h>
+
+#ifdef CONFIG_CLK_DEBUG
+#undef writel
+#undef readl
+static inline void writel(u32 val, void *addr)
+{
+	printf("Write [0x%p] = 0x%08x\n", addr, val);
+	*(u32 *)addr = val;
+}
+
+static inline u32 readl(void *addr)
+{
+	u32 val = *(u32 *)addr;
+	printf("Read  [0x%p] = 0x%08x\n", addr, val);
+	return val;
+}
+#endif
+
+struct clk;
+
+struct clk_lookup {
+	const char *dev_id;
+	const char *con_id;
+	struct clk *clk;
+};
+
+extern struct clk_lookup arch_clk_tbl[];
+extern unsigned int arch_clk_tbl_array_size;
+
+/**
+ * struct clk_ops - standard clock operations
+ * @enable: enable/disable clock, see clk_enable() and clk_disable()
+ * @set_rate: set the clock rate, see clk_set_rate().
+ * @get_rate: get the clock rate, see clk_get_rate().
+ * @round_rate: round a given clock rate, see clk_round_rate().
+ * @set_parent: set the clock's parent, see clk_set_parent().
+ *
+ * Group the common clock implementations together so that we
+ * don't have to keep setting the same fiels again. We leave
+ * enable in struct clk.
+ *
+ */
+struct clk_ops {
+	int (*enable)(struct clk *c, int enable);
+	int (*set_rate)(struct clk *c, unsigned long rate);
+	unsigned long (*get_rate)(struct clk *c);
+	unsigned long (*round_rate)(struct clk *c, unsigned long rate);
+	int (*set_parent)(struct clk *c, struct clk *parent);
+};
+
+struct clk {
+	struct clk *parent;
+	const char *name;
+	int use_cnt;
+	unsigned long rate;	/* in HZ */
+
+	/* programmable divider. 0 means fixed ratio to parent clock */
+	unsigned long div;
+
+	struct clk_src *src;
+	struct clk_ops *ops;
+
+	unsigned long ccu_clk_mgr_base;
+	int sel;
+};
+
+struct refclk *refclk_str_to_clk(const char *name);
+
+/* The common clock framework uses u8 to represent a parent index */
+#define PARENT_COUNT_MAX	((u32)U8_MAX)
+
+#define BAD_CLK_INDEX		U8_MAX	/* Can't ever be valid */
+#define BAD_CLK_NAME		((const char *)-1)
+
+#define BAD_SCALED_DIV_VALUE	U64_MAX
+
+/*
+ * Utility macros for object flag management. If possible, flags
+ * should be defined such that 0 is the desired default value.
+ */
+#define FLAG(type, flag)		BCM_CLK_ ## type ## _FLAGS_ ## flag
+#define FLAG_SET(obj, type, flag)	((obj)->flags |= FLAG(type, flag))
+#define FLAG_CLEAR(obj, type, flag)	((obj)->flags &= ~(FLAG(type, flag)))
+#define FLAG_FLIP(obj, type, flag)	((obj)->flags ^= FLAG(type, flag))
+#define FLAG_TEST(obj, type, flag)	(!!((obj)->flags & FLAG(type, flag)))
+
+/* Clock field state tests */
+
+#define gate_exists(gate)		FLAG_TEST(gate, GATE, EXISTS)
+#define gate_is_enabled(gate)		FLAG_TEST(gate, GATE, ENABLED)
+#define gate_is_hw_controllable(gate)	FLAG_TEST(gate, GATE, HW)
+#define gate_is_sw_controllable(gate)	FLAG_TEST(gate, GATE, SW)
+#define gate_is_sw_managed(gate)	FLAG_TEST(gate, GATE, SW_MANAGED)
+#define gate_is_no_disable(gate)	FLAG_TEST(gate, GATE, NO_DISABLE)
+
+#define gate_flip_enabled(gate)		FLAG_FLIP(gate, GATE, ENABLED)
+
+#define divider_exists(div)		FLAG_TEST(div, DIV, EXISTS)
+#define divider_is_fixed(div)		FLAG_TEST(div, DIV, FIXED)
+#define divider_has_fraction(div)	(!divider_is_fixed(div) && \
+						(div)->frac_width > 0)
+
+#define selector_exists(sel)		((sel)->width != 0)
+#define trigger_exists(trig)		FLAG_TEST(trig, TRIG, EXISTS)
+
+/* Clock type, used to tell common block what it's part of */
+enum bcm_clk_type {
+	bcm_clk_none,		/* undefined clock type */
+	bcm_clk_bus,
+	bcm_clk_core,
+	bcm_clk_peri
+};
+
+/*
+ * Gating control and status is managed by a 32-bit gate register.
+ *
+ * There are several types of gating available:
+ * - (no gate)
+ *     A clock with no gate is assumed to be always enabled.
+ * - hardware-only gating (auto-gating)
+ *     Enabling or disabling clocks with this type of gate is
+ *     managed automatically by the hardware. Such clocks can be
+ *     considered by the software to be enabled. The current status
+ *     of auto-gated clocks can be read from the gate status bit.
+ * - software-only gating
+ *     Auto-gating is not available for this type of clock.
+ *     Instead, software manages whether it's enabled by setting or
+ *     clearing the enable bit. The current gate status of a gate
+ *     under software control can be read from the gate status bit.
+ *     To ensure a change to the gating status is complete, the
+ *     status bit can be polled to verify that the gate has entered
+ *     the desired state.
+ * - selectable hardware or software gating
+ *     Gating for this type of clock can be configured to be either
+ *     under software or hardware control. Which type is in use is
+ *     determined by the hw_sw_sel bit of the gate register.
+ */
+struct bcm_clk_gate {
+	u32 offset;		/* gate register offset */
+	u32 status_bit;		/* 0: gate is disabled; 0: gatge is enabled */
+	u32 en_bit;		/* 0: disable; 1: enable */
+	u32 hw_sw_sel_bit;	/* 0: hardware gating; 1: software gating */
+	u32 flags;		/* BCM_CLK_GATE_FLAGS_* below */
+};
+
+/*
+ * Gate flags:
+ *   HW         means this gate can be auto-gated
+ *   SW         means the state of this gate can be software controlled
+ *   NO_DISABLE means this gate is (only) enabled if under software control
+ *   SW_MANAGED means the status of this gate is under software control
+ *   ENABLED    means this software-managed gate is *supposed* to be enabled
+ */
+#define BCM_CLK_GATE_FLAGS_EXISTS	((u32)1 << 0)	/* Gate is valid */
+#define BCM_CLK_GATE_FLAGS_HW		((u32)1 << 1)	/* Can auto-gate */
+#define BCM_CLK_GATE_FLAGS_SW		((u32)1 << 2)	/* Software control */
+#define BCM_CLK_GATE_FLAGS_NO_DISABLE	((u32)1 << 3)	/* HW or enabled */
+#define BCM_CLK_GATE_FLAGS_SW_MANAGED	((u32)1 << 4)	/* SW now in control */
+#define BCM_CLK_GATE_FLAGS_ENABLED	((u32)1 << 5)	/* If SW_MANAGED */
+
+/*
+ * Gate initialization macros.
+ *
+ * Any gate initially under software control will be enabled.
+ */
+
+/* A hardware/software gate initially under software control */
+#define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit)	\
+	{								\
+		.offset = (_offset),					\
+		.status_bit = (_status_bit),				\
+		.en_bit = (_en_bit),					\
+		.hw_sw_sel_bit = (_hw_sw_sel_bit),			\
+		.flags = FLAG(GATE, HW)|FLAG(GATE, SW)|			\
+			FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)|	\
+			FLAG(GATE, EXISTS),				\
+	}
+
+/* A hardware/software gate initially under hardware control */
+#define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit)	\
+	{								\
+		.offset = (_offset),					\
+		.status_bit = (_status_bit),				\
+		.en_bit = (_en_bit),					\
+		.hw_sw_sel_bit = (_hw_sw_sel_bit),			\
+		.flags = FLAG(GATE, HW)|FLAG(GATE, SW)|			\
+			FLAG(GATE, EXISTS),				\
+	}
+
+/* A hardware-or-enabled gate (enabled if not under hardware control) */
+#define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit)	\
+	{								\
+		.offset = (_offset),					\
+		.status_bit = (_status_bit),				\
+		.en_bit = (_en_bit),					\
+		.hw_sw_sel_bit = (_hw_sw_sel_bit),			\
+		.flags = FLAG(GATE, HW)|FLAG(GATE, SW)|			\
+			FLAG(GATE, NO_DISABLE)|FLAG(GATE, EXISTS),	\
+	}
+
+/* A software-only gate */
+#define SW_ONLY_GATE(_offset, _status_bit, _en_bit)			\
+	{								\
+		.offset = (_offset),					\
+		.status_bit = (_status_bit),				\
+		.en_bit = (_en_bit),					\
+		.flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)|		\
+			FLAG(GATE, ENABLED)|FLAG(GATE, EXISTS),		\
+	}
+
+/* A hardware-only gate */
+#define HW_ONLY_GATE(_offset, _status_bit)				\
+	{								\
+		.offset = (_offset),					\
+		.status_bit = (_status_bit),				\
+		.flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS),		\
+	}
+
+/*
+ * Each clock can have zero, one, or two dividers which change the
+ * output rate of the clock. Each divider can be either fixed or
+ * variable. If there are two dividers, they are the "pre-divider"
+ * and the "regular" or "downstream" divider. If there is only one,
+ * there is no pre-divider.
+ *
+ * A fixed divider is any non-zero (positive) value, and it
+ * indicates how the input rate is affected by the divider.
+ *
+ * The value of a variable divider is maintained in a sub-field of a
+ * 32-bit divider register. The position of the field in the
+ * register is defined by its offset and width. The value recorded
+ * in this field is always 1 less than the value it represents.
+ *
+ * In addition, a variable divider can indicate that some subset
+ * of its bits represent a "fractional" part of the divider. Such
+ * bits comprise the low-order portion of the divider field, and can
+ * be viewed as representing the portion of the divider that lies to
+ * the right of the decimal point. Most variable dividers have zero
+ * fractional bits. Variable dividers with non-zero fraction width
+ * still record a value 1 less than the value they represent; the
+ * added 1 does *not* affect the low-order bit in this case, it
+ * affects the bits above the fractional part only. (Often in this
+ * code a divider field value is distinguished from the value it
+ * represents by referring to the latter as a "divisor".)
+ *
+ * In order to avoid dealing with fractions, divider arithmetic is
+ * performed using "scaled" values. A scaled value is one that's
+ * been left-shifted by the fractional width of a divider. Dividing
+ * a scaled value by a scaled divisor produces the desired quotient
+ * without loss of precision and without any other special handling
+ * for fractions.
+ *
+ * The recorded value of a variable divider can be modified. To
+ * modify either divider (or both), a clock must be enabled (i.e.,
+ * using its gate). In addition, a trigger register (described
+ * below) must be used to commit the change, and polled to verify
+ * the change is complete.
+ */
+struct bcm_clk_div {
+	union {
+		struct {	/* variable divider */
+			u32 offset;	/* divider register offset */
+			u32 shift;	/* field shift */
+			u32 width;	/* field width */
+			u32 frac_width;	/* field fraction width */
+
+			u64 scaled_div;	/* scaled divider value */
+		};
+		u32 fixed;	/* non-zero fixed divider value */
+	};
+	u32 flags;		/* BCM_CLK_DIV_FLAGS_* below */
+};
+
+/*
+ * Divider flags:
+ *   EXISTS means this divider exists
+ *   FIXED means it is a fixed-rate divider
+ */
+#define BCM_CLK_DIV_FLAGS_EXISTS	((u32)1 << 0)	/* Divider is valid */
+#define BCM_CLK_DIV_FLAGS_FIXED		((u32)1 << 1)	/* Fixed-value */
+
+/* Divider initialization macros */
+
+/* A fixed (non-zero) divider */
+#define FIXED_DIVIDER(_value)						\
+	{								\
+		.fixed = (_value),					\
+		.flags = FLAG(DIV, EXISTS)|FLAG(DIV, FIXED),		\
+	}
+
+/* A divider with an integral divisor */
+#define DIVIDER(_offset, _shift, _width)				\
+	{								\
+		.offset = (_offset),					\
+		.shift = (_shift),					\
+		.width = (_width),					\
+		.scaled_div = BAD_SCALED_DIV_VALUE,			\
+		.flags = FLAG(DIV, EXISTS),				\
+	}
+
+/* A divider whose divisor has an integer and fractional part */
+#define FRAC_DIVIDER(_offset, _shift, _width, _frac_width)		\
+	{								\
+		.offset = (_offset),					\
+		.shift = (_shift),					\
+		.width = (_width),					\
+		.frac_width = (_frac_width),				\
+		.scaled_div = BAD_SCALED_DIV_VALUE,			\
+		.flags = FLAG(DIV, EXISTS),				\
+	}
+
+/*
+ * Clocks may have multiple "parent" clocks. If there is more than
+ * one, a selector must be specified to define which of the parent
+ * clocks is currently in use. The selected clock is indicated in a
+ * sub-field of a 32-bit selector register. The range of
+ * representable selector values typically exceeds the number of
+ * available parent clocks. Occasionally the reset value of a
+ * selector field is explicitly set to a (specific) value that does
+ * not correspond to a defined input clock.
+ *
+ * We register all known parent clocks with the common clock code
+ * using a packed array (i.e., no empty slots) of (parent) clock
+ * names, and refer to them later using indexes into that array.
+ * We maintain an array of selector values indexed by common clock
+ * index values in order to map between these common clock indexes
+ * and the selector values used by the hardware.
+ *
+ * Like dividers, a selector can be modified, but to do so a clock
+ * must be enabled, and a trigger must be used to commit the change.
+ */
+struct bcm_clk_sel {
+	u32 offset;		/* selector register offset */
+	u32 shift;		/* field shift */
+	u32 width;		/* field width */
+
+	u32 parent_count;	/* number of entries in parent_sel[] */
+	u32 *parent_sel;	/* array of parent selector values */
+	u8 clk_index;		/* current selected index in parent_sel[] */
+};
+
+/* Selector initialization macro */
+#define SELECTOR(_offset, _shift, _width)				\
+	{								\
+		.offset = (_offset),					\
+		.shift = (_shift),					\
+		.width = (_width),					\
+		.clk_index = BAD_CLK_INDEX,				\
+	}
+
+/*
+ * Making changes to a variable divider or a selector for a clock
+ * requires the use of a trigger. A trigger is defined by a single
+ * bit within a register. To signal a change, a 1 is written into
+ * that bit. To determine when the change has been completed, that
+ * trigger bit is polled; the read value will be 1 while the change
+ * is in progress, and 0 when it is complete.
+ *
+ * Occasionally a clock will have more than one trigger. In this
+ * case, the "pre-trigger" will be used when changing a clock's
+ * selector and/or its pre-divider.
+ */
+struct bcm_clk_trig {
+	u32 offset;		/* trigger register offset */
+	u32 bit;		/* trigger bit */
+	u32 flags;		/* BCM_CLK_TRIG_FLAGS_* below */
+};
+
+/*
+ * Trigger flags:
+ *   EXISTS means this trigger exists
+ */
+#define BCM_CLK_TRIG_FLAGS_EXISTS	((u32)1 << 0)	/* Trigger is valid */
+
+/* Trigger initialization macro */
+#define TRIGGER(_offset, _bit)						\
+	{								\
+		.offset = (_offset),					\
+		.bit = (_bit),						\
+		.flags = FLAG(TRIG, EXISTS),				\
+	}
+
+struct bus_clk_data {
+	struct bcm_clk_gate gate;
+};
+
+struct core_clk_data {
+	struct bcm_clk_gate gate;
+};
+
+struct peri_clk_data {
+	struct bcm_clk_gate gate;
+	struct bcm_clk_trig pre_trig;
+	struct bcm_clk_div pre_div;
+	struct bcm_clk_trig trig;
+	struct bcm_clk_div div;
+	struct bcm_clk_sel sel;
+	const char *clocks[];	/* must be last; use CLOCKS() to declare */
+};
+#define CLOCKS(...)	{ __VA_ARGS__, NULL, }
+#define NO_CLOCKS	{ NULL, }	/* Must use of no parent clocks */
+
+struct refclk {
+	struct clk clk;
+};
+
+struct peri_clock {
+	struct clk clk;
+	struct peri_clk_data *data;
+};
+
+struct ccu_clock {
+	struct clk clk;
+
+	int num_policy_masks;
+	unsigned long policy_freq_offset;
+	int freq_bit_shift;	/* 8 for most CCUs */
+	unsigned long policy_ctl_offset;
+	unsigned long policy0_mask_offset;
+	unsigned long policy1_mask_offset;
+	unsigned long policy2_mask_offset;
+	unsigned long policy3_mask_offset;
+	unsigned long policy0_mask2_offset;
+	unsigned long policy1_mask2_offset;
+	unsigned long policy2_mask2_offset;
+	unsigned long policy3_mask2_offset;
+	unsigned long lvm_en_offset;
+
+	int freq_id;
+	unsigned long *freq_tbl;
+};
+
+struct bus_clock {
+	struct clk clk;
+	struct bus_clk_data *data;
+	unsigned long *freq_tbl;
+};
+
+struct ref_clock {
+	struct clk clk;
+};
+
+static inline int is_same_clock(struct clk *a, struct clk *b)
+{
+	return a == b;
+}
+
+#define to_clk(p) (&((p)->clk))
+#define name_to_clk(name) (&((name##_clk).clk))
+/* declare a struct clk_lookup */
+#define CLK_LK(name) \
+{.con_id = __stringify(name##_clk), .clk = name_to_clk(name),}
+
+static inline struct refclk *to_refclk(struct clk *clock)
+{
+	return container_of(clock, struct refclk, clk);
+}
+
+static inline struct peri_clock *to_peri_clk(struct clk *clock)
+{
+	return container_of(clock, struct peri_clock, clk);
+}
+
+static inline struct ccu_clock *to_ccu_clk(struct clk *clock)
+{
+	return container_of(clock, struct ccu_clock, clk);
+}
+
+static inline struct bus_clock *to_bus_clk(struct clk *clock)
+{
+	return container_of(clock, struct bus_clock, clk);
+}
+
+static inline struct ref_clock *to_ref_clk(struct clk *clock)
+{
+	return container_of(clock, struct ref_clock, clk);
+}
+
+extern struct clk_ops peri_clk_ops;
+extern struct clk_ops ccu_clk_ops;
+extern struct clk_ops bus_clk_ops;
+extern struct clk_ops ref_clk_ops;
+
+int clk_get_and_enable(char *clkstr);

arch/arm/cpu/armv7/bcm235xx/clk-eth.c

@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Broadcom Corporation.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+#define WR_ACCESS_ADDR			ESUB_CLK_BASE_ADDR
+#define WR_ACCESS_PASSWORD				0xA5A500
+
+#define PLLE_POST_RESETB_ADDR		(ESUB_CLK_BASE_ADDR + 0x00000C00)
+
+#define PLLE_RESETB_ADDR		(ESUB_CLK_BASE_ADDR + 0x00000C58)
+#define PLLE_RESETB_I_PLL_RESETB_PLLE_MASK		0x00010000
+#define PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK	0x00000001
+
+#define PLL_LOCK_ADDR			(ESUB_CLK_BASE_ADDR + 0x00000C38)
+#define PLL_LOCK_PLL_LOCK_PLLE_MASK			0x00000001
+
+#define ESW_SYS_DIV_ADDR		(ESUB_CLK_BASE_ADDR + 0x00000A04)
+#define ESW_SYS_DIV_PLL_SELECT_MASK			0x00000300
+#define ESW_SYS_DIV_DIV_MASK				0x0000001C
+#define ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT		0x00000100
+#define ESW_SYS_DIV_DIV_SELECT				0x4
+#define ESW_SYS_DIV_TRIGGER_MASK			0x00000001
+
+#define ESUB_AXI_DIV_DEBUG_ADDR		(ESUB_CLK_BASE_ADDR + 0x00000E04)
+#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK		0x0000001C
+#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK	0x00000040
+#define ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT	0x0
+#define ESUB_AXI_DIV_DEBUG_TRIGGER_MASK			0x00000001
+
+#define PLL_MAX_RETRY	100
+
+/* Enable appropriate clocks for Ethernet */
+int clk_eth_enable(void)
+{
+	int rc = -1;
+	int retry_count = 0;
+	rc = clk_get_and_enable("esub_ccu_clk");
+
+	/* Enable Access to CCU registers */
+	writel((1 | WR_ACCESS_PASSWORD), WR_ACCESS_ADDR);
+
+	writel(readl(PLLE_POST_RESETB_ADDR) &
+	       ~PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
+	       PLLE_POST_RESETB_ADDR);
+
+	/* Take PLL out of reset and put into normal mode */
+	writel(readl(PLLE_RESETB_ADDR) | PLLE_RESETB_I_PLL_RESETB_PLLE_MASK,
+	       PLLE_RESETB_ADDR);
+
+	/* Wait for PLL lock */
+	rc = -1;
+	while (retry_count < PLL_MAX_RETRY) {
+		udelay(100);
+		if (readl(PLL_LOCK_ADDR) & PLL_LOCK_PLL_LOCK_PLLE_MASK) {
+			rc = 0;
+			break;
+		}
+		retry_count++;
+	}
+
+	if (rc == -1) {
+		printf("%s: ETH-PLL lock timeout, Ethernet is not enabled!\n",
+		       __func__);
+		return -1;
+	}
+
+	writel(readl(PLLE_POST_RESETB_ADDR) |
+	       PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
+	       PLLE_POST_RESETB_ADDR);
+
+	/* Switch esw_sys_clk to use 104MHz(208MHz/2) clock */
+	writel((readl(ESW_SYS_DIV_ADDR) &
+		~(ESW_SYS_DIV_PLL_SELECT_MASK | ESW_SYS_DIV_DIV_MASK)) |
+	       ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT | ESW_SYS_DIV_DIV_SELECT,
+	       ESW_SYS_DIV_ADDR);
+
+	writel(readl(ESW_SYS_DIV_ADDR) | ESW_SYS_DIV_TRIGGER_MASK,
+	       ESW_SYS_DIV_ADDR);
+
+	/* Wait for trigger complete */
+	rc = -1;
+	retry_count = 0;
+	while (retry_count < PLL_MAX_RETRY) {
+		udelay(100);
+		if (!(readl(ESW_SYS_DIV_ADDR) & ESW_SYS_DIV_TRIGGER_MASK)) {
+			rc = 0;
+			break;
+		}
+		retry_count++;
+	}
+
+	if (rc == -1) {
+		printf("%s: SYS CLK Trigger timeout, Ethernet is not enabled!\n",
+		       __func__);
+		return -1;
+	}
+
+	/* switch Esub AXI clock to 208MHz */
+	writel((readl(ESUB_AXI_DIV_DEBUG_ADDR) &
+		~(ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK |
+		  ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK |
+		  ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) |
+	       ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT |
+	       ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK,
+	       ESUB_AXI_DIV_DEBUG_ADDR);
+
+	writel(readl(ESUB_AXI_DIV_DEBUG_ADDR) |
+	       ESUB_AXI_DIV_DEBUG_TRIGGER_MASK,
+	       ESUB_AXI_DIV_DEBUG_ADDR);
+
+	/* Wait for trigger complete */
+	rc = -1;
+	retry_count = 0;
+	while (retry_count < PLL_MAX_RETRY) {
+		udelay(100);
+		if (!(readl(ESUB_AXI_DIV_DEBUG_ADDR) &
+		      ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) {
+			rc = 0;
+			break;
+		}
+		retry_count++;
+	}
+
+	if (rc == -1) {
+		printf("%s: AXI CLK Trigger timeout, Ethernet is not enabled!\n",
+		       __func__);
+		return -1;
+	}
+
+	/* Disable Access to CCU registers */
+	writel(WR_ACCESS_PASSWORD, WR_ACCESS_ADDR);
+
+	return rc;
+}

arch/arm/cpu/armv7/bcm235xx/clk-sdio.c

@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013 Broadcom Corporation.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+/* Enable appropriate clocks for an SDIO port */
+int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep)
+{
+	int ret;
+	struct clk *c;
+
+	char *clkstr;
+	char *slpstr;
+	char *ahbstr;
+
+	switch ((u32) base) {
+	case CONFIG_SYS_SDIO_BASE0:
+		clkstr = CONFIG_SYS_SDIO0 "_clk";
+		ahbstr = CONFIG_SYS_SDIO0 "_ahb_clk";
+		slpstr = CONFIG_SYS_SDIO0 "_sleep_clk";
+		break;
+	case CONFIG_SYS_SDIO_BASE1:
+		clkstr = CONFIG_SYS_SDIO1 "_clk";
+		ahbstr = CONFIG_SYS_SDIO1 "_ahb_clk";
+		slpstr = CONFIG_SYS_SDIO1 "_sleep_clk";
+		break;
+	case CONFIG_SYS_SDIO_BASE2:
+		clkstr = CONFIG_SYS_SDIO2 "_clk";
+		ahbstr = CONFIG_SYS_SDIO2 "_ahb_clk";
+		slpstr = CONFIG_SYS_SDIO2 "_sleep_clk";
+		break;
+	case CONFIG_SYS_SDIO_BASE3:
+		clkstr = CONFIG_SYS_SDIO3 "_clk";
+		ahbstr = CONFIG_SYS_SDIO3 "_ahb_clk";
+		slpstr = CONFIG_SYS_SDIO3 "_sleep_clk";
+		break;
+	default:
+		printf("%s: base 0x%p not found\n", __func__, base);
+		return -EINVAL;
+	}
+
+	ret = clk_get_and_enable(ahbstr);
+	if (ret)
+		return ret;
+
+	ret = clk_get_and_enable(slpstr);
+	if (ret)
+		return ret;
+
+	c = clk_get(clkstr);
+	if (c) {
+		ret = clk_set_rate(c, rate);
+		if (ret)
+			return ret;
+
+		ret = clk_enable(c);
+		if (ret)
+			return ret;
+	} else {
+		printf("%s: Couldn't find %s\n", __func__, clkstr);
+		return -EINVAL;
+	}
+	*actual_ratep = rate;
+	return 0;
+}

arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c

@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Broadcom Corporation.
+ */
+
+#include <common.h>
+#include <linux/errno.h>
+#include <asm/arch/sysmap.h>
+#include "clk-core.h"
+
+/* Enable appropriate clocks for the USB OTG port */
+int clk_usb_otg_enable(void *base)
+{
+	char *ahbstr;
+
+	switch ((u32) base) {
+	case HSOTG_BASE_ADDR:
+		ahbstr = "usb_otg_ahb_clk";
+		break;
+	default:
+		printf("%s: base 0x%p not found\n", __func__, base);
+		return -EINVAL;
+	}
+
+	return clk_get_and_enable(ahbstr);
+}

arch/arm/cpu/armv7/bcm281xx/Makefile

@@ -7,4 +7,5 @@ obj-y	+= clk-core.o
 obj-y	+= clk-bcm281xx.o
 obj-y	+= clk-sdio.o
 obj-y	+= clk-bsc.o
+obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
 obj-y	+= clk-usb-otg.o

arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c

@@ -9,6 +9,7 @@
  *
  */
 
+#include <common.h>
 #include <asm/io.h>
 #include <linux/errno.h>
 #include <asm/arch/sysmap.h>
@@ -307,6 +308,27 @@ static struct ccu_clock kps_ccu_clk = {
 	.freq_tbl = slave_axi_freq_tbl,
 };
 
+#ifdef CONFIG_BCM_SF2_ETH
+static struct ccu_clock esub_ccu_clk = {
+	.clk = {
+		.name = "esub_ccu_clk",
+		.ops = &ccu_clk_ops,
+		.ccu_clk_mgr_base = ESUB_CLK_BASE_ADDR,
+	},
+	.num_policy_masks = 1,
+	.policy_freq_offset = 0x00000008,
+	.freq_bit_shift = 8,
+	.policy_ctl_offset = 0x0000000c,
+	.policy0_mask_offset = 0x00000010,
+	.policy1_mask_offset = 0x00000014,
+	.policy2_mask_offset = 0x00000018,
+	.policy3_mask_offset = 0x0000001c,
+	.lvm_en_offset = 0x00000034,
+	.freq_id = 2,
+	.freq_tbl = esub_freq_tbl,
+};
+#endif
+
 /*
  * Bus clocks
  */
@@ -541,6 +563,9 @@ struct clk_lookup arch_clk_tbl[] = {
 	CLK_LK(bsc1_apb),
 	CLK_LK(bsc2_apb),
 	CLK_LK(bsc3_apb),
+#ifdef CONFIG_BCM_SF2_ETH
+	CLK_LK(esub_ccu),
+#endif
 };
 
 /* public array size */

arch/arm/cpu/armv7/bcm281xx/clk-bsc.c

@@ -3,6 +3,7 @@
  * Copyright 2013 Broadcom Corporation.
  */
 
+#include <common.h>
 #include <asm/io.h>
 #include <linux/errno.h>
 #include <asm/arch/sysmap.h>

arch/arm/cpu/armv7/bcm281xx/clk-core.c

@@ -9,6 +9,7 @@
  *
  */
 
+#include <common.h>
 #include <log.h>
 #include <asm/io.h>
 #include <linux/delay.h>
@@ -84,6 +85,7 @@ static int peri_clk_enable(struct clk *c, int enable)
 	struct bcm_clk_gate *gate = &cd->gate;
 	void *base = (void *)c->ccu_clk_mgr_base;
 
+
 	debug("%s: %s\n", __func__, c->name);
 
 	clk_get_rate(c);	/* Make sure rate and sel are filled in */

arch/arm/cpu/armv7/bcm281xx/clk-eth.c

@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Broadcom Corporation.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+#define WR_ACCESS_ADDR			ESUB_CLK_BASE_ADDR
+#define WR_ACCESS_PASSWORD				0xA5A500
+
+#define PLLE_POST_RESETB_ADDR		(ESUB_CLK_BASE_ADDR + 0x00000C00)
+
+#define PLLE_RESETB_ADDR		(ESUB_CLK_BASE_ADDR + 0x00000C58)
+#define PLLE_RESETB_I_PLL_RESETB_PLLE_MASK		0x00010000
+#define PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK	0x00000001
+
+#define PLL_LOCK_ADDR			(ESUB_CLK_BASE_ADDR + 0x00000C38)
+#define PLL_LOCK_PLL_LOCK_PLLE_MASK			0x00000001
+
+#define ESW_SYS_DIV_ADDR		(ESUB_CLK_BASE_ADDR + 0x00000A04)
+#define ESW_SYS_DIV_PLL_SELECT_MASK			0x00000300
+#define ESW_SYS_DIV_DIV_MASK				0x0000001C
+#define ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT		0x00000100
+#define ESW_SYS_DIV_DIV_SELECT				0x4
+#define ESW_SYS_DIV_TRIGGER_MASK			0x00000001
+
+#define ESUB_AXI_DIV_DEBUG_ADDR		(ESUB_CLK_BASE_ADDR + 0x00000E04)
+#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK		0x0000001C
+#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK	0x00000040
+#define ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT	0x0
+#define ESUB_AXI_DIV_DEBUG_TRIGGER_MASK			0x00000001
+
+#define PLL_MAX_RETRY	100
+
+/* Enable appropriate clocks for Ethernet */
+int clk_eth_enable(void)
+{
+	int rc = -1;
+	int retry_count = 0;
+	rc = clk_get_and_enable("esub_ccu_clk");
+
+	/* Enable Access to CCU registers */
+	writel((1 | WR_ACCESS_PASSWORD), WR_ACCESS_ADDR);
+
+	writel(readl(PLLE_POST_RESETB_ADDR) &
+	       ~PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
+	       PLLE_POST_RESETB_ADDR);
+
+	/* Take PLL out of reset and put into normal mode */
+	writel(readl(PLLE_RESETB_ADDR) | PLLE_RESETB_I_PLL_RESETB_PLLE_MASK,
+	       PLLE_RESETB_ADDR);
+
+	/* Wait for PLL lock */
+	rc = -1;
+	while (retry_count < PLL_MAX_RETRY) {
+		udelay(100);
+		if (readl(PLL_LOCK_ADDR) & PLL_LOCK_PLL_LOCK_PLLE_MASK) {
+			rc = 0;
+			break;
+		}
+		retry_count++;
+	}
+
+	if (rc == -1) {
+		printf("%s: ETH-PLL lock timeout, Ethernet is not enabled!\n",
+		       __func__);
+		return -1;
+	}
+
+	writel(readl(PLLE_POST_RESETB_ADDR) |
+	       PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
+	       PLLE_POST_RESETB_ADDR);
+
+	/* Switch esw_sys_clk to use 104MHz(208MHz/2) clock */
+	writel((readl(ESW_SYS_DIV_ADDR) &
+		~(ESW_SYS_DIV_PLL_SELECT_MASK | ESW_SYS_DIV_DIV_MASK)) |
+	       ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT | ESW_SYS_DIV_DIV_SELECT,
+	       ESW_SYS_DIV_ADDR);
+
+	writel(readl(ESW_SYS_DIV_ADDR) | ESW_SYS_DIV_TRIGGER_MASK,
+	       ESW_SYS_DIV_ADDR);
+
+	/* Wait for trigger complete */
+	rc = -1;
+	retry_count = 0;
+	while (retry_count < PLL_MAX_RETRY) {
+		udelay(100);
+		if (!(readl(ESW_SYS_DIV_ADDR) & ESW_SYS_DIV_TRIGGER_MASK)) {
+			rc = 0;
+			break;
+		}
+		retry_count++;
+	}
+
+	if (rc == -1) {
+		printf("%s: SYS CLK Trigger timeout, Ethernet is not enabled!\n",
+		       __func__);
+		return -1;
+	}
+
+	/* switch Esub AXI clock to 208MHz */
+	writel((readl(ESUB_AXI_DIV_DEBUG_ADDR) &
+		~(ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK |
+		  ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK |
+		  ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) |
+	       ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT |
+	       ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK,
+	       ESUB_AXI_DIV_DEBUG_ADDR);
+
+	writel(readl(ESUB_AXI_DIV_DEBUG_ADDR) |
+	       ESUB_AXI_DIV_DEBUG_TRIGGER_MASK,
+	       ESUB_AXI_DIV_DEBUG_ADDR);
+
+	/* Wait for trigger complete */
+	rc = -1;
+	retry_count = 0;
+	while (retry_count < PLL_MAX_RETRY) {
+		udelay(100);
+		if (!(readl(ESUB_AXI_DIV_DEBUG_ADDR) &
+		      ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) {
+			rc = 0;
+			break;
+		}
+		retry_count++;
+	}
+
+	if (rc == -1) {
+		printf("%s: AXI CLK Trigger timeout, Ethernet is not enabled!\n",
+		       __func__);
+		return -1;
+	}
+
+	/* Disable Access to CCU registers */
+	writel(WR_ACCESS_PASSWORD, WR_ACCESS_ADDR);
+
+	return rc;
+}

arch/arm/cpu/armv7/bcm281xx/clk-sdio.c

@@ -3,6 +3,7 @@
  * Copyright 2013 Broadcom Corporation.
  */
 
+#include <common.h>
 #include <asm/io.h>
 #include <linux/errno.h>
 #include <asm/arch/sysmap.h>

arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c

@@ -3,6 +3,7 @@
  * Copyright 2014 Broadcom Corporation.
  */
 
+#include <common.h>
 #include <linux/errno.h>
 #include <asm/arch/sysmap.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm281xx/reset.c

@@ -3,6 +3,7 @@
  * Copyright 2013 Broadcom Corporation.
  */
 
+#include <common.h>
 #include <cpu_func.h>
 #include <asm/io.h>
 #include <asm/arch/sysmap.h>

arch/arm/cpu/armv7/bcmcygnus/reset.c

@@ -3,6 +3,7 @@
  * Copyright 2014 Broadcom Corporation.
  */
 
+#include <common.h>
 #include <cpu_func.h>
 #include <asm/io.h>
 

arch/arm/cpu/armv7/bcmnsp/reset.c

@@ -3,6 +3,7 @@
  * Copyright 2014 Broadcom Corporation.
  */
 
+#include <common.h>
 #include <cpu_func.h>
 #include <asm/io.h>
 

arch/arm/cpu/armv7/cache_v7.c

@@ -6,8 +6,8 @@
  */
 #include <cpu_func.h>
 #include <asm/cache.h>
-#include <linux/errno.h>
 #include <linux/types.h>
+#include <common.h>
 #include <asm/armv7.h>
 #include <asm/utils.h>
 
@@ -210,8 +210,3 @@ __weak void v7_outer_cache_flush_all(void) {}
 __weak void v7_outer_cache_inval_all(void) {}
 __weak void v7_outer_cache_flush_range(u32 start, u32 end) {}
 __weak void v7_outer_cache_inval_range(u32 start, u32 end) {}
-
-int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm)
-{
-	return -ENOSYS;
-}

arch/arm/cpu/armv7/cp15.c

@@ -7,6 +7,7 @@
  * CP15 specific code
  */
 
+#include <common.h>
 #include <command.h>
 #include <asm/system.h>
 #include <asm/cache.h>

arch/arm/cpu/armv7/cpu.c

@@ -14,6 +14,7 @@
  * CPU specific code
  */
 
+#include <common.h>
 #include <command.h>
 #include <cpu_func.h>
 #include <irq_func.h>
@@ -32,7 +33,7 @@ int cleanup_before_linux_select(int flags)
 	 *
 	 * we turn off caches etc ...
 	 */
-#ifndef CONFIG_XPL_BUILD
+#ifndef CONFIG_SPL_BUILD
 	disable_interrupts();
 #endif
 

arch/arm/cpu/armv7/exception_level.c

@@ -8,12 +8,13 @@
  * secure mode before booting an operating system.
  */
 
+#include <common.h>
 #include <bootm.h>
 #include <cpu_func.h>
 #include <log.h>
-#include <setjmp.h>
 #include <asm/armv7.h>
 #include <asm/secure.h>
+#include <asm/setjmp.h>
 
 /**
  * entry_non_secure() - entry point when switching to non-secure mode
@@ -24,7 +25,7 @@
  *
  * @non_secure_jmp:	jump buffer for restoring stack and registers
  */
-static void entry_non_secure(jmp_buf non_secure_jmp)
+static void entry_non_secure(struct jmp_buf_data *non_secure_jmp)
 {
 	dcache_enable();
 	debug("Reached non-secure mode\n");
@@ -42,10 +43,10 @@ static void entry_non_secure(jmp_buf non_secure_jmp)
 void switch_to_non_secure_mode(void)
 {
 	static bool is_nonsec;
-	jmp_buf non_secure_jmp;
+	struct jmp_buf_data non_secure_jmp;
 
 	if (armv7_boot_nonsec() && !is_nonsec) {
-		if (setjmp(non_secure_jmp))
+		if (setjmp(&non_secure_jmp))
 			return;
 		dcache_disable();	/* flush cache before switch to HYP */
 		armv7_init_nonsec();