Prepare 2009.03

Update CHANGELOG Signed-off-by: Wolfgang Denk <wd@denx.de>
Replaced endpoint numbers with appropriate macros in usbtty.c.
2026-06-04 02:36:38 +03:00 · 2009-03-21 22:04:41 +01:00 · 2009-03-21 10:40:24 +01:00 · 2009-03-20 22:37:38 +01:00 · 2009-03-20 22:16:36 +01:00 · 2009-03-20 12:58:31 +01:00
57 changed files with 1028 additions and 528 deletions
--- a/339
+++ b/339
@@ -1,3 +1,342 @@
+commit 9e78dae2b276c5bf9ab92cd85173f6cb92b1b7d5
+Author: Vivek Kutal <vivek.kutal@azingo.com>
+Date:	Mon Feb 23 21:35:11 2009 +0530
+
+    Replaced endpoint numbers with appropriate macros in usbtty.c.
+
+    Signed-off-by: Vivek Kutal <vivek.kutal@azingo.com>
+    Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit a43ea5cc6d612471fbc74f0a26b2bea5864aa1d6
+Author: Jon Smirl <jonsmirl@gmail.com>
+Date:	Thu Mar 19 23:04:18 2009 -0400
+
+    .gitignore for generated files in api_examples directory
+
+    Add .gitignore for generated files in api_examples directory
+
+    Signed-off-by: Jon Smirl <jonsmirl@gmail.com>
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 40281a9ca21a6b6d7b996b4d4eeaa19026337231
+Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+Date:	Wed Mar 18 12:27:04 2009 +0900
+
+    net: sh_eth: Remove sh_eth_reset() from halt function
+
+    sh_eth_reset is function to reset Ether IP.
+    The MAC address is stored in IP, but it is initialized by this function.
+    OS (e.g. Linux Kernel) can not use this device when initialized.
+    This revises this problem.
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+
+commit f8853d105da7d69bc92a5b4578f9b85234e558ec
+Author: Anatolij Gustschin <agust@denx.de>
+Date:	Fri Mar 20 12:45:50 2009 +0100
+
+    ppc4xx: Fix bug in PCI outbound map configuration for canyonlands
+
+    PCI outbound address map configuration doesn't match the
+    PCI memory address range covered by appropriate TLB entry
+    configuration for canyonlands causing machine check
+    exceptions while accessing PCI memory regions. This patch
+    provides a fix for this issue.
+
+    Kazuaki Ichinohe observed and reported this issue while
+    testing display output with PCI ATI video card on canyonlands.
+
+    Signed-off-by: Anatolij Gustschin <agust@denx.de>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 7a88601a34132548c3c591ea87ab3468b51121b0
+Author: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+Date:	Fri Mar 6 10:09:37 2009 -0500
+
+    CFI: geometry reversal for STMicro M29W320DT
+
+    Follow up to the flash_fixup_stm to fix geometry reversal
+    on STMicro M29W320ET flash chip. The M29W320DT has 4 erase region.
+
+    Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 069f4364d807d7fdea3de7385ad2f8d83c587aec
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Wed Feb 25 17:29:40 2009 -0500
+
+    smc911x_eeprom: update register API
+
+    The smc911x driver changed the naming convention for its register funcs,
+    so update the eeprom code accordingly.
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+    CC: Ben Warren <biggerbadderben@gmail.com>
+
+commit 6a397ef0e6c58caab8bf427d447714bc9b3bb9d4
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date:	Tue Mar 17 10:06:39 2009 +0100
+
+    mpc52xx: Get rid of board-specific #ifdef's in cpu/mpc5xxx/ide.c
+
+    Total5200 and digsy MTC use I2C port 2 pins as a ATA chip select.
+    To avoid adding board-specific ifdefs to cpu/mpc5xxx/ide.c new
+    define CONFIG_SYS_ATA_CS_ON_I2C2 was introduced. It is used by
+    Total5200 and will be used by digsy MTC and other boards with
+    ATA CS on I2C pins.
+
+    Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit 1b6275dfb173bd2edb8f208dd050d6f47ae39654
+Author: Heiko Schocher <hs@denx.de>
+Date:	Thu Mar 12 07:37:34 2009 +0100
+
+    8xx: add support for new keymile kmsupx4 board.
+
+    This patch adds support for the kmsupx4 board from Keymile,
+    based on a Freescale MPC852T CPU
+
+    - serial console on SMC1
+    - 32 MB SDRAM
+    - 32 MB NOR Flash
+    - Ethernet over SCC3
+    - I2C Bitbang
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit d044954fe2a7e7a3dd104eb9c9d2104e38da2911
+Author: Heiko Schocher <hs@denx.de>
+Date:	Thu Mar 12 07:37:28 2009 +0100
+
+    8xx, mgsuvd: rename board to a more generic name
+
+    renaming the "mgsuvd" board port into "km8xx", because
+    there come more similar boards from keymile.
+    Compiling the mgsuvd board with "make mgsuvd_config"
+    remains.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 18b2f35bde1672e074a3d5048383cb56fda745cb
+Author: Heiko Schocher <hs@denx.de>
+Date:	Thu Mar 12 07:37:23 2009 +0100
+
+    8xx, mgsuvd: Coding Style cleanup config file
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 364123db6730d32330f818b65360d2cd27396667
+Author: Heiko Schocher <hs@denx.de>
+Date:	Thu Mar 12 07:37:18 2009 +0100
+
+    powerpc: common updates for keymile boards
+
+    - added to keymile-common.h:
+      - bootcount support
+      - COMMAND HISTORY
+      - CONFIG_AUTO_COMPLETE
+      - CONFIG_SYS_FLASH_PROTECTION
+      - JFFS2 support
+      - CONFIG_VERSION_VARIABLE
+    - extracted common I2C settings for all boards
+    - common default environment settings summarized
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 506f391888b82d1b83bdd749c3cea9eb2fd64df8
+Author: Heiko Schocher <hs@denx.de>
+Date:	Thu Mar 12 07:37:15 2009 +0100
+
+    8xx, icache: enabling ICache not before running from RAM
+
+    with the new CONFIG_SYS_DELAYED_ICACHE config option, ICache
+    is not enabled before code runs from RAM.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit cabf7b9c83bd780a5805ddbb4c0ce431d5b9f9f3
+Author: Heiko Schocher <hs@denx.de>
+Date:	Thu Mar 12 07:37:11 2009 +0100
+
+    82xx, mgcoge: fix environment sector size
+
+    Size of one environment sector is 0x20000.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 27057d416c7cc9eb1860953da8836352c07f13e9
+Author: Ladislav Michl <ladis@linux-mips.org>
+Date:	Mon Mar 16 23:27:31 2009 +0100
+
+    NetStar: config reindentation
+
+    Fix indentation broken by symbol renames. "Sort" driver related definitons.
+
+    Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
+
+commit 8d8235f84d3ef3f29b7d14e741369b5824b5bb4a
+Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Date:	Tue Mar 17 11:21:43 2009 +0000
+
+    ColdFire: Fix incorrect definition
+
+    Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+
+commit 9017d9325a5067b2ab0d70a2d3c907620c9ab7f8
+Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Date:	Mon Mar 2 19:16:45 2009 +0000
+
+    ColdFire: Fix M5329EVB and M5373EVB nand issue
+
+    The Nand flash was unable to read and write properly
+    due to Nand Chip Select (nCE) setup was in reverse
+    order. Also, increase the Nand time out value to 60.
+
+    Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+
+commit 42b68af1062f75bb4a91cf47e329a7e8100cd815
+Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Date:	Tue Jan 27 15:19:35 2009 +0000
+
+    ColdFire: PLATFORM_CPPFLAGS updates for new compiler
+
+    Update PLATFORM_CPPFLAGS to accept 4.3.x version of
+    ColdFire compiler.
+
+    Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+
+commit d6e4baf49987fc6f75e8574c0c27301a828b3132
+Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Date:	Tue Jan 27 12:57:47 2009 +0000
+
+    ColdFire: Provide gzip image size V2 & V3 platforms
+
+    Default gzip bootm size is 8MB. Some platforms require
+    more than 8MB
+
+    Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+
+commit c3a9e6374210679a81f611c1bcf968988bc20e41
+Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Date:	Wed Feb 18 11:49:31 2009 +0000
+
+    ColdFire: Fix M54451 serial boot dram setup
+
+    The serial boot dram extended/standard mode register was not
+    setup and was using default DRAM setup causing the U-boot was
+    unstable to boot up in serial mode.
+
+    Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+
+commit 32d11d58159a575f08a982cad8a5a941ffe5cc3d
+Author: arun c <arun.edarath@gmail.com>
+Date:	Thu Dec 4 15:57:15 2008 +0530
+
+    Coldfire: XL Bus minor fixes
+
+    According to coldfire manual data timeout > address time out
+    also use correct macro to program XARB_CFG
+
+    Signed-off-by: Arun C <arunedarath@mistralsolutions.com>
+
+commit 65d8bc94d8214812ccdf3372d3fef845cf4ec2e5
+Author: Scott Wood <scottwood@freescale.com>
+Date:	Tue Mar 17 12:06:04 2009 -0500
+
+    NAND: Have nboot accept .e and .i as legacy no-ops.
+
+    This was intended to happen before, but a trivial bug prevented it.
+
+    Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 0987505540918b2464b73069af3a5b766dbd3ceb
+Author: Ladislav Michl <ladis@linux-mips.org>
+Date:	Fri Mar 13 14:38:19 2009 +0100
+
+    NAND: Make nboot skip bad blocks
+
+    nboot command currently does not skip bad blocks and gives read error when
+    loading image stored over bad block. With patch applied, nboot works as
+    expected:
+
+    Device 0 bad blocks:
+      00780000
+      014a0000
+      02000000
+      02cc0000
+      04aa0000
+
+    Loading from NAND 128MiB 3,3V 8-bit, offset 0x2c00000
+       Image Name:   Linux-2.6.22-omap1
+       Created:      2008-11-20  23:44:32 UTC
+       Image Type:   ARM Linux Kernel Image (uncompressed)
+       Data Size:    1052520 Bytes =  1 MB
+       Load Address: 10008000
+       Entry Point:  10008000
+    Skipping bad block 0x02cc0000
+    Automatic boot of image at addr 0x10400000 ...
+    ...
+
+    Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
+    Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 0b2f38fe3c4555dd2b81c69880403c13ad723153
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Mar 12 07:27:25 2009 +0100
+
+    ppc4xx: lwmon5: Only use one CS (rank) in DDR2 configuration
+
+    This patch fixes a problem spotted by Mikhail Zolotaryov on Sequoia with
+    the DDR2 configuration to only use one CS (rank). As this code is most
+    likely copied from the original Sequoia version, this error was copied
+    as well.
+
+    This patch also removes some dead code.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 9199b9cc8f56aca26504b48cf702176208f46e54
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Mar 12 07:24:40 2009 +0100
+
+    ppc4xx: PMC440: Only use one CS (rank) in DDR2 configuration
+
+    This patch fixes a problem spotted by Mikhail Zolotaryov on Sequoia with
+    the DDR2 configuration to only use one CS (rank). As this code is most
+    likely copied from the original Sequoia version, this error was copied
+    as well.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit ee86fd15e1ccda4be41f1dba82b8c9efea9a3145
+Author: Mikhail Zolotaryov <lebon@lebon.org.ua>
+Date:	Wed Mar 11 10:54:46 2009 +0200
+
+    Fix AMCC Sequoia board DDR memory configuration
+
+    Sequoia board schematics (DES0211_11_SCH_11.pdf, page 5, unit U1D)
+    specifies that BankSel#1 is not connected, while bootloader memory
+    configuration is (board/amcc/sequoia/sdram.c):
+	   mtsdram(DDR0_10, 0x00000300);
+    i.e. both Chip Selects used - not correct.
+
+    If we change to correct value here:
+	   mtsdram(DDR0_10, 0x00000100);
+    memory is accessible OK also.
+
+    Signed-off-by: Mikhail Zolotaryov <lebon@lebon.org.ua>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit b3dd629e78870ba2dc9f8032978721c0fa02a856
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Sun Mar 15 22:40:09 2009 +0100
+
+    Prepare 2009.03-rc2
+
+    Update CHANEGLOG, fix minor coding style issue.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
 commit 394d30dd1ee23b80fd5e59e17ebe0feca927ab31
 Author: Jerry Van Baren <gvb.uboot@gmail.com>
 Date:	Fri Mar 13 11:40:10 2009 -0400
--- a/1
+++ b/1
@@ -380,6 +380,7 @@ Heiko Schocher <hs@denx.de>
 	ids8247		MPC8247
 	jupiter		MPC5200
 	kmeter1		MPC8360
+	kmsupx4		MPC852T
 	mgcoge		MPC8247
 	mgsuvd		MPC852
 	mucmc52		MPC5200
--- a/1
+++ b/1
@@ -117,6 +117,7 @@ LIST_8xx="		\
 	KUP4X		\
 	LANTEC		\
 	lwmon		\
+	kmsupx4		\
 	MBX		\
 	MBX860T		\
 	mgsuvd		\
--- a/7
+++ b/7
@@ -24,7 +24,7 @@
 VERSION = 2009
 PATCHLEVEL = 03
 SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION =
 ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 else
@@ -921,6 +921,9 @@ IVMS8_config:	unconfig
 		 }
 	@$(MKCONFIG) -a IVMS8 ppc mpc8xx ivm

+kmsupx4_config:		unconfig
+	@$(MKCONFIG) $(@:_config=) ppc mpc8xx km8xx keymile
+
 KUP4K_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc8xx kup4k kup

@@ -938,7 +941,7 @@ MBX860T_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc8xx mbx8xx

 mgsuvd_config:		unconfig
-	@$(MKCONFIG) $(@:_config=) ppc mpc8xx mgsuvd keymile
+	@$(MKCONFIG) $(@:_config=) ppc mpc8xx km8xx keymile

 MHPC_config:		unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc8xx mhpc eltec
--- a/5
+++ b/5
@@ -318,6 +318,11 @@ The following options need to be configured:
 		that this requires a (stable) reference clock (32 kHz
 		RTC clock or CONFIG_SYS_8XX_XIN)

+		CONFIG_SYS_DELAYED_ICACHE
+
+		Define this option if you want to enable the
+		ICache only when Code runs from RAM.
+
 - Intel Monahans options:
 		CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO

--- a/api_examples/.gitignore
+++ b/api_examples/.gitignore
@@ -0,0 +1,7 @@
+crc32.c
+ctype.c
+demo
+demo.bin
+ppcstring.S
+string.c
+vsprintf.c
--- a/board/amcc/sequoia/sdram.c
+++ b/board/amcc/sequoia/sdram.c
@@ -72,7 +72,7 @@ phys_size_t initdram (int board_type)
 	mtsdram(DDR0_07, 0x000D0100);
 	mtsdram(DDR0_08, 0x02430001);
 	mtsdram(DDR0_09, 0x00011D5F);
-	mtsdram(DDR0_10, 0x00000300);
+	mtsdram(DDR0_10, 0x00000100);
 	mtsdram(DDR0_11, 0x0027C800);
 	mtsdram(DDR0_12, 0x00000003);
 	mtsdram(DDR0_14, 0x00000000);
--- a/board/esd/pmc440/sdram.c
+++ b/board/esd/pmc440/sdram.c
@@ -70,7 +70,7 @@ phys_size_t initdram (int board_type)
 	mtsdram(DDR0_07, 0x000D0100);
 	mtsdram(DDR0_08, 0x02430001);
 	mtsdram(DDR0_09, 0x00011D5F);
-	mtsdram(DDR0_10, 0x00000300);
+	mtsdram(DDR0_10, 0x00000100);
 	mtsdram(DDR0_11, 0x0027C800);
 	mtsdram(DDR0_12, 0x00000003);
 	mtsdram(DDR0_14, 0x00000000);
--- a/board/freescale/m5329evb/nand.c
+++ b/board/freescale/m5329evb/nand.c
@@ -47,10 +47,12 @@ static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
 		ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;

 		IO_ADDR_W &= ~(SET_ALE | SET_CLE);
-		*nCE &= 0xFFFB;

 		if (ctrl & NAND_NCE)
+			*nCE &= 0xFFFB;
+		else
 			*nCE |= 0x0004;
+
 		if (ctrl & NAND_CLE)
 			IO_ADDR_W |= SET_CLE;
 		if (ctrl & NAND_ALE)
@@ -78,7 +80,7 @@ int board_nand_init(struct nand_chip *nand)
 	gpio->pclrr_timer = 0;
 	gpio->podr_timer = 0;

-	nand->chip_delay = 50;
+	nand->chip_delay = 60;
 	nand->ecc.mode = NAND_ECC_SOFT;
 	nand->cmd_ctrl = nand_hwcontrol;

--- a/board/freescale/m5373evb/nand.c
+++ b/board/freescale/m5373evb/nand.c
@@ -47,10 +47,12 @@ static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
 		ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;

 		IO_ADDR_W &= ~(SET_ALE | SET_CLE);
-		*nCE &= 0xFFFB;

 		if (ctrl & NAND_NCE)
+			*nCE &= 0xFFFB;
+		else
 			*nCE |= 0x0004;
+
 		if (ctrl & NAND_CLE)
 			IO_ADDR_W |= SET_CLE;
 		if (ctrl & NAND_ALE)
@@ -82,7 +84,7 @@ int board_nand_init(struct nand_chip *nand)
 	gpio->pclrr_timer = 0;
 	gpio->podr_timer = 0;

-	nand->chip_delay = 50;
+	nand->chip_delay = 60;
 	nand->ecc.mode = NAND_ECC_SOFT;
 	nand->cmd_ctrl = nand_hwcontrol;

--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c
@@ -295,11 +295,14 @@ int ivm_analyze_eeprom (unsigned char *buf, int len)

 int ivm_read_eeprom (void)
 {
+#if defined(CONFIG_I2C_MUX)
 	I2C_MUX_DEVICE *dev = NULL;
+#endif
 	uchar i2c_buffer[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
 	uchar	*buf;
 	unsigned dev_addr = CONFIG_SYS_IVM_EEPROM_ADR;

+#if defined(CONFIG_I2C_MUX)
 	/* First init the Bus, select the Bus */
 #if defined(CONFIG_SYS_I2C_IVM_BUS)
 	dev = i2c_mux_ident_muxstring ((uchar *)CONFIG_SYS_I2C_IVM_BUS);
@@ -313,6 +316,7 @@ int ivm_read_eeprom (void)
 		return -1;
 	}
 	i2c_set_bus_num (dev->busid);
+#endif

 	buf = (unsigned char *) getenv ("EEprom_ivm_addr");
 	if (buf != NULL)
@@ -390,7 +394,7 @@ static void setports (int gpio)
 #endif
 #endif

-#if defined(CONFIG_MGSUVD)
+#if defined(CONFIG_KM8XX)
 static void set_sda (int state)
 {
 	I2C_SDA(state);
--- a/board/keymile/common/keymile_hdlc_enet.h
+++ b/board/keymile/common/keymile_hdlc_enet.h
@@ -25,7 +25,7 @@
 #define _KEYMILE_HDLC_ENET_H_

 /* Unfortuantely, we have do this to get the flag defines in the cbd_t */
-#ifdef CONFIG_MGSUVD
+#ifdef CONFIG_KM8XX
 #include <commproc.h>
 #endif
 #ifdef CONFIG_MGCOGE
--- a/board/keymile/mgsuvd/Makefile
+++ b/board/keymile/mgsuvd/Makefile
@@ -29,7 +29,7 @@ endif
 LIB	= $(obj)lib$(BOARD).a

 COBJS	= $(BOARD).o ../common/common.o ../common/keymile_hdlc_enet.o \
-		mgsuvd_hdlc_enet.o
+		km8xx_hdlc_enet.o

 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
--- a/board/keymile/mgsuvd/config.mk
+++ b/board/keymile/mgsuvd/config.mk
--- a/board/keymile/mgsuvd/mgsuvd.c
+++ b/board/keymile/mgsuvd/mgsuvd.c
@@ -61,7 +61,12 @@ const uint sdram_table[] =

 int checkboard (void)
 {
-	puts ("Board: Keymile mgsuvd");
+	puts ("Board: Keymile ");
+#if defined(CONFIG_KMSUPX4)
+	puts ("kmsupx4");
+#else
+	puts ("mgsuvd");
+#endif
 	if (ethernet_present ())
 		puts (" with PIGGY.");
 	puts ("\n");
--- a/board/keymile/mgsuvd/mgsuvd_hdlc_enet.c
+++ b/board/keymile/mgsuvd/mgsuvd_hdlc_enet.c
--- a/board/keymile/mgsuvd/u-boot.lds
+++ b/board/keymile/mgsuvd/u-boot.lds
--- a/board/lwmon5/sdram.c
+++ b/board/lwmon5/sdram.c
@@ -160,49 +160,6 @@ static void program_ecc(u32 start_address,
 ************************************************************************/
 phys_size_t initdram (int board_type)
 {
-#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
-	/* CL=3 */
-	mtsdram(DDR0_02, 0x00000000);
-
-	mtsdram(DDR0_00, 0x0000190A);
-	mtsdram(DDR0_01, 0x01000000);
-	mtsdram(DDR0_03, 0x02030603); /* A suitable burst length was taken. CAS is right for our board */
-
-	mtsdram(DDR0_04, 0x0A030300);
-	mtsdram(DDR0_05, 0x02020308);
-	mtsdram(DDR0_06, 0x0103C812);
-	mtsdram(DDR0_07, 0x00090100);
-	mtsdram(DDR0_08, 0x02c80001);
-	mtsdram(DDR0_09, 0x00011D5F);
-	mtsdram(DDR0_10, 0x00000300);
-	mtsdram(DDR0_11, 0x000CC800);
-	mtsdram(DDR0_12, 0x00000003);
-	mtsdram(DDR0_14, 0x00000000);
-	mtsdram(DDR0_17, 0x1e000000);
-	mtsdram(DDR0_18, 0x1e1e1e1e);
-	mtsdram(DDR0_19, 0x1e1e1e1e);
-	mtsdram(DDR0_20, 0x0B0B0B0B);
-	mtsdram(DDR0_21, 0x0B0B0B0B);
-#ifdef CONFIG_DDR_ECC
-	mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC	*/
-#else
-	mtsdram(DDR0_22, 0x00267F0B);
-#endif
-
-	mtsdram(DDR0_23, 0x01000000);
-	mtsdram(DDR0_24, 0x01010001);
-
-	mtsdram(DDR0_26, 0x2D93028A);
-	mtsdram(DDR0_27, 0x0784682B);
-
-	mtsdram(DDR0_28, 0x00000080);
-	mtsdram(DDR0_31, 0x00000000);
-	mtsdram(DDR0_42, 0x01000006);
-
-	mtsdram(DDR0_43, 0x030A0200);
-	mtsdram(DDR0_44, 0x00000003);
-	mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
-#else
 	/* CL=4 */
 	mtsdram(DDR0_02, 0x00000000);

@@ -216,7 +173,7 @@ phys_size_t initdram (int board_type)
 	mtsdram(DDR0_07, 0x00090100);
 	mtsdram(DDR0_08, 0x03c80001);
 	mtsdram(DDR0_09, 0x00011D5F);
-	mtsdram(DDR0_10, 0x00000300);
+	mtsdram(DDR0_10, 0x00000100);
 	mtsdram(DDR0_11, 0x000CC800);
 	mtsdram(DDR0_12, 0x00000003);
 	mtsdram(DDR0_14, 0x00000000);
@@ -244,7 +201,6 @@ phys_size_t initdram (int board_type)
 	mtsdram(DDR0_43, 0x050A0200);
 	mtsdram(DDR0_44, 0x00000005);
 	mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
-#endif

 	denali_wait_for_dlllock();

--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -502,7 +502,7 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand,

 	s = strchr(cmd, '.');
 	if (s != NULL &&
-	    (strcmp(s, ".jffs2") && !strcmp(s, ".e") && !strcmp(s, ".i"))) {
+	    (strcmp(s, ".jffs2") && strcmp(s, ".e") && strcmp(s, ".i"))) {
 		printf("Unknown nand load suffix '%s'\n", s);
 		show_boot_progress(-53);
 		return 1;
@@ -511,7 +511,7 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand,
 	printf("\nLoading from %s, offset 0x%lx\n", nand->name, offset);

 	cnt = nand->writesize;
-	r = nand_read(nand, offset, &cnt, (u_char *) addr);
+	r = nand_read_skip_bad(nand, offset, &cnt, (u_char *) addr);
 	if (r) {
 		puts("** Read error\n");
 		show_boot_progress (-56);
@@ -543,8 +543,7 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand,
 	}
 	show_boot_progress (57);

-	/* FIXME: skip bad blocks */
-	r = nand_read(nand, offset, &cnt, (u_char *) addr);
+	r = nand_read_skip_bad(nand, offset, &cnt, (u_char *) addr);
 	if (r) {
 		puts("** Read error\n");
 		show_boot_progress (-58);
--- a/cpu/mcf5227x/config.mk
+++ b/cpu/mcf5227x/config.mk
@@ -24,8 +24,8 @@
 #

 PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
-ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2)
-PLATFORM_CPPFLAGS += -mcpu=5208 -fPIC
+ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1)
+PLATFORM_CPPFLAGS += -mcpu=52277 -fPIC
 else
 PLATFORM_CPPFLAGS += -m5307 -fPIC
 endif
--- a/cpu/mcf523x/config.mk
+++ b/cpu/mcf523x/config.mk
@@ -24,7 +24,7 @@
 #

 PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
-ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2)
+ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1)
 PLATFORM_CPPFLAGS += -mcpu=5235 -fPIC
 else
 PLATFORM_CPPFLAGS += -m5307 -fPIC
--- a/cpu/mcf52x2/config.mk
+++ b/cpu/mcf52x2/config.mk
@@ -34,7 +34,7 @@ is5275:=$(shell grep CONFIG_M5275 $(TOPDIR)/include/$(cfg))
 is5282:=$(shell grep CONFIG_M5282 $(TOPDIR)/include/$(cfg))


-ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2)
+ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1)

 ifneq (,$(findstring CONFIG_M5249,$(is5249)))
 PLATFORM_CPPFLAGS += -mcpu=5249
--- a/cpu/mcf532x/config.mk
+++ b/cpu/mcf532x/config.mk
@@ -24,7 +24,7 @@
 #

 PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
-ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2)
+ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1)
 PLATFORM_CPPFLAGS += -mcpu=5329 -fPIC
 else
 PLATFORM_CPPFLAGS += -m5307 -fPIC
--- a/cpu/mcf5445x/config.mk
+++ b/cpu/mcf5445x/config.mk
@@ -24,7 +24,7 @@
 #

 PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
-ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2)
+ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1)
 PLATFORM_CPPFLAGS += -mcpu=54455 -fPIC
 else
 PLATFORM_CPPFLAGS += -m5407 -fPIC
--- a/cpu/mcf5445x/start.S
+++ b/cpu/mcf5445x/start.S
@@ -243,9 +243,9 @@ wait1000:
 	nop
 #elif defined(CONFIG_M54451EVB)
 	/* Issue LEMR */
-	move.l	#(CONFIG_SYS_SDRAM_MODE), (%a2)
+	move.l	#(CONFIG_SYS_SDRAM_MODE), (%a1)
 	nop
-	move.l	#(CONFIG_SYS_SDRAM_EMOD), (%a2)
+	move.l	#(CONFIG_SYS_SDRAM_EMOD), (%a1)
 	nop
 #endif

--- a/cpu/mcf547x_8x/config.mk
+++ b/cpu/mcf547x_8x/config.mk
@@ -24,7 +24,7 @@
 #

 PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
-ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2)
+ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1)
 PLATFORM_CPPFLAGS += -mcpu=5485 -fPIC
 else
 PLATFORM_CPPFLAGS += -m5407 -fPIC
--- a/cpu/mcf547x_8x/cpu_init.c
+++ b/cpu/mcf547x_8x/cpu_init.c
@@ -49,14 +49,14 @@ void cpu_init_f(void)
 	volatile xlbarb_t *xlbarb = (volatile xlbarb_t *) MMAP_XARB;

 	xlbarb->adrto = 0x2000;
-	xlbarb->datto = 0x2000;
+	xlbarb->datto = 0x2500;
 	xlbarb->busto = 0x3000;

-	xlbarb->cfg = XARB_SR_AT | XARB_SR_DT;
+	xlbarb->cfg = XARB_CFG_AT | XARB_CFG_DT;

 	/* Master Priority Enable */
-	xlbarb->pri = 0;
 	xlbarb->prien = 0xff;
+	xlbarb->pri = 0;

 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
 	fbcs->csar0 = CONFIG_SYS_CS0_BASE;
--- a/cpu/mpc5xxx/ide.c
+++ b/cpu/mpc5xxx/ide.c
@@ -42,7 +42,7 @@ int ide_preinit (void)
 	struct mpc5xxx_sdma *psdma = (struct mpc5xxx_sdma *) MPC5XXX_SDMA;

 	reg = *(vu_long *) MPC5XXX_GPS_PORT_CONFIG;
-#if defined(CONFIG_TOTAL5200)
+#if defined(CONFIG_SYS_ATA_CS_ON_I2C2)
 	/* ATA cs0/1 on i2c2 clk/io */
 	reg = (reg & ~0x03000000ul) | 0x02000000ul;
 #else
--- a/cpu/mpc8xx/start.S
+++ b/cpu/mpc8xx/start.S
@@ -142,7 +142,7 @@ boot_warm:
 	lis	r3, IDC_DISABLE@h	/* Disable data cache */
 	mtspr	DC_CST, r3

-#if !(defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || defined (CONFIG_FLAGADM))
+#if !defined(CONFIG_SYS_DELAYED_ICACHE)
 					/* On IP860 and PCU E,
 					 * we cannot enable IC yet
 					 */
--- a/cpu/ppc4xx/4xx_pci.c
+++ b/cpu/ppc4xx/4xx_pci.c
@@ -550,10 +550,12 @@ int pci_440_init (struct pci_controller *hose)
 	out32r( PCIX0_POM0SA, 0 ); /* disable */
 	out32r( PCIX0_POM1SA, 0 ); /* disable */
 	out32r( PCIX0_POM2SA, 0 ); /* disable */
-#if defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if defined(CONFIG_440SPE)
 	out32r( PCIX0_POM0LAL, 0x10000000 );
 	out32r( PCIX0_POM0LAH, 0x0000000c );
+#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
+	out32r( PCIX0_POM0LAL, 0x20000000 );
+	out32r( PCIX0_POM0LAH, 0x0000000c );
 #else
 	out32r( PCIX0_POM0LAL, 0x00000000 );
 	out32r( PCIX0_POM0LAH, 0x00000003 );
--- a/drivers/i2c/soft_i2c.c
+++ b/drivers/i2c/soft_i2c.c
@@ -40,7 +40,7 @@
 #ifdef CONFIG_LPC2292
 #include <asm/arch/hardware.h>
 #endif
-#ifdef	CONFIG_MPC866			/* only valid for MPC866 */
+#if defined(CONFIG_MPC852T) || defined(CONFIG_MPC866)
 #include <asm/io.h>
 #endif
 #include <i2c.h>
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -1806,8 +1806,9 @@ static void flash_fixup_stm(flash_info_t *info, struct cfi_qry *qry)
 	if (qry->num_erase_regions > 1) {
 		/* reverse geometry if top boot part */
 		if (info->cfi_version < 0x3131) {
-			/* CFI < 1.1, guess by device id (only M29W320ET now) */
-			if (info->device_id == 0x2256) {
+			/* CFI < 1.1, guess by device id (M29W320{DT,ET} only) */
+			if (info->device_id == 0x22CA ||
+			    info->device_id == 0x2256) {
 				cfi_reverse_geometry(qry);
 			}
 		}
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -639,8 +639,6 @@ err:
 void sh_eth_halt(struct eth_device *dev)
 {
 	struct sh_eth_dev *eth = dev->priv;
-
-	sh_eth_reset(eth);
 	sh_eth_stop(eth);
 }

--- a/drivers/serial/usbtty.c
+++ b/drivers/serial/usbtty.c
@@ -215,7 +215,7 @@ static struct acm_config_desc acm_configuration_descriptors[NUM_CONFIGS] = {
 			.bLength =
 				sizeof(struct usb_endpoint_descriptor),
 			.bDescriptorType	= USB_DT_ENDPOINT,
-			.bEndpointAddress	= 0x01 | USB_DIR_IN,
+			.bEndpointAddress	= UDC_INT_ENDPOINT | USB_DIR_IN,
 			.bmAttributes		= USB_ENDPOINT_XFER_INT,
 			.wMaxPacketSize
 				= cpu_to_le16(CONFIG_USBD_SERIAL_INT_PKTSIZE),
@@ -241,7 +241,7 @@ static struct acm_config_desc acm_configuration_descriptors[NUM_CONFIGS] = {
 				.bLength		=
 					sizeof(struct usb_endpoint_descriptor),
 				.bDescriptorType	= USB_DT_ENDPOINT,
-				.bEndpointAddress	= 0x02 | USB_DIR_OUT,
+				.bEndpointAddress	= UDC_OUT_ENDPOINT | USB_DIR_OUT,
 				.bmAttributes		=
 					USB_ENDPOINT_XFER_BULK,
 				.wMaxPacketSize		=
@@ -252,7 +252,7 @@ static struct acm_config_desc acm_configuration_descriptors[NUM_CONFIGS] = {
 				.bLength		=
 					sizeof(struct usb_endpoint_descriptor),
 				.bDescriptorType	= USB_DT_ENDPOINT,
-				.bEndpointAddress	= 0x03 | USB_DIR_IN,
+				.bEndpointAddress	= UDC_IN_ENDPOINT | USB_DIR_IN,
 				.bmAttributes		=
 					USB_ENDPOINT_XFER_BULK,
 				.wMaxPacketSize		=
@@ -321,7 +321,7 @@ gserial_configuration_descriptors[NUM_CONFIGS] ={
 				.bLength =
 					sizeof(struct usb_endpoint_descriptor),
 				.bDescriptorType =	USB_DT_ENDPOINT,
-				.bEndpointAddress =	0x01 | USB_DIR_OUT,
+				.bEndpointAddress =	UDC_OUT_ENDPOINT | USB_DIR_OUT,
 				.bmAttributes =		USB_ENDPOINT_XFER_BULK,
 				.wMaxPacketSize =
 					cpu_to_le16(CONFIG_USBD_SERIAL_OUT_PKTSIZE),
@@ -331,7 +331,7 @@ gserial_configuration_descriptors[NUM_CONFIGS] ={
 				.bLength =
 					sizeof(struct usb_endpoint_descriptor),
 				.bDescriptorType =	USB_DT_ENDPOINT,
-				.bEndpointAddress =	0x02 | USB_DIR_IN,
+				.bEndpointAddress =	UDC_IN_ENDPOINT | USB_DIR_IN,
 				.bmAttributes =		USB_ENDPOINT_XFER_BULK,
 				.wMaxPacketSize =
 					cpu_to_le16(CONFIG_USBD_SERIAL_IN_PKTSIZE),
@@ -341,7 +341,7 @@ gserial_configuration_descriptors[NUM_CONFIGS] ={
 				.bLength =
 					sizeof(struct usb_endpoint_descriptor),
 				.bDescriptorType =	USB_DT_ENDPOINT,
-				.bEndpointAddress =	0x03 | USB_DIR_IN,
+				.bEndpointAddress =	UDC_INT_ENDPOINT | USB_DIR_IN,
 				.bmAttributes =		USB_ENDPOINT_XFER_INT,
 				.wMaxPacketSize =
 					cpu_to_le16(CONFIG_USBD_SERIAL_INT_PKTSIZE),
--- a/examples/smc911x_eeprom.c
+++ b/examples/smc911x_eeprom.c
@@ -59,7 +59,8 @@ static void dump_regs(void)
 {
 	u8 i, j = 0;
 	for (i = 0x50; i < 0xB8; i += sizeof(u32))
-		printf("%02x: 0x%08x %c", i, reg_read(CONFIG_DRIVER_SMC911X_BASE + i),
+		printf("%02x: 0x%08x %c", i,
+			smc911x_reg_read(CONFIG_DRIVER_SMC911X_BASE + i),
 			(j++ % 2 ? '\n' : ' '));
 }

@@ -68,18 +69,18 @@ static void dump_regs(void)
 */
 static int do_eeprom_cmd(int cmd, u8 reg)
 {
-	if (reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY) {
+	if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY) {
 		printf("eeprom_cmd: busy at start (E2P_CMD = 0x%08x)\n",
-			reg_read(E2P_CMD));
+			smc911x_reg_read(E2P_CMD));
 		return -1;
 	}

-	reg_write(E2P_CMD, E2P_CMD_EPC_BUSY | cmd | reg);
+	smc911x_reg_write(E2P_CMD, E2P_CMD_EPC_BUSY | cmd | reg);

-	while (reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY)
+	while (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY)
 		if (smsc_ctrlc()) {
 			printf("eeprom_cmd: timeout (E2P_CMD = 0x%08x)\n",
-				reg_read(E2P_CMD));
+				smc911x_reg_read(E2P_CMD));
 			return -1;
 		}

@@ -92,7 +93,7 @@ static int do_eeprom_cmd(int cmd, u8 reg)
 static u8 read_eeprom_reg(u8 reg)
 {
 	int ret = do_eeprom_cmd(E2P_CMD_EPC_CMD_READ, reg);
-	return (ret ? : reg_read(E2P_DATA));
+	return (ret ? : smc911x_reg_read(E2P_DATA));
 }

 /**
@@ -113,7 +114,7 @@ static int write_eeprom_reg(u8 value, u8 reg)
 		goto done;

 	/* write the eeprom reg */
-	reg_write(E2P_DATA, value);
+	smc911x_reg_write(E2P_DATA, value);
 	ret = do_eeprom_cmd(E2P_CMD_EPC_CMD_WRITE, reg);
 	if (ret)
 		goto done;
@@ -184,7 +185,7 @@ static void write_stuff(char *line)
 		write_eeprom_reg(value, reg);
 	} else {
 		printf("Writing MAC register %02x with %08x\n", reg, value);
-		reg_write(CONFIG_DRIVER_SMC911X_BASE + reg, value);
+		smc911x_reg_write(CONFIG_DRIVER_SMC911X_BASE + reg, value);
 	}
 }

@@ -248,13 +249,14 @@ static int smc911x_init(void)
 	smc911x_reset();

 	/* Make sure we set EEDIO/EECLK to the EEPROM */
-	if (reg_read(GPIO_CFG) & GPIO_CFG_EEPR_EN) {
-		while (reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY)
+	if (smc911x_reg_read(GPIO_CFG) & GPIO_CFG_EEPR_EN) {
+		while (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY)
 			if (smsc_ctrlc()) {
-				printf("init: timeout (E2P_CMD = 0x%08x)\n", reg_read(E2P_CMD));
+				printf("init: timeout (E2P_CMD = 0x%08x)\n",
+					smc911x_reg_read(E2P_CMD));
 				return 1;
 			}
-		reg_write(GPIO_CFG, reg_read(GPIO_CFG) & ~GPIO_CFG_EEPR_EN);
+		smc911x_reg_write(GPIO_CFG, smc911x_reg_read(GPIO_CFG) & ~GPIO_CFG_EEPR_EN);
 	}

 	return 0;
--- a/include/asm-m68k/m5301x.h
+++ b/include/asm-m68k/m5301x.h
@@ -601,4 +601,8 @@
 #define RTC_OCEN_OSCBYP			(0x00000010)
 #define RTC_OCEN_CLKEN			(0x00000008)

+/* SDRAM */
+#define SDRAMC_SDCR_CKE			(0x40000000)
+#define SDRAMC_SDCR_REF			(0x10000000)
+
 #endif				/* m5301x_h */
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -1122,11 +1122,11 @@ typedef struct scc_enet {
 #define SICR_ENET_CLKRT	((uint)0x0000003d)
 #endif	/* CONFIG_MBX */

-/***  MGSUVD  *********************************************************/
+/***  KM8XX  *********************************************************/

-/* The MGSUVD Service Module uses SCC3 for Ethernet */
+/* The KM8XX Service Module uses SCC3 for Ethernet */

-#ifdef CONFIG_MGSUVD
+#ifdef CONFIG_KM8XX
 #define PROFF_ENET	PROFF_SCC3		/* Ethernet on SCC3 */
 #define CPM_CR_ENET	CPM_CR_CH_SCC3
 #define SCC_ENET	2
@@ -1145,7 +1145,7 @@ typedef struct scc_enet {
 */
 #define SICR_ENET_MASK	((uint)0x00FF0000)
 #define SICR_ENET_CLKRT	((uint)0x00250000)
-#endif	/* CONFIG_MGSUVD */
+#endif	/* CONFIG_KM8XX */


 /***  MHPC  ********************************************************/
--- a/include/configs/FLAGADM.h
+++ b/include/configs/FLAGADM.h
@@ -173,6 +173,9 @@
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
+#define CONFIG_SYS_DELAYED_ICACHE	1	/* enable ICache not before
+						 * running in RAM.
+						 */

 /*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
--- a/include/configs/IP860.h
+++ b/include/configs/IP860.h
@@ -209,6 +209,9 @@
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
+#define CONFIG_SYS_DELAYED_ICACHE	1	/* enable ICache not before
+						 * running in RAM.
+						 */

 /*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
--- a/include/configs/M52277EVB.h
+++ b/include/configs/M52277EVB.h
@@ -246,6 +246,7 @@

 /* Initial Memory map for Linux */
 #define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

 /*
 * Configuration for environment
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -197,6 +197,7 @@
 */
 /* Initial Memory map for Linux */
 #define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

 /*-----------------------------------------------------------------------
 * FLASH organization
--- a/include/configs/M5253DEMO.h
+++ b/include/configs/M5253DEMO.h
@@ -200,6 +200,7 @@
 * the maximum mapped by the Linux kernel during initialization ??
 */
 #define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

 /* FLASH organization */
 #define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
--- a/include/configs/M5253EVBE.h
+++ b/include/configs/M5253EVBE.h
@@ -164,6 +164,7 @@
 * the maximum mapped by the Linux kernel during initialization ??
 */
 #define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

 /* FLASH organization */
 #define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
--- a/include/configs/M5275EVB.h
+++ b/include/configs/M5275EVB.h
@@ -190,7 +190,8 @@
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial mmap for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

 /*-----------------------------------------------------------------------
 * FLASH organization
--- a/include/configs/M53017EVB.h
+++ b/include/configs/M53017EVB.h
@@ -196,6 +196,7 @@
 * the maximum mapped by the Linux kernel during initialization ??
 */
 #define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

 /*-----------------------------------------------------------------------
 * FLASH organization
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -196,6 +196,7 @@
 * the maximum mapped by the Linux kernel during initialization ??
 */
 #define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

 /*-----------------------------------------------------------------------
 * FLASH organization
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -196,6 +196,7 @@
 * the maximum mapped by the Linux kernel during initialization ??
 */
 #define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

 /*-----------------------------------------------------------------------
 * FLASH organization
--- a/include/configs/Total5200.h
+++ b/include/configs/Total5200.h
@@ -397,6 +397,7 @@
 #define	CONFIG_IDE_RESET		/* reset for ide supported	*/
 #define CONFIG_IDE_PREINIT

+#define CONFIG_SYS_ATA_CS_ON_I2C2
 #define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
 #define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

--- a/include/configs/keymile-common.h
+++ b/include/configs/keymile-common.h
@@ -27,9 +27,7 @@
 /* Do boardspecific init for all boards */
 #define CONFIG_BOARD_EARLY_INIT_R       1

-#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGSUVD)
 #define CONFIG_BOOTCOUNT_LIMIT
-#endif

 /*
 * Command line configuration.
@@ -45,10 +43,11 @@
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_JFFS2_CMDLINE

 #undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */

-#define CONFIG_BOOTCOMMAND	"run net_nfs"
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
 #undef	CONFIG_BOOTARGS			/* the boot command will set bootargs */

@@ -68,6 +67,8 @@
 #define CONFIG_SYS_MAXARGS		16	/* max number of command args */
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size  */
 #define CONFIG_CMDLINE_EDITING		1	/* add command line history     */
+#define CONFIG_COMMAND_HISTORY		1
+#define CONFIG_AUTO_COMPLETE		/* add autocompletion support	*/

 #define CONFIG_HUSH_INIT_VAR	1

@@ -95,6 +96,25 @@
 #define CONFIG_SYS_SLOT_ID_OFF		(0x07)	/* register offset */
 #define CONFIG_SYS_SLOT_ID_MASK		(0x3f)	/* mask for slot ID bits */

+#define CONFIG_I2C_MULTI_BUS	1
+#define CONFIG_I2C_CMD_TREE	1
+#define CONFIG_SYS_MAX_I2C_BUS		2
+#define CONFIG_SYS_I2C_INIT_BOARD	1
+#define CONFIG_I2C_MUX		1
+
+/* EEprom support */
+#define CONFIG_SYS_I2C_MULTI_EEPROMS	1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/* Support the IVM EEprom */
+#define	CONFIG_SYS_IVM_EEPROM_ADR	0x50
+#define CONFIG_SYS_IVM_EEPROM_MAX_LEN	0x400
+#define CONFIG_SYS_IVM_EEPROM_PAGE_LEN	0x100
+
+#define	CONFIG_SYS_FLASH_PROTECTION 1
+
 /*
 * BOOTP options
 */
@@ -103,4 +123,130 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME

+/* define this to use the keymile's io muxing feature */
+/*#define CONFIG_IO_MUXING */
+
+#ifdef CONFIG_IO_MUXING
+#define	CONFIG_KM_DEF_ENV_IOMUX \
+	"nc=setenv ethact HDLC ETHERNET \0" \
+	"nce=setenv ethact SCC ETHERNET \0"	\
+	"stderr=serial,nc \0"	\
+	"stdin=serial,nc \0" \
+	"stdout=serial,nc \0" \
+	"tftpsrcp=69 \0" \
+	"tftpdstp=69 \0"
+#else
+#define	CONFIG_KM_DEF_ENV_IOMUX \
+	"stderr=serial \0" \
+	"stdin=serial \0"	 \
+	"stdout=serial \0"
+#endif
+
+#ifndef CONFIG_KM_DEF_ENV_PRIVATE
+#define	CONFIG_KM_DEF_ENV_PRIVATE \
+	"kmprivate=empty\0"
+#endif
+
+#define xstr(s)	str(s)
+#define str(s)	#s
+
+#ifndef CONFIG_KM_DEF_ENV
+#define CONFIG_KM_DEF_ENV	\
+	"netdev=eth0\0"							\
+	"u-boot_addr_r=100000\0"					\
+	"kernel_addr_r=200000\0"					\
+	"fdt_addr_r=600000\0"						\
+	"ram_ws=800000 \0"						\
+	"autoscr_ws=780000 \0"						\
+	"fdt_file=" xstr(CONFIG_HOSTNAME) "/" 				\
+		xstr(CONFIG_HOSTNAME) ".dtb\0"				\
+	"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin \0" 		\
+	"kernel_file=" xstr(CONFIG_HOSTNAME) "/uImage \0" 		\
+	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
+	"update=protect off " xstr(BOOTFLASH_START) " +${filesize};"	\
+		"erase " xstr(BOOTFLASH_START) "  +${filesize};"	\
+		"cp.b ${u-boot_addr_r} " xstr(BOOTFLASH_START) 		\
+		"  ${filesize};"					\
+		"protect on " xstr(BOOTFLASH_START) "  +${filesize}\0"	\
+	"load_fdt=tftp ${fdt_addr_r} ${fdt_file}; "			\
+		"setenv actual_fdt_addr ${fdt_addr_r} \0" 		\
+	"load_kernel=tftp ${kernel_addr_r} ${kernel_file}; " 		\
+		"setenv actual_kernel_addr ${kernel_addr_r} \0" 	\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"mtdargs=setenv bootargs root=${actual_rootfs} rw "		\
+		"rootfstype=jffs2 \0" 					\
+	"altmtdargs=setenv bootargs root=${backup_rootfs} rw "		\
+		"rootfstype=jffs2 \0" 					\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addboardid=setenv bootargs ${bootargs} " 			\
+		"hwKey=${IVM_HWKey} boardId=0x${IVM_BoardId} \0" 	\
+	"addpram=setenv bootargs ${bootargs} "				\
+		"mem=${mem} pram=${pram}\0"				\
+	"pram=" xstr(CONFIG_PRAM) "k\0"					\
+	"net_nfs=tftp ${kernel_addr_r} ${kernel_file}; "		\
+		"tftp ${fdt_addr_r} ${fdt_file}; "			\
+		"run nfsargs addip addcon addboardid addpram;"		\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"net_self=tftp ${kernel_addr_r} ${kernel_file}; "		\
+		"tftp ${fdt_addr_r} ${fdt_file}; "			\
+		"tftp ${ramdisk_addr} ${ramdisk_file}; "		\
+		"run ramargs addip addboardid addpram; "		\
+		"bootm ${kernel_addr_r} ${ramdisk_addr} ${fdt_addr_r}\0"\
+	"flash_nfs=run nfsargs addip addcon;"				\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"flash_self=run ramargs addip addcon addboardid addpram;"	\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"bootcmd=run mtdargs addip addcon addboardid addpram; "		\
+		"bootm ${actual_kernel_addr} - ${actual_fdt_addr} \0"	\
+	"altbootcmd=run altmtdargs addip addcon addboardid addpram; "	\
+		"bootm ${backup_kernel_addr} - ${backup_fdt_addr} \0"	\
+	"actual0=setenv actual_bank 0; setenv actual_kernel_addr "	\
+		"${bank0_kernel_addr}; "				\
+		"setenv actual_fdt_addr ${bank0_fdt_addr}; "		\
+		"setenv actual_rootfs ${bank0_rootfs} \0" 		\
+	"actual1=setenv actual_bank 1; setenv actual_kernel_addr "	\
+		"${bank1_kernel_addr}; "				\
+		"setenv actual_fdt_addr ${bank1_fdt_addr}; "		\
+		"setenv actual_rootfs ${bank1_rootfs} \0" 		\
+	"backup0=setenv backup_bank 0; setenv backup_kernel_addr " 	\
+		"${bank0_kernel_addr}; "				\
+		"setenv backup_fdt_addr ${bank0_fdt_addr}; "		\
+		"setenv backup_rootfs ${bank0_rootfs} \0"		\
+	"backup1=setenv backup_bank 1; setenv backup_kernel_addr "	\
+		"${bank1_kernel_addr}; "				\
+		"setenv backup_fdt_addr ${bank1_fdt_addr}; " 		\
+		"setenv backup_rootfs ${bank1_rootfs} \0" 		\
+	"setbank0=run actual0 backup1 \0" 				\
+	"setbank1=run actual1 backup0 \0" 				\
+	"release=setenv bootcmd "					\
+		"\'run mtdargs addip addcon addboardid addpram;" 	\
+		"bootm ${actual_kernel_addr} - ${actual_fdt_addr} \'; "	\
+		"saveenv \0"						\
+	"develop=setenv bootcmd "					\
+		"\'run nfsargs addip addcon addboardid addpram;" 	\
+		"bootm ${actual_kernel_addr} - ${actual_fdt_addr} \'; "	\
+		"saveenv \0"						\
+	"developall=setenv bootcmd "					\
+		"\'run load_fdt load_kernel nfsargs "			\
+		"addip addcon addboardid addpram; "			\
+		"bootm ${actual_kernel_addr} - ${actual_fdt_addr} \'; "	\
+		"saveenv \0"						\
+	"set_new_esw_script=setenv new_esw_script "			\
+		"new_esw_0x${IVM_BoardId}_0x${IVM_HWKey}.scr \0"	\
+	"new_esw=run set_new_esw_script; "				\
+		"tftp ${autoscr_ws} ${new_esw_script}; "		\
+		"iminfo ${autoscr_ws}; autoscr ${autoscr_ws} \0"	\
+	"bootlimit=0 \0" 						\
+	CONFIG_KM_DEF_ENV_IOMUX						\
+	CONFIG_KM_DEF_ENV_PRIVATE					\
+	""
+#endif /* CONFIG_KM_DEF_ENV */
+
+#define CONFIG_VERSION_VARIABLE 	/* include version env variable */
+
 #endif /* __CONFIG_KEYMILE_H */
--- a/include/configs/km8xx.h
+++ b/include/configs/km8xx.h
@@ -0,0 +1,343 @@
+/*
+ * (C) Copyright 2009
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * configuration options, keymile 8xx board specific
+ */
+
+#ifndef __CONFIG_KM8XX_H
+#define __CONFIG_KM8XX_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_KM8XX		1	/* on a km8xx board */
+
+/* include common defines/options for all Keymile boards */
+#include "keymile-common.h"
+
+#if defined(CONFIG_KMSUPX4)
+#undef	CONFIG_I2C_MUX			/* no I2C mux on this board */
+#endif
+
+#define CONFIG_8xx_GCLK_FREQ		66000000
+
+#define CONFIG_SYS_SMC_UCODE_PATCH	1	/* Relocate SMC1 */
+#define CONFIG_SYS_SMC_DPMEM_OFFSET	0x1fc0
+#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1 */
+#define CONFIG_SYS_SMC_RXBUFLEN	128
+#define CONFIG_SYS_MAXIDLE	10
+
+#define CONFIG_SYS_CPM_BOOTCOUNT_ADDR	0x1eb0	/* In case of SMC relocation,
+						 * the default value is not
+						 * working
+						 */
+
+#define BOOTFLASH_START	F0000000
+#define CONFIG_PRAM	512	/* protected RAM [KBytes] */
+
+#define CONFIG_PREBOOT	"echo;" \
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#define BOOTFLASH_START	F0000000
+#define CONFIG_PRAM	512	/* protected RAM [KBytes] */
+
+#if defined(CONFIG_MGSUVD)
+#define CONFIG_ENV_IVM	"EEprom_ivm=pca9544a:70:4 \0"
+#else
+#define CONFIG_ENV_IVM	""
+#endif
+
+#define MTDIDS_DEFAULT		"nor0=app"
+#define MTDPARTS_DEFAULT \
+	"mtdparts=app:384k(u-boot),128k(env),128k(envred),128k(free),"	\
+	"1536k(esw0),8704k(rootfs0),1536k(esw1),2432k(rootfs1),640k(var)," \
+	"768k(cfg)"
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_KM_DEF_ENV						\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"addcon=setenv bootargs ${bootargs} "				\
+		"console=ttyCPM0,${baudrate}\0"				\
+	"mtdids=nor0=app \0"						\
+	"mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0"			\
+	"partition=nor0,9 \0"						\
+	"new_env=prot off F0060000 F009FFFF; era F0060000 F009FFFF \0" 	\
+	CONFIG_ENV_IVM							\
+	""
+
+#undef CONFIG_RTC_MPC8xx		/* MPC866 does not support RTC	*/
+
+#define	CONFIG_TIMESTAMP		/* but print image timestmps	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	64
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xf0000000
+#define CONFIG_SYS_MONITOR_LEN		(384 << 10) /* 384 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10) /* 256 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_SIZE		32
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* (in ms) */
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET	CONFIG_SYS_MONITOR_LEN
+#define CONFIG_ENV_SIZE		0x04000 /* Total Size of Environment Sector */
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#define CONFIG_ENV_BUFFER_PRINT		1
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs	*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#define CONFIG_SYS_SYPCR	0xffffff89
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ */
+#if defined(CONFIG_MGSUVD)
+#define CONFIG_SYS_SIUMCR	0x00610480
+#else
+#define CONFIG_SYS_SIUMCR	0x00610400
+#endif
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#if defined(CONFIG_MGSUVD)
+#define SCCR_MASK	0x01800000
+#else
+#define SCCR_MASK	0x00000000
+#endif
+#define CONFIG_SYS_SCCR	0x01800000
+
+#define CONFIG_SYS_DER 0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xf0000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing: Default value of OR0 after reset
+ */
+#define CONFIG_SYS_OR0_PRELIM	0xfe000954
+#define CONFIG_SYS_BR0_PRELIM	0xf0000401
+
+/*
+ * BR1 and OR1 (SDRAM)
+ *
+ */
+#define SDRAM_BASE1_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_MAX_SIZE		(64 << 20)	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
+
+#define CONFIG_SYS_OR1_PRELIM	0xfc000800
+#define CONFIG_SYS_BR1_PRELIM	(0x000000C0 | 0x01)
+
+#define CONFIG_SYS_MPTPR	0x0200
+/* PTB=16, AMB=001, FIXME 1 RAS precharge cycles, 1 READ loop cycle (not used),
+   1 Write loop Cycle (not used), 1 Timer Loop Cycle */
+#if defined(CONFIG_MGSUVD)
+#define CONFIG_SYS_MBMR	0x10964111
+#else
+#define CONFIG_SYS_MBMR	0x20964111
+#endif
+#define CONFIG_SYS_MAR		0x00000088
+
+/*
+ * 4096	Rows from SDRAM example configuration
+ * 1000	factor s -> ms
+ * 64	PTP (pre-divider from MPTPR) from SDRAM example configuration
+ * 4	Number of refresh cycles per period
+ * 64	Refresh cycle in ms per number of rows
+ */
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 64 * 1000) / (4 * 64))
+
+/* GPIO/PIGGY on CS3 initialization values
+*/
+#define CONFIG_SYS_PIGGY_BASE	(0x30000000)
+#if defined(CONFIG_MGSUVD)
+#define CONFIG_SYS_OR3_PRELIM	(0xfe000d24)
+#define CONFIG_SYS_BR3_PRELIM	(0x30000401)
+#else
+#define CONFIG_SYS_OR3_PRELIM	(0xf8000d26)
+#define CONFIG_SYS_BR3_PRELIM	(0x30000401)
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02	/* Software reboot		    */
+
+#define CONFIG_SCC3_ENET
+#define CONFIG_ETHPRIME		"SCC ETHERNET"
+#define CONFIG_HAS_ETH0
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+#define OF_STDOUT_PATH		"/soc/cpm/serial@a80"
+
+/* enable I2C and select the hardware/software driver */
+#undef	CONFIG_HARD_I2C			/* I2C with hardware support */
+#define	CONFIG_SOFT_I2C		1	/* I2C bit-banged	*/
+/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SPEED		50000
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define I2C_SOFT_DECLARATIONS
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define I2C_BASE_DIR	((u16 *)(CONFIG_SYS_PIGGY_BASE + 0x04))
+#define I2C_BASE_PORT	((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x09))
+
+#define SDA_BIT		0x40
+#define SCL_BIT		0x80
+#define SDA_CONF	0x1000
+#define SCL_CONF	0x2000
+
+#define I2C_ACTIVE	do {} while (0)
+#define I2C_TRISTATE	do {} while (0)
+#define I2C_READ	((in_8(I2C_BASE_PORT) & SDA_BIT) == SDA_BIT)
+#define I2C_SDA(bit)	if(bit) { \
+				clrbits(be16, I2C_BASE_DIR, SDA_CONF); \
+			} else { \
+				clrbits(8, I2C_BASE_PORT, SDA_BIT); \
+				setbits(be16, I2C_BASE_DIR, SDA_CONF); \
+			}
+#define I2C_SCL(bit)	if(bit) { \
+				clrbits(be16, I2C_BASE_DIR, SCL_CONF); \
+			} else { \
+				clrbits(8, I2C_BASE_PORT, SCL_BIT); \
+				setbits(be16, I2C_BASE_DIR, SCL_CONF); \
+			}
+#define I2C_DELAY	udelay(50)	/* 1/4 I2C clock duration */
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+
+/* I2C SYSMON (LM75, AD7414 is almost compatible)		*/
+#define CONFIG_DTT_LM75		1	/* ON Semi's LM75	*/
+#if defined(CONFIG_MGSUVD)
+#define CONFIG_DTT_SENSORS	{0, 2, 4, 6}	/* Sensor addresses */
+#else
+#define CONFIG_DTT_SENSORS	{0}	/* Sensor addresses */
+#endif
+#define CONFIG_SYS_DTT_MAX_TEMP	70
+#define CONFIG_SYS_DTT_LOW_TEMP	-30
+#define CONFIG_SYS_DTT_HYSTERESIS	3
+#define CONFIG_SYS_DTT_BUS_NUM		(CONFIG_SYS_MAX_I2C_BUS)
+#endif	/* __CONFIG_KM8XX_H */
--- a/include/configs/kmeter1.h
+++ b/include/configs/kmeter1.h
@@ -33,6 +33,7 @@
 /* include common defines/options for all Keymile boards */
 #include "keymile-common.h"

+#undef CONFIG_SYS_I2C_INIT_BOARD
 #define CONFIG_MISC_INIT_R	1
 /*
 * System Clock Setup
@@ -319,15 +320,6 @@

 /* EEprom support */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
-#define CONFIG_SYS_I2C_MULTI_EEPROMS	1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/* Support the IVM EEprom */
-#define	CONFIG_SYS_IVM_EEPROM_ADR	0x50
-#define CONFIG_SYS_IVM_EEPROM_MAX_LEN	0x400
-#define CONFIG_SYS_IVM_EEPROM_PAGE_LEN	0x100

 /* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
 #define CONFIG_DTT_LM75		1	/* ON Semi's LM75		*/
@@ -457,47 +449,17 @@

 #define CONFIG_EXTRA_ENV_SETTINGS \
       CONFIG_KM_DEF_ENV						\
-	"netdev=eth0\0"							\
 	"rootpath=/opt/eldk/ppc_82xx\0"					\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs}"				\
-		" console=ttyS0,${baudrate}\0"				\
-	"fdt_addr=f0080000\0"						\
-	"kernel_addr=f00a0000\0"					\
-	"ramdisk_addr=f03a0000\0"					\
-	"kernel_addr_r=400000\0"					\
-	"fdt_addr_r=800000\0"						\
-	"ramdisk_addr_r=810000\0"					\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
-	"net_nfs=tftp ${kernel_addr_r} ${boot_file}; "			\
-		"tftp ${fdt_addr_r} ${fdt_file}; "			\
-		"run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
-	"fdt_file=/tftpboot/kmeter1/kmeter1.dtb\0"			\
-	"boot_file=/tftpboot/kmeter1/uImage\0"				\
+	"addcon=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 	"ramdisk_file=/tftpboot/kmeter1/uRamdisk\0"			\
-	"u-boot=/tftpboot/kmeter1/u-boot.bin\0"				\
-	"loadaddr=" MK_STR(CONFIG_SYS_LOAD_ADDR) "\0"			\
-	"load=tftp $loadaddr ${u-boot}\0"				\
-	"update=protect off " MK_STR(TEXT_BASE) " +$filesize;"		\
-		"erase " MK_STR(TEXT_BASE) " +$filesize;"		\
-		"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize;"	\
-		"protect on " MK_STR(TEXT_BASE) " +$filesize;"		\
-		"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize;"	\
-		"setenv filesize;saveenv\0"				\
-	"upd=run load update\0"						\
 	"loadram=tftp ${ramdisk_addr_r} ${ramdisk_file}\0"		\
 	"loadfdt=tftp ${fdt_addr_r} ${fdt_file}\0"			\
-	"loadkernel=tftp ${kernel_addr_r} ${boot_file}\0"		\
+	"loadkernel=tftp ${kernel_addr_r} ${bootfile}\0"		\
 	"unlock=yes\0"							\
+	"fdt_addr=F0080000\0"						\
+	"kernel_addr=F00a0000\0"					\
+	"ramdisk_addr=F03a0000\0"					\
+	"ramdisk_addr_r=F10000\0"					\
 	"EEprom_ivm=pca9547:70:9\0"					\
 	"dtt_bus=pca9547:70:a\0"					\
 	"mtdids=nor0=app \0"						\
--- a/include/configs/kmsupx4.h
+++ b/include/configs/kmsupx4.h
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2009
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MPC852T		1	/* This is a MPC852T CPU	*/
+#define CONFIG_KMSUPX4		1	/* ...on a kmsupx4 board	*/
+#define CONFIG_HOSTNAME		kmsupx4
+
+/* include common defines/options for all Keymile 8xx boards */
+#include "km8xx.h"
+
+#define CONFIG_SYS_DELAYED_ICACHE	1	/* enable ICache not before
+						 * running in RAM.
+						 */
+#endif	/* __CONFIG_H */
--- a/include/configs/mgcoge.h
+++ b/include/configs/mgcoge.h
@@ -86,39 +86,24 @@
 	"mtdparts=boot:384k(u-boot),128k(env),128k(envred),3456k(free);" \
 	"app:3m(esw0),10m(rootfs0),3m(esw1),10m(rootfs1),1m(var),5m(cfg)"

+#ifndef CONFIG_KM_DEF_ENV		/* if not set by keymile-common.h */
+#define CONFIG_KM_DEF_ENV "km-common=empty\0"
+#endif
 /*
 * Default environment settings
 */
-#define CONFIG_EXTRA_ENV_SETTINGS						\
-	"netdev=eth0\0"								\
-	"u-boot_addr=100000\0"							\
-	"kernel_addr=200000\0"							\
-	"fdt_addr=400000\0"							\
-	"rootpath=/opt/eldk-4.2/ppc_82xx\0"					\
-	"u-boot=/tftpboot/mgcoge/u-boot.bin\0"					\
-	"bootfile=/tftpboot/mgcoge/uImage\0"					\
-	"fdt_file=/tftpboot/mgcoge/mgcoge.dtb\0"				\
-	"load=tftp ${u-boot_addr} ${u-boot}\0"					\
-	"update=prot off fe000000 fe03ffff; era fe000000 fe03ffff; "		\
-		"cp.b ${u-boot_addr} fe000000 ${filesize};"			\
-		"prot on fe000000 fe03ffff\0"					\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"				\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "				\
-		"nfsroot=${serverip}:${rootpath}\0"				\
-	"addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0"	\
-	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"			\
-	"addip=setenv bootargs ${bootargs} "					\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:"			\
-		"${netmask}:${hostname}:${netdev}:off panic=1\0"		\
-	"net_nfs=tftp ${kernel_addr} ${bootfile}; "				\
-		"tftp ${fdt_addr} ${fdt_file}; run nfsargs addip addcons;"	\
-		"bootm ${kernel_addr} - ${fdt_addr}\0"				\
-	"net_self=tftp ${kernel_addr} ${bootfile}; "				\
-		"tftp ${fdt_addr} ${fdt_file}; "				\
-		"tftp ${ramdisk_addr} ${ramdisk_file}; "			\
-		"run ramargs addip; "						\
-		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"		\
-	"EEprom_ivm=pca9544a:70:4 \0"						\
+#define	CONFIG_EXTRA_ENV_SETTINGS	\
+	CONFIG_KM_DEF_ENV						\
+	"rootpath=/opt/eldk/ppc_82xx\0"					\
+	"addcon=setenv bootargs ${bootargs} "				\
+		"console=ttyCPM0,${baudrate}\0"				\
+	"mtdids=nor0=boot,nor1=app \0"					\
+	"mtdparts=mtdparts=boot:384k(u-boot),128k(env),128k(envred),"	\
+		"3456k(free);app:3m(esw0),10m(rootfs0),3m(esw1),"	\
+		"10m(rootfs1),1m(var),5m(cfg) \0"			\
+	"partition=nor1,5 \0"						\
+	"new_env=prot off FE060000 FE09FFFF; era FE060000 FE09FFFF \0" 	\
+	"EEprom_ivm=pca9544a:70:4 \0"					\
 	"mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0"				\
 	""

@@ -140,12 +125,12 @@
 #define CONFIG_SYS_RAMBOOT
 #endif

-#define CONFIG_SYS_MONITOR_LEN		(384 << 10)     /* Reserve 384KB for Monitor */
+#define CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 384KB for Monitor */

 #define CONFIG_ENV_IS_IN_FLASH

 #ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE	0x4000
+#define CONFIG_ENV_SECT_SIZE	0x20000
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 #define CONFIG_ENV_OFFSET	CONFIG_SYS_MONITOR_LEN

@@ -175,24 +160,6 @@
 			else    iop->pdat &= ~0x00020000
 #define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */

-#define CONFIG_I2C_MULTI_BUS	1
-#define CONFIG_I2C_CMD_TREE	1
-#define CONFIG_SYS_MAX_I2C_BUS		2
-#define CONFIG_SYS_I2C_INIT_BOARD	1
-#define CONFIG_I2C_MUX		1
-
-/* EEprom support */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
-#define CONFIG_SYS_I2C_MULTI_EEPROMS	1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/* Support the IVM EEprom */
-#define	CONFIG_SYS_IVM_EEPROM_ADR	0x50
-#define CONFIG_SYS_IVM_EEPROM_MAX_LEN	0x400
-#define CONFIG_SYS_IVM_EEPROM_PAGE_LEN	0x100
-
 /* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
 #define CONFIG_DTT_LM75		1	/* ON Semi's LM75		*/
 #define CONFIG_DTT_SENSORS	{0}	/* Sensor addresses		*/
--- a/include/configs/mgsuvd.h
+++ b/include/configs/mgsuvd.h
@@ -28,312 +28,11 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H

-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
 #define CONFIG_MPC866		1	/* This is a MPC866 CPU		*/
 #define CONFIG_MGSUVD		1	/* ...on a mgsuvd board	*/
 #define CONFIG_HOSTNAME		mgsuvd

-/* include common defines/options for all Keymile boards */
-#include "keymile-common.h"
-
-#define CONFIG_8xx_GCLK_FREQ		66000000
-
-#define CONFIG_SYS_SMC_UCODE_PATCH	1	/* Relocate SMC1 */
-#define CONFIG_SYS_SMC_DPMEM_OFFSET	0x1fc0
-#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#define CONFIG_SYS_SMC_RXBUFLEN	128
-#define CONFIG_SYS_MAXIDLE	10
-
-#define CONFIG_SYS_CPM_BOOTCOUNT_ADDR	0x1eb0	/* In case of SMC relocation, the
-					 * default value is not working */
-
-#define BOOTFLASH_START	F0000000
-#define CONFIG_PRAM	512	/* protected RAM [KBytes] */
-
-#define CONFIG_PREBOOT	"echo;" \
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#define CONFIG_EXTRA_ENV_SETTINGS						\
-	"netdev=eth0\0"								\
-	"addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0"	\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "				\
-		"nfsroot=${serverip}:${rootpath}\0"				\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"				\
-	"addip=setenv bootargs ${bootargs} "					\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"		\
-		":${hostname}:${netdev}:off panic=1\0"				\
-	"flash_nfs=run nfsargs addip;"						\
-		"bootm ${kernel_addr}\0"					\
-	"flash_self=run ramargs addip;"						\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"			\
-	"net_nfs=tftp ${kernel_addr} ${bootfile}; "				\
-		"tftp ${fdt_addr} ${fdt_file}; run nfsargs addip addcons;"	\
-		"bootm ${kernel_addr} - ${fdt_addr}\0"				\
-	"rootpath=/opt/eldk/ppc_8xx\0"						\
-	"bootfile=/tftpboot/mgsuvd/uImage\0"					\
-	"fdt_addr=400000\0"							\
-	"kernel_addr=200000\0"							\
-	"fdt_file=/tftpboot/mgsuvd/mgsuvd.dtb\0"				\
-	"load=tftp 200000 ${u-boot}\0"						\
-	"update=protect off f0000000 +${filesize};"				\
-		"erase f0000000 +${filesize};"					\
-		"cp.b 200000 f0000000 ${filesize};"				\
-		"protect on f0000000 +${filesize}\0"				\
-	""
-
-#undef CONFIG_RTC_MPC8xx		/* MPC866 does not support RTC	*/
-
-#define	CONFIG_TIMESTAMP		/* but print image timestmps	*/
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR		0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0xf0000000
-#define CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 384 kB for Monitor	*/
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_FLASH_SIZE		32
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */
-
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_OFFSET	CONFIG_SYS_MONITOR_LEN
-#define CONFIG_ENV_SIZE		0x04000 /* Total Size of Environment Sector	*/
-#define CONFIG_ENV_SECT_SIZE	0x20000 /* Total Size of Environment Sector	*/
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-#define CONFIG_ENV_BUFFER_PRINT		1
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#define CONFIG_SYS_SYPCR	0xffffff89
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SIUMCR	0x00610480
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	0x01800000
-#define CONFIG_SYS_SCCR	0x01800000
-
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0xf0000000	/* FLASH bank #0	*/
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
-
-/*
- * FLASH timing: Default value of OR0 after reset
- */
-#define CONFIG_SYS_OR0_PRELIM	0xfe000954
-#define CONFIG_SYS_BR0_PRELIM	0xf0000401
-
-/*
- * BR1 and OR1 (SDRAM)
- *
- */
-#define SDRAM_BASE1_PRELIM	0x00000000	/* SDRAM bank #0	*/
-#define SDRAM_MAX_SIZE		(64 << 20)	/* max 64 MB per bank	*/
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
-
-#define CONFIG_SYS_OR1_PRELIM	0xfc000800
-#define CONFIG_SYS_BR1_PRELIM	(0x000000C0 | 0x01)
-
-#define CONFIG_SYS_MPTPR	0x0200
-/* PTB=16, AMB=001, FIXME 1 RAS precharge cycles, 1 READ loop cycle (not used),
-   1 Write loop Cycle (not used), 1 Timer Loop Cycle */
-#define CONFIG_SYS_MBMR	0x10964111
-#define CONFIG_SYS_MAR		0x00000088
-
-/*
- * 4096	Rows from SDRAM example configuration
- * 1000	factor s -> ms
- * 64	PTP (pre-divider from MPTPR) from SDRAM example configuration
- * 4	Number of refresh cycles per period
- * 64	Refresh cycle in ms per number of rows
- */
-#define CONFIG_SYS_PTA_PER_CLK	((4096 * 64 * 1000) / (4 * 64))
-
-/* GPIO/PIGGY on CS3 initialization values
-*/
-#define CONFIG_SYS_PIGGY_BASE	(0x30000000)
-#define CONFIG_SYS_OR3_PRELIM	(0xfe000d24)
-#define CONFIG_SYS_BR3_PRELIM	(0x30000401)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#define CONFIG_SCC3_ENET
-#define CONFIG_ETHPRIME		"SCC ETHERNET"
-#define CONFIG_HAS_ETH0
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
-#define OF_STDOUT_PATH		"/soc/cpm/serial@a80"
-
-/* enable I2C and select the hardware/software driver */
-#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
-#define	CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
-#define CONFIG_SYS_I2C_SPEED		50000	/* I2C speed and slave address	*/
-#define CONFIG_SYS_I2C_SLAVE		0x7F
-#define I2C_SOFT_DECLARATIONS
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define I2C_BASE_DIR	((u16 *)(CONFIG_SYS_PIGGY_BASE + 0x04))
-#define I2C_BASE_PORT	((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x09))
-
-#define SDA_BIT		0x40
-#define SCL_BIT		0x80
-#define SDA_CONF	0x1000
-#define SCL_CONF	0x2000
-
-#define I2C_ACTIVE	do {} while (0)
-#define I2C_TRISTATE	do {} while (0)
-#define I2C_READ	((in_8(I2C_BASE_PORT) & SDA_BIT) == SDA_BIT)
-#define I2C_SDA(bit)	if(bit) { \
-				clrbits(be16, I2C_BASE_DIR, SDA_CONF); \
-			} else { \
-				clrbits(8, I2C_BASE_PORT, SDA_BIT); \
-				setbits(be16, I2C_BASE_DIR, SDA_CONF); \
-			}
-#define I2C_SCL(bit)	if(bit) { \
-				clrbits(be16, I2C_BASE_DIR, SCL_CONF); \
-			} else { \
-				clrbits(8, I2C_BASE_PORT, SCL_BIT); \
-				setbits(be16, I2C_BASE_DIR, SCL_CONF); \
-			}
-#define I2C_DELAY	udelay(50)	/* 1/4 I2C clock duration */
-
-#define CONFIG_I2C_MULTI_BUS	1
-#define CONFIG_I2C_CMD_TREE	1
-#define CONFIG_SYS_MAX_I2C_BUS		2
-#define CONFIG_SYS_I2C_INIT_BOARD	1
-#define CONFIG_I2C_MUX		1
-
-/* EEprom support */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
-#define CONFIG_SYS_I2C_MULTI_EEPROMS	1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/* Support the IVM EEprom */
-#define	CONFIG_SYS_IVM_EEPROM_ADR	0x50
-#define CONFIG_SYS_IVM_EEPROM_MAX_LEN	0x400
-#define CONFIG_SYS_IVM_EEPROM_PAGE_LEN	0x100
-
-/* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
-#define CONFIG_DTT_LM75		1	/* ON Semi's LM75		*/
-#define CONFIG_DTT_SENSORS	{0, 2, 4, 6}	/* Sensor addresses		*/
-#define CONFIG_SYS_DTT_MAX_TEMP	70
-#define CONFIG_SYS_DTT_LOW_TEMP	-30
-#define CONFIG_SYS_DTT_HYSTERESIS	3
-#define CONFIG_SYS_DTT_BUS_NUM		(CONFIG_SYS_MAX_I2C_BUS)
-
-#define MTDIDS_DEFAULT		"nor0=app"
-#define MTDPARTS_DEFAULT ( \
-	"mtdparts=app:384k(u-boot),128k(env),128k(envred),128k(free),"	\
-	"1536k(esw0),8704k(rootfs0),1536k(esw1),2432k(rootfs1),640k(var),768k(cfg)")
+/* include common defines/options for all Keymile 8xx boards */
+#include "km8xx.h"

 #endif	/* __CONFIG_H */
--- a/include/configs/netstar.h
+++ b/include/configs/netstar.h
@@ -64,12 +64,12 @@
 */
 #define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define PHYS_FLASH_1_SIZE	(1 * 1024 * 1024)
+#define PHYS_FLASH_1_SIZE		(1 * 1024 * 1024)
 #define CONFIG_SYS_MAX_FLASH_SECT	19
 #define CONFIG_SYS_FLASH_ERASE_TOUT	(5*CONFIG_SYS_HZ) /* in ticks */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	(5*CONFIG_SYS_HZ)

-#define CONFIG_SYS_MONITOR_BASE	PHYS_FLASH_1
+#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)

 /*
@@ -97,32 +97,27 @@
 /*
 * Hardware drivers
 */
-#define CONFIG_DRIVER_SMC91111
-#define CONFIG_SMC91111_BASE	0x04000300
-
-/*
- * NS16550 Configuration
- */
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
 #define CONFIG_SYS_NS16550_CLK		(CONFIG_XTAL_FREQ)	/* can be 12M/32Khz or 48Mhz  */
-#define CONFIG_SYS_NS16550_COM1	OMAP1510_UART1_BASE	/* uart1 */
+#define CONFIG_SYS_NS16550_COM1		OMAP1510_UART1_BASE	/* uart1 */

-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		115200
+#define CONFIG_DRIVER_SMC91111
+#define CONFIG_SMC91111_BASE		0x04000300
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x04000000 + (2 << 23)
+#define NAND_ALLOW_ERASE_ALL		1
+
+
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

 /*#define CONFIG_SKIP_RELOCATE_UBOOT*/
 /*#define CONFIG_SKIP_LOWLEVEL_INIT */

-/*
- * NAND flash
- */
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_SYS_NAND_BASE	0x04000000 + (2 << 23)
-#define NAND_ALLOW_ERASE_ALL	1
-
 /*
 * partitions (mtdparts command line support)
 */
@@ -136,7 +131,6 @@
 /*
 * Command line configuration.
 */
-
 #define CONFIG_CMD_BDI
 #define CONFIG_CMD_BOOTD
 #define CONFIG_CMD_DHCP
--- a/include/configs/pcu_e.h
+++ b/include/configs/pcu_e.h
@@ -246,6 +246,9 @@
 */
 #define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_DELAYED_ICACHE	1	/* enable ICache not before
+						 * running in RAM.
+						 */

 /*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
--- a/lib_ppc/board.c
+++ b/lib_ppc/board.c
@@ -736,8 +736,7 @@ void board_init_r (gd_t *id, ulong dest_addr)

 	WATCHDOG_RESET();

-#if defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || \
-	defined (CONFIG_FLAGADM) || defined(CONFIG_MPC83XX)
+#if defined(CONFIG_SYS_DELAYED_ICACHE) || defined(CONFIG_MPC83XX)
 	icache_enable ();	/* it's time to enable the instruction cache */
 #endif
Author	SHA1	Message	Date
Wolfgang Denk	e60beb13cf	Prepare 2009.03 Update CHANGELOG Signed-off-by: Wolfgang Denk <wd@denx.de>	2009-03-21 22:04:41 +01:00
Vivek Kutal	9e78dae2b2	Replaced endpoint numbers with appropriate macros in usbtty.c. Signed-off-by: Vivek Kutal <vivek.kutal@azingo.com> Signed-off-by: Remy Bohmer <linux@bohmer.net>	2009-03-21 10:40:24 +01:00
Jon Smirl	a43ea5cc6d	.gitignore for generated files in api_examples directory Add .gitignore for generated files in api_examples directory Signed-off-by: Jon Smirl <jonsmirl@gmail.com> Signed-off-by: Wolfgang Denk <wd@denx.de>	2009-03-20 22:37:38 +01:00
Nobuhiro Iwamatsu	40281a9ca2	net: sh_eth: Remove sh_eth_reset() from halt function sh_eth_reset is function to reset Ether IP. The MAC address is stored in IP, but it is initialized by this function. OS (e.g. Linux Kernel) can not use this device when initialized. This revises this problem. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>	2009-03-20 22:16:36 +01:00
Anatolij Gustschin	f8853d105d	ppc4xx: Fix bug in PCI outbound map configuration for canyonlands PCI outbound address map configuration doesn't match the PCI memory address range covered by appropriate TLB entry configuration for canyonlands causing machine check exceptions while accessing PCI memory regions. This patch provides a fix for this issue. Kazuaki Ichinohe observed and reported this issue while testing display output with PCI ATI video card on canyonlands. Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>	2009-03-20 12:58:31 +01:00
Richard Retanubun	7a88601a34	CFI: geometry reversal for STMicro M29W320DT Follow up to the flash_fixup_stm to fix geometry reversal on STMicro M29W320ET flash chip. The M29W320DT has 4 erase region. Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com> Signed-off-by: Stefan Roese <sr@denx.de>	2009-03-19 15:00:32 +01:00
Mike Frysinger	069f4364d8	smc911x_eeprom: update register API The smc911x driver changed the naming convention for its register funcs, so update the eeprom code accordingly. Signed-off-by: Mike Frysinger <vapier@gentoo.org> CC: Ben Warren <biggerbadderben@gmail.com>	2009-03-19 00:02:57 +01:00
Grzegorz Bernacki	6a397ef0e6	mpc52xx: Get rid of board-specific #ifdef's in cpu/mpc5xxx/ide.c Total5200 and digsy MTC use I2C port 2 pins as a ATA chip select. To avoid adding board-specific ifdefs to cpu/mpc5xxx/ide.c new define CONFIG_SYS_ATA_CS_ON_I2C2 was introduced. It is used by Total5200 and will be used by digsy MTC and other boards with ATA CS on I2C pins. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>	2009-03-18 20:54:56 +01:00
Heiko Schocher	1b6275dfb1	8xx: add support for new keymile kmsupx4 board. This patch adds support for the kmsupx4 board from Keymile, based on a Freescale MPC852T CPU - serial console on SMC1 - 32 MB SDRAM - 32 MB NOR Flash - Ethernet over SCC3 - I2C Bitbang Signed-off-by: Heiko Schocher <hs@denx.de>	2009-03-18 20:50:05 +01:00
Heiko Schocher	d044954fe2	8xx, mgsuvd: rename board to a more generic name renaming the "mgsuvd" board port into "km8xx", because there come more similar boards from keymile. Compiling the mgsuvd board with "make mgsuvd_config" remains. Signed-off-by: Heiko Schocher <hs@denx.de>	2009-03-18 20:50:04 +01:00
Heiko Schocher	18b2f35bde	8xx, mgsuvd: Coding Style cleanup config file Signed-off-by: Heiko Schocher <hs@denx.de>	2009-03-18 20:49:58 +01:00
Heiko Schocher	364123db67	powerpc: common updates for keymile boards - added to keymile-common.h: - bootcount support - COMMAND HISTORY - CONFIG_AUTO_COMPLETE - CONFIG_SYS_FLASH_PROTECTION - JFFS2 support - CONFIG_VERSION_VARIABLE - extracted common I2C settings for all boards - common default environment settings summarized Signed-off-by: Heiko Schocher <hs@denx.de>	2009-03-18 20:49:04 +01:00
Heiko Schocher	506f391888	8xx, icache: enabling ICache not before running from RAM with the new CONFIG_SYS_DELAYED_ICACHE config option, ICache is not enabled before code runs from RAM. Signed-off-by: Heiko Schocher <hs@denx.de>	2009-03-18 20:48:29 +01:00
Heiko Schocher	cabf7b9c83	82xx, mgcoge: fix environment sector size Size of one environment sector is 0x20000. Signed-off-by: Heiko Schocher <hs@denx.de>	2009-03-18 20:47:06 +01:00
Ladislav Michl	27057d416c	NetStar: config reindentation Fix indentation broken by symbol renames. "Sort" driver related definitons. Signed-off-by: Ladislav Michl <ladis@linux-mips.org>	2009-03-18 20:41:52 +01:00
Wolfgang Denk	efb47346d4	Merge branch 'master' of git://git.denx.de/u-boot-coldfire	2009-03-18 00:40:57 +01:00
Wolfgang Denk	efa0215228	Merge branch 'master' of git://git.denx.de/u-boot-nand-flash	2009-03-18 00:39:10 +01:00
TsiChung Liew	8d8235f84d	ColdFire: Fix incorrect definition Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>	2009-03-17 15:58:37 -06:00
TsiChung Liew	9017d9325a	ColdFire: Fix M5329EVB and M5373EVB nand issue The Nand flash was unable to read and write properly due to Nand Chip Select (nCE) setup was in reverse order. Also, increase the Nand time out value to 60. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>	2009-03-17 15:58:37 -06:00
TsiChung Liew	42b68af106	ColdFire: PLATFORM_CPPFLAGS updates for new compiler Update PLATFORM_CPPFLAGS to accept 4.3.x version of ColdFire compiler. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>	2009-03-17 15:58:37 -06:00
TsiChung Liew	d6e4baf499	ColdFire: Provide gzip image size V2 & V3 platforms Default gzip bootm size is 8MB. Some platforms require more than 8MB Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>	2009-03-17 15:58:37 -06:00
TsiChung Liew	c3a9e63742	ColdFire: Fix M54451 serial boot dram setup The serial boot dram extended/standard mode register was not setup and was using default DRAM setup causing the U-boot was unstable to boot up in serial mode. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>	2009-03-17 15:58:37 -06:00
arun c	32d11d5815	Coldfire: XL Bus minor fixes According to coldfire manual data timeout > address time out also use correct macro to program XARB_CFG Signed-off-by: Arun C <arunedarath@mistralsolutions.com>	2009-03-17 15:58:07 -06:00
Scott Wood	65d8bc94d8	NAND: Have nboot accept .e and .i as legacy no-ops. This was intended to happen before, but a trivial bug prevented it. Signed-off-by: Scott Wood <scottwood@freescale.com>	2009-03-17 12:06:04 -05:00
Ladislav Michl	0987505540	NAND: Make nboot skip bad blocks nboot command currently does not skip bad blocks and gives read error when loading image stored over bad block. With patch applied, nboot works as expected: Device 0 bad blocks: 00780000 014a0000 02000000 02cc0000 04aa0000 Loading from NAND 128MiB 3,3V 8-bit, offset 0x2c00000 Image Name: Linux-2.6.22-omap1 Created: 2008-11-20 23:44:32 UTC Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 1052520 Bytes = 1 MB Load Address: 10008000 Entry Point: 10008000 Skipping bad block 0x02cc0000 Automatic boot of image at addr 0x10400000 ... ... Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Scott Wood <scottwood@freescale.com>	2009-03-17 12:04:22 -05:00
Stefan Roese	0b2f38fe3c	ppc4xx: lwmon5: Only use one CS (rank) in DDR2 configuration This patch fixes a problem spotted by Mikhail Zolotaryov on Sequoia with the DDR2 configuration to only use one CS (rank). As this code is most likely copied from the original Sequoia version, this error was copied as well. This patch also removes some dead code. Signed-off-by: Stefan Roese <sr@denx.de>	2009-03-17 10:52:36 +01:00
Stefan Roese	9199b9cc8f	ppc4xx: PMC440: Only use one CS (rank) in DDR2 configuration This patch fixes a problem spotted by Mikhail Zolotaryov on Sequoia with the DDR2 configuration to only use one CS (rank). As this code is most likely copied from the original Sequoia version, this error was copied as well. Signed-off-by: Stefan Roese <sr@denx.de>	2009-03-17 10:52:36 +01:00
Mikhail Zolotaryov	ee86fd15e1	Fix AMCC Sequoia board DDR memory configuration Sequoia board schematics (DES0211_11_SCH_11.pdf, page 5, unit U1D) specifies that BankSel#1 is not connected, while bootloader memory configuration is (board/amcc/sequoia/sdram.c): mtsdram(DDR0_10, 0x00000300); i.e. both Chip Selects used - not correct. If we change to correct value here: mtsdram(DDR0_10, 0x00000100); memory is accessible OK also. Signed-off-by: Mikhail Zolotaryov <lebon@lebon.org.ua> Signed-off-by: Stefan Roese <sr@denx.de>	2009-03-17 10:52:36 +01:00