Prepare v2009.06

Update CHANGELOG, fix minor coding stylke issue. Update Makefile.

Signed-off-by: Wolfgang Denk <wd@denx.de>

CHANGELOG

@@ -1,3 +1,128 @@
+commit c3147c1762f8caf99649051116a2411bdf887c10
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Sun Jun 14 20:31:36 2009 +0200
+
+    Revert "SMC911x driver fixed for NFS boot"
+
+    This reverts commit ca9c8a1e10fac01e6a1129f82a7ce18bd818fa43,
+    which causes compile warnings ("large integer implicitly truncated
+    to unsigned type") on all systems that use this driver. The warning
+    results from passing long constants (TX_CFG, RX_CFG) into
+    smc911x_set_mac_csr() which is declared to accept "unsigned
+    character" arguments only.
+
+    Being close to a release, with nobody available to actually test the
+    code or the suggested fixes, it seems better to revert the patch.
+
+commit e7563aff174f77aa61dab1ef5d9b47bebaa43702
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Thu Jun 11 23:42:35 2009 -0500
+
+    fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT
+
+    The ddr code computes most things as 64-bit quantities and had some places
+    in the middle that it was using phy_addr_t and phys_size_t.
+
+    Instead we use unsigned long long through out and only at the last stage of
+    setting the LAWs and reporting the amount of memory to the board code do we
+    truncate down to what we can cover via phys_size_t.
+
+    This has the added benefit that the DDR controller itself is always setup
+    the same way regardless of how much memory we have.  Its only the LAW
+    setup that limits what is visible to the system.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit d4b130dc80761b430dc5b410159cd158fca1a348
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Thu Jun 11 23:40:34 2009 -0500
+
+    85xx: Use print_size to report amount of memory not mapped by TLBs
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 6e2aebc33fa740c068fe28d40eaf0319b7c7287e
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date:	Wed May 20 12:30:42 2009 -0400
+
+    85xx: Add README for MPC8569MDS
+
+    Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit b2aab386e957ba684d4f2a466bfaa91770e5058a
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date:	Wed May 20 12:30:33 2009 -0400
+
+    85xx: Add UART1 support for MPC8569MDS
+
+    MPC8569 UART1 signals are muxed with PortF bit[9-12], we need to define
+    those pins before using UART1.
+
+    Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 399b53cbab0b377ac4c5c16c19c6e41b68a9c719
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date:	Wed May 20 12:30:32 2009 -0400
+
+    85xx: Add PIB support at CS4/CS5 for MPC8569MDS
+
+    Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+    Signed-off-by: Yu Liu <Yu.Liu@freescale.com>
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit fb27949059f1bc84381a6216a819090f0cdbaa70
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date:	Thu Jun 4 16:12:39 2009 -0400
+
+    85xx: Fix some settings for MPC8569MDS board
+
+    - Increase the size of malloc to 512KB because MPC8569MDS needs more memory for
+    malloc to support up to eight Ethernet interfaces.
+    - Move Environment address out of uboot thus the saved environment variables
+    will not be erased after u-boot is re-programmed.
+
+    Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit c7f60fd29f2d638d080cdf1a49ad985b85f9429d
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date:	Wed May 20 12:30:30 2009 -0400
+
+    85xx: Fix MURAM size for MPC8569
+
+    MPC8569 has 128K bytes MURAM.
+
+    Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit a53c997dd7fc858f2a27f5a47b200567b9343ae5
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Fri May 22 20:23:51 2009 +0200
+
+    at91/cpu.c: add missing Copyright & GPL header
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit aa446a591aca46ef2b53cc6598ea8091feb45444
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date:	Sun Jun 7 21:45:16 2009 +0900
+
+    apollon: Fix a OBJCFLAGS typo
+
+    Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
+
+commit 580611cb0932143fc2d7a735cfa9ce1ef34d6002
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Wed Jun 10 00:19:28 2009 +0200
+
+    Prepare 2009.06-rc3
+
+    Update CHANGELOG
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
 commit 3a76ab5c166d5956885f803ce975e7151cc0ca0e
 Author: Wolfgang Denk <wd@denx.de>
 Date:	Wed Jun 10 00:15:11 2009 +0200
@@ -190,6 +315,26 @@ Date:	Sun May 3 12:11:40 2009 +0200
     Signed-off-by: Remy Bohmer <linux@bohmer.net>
     Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
 
+commit 3c9b1ee17e19bd6d80344678d41a85e52b0be713
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Fri Jun 5 14:11:33 2009 -0500
+
+    mpc83xx: don't set SICRH_TSOBI1 to RMII/RTBI operation
+
+    In GMII mode (which operates at 3.3V) both SICRH TSEC1/2 output buffer
+    impedance bits should be clear, i.e., SICRH[TSIOB1] = 0 and SICRH[TSIOB2] = 0.
+    SICRH[TSIOB1] was erroneously being set high.
+
+    U-Boot always operated this PHY interface in GMII mode.  It is assumed this
+    was missed in the clean up by the original board porters, and copied along
+    to the TQM and sbc boards.
+
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+    Acked-by: Ira Snyder <iws@ovro.caltech.edu>
+    Reviewed-by: David Hawkins <dwh@ovro.caltech.edu>
+    Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com>
+    CC: Dave Liu <DaveLiu@freescale.com>
+
 commit 2c0234fa79122a5aa77c4e17c33eb2fe184b61a7
 Author: Daniel Mack <daniel@caiaq.de>
 Date:	Wed Apr 8 13:23:37 2009 +0200

Makefile

@@ -24,7 +24,7 @@
 VERSION = 2009
 PATCHLEVEL = 06
 SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION =
 ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 else

board/freescale/mpc8569mds/mpc8569mds.c

@@ -77,6 +77,12 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
 	{2,  3, 2, 0, 1}, /* ENET2_GRXCLK              */
 	{2,  2, 1, 0, 2}, /* ENET2_GTXCLK              */
 
+	/* UART1 is muxed with QE PortF bit [9-12].*/
+	{5, 12, 2, 0, 3}, /* UART1_SIN */
+	{5, 9,  1, 0, 3}, /* UART1_SOUT */
+	{5, 10, 2, 0, 3}, /* UART1_CTS_B */
+	{5, 11, 1, 0, 2}, /* UART1_RTS_B */
+
 	{0,  0, 0, 0, QE_IOP_TAB_END} /* END of table */
 };
 

cpu/arm926ejs/at91/cpu.c

@@ -1,3 +1,26 @@
+/*
+ * (C) Copyright 2009
+ * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
 #include <config.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/at91_pmc.h>

cpu/mpc85xx/tlb.c

@@ -165,7 +165,7 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
 	}
 
 	if (memsize)
-		printf("%lldM left unmapped\n", memsize >> 20);
+		print_size(memsize, " left unmapped\n");
 
 	/*
 	 * Confirm that the requested amount of memory was mapped.

cpu/mpc8xxx/ddr/ctrl_regs.c

@@ -1199,8 +1199,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 
 	/* Chip Select Memory Bounds (CSn_BNDS) */
 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-		phys_size_t sa = 0;
-		phys_size_t ea = 0;
+		unsigned long long ea = 0, sa = 0;
 
 		if (popts->ba_intlv_ctl && (i > 0) &&
 			((popts->ba_intlv_ctl & 0x60) != FSL_DDR_CS2_CS3 )) {

cpu/mpc8xxx/ddr/ddr.h

@@ -54,7 +54,7 @@ typedef struct {
 #define STEP_PROGRAM_REGS            (1 << 6)
 #define STEP_ALL                     0xFFF
 
-extern phys_size_t
+extern unsigned long long
 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step);
 
 extern const char * step_to_string(unsigned int step);

cpu/mpc8xxx/ddr/ddr1_dimm_params.c

@@ -33,10 +33,10 @@
  * 2 or 5 bits off and shifting them up to the top.
  */
 
-static phys_size_t
+static unsigned long long
 compute_ranksize(unsigned int mem_type, unsigned char row_dens)
 {
-	phys_size_t bsize;
+	unsigned long long bsize;
 
 	/* Bottom 2 bits up to the top. */
 	bsize = ((row_dens >> 2) | ((row_dens & 3) << 6));

cpu/mpc8xxx/ddr/ddr2_dimm_params.c

@@ -32,10 +32,10 @@
  * 2 or 5 bits off and shifting them up to the top.
  *
  */
-static phys_size_t
+static unsigned long long
 compute_ranksize(unsigned int mem_type, unsigned char row_dens)
 {
-	phys_size_t bsize;
+	unsigned long long bsize;
 
 	/* Bottom 5 bits up to the top. */
 	bsize = ((row_dens >> 5) | ((row_dens & 31) << 3));

cpu/mpc8xxx/ddr/ddr3_dimm_params.c

@@ -52,10 +52,10 @@
  * 	011		32bits
  *
  */
-static phys_size_t
+static unsigned long long
 compute_ranksize(const ddr3_spd_eeprom_t *spd)
 {
-	phys_size_t bsize;
+	unsigned long long bsize;
 
 	int nbit_sdram_cap_bsize = 0;
 	int nbit_primary_bus_width = 0;

cpu/mpc8xxx/ddr/main.c

@@ -215,9 +215,7 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
 	}
 
 	if (*memctl_interleaving) {
-		phys_addr_t addr;
-		phys_size_t total_mem_per_ctlr = 0;
-
+		unsigned long long addr, total_mem_per_ctlr = 0;
 		/*
 		 * If interleaving between memory controllers,
 		 * make each controller start at a base address
@@ -235,14 +233,13 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
 
 		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 			addr = 0;
-			pinfo->common_timing_params[i].base_address =
-						(phys_addr_t)addr;
+			pinfo->common_timing_params[i].base_address = 0ull;
 			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 				unsigned long long cap
 					= pinfo->dimm_params[i][j].capacity;
 
 				pinfo->dimm_params[i][j].base_address = addr;
-				addr += (phys_addr_t)(cap >> dbw_cap_adj[i]);
+				addr += cap >> dbw_cap_adj[i];
 				total_mem_per_ctlr += cap >> dbw_cap_adj[i];
 			}
 		}
@@ -252,18 +249,17 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
 		 * Simple linear assignment if memory
 		 * controllers are not interleaved.
 		 */
-		phys_size_t cur_memsize = 0;
+		unsigned long long cur_memsize = 0;
 		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
-			phys_size_t total_mem_per_ctlr = 0;
+			u64 total_mem_per_ctlr = 0;
 			pinfo->common_timing_params[i].base_address =
-						(phys_addr_t)cur_memsize;
+						cur_memsize;
 			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 				/* Compute DIMM base addresses. */
 				unsigned long long cap =
 					pinfo->dimm_params[i][j].capacity;
-
 				pinfo->dimm_params[i][j].base_address =
-					(phys_addr_t)cur_memsize;
+					cur_memsize;
 				cur_memsize += cap >> dbw_cap_adj[i];
 				total_mem_per_ctlr += cap >> dbw_cap_adj[i];
 			}
@@ -275,13 +271,13 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
 	return 0;
 }
 
-phys_size_t
+unsigned long long
 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step)
 {
 	unsigned int i, j;
 	unsigned int all_controllers_memctl_interleaving = 0;
 	unsigned int all_controllers_rank_interleaving = 0;
-	phys_size_t total_mem = 0;
+	unsigned long long total_mem = 0;
 
 	fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
 	common_timing_params_t *timing_params = pinfo->common_timing_params;
@@ -424,15 +420,6 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step)
 			}
 		}
 
-#if !defined(CONFIG_PHYS_64BIT)
-		/* Check for 4G or more with a 32-bit phys_addr_t.  Bad. */
-		if (max_end >= 0xff) {
-			printf("This U-Boot only supports < 4G of DDR\n");
-			printf("You could rebuild it with CONFIG_PHYS_64BIT\n");
-			return CONFIG_MAX_MEM_MAPPED;
-		}
-#endif
-
 		total_mem = 1 + (((unsigned long long)max_end << 24ULL)
 				    | 0xFFFFFFULL);
 	}
@@ -450,7 +437,7 @@ phys_size_t fsl_ddr_sdram(void)
 {
 	unsigned int i;
 	unsigned int memctl_interleaved;
-	phys_size_t total_memory;
+	unsigned long long total_memory;
 	fsl_ddr_info_t info;
 
 	/* Reset info structure. */
@@ -515,7 +502,17 @@ phys_size_t fsl_ddr_sdram(void)
 		}
 	}
 
-	debug("total_memory = %llu\n", (u64)total_memory);
+	debug("total_memory = %llu\n", total_memory);
+
+#if !defined(CONFIG_PHYS_64BIT)
+	/* Check for 4G or more.  Bad. */
+	if (total_memory >= (1ull << 32)) {
+		printf("Detected %lld MB of memory\n", total_memory >> 20);
+		printf("This U-Boot only supports < 4G of DDR\n");
+		printf("You could rebuild it with CONFIG_PHYS_64BIT\n");
+		total_memory = CONFIG_MAX_MEM_MAPPED;
+	}
+#endif
 
 	return total_memory;
 }

cpu/mpc8xxx/ddr/util.c

@@ -64,6 +64,9 @@ __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
 			   unsigned int memctl_interleaved,
 			   unsigned int ctrl_num)
 {
+	unsigned long long base = memctl_common_params->base_address;
+	unsigned long long size = memctl_common_params->total_mem;
+
 	/*
 	 * If no DIMMs on this controller, do not proceed any further.
 	 */
@@ -71,6 +74,13 @@ __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
 		return;
 	}
 
+#if !defined(CONFIG_PHYS_64BIT)
+	if (base >= CONFIG_MAX_MEM_MAPPED)
+		return;
+	if ((base + size) >= CONFIG_MAX_MEM_MAPPED)
+		size = CONFIG_MAX_MEM_MAPPED - base;
+#endif
+
 	if (ctrl_num == 0) {
 		/*
 		 * Set up LAW for DDR controller 1 space.
@@ -78,16 +88,12 @@ __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
 		unsigned int lawbar1_target_id = memctl_interleaved
 			? LAW_TRGT_IF_DDR_INTRLV : LAW_TRGT_IF_DDR_1;
 
-		if (set_ddr_laws(memctl_common_params->base_address,
-				memctl_common_params->total_mem,
-				lawbar1_target_id) < 0) {
+		if (set_ddr_laws(base, size, lawbar1_target_id) < 0) {
 			printf("ERROR\n");
 			return ;
 		}
 	} else if (ctrl_num == 1) {
-		if (set_ddr_laws(memctl_common_params->base_address,
-				memctl_common_params->total_mem,
-				LAW_TRGT_IF_DDR_2) < 0) {
+		if (set_ddr_laws(base, size, LAW_TRGT_IF_DDR_2) < 0) {
 			printf("ERROR\n");
 			return ;
 		}

doc/README.mpc8569mds

@@ -0,0 +1,77 @@
+Overview
+--------
+MPC8569MDS is composed of two boards - PB (Processor Board) and PIB (Platform
+I/O Board). The mpc8569 PowerTM processor is mounted on PB board.
+
+Building U-boot
+-----------
+	make MPC8569MDS_config
+	make
+
+Memory Map
+----------
+0x0000_0000   0x7fff_ffff     DDR                     2G
+0xa000_0000   0xbfff_ffff     PCIe MEM                512MB
+0xe000_0000   0xe00f_ffff     CCSRBAR                 1M
+0xe280_0000   0xe2ff_ffff     PCIe I/O                8M
+0xc000_0000   0xdfff_ffff     SRIO                    512MB
+0xf000_0000   0xf3ff_ffff     SDRAM                   64MB
+0xf800_0000   0xf800_7fff     BCSR                    32KB
+0xf800_8000   0xf800_ffff     PIB (CS4)               32KB
+0xf801_0000   0xf801_7fff     PIB (CS5)               32KB
+0xfe00_0000   0xffff_ffff     Flash                   32MB
+
+
+Flashing u-boot Images
+---------------
+
+Use the following commands to program u-boot image into flash:
+
+	=> tftp 1000000 u-boot.bin
+	=> protect off all
+	=> erase fff80000 ffffffff
+	=> cp.b 1000000 fff80000 80000
+
+
+Setting the correct MAC addresses
+-----------------------
+The command - "mac", is introduced to set on-board system EEPROM in the format
+defined in board/freescale/common/sys_eeprom.c. we must set all 8 MAC
+addresses for the MPC8569MDS's 8 Ethernet ports and save it by "mac save" when
+we first get the board. The commands are as follows:
+	=> mac i NXID	/* Set NXID to this EEPROM */
+	=> mac e 01	/* Set Errata, this value is not defined by hardware
+			   designer, we can set whatever we want */
+	=> mac n a0	/* Set Serial Number. This is not defined by hardware
+			   designer, we can set whatever we want */
+	=> mac date 090512080000  /* Set the date in YYMMDDhhmmss format */
+
+	=> mac p 8	/* Set the number of mac ports, it should be 8 */
+	=> mac 0 xx:xx:xx:xx:xx:xx  /* xx:xx:xx:xx:xx:xx should be the real mac
+				       address, you can refer to the value on
+				       the sticker of the rear side of the board
+				     */
+	.....
+	=> mac 7 xx:xx:xx:xx:xx:xx
+	=> mac read
+	=> mac save
+
+After resetting the board, the ethxaddrs will be filled with the mac addresses
+if such environment variables are blank(never been set before). If the ethxaddr
+has been set but we want to update it, we can use the following commands:
+	=> setenv ethxaddr	/* x = "none",1,2,3,4,5,6,7 */
+	=> save
+	=> reset
+
+
+Programming the ucode to flash
+---------------------------------
+MPC8569 doesn't have ROM in QE, so we must upload the microcode(ucode) to QE's
+IRAM so that the QE can work. The ucode binary can be downloaded from
+http://opensource.freescale.com/firmware/, and it must be programmed to
+the address 0xfff0000 in the flash. Otherwise, the QE can't work and uboot
+hangs at "Net:"
+
+
+Please note the above two steps(setting mac addresses and programming ucode) are
+very important to get the board booting up and working properly.

drivers/net/smc911x.c

@@ -117,27 +117,6 @@ static int smc911x_phy_reset(void)
 	return 0;
 }
 
-static void smc911x_shutdown(void)
-{
-	unsigned int cr;
-
-	/* Turn of Rx and TX */
-	cr = smc911x_get_mac_csr(MAC_CR);
-	cr &= ~(MAC_CR_TXEN | MAC_CR_RXEN | MAC_CR_HBDIS);
-	smc911x_set_mac_csr(MAC_CR, cr);
-
-	/* Stop Transmission */
-	cr = smc911x_get_mac_csr(TX_CFG);
-	cr &= ~(TX_CFG_STOP_TX);
-	smc911x_set_mac_csr(TX_CFG, cr);
-	/* Stop receiving packets */
-	cr = smc911x_get_mac_csr(RX_CFG);
-	cr &= ~(RX_CFG_RXDOFF);
-	smc911x_set_mac_csr(RX_CFG, cr);
-
-}
-
-
 static void smc911x_phy_configure(void)
 {
 	int timeout;
@@ -246,7 +225,7 @@ int eth_send(volatile void *packet, int length)
 
 void eth_halt(void)
 {
-	smc911x_shutdown();
+	smc911x_reset();
 }
 
 int eth_rx(void)

include/asm-ppc/immap_qe.h

@@ -582,9 +582,12 @@ typedef struct qe_immap {
 	u8 res14[0x300];
 	u8 res15[0x3A00];
 	u8 res16[0x8000];	/* 0x108000 -  0x110000 */
-#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
+#if defined(CONFIG_MPC8568)
 	u8 muram[0x10000];	/* 0x1_0000 -  0x2_0000 Multi-user RAM */
 	u8 res17[0x20000];	/* 0x2_0000 -  0x4_0000 */
+#elif defined(CONFIG_MPC8569)
+	u8 muram[0x20000];	/* 0x1_0000 -  0x3_0000 Multi-user RAM */
+	u8 res17[0x10000];	/* 0x3_0000 -  0x4_0000 */
 #else
 	u8 muram[0xC000];	/* 0x110000 -  0x11C000 Multi-user RAM */
 	u8 res17[0x24000];	/* 0x11C000 -  0x140000 */
@@ -594,8 +597,10 @@ typedef struct qe_immap {
 
 extern qe_map_t *qe_immr;
 
-#if defined(CONFIG_MPC8568) || defined(CONFIG_MPC8569)
+#if defined(CONFIG_MPC8568)
 #define QE_MURAM_SIZE		0x10000UL
+#elif defined(CONFIG_MPC8569)
+#define QE_MURAM_SIZE		0x20000UL
 #elif defined(CONFIG_MPC8360)
 #define QE_MURAM_SIZE		0xc000UL
 #elif defined(CONFIG_MPC832X)

include/configs/MPC8349EMDS.h

@@ -598,7 +598,7 @@
 #define CONFIG_SYS_SCCR_TSEC2CM	1	/* TSEC2 & I2C0 clock mode (0-3) */
 
 /* System IO Config */
-#define CONFIG_SYS_SICRH SICRH_TSOBI1
+#define CONFIG_SYS_SICRH 0
 #define CONFIG_SYS_SICRL SICRL_LDP_A
 
 #define CONFIG_SYS_HID0_INIT	0x000000000

include/configs/MPC8569MDS.h

@@ -156,10 +156,18 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_BR0_PRELIM		0xfe000801
 #define	CONFIG_SYS_OR0_PRELIM		0xfe000ff7
 
-/*Chip slelect 1 - BCSR*/
+/*Chip select 1 - BCSR*/
 #define CONFIG_SYS_BR1_PRELIM		0xf8000801
 #define	CONFIG_SYS_OR1_PRELIM		0xffffe9f7
 
+/*Chip select 4 - PIB*/
+#define CONFIG_SYS_BR4_PRELIM		0xf8008801
+#define CONFIG_SYS_OR4_PRELIM		0xffffe9f7
+
+/*Chip select 5 - PIB*/
+#define CONFIG_SYS_BR5_PRELIM		0xf8010801
+#define CONFIG_SYS_OR5_PRELIM		0xffffe9f7
+
 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	512	/* sectors per device */
 #undef	CONFIG_SYS_FLASH_CHECKSUM
@@ -194,7 +202,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN	(256 * 1024)	/* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN	(128 * 1024)	/* Reserved for malloc */
+#define CONFIG_SYS_MALLOC_LEN	(512 * 1024)	/* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX		1
@@ -327,9 +335,9 @@ extern unsigned long get_clock_freq(void);
  * Environment
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SECT_SIZE	0x20000	/* 256K(one sector) for env */
-#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

include/configs/TQM834x.h

@@ -393,7 +393,7 @@ extern int tqm834x_num_flash_banks;
 #endif
 
 /* System IO Config */
-#define CONFIG_SYS_SICRH	SICRH_TSOBI1
+#define CONFIG_SYS_SICRH	0
 #define CONFIG_SYS_SICRL	SICRL_LDP_A
 
 /* i-cache and d-cache disabled */

include/configs/sbc8349.h

@@ -519,7 +519,7 @@
 #endif
 
 /* System IO Config */
-#define CONFIG_SYS_SICRH SICRH_TSOBI1
+#define CONFIG_SYS_SICRH 0
 #define CONFIG_SYS_SICRL SICRL_LDP_A
 
 #define CONFIG_SYS_HID0_INIT	0x000000000

onenand_ipl/board/apollon/Makefile

@@ -6,7 +6,7 @@ LDSCRIPT= $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/u-boot.onenand.lds
 LDFLAGS	= -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
 AFLAGS	+= -DCONFIG_ONENAND_IPL
 CFLAGS	+= -DCONFIG_ONENAND_IPL
-OBJCLFAGS += --gap-fill=0x00
+OBJCFLAGS += --gap-fill=0x00
 
 SOBJS	:= low_levelinit.o
 SOBJS	+= start.o