Prepare v2011.06

Signed-off-by: Wolfgang Denk <wd@denx.de>

.gitignore

@@ -13,6 +13,7 @@
 *~
 *.swp
 *.patch
+*.bin
 
 #
 # Top-level generic files
@@ -23,14 +24,15 @@
 /u-boot.hex
 /u-boot.imx
 /u-boot.map
-/u-boot.bin
 /u-boot.srec
 /u-boot.ldr
 /u-boot.ldr.hex
 /u-boot.ldr.srec
+/u-boot.img
+/u-boot.kwb
+/u-boot.sha1
+/u-boot.dis
 /u-boot.lds
-/u-boot-onenand.bin
-/u-boot-flexonenand.bin
 
 #
 # Generated files

MAINTAINERS

@@ -302,6 +302,11 @@ Dan Malek <dan@embeddedalley.com>
 	stxssa		MPC85xx
 	stxxtc		MPC8xx
 
+Ryan Mallon <ryan@bluewatersys.com>
+
+	snapper9260		ARM926EJS (AT91SAM9260 SoC)
+	snapper9g20		ARM926EJS (AT91SAM9G20 SoC)
+
 Eran Man <eran@nbase.co.il>
 
 	EVB64260_750CX	MPC750CX
@@ -430,13 +435,10 @@ Heiko Schocher <hs@denx.de>
 	kmsupx5		MPC8321
 	mgcoge		MPC8247
 	mgcoge3ne	MPC8247
-	mgcoge2un	ARM926EJS (Kirkwood SoC)
 	mucmc52		MPC5200
 	muas3001	MPC8270
 	municse		MPC5200
 	sc3		PPC405GP
-	suen3		ARM926EJS (Kirkwood SoC)
-	suen8		ARM926EJS (Kirkwood SoC)
 	suvd3		MPC8321
 	tuda1		MPC8321
 	tuxa1		MPC8321
@@ -567,13 +569,14 @@ Stefano Babic <sbabic@denx.de>
 	ea20		davinci
 	mx35pdk		i.MX35
 	mx51evk		i.MX51
-	polaris		xscale
-	trizepsiv	xscale
+	polaris		xscale/pxa
+	trizepsiv	xscale/pxa
  	vision2		i.MX51
 
 Jason Liu <r64343@freescale.com>
 
 	mx53evk         i.MX53
+	mx53loco        i.MX53
 
 Enric Balletbo i Serra <eballetbo@iseebcn.com>
 
@@ -600,7 +603,7 @@ Andreas Bie
 
 Cliff Brake <cliff.brake@gmail.com>
 
-	pxa255_idp	xscale
+	pxa255_idp	xscale/pxa
 
 Rick Bronson <rick@efn.org>
 
@@ -638,10 +641,7 @@ Kristoffer Ericson <kristoffer.ericson@gmail.com>
 Fabio Estevam <fabio.estevam@freescale.com>
 
 	mx31pdk		i.MX31
-
-Peter Figuli <peposh@etc.sk>
-
-	wepep250	xscale
+	mx53smd		i.MX53
 
 Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
 
@@ -677,7 +677,6 @@ Grazvydas Ignotas <notasas@gmail.com>
 Gary Jennejohn <garyj@denx.de>
 
 	smdk2400	ARM920T
-	trab		ARM920T
 
 Matthias Kaehlcke <matthias@kaehlcke.net>
 	edb9301			ARM920T (EP9301)
@@ -702,6 +701,10 @@ Minkyu Kang <mk7.kang@samsung.com>
 	s5p_goni		ARM ARMV7 (S5PC110 SoC)
 	s5pc210_universal	ARM ARMV7 (S5PC210 SoC)
 
+Chander Kashyap <k.chander@samsung.com>
+
+	SMDKV310		ARM ARMV7 (S5PC210 SoC)
+
 Frederik Kriewitz <frederik@kriewitz.eu>
 
 	devkit8000	ARM ARMV7 (OMAP3530 SoC)
@@ -714,7 +717,7 @@ Sergey Kubushyn <ksi@koi8.net>
 
 Prakash Kumar <prakash@embedx.com>
 
-	cerf250		xscale
+	cerf250		xscale/pxa
 
 Vipin Kumar <vipin.kumar@st.com>
 
@@ -792,9 +795,9 @@ John Rigby <jcrigby@gmail.com>
 
 Stefan Roese <sr@denx.de>
 
-	ixdpg425	xscale
-	pdnb3		xscale
-	scpu		xscale
+	ixdpg425	xscale/ixp
+	pdnb3		xscale/ixp
+	scpu		xscale/ixp
 
 Alessandro Rubini <rubini@unipv.it>
 Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>
@@ -814,18 +817,22 @@ Jens Scharsig <esw@bus-elektronik.de>
 Heiko Schocher <hs@denx.de>
 
 	magnesium	i.MX27
+	mgcoge3un	ARM926EJS (Kirkwood SoC)
+	suen3		ARM926EJS (Kirkwood SoC)
+	suen8		ARM926EJS (Kirkwood SoC)
 
 Robert Schwebel <r.schwebel@pengutronix.de>
 
-	csb226		xscale
-	innokom		xscale
+	csb226		xscale/pxa
+	innokom		xscale/pxa
 
 Michael Schwingen <michael@schwingen.org>
 
-	actux1		xscale
-	actux2		xscale
-	actux3		xscale
-	actux4		xscale
+	actux1		xscale/ixp
+	actux2		xscale/ixp
+	actux3		xscale/ixp
+	actux4		xscale/ixp
+	dvlhost		xscale/ixp
 
 Andrea Scian <andrea.scian@dave-tech.it>
 
@@ -849,12 +856,12 @@ Greg Ungerer <greg.ungerer@opengear.com>
 
 Marek Vasut <marek.vasut@gmail.com>
 
-	balloon3	xscale
-	colibri_pxa270	xscale
-	palmld		xscale
-	palmtc		xscale
-	vpac270		xscale
-	zipitz2		xscale
+	balloon3	xscale/pxa
+	colibri_pxa270	xscale/pxa
+	palmld		xscale/pxa
+	palmtc		xscale/pxa
+	vpac270		xscale/pxa
+	zipitz2		xscale/pxa
  	efikamx		i.MX51
 
 Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
@@ -905,9 +912,9 @@ Sughosh Ganu <urwithsughosh@gmail.com>
 Unknown / orphaned boards:
  	Board		CPU	Last known maintainer / Comment
 .........................................................................
-	cradle		xscale	Kyle Harris <kharris@nexus-tech.net> / dead address
-	ixdp425		xscale	Kyle Harris <kharris@nexus-tech.net> / dead address
-	lubbock		xscale	Kyle Harris <kharris@nexus-tech.net> / dead address
+	cradle		xscale/pxa	Kyle Harris <kharris@nexus-tech.net> / dead address
+	ixdp425		xscale/ixp	Kyle Harris <kharris@nexus-tech.net> / dead address
+	lubbock		xscale/pxa	Kyle Harris <kharris@nexus-tech.net> / dead address
 
 	imx31_phycore_eet i.MX31  Guennadi Liakhovetski <g.liakhovetski@gmx.de> / resigned
 	mx31ads		  i.MX31  Guennadi Liakhovetski <g.liakhovetski@gmx.de> / resigned

MAKEALL

@@ -374,7 +374,6 @@ LIST_ARM9="			\
 	spear320		\
 	spear600		\
 	suen3			\
-	trab			\
 	VCMA9			\
 	versatile		\
 	versatileab		\
@@ -454,9 +453,6 @@ LIST_at91="$(boards_by_soc at91)\
 	at91sam9g20ek		\
 	at91sam9m10g45ek	\
 	at91sam9rlek		\
-	CPUAT91			\
-	CPU9260			\
-	CPU9G20			\
 	pm9g45			\
 	SBC35_A9G20		\
 	TNY_A9260		\

Makefile

@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000-2010
+# (C) Copyright 2000-2011
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -24,7 +24,7 @@
 VERSION = 2011
 PATCHLEVEL = 06
 SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION =
 ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 else
@@ -140,7 +140,7 @@ SUBDIRS	= tools \
 	  examples/standalone \
 	  examples/api
 
-.PHONY : $(SUBDIRS)
+.PHONY : $(SUBDIRS) $(VERSION_FILE)
 
 ifeq ($(obj)include/config.mk,$(wildcard $(obj)include/config.mk))
 
@@ -163,6 +163,36 @@ endif
 # load other configuration
 include $(TOPDIR)/config.mk
 
+# If board code explicitly specified LDSCRIPT or CONFIG_SYS_LDSCRIPT, use
+# that (or fail if absent).  Otherwise, search for a linker script in a
+# standard location.
+
+ifndef LDSCRIPT
+	#LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug
+	ifdef CONFIG_SYS_LDSCRIPT
+		# need to strip off double quotes
+		LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+	endif
+endif
+
+ifndef LDSCRIPT
+	ifeq ($(CONFIG_NAND_U_BOOT),y)
+		LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
+		ifeq ($(wildcard $(LDSCRIPT)),)
+			LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
+		endif
+	endif
+	ifeq ($(wildcard $(LDSCRIPT)),)
+		LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+	endif
+	ifeq ($(wildcard $(LDSCRIPT)),)
+		LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot.lds
+	endif
+	ifeq ($(wildcard $(LDSCRIPT)),)
+$(error could not find linker script)
+	endif
+endif
+
 #########################################################################
 # U-Boot objects....order is important (i.e. start must be first)
 
@@ -236,7 +266,7 @@ endif
 LIBS += drivers/rtc/librtc.o
 LIBS += drivers/serial/libserial.o
 LIBS += drivers/twserial/libtws.o
-LIBS += drivers/usb/eth/libusb_eth.a
+LIBS += drivers/usb/eth/libusb_eth.o
 LIBS += drivers/usb/gadget/libusb_gadget.o
 LIBS += drivers/usb/host/libusb_host.o
 LIBS += drivers/usb/musb/libusb_musb.o
@@ -263,7 +293,7 @@ LIBS += $(CPUDIR)/s5p-common/libs5p-common.o
 endif
 
 LIBS := $(addprefix $(obj),$(sort $(LIBS)))
-.PHONY : $(LIBS) $(TIMESTAMP_FILE) $(VERSION_FILE)
+.PHONY : $(LIBS) $(TIMESTAMP_FILE)
 
 LIBBOARD = board/$(BOARDDIR)/lib$(BOARD).o
 LIBBOARD := $(addprefix $(obj),$(LIBBOARD))
@@ -322,6 +352,10 @@ ALL += $(obj)u-boot-onenand.bin
 ONENAND_BIN ?= $(obj)onenand_ipl/onenand-ipl-2k.bin
 endif
 
+ifeq ($(CONFIG_MMC_U_BOOT),y)
+ALL += $(obj)mmc_spl/u-boot-mmc-spl.bin
+endif
+
 all:		$(ALL)
 
 $(obj)u-boot.hex:	$(obj)u-boot
@@ -413,18 +447,10 @@ onenand_ipl:	$(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
 $(obj)u-boot-onenand.bin:	onenand_ipl $(obj)u-boot.bin
 		cat $(ONENAND_BIN) $(obj)u-boot.bin > $(obj)u-boot-onenand.bin
 
-$(VERSION_FILE):
-		@( localvers='$(shell $(TOPDIR)/tools/setlocalversion $(TOPDIR))' ; \
-		   printf '#define PLAIN_VERSION "%s%s"\n' \
-			"$(U_BOOT_VERSION)" "$${localvers}" ; \
-		   printf '#define U_BOOT_VERSION "U-Boot %s%s"\n' \
-			"$(U_BOOT_VERSION)" "$${localvers}" ; \
-		) > $@.tmp
-		@( printf '#define CC_VERSION_STRING "%s"\n' \
-		 '$(shell $(CC) --version | head -n 1)' )>>  $@.tmp
-		@( printf '#define LD_VERSION_STRING "%s"\n' \
-		 '$(shell $(LD) -v | head -n 1)' )>>  $@.tmp
-		@cmp -s $@ $@.tmp && rm -f $@.tmp || mv -f $@.tmp $@
+mmc_spl:	$(TIMESTAMP_FILE) $(VERSION_FILE) depend
+		$(MAKE) -C mmc_spl/board/$(BOARDDIR) all
+
+$(obj)mmc_spl/u-boot-mmc-spl.bin:	mmc_spl
 
 $(TIMESTAMP_FILE):
 		@LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"' > $@
@@ -500,20 +526,33 @@ $(obj)lib/asm-offsets.s:	$(obj)include/autoconf.mk.dep \
 else	# !config.mk
 all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \
 $(obj)u-boot.img $(obj)u-boot.dis $(obj)u-boot \
-$(filter-out tools,$(SUBDIRS)) $(TIMESTAMP_FILE) $(VERSION_FILE) \
+$(filter-out tools,$(SUBDIRS)) $(TIMESTAMP_FILE) \
 updater depend dep tags ctags etags cscope $(obj)System.map:
 	@echo "System not configured - see README" >&2
 	@ exit 1
 
-tools:
+tools: $(VERSION_FILE)
 	$(MAKE) -C $@ all
 endif	# config.mk
 
+$(VERSION_FILE):
+		@( localvers='$(shell $(TOPDIR)/tools/setlocalversion $(TOPDIR))' ; \
+		   printf '#define PLAIN_VERSION "%s%s"\n' \
+			"$(U_BOOT_VERSION)" "$${localvers}" ; \
+		   printf '#define U_BOOT_VERSION "U-Boot %s%s"\n' \
+			"$(U_BOOT_VERSION)" "$${localvers}" ; \
+		) > $@.tmp
+		@( printf '#define CC_VERSION_STRING "%s"\n' \
+		 '$(shell $(CC) --version | head -n 1)' )>>  $@.tmp
+		@( printf '#define LD_VERSION_STRING "%s"\n' \
+		 '$(shell $(LD) -v | head -n 1)' )>>  $@.tmp
+		@cmp -s $@ $@.tmp && rm -f $@.tmp || mv -f $@.tmp $@
+
 easylogo env gdb:
 	$(MAKE) -C tools/$@ all MTD_VERSION=${MTD_VERSION}
 gdbtools: gdb
 
-tools-all: easylogo env gdb
+tools-all: easylogo env gdb $(VERSION_FILE)
 	$(MAKE) -C tools HOST_TOOLS_ALL=y
 
 .PHONY : CHANGELOG
@@ -757,43 +796,6 @@ M5485HFE_config :	unconfig
 ## ARM926EJ-S Systems
 #########################################################################
 
-at91sam9260ek_nandflash_config \
-at91sam9260ek_dataflash_cs0_config \
-at91sam9260ek_dataflash_cs1_config \
-at91sam9260ek_config \
-at91sam9g20ek_nandflash_config \
-at91sam9g20ek_dataflash_cs0_config \
-at91sam9g20ek_dataflash_cs1_config \
-at91sam9g20ek_config	:	unconfig
-	@mkdir -p $(obj)include
-	@if [ "$(findstring 9g20,$@)" ] ; then \
-		echo "#define CONFIG_AT91SAM9G20EK 1"	>>$(obj)include/config.h ; \
-	else \
-		echo "#define CONFIG_AT91SAM9260EK 1"	>>$(obj)include/config.h ; \
-	fi;
-	@if [ "$(findstring _nandflash,$@)" ] ; then \
-		echo "#define CONFIG_SYS_USE_NANDFLASH 1"	>>$(obj)include/config.h ; \
-	elif [ "$(findstring dataflash_cs0,$@)" ] ; then \
-		echo "#define CONFIG_SYS_USE_DATAFLASH_CS0 1"	>>$(obj)include/config.h ; \
-	else \
-		echo "#define CONFIG_SYS_USE_DATAFLASH_CS1 1"	>>$(obj)include/config.h ; \
-	fi;
-	@$(MKCONFIG) -n $@ -a at91sam9260ek arm arm926ejs at91sam9260ek atmel at91
-
-at91sam9xeek_nandflash_config \
-at91sam9xeek_dataflash_cs0_config \
-at91sam9xeek_dataflash_cs1_config \
-at91sam9xeek_config	:	unconfig
-	@mkdir -p $(obj)include
-	@if [ "$(findstring _nandflash,$@)" ] ; then \
-		echo "#define CONFIG_SYS_USE_NANDFLASH 1"	>>$(obj)include/config.h ; \
-	elif [ "$(findstring dataflash_cs0,$@)" ] ; then \
-		echo "#define CONFIG_SYS_USE_DATAFLASH_CS0 1"	>>$(obj)include/config.h ; \
-	else \
-		echo "#define CONFIG_SYS_USE_DATAFLASH_CS1 1"	>>$(obj)include/config.h ; \
-	fi;
-	@$(MKCONFIG) -n $@ -a at91sam9260ek arm arm926ejs at91sam9260ek atmel at91
-
 at91sam9261ek_nandflash_config \
 at91sam9261ek_dataflash_cs0_config \
 at91sam9261ek_dataflash_cs3_config \
@@ -848,14 +850,6 @@ at91sam9rlek_config	:	unconfig
 	fi;
 	@$(MKCONFIG) -n $@ -a at91sam9rlek arm arm926ejs at91sam9rlek atmel at91
 
-CPU9G20_128M_config \
-CPU9G20_config \
-CPU9260_128M_config \
-CPU9260_config	:	unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
-	@$(MKCONFIG) -n $@ -a cpu9260 arm arm926ejs cpu9260 eukrea at91
-
 at91sam9m10g45ek_nandflash_config \
 at91sam9m10g45ek_dataflash_config \
 at91sam9m10g45ek_dataflash_cs0_config \
@@ -973,29 +967,6 @@ SX1_config:		unconfig
 	fi;
 	@$(MKCONFIG) -n $@ SX1 arm arm925t sx1
 
-# TRAB default configuration:	8 MB Flash, 32 MB RAM
-trab_config \
-trab_bigram_config \
-trab_bigflash_config \
-trab_old_config:	unconfig
-	@mkdir -p $(obj)include
-	@mkdir -p $(obj)board/trab
-	@[ -z "$(findstring _bigram,$@)" ] || \
-		{ echo "#define CONFIG_FLASH_8MB"  >>$(obj)include/config.h ; \
-		  echo "#define CONFIG_RAM_32MB"   >>$(obj)include/config.h ; \
-		}
-	@[ -z "$(findstring _bigflash,$@)" ] || \
-		{ echo "#define CONFIG_FLASH_16MB" >>$(obj)include/config.h ; \
-		  echo "#define CONFIG_RAM_16MB"   >>$(obj)include/config.h ; \
-		  echo "CONFIG_SYS_TEXT_BASE = 0x0CF40000" >$(obj)board/trab/config.tmp ; \
-		}
-	@[ -z "$(findstring _old,$@)" ] || \
-		{ echo "#define CONFIG_FLASH_8MB"  >>$(obj)include/config.h ; \
-		  echo "#define CONFIG_RAM_16MB"   >>$(obj)include/config.h ; \
-		  echo "CONFIG_SYS_TEXT_BASE = 0x0CF40000" >$(obj)board/trab/config.tmp ; \
-		}
-	@$(MKCONFIG) -n $@ -a trab arm arm920t trab - s3c24x0
-
 tx25_config	: unconfig
 	@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
 	@$(MKCONFIG) $@ arm arm926ejs tx25 karo mx25
@@ -1115,7 +1086,7 @@ clean:
 	@rm -f $(obj)board/cray/L1/{bootscript.c,bootscript.image}	  \
 	       $(obj)board/matrix_vision/*/bootscript.img		  \
 	       $(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin}	  \
-	       $(obj)board/trab/trab_fkt   $(obj)board/voiceblue/eeprom   \
+	       $(obj)board/voiceblue/eeprom 				  \
 	       $(obj)board/armltd/{integratorap,integratorcp}/u-boot.lds  \
 	       $(obj)u-boot.lds						  \
 	       $(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs]
@@ -1123,6 +1094,7 @@ clean:
 	@rm -f $(obj)lib/asm-offsets.s
 	@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,System.map}
 	@rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl.map}
+	@rm -f $(obj)mmc_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,u-boot-spl.bin,u-boot-mmc-spl.bin}
 	@rm -f $(ONENAND_BIN)
 	@rm -f $(obj)onenand_ipl/u-boot.lds
 	@rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
@@ -1147,6 +1119,7 @@ clobber:	clean
 	@rm -fr $(obj)include/generated
 	@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f
 	@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l -print | xargs rm -f
+	@[ ! -d $(obj)mmc_spl ] || find $(obj)mmc_spl -name "*" -type l -print | xargs rm -f
 
 ifeq ($(OBJTREE),$(SRCTREE))
 mrproper \

README

@@ -363,6 +363,11 @@ The following options need to be configured:
 		system clock.  On most PQ3 devices this is 8, on newer QorIQ
 		devices it can be 16 or 32.  The ratio varies from SoC to Soc.
 
+		CONFIG_SYS_FSL_PCIE_COMPAT
+
+		Defines the string to utilize when trying to match PCIe device
+		tree nodes for the given platform.
+
 - Intel Monahans options:
 		CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
 
@@ -711,7 +716,6 @@ The following options need to be configured:
 		CONFIG_CMD_SPI		* SPI serial bus support
 		CONFIG_CMD_TFTPSRV	* TFTP transfer in server mode
 		CONFIG_CMD_USB		* USB support
-		CONFIG_CMD_VFD		* VFD support (TRAB)
 		CONFIG_CMD_CDP		* Cisco Discover Protocol support
 		CONFIG_CMD_FSL		* Microblaze FSL support
 
@@ -2225,7 +2229,7 @@ FIT uImage format:
 Modem Support:
 --------------
 
-[so far only for SMDK2400 and TRAB boards]
+[so far only for SMDK2400 boards]
 
 - Modem support enable:
 		CONFIG_MODEM_SUPPORT

arch/arm/config.mk

@@ -62,6 +62,13 @@ PLATFORM_LIBS += $(OBJTREE)/arch/arm/lib/eabi_compat.o
 endif
 endif
 
+ifdef CONFIG_SYS_LDSCRIPT
+# need to strip off double quotes
+LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+else
+LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
+endif
+
 # needed for relocation
 ifndef CONFIG_NAND_SPL
 LDFLAGS_u-boot += -pie

arch/arm/cpu/arm1136/mx31/generic.c

@@ -133,7 +133,7 @@ u32 get_cpu_rev(void)
 	return srev | 0x8000;
 }
 
-char *get_reset_cause(void)
+static char *get_reset_cause(void)
 {
 	/* read RCSR register from CCM module */
 	struct clock_control_regs *ccm =
@@ -144,16 +144,12 @@ char *get_reset_cause(void)
 	switch (cause) {
 	case 0x0000:
 		return "POR";
-		break;
 	case 0x0001:
 		return "RST";
-		break;
 	case 0x0002:
 		return "WDOG";
-		break;
 	case 0x0006:
 		return "JTAG";
-		break;
 	default:
 		return "unknown reset";
 	}

arch/arm/cpu/arm920t/at91/reset.c

@@ -42,7 +42,7 @@ void  __attribute__((weak)) board_reset(void)
 
 void reset_cpu(ulong ignored)
 {
-	at91_st_t *st = (at91_st_t *) AT91_ST_BASE;
+	at91_st_t *st = (at91_st_t *) ATMEL_BASE_ST;
 #if defined(CONFIG_AT91RM9200_USART)
 	/*shutdown the console to avoid strange chars during reset */
 	serial_exit();

arch/arm/cpu/arm920t/at91/timer.c

@@ -32,7 +32,7 @@
 
 #include <common.h>
 
-#include <asm/arch/io.h>
+#include <asm/io.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/at91_tc.h>
 #include <asm/arch/at91_pmc.h>
@@ -44,11 +44,11 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int timer_init(void)
 {
-	at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE;
-	at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+	at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
+	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	/* enables TC1.0 clock */
-	writel(1 << AT91_ID_TC0, &pmc->pcer);	/* enable clock */
+	writel(1 << ATMEL_ID_TC0, &pmc->pcer);	/* enable clock */
 
 	writel(0, &tc->bcr);
 	writel(AT91_TC_BMR_TC0XC0S_NONE | AT91_TC_BMR_TC1XC1S_NONE |
@@ -96,14 +96,14 @@ void __udelay(unsigned long usec)
 void reset_timer_masked(void)
 {
 	/* reset time */
-	at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE;
+	at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
 	gd->lastinc = readl(&tc->tc[0].cv) & 0x0000ffff;
 	gd->tbl = 0;
 }
 
 ulong get_timer_raw(void)
 {
-	at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE;
+	at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
 	u32 now;
 
 	now = readl(&tc->tc[0].cv) & 0x0000ffff;

arch/arm/cpu/arm920t/s3c24x0/timer.c

@@ -177,7 +177,7 @@ ulong get_tbclk(void)
 {
 	ulong tbclk;
 
-#if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB)
+#if defined(CONFIG_SMDK2400)
 	tbclk = timer_load_val * 100;
 #elif defined(CONFIG_SBC2410X) || \
       defined(CONFIG_SMDK2410) || \
@@ -198,12 +198,6 @@ void reset_cpu(ulong ignored)
 {
 	struct s3c24x0_watchdog *watchdog;
 
-#ifdef CONFIG_TRAB
-	extern void disable_vfd(void);
-
-	disable_vfd();
-#endif
-
 	watchdog = s3c24x0_get_base_watchdog();
 
 	/* Disable watchdog */

arch/arm/cpu/arm926ejs/at91/lowlevel_init.S

@@ -230,37 +230,37 @@ SMRDATA1:
 	.word CONFIG_SYS_SDRC_MDR_VAL
 	.word AT91_ASM_SDRAMC_MR
 	.word CONFIG_SYS_SDRC_MR_VAL2
-	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_BASE
 	.word CONFIG_SYS_SDRAM_VAL1
 	.word AT91_ASM_SDRAMC_MR
 	.word CONFIG_SYS_SDRC_MR_VAL3
-	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_BASE
 	.word CONFIG_SYS_SDRAM_VAL2
-	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_BASE
 	.word CONFIG_SYS_SDRAM_VAL3
-	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_BASE
 	.word CONFIG_SYS_SDRAM_VAL4
-	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_BASE
 	.word CONFIG_SYS_SDRAM_VAL5
-	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_BASE
 	.word CONFIG_SYS_SDRAM_VAL6
-	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_BASE
 	.word CONFIG_SYS_SDRAM_VAL7
-	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_BASE
 	.word CONFIG_SYS_SDRAM_VAL8
-	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_BASE
 	.word CONFIG_SYS_SDRAM_VAL9
 	.word AT91_ASM_SDRAMC_MR
 	.word CONFIG_SYS_SDRC_MR_VAL4
-	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_BASE
 	.word CONFIG_SYS_SDRAM_VAL10
 	.word AT91_ASM_SDRAMC_MR
 	.word CONFIG_SYS_SDRC_MR_VAL5
-	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_BASE
 	.word CONFIG_SYS_SDRAM_VAL11
 	.word AT91_ASM_SDRAMC_TR
 	.word CONFIG_SYS_SDRC_TR_VAL2
-	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_BASE
 	.word CONFIG_SYS_SDRAM_VAL12
 	/* User reset enable*/
 	.word AT91_ASM_RSTC_MR

arch/arm/cpu/armv7/mx5/soc.c

@@ -65,14 +65,10 @@ u32 get_cpu_rev(void)
 		break;
 	}
 #else
-	switch (reg) {
-	case 0x20:
-		system_rev |= CHIP_REV_2_0;
-		break;
-	default:
+	if (reg < 0x20)
 		system_rev |= CHIP_REV_1_0;
-		break;
-	}
+	else
+		system_rev |= reg;
 #endif
 	return system_rev;
 }

arch/arm/cpu/armv7/s5p-common/Makefile

@@ -27,7 +27,8 @@ LIB	= $(obj)libs5p-common.o
 
 COBJS-y		+= cpu_info.o
 COBJS-y		+= timer.o
-COBJS-$(CONFIG_PWM)		+= pwm.o
+COBJS-y		+= sromc.o
+COBJS-$(CONFIG_PWM)	+= pwm.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS))

arch/arm/cpu/armv7/s5p-common/cpu_info.c

@@ -26,6 +26,8 @@
 
 /* Default is s5pc100 */
 unsigned int s5p_cpu_id = 0xC100;
+/* Default is EVT1 */
+unsigned int s5p_cpu_rev = 1;
 
 #ifdef CONFIG_ARCH_CPU_INIT
 int arch_cpu_init(void)

arch/arm/cpu/armv7/s5p-common/sromc.c

@@ -23,27 +23,27 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/smc.h>
+#include <asm/arch/sromc.h>
 
 /*
- * s5pc1xx_config_sromc() - select the proper SROMC Bank and configure the
- * 		    band width control and bank control registers
- * srom_bank	- SROM Bank 0 to 5
- * smc_bw_conf  - SMC Band witdh reg configuration value
- * smc_bc_conf  - SMC Bank Control reg configuration value
+ * s5p_config_sromc() - select the proper SROMC Bank and configure the
+ * band width control and bank control registers
+ * srom_bank	- SROM
+ * srom_bw_conf  - SMC Band witdh reg configuration value
+ * srom_bc_conf  - SMC Bank Control reg configuration value
  */
-void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf)
+void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf)
 {
 	u32 tmp;
-	struct s5pc1xx_smc *srom =
-		(struct s5pc1xx_smc *)samsung_get_base_sromc();
+	struct s5p_sromc *srom =
+		(struct s5p_sromc *)samsung_get_base_sromc();
 
 	/* Configure SMC_BW register to handle proper SROMC bank */
 	tmp = srom->bw;
 	tmp &= ~(0xF << (srom_bank * 4));
-	tmp |= smc_bw_conf;
+	tmp |= srom_bw_conf;
 	srom->bw = tmp;
 
 	/* Configure SMC_BC register */
-	srom->bc[srom_bank] = smc_bc_conf;
+	srom->bc[srom_bank] = srom_bc_conf;
 }

arch/arm/cpu/armv7/s5pc1xx/Makefile

@@ -32,7 +32,6 @@ SOBJS	= cache.o
 SOBJS	+= reset.o
 
 COBJS	+= clock.o
-COBJS	+= sromc.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))

arch/arm/cpu/armv7/s5pc1xx/clock.c

@@ -336,3 +336,8 @@ unsigned long get_uart_clk(int dev_index)
 {
 	return s5pc1xx_get_uart_clk(dev_index);
 }
+
+void set_mmc_clk(int dev_index, unsigned int div)
+{
+	/* Do NOTHING */
+}

arch/arm/cpu/armv7/s5pc2xx/clock.c

@@ -124,29 +124,35 @@ static unsigned long s5pc210_get_pwm_clk(void)
 	unsigned int sel;
 	unsigned int ratio;
 
-	/*
-	 * CLK_SRC_PERIL0
-	 * PWM_SEL [27:24]
-	 */
-	sel = readl(&clk->src_peril0);
-	sel = (sel >> 24) & 0xf;
+	if (s5p_get_cpu_rev() == 0) {
+		/*
+		 * CLK_SRC_PERIL0
+		 * PWM_SEL [27:24]
+		 */
+		sel = readl(&clk->src_peril0);
+		sel = (sel >> 24) & 0xf;
 
-	if (sel == 0x6)
+		if (sel == 0x6)
+			sclk = get_pll_clk(MPLL);
+		else if (sel == 0x7)
+			sclk = get_pll_clk(EPLL);
+		else if (sel == 0x8)
+			sclk = get_pll_clk(VPLL);
+		else
+			return 0;
+
+		/*
+		 * CLK_DIV_PERIL3
+		 * PWM_RATIO [3:0]
+		 */
+		ratio = readl(&clk->div_peril3);
+		ratio = ratio & 0xf;
+	} else if (s5p_get_cpu_rev() == 1) {
 		sclk = get_pll_clk(MPLL);
-	else if (sel == 0x7)
-		sclk = get_pll_clk(EPLL);
-	else if (sel == 0x8)
-		sclk = get_pll_clk(VPLL);
-	else
+		ratio = 8;
+	} else
 		return 0;
 
-	/*
-	 * CLK_DIV_PERIL3
-	 * PWM_RATIO [3:0]
-	 */
-	ratio = readl(&clk->div_peril3);
-	ratio = ratio & 0xf;
-
 	pclk = sclk / (ratio + 1);
 
 	return pclk;
@@ -199,6 +205,33 @@ static unsigned long s5pc210_get_uart_clk(int dev_index)
 	return uclk;
 }
 
+/* s5pc210: set the mmc clock */
+static void s5pc210_set_mmc_clk(int dev_index, unsigned int div)
+{
+	struct s5pc210_clock *clk =
+		(struct s5pc210_clock *)samsung_get_base_clock();
+	unsigned int addr;
+	unsigned int val;
+
+	/*
+	 * CLK_DIV_FSYS1
+	 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
+	 * CLK_DIV_FSYS2
+	 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
+	 */
+	if (dev_index < 2) {
+		addr = (unsigned int)&clk->div_fsys1;
+	} else {
+		addr = (unsigned int)&clk->div_fsys2;
+		dev_index -= 2;
+	}
+
+	val = readl(addr);
+	val &= ~(0xff << ((dev_index << 4) + 8));
+	val |= (div & 0xff) << ((dev_index << 4) + 8);
+	writel(val, addr);
+}
+
 unsigned long get_pll_clk(int pllreg)
 {
 	return s5pc210_get_pll_clk(pllreg);
@@ -218,3 +251,8 @@ unsigned long get_uart_clk(int dev_index)
 {
 	return s5pc210_get_uart_clk(dev_index);
 }
+
+void set_mmc_clk(int dev_index, unsigned int div)
+{
+	s5pc210_set_mmc_clk(dev_index, div);
+}

arch/arm/cpu/armv7/u8500/Makefile

@@ -1,5 +1,6 @@
 #
-# Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
 # project.
@@ -20,6 +21,26 @@
 # MA 02111-1307 USA
 #
 
-CONFIG_SYS_TEXT_BASE = 0x97800000
-IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg
-ALL += $(obj)u-boot.imx
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS	= timer.o clock.o
+SOBJS	= lowlevel.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

arch/arm/cpu/armv7/u8500/clock.c

@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2009 ST-Ericsson
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct clkrst {
+	unsigned int pcken;
+	unsigned int pckdis;
+	unsigned int kcken;
+	unsigned int kckdis;
+};
+
+static unsigned int clkrst_base[] = {
+	U8500_CLKRST1_BASE,
+	U8500_CLKRST2_BASE,
+	U8500_CLKRST3_BASE,
+	0,
+	U8500_CLKRST5_BASE,
+	U8500_CLKRST6_BASE,
+	U8500_CLKRST7_BASE,	/* ED only */
+};
+
+/* Turn on peripheral clock at PRCC level */
+void u8500_clock_enable(int periph, int cluster, int kern)
+{
+	struct clkrst *clkrst = (struct clkrst *) clkrst_base[periph - 1];
+
+	if (kern != -1)
+		writel(1 << kern, &clkrst->kcken);
+
+	if (cluster != -1)
+		writel(1 << cluster, &clkrst->pcken);
+}

arch/arm/cpu/armv7/u8500/lowlevel.S

@@ -1,9 +1,8 @@
 /*
- * (C) Copyright 2003
- * Martin Krause, TQ-Systems GmbH, <martin.krause@tqs.de>
+ * (C) Copyright 2011 ST-Ericsson
  *
- * Based on arch/arm/cpu/arm920t/serial.c, by Gary Jennejohn
- * (C) Copyright 2002 Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ * See file CREDITS for list of people who contributed to this
+ * project.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -17,21 +16,20 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
-#ifndef _RS485_H_
-#define _RS485_H_
+#include <config.h>
 
-#include <asm/arch/s3c24x0_cpu.h>
+.globl lowlevel_init
+lowlevel_init:
+	mov	pc, lr
 
-int rs485_init (void);
-int rs485_getc (void);
-void rs485_putc (const char c);
-int rs485_tstc (void);
-void rs485_puts (const char *s);
-void trab_rs485_enable_tx(void);
-void trab_rs485_enable_rx(void);
-
-#endif	/* _RS485_H_ */
+	.align	5
+.globl reset_cpu
+reset_cpu:
+	ldr r0, =CFG_PRCMU_BASE
+	ldr r1, =0x1
+	str r1, [r0, #0x228]
+_loop_forever:
+	b	_loop_forever

arch/arm/cpu/armv7/u8500/timer.c

@@ -0,0 +1,154 @@
+/*
+ * Copyright (C) 2010 Linaro Limited
+ * John Rigby <john.rigby@linaro.org>
+ *
+ * Based on original from Linux kernel source and
+ * internal ST-Ericsson U-Boot source.
+ * (C) Copyright 2009 Alessandro Rubini
+ * (C) Copyright 2010 ST-Ericsson
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * The MTU device has some interrupt control registers
+ * followed by 4 timers.
+ */
+
+/* The timers */
+struct u8500_mtu_timer {
+	u32 lr;			/* Load value */
+	u32 cv;			/* Current value */
+	u32 cr;			/* Control reg */
+	u32 bglr;		/* ??? */
+};
+
+/* The MTU that contains the timers */
+struct u8500_mtu {
+	u32 imsc;		/* Interrupt mask set/clear */
+	u32 ris;		/* Raw interrupt status */
+	u32 mis;		/* Masked interrupt status */
+	u32 icr;		/* Interrupt clear register */
+	struct u8500_mtu_timer pt[4];
+};
+
+/* bits for the control register */
+#define MTU_CR_ONESHOT		0x01	/* if 0 = wraps reloading from BGLR */
+#define MTU_CR_32BITS		0x02
+
+#define MTU_CR_PRESCALE_1	0x00
+#define MTU_CR_PRESCALE_16	0x04
+#define MTU_CR_PRESCALE_256	0x08
+#define MTU_CR_PRESCALE_MASK	0x0c
+
+#define MTU_CR_PERIODIC		0x40	/* if 0 = free-running */
+#define MTU_CR_ENA		0x80
+
+/*
+ * The MTU is clocked at 133 MHz by default. (V1 and later)
+ */
+#define TIMER_CLOCK		(133 * 1000 * 1000 / 16)
+#define COUNT_TO_USEC(x)	((x) * 16 / 133)
+#define USEC_TO_COUNT(x)	((x) * 133 / 16)
+#define TICKS_PER_HZ		(TIMER_CLOCK / CONFIG_SYS_HZ)
+#define TICKS_TO_HZ(x)		((x) / TICKS_PER_HZ)
+#define TIMER_LOAD_VAL		0xffffffff
+
+/*
+ * MTU timer to use (from 0 to 3).
+ */
+#define MTU_TIMER 2
+
+static struct u8500_mtu_timer *timer_base =
+	&((struct u8500_mtu *)U8500_MTU0_BASE_V1)->pt[MTU_TIMER];
+
+/* macro to read the 32 bit timer: since it decrements, we invert read value */
+#define READ_TIMER() (~readl(&timer_base->cv))
+
+/* Configure a free-running, auto-wrap counter with /16 prescaler */
+int timer_init(void)
+{
+	writel(MTU_CR_ENA | MTU_CR_PRESCALE_16 | MTU_CR_32BITS,
+	       &timer_base->cr);
+	return 0;
+}
+
+ulong get_timer_masked(void)
+{
+	/* current tick value */
+	ulong now = TICKS_TO_HZ(READ_TIMER());
+
+	if (now >= gd->lastinc)	/* normal (non rollover) */
+		gd->tbl += (now - gd->lastinc);
+	else			/* rollover */
+		gd->tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL) - gd->lastinc) + now;
+	gd->lastinc = now;
+	return gd->tbl;
+}
+
+/* Delay x useconds */
+void __udelay(ulong usec)
+{
+	long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+	ulong now, last = READ_TIMER();
+
+	while (tmo > 0) {
+		now = READ_TIMER();
+		if (now > last)	/* normal (non rollover) */
+			tmo -= now - last;
+		else		/* rollover */
+			tmo -= TIMER_LOAD_VAL - last + now;
+		last = now;
+	}
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+	gd->tbl = t;
+}
+
+/*
+ * Emulation of Power architecture long long timebase.
+ *
+ * TODO: Support gd->tbu for real long long timebase.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * Emulation of Power architecture timebase.
+ * NB: Low resolution compared to Power tbclk.
+ */
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}

arch/arm/cpu/ixp/config.mk

@@ -27,6 +27,11 @@ BIG_ENDIAN = y
 PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float -mbig-endian
 
 PLATFORM_CPPFLAGS += -mbig-endian -march=armv5te -mtune=strongarm1100
+
+# -fdata-sections triggers "section .bss overlaps section .rel.dyn" linker error
+PLATFORM_RELFLAGS += -ffunction-sections
+LDFLAGS_u-boot += --gc-sections
+
 # =========================================================================
 #
 # Supply options according to compiler version

arch/arm/cpu/ixp/cpu.c

@@ -36,8 +36,6 @@
 #include <asm/arch/ixp425.h>
 #include <asm/system.h>
 
-ulong loops_per_jiffy;
-
 static void cache_flush(void);
 
 #if defined(CONFIG_DISPLAY_CPUINFO)
@@ -51,17 +49,14 @@ int print_cpuinfo (void)
 	puts("CPU:   Intel IXP425 at ");
 	switch ((id & 0x000003f0) >> 4) {
 	case 0x1c:
-		loops_per_jiffy = 887467;
 		speed = 533;
 		break;
 
 	case 0x1d:
-		loops_per_jiffy = 666016;
 		speed = 400;
 		break;
 
 	case 0x1f:
-		loops_per_jiffy = 442901;
 		speed = 266;
 		break;
 	}

arch/arm/cpu/ixp/npe/Makefile

@@ -27,6 +27,7 @@ LIB := $(obj)libnpe.o
 
 LOCAL_CFLAGS  += -I$(TOPDIR)/arch/arm/cpu/ixp/npe/include -DCONFIG_IXP425_COMPONENT_ETHDB -D__linux
 CFLAGS  += $(LOCAL_CFLAGS)
+CPPFLAGS  += $(LOCAL_CFLAGS) # needed for depend
 HOSTCFLAGS  += $(LOCAL_CFLAGS)
 
 COBJS-$(CONFIG_IXP4XX_NPE) := npe.o \

arch/arm/cpu/ixp/npe/npe.c

@@ -359,36 +359,53 @@ static int npe_init(struct eth_device *dev, bd_t * bis)
 
 	debug("%s: 1\n", __FUNCTION__);
 
-	miiphy_read (dev->name, p_npe->phy_no, MII_BMSR, &reg_short);
+#ifdef CONFIG_MII_NPE0_FIXEDLINK
+	if (0 == p_npe->eth_id) {
+		speed = CONFIG_MII_NPE0_SPEED;
+		duplex = CONFIG_MII_NPE0_FULLDUPLEX ? FULL : HALF;
+	} else
+#endif
+#ifdef CONFIG_MII_NPE1_FIXEDLINK
+	if (1 == p_npe->eth_id) {
+		speed = CONFIG_MII_NPE1_SPEED;
+		duplex = CONFIG_MII_NPE1_FULLDUPLEX ? FULL : HALF;
+	} else
+#endif
+	{
+		miiphy_read(dev->name, p_npe->phy_no, MII_BMSR, &reg_short);
 
-	/*
-	 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
-	 */
-	if ((reg_short & BMSR_ANEGCAPABLE) && !(reg_short & BMSR_ANEGCOMPLETE)) {
-		puts ("Waiting for PHY auto negotiation to complete");
-		i = 0;
-		while (!(reg_short & BMSR_ANEGCOMPLETE)) {
-			/*
-			 * Timeout reached ?
-			 */
-			if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
-				puts (" TIMEOUT !\n");
-				break;
-			}
+		/*
+		 * Wait if PHY is capable of autonegotiation and
+		 * autonegotiation is not complete
+		 */
+		if ((reg_short & BMSR_ANEGCAPABLE) &&
+		    !(reg_short & BMSR_ANEGCOMPLETE)) {
+			puts("Waiting for PHY auto negotiation to complete");
+			i = 0;
+			while (!(reg_short & BMSR_ANEGCOMPLETE)) {
+				/*
+				 * Timeout reached ?
+				 */
+				if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
+					puts(" TIMEOUT !\n");
+					break;
+				}
 
-			if ((i++ % 1000) == 0) {
-				putc ('.');
-				miiphy_read (dev->name, p_npe->phy_no, MII_BMSR, &reg_short);
+				if ((i++ % 1000) == 0) {
+					putc('.');
+					miiphy_read(dev->name, p_npe->phy_no,
+						     MII_BMSR, &reg_short);
+				}
+				udelay(1000);	/* 1 ms */
 			}
-			udelay (1000);	/* 1 ms */
+			puts(" done\n");
+			/* another 500 ms (results in faster booting) */
+			udelay(500000);
 		}
-		puts (" done\n");
-		udelay (500000);	/* another 500 ms (results in faster booting) */
+		speed = miiphy_speed(dev->name, p_npe->phy_no);
+		duplex = miiphy_duplex(dev->name, p_npe->phy_no);
 	}
 
-	speed = miiphy_speed (dev->name, p_npe->phy_no);
-	duplex = miiphy_duplex (dev->name, p_npe->phy_no);
-
 	if (p_npe->print_speed) {
 		p_npe->print_speed = 0;
 		printf ("ENET Speed is %d Mbps - %s duplex connection\n",
@@ -621,9 +638,12 @@ int npe_initialize(bd_t * bis)
 			if (ixFeatureCtrlDeviceRead() == IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X) {
 				switch (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK) {
 				case IX_FEATURE_CTRL_SILICON_TYPE_B0:
+				default: /* newer than B0 */
 					/*
-					 * If it is B0 Silicon, we only enable port when its corresponding
-					 * Eth Coprocessor is available.
+					 * If it is B0 or newer Silicon, we
+					 * only enable port when its
+					 * corresponding Eth Coprocessor is
+					 * available.
 					 */
 					if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) ==
 					    IX_FEATURE_CTRL_COMPONENT_ENABLED)

arch/arm/cpu/ixp/start.S

@@ -65,7 +65,8 @@
 	.endm
 
 .globl _start
-_start: b	reset
+_start:
+	ldr	pc, _reset
 	ldr	pc, _undefined_instruction
 	ldr	pc, _software_interrupt
 	ldr	pc, _prefetch_abort
@@ -74,6 +75,7 @@ _start: b	reset
 	ldr	pc, _irq
 	ldr	pc, _fiq
 
+_reset:                 .word reset
 _undefined_instruction: .word undefined_instruction
 _software_interrupt:	.word software_interrupt
 _prefetch_abort:	.word prefetch_abort
@@ -167,12 +169,6 @@ reset:
 	str     r1, [r2]
 
 	/* make sure flash is visible at 0 */
-#if 0
-	ldr	r2, =IXP425_EXP_CFG0
-	ldr     r1, [r2]
-	orr     r1, r1, #0x80000000
-	str     r1, [r2]
-#endif
 	mov	r1, #CONFIG_SYS_SDR_CONFIG
 	ldr     r2, =IXP425_SDR_CONFIG
 	str     r1, [r2]
@@ -216,19 +212,6 @@ reset:
 	str	r1, [r4]
 	DELAY_FOR 0x4000, r0
 
-	/* copy */
-	mov     r0, #0
-	mov     r4, r0
-	add     r2, r0, #CONFIG_SYS_MONITOR_LEN
-	mov     r1, #0x10000000
-	mov     r5, r1
-
-    30:
-	ldr     r3, [r0], #4
-	str     r3, [r1], #4
-	cmp     r0, r2
-	bne     30b
-
 	/* invalidate I & D caches & BTB */
 	mcr	p15, 0, r0, c7, c7, 0
 	CPWAIT	r0
@@ -241,19 +224,12 @@ reset:
 	mcr	p15, 0, r0, c7, c10, 4
 	CPWAIT	r0
 
-	/* move flash to 0x50000000 */
+	/* remove flash mirror at 0x00000000 */
 	ldr	r2, =IXP425_EXP_CFG0
 	ldr     r1, [r2]
 	bic     r1, r1, #0x80000000
 	str     r1, [r2]
 
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-
 	/* invalidate I & Data TLB */
 	mcr	p15, 0, r0, c8, c7, 0
 	CPWAIT r0
@@ -269,7 +245,7 @@ reset:
 	orr	r0,r0,#0x13
 	msr	cpsr,r0
 
-/* Set stackpointer in internal RAM to call board_init_f */
+/* Set initial stackpointer in SDRAM to call board_init_f */
 call_board_init_f:
 	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
 	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
@@ -575,33 +551,5 @@ reset_cpu:
 	str     r1, [r2]
 	b	reset_endless
 
-
 reset_endless:
-
 	b	reset_endless
-
-#ifdef CONFIG_USE_IRQ
-
-.LC0:		.word	loops_per_jiffy
-
-/*
- * 0 <= r0 <= 2000
- */
-.globl __udelay
-__udelay:
-	mov	r2,     #0x6800
-	orr	r2, r2, #0x00db
-	mul	r0, r2, r0
-	ldr	r2, .LC0
-	ldr	r2, [r2]		@ max = 0x0fffffff
-	mov	r0, r0, lsr #11		@ max = 0x00003fff
-	mov	r2, r2, lsr #11		@ max = 0x0003ffff
-	mul	r0, r2, r0		@ max = 2^32-1
-	movs	r0, r0, lsr #6
-
-delay_loop:
-	subs	r0, r0, #1
-	bne	delay_loop
-	mov	pc, lr
-
-#endif /* CONFIG_USE_IRQ */

arch/arm/cpu/ixp/timer.c

@@ -1,4 +1,7 @@
 /*
+ * (C) Copyright 2010
+ * Michael Schwingen, michael@schwingen.org
+ *
  * (C) Copyright 2006
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
@@ -31,105 +34,94 @@
 
 #include <common.h>
 #include <asm/arch/ixp425.h>
+#include <asm/io.h>
+#include <div64.h>
 
-#ifdef CONFIG_TIMER_IRQ
-
-#define FREQ		66666666
-#define CLOCK_TICK_RATE	(((FREQ / CONFIG_SYS_HZ & ~IXP425_OST_RELOAD_MASK) + 1) * CONFIG_SYS_HZ)
-#define LATCH		((CLOCK_TICK_RATE + CONFIG_SYS_HZ/2) / CONFIG_SYS_HZ)	/* For divider */
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
- * When interrupts are enabled, use timer 2 for time/delay generation...
+ * The IXP42x time-stamp timer runs at 2*OSC_IN (66.666MHz when using a
+ * 33.333MHz crystal).
  */
-
-static volatile ulong timestamp;
-
-static void timer_isr(void *data)
+static inline unsigned long long tick_to_time(unsigned long long tick)
 {
-	unsigned int *pTime = (unsigned int *)data;
-
-	(*pTime)++;
-
-	/*
-	 * Reset IRQ source
-	 */
-	*IXP425_OSST = IXP425_OSST_TIMER_2_PEND;
+	tick *= CONFIG_SYS_HZ;
+	do_div(tick, CONFIG_IXP425_TIMER_CLK);
+	return tick;
 }
 
-ulong get_timer (ulong base)
+static inline unsigned long long time_to_tick(unsigned long long time)
 {
-	return timestamp - base;
+	time *= CONFIG_IXP425_TIMER_CLK;
+	do_div(time, CONFIG_SYS_HZ);
+	return time;
 }
 
-void reset_timer (void)
+static inline unsigned long long us_to_tick(unsigned long long us)
 {
-	timestamp = 0;
+	us = us * CONFIG_IXP425_TIMER_CLK + 999999;
+	do_div(us, 1000000);
+	return us;
 }
 
-int timer_init (void)
+unsigned long long get_ticks(void)
 {
-	/* install interrupt handler for timer */
-	irq_install_handler(IXP425_TIMER_2_IRQ, timer_isr, (void *)&timestamp);
+	ulong now = readl(IXP425_OSTS_B);
 
-	/* setup the Timer counter value */
-	*IXP425_OSRT2 = (LATCH & ~IXP425_OST_RELOAD_MASK) | IXP425_OST_ENABLE;
-
-	/* enable timer irq */
-	*IXP425_ICMR = (1 << IXP425_TIMER_2_IRQ);
-
-	return 0;
-}
-#else
-ulong get_timer (ulong base)
-{
-       return get_timer_masked () - base;
-}
-
-void ixp425_udelay(unsigned long usec)
-{
-	/*
-	 * This function has a max usec, but since it is called from udelay
-	 * we should not have to worry... be happy
-	 */
-	unsigned long usecs = CONFIG_SYS_HZ/1000000L & ~IXP425_OST_RELOAD_MASK;
-
-	*IXP425_OSST = IXP425_OSST_TIMER_1_PEND;
-	usecs |= IXP425_OST_ONE_SHOT | IXP425_OST_ENABLE;
-	*IXP425_OSRT1 = usecs;
-	while (!(*IXP425_OSST & IXP425_OSST_TIMER_1_PEND));
-}
-
-void __udelay (unsigned long usec)
-{
-	while (usec--) ixp425_udelay(1);
-}
-
-static ulong reload_constant = 0xfffffff0;
-
-void reset_timer_masked (void)
-{
-	ulong reload = reload_constant | IXP425_OST_ONE_SHOT | IXP425_OST_ENABLE;
-
-	*IXP425_OSST = IXP425_OSST_TIMER_1_PEND;
-	*IXP425_OSRT1 = reload;
-}
-
-ulong get_timer_masked (void)
-{
-	/*
-	 * Note that it is possible for this to wrap!
-	 * In this case we return max.
-	 */
-	ulong current = *IXP425_OST1;
-	if (*IXP425_OSST & IXP425_OSST_TIMER_1_PEND)
-	{
-		return reload_constant;
+	if (readl(IXP425_OSST) & IXP425_OSST_TIMER_TS_PEND) {
+		/* rollover of timestamp timer register */
+		gd->timestamp += (0xFFFFFFFF - gd->lastinc) + now + 1;
+		writel(IXP425_OSST_TIMER_TS_PEND, IXP425_OSST);
+	} else {
+		/* move stamp forward with absolut diff ticks */
+		gd->timestamp += (now - gd->lastinc);
 	}
-	return (reload_constant - current);
+	gd->lastinc = now;
+	return gd->timestamp;
+}
+
+
+void reset_timer_masked(void)
+{
+	/* capture current timestamp counter */
+	gd->lastinc = readl(IXP425_OSTS_B);
+	/* start "advancing" time stamp from 0 */
+	gd->timestamp = 0;
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+ulong get_timer_masked(void)
+{
+	return tick_to_time(get_ticks());
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+	gd->timestamp = time_to_tick(t);
+}
+
+/* delay x useconds AND preserve advance timestamp value */
+void __udelay(unsigned long usec)
+{
+	unsigned long long tmp;
+
+	tmp = get_ticks() + us_to_tick(usec);
+
+	while (get_ticks() < tmp)
+		;
 }
 
 int timer_init(void)
 {
+	writel(IXP425_OSST_TIMER_TS_PEND, IXP425_OSST);
 	return 0;
 }
-#endif

arch/arm/cpu/ixp/u-boot.lds

@@ -31,8 +31,8 @@ SECTIONS
 	. = ALIGN(4);
 	.text :
 	{
-		arch/arm/cpu/ixp/start.o(.text)
-		*(.text)
+		arch/arm/cpu/ixp/start.o(.text*)
+		*(.text*)
 	}
 
 	. = ALIGN(4);
@@ -40,7 +40,7 @@ SECTIONS
 
 	. = ALIGN(4);
 	.data : {
-		*(.data)
+		*(.data*)
 	}
 
 	. = ALIGN(4);
@@ -67,7 +67,7 @@ SECTIONS
 
 	.bss __rel_dyn_start (OVERLAY) : {
 		__bss_start = .;
-		*(.bss)
+		*(.bss*)
 		 . = ALIGN(4);
 		__bss_end__ = .;
 	}

arch/arm/include/asm/arch-at91/at91_matrix.h

@@ -26,18 +26,18 @@
 #ifdef __ASSEMBLY__
 
 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
-#define AT91_ASM_MATRIX_CSA0	(AT91_MATRIX_BASE + 0x11C)
+#define AT91_ASM_MATRIX_CSA0	(ATMEL_BASE_MATRIX + 0x11C)
 #elif defined(CONFIG_AT91SAM9261)
-#define AT91_ASM_MATRIX_CSA0	(AT91_MATRIX_BASE + 0x30)
+#define AT91_ASM_MATRIX_CSA0	(ATMEL_BASE_MATRIX + 0x30)
 #elif defined(CONFIG_AT91SAM9263)
-#define AT91_ASM_MATRIX_CSA0	(AT91_MATRIX_BASE + 0x120)
+#define AT91_ASM_MATRIX_CSA0	(ATMEL_BASE_MATRIX + 0x120)
 #elif defined(CONFIG_AT91SAM9G45)
-#define AT91_ASM_MATRIX_CSA0	(AT91_MATRIX_BASE + 0x128)
+#define AT91_ASM_MATRIX_CSA0	(ATMEL_BASE_MATRIX + 0x128)
 #else
 #error AT91_ASM_MATRIX_CSA0 is not definied for current CPU
 #endif
 
-#define AT91_ASM_MATRIX_MCFG	AT91_MATRIX_BASE
+#define AT91_ASM_MATRIX_MCFG	ATMEL_BASE_MATRIX
 
 #else
 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)

arch/arm/include/asm/arch-at91/at91_mc.h

@@ -23,12 +23,12 @@
 #ifndef AT91_MC_H
 #define AT91_MC_H
 
-#define AT91_ASM_MC_EBI_CSA	(AT91_MC_BASE + 0x60)
-#define AT91_ASM_MC_EBI_CFG	(AT91_MC_BASE + 0x64)
-#define AT91_ASM_MC_SMC_CSR0	(AT91_MC_BASE + 0x70)
-#define AT91_ASM_MC_SDRAMC_MR	(AT91_MC_BASE + 0x90)
-#define AT91_ASM_MC_SDRAMC_TR	(AT91_MC_BASE + 0x94)
-#define AT91_ASM_MC_SDRAMC_CR	(AT91_MC_BASE + 0x98)
+#define AT91_ASM_MC_EBI_CSA	(ATMEL_BASE_MC + 0x60)
+#define AT91_ASM_MC_EBI_CFG	(ATMEL_BASE_MC + 0x64)
+#define AT91_ASM_MC_SMC_CSR0	(ATMEL_BASE_MC + 0x70)
+#define AT91_ASM_MC_SDRAMC_MR	(ATMEL_BASE_MC + 0x90)
+#define AT91_ASM_MC_SDRAMC_TR	(ATMEL_BASE_MC + 0x94)
+#define AT91_ASM_MC_SDRAMC_CR	(ATMEL_BASE_MC + 0x98)
 
 #ifndef __ASSEMBLY__
 

arch/arm/include/asm/arch-at91/at91_pio.h

@@ -20,20 +20,20 @@
 
 #define AT91_ASM_PIO_RANGE	0x200
 #define AT91_ASM_PIOC_ASR	\
-	(AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70)
+	(ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70)
 #define AT91_ASM_PIOC_BSR	\
-	(AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x74)
+	(ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x74)
 #define AT91_ASM_PIOC_PDR	\
-	(AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x04)
+	(ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x04)
 #define AT91_ASM_PIOC_PUDR	\
-	(AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x60)
+	(ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x60)
 
 #define AT91_ASM_PIOD_PDR	\
-	(AT91_PIO_BASE + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x04)
+	(ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x04)
 #define AT91_ASM_PIOD_PUDR	\
-	(AT91_PIO_BASE + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x60)
+	(ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x60)
 #define AT91_ASM_PIOD_ASR	\
-	(AT91_PIO_BASE + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x70)
+	(ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x70)
 
 #ifndef __ASSEMBLY__
 

arch/arm/include/asm/arch-at91/at91_pmc.h

@@ -17,11 +17,11 @@
 #ifndef AT91_PMC_H
 #define AT91_PMC_H
 
-#define	AT91_ASM_PMC_MOR	(AT91_PMC_BASE + 0x20)
-#define	AT91_ASM_PMC_PLLAR	(AT91_PMC_BASE + 0x28)
-#define	AT91_ASM_PMC_PLLBR	(AT91_PMC_BASE + 0x2c)
-#define AT91_ASM_PMC_MCKR	(AT91_PMC_BASE + 0x30)
-#define AT91_ASM_PMC_SR		(AT91_PMC_BASE + 0x68)
+#define	AT91_ASM_PMC_MOR	(ATMEL_BASE_PMC + 0x20)
+#define	AT91_ASM_PMC_PLLAR	(ATMEL_BASE_PMC + 0x28)
+#define	AT91_ASM_PMC_PLLBR	(ATMEL_BASE_PMC + 0x2c)
+#define AT91_ASM_PMC_MCKR	(ATMEL_BASE_PMC + 0x30)
+#define AT91_ASM_PMC_SR		(ATMEL_BASE_PMC + 0x68)
 
 #ifndef __ASSEMBLY__
 

arch/arm/include/asm/arch-at91/at91_rstc.h

@@ -16,7 +16,7 @@
 #ifndef AT91_RSTC_H
 #define AT91_RSTC_H
 
-#define AT91_ASM_RSTC_MR	(AT91_RSTC_BASE + 0x08)
+#define AT91_ASM_RSTC_MR	(ATMEL_BASE_RSTC + 0x08)
 
 #ifndef __ASSEMBLY__
 

arch/arm/include/asm/arch-at91/at91_wdt.h

@@ -19,7 +19,7 @@
 
 #ifdef __ASSEMBLY__
 
-#define AT91_ASM_WDT_MR	(AT91_WDT_BASE +  0x04)
+#define AT91_ASM_WDT_MR	(ATMEL_BASE_WDT +  0x04)
 
 #else
 

arch/arm/include/asm/arch-at91/at91rm9200.h

@@ -21,115 +21,126 @@
 #ifndef __AT91RM9200_H__
 #define __AT91RM9200_H__
 
+#define CONFIG_AT91FAMILY	/* it's a member of AT91 */
+#define CONFIG_ARM920T		/* This is an ARM920T Core	*/
+
 /* Periperial Identifiers */
 
-#define AT91_ID_SYS	1	/* System Peripheral */
-#define AT91_ID_PIOA	2	/* PIO port A */
-#define AT91_ID_PIOB	3	/* PIO port B */
-#define AT91_ID_PIOC	4	/* PIO port C */
-#define AT91_ID_PIOD	5	/* PIO port D BGA only */
-#define AT91_ID_USART0	6	/* USART 0 */
-#define AT91_ID_USART1	7	/* USART 1 */
-#define AT91_ID_USART2	8	/* USART 2 */
-#define AT91_ID_USART3	9	/* USART 3 */
-#define AT91_ID_MCI	10	/* Multimedia Card Interface */
-#define AT91_ID_UDP	11	/* USB Device Port */
-#define AT91_ID_TWI	12	/* Two Wire Interface */
-#define AT91_ID_SPI	13	/* Serial Peripheral Interface */
-#define AT91_ID_SSC0	14	/* Synch. Serial Controller 0 */
-#define AT91_ID_SSC1	15	/* Synch. Serial Controller 1 */
-#define AT91_ID_SSC2	16	/* Synch. Serial Controller 2 */
-#define AT91_ID_TC0	17	/* Timer Counter 0 */
-#define AT91_ID_TC1	18	/* Timer Counter 1 */
-#define AT91_ID_TC2	19	/* Timer Counter 2 */
-#define AT91_ID_TC3	20	/* Timer Counter 3 */
-#define AT91_ID_TC4	21	/* Timer Counter 4 */
-#define AT91_ID_TC5	22	/* Timer Counter 5 */
-#define AT91_ID_UHP	23	/* OHCI USB Host Port */
-#define AT91_ID_EMAC	24	/* Ethernet MAC */
-#define AT91_ID_IRQ0	25	/* Advanced Interrupt Controller */
-#define AT91_ID_IRQ1	26	/* Advanced Interrupt Controller */
-#define AT91_ID_IRQ2	27	/* Advanced Interrupt Controller */
-#define AT91_ID_IRQ3	28	/* Advanced Interrupt Controller */
-#define AT91_ID_IRQ4	29	/* Advanced Interrupt Controller */
-#define AT91_ID_IRQ5	30	/* Advanced Interrupt Controller */
-#define AT91_ID_IRQ6	31	/* Advanced Interrupt Controller */
+#define ATMEL_ID_SYS	1	/* System Peripheral */
+#define ATMEL_ID_PIOA	2	/* PIO port A */
+#define ATMEL_ID_PIOB	3	/* PIO port B */
+#define ATMEL_ID_PIOC	4	/* PIO port C */
+#define ATMEL_ID_PIOD	5	/* PIO port D BGA only */
+#define ATMEL_ID_USART0	6	/* USART 0 */
+#define ATMEL_ID_USART1	7	/* USART 1 */
+#define ATMEL_ID_USART2	8	/* USART 2 */
+#define ATMEL_ID_USART3	9	/* USART 3 */
+#define ATMEL_ID_MCI	10	/* Multimedia Card Interface */
+#define ATMEL_ID_UDP	11	/* USB Device Port */
+#define ATMEL_ID_TWI	12	/* Two Wire Interface */
+#define ATMEL_ID_SPI	13	/* Serial Peripheral Interface */
+#define ATMEL_ID_SSC0	14	/* Synch. Serial Controller 0 */
+#define ATMEL_ID_SSC1	15	/* Synch. Serial Controller 1 */
+#define ATMEL_ID_SSC2	16	/* Synch. Serial Controller 2 */
+#define ATMEL_ID_TC0	17	/* Timer Counter 0 */
+#define ATMEL_ID_TC1	18	/* Timer Counter 1 */
+#define ATMEL_ID_TC2	19	/* Timer Counter 2 */
+#define ATMEL_ID_TC3	20	/* Timer Counter 3 */
+#define ATMEL_ID_TC4	21	/* Timer Counter 4 */
+#define ATMEL_ID_TC5	22	/* Timer Counter 5 */
+#define ATMEL_ID_UHP	23	/* OHCI USB Host Port */
+#define ATMEL_ID_EMAC	24	/* Ethernet MAC */
+#define ATMEL_ID_IRQ0	25	/* Advanced Interrupt Controller */
+#define ATMEL_ID_IRQ1	26	/* Advanced Interrupt Controller */
+#define ATMEL_ID_IRQ2	27	/* Advanced Interrupt Controller */
+#define ATMEL_ID_IRQ3	28	/* Advanced Interrupt Controller */
+#define ATMEL_ID_IRQ4	29	/* Advanced Interrupt Controller */
+#define ATMEL_ID_IRQ5	30	/* Advanced Interrupt Controller */
+#define ATMEL_ID_IRQ6	31	/* Advanced Interrupt Controller */
 
-#define AT91_USB_HOST_BASE	0x00300000
+#define ATMEL_USB_HOST_BASE	0x00300000
 
-#define AT91_TC_BASE		0xFFFA0000
-#define AT91_UDP_BASE		0xFFFB0000
-#define AT91_MCI_BASE		0xFFFB4000
-#define AT91_TWI_BASE		0xFFFB8000
-#define AT91_EMAC_BASE		0xFFFBC000
-#define AT91_USART_BASE		0xFFFC0000	/* 4x 0x4000 Offset */
-#define AT91_SCC_BASE		0xFFFD0000	/* 4x 0x4000 Offset */
-#define AT91_SPI_BASE		0xFFFE0000
+#define ATMEL_BASE_TC		0xFFFA0000
+#define ATMEL_BASE_UDP		0xFFFB0000
+#define ATMEL_BASE_MCI		0xFFFB4000
+#define ATMEL_BASE_TWI		0xFFFB8000
+#define ATMEL_BASE_EMAC		0xFFFBC000
+#define ATMEL_BASE_USART	0xFFFC0000	/* 4x 0x4000 Offset */
+#define ATMEL_BASE_USART0	ATMEL_BASE_USART
+#define ATMEL_BASE_USART1	(ATMEL_BASE_USART + 0x4000)
+#define ATMEL_BASE_USART2	(ATMEL_BASE_USART + 0x8000)
+#define ATMEL_BASE_USART3	(ATMEL_BASE_USART + 0xC000)
 
-#define AT91_AIC_BASE		0xFFFFF000
-#define AT91_DBGU_BASE		0xFFFFF200
-#define AT91_PIO_BASE		0xFFFFF400	/* 4x 0x200 Offset */
-#define AT91_PMC_BASE		0xFFFFFC00
-#define AT91_ST_BASE		0xFFFFFD00
-#define AT91_ST_BASE		0xFFFFFD00
-#define AT91_RTC_BASE		0xFFFFFE00
-#define AT91_MC_BASE		0xFFFFFF00
+#define ATMEL_BASE_SCC		0xFFFD0000	/* 4x 0x4000 Offset */
+#define ATMEL_BASE_SPI		0xFFFE0000
 
+#define ATMEL_BASE_AIC		0xFFFFF000
+#define ATMEL_BASE_DBGU		0xFFFFF200
+#define ATMEL_BASE_PIO		0xFFFFF400	/* 4x 0x200 Offset */
+#define ATMEL_BASE_PMC		0xFFFFFC00
+#define ATMEL_BASE_ST		0xFFFFFD00
+#define ATMEL_BASE_RTC		0xFFFFFE00
+#define ATMEL_BASE_MC		0xFFFFFF00
+
+#define AT91_PIO_BASE	ATMEL_BASE_PIO
 
 /* AT91RM9200 Periperial Multiplexing A */
 /* Port A */
-#define AT91_PMX_AA_EREFCK	0x00000080
-#define AT91_PMX_AA_ETXCK	0x00000080
-#define AT91_PMX_AA_ETXEN	0x00000100
-#define AT91_PMX_AA_ETX0	0x00000200
-#define AT91_PMX_AA_ETX1	0x00000400
-#define AT91_PMX_AA_ECRS	0x00000800
-#define AT91_PMX_AA_ECRSDV	0x00000800
-#define AT91_PMX_AA_ERX0	0x00001000
-#define AT91_PMX_AA_ERX1	0x00002000
-#define AT91_PMX_AA_ERXER	0x00004000
-#define AT91_PMX_AA_EMDC	0x00008000
-#define AT91_PMX_AA_EMDIO	0x00010000
+#define ATMEL_PMX_AA_EREFCK	0x00000080
+#define ATMEL_PMX_AA_ETXCK	0x00000080
+#define ATMEL_PMX_AA_ETXEN	0x00000100
+#define ATMEL_PMX_AA_ETX0	0x00000200
+#define ATMEL_PMX_AA_ETX1	0x00000400
+#define ATMEL_PMX_AA_ECRS	0x00000800
+#define ATMEL_PMX_AA_ECRSDV	0x00000800
+#define ATMEL_PMX_AA_ERX0	0x00001000
+#define ATMEL_PMX_AA_ERX1	0x00002000
+#define ATMEL_PMX_AA_ERXER	0x00004000
+#define ATMEL_PMX_AA_EMDC	0x00008000
+#define ATMEL_PMX_AA_EMDIO	0x00010000
 
-#define AT91_PMX_AA_TXD2	0x00810000
+#define ATMEL_PMX_AA_TXD2	0x00810000
 
-#define AT91_PMX_AA_TWD		0x02000000
-#define AT91_PMX_AA_TWCK	0x04000000
+#define ATMEL_PMX_AA_TWD	0x02000000
+#define ATMEL_PMX_AA_TWCK	0x04000000
 
 /* Port B */
-#define AT91_PMX_BA_ERXCK	0x00080000
-#define AT91_PMX_BA_ECOL	0x00040000
-#define AT91_PMX_BA_ERXDV	0x00020000
-#define AT91_PMX_BA_ERX3	0x00010000
-#define AT91_PMX_BA_ERX2 	0x00008000
-#define AT91_PMX_BA_ETXER	0x00004000
-#define AT91_PMX_BA_ETX3	0x00002000
-#define AT91_PMX_BA_ETX2	0x00001000
+#define ATMEL_PMX_BA_ERXCK	0x00080000
+#define ATMEL_PMX_BA_ECOL	0x00040000
+#define ATMEL_PMX_BA_ERXDV	0x00020000
+#define ATMEL_PMX_BA_ERX3	0x00010000
+#define ATMEL_PMX_BA_ERX2	0x00008000
+#define ATMEL_PMX_BA_ETXER	0x00004000
+#define ATMEL_PMX_BA_ETX3	0x00002000
+#define ATMEL_PMX_BA_ETX2	0x00001000
 
 /* Port B */
 
-#define AT91_PMX_CA_BFCK	0x00000001
-#define AT91_PMX_CA_BFRDY	0x00000002
-#define AT91_PMX_CA_SMOE	0x00000002
-#define AT91_PMX_CA_BFAVD	0x00000004
-#define AT91_PMX_CA_BFBAA	0x00000008
-#define AT91_PMX_CA_SMWE	0x00000008
-#define AT91_PMX_CA_BFOE	0x00000010
-#define AT91_PMX_CA_BFWE	0x00000020
-#define AT91_PMX_CA_NWAIT	0x00000040
-#define AT91_PMX_CA_A23		0x00000080
-#define AT91_PMX_CA_A24		0x00000100
-#define AT91_PMX_CA_A25		0x00000200
-#define AT91_PMX_CA_CFRNW	0x00000200
-#define AT91_PMX_CA_NCS4	0x00000400
-#define AT91_PMX_CA_CFCS	0x00000400
-#define AT91_PMX_CA_NCS5	0x00000800
-#define AT91_PMX_CA_CFCE1	0x00001000
-#define AT91_PMX_CA_NCS6	0x00001000
-#define AT91_PMX_CA_CFCE2	0x00002000
-#define AT91_PMX_CA_NCS7	0x00002000
-#define AT91_PMX_CA_D16_31	0xFFFF0000
+#define ATMEL_PMX_CA_BFCK	0x00000001
+#define ATMEL_PMX_CA_BFRDY	0x00000002
+#define ATMEL_PMX_CA_SMOE	0x00000002
+#define ATMEL_PMX_CA_BFAVD	0x00000004
+#define ATMEL_PMX_CA_BFBAA	0x00000008
+#define ATMEL_PMX_CA_SMWE	0x00000008
+#define ATMEL_PMX_CA_BFOE	0x00000010
+#define ATMEL_PMX_CA_BFWE	0x00000020
+#define ATMEL_PMX_CA_NWAIT	0x00000040
+#define ATMEL_PMX_CA_A23	0x00000080
+#define ATMEL_PMX_CA_A24	0x00000100
+#define ATMEL_PMX_CA_A25	0x00000200
+#define ATMEL_PMX_CA_CFRNW	0x00000200
+#define ATMEL_PMX_CA_NCS4	0x00000400
+#define ATMEL_PMX_CA_CFCS	0x00000400
+#define ATMEL_PMX_CA_NCS5	0x00000800
+#define ATMEL_PMX_CA_CFCE1	0x00001000
+#define ATMEL_PMX_CA_NCS6	0x00001000
+#define ATMEL_PMX_CA_CFCE2	0x00002000
+#define ATMEL_PMX_CA_NCS7	0x00002000
+#define ATMEL_PMX_CA_D16_31	0xFFFF0000
 
-#define CONFIG_SYS_AT91_CPU_NAME	"AT91RM9200"
+#define ATMEL_PIO_PORTS		4	/* theese SoCs have 4 PIO */
+#define ATMEL_PMC_UHP		AT91RM9200_PMC_UHP
+
+#define CONFIG_SYS_ATMEL_CPU_NAME	"AT91RM9200"
 
 #endif

arch/arm/include/asm/arch-at91/at91sam9260.h

@@ -141,6 +141,7 @@
  */
 #define ATMEL_PIO_PORTS		3		/* these SoCs have 3 PIO */
 #define ATMEL_PMC_UHP		AT91SAM926x_PMC_UHP
+#define ATMEL_BASE_PIO		ATMEL_BASE_PIOA
 
 /*
  * SoC specific defines

arch/arm/include/asm/arch-at91/at91sam9261.h

@@ -125,6 +125,7 @@
  * Other misc defines
  */
 #define ATMEL_PIO_PORTS		3		/* theese SoCs have 3 PIO */
+#define ATMEL_BASE_PIO		ATMEL_BASE_PIOA
 
 /*
  * SoC specific defines

arch/arm/include/asm/arch-at91/at91sam9263.h

@@ -128,6 +128,7 @@
  * Other misc defines
  */
 #define ATMEL_PIO_PORTS		5		/* this SoCs has 5 PIO */
+#define ATMEL_BASE_PIO		ATMEL_BASE_PIOA
 
 /*
  * Cpu Name

arch/arm/include/asm/arch-at91/at91sam9_sdramc.h

@@ -19,19 +19,19 @@
 
 #ifdef __ASSEMBLY__
 
-#ifndef AT91_SDRAMC_BASE
-#define AT91_SDRAMC_BASE	AT91_SDRAMC0_BASE
+#ifndef ATMEL_BASE_SDRAMC
+#define ATMEL_BASE_SDRAMC	AT91_SDRAMC0_BASE
 #endif
 
-#define AT91_ASM_SDRAMC_MR	AT91_SDRAMC_BASE
-#define AT91_ASM_SDRAMC_TR	(AT91_SDRAMC_BASE + 0x04)
-#define AT91_ASM_SDRAMC_CR	(AT91_SDRAMC_BASE + 0x08)
-#define AT91_ASM_SDRAMC_MDR	(AT91_SDRAMC_BASE + 0x24)
+#define AT91_ASM_SDRAMC_MR	ATMEL_BASE_SDRAMC
+#define AT91_ASM_SDRAMC_TR	(ATMEL_BASE_SDRAMC + 0x04)
+#define AT91_ASM_SDRAMC_CR	(ATMEL_BASE_SDRAMC + 0x08)
+#define AT91_ASM_SDRAMC_MDR	(ATMEL_BASE_SDRAMC + 0x24)
 
 #endif
 
 /* SDRAM Controller (SDRAMC) registers */
-#define AT91_SDRAMC_MR		(AT91_SDRAMC + 0x00)	/* SDRAM Controller Mode Register */
+#define AT91_SDRAMC_MR		(ATMEL_BASE_SDRAMC + 0x00)	/* SDRAM Controller Mode Register */
 #define		AT91_SDRAMC_MODE	(0xf << 0)		/* Command Mode */
 #define			AT91_SDRAMC_MODE_NORMAL		0
 #define			AT91_SDRAMC_MODE_NOP		1
@@ -41,10 +41,10 @@
 #define			AT91_SDRAMC_MODE_EXT_LMR	5
 #define			AT91_SDRAMC_MODE_DEEP		6
 
-#define AT91_SDRAMC_TR		(AT91_SDRAMC + 0x04)	/* SDRAM Controller Refresh Timer Register */
+#define AT91_SDRAMC_TR		(ATMEL_BASE_SDRAMC + 0x04)	/* SDRAM Controller Refresh Timer Register */
 #define		AT91_SDRAMC_COUNT	(0xfff << 0)		/* Refresh Timer Counter */
 
-#define AT91_SDRAMC_CR		(AT91_SDRAMC + 0x08)	/* SDRAM Controller Configuration Register */
+#define AT91_SDRAMC_CR		(ATMEL_BASE_SDRAMC + 0x08)	/* SDRAM Controller Configuration Register */
 #define		AT91_SDRAMC_NC		(3 << 0)		/* Number of Column Bits */
 #define			AT91_SDRAMC_NC_8	(0 << 0)
 #define			AT91_SDRAMC_NC_9	(1 << 0)
@@ -71,7 +71,7 @@
 #define		AT91_SDRAMC_TRAS	(0xf << 24)		/* Active to Precharge Delay */
 #define		AT91_SDRAMC_TXSR	(0xf << 28)		/* Exit Self Refresh to Active Delay */
 
-#define AT91_SDRAMC_LPR		(AT91_SDRAMC + 0x10)	/* SDRAM Controller Low Power Register */
+#define AT91_SDRAMC_LPR		(ATMEL_BASE_SDRAMC + 0x10)	/* SDRAM Controller Low Power Register */
 #define		AT91_SDRAMC_LPCB		(3 << 0)	/* Low-power Configurations */
 #define			AT91_SDRAMC_LPCB_DISABLE		0
 #define			AT91_SDRAMC_LPCB_SELF_REFRESH		1
@@ -85,13 +85,13 @@
 #define			AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES	(1 << 12)
 #define			AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES	(2 << 12)
 
-#define AT91_SDRAMC_IER		(AT91_SDRAMC + 0x14)	/* SDRAM Controller Interrupt Enable Register */
-#define AT91_SDRAMC_IDR		(AT91_SDRAMC + 0x18)	/* SDRAM Controller Interrupt Disable Register */
-#define AT91_SDRAMC_IMR		(AT91_SDRAMC + 0x1C)	/* SDRAM Controller Interrupt Mask Register */
-#define AT91_SDRAMC_ISR		(AT91_SDRAMC + 0x20)	/* SDRAM Controller Interrupt Status Register */
+#define AT91_SDRAMC_IER		(ATMEL_BASE_SDRAMC + 0x14)	/* SDRAM Controller Interrupt Enable Register */
+#define AT91_SDRAMC_IDR		(ATMEL_BASE_SDRAMC + 0x18)	/* SDRAM Controller Interrupt Disable Register */
+#define AT91_SDRAMC_IMR		(ATMEL_BASE_SDRAMC + 0x1C)	/* SDRAM Controller Interrupt Mask Register */
+#define AT91_SDRAMC_ISR		(ATMEL_BASE_SDRAMC + 0x20)	/* SDRAM Controller Interrupt Status Register */
 #define		AT91_SDRAMC_RES		(1 << 0)		/* Refresh Error Status */
 
-#define AT91_SDRAMC_MDR		(AT91_SDRAMC + 0x24)	/* SDRAM Memory Device Register */
+#define AT91_SDRAMC_MDR		(ATMEL_BASE_SDRAMC + 0x24)	/* SDRAM Memory Device Register */
 #define		AT91_SDRAMC_MD		(3 << 0)		/* Memory Device Type */
 #define			AT91_SDRAMC_MD_SDRAM		0
 #define			AT91_SDRAMC_MD_LOW_POWER_SDRAM	1

arch/arm/include/asm/arch-at91/at91sam9_smc.h

@@ -18,14 +18,14 @@
 
 #ifdef __ASSEMBLY__
 
-#ifndef AT91_SMC_BASE
-#define AT91_SMC_BASE	AT91_SMC0_BASE
+#ifndef ATMEL_BASE_SMC
+#define ATMEL_BASE_SMC	ATMEL_BASE_SMC0
 #endif
 
-#define AT91_ASM_SMC_SETUP0	AT91_SMC_BASE
-#define AT91_ASM_SMC_PULSE0	(AT91_SMC_BASE + 0x04)
-#define AT91_ASM_SMC_CYCLE0	(AT91_SMC_BASE + 0x08)
-#define AT91_ASM_SMC_MODE0	(AT91_SMC_BASE + 0x0C)
+#define AT91_ASM_SMC_SETUP0	ATMEL_BASE_SMC
+#define AT91_ASM_SMC_PULSE0	(ATMEL_BASE_SMC + 0x04)
+#define AT91_ASM_SMC_CYCLE0	(ATMEL_BASE_SMC + 0x08)
+#define AT91_ASM_SMC_MODE0	(ATMEL_BASE_SMC + 0x0C)
 
 #else
 

arch/arm/include/asm/arch-ixp/ixp425.h

@@ -391,9 +391,8 @@
 #define IXP425_TIMER_REG(x) (IXP425_TIMER_BASE_PHYS+(x))
 #endif
 
-#if 0 /* test-only: also defined in npe/include/... */
-#define IXP425_OSTS	IXP425_TIMER_REG(IXP425_OSTS_OFFSET)
-#endif
+/* _B to avoid collision: also defined in npe/include/... */
+#define IXP425_OSTS_B	IXP425_TIMER_REG(IXP425_OSTS_OFFSET)
 #define IXP425_OST1	IXP425_TIMER_REG(IXP425_OST1_OFFSET)
 #define IXP425_OSRT1	IXP425_TIMER_REG(IXP425_OSRT1_OFFSET)
 #define IXP425_OST2	IXP425_TIMER_REG(IXP425_OST2_OFFSET)

arch/arm/include/asm/arch-ixp/ixp425pci.h

@@ -22,88 +22,21 @@
  * MA 02111-1307 USA
  */
 
-#ifndef _IXP425PCI_H_
-#define _IXP425PCI_H_
+#ifndef _IXP425PCI_H
+#define _IXP425PCI_H
 
-#define TRUE	1
-#define FALSE	0
 #define OK	0
 #define ERROR	-1
-#define BOOL	int
 
-#define IXP425_PCI_MAX_BAR_PER_FUNC  6
-#define IXP425_PCI_MAX_BAR (IXP425_PCI_MAX_BAR_PER_FUNC * \
-			    IXP425_PCI_MAX_FUNC_ON_BUS)
-
-enum PciBarId
-{
-	CSR_BAR=0,
-	IO_BAR,
-	SD_BAR,
-	NO_BAR
-};
-
-/*Base address register descriptor*/
-typedef struct
-{
-	unsigned int size;
-	unsigned int address;
-} PciBar;
-
-typedef struct
-{
-	unsigned int bus;
-	unsigned int device;
-	unsigned int func;
-	unsigned int irq;
-	BOOL error;
-	unsigned short vendor_id;
-	unsigned short device_id;
-	/*We need an extra entry in this array for dummy placeholder*/
-	PciBar bar[IXP425_PCI_MAX_BAR_PER_FUNC + 1];
-} PciDevice;
+struct pci_controller;
+extern void pci_ixp_init(struct pci_controller *hose);
 
 /* Mask definitions*/
-#define IXP425_PCI_TOP_WORD_OF_LONG_MASK	0xffff0000
-#define IXP425_PCI_TOP_BYTE_OF_LONG_MASK	0xff000000
-#define IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK	0x0000ffff
-#define IXP425_PCI_BOTTOM_TRIBYTES_OF_LONG_MASK 0x00ffffff
 #define IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK	0x0000000f
-#define IXP425_PCI_MAX_UINT32			0xffffffff
-
-
-#define IXP425_PCI_BAR_QUERY			0xffffffff
-
-#define IXP425_PCI_BAR_MEM_BASE 0x100000
-#define IXP425_PCI_BAR_IO_BASE	0x000000
-
-/*define the maximum number of bus segments - we support a single segment*/
-#define IXP425_PCI_MAX_BUS  1
-/*define the maximum number of cards per bus segment*/
-#define IXP425_PCI_MAX_DEV  4
-/*define the maximum number of functions per device*/
-#define IXP425_PCI_MAX_FUNC 8
-/* define the maximum number of separate functions that we can
-   potentially have on the bus*/
-#define IXP425_PCI_MAX_FUNC_ON_BUS (1+ IXP425_PCI_MAX_FUNC *	\
-				    IXP425_PCI_MAX_DEV *	\
-				    IXP425_PCI_MAX_BUS)
-/*define the maximum number of BARs per function*/
-#define IXP425_PCI_MAX_BAR_PER_FUNC  6
-#define IXP425_PCI_MAX_BAR (IXP425_PCI_MAX_BAR_PER_FUNC *	\
-			    IXP425_PCI_MAX_FUNC_ON_BUS)
 
 #define PCI_NP_CBE_BESL	 (4)
 #define PCI_NP_AD_FUNCSL (8)
 
-#define REG_WRITE(b,o,v) (*(volatile unsigned int*)((b+o))=(v))
-#define REG_READ(b,o,v)	 ((v)=(*(volatile unsigned int*)((b+o))))
-
-#define PCI_DELAY	500
-#define USEC_LOOP_COUNT 533
-#define PCI_SETTLE_USEC 200
-#define PCI_MIN_RESET_ASSERT_USEC 2000
-
 /*Register addressing definitions for PCI controller configuration
   and status registers*/
 
@@ -150,28 +83,6 @@ typedef struct
 #define NP_CMD_CONFIGWRITE (0xb)
 */
 
-/*define the default setting of the AHB memory base reg*/
-#define IXP425_PCI_AHBMEMBASE_DEFAULT 0x00010203
-#define IXP425_PCI_AHBIOBASE_DEFAULT  0x0
-#define IXP425_PCI_PCIMEMBASE_DEFAULT 0x0
-
-/*define the default settings for the controller's BARs*/
-#ifdef IXP425_PCI_SIMPLE_MAPPING
-#define IXP425_PCI_BAR_0_DEFAULT 0x00000000
-#define IXP425_PCI_BAR_1_DEFAULT 0x01000000
-#define IXP425_PCI_BAR_2_DEFAULT 0x02000000
-#define IXP425_PCI_BAR_3_DEFAULT 0x03000000
-#define IXP425_PCI_BAR_4_DEFAULT 0x00000000
-#define IXP425_PCI_BAR_5_DEFAULT 0x00000000
-#else
-#define IXP425_PCI_BAR_0_DEFAULT 0x40000000
-#define IXP425_PCI_BAR_1_DEFAULT 0x41000000
-#define IXP425_PCI_BAR_2_DEFAULT 0x42000000
-#define IXP425_PCI_BAR_3_DEFAULT 0x43000000
-#define IXP425_PCI_BAR_4_DEFAULT 0x00000000
-#define IXP425_PCI_BAR_5_DEFAULT 0x00000000
-#endif
-
 /*Configuration Port register bit definitions*/
 #define PCI_CRP_WRITE BIT(16)
 
@@ -228,17 +139,6 @@ typedef struct
 #define PCI_CFG_SPECIAL_USE	0x41
 #define PCI_CFG_MODE		0x43
 
-/*Specify the initial command we send to PCI devices*/
-#define INITIAL_PCI_CMD (PCI_CMD_IO_ENABLE	   \
-			 | PCI_CMD_MEM_ENABLE	   \
-			 | PCI_CMD_MASTER_ENABLE   \
-			 | PCI_CMD_WI_ENABLE)
-
-/*define the sub vendor and subsystem to be used */
-#define IXP425_PCI_SUB_VENDOR_SYSTEM 0x00000000
-
-#define PCI_IRQ_LINES		4
-
 #define PCI_CMD_IO_ENABLE	0x0001	/* IO access enable */
 #define PCI_CMD_MEM_ENABLE	0x0002	/* memory access enable */
 #define PCI_CMD_MASTER_ENABLE	0x0004	/* bus master enable */
@@ -287,26 +187,4 @@ typedef struct
 #define PCI_DMACTRL_PADC1   BIT(14)
 #define PCI_DMACTRL_PADE1   BIT(15)
 
-/* GPIO related register */
-#undef IXP425_GPIO_GPOUTR
-#undef IXP425_GPIO_GPOER
-#undef IXP425_GPIO_GPINR
-#undef IXP425_GPIO_GPISR
-#undef IXP425_GPIO_GPIT1R
-#undef IXP425_GPIO_GPIT2R
-#undef IXP425_GPIO_GPCLKR
-
-#define IXP425_GPIO_GPOUTR	0xC8004000
-#define IXP425_GPIO_GPOER	0xC8004004
-#define IXP425_GPIO_GPINR	0xC8004008
-#define IXP425_GPIO_GPISR	0xC800400C
-#define IXP425_GPIO_GPIT1R	0xC8004010
-#define IXP425_GPIO_GPIT2R	0xC8004014
-#define IXP425_GPIO_GPCLKR	0xC8004018
-
-#define READ_GPIO_REG(addr,val) \
-		(val) = *((volatile int *)(addr));
-#define WRITE_GPIO_REG(addr,val) \
-		*((volatile int *)(addr)) = (val);
-
 #endif

arch/arm/include/asm/arch-mx31/clock.h

@@ -32,5 +32,6 @@ extern void mx31_set_pad(enum iomux_pins pin, u32 config);
 void mx31_uart1_hw_init(void);
 void mx31_spi2_hw_init(void);
 void mxc_hw_watchdog_enable(void);
+void mxc_hw_watchdog_reset(void);
 
 #endif /* __ASM_ARCH_CLOCK_H */

arch/arm/include/asm/arch-s5pc1xx/clk.h

@@ -33,5 +33,6 @@ unsigned long get_pll_clk(int pllreg);
 unsigned long get_arm_clk(void);
 unsigned long get_pwm_clk(void);
 unsigned long get_uart_clk(int dev_index);
+void set_mmc_clk(int dev_index, unsigned int div);
 
 #endif

arch/arm/include/asm/arch-s5pc1xx/gpio.h

@@ -149,8 +149,8 @@ void gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
 
 /* Drive Strength level */
 #define GPIO_DRV_1X	0x0
-#define GPIO_DRV_2X	0x1
-#define GPIO_DRV_3X	0x2
+#define GPIO_DRV_3X	0x1
+#define GPIO_DRV_2X	0x2
 #define GPIO_DRV_4X	0x3
 #define GPIO_DRV_FAST	0x0
 #define GPIO_DRV_SLOW	0x1

arch/arm/include/asm/arch-s5pc1xx/mmc.h

@@ -64,6 +64,7 @@ struct mmc_host {
 	struct s5p_mmc *reg;
 	unsigned int version;	/* SDHCI spec. version */
 	unsigned int clock;	/* Current clock (MHz) */
+	int dev_index;
 };
 
 int s5p_mmc_init(int dev_index, int bus_width);

arch/arm/include/asm/arch-s5pc1xx/sromc.h

@@ -23,8 +23,8 @@
  * 	 Only SROMC is defined as of now
  */
 
-#ifndef __ASM_ARCH_SMC_H_
-#define __ASM_ARCH_SMC_H_
+#ifndef __ASM_ARCH_SROMC_H_
+#define __ASM_ARCH_SROMC_H_
 
 #define SMC_DATA16_WIDTH(x)    (1<<((x*4)+0))
 #define SMC_BYTE_ADDR_MODE(x)  (1<<((x*4)+1))  /* 0-> Half-word base address*/
@@ -41,13 +41,13 @@
 #define SMC_BC_PMC(x)  (x << 0)  /* normal(1data)page mode configuration */
 
 #ifndef __ASSEMBLY__
-struct s5pc1xx_smc {
+struct s5p_sromc {
 	unsigned int	bw;
 	unsigned int	bc[6];
 };
 #endif	/* __ASSEMBLY__ */
 
 /* Configure the Band Width and Bank Control Regs for required SROMC Bank */
-void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf);
+void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
 
 #endif /* __ASM_ARCH_SMC_H_ */

arch/arm/include/asm/arch-s5pc2xx/clk.h

@@ -32,5 +32,6 @@ unsigned long get_pll_clk(int pllreg);
 unsigned long get_arm_clk(void);
 unsigned long get_pwm_clk(void);
 unsigned long get_uart_clk(int dev_index);
+void set_mmc_clk(int dev_index, unsigned int div);
 
 #endif

arch/arm/include/asm/arch-s5pc2xx/cpu.h

@@ -51,6 +51,12 @@
 #include <asm/io.h>
 /* CPU detection macros */
 extern unsigned int s5p_cpu_id;
+extern unsigned int s5p_cpu_rev;
+
+static inline int s5p_get_cpu_rev(void)
+{
+	return s5p_cpu_rev;
+}
 
 static inline void s5p_set_cpu_id(void)
 {
@@ -61,8 +67,12 @@ static inline void s5p_set_cpu_id(void)
 	 * 0xC200: S5PC210 EVT0
 	 * 0xC210: S5PC210 EVT1
 	 */
-	if (s5p_cpu_id == 0xC200)
+	if (s5p_cpu_id == 0xC200) {
 		s5p_cpu_id |= 0x10;
+		s5p_cpu_rev = 0;
+	} else if (s5p_cpu_id == 0xC210) {
+		s5p_cpu_rev = 1;
+	}
 }
 
 #define IS_SAMSUNG_TYPE(type, id)			\

arch/arm/include/asm/arch-s5pc2xx/gpio.h

@@ -99,14 +99,13 @@ void gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
 /* Pull mode */
 #define GPIO_PULL_NONE	0x0
 #define GPIO_PULL_DOWN	0x1
-#define GPIO_PULL_UP	0x2
+#define GPIO_PULL_UP	0x3
 
 /* Drive Strength level */
 #define GPIO_DRV_1X	0x0
-#define GPIO_DRV_2X	0x1
-#define GPIO_DRV_3X	0x2
+#define GPIO_DRV_3X	0x1
+#define GPIO_DRV_2X	0x2
 #define GPIO_DRV_4X	0x3
 #define GPIO_DRV_FAST	0x0
 #define GPIO_DRV_SLOW	0x1
-
 #endif

arch/arm/include/asm/arch-s5pc2xx/mmc.h

@@ -64,6 +64,7 @@ struct mmc_host {
 	struct s5p_mmc *reg;
 	unsigned int version;	/* SDHCI spec. version */
 	unsigned int clock;	/* Current clock (MHz) */
+	int dev_index;
 };
 
 int s5p_mmc_init(int dev_index, int bus_width);

arch/arm/include/asm/arch-s5pc2xx/sromc.h

@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Naveen Krishna Ch <ch.naveen@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Note: This file contains the register description for SROMC
+ *
+ */
+
+#ifndef __ASM_ARCH_SROMC_H_
+#define __ASM_ARCH_SROMC_H_
+
+#define SROMC_DATA16_WIDTH(x)    (1<<((x*4)+0))
+#define SROMC_BYTE_ADDR_MODE(x)  (1<<((x*4)+1))  /* 0-> Half-word base address*/
+						/* 1-> Byte base address*/
+#define SROMC_WAIT_ENABLE(x)     (1<<((x*4)+2))
+#define SROMC_BYTE_ENABLE(x)     (1<<((x*4)+3))
+
+#define SROMC_BC_TACS(x) (x << 28) /* address set-up */
+#define SROMC_BC_TCOS(x) (x << 24) /* chip selection set-up */
+#define SROMC_BC_TACC(x) (x << 16) /* access cycle */
+#define SROMC_BC_TCOH(x) (x << 12) /* chip selection hold */
+#define SROMC_BC_TAH(x)  (x << 8)  /* address holding time */
+#define SROMC_BC_TACP(x) (x << 4)  /* page mode access cycle */
+#define SROMC_BC_PMC(x)  (x << 0)  /* normal(1data)page mode configuration */
+
+#ifndef __ASSEMBLY__
+struct s5p_sromc {
+	unsigned int	bw;
+	unsigned int	bc[4];
+};
+#endif	/* __ASSEMBLY__ */
+
+/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
+void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
+
+#endif /* __ASM_ARCH_SROMC_H_ */

arch/arm/include/asm/arch-u8500/clock.h

@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2009
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_CLOCK
+#define __ASM_ARCH_CLOCK
+
+struct prcmu {
+	unsigned int armclkfix_mgt;
+	unsigned int armclk_mgt;
+	unsigned int svammdspclk_mgt;
+	unsigned int siammdspclk_mgt;
+	unsigned int reserved;
+	unsigned int sgaclk_mgt;
+	unsigned int uartclk_mgt;
+	unsigned int msp02clk_mgt;
+	unsigned int i2cclk_mgt;
+	unsigned int sdmmcclk_mgt;
+	unsigned int slimclk_mgt;
+	unsigned int per1clk_mgt;
+	unsigned int per2clk_mgt;
+	unsigned int per3clk_mgt;
+	unsigned int per5clk_mgt;
+	unsigned int per6clk_mgt;
+	unsigned int per7clk_mgt;
+	unsigned int lcdclk_mgt;
+	unsigned int reserved1;
+	unsigned int bmlclk_mgt;
+	unsigned int hsitxclk_mgt;
+	unsigned int hsirxclk_mgt;
+	unsigned int hdmiclk_mgt;
+	unsigned int apeatclk_mgt;
+	unsigned int apetraceclk_mgt;
+	unsigned int mcdeclk_mgt;
+	unsigned int ipi2cclk_mgt;
+	unsigned int dsialtclk_mgt;
+	unsigned int spare2clk_mgt;
+	unsigned int dmaclk_mgt;
+	unsigned int b2r2clk_mgt;
+	unsigned int tvclk_mgt;
+	unsigned int unused[82];
+	unsigned int tcr;
+	unsigned int unused1[23];
+	unsigned int ape_softrst;
+};
+
+extern void u8500_clock_enable(int periph, int kern, int cluster);
+
+static inline void u8500_prcmu_enable(unsigned int *reg)
+{
+	writel(readl(reg) | (1 << 8), reg);
+}
+
+#endif /* __ASM_ARCH_CLOCK */

arch/arm/include/asm/arch-u8500/gpio.h

@@ -0,0 +1,247 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2009
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _UX500_GPIO_h
+#define _UX500_GPIO_h
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/u8500.h>
+
+#define GPIO_TOTAL_PINS                 268
+
+#define GPIO_PINS_PER_BLOCK	32
+#define GPIO_BLOCKS_COUNT       (GPIO_TOTAL_PINS/GPIO_PINS_PER_BLOCK + 1)
+#define GPIO_BLOCK(pin)		(((pin + GPIO_PINS_PER_BLOCK) >> 5) - 1)
+
+
+struct gpio_register {
+	u32 gpio_dat;	/* data register : 0x000 */
+	u32 gpio_dats;	/* data Set register : 0x004 */
+	u32 gpio_datc;	/* data Clear register : 0x008 */
+	u32 gpio_pdis;	/* Pull disable register : 0x00C */
+	u32 gpio_dir;	/* data direction register : 0x010 */
+	u32 gpio_dirs;	/* data dir Set register : 0x014 */
+	u32 gpio_dirc;	/* data dir Clear register : 0x018 */
+	u32 gpio_slpm;	/* Sleep mode register : 0x01C */
+	u32 gpio_afsa;	/* AltFun A Select reg : 0x020 */
+	u32 gpio_afsb;	/* AltFun B Select reg : 0x024 */
+	u32 gpio_lowemi;/* low EMI Select reg : 0x028 */
+	u32 reserved_1[(0x040 - 0x02C) >> 2];	/*0x028-0x3C Reserved*/
+	u32 gpio_rimsc;	/* rising edge intr set/clear : 0x040 */
+	u32 gpio_fimsc;	/* falling edge intr set/clear register : 0x044 */
+	u32 gpio_mis;	/* masked interrupt status register : 0x048 */
+	u32 gpio_ic;	/* Interrupt Clear register : 0x04C */
+	u32 gpio_rwimsc;/* Rising-edge Wakeup IMSC register : 0x050 */
+	u32 gpio_fwimsc;/* Falling-edge Wakeup IMSC register : 0x054 */
+	u32 gpio_wks;	/* Wakeup Status register : 0x058 */
+};
+
+/* Error values returned by functions */
+enum gpio_error {
+	GPIO_OK = 0,
+	GPIO_UNSUPPORTED_HW = -2,
+	GPIO_UNSUPPORTED_FEATURE = -3,
+	GPIO_INVALID_PARAMETER = -4,
+	GPIO_REQUEST_NOT_APPLICABLE = -5,
+	GPIO_REQUEST_PENDING = -6,
+	GPIO_NOT_CONFIGURED = -7,
+	GPIO_INTERNAL_ERROR = -8,
+	GPIO_INTERNAL_EVENT = 1,
+	GPIO_REMAINING_EVENT = 2,
+	GPIO_NO_MORE_PENDING_EVENT = 3,
+	GPIO_INVALID_CLIENT = -25,
+	GPIO_INVALID_PIN = -26,
+	GPIO_PIN_BUSY = -27,
+	GPIO_PIN_NOT_ALLOCATED = -28,
+	GPIO_WRONG_CLIENT = -29,
+	GPIO_UNSUPPORTED_ALTFUNC = -30,
+};
+
+/*GPIO DEVICE ID */
+enum gpio_device_id {
+	GPIO_DEVICE_ID_0,
+	GPIO_DEVICE_ID_1,
+	GPIO_DEVICE_ID_2,
+	GPIO_DEVICE_ID_3,
+	GPIO_DEVICE_ID_INVALID
+};
+
+/*
+ * Alternate Function:
+ *  refered in altfun_table to pointout particular altfun to be enabled
+ *  when using GPIO_ALT_FUNCTION A/B/C enable/disable operation
+ */
+enum gpio_alt_function {
+	GPIO_ALT_UART_0_MODEM,
+	GPIO_ALT_UART_0_NO_MODEM,
+	GPIO_ALT_UART_1,
+	GPIO_ALT_UART_2,
+	GPIO_ALT_I2C_0,
+	GPIO_ALT_I2C_1,
+	GPIO_ALT_I2C_2,
+	GPIO_ALT_I2C_3,
+	GPIO_ALT_MSP_0,
+	GPIO_ALT_MSP_1,
+	GPIO_ALT_MSP_2,
+	GPIO_ALT_MSP_3,
+	GPIO_ALT_MSP_4,
+	GPIO_ALT_MSP_5,
+	GPIO_ALT_SSP_0,
+	GPIO_ALT_SSP_1,
+	GPIO_ALT_MM_CARD0,
+	GPIO_ALT_SD_CARD0,
+	GPIO_ALT_DMA_0,
+	GPIO_ALT_DMA_1,
+	GPIO_ALT_HSI0,
+	GPIO_ALT_CCIR656_INPUT,
+	GPIO_ALT_CCIR656_OUTPUT,
+	GPIO_ALT_LCD_PANEL,
+	GPIO_ALT_MDIF,
+	GPIO_ALT_SDRAM,
+	GPIO_ALT_HAMAC_AUDIO_DBG,
+	GPIO_ALT_HAMAC_VIDEO_DBG,
+	GPIO_ALT_CLOCK_RESET,
+	GPIO_ALT_TSP,
+	GPIO_ALT_IRDA,
+	GPIO_ALT_USB_MINIMUM,
+	GPIO_ALT_USB_I2C,
+	GPIO_ALT_OWM,
+	GPIO_ALT_PWL,
+	GPIO_ALT_FSMC,
+	GPIO_ALT_COMP_FLASH,
+	GPIO_ALT_SRAM_NOR_FLASH,
+	GPIO_ALT_FSMC_ADDLINE_0_TO_15,
+	GPIO_ALT_SCROLL_KEY,
+	GPIO_ALT_MSHC,
+	GPIO_ALT_HPI,
+	GPIO_ALT_USB_OTG,
+	GPIO_ALT_SDIO,
+	GPIO_ALT_HSMMC,
+	GPIO_ALT_FSMC_ADD_DATA_0_TO_25,
+	GPIO_ALT_HSI1,
+	GPIO_ALT_NOR,
+	GPIO_ALT_NAND,
+	GPIO_ALT_KEYPAD,
+	GPIO_ALT_VPIP,
+	GPIO_ALT_CAM,
+	GPIO_ALT_CCP1,
+	GPIO_ALT_EMMC,
+	GPIO_ALT_POP_EMMC,
+	GPIO_ALT_FUNMAX		/* Add new alt func before this */
+};
+
+/* Defines pin assignment(Software mode or Alternate mode) */
+enum gpio_mode {
+	GPIO_MODE_LEAVE_UNCHANGED,	/* Parameter will be ignored */
+	GPIO_MODE_SOFTWARE,	/* Pin connected to GPIO (SW controlled) */
+	GPIO_ALTF_A,		/* Pin connected to altfunc 1 (HW periph 1) */
+	GPIO_ALTF_B,		/* Pin connected to altfunc 2 (HW periph 2) */
+	GPIO_ALTF_C,		/* Pin connected to altfunc 3 (HW periph 3) */
+	GPIO_ALTF_FIND,		/* Pin connected to altfunc 3 (HW periph 3) */
+	GPIO_ALTF_DISABLE	/* Pin connected to altfunc 3 (HW periph 3) */
+};
+
+/* Defines GPIO pin direction */
+enum gpio_direction {
+	GPIO_DIR_LEAVE_UNCHANGED,	/* Parameter will be ignored */
+	GPIO_DIR_INPUT,		/* GPIO set as input */
+	GPIO_DIR_OUTPUT		/* GPIO set as output */
+};
+
+/* Interrupt trigger mode */
+enum gpio_trig {
+	GPIO_TRIG_LEAVE_UNCHANGED,	/* Parameter will be ignored */
+	GPIO_TRIG_DISABLE,	/* Trigger no IT */
+	GPIO_TRIG_RISING_EDGE,	/* Trigger an IT on rising edge */
+	GPIO_TRIG_FALLING_EDGE,	/* Trigger an IT on falling edge */
+	GPIO_TRIG_BOTH_EDGES,	/* Trigger an IT on rising and falling edge */
+	GPIO_TRIG_HIGH_LEVEL,	/* Trigger an IT on high level */
+	GPIO_TRIG_LOW_LEVEL	/* Trigger an IT on low level */
+};
+
+/* Configuration parameters for one GPIO pin.*/
+struct gpio_config {
+	enum gpio_mode mode;
+	enum gpio_direction direction;
+	enum gpio_trig trig;
+	char *dev_name;		/* Who owns the gpio pin */
+};
+
+/* GPIO pin data*/
+enum gpio_data {
+	GPIO_DATA_LOW,
+	GPIO_DATA_HIGH
+};
+
+/* GPIO behaviour in sleep mode */
+enum gpio_sleep_mode {
+	GPIO_SLEEP_MODE_LEAVE_UNCHANGED,	/* Parameter will be ignored */
+	GPIO_SLEEP_MODE_INPUT_DEFAULTVOLT,	/* GPIO is an input with pull
+						   up/down enabled when in sleep
+						   mode. */
+	GPIO_SLEEP_MODE_CONTROLLED_BY_GPIO	/* GPIO pin is controlled by
+						   GPIO IP. So mode, direction
+						   and data values for GPIO pin
+						   in sleep mode are determined
+						   by configuration set to GPIO
+						   pin before entering to sleep
+						   mode. */
+};
+
+/* GPIO ability to wake the system up from sleep mode.*/
+enum gpio_wake {
+	GPIO_WAKE_LEAVE_UNCHANGED,	/* Parameter will be ignored */
+	GPIO_WAKE_DISABLE,	/* No wake of system from sleep mode. */
+	GPIO_WAKE_LOW_LEVEL,	/* Wake the system up on a LOW level. */
+	GPIO_WAKE_HIGH_LEVEL,	/* Wake the system up on a HIGH level. */
+	GPIO_WAKE_RISING_EDGE,	/* Wake the system up on a RISING edge. */
+	GPIO_WAKE_FALLING_EDGE,	/* Wake the system up on a FALLING edge. */
+	GPIO_WAKE_BOTH_EDGES	/* Wake the system up on both RISE and FALL. */
+};
+
+/* Configuration parameters for one GPIO pin in sleep mode.*/
+struct gpio_sleep_config {
+	enum gpio_sleep_mode sleep_mode;/* GPIO behaviour in sleep mode. */
+	enum gpio_wake wake;		/* GPIO ability to wake up system. */
+};
+
+extern int gpio_setpinconfig(int pin_id, struct gpio_config *pin_config);
+extern int gpio_resetpinconfig(int pin_id, char *dev_name);
+extern int gpio_writepin(int pin_id, enum gpio_data value, char *dev_name);
+extern int gpio_readpin(int pin_id, enum gpio_data *value);
+extern int gpio_altfuncenable(enum gpio_alt_function altfunc,
+				      char *dev_name);
+extern int gpio_altfuncdisable(enum gpio_alt_function altfunc,
+				       char *dev_name);
+
+struct gpio_altfun_data {
+	u16 altfun;
+	u16 start;
+	u16 end;
+	u16 cont;
+	u8 type;
+};
+#endif

arch/arm/include/asm/arch-u8500/hardware.h

@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2009
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+/* Peripheral clusters */
+
+#define U8500_PER3_BASE		0x80000000
+#define U8500_PER2_BASE		0x80110000
+#define U8500_PER1_BASE		0x80120000
+#define U8500_PER4_BASE		0x80150000
+
+#define U8500_PER6_BASE		0xa03c0000
+#define U8500_PER7_BASE		0xa03d0000
+#define U8500_PER5_BASE		0xa03e0000
+
+/* GPIO */
+
+#define U8500_GPIO0_BASE	(U8500_PER1_BASE + 0xE000)
+#define U8500_GPIO1_BASE	(U8500_PER1_BASE + 0xE000 + 0x80)
+
+#define U8500_GPIO2_BASE	(U8500_PER3_BASE + 0xE000)
+#define U8500_GPIO3_BASE	(U8500_PER3_BASE + 0xE000 + 0x80)
+#define U8500_GPIO4_BASE	(U8500_PER3_BASE + 0xE000 + 0x100)
+#define U8500_GPIO5_BASE	(U8500_PER3_BASE + 0xE000 + 0x180)
+
+#define U8500_GPIO6_BASE	(U8500_PER2_BASE + 0xE000)
+#define U8500_GPIO7_BASE	(U8500_PER2_BASE + 0xE000 + 0x80)
+
+#define U8500_GPIO8_BASE	(U8500_PER5_BASE + 0x1E000)
+
+/* Per7 */
+#define U8500_CLKRST7_BASE	(U8500_PER7_BASE + 0xf000)
+
+/* Per6 */
+#define U8500_MTU0_BASE_V1	(U8500_PER6_BASE + 0x6000)
+#define U8500_MTU1_BASE_V1	(U8500_PER6_BASE + 0x7000)
+#define U8500_CLKRST6_BASE	(U8500_PER6_BASE + 0xf000)
+
+/* Per5 */
+#define U8500_CLKRST5_BASE	(U8500_PER5_BASE + 0x1f000)
+
+/* Per4 */
+#define U8500_PRCMU_BASE	(U8500_PER4_BASE + 0x07000)
+#define U8500_PRCMU_TCDM_BASE   (U8500_PER4_BASE + 0x0f000)
+
+/* Per3 */
+#define U8500_UART2_BASE	(U8500_PER3_BASE + 0x7000)
+#define U8500_CLKRST3_BASE	(U8500_PER3_BASE + 0xf000)
+
+/* Per2 */
+#define U8500_CLKRST2_BASE	(U8500_PER2_BASE + 0xf000)
+
+/* Per1 */
+#define U8500_UART0_BASE	(U8500_PER1_BASE + 0x0000)
+#define U8500_UART1_BASE	(U8500_PER1_BASE + 0x1000)
+#define U8500_CLKRST1_BASE	(U8500_PER1_BASE + 0xf000)
+
+/* Last page of Boot ROM */
+#define U8500_BOOTROM_BASE      0x9001f000
+#define U8500_BOOTROM_ASIC_ID_OFFSET    0x0ff4
+
+#endif /* __ASM_ARCH_HARDWARE_H */

arch/arm/include/asm/arch-u8500/sys_proto.h

@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+void gpio_init(void);
+
+#endif  /* _SYS_PROTO_H_ */

arch/arm/include/asm/arch-u8500/u8500.h

@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2009
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __U8500_H
+#define __U8500_H
+
+/*
+ * base register values for U8500
+ */
+#define CFG_PRCMU_BASE		0x80157000	/* Power, reset and clock
+						   Management Unit */
+#define CFG_SDRAMC_BASE		0x903CF000	/* SDRAMC cnf registers */
+#define CFG_FSMC_BASE		0x80000000	/* FSMC Controller */
+
+/*
+ * U8500 GPIO register base for 9 banks
+ */
+#define U8500_GPIO_0_BASE			0x8012E000
+#define U8500_GPIO_1_BASE			0x8012E080
+#define U8500_GPIO_2_BASE			0x8000E000
+#define U8500_GPIO_3_BASE			0x8000E080
+#define U8500_GPIO_4_BASE			0x8000E100
+#define U8500_GPIO_5_BASE			0x8000E180
+#define U8500_GPIO_6_BASE			0x8011E000
+#define U8500_GPIO_7_BASE			0x8011E080
+#define U8500_GPIO_8_BASE			0xA03FE000
+
+#endif	/* __U8500_H */

arch/arm/include/asm/global_data.h

@@ -41,9 +41,6 @@ typedef	struct	global_data {
 	unsigned long	env_addr;	/* Address  of Environment struct */
 	unsigned long	env_valid;	/* Checksum of Environment valid? */
 	unsigned long	fb_base;	/* base address of frame buffer */
-#ifdef CONFIG_VFD
-	unsigned char	vfd_type;	/* display type */
-#endif
 #ifdef CONFIG_FSL_ESDHC
 	unsigned long	sdhc_clk;
 #endif
@@ -63,6 +60,9 @@ typedef	struct	global_data {
 	unsigned long	tbu;
 	unsigned long long	timer_reset_value;
 	unsigned long	lastinc;
+#endif
+#ifdef CONFIG_IXP425
+	unsigned long	timestamp;
 #endif
 	unsigned long	relocaddr;	/* Start address of U-Boot in RAM */
 	phys_size_t	ram_size;	/* RAM size */

arch/arm/lib/board.c

@@ -262,9 +262,6 @@ init_fnc_t *init_sequence[] = {
 	init_func_i2c,
 #endif
 	dram_init,		/* configure available RAM banks */
-#if defined(CONFIG_CMD_PCI) || defined (CONFIG_PCI)
-	arm_pci_init,
-#endif
 	NULL,
 };
 
@@ -344,17 +341,6 @@ void board_init_f (ulong bootflag)
 	addr &= ~(4096 - 1);
 	debug ("Top of RAM usable for U-Boot at: %08lx\n", addr);
 
-#ifdef CONFIG_VFD
-#	ifndef PAGE_SIZE
-#	  define PAGE_SIZE 4096
-#	endif
-	/*
-	 * reserve memory for VFD display (always full pages)
-	 */
-	addr -= vfd_setmem (addr);
-	gd->fb_base = addr;
-#endif /* CONFIG_VFD */
-
 #ifdef CONFIG_LCD
 #ifdef CONFIG_FB_ADDR
 	gd->fb_base = CONFIG_FB_ADDR;
@@ -533,10 +519,9 @@ void board_init_r (gd_t *id, ulong dest_addr)
 	/* initialize environment */
 	env_relocate ();
 
-#ifdef CONFIG_VFD
-	/* must do this after the framebuffer is allocated */
-	drv_vfd_init();
-#endif /* CONFIG_VFD */
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+	arm_pci_init();
+#endif
 
 	/* IP Address */
 	gd->bd->bi_ip_addr = getenv_IPaddr ("ipaddr");

arch/blackfin/config.mk

@@ -76,10 +76,6 @@ LDR_FLAGS += $(LDR_FLAGS-y)
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
 
-ifeq ($(wildcard $(TOPDIR)/board/$(BOARD)/u-boot.lds*),)
-LDSCRIPT = $(obj)arch/$(ARCH)/lib/u-boot.lds.S
-endif
-
 ifneq ($(CONFIG_SYS_TEXT_BASE),)
 $(error do not set CONFIG_SYS_TEXT_BASE for Blackfin boards)
 endif

arch/blackfin/cpu/reset.c

@@ -9,6 +9,7 @@
 #include <common.h>
 #include <command.h>
 #include <asm/blackfin.h>
+#include <asm/mach-common/bits/bootrom.h>
 #include "cpu.h"
 
 /* A system soft reset makes external memory unusable so force
@@ -29,46 +30,40 @@ static void bfin_reset(void)
 	 */
 	__builtin_bfin_ssync();
 
-	/* The bootrom checks to see how it was reset and will
-	 * automatically perform a software reset for us when
-	 * it starts executing after the core reset.
+	/* Initiate System software reset. */
+	bfin_write_SWRST(0x7);
+
+	/* Due to the way reset is handled in the hardware, we need
+	 * to delay for 10 SCLKS.  The only reliable way to do this is
+	 * to calculate the CCLK/SCLK ratio and multiply 10.  For now,
+	 * we'll assume worse case which is a 1:15 ratio.
 	 */
-	if (ANOMALY_05000353 || ANOMALY_05000386) {
-		/* Initiate System software reset. */
-		bfin_write_SWRST(0x7);
+	asm(
+		"LSETUP (1f, 1f) LC0 = %0\n"
+		"1: nop;"
+		:
+		: "a" (15 * 10)
+		: "LC0", "LB0", "LT0"
+	);
 
-		/* Due to the way reset is handled in the hardware, we need
-		 * to delay for 10 SCLKS.  The only reliable way to do this is
-		 * to calculate the CCLK/SCLK ratio and multiply 10.  For now,
-		 * we'll assume worse case which is a 1:15 ratio.
-		 */
-		asm(
-			"LSETUP (1f, 1f) LC0 = %0\n"
-			"1: nop;"
-			:
-			: "a" (15 * 10)
-			: "LC0", "LB0", "LT0"
-		);
+	/* Clear System software reset */
+	bfin_write_SWRST(0);
 
-		/* Clear System software reset */
-		bfin_write_SWRST(0);
-
-		/* The BF526 ROM will crash during reset */
+	/* The BF526 ROM will crash during reset */
 #if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
-		bfin_read_SWRST();
+	bfin_read_SWRST();
 #endif
 
-		/* Wait for the SWRST write to complete.  Cannot rely on SSYNC
-		 * though as the System state is all reset now.
-		 */
-		asm(
-			"LSETUP (1f, 1f) LC1 = %0\n"
-			"1: nop;"
-			:
-			: "a" (15 * 1)
-			: "LC1", "LB1", "LT1"
-		);
-	}
+	/* Wait for the SWRST write to complete.  Cannot rely on SSYNC
+	 * though as the System state is all reset now.
+	 */
+	asm(
+		"LSETUP (1f, 1f) LC1 = %0\n"
+		"1: nop;"
+		:
+		: "a" (15 * 1)
+		: "LC1", "LB1", "LT1"
+	);
 
 	while (1)
 		/* Issue core reset */
@@ -84,7 +79,10 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	if (board_reset)
 		board_reset();
-	while (1)
-		asm("jump (%0);" : : "a" (bfin_reset));
+	if (ANOMALY_05000353 || ANOMALY_05000386)
+		while (1)
+			asm("jump (%0);" : : "a" (bfin_reset));
+	else
+		bfrom_SoftReset((void *)(L1_SRAM_SCRATCH_END - 20));
 	return 0;
 }

arch/powerpc/include/asm/config_mpc85xx.h

@@ -96,6 +96,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
 
 /* P1011 is single core version of P1020 */
 #elif defined(CONFIG_P1011)
@@ -175,6 +176,7 @@
 #define CONFIG_SYS_QMAN_NUM_PORTALS	3
 #define CONFIG_SYS_BMAN_NUM_PORTALS	3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x10000
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
 
 #elif defined(CONFIG_P1020)
 #define CONFIG_MAX_CPUS			2
@@ -216,6 +218,7 @@
 #define CONFIG_SYS_QMAN_NUM_PORTALS	3
 #define CONFIG_SYS_BMAN_NUM_PORTALS	3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x10000
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
 
 /* P1024 is lower end variant of P1020 */
 #elif defined(CONFIG_P1024)
@@ -265,6 +268,7 @@
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	32
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -280,6 +284,7 @@
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	32
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -291,6 +296,7 @@
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,p4080-pcie"
 
 #elif defined(CONFIG_PPC_P4080)
 #define CONFIG_MAX_CPUS			8
@@ -305,6 +311,7 @@
 #define CONFIG_NUM_DDR_CONTROLLERS	2
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,p4080-pcie"
 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
@@ -330,6 +337,7 @@
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	32
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -345,6 +353,7 @@
 #define CONFIG_NUM_DDR_CONTROLLERS	2
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	32
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111

arch/powerpc/include/asm/fsl_pci.h

@@ -233,7 +233,7 @@ int fsl_pcie_init_board(int busno);
 #if !defined(CONFIG_PCI)
 #define FT_FSL_PCI_SETUP
 #elif defined(CONFIG_FSL_CORENET)
-#define FSL_PCIE_COMPAT	"fsl,p4080-pcie"
+#define FSL_PCIE_COMPAT	CONFIG_SYS_FSL_PCIE_COMPAT
 #define FT_FSL_PCI_SETUP \
 	FT_FSL_PCIE1_SETUP; \
 	FT_FSL_PCIE2_SETUP; \
@@ -242,7 +242,11 @@ int fsl_pcie_init_board(int busno);
 #define FT_FSL_PCIE_SETUP FT_FSL_PCI_SETUP
 #elif defined(CONFIG_MPC85xx)
 #define FSL_PCI_COMPAT	"fsl,mpc8540-pci"
+#ifdef CONFIG_SYS_FSL_PCIE_COMPAT
+#define FSL_PCIE_COMPAT	CONFIG_SYS_FSL_PCIE_COMPAT
+#else
 #define FSL_PCIE_COMPAT	"fsl,mpc8548-pcie"
+#endif
 #define FT_FSL_PCI_SETUP \
 	FT_FSL_PCI1_SETUP; \
 	FT_FSL_PCI2_SETUP; \

board/BuS/eb_cpux9k2/cpux9k2.c

@@ -57,12 +57,12 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_init(void)
 {
-	at91_pio_t *pio	= (at91_pio_t *) AT91_PIO_BASE;
+	at91_pio_t *pio	= (at91_pio_t *) ATMEL_BASE_PIO;
 	/* Enable Ctrlc */
 	console_init_f();
 
 	/* Correct IRDA resistor problem / Set PA23_TXD in Output */
-	writel(AT91_PMX_AA_TXD2, &pio->pioa.oer);
+	writel(ATMEL_PMX_AA_TXD2, &pio->pioa.oer);
 
 	gd->bd->bi_arch_number = MACH_TYPE_EB_CPUX9K2;
 	/* adress of boot parameters */
@@ -147,7 +147,7 @@ int dram_init(void)
 int board_eth_init(bd_t *bis)
 {
 	int rc = 0;
-	rc = at91emac_register(bis, (u32) AT91_EMAC_BASE);
+	rc = at91emac_register(bis, (u32) ATMEL_BASE_EMAC);
 	return rc;
 }
 #endif
@@ -164,9 +164,9 @@ int board_eth_init(bd_t *bis)
 void cpux9k2_nand_hw_init(void)
 {
 	unsigned long csr;
-	at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
-	at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
-	at91_mc_t *mc = (at91_mc_t *) AT91_MC_BASE;
+	at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
+	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+	at91_mc_t *mc = (at91_mc_t *) ATMEL_BASE_MC;
 
 	/* Setup Smart Media, fitst enable the address range of CS3 */
 	writel(readl(&mc->ebi.csa) | AT91_EBI_CSA_CS3A, &mc->ebi.csa);
@@ -178,23 +178,23 @@ void cpux9k2_nand_hw_init(void)
 		AT91_SMC_CSR_WSEN;
 	writel(csr, &mc->smc.csr[3]);
 
-	writel(AT91_PMX_CA_SMOE | AT91_PMX_CA_SMWE, &pio->pioc.asr);
-	writel(AT91_PMX_CA_BFCK | AT91_PMX_CA_SMOE | AT91_PMX_CA_SMWE,
+	writel(ATMEL_PMX_CA_SMOE | ATMEL_PMX_CA_SMWE, &pio->pioc.asr);
+	writel(ATMEL_PMX_CA_BFCK | ATMEL_PMX_CA_SMOE | ATMEL_PMX_CA_SMWE,
 		&pio->pioc.pdr);
 
 	/* Configure PC2 as input (signal Nand READY ) */
-	writel(AT91_PMX_CA_BFAVD, &pio->pioc.per);
-	writel(AT91_PMX_CA_BFAVD, &pio->pioc.odr); /* disable output */
-	writel(AT91_PMX_CA_BFCK, &pio->pioc.codr);
+	writel(ATMEL_PMX_CA_BFAVD, &pio->pioc.per);
+	writel(ATMEL_PMX_CA_BFAVD, &pio->pioc.odr); /* disable output */
+	writel(ATMEL_PMX_CA_BFCK, &pio->pioc.codr);
 
 	/* PIOC clock enabling */
-	writel(1 << AT91_ID_PIOC, &pmc->pcer);
+	writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
 }
 
 static void board_nand_hwcontrol(struct mtd_info *mtd,
 	int cmd, unsigned int ctrl)
 {
-	at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+	at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
 	struct nand_chip *this = mtd->priv;
 	ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
 
@@ -219,7 +219,7 @@ static void board_nand_hwcontrol(struct mtd_info *mtd,
 
 static int board_nand_dev_ready(struct mtd_info *mtd)
 {
-	at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+	at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
 	return ((readl(&pio->pioc.pdsr) & (1 << 2)) != 0);
 }
 
@@ -248,8 +248,8 @@ int drv_video_init(void)
 #endif
 	char *s;
 	unsigned long csr;
-	at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
-	at91_mc_t *mc = (at91_mc_t *) AT91_MC_BASE;
+	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+	at91_mc_t *mc = (at91_mc_t *) ATMEL_BASE_MC;
 
 	printf("Init Video as ");
 	s = getenv("displaywidth");
@@ -270,7 +270,7 @@ int drv_video_init(void)
 		AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_16 |
 		AT91_SMC_CSR_BAT_16 | AT91_SMC_CSR_WSEN;
 	writel(csr, &mc->smc.csr[2]);
-	writel(1 << AT91_ID_PIOB, &pmc->pcer);
+	writel(1 << ATMEL_ID_PIOB, &pmc->pcer);
 
 	vcxk_init(display_width, display_height);
 #ifdef CONFIG_SPLASH_SCREEN
@@ -290,11 +290,11 @@ int drv_video_init(void)
 void i2c_init_board(void)
 {
 	u32 pin;
-	at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
-	at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+	at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
 
-	writel(1 << AT91_ID_PIOA, &pmc->pcer);
-	pin = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK;
+	writel(1 << ATMEL_ID_PIOA, &pmc->pcer);
+	pin = ATMEL_PMX_AA_TWD | ATMEL_PMX_AA_TWCK;
 	writel(pin, &pio->pioa.idr);
 	writel(pin, &pio->pioa.pudr);
 	writel(pin, &pio->pioa.per);
@@ -310,7 +310,7 @@ void i2c_init_board(void)
 
 void __led_toggle(led_id_t mask)
 {
-	at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+	at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
 
 	if (readl(&pio->piod.odsr) & mask)
 		writel(mask, &pio->piod.codr);
@@ -320,10 +320,10 @@ void __led_toggle(led_id_t mask)
 
 void __led_init(led_id_t mask, int state)
 {
-	at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
-	at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+	at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
 
-	writel(1 << AT91_ID_PIOD, &pmc->pcer);	/* Enable PIOB clock */
+	writel(1 << ATMEL_ID_PIOD, &pmc->pcer);	/* Enable PIOB clock */
 	/* Disable peripherals on LEDs */
 	writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.per);
 	/* Enable pins as outputs */
@@ -336,7 +336,7 @@ void __led_init(led_id_t mask, int state)
 
 void __led_set(led_id_t mask, int state)
 {
-	at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+	at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
 	if (state == STATUS_LED_ON)
 		writel(mask, &pio->piod.codr);
 	else

board/actux1/actux1.c

@@ -37,49 +37,57 @@
 #include <asm/arch/ixp425.h>
 #include <asm/io.h>
 #include <miiphy.h>
+#ifdef CONFIG_PCI
+#include <pci.h>
+#include <asm/arch/ixp425pci.h>
+#endif
 
 #include "actux1_hw.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int board_init (void)
+int board_early_init_f(void)
+{
+	/* CS5: Debug port */
+	writel(0x9d520003, IXP425_EXP_CS5);
+	/* CS6: HwRel */
+	writel(0x81860001, IXP425_EXP_CS6);
+	/* CS7: LEDs */
+	writel(0x80900003, IXP425_EXP_CS7);
+	return 0;
+}
+
+int board_init(void)
 {
 	gd->bd->bi_arch_number = MACH_TYPE_ACTUX1;
 
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x00000100;
 
-	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
 
-	/* Setup GPIO's for PCI INTA */
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI1_INTA);
-	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI1_INTA);
+	/* Setup GPIOs for PCI INTA */
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI1_INTA);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI1_INTA);
 
-	/* Setup GPIO's for 33MHz clock output */
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
-	*IXP425_GPIO_GPCLKR = 0x011001FF;
+	/* Setup GPIOs for 33MHz clock output */
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
+	writel(0x011001FF, IXP425_GPIO_GPCLKR);
 
-	/* CS5: Debug port */
-	*IXP425_EXP_CS5 = 0x9d520003;
-	/* CS6: HwRel */
-	*IXP425_EXP_CS6 = 0x81860001;
-	/* CS7: LEDs */
-	*IXP425_EXP_CS7 = 0x80900003;
+	udelay(533);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
 
-	udelay (533);
-	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
+	ACTUX1_LED1(2);
+	ACTUX1_LED2(2);
+	ACTUX1_LED3(0);
+	ACTUX1_LED4(0);
+	ACTUX1_LED5(0);
+	ACTUX1_LED6(0);
+	ACTUX1_LED7(0);
 
-	ACTUX1_LED1 (2);
-	ACTUX1_LED2 (2);
-	ACTUX1_LED3 (0);
-	ACTUX1_LED4 (0);
-	ACTUX1_LED5 (0);
-	ACTUX1_LED6 (0);
-	ACTUX1_LED7 (0);
-
-	ACTUX1_HS (ACTUX1_HS_DCD);
+	ACTUX1_HS(ACTUX1_HS_DCD);
 
 	return 0;
 }
@@ -87,21 +95,21 @@ int board_init (void)
 /*
  * Check Board Identity
  */
-int checkboard (void)
+int checkboard(void)
 {
 	char buf[64];
 	int i = getenv_f("serial#", buf, sizeof(buf));
 
-	puts ("Board: AcTux-1 rev.");
-	putc (ACTUX1_BOARDREL + 'A' - 1);
+	puts("Board: AcTux-1 rev.");
+	putc(ACTUX1_BOARDREL + 'A' - 1);
 
 	if (i > 0) {
 		puts(", serial# ");
 		puts(buf);
 	}
-	putc ('\n');
+	putc('\n');
 
-	return (0);
+	return 0;
 }
 
 /*************************************************************************
@@ -110,39 +118,36 @@ int checkboard (void)
  * 1 = Rev. A
  * 2 = Rev. B
  *************************************************************************/
-u32 get_board_rev (void)
+u32 get_board_rev(void)
 {
 	return ACTUX1_BOARDREL;
 }
 
-int dram_init (void)
+int dram_init(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return (0);
+	gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
+	return 0;
 }
 
-#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
-extern struct pci_controller hose;
-extern void pci_ixp_init (struct pci_controller *hose);
 
-void pci_init_board (void)
+#ifdef CONFIG_PCI
+struct pci_controller hose;
+
+void pci_init_board(void)
 {
-	extern void pci_ixp_init (struct pci_controller *hose);
-	pci_ixp_init (&hose);
+	pci_ixp_init(&hose);
 }
 #endif
 
-void reset_phy (void)
+void reset_phy(void)
 {
 	u16 id1, id2;
 
 	/* initialize the PHY */
-	miiphy_reset ("NPE0", CONFIG_PHY_ADDR);
+	miiphy_reset("NPE0", CONFIG_PHY_ADDR);
 
-	miiphy_read ("NPE0", CONFIG_PHY_ADDR, MII_PHYSID1, &id1);
-	miiphy_read ("NPE0", CONFIG_PHY_ADDR, MII_PHYSID2, &id2);
+	miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID1, &id1);
+	miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID2, &id2);
 
 	id2 &= 0xFFF0;		/* mask out revision bits */
 
@@ -153,9 +158,9 @@ void reset_phy (void)
 		 * LED2 (unused) = LINK,
 		 * LED3(red) = Coll
 		 */
-		miiphy_write ("NPE0", CONFIG_PHY_ADDR, 20, 0xD432);
+		miiphy_write("NPE0", CONFIG_PHY_ADDR, 20, 0xD432);
 	} else if (id1 == 0x143 && id2 == 0xbc30) {
 		/* BCM5241: default values are OK */
 	} else
-		printf ("unknown ethernet PHY ID: %x %x\n", id1, id2);
+		printf("unknown ethernet PHY ID: %x %x\n", id1, id2);
 }

board/actux1/config.mk

@@ -1,4 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0x00e00000
-
-# include NPE ethernet driver
-BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.o

board/actux1/u-boot.lds

@@ -30,15 +30,15 @@ SECTIONS
 
 	. = ALIGN (4);
 	.text : {
-		arch/arm/cpu/ixp/start.o(.text)
-		lib/string.o(.text)
-		lib/vsprintf.o(.text)
-		arch/arm/lib/board.o(.text)
-		common/dlmalloc.o(.text)
-		arch/arm/cpu/ixp/cpu.o(.text)
+		arch/arm/cpu/ixp/start.o(.text*)
+		net/libnet.o(.text*)
+		board/actux1/libactux1.o(.text*)
+		arch/arm/cpu/ixp/libixp.o(.text*)
+		drivers/serial/libserial.o(.text*)
+
 		. = env_offset;
 		common/env_embedded.o(.ppcenv)
-		* (.text)
+		*(.text*)
 	}
 
 	. = ALIGN (4);
@@ -47,7 +47,7 @@ SECTIONS
 	}
 	. = ALIGN (4);
 	.data : {
-		*(.data)
+		*(.data*)
 	}
 	. = ALIGN (4);
 	.got : {
@@ -61,10 +61,27 @@ SECTIONS
 	__u_boot_cmd_end =.;
 
 	. = ALIGN (4);
-	__bss_start =.;
-	.bss (NOLOAD): {
-		*(.bss)
-		. = ALIGN(4);
+	.rel.dyn : {
+		__rel_dyn_start = .;
+		*(.rel*)
+		__rel_dyn_end = .;
+	}
+
+	.dynsym : {
+		__dynsym_start = .;
+		*(.dynsym)
+	}
+
+	.bss __rel_dyn_start (OVERLAY) : {
+		__bss_start = .;
+		*(.bss*)
+		 . = ALIGN(4);
+		_end = .;
 	}
 	__bss_end__ =.;
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
 }

board/actux2/actux2.c

@@ -43,50 +43,55 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int board_init (void)
+int board_early_init_f(void)
+{
+	/* CS1: IPAC-X */
+	writel(0x94d10013, IXP425_EXP_CS1);
+	/* CS5: Debug port */
+	writel(0x9d520003, IXP425_EXP_CS5);
+	/* CS6: HW release register */
+	writel(0x81860001, IXP425_EXP_CS6);
+	/* CS7: LEDs */
+	writel(0x80900003, IXP425_EXP_CS7);
+
+	return 0;
+}
+
+int board_init(void)
 {
 	gd->bd->bi_arch_number = MACH_TYPE_ACTUX2;
 
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x00000100;
 
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_ETHRST);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DSR);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DCD);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_ETHRST);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DSR);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DCD);
 
-	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_ETHRST);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_ETHRST);
 
-	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_DSR);
-	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_DCD);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DSR);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DCD);
 
-	/* Setup GPIO's for Interrupt inputs */
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_DBGINT);
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_ETHINT);
+	/* Setup GPIOs for Interrupt inputs */
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DBGINT);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_ETHINT);
 
-	/* Setup GPIO's for 33MHz clock output */
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
-	*IXP425_GPIO_GPCLKR = 0x011001FF;
+	/* Setup GPIOs for 33MHz clock output */
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
+	writel(0x011001FF, IXP425_GPIO_GPCLKR);
 
-	/* CS1: IPAC-X */
-	*IXP425_EXP_CS1 = 0x94d10013;
-	/* CS5: Debug port */
-	*IXP425_EXP_CS5 = 0x9d520003;
-	/* CS6: HW release register */
-	*IXP425_EXP_CS6 = 0x81860001;
-	/* CS7: LEDs */
-	*IXP425_EXP_CS7 = 0x80900003;
+	udelay(533);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_ETHRST);
 
-	udelay (533);
-	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_ETHRST);
-
-	ACTUX2_LED1 (1);
-	ACTUX2_LED2 (0);
-	ACTUX2_LED3 (0);
-	ACTUX2_LED4 (0);
+	ACTUX2_LED1(1);
+	ACTUX2_LED2(0);
+	ACTUX2_LED3(0);
+	ACTUX2_LED4(0);
 
 	return 0;
 }
@@ -94,29 +99,27 @@ int board_init (void)
 /*
  * Check Board Identity
  */
-int checkboard (void)
+int checkboard(void)
 {
 	char buf[64];
 	int i = getenv_f("serial#", buf, sizeof(buf));
 
-	puts ("Board: AcTux-2 rev.");
-	putc (ACTUX2_BOARDREL + 'A' - 1);
+	puts("Board: AcTux-2 rev.");
+	putc(ACTUX2_BOARDREL + 'A' - 1);
 
 	if (i > 0) {
 		puts(", serial# ");
 		puts(buf);
 	}
-	putc ('\n');
+	putc('\n');
 
-	return (0);
+	return 0;
 }
 
-int dram_init (void)
+int dram_init(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return (0);
+	gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
+	return 0;
 }
 
 /*************************************************************************
@@ -125,13 +128,13 @@ int dram_init (void)
  * 1 = Rev. A
  * 2 = Rev. B
  *************************************************************************/
-u32 get_board_rev (void)
+u32 get_board_rev(void)
 {
 	return ACTUX2_BOARDREL;
 }
 
-void reset_phy (void)
+void reset_phy(void)
 {
 	/* init IcPlus IP175C ethernet switch to native IP175C mode */
-	miiphy_write ("NPE0", 29, 31, 0x175C);
+	miiphy_write("NPE0", 29, 31, 0x175C);
 }

board/actux2/config.mk

@@ -1,4 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0x00e00000
-
-# include NPE ethernet driver
-BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.o

board/actux2/u-boot.lds

@@ -30,34 +30,29 @@ SECTIONS
 
 	. = ALIGN (4);
 	.text : {
-		arch/arm/cpu/ixp/start.o(.text)
-		lib/string.o(.text)
-		lib/vsprintf.o(.text)
-		arch/arm/lib/board.o(.text)
-		common/dlmalloc.o(.text)
-		arch/arm/cpu/ixp/cpu.o(.text)
+		arch/arm/cpu/ixp/start.o(.text*)
+		net/libnet.o(.text*)
+		board/actux2/libactux2.o(.text*)
+		arch/arm/cpu/ixp/libixp.o(.text*)
+		drivers/serial/libserial.o(.text*)
 
 		. = env_offset;
-		common/env_embedded.o (.ppcenv)
-
-		* (.text)
+		common/env_embedded.o(.ppcenv)
+		*(.text*)
 	}
 
 	. = ALIGN (4);
 	.rodata : {
 		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
 	}
-
 	. = ALIGN (4);
 	.data : {
-		*(.data)
+		*(.data*)
 	}
-
 	. = ALIGN (4);
 	.got : {
 		*(.got)
 	}
-
 	. =.;
 	__u_boot_cmd_start =.;
 	.u_boot_cmd : {
@@ -66,10 +61,27 @@ SECTIONS
 	__u_boot_cmd_end =.;
 
 	. = ALIGN (4);
-	__bss_start =.;
-	.bss (NOLOAD): {
-		*(.bss)
-		. = ALIGN(4);
+	.rel.dyn : {
+		__rel_dyn_start = .;
+		*(.rel*)
+		__rel_dyn_end = .;
+	}
+
+	.dynsym : {
+		__dynsym_start = .;
+		*(.dynsym)
+	}
+
+	.bss __rel_dyn_start (OVERLAY) : {
+		__bss_start = .;
+		*(.bss*)
+		 . = ALIGN(4);
+		_end = .;
 	}
 	__bss_end__ =.;
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
 }

board/actux3/actux3.c

@@ -36,72 +36,76 @@
 #include <malloc.h>
 #include <asm/arch/ixp425.h>
 #include <asm/io.h>
-
 #include <miiphy.h>
-
 #include "actux3_hw.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int board_init (void)
+int board_early_init_f(void)
+{
+	/* CS1: IPAC-X */
+	writel(0x94d10013, IXP425_EXP_CS1);
+	/* CS5: Debug port */
+	writel(0x9d520003, IXP425_EXP_CS5);
+	/* CS6: Release/Option register */
+	writel(0x81860001, IXP425_EXP_CS6);
+	/* CS7: LEDs */
+	writel(0x80900003, IXP425_EXP_CS7);
+
+	return 0;
+}
+
+int board_init(void)
 {
 	gd->bd->bi_arch_number = MACH_TYPE_ACTUX3;
 
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x00000100;
 
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_ETHRST);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DSR);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DCD);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED5_GN);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED6_RT);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED6_GN);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_ETHRST);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DSR);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DCD);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED5_GN);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_RT);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_GN);
 
-	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_ETHRST);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_ETHRST);
 
-	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_DSR);
-	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_DCD);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DSR);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DCD);
 
-	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED5_GN);
-	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED6_RT);
-	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED6_GN);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED5_GN);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_RT);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_GN);
 
 	/*
 	 * Setup GPIO's for Interrupt inputs
 	 */
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_DBGINT);
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_ETHINT);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DBGINT);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_ETHINT);
 
 	/*
 	 * Setup GPIO's for 33MHz clock output
 	 */
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
-	*IXP425_GPIO_GPCLKR = 0x011001FF;
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
+	writel(0x011001FF, IXP425_GPIO_GPCLKR);
 
-	/* CS1: IPAC-X */
-	*IXP425_EXP_CS1 = 0x94d10013;
-	/* CS5: Debug port */
-	*IXP425_EXP_CS5 = 0x9d520003;
-	/* CS6: Release/Option register */
-	*IXP425_EXP_CS6 = 0x81860001;
-	/* CS7: LEDs */
-	*IXP425_EXP_CS7 = 0x80900003;
+	/* we need a minimum PCI reset pulse width after enabling the clock */
+	udelay(533);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_ETHRST);
 
-	udelay (533);
-	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_ETHRST);
-
-	ACTUX3_LED1_RT (1);
-	ACTUX3_LED1_GN (0);
-	ACTUX3_LED2_RT (0);
-	ACTUX3_LED2_GN (0);
-	ACTUX3_LED3_RT (0);
-	ACTUX3_LED3_GN (0);
-	ACTUX3_LED4_GN (0);
-	ACTUX3_LED5_RT (0);
+	ACTUX3_LED1_RT(1);
+	ACTUX3_LED1_GN(0);
+	ACTUX3_LED2_RT(0);
+	ACTUX3_LED2_GN(0);
+	ACTUX3_LED3_RT(0);
+	ACTUX3_LED3_GN(0);
+	ACTUX3_LED4_GN(0);
+	ACTUX3_LED5_RT(0);
 
 	return 0;
 }
@@ -109,21 +113,21 @@ int board_init (void)
 /*
  * Check Board Identity
  */
-int checkboard (void)
+int checkboard(void)
 {
 	char buf[64];
 	int i = getenv_f("serial#", buf, sizeof(buf));
 
-	puts ("Board: AcTux-3 rev.");
-	putc (ACTUX3_BOARDREL + 'A' - 1);
+	puts("Board: AcTux-3 rev.");
+	putc(ACTUX3_BOARDREL + 'A' - 1);
 
 	if (i > 0) {
 		puts (", serial# ");
 		puts (buf);
 	}
-	putc ('\n');
+	putc('\n');
 
-	return (0);
+	return 0;
 }
 
 /*************************************************************************
@@ -132,34 +136,32 @@ int checkboard (void)
  * 1 = Rev. A
  * 2 = Rev. B
  *************************************************************************/
-u32 get_board_rev (void)
+u32 get_board_rev(void)
 {
 	return ACTUX3_BOARDREL;
 }
 
-int dram_init (void)
+int dram_init(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return (0);
+	gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
+	return 0;
 }
 
-void reset_phy (void)
+void reset_phy(void)
 {
 	int i;
 
 	/* initialize the PHY */
-	miiphy_reset ("NPE0", CONFIG_PHY_ADDR);
+	miiphy_reset("NPE0", CONFIG_PHY_ADDR);
 
 	/* all LED outputs = Link/Act */
-	miiphy_write ("NPE0", CONFIG_PHY_ADDR, 0x16, 0x0AAA);
+	miiphy_write("NPE0", CONFIG_PHY_ADDR, 0x16, 0x0AAA);
 
 	/*
 	 * The Marvell 88E6060 switch comes up with all ports disabled.
 	 * set all ethernet switch ports to forwarding state
 	*/
 	for (i = 1; i <= 5; i++)
-		miiphy_write ("NPE0", CONFIG_PHY_ADDR + 8 + i, 0x04, 0x03);
+		miiphy_write("NPE0", CONFIG_PHY_ADDR + 8 + i, 0x04, 0x03);
 
 }

board/actux3/config.mk

@@ -1,4 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0x00e00000
-
-# include NPE ethernet driver
-BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.o

board/actux3/u-boot.lds

@@ -30,34 +30,29 @@ SECTIONS
 
 	. = ALIGN (4);
 	.text : {
-		arch/arm/cpu/ixp/start.o (.text)
-		lib/string.o (.text)
-		lib/vsprintf.o (.text)
-		arch/arm/lib/board.o (.text)
-		common/dlmalloc.o (.text)
-		arch/arm/cpu/ixp/cpu.o (.text)
+		arch/arm/cpu/ixp/start.o(.text*)
+		net/libnet.o(.text*)
+		board/actux3/libactux3.o(.text*)
+		arch/arm/cpu/ixp/libixp.o(.text*)
+		drivers/serial/libserial.o(.text*)
 
 		. = env_offset;
-		common/env_embedded.o (.ppcenv)
-
-		* (.text)
+		common/env_embedded.o(.ppcenv)
+		*(.text*)
 	}
 
-	. = ALIGN (4);
+	. = ALIGN(4);
 	.rodata : {
 		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
 	}
-
-	. = ALIGN (4);
+	. = ALIGN(4);
 	.data : {
-		*(.data)
+		*(.data*)
 	}
-
-	. = ALIGN (4);
+	. = ALIGN(4);
 	.got : {
 		*(.got)
 	}
-
 	. =.;
 	__u_boot_cmd_start =.;
 	.u_boot_cmd : {
@@ -66,10 +61,27 @@ SECTIONS
 	__u_boot_cmd_end =.;
 
 	. = ALIGN (4);
-	__bss_start =.;
-	.bss (NOLOAD): {
-		*(.bss)
-		. = ALIGN(4);
+	.rel.dyn : {
+		__rel_dyn_start = .;
+		*(.rel*)
+		__rel_dyn_end = .;
+	}
+
+	.dynsym : {
+		__dynsym_start = .;
+		*(.dynsym)
+	}
+
+	.bss __rel_dyn_start (OVERLAY) : {
+		__bss_start = .;
+		*(.bss*)
+		 . = ALIGN(4);
+		_end = .;
 	}
 	__bss_end__ =.;
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
 }

board/actux4/actux4.c

@@ -35,92 +35,107 @@
 #include <command.h>
 #include <malloc.h>
 #include <asm/arch/ixp425.h>
-
+#include <asm/io.h>
 #include <miiphy.h>
+#ifdef CONFIG_PCI
+#include <pci.h>
+#include <asm/arch/ixp425pci.h>
+#endif
 
 #include "actux4_hw.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int board_init (void)
+int board_early_init_f(void)
+{
+	writel(0xbd113c42, IXP425_EXP_CS1);
+	return 0;
+}
+
+int board_init(void)
 {
 	gd->bd->bi_arch_number = MACH_TYPE_ACTUX4;
 
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x00000100;
 
-	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_nPWRON);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_nPWRON);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_nPWRON);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_nPWRON);
 
-	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
 
 	/* led not populated on board*/
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED3);
-	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED3);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED3);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED3);
 
 	/* middle LED */
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED2);
-	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED2);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED2);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED2);
 
 	/* right LED */
 	/* weak pulldown = LED weak on */
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_LED1);
-	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED1);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_LED1);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED1);
 
 	/* Setup GPIO's for Interrupt inputs */
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTA);
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTB);
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTC);
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_RTCINT);
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI_INTA);
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI_INTB);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTA);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTB);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTC);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RTCINT);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB);
 
-	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTA);
-	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTB);
-	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTC);
-	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_RTCINT);
-	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI_INTA);
-	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI_INTB);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTA);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTB);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTC);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RTCINT);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB);
 
 	/* Setup GPIO's for 33MHz clock output */
-	*IXP425_GPIO_GPCLKR = 0x011001FF;
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
+	writel(0x011001FF, IXP425_GPIO_GPCLKR);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
 
-	*IXP425_EXP_CS1 = 0xbd113c42;
-
-	udelay (10000);
-	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
-	udelay (10000);
-	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
-	udelay (10000);
-	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
+	udelay(10000);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
+	udelay(10000);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
+	udelay(10000);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
 
 	return 0;
 }
 
 /* Check Board Identity */
-int checkboard (void)
+int checkboard(void)
 {
-	puts ("Board: AcTux-4\n");
-	return (0);
+	puts("Board: AcTux-4\n");
+	return 0;
 }
 
-int dram_init (void)
+int dram_init(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return (0);
+	gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
+	return 0;
 }
 
+#ifdef CONFIG_PCI
+struct pci_controller hose;
+
+void pci_init_board(void)
+{
+	pci_ixp_init(&hose);
+}
+#endif
+
 /*
  * Hardcoded flash setup:
  * Flash 0 is a non-CFI SST 39VF020 flash, 8 bit flash / 8 bit bus.
  * Flash 1 is an Intel *16 flash using the CFI driver.
  */
-ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
 {
 	if (banknum == 0) {	/* non-CFI boot flash */
 		info->portwidth = 1;

board/actux4/config.mk

@@ -1,4 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0x00e00000
-
-# include NPE ethernet driver
-BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.o

board/afeb9260/afeb9260.c

@@ -31,7 +31,7 @@
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
+#include <asm/io.h>
 #include <asm/arch/hardware.h>
 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
 #include <netdev.h>
@@ -48,28 +48,28 @@ DECLARE_GLOBAL_DATA_PTR;
 static void afeb9260_nand_hw_init(void)
 {
 	unsigned long csa;
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
 
-	/* Enable CS3 */
-	csa = at91_sys_read(AT91_MATRIX_EBICSA);
-	at91_sys_write(AT91_MATRIX_EBICSA,
-		       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+	/* Assign CS3 to NAND/SmartMedia Interface */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+	writel(csa, &matrix->ebicsa);
 
 	/* Configure SMC CS3 for NAND/SmartMedia */
-	at91_sys_write(AT91_SMC_SETUP(3),
-		       AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
-		       AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
-	at91_sys_write(AT91_SMC_PULSE(3),
-		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
-		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
-	at91_sys_write(AT91_SMC_CYCLE(3),
-		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
-	at91_sys_write(AT91_SMC_MODE(3),
-		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-		       AT91_SMC_EXNWMODE_DISABLE |
-		       AT91_SMC_DBW_8 |
-		       AT91_SMC_TDF_(2));
-
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+		&smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
+		AT91_SMC_MODE_DBW_8 |
+		AT91_SMC_MODE_TDF_CYCLE(2),
+		&smc->cs[3].mode);
 
 	/* Configure RDY/BSY */
 	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
@@ -81,10 +81,15 @@ static void afeb9260_nand_hw_init(void)
 #ifdef CONFIG_MACB
 static void afeb9260_macb_hw_init(void)
 {
-	unsigned long rstc;
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
+	struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
+	unsigned long erstl;
+
+
+	/* Enable EMAC clock */
+	writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
 
-	/* Enable clock */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
 
 	/*
 	 * Disable pull-up on:
@@ -103,24 +108,22 @@ static void afeb9260_macb_hw_init(void)
 	       pin_to_mask(AT91_PIN_PA25) |
 	       pin_to_mask(AT91_PIN_PA26) |
 	       pin_to_mask(AT91_PIN_PA28),
-	       pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
+	       &pioa->pudr);
 
-	rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
+	erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
 
 	/* Need to reset PHY -> 500ms reset */
-	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
-				     AT91_RSTC_ERSTL | (0x0D << 8) |
-				     AT91_RSTC_URSTEN);
-
-	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
+	writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
+		AT91_RSTC_MR_URSTEN, &rstc->mr);
+	writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
 
 	/* Wait for end hardware reset */
-	while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
-
+	while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
+		;
 	/* Restore NRST value */
-	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
-				     (rstc) |
-				     AT91_RSTC_URSTEN);
+	writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
+		&rstc->mr);
+
 
 	/* Re-enable pull-up */
 	writel(pin_to_mask(AT91_PIN_PA14) |
@@ -129,23 +132,29 @@ static void afeb9260_macb_hw_init(void)
 	       pin_to_mask(AT91_PIN_PA25) |
 	       pin_to_mask(AT91_PIN_PA26) |
 	       pin_to_mask(AT91_PIN_PA28),
-	       pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
+	       &pioa->puer);
 
 	at91_macb_hw_init();
 }
 #endif
-
+int board_early_init_f(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	/* Enable clocks for all PIOs */
+	writel((1 << ATMEL_ID_PIOA) |
+		(1 << ATMEL_ID_PIOB) |
+		(1 << ATMEL_ID_PIOC),
+		&pmc->pcer);
+	return 0;
+}
 int board_init(void)
 {
-	/* Enable Ctrlc */
-	console_init_f();
-
 	/* arch number of AT91SAM9260EK-Board */
 	gd->bd->bi_arch_number = MACH_TYPE_AFEB9260;
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
-	at91_serial_hw_init();
+	at91_seriald_hw_init();
 #ifdef CONFIG_CMD_NAND
 	afeb9260_nand_hw_init();
 #endif
@@ -159,8 +168,10 @@ int board_init(void)
 
 int dram_init(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	gd->ram_size = get_ram_size(
+	(void *)CONFIG_SYS_SDRAM_BASE,
+		CONFIG_SYS_SDRAM_SIZE);
+
 	return 0;
 }
 
@@ -174,7 +185,7 @@ int board_eth_init(bd_t *bis)
 {
 	int rc = 0;
 #ifdef CONFIG_MACB
-	rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x01);
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x01);
 #endif
 	return rc;
 }

board/armltd/vexpress/ca9x4_ct_vxp.c

@@ -38,6 +38,7 @@
 #include <asm/arch/systimer.h>
 #include <asm/arch/sysctrl.h>
 #include <asm/arch/wdt.h>
+#include "../drivers/mmc/arm_pl180_mmci.h"
 
 static ulong timestamp;
 static ulong lastdec;

board/atmel/at91rm9200ek/at91rm9200ek.c

@@ -44,7 +44,7 @@ int board_init(void)
 	 * Correct IRDA resistor problem
 	 * Set PA23_TXD in Output
 	 */
-	writel(AT91_PMX_AA_TXD2, &pio->pioa.oer);
+	writel(ATMEL_PMX_AA_TXD2, &pio->pioa.oer);
 
 	/* arch number of AT91RM9200EK-Board */
 	gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200EK;
@@ -65,6 +65,6 @@ int dram_init (void)
 #ifdef CONFIG_DRIVER_AT91EMAC
 int board_eth_init(bd_t *bis)
 {
-	return at91emac_register(bis, (u32) AT91_EMAC_BASE);
+	return at91emac_register(bis, (u32) ATMEL_BASE_EMAC);
 }
 #endif

board/atmel/at91rm9200ek/led.c

@@ -26,8 +26,10 @@
  */
 
 #include <common.h>
-#include <asm/arch/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
 #include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pio.h>
 
 /* bit mask in PIO port B */
 #define	GREEN_LED	(1<<0)
@@ -36,47 +38,47 @@
 
 void	green_LED_on(void)
 {
-	at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
 	writel(GREEN_LED, &pio->piob.codr);
 }
 
 void	 yellow_LED_on(void)
 {
-	at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
 	writel(YELLOW_LED, &pio->piob.codr);
 }
 
 void	 red_LED_on(void)
 {
-	at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
 	writel(RED_LED, &pio->piob.codr);
 }
 
 void	green_LED_off(void)
 {
-	at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
 	writel(GREEN_LED, &pio->piob.sodr);
 }
 
 void	yellow_LED_off(void)
 {
-	at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
 	writel(YELLOW_LED, &pio->piob.sodr);
 }
 
 void	red_LED_off(void)
 {
-	at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
 	writel(RED_LED, &pio->piob.sodr);
 }
 
 void coloured_LED_init (void)
 {
-	at91_pmc_t *pmc = (at91_pmc_t *)AT91_PMC_BASE;
-	at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+	at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
+	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
 
 	/* Enable PIOB clock */
-	writel(1 << AT91_ID_PIOB, &pmc->pcer);
+	writel(1 << ATMEL_ID_PIOB, &pmc->pcer);
 
 	/* Disable peripherals on LEDs */
 	writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.per);

board/atmel/at91sam9260ek/at91sam9260ek.c

@@ -23,17 +23,16 @@
  */
 
 #include <common.h>
-#include <asm/arch/at91sam9260.h>
+#include <asm/io.h>
 #include <asm/arch/at91sam9260_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
-#include <asm/arch/hardware.h>
+
 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
-#include <net.h>
+# include <net.h>
 #endif
 #include <netdev.h>
 
@@ -47,49 +46,53 @@ DECLARE_GLOBAL_DATA_PTR;
 #ifdef CONFIG_CMD_NAND
 static void at91sam9260ek_nand_hw_init(void)
 {
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
 	unsigned long csa;
 
-	/* Enable CS3 */
-	csa = at91_sys_read(AT91_MATRIX_EBICSA);
-	at91_sys_write(AT91_MATRIX_EBICSA,
-		       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+	/* Assign CS3 to NAND/SmartMedia Interface */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+	writel(csa, &matrix->ebicsa);
 
 	/* Configure SMC CS3 for NAND/SmartMedia */
-	at91_sys_write(AT91_SMC_SETUP(3),
-		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
-		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
-	at91_sys_write(AT91_SMC_PULSE(3),
-		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
-		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
-	at91_sys_write(AT91_SMC_CYCLE(3),
-		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
-	at91_sys_write(AT91_SMC_MODE(3),
-		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-		       AT91_SMC_EXNWMODE_DISABLE |
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+		&smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
 #ifdef CONFIG_SYS_NAND_DBW_16
-		       AT91_SMC_DBW_16 |
+		AT91_SMC_MODE_DBW_16 |
 #else /* CONFIG_SYS_NAND_DBW_8 */
-		       AT91_SMC_DBW_8 |
+		AT91_SMC_MODE_DBW_8 |
 #endif
-		       AT91_SMC_TDF_(2));
-
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
+		AT91_SMC_MODE_TDF_CYCLE(2),
+		&smc->cs[3].mode);
 
 	/* Configure RDY/BSY */
 	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
 
 	/* Enable NandFlash */
 	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+
 }
 #endif
 
 #ifdef CONFIG_MACB
 static void at91sam9260ek_macb_hw_init(void)
 {
-	unsigned long rstc;
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
+	struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
+	unsigned long erstl;
 
-	/* Enable clock */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
+	/* Enable EMAC clock */
+	writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
 
 	/*
 	 * Disable pull-up on:
@@ -103,48 +106,57 @@ static void at91sam9260ek_macb_hw_init(void)
 	 * PHY has internal pull-down
 	 */
 	writel(pin_to_mask(AT91_PIN_PA14) |
-	       pin_to_mask(AT91_PIN_PA15) |
-	       pin_to_mask(AT91_PIN_PA17) |
-	       pin_to_mask(AT91_PIN_PA25) |
-	       pin_to_mask(AT91_PIN_PA26) |
-	       pin_to_mask(AT91_PIN_PA28),
-	       pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
+		pin_to_mask(AT91_PIN_PA15) |
+		pin_to_mask(AT91_PIN_PA17) |
+		pin_to_mask(AT91_PIN_PA25) |
+		pin_to_mask(AT91_PIN_PA26) |
+		pin_to_mask(AT91_PIN_PA28),
+		&pioa->pudr);
 
-	rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
+	erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
 
 	/* Need to reset PHY -> 500ms reset */
-	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
-				     (AT91_RSTC_ERSTL & (0x0D << 8)) |
-				     AT91_RSTC_URSTEN);
+	writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
+		AT91_RSTC_MR_URSTEN, &rstc->mr);
 
-	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
+	writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
 
 	/* Wait for end hardware reset */
-	while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
+	while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
+		;
 
 	/* Restore NRST value */
-	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
-				     (rstc) |
-				     AT91_RSTC_URSTEN);
+	writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
+		&rstc->mr);
 
 	/* Re-enable pull-up */
 	writel(pin_to_mask(AT91_PIN_PA14) |
-	       pin_to_mask(AT91_PIN_PA15) |
-	       pin_to_mask(AT91_PIN_PA17) |
-	       pin_to_mask(AT91_PIN_PA25) |
-	       pin_to_mask(AT91_PIN_PA26) |
-	       pin_to_mask(AT91_PIN_PA28),
-	       pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
+		pin_to_mask(AT91_PIN_PA15) |
+		pin_to_mask(AT91_PIN_PA17) |
+		pin_to_mask(AT91_PIN_PA25) |
+		pin_to_mask(AT91_PIN_PA26) |
+		pin_to_mask(AT91_PIN_PA28),
+		&pioa->puer);
 
+	/* Initialize EMAC=MACB hardware */
 	at91_macb_hw_init();
 }
 #endif
 
+int board_early_init_f(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	/* Enable clocks for all PIOs */
+	writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
+		(1 << ATMEL_ID_PIOC),
+		&pmc->pcer);
+
+	return 0;
+}
+
 int board_init(void)
 {
-	/* Enable Ctrlc */
-	console_init_f();
-
 #ifdef CONFIG_AT91SAM9G20EK
 	/* arch number of AT91SAM9260EK-Board */
 	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G20EK;
@@ -153,9 +165,9 @@ int board_init(void)
 	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9260EK;
 #endif
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
-	at91_serial_hw_init();
+	at91_seriald_hw_init();
 #ifdef CONFIG_CMD_NAND
 	at91sam9260ek_nand_hw_init();
 #endif
@@ -171,8 +183,9 @@ int board_init(void)
 
 int dram_init(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	gd->ram_size = get_ram_size(
+		(void *)CONFIG_SYS_SDRAM_BASE,
+		CONFIG_SYS_SDRAM_SIZE);
 	return 0;
 }
 
@@ -186,7 +199,7 @@ int board_eth_init(bd_t *bis)
 {
 	int rc = 0;
 #ifdef CONFIG_MACB
-	rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00);
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
 #endif
 	return rc;
 }

board/atmel/at91sam9260ek/config.mk

@@ -1 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0x23f00000

board/atmel/at91sam9260ek/led.c

@@ -23,16 +23,12 @@
  */
 
 #include <common.h>
-#include <asm/arch/at91sam9260.h>
-#include <asm/arch/at91_pmc.h>
+#include <asm/io.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
 
 void coloured_LED_init(void)
 {
-	/* Enable clock */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA);
-
+	/* Clock is enabled in board_early_init_f() */
 	at91_set_gpio_output(CONFIG_RED_LED, 1);
 	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
 

board/bct-brettl2/config.mk

@@ -25,3 +25,4 @@
 
 CFLAGS_lib += -O2
 CFLAGS_lib/lzma += -O2
+CFLAGS_lib/zlib += -O2

board/bf518f-ezbrd/config.mk

@@ -25,3 +25,4 @@
 
 CFLAGS_lib += -O2
 CFLAGS_lib/lzma += -O2
+CFLAGS_lib/zlib += -O2

board/bf526-ezbrd/config.mk

@@ -25,3 +25,4 @@
 
 CFLAGS_lib += -O2
 CFLAGS_lib/lzma += -O2
+CFLAGS_lib/zlib += -O2

board/bf527-ad7160-eval/config.mk

@@ -25,3 +25,4 @@
 
 CFLAGS_lib += -O2
 CFLAGS_lib/lzma += -O2
+CFLAGS_lib/zlib += -O2

board/bf527-ezkit/config.mk

@@ -25,3 +25,4 @@
 
 CFLAGS_lib += -O2
 CFLAGS_lib/lzma += -O2
+CFLAGS_lib/zlib += -O2

board/bf527-sdp/config.mk

@@ -25,6 +25,7 @@
 
 CFLAGS_lib += -O2
 CFLAGS_lib/lzma += -O2
+CFLAGS_lib/zlib += -O2
 
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 6

board/bf533-ezkit/config.mk

@@ -25,6 +25,7 @@
 
 CFLAGS_lib += -O2
 CFLAGS_lib/lzma += -O2
+CFLAGS_lib/zlib += -O2
 
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8

board/bf533-stamp/config.mk

@@ -25,6 +25,7 @@
 
 CFLAGS_lib += -O2
 CFLAGS_lib/lzma += -O2
+CFLAGS_lib/zlib += -O2
 
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8

board/bf537-stamp/config.mk

@@ -25,6 +25,7 @@
 
 CFLAGS_lib += -O2
 CFLAGS_lib/lzma += -O2
+CFLAGS_lib/zlib += -O2
 
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8

board/bf538f-ezkit/config.mk

@@ -25,6 +25,7 @@
 
 CFLAGS_lib += -O2
 CFLAGS_lib/lzma += -O2
+CFLAGS_lib/zlib += -O2
 
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8

board/bf548-ezkit/config.mk

@@ -25,6 +25,7 @@
 
 CFLAGS_lib += -O2
 CFLAGS_lib/lzma += -O2
+CFLAGS_lib/zlib += -O2
 
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA       := --dma 6

board/bf561-acvilon/config.mk

@@ -25,6 +25,7 @@
 
 CFLAGS_lib += -O2
 CFLAGS_lib/lzma += -O2
+CFLAGS_lib/zlib += -O2
 
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16

board/bf561-ezkit/config.mk

@@ -25,6 +25,7 @@
 
 CFLAGS_lib += -O2
 CFLAGS_lib/lzma += -O2
+CFLAGS_lib/zlib += -O2
 
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16

board/bluewater/snapper9260/Makefile

@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2011 Bluewater Systems
+# Ryan Mallon <ryan@bluewatersys.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= snapper9260.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/bluewater/snapper9260/snapper9260.c

@@ -0,0 +1,169 @@
+/*
+ * Bluewater Systems Snapper 9260/9G20 modules
+ *
+ * (C) Copyright 2011 Bluewater Systems
+ *   Author: Andre Renaud <andre@bluewatersys.com>
+ *   Author: Ryan Mallon <ryan@bluewatersys.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <net.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <pca953x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* IO Expander pins */
+#define IO_EXP_ETH_RESET	(0 << 1)
+#define IO_EXP_ETH_POWER	(1 << 1)
+
+static void macb_hw_init(void)
+{
+	struct at91_pmc *pmc   = (struct at91_pmc  *)ATMEL_BASE_PMC;
+	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
+	struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
+	unsigned long erstl;
+
+	/* Enable clock */
+	writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
+
+	/* Disable pull-ups to prevent PHY going into test mode */
+	writel(pin_to_mask(AT91_PIN_PA14) |
+	       pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA18),
+	       &pioa->pudr);
+
+	/* Power down ethernet */
+	pca953x_set_dir(0x28, IO_EXP_ETH_POWER, PCA953X_DIR_OUT);
+	pca953x_set_val(0x28, IO_EXP_ETH_POWER, 1);
+
+	/* Hold ethernet in reset */
+	pca953x_set_dir(0x28, IO_EXP_ETH_RESET, PCA953X_DIR_OUT);
+	pca953x_set_val(0x28, IO_EXP_ETH_RESET, 0);
+
+	/* Enable ethernet power */
+	pca953x_set_val(0x28, IO_EXP_ETH_POWER, 0);
+
+	/* Need to reset PHY -> 500ms reset */
+	erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
+	writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
+	       AT91_RSTC_MR_URSTEN, &rstc->mr);
+	writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
+
+	/* Wait for end hardware reset */
+	while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
+		;
+
+	/* Restore NRST value */
+	writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
+
+	/* Bring the ethernet out of reset */
+	pca953x_set_val(0x28, IO_EXP_ETH_RESET, 1);
+
+	/* The phy internal reset take 21ms */
+	udelay(21 * 1000);
+
+	/* Re-enable pull-up */
+	writel(pin_to_mask(AT91_PIN_PA14) |
+	       pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA18),
+	       &pioa->puer);
+
+	at91_macb_hw_init();
+}
+
+static void nand_hw_init(void)
+{
+	struct at91_smc *smc       = (struct at91_smc    *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	unsigned long csa;
+
+	/* Enable CS3 as NAND/SmartMedia */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+	writel(csa, &matrix->ebicsa);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+	       &smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
+	       AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
+	       &smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
+	       &smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+	       AT91_SMC_MODE_DBW_8 |
+	       AT91_SMC_MODE_TDF_CYCLE(3),
+	       &smc->cs[3].mode);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+
+int board_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	/* Enable PIO clocks */
+	writel((1 << ATMEL_ID_PIOA) |
+	       (1 << ATMEL_ID_PIOB) |
+	       (1 << ATMEL_ID_PIOC), &pmc->pcer);
+
+	/* The mach-type is the same for both Snapper 9260 and 9G20 */
+	gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260;
+
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	/* Initialise peripherals */
+	at91_seriald_hw_init();
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	nand_hw_init();
+	macb_hw_init();
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x1f);
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+void reset_phy(void)
+{
+}

board/cm-bf527/config.mk

@@ -25,3 +25,4 @@
 
 CFLAGS_lib += -O2
 CFLAGS_lib/lzma += -O2
+CFLAGS_lib/zlib += -O2