Prepare v2013.01.01

Signed-off-by: Tom Rini <trini@ti.com>
vfat: Fix mkcksum argument sizes
2026-06-04 18:56:43 +03:00 · 2013-01-31 14:47:42 -05:00 · 2013-01-31 14:46:43 -05:00 · 2013-01-31 14:46:40 -05:00
2485 changed files with 74272 additions and 139149 deletions
--- a/.checkpatch.conf
+++ b/.checkpatch.conf
@@ -12,12 +12,3 @@

 # For min/max
 --ignore MINMAX
-
-# enable more tests
--strict
-
-# Not Linux, so we don't recommend usleep_range() over udelay()
--ignore USLEEP_RANGE
-
-# Ignore networking block comment style
--ignore NETWORKING_BLOCK_COMMENT_STYLE
--- a/.gitignore
+++ b/.gitignore
@@ -15,7 +15,6 @@
 *.swp
 *.patch
 *.bin
-*.cfgtmp

 # Build tree
 /build-*
@@ -25,13 +24,10 @@
 #

 /MLO
-/SPL
 /System.map
 /u-boot
 /u-boot.hex
 /u-boot.imx
-/u-boot-with-spl.imx
-/u-boot-with-nand-spl.imx
 /u-boot.map
 /u-boot.srec
 /u-boot.ldr
@@ -46,8 +42,8 @@
 /u-boot.ais
 /u-boot.dtb
 /u-boot.sb
-/u-boot.bd
 /u-boot.geany
+/include/u-boot.lst

 #
 # Generated files
@@ -80,11 +76,5 @@ cscope.*
 /ctags
 /etags

-# gnu global files
-GPATH
-GRTAGS
-GSYMS
-GTAGS
-
 # spl ais files
 /spl/*.ais
--- a/4
+++ b/4
@@ -124,10 +124,6 @@ N: James F. Dougherty
 E: jfd@GigabitNetworks.COM
 D: Port to the MOUSSE board

-N: Mike Dunn
-E: mikedunn@newsguy.com
-D: Palmtreo680 board, docg4 nand flash driver
-
 N: Dave Ellis
 E: DGE@sixnetio.com
 D: EEPROM Speedup, SXNI855T port
--- a/126
+++ b/126
@@ -27,10 +27,6 @@ Poonam Aggrwal <poonam.aggrwal@freescale.com>

 	BSC9131RDB	BSC9131

-Naveen Burmi <NaveenBurmi@freescale.com>
-
-	BSC9132QDS	BSC9132
-
 Greg Allen <gallen@arlut.utexas.edu>

 	UTX8245		MPC8245
@@ -150,6 +146,9 @@ Wolfgang Denk <wd@denx.de>

 	P3G4		MPC7410

+	PCIPPC2		MPC750
+	PCIPPC6		MPC750
+
 Phil Edworthy <phil.edworthy@renesas.com>

 	rsk7264		SH7264
@@ -160,9 +159,8 @@ egnite GmbH <info@egnite.de>

 Dirk Eibach <eibach@gdsys.de>

-	controlcenterd	P1022
 	devconcenter	PPC460EX
-	dlvision	PPC405EP
+	dlvision        PPC405EP
 	dlvision-10g	PPC405EP
 	gdppc440etx	PPC440EP/GR
 	intip		PPC460EX
@@ -232,7 +230,6 @@ Wolfgang Grandegger <wg@denx.de>

 Anatolij Gustschin <agust@denx.de>

-	ac14xx		MPC5121e
 	O2D		MPC5200
 	O2D300		MPC5200
 	O2DNT2		MPC5200
@@ -396,7 +393,6 @@ Ricardo Ribalda <ricardo.ribalda@uam.es>
 Stefan Roese <sr@denx.de>

 	a3m071		MPC5200
-	a4m2k		MPC5200

 	P3M7448		MPC7448

@@ -607,8 +603,6 @@ Enric Balletbo i Serra <eballetbo@iseebcn.com>

 	igep0020	ARM ARMV7 (OMAP3xx SoC)
 	igep0030	ARM ARMV7 (OMAP3xx SoC)
-	igep0032	ARM ARMV7 (OMAP3xx SoC)
-	igep0033	ARM ARMV7 (AM33xx Soc)

 Eric Benard <eric@eukrea.com>

@@ -652,9 +646,6 @@ Wolfgang Denk <wd@denx.de>
 	imx27lite	i.MX27
 	qong		i.MX31

-Mike Dunn <mikedunn@newsguy.com>
-	palmtreo680	pxa270
-
 Kristoffer Ericson <kristoffer.ericson@gmail.com>

 	jornada	SA1110
@@ -666,10 +657,8 @@ Fabio Estevam <fabio.estevam@freescale.com>
 	mx31pdk		i.MX31
 	mx53ard		i.MX53
 	mx53smd		i.MX53
-	mx6sabresd	i.MX6Q/DL
+	mx6qsabresd	i.MX6Q
 	mx6qsabreauto	i.MX6Q
-	wandboard	i.MX6DL/S/Q
-	mx6slevk	i.MX6SL

 Daniel Gorsulowski <daniel.gorsulowski@esd.eu>

@@ -689,16 +678,12 @@ Simon Guinot <simon.guinot@sequanux.org>

 Igor Grinberg <grinberg@compulab.co.il>

-	cm_t35		ARM ARMV7 (OMAP3xx Soc)
+	cm-t35		ARM ARMV7 (OMAP3xx Soc)

 Stefan Herbrechtsmeier <stefan@code.herbrechtsmeier.net>

 	dns325		ARM926EJS (Kirkwood SoC)

-Lauri Hintsala <lauri.hintsala@bluegiga.com>
-
-	apx4devkit	i.MX28
-
 Vaibhav Hiremath <hvaibhav@ti.com>

 	am3517_evm	ARM ARMV7 (AM35x SoC)
@@ -817,6 +802,10 @@ Linus Walleij <linus.walleij@linaro.org>
 	integratorap	various
 	integratorcp	various

+Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
+
+	apx4devkit	i.MX28
+
 Luka Perkov <luka@openwrt.org>

 	ib62x0		ARM926EJS
@@ -826,9 +815,6 @@ Dave Peverley <dpeverley@mpc-data.co.uk>

 	omap730p2	ARM926EJS

-Lars Poeschel <poeschel@lemonage.de>
-	pcm051  	ARM ARMV7 (AM33xx Soc)
-
 Mathieu Poirier <mathieu.poirier@linaro.org>

 	snowball	ARM ARMV7 (u8500 SoC)
@@ -840,10 +826,6 @@ Stelian Pop <stelian@popies.net>
 	at91sam9263ek	ARM926EJS (AT91SAM9263 SoC)
 	at91sam9rlek	ARM926EJS (AT91SAM9RL SoC)

-Matt Porter <mporter@ti.com>
-
-	ti814x_evm	ARM ARMV7 (TI814x Soc)
-
 Dave Purdy <david.c.purdy@gmail.com>

 	pogo_e02	ARM926EJS (Kirkwood SoC)
@@ -854,10 +836,6 @@ Sricharan R <r.sricharan@ti.com>
 	omap4_sdp4430	ARM ARMV7 (OMAP4xx SoC)
 	omap5_evm	ARM ARMV7 (OMAP5xx Soc)

-Suriyan Ramasami <suriyan.r@gmail.com>
-
-	goflexhome	ARM926EJS (Kirkwood SoC)
-
 Thierry Reding <thierry.reding@avionic-design.de>

 	plutux		Tegra20 (ARM7 & A9 Dual Core)
@@ -887,8 +865,6 @@ Stefan Roese <sr@denx.de>

 	x600		ARM926EJS (spear600 Soc)

-	titanium	i.MX6Q
-
 	pdnb3		xscale/ixp
 	scpu		xscale/ixp

@@ -901,10 +877,6 @@ Steve Sakoman <sakoman@gmail.com>

 	omap3_overo	ARM ARMV7 (OMAP3xx SoC)

-Leo Sartre <lsartre@adeneo-embedded.com>
-
-	cgtqmx6qeval		i.MX6Q
-
 Jens Scharsig <esw@bus-elektronik.de>

 	eb_cpux9k2	ARM920T (AT91RM9200 SoC)
@@ -930,11 +902,6 @@ Matt Sealey <matt@genesi-usa.com>

 Bo Shen <voice.shen@atmel.com>
 	at91sam9x5ek		ARM926EJS (AT91SAM9G15,G25,G35,X25,X35 SoC)
-	sama5d3xek		ARMV7 (SAMA5D31, D33, D34, D35 SoC)
-
-Rajeshwari Shinde <rajeshwari.s@samsung.com>
-
-	snow			ARM ARMV7 (EXYNOS5250 SoC)

 Michal Simek <monstr@monstr.eu>

@@ -968,27 +935,16 @@ Marek Vasut <marek.vasut@gmail.com>
 	palmtc		xscale/pxa
 	vpac270		xscale/pxa
 	zipitz2		xscale/pxa
-	mx23_olinuxino	i.MX23
 	m28evk		i.MX28
 	sc_sps_1	i.MX28
-	m53evk		i.MX53

 Hugo Villeneuve <hugo.villeneuve@lyrtech.com>

 	SFFSDR		ARM926EJS

-Lokesh Vutla <lokeshvutla@ti.com>
-
-	dra7xx_evm	ARM ARMV7 (DRA7xx Soc)
-
 Matt Waddel <matt.waddel@linaro.org>

-	vexpress_ca9x4	ARM ARMV7 (Quad Core)
-	vexpress_ca5x2	ARM ARMV7 (Dual Core)
-
-Otavio Salvador <otavio@ossystems.com.br>
-
-	mx23evk		i.MX23
+	ca9x4_ct_vxp	ARM ARMV7 (Quad Core)

 Prafulla Wadaskar <prafulla@marvell.com>

@@ -1007,8 +963,6 @@ Tom Warren <twarren@nvidia.com>

 	harmony		Tegra20 (ARM7 & A9 Dual Core)
 	seaboard	Tegra20 (ARM7 & A9 Dual Core)
-	cardhu		Tegra30 (ARM7 & A9 Quad Core)
-	dalmore		Tegra114 (ARM7 & A15 Quad Core)

 Tom Warren <twarren@nvidia.com>
 Stephen Warren <swarren@nvidia.com>
@@ -1017,7 +971,6 @@ Stephen Warren <swarren@nvidia.com>
 	paz00		Tegra20 (ARM7 & A9 Dual Core)
 	trimslice	Tegra20 (ARM7 & A9 Dual Core)
 	whistler	Tegra20 (ARM7 & A9 Dual Core)
-	beaver		Tegra30 (ARM7 & A9 Quad Core)

 Stephen Warren <swarren@wwwdotorg.org>

@@ -1037,8 +990,9 @@ Matthias Weisser <weisserm@arcor.de>
 	jadecpu		ARM926EJS (MB86R01 SoC)
 	zmx25		ARM926EJS (imx25 SoC)

-Josh Wu <josh.wu@atmel.com>
-	at91sam9n12ek	ARM926EJS (AT91SAM9N12 SoC)
+Richard Woodruff <r-woodruff2@ti.com>
+
+	omap2420h4	ARM1136EJS

 Ilya Yanok <yanok@emcraft.com>

@@ -1053,6 +1007,10 @@ Vladimir Zapolskiy <vz@mleia.com>

 	devkit3250	lpc32xx

+Zhong Hongbo <bocui107@gmail.com>
+
+	SMDK6400	ARM1176 (S3C6400 SoC)
+
 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
 Tetsuyuki Kobayashi <koba@kmckk.co.jp>

@@ -1066,22 +1024,6 @@ Pali Rohár <pali.rohar@gmail.com>

 	nokia_rx51	ARM ARMV7 (OMAP34xx SoC)

-Eric Nelson <eric.nelson@boundarydevices.com>
-	nitrogen6dl		i.MX6DL		1GB
-	nitrogen6dl2g		i.MX6DL		2GB
-	nitrogen6q		i.MX6Q/6D	1GB
-	nitrogen6q2g    	i.MX6Q/6D	2GB
-	nitrogen6s		i.MX6S		512MB
-	nitrogen6s1g		i.MX6S		1GB
-
-Alison Wang <b18965@freescale.com>
-
-	vf610twr	VF610
-
-Sergey Yanovich <ynvich@gmail.com>
-
-	lp8x4x		xscale/pxa
-
 -------------------------------------------------------------------------

 Unknown / orphaned boards:
@@ -1102,19 +1044,9 @@ Unknown / orphaned boards:
 #	Board		CPU						#
 #########################################################################

-Simon Glass <sjg@chromium.org>
+Graeme Russ <graeme.russ@gmail.com>

-	chromebook-x86	Coreboot runs first, then U-Boot
-			Supports Intel Sandy Bridge / Ivy Bridge so far
-
-			Chromebooks for x86, including:
-				Samsung Series 5 Chromebook
-				Acer AC700 Chromebook
-				Acer C7 Chromebook
-				Samsung Chromebook 550
-				HP Pavillion Chromebook
-				Acer C710 Chromebook
-				Chromebook Pixel
+	eNET		AMD SC520

 #########################################################################
 # MIPS Systems:								#
@@ -1134,6 +1066,10 @@ Stefan Roese <sr@denx.de>

 	vct_xxx		MIPS32 4Kc

+Xiangfu Liu <xiangfu@openmobilefree.net>
+
+	qi_lb60		MIPS32 (XBurst Jz4740 SoC)
+
 -------------------------------------------------------------------------

 Unknown / orphaned boards:
@@ -1278,7 +1214,7 @@ Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
 #	Board		CPU						#
 #########################################################################

-Sonic Zhang <sonic.adi@gmail.com>
+Mike Frysinger <vapier@gentoo.org>
 Blackfin Team <u-boot-devel@blackfin.uclinux.org>

 	BF506F-EZKIT	BF506
@@ -1295,7 +1231,6 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>
 	BF538F-EZKIT	BF538
 	BF548-EZKIT	BF548
 	BF561-EZKIT	BF561
-	BF609-EZKIT	BF609

 M.Hasewinkel (MHA) <info@ssv-embedded.de>

@@ -1375,17 +1310,6 @@ Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>

 	openrisc-generic	OpenRISC

-#########################################################################
-# Sandbox:								#
-#									#
-# Maintainer Name, Email Address					#
-#	Board		CPU						#
-#########################################################################
-
-Simon Glass <sjg@chromium.org>
-
-	sandbox		sandbox
-
 #########################################################################
 # End of MAINTAINERS list						#
 #########################################################################
--- a/64
+++ b/64
@@ -35,9 +35,6 @@ usage()
 	Environment variables:
 	  BUILD_NCPUS      number of parallel make jobs (default: auto)
 	  CROSS_COMPILE    cross-compiler toolchain prefix (default: "")
-	  CROSS_COMPILE_<ARCH> cross-compiler toolchain prefix for
-	                   architecture "ARCH".  Substitute "ARCH" for any
-	                   supported architecture (default: "")
 	  MAKEALL_LOGDIR   output all logs to here (default: ./LOG/)
 	  BUILD_DIR        output build directory (default: ./)
 	  BUILD_NBUILDS	   number of parallel targets (default: 1)
@@ -104,9 +101,9 @@ while true ; do
 	-s|--soc)
 		# echo "Option SoC: argument \`$2'"
 		if [ "$opt_s" ] ; then
-			opt_s="${opt_s%)} || \$6 == \"$2\" || \$6 ~ /$2/)"
+			opt_s="${opt_s%)} || \$6 == \"$2\")"
 		else
-			opt_s="(\$6 == \"$2\" || \$6 ~ /$2/)"
+			opt_s="(\$6 == \"$2\")"
 		fi
 		SELECTED='y'
 		shift 2 ;;
@@ -183,6 +180,13 @@ else
 	JOBS=""
 fi

+
+if [ "${CROSS_COMPILE}" ] ; then
+	MAKE="make CROSS_COMPILE=${CROSS_COMPILE}"
+else
+	MAKE=make
+fi
+
 if [ "${MAKEALL_LOGDIR}" ] ; then
 	LOG_DIR=${MAKEALL_LOGDIR}
 else
@@ -267,6 +271,12 @@ LIST_8xx="$(boards_by_cpu mpc8xx)"

 LIST_4xx="$(boards_by_cpu ppc4xx)"

+#########################################################################
+## MPC8220 Systems
+#########################################################################
+
+LIST_8220="$(boards_by_cpu mpc8220)"
+
 #########################################################################
 ## MPC824x Systems
 #########################################################################
@@ -318,6 +328,7 @@ LIST_powerpc="		\
 	${LIST_512x}	\
 	${LIST_5xxx}	\
 	${LIST_8xx}	\
+	${LIST_8220}	\
 	${LIST_824x}	\
 	${LIST_8260}	\
 	${LIST_83xx}	\
@@ -435,11 +446,16 @@ LIST_mips="		\
 ## MIPS Systems		(little endian)
 #########################################################################

+LIST_xburst_el="	\
+	qi_lb60		\
+"
+
 LIST_au1xx0_el="	\
 	dbau1550_el	\
 	pb1000		\
 "
 LIST_mips_el="			\
+	${LIST_xburst_el}	\
 	${LIST_au1xx0_el}	\
 "
 #########################################################################
@@ -569,18 +585,6 @@ get_target_maintainers() {
 	echo "$mail"
 }

-get_target_arch() {
-	local target=$1
-
-	# Automatic mode
-	local line=`egrep -i "^[[:space:]]*${target}[[:space:]]" boards.cfg`
-
-	if [ -z "${line}" ] ; then echo "" ; return ; fi
-
-	set ${line}
-	echo "$2"
-}
-
 list_target() {
 	if [ "$PRINT_MAINTS" != 'y' ] ; then
 		echo "$1"
@@ -651,16 +655,6 @@ build_target() {

 	export BUILD_DIR="${output_dir}"

-	target_arch=$(get_target_arch ${target})
-	eval cross_toolchain=\$CROSS_COMPILE_`echo $target_arch | tr '[:lower:]' '[:upper:]'`
-	if [ "${cross_toolchain}" ] ; then
-	    MAKE="make CROSS_COMPILE=${cross_toolchain}"
-	elif [ "${CROSS_COMPILE}" ] ; then
-	    MAKE="make CROSS_COMPILE=${CROSS_COMPILE}"
-	else
-	    MAKE=make
-	fi
-
 	${MAKE} distclean >/dev/null
 	${MAKE} -s ${target}_config

@@ -790,20 +784,8 @@ build_targets() {
 #-----------------------------------------------------------------------

 kill_children() {
-	local OS=$(uname -s)
-	local children=""
-	case "${OS}" in
-		"Darwin")
-			# Mac OS X is known to have BSD style ps
-			local pgid=$(ps -p $$ -o pgid | sed -e "/PGID/d")
-			children=$(ps -g $pgid -o pid | sed -e "/PID\|$$\|$pgid/d")
-			;;
-		*)
-			# everything else tries the GNU style
-			local pgid=$(ps -p $$ --no-headers -o "%r" | tr -d ' ')
-			children=$(pgrep -g $pgid | sed -e "/$$\|$pgid/d")
-			;;
-	esac
+	local pgid=`ps -p $$ --no-headers -o "%r" | tr -d ' '`
+	local children=`pgrep -g $pgid | grep -v $$ | grep -v $pgid`

 	kill $children 2> /dev/null
 	wait $children 2> /dev/null
--- a/144
+++ b/144
@@ -22,8 +22,8 @@
 #

 VERSION = 2013
-PATCHLEVEL = 07
-SUBLEVEL =
+PATCHLEVEL = 01
+SUBLEVEL = 01
 EXTRAVERSION =
 ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
@@ -46,7 +46,12 @@ HOSTARCH := $(shell uname -m | \
 HOSTOS := $(shell uname -s | tr '[:upper:]' '[:lower:]' | \
 	    sed -e 's/\(cygwin\).*/cygwin/')

-export	HOSTARCH HOSTOS
+# Set shell to bash if possible, otherwise fall back to sh
+SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \
+	else if [ -x /bin/bash ]; then echo /bin/bash; \
+	else echo sh; fi; fi)
+
+export	HOSTARCH HOSTOS SHELL

 # Deal with colliding definitions from tcsh etc.
 VENDOR=
@@ -183,16 +188,6 @@ endif
 # load other configuration
 include $(TOPDIR)/config.mk

-# Targets which don't build the source code
-NON_BUILD_TARGETS = backup clean clobber distclean mkproper tidy unconfig
-
-# Only do the generic board check when actually building, not configuring
-ifeq ($(filter $(NON_BUILD_TARGETS),$(MAKECMDGOALS)),)
-ifeq ($(findstring _config,$(MAKECMDGOALS)),)
-$(CHECK_GENERIC_BOARD)
-endif
-endif
-
 # If board code explicitly specified LDSCRIPT or CONFIG_SYS_LDSCRIPT, use
 # that (or fail if absent).  Otherwise, search for a linker script in a
 # standard location.
@@ -235,6 +230,10 @@ endif
 # U-Boot objects....order is important (i.e. start must be first)

 OBJS  = $(CPUDIR)/start.o
+ifeq ($(CPU),x86)
+RESET_OBJS-$(CONFIG_X86_NO_RESET_VECTOR) += $(CPUDIR)/start16.o
+RESET_OBJS-$(CONFIG_X86_NO_RESET_VECTOR) += $(CPUDIR)/resetvec.o
+endif
 ifeq ($(CPU),ppc4xx)
 OBJS += $(CPUDIR)/resetvec.o
 endif
@@ -242,12 +241,11 @@ ifeq ($(CPU),mpc85xx)
 OBJS += $(CPUDIR)/resetvec.o
 endif

-OBJS := $(addprefix $(obj),$(OBJS))
+OBJS := $(addprefix $(obj),$(OBJS) $(RESET_OBJS-))

 HAVE_VENDOR_COMMON_LIB = $(if $(wildcard board/$(VENDOR)/common/Makefile),y,n)

 LIBS-y += lib/libgeneric.o
-LIBS-y += lib/rsa/librsa.o
 LIBS-y += lib/lzma/liblzma.o
 LIBS-y += lib/lzo/liblzo.o
 LIBS-y += lib/zlib/libz.o
@@ -270,7 +268,6 @@ LIBS-y += fs/libfs.o \
 	fs/fdos/libfdos.o \
 	fs/jffs2/libjffs2.o \
 	fs/reiserfs/libreiserfs.o \
-	fs/sandbox/libsandboxfs.o \
 	fs/ubifs/libubifs.o \
 	fs/yaffs2/libyaffs2.o \
 	fs/zfs/libzfs.o
@@ -279,7 +276,6 @@ LIBS-y += disk/libdisk.o
 LIBS-y += drivers/bios_emulator/libatibiosemu.o
 LIBS-y += drivers/block/libblock.o
 LIBS-$(CONFIG_BOOTCOUNT_LIMIT) += drivers/bootcount/libbootcount.o
-LIBS-y += drivers/crypto/libcrypto.o
 LIBS-y += drivers/dma/libdma.o
 LIBS-y += drivers/fpga/libfpga.o
 LIBS-y += drivers/gpio/libgpio.o
@@ -321,7 +317,7 @@ endif
 LIBS-y += drivers/rtc/librtc.o
 LIBS-y += drivers/serial/libserial.o
 LIBS-y += drivers/sound/libsound.o
-LIBS-y += drivers/tpm/libtpm.o
+LIBS-$(CONFIG_GENERIC_LPC_TPM) += drivers/tpm/libtpm.o
 LIBS-y += drivers/twserial/libtws.o
 LIBS-y += drivers/usb/eth/libusb_eth.o
 LIBS-y += drivers/usb/gadget/libusb_gadget.o
@@ -338,11 +334,11 @@ LIBS-y += api/libapi.o
 LIBS-y += post/libpost.o
 LIBS-y += test/libtest.o

-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),)
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
 LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
 endif

-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610))
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
 LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
 endif

@@ -352,7 +348,7 @@ endif
 ifeq ($(SOC),exynos)
 LIBS-y += $(CPUDIR)/s5p-common/libs5p-common.o
 endif
-ifneq ($(CONFIG_TEGRA),)
+ifeq ($(SOC),tegra20)
 LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o
 LIBS-y += arch/$(ARCH)/cpu/tegra-common/libcputegra-common.o
 LIBS-y += $(CPUDIR)/tegra-common/libtegra-common.o
@@ -413,13 +409,11 @@ ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
 ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin
 ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin
 ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin
-ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin
-ifneq ($(CONFIG_SPL_TARGET),)
 ALL-$(CONFIG_SPL) += $(obj)$(subst ",,$(CONFIG_SPL_TARGET))
-endif
+ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin

 # enable combined SPL/u-boot/dtb rules for tegra
-ifneq ($(CONFIG_TEGRA),)
+ifeq ($(SOC),tegra20)
 ifeq ($(CONFIG_OF_SEPARATE),y)
 ALL-y += $(obj)u-boot-dtb-tegra.bin
 else
@@ -473,8 +467,9 @@ $(obj)u-boot.img:	$(obj)u-boot.bin
 			sed -e 's/"[	 ]*$$/ for $(BOARD) board"/') \
 		-d $< $@

-$(obj)u-boot.imx: $(obj)u-boot.bin depend
-		$(MAKE) -C $(SRCTREE)/arch/arm/imx-common $(OBJTREE)/u-boot.imx
+$(obj)u-boot.imx:       $(obj)u-boot.bin
+		$(obj)tools/mkimage -n  $(CONFIG_IMX_CONFIG) -T imximage \
+		-e $(CONFIG_SYS_TEXT_BASE) -d $< $@

 $(obj)u-boot.kwb:       $(obj)u-boot.bin
 		$(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \
@@ -491,22 +486,11 @@ $(obj)u-boot.sha1:	$(obj)u-boot.bin
 $(obj)u-boot.dis:	$(obj)u-boot
 		$(OBJDUMP) -d $< > $@

-
-
 $(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
-		$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \
-			-I binary -O binary $< $(obj)spl/u-boot-spl-pad.bin
+		$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
 		cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@
 		rm $(obj)spl/u-boot-spl-pad.bin

-$(obj)u-boot-with-spl.imx: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
-		$(MAKE) -C $(SRCTREE)/arch/arm/imx-common \
-			$(OBJTREE)/u-boot-with-spl.imx
-
-$(obj)u-boot-with-nand-spl.imx: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
-		$(MAKE) -C $(SRCTREE)/arch/arm/imx-common \
-			$(OBJTREE)/u-boot-with-nand-spl.imx
-
 $(obj)u-boot.ubl:       $(obj)u-boot-with-spl.bin
 		$(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \
 		-e $(CONFIG_SYS_TEXT_BASE) -d $< $(obj)u-boot.ubl
@@ -523,9 +507,12 @@ $(obj)u-boot.ais:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
 		cat $(obj)spl/u-boot-spl-pad.ais $(obj)u-boot.img > \
 			$(obj)u-boot.ais

+# Specify the target for use in elftosb call
+ELFTOSB_TARGET-$(CONFIG_MX28) = imx28

 $(obj)u-boot.sb:       $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
-		$(MAKE) -C $(SRCTREE)/$(CPUDIR)/$(SOC)/ $(OBJTREE)/u-boot.sb
+		elftosb -zf $(ELFTOSB_TARGET-y) -c $(TOPDIR)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd \
+			-o $(obj)u-boot.sb

 # On x600 (SPEAr600) U-Boot is appended to U-Boot SPL.
 # Both images are created using mkimage (crc etc), so that the ROM
@@ -543,33 +530,24 @@ $(obj)u-boot.spr:	$(obj)u-boot.img $(obj)spl/u-boot-spl.bin
 			conv=notrunc 2>/dev/null
 		cat $(obj)spl/u-boot-spl-pad.img $(obj)u-boot.img > $@

-ifneq ($(CONFIG_TEGRA),)
-$(obj)u-boot-nodtb-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
-		$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
-		cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@
-		rm $(obj)spl/u-boot-spl-pad.bin
-
+ifeq ($(SOC),tegra20)
 ifeq ($(CONFIG_OF_SEPARATE),y)
-$(obj)u-boot-dtb-tegra.bin: $(obj)u-boot-nodtb-tegra.bin $(obj)u-boot.dtb
-		cat $(obj)u-boot-nodtb-tegra.bin $(obj)u-boot.dtb > $@
+nodtb=dtb
+dtbfile=$(obj)u-boot.dtb
+else
+nodtb=nodtb
+dtbfile=
 endif
+
+$(obj)u-boot-$(nodtb)-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin $(dtbfile)
+		$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
+		cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin $(dtbfile) > $@
+		rm $(obj)spl/u-boot-spl-pad.bin
 endif

 $(obj)u-boot-img.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
 		cat $(obj)spl/u-boot-spl.bin $(obj)u-boot.img > $@

-# PPC4xx needs the SPL at the end of the image, since the reset vector
-# is located at 0xfffffffc. So we can't use the "u-boot-img.bin" target
-# and need to introduce a new build target with the full blown U-Boot
-# at the start padded up to the start of the SPL image. And then concat
-# the SPL image to the end.
-$(obj)u-boot-img-spl-at-end.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
-		tr "\000" "\377" < /dev/zero | dd ibs=1 count=$(CONFIG_UBOOT_PAD_TO) \
-			of=$(obj)u-boot-pad.img 2>/dev/null
-		dd if=$(obj)u-boot.img of=$(obj)u-boot-pad.img \
-			conv=notrunc 2>/dev/null
-		cat $(obj)u-boot-pad.img $(obj)spl/u-boot-spl.bin > $@
-
 ifeq ($(CONFIG_SANDBOX),y)
 GEN_UBOOT = \
 		cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \
@@ -577,8 +555,10 @@ GEN_UBOOT = \
 			$(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map -o u-boot
 else
 GEN_UBOOT = \
+		UNDEF_LST=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \
+		sed  -n -e 's/.*\($(SYM_PREFIX)_u_boot_list_.*\)/-u\1/p'|sort|uniq`;\
 		cd $(LNDIR) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \
-			$(__OBJS) \
+			$$UNDEF_LST $(__OBJS) \
 			--start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
 			-Map u-boot.map -o u-boot
 endif
@@ -611,7 +591,11 @@ $(SUBDIR_EXAMPLES): $(obj)u-boot
 $(LDSCRIPT):	depend
 		$(MAKE) -C $(dir $@) $(notdir $@)

-$(obj)u-boot.lds: $(LDSCRIPT)
+# The following line expands into whole rule which generates u-boot.lst,
+# the file containing u-boots LG-array linker section. This is included into
+# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
+$(eval $(call make_u_boot_list, $(obj)include/u-boot.lst, $(LIBBOARD) $(LIBS)))
+$(obj)u-boot.lds: $(LDSCRIPT) $(obj)include/u-boot.lst
 		$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$< >$@

 nand_spl:	$(TIMESTAMP_FILE) $(VERSION_FILE) depend
@@ -744,13 +728,6 @@ tools: $(VERSION_FILE) $(TIMESTAMP_FILE)
 	$(MAKE) -C $@ all
 endif	# config.mk

-# ARM relocations should all be R_ARM_RELATIVE.
-checkarmreloc: $(obj)u-boot
-	@if test "R_ARM_RELATIVE" != \
-		"`$(CROSS_COMPILE)readelf -r $< | cut -d ' ' -f 4 | grep R_ARM | sort -u`"; \
-		then echo "$< contains relocations other than \
-		R_ARM_RELATIVE"; false; fi
-
 $(VERSION_FILE):
 		@mkdir -p $(dir $(VERSION_FILE))
 		@( localvers='$(shell $(TOPDIR)/tools/setlocalversion $(TOPDIR))' ; \
@@ -808,6 +785,23 @@ $(obj).boards.depend:	boards.cfg
 lcname	= $(shell echo $(1) | sed -e 's/\(.*\)_config/\L\1/')
 ucname	= $(shell echo $(1) | sed -e 's/\(.*\)_config/\U\1/')

+#########################################################################
+## ARM1176 Systems
+#########################################################################
+smdk6400_noUSB_config	\
+smdk6400_config	:	unconfig
+	@mkdir -p $(obj)include $(obj)board/samsung/smdk6400
+	@mkdir -p $(obj)nand_spl/board/samsung/smdk6400
+	@echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
+	@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
+	@if [ -z "$(findstring smdk6400_noUSB_config,$@)" ]; then			\
+		echo "RAM_TEXT = 0x57e00000" >> $(obj)board/samsung/smdk6400/config.tmp;\
+	else										\
+		echo "RAM_TEXT = 0xc7e00000" >> $(obj)board/samsung/smdk6400/config.tmp;\
+	fi
+	@$(MKCONFIG) smdk6400 arm arm1176 smdk6400 samsung s3c64xx
+	@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
+
 #########################################################################
 #########################################################################

@@ -832,12 +826,12 @@ clean:
 	       $(obj)tools/mk{smdk5250,}spl				  \
 	       $(obj)tools/mxsboot					  \
 	       $(obj)tools/ncb		   $(obj)tools/ubsha1		  \
-	       $(obj)tools/kernel-doc/docproc				  \
-	       $(obj)tools/proftool
+	       $(obj)tools/kernel-doc/docproc
 	@rm -f $(obj)board/cray/L1/{bootscript.c,bootscript.image}	  \
 	       $(obj)board/matrix_vision/*/bootscript.img		  \
 	       $(obj)board/voiceblue/eeprom 				  \
 	       $(obj)u-boot.lds						  \
+	       $(obj)include/u-boot.lst			  		  \
 	       $(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs]	  \
 	       $(obj)arch/blackfin/cpu/init.{lds,elf}
 	@rm -f $(obj)include/bmp_logo.h
@@ -849,8 +843,7 @@ clean:
 	@$(MAKE) -s -C doc/DocBook/ cleandocs
 	@find $(OBJTREE) -type f \
 		\( -name 'core' -o -name '*.bak' -o -name '*~' -o -name '*.su' \
-		-o -name '*.o'	-o -name '*.a' -o -name '*.exe' \
-		-o -name '*.cfgtmp' \) -print \
+		-o -name '*.o'	-o -name '*.a' -o -name '*.exe'	\) -print \
 		| xargs rm -f

 # Removes everything not needed for testing u-boot
@@ -867,18 +860,15 @@ clobber:	tidy
 	@rm -f $(obj)u-boot.kwb
 	@rm -f $(obj)u-boot.pbl
 	@rm -f $(obj)u-boot.imx
-	@rm -f $(obj)u-boot-with-spl.imx
-	@rm -f $(obj)u-boot-with-nand-spl.imx
 	@rm -f $(obj)u-boot.ubl
 	@rm -f $(obj)u-boot.ais
 	@rm -f $(obj)u-boot.dtb
 	@rm -f $(obj)u-boot.sb
-	@rm -f $(obj)u-boot.bd
 	@rm -f $(obj)u-boot.spr
 	@rm -f $(obj)nand_spl/{u-boot.{lds,lst},System.map}
 	@rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map}
 	@rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map}
-	@rm -f $(obj)spl/u-boot-spl.lds
+	@rm -f $(obj)spl/{u-boot-spl.lds,u-boot.lst}
 	@rm -f $(obj)MLO MLO.byteswap
 	@rm -f $(obj)SPL
 	@rm -f $(obj)tools/xway-swap-bytes
--- a/419
+++ b/419
@@ -201,6 +201,7 @@ Directory Hierarchy:
      /mpc5xx		Files specific to Freescale MPC5xx CPUs
      /mpc5xxx		Files specific to Freescale MPC5xxx CPUs
      /mpc8xx		Files specific to Freescale MPC8xx CPUs
+      /mpc8220		Files specific to Freescale MPC8220 CPUs
      /mpc824x		Files specific to Freescale MPC824x CPUs
      /mpc8260		Files specific to Freescale MPC8260 CPUs
      /mpc85xx		Files specific to Freescale MPC85xx CPUs
@@ -413,22 +414,11 @@ The following options need to be configured:
 		See Freescale App Note 4493 for more information about
 		this erratum.

-		CONFIG_A003399_NOR_WORKAROUND
-		Enables a workaround for IFC erratum A003399. It is only
-		requred during NOR boot.
-
 		CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY

 		This is the value to write into CCSR offset 0x18600
 		according to the A004510 workaround.

-		CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
-		This value denotes start offset of M2 memory
-		which is directly connected to the DSP core.
-
-		CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
-		This value denotes start offset of DSP CCSR space.
-
 - Generic CPU options:
 		CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN

@@ -495,24 +485,6 @@ The following options need to be configured:
 		Thumb2 this flag will result in Thumb2 code generated by
 		GCC.

-		CONFIG_ARM_ERRATA_716044
-		CONFIG_ARM_ERRATA_742230
-		CONFIG_ARM_ERRATA_743622
-		CONFIG_ARM_ERRATA_751472
-
-		If set, the workarounds for these ARM errata are applied early
-		during U-Boot startup. Note that these options force the
-		workarounds to be applied; no CPU-type/version detection
-		exists, unlike the similar options in the Linux kernel. Do not
-		set these options unless they apply!
-
- CPU timer options:
-		CONFIG_SYS_HZ
-
-		The frequency of the timer returned by get_timer().
-		get_timer() must operate in milliseconds and this CONFIG
-		option must be set to 1000.
-
 - Linux Kernel Interface:
 		CONFIG_CLOCKS_IN_MHZ

@@ -644,6 +616,14 @@ The following options need to be configured:
 		boot loader that has already initialized the UART.  Define this
 		variable to flush the UART at init time.

+		CONFIG_SYS_NS16550_BROKEN_TEMT
+
+		16550 UART set the Transmitter Empty (TEMT) Bit when all output
+		has finished and the transmitter is totally empty. U-Boot waits
+		for this bit to be set to initialize the serial console. On some
+		broken platforms this bit is not set in SPL making U-Boot to
+		hang while waiting for TEMT. Define this option to avoid it.
+

 - Console Interface:
 		Depending on board, define exactly one serial port
@@ -854,7 +834,6 @@ The following options need to be configured:
 		CONFIG_CMD_FDOS		* Dos diskette Support
 		CONFIG_CMD_FLASH	  flinfo, erase, protect
 		CONFIG_CMD_FPGA		  FPGA device initialization support
-		CONFIG_CMD_FUSE		* Device fuse support
 		CONFIG_CMD_GETTIME	* Get time since boot
 		CONFIG_CMD_GO		* the 'go' command (exec code)
 		CONFIG_CMD_GREPENV	* search environment
@@ -863,8 +842,7 @@ The following options need to be configured:
 		CONFIG_CMD_I2C		* I2C serial bus support
 		CONFIG_CMD_IDE		* IDE harddisk support
 		CONFIG_CMD_IMI		  iminfo
-		CONFIG_CMD_IMLS		  List all images found in NOR flash
-		CONFIG_CMD_IMLS_NAND	* List all images found in NAND flash
+		CONFIG_CMD_IMLS		  List all found images
 		CONFIG_CMD_IMMAP	* IMMR dump support
 		CONFIG_CMD_IMPORTENV	* import an environment
 		CONFIG_CMD_INI		* import data from an ini file into the env
@@ -872,24 +850,22 @@ The following options need to be configured:
 		CONFIG_CMD_ITEST	  Integer/string test of 2 values
 		CONFIG_CMD_JFFS2	* JFFS2 Support
 		CONFIG_CMD_KGDB		* kgdb
-		CONFIG_CMD_LDRINFO	* ldrinfo (display Blackfin loader)
+		CONFIG_CMD_LDRINFO	  ldrinfo (display Blackfin loader)
 		CONFIG_CMD_LINK_LOCAL	* link-local IP address auto-configuration
 					  (169.254.*.*)
 		CONFIG_CMD_LOADB	  loadb
 		CONFIG_CMD_LOADS	  loads
-		CONFIG_CMD_MD5SUM	* print md5 message digest
+		CONFIG_CMD_MD5SUM	  print md5 message digest
 					  (requires CONFIG_CMD_MEMORY and CONFIG_MD5)
 		CONFIG_CMD_MEMINFO	* Display detailed memory information
 		CONFIG_CMD_MEMORY	  md, mm, nm, mw, cp, cmp, crc, base,
-					  loop, loopw
-		CONFIG_CMD_MEMTEST	* mtest
+					  loop, loopw, mtest
 		CONFIG_CMD_MISC		  Misc functions like sleep etc
 		CONFIG_CMD_MMC		* MMC memory mapped support
 		CONFIG_CMD_MII		* MII utility commands
 		CONFIG_CMD_MTDPARTS	* MTD partition support
 		CONFIG_CMD_NAND		* NAND support
 		CONFIG_CMD_NET		  bootp, tftpboot, rarpboot
-		CONFIG_CMD_NFS		  NFS support
 		CONFIG_CMD_PCA953X	* PCA953x I2C gpio commands
 		CONFIG_CMD_PCA953X_INFO * PCA953x I2C gpio info command
 		CONFIG_CMD_PCI		* pciinfo
@@ -900,7 +876,6 @@ The following options need to be configured:
 		CONFIG_CMD_READ		* Read raw data from partition
 		CONFIG_CMD_REGINFO	* Register dump
 		CONFIG_CMD_RUN		  run command in env variable
-		CONFIG_CMD_SANDBOX	* sb command to access sandbox features
 		CONFIG_CMD_SAVES	* save S record dump
 		CONFIG_CMD_SCSI		* SCSI Support
 		CONFIG_CMD_SDRAM	* print SDRAM configuration information
@@ -908,9 +883,8 @@ The following options need to be configured:
 		CONFIG_CMD_SETGETDCR	  Support for DCR Register access
 					  (4xx only)
 		CONFIG_CMD_SF		* Read/write/erase SPI NOR flash
-		CONFIG_CMD_SHA1SUM	* print sha1 memory digest
+		CONFIG_CMD_SHA1SUM	  print sha1 memory digest
 					  (requires CONFIG_CMD_MEMORY)
-		CONFIG_CMD_SOFTSWITCH	* Soft switch setting command for BF60x
 		CONFIG_CMD_SOURCE	  "source" command Support
 		CONFIG_CMD_SPI		* SPI serial bus support
 		CONFIG_CMD_TFTPSRV	* TFTP transfer in server mode
@@ -920,7 +894,6 @@ The following options need to be configured:
 		CONFIG_CMD_USB		* USB support
 		CONFIG_CMD_CDP		* Cisco Discover Protocol support
 		CONFIG_CMD_MFSL		* Microblaze FSL support
-		CONFIG_CMD_XIMG		  Load part of Multi Image


 		EXAMPLE: If you want all functions except of network
@@ -944,13 +917,6 @@ The following options need to be configured:

 		XXX - this list needs to get updated!

- Regular expression support:
-		CONFIG_REGEX
-                If this variable is defined, U-Boot is linked against
-                the SLRE (Super Light Regular Expression) library,
-                which adds regex support to some commands, as for
-                example "env grep" and "setexpr".
-
 - Device tree:
 		CONFIG_OF_CONTROL
 		If this variable is defined, U-Boot will use a device tree
@@ -1222,26 +1188,7 @@ The following options need to be configured:
 			If this option is set, the driver enables cache flush.

 - TPM Support:
-		CONFIG_TPM
-		Support TPM devices.
-
-		CONFIG_TPM_TIS_I2C
-		Support for i2c bus TPM devices. Only one device
-		per system is supported at this time.
-
-			CONFIG_TPM_TIS_I2C_BUS_NUMBER
-			Define the the i2c bus number for the TPM device
-
-			CONFIG_TPM_TIS_I2C_SLAVE_ADDRESS
-			Define the TPM's address on the i2c bus
-
-			CONFIG_TPM_TIS_I2C_BURST_LIMITATION
-			Define the burst count bytes upper limit
-
-		CONFIG_TPM_ATMEL_TWI
-		Support for Atmel TWI TPM device. Requires I2C support.
-
-		CONFIG_TPM_TIS_LPC
+		CONFIG_GENERIC_LPC_TPM
 		Support for generic parallel port TPM devices. Only one device
 		per system is supported at this time.

@@ -1250,20 +1197,6 @@ The following options need to be configured:
 			to. Contemporary x86 systems usually map it at
 			0xfed40000.

-		CONFIG_CMD_TPM
-		Add tpm monitor functions.
-		Requires CONFIG_TPM. If CONFIG_TPM_AUTH_SESSIONS is set, also
-		provides monitor access to authorized functions.
-
-		CONFIG_TPM
-		Define this to enable the TPM support library which provides
-		functional interfaces to some TPM commands.
-		Requires support for a TPM device.
-
-		CONFIG_TPM_AUTH_SESSIONS
-		Define this to enable authorized functions in the TPM library.
-		Requires CONFIG_TPM and CONFIG_SHA1.
-
 - USB Support:
 		At the moment only the UHCI host controller is
 		supported (PIP405, MIP405, MPC5200); define
@@ -1291,9 +1224,6 @@ The following options need to be configured:
 		CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
 		txfilltuning field in the EHCI controller on reset.

-		CONFIG_USB_HUB_MIN_POWER_ON_DELAY defines the minimum
-		interval for usb hub power-on delay.(minimum 100msec)
-
 - USB Device:
 		Define the below if you wish to use the USB console.
 		Once firmware is rebuilt from a serial console issue the
@@ -1393,35 +1323,6 @@ The following options need to be configured:
 			CONFIG_SH_MMCIF_CLK
 			Define the clock frequency for MMCIF

- USB Device Firmware Update (DFU) class support:
-		CONFIG_DFU_FUNCTION
-		This enables the USB portion of the DFU USB class
-
-		CONFIG_CMD_DFU
-		This enables the command "dfu" which is used to have
-		U-Boot create a DFU class device via USB.  This command
-		requires that the "dfu_alt_info" environment variable be
-		set and define the alt settings to expose to the host.
-
-		CONFIG_DFU_MMC
-		This enables support for exposing (e)MMC devices via DFU.
-
-		CONFIG_DFU_NAND
-		This enables support for exposing NAND devices via DFU.
-
-		CONFIG_SYS_DFU_DATA_BUF_SIZE
-		Dfu transfer uses a buffer before writing data to the
-		raw storage device. Make the size (in bytes) of this buffer
-		configurable. The size of this buffer is also configurable
-		through the "dfu_bufsiz" environment variable.
-
-		CONFIG_SYS_DFU_MAX_FILE_SIZE
-		When updating files rather than the raw storage device,
-		we use a static buffer to copy the file into and then write
-		the buffer once we've been given the whole file.  Define
-		this to the maximum filesize (in bytes) for the buffer.
-		Default is 4 MiB if undefined.
-
 - Journaling Flash filesystem support:
 		CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE,
 		CONFIG_JFFS2_NAND_DEV
@@ -1468,11 +1369,6 @@ CBFS (Coreboot Filesystem) support
 		Export function i8042_kbd_init, i8042_tstc and i8042_getc
 		for cfb_console. Supports cursor blinking.

-		CONFIG_CROS_EC_KEYB
-		Enables a Chrome OS keyboard using the CROS_EC interface.
-		This uses CROS_EC to communicate with a second microcontroller
-		which provides key scans on request.
-
 - Video support:
 		CONFIG_VIDEO

@@ -1634,17 +1530,6 @@ CBFS (Coreboot Filesystem) support
 		allows for a "silent" boot where a splash screen is
 		loaded very quickly after power-on.

-		CONFIG_SPLASHIMAGE_GUARD
-
-		If this option is set, then U-Boot will prevent the environment
-		variable "splashimage" from being set to a problematic address
-		(see README.displaying-bmps and README.arm-unaligned-accesses).
-		This option is useful for targets where, due to alignment
-		restrictions, an improperly aligned BMP image will cause a data
-		abort. If you think you will not have problems with unaligned
-		accesses (for example because your toolchain prevents them)
-		there is no need to set this option.
-
 		CONFIG_SPLASH_SCREEN_ALIGN

 		If this option is set the splash image can be freely positioned
@@ -2020,15 +1905,15 @@ CBFS (Coreboot Filesystem) support

 		I2C_READ

-		Code that returns true if the I2C data line is high,
-		false if it is low.
+		Code that returns TRUE if the I2C data line is high,
+		FALSE if it is low.

 		eg: #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)

 		I2C_SDA(bit)

-		If <bit> is true, sets the I2C data line high. If it
-		is false, it clears it (low).
+		If <bit> is TRUE, sets the I2C data line high. If it
+		is FALSE, it clears it (low).

 		eg: #define I2C_SDA(bit) \
 			if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
@@ -2036,8 +1921,8 @@ CBFS (Coreboot Filesystem) support

 		I2C_SCL(bit)

-		If <bit> is true, sets the I2C clock line high. If it
-		is false, it clears it (low).
+		If <bit> is TRUE, sets the I2C clock line high. If it
+		is FALSE, it clears it (low).

 		eg: #define I2C_SCL(bit) \
 			if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
@@ -2542,11 +2427,6 @@ CBFS (Coreboot Filesystem) support
 		Define this option to include a destructive SPI flash
 		test ('sf test').

-		CONFIG_SPI_FLASH_BAR		Ban/Extended Addr Reg
-
-		Define this option to use the Bank addr/Extended addr
-		support on SPI flashes which has size > 16Mbytes.
-
 - SystemACE Support:
 		CONFIG_SYSTEMACE

@@ -2598,16 +2478,6 @@ CBFS (Coreboot Filesystem) support
 		Note: There is also a sha1sum command, which should perhaps
 		be deprecated in favour of 'hash sha1'.

- Signing support:
-		CONFIG_RSA
-
-		This enables the RSA algorithm used for FIT image verification
-		in U-Boot. See doc/uImage/signature for more information.
-
-		The signing part is build into mkimage regardless of this
-		option.
-
-
 - Show boot progress:
 		CONFIG_SHOW_BOOT_PROGRESS

@@ -2832,11 +2702,6 @@ FIT uImage format:
 		most specific compatibility entry of U-Boot's fdt's root node.
 		The order of entries in the configuration's fdt is ignored.

-		CONFIG_FIT_SIGNATURE
-		This option enables signature verification of FIT uImages,
-		using a hash signed and verified using RSA. See
-		doc/uImage.FIT/signature.txt for more details.
-
 - Standalone program support:
 		CONFIG_STANDALONE_LOAD_ADDR

@@ -2878,32 +2743,6 @@ FIT uImage format:
 		Adds the MTD partitioning infrastructure from the Linux
 		kernel. Needed for UBI support.

- UBI support
-		CONFIG_CMD_UBI
-
-		Adds commands for interacting with MTD partitions formatted
-		with the UBI flash translation layer
-
-		Requires also defining CONFIG_RBTREE
-
-		CONFIG_UBI_SILENCE_MSG
-
-		Make the verbose messages from UBI stop printing.  This leaves
-		warnings and errors enabled.
-
- UBIFS support
-		CONFIG_CMD_UBIFS
-
-		Adds commands for interacting with UBI volumes formatted as
-		UBIFS.  UBIFS is read-only in u-boot.
-
-		Requires UBI support as well as CONFIG_LZO
-
-		CONFIG_UBIFS_SILENCE_MSG
-
-		Make the verbose messages from UBIFS stop printing.  This leaves
-		warnings and errors enabled.
-
 - SPL framework
 		CONFIG_SPL
 		Enable building of SPL globally.
@@ -2911,18 +2750,8 @@ FIT uImage format:
 		CONFIG_SPL_LDSCRIPT
 		LDSCRIPT for linking the SPL binary.

-		CONFIG_SPL_MAX_FOOTPRINT
-		Maximum size in memory allocated to the SPL, BSS included.
-		When defined, the linker checks that the actual memory
-		used by SPL from _start to __bss_end does not exceed it.
-		CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE
-		must not be both defined at the same time.
-
 		CONFIG_SPL_MAX_SIZE
-		Maximum size of the SPL image (text, data, rodata, and
-		linker lists sections), BSS excluded.
-		When defined, the linker checks that the actual size does
-		not exceed it.
+		Maximum binary size (text, data and rodata) of the SPL binary.

 		CONFIG_SPL_TEXT_BASE
 		TEXT_BASE for linking the SPL binary.
@@ -2935,11 +2764,7 @@ FIT uImage format:
 		Link address for the BSS within the SPL binary.

 		CONFIG_SPL_BSS_MAX_SIZE
-		Maximum size in memory allocated to the SPL BSS.
-		When defined, the linker checks that the actual memory used
-		by SPL from __bss_start to __bss_end does not exceed it.
-		CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE
-		must not be both defined at the same time.
+		Maximum binary size of the BSS section of the SPL binary.

 		CONFIG_SPL_STACK
 		Adress of the start of the stack SPL will use
@@ -2988,36 +2813,12 @@ FIT uImage format:
 		Address, size and partition on the MMC to load U-Boot from
 		when the MMC is being used in raw mode.

-		CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
-		Sector to load kernel uImage from when MMC is being
-		used in raw mode (for Falcon mode)
-
-		CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR,
-		CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
-		Sector and number of sectors to load kernel argument
-		parameters from when MMC is being used in raw mode
-		(for falcon mode)
-
 		CONFIG_SPL_FAT_SUPPORT
 		Support for fs/fat/libfat.o in SPL binary

 		CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME
 		Filename to read to load U-Boot when reading from FAT

-		CONFIG_SPL_FAT_LOAD_KERNEL_NAME
-		Filename to read to load kernel uImage when reading
-		from FAT (for Falcon mode)
-
-		CONFIG_SPL_FAT_LOAD_ARGS_NAME
-		Filename to read to load kernel argument parameters
-		when reading from FAT (for Falcon mode)
-
-		CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
-		Set this for NAND SPL on PPC mpc83xx targets, so that
-		start.S waits for the rest of the SPL to load before
-		continuing (the hardware starts execution after just
-		loading the first page rather than the full 4K).
-
 		CONFIG_SPL_NAND_BASE
 		Include nand_base.c in the SPL.  Requires
 		CONFIG_SPL_NAND_DRIVERS.
@@ -3075,32 +2876,11 @@ FIT uImage format:
 		CONFIG_SPL_LIBGENERIC_SUPPORT
 		Support for lib/libgeneric.o in SPL binary

-		CONFIG_SPL_ENV_SUPPORT
-		Support for the environment operating in SPL binary
-
-		CONFIG_SPL_NET_SUPPORT
-		Support for the net/libnet.o in SPL binary.
-		It conflicts with SPL env from storage medium specified by
-		CONFIG_ENV_IS_xxx but CONFIG_ENV_IS_NOWHERE
-
-		CONFIG_SPL_PAD_TO
-		Image offset to which the SPL should be padded before appending
-		the SPL payload. By default, this is defined as
-		CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
-		CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
-		payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
-
 		CONFIG_SPL_TARGET
 		Final target image containing SPL and payload.  Some SPLs
 		use an arch-specific makefile fragment instead, for
 		example if more than one image needs to be produced.

-		CONFIG_FIT_SPL_PRINT
-		Printing information about a FIT image adds quite a bit of
-		code to SPL. So this is normally disabled in SPL. Use this
-		option to re-enable it. This will affect the output of the
-		bootm command when booting a FIT image.
-
 Modem Support:
 --------------

@@ -3360,15 +3140,6 @@ Configuration Settings:
 		digits and dots.  Recommended value: 45 (9..1) for 80
 		column displays, 15 (3..1) for 40 column displays.

- CONFIG_FLASH_VERIFY
-		If defined, the content of the flash (destination) is compared
-		against the source after the write operation. An error message
-		will be printed when the contents are not identical.
-		Please note that this option is useless in nearly all cases,
-		since such flash programming errors usually are detected earlier
-		while unprotecting/erasing/programming. Please only enable
-		this option if you really know what you are doing.
-
 - CONFIG_SYS_RX_ETH_BUFFER:
 		Defines the number of Ethernet receive buffers. On some
 		Ethernet controllers it is recommended to set this value
@@ -3428,27 +3199,6 @@ Configuration Settings:
 	If defined, don't allow the -f switch to env set override variable
 	access flags.

- CONFIG_SYS_GENERIC_BOARD
-	This selects the architecture-generic board system instead of the
-	architecture-specific board files. It is intended to move boards
-	to this new framework over time. Defining this will disable the
-	arch/foo/lib/board.c file and use common/board_f.c and
-	common/board_r.c instead. To use this option your architecture
-	must support it (i.e. must define __HAVE_ARCH_GENERIC_BOARD in
-	its config.mk file). If you find problems enabling this option on
-	your board please report the problem and send patches!
-
- CONFIG_SYS_SYM_OFFSETS
-	This is set by architectures that use offsets for link symbols
-	instead of absolute values. So bss_start is obtained using an
-	offset _bss_start_ofs from CONFIG_SYS_TEXT_BASE, rather than
-	directly. You should not need to touch this setting.
-
- CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only)
-	This is set by OMAP boards for the max time that reset should
-	be asserted. See doc/README.omap-reset-time for details on how
-	the value can be calulated on a given board.
-
 The following definitions that deal with the placement and management
 of environment data (variable area); in general, we support the
 following configurations:
@@ -3682,84 +3432,6 @@ but it can not erase, write this NOR flash by SRIO or PCIE interface.
 	environment. If redundant environment is used, it will be copied to
 	CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE.

- CONFIG_ENV_IS_IN_UBI:
-
-	Define this if you have an UBI volume that you want to use for the
-	environment.  This has the benefit of wear-leveling the environment
-	accesses, which is important on NAND.
-
-	- CONFIG_ENV_UBI_PART:
-
-	  Define this to a string that is the mtd partition containing the UBI.
-
-	- CONFIG_ENV_UBI_VOLUME:
-
-	  Define this to the name of the volume that you want to store the
-	  environment in.
-
-	- CONFIG_ENV_UBI_VOLUME_REDUND:
-
-	  Define this to the name of another volume to store a second copy of
-	  the environment in.  This will enable redundant environments in UBI.
-	  It is assumed that both volumes are in the same MTD partition.
-
-	- CONFIG_UBI_SILENCE_MSG
-	- CONFIG_UBIFS_SILENCE_MSG
-
-	  You will probably want to define these to avoid a really noisy system
-	  when storing the env in UBI.
-
- CONFIG_ENV_IS_IN_MMC:
-
-	Define this if you have an MMC device which you want to use for the
-	environment.
-
-	- CONFIG_SYS_MMC_ENV_DEV:
-
-	  Specifies which MMC device the environment is stored in.
-
-	- CONFIG_SYS_MMC_ENV_PART (optional):
-
-	  Specifies which MMC partition the environment is stored in. If not
-	  set, defaults to partition 0, the user area. Common values might be
-	  1 (first MMC boot partition), 2 (second MMC boot partition).
-
-	- CONFIG_ENV_OFFSET:
-	- CONFIG_ENV_SIZE:
-
-	  These two #defines specify the offset and size of the environment
-	  area within the specified MMC device.
-
-	  If offset is positive (the usual case), it is treated as relative to
-	  the start of the MMC partition. If offset is negative, it is treated
-	  as relative to the end of the MMC partition. This can be useful if
-	  your board may be fitted with different MMC devices, which have
-	  different sizes for the MMC partitions, and you always want the
-	  environment placed at the very end of the partition, to leave the
-	  maximum possible space before it, to store other data.
-
-	  These two values are in units of bytes, but must be aligned to an
-	  MMC sector boundary.
-
-	- CONFIG_ENV_OFFSET_REDUND (optional):
-
-	  Specifies a second storage area, of CONFIG_ENV_SIZE size, used to
-	  hold a redundant copy of the environment data. This provides a
-	  valid backup copy in case the other copy is corrupted, e.g. due
-	  to a power failure during a "saveenv" operation.
-
-	  This value may also be positive or negative; this is handled in the
-	  same way as CONFIG_ENV_OFFSET.
-
-	  This value is also in units of bytes, but must also be aligned to
-	  an MMC sector boundary.
-
-	- CONFIG_ENV_SIZE_REDUND (optional):
-
-	  This value need not be set, even when CONFIG_ENV_OFFSET_REDUND is
-	  set. If this value is set, it must be set to the same value as
-	  CONFIG_ENV_SIZE.
-
 - CONFIG_SYS_SPI_INIT_OFFSET

 	Defines offset to the initial SPI buffer area in DPRAM. The
@@ -4013,9 +3685,6 @@ Low Level (hardware related) configuration options:
 		a second time.	Useful for platforms that are pre-booted
 		by coreboot or similar.

- CONFIG_PCI_INDIRECT_BRIDGE:
-		Enable support for indirect PCI bridges.
-
 - CONFIG_SYS_SRIO:
 		Chip has SRIO or not

@@ -4025,9 +3694,6 @@ Low Level (hardware related) configuration options:
 - CONFIG_SRIO2:
 		Board has SRIO 2 port available

- CONFIG_SRIO_PCIE_BOOT_MASTER
-		Board can support master function for Boot from SRIO and PCIE
-
 - CONFIG_SYS_SRIOn_MEM_VIRT:
 		Virtual Address of SRIO port 'n' memory region

@@ -4037,13 +3703,9 @@ Low Level (hardware related) configuration options:
 - CONFIG_SYS_SRIOn_MEM_SIZE:
 		Size of SRIO port 'n' memory region

- CONFIG_SYS_NAND_BUSWIDTH_16BIT
-		Defined to tell the NAND controller that the NAND chip is using
-		a 16 bit bus.
-		Not all NAND drivers use this symbol.
-		Example of drivers that use it:
-		- drivers/mtd/nand/ndfc.c
-		- drivers/mtd/nand/mxc_nand.c
+- CONFIG_SYS_NDFC_16
+		Defined to tell the NDFC that the NAND chip is using a
+		16 bit bus.

 - CONFIG_SYS_NDFC_EBC0_CFG
 		Sets the EBC0_CFG register for the NDFC. If not defined
@@ -4138,34 +3800,21 @@ Low Level (hardware related) configuration options:
 		that is executed before the actual U-Boot. E.g. when
 		compiling a NAND SPL.

- CONFIG_SYS_MPC85XX_NO_RESETVEC
-		Only for 85xx systems. If this variable is specified, the section
-		.resetvec is not kept and the section .bootpg is placed in the
-		previous 4k of the .text section.
-
- CONFIG_ARCH_MAP_SYSMEM
-		Generally U-Boot (and in particular the md command) uses
-		effective address. It is therefore not necessary to regard
-		U-Boot address as virtual addresses that need to be translated
-		to physical addresses. However, sandbox requires this, since
-		it maintains its own little RAM buffer which contains all
-		addressable memory. This option causes some memory accesses
-		to be mapped through map_sysmem() / unmap_sysmem().
-
 - CONFIG_USE_ARCH_MEMCPY
  CONFIG_USE_ARCH_MEMSET
 		If these options are used a optimized version of memcpy/memset will
 		be used if available. These functions may be faster under some
 		conditions but may increase the binary size.

- CONFIG_X86_RESET_VECTOR
-		If defined, the x86 reset vector code is included. This is not
-		needed when U-Boot is running from Coreboot.
+- CONFIG_X86_NO_RESET_VECTOR
+		If defined, the x86 reset vector code is excluded. You will need
+		to do this when U-Boot is running from Coreboot.

- CONFIG_SYS_MPUCLK
-		Defines the MPU clock speed (in MHz).
+- CONFIG_X86_NO_REAL_MODE
+		If defined, x86 real mode code is omitted. This assumes a
+		32-bit environment where such code is not needed. You will
+		need to do this when U-Boot is running from Coreboot.

-		NOTE : currently only supported on AM335x platforms.

 Freescale QE/FMAN Firmware Support:
 -----------------------------------
@@ -5228,7 +4877,7 @@ On some platforms, it's possible to boot Linux zImage. This is done
 using the "bootz" command. The syntax of "bootz" command is the same
 as the syntax of "bootm" command.

-Note, defining the CONFIG_SUPPORT_RAW_INITRD allows user to supply
+Note, defining the CONFIG_SUPPORT_INITRD_RAW allows user to supply
 kernel with raw initrd images. The syntax is slightly different, the
 address of the initrd must be augmented by it's size, in the following
 format: "<initrd addres>:<initrd size>".
--- a/api/api_display.c
+++ b/api/api_display.c
@@ -45,8 +45,8 @@ int display_get_info(int type, struct display_info *di)
 	case DISPLAY_TYPE_LCD:
 		di->pixel_width  = panel_info.vl_col;
 		di->pixel_height = panel_info.vl_row;
-		di->screen_rows = lcd_get_screen_rows();
-		di->screen_cols = lcd_get_screen_columns();
+		di->screen_rows = CONSOLE_ROWS;
+		di->screen_cols = CONSOLE_COLS;
 		break;
 #endif
 	}
--- a/api/api_platform-powerpc.c
+++ b/api/api_platform-powerpc.c
@@ -55,6 +55,8 @@ int platform_sys_info(struct sys_info *si)
 #define bi_bar	bi_mbar_base
 #elif defined(CONFIG_MPC83xx)
 #define bi_bar	bi_immrbar
+#elif defined(CONFIG_MPC8220)
+#define bi_bar	bi_mbar_base
 #endif

 #if defined(bi_bar)
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -24,19 +24,13 @@
 CROSS_COMPILE ?= arm-linux-

 ifndef CONFIG_STANDALONE_LOAD_ADDR
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),)
+ifeq ($(SOC),omap3)
 CONFIG_STANDALONE_LOAD_ADDR = 0x80300000
 else
 CONFIG_STANDALONE_LOAD_ADDR = 0xc100000
 endif
 endif

-LDFLAGS_FINAL += --gc-sections
-PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
-
-# Support generic board on ARM
-__HAVE_ARCH_GENERIC_BOARD := y
-
 PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__

 # Choose between ARM/Thumb instruction sets
@@ -90,7 +84,9 @@ endif
 endif

 # needed for relocation
+ifndef CONFIG_NAND_SPL
 LDFLAGS_u-boot += -pie
+endif

 #
 # FIXME: binutils versions < 2.22 have a bug in the assembler where
@@ -109,8 +105,3 @@ ifeq ($(GAS_BUG_12532),y)
 PLATFORM_RELFLAGS += -fno-optimize-sibling-calls
 endif
 endif
-
-# check that only R_ARM_RELATIVE relocations are generated
-ifneq ($(CONFIG_SPL_BUILD),y)
-ALL-y	+= checkarmreloc
-endif
--- a/arch/arm/cpu/arm1136/config.mk
+++ b/arch/arm/cpu/arm1136/config.mk
@@ -31,13 +31,6 @@ PLATFORM_CPPFLAGS += -march=armv5
 # =========================================================================
 PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
 PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
-
-ifneq ($(CONFIG_IMX_CONFIG),)
-ifdef CONFIG_SPL
 ifdef CONFIG_SPL_BUILD
 ALL-y	+= $(OBJTREE)/SPL
 endif
-else
-ALL-y	+= $(obj)u-boot.imx
-endif
-endif
--- a/arch/arm/cpu/arm1136/mx31/timer.c
+++ b/arch/arm/cpu/arm1136/mx31/timer.c
@@ -115,13 +115,13 @@ unsigned long long get_ticks(void)
 {
 	ulong now = GPTCNT; /* current tick value */

-	if (now >= gd->arch.lastinc)	/* normal mode (non roll) */
+	if (now >= gd->lastinc)	/* normal mode (non roll) */
 		/* move stamp forward with absolut diff ticks */
-		gd->arch.tbl += (now - gd->arch.lastinc);
+		gd->tbl += (now - gd->lastinc);
 	else			/* we have rollover of incrementer */
-		gd->arch.tbl += (0xFFFFFFFF - gd->arch.lastinc) + now;
-	gd->arch.lastinc = now;
-	return gd->arch.tbl;
+		gd->tbl += (0xFFFFFFFF - gd->lastinc) + now;
+	gd->lastinc = now;
+	return gd->tbl;
 }

 ulong get_timer_masked(void)
--- a/arch/arm/cpu/arm1136/mx35/Makefile
+++ b/arch/arm/cpu/arm1136/mx35/Makefile
@@ -29,6 +29,7 @@ LIB	= $(obj)lib$(SOC).o

 COBJS	+= generic.o
 COBJS	+= timer.o
+COBJS	+= iomux.o
 COBJS	+= mx35_sdram.o

 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
--- a/arch/arm/cpu/arm1136/mx35/generic.c
+++ b/arch/arm/cpu/arm1136/mx35/generic.c
@@ -478,11 +478,11 @@ int get_clocks(void)
 {
 #ifdef CONFIG_FSL_ESDHC
 #if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
-	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 #elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
-	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 #else
-	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
 #endif
 #endif
 	return 0;
@@ -519,7 +519,7 @@ u32 spl_boot_device(void)
 		case RCSR_MEM_TYPE_NOR:
 			return BOOT_DEVICE_NOR;
 		case RCSR_MEM_TYPE_ONENAND:
-			return BOOT_DEVICE_ONENAND;
+			return BOOT_DEVICE_ONE_NAND;
 		default:
 			return BOOT_DEVICE_NONE;
 		}
--- a/arch/arm/cpu/arm1136/mx35/iomux.c
+++ b/arch/arm/cpu/arm1136/mx35/iomux.c
@@ -0,0 +1,114 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx35_pins.h>
+#include <asm/arch/iomux.h>
+
+/*
+ * IOMUX register (base) addresses
+ */
+enum iomux_reg_addr {
+	IOMUXGPR = IOMUXC_BASE_ADDR,			/* General purpose */
+	IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR + 4,		/* MUX control */
+	IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + 0x324,	/* last MUX control */
+	IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + 0x328,	/* Pad control */
+	IOMUXSW_PAD_END = IOMUXC_BASE_ADDR + 0x794,	/* last Pad control */
+	IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + 0x7AC,	/* input select */
+	IOMUXSW_INPUT_END = IOMUXC_BASE_ADDR + 0x9F4,	/* last input select */
+};
+
+#define MUX_PIN_NUM_MAX		\
+		(((IOMUXSW_PAD_END - IOMUXSW_PAD_CTL) >> 2) + 1)
+#define MUX_INPUT_NUM_MUX	\
+		(((IOMUXSW_INPUT_END - IOMUXSW_INPUT_CTL) >> 2) + 1)
+
+/*
+ * Request ownership for an IO pin. This function has to be the first one
+ * being called before that pin is used.
+ */
+void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
+{
+	u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
+
+	if (mux_reg != NON_MUX_I) {
+		mux_reg += IOMUXGPR;
+		writel(cfg, mux_reg);
+	}
+}
+
+/*
+ * Release ownership for an IO pin
+ */
+void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
+{
+}
+
+/*
+ * This function configures the pad value for a IOMUX pin.
+ *
+ * @param  pin     a pin number as defined in iomux_pin_name_t
+ * @param  config  the ORed value of elements defined in iomux_pad_config_t
+ */
+void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
+{
+	u32 pad_reg = IOMUXGPR + PIN_TO_IOMUX_PAD(pin);
+
+	writel(config, pad_reg);
+}
+
+/*
+ * This function enables/disables the general purpose function for a particular
+ * signal.
+ *
+ * @param  gp   one signal as defined in iomux_gp_func_t
+ * @param  en   enable/disable
+ */
+void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en)
+{
+	u32 l;
+
+	l = readl(IOMUXGPR);
+	if (en)
+		l |= gp;
+	else
+		l &= ~gp;
+
+	writel(l, IOMUXGPR);
+}
+
+/*
+ * This function configures input path.
+ *
+ * @param input index of input select register as defined in
+ *			iomux_input_select_t
+ * @param config the binary value of elements defined in
+ *			iomux_input_config_t
+ */
+void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
+{
+	u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
+
+	writel(config, reg);
+}
--- a/arch/arm/cpu/arm1136/mx35/timer.c
+++ b/arch/arm/cpu/arm1136/mx35/timer.c
@@ -32,8 +32,8 @@

 DECLARE_GLOBAL_DATA_PTR;

-#define timestamp	(gd->arch.tbl)
-#define lastinc		(gd->arch.lastinc)
+#define timestamp	(gd->tbl)
+#define lastinc		(gd->lastinc)

 /* General purpose timers bitfields */
 #define GPTCR_SWR       (1<<15)	/* Software reset */
--- a/arch/arm/cpu/arm1136/omap24xx/timer.c
+++ b/arch/arm/cpu/arm1136/omap24xx/timer.c
@@ -31,16 +31,13 @@
 */

 #include <common.h>
-#include <asm/io.h>
 #include <asm/arch/bits.h>
 #include <asm/arch/omap2420.h>

-#define TIMER_CLOCK	(CONFIG_SYS_CLK_FREQ / (2 << CONFIG_SYS_PTV))
 #define TIMER_LOAD_VAL 0

 /* macro to read the 32 bit timer */
-#define READ_TIMER	readl(CONFIG_SYS_TIMERBASE+TCRR) \
-			/ (TIMER_CLOCK / CONFIG_SYS_HZ)
+#define READ_TIMER (*((volatile ulong *)(CONFIG_SYS_TIMERBASE+TCRR)))

 DECLARE_GLOBAL_DATA_PTR;

@@ -54,8 +51,8 @@ int timer_init (void)
 	*((int32_t *) (CONFIG_SYS_TIMERBASE + TCLR)) = val;	/* start timer */

 	/* reset time */
-	gd->arch.lastinc = READ_TIMER;	/* capture current incrementer value */
-	gd->arch.tbl = 0;		/* start "advancing" time stamp */
+	gd->lastinc = READ_TIMER;	/* capture current incrementer value */
+	gd->tbl = 0;			/* start "advancing" time stamp */

 	return(0);
 }
@@ -84,8 +81,8 @@ void __udelay (unsigned long usec)
 	tmp = get_timer (0);		/* get current timestamp */
 	if ((tmo + tmp + 1) < tmp) {	/* if setting this forward will roll */
 					/* time stamp, then reset time */
-		gd->arch.lastinc = READ_TIMER;	/* capture incrementer value */
-		gd->arch.tbl = 0;			/* start time stamp */
+		gd->lastinc = READ_TIMER;	/* capture incrementer value */
+		gd->tbl = 0;			/* start time stamp */
 	} else {
 		tmo	+= tmp;		/* else, set advancing stamp wake up time */
 	}
@@ -97,16 +94,12 @@ ulong get_timer_masked (void)
 {
 	ulong now = READ_TIMER;		/* current tick value */

-	if (now >= gd->arch.lastinc) {		/* normal mode (non roll) */
-		/* move stamp fordward with absoulte diff ticks */
-		gd->arch.tbl += (now - gd->arch.lastinc);
-	} else {
-		/* we have rollover of incrementer */
-		gd->arch.tbl += ((0xFFFFFFFF / (TIMER_CLOCK / CONFIG_SYS_HZ))
-				 - gd->arch.lastinc) + now;
-	}
-	gd->arch.lastinc = now;
-	return gd->arch.tbl;
+	if (now >= gd->lastinc)		/* normal mode (non roll) */
+		gd->tbl += (now - gd->lastinc); /* move stamp fordward with absoulte diff ticks */
+	else				/* we have rollover of incrementer */
+		gd->tbl += (0xFFFFFFFF - gd->lastinc) + now;
+	gd->lastinc = now;
+	return gd->tbl;
 }

 /* waits specified delay value and resets timestamp */
--- a/arch/arm/cpu/arm1136/start.S
+++ b/arch/arm/cpu/arm1136/start.S
@@ -88,11 +88,7 @@ _end_vect:

 .globl _TEXT_BASE
 _TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
 	.word	CONFIG_SYS_TEXT_BASE
-#endif

 /*
 * These are defined in the board-specific linker script.
@@ -104,9 +100,13 @@ _TEXT_BASE:
 _bss_start_ofs:
 	.word __bss_start - _start

+.global	_image_copy_end_ofs
+_image_copy_end_ofs:
+	.word 	__image_copy_end - _start
+
 .globl _bss_end_ofs
 _bss_end_ofs:
-	.word __bss_end - _start
+	.word __bss_end__ - _start

 .globl _end_ofs
 _end_ofs:
@@ -142,6 +142,24 @@ reset:
 	orr	r0,r0,#0xd3
 	msr	cpsr,r0

+#ifdef CONFIG_OMAP2420H4
+       /* Copy vectors to mask ROM indirect addr */
+	adr	r0, _start		/* r0 <- current position of code   */
+		add     r0, r0, #4				/* skip reset vector			*/
+	mov	r2, #64			/* r2 <- size to copy  */
+	add	r2, r0, r2		/* r2 <- source end address	    */
+	mov	r1, #SRAM_OFFSET0	  /* build vect addr */
+	mov	r3, #SRAM_OFFSET1
+	add	r1, r1, r3
+	mov	r3, #SRAM_OFFSET2
+	add	r1, r1, r3
+next:
+	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
+	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
+	cmp	r0, r2			/* until source end address [r2]    */
+	bne	next			/* loop until equal */
+	bl	cpy_clk_code		/* put dpll adjust code behind vectors */
+#endif
 	/* the mask ROM code should have PLL and others stable */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	bl  cpu_init_crit
@@ -151,6 +169,91 @@ reset:

 /*------------------------------------------------------------------------------*/

+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ */
+	.globl	relocate_code
+relocate_code:
+	mov	r4, r0	/* save addr_sp */
+	mov	r5, r1	/* save addr of gd */
+	mov	r6, r2	/* save addr of destination */
+
+	adr	r0, _start
+	cmp	r0, r6
+	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
+	beq	relocate_done		/* skip relocation */
+	mov	r1, r6			/* r1 <- scratch for copy_loop */
+	ldr	r3, _image_copy_end_ofs
+	add	r2, r0, r3		/* r2 <- source end address	    */
+
+copy_loop:
+	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
+	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
+
+#ifndef CONFIG_SPL_BUILD
+	/*
+	 * fix .rel.dyn relocations
+	 */
+	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
+	sub	r9, r6, r0		/* r9 <- relocation offset */
+	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
+	add	r10, r10, r0		/* r10 <- sym table in FLASH */
+	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
+	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
+	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
+	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
+fixloop:
+	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
+	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
+	ldr	r1, [r2, #4]
+	and	r7, r1, #0xff
+	cmp	r7, #23			/* relative fixup? */
+	beq	fixrel
+	cmp	r7, #2			/* absolute fixup? */
+	beq	fixabs
+	/* ignore unknown type of fixup */
+	b	fixnext
+fixabs:
+	/* absolute fix: set location to (offset) symbol value */
+	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
+	add	r1, r10, r1		/* r1 <- address of symbol in table */
+	ldr	r1, [r1, #4]		/* r1 <- symbol value */
+	add	r1, r1, r9		/* r1 <- relocated sym addr */
+	b	fixnext
+fixrel:
+	/* relative fix: increase location by offset */
+	ldr	r1, [r0]
+	add	r1, r1, r9
+fixnext:
+	str	r1, [r0]
+	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
+	cmp	r2, r3
+	blo	fixloop
+	bx	lr
+
+#endif
+
+relocate_done:
+
+	bx	lr
+
+#ifndef CONFIG_SPL_BUILD
+
+_rel_dyn_start_ofs:
+	.word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+	.word __rel_dyn_end - _start
+_dynsym_start_ofs:
+	.word __dynsym_start - _start
+
+#endif
+
 	.globl	c_runtime_cpu_setup
 c_runtime_cpu_setup:

@@ -289,9 +392,8 @@ cpu_init_crit:
 	str	r0, [r13]			@ save R0's value.
 	ldr	r0, IRQ_STACK_START_IN		@ get data regions start
 	str	lr, [r0]			@ save caller lr in position 0 of saved stack
-	mrs	lr, spsr			@ get the spsr
+	mrs	r0, spsr			@ get the spsr
 	str	lr, [r0, #4]			@ save spsr in position 1 of saved stack
-	ldr	lr, [r0]			@ restore lr
 	ldr	r0, [r13]			@ restore r0
 	add	r13, r13, #4			@ pop stack entry
 	.endm
--- a/arch/arm/cpu/arm1136/u-boot-spl.lds
+++ b/arch/arm/cpu/arm1136/u-boot-spl.lds
@@ -38,7 +38,7 @@ SECTIONS
 	.text      :
 	{
 	__start = .;
-	  arch/arm/cpu/arm1136/start.o	(.text*)
+	  arch/arm/cpu/arm1136/start.o	(.text)
 	  *(.text*)
 	} >.sram

@@ -57,6 +57,6 @@ SECTIONS
 		__bss_start = .;
 		*(.bss*)
 		. = ALIGN(4);
-		__bss_end = .;
+		__bss_end__ = .;
 	} >.sdram
 }
--- a/arch/arm/cpu/arm1176/bcm2835/Makefile
+++ b/arch/arm/cpu/arm1176/bcm2835/Makefile
@@ -17,7 +17,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(SOC).o

 SOBJS	:= lowlevel_init.o
-COBJS	:= init.o reset.o timer.o mbox.o
+COBJS	:= init.o reset.o timer.o

 SRCS	:= $(SOBJS:.o=.c) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
--- a/arch/arm/cpu/arm1176/bcm2835/mbox.c
+++ b/arch/arm/cpu/arm1176/bcm2835/mbox.c
@@ -1,164 +0,0 @@
-/*
- * (C) Copyright 2012 Stephen Warren
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mbox.h>
-
-#define TIMEOUT (100 * 1000) /* 100mS in uS */
-
-int bcm2835_mbox_call_raw(u32 chan, u32 send, u32 *recv)
-{
-	struct bcm2835_mbox_regs *regs =
-		(struct bcm2835_mbox_regs *)BCM2835_MBOX_PHYSADDR;
-	ulong endtime = get_timer(0) + TIMEOUT;
-	u32 val;
-
-	debug("time: %lu timeout: %lu\n", get_timer(0), endtime);
-
-	if (send & BCM2835_CHAN_MASK) {
-		printf("mbox: Illegal mbox data 0x%08x\n", send);
-		return -1;
-	}
-
-	/* Drain any stale responses */
-
-	for (;;) {
-		val = readl(&regs->status);
-		if (val & BCM2835_MBOX_STATUS_RD_EMPTY)
-			break;
-		if (get_timer(0) >= endtime) {
-			printf("mbox: Timeout draining stale responses\n");
-			return -1;
-		}
-		val = readl(&regs->read);
-	}
-
-	/* Wait for space to send */
-
-	for (;;) {
-		val = readl(&regs->status);
-		if (!(val & BCM2835_MBOX_STATUS_WR_FULL))
-			break;
-		if (get_timer(0) >= endtime) {
-			printf("mbox: Timeout waiting for send space\n");
-			return -1;
-		}
-	}
-
-	/* Send the request */
-
-	val = BCM2835_MBOX_PACK(chan, send);
-	debug("mbox: TX raw: 0x%08x\n", val);
-	writel(val, &regs->write);
-
-	/* Wait for the response */
-
-	for (;;) {
-		val = readl(&regs->status);
-		if (!(val & BCM2835_MBOX_STATUS_RD_EMPTY))
-			break;
-		if (get_timer(0) >= endtime) {
-			printf("mbox: Timeout waiting for response\n");
-			return -1;
-		}
-	}
-
-	/* Read the response */
-
-	val = readl(&regs->read);
-	debug("mbox: RX raw: 0x%08x\n", val);
-
-	/* Validate the response */
-
-	if (BCM2835_MBOX_UNPACK_CHAN(val) != chan) {
-		printf("mbox: Response channel mismatch\n");
-		return -1;
-	}
-
-	*recv = BCM2835_MBOX_UNPACK_DATA(val);
-
-	return 0;
-}
-
-#ifdef DEBUG
-void dump_buf(struct bcm2835_mbox_hdr *buffer)
-{
-	u32 *p;
-	u32 words;
-	int i;
-
-	p = (u32 *)buffer;
-	words = buffer->buf_size / 4;
-	for (i = 0; i < words; i++)
-		printf("    0x%04x: 0x%08x\n", i * 4, p[i]);
-}
-#endif
-
-int bcm2835_mbox_call_prop(u32 chan, struct bcm2835_mbox_hdr *buffer)
-{
-	int ret;
-	u32 rbuffer;
-	struct bcm2835_mbox_tag_hdr *tag;
-	int tag_index;
-
-#ifdef DEBUG
-	printf("mbox: TX buffer\n");
-	dump_buf(buffer);
-#endif
-
-	ret = bcm2835_mbox_call_raw(chan, (u32)buffer, &rbuffer);
-	if (ret)
-		return ret;
-	if (rbuffer != (u32)buffer) {
-		printf("mbox: Response buffer mismatch\n");
-		return -1;
-	}
-
-#ifdef DEBUG
-	printf("mbox: RX buffer\n");
-	dump_buf(buffer);
-#endif
-
-	/* Validate overall response status */
-
-	if (buffer->code != BCM2835_MBOX_RESP_CODE_SUCCESS) {
-		printf("mbox: Header response code invalid\n");
-		return -1;
-	}
-
-	/* Validate each tag's response status */
-
-	tag = (void *)(buffer + 1);
-	tag_index = 0;
-	while (tag->tag) {
-		if (!(tag->val_len & BCM2835_MBOX_TAG_VAL_LEN_RESPONSE)) {
-			printf("mbox: Tag %d missing val_len response bit\n",
-				tag_index);
-			return -1;
-		}
-		/*
-		 * Clear the reponse bit so clients can just look right at the
-		 * length field without extra processing
-		 */
-		tag->val_len &= ~BCM2835_MBOX_TAG_VAL_LEN_RESPONSE;
-		tag = (void *)(((u8 *)tag) + sizeof(*tag) + tag->val_buf_size);
-		tag_index++;
-	}
-
-	return 0;
-}
--- a/arch/arm/cpu/arm1176/bcm2835/timer.c
+++ b/arch/arm/cpu/arm1176/bcm2835/timer.c
@@ -23,7 +23,7 @@ int timer_init(void)
 	return 0;
 }

-ulong get_timer_us(ulong base)
+ulong get_timer(ulong base)
 {
 	struct bcm2835_timer_regs *regs =
 		(struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR;
@@ -31,14 +31,6 @@ ulong get_timer_us(ulong base)
 	return readl(&regs->clo) - base;
 }

-ulong get_timer(ulong base)
-{
-	ulong us = get_timer_us(0);
-	us /= (1000000 / CONFIG_SYS_HZ);
-	us -= base;
-	return us;
-}
-
 unsigned long long get_ticks(void)
 {
 	return get_timer(0);
@@ -54,10 +46,10 @@ void __udelay(unsigned long usec)
 	ulong endtime;
 	signed long diff;

-	endtime = get_timer_us(0) + usec;
+	endtime = get_timer(0) + usec;

 	do {
-		ulong now = get_timer_us(0);
+		ulong now = get_timer(0);
 		diff = endtime - now;
 	} while (diff >= 0);
 }
--- a/arch/arm/cpu/arm1176/s3c64xx/Makefile
+++ b/arch/arm/cpu/arm1176/s3c64xx/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+SOBJS	= reset.o
+
+COBJS-$(CONFIG_S3C6400)	+= cpu_init.o speed.o
+COBJS-y	+= timer.o init.o
+
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all:	$(obj).depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- a/arch/arm/cpu/arm1176/s3c64xx/config.mk
+++ b/arch/arm/cpu/arm1176/s3c64xx/config.mk
@@ -0,0 +1,34 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
+
+# Make ARMv5 to allow more compilers to work, even though its v6.
+PLATFORM_CPPFLAGS += -march=armv5t
+# =========================================================================
+#
+# Supply options according to compiler version
+#
+# =========================================================================
+PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\
+			$(call cc-option,-malignment-traps,))
+PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
--- a/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S
+++ b/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S
@@ -0,0 +1,135 @@
+/*
+ * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400
+ *
+ * Copyright (C) 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/s3c6400.h>
+
+	.globl mem_ctrl_asm_init
+mem_ctrl_asm_init:
+	/* DMC1 base address 0x7e001000 */
+	ldr	r0, =ELFIN_DMC1_BASE
+
+	ldr	r1, =0x4
+	str	r1, [r0, #INDEX_DMC_MEMC_CMD]
+
+	ldr	r1, =DMC_DDR_REFRESH_PRD
+	str	r1, [r0, #INDEX_DMC_REFRESH_PRD]
+
+	ldr	r1, =DMC_DDR_CAS_LATENCY
+	str	r1, [r0, #INDEX_DMC_CAS_LATENCY]
+
+	ldr	r1, =DMC_DDR_t_DQSS
+	str	r1, [r0, #INDEX_DMC_T_DQSS]
+
+	ldr	r1, =DMC_DDR_t_MRD
+	str	r1, [r0, #INDEX_DMC_T_MRD]
+
+	ldr	r1, =DMC_DDR_t_RAS
+	str	r1, [r0, #INDEX_DMC_T_RAS]
+
+	ldr	r1, =DMC_DDR_t_RC
+	str	r1, [r0, #INDEX_DMC_T_RC]
+
+	ldr	r1, =DMC_DDR_t_RCD
+	ldr	r2, =DMC_DDR_schedule_RCD
+	orr	r1, r1, r2
+	str	r1, [r0, #INDEX_DMC_T_RCD]
+
+	ldr	r1, =DMC_DDR_t_RFC
+	ldr	r2, =DMC_DDR_schedule_RFC
+	orr	r1, r1, r2
+	str	r1, [r0, #INDEX_DMC_T_RFC]
+
+	ldr	r1, =DMC_DDR_t_RP
+	ldr	r2, =DMC_DDR_schedule_RP
+	orr	r1, r1, r2
+	str	r1, [r0, #INDEX_DMC_T_RP]
+
+	ldr	r1, =DMC_DDR_t_RRD
+	str	r1, [r0, #INDEX_DMC_T_RRD]
+
+	ldr	r1, =DMC_DDR_t_WR
+	str	r1, [r0, #INDEX_DMC_T_WR]
+
+	ldr	r1, =DMC_DDR_t_WTR
+	str	r1, [r0, #INDEX_DMC_T_WTR]
+
+	ldr	r1, =DMC_DDR_t_XP
+	str	r1, [r0, #INDEX_DMC_T_XP]
+
+	ldr	r1, =DMC_DDR_t_XSR
+	str	r1, [r0, #INDEX_DMC_T_XSR]
+
+	ldr	r1, =DMC_DDR_t_ESR
+	str	r1, [r0, #INDEX_DMC_T_ESR]
+
+	ldr	r1, =DMC1_MEM_CFG
+	str	r1, [r0, #INDEX_DMC_MEMORY_CFG]
+
+	ldr	r1, =DMC1_MEM_CFG2
+	str	r1, [r0, #INDEX_DMC_MEMORY_CFG2]
+
+	ldr	r1, =DMC1_CHIP0_CFG
+	str	r1, [r0, #INDEX_DMC_CHIP_0_CFG]
+
+	ldr	r1, =DMC_DDR_32_CFG
+	str	r1, [r0, #INDEX_DMC_USER_CONFIG]
+
+	/* DMC0 DDR Chip 0 configuration direct command reg */
+	ldr	r1, =DMC_NOP0
+	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
+
+	/* Precharge All */
+	ldr	r1, =DMC_PA0
+	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
+
+	/* Auto Refresh 2 time */
+	ldr	r1, =DMC_AR0
+	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
+	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
+
+	/* MRS */
+	ldr	r1, =DMC_mDDR_EMR0
+	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
+
+	/* Mode Reg */
+	ldr	r1, =DMC_mDDR_MR0
+	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
+
+	/* Enable DMC1 */
+	mov	r1, #0x0
+	str	r1, [r0, #INDEX_DMC_MEMC_CMD]
+
+check_dmc1_ready:
+	ldr	r1, [r0, #INDEX_DMC_MEMC_STATUS]
+	mov	r2, #0x3
+	and	r1, r1, r2
+	cmp	r1, #0x1
+	bne	check_dmc1_ready
+	nop
+
+	mov	pc, lr
+
+	.ltorg
--- a/arch/arm/cpu/arm1176/s3c64xx/init.c
+++ b/arch/arm/cpu/arm1176/s3c64xx/init.c
@@ -1,5 +1,7 @@
 /*
- * Copyright (c) 2012 The Chromium OS Authors.
+ * (C) Copyright 2012 Ashok Kumar Reddy Kourla
+ * ashokkourla2000@gmail.com
+ *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
@@ -12,16 +14,13 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
 */

-#ifndef __ASM_SH_SECTIONS_H
-#define __ASM_SH_SECTIONS_H
+#include<common.h>

-#include <asm-generic/sections.h>
+int arch_cpu_init(void)
+{
+	icache_enable();

-#endif
+	return 0;
+}
--- a/arch/arm/include/asm/arch-tegra30/spl.h
+++ b/arch/arm/include/asm/arch-tegra30/spl.h
@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2012
- * NVIDIA Corporation <www.nvidia.com>
+ * Copyright (c) 2009 Samsung Electronics.
+ * Minkyu Kang <mk7.kang@samsung.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
@@ -20,9 +20,15 @@
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
-#ifndef	_ASM_ARCH_SPL_H_
-#define	_ASM_ARCH_SPL_H_

-#define BOOT_DEVICE_RAM         1
+#include <asm/arch/s3c6400.h>

-#endif
+.globl reset_cpu
+reset_cpu:
+	ldr	r1, =ELFIN_CLOCK_POWER_BASE
+	ldr	r2, [r1, #SYS_ID_OFFSET]
+	ldr	r3, =0xffff
+	and	r2, r3, r2, lsr #12
+	str	r2, [r1, #SW_RST_OFFSET]
+_loop_forever:
+	b	_loop_forever
--- a/arch/arm/cpu/arm1176/s3c64xx/speed.c
+++ b/arch/arm/cpu/arm1176/s3c64xx/speed.c
@@ -0,0 +1,145 @@
+/*
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This code should work for both the S3C2400 and the S3C2410
+ * as they seem to have the same PLL and clock machinery inside.
+ * The different address mapping is handled by the s3c24xx.h files below.
+ */
+
+#include <common.h>
+#include <asm/arch/s3c6400.h>
+
+#define APLL 0
+#define MPLL 1
+#define EPLL 2
+
+/* ------------------------------------------------------------------------- */
+/*
+ * NOTE: This describes the proper use of this file.
+ *
+ * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
+ *
+ * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
+ * the specified bus in HZ.
+ */
+/* ------------------------------------------------------------------------- */
+
+static ulong get_PLLCLK(int pllreg)
+{
+	ulong r, m, p, s;
+
+	switch (pllreg) {
+	case APLL:
+		r = APLL_CON_REG;
+		break;
+	case MPLL:
+		r = MPLL_CON_REG;
+		break;
+	case EPLL:
+		r = EPLL_CON0_REG;
+		break;
+	default:
+		hang();
+	}
+
+	m = (r >> 16) & 0x3ff;
+	p = (r >> 8) & 0x3f;
+	s = r & 0x7;
+
+	return m * (CONFIG_SYS_CLK_FREQ / (p * (1 << s)));
+}
+
+/* return ARMCORE frequency */
+ulong get_ARMCLK(void)
+{
+	ulong div;
+
+	div = CLK_DIV0_REG;
+
+	return get_PLLCLK(APLL) / ((div & 0x7) + 1);
+}
+
+/* return FCLK frequency */
+ulong get_FCLK(void)
+{
+	return get_PLLCLK(APLL);
+}
+
+/* return HCLK frequency */
+ulong get_HCLK(void)
+{
+	ulong fclk;
+
+	uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1;
+	uint hclk_div = ((CLK_DIV0_REG >> 8) & 0x1) + 1;
+
+	/*
+	 * Bit 7 exists on s3c6410, and not on s3c6400, it is reserved on
+	 * s3c6400 and is always 0, and it is indeed running in ASYNC mode
+	 */
+	if (OTHERS_REG & 0x80)
+		fclk = get_FCLK();		/* SYNC Mode	*/
+	else
+		fclk = get_PLLCLK(MPLL);	/* ASYNC Mode	*/
+
+	return fclk / (hclk_div * hclkx2_div);
+}
+
+/* return PCLK frequency */
+ulong get_PCLK(void)
+{
+	ulong fclk;
+	uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1;
+	uint pre_div = ((CLK_DIV0_REG >> 12) & 0xf) + 1;
+
+	if (OTHERS_REG & 0x80)
+		fclk = get_FCLK();		/* SYNC Mode	*/
+	else
+		fclk = get_PLLCLK(MPLL);	/* ASYNC Mode	*/
+
+	return fclk / (hclkx2_div * pre_div);
+}
+
+/* return UCLK frequency */
+ulong get_UCLK(void)
+{
+	return get_PLLCLK(EPLL);
+}
+
+int print_cpuinfo(void)
+{
+	printf("\nCPU:     S3C6400@%luMHz\n", get_ARMCLK() / 1000000);
+	printf("         Fclk = %luMHz, Hclk = %luMHz, Pclk = %luMHz ",
+	       get_FCLK() / 1000000, get_HCLK() / 1000000,
+	       get_PCLK() / 1000000);
+
+	if (OTHERS_REG & 0x80)
+		printf("(SYNC Mode) \n");
+	else
+		printf("(ASYNC Mode) \n");
+	return 0;
+}
--- a/arch/arm/cpu/arm1176/s3c64xx/timer.c
+++ b/arch/arm/cpu/arm1176/s3c64xx/timer.c
@@ -0,0 +1,160 @@
+/*
+ * (C) Copyright 2003
+ * Texas Instruments <www.ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2004
+ * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/proc-armv/ptrace.h>
+#include <asm/arch/s3c6400.h>
+#include <div64.h>
+
+static ulong timer_load_val;
+
+#define PRESCALER	167
+
+static s3c64xx_timers *s3c64xx_get_base_timers(void)
+{
+	return (s3c64xx_timers *)ELFIN_TIMER_BASE;
+}
+
+/* macro to read the 16 bit timer */
+static inline ulong read_timer(void)
+{
+	s3c64xx_timers *const timers = s3c64xx_get_base_timers();
+
+	return timers->TCNTO4;
+}
+
+/* Internal tick units */
+/* Last decremneter snapshot */
+static unsigned long lastdec;
+/* Monotonic incrementing timer */
+static unsigned long long timestamp;
+
+int timer_init(void)
+{
+	s3c64xx_timers *const timers = s3c64xx_get_base_timers();
+
+	/* use PWM Timer 4 because it has no output */
+	/*
+	 * We use the following scheme for the timer:
+	 * Prescaler is hard fixed at 167, divider at 1/4.
+	 * This gives at PCLK frequency 66MHz approx. 10us ticks
+	 * The timer is set to wrap after 100s, at 66MHz this obviously
+	 * happens after 10,000,000 ticks. A long variable can thus
+	 * keep values up to 40,000s, i.e., 11 hours. This should be
+	 * enough for most uses:-) Possible optimizations: select a
+	 * binary-friendly frequency, e.g., 1ms / 128. Also calculate
+	 * the prescaler automatically for other PCLK frequencies.
+	 */
+	timers->TCFG0 = PRESCALER << 8;
+	if (timer_load_val == 0) {
+		timer_load_val = get_PCLK() / PRESCALER * (100 / 4); /* 100s */
+		timers->TCFG1 = (timers->TCFG1 & ~0xf0000) | 0x20000;
+	}
+
+	/* load value for 10 ms timeout */
+	lastdec = timers->TCNTB4 = timer_load_val;
+	/* auto load, manual update of Timer 4 */
+	timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO |
+		TCON_4_UPDATE;
+
+	/* auto load, start Timer 4 */
+	timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO | COUNT_4_ON;
+	timestamp = 0;
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	ulong now = read_timer();
+
+	if (lastdec >= now) {
+		/* normal mode */
+		timestamp += lastdec - now;
+	} else {
+		/* we have an overflow ... */
+		timestamp += lastdec + timer_load_val - now;
+	}
+	lastdec = now;
+
+	return timestamp;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	/* We overrun in 100s */
+	return (ulong)(timer_load_val / 100);
+}
+
+ulong get_timer_masked(void)
+{
+	unsigned long long res = get_ticks();
+	do_div (res, (timer_load_val / (100 * CONFIG_SYS_HZ)));
+	return res;
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void __udelay(unsigned long usec)
+{
+	unsigned long long tmp;
+	ulong tmo;
+
+	tmo = (usec + 9) / 10;
+	tmp = get_ticks() + tmo;	/* get current timestamp */
+
+	while (get_ticks() < tmp)/* loop till event */
+		 /*NOP*/;
+}
--- a/arch/arm/cpu/arm1176/start.S
+++ b/arch/arm/cpu/arm1176/start.S
@@ -33,8 +33,11 @@
 #include <asm-offsets.h>
 #include <config.h>
 #include <version.h>
+#ifdef CONFIG_ENABLE_MMU
+#include <asm/proc/domain.h>
+#endif

-#ifndef CONFIG_SYS_PHY_UBOOT_BASE
+#if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE)
 #define CONFIG_SYS_PHY_UBOOT_BASE	CONFIG_SYS_UBOOT_BASE
 #endif

@@ -48,7 +51,7 @@

 .globl _start
 _start: b	reset
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_NAND_SPL
 	ldr	pc, _undefined_instruction
 	ldr	pc, _software_interrupt
 	ldr	pc, _prefetch_abort
@@ -95,11 +98,15 @@ _end_vect:

 .globl _TEXT_BASE
 _TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
 	.word	CONFIG_SYS_TEXT_BASE
-#endif
+
+/*
+ * Below variable is very important because we use MMU in U-Boot.
+ * Without it, we cannot run code correctly before MMU is ON.
+ * by scsuh.
+ */
+_TEXT_PHY_BASE:
+	.word	CONFIG_SYS_PHY_UBOOT_BASE

 /*
 * These are defined in the board-specific linker script.
@@ -114,7 +121,7 @@ _bss_start_ofs:

 .globl _bss_end_ofs
 _bss_end_ofs:
-	.word __bss_end - _start
+	.word __bss_end__ - _start

 .globl _end_ofs
 _end_ofs:
@@ -157,7 +164,7 @@ cpu_init_crit:
 	 * When booting from NAND - it has definitely been a reset, so, no need
 	 * to flush caches and disable the MMU
 	 */
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_NAND_SPL
 	/*
 	 * flush v4 I/D caches
 	 */
@@ -221,12 +228,169 @@ skip_tcmdisable:

 /*------------------------------------------------------------------------------*/

+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ */
+	.globl	relocate_code
+relocate_code:
+	mov	r4, r0	/* save addr_sp */
+	mov	r5, r1	/* save addr of gd */
+	mov	r6, r2	/* save addr of destination */
+
+	adr	r0, _start
+	cmp	r0, r6
+	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
+	beq	relocate_done		/* skip relocation */
+	mov	r1, r6			/* r1 <- scratch for copy_loop */
+	ldr	r3, _bss_start_ofs
+	add	r2, r0, r3		/* r2 <- source end address	    */
+
+copy_loop:
+	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
+	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
+
+#ifndef CONFIG_SPL_BUILD
+	/*
+	 * fix .rel.dyn relocations
+	 */
+	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
+	sub	r9, r6, r0		/* r9 <- relocation offset */
+	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
+	add	r10, r10, r0		/* r10 <- sym table in FLASH */
+	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
+	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
+	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
+	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
+fixloop:
+	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
+	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
+	ldr	r1, [r2, #4]
+	and	r7, r1, #0xff
+	cmp	r7, #23			/* relative fixup? */
+	beq	fixrel
+	cmp	r7, #2			/* absolute fixup? */
+	beq	fixabs
+	/* ignore unknown type of fixup */
+	b	fixnext
+fixabs:
+	/* absolute fix: set location to (offset) symbol value */
+	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
+	add	r1, r10, r1		/* r1 <- address of symbol in table */
+	ldr	r1, [r1, #4]		/* r1 <- symbol value */
+	add	r1, r1, r9		/* r1 <- relocated sym addr */
+	b	fixnext
+fixrel:
+	/* relative fix: increase location by offset */
+	ldr	r1, [r0]
+	add	r1, r1, r9
+fixnext:
+	str	r1, [r0]
+	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
+	cmp	r2, r3
+	blo	fixloop
+#endif
+
+#ifdef CONFIG_ENABLE_MMU
+enable_mmu:
+	/* enable domain access */
+	ldr	r5, =0x0000ffff
+	mcr	p15, 0, r5, c3, c0, 0	/* load domain access register */
+
+	/* Set the TTB register */
+	ldr	r0, _mmu_table_base
+	ldr	r1, =CONFIG_SYS_PHY_UBOOT_BASE
+	ldr	r2, =0xfff00000
+	bic	r0, r0, r2
+	orr	r1, r0, r1
+	mcr	p15, 0, r1, c2, c0, 0
+
+	/* Enable the MMU */
+	mrc	p15, 0, r0, c1, c0, 0
+	orr	r0, r0, #1		/* Set CR_M to enable MMU */
+
+	/* Prepare to enable the MMU */
+	adr	r1, skip_hw_init
+	and	r1, r1, #0x3fc
+	ldr	r2, _TEXT_BASE
+	ldr	r3, =0xfff00000
+	and	r2, r2, r3
+	orr	r2, r2, r1
+	b	mmu_enable
+
+	.align 5
+	/* Run in a single cache-line */
+mmu_enable:
+
+	mcr	p15, 0, r0, c1, c0, 0
+	nop
+	nop
+	mov	pc, r2
+skip_hw_init:
+#endif
+
+relocate_done:
+
+	bx	lr
+
+_rel_dyn_start_ofs:
+	.word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+	.word __rel_dyn_end - _start
+_dynsym_start_ofs:
+	.word __dynsym_start - _start
+
+#ifdef CONFIG_ENABLE_MMU
+_mmu_table_base:
+	.word mmu_table
+#endif
+
 	.globl	c_runtime_cpu_setup
 c_runtime_cpu_setup:

 	mov	pc, lr

-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_NAND_SPL
+/*
+ * we assume that cache operation is done before. (eg. cleanup_before_linux())
+ * actually, we don't need to do anything about cache if not use d-cache in
+ * U-Boot. So, in this function we clean only MMU. by scsuh
+ *
+ * void	theLastJump(void *kernel, int arch_num, uint boot_params);
+ */
+#ifdef CONFIG_ENABLE_MMU
+	.globl theLastJump
+theLastJump:
+	mov	r9, r0
+	ldr	r3, =0xfff00000
+	ldr	r4, _TEXT_PHY_BASE
+	adr	r5, phy_last_jump
+	bic	r5, r5, r3
+	orr	r5, r5, r4
+	mov	pc, r5
+phy_last_jump:
+	/*
+	 * disable MMU stuff
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #0x00002300	/* clear bits 13, 9:8 (--V- --RS) */
+	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
+	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
+	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
+	mcr	p15, 0, r0, c1, c0, 0
+
+	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+
+	mov	r0, #0
+	mov	pc, r9
+#endif
+
+
 /*
 *************************************************************************
 *
@@ -316,11 +480,9 @@ c_runtime_cpu_setup:
 	/* save caller lr in position 0 of saved stack */
 	str	lr, [r0]
 	/* get the spsr */
-	mrs	lr, spsr
+	mrs	r0, spsr
 	/* save spsr in position 1 of saved stack */
 	str	lr, [r0, #4]
-	/* restore lr */
-	ldr	lr, [r0]
 	/* restore r0 */
 	ldr	r0, [r13]
 	/* pop stack entry */
@@ -371,4 +533,4 @@ fiq:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_fiq
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_NAND_SPL */
--- a/arch/arm/cpu/arm720t/start.S
+++ b/arch/arm/cpu/arm720t/start.S
@@ -85,7 +85,7 @@ _pad:			.word 0x12345678 /* now 16*4=64 */

 .globl _TEXT_BASE
 _TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
+#ifdef CONFIG_SPL_BUILD
 	.word	CONFIG_SPL_TEXT_BASE
 #else
 	.word	CONFIG_SYS_TEXT_BASE
@@ -103,7 +103,7 @@ _bss_start_ofs:

 .globl _bss_end_ofs
 _bss_end_ofs:
-	.word __bss_end - _start
+	.word __bss_end__ - _start

 .globl _end_ofs
 _end_ofs:
@@ -151,6 +151,85 @@ reset:

 /*------------------------------------------------------------------------------*/

+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ */
+	.globl	relocate_code
+relocate_code:
+	mov	r4, r0	/* save addr_sp */
+	mov	r5, r1	/* save addr of gd */
+	mov	r6, r2	/* save addr of destination */
+
+	adr	r0, _start
+	cmp	r0, r6
+	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
+	beq	relocate_done		/* skip relocation */
+	mov	r1, r6			/* r1 <- scratch for copy_loop */
+	ldr	r3, _bss_start_ofs
+	add	r2, r0, r3		/* r2 <- source end address	    */
+
+copy_loop:
+	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
+	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
+
+#ifndef CONFIG_SPL_BUILD
+	/*
+	 * fix .rel.dyn relocations
+	 */
+	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
+	sub	r9, r6, r0		/* r9 <- relocation offset */
+	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
+	add	r10, r10, r0		/* r10 <- sym table in FLASH */
+	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
+	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
+	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
+	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
+fixloop:
+	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
+	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
+	ldr	r1, [r2, #4]
+	and	r7, r1, #0xff
+	cmp	r7, #23			/* relative fixup? */
+	beq	fixrel
+	cmp	r7, #2			/* absolute fixup? */
+	beq	fixabs
+	/* ignore unknown type of fixup */
+	b	fixnext
+fixabs:
+	/* absolute fix: set location to (offset) symbol value */
+	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
+	add	r1, r10, r1		/* r1 <- address of symbol in table */
+	ldr	r1, [r1, #4]		/* r1 <- symbol value */
+	add	r1, r1, r9		/* r1 <- relocated sym addr */
+	b	fixnext
+fixrel:
+	/* relative fix: increase location by offset */
+	ldr	r1, [r0]
+	add	r1, r1, r9
+fixnext:
+	str	r1, [r0]
+	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
+	cmp	r2, r3
+	blo	fixloop
+#endif
+
+relocate_done:
+
+	mov	pc, lr
+
+_rel_dyn_start_ofs:
+	.word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+	.word __rel_dyn_end - _start
+_dynsym_start_ofs:
+	.word __dynsym_start - _start
+
 	.globl	c_runtime_cpu_setup
 c_runtime_cpu_setup:

@@ -167,9 +246,9 @@ c_runtime_cpu_setup:
 *************************************************************************
 */

-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 cpu_init_crit:

+#if !defined(CONFIG_TEGRA)
 	mov	ip, lr
 	/*
 	 * before relocating, we have to setup RAM timing
@@ -178,9 +257,9 @@ cpu_init_crit:
 	 */
 	bl	lowlevel_init
 	mov	lr, ip
+#endif

 	mov	pc, lr
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */


 #ifndef CONFIG_SPL_BUILD
--- a/arch/arm/cpu/arm720t/tegra-common/Makefile
+++ b/arch/arm/cpu/arm720t/tegra-common/Makefile
@@ -28,7 +28,6 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)libtegra-common.o

 COBJS-$(CONFIG_SPL_BUILD) += spl.o
-COBJS-y	+= cpu.o

 SRCS	:= $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS-y))
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c
@@ -1,341 +0,0 @@
-/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gp_padctrl.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/pmc.h>
-#include <asm/arch-tegra/scu.h>
-#include "cpu.h"
-
-int get_num_cpus(void)
-{
-	struct apb_misc_gp_ctlr *gp;
-	uint rev;
-
-	gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
-	rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
-
-	switch (rev) {
-	case CHIPID_TEGRA20:
-		return 2;
-		break;
-	case CHIPID_TEGRA30:
-	case CHIPID_TEGRA114:
-	default:
-		return 4;
-		break;
-	}
-}
-
-/*
- * Timing tables for each SOC for all four oscillator options.
- */
-struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
-	/* T20: 1 GHz */
-	/*  n,  m, p, cpcon */
-	{{ 1000, 13, 0, 12},	/* OSC 13M */
-	 { 625,  12, 0, 8},	/* OSC 19.2M */
-	 { 1000, 12, 0, 12},	/* OSC 12M */
-	 { 1000, 26, 0, 12},	/* OSC 26M */
-	},
-
-	/* T25: 1.2 GHz */
-	{{ 923, 10, 0, 12},
-	 { 750, 12, 0, 8},
-	 { 600,  6, 0, 12},
-	 { 600, 13, 0, 12},
-	},
-
-	/* T30: 1.4 GHz */
-	{{ 862, 8, 0, 8},
-	 { 583, 8, 0, 4},
-	 { 700, 6, 0, 8},
-	 { 700, 13, 0, 8},
-	},
-
-	/* T114: 1.4 GHz */
-	{{ 862, 8, 0, 8},
-	 { 583, 8, 0, 4},
-	 { 696, 12, 0, 8},
-	 { 700, 13, 0, 8},
-	},
-};
-
-void adjust_pllp_out_freqs(void)
-{
-	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-	struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_PERIPH];
-	u32 reg;
-
-	/* Set T30 PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
-	reg = readl(&pll->pll_out[0]);	/* OUTA, contains OUT2 / OUT1 */
-	reg |= (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) | PLLP_OUT2_OVR
-		| (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) | PLLP_OUT1_OVR;
-	writel(reg, &pll->pll_out[0]);
-
-	reg = readl(&pll->pll_out[1]);   /* OUTB, contains OUT4 / OUT3 */
-	reg |= (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) | PLLP_OUT4_OVR
-		| (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) | PLLP_OUT3_OVR;
-	writel(reg, &pll->pll_out[1]);
-}
-
-int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
-		u32 divp, u32 cpcon)
-{
-	u32 reg;
-
-	/* If PLLX is already enabled, just return */
-	if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
-		debug("pllx_set_rate: PLLX already enabled, returning\n");
-		return 0;
-	}
-
-	debug(" pllx_set_rate entry\n");
-
-	/* Set BYPASS, m, n and p to PLLX_BASE */
-	reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT);
-	reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT));
-	writel(reg, &pll->pll_base);
-
-	/* Set cpcon to PLLX_MISC */
-	reg = (cpcon << PLL_CPCON_SHIFT);
-
-	/* Set dccon to PLLX_MISC if freq > 600MHz */
-	if (divn > 600)
-		reg |= (1 << PLL_DCCON_SHIFT);
-	writel(reg, &pll->pll_misc);
-
-	/* Enable PLLX */
-	reg = readl(&pll->pll_base);
-	reg |= PLL_ENABLE_MASK;
-
-	/* Disable BYPASS */
-	reg &= ~PLL_BYPASS_MASK;
-	writel(reg, &pll->pll_base);
-
-	/* Set lock_enable to PLLX_MISC */
-	reg = readl(&pll->pll_misc);
-	reg |= PLL_LOCK_ENABLE_MASK;
-	writel(reg, &pll->pll_misc);
-
-	return 0;
-}
-
-void init_pllx(void)
-{
-	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-	struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
-	int soc_type, sku_info, chip_sku;
-	enum clock_osc_freq osc;
-	struct clk_pll_table *sel;
-
-	debug("init_pllx entry\n");
-
-	/* get SOC (chip) type */
-	soc_type = tegra_get_chip();
-	debug(" init_pllx: SoC = 0x%02X\n", soc_type);
-
-	/* get SKU info */
-	sku_info = tegra_get_sku_info();
-	debug(" init_pllx: SKU info byte = 0x%02X\n", sku_info);
-
-	/* get chip SKU, combo of the above info */
-	chip_sku = tegra_get_chip_sku();
-	debug(" init_pllx: Chip SKU = %d\n", chip_sku);
-
-	/* get osc freq */
-	osc = clock_get_osc_freq();
-	debug(" init_pllx: osc = %d\n", osc);
-
-	/* set pllx */
-	sel = &tegra_pll_x_table[chip_sku][osc];
-	pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
-
-	/* adjust PLLP_out1-4 on T3x/T114 */
-	if (soc_type >= CHIPID_TEGRA30) {
-		debug("  init_pllx: adjusting PLLP out freqs\n");
-		adjust_pllp_out_freqs();
-	}
-}
-
-void enable_cpu_clock(int enable)
-{
-	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-	u32 clk;
-
-	/*
-	 * NOTE:
-	 * Regardless of whether the request is to enable or disable the CPU
-	 * clock, every processor in the CPU complex except the master (CPU 0)
-	 * will have it's clock stopped because the AVP only talks to the
-	 * master.
-	 */
-
-	if (enable) {
-		/* Initialize PLLX */
-		init_pllx();
-
-		/* Wait until all clocks are stable */
-		udelay(PLL_STABILIZATION_DELAY);
-
-		writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
-		writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
-	}
-
-	/*
-	 * Read the register containing the individual CPU clock enables and
-	 * always stop the clocks to CPUs > 0.
-	 */
-	clk = readl(&clkrst->crc_clk_cpu_cmplx);
-	clk |= 1 << CPU1_CLK_STP_SHIFT;
-	if (get_num_cpus() == 4)
-		clk |= (1 << CPU2_CLK_STP_SHIFT) + (1 << CPU3_CLK_STP_SHIFT);
-
-	/* Stop/Unstop the CPU clock */
-	clk &= ~CPU0_CLK_STP_MASK;
-	clk |= !enable << CPU0_CLK_STP_SHIFT;
-	writel(clk, &clkrst->crc_clk_cpu_cmplx);
-
-	clock_enable(PERIPH_ID_CPU);
-}
-
-static int is_cpu_powered(void)
-{
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-
-	return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
-}
-
-static void remove_cpu_io_clamps(void)
-{
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-	u32 reg;
-
-	/* Remove the clamps on the CPU I/O signals */
-	reg = readl(&pmc->pmc_remove_clamping);
-	reg |= CPU_CLMP;
-	writel(reg, &pmc->pmc_remove_clamping);
-
-	/* Give I/O signals time to stabilize */
-	udelay(IO_STABILIZATION_DELAY);
-}
-
-void powerup_cpu(void)
-{
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-	u32 reg;
-	int timeout = IO_STABILIZATION_DELAY;
-
-	if (!is_cpu_powered()) {
-		/* Toggle the CPU power state (OFF -> ON) */
-		reg = readl(&pmc->pmc_pwrgate_toggle);
-		reg &= PARTID_CP;
-		reg |= START_CP;
-		writel(reg, &pmc->pmc_pwrgate_toggle);
-
-		/* Wait for the power to come up */
-		while (!is_cpu_powered()) {
-			if (timeout-- == 0)
-				printf("CPU failed to power up!\n");
-			else
-				udelay(10);
-		}
-
-		/*
-		 * Remove the I/O clamps from CPU power partition.
-		 * Recommended only on a Warm boot, if the CPU partition gets
-		 * power gated. Shouldn't cause any harm when called after a
-		 * cold boot according to HW, probably just redundant.
-		 */
-		remove_cpu_io_clamps();
-	}
-}
-
-void reset_A9_cpu(int reset)
-{
-	/*
-	* NOTE:  Regardless of whether the request is to hold the CPU in reset
-	*        or take it out of reset, every processor in the CPU complex
-	*        except the master (CPU 0) will be held in reset because the
-	*        AVP only talks to the master. The AVP does not know that there
-	*        are multiple processors in the CPU complex.
-	*/
-	int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug;
-	int num_cpus = get_num_cpus();
-	int cpu;
-
-	debug("reset_a9_cpu entry\n");
-	/* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
-	for (cpu = 1; cpu < num_cpus; cpu++)
-		reset_cmplx_set_enable(cpu, mask, 1);
-	reset_cmplx_set_enable(0, mask, reset);
-
-	/* Enable/Disable master CPU reset */
-	reset_set_enable(PERIPH_ID_CPU, reset);
-}
-
-void clock_enable_coresight(int enable)
-{
-	u32 rst, src = 2;
-	int soc_type;
-
-	debug("clock_enable_coresight entry\n");
-	clock_set_enable(PERIPH_ID_CORESIGHT, enable);
-	reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
-
-	if (enable) {
-		/*
-		 * Put CoreSight on PLLP_OUT0 and divide it down as per
-		 * PLLP base frequency based on SoC type (T20/T30/T114).
-		 * Clock divider request would setup CSITE clock as 144MHz
-		 * for PLLP base 216MHz and 204MHz for PLLP base 408MHz
-		 */
-
-		soc_type = tegra_get_chip();
-		if (soc_type == CHIPID_TEGRA30 || soc_type == CHIPID_TEGRA114)
-			src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000);
-		else if (soc_type == CHIPID_TEGRA20)
-			src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
-		else
-			printf("%s: Unknown SoC type %X!\n",
-				 __func__, soc_type);
-
-		clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
-
-		/* Unlock the CPU CoreSight interfaces */
-		rst = CORESIGHT_UNLOCK;
-		writel(rst, CSITE_CPU_DBG0_LAR);
-		writel(rst, CSITE_CPU_DBG1_LAR);
-		if (get_num_cpus() == 4) {
-			writel(rst, CSITE_CPU_DBG2_LAR);
-			writel(rst, CSITE_CPU_DBG3_LAR);
-		}
-	}
-}
-
-void halt_avp(void)
-{
-	for (;;) {
-		writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
-			| HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
-			FLOW_CTLR_HALT_COP_EVENTS);
-	}
-}
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.h
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.h
@@ -26,13 +26,7 @@
 #define PLL_STABILIZATION_DELAY (300)
 #define IO_STABILIZATION_DELAY	(1000)

-#if defined(CONFIG_TEGRA20)
 #define NVBL_PLLP_KHZ	(216000)
-#elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
-#define NVBL_PLLP_KHZ	(408000)
-#else
-#error "Unknown Tegra chip!"
-#endif

 #define PLLX_ENABLED		(1 << 30)
 #define CCLK_BURST_POLICY	0x20008888
@@ -50,11 +44,50 @@

 #define CORESIGHT_UNLOCK	0xC5ACCE55;

+/* AP20-Specific Base Addresses */
+
+/* AP20 Base physical address of SDRAM. */
+#define AP20_BASE_PA_SDRAM      0x00000000
+/* AP20 Base physical address of internal SRAM. */
+#define AP20_BASE_PA_SRAM       0x40000000
+/* AP20 Size of internal SRAM (256KB). */
+#define AP20_BASE_PA_SRAM_SIZE  0x00040000
+/* AP20 Base physical address of flash. */
+#define AP20_BASE_PA_NOR_FLASH  0xD0000000
+/* AP20 Base physical address of boot information table. */
+#define AP20_BASE_PA_BOOT_INFO  AP20_BASE_PA_SRAM
+
+/*
+ * Super-temporary stacks for EXTREMELY early startup. The values chosen for
+ * these addresses must be valid on ALL SOCs because this value is used before
+ * we are able to differentiate between the SOC types.
+ *
+ * NOTE: The since CPU's stack will eventually be moved from IRAM to SDRAM, its
+ *       stack is placed below the AVP stack. Once the CPU stack has been moved,
+ *       the AVP is free to use the IRAM the CPU stack previously occupied if
+ *       it should need to do so.
+ *
+ * NOTE: In multi-processor CPU complex configurations, each processor will have
+ *       its own stack of size CPU_EARLY_BOOT_STACK_SIZE. CPU 0 will have a
+ *       limit of CPU_EARLY_BOOT_STACK_LIMIT. Each successive CPU will have a
+ *       stack limit that is CPU_EARLY_BOOT_STACK_SIZE less then the previous
+ *       CPU.
+ */
+
+/* Common AVP early boot stack limit */
+#define AVP_EARLY_BOOT_STACK_LIMIT	\
+	(AP20_BASE_PA_SRAM + (AP20_BASE_PA_SRAM_SIZE/2))
+/* Common AVP early boot stack size */
+#define AVP_EARLY_BOOT_STACK_SIZE	0x1000
+/* Common CPU early boot stack limit */
+#define CPU_EARLY_BOOT_STACK_LIMIT	\
+	(AVP_EARLY_BOOT_STACK_LIMIT - AVP_EARLY_BOOT_STACK_SIZE)
+/* Common CPU early boot stack size */
+#define CPU_EARLY_BOOT_STACK_SIZE	0x1000
+
 #define EXCEP_VECTOR_CPU_RESET_VECTOR	(NV_PA_EVP_BASE + 0x100)
 #define CSITE_CPU_DBG0_LAR		(NV_PA_CSITE_BASE + 0x10FB0)
 #define CSITE_CPU_DBG1_LAR		(NV_PA_CSITE_BASE + 0x12FB0)
-#define CSITE_CPU_DBG2_LAR		(NV_PA_CSITE_BASE + 0x14FB0)
-#define CSITE_CPU_DBG3_LAR		(NV_PA_CSITE_BASE + 0x16FB0)

 #define FLOW_CTLR_HALT_COP_EVENTS	(NV_PA_FLOW_BASE + 4)
 #define FLOW_MODE_STOP			2
@@ -62,25 +95,6 @@
 #define HALT_COP_EVENT_IRQ_1		(1 << 11)
 #define HALT_COP_EVENT_FIQ_1		(1 << 9)

-#define FLOW_MODE_NONE		0
-
-#define SIMPLE_PLLX     (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
-
-struct clk_pll_table {
-	u16	n;
-	u16	m;
-	u8	p;
-	u8	cpcon;
-};
-
-void clock_enable_coresight(int enable);
-void enable_cpu_clock(int enable);
-void halt_avp(void)  __attribute__ ((noreturn));
-void init_pllx(void);
-void powerup_cpu(void);
-void reset_A9_cpu(int reset);
 void start_cpu(u32 reset_vector);
-int tegra_get_chip(void);
-int tegra_get_sku_info(void);
-int tegra_get_chip_sku(void);
-void adjust_pllp_out_freqs(void);
+int ap20_cpu_is_cortexa9(void);
+void halt_avp(void)  __attribute__ ((noreturn));
--- a/arch/arm/cpu/arm720t/tegra-common/spl.c
+++ b/arch/arm/cpu/arm720t/tegra-common/spl.c
@@ -23,6 +23,7 @@
 * MA 02111-1307 USA
 */
 #include <common.h>
+#include "cpu.h"
 #include <spl.h>

 #include <asm/io.h>
@@ -31,7 +32,7 @@
 #include <asm/arch/tegra.h>
 #include <asm/arch-tegra/board.h>
 #include <asm/arch/spl.h>
-#include "cpu.h"
+

 void spl_board_init(void)
 {
--- a/arch/arm/cpu/arm720t/tegra114/Makefile
+++ b/arch/arm/cpu/arm720t/tegra114/Makefile
@@ -1,42 +0,0 @@
-#
-# Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-#COBJS-y	+= cpu.o t11x.o
-COBJS-y	+= cpu.o
-
-SRCS	:= $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
--- a/arch/arm/cpu/arm720t/tegra114/config.mk
+++ b/arch/arm/cpu/arm720t/tegra114/config.mk
@@ -1,19 +0,0 @@
-#
-# Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-#
-USE_PRIVATE_LIBGCC = yes
--- a/arch/arm/cpu/arm720t/tegra114/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra114/cpu.c
@@ -1,324 +0,0 @@
-/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/flow.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/pmc.h>
-#include "../tegra-common/cpu.h"
-
-/* Tegra114-specific CPU init code */
-static void enable_cpu_power_rail(void)
-{
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-	u32 reg;
-
-	debug("enable_cpu_power_rail entry\n");
-
-	/* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
-	pinmux_tristate_disable(PINGRP_PWR_I2C_SCL);
-	pinmux_tristate_disable(PINGRP_PWR_I2C_SDA);
-
-	/*
-	 * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
-	 * set it for 25ms (102MHz * .025)
-	 */
-	reg = 0x26E8F0;
-	writel(reg, &pmc->pmc_cpupwrgood_timer);
-
-	/* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */
-	clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL);
-	setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE);
-
-	/*
-	 * Set CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2_0_CAR2PMC_CPU_ACK_WIDTH
-	 * to 408 to satisfy the requirement of having at least 16 CPU clock
-	 * cycles before clamp removal.
-	 */
-
-	clrbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 0xFFF);
-	setbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 408);
-}
-
-static void enable_cpu_clocks(void)
-{
-	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-	u32 reg;
-
-	debug("enable_cpu_clocks entry\n");
-
-	/* Wait for PLL-X to lock */
-	do {
-		reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
-	} while ((reg & (1 << 27)) == 0);
-
-	/* Wait until all clocks are stable */
-	udelay(PLL_STABILIZATION_DELAY);
-
-	writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
-	writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
-
-	/* Always enable the main CPU complex clocks */
-	clock_enable(PERIPH_ID_CPU);
-	clock_enable(PERIPH_ID_CPULP);
-	clock_enable(PERIPH_ID_CPUG);
-}
-
-static void remove_cpu_resets(void)
-{
-	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-	u32 reg;
-
-	debug("remove_cpu_resets entry\n");
-	/* Take the slow non-CPU partition out of reset */
-	reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr);
-	writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpulp_cmplx_clr);
-
-	/* Take the fast non-CPU partition out of reset */
-	reg = readl(&clkrst->crc_rst_cpug_cmplx_clr);
-	writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpug_cmplx_clr);
-
-	/* Clear the SW-controlled reset of the slow cluster */
-	reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr);
-	reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0);
-	writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
-
-	/* Clear the SW-controlled reset of the fast cluster */
-	reg = readl(&clkrst->crc_rst_cpug_cmplx_clr);
-	reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0);
-	reg |= (CLR_CPURESET1+CLR_DBGRESET1+CLR_CORERESET1+CLR_CXRESET1);
-	reg |= (CLR_CPURESET2+CLR_DBGRESET2+CLR_CORERESET2+CLR_CXRESET2);
-	reg |= (CLR_CPURESET3+CLR_DBGRESET3+CLR_CORERESET3+CLR_CXRESET3);
-	writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
-}
-
-/**
- * The T114 requires some special clock initialization, including setting up
- * the DVC I2C, turning on MSELECT and selecting the G CPU cluster
- */
-void t114_init_clocks(void)
-{
-	struct clk_rst_ctlr *clkrst =
-			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-	struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
-	u32 val;
-
-	debug("t114_init_clocks entry\n");
-
-	/* Set active CPU cluster to G */
-	clrbits_le32(&flow->cluster_control, 1);
-
-	/*
-	 * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run
-	 * at 108 MHz. This is glitch free as only the source is changed, no
-	 * special precaution needed.
-	 */
-	val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
-		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
-		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
-		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
-		(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
-	writel(val, &clkrst->crc_sclk_brst_pol);
-
-	writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
-
-	debug("Setting up PLLX\n");
-	init_pllx();
-
-	val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT);
-	writel(val, &clkrst->crc_clk_sys_rate);
-
-	/* Enable clocks to required peripherals. TBD - minimize this list */
-	debug("Enabling clocks\n");
-
-	clock_set_enable(PERIPH_ID_CACHE2, 1);
-	clock_set_enable(PERIPH_ID_GPIO, 1);
-	clock_set_enable(PERIPH_ID_TMR, 1);
-	clock_set_enable(PERIPH_ID_RTC, 1);
-	clock_set_enable(PERIPH_ID_CPU, 1);
-	clock_set_enable(PERIPH_ID_EMC, 1);
-	clock_set_enable(PERIPH_ID_I2C5, 1);
-	clock_set_enable(PERIPH_ID_FUSE, 1);
-	clock_set_enable(PERIPH_ID_PMC, 1);
-	clock_set_enable(PERIPH_ID_APBDMA, 1);
-	clock_set_enable(PERIPH_ID_MEM, 1);
-	clock_set_enable(PERIPH_ID_IRAMA, 1);
-	clock_set_enable(PERIPH_ID_IRAMB, 1);
-	clock_set_enable(PERIPH_ID_IRAMC, 1);
-	clock_set_enable(PERIPH_ID_IRAMD, 1);
-	clock_set_enable(PERIPH_ID_CORESIGHT, 1);
-	clock_set_enable(PERIPH_ID_MSELECT, 1);
-	clock_set_enable(PERIPH_ID_EMC1, 1);
-	clock_set_enable(PERIPH_ID_MC1, 1);
-	clock_set_enable(PERIPH_ID_DVFS, 1);
-
-	/*
-	 * Set MSELECT clock source as PLLP (00), and ask for a clock
-	 * divider that would set the MSELECT clock at 102MHz for a
-	 * PLLP base of 408MHz.
-	 */
-	clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0,
-		CLK_DIVIDER(NVBL_PLLP_KHZ, 102000));
-
-	/* I2C5 (DVC) gets CLK_M and a divisor of 17 */
-	clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16);
-
-	/* Give clocks time to stabilize */
-	udelay(1000);
-
-	/* Take required peripherals out of reset */
-	debug("Taking periphs out of reset\n");
-	reset_set_enable(PERIPH_ID_CACHE2, 0);
-	reset_set_enable(PERIPH_ID_GPIO, 0);
-	reset_set_enable(PERIPH_ID_TMR, 0);
-	reset_set_enable(PERIPH_ID_COP, 0);
-	reset_set_enable(PERIPH_ID_EMC, 0);
-	reset_set_enable(PERIPH_ID_I2C5, 0);
-	reset_set_enable(PERIPH_ID_FUSE, 0);
-	reset_set_enable(PERIPH_ID_APBDMA, 0);
-	reset_set_enable(PERIPH_ID_MEM, 0);
-	reset_set_enable(PERIPH_ID_CORESIGHT, 0);
-	reset_set_enable(PERIPH_ID_MSELECT, 0);
-	reset_set_enable(PERIPH_ID_EMC1, 0);
-	reset_set_enable(PERIPH_ID_MC1, 0);
-	reset_set_enable(PERIPH_ID_DVFS, 0);
-
-	debug("t114_init_clocks exit\n");
-}
-
-static int is_partition_powered(u32 mask)
-{
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-	u32 reg;
-
-	/* Get power gate status */
-	reg = readl(&pmc->pmc_pwrgate_status);
-	return (reg & mask) == mask;
-}
-
-static int is_clamp_enabled(u32 mask)
-{
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-	u32 reg;
-
-	/* Get clamp status. TODO: Add pmc_clamp_status alias to pmc.h */
-	reg = readl(&pmc->pmc_pwrgate_timer_on);
-	return (reg & mask) == mask;
-}
-
-static void power_partition(u32 status, u32 partid)
-{
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-
-	debug("%s: status = %08X, part ID = %08X\n", __func__, status, partid);
-	/* Is the partition already on? */
-	if (!is_partition_powered(status)) {
-		/* No, toggle the partition power state (OFF -> ON) */
-		debug("power_partition, toggling state\n");
-		clrbits_le32(&pmc->pmc_pwrgate_toggle, 0x1F);
-		setbits_le32(&pmc->pmc_pwrgate_toggle, partid);
-		setbits_le32(&pmc->pmc_pwrgate_toggle, START_CP);
-
-		/* Wait for the power to come up */
-		while (!is_partition_powered(status))
-			;
-
-		/* Wait for the clamp status to be cleared */
-		while (is_clamp_enabled(status))
-			;
-
-		/* Give I/O signals time to stabilize */
-		udelay(IO_STABILIZATION_DELAY);
-	}
-}
-
-void powerup_cpus(void)
-{
-	debug("powerup_cpus entry\n");
-
-	/* We boot to the fast cluster */
-	debug("powerup_cpus entry: G cluster\n");
-	/* Power up the fast cluster rail partition */
-	power_partition(CRAIL, CRAILID);
-
-	/* Power up the fast cluster non-CPU partition */
-	power_partition(C0NC, C0NCID);
-
-	/* Power up the fast cluster CPU0 partition */
-	power_partition(CE0, CE0ID);
-}
-
-void start_cpu(u32 reset_vector)
-{
-	u32 imme, inst;
-
-	debug("start_cpu entry, reset_vector = %x\n", reset_vector);
-
-	t114_init_clocks();
-
-	/* Enable VDD_CPU */
-	enable_cpu_power_rail();
-
-	/* Get the CPU(s) running */
-	enable_cpu_clocks();
-
-	/* Enable CoreSight */
-	clock_enable_coresight(1);
-
-	/* Take CPU(s) out of reset */
-	remove_cpu_resets();
-
-	/* Set the entry point for CPU execution from reset */
-
-	/*
-	 * A01P with patched boot ROM; vector hard-coded to 0x4003fffc.
-	 * See nvbug 1193357 for details.
-	 */
-
-	/* mov r0, #lsb(reset_vector) */
-	imme = reset_vector & 0xffff;
-	inst = imme & 0xfff;
-	inst |= ((imme >> 12) << 16);
-	inst |= 0xe3000000;
-	writel(inst, 0x4003fff0);
-
-	/* movt r0, #msb(reset_vector) */
-	imme = (reset_vector >> 16) & 0xffff;
-	inst = imme & 0xfff;
-	inst |= ((imme >> 12) << 16);
-	inst |= 0xe3400000;
-	writel(inst, 0x4003fff4);
-
-	/* bx r0 */
-	writel(0xe12fff10, 0x4003fff8);
-
-	/* b -12 */
-	imme = (u32)-20;
-	inst = (imme >> 2) & 0xffffff;
-	inst |= 0xea000000;
-	writel(inst, 0x4003fffc);
-
-	/* Write to orignal location for compatibility */
-	writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
-
-	/* If the CPU(s) don't already have power, power 'em up */
-	powerup_cpus();
-}
--- a/arch/arm/cpu/arm720t/tegra20/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra20/cpu.c
@@ -1,25 +1,160 @@
 /*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
+* (C) Copyright 2010-2011
+* NVIDIA Corporation <www.nvidia.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/

 #include <common.h>
 #include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/pinmux.h>
 #include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
 #include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/scu.h>
 #include "../tegra-common/cpu.h"

+/* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */
+int ap20_cpu_is_cortexa9(void)
+{
+	u32 id = readb(NV_PA_PG_UP_BASE + PG_UP_TAG_0);
+	return id == (PG_UP_TAG_0_PID_CPU & 0xff);
+}
+
+void init_pllx(void)
+{
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_XCPU];
+	u32 reg;
+
+	/* If PLLX is already enabled, just return */
+	if (readl(&pll->pll_base) & PLL_ENABLE_MASK)
+		return;
+
+	/* Set PLLX_MISC */
+	writel(1 << PLL_CPCON_SHIFT, &pll->pll_misc);
+
+	/* Use 12MHz clock here */
+	reg = PLL_BYPASS_MASK | (12 << PLL_DIVM_SHIFT);
+	reg |= 1000 << PLL_DIVN_SHIFT;
+	writel(reg, &pll->pll_base);
+
+	reg |= PLL_ENABLE_MASK;
+	writel(reg, &pll->pll_base);
+
+	reg &= ~PLL_BYPASS_MASK;
+	writel(reg, &pll->pll_base);
+}
+
+static void enable_cpu_clock(int enable)
+{
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 clk;
+
+	/*
+	 * NOTE:
+	 * Regardless of whether the request is to enable or disable the CPU
+	 * clock, every processor in the CPU complex except the master (CPU 0)
+	 * will have it's clock stopped because the AVP only talks to the
+	 * master. The AVP does not know (nor does it need to know) that there
+	 * are multiple processors in the CPU complex.
+	 */
+
+	if (enable) {
+		/* Initialize PLLX */
+		init_pllx();
+
+		/* Wait until all clocks are stable */
+		udelay(PLL_STABILIZATION_DELAY);
+
+		writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
+		writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
+	}
+
+	/*
+	 * Read the register containing the individual CPU clock enables and
+	 * always stop the clock to CPU 1.
+	 */
+	clk = readl(&clkrst->crc_clk_cpu_cmplx);
+	clk |= 1 << CPU1_CLK_STP_SHIFT;
+
+	/* Stop/Unstop the CPU clock */
+	clk &= ~CPU0_CLK_STP_MASK;
+	clk |= !enable << CPU0_CLK_STP_SHIFT;
+	writel(clk, &clkrst->crc_clk_cpu_cmplx);
+
+	clock_enable(PERIPH_ID_CPU);
+}
+
+static int is_cpu_powered(void)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+	return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
+}
+
+static void remove_cpu_io_clamps(void)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	u32 reg;
+
+	/* Remove the clamps on the CPU I/O signals */
+	reg = readl(&pmc->pmc_remove_clamping);
+	reg |= CPU_CLMP;
+	writel(reg, &pmc->pmc_remove_clamping);
+
+	/* Give I/O signals time to stabilize */
+	udelay(IO_STABILIZATION_DELAY);
+}
+
+static void powerup_cpu(void)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	u32 reg;
+	int timeout = IO_STABILIZATION_DELAY;
+
+	if (!is_cpu_powered()) {
+		/* Toggle the CPU power state (OFF -> ON) */
+		reg = readl(&pmc->pmc_pwrgate_toggle);
+		reg &= PARTID_CP;
+		reg |= START_CP;
+		writel(reg, &pmc->pmc_pwrgate_toggle);
+
+		/* Wait for the power to come up */
+		while (!is_cpu_powered()) {
+			if (timeout-- == 0)
+				printf("CPU failed to power up!\n");
+			else
+				udelay(10);
+		}
+
+		/*
+		 * Remove the I/O clamps from CPU power partition.
+		 * Recommended only on a Warm boot, if the CPU partition gets
+		 * power gated. Shouldn't cause any harm when called after a
+		 * cold boot according to HW, probably just redundant.
+		 */
+		remove_cpu_io_clamps();
+	}
+}
+
 static void enable_cpu_power_rail(void)
 {
 	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
@@ -38,6 +173,49 @@ static void enable_cpu_power_rail(void)
 	udelay(3750);
 }

+static void reset_A9_cpu(int reset)
+{
+	/*
+	* NOTE:  Regardless of whether the request is to hold the CPU in reset
+	*        or take it out of reset, every processor in the CPU complex
+	*        except the master (CPU 0) will be held in reset because the
+	*        AVP only talks to the master. The AVP does not know that there
+	*        are multiple processors in the CPU complex.
+	*/
+
+	/* Hold CPU 1 in reset, and CPU 0 if asked */
+	reset_cmplx_set_enable(1, crc_rst_cpu | crc_rst_de | crc_rst_debug, 1);
+	reset_cmplx_set_enable(0, crc_rst_cpu | crc_rst_de | crc_rst_debug,
+			       reset);
+
+	/* Enable/Disable master CPU reset */
+	reset_set_enable(PERIPH_ID_CPU, reset);
+}
+
+static void clock_enable_coresight(int enable)
+{
+	u32 rst, src;
+
+	clock_set_enable(PERIPH_ID_CORESIGHT, enable);
+	reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
+
+	if (enable) {
+		/*
+		 * Put CoreSight on PLLP_OUT0 (216 MHz) and divide it down by
+		 *  1.5, giving an effective frequency of 144MHz.
+		 * Set PLLP_OUT0 [bits31:30 = 00], and use a 7.1 divisor
+		 *  (bits 7:0), so 00000001b == 1.5 (n+1 + .5)
+		 */
+		src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
+		clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
+
+		/* Unlock the CPU CoreSight interfaces */
+		rst = 0xC5ACCE55;
+		writel(rst, CSITE_CPU_DBG0_LAR);
+		writel(rst, CSITE_CPU_DBG1_LAR);
+	}
+}
+
 void start_cpu(u32 reset_vector)
 {
 	/* Enable VDD_CPU */
@@ -68,3 +246,13 @@ void start_cpu(u32 reset_vector)
 	/* Take the CPU out of reset */
 	reset_A9_cpu(0);
 }
+
+
+void halt_avp(void)
+{
+	for (;;) {
+		writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
+			| HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
+			FLOW_CTLR_HALT_COP_EVENTS);
+	}
+}
--- a/arch/arm/cpu/arm720t/tegra30/Makefile
+++ b/arch/arm/cpu/arm720t/tegra30/Makefile
@@ -1,41 +0,0 @@
-#
-# Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-y	+= cpu.o
-
-SRCS	:= $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
--- a/arch/arm/cpu/arm720t/tegra30/config.mk
+++ b/arch/arm/cpu/arm720t/tegra30/config.mk
@@ -1,19 +0,0 @@
-#
-# Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-#
-USE_PRIVATE_LIBGCC = yes
--- a/arch/arm/cpu/arm720t/tegra30/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra30/cpu.c
@@ -1,176 +0,0 @@
-/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/flow.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/pmc.h>
-#include <asm/arch-tegra/tegra_i2c.h>
-#include "../tegra-common/cpu.h"
-
-/* Tegra30-specific CPU init code */
-void tegra_i2c_ll_write_addr(uint addr, uint config)
-{
-	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
-
-	writel(addr, &reg->cmd_addr0);
-	writel(config, &reg->cnfg);
-}
-
-void tegra_i2c_ll_write_data(uint data, uint config)
-{
-	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
-
-	writel(data, &reg->cmd_data1);
-	writel(config, &reg->cnfg);
-}
-
-#define TPS65911_I2C_ADDR		0x5A
-#define TPS65911_VDDCTRL_OP_REG		0x28
-#define TPS65911_VDDCTRL_SR_REG		0x27
-#define TPS65911_VDDCTRL_OP_DATA	(0x2300 | TPS65911_VDDCTRL_OP_REG)
-#define TPS65911_VDDCTRL_SR_DATA	(0x0100 | TPS65911_VDDCTRL_SR_REG)
-#define I2C_SEND_2_BYTES		0x0A02
-
-static void enable_cpu_power_rail(void)
-{
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-	u32 reg;
-
-	debug("enable_cpu_power_rail entry\n");
-	reg = readl(&pmc->pmc_cntrl);
-	reg |= CPUPWRREQ_OE;
-	writel(reg, &pmc->pmc_cntrl);
-
-	/*
-	 * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
-	 * First set VDD to 1.4V, then enable the VDD regulator.
-	 */
-	tegra_i2c_ll_write_addr(TPS65911_I2C_ADDR, 2);
-	tegra_i2c_ll_write_data(TPS65911_VDDCTRL_OP_DATA, I2C_SEND_2_BYTES);
-	udelay(1000);
-	tegra_i2c_ll_write_data(TPS65911_VDDCTRL_SR_DATA, I2C_SEND_2_BYTES);
-	udelay(10 * 1000);
-}
-
-/**
- * The T30 requires some special clock initialization, including setting up
- * the dvc i2c, turning on mselect and selecting the G CPU cluster
- */
-void t30_init_clocks(void)
-{
-	struct clk_rst_ctlr *clkrst =
-			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-	struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
-	u32 val;
-
-	debug("t30_init_clocks entry\n");
-	/* Set active CPU cluster to G */
-	clrbits_le32(flow->cluster_control, 1 << 0);
-
-	/*
-	 * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run
-	 * at 108 MHz. This is glitch free as only the source is changed, no
-	 * special precaution needed.
-	 */
-	val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
-		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
-		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
-		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
-		(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
-	writel(val, &clkrst->crc_sclk_brst_pol);
-
-	writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
-
-	val = (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) |
-		(1 << CLK_SYS_RATE_AHB_RATE_SHIFT) |
-		(0 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT) |
-		(0 << CLK_SYS_RATE_APB_RATE_SHIFT);
-	writel(val, &clkrst->crc_clk_sys_rate);
-
-	/* Put i2c, mselect in reset and enable clocks */
-	reset_set_enable(PERIPH_ID_DVC_I2C, 1);
-	clock_set_enable(PERIPH_ID_DVC_I2C, 1);
-	reset_set_enable(PERIPH_ID_MSELECT, 1);
-	clock_set_enable(PERIPH_ID_MSELECT, 1);
-
-	/* Switch MSELECT clock to PLLP (00) and use a divisor of 2 */
-	clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, 2);
-
-	/*
-	 * Our high-level clock routines are not available prior to
-	 * relocation. We use the low-level functions which require a
-	 * hard-coded divisor. Use CLK_M with divide by (n + 1 = 17)
-	 */
-	clock_ll_set_source_divisor(PERIPH_ID_DVC_I2C, 3, 16);
-
-	/*
-	 * Give clocks time to stabilize, then take i2c and mselect out of
-	 * reset
-	 */
-	udelay(1000);
-	reset_set_enable(PERIPH_ID_DVC_I2C, 0);
-	reset_set_enable(PERIPH_ID_MSELECT, 0);
-}
-
-static void set_cpu_running(int run)
-{
-	struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
-
-	debug("set_cpu_running entry, run = %d\n", run);
-	writel(run ? FLOW_MODE_NONE : FLOW_MODE_STOP, &flow->halt_cpu_events);
-}
-
-void start_cpu(u32 reset_vector)
-{
-	debug("start_cpu entry, reset_vector = %x\n", reset_vector);
-	t30_init_clocks();
-
-	/* Enable VDD_CPU */
-	enable_cpu_power_rail();
-
-	set_cpu_running(0);
-
-	/* Hold the CPUs in reset */
-	reset_A9_cpu(1);
-
-	/* Disable the CPU clock */
-	enable_cpu_clock(0);
-
-	/* Enable CoreSight */
-	clock_enable_coresight(1);
-
-	/*
-	 * Set the entry point for CPU execution from reset,
-	 *  if it's a non-zero value.
-	 */
-	if (reset_vector)
-		writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
-
-	/* Enable the CPU clock */
-	enable_cpu_clock(1);
-
-	/* If the CPU doesn't already have power, power it up */
-	powerup_cpu();
-
-	/* Take the CPU out of reset */
-	reset_A9_cpu(0);
-
-	set_cpu_running(1);
-}
--- a/arch/arm/cpu/arm920t/a320/timer.c
+++ b/arch/arm/cpu/arm920t/a320/timer.c
@@ -31,14 +31,14 @@ DECLARE_GLOBAL_DATA_PTR;
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
 	tick *= CONFIG_SYS_HZ;
-	do_div(tick, gd->arch.timer_rate_hz);
+	do_div(tick, gd->timer_rate_hz);

 	return tick;
 }

 static inline unsigned long long usec_to_tick(unsigned long long usec)
 {
-	usec *= gd->arch.timer_rate_hz;
+	usec *= gd->timer_rate_hz;
 	do_div(usec, 1000000);

 	return usec;
@@ -74,8 +74,8 @@ int timer_init(void)
 	cr |= FTTMR010_TM3_ENABLE;
 	writel(cr, &tmr->cr);

-	gd->arch.timer_rate_hz = TIMER_CLOCK;
-	gd->arch.tbu = gd->arch.tbl = 0;
+	gd->timer_rate_hz = TIMER_CLOCK;
+	gd->tbu = gd->tbl = 0;

 	return 0;
 }
@@ -89,10 +89,10 @@ unsigned long long get_ticks(void)
 	ulong now = TIMER_LOAD_VAL - readl(&tmr->timer3_counter);

 	/* increment tbu if tbl has rolled over */
-	if (now < gd->arch.tbl)
-		gd->arch.tbu++;
-	gd->arch.tbl = now;
-	return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
+	if (now < gd->tbl)
+		gd->tbu++;
+	gd->tbl = now;
+	return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
 }

 void __udelay(unsigned long usec)
@@ -126,5 +126,5 @@ ulong get_timer(ulong base)
 */
 ulong get_tbclk(void)
 {
-	return gd->arch.timer_rate_hz;
+	return gd->timer_rate_hz;
 }
--- a/arch/arm/cpu/arm920t/at91/clock.c
+++ b/arch/arm/cpu/arm920t/at91/clock.c
@@ -29,11 +29,11 @@ static unsigned long at91_css_to_rate(unsigned long css)
 	case AT91_PMC_MCKR_CSS_SLOW:
 		return CONFIG_SYS_AT91_SLOW_CLOCK;
 	case AT91_PMC_MCKR_CSS_MAIN:
-		return gd->arch.main_clk_rate_hz;
+		return gd->main_clk_rate_hz;
 	case AT91_PMC_MCKR_CSS_PLLA:
-		return gd->arch.plla_rate_hz;
+		return gd->plla_rate_hz;
 	case AT91_PMC_MCKR_CSS_PLLB:
-		return gd->arch.pllb_rate_hz;
+		return gd->pllb_rate_hz;
 	}

 	return 0;
@@ -124,10 +124,10 @@ int at91_clock_init(unsigned long main_clock)
 		main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
 	}
 #endif
-	gd->arch.main_clk_rate_hz = main_clock;
+	gd->main_clk_rate_hz = main_clock;

 	/* report if PLLA is more than mildly overclocked */
-	gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
+	gd->plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));

 #ifdef CONFIG_USB_ATMEL
 	/*
@@ -136,10 +136,9 @@ int at91_clock_init(unsigned long main_clock)
 	 *
 	 * REVISIT:  assumes MCK doesn't derive from PLLB!
 	 */
-	gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
+	gd->at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
 			     AT91_PMC_PLLBR_USBDIV_2;
-	gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,
-					      gd->arch.at91_pllb_usb_init);
+	gd->pllb_rate_hz = at91_pll_rate(main_clock, gd->at91_pllb_usb_init);
 #endif

 	/*
@@ -147,14 +146,13 @@ int at91_clock_init(unsigned long main_clock)
 	 * For now, assume this parentage won't change.
 	 */
 	mckr = readl(&pmc->mckr);
-	gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
-	freq = gd->arch.mck_rate_hz;
+	gd->mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
+	freq = gd->mck_rate_hz;

 	freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2));	/* prescale */
 	/* mdiv */
-	gd->arch.mck_rate_hz = freq /
-			(1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
-	gd->arch.cpu_clk_rate_hz = freq;
+	gd->mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
+	gd->cpu_clk_rate_hz = freq;

 	return 0;
 }
--- a/arch/arm/cpu/arm920t/at91/timer.c
+++ b/arch/arm/cpu/arm920t/at91/timer.c
@@ -63,8 +63,8 @@ int timer_init(void)
 	writel(TIMER_LOAD_VAL, &tc->tc[0].rc);

 	writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
-	gd->arch.lastinc = 0;
-	gd->arch.tbl = 0;
+	gd->lastinc = 0;
+	gd->tbl = 0;

 	return 0;
 }
@@ -89,16 +89,16 @@ ulong get_timer_raw(void)

 	now = readl(&tc->tc[0].cv) & 0x0000ffff;

-	if (now >= gd->arch.lastinc) {
+	if (now >= gd->lastinc) {
 		/* normal mode */
-		gd->arch.tbl += now - gd->arch.lastinc;
+		gd->tbl += now - gd->lastinc;
 	} else {
 		/* we have an overflow ... */
-		gd->arch.tbl += now + TIMER_LOAD_VAL - gd->arch.lastinc;
+		gd->tbl += now + TIMER_LOAD_VAL - gd->lastinc;
 	}
-	gd->arch.lastinc = now;
+	gd->lastinc = now;

-	return gd->arch.tbl;
+	return gd->tbl;
 }

 ulong get_timer_masked(void)
--- a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
+++ b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
@@ -31,19 +31,18 @@ SECTIONS
 	. = ALIGN(4);
 	.text      :
 	{
-		*(.__image_copy_start)
-	  arch/arm/cpu/arm920t/start.o	(.text*)
+	  arch/arm/cpu/arm920t/start.o	(.text)
 		/* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */
 	  . = 0x1000;
 	  LONG(0x53555243)
-	  *(.text*)
+	  *(.text)
 	}

 	. = ALIGN(4);
-	.rodata : { *(.rodata*) }
+	.rodata : { *(.rodata) }

 	. = ALIGN(4);
-	.data : { *(.data*) }
+	.data : { *(.data) }

 	. = ALIGN(4);
 	.got : { *(.got) }
@@ -52,19 +51,13 @@ SECTIONS

 	. = ALIGN(4);
 	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
+	#include <u-boot.lst>
 	}

 	. = ALIGN(4);
-
-	.image_copy_end :
-	{
-		*(.__image_copy_end)
-	}
-
 	__bss_start = .;
-	.bss : { *(.bss*) }
-	__bss_end = .;
+	.bss : { *(.bss) }
+	__bss_end__ = .;

 	_end = .;
 }
--- a/arch/arm/cpu/arm920t/s3c24x0/timer.c
+++ b/arch/arm/cpu/arm920t/s3c24x0/timer.c
@@ -45,25 +45,25 @@ int timer_init(void)
 	/* use PWM Timer 4 because it has no output */
 	/* prescaler for Timer 4 is 16 */
 	writel(0x0f00, &timers->tcfg0);
-	if (gd->arch.tbu == 0) {
+	if (gd->tbu == 0) {
 		/*
 		 * for 10 ms clock period @ PCLK with 4 bit divider = 1/2
 		 * (default) and prescaler = 16. Should be 10390
 		 * @33.25MHz and 15625 @ 50 MHz
 		 */
-		gd->arch.tbu = get_PCLK() / (2 * 16 * 100);
-		gd->arch.timer_rate_hz = get_PCLK() / (2 * 16);
+		gd->tbu = get_PCLK() / (2 * 16 * 100);
+		gd->timer_rate_hz = get_PCLK() / (2 * 16);
 	}
 	/* load value for 10 ms timeout */
-	writel(gd->arch.tbu, &timers->tcntb4);
+	writel(gd->tbu, &timers->tcntb4);
 	/* auto load, manual update of timer 4 */
 	tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000;
 	writel(tmr, &timers->tcon);
 	/* auto load, start timer 4 */
 	tmr = (tmr & ~0x0700000) | 0x0500000;
 	writel(tmr, &timers->tcon);
-	gd->arch.lastinc = 0;
-	gd->arch.tbl = 0;
+	gd->lastinc = 0;
+	gd->tbl = 0;

 	return 0;
 }
@@ -82,7 +82,7 @@ void __udelay (unsigned long usec)
 	ulong start = get_ticks();

 	tmo = usec / 1000;
-	tmo *= (gd->arch.tbu * 100);
+	tmo *= (gd->tbu * 100);
 	tmo /= 1000;

 	while ((ulong) (get_ticks() - start) < tmo)
@@ -93,7 +93,7 @@ ulong get_timer_masked(void)
 {
 	ulong tmr = get_ticks();

-	return tmr / (gd->arch.timer_rate_hz / CONFIG_SYS_HZ);
+	return tmr / (gd->timer_rate_hz / CONFIG_SYS_HZ);
 }

 void udelay_masked(unsigned long usec)
@@ -104,10 +104,10 @@ void udelay_masked(unsigned long usec)

 	if (usec >= 1000) {
 		tmo = usec / 1000;
-		tmo *= (gd->arch.tbu * 100);
+		tmo *= (gd->tbu * 100);
 		tmo /= 1000;
 	} else {
-		tmo = usec * (gd->arch.tbu * 100);
+		tmo = usec * (gd->tbu * 100);
 		tmo /= (1000 * 1000);
 	}

@@ -128,16 +128,16 @@ unsigned long long get_ticks(void)
 	struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
 	ulong now = readl(&timers->tcnto4) & 0xffff;

-	if (gd->arch.lastinc >= now) {
+	if (gd->lastinc >= now) {
 		/* normal mode */
-		gd->arch.tbl += gd->arch.lastinc - now;
+		gd->tbl += gd->lastinc - now;
 	} else {
 		/* we have an overflow ... */
-		gd->arch.tbl += gd->arch.lastinc + gd->arch.tbu - now;
+		gd->tbl += gd->lastinc + gd->tbu - now;
 	}
-	gd->arch.lastinc = now;
+	gd->lastinc = now;

-	return gd->arch.tbl;
+	return gd->tbl;
 }

 /*
--- a/arch/arm/cpu/arm920t/start.S
+++ b/arch/arm/cpu/arm920t/start.S
@@ -73,11 +73,7 @@ _fiq:			.word fiq

 .globl _TEXT_BASE
 _TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
 	.word	CONFIG_SYS_TEXT_BASE
-#endif

 /*
 * These are defined in the board-specific linker script.
@@ -91,7 +87,7 @@ _bss_start_ofs:

 .globl _bss_end_ofs
 _bss_end_ofs:
-	.word __bss_end - _start
+	.word __bss_end__ - _start

 .globl _end_ofs
 _end_ofs:
@@ -190,6 +186,85 @@ copyex:

 /*------------------------------------------------------------------------------*/

+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ */
+	.globl	relocate_code
+relocate_code:
+	mov	r4, r0	/* save addr_sp */
+	mov	r5, r1	/* save addr of gd */
+	mov	r6, r2	/* save addr of destination */
+
+	adr	r0, _start
+	cmp	r0, r6
+	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
+	beq	relocate_done		/* skip relocation */
+	mov	r1, r6			/* r1 <- scratch for copy_loop */
+	ldr	r3, _bss_start_ofs
+	add	r2, r0, r3		/* r2 <- source end address	    */
+
+copy_loop:
+	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
+	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
+
+#ifndef CONFIG_SPL_BUILD
+	/*
+	 * fix .rel.dyn relocations
+	 */
+	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
+	sub	r9, r6, r0		/* r9 <- relocation offset */
+	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
+	add	r10, r10, r0		/* r10 <- sym table in FLASH */
+	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
+	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
+	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
+	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
+fixloop:
+	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
+	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
+	ldr	r1, [r2, #4]
+	and	r7, r1, #0xff
+	cmp	r7, #23			/* relative fixup? */
+	beq	fixrel
+	cmp	r7, #2			/* absolute fixup? */
+	beq	fixabs
+	/* ignore unknown type of fixup */
+	b	fixnext
+fixabs:
+	/* absolute fix: set location to (offset) symbol value */
+	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
+	add	r1, r10, r1		/* r1 <- address of symbol in table */
+	ldr	r1, [r1, #4]		/* r1 <- symbol value */
+	add	r1, r1, r9		/* r1 <- relocated sym addr */
+	b	fixnext
+fixrel:
+	/* relative fix: increase location by offset */
+	ldr	r1, [r0]
+	add	r1, r1, r9
+fixnext:
+	str	r1, [r0]
+	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
+	cmp	r2, r3
+	blo	fixloop
+#endif
+
+relocate_done:
+
+	mov	pc, lr
+
+_rel_dyn_start_ofs:
+	.word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+	.word __rel_dyn_end - _start
+_dynsym_start_ofs:
+	.word __dynsym_start - _start
+
 	.globl	c_runtime_cpu_setup
 c_runtime_cpu_setup:

--- a/arch/arm/cpu/arm925t/start.S
+++ b/arch/arm/cpu/arm925t/start.S
@@ -79,11 +79,7 @@ _fiq:			.word fiq

 .globl _TEXT_BASE
 _TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
 	.word	CONFIG_SYS_TEXT_BASE
-#endif

 /*
 * These are defined in the board-specific linker script.
@@ -97,7 +93,7 @@ _bss_start_ofs:

 .globl _bss_end_ofs
 _bss_end_ofs:
-	.word __bss_end - _start
+	.word __bss_end__ - _start

 .globl _end_ofs
 _end_ofs:
@@ -180,6 +176,85 @@ poll1:

 /*------------------------------------------------------------------------------*/

+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ */
+	.globl	relocate_code
+relocate_code:
+	mov	r4, r0	/* save addr_sp */
+	mov	r5, r1	/* save addr of gd */
+	mov	r6, r2	/* save addr of destination */
+
+	adr	r0, _start
+	cmp	r0, r6
+	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
+	beq	relocate_done		/* skip relocation */
+	mov	r1, r6			/* r1 <- scratch for copy_loop */
+	ldr	r3, _bss_start_ofs
+	add	r2, r0, r3		/* r2 <- source end address	    */
+
+copy_loop:
+	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
+	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
+
+#ifndef CONFIG_SPL_BUILD
+	/*
+	 * fix .rel.dyn relocations
+	 */
+	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
+	sub	r9, r6, r0		/* r9 <- relocation offset */
+	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
+	add	r10, r10, r0		/* r10 <- sym table in FLASH */
+	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
+	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
+	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
+	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
+fixloop:
+	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
+	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
+	ldr	r1, [r2, #4]
+	and	r7, r1, #0xff
+	cmp	r7, #23			/* relative fixup? */
+	beq	fixrel
+	cmp	r7, #2			/* absolute fixup? */
+	beq	fixabs
+	/* ignore unknown type of fixup */
+	b	fixnext
+fixabs:
+	/* absolute fix: set location to (offset) symbol value */
+	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
+	add	r1, r10, r1		/* r1 <- address of symbol in table */
+	ldr	r1, [r1, #4]		/* r1 <- symbol value */
+	add	r1, r1, r9		/* r1 <- relocated sym addr */
+	b	fixnext
+fixrel:
+	/* relative fix: increase location by offset */
+	ldr	r1, [r0]
+	add	r1, r1, r9
+fixnext:
+	str	r1, [r0]
+	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
+	cmp	r2, r3
+	blo	fixloop
+#endif
+
+relocate_done:
+
+	mov	pc, lr
+
+_rel_dyn_start_ofs:
+	.word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+	.word __rel_dyn_end - _start
+_dynsym_start_ofs:
+	.word __dynsym_start - _start
+
 	.globl	c_runtime_cpu_setup
 c_runtime_cpu_setup:

--- a/arch/arm/cpu/arm926ejs/armada100/timer.c
+++ b/arch/arm/cpu/arm926ejs/armada100/timer.c
@@ -61,7 +61,7 @@ struct armd1tmr_registers {
 #define	COUNT_RD_REQ		0x1

 DECLARE_GLOBAL_DATA_PTR;
-/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
+/* Using gd->tbu from timestamp and gd->tbl for lastdec */

 /* For preventing risk of instability in reading counter value,
 * first set read request to register cvwr and then read same
@@ -82,16 +82,16 @@ ulong get_timer_masked(void)
 {
 	ulong now = read_timer();

-	if (now >= gd->arch.tbl) {
+	if (now >= gd->tbl) {
 		/* normal mode */
-		gd->arch.tbu += now - gd->arch.tbl;
+		gd->tbu += now - gd->tbl;
 	} else {
 		/* we have an overflow ... */
-		gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
+		gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
 	}
-	gd->arch.tbl = now;
+	gd->tbl = now;

-	return gd->arch.tbu;
+	return gd->tbu;
 }

 ulong get_timer(ulong base)
@@ -135,9 +135,9 @@ int timer_init(void)

 	/* Enable timer 0 */
 	writel(0x1, &armd1timers->cer);
-	/* init the gd->arch.tbu and gd->arch.tbl value */
-	gd->arch.tbl = read_timer();
-	gd->arch.tbu = 0;
+	/* init the gd->tbu and gd->tbl value */
+	gd->tbl = read_timer();
+	gd->tbu = 0;

 	return 0;
 }
--- a/arch/arm/cpu/arm926ejs/at91/Makefile
+++ b/arch/arm/cpu/arm926ejs/at91/Makefile
@@ -35,7 +35,6 @@ COBJS-$(CONFIG_AT91SAM9263)	+= at91sam9263_devices.o
 COBJS-$(CONFIG_AT91SAM9RL)	+= at91sam9rl_devices.o
 COBJS-$(CONFIG_AT91SAM9M10G45)	+= at91sam9m10g45_devices.o
 COBJS-$(CONFIG_AT91SAM9G45)	+= at91sam9m10g45_devices.o
-COBJS-$(CONFIG_AT91SAM9N12)	+= at91sam9n12_devices.o
 COBJS-$(CONFIG_AT91SAM9X5)	+= at91sam9x5_devices.o
 COBJS-$(CONFIG_AT91_EFLASH)	+= eflash.o
 COBJS-$(CONFIG_AT91_LED)	+= led.o
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
@@ -203,10 +203,6 @@ void at91_macb_hw_init(void)
 #if defined(CONFIG_GENERIC_ATMEL_MCI)
 void at91_mci_hw_init(void)
 {
-	/* Enable mci clock */
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-	writel(1 << ATMEL_ID_MCI, &pmc->pcer);
-
 	at91_set_a_periph(AT91_PIO_PORTA, 8, 1);	/* MCCK */
 #if defined(CONFIG_ATMEL_MCI_PORTB)
 	at91_set_b_periph(AT91_PIO_PORTA, 1, 1);	/* MCCDB */
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c
@@ -1,177 +0,0 @@
-/*
- * (C) Copyright 2013 Atmel Corporation
- * Josh Wu <josh.wu@atmel.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pio.h>
-
-unsigned int has_lcdc()
-{
-	return 1;
-}
-
-void at91_serial0_hw_init(void)
-{
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 0, 1);		/* TXD0 */
-	at91_set_a_periph(AT91_PIO_PORTA, 1, 0);		/* RXD0 */
-	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 5, 1);		/* TXD1 */
-	at91_set_a_periph(AT91_PIO_PORTA, 6, 0);		/* RXD1 */
-	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 7, 1);		/* TXD2 */
-	at91_set_a_periph(AT91_PIO_PORTA, 8, 0);		/* RXD2 */
-	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
-}
-
-void at91_serial3_hw_init(void)
-{
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
-	at91_set_b_periph(AT91_PIO_PORTC, 22, 1);		/* TXD3 */
-	at91_set_b_periph(AT91_PIO_PORTC, 23, 0);		/* RXD3 */
-	writel(1 << ATMEL_ID_USART3, &pmc->pcer);
-}
-
-void at91_seriald_hw_init(void)
-{
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 10, 1);		/* DTXD */
-	at91_set_a_periph(AT91_PIO_PORTA, 9, 0);		/* DRXD */
-	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
-}
-
-#ifdef CONFIG_ATMEL_SPI
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 11, 0);	/* SPI0_MISO */
-	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* SPI0_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* SPI0_SPCK */
-
-	/* Enable clock */
-	writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
-
-	if (cs_mask & (1 << 0))
-		at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
-	if (cs_mask & (1 << 1))
-		at91_set_pio_output(AT91_PIO_PORTA, 7, 1);
-	if (cs_mask & (1 << 2))
-		at91_set_pio_output(AT91_PIO_PORTA, 1, 1);
-	if (cs_mask & (1 << 3))
-		at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
-}
-
-void at91_spi1_hw_init(unsigned long cs_mask)
-{
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
-	at91_set_b_periph(AT91_PIO_PORTA, 21, 0);	/* SPI1_MISO */
-	at91_set_b_periph(AT91_PIO_PORTA, 22, 0);	/* SPI1_MOSI */
-	at91_set_b_periph(AT91_PIO_PORTA, 23, 0);	/* SPI1_SPCK */
-
-	/* Enable clock */
-	writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
-
-	if (cs_mask & (1 << 0))
-		at91_set_pio_output(AT91_PIO_PORTA, 8, 1);
-	if (cs_mask & (1 << 1))
-		at91_set_pio_output(AT91_PIO_PORTA, 0, 1);
-	if (cs_mask & (1 << 2))
-		at91_set_pio_output(AT91_PIO_PORTA, 31, 1);
-	if (cs_mask & (1 << 3))
-		at91_set_pio_output(AT91_PIO_PORTA, 30, 1);
-}
-#endif
-
-void at91_mci_hw_init(void)
-{
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 17, 0);	/* MCCK */
-	at91_set_a_periph(AT91_PIO_PORTA, 16, 0);	/* MCCDA */
-	at91_set_a_periph(AT91_PIO_PORTA, 15, 0);	/* MCDA0 */
-	at91_set_a_periph(AT91_PIO_PORTA, 18, 0);	/* MCDA1 */
-	at91_set_a_periph(AT91_PIO_PORTA, 19, 0);	/* MCDA2 */
-	at91_set_a_periph(AT91_PIO_PORTA, 20, 0);	/* MCDA3 */
-
-	writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer);
-}
-
-#ifdef CONFIG_LCD
-void at91_lcd_hw_init(void)
-{
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
-	at91_set_a_periph(AT91_PIO_PORTC, 24, 0);	/* LCDDPWR */
-	at91_set_a_periph(AT91_PIO_PORTC, 26, 0);	/* LCDVSYNC */
-	at91_set_a_periph(AT91_PIO_PORTC, 27, 0);	/* LCDHSYNC */
-	at91_set_a_periph(AT91_PIO_PORTC, 28, 0);	/* LCDDOTCK */
-	at91_set_a_periph(AT91_PIO_PORTC, 29, 0);	/* LCDDEN */
-	at91_set_a_periph(AT91_PIO_PORTC, 30, 0);	/* LCDDOTCK */
-
-	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* LCDD0 */
-	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* LCDD1 */
-	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* LCDD2 */
-	at91_set_a_periph(AT91_PIO_PORTC, 3, 0);	/* LCDD3 */
-	at91_set_a_periph(AT91_PIO_PORTC, 4, 0);	/* LCDD4 */
-	at91_set_a_periph(AT91_PIO_PORTC, 5, 0);	/* LCDD5 */
-	at91_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* LCDD6 */
-	at91_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* LCDD7 */
-	at91_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* LCDD8 */
-	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* LCDD9 */
-	at91_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD10 */
-	at91_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD11 */
-	at91_set_a_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD12 */
-	at91_set_a_periph(AT91_PIO_PORTC, 13, 0);	/* LCDD13 */
-	at91_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD14 */
-	at91_set_a_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD15 */
-	at91_set_a_periph(AT91_PIO_PORTC, 16, 0);	/* LCDD16 */
-	at91_set_a_periph(AT91_PIO_PORTC, 17, 0);	/* LCDD17 */
-	at91_set_a_periph(AT91_PIO_PORTC, 18, 0);	/* LCDD18 */
-	at91_set_a_periph(AT91_PIO_PORTC, 19, 0);	/* LCDD19 */
-	at91_set_a_periph(AT91_PIO_PORTC, 20, 0);	/* LCDD20 */
-	at91_set_a_periph(AT91_PIO_PORTC, 21, 0);	/* LCDD21 */
-	at91_set_a_periph(AT91_PIO_PORTC, 22, 0);	/* LCDD22 */
-	at91_set_a_periph(AT91_PIO_PORTC, 23, 0);	/* LCDD23 */
-
-	writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
-}
-#endif
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
@@ -61,20 +61,20 @@ char *get_cpu_name()
 	if (cpu_is_at91sam9x5()) {
 		switch (extension_id) {
 		case ARCH_EXID_AT91SAM9G15:
-			return "AT91SAM9G15";
+			return CONFIG_SYS_AT91_G15_CPU_NAME;
 		case ARCH_EXID_AT91SAM9G25:
-			return "AT91SAM9G25";
+			return CONFIG_SYS_AT91_G25_CPU_NAME;
 		case ARCH_EXID_AT91SAM9G35:
-			return "AT91SAM9G35";
+			return CONFIG_SYS_AT91_G35_CPU_NAME;
 		case ARCH_EXID_AT91SAM9X25:
-			return "AT91SAM9X25";
+			return CONFIG_SYS_AT91_X25_CPU_NAME;
 		case ARCH_EXID_AT91SAM9X35:
-			return "AT91SAM9X35";
+			return CONFIG_SYS_AT91_X35_CPU_NAME;
 		default:
-			return "Unknown CPU type";
+			return CONFIG_SYS_AT91_UNKNOWN_CPU;
 		}
 	} else {
-		return "Unknown CPU type";
+		return CONFIG_SYS_AT91_UNKNOWN_CPU;
 	}
 }

@@ -246,14 +246,14 @@ void at91_macb_hw_init(void)
 #ifndef CONFIG_RMII
 	/* Only emac0 support MII */
 	if (has_emac0()) {
-		at91_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* ECRS */
-		at91_set_a_periph(AT91_PIO_PORTB, 17, 0);	/* ECOL */
-		at91_set_a_periph(AT91_PIO_PORTB, 13, 0);	/* ERX2 */
-		at91_set_a_periph(AT91_PIO_PORTB, 14, 0);	/* ERX3 */
-		at91_set_a_periph(AT91_PIO_PORTB, 15, 0);	/* ERXCK */
-		at91_set_a_periph(AT91_PIO_PORTB, 11, 0);	/* ETX2 */
-		at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* ETX3 */
-		at91_set_a_periph(AT91_PIO_PORTB, 8, 0);	/* ETXER */
+		at91_set_b_periph(AT91_PIO_PORTB, 16, 0);	/* ECRS */
+		at91_set_b_periph(AT91_PIO_PORTB, 17, 0);	/* ECOL */
+		at91_set_b_periph(AT91_PIO_PORTB, 13, 0);	/* ERX2 */
+		at91_set_b_periph(AT91_PIO_PORTB, 14, 0);	/* ERX3 */
+		at91_set_b_periph(AT91_PIO_PORTB, 15, 0);	/* ERXCK */
+		at91_set_b_periph(AT91_PIO_PORTB, 11, 0);	/* ETX2 */
+		at91_set_b_periph(AT91_PIO_PORTB, 12, 0);	/* ETX3 */
+		at91_set_b_periph(AT91_PIO_PORTB, 8, 0);	/* ETXER */
 	}
 #endif
 }
--- a/arch/arm/cpu/arm926ejs/at91/clock.c
+++ b/arch/arm/cpu/arm926ejs/at91/clock.c
@@ -29,11 +29,11 @@ static unsigned long at91_css_to_rate(unsigned long css)
 	case AT91_PMC_MCKR_CSS_SLOW:
 		return CONFIG_SYS_AT91_SLOW_CLOCK;
 	case AT91_PMC_MCKR_CSS_MAIN:
-		return gd->arch.main_clk_rate_hz;
+		return gd->main_clk_rate_hz;
 	case AT91_PMC_MCKR_CSS_PLLA:
-		return gd->arch.plla_rate_hz;
+		return gd->plla_rate_hz;
 	case AT91_PMC_MCKR_CSS_PLLB:
-		return gd->arch.pllb_rate_hz;
+		return gd->pllb_rate_hz;
 	}

 	return 0;
@@ -132,10 +132,10 @@ int at91_clock_init(unsigned long main_clock)
 		main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
 	}
 #endif
-	gd->arch.main_clk_rate_hz = main_clock;
+	gd->main_clk_rate_hz = main_clock;

 	/* report if PLLA is more than mildly overclocked */
-	gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
+	gd->plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));

 #ifdef CONFIG_USB_ATMEL
 	/*
@@ -144,10 +144,9 @@ int at91_clock_init(unsigned long main_clock)
 	 *
 	 * REVISIT:  assumes MCK doesn't derive from PLLB!
 	 */
-	gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
+	gd->at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
 			     AT91_PMC_PLLBR_USBDIV_2;
-	gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,
-					      gd->arch.at91_pllb_usb_init);
+	gd->pllb_rate_hz = at91_pll_rate(main_clock, gd->at91_pllb_usb_init);
 #endif

 	/*
@@ -156,37 +155,36 @@ int at91_clock_init(unsigned long main_clock)
 	 */
 	mckr = readl(&pmc->mckr);
 #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
-		|| defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
+		|| defined(CONFIG_AT91SAM9X5)
 	/* plla divisor by 2 */
-	gd->arch.plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
+	gd->plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
 #endif
-	gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
-	freq = gd->arch.mck_rate_hz;
+	gd->mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
+	freq = gd->mck_rate_hz;

 	freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2));	/* prescale */
 #if defined(CONFIG_AT91SAM9G20)
 	/* mdiv ; (x >> 7) = ((x >> 8) * 2) */
-	gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
+	gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
 		freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
 	if (mckr & AT91_PMC_MCKR_MDIV_MASK)
 		freq /= 2;			/* processor clock division */
 #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
-		|| defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
+		|| defined(CONFIG_AT91SAM9X5)
 	/* mdiv <==> divisor
 	 *  0   <==>   1
 	 *  1   <==>   2
 	 *  2   <==>   4
 	 *  3   <==>   3
 	 */
-	gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
+	gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
 		(AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
 		? freq / 3
 		: freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
 #else
-	gd->arch.mck_rate_hz = freq /
-			(1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
+	gd->mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
 #endif
-	gd->arch.cpu_clk_rate_hz = freq;
+	gd->cpu_clk_rate_hz = freq;

 	return 0;
 }
--- a/arch/arm/cpu/arm926ejs/at91/timer.c
+++ b/arch/arm/cpu/arm926ejs/at91/timer.c
@@ -52,14 +52,14 @@ DECLARE_GLOBAL_DATA_PTR;
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
 	tick *= CONFIG_SYS_HZ;
-	do_div(tick, gd->arch.timer_rate_hz);
+	do_div(tick, gd->timer_rate_hz);

 	return tick;
 }

 static inline unsigned long long usec_to_tick(unsigned long long usec)
 {
-	usec *= gd->arch.timer_rate_hz;
+	usec *= gd->timer_rate_hz;
 	do_div(usec, 1000000);

 	return usec;
@@ -79,8 +79,8 @@ int timer_init(void)
 	/* Enable PITC */
 	writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);

-	gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
-	gd->arch.tbu = gd->arch.tbl = 0;
+	gd->timer_rate_hz = gd->mck_rate_hz / 16;
+	gd->tbu = gd->tbl = 0;

 	return 0;
 }
@@ -95,10 +95,10 @@ unsigned long long get_ticks(void)
 	ulong now = readl(&pit->piir);

 	/* increment tbu if tbl has rolled over */
-	if (now < gd->arch.tbl)
-		gd->arch.tbu++;
-	gd->arch.tbl = now;
-	return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
+	if (now < gd->tbl)
+		gd->tbu++;
+	gd->tbl = now;
+	return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
 }

 void __udelay(unsigned long usec)
@@ -132,5 +132,5 @@ ulong get_timer(ulong base)
 */
 ulong get_tbclk(void)
 {
-	return gd->arch.timer_rate_hz;
+	return gd->timer_rate_hz;
 }
--- a/arch/arm/cpu/arm926ejs/config.mk
+++ b/arch/arm/cpu/arm926ejs/config.mk
@@ -33,11 +33,7 @@ PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-mali
 PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)

 ifneq ($(CONFIG_IMX_CONFIG),)
-ifdef CONFIG_SPL
-ifdef CONFIG_SPL_BUILD
-ALL-y	+= $(OBJTREE)/SPL
-endif
-else
+
 ALL-y	+= $(obj)u-boot.imx
-endif
+
 endif
--- a/arch/arm/cpu/arm926ejs/davinci/Makefile
+++ b/arch/arm/cpu/arm926ejs/davinci/Makefile
@@ -33,7 +33,6 @@ COBJS-$(CONFIG_SOC_DM355)	+= dm355.o
 COBJS-$(CONFIG_SOC_DM365)	+= dm365.o
 COBJS-$(CONFIG_SOC_DM644X)	+= dm644x.o
 COBJS-$(CONFIG_SOC_DM646X)	+= dm646x.o
-COBJS-$(CONFIG_SOC_DA830)	+= da830_pinmux.o
 COBJS-$(CONFIG_SOC_DA850)	+= da850_pinmux.o
 COBJS-$(CONFIG_DRIVER_TI_EMAC)	+= lxt972.o dp83848.o et1011c.o ksz8873.o

--- a/arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c
+++ b/arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c
@@ -1,151 +0,0 @@
-/*
- * Pinmux configurations for the DA830 SoCs
- *
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <asm/arch/davinci_misc.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/pinmux_defs.h>
-
-/* SPI0 pin muxer settings */
-const struct pinmux_config spi0_pins_base[] = {
-	{ pinmux(7), 1, 3 },  /* SPI0_SOMI */
-	{ pinmux(7), 1, 4 },  /* SPI0_SIMO */
-	{ pinmux(7), 1, 6 }   /* SPI0_CLK */
-};
-
-const struct pinmux_config spi0_pins_scs0[] = {
-	{ pinmux(7), 1, 7 }   /* SPI0_SCS[0] */
-};
-
-const struct pinmux_config spi0_pins_ena[] = {
-	{ pinmux(7), 1, 5 }   /* SPI0_ENA */
-};
-
-/* NAND pin muxer settings */
-const struct pinmux_config emifa_pins_cs0[] = {
-	{ pinmux(18), 1, 2 }   /* EMA_CS[0] */
-};
-
-const struct pinmux_config emifa_pins_cs2[] = {
-	{ pinmux(18), 1, 3 }   /* EMA_CS[2] */
-};
-
-const struct pinmux_config emifa_pins_cs3[] = {
-	{ pinmux(18), 1, 4 }   /* EMA_CS[3] */
-};
-
-#ifdef CONFIG_USE_NAND
-const struct pinmux_config emifa_pins[] = {
-	{ pinmux(13), 1, 6 },  /* EMA_D[0] */
-	{ pinmux(13), 1, 7 },  /* EMA_D[1] */
-	{ pinmux(14), 1, 0 },  /* EMA_D[2] */
-	{ pinmux(14), 1, 1 },  /* EMA_D[3] */
-	{ pinmux(14), 1, 2 },  /* EMA_D[4] */
-	{ pinmux(14), 1, 3 },  /* EMA_D[5] */
-	{ pinmux(14), 1, 4 },  /* EMA_D[6] */
-	{ pinmux(14), 1, 5 },  /* EMA_D[7] */
-	{ pinmux(14), 1, 6 },  /* EMA_D[8] */
-	{ pinmux(14), 1, 7 },  /* EMA_D[9] */
-	{ pinmux(15), 1, 0 },  /* EMA_D[10] */
-	{ pinmux(15), 1, 1 },  /* EMA_D[11] */
-	{ pinmux(15), 1, 2 },  /* EMA_D[12] */
-	{ pinmux(15), 1, 3 },  /* EMA_D[13] */
-	{ pinmux(15), 1, 4 },  /* EMA_D[14] */
-	{ pinmux(15), 1, 5 },  /* EMA_D[15] */
-	{ pinmux(15), 1, 6 },  /* EMA_A[0] */
-	{ pinmux(15), 1, 7 },  /* EMA_A[1] */
-	{ pinmux(16), 1, 0 },  /* EMA_A[2] */
-	{ pinmux(16), 1, 1 },  /* EMA_A[3] */
-	{ pinmux(16), 1, 2 },  /* EMA_A[4] */
-	{ pinmux(16), 1, 3 },  /* EMA_A[5] */
-	{ pinmux(16), 1, 4 },  /* EMA_A[6] */
-	{ pinmux(16), 1, 5 },  /* EMA_A[7] */
-	{ pinmux(16), 1, 6 },  /* EMA_A[8] */
-	{ pinmux(16), 1, 7 },  /* EMA_A[9] */
-	{ pinmux(17), 1, 0 },  /* EMA_A[10] */
-	{ pinmux(17), 1, 1 },  /* EMA_A[11] */
-	{ pinmux(17), 1, 2 },  /* EMA_A[12] */
-	{ pinmux(17), 1, 3 },  /* EMA_BA[1] */
-	{ pinmux(17), 1, 4 },  /* EMA_BA[0] */
-	{ pinmux(17), 1, 5 },  /* EMA_CLK */
-	{ pinmux(17), 1, 6 },  /* EMA_SDCKE */
-	{ pinmux(17), 1, 7 },  /* EMA_CAS */
-	{ pinmux(18), 1, 0 },  /* EMA_CAS */
-	{ pinmux(18), 1, 1 },  /* EMA_WE */
-	{ pinmux(18), 1, 5 },  /* EMA_OE */
-	{ pinmux(18), 1, 6 },  /* EMA_WE_DQM[1] */
-	{ pinmux(18), 1, 7 },  /* EMA_WE_DQM[0] */
-	{ pinmux(10), 1, 0 }   /* Tristate */
-};
-#endif
-
-/* EMAC PHY interface pins */
-const struct pinmux_config emac_pins_rmii[] = {
-	{ pinmux(10), 2, 1 },  /* RMII_TXD[0] */
-	{ pinmux(10), 2, 2 },  /* RMII_TXD[1] */
-	{ pinmux(10), 2, 3 },  /* RMII_TXEN */
-	{ pinmux(10), 2, 4 },  /* RMII_CRS_DV */
-	{ pinmux(10), 2, 5 },  /* RMII_RXD[0] */
-	{ pinmux(10), 2, 6 },  /* RMII_RXD[1] */
-	{ pinmux(10), 2, 7 }   /* RMII_RXER */
-};
-
-const struct pinmux_config emac_pins_mdio[] = {
-	{ pinmux(11), 2, 0 },  /* MDIO_CLK */
-	{ pinmux(11), 2, 1 }   /* MDIO_D */
-};
-
-const struct pinmux_config emac_pins_rmii_clk_source[] = {
-	{ pinmux(9), 0, 5 }    /* ref.clk from external source */
-};
-
-/* UART2 pin muxer settings */
-const struct pinmux_config uart2_pins_txrx[] = {
-	{ pinmux(8), 2, 7 },   /* UART2_RXD */
-	{ pinmux(9), 2, 0 }    /* UART2_TXD */
-};
-
-/* I2C0 pin muxer settings */
-const struct pinmux_config i2c0_pins[] = {
-	{ pinmux(8), 2, 3 },   /* I2C0_SDA */
-	{ pinmux(8), 2, 4 }    /* I2C0_SCL */
-};
-
-/* USB0_DRVVBUS pin muxer settings */
-const struct pinmux_config usb_pins[] = {
-	{ pinmux(9), 1, 1 }    /* USB0_DRVVBUS */
-};
-
-#ifdef CONFIG_DAVINCI_MMC
-/* MMC0 pin muxer settings */
-const struct pinmux_config mmc0_pins_8bit[] = {
-	{ pinmux(15), 2, 7 },  /* MMCSD0_CLK */
-	{ pinmux(16), 2, 0 },  /* MMCSD0_CMD */
-	{ pinmux(13), 2, 6 },  /* MMCSD0_DAT_0 */
-	{ pinmux(13), 2, 7 },  /* MMCSD0_DAT_1 */
-	{ pinmux(14), 2, 0 },  /* MMCSD0_DAT_2 */
-	{ pinmux(14), 2, 1 },  /* MMCSD0_DAT_3 */
-	{ pinmux(14), 2, 2 },  /* MMCSD0_DAT_4 */
-	{ pinmux(14), 2, 3 },  /* MMCSD0_DAT_5 */
-	{ pinmux(14), 2, 4 },  /* MMCSD0_DAT_6 */
-	{ pinmux(14), 2, 5 }   /* MMCSD0_DAT_7 */
-	/* DA830 supports 8-bit mode */
-};
-#endif
--- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
+++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
@@ -32,14 +32,6 @@
 #include <asm/arch/emif_defs.h>
 #include <asm/arch/pll_defs.h>

-void davinci_enable_uart0(void)
-{
-	lpsc_on(DAVINCI_LPSC_UART0);
-
-	/* Bringup UART0 out of reset */
-	REG(UART0_PWREMU_MGMT) = 0x00006001;
-}
-
 #if defined(CONFIG_SYS_DA850_PLL_INIT)
 void da850_waitloop(unsigned long loopcnt)
 {
--- a/arch/arm/cpu/arm926ejs/davinci/misc.c
+++ b/arch/arm/cpu/arm926ejs/davinci/misc.c
@@ -104,7 +104,7 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr)
 	int ret;

 	ret = eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr);
-	if (!ret) {
+	if (ret) {
 		/*
 		 * There is no MAC address in the environment, so we
 		 * initialize it from the value in the EEPROM.
@@ -115,7 +115,7 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr)
 		ret = !eth_setenv_enetaddr("ethaddr", rom_enetaddr);
 	}
 	if (!ret)
-		printf("Failed to set mac address from EEPROM: %d\n", ret);
+		printf("Failed to set mac address from EEPROM\n");
 }
 #endif	/* CONFIG_DRIVER_TI_EMAC */

--- a/arch/arm/cpu/arm926ejs/davinci/spl.c
+++ b/arch/arm/cpu/arm926ejs/davinci/spl.c
@@ -64,7 +64,7 @@ void board_init_f(ulong dummy)
 #endif

 	/* Third, we clear the BSS. */
-	memset(__bss_start, 0, __bss_end - __bss_start);
+	memset(__bss_start, 0, __bss_end__ - __bss_start);

 	/* Finally, setup gd and move to the next step. */
 	gd = &gdata;
--- a/arch/arm/cpu/arm926ejs/davinci/timer.c
+++ b/arch/arm/cpu/arm926ejs/davinci/timer.c
@@ -60,8 +60,8 @@ int timer_init(void)
 	writel(0x0, &timer->tim34);
 	writel(TIMER_LOAD_VAL, &timer->prd34);
 	writel(2 << 22, &timer->tcr);
-	gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
-	gd->arch.timer_reset_value = 0;
+	gd->timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
+	gd->timer_reset_value = 0;

 	return(0);
 }
@@ -74,28 +74,27 @@ unsigned long long get_ticks(void)
 	unsigned long now = readl(&timer->tim34);

 	/* increment tbu if tbl has rolled over */
-	if (now < gd->arch.tbl)
-		gd->arch.tbu++;
-	gd->arch.tbl = now;
+	if (now < gd->tbl)
+		gd->tbu++;
+	gd->tbl = now;

-	return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
+	return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
 }

 ulong get_timer(ulong base)
 {
 	unsigned long long timer_diff;

-	timer_diff = get_ticks() - gd->arch.timer_reset_value;
+	timer_diff = get_ticks() - gd->timer_reset_value;

-	return lldiv(timer_diff,
-		     (gd->arch.timer_rate_hz / CONFIG_SYS_HZ)) - base;
+	return lldiv(timer_diff, (gd->timer_rate_hz / CONFIG_SYS_HZ)) - base;
 }

 void __udelay(unsigned long usec)
 {
 	unsigned long long endtime;

-	endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz,
+	endtime = lldiv((unsigned long long)usec * gd->timer_rate_hz,
 			1000000UL);
 	endtime += get_ticks();

@@ -109,7 +108,7 @@ void __udelay(unsigned long usec)
 */
 ulong get_tbclk(void)
 {
-	return gd->arch.timer_rate_hz;
+	return gd->timer_rate_hz;
 }

 #ifdef CONFIG_HW_WATCHDOG
--- a/arch/arm/cpu/arm926ejs/kirkwood/timer.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/timer.c
@@ -86,8 +86,8 @@ struct kwtmr_registers *kwtmr_regs = (struct kwtmr_registers *)KW_TIMER_BASE;

 DECLARE_GLOBAL_DATA_PTR;

-#define timestamp gd->arch.tbl
-#define lastdec gd->arch.lastinc
+#define timestamp gd->tbl
+#define lastdec gd->lastinc

 ulong get_timer_masked(void)
 {
--- a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c
+++ b/arch/arm/cpu/arm926ejs/mb86r0x/timer.c
@@ -35,8 +35,8 @@

 DECLARE_GLOBAL_DATA_PTR;

-#define timestamp gd->arch.tbl
-#define lastdec gd->arch.lastinc
+#define timestamp gd->tbl
+#define lastdec gd->lastinc

 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
--- a/arch/arm/cpu/arm926ejs/mx25/generic.c
+++ b/arch/arm/cpu/arm926ejs/mx25/generic.c
@@ -27,6 +27,7 @@
 #include <netdev.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
+#include <asm/arch/imx25-pinmux.h>
 #include <asm/arch/clock.h>

 #ifdef CONFIG_FSL_ESDHC
@@ -228,9 +229,9 @@ int get_clocks(void)
 {
 #ifdef CONFIG_FSL_ESDHC
 #if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
-	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 #else
-	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
 #endif
 #endif
 	return 0;
@@ -247,7 +248,123 @@ int cpu_mmc_init(bd_t *bis)
 }
 #endif

+#ifdef CONFIG_MXC_UART
+void mx25_uart1_init_pins(void)
+{
+	struct iomuxc_mux_ctl *muxctl;
+	struct iomuxc_pad_ctl *padctl;
+	u32 inpadctl;
+	u32 outpadctl;
+	u32 muxmode0;
+
+	muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
+	padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
+	muxmode0 = MX25_PIN_MUX_MODE(0);
+	/*
+	 * set up input pins with hysteresis and 100K pull-ups
+	 */
+	inpadctl = MX25_PIN_PAD_CTL_HYS
+	    | MX25_PIN_PAD_CTL_PKE
+	    | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PU;
+
+	/*
+	 * set up output pins with 100K pull-downs
+	 * FIXME: need to revisit this
+	 *      PUE is ignored if PKE is not set
+	 *      so the right value here is likely
+	 *        0x0 for no pull up/down
+	 *      or
+	 *        0xc0 for 100k pull down
+	 */
+	outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
+
+	/* UART1 */
+	/* rxd */
+	writel(muxmode0, &muxctl->pad_uart1_rxd);
+	writel(inpadctl, &padctl->pad_uart1_rxd);
+
+	/* txd */
+	writel(muxmode0, &muxctl->pad_uart1_txd);
+	writel(outpadctl, &padctl->pad_uart1_txd);
+
+	/* rts */
+	writel(muxmode0, &muxctl->pad_uart1_rts);
+	writel(outpadctl, &padctl->pad_uart1_rts);
+
+	/* cts */
+	writel(muxmode0, &muxctl->pad_uart1_cts);
+	writel(inpadctl, &padctl->pad_uart1_cts);
+}
+#endif /* CONFIG_MXC_UART */
+
 #ifdef CONFIG_FEC_MXC
+void mx25_fec_init_pins(void)
+{
+	struct iomuxc_mux_ctl *muxctl;
+	struct iomuxc_pad_ctl *padctl;
+	u32 inpadctl_100kpd;
+	u32 inpadctl_22kpu;
+	u32 outpadctl;
+	u32 muxmode0;
+
+	muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
+	padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
+	muxmode0 = MX25_PIN_MUX_MODE(0);
+	inpadctl_100kpd = MX25_PIN_PAD_CTL_HYS
+	    | MX25_PIN_PAD_CTL_PKE
+	    | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
+	inpadctl_22kpu = MX25_PIN_PAD_CTL_HYS
+	    | MX25_PIN_PAD_CTL_PKE
+	    | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_22K_PU;
+	/*
+	 * set up output pins with 100K pull-downs
+	 * FIXME: need to revisit this
+	 *      PUE is ignored if PKE is not set
+	 *      so the right value here is likely
+	 *        0x0 for no pull
+	 *      or
+	 *        0xc0 for 100k pull down
+	 */
+	outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
+
+	/* FEC_TX_CLK */
+	writel(muxmode0, &muxctl->pad_fec_tx_clk);
+	writel(inpadctl_100kpd, &padctl->pad_fec_tx_clk);
+
+	/* FEC_RX_DV */
+	writel(muxmode0, &muxctl->pad_fec_rx_dv);
+	writel(inpadctl_100kpd, &padctl->pad_fec_rx_dv);
+
+	/* FEC_RDATA0 */
+	writel(muxmode0, &muxctl->pad_fec_rdata0);
+	writel(inpadctl_100kpd, &padctl->pad_fec_rdata0);
+
+	/* FEC_TDATA0 */
+	writel(muxmode0, &muxctl->pad_fec_tdata0);
+	writel(outpadctl, &padctl->pad_fec_tdata0);
+
+	/* FEC_TX_EN */
+	writel(muxmode0, &muxctl->pad_fec_tx_en);
+	writel(outpadctl, &padctl->pad_fec_tx_en);
+
+	/* FEC_MDC */
+	writel(muxmode0, &muxctl->pad_fec_mdc);
+	writel(outpadctl, &padctl->pad_fec_mdc);
+
+	/* FEC_MDIO */
+	writel(muxmode0, &muxctl->pad_fec_mdio);
+	writel(inpadctl_22kpu, &padctl->pad_fec_mdio);
+
+	/* FEC_RDATA1 */
+	writel(muxmode0, &muxctl->pad_fec_rdata1);
+	writel(inpadctl_100kpd, &padctl->pad_fec_rdata1);
+
+	/* FEC_TDATA1 */
+	writel(muxmode0, &muxctl->pad_fec_tdata1);
+	writel(outpadctl, &padctl->pad_fec_tdata1);
+
+}
+
 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 {
 	int i;
--- a/arch/arm/cpu/arm926ejs/mx25/timer.c
+++ b/arch/arm/cpu/arm926ejs/mx25/timer.c
@@ -44,8 +44,8 @@

 DECLARE_GLOBAL_DATA_PTR;

-#define timestamp	(gd->arch.tbl)
-#define lastinc		(gd->arch.lastinc)
+#define timestamp	(gd->tbl)
+#define lastinc		(gd->lastinc)

 /*
 * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
--- a/arch/arm/cpu/arm926ejs/mx27/generic.c
+++ b/arch/arm/cpu/arm926ejs/mx27/generic.c
@@ -159,8 +159,6 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 	switch (clk) {
 	case MXC_ARM_CLK:
 		return imx_get_armclk();
-	case MXC_I2C_CLK:
-		return imx_get_ahbclk()/2;
 	case MXC_UART_CLK:
 		return imx_get_perclk1();
 	case MXC_FEC_CLK:
@@ -382,11 +380,3 @@ void mx27_sd2_init_pins(void)

 }
 #endif /* CONFIG_MXC_MMC */
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-	/* Enable D-cache. I-cache is already enabled in start.S */
-	dcache_enable();
-}
-#endif /* CONFIG_SYS_DCACHE_OFF */
--- a/arch/arm/cpu/arm926ejs/mx27/timer.c
+++ b/arch/arm/cpu/arm926ejs/mx27/timer.c
@@ -45,8 +45,8 @@

 DECLARE_GLOBAL_DATA_PTR;

-#define timestamp	(gd->arch.tbl)
-#define lastinc		(gd->arch.lastinc)
+#define timestamp	(gd->tbl)
+#define lastinc		(gd->lastinc)

 /*
 * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
--- a/arch/arm/cpu/arm926ejs/mxs/Makefile
+++ b/arch/arm/cpu/arm926ejs/mxs/Makefile
@@ -40,16 +40,6 @@ all:	$(obj).depend $(LIB)
 $(LIB):	$(OBJS)
 	$(call cmd_link_o_target, $(OBJS))

-# Specify the target for use in elftosb call
-ELFTOSB_TARGET-$(CONFIG_MX23) = imx23
-ELFTOSB_TARGET-$(CONFIG_MX28) = imx28
-
-$(OBJTREE)/u-boot.bd: $(SRCTREE)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd
-	sed "s@OBJTREE@$(OBJTREE)@g" $^ > $@
-
-$(OBJTREE)/u-boot.sb: $(OBJTREE)/u-boot.bin $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/u-boot.bd
-		elftosb -zf $(ELFTOSB_TARGET-y) -c $(OBJTREE)/u-boot.bd -o $(OBJTREE)/u-boot.sb
-
 #########################################################################

 # defines $(obj).depend target
--- a/arch/arm/cpu/arm926ejs/mxs/clock.c
+++ b/arch/arm/cpu/arm926ejs/mxs/clock.c
@@ -1,5 +1,5 @@
 /*
- * Freescale i.MX23/i.MX28 clock setup code
+ * Freescale i.MX28 clock setup code
 *
 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
 * on behalf of DENX Software Engineering GmbH
@@ -32,25 +32,16 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>

-/*
- * The PLL frequency is 480MHz and XTAL frequency is 24MHz
- *   iMX23: datasheet section 4.2
- *   iMX28: datasheet section 10.2
- */
+/* The PLL frequency is always 480MHz, see section 10.2 in iMX28 datasheet. */
 #define	PLL_FREQ_KHZ	480000
 #define	PLL_FREQ_COEF	18
+/* The XTAL frequency is always 24MHz, see section 10.2 in iMX28 datasheet. */
 #define	XTAL_FREQ_KHZ	24000

 #define	PLL_FREQ_MHZ	(PLL_FREQ_KHZ / 1000)
 #define	XTAL_FREQ_MHZ	(XTAL_FREQ_KHZ / 1000)

-#if defined(CONFIG_MX23)
-#define MXC_SSPCLK_MAX MXC_SSPCLK0
-#elif defined(CONFIG_MX28)
-#define MXC_SSPCLK_MAX MXC_SSPCLK3
-#endif
-
-static uint32_t mxs_get_pclk(void)
+static uint32_t mx28_get_pclk(void)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@@ -82,7 +73,7 @@ static uint32_t mxs_get_pclk(void)
 	return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
 }

-static uint32_t mxs_get_hclk(void)
+static uint32_t mx28_get_hclk(void)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@@ -97,10 +88,10 @@ static uint32_t mxs_get_hclk(void)
 		return 0;

 	div = clkctrl & CLKCTRL_HBUS_DIV_MASK;
-	return mxs_get_pclk() / div;
+	return mx28_get_pclk() / div;
 }

-static uint32_t mxs_get_emiclk(void)
+static uint32_t mx28_get_emiclk(void)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@@ -125,17 +116,11 @@ static uint32_t mxs_get_emiclk(void)
 	return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
 }

-static uint32_t mxs_get_gpmiclk(void)
+static uint32_t mx28_get_gpmiclk(void)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
-#if defined(CONFIG_MX23)
-	uint8_t *reg =
-		&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU];
-#elif defined(CONFIG_MX28)
-	uint8_t *reg =
-		&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI];
-#endif
+
 	uint32_t clkctrl, clkseq, div;
 	uint8_t clkfrac, frac;

@@ -149,7 +134,7 @@ static uint32_t mxs_get_gpmiclk(void)
 	}

 	/* REF Path */
-	clkfrac = readb(reg);
+	clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI]);
 	frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
 	div = clkctrl & CLKCTRL_GPMI_DIV_MASK;
 	return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
@@ -158,7 +143,7 @@ static uint32_t mxs_get_gpmiclk(void)
 /*
 * Set IO clock frequency, in kHz
 */
-void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq)
+void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@@ -191,7 +176,7 @@ void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq)
 /*
 * Get IO clock, returns IO clock in kHz
 */
-static uint32_t mxs_get_ioclk(enum mxs_ioclock io)
+static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@@ -212,13 +197,13 @@ static uint32_t mxs_get_ioclk(enum mxs_ioclock io)
 /*
 * Configure SSP clock frequency, in kHz
 */
-void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
+void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 	uint32_t clk, clkreg;

-	if (ssp > MXC_SSPCLK_MAX)
+	if (ssp > MXC_SSPCLK3)
 		return;

 	clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
@@ -231,7 +216,7 @@ void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
 	if (xtal)
 		clk = XTAL_FREQ_KHZ;
 	else
-		clk = mxs_get_ioclk(ssp >> 1);
+		clk = mx28_get_ioclk(ssp >> 1);

 	if (freq > clk)
 		return;
@@ -256,14 +241,14 @@ void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
 /*
 * Return SSP frequency, in kHz
 */
-static uint32_t mxs_get_sspclk(enum mxs_sspclock ssp)
+static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 	uint32_t clkreg;
 	uint32_t clk, tmp;

-	if (ssp > MXC_SSPCLK_MAX)
+	if (ssp > MXC_SSPCLK3)
 		return 0;

 	tmp = readl(&clkctrl_regs->hw_clkctrl_clkseq);
@@ -278,7 +263,7 @@ static uint32_t mxs_get_sspclk(enum mxs_sspclock ssp)
 	if (tmp == 0)
 		return 0;

-	clk = mxs_get_ioclk(ssp >> 1);
+	clk = mx28_get_ioclk(ssp >> 1);

 	return clk / tmp;
 }
@@ -286,15 +271,14 @@ static uint32_t mxs_get_sspclk(enum mxs_sspclock ssp)
 /*
 * Set SSP/MMC bus frequency, in kHz)
 */
-void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq)
+void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq)
 {
 	struct mxs_ssp_regs *ssp_regs;
-	const enum mxs_sspclock clk = mxs_ssp_clock_by_bus(bus);
-	const uint32_t sspclk = mxs_get_sspclk(clk);
+	const uint32_t sspclk = mx28_get_sspclk(bus);
 	uint32_t reg;
 	uint32_t divide, rate, tgtclk;

-	ssp_regs = mxs_ssp_regs_by_bus(bus);
+	ssp_regs = (struct mxs_ssp_regs *)(MXS_SSP0_BASE + (bus * 0x2000));

 	/*
 	 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
@@ -325,127 +309,32 @@ void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq)
 		bus, tgtclk, freq);
 }

-void mxs_set_lcdclk(uint32_t freq)
-{
-	struct mxs_clkctrl_regs *clkctrl_regs =
-		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
-	uint32_t fp, x, k_rest, k_best, x_best, tk;
-	int32_t k_best_l = 999, k_best_t = 0, x_best_l = 0xff, x_best_t = 0xff;
-
-	if (freq == 0)
-		return;
-
-#if defined(CONFIG_MX23)
-	writel(CLKCTRL_CLKSEQ_BYPASS_PIX, &clkctrl_regs->hw_clkctrl_clkseq_clr);
-#elif defined(CONFIG_MX28)
-	writel(CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF, &clkctrl_regs->hw_clkctrl_clkseq_clr);
-#endif
-
-	/*
-	 *             /               18 \     1       1
-	 * freq kHz = | 480000000 Hz * --  | * --- * ------
-	 *             \                x /     k     1000
-	 *
-	 *      480000000 Hz   18
-	 *      ------------ * --
-	 *        freq kHz      x
-	 * k = -------------------
-	 *             1000
-	 */
-
-	fp = ((PLL_FREQ_KHZ * 1000) / freq) * 18;
-
-	for (x = 18; x <= 35; x++) {
-		tk = fp / x;
-		if ((tk / 1000 == 0) || (tk / 1000 > 255))
-			continue;
-
-		k_rest = tk % 1000;
-
-		if (k_rest < (k_best_l % 1000)) {
-			k_best_l = tk;
-			x_best_l = x;
-		}
-
-		if (k_rest > (k_best_t % 1000)) {
-			k_best_t = tk;
-			x_best_t = x;
-		}
-	}
-
-	if (1000 - (k_best_t % 1000) > (k_best_l % 1000)) {
-		k_best = k_best_l;
-		x_best = x_best_l;
-	} else {
-		k_best = k_best_t;
-		x_best = x_best_t;
-	}
-
-	k_best /= 1000;
-
-#if defined(CONFIG_MX23)
-	writeb(CLKCTRL_FRAC_CLKGATE,
-		&clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_PIX]);
-	writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK),
-		&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_PIX]);
-	writeb(CLKCTRL_FRAC_CLKGATE,
-		&clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_PIX]);
-
-	writel(CLKCTRL_PIX_CLKGATE,
-		&clkctrl_regs->hw_clkctrl_pix_set);
-	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_pix,
-			CLKCTRL_PIX_DIV_MASK | CLKCTRL_PIX_CLKGATE,
-			k_best << CLKCTRL_PIX_DIV_OFFSET);
-
-	while (readl(&clkctrl_regs->hw_clkctrl_pix) & CLKCTRL_PIX_BUSY)
-		;
-#elif defined(CONFIG_MX28)
-	writeb(CLKCTRL_FRAC_CLKGATE,
-		&clkctrl_regs->hw_clkctrl_frac1_set[CLKCTRL_FRAC1_PIX]);
-	writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK),
-		&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_PIX]);
-	writeb(CLKCTRL_FRAC_CLKGATE,
-		&clkctrl_regs->hw_clkctrl_frac1_clr[CLKCTRL_FRAC1_PIX]);
-
-	writel(CLKCTRL_DIS_LCDIF_CLKGATE,
-		&clkctrl_regs->hw_clkctrl_lcdif_set);
-	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_lcdif,
-			CLKCTRL_DIS_LCDIF_DIV_MASK | CLKCTRL_DIS_LCDIF_CLKGATE,
-			k_best << CLKCTRL_DIS_LCDIF_DIV_OFFSET);
-
-	while (readl(&clkctrl_regs->hw_clkctrl_lcdif) & CLKCTRL_DIS_LCDIF_BUSY)
-		;
-#endif
-}
-
 uint32_t mxc_get_clock(enum mxc_clock clk)
 {
 	switch (clk) {
 	case MXC_ARM_CLK:
-		return mxs_get_pclk() * 1000000;
+		return mx28_get_pclk() * 1000000;
 	case MXC_GPMI_CLK:
-		return mxs_get_gpmiclk() * 1000000;
+		return mx28_get_gpmiclk() * 1000000;
 	case MXC_AHB_CLK:
 	case MXC_IPG_CLK:
-		return mxs_get_hclk() * 1000000;
+		return mx28_get_hclk() * 1000000;
 	case MXC_EMI_CLK:
-		return mxs_get_emiclk();
+		return mx28_get_emiclk();
 	case MXC_IO0_CLK:
-		return mxs_get_ioclk(MXC_IOCLK0);
+		return mx28_get_ioclk(MXC_IOCLK0);
 	case MXC_IO1_CLK:
-		return mxs_get_ioclk(MXC_IOCLK1);
+		return mx28_get_ioclk(MXC_IOCLK1);
+	case MXC_SSP0_CLK:
+		return mx28_get_sspclk(MXC_SSPCLK0);
+	case MXC_SSP1_CLK:
+		return mx28_get_sspclk(MXC_SSPCLK1);
+	case MXC_SSP2_CLK:
+		return mx28_get_sspclk(MXC_SSPCLK2);
+	case MXC_SSP3_CLK:
+		return mx28_get_sspclk(MXC_SSPCLK3);
 	case MXC_XTAL_CLK:
 		return XTAL_FREQ_KHZ * 1000;
-	case MXC_SSP0_CLK:
-		return mxs_get_sspclk(MXC_SSPCLK0);
-#ifdef CONFIG_MX28
-	case MXC_SSP1_CLK:
-		return mxs_get_sspclk(MXC_SSPCLK1);
-	case MXC_SSP2_CLK:
-		return mxs_get_sspclk(MXC_SSPCLK2);
-	case MXC_SSP3_CLK:
-		return mxs_get_sspclk(MXC_SSPCLK3);
-#endif
 	}

 	return 0;
--- a/arch/arm/cpu/arm926ejs/mxs/mxs.c
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c
@@ -1,5 +1,5 @@
 /*
- * Freescale i.MX23/i.MX28 common code
+ * Freescale i.MX28 common code
 *
 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
 * on behalf of DENX Software Engineering GmbH
@@ -30,15 +30,20 @@
 #include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
-#include <asm/imx-common/dma.h>
+#include <asm/arch/dma.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/sys_proto.h>
-#include <linux/compiler.h>

 DECLARE_GLOBAL_DATA_PTR;

+/* 1 second delay should be plenty of time for block reset. */
+#define	RESET_MAX_TIMEOUT	1000000
+
+#define	MXS_BLOCK_SFTRST	(1 << 31)
+#define	MXS_BLOCK_CLKGATE	(1 << 30)
+
 /* Lowlevel init isn't used on i.MX28, so just have a dummy here */
 inline void lowlevel_init(void) {}

@@ -76,32 +81,70 @@ void enable_caches(void)
 #endif
 }

-/*
- * This function will craft a jumptable at 0x0 which will redirect interrupt
- * vectoring to proper location of U-Boot in RAM.
- *
- * The structure of the jumptable will be as follows:
- *  ldr pc, [pc, #0x18] ..... for each vector, thus repeated 8 times
- *  <destination address> ... for each previous ldr, thus also repeated 8 times
- *
- * The "ldr pc, [pc, #0x18]" instruction above loads address from memory at
- * offset 0x18 from current value of PC register. Note that PC is already
- * incremented by 4 when computing the offset, so the effective offset is
- * actually 0x20, this the associated <destination address>. Loading the PC
- * register with an address performs a jump to that address.
- */
+int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
+								int timeout)
+{
+	while (--timeout) {
+		if ((readl(&reg->reg) & mask) == mask)
+			break;
+		udelay(1);
+	}
+
+	return !timeout;
+}
+
+int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
+								int timeout)
+{
+	while (--timeout) {
+		if ((readl(&reg->reg) & mask) == 0)
+			break;
+		udelay(1);
+	}
+
+	return !timeout;
+}
+
+int mxs_reset_block(struct mxs_register_32 *reg)
+{
+	/* Clear SFTRST */
+	writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
+
+	if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
+		return 1;
+
+	/* Clear CLKGATE */
+	writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
+
+	/* Set SFTRST */
+	writel(MXS_BLOCK_SFTRST, &reg->reg_set);
+
+	/* Wait for CLKGATE being set */
+	if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
+		return 1;
+
+	/* Clear SFTRST */
+	writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
+
+	if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
+		return 1;
+
+	/* Clear CLKGATE */
+	writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
+
+	if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
+		return 1;
+
+	return 0;
+}
+
 void mx28_fixup_vt(uint32_t start_addr)
 {
-	/* ldr pc, [pc, #0x18] */
-	const uint32_t ldr_pc = 0xe59ff018;
-	/* Jumptable location is 0x0 */
-	uint32_t *vt = (uint32_t *)0x0;
+	uint32_t *vt = (uint32_t *)0x20;
 	int i;

-	for (i = 0; i < 8; i++) {
-		vt[i] = ldr_pc;
-		vt[i + 8] = start_addr + (4 * i);
-	}
+	for (i = 0; i < 8; i++)
+		vt[i] = start_addr + (4 * i);
 }

 #ifdef	CONFIG_ARCH_MISC_INIT
@@ -153,8 +196,6 @@ static const char *get_cpu_type(void)
 		(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;

 	switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
-	case HW_DIGCTL_CHIPID_MX23:
-		return "23";
 	case HW_DIGCTL_CHIPID_MX28:
 		return "28";
 	default:
@@ -169,21 +210,6 @@ static const char *get_cpu_rev(void)
 	uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF;

 	switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
-	case HW_DIGCTL_CHIPID_MX23:
-		switch (rev) {
-		case 0x0:
-			return "1.0";
-		case 0x1:
-			return "1.1";
-		case 0x2:
-			return "1.2";
-		case 0x3:
-			return "1.3";
-		case 0x4:
-			return "1.4";
-		default:
-			return "??";
-		}
 	case HW_DIGCTL_CHIPID_MX28:
 		switch (rev) {
 		case 0x1:
@@ -250,7 +276,7 @@ int cpu_eth_init(bd_t *bis)
 }
 #endif

-__weak void mx28_adjust_mac(int dev_id, unsigned char *mac)
+static void __mx28_adjust_mac(int dev_id, unsigned char *mac)
 {
 	mac[0] = 0x00;
 	mac[1] = 0x04; /* Use FSL vendor MAC address by default */
@@ -259,6 +285,9 @@ __weak void mx28_adjust_mac(int dev_id, unsigned char *mac)
 		mac[5] += 1;
 }

+void mx28_adjust_mac(int dev_id, unsigned char *mac)
+	__attribute__((weak, alias("__mx28_adjust_mac")));
+
 #ifdef	CONFIG_MX28_FEC_MAC_IN_OCOTP

 #define	MXS_OCOTP_MAX_TIMEOUT	1000000
--- a/arch/arm/cpu/arm926ejs/mxs/mxs_init.h
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs_init.h
@@ -30,7 +30,7 @@ void early_delay(int delay);

 void mxs_power_init(void);

-#ifdef	CONFIG_SPL_MXS_PSWITCH_WAIT
+#ifdef	CONFIG_SPL_MX28_PSWITCH_WAIT
 void mxs_power_wait_pswitch(void);
 #else
 static inline void mxs_power_wait_pswitch(void) { }
--- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
@@ -51,21 +51,12 @@ void early_delay(int delay)

 #define	MUX_CONFIG_BOOTMODE_PAD	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
 static const iomux_cfg_t iomux_boot[] = {
-#if defined(CONFIG_MX23)
-	MX23_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD,
-	MX23_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD,
-	MX23_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD,
-	MX23_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD,
-	MX23_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD,
-	MX23_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
-#elif defined(CONFIG_MX28)
 	MX28_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD,
 	MX28_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD,
 	MX28_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD,
 	MX28_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD,
 	MX28_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD,
 	MX28_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
-#endif
 };

 static uint8_t mxs_get_bootmode_index(void)
@@ -77,21 +68,6 @@ static uint8_t mxs_get_bootmode_index(void)
 	/* Setup IOMUX of bootmode pads to GPIO */
 	mxs_iomux_setup_multiple_pads(iomux_boot, ARRAY_SIZE(iomux_boot));

-#if defined(CONFIG_MX23)
-	/* Setup bootmode pins as GPIO input */
-	gpio_direction_input(MX23_PAD_LCD_D00__GPIO_1_0);
-	gpio_direction_input(MX23_PAD_LCD_D01__GPIO_1_1);
-	gpio_direction_input(MX23_PAD_LCD_D02__GPIO_1_2);
-	gpio_direction_input(MX23_PAD_LCD_D03__GPIO_1_3);
-	gpio_direction_input(MX23_PAD_LCD_D05__GPIO_1_5);
-
-	/* Read bootmode pads */
-	bootmode |= (gpio_get_value(MX23_PAD_LCD_D00__GPIO_1_0) ? 1 : 0) << 0;
-	bootmode |= (gpio_get_value(MX23_PAD_LCD_D01__GPIO_1_1) ? 1 : 0) << 1;
-	bootmode |= (gpio_get_value(MX23_PAD_LCD_D02__GPIO_1_2) ? 1 : 0) << 2;
-	bootmode |= (gpio_get_value(MX23_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3;
-	bootmode |= (gpio_get_value(MX23_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5;
-#elif defined(CONFIG_MX28)
 	/* Setup bootmode pins as GPIO input */
 	gpio_direction_input(MX28_PAD_LCD_D00__GPIO_1_0);
 	gpio_direction_input(MX28_PAD_LCD_D01__GPIO_1_1);
@@ -107,7 +83,6 @@ static uint8_t mxs_get_bootmode_index(void)
 	bootmode |= (gpio_get_value(MX28_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3;
 	bootmode |= (gpio_get_value(MX28_PAD_LCD_D04__GPIO_1_4) ? 1 : 0) << 4;
 	bootmode |= (gpio_get_value(MX28_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5;
-#endif

 	for (i = 0; i < ARRAY_SIZE(mxs_boot_modes); i++) {
 		masked = bootmode & mxs_boot_modes[i].boot_mask;
@@ -148,3 +123,10 @@ inline void board_init_r(gd_t *id, ulong dest_addr)
 	for (;;)
 		;
 }
+
+void hang(void) __attribute__ ((noreturn));
+void hang(void)
+{
+	for (;;)
+		;
+}
--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
@@ -27,8 +27,6 @@
 #include <config.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-#include <linux/compiler.h>

 #include "mxs_init.h"

@@ -46,17 +44,17 @@ static uint32_t dram_vals[] = {
 	0x00000000, 0x00000000, 0x00010101, 0x01010101,
 	0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101,
 	0x00000100, 0x00000100, 0x00000000, 0x00000002,
-	0x01010000, 0x07080403, 0x06005003, 0x0a0000c8,
-	0x02009c40, 0x0002030c, 0x0036a609, 0x031a0612,
+	0x01010000, 0x05060302, 0x06005003, 0x0a0000c8,
+	0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612,
 	0x02030202, 0x00c8001c, 0x00000000, 0x00000000,
 	0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
 	0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
 	0x00000003, 0x00000000, 0x00000000, 0x00000000,
 	0x00000000, 0x00000000, 0x00000000, 0x00000000,
 	0x00000000, 0x00000000, 0x00000612, 0x01000F02,
-	0x06120612, 0x00000200, 0x00020007, 0xf4004a27,
-	0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07000300,
-	0x07000300, 0x07400300, 0x07400300, 0x00000005,
+	0x06120612, 0x00000200, 0x00020007, 0xf5014b27,
+	0xf5014b27, 0xf5014b27, 0xf5014b27, 0x07000300,
+	0x07000300, 0x07000300, 0x07000300, 0x00000006,
 	0x00000000, 0x00000000, 0x01000000, 0x01020408,
 	0x08040201, 0x000f1133, 0x00000000, 0x00001f04,
 	0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
@@ -77,40 +75,25 @@ static uint32_t dram_vals[] = {
 	0x00000000, 0x00000000, 0x00000000, 0x00000000,
 	0x00000000, 0x00000000, 0x00000000, 0x00000000,
 	0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00010000, 0x00030404,
-	0x00000003, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00010000, 0x00020304,
+	0x00000004, 0x00000000, 0x00000000, 0x00000000,
 	0x00000000, 0x00000000, 0x00000000, 0x01010000,
 	0x01000000, 0x03030000, 0x00010303, 0x01020202,
 	0x00000000, 0x02040303, 0x21002103, 0x00061200,
-	0x06120612, 0x04420442, 0x04420442, 0x00040004,
+	0x06120612, 0x04320432, 0x04320432, 0x00040004,
 	0x00040004, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0xffffffff
-
-/*
- * i.MX23 DDR at 133MHz
- */
-#elif defined(CONFIG_MX23)
-	0x01010001, 0x00010100, 0x01000101, 0x00000001,
-	0x00000101, 0x00000000, 0x00010000, 0x01000001,
-	0x00000000, 0x00000001, 0x07000200, 0x00070202,
-	0x02020000, 0x04040a01, 0x00000201, 0x02040000,
-	0x02000000, 0x19000f08, 0x0d0d0000, 0x02021313,
-	0x02061521, 0x0000000a, 0x00080008, 0x00200020,
-	0x00200020, 0x00200020, 0x000003f7, 0x00000000,
-	0x00000000, 0x00000020, 0x00000020, 0x00c80000,
-	0x000a23cd, 0x000000c8, 0x00006665, 0x00000000,
-	0x00000101, 0x00040001, 0x00000000, 0x00000000,
-	0x00010000
+	0x00000000, 0x00010001
 #else
 #error Unsupported memory initialization
 #endif
 };

-__weak void mxs_adjust_memory_params(uint32_t *dram_vals)
+void __mxs_adjust_memory_params(uint32_t *dram_vals)
 {
 }
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+	__attribute__((weak, alias("__mxs_adjust_memory_params")));

-#ifdef CONFIG_MX28
 static void initialize_dram_values(void)
 {
 	int i;
@@ -120,54 +103,18 @@ static void initialize_dram_values(void)
 	for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
 		writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
 }
-#else
-static void initialize_dram_values(void)
-{
-	int i;
-
-	mxs_adjust_memory_params(dram_vals);
-
-	/*
-	 * HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as
-	 * per FSL bootlets code.
-	 *
-	 * mx23 Reference Manual marks HW_DRAM_CTL27 and HW_DRAM_CTL28 as
-	 * "reserved".
-	 * HW_DRAM_CTL8 is setup as the last element.
-	 * So skip the initialization of these HW_DRAM_CTL registers.
-	 */
-	for (i = 0; i < ARRAY_SIZE(dram_vals); i++) {
-		if (i == 8 || i == 27 || i == 28 || i == 35)
-			continue;
-		writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
-	}
-
-	/*
-	 * Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last
-	 * element to be set
-	 */
-	writel((1 << 24), MXS_DRAM_BASE + (4 * 8));
-}
-#endif

 static void mxs_mem_init_clock(void)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
-#if defined(CONFIG_MX23)
-	/* Fractional divider for ref_emi is 33 ; 480 * 18 / 33 = 266MHz */
-	const unsigned char divider = 33;
-#elif defined(CONFIG_MX28)
-	/* Fractional divider for ref_emi is 21 ; 480 * 18 / 21 = 411MHz */
-	const unsigned char divider = 21;
-#endif

 	/* Gate EMI clock */
 	writeb(CLKCTRL_FRAC_CLKGATE,
 		&clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]);

-	/* Set fractional divider for ref_emi */
-	writeb(CLKCTRL_FRAC_CLKGATE | (divider & CLKCTRL_FRAC_FRAC_MASK),
+	/* Set fractional divider for ref_emi to 480 * 18 / 21 = 411MHz */
+	writeb(CLKCTRL_FRAC_CLKGATE | (21 & CLKCTRL_FRAC_FRAC_MASK),
 		&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]);

 	/* Ungate EMI clock */
@@ -250,55 +197,10 @@ uint32_t mxs_mem_get_size(void)
 	return sz;
 }

-#ifdef CONFIG_MX23
-static void mx23_mem_setup_vddmem(void)
-{
-	struct mxs_power_regs *power_regs =
-		(struct mxs_power_regs *)MXS_POWER_BASE;
-
-	clrbits_le32(&power_regs->hw_power_vddmemctrl,
-		POWER_VDDMEMCTRL_ENABLE_ILIMIT);
-
-}
-
-static void mx23_mem_init(void)
-{
-	/*
-	 * Reset/ungate the EMI block. This is essential, otherwise the system
-	 * suffers from memory instability. This thing is mx23 specific and is
-	 * no longer present on mx28.
-	 */
-	mxs_reset_block((struct mxs_register_32 *)MXS_EMI_BASE);
-
-	mx23_mem_setup_vddmem();
-
-	/*
-	 * Configure the DRAM registers
-	 */
-
-	/* Clear START and SREFRESH bit from DRAM_CTL8 */
-	clrbits_le32(MXS_DRAM_BASE + 0x20, (1 << 16) | (1 << 8));
-
-	initialize_dram_values();
-
-	/* Set START bit in DRAM_CTL8 */
-	setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16);
-
-	clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17);
-	early_delay(20000);
-
-	/* Adjust EMI port priority. */
-	clrsetbits_le32(0x80020000, 0x1f << 16, 0x2);
-	early_delay(20000);
-
-	setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);
-	setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11);
-}
-#endif
-
-#ifdef CONFIG_MX28
-static void mx28_mem_init(void)
+void mxs_mem_init(void)
 {
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 	struct mxs_pinctrl_regs *pinctrl_regs =
 		(struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE;

@@ -306,6 +208,16 @@ static void mx28_mem_init(void)
 	writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
 		&pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);

+	/* Power up PLL0 */
+	writel(CLKCTRL_PLL0CTRL0_POWER,
+		&clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
+
+	early_delay(11000);
+
+	mxs_mem_init_clock();
+
+	mxs_mem_setup_vdda();
+
 	/*
 	 * Configure the DRAM registers
 	 */
@@ -324,22 +236,6 @@ static void mx28_mem_init(void)
 	/* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */
 	while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20)))
 		;
-}
-#endif
-
-void mxs_mem_init(void)
-{
-	early_delay(11000);
-
-	mxs_mem_init_clock();
-
-	mxs_mem_setup_vdda();
-
-#if defined(CONFIG_MX23)
-	mx23_mem_init();
-#elif defined(CONFIG_MX28)
-	mx28_mem_init();
-#endif

 	early_delay(10000);

--- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
@@ -687,12 +687,6 @@ static void mxs_power_configure_power_source(void)
 	mxs_init_batt_bo();

 	mxs_switch_vddd_to_dcdc_source();
-
-#ifdef CONFIG_MX23
-	/* Fire up the VDDMEM LinReg now that we're all set. */
-	writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
-		&power_regs->hw_power_vddmemctrl);
-#endif
 }

 static void mxs_enable_output_rail_protection(void)
@@ -787,11 +781,7 @@ struct mxs_vddx_cfg {
 static const struct mxs_vddx_cfg mxs_vddio_cfg = {
 	.reg			= &(((struct mxs_power_regs *)MXS_POWER_BASE)->
 					hw_power_vddioctrl),
-#if defined(CONFIG_MX23)
-	.step_mV		= 25,
-#else
 	.step_mV		= 50,
-#endif
 	.lowest_mV		= 2800,
 	.powered_by_linreg	= mxs_get_vddio_power_source_off,
 	.trg_mask		= POWER_VDDIOCTRL_TRG_MASK,
@@ -814,21 +804,6 @@ static const struct mxs_vddx_cfg mxs_vddd_cfg = {
 	.bo_offset_offset	= POWER_VDDDCTRL_BO_OFFSET_OFFSET,
 };

-#ifdef CONFIG_MX23
-static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
-	.reg			= &(((struct mxs_power_regs *)MXS_POWER_BASE)->
-					hw_power_vddmemctrl),
-	.step_mV		= 50,
-	.lowest_mV		= 1700,
-	.powered_by_linreg	= NULL,
-	.trg_mask		= POWER_VDDMEMCTRL_TRG_MASK,
-	.bo_irq			= 0,
-	.bo_enirq		= 0,
-	.bo_offset_mask		= 0,
-	.bo_offset_offset	= 0,
-};
-#endif
-
 static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
 				uint32_t new_target, uint32_t new_brownout)
 {
@@ -846,10 +821,9 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
 	cur_target += cfg->lowest_mV;

 	adjust_up = new_target > cur_target;
-	if (cfg->powered_by_linreg)
-		powered_by_linreg = cfg->powered_by_linreg();
+	powered_by_linreg = cfg->powered_by_linreg();

-	if (adjust_up && cfg->bo_irq) {
+	if (adjust_up) {
 		if (powered_by_linreg) {
 			bo_int = readl(cfg->reg);
 			clrbits_le32(cfg->reg, cfg->bo_enirq);
@@ -890,16 +864,14 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
 		cur_target += cfg->lowest_mV;
 	} while (new_target > cur_target);

-	if (cfg->bo_irq) {
-		if (adjust_up && powered_by_linreg) {
-			writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
-			if (bo_int & cfg->bo_enirq)
-				setbits_le32(cfg->reg, cfg->bo_enirq);
-		}
-
-		clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
-				new_brownout << cfg->bo_offset_offset);
+	if (adjust_up && powered_by_linreg) {
+		writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
+		if (bo_int & cfg->bo_enirq)
+			setbits_le32(cfg->reg, cfg->bo_enirq);
 	}
+
+	clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
+			new_brownout << cfg->bo_offset_offset);
 }

 static void mxs_setup_batt_detect(void)
@@ -909,23 +881,11 @@ static void mxs_setup_batt_detect(void)
 	early_delay(10);
 }

-static void mxs_ungate_power(void)
-{
-#ifdef CONFIG_MX23
-	struct mxs_power_regs *power_regs =
-		(struct mxs_power_regs *)MXS_POWER_BASE;
-
-	writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr);
-#endif
-}
-
 void mxs_power_init(void)
 {
 	struct mxs_power_regs *power_regs =
 		(struct mxs_power_regs *)MXS_POWER_BASE;

-	mxs_ungate_power();
-
 	mxs_power_clock2xtal();
 	mxs_power_clear_auto_restart();
 	mxs_power_set_linreg();
@@ -938,9 +898,7 @@ void mxs_power_init(void)

 	mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150);
 	mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1000);
-#ifdef CONFIG_MX23
-	mxs_power_set_vddx(&mxs_vddmem_cfg, 2500, 1700);
-#endif
+
 	writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
 		POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
 		POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
@@ -951,7 +909,7 @@ void mxs_power_init(void)
 	early_delay(1000);
 }

-#ifdef	CONFIG_SPL_MXS_PSWITCH_WAIT
+#ifdef	CONFIG_SPL_MX28_PSWITCH_WAIT
 void mxs_power_wait_pswitch(void)
 {
 	struct mxs_power_regs *power_regs =
--- a/arch/arm/cpu/arm926ejs/mxs/start.S
+++ b/arch/arm/cpu/arm926ejs/mxs/start.S
@@ -119,11 +119,7 @@ fiq:

 .globl _TEXT_BASE
 _TEXT_BASE:
-#ifdef CONFIG_SPL_TEXT_BASE
-	.word	CONFIG_SPL_TEXT_BASE
-#else
 	.word	CONFIG_SYS_TEXT_BASE
-#endif

 /*
 * These are defined in the board-specific linker script.
@@ -137,7 +133,7 @@ _bss_start_ofs:

 .globl _bss_end_ofs
 _bss_end_ofs:
-	.word __bss_end - _start
+	.word __bss_end__ - _start

 .globl _end_ofs
 _end_ofs:
--- a/arch/arm/cpu/arm926ejs/mxs/timer.c
+++ b/arch/arm/cpu/arm926ejs/mxs/timer.c
@@ -32,36 +32,32 @@
 #include <asm/arch/sys_proto.h>

 /* Maximum fixed count */
-#if defined(CONFIG_MX23)
-#define TIMER_LOAD_VAL 0xffff
-#elif defined(CONFIG_MX28)
-#define TIMER_LOAD_VAL 0xffffffff
-#endif
+#define TIMER_LOAD_VAL	0xffffffff

 DECLARE_GLOBAL_DATA_PTR;

-#define timestamp (gd->arch.tbl)
-#define lastdec (gd->arch.lastinc)
+#define timestamp (gd->tbl)
+#define lastdec (gd->lastinc)

 /*
 * This driver uses 1kHz clock source.
 */
-#define	MXS_INCREMENTER_HZ		1000
+#define	MX28_INCREMENTER_HZ		1000

 static inline unsigned long tick_to_time(unsigned long tick)
 {
-	return tick / (MXS_INCREMENTER_HZ / CONFIG_SYS_HZ);
+	return tick / (MX28_INCREMENTER_HZ / CONFIG_SYS_HZ);
 }

 static inline unsigned long time_to_tick(unsigned long time)
 {
-	return time * (MXS_INCREMENTER_HZ / CONFIG_SYS_HZ);
+	return time * (MX28_INCREMENTER_HZ / CONFIG_SYS_HZ);
 }

 /* Calculate how many ticks happen in "us" microseconds */
 static inline unsigned long us_to_tick(unsigned long us)
 {
-	return (us * MXS_INCREMENTER_HZ) / 1000000;
+	return (us * MX28_INCREMENTER_HZ) / 1000000;
 }

 int timer_init(void)
@@ -73,11 +69,7 @@ int timer_init(void)
 	mxs_reset_block(&timrot_regs->hw_timrot_rotctrl_reg);

 	/* Set fixed_count to 0 */
-#if defined(CONFIG_MX23)
-	writel(0, &timrot_regs->hw_timrot_timcount0);
-#elif defined(CONFIG_MX28)
 	writel(0, &timrot_regs->hw_timrot_fixed_count0);
-#endif

 	/* Set UPDATE bit and 1Khz frequency */
 	writel(TIMROT_TIMCTRLn_UPDATE | TIMROT_TIMCTRLn_RELOAD |
@@ -85,11 +77,7 @@ int timer_init(void)
 		&timrot_regs->hw_timrot_timctrl0);

 	/* Set fixed_count to maximal value */
-#if defined(CONFIG_MX23)
-	writel(TIMER_LOAD_VAL - 1, &timrot_regs->hw_timrot_timcount0);
-#elif defined(CONFIG_MX28)
 	writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0);
-#endif

 	return 0;
 }
@@ -98,16 +86,9 @@ unsigned long long get_ticks(void)
 {
 	struct mxs_timrot_regs *timrot_regs =
 		(struct mxs_timrot_regs *)MXS_TIMROT_BASE;
-	uint32_t now;

 	/* Current tick value */
-#if defined(CONFIG_MX23)
-	/* Upper bits are the valid ones. */
-	now = readl(&timrot_regs->hw_timrot_timcount0) >>
-		TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET;
-#elif defined(CONFIG_MX28)
-	now = readl(&timrot_regs->hw_timrot_running_count0);
-#endif
+	uint32_t now = readl(&timrot_regs->hw_timrot_running_count0);

 	if (lastdec >= now) {
 		/*
@@ -136,17 +117,17 @@ ulong get_timer(ulong base)
 }

 /* We use the HW_DIGCTL_MICROSECONDS register for sub-millisecond timer. */
-#define	MXS_HW_DIGCTL_MICROSECONDS	0x8001c0c0
+#define	MX28_HW_DIGCTL_MICROSECONDS	0x8001c0c0

 void __udelay(unsigned long usec)
 {
 	uint32_t old, new, incr;
 	uint32_t counter = 0;

-	old = readl(MXS_HW_DIGCTL_MICROSECONDS);
+	old = readl(MX28_HW_DIGCTL_MICROSECONDS);

 	while (counter < usec) {
-		new = readl(MXS_HW_DIGCTL_MICROSECONDS);
+		new = readl(MX28_HW_DIGCTL_MICROSECONDS);

 		/* Check if the timer wrapped. */
 		if (new < old) {
@@ -171,5 +152,5 @@ void __udelay(unsigned long usec)

 ulong get_tbclk(void)
 {
-	return MXS_INCREMENTER_HZ;
+	return MX28_INCREMENTER_HZ;
 }
--- a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd
+++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd
@@ -1,18 +0,0 @@
-options {
-	driveTag = 0x00;
-	flags = 0x01;
-}
-
-sources {
-	u_boot_spl="OBJTREE/spl/u-boot-spl.bin";
-	u_boot="OBJTREE/u-boot.bin";
-}
-
-section (0) {
-	load u_boot_spl > 0x0000;
-	load ivt (entry = 0x0014) > 0x8000;
-	call 0x8000;
-
-	load u_boot > 0x40000100;
-	call 0x40000100;
-}
--- a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd
+++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd
@@ -1,6 +1,6 @@
 sources {
-	u_boot_spl="OBJTREE/spl/u-boot-spl.bin";
-	u_boot="OBJTREE/u-boot.bin";
+	u_boot_spl="spl/u-boot-spl.bin";
+	u_boot="u-boot.bin";
 }

 section (0) {
--- a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
+++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
@@ -37,8 +37,8 @@ SECTIONS
 	. = ALIGN(4);
 	.text	:
 	{
-		arch/arm/cpu/arm926ejs/mxs/start.o	(.text*)
-		*(.text*)
+		arch/arm/cpu/arm926ejs/mxs/start.o	(.text)
+		*(.text)
 	}

 	. = ALIGN(4);
@@ -46,7 +46,13 @@ SECTIONS

 	. = ALIGN(4);
 	.data : {
-		*(.data*)
+		*(.data)
+	}
+
+	. = ALIGN(4);
+
+	.u_boot_list : {
+		#include <u-boot.lst>
 	}

 	. = ALIGN(4);
@@ -57,12 +63,17 @@ SECTIONS
 		__rel_dyn_end = .;
 	}

+	.dynsym : {
+		__dynsym_start = .;
+		*(.dynsym)
+	}
+
 	.bss : {
 		. = ALIGN(4);
 		__bss_start = .;
 		*(.bss*)
 		. = ALIGN(4);
-		__bss_end = .;
+		__bss_end__ = .;
 	}

 	_end = .;
--- a/arch/arm/cpu/arm926ejs/omap/timer.c
+++ b/arch/arm/cpu/arm926ejs/omap/timer.c
@@ -36,19 +36,16 @@
 */

 #include <common.h>
-#include <asm/io.h>

-#define TIMER_CLOCK	(CONFIG_SYS_CLK_FREQ / (2 << CONFIG_SYS_PTV))
-#define TIMER_LOAD_VAL	0xffffffff
+#define TIMER_LOAD_VAL 0xffffffff

 /* macro to read the 32 bit timer */
-#define READ_TIMER	readl(CONFIG_SYS_TIMERBASE+8) \
-			/ (TIMER_CLOCK / CONFIG_SYS_HZ)
+#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+8))

 DECLARE_GLOBAL_DATA_PTR;

-#define timestamp gd->arch.tbl
-#define lastdec gd->arch.lastinc
+#define timestamp gd->tbl
+#define lastdec gd->lastinc

 int timer_init (void)
 {
@@ -117,8 +114,7 @@ ulong get_timer_masked (void)
 		 * (TLV-now) amount of time after passing though -1
 		 * nts = new "advancing time stamp"...it could also roll and cause problems.
 		 */
-		timestamp += lastdec + (TIMER_LOAD_VAL / (TIMER_CLOCK /
-					CONFIG_SYS_HZ)) - now;
+		timestamp += lastdec + TIMER_LOAD_VAL - now;
 	}
 	lastdec = now;

@@ -164,5 +160,8 @@ unsigned long long get_ticks(void)
 */
 ulong get_tbclk (void)
 {
-	return CONFIG_SYS_HZ;
+	ulong tbclk;
+
+	tbclk = CONFIG_SYS_HZ;
+	return tbclk;
 }
--- a/arch/arm/cpu/arm926ejs/orion5x/timer.c
+++ b/arch/arm/cpu/arm926ejs/orion5x/timer.c
@@ -92,8 +92,8 @@ static inline ulong read_timer(void)

 DECLARE_GLOBAL_DATA_PTR;

-#define timestamp gd->arch.tbl
-#define lastdec gd->arch.lastinc
+#define timestamp gd->tbl
+#define lastdec gd->lastinc

 ulong get_timer_masked(void)
 {
--- a/arch/arm/cpu/arm926ejs/pantheon/timer.c
+++ b/arch/arm/cpu/arm926ejs/pantheon/timer.c
@@ -60,7 +60,7 @@ struct panthtmr_registers {
 #define	COUNT_RD_REQ		0x1

 DECLARE_GLOBAL_DATA_PTR;
-/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
+/* Using gd->tbu from timestamp and gd->tbl for lastdec */

 /*
 * For preventing risk of instability in reading counter value,
@@ -90,16 +90,16 @@ ulong get_timer_masked(void)
 {
 	ulong now = read_timer();

-	if (now >= gd->arch.tbl) {
+	if (now >= gd->tbl) {
 		/* normal mode */
-		gd->arch.tbu += now - gd->arch.tbl;
+		gd->tbu += now - gd->tbl;
 	} else {
 		/* we have an overflow ... */
-		gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
+		gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
 	}
-	gd->arch.tbl = now;
+	gd->tbl = now;

-	return gd->arch.tbu;
+	return gd->tbu;
 }

 ulong get_timer(ulong base)
@@ -144,9 +144,9 @@ int timer_init(void)

 	/* Enable timer 0 */
 	writel(0x1, &panthtimers->cer);
-	/* init the gd->arch.tbu and gd->arch.tbl value */
-	gd->arch.tbl = read_timer();
-	gd->arch.tbu = 0;
+	/* init the gd->tbu and gd->tbl value */
+	gd->tbl = read_timer();
+	gd->tbu = 0;

 	return 0;
 }
--- a/arch/arm/cpu/arm926ejs/spear/spear600.c
+++ b/arch/arm/cpu/arm926ejs/spear/spear600.c
@@ -28,6 +28,9 @@
 #include <asm/arch/spr_misc.h>
 #include <asm/arch/spr_defs.h>

+#define FALSE				0
+#define TRUE				(!FALSE)
+
 static void sel_1v8(void)
 {
 	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
@@ -130,8 +133,8 @@ void soc_init(void)
 /*
 * xxx_boot_selected:
 *
- * return true if the particular booting option is selected
- * return false otherwise
+ * return TRUE if the particular booting option is selected
+ * return FALSE otherwise
 */
 static u32 read_bootstrap(void)
 {
@@ -147,18 +150,18 @@ int snor_boot_selected(void)
 		/* Check whether SNOR boot is selected */
 		if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) ==
 			CONFIG_SPEAR_ONLYSNORBOOT)
-			return true;
+			return TRUE;

 		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
 			CONFIG_SPEAR_NORNAND8BOOT)
-			return true;
+			return TRUE;

 		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
 			CONFIG_SPEAR_NORNAND16BOOT)
-			return true;
+			return TRUE;
 	}

-	return false;
+	return FALSE;
 }

 int nand_boot_selected(void)
@@ -169,20 +172,20 @@ int nand_boot_selected(void)
 		/* Check whether NAND boot is selected */
 		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
 			CONFIG_SPEAR_NORNAND8BOOT)
-			return true;
+			return TRUE;

 		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
 			CONFIG_SPEAR_NORNAND16BOOT)
-			return true;
+			return TRUE;
 	}

-	return false;
+	return FALSE;
 }

 int pnor_boot_selected(void)
 {
 	/* Parallel NOR boot is not selected in any SPEAr600 revision */
-	return false;
+	return FALSE;
 }

 int usb_boot_selected(void)
@@ -192,39 +195,39 @@ int usb_boot_selected(void)
 	if (USB_BOOT_SUPPORTED) {
 		/* Check whether USB boot is selected */
 		if (!(bootstrap & CONFIG_SPEAR_USBBOOT))
-			return true;
+			return TRUE;
 	}

-	return false;
+	return FALSE;
 }

 int tftp_boot_selected(void)
 {
 	/* TFTP boot is not selected in any SPEAr600 revision */
-	return false;
+	return FALSE;
 }

 int uart_boot_selected(void)
 {
 	/* UART boot is not selected in any SPEAr600 revision */
-	return false;
+	return FALSE;
 }

 int spi_boot_selected(void)
 {
 	/* SPI boot is not selected in any SPEAr600 revision */
-	return false;
+	return FALSE;
 }

 int i2c_boot_selected(void)
 {
 	/* I2C boot is not selected in any SPEAr600 revision */
-	return false;
+	return FALSE;
 }

 int mmc_boot_selected(void)
 {
-	return false;
+	return FALSE;
 }

 void plat_late_init(void)
--- a/arch/arm/cpu/arm926ejs/spear/spl.c
+++ b/arch/arm/cpu/arm926ejs/spear/spl.c
@@ -31,6 +31,13 @@
 #include <asm/arch/spr_misc.h>
 #include <asm/arch/spr_syscntl.h>

+inline void hang(void)
+{
+	serial_puts("### ERROR ### Please RESET the board ###\n");
+	for (;;)
+		;
+}
+
 static void ddr_clock_init(void)
 {
 	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
--- a/arch/arm/cpu/arm926ejs/spear/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/spear/spl_boot.c
@@ -120,7 +120,7 @@ u32 spl_boot(void)
 	/*
 	 * All the supported booting devices are listed here. Each of
 	 * the booting type supported by the platform would define the
-	 * macro xxx_BOOT_SUPPORTED to true.
+	 * macro xxx_BOOT_SUPPORTED to TRUE.
 	 */

 	if (SNOR_BOOT_SUPPORTED && snor_boot_selected()) {
--- a/arch/arm/cpu/arm926ejs/spear/timer.c
+++ b/arch/arm/cpu/arm926ejs/spear/timer.c
@@ -38,8 +38,8 @@ static struct misc_regs *const misc_regs_p =

 DECLARE_GLOBAL_DATA_PTR;

-#define timestamp gd->arch.tbl
-#define lastdec gd->arch.lastinc
+#define timestamp gd->tbl
+#define lastdec gd->lastinc

 int timer_init(void)
 {
--- a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
+++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
@@ -37,8 +37,8 @@ SECTIONS
 	. = ALIGN(4);
 	.text	:
 	{
-		arch/arm/cpu/arm926ejs/spear/start.o	(.text*)
-		*(.text*)
+		arch/arm/cpu/arm926ejs/spear/start.o	(.text)
+		*(.text)
 	}

 	. = ALIGN(4);
@@ -46,7 +46,13 @@ SECTIONS

 	. = ALIGN(4);
 	.data : {
-		*(.data*)
+		*(.data)
+	}
+
+	. = ALIGN(4);
+
+	.u_boot_list : {
+		#include <u-boot.lst>
 	}

 	. = ALIGN(4);
@@ -57,12 +63,17 @@ SECTIONS
 		__rel_dyn_end = .;
 	}

+	.dynsym : {
+		__dynsym_start = .;
+		*(.dynsym)
+	}
+
 	.bss : {
 		. = ALIGN(4);
 		__bss_start = .;
 		*(.bss*)
 		. = ALIGN(4);
-		__bss_end = .;
+		__bss_end__ = .;
 	}

 	_end = .;
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -120,11 +120,15 @@ _fiq:

 .globl _TEXT_BASE
 _TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
+#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */
+	.word	CONFIG_SYS_TEXT_BASE
+#else
+#ifdef CONFIG_SPL_BUILD
 	.word	CONFIG_SPL_TEXT_BASE
 #else
 	.word	CONFIG_SYS_TEXT_BASE
 #endif
+#endif

 /*
 * These are defined in the board-specific linker script.
@@ -138,12 +142,18 @@ _bss_start_ofs:

 .globl _bss_end_ofs
 _bss_end_ofs:
-	.word __bss_end - _start
+	.word __bss_end__ - _start

 .globl _end_ofs
 _end_ofs:
 	.word _end - _start

+#ifdef CONFIG_NAND_U_BOOT
+.globl _end
+_end:
+	.word __bss_end__
+#endif
+
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
 .globl IRQ_STACK_START
@@ -186,6 +196,89 @@ reset:

 /*------------------------------------------------------------------------------*/

+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_NAND_SPL)
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ */
+	.globl	relocate_code
+relocate_code:
+	mov	r4, r0	/* save addr_sp */
+	mov	r5, r1	/* save addr of gd */
+	mov	r6, r2	/* save addr of destination */
+
+	adr	r0, _start
+	sub	r9, r6, r0		/* r9 <- relocation offset */
+	cmp	r0, r6
+	moveq	r9, #0			/* no relocation. offset(r9) = 0 */
+	beq	relocate_done		/* skip relocation */
+	mov	r1, r6			/* r1 <- scratch for copy loop */
+	ldr	r3, _bss_start_ofs
+	add	r2, r0, r3		/* r2 <- source end address	    */
+
+copy_loop:
+	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
+	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
+
+#ifndef CONFIG_SPL_BUILD
+	/*
+	 * fix .rel.dyn relocations
+	 */
+	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
+	sub	r9, r6, r0		/* r9 <- relocation offset */
+	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
+	add	r10, r10, r0		/* r10 <- sym table in FLASH */
+	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
+	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
+	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
+	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
+fixloop:
+	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
+	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
+	ldr	r1, [r2, #4]
+	and	r7, r1, #0xff
+	cmp	r7, #23			/* relative fixup? */
+	beq	fixrel
+	cmp	r7, #2			/* absolute fixup? */
+	beq	fixabs
+	/* ignore unknown type of fixup */
+	b	fixnext
+fixabs:
+	/* absolute fix: set location to (offset) symbol value */
+	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
+	add	r1, r10, r1		/* r1 <- address of symbol in table */
+	ldr	r1, [r1, #4]		/* r1 <- symbol value */
+	add	r1, r1, r9		/* r1 <- relocated sym addr */
+	b	fixnext
+fixrel:
+	/* relative fix: increase location by offset */
+	ldr	r1, [r0]
+	add	r1, r1, r9
+fixnext:
+	str	r1, [r0]
+	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
+	cmp	r2, r3
+	blo	fixloop
+#endif
+
+relocate_done:
+
+	bx	lr
+
+_rel_dyn_start_ofs:
+	.word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+	.word __rel_dyn_end - _start
+_dynsym_start_ofs:
+	.word __dynsym_start - _start
+
+#endif
+
 	.globl	c_runtime_cpu_setup
 c_runtime_cpu_setup:

--- a/arch/arm/cpu/arm926ejs/versatile/timer.c
+++ b/arch/arm/cpu/arm926ejs/versatile/timer.c
@@ -44,8 +44,8 @@

 DECLARE_GLOBAL_DATA_PTR;

-#define timestamp gd->arch.tbl
-#define lastdec gd->arch.lastinc
+#define timestamp gd->tbl
+#define lastdec gd->lastinc

 #define TIMER_ENABLE	(1 << 7)
 #define TIMER_MODE_MSK	(1 << 6)
--- a/arch/arm/cpu/arm946es/start.S
+++ b/arch/arm/cpu/arm946es/start.S
@@ -89,11 +89,7 @@ _vectors_end:

 .globl _TEXT_BASE
 _TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
 	.word	CONFIG_SYS_TEXT_BASE
-#endif

 /*
 * These are defined in the board-specific linker script.
@@ -107,7 +103,7 @@ _bss_start_ofs:

 .globl _bss_end_ofs
 _bss_end_ofs:
-	.word __bss_end - _start
+	.word __bss_end__ - _start

 .globl _end_ofs
 _end_ofs:
@@ -155,6 +151,85 @@ reset:

 /*------------------------------------------------------------------------------*/

+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ */
+	.globl	relocate_code
+relocate_code:
+	mov	r4, r0	/* save addr_sp */
+	mov	r5, r1	/* save addr of gd */
+	mov	r6, r2	/* save addr of destination */
+
+	adr	r0, _start
+	cmp	r0, r6
+	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
+	beq	relocate_done		/* skip relocation */
+	mov	r1, r6			/* r1 <- scratch for copy_loop */
+	ldr	r3, _bss_start_ofs
+	add	r2, r0, r3		/* r2 <- source end address	    */
+
+copy_loop:
+	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
+	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
+
+#ifndef CONFIG_SPL_BUILD
+	/*
+	 * fix .rel.dyn relocations
+	 */
+	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
+	sub	r9, r6, r0		/* r9 <- relocation offset */
+	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
+	add	r10, r10, r0		/* r10 <- sym table in FLASH */
+	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
+	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
+	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
+	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
+fixloop:
+	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
+	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
+	ldr	r1, [r2, #4]
+	and	r7, r1, #0xff
+	cmp	r7, #23			/* relative fixup? */
+	beq	fixrel
+	cmp	r7, #2			/* absolute fixup? */
+	beq	fixabs
+	/* ignore unknown type of fixup */
+	b	fixnext
+fixabs:
+	/* absolute fix: set location to (offset) symbol value */
+	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
+	add	r1, r10, r1		/* r1 <- address of symbol in table */
+	ldr	r1, [r1, #4]		/* r1 <- symbol value */
+	add	r1, r1, r9		/* r1 <- relocated sym addr */
+	b	fixnext
+fixrel:
+	/* relative fix: increase location by offset */
+	ldr	r1, [r0]
+	add	r1, r1, r9
+fixnext:
+	str	r1, [r0]
+	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
+	cmp	r2, r3
+	blo	fixloop
+#endif
+
+relocate_done:
+
+	mov	pc, lr
+
+_rel_dyn_start_ofs:
+	.word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+	.word __rel_dyn_end - _start
+_dynsym_start_ofs:
+	.word __dynsym_start - _start
+
 	.globl	c_runtime_cpu_setup
 c_runtime_cpu_setup:

--- a/arch/arm/cpu/arm_intcm/start.S
+++ b/arch/arm/cpu/arm_intcm/start.S
@@ -85,11 +85,7 @@ _fiq:

 .globl _TEXT_BASE
 _TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
+	.word	CONFIG_SYS_TEXT_BASE /* address of _start in the linked image */

 /*
 * These are defined in the board-specific linker script.
@@ -103,7 +99,7 @@ _bss_start_ofs:

 .globl _bss_end_ofs
 _bss_end_ofs:
-	.word __bss_end - _start
+	.word __bss_end__ - _start

 .globl _end_ofs
 _end_ofs:
@@ -151,6 +147,85 @@ reset:

 /*------------------------------------------------------------------------------*/

+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ */
+	.globl	relocate_code
+relocate_code:
+	mov	r4, r0	/* save addr_sp */
+	mov	r5, r1	/* save addr of gd */
+	mov	r6, r2	/* save addr of destination */
+
+	adr	r0, _start
+	cmp	r0, r6
+	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
+	beq	relocate_done		/* skip relocation */
+	mov	r1, r6			/* r1 <- scratch for copy_loop */
+	ldr	r3, _bss_start_ofs
+	add	r2, r0, r3		/* r2 <- source end address	    */
+
+copy_loop:
+	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
+	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
+
+#ifndef CONFIG_SPL_BUILD
+	/*
+	 * fix .rel.dyn relocations
+	 */
+	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
+	sub	r9, r6, r0		/* r9 <- relocation offset */
+	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
+	add	r10, r10, r0		/* r10 <- sym table in FLASH */
+	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
+	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
+	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
+	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
+fixloop:
+	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
+	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
+	ldr	r1, [r2, #4]
+	and	r7, r1, #0xff
+	cmp	r7, #23			/* relative fixup? */
+	beq	fixrel
+	cmp	r7, #2			/* absolute fixup? */
+	beq	fixabs
+	/* ignore unknown type of fixup */
+	b	fixnext
+fixabs:
+	/* absolute fix: set location to (offset) symbol value */
+	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
+	add	r1, r10, r1		/* r1 <- address of symbol in table */
+	ldr	r1, [r1, #4]		/* r1 <- symbol value */
+	add	r1, r1, r9		/* r1 <- relocated sym addr */
+	b	fixnext
+fixrel:
+	/* relative fix: increase location by offset */
+	ldr	r1, [r0]
+	add	r1, r1, r9
+fixnext:
+	str	r1, [r0]
+	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
+	cmp	r2, r3
+	blo	fixloop
+#endif
+
+relocate_done:
+
+	bx	lr
+
+_rel_dyn_start_ofs:
+	.word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+	.word __rel_dyn_end - _start
+_dynsym_start_ofs:
+	.word __dynsym_start - _start
+
 	.globl	c_runtime_cpu_setup
 c_runtime_cpu_setup:

--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -32,7 +32,7 @@ COBJS	+= cache_v7.o
 COBJS	+= cpu.o
 COBJS	+= syslib.o

-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI814X),)
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA20),)
 SOBJS	+= lowlevel_init.o
 endif

--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -16,8 +16,7 @@ include $(TOPDIR)/config.mk

 LIB	= $(obj)lib$(SOC).o

-COBJS-$(CONFIG_AM33XX)	+= clock_am33xx.o
-COBJS-$(CONFIG_TI814X)	+= clock_ti814x.o
+COBJS	+= clock.o
 COBJS	+= sys_info.o
 COBJS	+= mem.o
 COBJS	+= ddr.o
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -56,11 +56,11 @@ int cpu_mmc_init(bd_t *bis)
 {
 	int ret;

-	ret = omap_mmc_init(0, 0, 0, -1, -1);
+	ret = omap_mmc_init(0, 0, 0);
 	if (ret)
 		return ret;

-	return omap_mmc_init(1, 0, 0, -1, -1);
+	return omap_mmc_init(1, 0, 0);
 }
 #endif

@@ -141,51 +141,11 @@ int arch_misc_init(void)
 {
 #ifdef CONFIG_AM335X_USB0
 	musb_register(&otg0_plat, &otg0_board_data,
-		(void *)USB0_OTG_BASE);
+		(void *)AM335X_USB0_OTG_BASE);
 #endif
 #ifdef CONFIG_AM335X_USB1
 	musb_register(&otg1_plat, &otg1_board_data,
-		(void *)USB1_OTG_BASE);
+		(void *)AM335X_USB1_OTG_BASE);
 #endif
 	return 0;
 }
-
-#ifdef CONFIG_SPL_BUILD
-void rtc32k_enable(void)
-{
-	struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
-
-	/*
-	 * Unlock the RTC's registers.  For more details please see the
-	 * RTC_SS section of the TRM.  In order to unlock we need to
-	 * write these specific values (keys) in this order.
-	 */
-	writel(0x83e70b13, &rtc->kick0r);
-	writel(0x95a4f1e0, &rtc->kick1r);
-
-	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
-	writel((1 << 3) | (1 << 6), &rtc->osc);
-}
-
-#define UART_RESET		(0x1 << 1)
-#define UART_CLK_RUNNING_MASK	0x1
-#define UART_SMART_IDLE_EN	(0x1 << 0x3)
-
-void uart_soft_reset(void)
-{
-	struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
-	u32 regval;
-
-	regval = readl(&uart_base->uartsyscfg);
-	regval |= UART_RESET;
-	writel(regval, &uart_base->uartsyscfg);
-	while ((readl(&uart_base->uartsyssts) &
-		UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
-		;
-
-	/* Disable smart idle */
-	regval = readl(&uart_base->uartsyscfg);
-	regval |= UART_SMART_IDLE_EN;
-	writel(regval, &uart_base->uartsyscfg);
-}
-#endif
--- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
@@ -1,9 +1,9 @@
 /*
- * clock_am33xx.c
+ * clock.c
 *
 * clocks for AM33XX based boards
 *
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
@@ -42,35 +42,6 @@
 #define CPGMAC0_IDLE		0x30000
 #define DPLL_CLKDCOLDO_GATE_CTRL        0x300

-#define OSC	(V_OSCK/1000000)
-
-#define MPUPLL_M	CONFIG_SYS_MPUCLK
-#define MPUPLL_N	(OSC-1)
-#define MPUPLL_M2	1
-
-/* Core PLL Fdll = 1 GHZ, */
-#define COREPLL_M	1000
-#define COREPLL_N	(OSC-1)
-
-#define COREPLL_M4	10	/* CORE_CLKOUTM4 = 200 MHZ */
-#define COREPLL_M5	8	/* CORE_CLKOUTM5 = 250 MHZ */
-#define COREPLL_M6	4	/* CORE_CLKOUTM6 = 500 MHZ */
-
-/*
- * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
- * frequency needs to be set to 960 MHZ. Hence,
- * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
- */
-#define PERPLL_M	960
-#define PERPLL_N	(OSC-1)
-#define PERPLL_M2	5
-
-/* DDR Freq is 266 MHZ for now */
-/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
-#define DDRPLL_M	266
-#define DDRPLL_N	(OSC-1)
-#define DDRPLL_M2	1
-
 const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
 const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
 const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
@@ -195,11 +166,6 @@ static void enable_per_clocks(void)
 	while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
 		;

-	/* MMC1 */
-	writel(PRCM_MOD_EN, &cmper->mmc1clkctrl);
-	while (readl(&cmper->mmc1clkctrl) != PRCM_MOD_EN)
-		;
-
 	/* i2c0 */
 	writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl);
 	while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN)
@@ -246,7 +212,7 @@ static void enable_per_clocks(void)
 		;
 }

-void mpu_pll_config_val(int mpull_m)
+static void mpu_pll_config(void)
 {
 	u32 clkmode, clksel, div_m2;

@@ -260,7 +226,7 @@ void mpu_pll_config_val(int mpull_m)
 		;

 	clksel = clksel & (~CLK_SEL_MASK);
-	clksel = clksel | ((mpull_m << CLK_SEL_SHIFT) | MPUPLL_N);
+	clksel = clksel | ((MPUPLL_M << CLK_SEL_SHIFT) | MPUPLL_N);
 	writel(clksel, &cmwkup->clkseldpllmpu);

 	div_m2 = div_m2 & ~CLK_DIV_MASK;
@@ -274,11 +240,6 @@ void mpu_pll_config_val(int mpull_m)
 		;
 }

-static void mpu_pll_config(void)
-{
-	mpu_pll_config_val(CONFIG_SYS_MPUCLK);
-}
-
 static void core_pll_config(void)
 {
 	u32 clkmode, clksel, div_m4, div_m5, div_m6;
--- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
@@ -1,505 +0,0 @@
-/*
- * clock_ti814x.c
- *
- * Clocks for TI814X based boards
- *
- * Copyright (C) 2013, Texas Instruments, Incorporated
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-
-/* PRCM */
-#define PRCM_MOD_EN		0x2
-
-/* CLK_SRC */
-#define OSC_SRC0		0
-#define OSC_SRC1		1
-
-#define L3_OSC_SRC		OSC_SRC0
-
-#define OSC_0_FREQ		20
-
-#define DCO_HS2_MIN		500
-#define DCO_HS2_MAX		1000
-#define DCO_HS1_MIN		1000
-#define DCO_HS1_MAX		2000
-
-#define SELFREQDCO_HS2		0x00000801
-#define SELFREQDCO_HS1		0x00001001
-
-#define MPU_N			0x1
-#define MPU_M			0x3C
-#define MPU_M2			1
-#define MPU_CLKCTRL		0x1
-
-#define L3_N			19
-#define L3_M			880
-#define L3_M2			4
-#define L3_CLKCTRL		0x801
-
-#define DDR_N			19
-#define DDR_M			666
-#define DDR_M2			2
-#define DDR_CLKCTRL		0x801
-
-/* ADPLLJ register values */
-#define ADPLLJ_CLKCTRL_HS2	0x00000801 /* HS2 mode, TINT2 = 1 */
-#define ADPLLJ_CLKCTRL_HS1	0x00001001 /* HS1 mode, TINT2 = 1 */
-#define ADPLLJ_CLKCTRL_CLKDCOLDOEN	(1 << 29)
-#define ADPLLJ_CLKCTRL_IDLE		(1 << 23)
-#define ADPLLJ_CLKCTRL_CLKOUTEN		(1 << 20)
-#define ADPLLJ_CLKCTRL_CLKOUTLDOEN	(1 << 19)
-#define ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ	(1 << 17)
-#define ADPLLJ_CLKCTRL_LPMODE		(1 << 12)
-#define ADPLLJ_CLKCTRL_DRIFTGUARDIAN	(1 << 11)
-#define ADPLLJ_CLKCTRL_REGM4XEN		(1 << 10)
-#define ADPLLJ_CLKCTRL_TINITZ		(1 << 0)
-#define ADPLLJ_CLKCTRL_CLKDCO		(ADPLLJ_CLKCTRL_CLKDCOLDOEN | \
-					 ADPLLJ_CLKCTRL_CLKOUTEN | \
-					 ADPLLJ_CLKCTRL_CLKOUTLDOEN | \
-					 ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ)
-
-#define ADPLLJ_STATUS_PHASELOCK		(1 << 10)
-#define ADPLLJ_STATUS_FREQLOCK		(1 << 9)
-#define ADPLLJ_STATUS_PHSFRQLOCK	(ADPLLJ_STATUS_PHASELOCK | \
-					 ADPLLJ_STATUS_FREQLOCK)
-#define ADPLLJ_STATUS_BYPASSACK		(1 << 8)
-#define ADPLLJ_STATUS_BYPASS		(1 << 0)
-#define ADPLLJ_STATUS_BYPASSANDACK	(ADPLLJ_STATUS_BYPASSACK | \
-					 ADPLLJ_STATUS_BYPASS)
-
-#define ADPLLJ_TENABLE_ENB		(1 << 0)
-#define ADPLLJ_TENABLEDIV_ENB		(1 << 0)
-
-#define ADPLLJ_M2NDIV_M2SHIFT		16
-
-#define MPU_PLL_BASE			(PLL_SUBSYS_BASE + 0x048)
-#define L3_PLL_BASE			(PLL_SUBSYS_BASE + 0x110)
-#define DDR_PLL_BASE			(PLL_SUBSYS_BASE + 0x290)
-
-struct ad_pll {
-	unsigned int pwrctrl;
-	unsigned int clkctrl;
-	unsigned int tenable;
-	unsigned int tenablediv;
-	unsigned int m2ndiv;
-	unsigned int mn2div;
-	unsigned int fracdiv;
-	unsigned int bwctrl;
-	unsigned int fracctrl;
-	unsigned int status;
-	unsigned int m3div;
-	unsigned int rampctrl;
-};
-
-#define OSC_SRC_CTRL			(PLL_SUBSYS_BASE + 0x2C0)
-
-/* PRCM */
-#define ENET_CLKCTRL_CMPL		0x30000
-
-#define CM_DEFAULT_BASE			(PRCM_BASE + 0x0500)
-
-struct cm_def {
-	unsigned int resv0[2];
-	unsigned int l3fastclkstctrl;
-	unsigned int resv1[1];
-	unsigned int pciclkstctrl;
-	unsigned int resv2[1];
-	unsigned int ducaticlkstctrl;
-	unsigned int resv3[1];
-	unsigned int emif0clkctrl;
-	unsigned int emif1clkctrl;
-	unsigned int dmmclkctrl;
-	unsigned int fwclkctrl;
-	unsigned int resv4[10];
-	unsigned int usbclkctrl;
-	unsigned int resv5[1];
-	unsigned int sataclkctrl;
-	unsigned int resv6[4];
-	unsigned int ducaticlkctrl;
-	unsigned int pciclkctrl;
-};
-
-#define CM_ALWON_BASE			(PRCM_BASE + 0x1400)
-
-struct cm_alwon {
-	unsigned int l3slowclkstctrl;
-	unsigned int ethclkstctrl;
-	unsigned int l3medclkstctrl;
-	unsigned int mmu_clkstctrl;
-	unsigned int mmucfg_clkstctrl;
-	unsigned int ocmc0clkstctrl;
-	unsigned int vcpclkstctrl;
-	unsigned int mpuclkstctrl;
-	unsigned int sysclk4clkstctrl;
-	unsigned int sysclk5clkstctrl;
-	unsigned int sysclk6clkstctrl;
-	unsigned int rtcclkstctrl;
-	unsigned int l3fastclkstctrl;
-	unsigned int resv0[67];
-	unsigned int mcasp0clkctrl;
-	unsigned int mcasp1clkctrl;
-	unsigned int mcasp2clkctrl;
-	unsigned int mcbspclkctrl;
-	unsigned int uart0clkctrl;
-	unsigned int uart1clkctrl;
-	unsigned int uart2clkctrl;
-	unsigned int gpio0clkctrl;
-	unsigned int gpio1clkctrl;
-	unsigned int i2c0clkctrl;
-	unsigned int i2c1clkctrl;
-	unsigned int mcasp345clkctrl;
-	unsigned int atlclkctrl;
-	unsigned int mlbclkctrl;
-	unsigned int pataclkctrl;
-	unsigned int resv1[1];
-	unsigned int uart3clkctrl;
-	unsigned int uart4clkctrl;
-	unsigned int uart5clkctrl;
-	unsigned int wdtimerclkctrl;
-	unsigned int spiclkctrl;
-	unsigned int mailboxclkctrl;
-	unsigned int spinboxclkctrl;
-	unsigned int mmudataclkctrl;
-	unsigned int resv2[2];
-	unsigned int mmucfgclkctrl;
-	unsigned int resv3[2];
-	unsigned int ocmc0clkctrl;
-	unsigned int vcpclkctrl;
-	unsigned int resv4[2];
-	unsigned int controlclkctrl;
-	unsigned int resv5[2];
-	unsigned int gpmcclkctrl;
-	unsigned int ethernet0clkctrl;
-	unsigned int ethernet1clkctrl;
-	unsigned int mpuclkctrl;
-	unsigned int debugssclkctrl;
-	unsigned int l3clkctrl;
-	unsigned int l4hsclkctrl;
-	unsigned int l4lsclkctrl;
-	unsigned int rtcclkctrl;
-	unsigned int tpccclkctrl;
-	unsigned int tptc0clkctrl;
-	unsigned int tptc1clkctrl;
-	unsigned int tptc2clkctrl;
-	unsigned int tptc3clkctrl;
-	unsigned int resv7[4];
-	unsigned int dcan01clkctrl;
-	unsigned int mmchs0clkctrl;
-	unsigned int mmchs1clkctrl;
-	unsigned int mmchs2clkctrl;
-	unsigned int custefuseclkctrl;
-};
-
-#define SATA_PLL_BASE			(CTRL_BASE + 0x0720)
-
-struct sata_pll {
-	unsigned int pllcfg0;
-	unsigned int pllcfg1;
-	unsigned int pllcfg2;
-	unsigned int pllcfg3;
-	unsigned int pllcfg4;
-	unsigned int pllstatus;
-	unsigned int rxstatus;
-	unsigned int txstatus;
-	unsigned int testcfg;
-};
-
-#define SEL_IN_FREQ		(0x1 << 31)
-#define DIGCLRZ			(0x1 << 30)
-#define ENDIGLDO		(0x1 << 4)
-#define APLL_CP_CURR		(0x1 << 3)
-#define ENBGSC_REF		(0x1 << 2)
-#define ENPLLLDO		(0x1 << 1)
-#define ENPLL			(0x1 << 0)
-
-#define SATA_PLLCFG0_1 (SEL_IN_FREQ | ENBGSC_REF)
-#define SATA_PLLCFG0_2 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF)
-#define SATA_PLLCFG0_3 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF | ENPLLLDO)
-#define SATA_PLLCFG0_4 (SEL_IN_FREQ | DIGCLRZ | ENDIGLDO | ENBGSC_REF | \
-			ENPLLLDO | ENPLL)
-
-#define PLL_LOCK		(0x1 << 0)
-
-#define ENSATAMODE		(0x1 << 31)
-#define PLLREFSEL		(0x1 << 30)
-#define MDIVINT			(0x4b << 18)
-#define EN_CLKAUX		(0x1 << 5)
-#define EN_CLK125M		(0x1 << 4)
-#define EN_CLK100M		(0x1 << 3)
-#define EN_CLK50M		(0x1 << 2)
-
-#define SATA_PLLCFG1 (ENSATAMODE |	\
-		      PLLREFSEL |	\
-		      MDIVINT |		\
-		      EN_CLKAUX |	\
-		      EN_CLK125M |	\
-		      EN_CLK100M |	\
-		      EN_CLK50M)
-
-#define DIGLDO_EN_CAPLESSMODE	(0x1 << 22)
-#define PLLDO_EN_LDO_STABLE	(0x1 << 11)
-#define PLLDO_EN_BUF_CUR	(0x1 << 7)
-#define PLLDO_EN_LP		(0x1 << 6)
-#define PLLDO_CTRL_TRIM_1_4V	(0x10 << 1)
-
-#define SATA_PLLCFG3 (DIGLDO_EN_CAPLESSMODE |	\
-		      PLLDO_EN_LDO_STABLE |	\
-		      PLLDO_EN_BUF_CUR |	\
-		      PLLDO_EN_LP |		\
-		      PLLDO_CTRL_TRIM_1_4V)
-
-const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
-const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
-const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE;
-
-/*
- * Enable the peripheral clock for required peripherals
- */
-static void enable_per_clocks(void)
-{
-	/* UART0 */
-	writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
-	while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
-		;
-
-	/* HSMMC1 */
-	writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl);
-	while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN)
-		;
-
-	/* Ethernet */
-	writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
-	writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
-	while ((readl(&cmalwon->ethernet0clkctrl) & ENET_CLKCTRL_CMPL) != 0)
-		;
-	writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
-	while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0)
-		;
-}
-
-/*
- * select the HS1 or HS2 for DCO Freq
- * return : CLKCTRL
- */
-static u32 pll_dco_freq_sel(u32 clkout_dco)
-{
-	if (clkout_dco >= DCO_HS2_MIN && clkout_dco < DCO_HS2_MAX)
-		return SELFREQDCO_HS2;
-	else if (clkout_dco >= DCO_HS1_MIN && clkout_dco < DCO_HS1_MAX)
-		return SELFREQDCO_HS1;
-	else
-		return -1;
-}
-
-/*
- * select the sigma delta config
- * return: sigma delta val
- */
-static u32 pll_sigma_delta_val(u32 clkout_dco)
-{
-	u32 sig_val = 0;
-	float frac_div;
-
-	frac_div = (float) clkout_dco / 250;
-	frac_div = frac_div + 0.90;
-	sig_val = (int)frac_div;
-	sig_val = sig_val << 24;
-
-	return sig_val;
-}
-
-/*
- * configure individual ADPLLJ
- */
-static void pll_config(u32 base, u32 n, u32 m, u32 m2,
-		       u32 clkctrl_val, int adpllj)
-{
-	const struct ad_pll *adpll = (struct ad_pll *)base;
-	u32 m2nval, mn2val, read_clkctrl = 0, clkout_dco = 0;
-	u32 sig_val = 0, hs_mod = 0;
-
-	m2nval = (m2 << ADPLLJ_M2NDIV_M2SHIFT) | n;
-	mn2val = m;
-
-	/* calculate clkout_dco */
-	clkout_dco = ((OSC_0_FREQ / (n+1)) * m);
-
-	/* sigma delta & Hs mode selection skip for ADPLLS*/
-	if (adpllj) {
-		sig_val = pll_sigma_delta_val(clkout_dco);
-		hs_mod = pll_dco_freq_sel(clkout_dco);
-	}
-
-	/* by-pass pll */
-	read_clkctrl = readl(&adpll->clkctrl);
-	writel((read_clkctrl | ADPLLJ_CLKCTRL_IDLE), &adpll->clkctrl);
-	while ((readl(&adpll->status) & ADPLLJ_STATUS_BYPASSANDACK)
-		!= ADPLLJ_STATUS_BYPASSANDACK)
-		;
-
-	/* clear TINITZ */
-	read_clkctrl = readl(&adpll->clkctrl);
-	writel((read_clkctrl & ~ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
-
-	/*
-	 * ref_clk = 20/(n + 1);
-	 * clkout_dco = ref_clk * m;
-	 * clk_out = clkout_dco/m2;
-	*/
-	read_clkctrl = readl(&adpll->clkctrl) &
-			     ~(ADPLLJ_CLKCTRL_LPMODE |
-			     ADPLLJ_CLKCTRL_DRIFTGUARDIAN |
-			     ADPLLJ_CLKCTRL_REGM4XEN);
-	writel(m2nval, &adpll->m2ndiv);
-	writel(mn2val, &adpll->mn2div);
-
-	/* Skip for modena(ADPLLS) */
-	if (adpllj) {
-		writel(sig_val, &adpll->fracdiv);
-		writel((read_clkctrl | hs_mod), &adpll->clkctrl);
-	}
-
-	/* Load M2, N2 dividers of ADPLL */
-	writel(ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
-	writel(~ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
-
-	/* Load M, N dividers of ADPLL */
-	writel(ADPLLJ_TENABLE_ENB, &adpll->tenable);
-	writel(~ADPLLJ_TENABLE_ENB, &adpll->tenable);
-
-	/* Configure CLKDCOLDOEN,CLKOUTLDOEN,CLKOUT Enable BITS */
-	read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_CLKDCO;
-	if (adpllj)
-		writel((read_clkctrl | ADPLLJ_CLKCTRL_CLKDCO),
-						&adpll->clkctrl);
-
-	/* Enable TINTZ and disable IDLE(PLL in Active & Locked Mode */
-	read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_IDLE;
-	writel((read_clkctrl | ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
-
-	/* Wait for phase and freq lock */
-	while ((readl(&adpll->status) & ADPLLJ_STATUS_PHSFRQLOCK) !=
-	       ADPLLJ_STATUS_PHSFRQLOCK)
-		;
-}
-
-static void unlock_pll_control_mmr(void)
-{
-	/* TRM 2.10.1.4 and 3.2.7-3.2.11 */
-	writel(0x1EDA4C3D, 0x481C5040);
-	writel(0x2FF1AC2B, 0x48140060);
-	writel(0xF757FDC0, 0x48140064);
-	writel(0xE2BC3A6D, 0x48140068);
-	writel(0x1EBF131D, 0x4814006c);
-	writel(0x6F361E05, 0x48140070);
-}
-
-static void mpu_pll_config(void)
-{
-	pll_config(MPU_PLL_BASE, MPU_N, MPU_M, MPU_M2, MPU_CLKCTRL, 0);
-}
-
-static void l3_pll_config(void)
-{
-	u32 l3_osc_src, rd_osc_src = 0;
-
-	l3_osc_src = L3_OSC_SRC;
-	rd_osc_src = readl(OSC_SRC_CTRL);
-
-	if (OSC_SRC0 == l3_osc_src)
-		writel((rd_osc_src & 0xfffffffe)|0x0, OSC_SRC_CTRL);
-	else
-		writel((rd_osc_src & 0xfffffffe)|0x1, OSC_SRC_CTRL);
-
-	pll_config(L3_PLL_BASE, L3_N, L3_M, L3_M2, L3_CLKCTRL, 1);
-}
-
-void ddr_pll_config(unsigned int ddrpll_m)
-{
-	pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1);
-}
-
-void sata_pll_config(void)
-{
-	/*
-	 * This sequence for configuring the SATA PLL
-	 * resident in the control module is documented
-	 * in TI8148 TRM section 21.3.1
-	 */
-	writel(SATA_PLLCFG1, &spll->pllcfg1);
-	udelay(50);
-
-	writel(SATA_PLLCFG3, &spll->pllcfg3);
-	udelay(50);
-
-	writel(SATA_PLLCFG0_1, &spll->pllcfg0);
-	udelay(50);
-
-	writel(SATA_PLLCFG0_2, &spll->pllcfg0);
-	udelay(50);
-
-	writel(SATA_PLLCFG0_3, &spll->pllcfg0);
-	udelay(50);
-
-	writel(SATA_PLLCFG0_4, &spll->pllcfg0);
-	udelay(50);
-
-	while (((readl(&spll->pllstatus) & PLL_LOCK) == 0))
-		;
-}
-
-void enable_emif_clocks(void) {};
-
-void enable_dmm_clocks(void)
-{
-	writel(PRCM_MOD_EN, &cmdef->fwclkctrl);
-	writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
-	writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
-	while ((readl(&cmdef->emif0clkctrl)) != PRCM_MOD_EN)
-		;
-	writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
-	while ((readl(&cmdef->emif1clkctrl)) != PRCM_MOD_EN)
-		;
-	while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)
-		;
-	writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
-	while ((readl(&cmdef->dmmclkctrl)) != PRCM_MOD_EN)
-		;
-	writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl);
-	while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
-		;
-}
-
-/*
- * Configure the PLL/PRCM for necessary peripherals
- */
-void pll_init()
-{
-	unlock_pll_control_mmr();
-
-	/* Enable the control module */
-	writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
-
-	/* Configure PLLs */
-	mpu_pll_config();
-	l3_pll_config();
-	sata_pll_config();
-
-	/* Enable the required peripherals */
-	enable_per_clocks();
-}
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -24,20 +24,15 @@ http://www.ti.com/
 /**
 * Base address for EMIF instances
 */
-static struct emif_reg_struct *emif_reg[2] = {
-				(struct emif_reg_struct *)EMIF4_0_CFG_BASE,
-				(struct emif_reg_struct *)EMIF4_1_CFG_BASE};
+static struct emif_reg_struct *emif_reg = {
+				(struct emif_reg_struct *)EMIF4_0_CFG_BASE};

 /**
- * Base addresses for DDR PHY cmd/data regs
+ * Base address for DDR instance
 */
-static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
-				(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
-				(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};
-
-static struct ddr_data_regs *ddr_data_reg[2] = {
-				(struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
-				(struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};
+static struct ddr_regs *ddr_reg[2] = {
+				(struct ddr_regs *)DDR_PHY_BASE_ADDR,
+				(struct ddr_regs *)DDR_PHY_BASE_ADDR2};

 /**
 * Base address for ddr io control instances
@@ -48,93 +43,70 @@ static struct ddr_cmdtctrl *ioctrl_reg = {
 /**
 * Configure SDRAM
 */
-void config_sdram(const struct emif_regs *regs, int nr)
+void config_sdram(const struct emif_regs *regs)
 {
-	if (regs->zq_config) {
-		/*
-		 * A value of 0x2800 for the REF CTRL will give us
-		 * about 570us for a delay, which will be long enough
-		 * to configure things.
-		 */
-		writel(0x2800, &emif_reg[nr]->emif_sdram_ref_ctrl);
-		writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
+	writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
+	writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
+	if (regs->zq_config){
+		writel(regs->zq_config, &emif_reg->emif_zq_config);
 		writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
-		writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
-		writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
-		writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 	}
-	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
-	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
-	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
+	writel(regs->sdram_config, &emif_reg->emif_sdram_config);
 }

 /**
 * Set SDRAM timings
 */
-void set_sdram_timings(const struct emif_regs *regs, int nr)
+void set_sdram_timings(const struct emif_regs *regs)
 {
-	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
-	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
-	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
-	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
-	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
-	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
+	writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1);
+	writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1_shdw);
+	writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2);
+	writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2_shdw);
+	writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3);
+	writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3_shdw);
 }

 /**
 * Configure DDR PHY
 */
-void config_ddr_phy(const struct emif_regs *regs, int nr)
+void config_ddr_phy(const struct emif_regs *regs)
 {
-	writel(regs->emif_ddr_phy_ctlr_1,
-		&emif_reg[nr]->emif_ddr_phy_ctrl_1);
-	writel(regs->emif_ddr_phy_ctlr_1,
-		&emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
+	writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1);
+	writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1_shdw);
 }

 /**
 * Configure DDR CMD control registers
 */
-void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
+void config_cmd_ctrl(const struct cmd_control *cmd)
 {
-	writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
-	writel(cmd->cmd0dldiff, &ddr_cmd_reg[nr]->cm0dldiff);
-	writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
+	writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio);
+	writel(cmd->cmd0dldiff, &ddr_reg[0]->cm0dldiff);
+	writel(cmd->cmd0iclkout, &ddr_reg[0]->cm0iclkout);

-	writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
-	writel(cmd->cmd1dldiff, &ddr_cmd_reg[nr]->cm1dldiff);
-	writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
+	writel(cmd->cmd1csratio, &ddr_reg[0]->cm1csratio);
+	writel(cmd->cmd1dldiff, &ddr_reg[0]->cm1dldiff);
+	writel(cmd->cmd1iclkout, &ddr_reg[0]->cm1iclkout);

-	writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
-	writel(cmd->cmd2dldiff, &ddr_cmd_reg[nr]->cm2dldiff);
-	writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
+	writel(cmd->cmd2csratio, &ddr_reg[0]->cm2csratio);
+	writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff);
+	writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout);
 }

 /**
 * Configure DDR DATA registers
 */
-void config_ddr_data(const struct ddr_data *data, int nr)
+void config_ddr_data(int macrono, const struct ddr_data *data)
 {
-	int i;
-
-	for (i = 0; i < DDR_DATA_REGS_NR; i++) {
-		writel(data->datardsratio0,
-			&(ddr_data_reg[nr]+i)->dt0rdsratio0);
-		writel(data->datawdsratio0,
-			&(ddr_data_reg[nr]+i)->dt0wdsratio0);
-		writel(data->datawiratio0,
-			&(ddr_data_reg[nr]+i)->dt0wiratio0);
-		writel(data->datagiratio0,
-			&(ddr_data_reg[nr]+i)->dt0giratio0);
-		writel(data->datafwsratio0,
-			&(ddr_data_reg[nr]+i)->dt0fwsratio0);
-		writel(data->datawrsratio0,
-			&(ddr_data_reg[nr]+i)->dt0wrsratio0);
-		writel(data->datauserank0delay,
-			&(ddr_data_reg[nr]+i)->dt0rdelays0);
-		writel(data->datadldiff0,
-			&(ddr_data_reg[nr]+i)->dt0dldiff0);
-	}
+	writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0);
+	writel(data->datawdsratio0, &ddr_reg[macrono]->dt0wdsratio0);
+	writel(data->datawiratio0, &ddr_reg[macrono]->dt0wiratio0);
+	writel(data->datagiratio0, &ddr_reg[macrono]->dt0giratio0);
+	writel(data->datafwsratio0, &ddr_reg[macrono]->dt0fwsratio0);
+	writel(data->datawrsratio0, &ddr_reg[macrono]->dt0wrsratio0);
+	writel(data->datauserank0delay, &ddr_reg[macrono]->dt0rdelays0);
+	writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
 }

 void config_io_ctrl(unsigned long val)
--- a/arch/arm/cpu/armv7/am33xx/elm.c
+++ b/arch/arm/cpu/armv7/am33xx/elm.c
@@ -33,7 +33,7 @@
 #include <asm/io.h>
 #include <asm/errno.h>
 #include <asm/arch/cpu.h>
-#include <asm/omap_gpmc.h>
+#include <asm/arch/omap_gpmc.h>
 #include <asm/arch/elm.h>

 #define ELM_DEFAULT_POLY (0)
--- a/Show More
+++ b/Show More