Prepare v2015.07-rc3

Signed-off-by: Tom Rini <trini@konsulko.com>

Makefile

@@ -1,7 +1,7 @@
 VERSION = 2015
 PATCHLEVEL = 07
 SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION = -rc3
 NAME =
 
 # *DOCUMENTATION*

README

@@ -1048,9 +1048,7 @@ The following options need to be configured:
 		Monitor commands can be included or excluded
 		from the build by using the #include files
 		<config_cmd_all.h> and #undef'ing unwanted
-		commands, or using <config_cmd_default.h>
-		and augmenting with additional #define's
-		for wanted commands.
+		commands, or adding #define's for wanted commands.
 
 		The default command configuration includes all commands
 		except those marked below with a "*".
@@ -3037,6 +3035,19 @@ CBFS (Coreboot Filesystem) support
 		this is instead controlled by the value of
 		/config/load-environment.
 
+- Parallel Flash support:
+		CONFIG_SYS_NO_FLASH
+
+		Traditionally U-boot was run on systems with parallel NOR
+		flash. This option is used to disable support for parallel NOR
+		flash. This option should be defined if the board does not have
+		parallel flash.
+
+		If this option is not defined one of the generic flash drivers
+		(e.g.  CONFIG_FLASH_CFI_DRIVER or CONFIG_ST_SMI) must be
+		selected or the board must provide an implementation of the
+		flash API (see include/flash.h).
+
 - DataFlash Support:
 		CONFIG_HAS_DATAFLASH
 
@@ -3079,6 +3090,15 @@ CBFS (Coreboot Filesystem) support
 		memories can be connected with a given cs line.
 		Currently Xilinx Zynq qspi supports these type of connections.
 
+		CONFIG_SPI_FLASH_MTD		spi-flash MTD layer
+
+		Define this option to use mtd support for spi flash layer, this
+		adapter is for translating mtd_read/mtd_write commands into
+		spi_flash_read/spi_flash_write commands. It is not intended to
+		use it within sf_cmd or the SPI flash subsystem. Such an adapter
+		is needed for subsystems like UBI which can only operate on top
+		of the MTD layer.
+
 - SystemACE Support:
 		CONFIG_SYSTEMACE
 

arch/Kconfig

@@ -25,6 +25,7 @@ config ARM
 config AVR32
 	bool "AVR32 architecture"
 	select HAVE_GENERIC_BOARD
+	select SYS_GENERIC_BOARD
 
 config BLACKFIN
 	bool "Blackfin architecture"

arch/arc/Kconfig

@@ -4,9 +4,6 @@ menu "ARC architecture"
 config SYS_ARCH
 	default "arc"
 
-config USE_PRIVATE_LIBGCC
-	default y
-
 config SYS_CPU
 	default "arcv1" if ISA_ARCOMPACT
 	default "arcv2" if ISA_ARCV2

arch/arm/Kconfig

@@ -346,8 +346,13 @@ config TARGET_DRACO
 	select CPU_V7
 	select SUPPORT_SPL
 
-config TARGET_DXR2
-	bool "Support dxr2"
+config TARGET_THUBAN
+	bool "Support thuban"
+	select CPU_V7
+	select SUPPORT_SPL
+
+config TARGET_RASTABAN
+	bool "Support rastaban"
 	select CPU_V7
 	select SUPPORT_SPL
 
@@ -369,6 +374,14 @@ config TARGET_PENGWYN
 	select DM_SERIAL
 	select DM_GPIO
 
+config TARGET_AM335X_BALTOS
+	bool "Support am335x_baltos"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
 config TARGET_AM335X_EVM
 	bool "Support am335x_evm"
 	select CPU_V7
@@ -668,6 +681,7 @@ config TEGRA
 	select SUPPORT_SPL
 	select SPL
 	select OF_CONTROL
+	select SPL_DISABLE_OF_CONTROL
 	select CPU_V7
 	select DM
 	select DM_SPI_FLASH
@@ -794,6 +808,7 @@ config ARCH_UNIPHIER
 	select DM
 	select DM_SERIAL
 	select DM_I2C
+	select SPL_DISABLE_OF_CONTROL
 	help
 	  Support for UniPhier SoC family developed by Socionext Inc.
 	  (formerly, System LSI Business Division of Panasonic Corporation)
@@ -962,6 +977,7 @@ source "board/trizepsiv/Kconfig"
 source "board/ttcontrol/vision2/Kconfig"
 source "board/udoo/Kconfig"
 source "board/vpac270/Kconfig"
+source "board/vscom/baltos/Kconfig"
 source "board/wandboard/Kconfig"
 source "board/warp/Kconfig"
 source "board/woodburn/Kconfig"

arch/arm/cpu/armv7/am33xx/ddr.c

@@ -123,30 +123,33 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
 	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 
-	/* Perform hardware leveling. */
-	udelay(1000);
-	writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
-	       0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
-	writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) |
-	       0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
+	/* Perform hardware leveling for DDR3 */
+	if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) {
+		udelay(1000);
+		writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
+		       0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
+		writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) |
+		       0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
 
-	writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
+		writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
 
-	/* Enable read leveling */
-	writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
+		/* Enable read leveling */
+		writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
 
-	/*
-	 * Enable full read and write leveling.  Wait for read and write
-	 * leveling bit to clear RDWRLVLFULL_START bit 31
-	 */
-	while((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000) != 0)
-		;
+		/*
+		 * Enable full read and write leveling.  Wait for read and write
+		 * leveling bit to clear RDWRLVLFULL_START bit 31
+		 */
+		while ((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000)
+		      != 0)
+			;
 
-	/* Check the timeout register to see if leveling is complete */
-	if((readl(&emif_reg[nr]->emif_status) & 0x70) != 0)
-		puts("DDR3 H/W leveling incomplete with errors\n");
+		/* Check the timeout register to see if leveling is complete */
+		if ((readl(&emif_reg[nr]->emif_status) & 0x70) != 0)
+			puts("DDR3 H/W leveling incomplete with errors\n");
 
-	if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) {
+	} else {
+		/* DDR2 */
 		configure_mr(nr, 0);
 		configure_mr(nr, 1);
 	}
@@ -182,10 +185,50 @@ void set_sdram_timings(const struct emif_regs *regs, int nr)
 	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
 }
 
+/*
+ * Configure EXT PHY registers for software leveling
+ */
+static void ext_phy_settings_swlvl(const struct emif_regs *regs, int nr)
+{
+	u32 *ext_phy_ctrl_base = 0;
+	u32 *emif_ext_phy_ctrl_base = 0;
+	__maybe_unused const u32 *ext_phy_ctrl_const_regs;
+	u32 i = 0;
+	__maybe_unused u32 size;
+
+	ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
+	emif_ext_phy_ctrl_base =
+			(u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
+
+	/* Configure external phy control timing registers */
+	for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
+		writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
+		/* Update shadow registers */
+		writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
+	}
+
+#ifdef CONFIG_AM43XX
+	/*
+	 * External phy 6-24 registers do not change with ddr frequency.
+	 * These only need to be set on DDR2 on AM43xx.
+	 */
+	emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
+
+	if (!size)
+		return;
+
+	for (i = 0; i < size; i++) {
+		writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
+		/* Update shadow registers */
+		writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
+	}
+#endif
+}
+
 /*
  * Configure EXT PHY registers for hardware leveling
  */
-static void ext_phy_settings(const struct emif_regs *regs, int nr)
+static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr)
 {
 	/*
 	 * Enable hardware leveling on the EMIF.  For details about these
@@ -256,8 +299,12 @@ void config_ddr_phy(const struct emif_regs *regs, int nr)
 	writel(regs->emif_ddr_phy_ctlr_1,
 		&emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
 
-	if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5)
-		ext_phy_settings(regs, nr);
+	if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5) {
+		if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
+			ext_phy_settings_hwlvl(regs, nr);
+		else
+			ext_phy_settings_swlvl(regs, nr);
+	}
 }
 
 /**

arch/arm/cpu/armv7/am33xx/emif4.c

@@ -124,8 +124,9 @@ void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
 	/* Set CKE to be controlled by EMIF/DDR PHY */
 	writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
 
-	/* Allow EMIF to control DDR_RESET */
-	writel(0x00000000, &ddrctrl->ddrioctrl);
+	if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
+		/* Allow EMIF to control DDR_RESET */
+		writel(0x00000000, &ddrctrl->ddrioctrl);
 #endif
 
 	/* Program EMIF instance */

arch/arm/cpu/armv7/cpu.c

@@ -24,7 +24,7 @@
 
 void __weak cpu_cache_initialization(void){}
 
-int cleanup_before_linux(void)
+int cleanup_before_linux_select(int flags)
 {
 	/*
 	 * this function is called just before we call linux
@@ -42,24 +42,30 @@ int cleanup_before_linux(void)
 	icache_disable();
 	invalidate_icache_all();
 
-	/*
-	 * turn off D-cache
-	 * dcache_disable() in turn flushes the d-cache and disables MMU
-	 */
-	dcache_disable();
-	v7_outer_cache_disable();
+	if (flags & CBL_DISABLE_CACHES) {
+		/*
+		* turn off D-cache
+		* dcache_disable() in turn flushes the d-cache and disables MMU
+		*/
+		dcache_disable();
+		v7_outer_cache_disable();
 
-	/*
-	 * After D-cache is flushed and before it is disabled there may
-	 * be some new valid entries brought into the cache. We are sure
-	 * that these lines are not dirty and will not affect our execution.
-	 * (because unwinding the call-stack and setting a bit in CP15 SCTLR
-	 * is all we did during this. We have not pushed anything on to the
-	 * stack. Neither have we affected any static data)
-	 * So just invalidate the entire d-cache again to avoid coherency
-	 * problems for kernel
-	 */
-	invalidate_dcache_all();
+		/*
+		* After D-cache is flushed and before it is disabled there may
+		* be some new valid entries brought into the cache. We are
+		* sure that these lines are not dirty and will not affect our
+		* execution. (because unwinding the call-stack and setting a
+		* bit in CP15 SCTRL is all we did during this. We have not
+		* pushed anything on to the stack. Neither have we affected
+		* any static data) So just invalidate the entire d-cache again
+		* to avoid coherency problems for kernel
+		*/
+		invalidate_dcache_all();
+	} else {
+		flush_dcache_all();
+		invalidate_icache_all();
+		icache_enable();
+	}
 
 	/*
 	 * Some CPU need more cache attention before starting the kernel.
@@ -68,3 +74,8 @@ int cleanup_before_linux(void)
 
 	return 0;
 }
+
+int cleanup_before_linux(void)
+{
+	return cleanup_before_linux_select(CBL_ALL);
+}

arch/arm/cpu/armv7/exynos/Kconfig

@@ -8,6 +8,7 @@ config TARGET_SMDKV310
 	select SUPPORT_SPL
 	bool "Exynos4210 SMDKV310 board"
 	select OF_CONTROL
+	select SPL_DISABLE_OF_CONTROL
 
 config TARGET_TRATS
 	bool "Exynos4210 Trats board"
@@ -28,6 +29,7 @@ config TARGET_ODROID
 config TARGET_ODROID_XU3
 	bool "Exynos5422 Odroid board"
 	select OF_CONTROL
+	select SPL_DISABLE_OF_CONTROL
 
 config TARGET_ARNDALE
 	bool "Exynos5250 Arndale board"
@@ -35,40 +37,43 @@ config TARGET_ARNDALE
 	select CPU_V7_HAS_VIRT
 	select SUPPORT_SPL
 	select OF_CONTROL
+	select SPL_DISABLE_OF_CONTROL
 
 config TARGET_SMDK5250
 	bool "SMDK5250 board"
 	select SUPPORT_SPL
 	select OF_CONTROL
+	select SPL_DISABLE_OF_CONTROL
 
 config TARGET_SNOW
 	bool "Snow board"
 	select SUPPORT_SPL
 	select OF_CONTROL
+	select SPL_DISABLE_OF_CONTROL
 
 config TARGET_SMDK5420
 	bool "SMDK5420 board"
 	select SUPPORT_SPL
 	select OF_CONTROL
+	select SPL_DISABLE_OF_CONTROL
 
 config TARGET_PEACH_PI
 	bool "Peach Pi board"
 	select SUPPORT_SPL
 	select OF_CONTROL
+	select SPL_DISABLE_OF_CONTROL
 
 config TARGET_PEACH_PIT
 	bool "Peach Pit board"
 	select SUPPORT_SPL
 	select OF_CONTROL
+	select SPL_DISABLE_OF_CONTROL
 
 endchoice
 
 config SYS_SOC
 	default "exynos"
 
-config DM_USB
-	default y
-
 source "board/samsung/smdkv310/Kconfig"
 source "board/samsung/trats/Kconfig"
 source "board/samsung/universal_c210/Kconfig"

arch/arm/cpu/armv7/omap-common/clocks-common.c

@@ -372,6 +372,7 @@ static void setup_dplls(void)
 {
 	u32 temp;
 	const struct dpll_params *params;
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
 
 	debug("setup_dplls\n");
 
@@ -382,7 +383,8 @@ static void setup_dplls(void)
 	 * Core DPLL will be locked after setting up EMIF
 	 * using the FREQ_UPDATE method(freq_update_core())
 	 */
-	if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
+	if (emif_sdram_type(readl(&emif->emif_sdram_config)) ==
+	    EMIF_SDRAM_TYPE_LPDDR2)
 		do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
 							DPLL_NO_LOCK, "core");
 	else
@@ -508,6 +510,12 @@ static u32 optimize_vcore_voltage(struct volts const *v)
 	return val;
 }
 
+#ifdef CONFIG_IODELAY_RECALIBRATION
+void __weak recalibrate_iodelay(void)
+{
+}
+#endif
+
 /*
  * Setup the voltages for the main SoC core power domains.
  * We start with the maximum voltages allowed here, as set in the corresponding
@@ -561,6 +569,16 @@ void scale_vcores(struct vcores_data const *vcores)
 
 	debug("cor: %d\n", vcores->core.value);
 	do_scale_vcore(vcores->core.addr, vcores->core.value, vcores->core.pmic);
+	/*
+	 * IO delay recalibration should be done immediately after
+	 * adjusting AVS voltages for VDD_CORE_L.
+	 * Respective boards should call __recalibrate_iodelay()
+	 * with proper mux, virtual and manual mode configurations.
+	 */
+#ifdef CONFIG_IODELAY_RECALIBRATION
+	recalibrate_iodelay();
+#endif
+
 	debug("mpu: %d\n", vcores->mpu.value);
 	do_scale_vcore(vcores->mpu.addr, vcores->mpu.value, vcores->mpu.pmic);
 	/* Configure MPU ABB LDO after scale */
@@ -587,6 +605,16 @@ void scale_vcores(struct vcores_data const *vcores)
 	val = optimize_vcore_voltage(&vcores->core);
 	do_scale_vcore(vcores->core.addr, val, vcores->core.pmic);
 
+	/*
+	 * IO delay recalibration should be done immediately after
+	 * adjusting AVS voltages for VDD_CORE_L.
+	 * Respective boards should call __recalibrate_iodelay()
+	 * with proper mux, virtual and manual mode configurations.
+	 */
+#ifdef CONFIG_IODELAY_RECALIBRATION
+	recalibrate_iodelay();
+#endif
+
 	val = optimize_vcore_voltage(&vcores->mpu);
 	do_scale_vcore(vcores->mpu.addr, val, vcores->mpu.pmic);
 

arch/arm/cpu/armv7/omap-common/emif-common.c

@@ -242,13 +242,122 @@ static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
 	       __udelay(130);
 }
 
-static void ddr3_leveling(u32 base, const struct emif_regs *regs)
+static void update_hwleveling_output(u32 base, const struct emif_regs *regs)
 {
-	if (is_omap54xx())
-		omap5_ddr3_leveling(base, regs);
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+	u32 *emif_ext_phy_ctrl_reg, *emif_phy_status;
+	u32 reg, i;
+
+	emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7];
+
+	/* Update PHY_REG_RDDQS_RATIO */
+	emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7;
+	for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) {
+		reg = readl(emif_phy_status++);
+		writel(reg, emif_ext_phy_ctrl_reg++);
+		writel(reg, emif_ext_phy_ctrl_reg++);
+	}
+
+	/* Update PHY_REG_FIFO_WE_SLAVE_RATIO */
+	emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2;
+	for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) {
+		reg = readl(emif_phy_status++);
+		writel(reg, emif_ext_phy_ctrl_reg++);
+		writel(reg, emif_ext_phy_ctrl_reg++);
+	}
+
+	/* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */
+	emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12;
+	for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) {
+		reg = readl(emif_phy_status++);
+		writel(reg, emif_ext_phy_ctrl_reg++);
+		writel(reg, emif_ext_phy_ctrl_reg++);
+	}
+
+	/* Disable Leveling */
+	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
+	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
+	writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);
 }
 
-static void ddr3_init(u32 base, const struct emif_regs *regs)
+static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	/* Clear Error Status */
+	clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36,
+			EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR,
+			EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
+
+	clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36_shdw,
+			EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR,
+			EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
+
+	/* Disable refreshed before leveling */
+	clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT,
+			EMIF_REG_INITREF_DIS_SHIFT);
+
+	/* Start Full leveling */
+	writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
+
+	__udelay(300);
+
+	/* Check for leveling timeout */
+	if (readl(&emif->emif_status) & EMIF_REG_LEVELING_TO_MASK) {
+		printf("Leveling timeout on EMIF%d\n", emif_num(base));
+		return;
+	}
+
+	/* Enable refreshes after leveling */
+	clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT);
+
+	debug("HW leveling success\n");
+	/*
+	 * Update slave ratios in EXT_PHY_CTRLx registers
+	 * as per HW leveling output
+	 */
+	update_hwleveling_output(base, regs);
+}
+
+static void dra7_ddr3_init(u32 base, const struct emif_regs *regs)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	if (warm_reset())
+		emif_reset_phy(base);
+	do_ext_phy_settings(base, regs);
+
+	writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK,
+	       &emif->emif_sdram_ref_ctrl);
+	/* Update timing registers */
+	writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
+	writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
+	writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
+
+	writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config);
+	writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
+	writel(regs->zq_config, &emif->emif_zq_config);
+	writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
+	writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
+	writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl);
+
+	writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
+	writel(regs->emif_rd_wr_exec_thresh, &emif->emif_rd_wr_exec_thresh);
+
+	writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
+
+	writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
+	writel(regs->sdram_config_init, &emif->emif_sdram_config);
+
+	__udelay(1000);
+
+	writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);
+
+	if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK)
+		dra7_ddr3_leveling(base, regs);
+}
+
+static void omap5_ddr3_init(u32 base, const struct emif_regs *regs)
 {
 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 
@@ -269,25 +378,20 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
 
 	writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
 
-	/*
-	 * The same sequence should work on OMAP5432 as well. But strange that
-	 * it is not working
-	 */
-	if (is_dra7xx()) {
-		do_ext_phy_settings(base, regs);
-		writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);
-		writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
-		writel(regs->sdram_config_init, &emif->emif_sdram_config);
-	} else {
-		writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
-		writel(regs->sdram_config_init, &emif->emif_sdram_config);
-		do_ext_phy_settings(base, regs);
-	}
+	writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
+	writel(regs->sdram_config_init, &emif->emif_sdram_config);
+	do_ext_phy_settings(base, regs);
 
-	/* enable leveling */
 	writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
+	omap5_ddr3_leveling(base, regs);
+}
 
-	ddr3_leveling(base, regs);
+static void ddr3_init(u32 base, const struct emif_regs *regs)
+{
+	if (is_omap54xx())
+		omap5_ddr3_init(base, regs);
+	else
+		dra7_ddr3_init(base, regs);
 }
 
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
@@ -1066,16 +1170,18 @@ static void do_sdram_init(u32 base)
 	 * Changing the timing registers in EMIF can happen(going from one
 	 * OPP to another)
 	 */
-	if (!(in_sdram || warm_reset())) {
-		if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
+	if (!in_sdram && (!warm_reset() || is_dra7xx())) {
+		if (emif_sdram_type(regs->sdram_config) ==
+		    EMIF_SDRAM_TYPE_LPDDR2)
 			lpddr2_init(base, regs);
 		else
 			ddr3_init(base, regs);
 	}
-	if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
+	if (warm_reset() && (emif_sdram_type(regs->sdram_config) ==
+	    EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) {
 		set_lpmode_selfrefresh(base);
 		emif_reset_phy(base);
-		ddr3_leveling(base, regs);
+		omap5_ddr3_leveling(base, regs);
 	}
 
 	/* Write to the shadow registers */
@@ -1294,7 +1400,8 @@ static void do_bug0039_workaround(u32 base)
 void sdram_init(void)
 {
 	u32 in_sdram, size_prog, size_detect;
-	u32 sdram_type = emif_sdram_type();
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
+	u32 sdram_type = emif_sdram_type(emif->emif_sdram_config);
 
 	debug(">>sdram_init()\n");
 

arch/arm/cpu/armv7/omap5/Makefile

@@ -11,3 +11,4 @@ obj-y	+= sdram.o
 obj-y	+= prcm-regs.o
 obj-y	+= hw_data.o
 obj-y	+= abb.o
+obj-$(CONFIG_IODELAY_RECALIBRATION) += dra7xx_iodelay.o

arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c

@@ -0,0 +1,238 @@
+/*
+ * (C) Copyright 2015
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/utils.h>
+#include <asm/arch/dra7xx_iodelay.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mux_dra7xx.h>
+#include <asm/omap_common.h>
+
+static int isolate_io(u32 isolate)
+{
+	if (isolate) {
+		clrsetbits_le32((*ctrl)->control_pbias, SDCARD_PWRDNZ,
+				SDCARD_PWRDNZ);
+		clrsetbits_le32((*ctrl)->control_pbias, SDCARD_BIAS_PWRDNZ,
+				SDCARD_BIAS_PWRDNZ);
+	}
+
+	/* Override control on ISOCLKIN signal to IO pad ring. */
+	clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK,
+			PMCTRL_ISOCLK_OVERRIDE_CTRL);
+	if (!wait_on_value(PMCTRL_ISOCLK_STATUS_MASK, PMCTRL_ISOCLK_STATUS_MASK,
+			   (u32 *)(*prcm)->prm_io_pmctrl, LDELAY))
+		return ERR_DEISOLATE_IO << isolate;
+
+	/* Isolate/Deisolate IO */
+	clrsetbits_le32((*ctrl)->ctrl_core_sma_sw_0, CTRL_ISOLATE_MASK,
+			isolate << CTRL_ISOLATE_SHIFT);
+	/* Dummy read to add delay t > 10ns */
+	readl((*ctrl)->ctrl_core_sma_sw_0);
+
+	/* Return control on ISOCLKIN to hardware */
+	clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK,
+			PMCTRL_ISOCLK_NOT_OVERRIDE_CTRL);
+	if (!wait_on_value(PMCTRL_ISOCLK_STATUS_MASK,
+			   0 << PMCTRL_ISOCLK_STATUS_SHIFT,
+			   (u32 *)(*prcm)->prm_io_pmctrl, LDELAY))
+		return ERR_DEISOLATE_IO << isolate;
+
+	return 0;
+}
+
+static int calibrate_iodelay(u32 base)
+{
+	u32 reg;
+
+	/* Configure REFCLK period */
+	reg = readl(base + CFG_REG_2_OFFSET);
+	reg &= ~CFG_REG_REFCLK_PERIOD_MASK;
+	reg |= CFG_REG_REFCLK_PERIOD;
+	writel(reg, base + CFG_REG_2_OFFSET);
+
+	/* Initiate Calibration */
+	clrsetbits_le32(base + CFG_REG_0_OFFSET, CFG_REG_CALIB_STRT_MASK,
+			CFG_REG_CALIB_STRT << CFG_REG_CALIB_STRT_SHIFT);
+	if (!wait_on_value(CFG_REG_CALIB_STRT_MASK, CFG_REG_CALIB_END,
+			   (u32 *)(base + CFG_REG_0_OFFSET), LDELAY))
+		return ERR_CALIBRATE_IODELAY;
+
+	return 0;
+}
+
+static int update_delay_mechanism(u32 base)
+{
+	/* Initiate the reload of calibrated values. */
+	clrsetbits_le32(base + CFG_REG_0_OFFSET, CFG_REG_ROM_READ_MASK,
+			CFG_REG_ROM_READ_START);
+	if (!wait_on_value(CFG_REG_ROM_READ_MASK, CFG_REG_ROM_READ_END,
+			   (u32 *)(base + CFG_REG_0_OFFSET), LDELAY))
+		return ERR_UPDATE_DELAY;
+
+	return 0;
+}
+
+static u32 calculate_delay(u32 base, u16 offset, u16 den)
+{
+	u16 refclk_period, dly_cnt, ref_cnt;
+	u32 reg, q, r;
+
+	refclk_period = readl(base + CFG_REG_2_OFFSET) &
+			      CFG_REG_REFCLK_PERIOD_MASK;
+
+	reg = readl(base + offset);
+	dly_cnt = (reg & CFG_REG_DLY_CNT_MASK) >> CFG_REG_DLY_CNT_SHIFT;
+	ref_cnt = (reg & CFG_REG_REF_CNT_MASK) >> CFG_REG_REF_CNT_SHIFT;
+
+	if (!dly_cnt || !den)
+		return 0;
+
+	/*
+	 * To avoid overflow and integer truncation, delay value
+	 * is calculated as quotient + remainder.
+	 */
+	q = 5 * ((ref_cnt * refclk_period) / (dly_cnt * den));
+	r = (10 * ((ref_cnt * refclk_period) % (dly_cnt * den))) /
+		(2 * dly_cnt * den);
+
+	return q + r;
+}
+
+static u32 get_cfg_reg(u16 a_delay, u16 g_delay, u32 cpde, u32 fpde)
+{
+	u32 g_delay_coarse, g_delay_fine;
+	u32 a_delay_coarse, a_delay_fine;
+	u32 c_elements, f_elements;
+	u32 total_delay, reg = 0;
+
+	g_delay_coarse = g_delay / 920;
+	g_delay_fine = ((g_delay % 920) * 10) / 60;
+
+	a_delay_coarse = a_delay / cpde;
+	a_delay_fine = ((a_delay % cpde) * 10) / fpde;
+
+	c_elements = g_delay_coarse + a_delay_coarse;
+	f_elements = (g_delay_fine + a_delay_fine) / 10;
+
+	if (f_elements > 22) {
+		total_delay = c_elements * cpde + f_elements * fpde;
+
+		c_elements = total_delay / cpde;
+		f_elements = (total_delay % cpde) / fpde;
+	}
+
+	reg = (c_elements << CFG_X_COARSE_DLY_SHIFT) & CFG_X_COARSE_DLY_MASK;
+	reg |= (f_elements << CFG_X_FINE_DLY_SHIFT) & CFG_X_FINE_DLY_MASK;
+	reg |= CFG_X_SIGNATURE << CFG_X_SIGNATURE_SHIFT;
+	reg |= CFG_X_LOCK << CFG_X_LOCK_SHIFT;
+
+	return reg;
+}
+
+static int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array,
+			   int niodelays)
+{
+	struct iodelay_cfg_entry *iodelay = (struct iodelay_cfg_entry *)array;
+	u32 reg, cpde, fpde, i;
+
+	if (!niodelays)
+		return 0;
+
+	cpde = calculate_delay((*ctrl)->iodelay_config_base, CFG_REG_3_OFFSET,
+			       88);
+	if (!cpde)
+		return ERR_CPDE;
+
+	fpde = calculate_delay((*ctrl)->iodelay_config_base, CFG_REG_4_OFFSET,
+			       264);
+	if (!fpde)
+		return ERR_FPDE;
+
+	for (i = 0; i < niodelays; i++, iodelay++) {
+		reg = get_cfg_reg(iodelay->a_delay, iodelay->g_delay, cpde,
+				  fpde);
+		writel(reg, base + iodelay->offset);
+	}
+
+	return 0;
+}
+
+void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
+			   struct iodelay_cfg_entry const *iodelay,
+			   int niodelays)
+{
+	int ret = 0;
+
+	/* IO recalibration should be done only from SRAM */
+	if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) {
+		puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n");
+		return;
+	}
+
+	/* unlock IODELAY CONFIG registers */
+	writel(CFG_IODELAY_UNLOCK_KEY, (*ctrl)->iodelay_config_base +
+	       CFG_REG_8_OFFSET);
+
+	ret = calibrate_iodelay((*ctrl)->iodelay_config_base);
+	if (ret)
+		goto err;
+
+	ret = isolate_io(ISOLATE_IO);
+	if (ret)
+		goto err;
+
+	ret = update_delay_mechanism((*ctrl)->iodelay_config_base);
+	if (ret)
+		goto err;
+
+	/* Configure Mux settings */
+	do_set_mux32((*ctrl)->control_padconf_core_base, pad, npads);
+
+	/* Configure Manual IO timing modes */
+	ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
+	if (ret)
+		goto err;
+
+	ret = isolate_io(DEISOLATE_IO);
+
+err:
+	/* lock IODELAY CONFIG registers */
+	writel(CFG_IODELAY_LOCK_KEY, (*ctrl)->iodelay_config_base +
+	       CFG_REG_8_OFFSET);
+	/*
+	 * UART cannot be used during IO recalibration sequence as IOs are in
+	 * isolation. So error handling and debug prints are done after
+	 * complete IO delay recalibration sequence
+	 */
+	switch (ret) {
+	case ERR_CALIBRATE_IODELAY:
+		puts("IODELAY: IO delay calibration sequence failed\n");
+		break;
+	case ERR_ISOLATE_IO:
+		puts("IODELAY: Isolation of Device IOs failed\n");
+		break;
+	case ERR_UPDATE_DELAY:
+		puts("IODELAY: Delay mechanism update with new calibrated values failed\n");
+		break;
+	case ERR_DEISOLATE_IO:
+		puts("IODELAY: De-isolation of Device IOs failed\n");
+		break;
+	case ERR_CPDE:
+		puts("IODELAY: CPDE calculation failed\n");
+		break;
+	case ERR_FPDE:
+		puts("IODELAY: FPDE calculation failed\n");
+		break;
+	default:
+		debug("IODELAY: IO delay recalibration successfully completed\n");
+	}
+}

arch/arm/cpu/armv7/omap5/hw_data.c

@@ -534,6 +534,9 @@ void enable_basic_clocks(void)
 void enable_basic_uboot_clocks(void)
 {
 	u32 const clk_domains_essential[] = {
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+		(*prcm)->cm_ipu_clkstctrl,
+#endif
 		0
 	};
 
@@ -547,7 +550,11 @@ void enable_basic_uboot_clocks(void)
 		(*prcm)->cm_l4per_i2c2_clkctrl,
 		(*prcm)->cm_l4per_i2c3_clkctrl,
 		(*prcm)->cm_l4per_i2c4_clkctrl,
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+		(*prcm)->cm_ipu_i2c5_clkctrl,
+#else
 		(*prcm)->cm_l4per_i2c5_clkctrl,
+#endif
 		(*prcm)->cm_l3init_hsusbhost_clkctrl,
 		(*prcm)->cm_l3init_fsusb_clkctrl,
 		0
@@ -592,8 +599,8 @@ const struct ctrl_ioregs ioregs_dra7xx_es1 = {
 	.ctrl_ddrch = 0x40404040,
 	.ctrl_lpddr2ch = 0x40404040,
 	.ctrl_ddr3ch = 0x80808080,
-	.ctrl_ddrio_0 = 0xA2084210,
-	.ctrl_ddrio_1 = 0x84210840,
+	.ctrl_ddrio_0 = 0x00094A40,
+	.ctrl_ddrio_1 = 0x04A52000,
 	.ctrl_ddrio_2 = 0x84210000,
 	.ctrl_emif_sdram_config_ext = 0x0001C1A7,
 	.ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
@@ -604,8 +611,8 @@ const struct ctrl_ioregs ioregs_dra72x_es1 = {
 	.ctrl_ddrch = 0x40404040,
 	.ctrl_lpddr2ch = 0x40404040,
 	.ctrl_ddr3ch = 0x60606080,
-	.ctrl_ddrio_0 = 0xA2084210,
-	.ctrl_ddrio_1 = 0x84210840,
+	.ctrl_ddrio_0 = 0x00094A40,
+	.ctrl_ddrio_1 = 0x04A52000,
 	.ctrl_ddrio_2 = 0x84210000,
 	.ctrl_emif_sdram_config_ext = 0x0001C1A7,
 	.ctrl_emif_sdram_config_ext_final = 0x0001C1A7,

arch/arm/cpu/armv7/omap5/hwinit.c

@@ -40,6 +40,15 @@ static struct gpio_bank gpio_bank_54xx[8] = {
 
 const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
 
+void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size)
+{
+	int i;
+	struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
+
+	for (i = 0; i < size; i++, pad++)
+		writel(pad->val, base + pad->offset);
+}
+
 #ifdef CONFIG_SPL_BUILD
 /* LPDDR2 specific IO settings */
 static void io_settings_lpddr2(void)
@@ -75,16 +84,20 @@ static void io_settings_ddr3(void)
 
 	writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
 	writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
-	writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
+
+	if (!is_dra7xx()) {
+		writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
+		writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
+	}
 
 	/* omap5432 does not use lpddr2 */
 	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
-	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
 
 	writel(ioregs->ctrl_emif_sdram_config_ext,
 	       (*ctrl)->control_emif1_sdram_config_ext);
-	writel(ioregs->ctrl_emif_sdram_config_ext,
-	       (*ctrl)->control_emif2_sdram_config_ext);
+	if (!is_dra72x())
+		writel(ioregs->ctrl_emif_sdram_config_ext,
+		       (*ctrl)->control_emif2_sdram_config_ext);
 
 	if (is_omap54xx()) {
 		/* Disable DLL select */
@@ -109,6 +122,7 @@ static void io_settings_ddr3(void)
 void do_io_settings(void)
 {
 	u32 io_settings = 0, mask = 0;
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
 
 	/* Impedance settings EMMC, C2C 1,2, hsi2 */
 	mask = (ds_mask << 2) | (ds_mask << 8) |
@@ -164,7 +178,7 @@ void do_io_settings(void)
 		       (sc_fast << 17) | (sc_fast << 14);
 	writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
 
-	if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
+	if (emif_sdram_type(emif->emif_sdram_config) == EMIF_SDRAM_TYPE_LPDDR2)
 		io_settings_lpddr2();
 	else
 		io_settings_ddr3();

arch/arm/cpu/armv7/omap5/prcm-regs.c

@@ -378,6 +378,7 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
 	.control_status				= 0x4A002134,
 	.control_phy_power_usb			= 0x4A002370,
 	.control_phy_power_sata			= 0x4A002374,
+	.ctrl_core_sma_sw_0			= 0x4A0023FC,
 	.control_core_mac_id_0_lo		= 0x4A002514,
 	.control_core_mac_id_0_hi		= 0x4A002518,
 	.control_core_mac_id_1_lo		= 0x4A00251C,
@@ -457,6 +458,7 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
 	.control_efuse_3			= 0x4AE0C5D0,
 	.control_efuse_4			= 0x4AE0C5D4,
 	.control_efuse_13			= 0x4AE0C5F0,
+	.iodelay_config_base			= 0x4844A000,
 };
 
 struct prcm_regs const omap5_es2_prcm = {
@@ -815,6 +817,10 @@ struct prcm_regs const dra7xx_prcm = {
 	.cm_dsp_clkstctrl			= 0x4a005400,
 	.cm_dsp_dsp_clkctrl			= 0x4a005420,
 
+	/* cm IPU */
+	.cm_ipu_clkstctrl			= 0x4a005540,
+	.cm_ipu_i2c5_clkctrl			= 0x4a005578,
+
 	/* prm irqstatus regs */
 	.prm_irqstatus_mpu_2			= 0x4ae06014,
 
@@ -976,6 +982,7 @@ struct prcm_regs const dra7xx_prcm = {
 	.prm_rstctrl				= 0x4ae07d00,
 	.prm_rstst				= 0x4ae07d04,
 	.prm_rsttime				= 0x4ae07d08,
+	.prm_io_pmctrl				= 0x4ae07d20,
 	.prm_vc_val_bypass			= 0x4ae07da0,
 	.prm_vc_cfg_i2c_mode			= 0x4ae07db4,
 	.prm_vc_cfg_i2c_clk			= 0x4ae07db8,

arch/arm/cpu/armv7/omap5/sdram.c

@@ -146,18 +146,18 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
 	.sdram_tim1                     = 0xCCCF36B3,
 	.sdram_tim2                     = 0x308F7FDA,
 	.sdram_tim3                     = 0x027F88A8,
-	.read_idle_ctrl                 = 0x00050001,
+	.read_idle_ctrl                 = 0x00050000,
 	.zq_config                      = 0x0007190B,
 	.temp_alert_config              = 0x00000000,
-	.emif_ddr_phy_ctlr_1_init       = 0x0E24400A,
-	.emif_ddr_phy_ctlr_1            = 0x0E24400A,
+	.emif_ddr_phy_ctlr_1_init       = 0x0024400B,
+	.emif_ddr_phy_ctlr_1            = 0x0E24400B,
 	.emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 	.emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 	.emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 	.emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
 	.emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
-	.emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 	.emif_rd_wr_lvl_ctl             = 0x00000000,
 	.emif_rd_wr_exec_thresh         = 0x00000305
 };
@@ -171,18 +171,18 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
 	.sdram_tim1                     = 0xCCCF36B3,
 	.sdram_tim2                     = 0x308F7FDA,
 	.sdram_tim3                     = 0x027F88A8,
-	.read_idle_ctrl                 = 0x00050001,
+	.read_idle_ctrl                 = 0x00050000,
 	.zq_config                      = 0x0007190B,
 	.temp_alert_config              = 0x00000000,
-	.emif_ddr_phy_ctlr_1_init       = 0x0E24400A,
-	.emif_ddr_phy_ctlr_1            = 0x0E24400A,
+	.emif_ddr_phy_ctlr_1_init       = 0x0024400B,
+	.emif_ddr_phy_ctlr_1            = 0x0E24400B,
 	.emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 	.emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 	.emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 	.emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
 	.emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
-	.emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 	.emif_rd_wr_lvl_ctl             = 0x00000000,
 	.emif_rd_wr_exec_thresh         = 0x00000305
 };
@@ -191,15 +191,15 @@ const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
 	.sdram_config_init              = 0x61862B32,
 	.sdram_config                   = 0x61862B32,
 	.sdram_config2			= 0x08000000,
-	.ref_ctrl                       = 0x0000493E,
+	.ref_ctrl                       = 0x0000514C,
 	.ref_ctrl_final			= 0x0000144A,
 	.sdram_tim1                     = 0xD113781C,
-	.sdram_tim2                     = 0x308F7FE3,
-	.sdram_tim3                     = 0x009F86A8,
+	.sdram_tim2                     = 0x305A7FDA,
+	.sdram_tim3                     = 0x409F86A8,
 	.read_idle_ctrl                 = 0x00050000,
-	.zq_config                      = 0x0007190B,
+	.zq_config                      = 0x5007190B,
 	.temp_alert_config              = 0x00000000,
-	.emif_ddr_phy_ctlr_1_init       = 0x0E24400D,
+	.emif_ddr_phy_ctlr_1_init       = 0x0024400D,
 	.emif_ddr_phy_ctlr_1            = 0x0E24400D,
 	.emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 	.emif_ddr_ext_phy_ctrl_2        = 0x00A400A4,
@@ -207,7 +207,7 @@ const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
 	.emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
 	.emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
 	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
-	.emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 	.emif_rd_wr_lvl_ctl             = 0x00000000,
 	.emif_rd_wr_exec_thresh         = 0x00000305
 };
@@ -421,8 +421,14 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
 	0x0
 };
 
+/* Ext phy ctrl 1-35 regs */
 const u32
 dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
+	0x10040100,
+	0x00910091,
+	0x00950095,
+	0x009B009B,
+	0x009E009E,
 	0x00980098,
 	0x00340034,
 	0x00350035,
@@ -441,17 +447,28 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
 	0x00500050,
 	0x00000000,
 	0x00600020,
-	0x40010080,
+	0x40011080,
 	0x08102040,
 	0x0,
 	0x0,
 	0x0,
 	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
 	0x0
 };
 
+/* Ext phy ctrl 1-35 regs */
 const u32
 dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
+	0x10040100,
+	0x00910091,
+	0x00950095,
+	0x009B009B,
+	0x009E009E,
 	0x00980098,
 	0x00330033,
 	0x00330033,
@@ -470,17 +487,28 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
 	0x00500050,
 	0x00000000,
 	0x00600020,
-	0x40010080,
+	0x40011080,
 	0x08102040,
 	0x0,
 	0x0,
 	0x0,
 	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
 	0x0
 };
 
+/* Ext phy ctrl 1-35 regs */
 const u32
 dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = {
+	0x10040100,
+	0x00A400A4,
+	0x00A900A9,
+	0x00B000B0,
+	0x00B000B0,
 	0x00A400A4,
 	0x00390039,
 	0x00320032,
@@ -505,6 +533,11 @@ dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = {
 	0x0,
 	0x0,
 	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
 	0x0
 };
 
@@ -562,7 +595,7 @@ void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
 	*regs = &mr_regs;
 }
 
-void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
+static void do_ext_phy_settings_omap5(u32 base, const struct emif_regs *regs)
 {
 	u32 *ext_phy_ctrl_base = 0;
 	u32 *emif_ext_phy_ctrl_base = 0;
@@ -601,6 +634,58 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
 	}
 }
 
+static void do_ext_phy_settings_dra7(u32 base, const struct emif_regs *regs)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+	u32 *emif_ext_phy_ctrl_base = 0;
+	u32 emif_nr;
+	const u32 *ext_phy_ctrl_const_regs;
+	u32 i, hw_leveling, size;
+
+	emif_nr = (base == EMIF1_BASE) ? 1 : 2;
+
+	hw_leveling = regs->emif_rd_wr_lvl_rmp_ctl >> EMIF_REG_RDWRLVL_EN_SHIFT;
+
+	emif_ext_phy_ctrl_base = (u32 *)&(emif->emif_ddr_ext_phy_ctrl_1);
+
+	emif_get_ext_phy_ctrl_const_regs(emif_nr,
+					 &ext_phy_ctrl_const_regs, &size);
+
+	writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[0]);
+	writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[1]);
+
+	if (!hw_leveling) {
+		/*
+		 * Copy the predefined PHY register values
+		 * in case of sw leveling
+		 */
+		for (i = 1; i < 25; i++) {
+			writel(ext_phy_ctrl_const_regs[i],
+			       &emif_ext_phy_ctrl_base[i * 2]);
+			writel(ext_phy_ctrl_const_regs[i],
+			       &emif_ext_phy_ctrl_base[i * 2 + 1]);
+		}
+	} else {
+		/*
+		 * Write the init value for HW levling to occur
+		 */
+		for (i = 21; i < 35; i++) {
+			writel(ext_phy_ctrl_const_regs[i],
+			       &emif_ext_phy_ctrl_base[i * 2]);
+			writel(ext_phy_ctrl_const_regs[i],
+			       &emif_ext_phy_ctrl_base[i * 2 + 1]);
+		}
+	}
+}
+
+void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
+{
+	if (is_omap54xx())
+		do_ext_phy_settings_omap5(base, regs);
+	else
+		do_ext_phy_settings_dra7(base, regs);
+}
+
 #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
 	.max_freq	= 532000000,

arch/arm/cpu/armv7/s5pc1xx/Kconfig

@@ -7,10 +7,12 @@ choice
 config TARGET_S5P_GONI
 	bool "S5P Goni board"
 	select OF_CONTROL
+	select SPL_DISABLE_OF_CONTROL
 
 config TARGET_SMDKC100
 	bool "Support smdkc100 board"
 	select OF_CONTROL
+	select SPL_DISABLE_OF_CONTROL
 
 endchoice
 

arch/arm/cpu/armv7/sunxi/board.c

@@ -119,20 +119,11 @@ void s_init(void)
 #ifdef CONFIG_SPL_BUILD
 /* The sunxi internal brom will try to loader external bootloader
  * from mmc0, nand flash, mmc2.
- *
- * Unfortunately we can't check how SPL was loaded so assume it's
- * always the first SD/MMC controller, unless it was explicitly
- * stated that SPL is on nand flash.
+ * Unfortunately we can't check how SPL was loaded so assume
+ * it's always the first SD/MMC controller
  */
 u32 spl_boot_device(void)
 {
-#if defined(CONFIG_SPL_NAND_SUPPORT)
-	/*
-	 * This is compile time configuration informing SPL, that it
-	 * was loaded from nand flash.
-	 */
-	return BOOT_DEVICE_NAND;
-#else
 	/*
 	 * When booting from the SD card, the "eGON.BT0" signature is expected
 	 * to be found in memory at the address 0x0004 (see the "mksunxiboot"
@@ -153,7 +144,6 @@ u32 spl_boot_device(void)
 		return BOOT_DEVICE_MMC1;
 	else
 		return BOOT_DEVICE_BOARD;
-#endif
 }
 
 /* No confirmation data available in SPL yet. Hardcode bootmode */
@@ -202,6 +192,7 @@ void reset_cpu(ulong addr)
 	writel(WDT_CFG_RESET, &wdog->cfg);
 	writel(WDT_MODE_EN, &wdog->mode);
 	writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
+	while (1) { }
 #endif
 }
 
@@ -223,6 +214,7 @@ int cpu_eth_init(bd_t *bis)
 	__maybe_unused int rc;
 
 #ifdef CONFIG_MACPWR
+	gpio_request(CONFIG_MACPWR, "macpwr");
 	gpio_direction_output(CONFIG_MACPWR, 1);
 	mdelay(200);
 #endif

arch/arm/dts/Makefile

@@ -138,7 +138,8 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
 
 targets += $(dtb-y)
 
-DTC_FLAGS += -R 4 -p 0x1000
+# Add any required device tree compiler flags here
+DTC_FLAGS +=
 
 PHONY += dtbs
 dtbs: $(addprefix $(obj)/, $(dtb-y))

arch/arm/dts/exynos4412-odroid.dts

@@ -43,140 +43,102 @@
 
 			voltage-regulators {
 				ldo1_reg: ldo1 {
-					regulator-compatible = "LDO1";
 					regulator-name = "VDD_ALIVE_1.0V";
 					regulator-min-microvolt = <1000000>;
 					regulator-max-microvolt = <1000000>;
 				};
 
 				ldo2_reg: ldo2 {
-					regulator-compatible = "LDO2";
 					regulator-name = "VDDQ_VM1M2_1.2V";
 					regulator-min-microvolt = <1200000>;
 					regulator-max-microvolt = <1200000>;
 				};
 
 				ldo3_reg: ldo3 {
-					regulator-compatible = "LDO3";
 					regulator-name = "VCC_1.8V_AP";
 					regulator-min-microvolt = <1800000>;
 					regulator-max-microvolt = <1800000>;
 				};
 
 				ldo4_reg: ldo4 {
-					regulator-compatible = "LDO4";
 					regulator-name = "VDDQ_MMC2_2.8V";
 					regulator-min-microvolt = <2800000>;
 					regulator-max-microvolt = <2800000>;
 				};
 
 				ldo5_reg: ldo5 {
-					regulator-compatible = "LDO5";
 					regulator-name = "VDDQ_MMC0/1/3_1.8V";
 					regulator-min-microvolt = <1800000>;
 					regulator-max-microvolt = <1800000>;
 				};
 
 				ldo6_reg: ldo6 {
-					regulator-compatible = "LDO6";
 					regulator-name = "VMPLL_1.0V";
 					regulator-min-microvolt = <1100000>;
 					regulator-max-microvolt = <1100000>;
 				};
 
 				ldo7_reg: ldo7 {
-					regulator-compatible = "LDO7";
 					regulator-name = "VPLL_1.1V";
 					regulator-min-microvolt = <1100000>;
 					regulator-max-microvolt = <1100000>;
 				};
 
 				ldo8_reg: ldo8 {
-					regulator-compatible = "LDO8";
 					regulator-name = "VDD_MIPI/HDMI_1.0V";
 					regulator-min-microvolt = <1000000>;
 					regulator-max-microvolt = <1000000>;
 				};
 
-				ldo9_reg: ldo9 {
-					regulator-compatible = "LDO9";
-					regulator-name = "nc";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-				};
-
 				ldo10_reg: ldo10 {
-					regulator-compatible = "LDO10";
 					regulator-name = "VDD_MIPI/HDMI_1.8V";
 					regulator-min-microvolt = <1800000>;
 					regulator-max-microvolt = <1800000>;
 				};
 
 				ldo11_reg: ldo11 {
-					regulator-compatible = "LDO11";
 					regulator-name = "VDD_ABB1_1.8V";
 					regulator-min-microvolt = <1800000>;
 					regulator-max-microvolt = <1800000>;
 				};
 
 				ldo12_reg: ldo12 {
-					regulator-compatible = "LDO12";
 					regulator-name = "VDD_UOTG_3.0V";
 					regulator-min-microvolt = <3000000>;
 					regulator-max-microvolt = <3000000>;
 				};
 
 				ldo13_reg: ldo13 {
-					regulator-compatible = "LDO13";
 					regulator-name = "VDD_C2C_1.8V";
 					regulator-min-microvolt = <1800000>;
 					regulator-max-microvolt = <1800000>;
 				};
 
 				ldo14_reg: ldo14 {
-					regulator-compatible = "LDO14";
 					regulator-name = "VDD_ABB02_1.8V";
 					regulator-min-microvolt = <1800000>;
 					regulator-max-microvolt = <1800000>;
 				};
 
 				ldo15_reg: ldo15 {
-					regulator-compatible = "LDO15";
 					regulator-name = "VDD_HSIC/OTG_1.0V";
 					regulator-min-microvolt = <1000000>;
 					regulator-max-microvolt = <1000000>;
 				};
 
 				ldo16_reg: ldo16 {
-					regulator-compatible = "LDO16";
 					regulator-name = "VDD_HSIC_1.8V";
 					regulator-min-microvolt = <1800000>;
 					regulator-max-microvolt = <1800000>;
 				};
 
 				ldo17_reg: ldo17 {
-					regulator-compatible = "LDO17";
 					regulator-name = "VDDQ_CAM_1.2V";
 					regulator-min-microvolt = <1200000>;
 					regulator-max-microvolt = <1200000>;
 				};
 
-				ldo18_reg: ldo18 {
-					regulator-compatible = "LDO18";
-					regulator-name = "nc";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-				};
-
-				ldo19_reg: ldo19 {
-					regulator-compatible = "LDO19";
-					regulator-name = "nc";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-				};
-
 				ldo20_reg: ldo20 {
-					regulator-compatible = "LDO20";
 					regulator-name = "VDDQ_EMMC_1.8V";
 					regulator-min-microvolt = <1800000>;
 					regulator-max-microvolt = <1800000>;
@@ -185,7 +147,6 @@
 				};
 
 				ldo21_reg: ldo21 {
-					regulator-compatible = "LDO21";
 					regulator-name = "TFLASH_2.8V";
 					regulator-min-microvolt = <2800000>;
 					regulator-max-microvolt = <2800000>;
@@ -194,7 +155,6 @@
 				};
 
 				ldo22_reg: ldo22 {
-					regulator-compatible = "LDO22";
 					regulator-name = "VDDQ_EMMC_2.8V";
 					regulator-min-microvolt = <2800000>;
 					regulator-max-microvolt = <2800000>;
@@ -202,20 +162,6 @@
 					regulator-boot-on;
 				};
 
-				ldo23_reg: ldo23 {
-					regulator-compatible = "LDO23";
-					regulator-name = "nc";
-					regulator-min-microvolt = <3300000>;
-					regulator-max-microvolt = <3300000>;
-				};
-
-				ldo24_reg: ldo24 {
-					regulator-compatible = "LDO24";
-					regulator-name = "nc";
-					regulator-min-microvolt = <3000000>;
-					regulator-max-microvolt = <3000000>;
-				};
-
 				ldo25_reg: ldo25 {
 					regulator-compatible = "LDO25";
 					regulator-name = "VDDQ_LCD_3.0V";
@@ -223,75 +169,53 @@
 					regulator-max-microvolt = <3000000>;
 				};
 
-				ldo26_reg: ldo26 {
-					regulator-compatible = "LDO26";
-					regulator-name = "nc";
-					regulator-min-microvolt = <3000000>;
-					regulator-max-microvolt = <3000000>;
-				};
-
-				buck1_reg: buck@1 {
-					regulator-compatible = "BUCK1";
+				buck1_reg: buck1 {
 					regulator-name = "VDD_MIF_1.0V";
 					regulator-min-microvolt = <8500000>;
 					regulator-max-microvolt = <1100000>;
 				};
 
-				buck2_reg: buck@2 {
-					regulator-compatible = "BUCK2";
+				buck2_reg: buck2 {
 					regulator-name = "VDD_ARM_1.0V";
 					regulator-min-microvolt = <850000>;
 					regulator-max-microvolt = <1500000>;
 				};
 
 				buck3_reg: buck3 {
-					regulator-compatible = "BUCK3";
 					regulator-name = "VDD_INT_1.1V";
 					regulator-min-microvolt = <850000>;
 					regulator-max-microvolt = <1150000>;
 				};
 
 				buck4_reg: buck4 {
-					regulator-compatible = "BUCK4";
 					regulator-name = "VDD_G3D_1.0V";
 					regulator-min-microvolt = <850000>;
 					regulator-max-microvolt = <1150000>;
 				};
 
 				buck5_reg: buck5 {
-					regulator-compatible = "BUCK5";
 					regulator-name = "VDDQ_AP_1.2V";
 					regulator-min-microvolt = <1200000>;
 					regulator-max-microvolt = <1200000>;
 				};
 
 				buck6_reg: buck6 {
-					regulator-compatible = "BUCK6";
 					regulator-name = "VCC_INL1/7_1.35V";
 					regulator-min-microvolt = <1350000>;
 					regulator-max-microvolt = <1350000>;
 				};
 
 				buck7_reg: buck7 {
-					regulator-compatible = "BUCK7";
 					regulator-name = "VCC_INL2/3/5_2.0V";
 					regulator-min-microvolt = <2000000>;
 					regulator-max-microvolt = <2000000>;
 				};
 
 				buck8_reg: buck8 {
-					regulator-compatible = "BUCK8";
 					regulator-name = "VCC_P3V3_2.85V";
 					regulator-min-microvolt = <2850000>;
 					regulator-max-microvolt = <3300000>;
 				};
-
-				buck9_reg: buck9 {
-					regulator-compatible = "BUCK9";
-					regulator-name = "nc";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <1200000>;
-				};
 			};
 		};
 	};

arch/arm/dts/ls1021a-qds.dts

@@ -30,7 +30,7 @@
 	dspiflash: at45db021d@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "spi-flash";
+		compatible = "atmel,dataflash";
 		spi-max-frequency = <16000000>;
 		spi-cpol;
 		spi-cpha;

arch/arm/dts/tegra124-nyan-big.dts

@@ -163,12 +163,15 @@
 
 	spi@7000d400 {
 		status = "okay";
+		spi-deactivate-delay = <200>;
+		spi-max-frequency = <3000000>;
 
 		cros_ec: cros-ec@0 {
 			compatible = "google,cros-ec-spi";
 			spi-max-frequency = <3000000>;
 			interrupt-parent = <&gpio>;
 			interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
+			ec-interrupt = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
 			reg = <0>;
 
 			google,cros-ec-spi-msg-delay = <2000>;

arch/arm/include/asm/arch-exynos/cpu.h

@@ -167,6 +167,7 @@
 #define EXYNOS5420_USB_HOST_EHCI_BASE	0x12110000
 #define EXYNOS5420_MMC_BASE		0x12200000
 #define EXYNOS5420_SROMC_BASE		0x12250000
+#define EXYNOS5420_USB3PHY_BASE	0x12500000
 #define EXYNOS5420_UART_BASE		0x12C00000
 #define EXYNOS5420_I2C_BASE		0x12C60000
 #define EXYNOS5420_I2C_8910_BASE	0x12E00000
@@ -187,7 +188,6 @@
 #define EXYNOS5420_FIMD_BASE		DEVICE_NOT_AVAILABLE
 #define EXYNOS5420_ADC_BASE		DEVICE_NOT_AVAILABLE
 #define EXYNOS5420_MODEM_BASE		DEVICE_NOT_AVAILABLE
-#define EXYNOS5420_USB3PHY_BASE		DEVICE_NOT_AVAILABLE
 #define EXYNOS5420_USB_HOST_XHCI_BASE	DEVICE_NOT_AVAILABLE
 
 

arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h

@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2015
+ * Texas Instruments Incorporated
+ *
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DRA7_IODELAY_H_
+#define _DRA7_IODELAY_H_
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+
+/* CONFIG_REG_0 */
+#define CFG_REG_0_OFFSET		0xC
+#define CFG_REG_ROM_READ_SHIFT		1
+#define CFG_REG_ROM_READ_MASK		(1 << 1)
+#define CFG_REG_CALIB_STRT_SHIFT	0
+#define CFG_REG_CALIB_STRT_MASK		(1 << 0)
+#define CFG_REG_CALIB_STRT		1
+#define CFG_REG_CALIB_END		0
+#define CFG_REG_ROM_READ_START		(1 << 1)
+#define CFG_REG_ROM_READ_END		(0 << 1)
+
+/* CONFIG_REG_2 */
+#define CFG_REG_2_OFFSET		0x14
+#define CFG_REG_REFCLK_PERIOD_SHIFT	0
+#define CFG_REG_REFCLK_PERIOD_MASK	(0xFFFF << 0)
+#define CFG_REG_REFCLK_PERIOD		0x2EF
+
+/* CONFIG_REG_8 */
+#define CFG_REG_8_OFFSET		0x2C
+#define CFG_IODELAY_UNLOCK_KEY		0x0000AAAA
+#define CFG_IODELAY_LOCK_KEY		0x0000AAAB
+
+/* CONFIG_REG_3/4 */
+#define CFG_REG_3_OFFSET	0x18
+#define CFG_REG_4_OFFSET	0x1C
+#define CFG_REG_DLY_CNT_SHIFT	16
+#define CFG_REG_DLY_CNT_MASK	(0xFFFF << 16)
+#define CFG_REG_REF_CNT_SHIFT	0
+#define CFG_REG_REF_CNT_MASK	(0xFFFF << 0)
+
+/* CTRL_CORE_SMA_SW_0 */
+#define CTRL_ISOLATE_SHIFT		2
+#define CTRL_ISOLATE_MASK		(1 << 2)
+#define ISOLATE_IO			1
+#define DEISOLATE_IO			0
+
+/* PRM_IO_PMCTRL */
+#define PMCTRL_ISOCLK_OVERRIDE_SHIFT	0
+#define PMCTRL_ISOCLK_OVERRIDE_MASK	(1 << 0)
+#define PMCTRL_ISOCLK_STATUS_SHIFT	1
+#define PMCTRL_ISOCLK_STATUS_MASK	(1 << 1)
+#define PMCTRL_ISOCLK_OVERRIDE_CTRL	1
+#define PMCTRL_ISOCLK_NOT_OVERRIDE_CTRL	0
+
+#define ERR_CALIBRATE_IODELAY		0x1
+#define ERR_DEISOLATE_IO		0x2
+#define ERR_ISOLATE_IO			0x4
+#define ERR_UPDATE_DELAY		0x8
+#define ERR_CPDE			0x3
+#define ERR_FPDE			0x5
+
+/* CFG_XXX */
+#define CFG_X_SIGNATURE_SHIFT		12
+#define CFG_X_SIGNATURE_MASK		(0x3F << 12)
+#define CFG_X_LOCK_SHIFT		10
+#define CFG_X_LOCK_MASK			(0x1 << 10)
+#define CFG_X_COARSE_DLY_SHIFT		5
+#define CFG_X_COARSE_DLY_MASK		(0x1F << 5)
+#define CFG_X_FINE_DLY_SHIFT		0
+#define CFG_X_FINE_DLY_MASK		(0x1F << 0)
+#define CFG_X_SIGNATURE			0x29
+#define CFG_X_LOCK			1
+
+void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
+			   struct iodelay_cfg_entry const *iodelay,
+			   int niodelays);
+
+#endif

arch/arm/include/asm/arch-omap5/mux_dra7xx.h

@@ -26,6 +26,21 @@
 #define WKEN	(1 << 24)
 #define WKDIS	(0 << 24)
 
+#define PULL_ENA		(0 << 16)
+#define PULL_DIS		(1 << 16)
+#define PULL_UP			(1 << 17)
+#define INPUT_EN		(1 << 18)
+#define SLEWCONTROL		(1 << 19)
+
+/* Active pin states */
+#define PIN_OUTPUT		(0 | PULL_DIS)
+#define PIN_OUTPUT_PULLUP	(PULL_UP)
+#define PIN_OUTPUT_PULLDOWN	(0)
+#define PIN_INPUT		(INPUT_EN | PULL_DIS)
+#define PIN_INPUT_SLEW		(INPUT_EN | SLEWCONTROL)
+#define PIN_INPUT_PULLUP	(PULL_ENA | INPUT_EN | PULL_UP)
+#define PIN_INPUT_PULLDOWN	(PULL_ENA | INPUT_EN)
+
 #define M0	0
 #define M1	1
 #define M2	2
@@ -43,6 +58,28 @@
 #define M14	14
 #define M15	15
 
+#define MODE_SELECT		(1 << 8)
+#define DELAYMODE_SHIFT		4
+
+#define MANUAL_MODE	MODE_SELECT
+
+#define VIRTUAL_MODE0	(MODE_SELECT | (0x0 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE1	(MODE_SELECT | (0x1 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE2	(MODE_SELECT | (0x2 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE3	(MODE_SELECT | (0x3 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE4	(MODE_SELECT | (0x4 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE5	(MODE_SELECT | (0x5 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE6	(MODE_SELECT | (0x6 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE7	(MODE_SELECT | (0x7 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE8	(MODE_SELECT | (0x8 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE9	(MODE_SELECT | (0x9 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE10	(MODE_SELECT | (0xa << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE11	(MODE_SELECT | (0xb << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE12	(MODE_SELECT | (0xc << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE13	(MODE_SELECT | (0xd << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE14	(MODE_SELECT | (0xe << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE15	(MODE_SELECT | (0xf << DELAYMODE_SHIFT))
+
 #define SAFE_MODE	M15
 
 #define GPMC_AD0	0x000

arch/arm/include/asm/arch-omap5/omap.h

@@ -216,27 +216,6 @@ struct s32ktimer {
 #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK	(0x1 << 10)
 #define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK	(0x1f << 0)
 
-/* IO Delay module defines */
-#define CFG_IO_DELAY_BASE		0x4844A000
-#define CFG_IO_DELAY_LOCK		(CFG_IO_DELAY_BASE + 0x02C)
-
-/* CPSW IO Delay registers*/
-#define CFG_RGMII0_TXCTL		(CFG_IO_DELAY_BASE + 0x74C)
-#define CFG_RGMII0_TXD0			(CFG_IO_DELAY_BASE + 0x758)
-#define CFG_RGMII0_TXD1			(CFG_IO_DELAY_BASE + 0x764)
-#define CFG_RGMII0_TXD2			(CFG_IO_DELAY_BASE + 0x770)
-#define CFG_RGMII0_TXD3			(CFG_IO_DELAY_BASE + 0x77C)
-#define CFG_VIN2A_D13			(CFG_IO_DELAY_BASE + 0xA7C)
-#define CFG_VIN2A_D17			(CFG_IO_DELAY_BASE + 0xAAC)
-#define CFG_VIN2A_D16			(CFG_IO_DELAY_BASE + 0xAA0)
-#define CFG_VIN2A_D15			(CFG_IO_DELAY_BASE + 0xA94)
-#define CFG_VIN2A_D14			(CFG_IO_DELAY_BASE + 0xA88)
-
-#define CFG_IO_DELAY_UNLOCK_KEY		0x0000AAAA
-#define CFG_IO_DELAY_LOCK_KEY		0x0000AAAB
-#define CFG_IO_DELAY_ACCESS_PATTERN	0x00029000
-#define CFG_IO_DELAY_LOCK_MASK		0x400
-
 #ifndef __ASSEMBLY__
 struct srcomp_params {
 	s8 divide_factor;
@@ -255,9 +234,5 @@ struct ctrl_ioregs {
 	u32 ctrl_ddr_ctrl_ext_0;
 };
 
-struct io_delay {
-	u32 addr;
-	u32 dly;
-};
 #endif /* __ASSEMBLY__ */
 #endif

arch/arm/include/asm/arch-omap5/sys_proto.h

@@ -18,6 +18,18 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/*
+ * Structure for Iodelay configuration registers.
+ * Theoretical max for g_delay is 21560 ps.
+ * Theoretical max for a_delay is 1/3rd of g_delay max.
+ * So using u16 for both a/g_delay.
+ */
+struct iodelay_cfg_entry {
+	u16 offset;
+	u16 a_delay;
+	u16 g_delay;
+};
+
 struct pad_conf_entry {
 	u32 offset;
 	u32 val;
@@ -32,6 +44,7 @@ void gpmc_init(void);
 void watchdog_init(void);
 u32 get_device_type(void);
 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
+void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size);
 void set_muxconf_regs_essential(void);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);

arch/arm/include/asm/arch-sunxi/gpio.h

@@ -157,8 +157,6 @@ enum sunxi_gpio_number {
 #define SUN5I_GPB_UART0		2
 #define SUN8I_GPB_UART2		2
 
-#define SUNXI_GPC_NAND		2
-
 #define SUNXI_GPC_SDC2		3
 #define SUN6I_GPC_SDC3		4
 

arch/arm/include/asm/arch-sunxi/nand.h

@@ -1,67 +0,0 @@
-/*
- * (C) Copyright 2015 Roy Spliet <rspliet@ultimaker.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _SUNXI_NAND_H
-#define _SUNXI_NAND_H
-
-#include <linux/types.h>
-
-struct sunxi_nand
-{
-	u32 ctl;		/* 0x000 Configure and control */
-	u32 st;			/* 0x004 Status information */
-	u32 intr;		/* 0x008 Interrupt control */
-	u32 timing_ctl;		/* 0x00C Timing control */
-	u32 timing_cfg;		/* 0x010 Timing configure */
-	u32 addr_low;		/* 0x014 Low word address */
-	u32 addr_high;		/* 0x018 High word address */
-	u32 block_num;		/* 0x01C Data block number */
-	u32 data_cnt;		/* 0x020 Data counter for transfer */
-	u32 cmd;		/* 0x024 NDFC commands */
-	u32 rcmd_set;		/* 0x028 Read command set for vendor NAND mem */
-	u32 wcmd_set;		/* 0x02C Write command set */
-	u32 io_data;		/* 0x030 IO data */
-	u32 ecc_ctl;		/* 0x034 ECC configure and control */
-	u32 ecc_st;		/* 0x038 ECC status and operation info */
-	u32 efr;		/* 0x03C Enhanced feature */
-	u32 err_cnt0;		/* 0x040 Corrected error bit counter 0 */
-	u32 err_cnt1;		/* 0x044 Corrected error bit counter 1 */
-	u32 user_data[16];	/* 0x050[16] User data field */
-	u32 efnand_st;		/* 0x090 EFNAND status */
-	u32 res0[3];
-	u32 spare_area;		/* 0x0A0 Spare area configure */
-	u32 pat_id;		/* 0x0A4 Pattern ID register */
-	u32 rdata_sta_ctl;	/* 0x0A8 Read data status control */
-	u32 rdata_sta_0;	/* 0x0AC Read data status 0 */
-	u32 rdata_sta_1;	/* 0x0B0 Read data status 1 */
-	u32 res1[3];
-	u32 mdma_addr;		/* 0x0C0 MBUS DMA Address */
-	u32 mdma_cnt;		/* 0x0C4 MBUS DMA data counter */
-};
-
-#define SUNXI_NAND_CTL_EN			(1 << 0)
-#define SUNXI_NAND_CTL_RST			(1 << 1)
-#define SUNXI_NAND_CTL_PAGE_SIZE(a)		((fls(a) - 11) << 8)
-#define SUNXI_NAND_CTL_RAM_METHOD_DMA		(1 << 14)
-
-#define SUNXI_NAND_ST_CMD_INT			(1 << 1)
-#define SUNXI_NAND_ST_DMA_INT			(1 << 2)
-#define SUNXI_NAND_ST_FIFO_FULL			(1 << 3)
-
-#define SUNXI_NAND_CMD_ADDR_CYCLES(a)		((a - 1) << 16);
-#define SUNXI_NAND_CMD_SEND_CMD1		(1 << 22)
-#define SUNXI_NAND_CMD_WAIT_FLAG		(1 << 23)
-#define SUNXI_NAND_CMD_ORDER_INTERLEAVE		0
-#define SUNXI_NAND_CMD_ORDER_SEQ		(1 << 25)
-
-#define SUNXI_NAND_ECC_CTL_ECC_EN		(1 << 0)
-#define SUNXI_NAND_ECC_CTL_PIPELINE		(1 << 3)
-#define SUNXI_NAND_ECC_CTL_BS_512B		(1 << 5)
-#define SUNXI_NAND_ECC_CTL_RND_EN		(1 << 9)
-#define SUNXI_NAND_ECC_CTL_MODE(a)		((a) << 12)
-#define SUNXI_NAND_ECC_CTL_RND_SEED(a)		((a) << 16)
-
-#endif /* _SUNXI_NAND_H */

arch/arm/include/asm/arch-tegra/clock.h

@@ -336,4 +336,12 @@ void arch_timer_init(void);
 
 void tegra30_set_up_pllp(void);
 
+/**
+ * Enable output clock for external peripherals
+ *
+ * @param clk_id	Clock ID to output (1, 2 or 3)
+ * @return 0 if OK. -ve on error
+ */
+int clock_external_output(int clk_id);
+
 #endif  /* _TEGRA_CLOCK_H_ */

arch/arm/include/asm/arch-tegra/sys_proto.h

@@ -25,4 +25,11 @@ int tegra_board_id(void);
  */
 int tegra_lcd_pmic_init(int board_id);
 
+/**
+ * nvidia_board_init() - perform any board-specific init
+ *
+ * @return 0 if OK, -ve on error
+ */
+int nvidia_board_init(void);
+
 #endif

arch/arm/include/asm/arch-tegra124/clock-tables.h

@@ -285,12 +285,12 @@ enum periph_id {
 	/* 184 */
 	PERIPH_ID_GPU,
 	PERIPH_ID_AMX1,
-	PERIPH_ID_X_RESERVED26,
-	PERIPH_ID_X_RESERVED27,
-	PERIPH_ID_X_RESERVED28,
-	PERIPH_ID_X_RESERVED29,
-	PERIPH_ID_X_RESERVED30,
-	PERIPH_ID_X_RESERVED31,
+	PERIPH_ID_AFC5,
+	PERIPH_ID_AFC4,
+	PERIPH_ID_AFC3,
+	PERIPH_ID_AFC2,
+	PERIPH_ID_AFC1,
+	PERIPH_ID_AFC0,
 
 	PERIPH_ID_COUNT,
 	PERIPH_ID_NONE = -1,

arch/arm/include/asm/arch-tegra124/flow.h

@@ -26,6 +26,12 @@ struct flow_ctlr {
 	u32 cpu_pwr_csr;	/* offset 0x38 */
 	u32 mpid;		/* offset 0x3c */
 	u32 ram_repair;		/* offset 0x40 */
+	u32 flow_dbg_sel;	/* offset 0x44 */
+	u32 flow_dbg_cnt0;	/* offset 0x48 */
+	u32 flow_dbg_cnt1;	/* offset 0x4c */
+	u32 flow_dbg_qual;	/* offset 0x50 */
+	u32 flow_ctlr_spare;	/* offset 0x54 */
+	u32 ram_repair_cluster1;/* offset 0x58 */
 };
 
 /* HALT_COP_EVENTS_0, 0x04 */
@@ -43,4 +49,10 @@ struct flow_ctlr {
 #define CSR_WAIT_WFI_SHIFT	8
 #define CSR_PWR_OFF_STS		(1 << 16)
 
+/* RAM_REPAIR, 0x40, 0x58 */
+enum {
+	RAM_REPAIR_REQ = 0x1 << 0,
+	RAM_REPAIR_STS = 0x1 << 1,
+};
+
 #endif	/*  _TEGRA124_FLOW_H_ */

arch/arm/include/asm/emif.h

@@ -44,6 +44,8 @@
 #define EMIF_REG_DUAL_CLK_MODE_MASK			(1 << 30)
 #define EMIF_REG_FAST_INIT_SHIFT			29
 #define EMIF_REG_FAST_INIT_MASK			(1 << 29)
+#define EMIF_REG_LEVLING_TO_SHIFT		4
+#define EMIF_REG_LEVELING_TO_MASK		(7 << 4)
 #define EMIF_REG_PHY_DLL_READY_SHIFT		2
 #define EMIF_REG_PHY_DLL_READY_MASK			(1 << 2)
 
@@ -509,6 +511,13 @@
 #define EMIF_REG_RDWRLVLINC_RMP_WIN_SHIFT	0
 #define EMIF_REG_RDWRLVLINC_RMP_WIN_MASK	(0x1FFF << 0)
 
+/* EMIF_PHY_CTRL_36 */
+#define EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR	(1 << 8)
+
+#define PHY_RDDQS_RATIO_REGS		5
+#define PHY_FIFO_WE_SLAVE_RATIO_REGS	5
+#define PHY_REG_WR_DQ_SLAVE_RATIO_REGS	10
+
 /*Leveling Fields */
 #define DDR3_WR_LVL_INT		0x73
 #define DDR3_RD_LVL_INT		0x33
@@ -1200,12 +1209,10 @@ static inline u32 get_emif_rev(u32 base)
  * which is typically the case. So it is sufficient to get
  * SDRAM type from EMIF1.
  */
-static inline u32 emif_sdram_type(void)
+static inline u32 emif_sdram_type(u32 sdram_config)
 {
-	struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
-
-	return (readl(&emif->emif_sdram_config) &
-		EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
+	return (sdram_config & EMIF_REG_SDRAM_TYPE_MASK)
+	       >> EMIF_REG_SDRAM_TYPE_SHIFT;
 }
 
 /* assert macros */
@@ -1235,6 +1242,5 @@ extern u32 *const T_den;
 #endif
 
 void config_data_eye_leveling_samples(u32 emif_base);
-u32 emif_sdram_type(void);
 const struct read_write_regs *get_bug_regs(u32 *iterations);
 #endif

arch/arm/include/asm/omap_common.h

@@ -313,6 +313,7 @@ struct prcm_regs {
 	u32 prm_rstctrl;
 	u32 prm_rstst;
 	u32 prm_rsttime;
+	u32 prm_io_pmctrl;
 	u32 prm_vc_val_bypass;
 	u32 prm_vc_cfg_i2c_mode;
 	u32 prm_vc_cfg_i2c_clk;
@@ -344,6 +345,10 @@ struct prcm_regs {
 	/* GMAC Clk Ctrl */
 	u32 cm_gmac_gmac_clkctrl;
 	u32 cm_gmac_clkstctrl;
+
+	/* IPU */
+	u32 cm_ipu_clkstctrl;
+	u32 cm_ipu_i2c5_clkctrl;
 };
 
 struct omap_sys_ctrl_regs {
@@ -455,6 +460,8 @@ struct omap_sys_ctrl_regs {
 	u32 control_efuse_12;
 	u32 control_efuse_13;
 	u32 control_padconf_wkup_base;
+	u32 iodelay_config_base;
+	u32 ctrl_core_sma_sw_0;
 };
 
 struct dpll_params {
@@ -583,6 +590,7 @@ s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
 
 void usb_fake_mac_from_die_id(u32 *id);
 void usb_set_serial_num_from_die_id(u32 *id);
+void recalibrate_iodelay(void);
 
 void omap_smc1(u32 service, u32 val);
 
@@ -622,12 +630,19 @@ static inline u8 is_omap54xx(void)
 }
 
 #define DRA7XX		0x07000000
+#define DRA72X		0x07200000
 
 static inline u8 is_dra7xx(void)
 {
 	extern u32 *const omap_si_rev;
 	return ((*omap_si_rev & 0xFF000000) == DRA7XX);
 }
+
+static inline u8 is_dra72x(void)
+{
+	extern u32 *const omap_si_rev;
+	return (*omap_si_rev & 0xFFF00000) == DRA72X;
+}
 #endif
 
 /*

arch/arm/mach-bcm283x/Kconfig

@@ -15,9 +15,6 @@ config TARGET_RPI_2
 
 endchoice
 
-config PHYS_TO_BUS
-	default y
-
 config SYS_BOARD
 	default "rpi" if TARGET_RPI
 	default "rpi_2" if TARGET_RPI_2

arch/arm/mach-keystone/clock.c

@@ -246,18 +246,18 @@ static inline u32 read_efuse_bootrom(void)
 }
 #endif
 
-inline int get_max_dev_speed(void)
-{
-	return get_max_speed(read_efuse_bootrom() & 0xffff, dev_speeds);
-}
-
 #ifndef CONFIG_SOC_K2E
 inline int get_max_arm_speed(void)
 {
-	return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, arm_speeds);
+	return get_max_speed(read_efuse_bootrom() & 0xffff, arm_speeds);
 }
 #endif
 
+inline int get_max_dev_speed(void)
+{
+	return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, dev_speeds);
+}
+
 void pass_pll_pa_clk_enable(void)
 {
 	u32 reg;

arch/arm/mach-mvebu/cpu.c

@@ -7,6 +7,7 @@
 #include <common.h>
 #include <netdev.h>
 #include <asm/io.h>
+#include <asm/pl310.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/soc.h>
 
@@ -160,10 +161,17 @@ static void update_sdram_window_sizes(void)
 }
 
 #ifdef CONFIG_ARCH_CPU_INIT
+static void set_cbar(u32 addr)
+{
+	asm("mcr p15, 4, %0, c15, c0" : : "r" (addr));
+}
+
+
 int arch_cpu_init(void)
 {
 	/* Linux expects the internal registers to be at 0xf1000000 */
 	writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
+	set_cbar(SOC_REGS_PHY_BASE + 0xC000);
 
 	/*
 	 * We need to call mvebu_mbus_probe() before calling
@@ -240,6 +248,13 @@ int cpu_eth_init(bd_t *bis)
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
 {
+	struct pl310_regs *const pl310 =
+		(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+
+	/* First disable L2 cache - may still be enable from BootROM */
+	if (mvebu_soc_family() == MVEBU_SOC_A38X)
+		clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
 	/* Avoid problem with e.g. neta ethernet driver */
 	invalidate_dcache_all();
 

arch/arm/mach-tegra/Kconfig

@@ -21,12 +21,6 @@ endchoice
 config SYS_MALLOC_F_LEN
 	default 0x1800
 
-config USE_PRIVATE_LIBGCC
-	default y
-
-config SPL_DM
-	default y
-
 source "arch/arm/mach-tegra/tegra20/Kconfig"
 source "arch/arm/mach-tegra/tegra30/Kconfig"
 source "arch/arm/mach-tegra/tegra114/Kconfig"

arch/arm/mach-tegra/board2.c

@@ -107,6 +107,11 @@ __weak int tegra_lcd_pmic_init(int board_it)
 	return 0;
 }
 
+__weak int nvidia_board_init(void)
+{
+	return 0;
+}
+
 /*
  * Routine: board_init
  * Description: Early hardware init.
@@ -156,7 +161,6 @@ int board_init(void)
 
 #ifdef CONFIG_USB_EHCI_TEGRA
 	pin_mux_usb();
-	usb_process_devicetree(gd->fdt_blob);
 #endif
 
 #ifdef CONFIG_LCD
@@ -180,8 +184,7 @@ int board_init(void)
 	/* prepare the WB code to LP0 location */
 	warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
 #endif
-
-	return 0;
+	return nvidia_board_init();
 }
 
 #ifdef CONFIG_BOARD_EARLY_INIT_F

arch/arm/mach-tegra/clock.c

@@ -17,11 +17,13 @@
 /* Tegra SoC common clock control functions */
 
 #include <common.h>
+#include <errno.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/tegra.h>
 #include <asm/arch-tegra/ap.h>
 #include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
 #include <asm/arch-tegra/timer.h>
 #include <div64.h>
 #include <fdtdec.h>
@@ -82,7 +84,7 @@ static struct clk_pll *get_pll(enum clock_id clkid)
 
 	assert(clock_id_is_pll(clkid));
 	if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) {
-		debug("%s: Invalid PLL\n", __func__);
+		debug("%s: Invalid PLL %d\n", __func__, clkid);
 		return NULL;
 	}
 	return &clkrst->crc_pll[clkid];
@@ -118,9 +120,12 @@ int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
 		u32 divp, u32 cpcon, u32 lfcon)
 {
-	struct clk_pll *pll = get_pll(clkid);
+	struct clk_pll *pll = NULL;
 	u32 misc_data, data;
 
+	if (clkid < (enum clock_id)TEGRA_CLK_PLLS)
+		pll = get_pll(clkid);
+
 	/*
 	 * We cheat by treating all PLL (except PLLU) in the same fashion.
 	 * This works only because:
@@ -702,3 +707,18 @@ void tegra30_set_up_pllp(void)
 
 	set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4);
 }
+
+int clock_external_output(int clk_id)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+	if (clk_id >= 1 && clk_id <= 3) {
+		setbits_le32(&pmc->pmc_clk_out_cntrl,
+			     1 << (2 + (clk_id - 1) * 8));
+	} else {
+		printf("%s: Unknown output clock id %d\n", __func__, clk_id);
+		return -EINVAL;
+	}
+
+	return 0;
+}

arch/arm/mach-tegra/powergate.c

@@ -9,7 +9,7 @@
 
 #include <asm/io.h>
 #include <asm/types.h>
-
+#include <asm/arch/flow.h>
 #include <asm/arch/powergate.h>
 #include <asm/arch/tegra.h>
 
@@ -75,11 +75,29 @@ static int tegra_powergate_remove_clamping(enum tegra_powergate id)
 	return 0;
 }
 
+static void tegra_powergate_ram_repair(void)
+{
+#ifdef CONFIG_TEGRA124
+	struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+
+	/* Request RAM repair for cluster 0 and wait until complete */
+	setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ);
+	while (!(readl(&flow->ram_repair) & RAM_REPAIR_STS))
+		;
+
+	/* Same for cluster 1 */
+	setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ);
+	while (!(readl(&flow->ram_repair_cluster1) & RAM_REPAIR_STS))
+		;
+#endif
+}
+
 int tegra_powergate_sequence_power_up(enum tegra_powergate id,
 				      enum periph_id periph)
 {
 	int err;
 
+	tegra_powergate_ram_repair();
 	reset_set_enable(periph, 1);
 
 	err = tegra_powergate_power_on(id);

arch/arm/mach-tegra/tegra124/Kconfig

@@ -10,7 +10,7 @@ config TARGET_JETSON_TK1
 	select CPU_V7_HAS_VIRT if !SPL_BUILD
 
 config TARGET_NYAN_BIG
-	bool "Google/NVIDIA Nyan-big Chrombook"
+	bool "Google/NVIDIA Nyan-big Chromebook"
 	help
 	  Nyan Big is a Tegra124 clamshell board that is very similar
 	  to venice2, but it has a different panel, the sdcard CD and WP

arch/arm/mach-tegra/tegra124/clock.c

@@ -475,7 +475,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
 	PERIPHC_ACTMON,
 
 	/* 120 */
-	NONE(EXTPERIPH1),
+	PERIPHC_EXTPERIPH1,
 	NONE(EXTPERIPH2),
 	NONE(EXTPERIPH3),
 	NONE(OOB),

arch/avr32/Kconfig

@@ -17,35 +17,14 @@ config TARGET_ATNGW100MKII
 config TARGET_ATSTK1002
 	bool "Support atstk1002"
 
-config TARGET_ATSTK1003
-	bool "Support atstk1003"
-
-config TARGET_ATSTK1004
-	bool "Support atstk1004"
-
-config TARGET_ATSTK1006
-	bool "Support atstk1006"
-
-config TARGET_FAVR_32_EZKIT
-	bool "Support favr-32-ezkit"
-
 config TARGET_GRASSHOPPER
 	bool "Support grasshopper"
 
-config TARGET_MIMC200
-	bool "Support mimc200"
-
-config TARGET_HAMMERHEAD
-	bool "Support hammerhead"
-
 endchoice
 
 source "board/atmel/atngw100/Kconfig"
 source "board/atmel/atngw100mkii/Kconfig"
 source "board/atmel/atstk1000/Kconfig"
-source "board/earthlcd/favr-32-ezkit/Kconfig"
 source "board/in-circuit/grasshopper/Kconfig"
-source "board/mimc/mimc200/Kconfig"
-source "board/miromico/hammerhead/Kconfig"
 
 endmenu

arch/avr32/lib/Makefile

@@ -8,9 +8,6 @@
 #
 
 obj-y	+= memset.o
-ifndef CONFIG_SYS_GENERIC_BOARD
-obj-y	+= board.o
-endif
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-y	+= interrupts.o
 obj-y	+= dram_init.o

arch/avr32/lib/board.c

@@ -1,256 +0,0 @@
-/*
- * Copyright (C) 2004-2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <stdio_dev.h>
-#include <version.h>
-#include <net.h>
-
-#ifdef CONFIG_BITBANGMII
-#include <miiphy.h>
-#endif
-
-#include <asm/sections.h>
-#include <asm/arch/mmu.h>
-#include <asm/arch/hardware.h>
-
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-#include <mmc.h>
-#endif
-DECLARE_GLOBAL_DATA_PTR;
-
-unsigned long monitor_flash_len;
-
-__weak void dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size =  gd->ram_size;
-}
-
-/* Weak aliases for optional board functions */
-static int __do_nothing(void)
-{
-	return 0;
-}
-int board_postclk_init(void) __attribute__((weak, alias("__do_nothing")));
-int board_early_init_r(void) __attribute__((weak, alias("__do_nothing")));
-
-static int init_baudrate(void)
-{
-	gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
-	return 0;
-}
-
-static int display_banner (void)
-{
-	printf ("\n\n%s\n\n", version_string);
-	printf ("U-Boot code: %08lx -> %08lx  data: %08lx -> %08lx\n",
-		(unsigned long)_text, (unsigned long)_etext,
-		(unsigned long)_data, (unsigned long)(&__bss_end));
-	return 0;
-}
-
-static int display_dram_config (void)
-{
-	int i;
-
-	puts ("DRAM Configuration:\n");
-
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		printf ("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
-		print_size (gd->bd->bi_dram[i].size, "\n");
-	}
-
-	return 0;
-}
-
-static void display_flash_config (void)
-{
-	puts ("Flash: ");
-	print_size(gd->bd->bi_flashsize, " ");
-	printf("at address 0x%08lx\n", gd->bd->bi_flashstart);
-}
-
-void board_init_f(ulong board_type)
-{
-	gd_t gd_data;
-	gd_t *new_gd;
-	bd_t *bd;
-	unsigned long *new_sp;
-	unsigned long monitor_len;
-	unsigned long monitor_addr;
-	unsigned long addr;
-
-	/* Initialize the global data pointer */
-	memset(&gd_data, 0, sizeof(gd_data));
-	gd = &gd_data;
-
-	/* Perform initialization sequence */
-	board_early_init_f();
-	arch_cpu_init();
-	board_postclk_init();
-	env_init();
-	init_baudrate();
-	serial_init();
-	console_init_f();
-	display_banner();
-	dram_init();
-
-	/* If we have no SDRAM, we can't go on */
-	if (gd->ram_size <= 0)
-		panic("No working SDRAM available\n");
-
-	/*
-	 * Now that we have DRAM mapped and working, we can
-	 * relocate the code and continue running from DRAM.
-	 *
-	 * Reserve memory at end of RAM for (top down in that order):
-	 *  - u-boot image
-	 *  - heap for malloc()
-	 *  - board info struct
-	 *  - global data struct
-	 *  - stack
-	 */
-	addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
-	monitor_len = (char *)(&__bss_end) - _text;
-
-	/*
-	 * Reserve memory for u-boot code, data and bss.
-	 * Round down to next 4 kB limit.
-	 */
-	addr -= monitor_len;
-	addr &= ~(4096UL - 1);
-	monitor_addr = addr;
-
-	/* Reserve memory for malloc() */
-	addr -= CONFIG_SYS_MALLOC_LEN;
-
-#ifdef CONFIG_LCD
-#ifdef CONFIG_FB_ADDR
-	printf("LCD: Frame buffer allocated at preset 0x%08x\n",
-	       CONFIG_FB_ADDR);
-	gd->fb_base = CONFIG_FB_ADDR;
-#else
-	addr = lcd_setmem(addr);
-	printf("LCD: Frame buffer allocated at 0x%08lx\n", addr);
-	gd->fb_base = addr;
-#endif /* CONFIG_FB_ADDR */
-#endif /* CONFIG_LCD */
-
-	/* Allocate a Board Info struct on a word boundary */
-	addr -= sizeof(bd_t);
-	addr &= ~3UL;
-	gd->bd = bd = (bd_t *)addr;
-
-	/* Allocate a new global data copy on a 8-byte boundary. */
-	addr -= sizeof(gd_t);
-	addr &= ~7UL;
-	new_gd = (gd_t *)addr;
-
-	/* And finally, a new, bigger stack. */
-	new_sp = (unsigned long *)addr;
-	gd->start_addr_sp = addr;
-	*(--new_sp) = 0;
-	*(--new_sp) = 0;
-
-	dram_init_banksize();
-
-	memcpy(new_gd, gd, sizeof(gd_t));
-
-	relocate_code((unsigned long)new_sp, new_gd, monitor_addr);
-}
-
-void board_init_r(gd_t *new_gd, ulong dest_addr)
-{
-#ifndef CONFIG_ENV_IS_NOWHERE
-	extern char * env_name_spec;
-#endif
-	bd_t *bd;
-
-	gd = new_gd;
-	bd = gd->bd;
-
-	gd->flags |= GD_FLG_RELOC;
-	gd->reloc_off = dest_addr - CONFIG_SYS_MONITOR_BASE;
-
-	/* Enable the MMU so that we can keep u-boot simple */
-	mmu_init_r(dest_addr);
-
-	board_early_init_r();
-
-	monitor_flash_len = _edata - _text;
-
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
-	/*
-	 * We have to relocate the command table manually
-	 */
-	fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
-			ll_entry_count(cmd_tbl_t, cmd));
-#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
-
-	/* there are some other pointer constants we must deal with */
-#ifndef CONFIG_ENV_IS_NOWHERE
-	env_name_spec += gd->reloc_off;
-#endif
-
-	timer_init();
-
-	/* The malloc area is right below the monitor image in RAM */
-	mem_malloc_init(CONFIG_SYS_MONITOR_BASE + gd->reloc_off -
-			CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN);
-
-	enable_interrupts();
-
-	bd->bi_flashstart = 0;
-	bd->bi_flashsize = 0;
-	bd->bi_flashoffset = 0;
-
-#ifndef CONFIG_SYS_NO_FLASH
-	bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
-	bd->bi_flashsize = flash_init();
-	bd->bi_flashoffset = (unsigned long)_edata - (unsigned long)_text;
-
-	if (bd->bi_flashsize)
-		display_flash_config();
-#endif
-
-	if (bd->bi_dram[0].size)
-		display_dram_config();
-
-	gd->bd->bi_boot_params = malloc(CONFIG_SYS_BOOTPARAMS_LEN);
-	if (!gd->bd->bi_boot_params)
-		puts("WARNING: Cannot allocate space for boot parameters\n");
-
-	/* initialize environment */
-	env_relocate();
-
-	stdio_init();
-	jumptable_init();
-	console_init_r();
-
-	/* Initialize from environment */
-	load_addr = getenv_ulong("loadaddr", 16, load_addr);
-
-#ifdef CONFIG_BITBANGMII
-	bb_miiphy_init();
-#endif
-#if defined(CONFIG_CMD_NET)
-	puts("Net:   ");
-	eth_initialize();
-#endif
-
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-	mmc_initialize(gd->bd);
-#endif
-	for (;;) {
-		main_loop();
-	}
-}

arch/mips/Kconfig

@@ -8,9 +8,6 @@ config SYS_CPU
 	default "mips32" if CPU_MIPS32_R1 || CPU_MIPS32_R2
 	default "mips64" if CPU_MIPS64_R1 || CPU_MIPS64_R2
 
-config USE_PRIVATE_LIBGCC
-	default y
-
 choice
 	prompt "Target select"
 	optional

arch/sandbox/cpu/cpu.c

@@ -52,6 +52,11 @@ int cleanup_before_linux(void)
 	return 0;
 }
 
+int cleanup_before_linux_select(int flags)
+{
+	return 0;
+}
+
 void *map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
 {
 #ifdef CONFIG_PCI

arch/sh/Kconfig

@@ -125,9 +125,6 @@ config SYS_CPU
 	default "sh3" if CPU_SH3
 	default "sh4" if CPU_SH4
 
-config USE_PRIVATE_LIBGCC
-	default y
-
 source "board/alphaproject/ap_sh4a_4a/Kconfig"
 source "board/espt/Kconfig"
 source "board/mpr2/Kconfig"

arch/x86/Kconfig

@@ -4,12 +4,6 @@ menu "x86 architecture"
 config SYS_ARCH
 	default "x86"
 
-config USE_PRIVATE_LIBGCC
-	default y
-
-config SYS_VSNPRINTF
-	default y
-
 choice
 	prompt "Mainboard vendor"
 	default VENDOR_EMULATION
@@ -335,13 +329,4 @@ config PCIE_ECAM_BASE
 	  assigned to PCI devices - i.e. the memory and prefetch regions, as
 	  passed to pci_set_region().
 
-config BOOTSTAGE
-	default y
-
-config BOOTSTAGE_REPORT
-	default y
-
-config CMD_BOOTSTAGE
-	default y
-
 endmenu

board/Arcturus/ucp1020/Kconfig

@@ -12,14 +12,6 @@ config SYS_CONFIG_NAME
 	string
 	default "UCP1020"
 
-config SPI_FLASH
-	bool
-	default y
-
-config SPI_PCI
-	bool
-	default y
-
 choice
 	prompt "Target image select"
 

board/BuR/common/common.c

@@ -64,14 +64,21 @@ void lcdbacklight(int on)
 	unsigned int pwmfrq = getenv_ulong("ds1_pwmfreq", 10, ~0UL);
 #endif
 	unsigned int tmp;
-
-	struct gptimer *const timerhw = (struct gptimer *)DM_TIMER6_BASE;
+	struct gptimer *timerhw;
 
 	if (on)
 		bright = bright != ~0UL ? bright : 50;
 	else
 		bright = 0;
 
+	switch (driver) {
+	case 2:
+		timerhw = (struct gptimer *)DM_TIMER5_BASE;
+		break;
+	default:
+		timerhw = (struct gptimer *)DM_TIMER6_BASE;
+	}
+
 	switch (driver) {
 	case 0:	/* PMIC LED-Driver */
 		/* brightness level */
@@ -83,7 +90,8 @@ void lcdbacklight(int on)
 				   bright != 0 ? 0x0A : 0x02,
 				   0xFF);
 		break;
-	case 1: /* PWM using timer6 */
+	case 1:
+	case 2: /* PWM using timer */
 		if (pwmfrq != ~0UL) {
 			timerhw->tiocp_cfg = TCFG_RESET;
 			udelay(10);

board/atmel/atstk1000/Kconfig

@@ -13,51 +13,3 @@ config SYS_CONFIG_NAME
 	default "atstk1002"
 
 endif
-
-if TARGET_ATSTK1003
-
-config SYS_BOARD
-	default "atstk1000"
-
-config SYS_VENDOR
-	default "atmel"
-
-config SYS_SOC
-	default "at32ap700x"
-
-config SYS_CONFIG_NAME
-	default "atstk1003"
-
-endif
-
-if TARGET_ATSTK1004
-
-config SYS_BOARD
-	default "atstk1000"
-
-config SYS_VENDOR
-	default "atmel"
-
-config SYS_SOC
-	default "at32ap700x"
-
-config SYS_CONFIG_NAME
-	default "atstk1004"
-
-endif
-
-if TARGET_ATSTK1006
-
-config SYS_BOARD
-	default "atstk1000"
-
-config SYS_VENDOR
-	default "atmel"
-
-config SYS_SOC
-	default "at32ap700x"
-
-config SYS_CONFIG_NAME
-	default "atstk1006"
-
-endif

board/atmel/atstk1000/MAINTAINERS

@@ -1,12 +1,6 @@
 ATSTK1000 BOARD
-#M:	Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
-S:	Orphan (since 2014-06)
+M:	Andreas Bießmann <andreas.biessmann@corscience.de>
+S:	Maintained
 F:	board/atmel/atstk1000/
 F:	include/configs/atstk1002.h
 F:	configs/atstk1002_defconfig
-F:	include/configs/atstk1003.h
-F:	configs/atstk1003_defconfig
-F:	include/configs/atstk1004.h
-F:	configs/atstk1004_defconfig
-F:	include/configs/atstk1006.h
-F:	configs/atstk1006_defconfig

board/atmel/atstk1000/atstk1000.c

@@ -30,32 +30,12 @@ struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
 };
 
 static const struct sdram_config sdram_config = {
-#if defined(CONFIG_ATSTK1006)
-	/* Dual MT48LC16M16A2-7E (64 MB) on daughterboard */
 	.data_bits	= SDRAM_DATA_32BIT,
-	.row_bits	= 13,
-	.col_bits	= 9,
-	.bank_bits	= 2,
-	.cas		= 2,
-	.twr		= 2,
-	.trc		= 7,
-	.trp		= 2,
-	.trcd		= 2,
-	.tras		= 4,
-	.txsr		= 7,
-	/* 7.81 us */
-	.refresh_period	= (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
-#else
-	/* MT48LC2M32B2P-5 (8 MB) on motherboard */
-#ifdef CONFIG_ATSTK1004
-	.data_bits	= SDRAM_DATA_16BIT,
-#else
-	.data_bits	= SDRAM_DATA_32BIT,
-#endif
 #ifdef CONFIG_ATSTK1000_16MB_SDRAM
 	/* MT48LC4M32B2P-6 (16 MB) on mod'ed motherboard */
 	.row_bits	= 12,
 #else
+	/* MT48LC2M32B2P-5 (8 MB) on motherboard */
 	.row_bits	= 11,
 #endif
 	.col_bits	= 8,
@@ -69,7 +49,6 @@ static const struct sdram_config sdram_config = {
 	.txsr		= 5,
 	/* 15.6 us */
 	.refresh_period	= (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
-#endif
 };
 
 int board_early_init_f(void)

board/earthlcd/favr-32-ezkit/Kconfig

@@ -1,15 +0,0 @@
-if TARGET_FAVR_32_EZKIT
-
-config SYS_BOARD
-	default "favr-32-ezkit"
-
-config SYS_VENDOR
-	default "earthlcd"
-
-config SYS_SOC
-	default "at32ap700x"
-
-config SYS_CONFIG_NAME
-	default "favr-32-ezkit"
-
-endif

board/earthlcd/favr-32-ezkit/MAINTAINERS

@@ -1,6 +0,0 @@
-FAVR-32-EZKIT BOARD
-#M:	Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
-S:	Orphan (since 2014-06)
-F:	board/earthlcd/favr-32-ezkit/
-F:	include/configs/favr-32-ezkit.h
-F:	configs/favr-32-ezkit_defconfig

board/earthlcd/favr-32-ezkit/Makefile

@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2008 Atmel Corporation
-#
-# SPDX-License-Identifier:	GPL-2.0+
-
-obj-y	:= favr-32-ezkit.o flash.o

board/earthlcd/favr-32-ezkit/favr-32-ezkit.c

@@ -1,81 +0,0 @@
-/*
- * Copyright (C) 2008 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <netdev.h>
-
-#include <asm/io.h>
-#include <asm/sdram.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/hmatrix.h>
-#include <asm/arch/mmu.h>
-#include <asm/arch/portmux.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
-	{
-		.virt_pgno	= CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
-		.nr_pages	= CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
-		.phys		= (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
-					| MMU_VMR_CACHE_NONE,
-	}, {
-		.virt_pgno	= CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
-		.nr_pages	= EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
-		.phys		= (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
-					| MMU_VMR_CACHE_WRBACK,
-	},
-};
-
-static const struct sdram_config sdram_config = {
-	/* MT48LC4M32B2P-6 (16 MB) */
-	.data_bits	= SDRAM_DATA_32BIT,
-	.row_bits	= 12,
-	.col_bits	= 8,
-	.bank_bits	= 2,
-	.cas		= 3,
-	.twr		= 2,
-	.trc		= 7,
-	.trp		= 2,
-	.trcd		= 2,
-	.tras		= 5,
-	.txsr		= 5,
-	/* 15.6 us */
-	.refresh_period	= (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
-};
-
-int board_early_init_f(void)
-{
-	/* Enable SDRAM in the EBI mux */
-	hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
-
-	portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH);
-
-	sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
-
-	portmux_enable_usart3(PORTMUX_DRIVE_MIN);
-#if defined(CONFIG_MACB)
-	portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
-#endif
-#if defined(CONFIG_MMC)
-	portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
-#endif
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	gd->bd->bi_phy_id[0] = 0x01;
-	return 0;
-}
-
-#if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET)
-int board_eth_init(bd_t *bi)
-{
-	return macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0,
-		bi->bi_phy_id[0]);
-}
-#endif

board/earthlcd/favr-32-ezkit/flash.c

@@ -1,216 +0,0 @@
-/*
- * Copyright (C) 2008 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-
-#ifdef CONFIG_FAVR32_EZKIT_EXT_FLASH
-#include <asm/arch/cacheflush.h>
-#include <asm/io.h>
-#include <asm/sections.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-flash_info_t flash_info[1];
-
-static void flash_identify(uint16_t *flash, flash_info_t *info)
-{
-	unsigned long flags;
-
-	flags = disable_interrupts();
-
-	dcache_flush_unlocked();
-
-	writew(0xaa, flash + 0x555);
-	writew(0x55, flash + 0xaaa);
-	writew(0x90, flash + 0x555);
-	info->flash_id = readl(flash);
-	writew(0xff, flash);
-
-	readw(flash);
-
-	if (flags)
-		enable_interrupts();
-}
-
-unsigned long flash_init(void)
-{
-	unsigned long addr;
-	unsigned int i;
-
-	flash_info[0].size = CONFIG_SYS_FLASH_SIZE;
-	flash_info[0].sector_count = 135;
-
-	flash_identify(uncached((void *)CONFIG_SYS_FLASH_BASE), &flash_info[0]);
-
-	for (i = 0, addr = 0; i < 8; i++, addr += 0x2000)
-		flash_info[0].start[i] = addr;
-	for (; i < flash_info[0].sector_count; i++, addr += 0x10000)
-		flash_info[0].start[i] = addr;
-
-	return CONFIG_SYS_FLASH_SIZE;
-}
-
-void flash_print_info(flash_info_t *info)
-{
-	printf("Flash: Vendor ID: 0x%02lx, Product ID: 0x%02lx\n",
-	       info->flash_id >> 16, info->flash_id & 0xffff);
-	printf("Size: %ld MB in %d sectors\n",
-	       info->size >> 10, info->sector_count);
-}
-
-int flash_erase(flash_info_t *info, int s_first, int s_last)
-{
-	unsigned long flags;
-	unsigned long start_time;
-	uint16_t *fb, *sb;
-	unsigned int i;
-	int ret;
-	uint16_t status;
-
-	if ((s_first < 0) || (s_first > s_last)
-	    || (s_last >= info->sector_count)) {
-		puts("Error: first and/or last sector out of range\n");
-		return ERR_INVAL;
-	}
-
-	for (i = s_first; i < s_last; i++)
-		if (info->protect[i]) {
-			printf("Error: sector %d is protected\n", i);
-			return ERR_PROTECTED;
-		}
-
-	fb = (uint16_t *)uncached(info->start[0]);
-
-	dcache_flush_unlocked();
-
-	for (i = s_first; (i <= s_last) && !ctrlc(); i++) {
-		printf("Erasing sector %3d...", i);
-
-		sb = (uint16_t *)uncached(info->start[i]);
-
-		flags = disable_interrupts();
-
-		start_time = get_timer(0);
-
-		/* Unlock sector */
-		writew(0xaa, fb + 0x555);
-		writew(0x70, sb);
-
-		/* Erase sector */
-		writew(0xaa, fb + 0x555);
-		writew(0x55, fb + 0xaaa);
-		writew(0x80, fb + 0x555);
-		writew(0xaa, fb + 0x555);
-		writew(0x55, fb + 0xaaa);
-		writew(0x30, sb);
-
-		/* Wait for completion */
-		ret = ERR_OK;
-		do {
-			/* TODO: Timeout */
-			status = readw(sb);
-		} while ((status != 0xffff) && !(status & 0x28));
-
-		writew(0xf0, fb);
-
-		/*
-		 * Make sure the command actually makes it to the bus
-		 * before we re-enable interrupts.
-		 */
-		readw(fb);
-
-		if (flags)
-			enable_interrupts();
-
-		if (status != 0xffff) {
-			printf("Flash erase error at address 0x%p: 0x%02x\n",
-			       sb, status);
-			ret = ERR_PROG_ERROR;
-			break;
-		}
-	}
-
-	if (ctrlc())
-		printf("User interrupt!\n");
-
-	return ERR_OK;
-}
-
-int write_buff(flash_info_t *info, uchar *src,
-			   ulong addr, ulong count)
-{
-	unsigned long flags;
-	uint16_t *base, *p, *s, *end;
-	uint16_t word, status, status1;
-	int ret = ERR_OK;
-
-	if (addr < info->start[0]
-	    || (addr + count) > (info->start[0] + info->size)
-	    || (addr + count) < addr) {
-		puts("Error: invalid address range\n");
-		return ERR_INVAL;
-	}
-
-	if (addr & 1 || count & 1 || (unsigned int)src & 1) {
-		puts("Error: misaligned source, destination or count\n");
-		return ERR_ALIGN;
-	}
-
-	base = (uint16_t *)uncached(info->start[0]);
-	end = (uint16_t *)uncached(addr + count);
-
-	flags = disable_interrupts();
-
-	dcache_flush_unlocked();
-	sync_write_buffer();
-
-	for (p = (uint16_t *)uncached(addr), s = (uint16_t *)src;
-	     p < end && !ctrlc(); p++, s++) {
-		word = *s;
-
-		writew(0xaa, base + 0x555);
-		writew(0x55, base + 0xaaa);
-		writew(0xa0, base + 0x555);
-		writew(word, p);
-
-		sync_write_buffer();
-
-		/* Wait for completion */
-		status1 = readw(p);
-		do {
-			/* TODO: Timeout */
-			status = status1;
-			status1 = readw(p);
-		} while (((status ^ status1) & 0x40)	/* toggled */
-			 && !(status1 & 0x28));		/* error bits */
-
-		/*
-		 * We'll need to check once again for toggle bit
-		 * because the toggle bit may stop toggling as I/O5
-		 * changes to "1" (ref at49bv642.pdf p9)
-		 */
-		status1 = readw(p);
-		status = readw(p);
-		if ((status ^ status1) & 0x40) {
-			printf("Flash write error at address 0x%p: "
-			       "0x%02x != 0x%02x\n",
-			       p, status,word);
-			ret = ERR_PROG_ERROR;
-			writew(0xf0, base);
-			readw(base);
-			break;
-		}
-
-		writew(0xf0, base);
-		readw(base);
-	}
-
-	if (flags)
-		enable_interrupts();
-
-	return ret;
-}
-
-#endif /* CONFIG_FAVR32_EZKIT_EXT_FLASH */

board/highbank/Makefile

@@ -5,4 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y	:= highbank.o
+obj-y	:= highbank.o ahci.o

board/highbank/ahci.c

@@ -0,0 +1,218 @@
+/*
+ * Copyright 2012 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <ahci.h>
+#include <asm/io.h>
+
+#define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) | (((addr) >> 9) & 0x7f))
+#define CPHY_ADDR(base, dev, addr) ((base) | (((addr) & 0x1ff) << 2))
+#define CPHY_BASE			0xfff58000
+#define CPHY_WIDTH			0x1000
+#define CPHY_DTE_XS			5
+#define CPHY_MII			31
+#define SERDES_CR_CTL			0x80a0
+#define SERDES_CR_ADDR			0x80a1
+#define SERDES_CR_DATA			0x80a2
+#define CR_BUSY				0x0001
+#define CR_START			0x0001
+#define CR_WR_RDN			0x0002
+#define CPHY_TX_INPUT_STS		0x2001
+#define CPHY_RX_INPUT_STS		0x2002
+#define CPHY_SATA_TX_OVERRIDE_BIT	0x8000
+#define CPHY_SATA_RX_OVERRIDE_BIT	0x4000
+#define CPHY_TX_INPUT_OVERRIDE		0x2004
+#define CPHY_RX_INPUT_OVERRIDE		0x2005
+#define SPHY_LANE			0x100
+#define SPHY_HALF_RATE			0x0001
+#define CPHY_SATA_DPLL_MODE		0x0700
+#define CPHY_SATA_DPLL_SHIFT		8
+#define CPHY_SATA_TX_ATTEN		0x1c00
+#define CPHY_SATA_TX_ATTEN_SHIFT	10
+
+#define HB_SREG_SATA_ATTEN		0xfff3cf24
+
+#define SATA_PORT_BASE			0xffe08000
+#define SATA_VERSIONR			0xf8
+#define SATA_HB_VERSION			0x3332302a
+
+static u32 __combo_phy_reg_read(u8 phy, u8 dev, u32 addr)
+{
+	u32 data;
+	writel(CPHY_MAP(dev, addr), CPHY_BASE + 0x800 + CPHY_WIDTH * phy);
+	data = readl(CPHY_ADDR(CPHY_BASE + CPHY_WIDTH * phy, dev, addr));
+	return data;
+}
+
+static void __combo_phy_reg_write(u8 phy, u8 dev, u32 addr, u32 data)
+{
+	writel(CPHY_MAP(dev, addr), CPHY_BASE + 0x800 + CPHY_WIDTH * phy);
+	writel(data, CPHY_ADDR(CPHY_BASE + CPHY_WIDTH * phy, dev, addr));
+}
+
+static u32 combo_phy_read(u8 phy, u32 addr)
+{
+	u8 dev = CPHY_DTE_XS;
+	if (phy == 5)
+		dev = CPHY_MII;
+	while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY)
+		udelay(5);
+	__combo_phy_reg_write(phy, dev, SERDES_CR_ADDR, addr);
+	__combo_phy_reg_write(phy, dev, SERDES_CR_CTL, CR_START);
+	while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY)
+		udelay(5);
+	return __combo_phy_reg_read(phy, dev, SERDES_CR_DATA);
+}
+
+static void combo_phy_write(u8 phy, u32 addr, u32 data)
+{
+	u8 dev = CPHY_DTE_XS;
+	if (phy == 5)
+		dev = CPHY_MII;
+	while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY)
+		udelay(5);
+	__combo_phy_reg_write(phy, dev, SERDES_CR_ADDR, addr);
+	__combo_phy_reg_write(phy, dev, SERDES_CR_DATA, data);
+	__combo_phy_reg_write(phy, dev, SERDES_CR_CTL, CR_WR_RDN | CR_START);
+}
+
+static void cphy_spread_spectrum_override(u8 phy, u8 lane, u32 val)
+{
+	u32 tmp;
+	tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
+	tmp &= ~CPHY_SATA_RX_OVERRIDE_BIT;
+	combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+
+	tmp |= CPHY_SATA_RX_OVERRIDE_BIT;
+	combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+
+	tmp &= ~CPHY_SATA_DPLL_MODE;
+	tmp |= (val << CPHY_SATA_DPLL_SHIFT) & CPHY_SATA_DPLL_MODE;
+	combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+}
+
+static void cphy_tx_attenuation_override(u8 phy, u8 lane)
+{
+	u32 val;
+	u32 tmp;
+	u8  shift;
+
+	shift = ((phy == 5) ? 4 : lane) * 4;
+
+	val = (readl(HB_SREG_SATA_ATTEN) >> shift) & 0xf;
+
+	if (val & 0x8)
+		return;
+
+	tmp = combo_phy_read(phy, CPHY_TX_INPUT_STS + lane * SPHY_LANE);
+	tmp &= ~CPHY_SATA_TX_OVERRIDE_BIT;
+	combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+
+	tmp |= CPHY_SATA_TX_OVERRIDE_BIT;
+	combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+
+	tmp |= (val << CPHY_SATA_TX_ATTEN_SHIFT) & CPHY_SATA_TX_ATTEN;
+	combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+}
+
+static void cphy_disable_port_overrides(u8 port)
+{
+	u32 tmp;
+	u8 lane = 0, phy = 0;
+
+	if (port == 0)
+		phy = 5;
+	else if (port < 5)
+		lane = port - 1;
+	else
+		return;
+	tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
+	tmp &= ~CPHY_SATA_RX_OVERRIDE_BIT;
+	combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+
+	tmp = combo_phy_read(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE);
+	tmp &= ~CPHY_SATA_TX_OVERRIDE_BIT;
+	combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+}
+
+void cphy_disable_overrides(void)
+{
+	int i;
+	u32 port_map;
+
+	port_map = readl(0xffe08000 + HOST_PORTS_IMPL);
+	for (i = 0; i < 5; i++) {
+		if (port_map & (1 << i))
+			cphy_disable_port_overrides(i);
+	}
+}
+
+static void cphy_override_lane(u8 port)
+{
+	u32 tmp, k = 0;
+	u8 lane = 0, phy = 0;
+
+	if (port == 0)
+		phy = 5;
+	else if (port < 5)
+		lane = port - 1;
+	else
+		return;
+
+	do {
+		tmp = combo_phy_read(0, CPHY_RX_INPUT_STS +
+					lane * SPHY_LANE);
+	} while ((tmp & SPHY_HALF_RATE) && (k++ < 1000));
+	cphy_spread_spectrum_override(phy, lane, 3);
+	cphy_tx_attenuation_override(phy, lane);
+}
+
+#define WAIT_MS_LINKUP	4
+
+int ahci_link_up(struct ahci_probe_ent *probe_ent, int port)
+{
+	u32 tmp;
+	int j = 0;
+	u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio;
+	u32 is_highbank = readl(SATA_PORT_BASE + SATA_VERSIONR) ==
+				SATA_HB_VERSION ? 1 : 0;
+
+	/* Bring up SATA link.
+	 * SATA link bringup time is usually less than 1 ms; only very
+	 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
+	 */
+	while (j < WAIT_MS_LINKUP) {
+		if (is_highbank && (j == 0)) {
+			cphy_disable_port_overrides(port);
+			writel(0x301, port_mmio + PORT_SCR_CTL);
+			udelay(1000);
+			writel(0x300, port_mmio + PORT_SCR_CTL);
+			udelay(1000);
+			cphy_override_lane(port);
+		}
+
+		tmp = readl(port_mmio + PORT_SCR_STAT);
+		if ((tmp & 0xf) == 0x3)
+			return 0;
+		udelay(1000);
+		j++;
+
+		if ((j == WAIT_MS_LINKUP) && (tmp & 0xf))
+			j = 0;	/* retry phy reset */
+	}
+	return 1;
+}

board/highbank/highbank.c

@@ -14,9 +14,11 @@
 
 #define HB_AHCI_BASE			0xffe08000
 
+#define HB_SCU_A9_PWR_STATUS		0xfff10008
 #define HB_SREG_A9_PWR_REQ		0xfff3cf00
 #define HB_SREG_A9_BOOT_SRC_STAT	0xfff3cf04
 #define HB_SREG_A9_PWRDOM_STAT		0xfff3cf20
+#define HB_SREG_A15_PWR_CTRL		0xfff3c200
 
 #define HB_PWR_SUSPEND			0
 #define HB_PWR_SOFT_RESET		1
@@ -27,8 +29,14 @@
 #define PWRDOM_STAT_PCI			0x40000000
 #define PWRDOM_STAT_EMMC		0x20000000
 
+#define HB_SCU_A9_PWR_NORMAL		0
+#define HB_SCU_A9_PWR_DORMANT		2
+#define HB_SCU_A9_PWR_OFF		3
+
 DECLARE_GLOBAL_DATA_PTR;
 
+void cphy_disable_overrides(void);
+
 /*
  * Miscellaneous platform dependent initialisations
  */
@@ -56,6 +64,7 @@ void scsi_init(void)
 {
 	u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
 
+	cphy_disable_overrides();
 	if (reg & PWRDOM_STAT_SATA) {
 		ahci_init((void __iomem *)HB_AHCI_BASE);
 		scsi_scan(1);
@@ -111,9 +120,31 @@ int ft_board_setup(void *fdt, bd_t *bd)
 }
 #endif
 
+static int is_highbank(void)
+{
+	uint32_t midr;
+
+	asm volatile ("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr));
+
+	return (midr & 0xfff0) == 0xc090;
+}
+
 void reset_cpu(ulong addr)
 {
 	writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ);
+	if (is_highbank())
+		writeb(HB_SCU_A9_PWR_OFF, HB_SCU_A9_PWR_STATUS);
+	else
+		writel(0x1, HB_SREG_A15_PWR_CTRL);
 
 	wfi();
 }
+
+/*
+ * turn off the override before transferring control to Linux, since Linux
+ * may not support spread spectrum.
+ */
+void arch_preboot_os(void)
+{
+	cphy_disable_overrides();
+}

board/mimc/mimc200/Kconfig

@@ -1,15 +0,0 @@
-if TARGET_MIMC200
-
-config SYS_BOARD
-	default "mimc200"
-
-config SYS_VENDOR
-	default "mimc"
-
-config SYS_SOC
-	default "at32ap700x"
-
-config SYS_CONFIG_NAME
-	default "mimc200"
-
-endif

board/mimc/mimc200/MAINTAINERS

@@ -1,6 +0,0 @@
-MIMC200 BOARD
-M:	Mark Jackson <mpfj@mimc.co.uk>
-S:	Maintained
-F:	board/mimc/mimc200/
-F:	include/configs/mimc200.h
-F:	configs/mimc200_defconfig

board/mimc/mimc200/Makefile

@@ -1,6 +0,0 @@
-#
-# Copyright (C) 2005-2006 Atmel Corporation
-#
-# SPDX-License-Identifier:	GPL-2.0+
-
-obj-y	:= mimc200.o

board/mimc/mimc200/mimc200.c

@@ -1,197 +0,0 @@
-/*
- * Copyright (C) 2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <netdev.h>
-
-#include <asm/io.h>
-#include <asm/sdram.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/hmatrix.h>
-#include <asm/arch/mmu.h>
-#include <asm/arch/portmux.h>
-#include <atmel_lcdc.h>
-#include <lcd.h>
-
-#include "../../../arch/avr32/cpu/hsmc3.h"
-
-struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
-	{
-		.virt_pgno	= CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
-		.nr_pages	= CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
-		.phys		= (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
-					| MMU_VMR_CACHE_NONE,
-	}, {
-		.virt_pgno	= EBI_SRAM_CS2_BASE >> MMU_PAGE_SHIFT,
-		.nr_pages	= EBI_SRAM_CS2_SIZE >> MMU_PAGE_SHIFT,
-		.phys		= (EBI_SRAM_CS2_BASE >> MMU_PAGE_SHIFT)
-					| MMU_VMR_CACHE_NONE,
-	}, {
-		.virt_pgno	= CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
-		.nr_pages	= EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
-		.phys		= (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
-					| MMU_VMR_CACHE_WRBACK,
-	},
-};
-
-#if defined(CONFIG_LCD)
-/* 480x272x16 @ 72 Hz */
-vidinfo_t panel_info = {
-	.vl_col			= 480,		/* Number of columns */
-	.vl_row			= 272,		/* Number of rows */
-	.vl_clk			= 5000000,	/* pixel clock in ps */
-	.vl_sync		= ATMEL_LCDC_INVCLK_INVERTED |
-				  ATMEL_LCDC_INVLINE_INVERTED |
-				  ATMEL_LCDC_INVFRAME_INVERTED,
-	.vl_bpix		= LCD_COLOR16,	/* Bits per pixel, BPP = 2^n */
-	.vl_tft			= 1,		/* 0 = passive, 1 = TFT */
-	.vl_hsync_len		= 42,		/* Length of horizontal sync */
-	.vl_left_margin		= 1,		/* Time from sync to picture */
-	.vl_right_margin	= 1,		/* Time from picture to sync */
-	.vl_vsync_len		= 1,		/* Length of vertical sync */
-	.vl_upper_margin	= 12,		/* Time from sync to picture */
-	.vl_lower_margin	= 1,		/* Time from picture to sync */
-	.mmio			= LCDC_BASE,	/* Memory mapped registers */
-};
-
-void lcd_enable(void)
-{
-}
-
-void lcd_disable(void)
-{
-}
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static const struct sdram_config sdram_config = {
-	.data_bits	= SDRAM_DATA_16BIT,
-	.row_bits	= 13,
-	.col_bits	= 9,
-	.bank_bits	= 2,
-	.cas		= 3,
-	.twr		= 2,
-	.trc		= 6,
-	.trp		= 2,
-	.trcd		= 2,
-	.tras		= 6,
-	.txsr		= 6,
-	/* 15.6 us */
-	.refresh_period	= (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
-};
-
-int board_early_init_f(void)
-{
-	/* Enable SDRAM in the EBI mux */
-	hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
-
-	/* Enable 26 address bits and NCS2 */
-	portmux_enable_ebi(16, 26, PORTMUX_EBI_CS(2), PORTMUX_DRIVE_HIGH);
-	sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
-
-	portmux_enable_usart1(PORTMUX_DRIVE_MIN);
-
-	/* de-assert "force sys reset" pin */
-	portmux_select_gpio(PORTMUX_PORT_D, 1 << 15,
-			PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
-
-	/* init custom i/o */
-	/* cpu type inputs */
-	portmux_select_gpio(PORTMUX_PORT_E, (1 << 19) | (1 << 20) | (1 << 23),
-			PORTMUX_DIR_INPUT);
-	/* main board type inputs */
-	portmux_select_gpio(PORTMUX_PORT_B, (1 << 19) | (1 << 29),
-			PORTMUX_DIR_INPUT);
-	/* DEBUG input (use weak pullup) */
-	portmux_select_gpio(PORTMUX_PORT_E, 1 << 21,
-			PORTMUX_DIR_INPUT | PORTMUX_PULL_UP);
-
-	/* are we suppressing the console ? */
-	if (gpio_get_value(GPIO_PIN_PE(21)) == 1)
-		gd->flags |= (GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE);
-
-	/* reset phys */
-	portmux_select_gpio(PORTMUX_PORT_E, 1 << 24, PORTMUX_DIR_INPUT);
-	portmux_select_gpio(PORTMUX_PORT_C, 1 << 18,
-			PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
-
-	udelay(5000);
-
-	/* release phys reset */
-	gpio_set_value(GPIO_PIN_PC(18), 0);	/* PHY RESET (Release)	*/
-
-	/* setup Data Flash chip select (NCS2) */
-	hsmc3_writel(MODE2, 0x20121003);
-	hsmc3_writel(CYCLE2, 0x000a0009);
-	hsmc3_writel(PULSE2, 0x0a060806);
-	hsmc3_writel(SETUP2, 0x00030102);
-
-	/* setup FRAM chip select (NCS3) */
-	hsmc3_writel(MODE3, 0x10120001);
-	hsmc3_writel(CYCLE3, 0x001e001d);
-	hsmc3_writel(PULSE3, 0x08040704);
-	hsmc3_writel(SETUP3, 0x02050204);
-
-#if defined(CONFIG_MACB)
-	/* init macb0 pins */
-	portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
-	portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
-#endif
-
-#if defined(CONFIG_MMC)
-	portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
-#endif
-
-#if defined(CONFIG_LCD)
-	portmux_enable_lcdc(1);
-#endif
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	gd->bd->bi_phy_id[0] = 0x01;
-	gd->bd->bi_phy_id[1] = 0x03;
-	return 0;
-}
-
-int board_postclk_init(void)
-{
-	/* Use GCLK0 as 10MHz output */
-	gclk_enable_output(0, PORTMUX_DRIVE_LOW);
-	gclk_set_rate(0, GCLK_PARENT_OSC0, 10000000);
-	return 0;
-}
-
-/* SPI chip select control */
-#ifdef CONFIG_ATMEL_SPI
-#include <spi.h>
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	return (bus == 0) && (cs == 0);
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-}
-#endif /* CONFIG_ATMEL_SPI */
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bi)
-{
-	macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
-	macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
-
-	return 0;
-}
-#endif

board/miromico/hammerhead/Kconfig

@@ -1,15 +0,0 @@
-if TARGET_HAMMERHEAD
-
-config SYS_BOARD
-	default "hammerhead"
-
-config SYS_VENDOR
-	default "miromico"
-
-config SYS_SOC
-	default "at32ap700x"
-
-config SYS_CONFIG_NAME
-	default "hammerhead"
-
-endif

board/miromico/hammerhead/MAINTAINERS

@@ -1,6 +0,0 @@
-HAMMERHEAD BOARD
-M:	Alex Raimondi <alex.raimondi@miromico.ch>
-S:	Maintained
-F:	board/miromico/hammerhead/
-F:	include/configs/hammerhead.h
-F:	configs/hammerhead_defconfig

board/miromico/hammerhead/Makefile

@@ -1,6 +0,0 @@
-#
-# Copyright (C) 2008 Miromico AG
-#
-# SPDX-License-Identifier:	GPL-2.0+
-
-obj-y	:= hammerhead.o

board/miromico/hammerhead/hammerhead.c

@@ -1,91 +0,0 @@
-/*
- * Copyright (C) 2008 Miromico AG
- *
- * Mostly copied form atmel ATNGW100 sources
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-
-#include <asm/io.h>
-#include <asm/sdram.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/hmatrix.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/mmu.h>
-#include <asm/arch/portmux.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
-	{
-		.virt_pgno	= CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
-		.nr_pages	= CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
-		.phys		= (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
-					| MMU_VMR_CACHE_NONE,
-	}, {
-		.virt_pgno	= CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
-		.nr_pages	= EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
-		.phys		= (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
-					| MMU_VMR_CACHE_WRBACK,
-	},
-};
-
-static const struct sdram_config sdram_config = {
-	.data_bits	= SDRAM_DATA_32BIT,
-	.row_bits	= 13,
-	.col_bits	= 9,
-	.bank_bits	= 2,
-	.cas		= 3,
-	.twr		= 2,
-	.trc		= 7,
-	.trp		= 2,
-	.trcd		= 2,
-	.tras		= 5,
-	.txsr		= 5,
-	/* 7.81 us */
-	.refresh_period	= (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
-};
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
-	return macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0,
-		bis->bi_phy_id[0]);
-}
-#endif
-
-int board_early_init_f(void)
-{
-	/* Enable SDRAM in the EBI mux */
-	hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
-
-	portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH);
-	sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
-
-	portmux_enable_usart1(PORTMUX_DRIVE_MIN);
-
-#if defined(CONFIG_MACB)
-	portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
-#endif
-#if defined(CONFIG_MMC)
-	portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
-#endif
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	gd->bd->bi_phy_id[0] = 0x01;
-	return 0;
-}
-
-int board_postclk_init(void)
-{
-	/* Hammerhead boards uses GCLK3 as 25MHz output to ethernet PHY */
-	gclk_enable_output(3, PORTMUX_DRIVE_LOW);
-	gclk_set_rate(3, GCLK_PARENT_OSC0, 25000000);
-	return 0;
-}

board/nokia/rx51/lowlevel_init.S

@@ -105,10 +105,6 @@ fix_start:
 	/* r6 - maximal u-boot size */
 	ldr	r6, imagesize
 
-	/* fix return address */
-	subhi	lr, lr, r5
-	addlo	lr, lr, r5
-
 	/* r1 - start of u-boot after */
 	ldr	r1, startaddr
 

board/nvidia/nyan-big/MAINTAINERS

@@ -1,4 +1,4 @@
-NORRIN BOARD
+NYAN-BIG BOARD
 M:	Allen Martin <amartin@nvidia.com>
 S:	Maintained
 F:	board/nvidia/nyan-big/

board/nvidia/nyan-big/nyan-big.c

@@ -8,7 +8,12 @@
 #include <common.h>
 #include <errno.h>
 #include <asm/gpio.h>
+#include <asm/io.h>
 #include <asm/arch/pinmux.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mc.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
 #include <power/as3722.h>
 #include <power/pmic.h>
 #include "pinmux-config-nyan-big.h"
@@ -57,3 +62,67 @@ int tegra_lcd_pmic_init(int board_id)
 
 	return 0;
 }
+
+/* Setup required information for Linux kernel */
+static void setup_kernel_info(void)
+{
+	struct mc_ctlr *mc = (void *)NV_PA_MC_BASE;
+
+	/* The kernel graphics driver needs this region locked down */
+	writel(0, &mc->mc_video_protect_bom);
+	writel(0, &mc->mc_video_protect_size_mb);
+	writel(1, &mc->mc_video_protect_reg_ctrl);
+}
+
+/*
+ * We need to take ALL audio devices conntected to AHUB (AUDIO, APBIF,
+ * I2S, DAM, AMX, ADX, SPDIF, AFC) out of reset and enable the clocks.
+ * Otherwise reading AHUB devices will hang when the kernel boots.
+ */
+static void enable_required_clocks(void)
+{
+	static enum periph_id ids[] = {
+		PERIPH_ID_I2S0,
+		PERIPH_ID_I2S1,
+		PERIPH_ID_I2S2,
+		PERIPH_ID_I2S3,
+		PERIPH_ID_I2S4,
+		PERIPH_ID_AUDIO,
+		PERIPH_ID_APBIF,
+		PERIPH_ID_DAM0,
+		PERIPH_ID_DAM1,
+		PERIPH_ID_DAM2,
+		PERIPH_ID_AMX0,
+		PERIPH_ID_AMX1,
+		PERIPH_ID_ADX0,
+		PERIPH_ID_ADX1,
+		PERIPH_ID_SPDIF,
+		PERIPH_ID_AFC0,
+		PERIPH_ID_AFC1,
+		PERIPH_ID_AFC2,
+		PERIPH_ID_AFC3,
+		PERIPH_ID_AFC4,
+		PERIPH_ID_AFC5,
+		PERIPH_ID_EXTPERIPH1
+	};
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(ids); i++)
+		clock_enable(ids[i]);
+	udelay(2);
+	for (i = 0; i < ARRAY_SIZE(ids); i++)
+		reset_set_enable(ids[i], 0);
+}
+
+int nvidia_board_init(void)
+{
+	clock_start_periph_pll(PERIPH_ID_EXTPERIPH1, CLOCK_ID_OSC, 12000000);
+	clock_start_periph_pll(PERIPH_ID_I2S1, CLOCK_ID_OSC, 1500000);
+
+	/* For external MAX98090 audio codec */
+	clock_external_output(1);
+	setup_kernel_info();
+	enable_required_clocks();
+
+	return 0;
+}

board/samsung/common/board.c

@@ -24,8 +24,9 @@
 #include <asm/arch/sromc.h>
 #include <lcd.h>
 #include <i2c.h>
-#include <samsung/misc.h>
 #include <usb.h>
+#include <dwc3-uboot.h>
+#include <samsung/misc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -378,5 +379,8 @@ void reset_misc(void)
 
 int board_usb_cleanup(int index, enum usb_init_type init)
 {
+#ifdef CONFIG_USB_DWC3
+	dwc3_uboot_exit(index);
+#endif
 	return 0;
 }

board/samsung/common/bootscripts/autoboot.cmd

@@ -0,0 +1,92 @@
+# This is an example file to generate boot.scr - a boot script for U-Boot
+# Generate boot.scr:
+# ./tools/mkimage -c none -A arm -T script -d autoboot.cmd boot.scr
+#
+# It requires a list of environment variables to be defined before load:
+# platform dependent: boardname, fdtfile, console
+# system dependent: mmcbootdev, mmcbootpart, mmcrootdev, mmcrootpart, rootfstype
+#
+setenv fdtaddr     "40800000"
+setenv initrdname  "uInitrd"
+setenv initrdaddr  "42000000"
+setenv loaddtb     "load mmc ${mmcbootdev}:${mmcbootpart} ${fdtaddr} ${fdtfile}"
+setenv loadinitrd  "load mmc ${mmcbootdev}:${mmcbootpart} ${initrdaddr} ${initrdname}"
+setenv loadkernel  "load mmc ${mmcbootdev}:${mmcbootpart} '${kerneladdr}' '${kernelname}'"
+setenv kernel_args "setenv bootargs ${console} root=/dev/mmcblk${mmcrootdev}p${mmcrootpart} rootfstype=${rootfstype} rootwait ${opts}"
+
+#### Routine: check_dtb - check that target.dtb exists on boot partition
+setenv check_dtb "
+if test -e mmc '${mmcbootdev}':'${mmcbootpart}' '${fdtfile}'; then
+	run loaddtb;
+	setenv fdt_addr ${fdtaddr};
+else
+	echo Warning! Booting without DTB: '${fdtfile}'!;
+	setenv fdt_addr;
+fi;"
+
+#### Routine: check_ramdisk - check that uInitrd exists on boot partition
+setenv check_ramdisk "
+if test -e mmc '${mmcbootdev}':'${mmcbootpart}' '${initrdname}'; then
+	echo "Found ramdisk image.";
+	run loadinitrd;
+	setenv initrd_addr ${initrdaddr};
+else
+	echo Warning! Booting without RAMDISK: '${initrdname}'!;
+	setenv initrd_addr -;
+fi;"
+
+#### Routine: boot_fit - check that env $boardname is set and boot proper config of ITB image
+setenv setboot_fit "
+if test -e '${boardname}'; then
+	setenv fdt_addr ;
+	setenv initrd_addr ;
+	setenv kerneladdr  0x42000000;
+	setenv kernelname  Image.itb;
+	setenv itbcfg      "\"#${boardname}\"";
+	setenv imgbootcmd  bootm;
+else
+	echo Warning! Variable: \$boardname is undefined!;
+fi"
+
+#### Routine: setboot_uimg - prepare env to boot uImage
+setenv setboot_uimg "
+	setenv kerneladdr 0x40007FC0;
+	setenv kernelname uImage;
+	setenv itbcfg     ;
+	setenv imgbootcmd bootm;
+	run check_dtb;
+	run check_ramdisk;"
+
+#### Routine: setboot_zimg - prepare env to boot zImage
+setenv setboot_zimg "
+	setenv kerneladdr 0x40007FC0;
+	setenv kernelname zImage;
+	setenv itbcfg     ;
+	setenv imgbootcmd bootz;
+	run check_dtb;
+	run check_ramdisk;"
+
+#### Routine: boot_img - boot the kernel after env setup
+setenv boot_img "
+	run loadkernel;
+	run kernel_args;
+	'${imgbootcmd}' '${kerneladdr}${itbcfg}' '${initrd_addr}' '${fdt_addr}';"
+
+#### Routine: autoboot - choose proper boot path
+setenv autoboot "
+if test -e mmc 0:${mmcbootpart} Image.itb; then
+	echo Found kernel image: Image.itb;
+	run setboot_fit;
+	run boot_img;
+elif test -e mmc 0:${mmcbootpart} zImage; then
+	echo Found kernel image: zImage;
+	run setboot_zimg;
+	run boot_img;
+elif test -e mmc 0:${mmcbootpart} uImage; then
+	echo Found kernel image: uImage;
+	run setboot_uimg;
+	run boot_img;
+fi;"
+
+#### Execute the defined autoboot macro
+run autoboot

board/samsung/common/bootscripts/bootzimg.cmd

@@ -0,0 +1,10 @@
+setenv kernelname zImage;
+setenv boot_kernel "setenv bootargs \"${console} root=/dev/mmcblk${mmcrootdev}p${mmcrootpart} rootfstype=${rootfstype} rootwait ${opts}\";
+load mmc ${mmcbootdev}:${mmcbootpart} 0x40007FC0 '${kernelname}';
+if load mmc ${mmcbootdev}:${mmcbootpart} 40800000 ${fdtfile}; then
+	bootz 0x40007FC0 - 40800000;
+else
+	echo Warning! Booting without DTB: '${fdtfile}'!;
+	bootz 0x40007FC0 -;
+fi;"
+run boot_kernel;

board/samsung/smdk5420/smdk5420.c

@@ -6,19 +6,25 @@
 
 #include <common.h>
 #include <fdtdec.h>
+#include <errno.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/board.h>
+#include <asm/arch/power.h>
+#include <asm/arch/system.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/dp_info.h>
+#include <asm/arch/xhci-exynos.h>
+#include <power/tps65090_pmic.h>
 #include <i2c.h>
 #include <lcd.h>
+#include <mmc.h>
 #include <parade.h>
 #include <spi.h>
-#include <errno.h>
-#include <asm/gpio.h>
-#include <asm/arch/board.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/system.h>
-#include <asm/arch/dp_info.h>
-#include <power/tps65090_pmic.h>
+#include <usb.h>
+#include <dwc3-uboot.h>
+#include <samsung-usb-phy-uboot.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -75,3 +81,63 @@ int board_get_revision(void)
 {
 	return 0;
 }
+
+#ifdef CONFIG_USB_DWC3
+static struct dwc3_device dwc3_device_data = {
+	.maximum_speed = USB_SPEED_SUPER,
+	.base = 0x12400000,
+	.dr_mode = USB_DR_MODE_PERIPHERAL,
+	.index = 0,
+};
+
+int usb_gadget_handle_interrupts(void)
+{
+	dwc3_uboot_handle_interrupt(0);
+	return 0;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	struct exynos_usb3_phy *phy = (struct exynos_usb3_phy *)
+		samsung_get_base_usb3_phy();
+
+	if (!phy) {
+		error("usb3 phy not supported");
+		return -ENODEV;
+	}
+
+	set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_EN);
+	exynos5_usb3_phy_init(phy);
+
+	return dwc3_uboot_init(&dwc3_device_data);
+}
+#endif
+#ifdef CONFIG_SET_DFU_ALT_INFO
+char *get_dfu_alt_system(char *interface, char *devstr)
+{
+	return getenv("dfu_alt_system");
+}
+
+char *get_dfu_alt_boot(char *interface, char *devstr)
+{
+	struct mmc *mmc;
+	char *alt_boot;
+	int dev_num;
+
+	dev_num = simple_strtoul(devstr, NULL, 10);
+
+	mmc = find_mmc_device(dev_num);
+	if (!mmc)
+		return NULL;
+
+	if (mmc_init(mmc))
+		return NULL;
+
+	if (IS_SD(mmc))
+		alt_boot = CONFIG_DFU_ALT_BOOT_SD;
+	else
+		alt_boot = CONFIG_DFU_ALT_BOOT_EMMC;
+
+	return alt_boot;
+}
+#endif

board/siemens/common/board.c

@@ -75,8 +75,9 @@ int board_init(void)
 	i2c_set_bus_num(0);
 	if (read_eeprom() < 0)
 		puts("Could not get board ID.\n");
-
+#ifdef CONFIG_MACH_TYPE
 	gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+#endif
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
 #ifdef CONFIG_FACTORYSET
@@ -102,21 +103,29 @@ const struct dpll_params *get_dpll_ddr_params(void)
 }
 
 #ifndef CONFIG_SPL_BUILD
+
+#define MAX_NR_LEDS	10
+#define MAX_PIN_NUMBER	128
+#define STARTUP	0
+
 #if defined(BOARD_DFU_BUTTON_GPIO)
-/*
- * This command returns the status of the user button on
- * Input - none
- * Returns -	1 if button is held down
- *		0 if button is not held down
- */
-static int
-do_userbutton(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+unsigned char get_button_state(char * const envname, unsigned char def)
 {
 	int button = 0;
 	int gpio;
+	char *ptr_env;
 
-	gpio = BOARD_DFU_BUTTON_GPIO;
-	gpio_request(gpio, "DFU");
+	/* If button is not found we take default */
+	ptr_env = getenv(envname);
+	if (NULL == ptr_env) {
+		gpio = def;
+	} else {
+		gpio = (unsigned char)simple_strtoul(ptr_env, NULL, 0);
+		if (gpio > MAX_PIN_NUMBER)
+			gpio = def;
+	}
+
+	gpio_request(gpio, "");
 	gpio_direction_input(gpio);
 	if (gpio_get_value(gpio))
 		button = 1;
@@ -127,6 +136,20 @@ do_userbutton(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 	return button;
 }
+/**
+ * This command returns the status of the user button on
+ * Input - none
+ * Returns -	1 if button is held down
+ *		0 if button is not held down
+ */
+static int
+do_userbutton(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int button = 0;
+	button = get_button_state("button_dfu0", BOARD_DFU_BUTTON_GPIO);
+	button |= get_button_state("button_dfu1", BOARD_DFU_BUTTON_GPIO);
+	return button;
+}
 
 U_BOOT_CMD(
 	dfubutton, CONFIG_SYS_MAXARGS, 1, do_userbutton,
@@ -134,46 +157,6 @@ U_BOOT_CMD(
 	""
 );
 #endif
-/*
- * This command sets led
- * Input -	name of led
- *		value of led
- * Returns -	1 if input does not match
- *		0 if led was set
- */
-static int
-do_setled(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int gpio = 0;
-	if (argc != 3)
-		goto exit;
-#if defined(BOARD_STATUS_LED)
-	if (!strcmp(argv[1], "stat"))
-		gpio = BOARD_STATUS_LED;
-#endif
-#if defined(BOARD_DFU_BUTTON_LED)
-	if (!strcmp(argv[1], "dfu"))
-		gpio = BOARD_DFU_BUTTON_LED;
-#endif
-	/* If argument does not mach exit */
-	if (gpio == 0)
-		goto exit;
-	gpio_request(gpio, "");
-	gpio_direction_output(gpio, 1);
-	if (!strcmp(argv[2], "1"))
-		gpio_set_value(gpio, 1);
-	else
-		gpio_set_value(gpio, 0);
-	return 0;
-exit:
-	return 1;
-}
-
-U_BOOT_CMD(
-	led, CONFIG_SYS_MAXARGS, 2, do_setled,
-	"Set led on or off",
-	"dfu val - set dfu led\nled stat val - set status led"
-);
 
 static int
 do_usertestwdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -189,4 +172,95 @@ U_BOOT_CMD(
 	"Sends U-Boot into infinite loop",
 	""
 );
+
+/**
+ * Get led gpios from env and set them.
+ * The led define in environment need to need to be of the form ledN=NN,S0,S1
+ * where N is an unsigned integer from 0 to 9 and S0 and S1 is 0 or 1. S0
+ * defines the startup state of the led, S1 the special state of the led when
+ * it enters e.g. dfu mode.
+ */
+void set_env_gpios(unsigned char state)
+{
+	char *ptr_env;
+	char str_tmp[5];	/* must contain "ledX"*/
+	char num[1];
+	unsigned char i, idx, pos1, pos2, ccount;
+	unsigned char gpio_n, gpio_s0, gpio_s1;
+
+	for (i = 0; i < MAX_NR_LEDS; i++) {
+		strcpy(str_tmp, "led");
+		sprintf(num, "%d", i);
+		strcat(str_tmp, num);
+
+		/* If env var is not found we stop */
+		ptr_env = getenv(str_tmp);
+		if (NULL == ptr_env)
+			break;
+
+		/* Find sperators position */
+		pos1 = 0;
+		pos2 = 0;
+		ccount = 0;
+		for (idx = 0; ptr_env[idx] != '\0'; idx++) {
+			if (ptr_env[idx] == ',') {
+				if (ccount++ < 1)
+					pos1 = idx;
+				else
+					pos2 = idx;
+			}
+		}
+		/* Bad led description skip this definition */
+		if (pos2 <= pos1 || ccount > 2)
+			continue;
+
+		/* Get pin number and request gpio */
+		memset(str_tmp, 0, sizeof(str_tmp));
+		strncpy(str_tmp, ptr_env, pos1*sizeof(char));
+		gpio_n = (unsigned char)simple_strtoul(str_tmp, NULL, 0);
+
+		/* Invalid gpio number skip definition */
+		if (gpio_n > MAX_PIN_NUMBER)
+			continue;
+
+		gpio_request(gpio_n, "");
+
+		if (state == STARTUP) {
+			/* get pin state 0 and set */
+			memset(str_tmp, 0, sizeof(str_tmp));
+			strncpy(str_tmp, ptr_env+pos1+1,
+				(pos2-pos1-1)*sizeof(char));
+			gpio_s0 = (unsigned char)simple_strtoul(str_tmp, NULL,
+								0);
+
+			gpio_direction_output(gpio_n, gpio_s0);
+
+		} else {
+			/* get pin state 1 and set */
+			memset(str_tmp, 0, sizeof(str_tmp));
+			strcpy(str_tmp, ptr_env+pos2+1);
+			gpio_s1 = (unsigned char)simple_strtoul(str_tmp, NULL,
+								0);
+			gpio_direction_output(gpio_n, gpio_s1);
+		}
+	} /* loop through defined led in environment */
+}
+
+static int do_board_led(cmd_tbl_t *cmdtp, int flag, int argc,
+			   char *const argv[])
+{
+	if (argc != 2)
+		return CMD_RET_USAGE;
+	if ((unsigned char)simple_strtoul(argv[1], NULL, 0) == STARTUP)
+		set_env_gpios(0);
+	else
+		set_env_gpios(1);
+	return 0;
+};
+
+U_BOOT_CMD(
+	draco_led, CONFIG_SYS_MAXARGS, 2,	do_board_led,
+	"Set LEDs defined in environment",
+	"<0|1>"
+);
 #endif /* !CONFIG_SPL_BUILD */

board/siemens/draco/Kconfig

@@ -14,7 +14,7 @@ config SYS_CONFIG_NAME
 
 endif
 
-if TARGET_DXR2
+if TARGET_THUBAN
 
 config SYS_BOARD
 	default "draco"
@@ -26,6 +26,22 @@ config SYS_SOC
 	default "am33xx"
 
 config SYS_CONFIG_NAME
-	default "dxr2"
+	default "thuban"
+
+endif
+
+if TARGET_RASTABAN
+
+config SYS_BOARD
+	default "draco"
+
+config SYS_VENDOR
+	default "siemens"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "rastaban"
 
 endif

board/siemens/draco/MAINTAINERS

@@ -4,5 +4,7 @@ S:	Maintained
 F:	board/siemens/draco/
 F:	include/configs/draco.h
 F:	configs/draco_defconfig
-F:	include/configs/dxr2.h
-F:	configs/dxr2_defconfig
+F:	include/configs/thuban.h
+F:	configs/thuban_defconfig
+F:	include/configs/rastaban.h
+F:	configs/rastaban_defconfig

board/siemens/draco/board.c

@@ -43,7 +43,7 @@ static struct draco_baseboard_id __attribute__((section(".data"))) settings;
 /* Default@303MHz-i0 */
 const struct ddr3_data ddr3_default = {
 	0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
-	0x0079, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x00100206, 0x61A44A32,
+	0x0079, 0x0888A39B, 0x26517FDA, 0x501F84EF, 0x00100206, 0x61A44A32,
 	0x0000093B, 0x0000014A,
 	"default name @303MHz           \0",
 	"default marking                \0",
@@ -71,8 +71,8 @@ static void print_ddr3_timings(void)
 	printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ);
 	printf("device:\t\t%s\n", settings.ddr3.manu_name);
 	printf("marking:\t%s\n", settings.ddr3.manu_marking);
-	printf("timing parameters\n");
-	printf("diff\teeprom\tdefault\n");
+	printf("%-20s, %-8s, %-8s, %-4s\n", "timing parameters", "eeprom",
+	       "default", "diff");
 	PRINTARGS(magic);
 	PRINTARGS(version);
 	PRINTARGS(ddr3_sratio);
@@ -96,9 +96,12 @@ static void print_ddr3_timings(void)
 
 static void print_chip_data(void)
 {
+	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
 	printf("\nCPU BOARD\n");
 	printf("device: \t'%s'\n", settings.chip.sdevname);
 	printf("hw version: \t'%s'\n", settings.chip.shwver);
+	printf("max freq: \t%d MHz\n", dpll_mpu_opp100.m);
 }
 #endif /* CONFIG_SPL_BUILD */
 
@@ -193,6 +196,11 @@ struct ctrl_ioregs draco_ddr3_ioregs = {
 
 	config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data,
 		   &draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0);
+
+	/* For Samsung 2Gbit RAM we need this delay otherwise config fails after
+	 * soft reset.
+	 */
+	udelay(2000);
 }
 
 static void spl_siemens_board_init(void)
@@ -201,6 +209,26 @@ static void spl_siemens_board_init(void)
 }
 #endif /* if def CONFIG_SPL_BUILD */
 
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	omap_nand_switch_ecc(1, 8);
+#ifdef CONFIG_FACTORYSET
+	/* Set ASN in environment*/
+	if (factory_dat.asn[0] != 0) {
+		setenv("dtb_name", (char *)factory_dat.asn);
+	} else {
+		/* dtb suffix gets added in load script */
+		setenv("dtb_name", "am335x-draco");
+	}
+#else
+	setenv("dtb_name", "am335x-draco");
+#endif
+
+	return 0;
+}
+#endif
+
 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 static void cpsw_control(int enabled)
@@ -280,13 +308,4 @@ U_BOOT_CMD(
 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
 
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
-	omap_nand_switch_ecc(1, 8);
-
-	return 0;
-}
-#endif
-
 #include "../common/board.c"

board/siemens/draco/board.h

@@ -16,9 +16,13 @@
 #ifndef _BOARD_H_
 #define _BOARD_H_
 
-#define PARGS3(x)	settings.ddr3.x-ddr3_default.x, \
-			settings.ddr3.x, ddr3_default.x
-#define PRINTARGS(y)	printf("%x, %8x, %8x : "#y"\n", PARGS3(y))
+#define PARGS(x)	#x , /* Parameter Name */ \
+			settings.ddr3.x, /* EEPROM Value */ \
+			ddr3_default.x, /* Default Value */ \
+			settings.ddr3.x-ddr3_default.x /* Difference */
+
+#define PRINTARGS(y)	printf("%-20s, %8x, %8x, %4d\n", PARGS(y))
+
 #define MAGIC_CHIP	0x50494843
 
 /* Automatic generated definition */
@@ -69,4 +73,7 @@ void enable_uart4_pin_mux(void);
 void enable_uart5_pin_mux(void);
 void enable_i2c0_pin_mux(void);
 void enable_board_pin_mux(void);
+
+/* Forwared declaration, defined in common board.c */
+void set_env_gpios(unsigned char state);
 #endif

board/siemens/draco/mux.c

@@ -60,7 +60,7 @@ static struct module_pin_mux nand_pin_mux[] = {
 
 static struct module_pin_mux gpios_pin_mux[] = {
 	/* DFU button GPIO0_27*/
-	{OFFSET(gpmc_ad11), (MODE(7) | PULLUDEN | RXACTIVE)},
+	{OFFSET(gpmc_ad11), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
 	{OFFSET(gpmc_csn3), MODE(7) },			/* LED0 GPIO2_0 */
 	{OFFSET(emu0), MODE(7)},			/* LED1 GPIO3_7 */
 	/* Triacs in HW Rev 2 */
@@ -222,7 +222,7 @@ static struct module_pin_mux gpios_pin_mux[] = {
 	{OFFSET(vrefp), MODE(7) | RXACTIVE | PULLUDDIS},
 	{OFFSET(vrefn), MODE(7) | RXACTIVE | PULLUDDIS},
 	/* nRST for SMSC LAN9303 switch - GPIO2_24 */
-	{OFFSET(lcd_pclk), MODE(7) },			/* LAN9303 nRST */
+	{OFFSET(lcd_pclk), MODE(7) | PULLUDEN | PULLUP_EN }, /* LAN9303 nRST */
 	{-1},
 };
 

board/sunxi/Kconfig

@@ -280,18 +280,6 @@ config MMC_SUNXI_SLOT_EXTRA
 	slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
 	support for this.
 
-config SPL_NAND_SUPPORT
-	bool "SPL/NAND mode support"
-	depends on SPL
-	default n
-	---help---
-	  This enables support for booting from NAND internal
-	  memory. U-Boot SPL doesn't detect where is it load from,
-	  therefore this option is needed to properly load image from
-	  flash. Option also disables MMC functionality on U-Boot due to
-	  initialization errors encountered, when both controllers are
-	  enabled.
-
 config USB0_VBUS_PIN
 	string "Vbus enable pin for usb0 (otg)"
 	default ""
@@ -566,25 +554,4 @@ config GMAC_TX_DELAY
 	---help---
 	Set the GMAC Transmit Clock Delay Chain value.
 
-config SYS_MALLOC_CLEAR_ON_INIT
-	default n
-
-config NETDEVICES
-	default y
-
-config DM_ETH
-	default y
-
-config DM_SERIAL
-	default y
-
-config DM_USB
-	default y if !USB_MUSB_SUNXI
-
-config CMD_SETEXPR
-	default y
-
-config CMD_NET
-	default y
-
 endif

board/sunxi/board.c

@@ -22,9 +22,6 @@
 #ifdef CONFIG_AXP221_POWER
 #include <axp221.h>
 #endif
-#ifdef CONFIG_NAND_SUNXI
-#include <nand.h>
-#endif
 #include <asm/arch/clock.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/display.h>
@@ -318,21 +315,6 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
-#ifdef CONFIG_NAND
-void board_nand_init(void)
-{
-	unsigned int pin;
-	static u8 ports[] = CONFIG_NAND_SUNXI_GPC_PORTS;
-
-	/* Configure AHB muxes to connect output pins with NAND controller */
-	for (pin = 0; pin < 16; pin++)
-		sunxi_gpio_set_cfgpin(SUNXI_GPC(pin), SUNXI_GPC_NAND);
-
-	for (pin = 0; pin < ARRAY_SIZE(ports); pin++)
-		sunxi_gpio_set_cfgpin(SUNXI_GPC(ports[pin]), SUNXI_GPC_NAND);
-}
-#endif
-
 void i2c_init_board(void)
 {
 #ifdef CONFIG_I2C0_ENABLE

board/ti/am43xx/board.c

@@ -148,6 +148,29 @@ static const struct dpll_params idk_dpll_ddr = {
 	400, 23, 1, -1, 2, -1, -1
 };
 
+static const u32 ext_phy_ctrl_const_base_lpddr2[] = {
+	0x00500050,
+	0x00350035,
+	0x00350035,
+	0x00350035,
+	0x00350035,
+	0x00350035,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x40001000,
+	0x08102040
+};
+
 const struct ctrl_ioregs ioregs_lpddr2 = {
 	.cm0ioctl		= LPDDR2_ADDRCTRL_IOCTRL_VALUE,
 	.cm1ioctl		= LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
@@ -318,6 +341,16 @@ static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
 	.emif_cos_config		= 0x00ffffff
 };
 
+void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
+{
+	if (board_is_eposevm()) {
+		*regs = ext_phy_ctrl_const_base_lpddr2;
+		*size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
+	}
+
+	return;
+}
+
 /*
  * get_sys_clk_index : returns the index of the sys_clk read from
  *			ctrl status register. This value is either

board/ti/beagle_x15/board.c

@@ -14,7 +14,10 @@
 #include <usb.h>
 #include <asm/omap_common.h>
 #include <asm/emif.h>
+#include <asm/gpio.h>
+#include <asm/arch/gpio.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/dra7xx_iodelay.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sata.h>
@@ -29,6 +32,9 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* GPIO 7_11 */
+#define GPIO_DDR_VTT_EN 203
+
 const struct omap_sysinfo sysinfo = {
 	"Board: BeagleBoard x15\n"
 };
@@ -52,23 +58,29 @@ static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
 	.sdram_tim1		= 0xceef266b,
 	.sdram_tim2		= 0x328f7fda,
 	.sdram_tim3		= 0x027f88a8,
-	.read_idle_ctrl		= 0x00050001,
+	.read_idle_ctrl		= 0x00050000,
 	.zq_config		= 0x0007190b,
 	.temp_alert_config	= 0x00000000,
-	.emif_ddr_phy_ctlr_1_init = 0x0e24400a,
-	.emif_ddr_phy_ctlr_1	= 0x0e24400a,
+	.emif_ddr_phy_ctlr_1_init = 0x0024400b,
+	.emif_ddr_phy_ctlr_1	= 0x0e24400b,
 	.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
 	.emif_ddr_ext_phy_ctrl_2 = 0x00740074,
 	.emif_ddr_ext_phy_ctrl_3 = 0x00780078,
 	.emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
 	.emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
 	.emif_rd_wr_lvl_rmp_win	= 0x00000000,
-	.emif_rd_wr_lvl_rmp_ctl	= 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl	= 0x80000000,
 	.emif_rd_wr_lvl_ctl	= 0x00000000,
 	.emif_rd_wr_exec_thresh	= 0x00000305
 };
 
+/* Ext phy ctrl regs 1-35 */
 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
+	0x10040100,
+	0x00740074,
+	0x00780078,
+	0x007c007c,
+	0x007b007b,
 	0x00800080,
 	0x00360036,
 	0x00340034,
@@ -90,14 +102,19 @@ static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
 
 	0x00000000,
 	0x00600020,
-	0x40010080,
+	0x40011080,
 	0x08102040,
 
 	0x00400040,
 	0x00400040,
 	0x00400040,
 	0x00400040,
-	0x00400040
+	0x00400040,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0
 };
 
 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
@@ -109,23 +126,28 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 	.sdram_tim1		= 0xceef266b,
 	.sdram_tim2		= 0x328f7fda,
 	.sdram_tim3		= 0x027f88a8,
-	.read_idle_ctrl		= 0x00050001,
+	.read_idle_ctrl		= 0x00050000,
 	.zq_config		= 0x0007190b,
 	.temp_alert_config	= 0x00000000,
-	.emif_ddr_phy_ctlr_1_init = 0x0e24400a,
-	.emif_ddr_phy_ctlr_1	= 0x0e24400a,
+	.emif_ddr_phy_ctlr_1_init = 0x0024400b,
+	.emif_ddr_phy_ctlr_1	= 0x0e24400b,
 	.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
 	.emif_ddr_ext_phy_ctrl_2 = 0x00820082,
 	.emif_ddr_ext_phy_ctrl_3 = 0x008b008b,
 	.emif_ddr_ext_phy_ctrl_4 = 0x00800080,
 	.emif_ddr_ext_phy_ctrl_5 = 0x007e007e,
 	.emif_rd_wr_lvl_rmp_win	= 0x00000000,
-	.emif_rd_wr_lvl_rmp_ctl	= 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl	= 0x80000000,
 	.emif_rd_wr_lvl_ctl	= 0x00000000,
 	.emif_rd_wr_exec_thresh	= 0x00000305
 };
 
 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
+	0x10040100,
+	0x00820082,
+	0x008b008b,
+	0x00800080,
+	0x007e007e,
 	0x00800080,
 	0x00370037,
 	0x00390039,
@@ -145,14 +167,19 @@ static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
 
 	0x00000000,
 	0x00600020,
-	0x40010080,
+	0x40011080,
 	0x08102040,
 
 	0x00400040,
 	0x00400040,
 	0x00400040,
 	0x00400040,
-	0x00400040
+	0x00400040,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0
 };
 
 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
@@ -240,24 +267,21 @@ int board_late_init(void)
 	return 0;
 }
 
-static void do_set_mux32(u32 base,
-			 struct pad_conf_entry const *array, int size)
-{
-	int i;
-	struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
-
-	for (i = 0; i < size; i++, pad++)
-		writel(pad->val, base + pad->offset);
-}
-
 void set_muxconf_regs_essential(void)
 {
 	do_set_mux32((*ctrl)->control_padconf_core_base,
-		     core_padconf_array_essential,
-		     sizeof(core_padconf_array_essential) /
-		     sizeof(struct pad_conf_entry));
+		     early_padconf, ARRAY_SIZE(early_padconf));
 }
 
+#ifdef CONFIG_IODELAY_RECALIBRATION
+void recalibrate_iodelay(void)
+{
+	__recalibrate_iodelay(core_padconf_array_essential,
+			      ARRAY_SIZE(core_padconf_array_essential),
+			      iodelay_cfg_array, ARRAY_SIZE(iodelay_cfg_array));
+}
+#endif
+
 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
@@ -385,3 +409,21 @@ int board_eth_init(bd_t *bis)
 	return ret;
 }
 #endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+/* VTT regulator enable */
+static inline void vtt_regulator_enable(void)
+{
+	if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
+		return;
+
+	gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
+	gpio_direction_output(GPIO_DDR_VTT_EN, 1);
+}
+
+int board_early_init_f(void)
+{
+	vtt_regulator_enable();
+	return 0;
+}
+#endif

board/ti/beagle_x15/mux_data.h

@@ -13,43 +13,318 @@
 #include <asm/arch/mux_dra7xx.h>
 
 const struct pad_conf_entry core_padconf_array_essential[] = {
-	{MMC1_CLK, (IEN | PTU | PDIS | M0)},	/* MMC1_CLK */
-	{MMC1_CMD, (IEN | PTU | PDIS | M0)},	/* MMC1_CMD */
-	{MMC1_DAT0, (IEN | PTU | PDIS | M0)},	/* MMC1_DAT0 */
-	{MMC1_DAT1, (IEN | PTU | PDIS | M0)},	/* MMC1_DAT1 */
-	{MMC1_DAT2, (IEN | PTU | PDIS | M0)},	/* MMC1_DAT2 */
-	{MMC1_DAT3, (IEN | PTU | PDIS | M0)},	/* MMC1_DAT3 */
-	{MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */
-	{MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */
-	{GPMC_A19, (IEN | PTU | PDIS | M1)},	/* mmc2_dat4 */
-	{GPMC_A20, (IEN | PTU | PDIS | M1)},	/* mmc2_dat5 */
-	{GPMC_A21, (IEN | PTU | PDIS | M1)},	/* mmc2_dat6 */
-	{GPMC_A22, (IEN | PTU | PDIS | M1)},	/* mmc2_dat7 */
-	{GPMC_A23, (IEN | PTU | PDIS | M1)},	/* mmc2_clk */
-	{GPMC_A24, (IEN | PTU | PDIS | M1)},	/* mmc2_dat0 */
-	{GPMC_A25, (IEN | PTU | PDIS | M1)},	/* mmc2_dat1 */
-	{GPMC_A26, (IEN | PTU | PDIS | M1)},	/* mmc2_dat2 */
-	{GPMC_A27, (IEN | PTU | PDIS | M1)},	/* mmc2_dat3 */
-	{GPMC_CS1, (IEN | PTU | PDIS | M1)},	/* mmm2_cmd */
-	{UART2_CTSN, (FSC | IEN | PTU | PDIS | M2)}, /* uart2_ctsn.uart3_rxd */
-	{UART2_RTSN, (FSC | IEN | PTU | PDIS | M1)}, /* uart2_rtsn.uart3_txd */
-	{I2C1_SDA, (IEN | PTU | PDIS | M0)},	/* I2C1_SDA */
-	{I2C1_SCL, (IEN | PTU | PDIS | M0)},	/* I2C1_SCL */
-	{MDIO_MCLK, (PTU | PEN | M0)},		/* MDIO_MCLK  */
-	{MDIO_D, (IEN | PTU | PEN | M0)},	/* MDIO_D  */
-	{RGMII0_TXC, (M0) },
-	{RGMII0_TXCTL, (M0) },
-	{RGMII0_TXD3, (M0) },
-	{RGMII0_TXD2, (M0) },
-	{RGMII0_TXD1, (M0) },
-	{RGMII0_TXD0, (M0) },
-	{RGMII0_RXC, (IEN | M0) },
-	{RGMII0_RXCTL, (IEN | M0) },
-	{RGMII0_RXD3, (IEN | M0) },
-	{RGMII0_RXD2, (IEN | M0) },
-	{RGMII0_RXD1, (IEN | M0) },
-	{RGMII0_RXD0, (IEN | M0) },
-	{USB1_DRVVBUS, (M0 | FSC) },
-	{SPI1_CS1, (PEN | IDIS | M14) }, /* GPIO7_11 */
+	{GPMC_AD0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad0.vin3a_d0 */
+	{GPMC_AD1, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_ad1.vin3a_d1 */
+	{GPMC_AD2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad2.vin3a_d2 */
+	{GPMC_AD3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad3.vin3a_d3 */
+	{GPMC_AD4, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad4.vin3a_d4 */
+	{GPMC_AD5, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_ad5.vin3a_d5 */
+	{GPMC_AD6, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad6.vin3a_d6 */
+	{GPMC_AD7, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad7.vin3a_d7 */
+	{GPMC_AD8, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_ad8.vin3a_d8 */
+	{GPMC_AD9, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad9.vin3a_d9 */
+	{GPMC_AD10, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad10.vin3a_d10 */
+	{GPMC_AD11, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad11.vin3a_d11 */
+	{GPMC_AD12, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad12.vin3a_d12 */
+	{GPMC_AD13, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad13.vin3a_d13 */
+	{GPMC_AD14, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad14.vin3a_d14 */
+	{GPMC_AD15, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_ad15.vin3a_d15 */
+	{GPMC_A0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a0.vin3a_d16 */
+	{GPMC_A1, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a1.vin3a_d17 */
+	{GPMC_A2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a2.vin3a_d18 */
+	{GPMC_A3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a3.vin3a_d19 */
+	{GPMC_A4, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a4.vin3a_d20 */
+	{GPMC_A5, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a5.vin3a_d21 */
+	{GPMC_A6, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a6.vin3a_d22 */
+	{GPMC_A7, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a7.vin3a_d23 */
+	{GPMC_A8, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a8.vin3a_hsync0 */
+	{GPMC_A9, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a9.vin3a_vsync0 */
+	{GPMC_A10, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a10.vin3a_de0 */
+	{GPMC_A11, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a11.vin3a_fld0 */
+	{GPMC_A12, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_a12.gpio2_2 */
+	{GPMC_A13, (M14 | PIN_INPUT_PULLDOWN)},	/* gpmc_a13.gpio2_3 */
+	{GPMC_A14, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_a14.gpio2_4 */
+	{GPMC_A15, (M14 | PIN_INPUT_PULLDOWN)},	/* gpmc_a15.gpio2_5 */
+	{GPMC_A16, (M14 | PIN_INPUT_PULLDOWN)},	/* gpmc_a16.gpio2_6 */
+	{GPMC_A17, (M14 | PIN_INPUT_PULLDOWN)},	/* gpmc_a17.gpio2_7 */
+	{GPMC_A18, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_a18.gpio2_8 */
+	{GPMC_A19, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a19.mmc2_dat4 */
+	{GPMC_A20, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a20.mmc2_dat5 */
+	{GPMC_A21, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a21.mmc2_dat6 */
+	{GPMC_A22, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a22.mmc2_dat7 */
+	{GPMC_A23, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a23.mmc2_clk */
+	{GPMC_A24, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a24.mmc2_dat0 */
+	{GPMC_A25, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a25.mmc2_dat1 */
+	{GPMC_A26, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a26.mmc2_dat2 */
+	{GPMC_A27, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a27.mmc2_dat3 */
+	{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_cs1.mmc2_cmd */
+	{GPMC_CS0, (M14 | PIN_INPUT_PULLDOWN)},	/* gpmc_cs0.gpio2_19 */
+	{GPMC_CS2, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_cs2.gpio2_20 */
+	{GPMC_CS3, (M2 | PIN_INPUT_PULLDOWN)},	/* gpmc_cs3.vin3a_clk0 */
+	{GPMC_CLK, (M9 | PIN_INPUT_PULLDOWN)},	/* gpmc_clk.dma_evt1 */
+	{GPMC_ADVN_ALE, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_advn_ale.gpio2_23 */
+	{GPMC_OEN_REN, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_oen_ren.gpio2_24 */
+	{GPMC_WEN, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_wen.gpio2_25 */
+	{GPMC_BEN0, (M9 | PIN_INPUT_PULLDOWN)},	/* gpmc_ben0.dma_evt3 */
+	{GPMC_BEN1, (M9 | PIN_INPUT_PULLDOWN)},	/* gpmc_ben1.dma_evt4 */
+	{GPMC_WAIT0, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_wait0.gpio2_28 */
+	{VIN1B_CLK1, (M14 | PIN_INPUT_SLEW)},	/* vin1b_clk1.gpio2_31 */
+	{VIN1A_D2, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d2.gpio3_6 */
+	{VIN1A_D3, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d3.gpio3_7 */
+	{VIN1A_D4, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d4.gpio3_8 */
+	{VIN1A_D5, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d5.gpio3_9 */
+	{VIN1A_D6, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d6.gpio3_10 */
+	{VIN1A_D7, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d7.gpio3_11 */
+	{VIN1A_D8, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d8.gpio3_12 */
+	{VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d10.gpio3_14 */
+	{VIN1A_D11, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d11.gpio3_15 */
+	{VIN1A_D12, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d12.gpio3_16 */
+	{VIN1A_D14, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d14.gpio3_18 */
+	{VIN1A_D16, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d16.gpio3_20 */
+	{VIN1A_D19, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d19.gpio3_23 */
+	{VIN1A_D20, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d20.gpio3_24 */
+	{VIN1A_D21, (M0 | PIN_INPUT_PULLDOWN)},	/* vin1a_d21.vin1a_d21 */
+	{VIN1A_D22, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d22.gpio3_26 */
+	{VIN2A_CLK0, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_clk0.gpio3_28 */
+	{VIN2A_DE0, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_de0.gpio3_29 */
+	{VIN2A_FLD0, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_fld0.gpio3_30 */
+	{VIN2A_HSYNC0, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_hsync0.pr1_uart0_cts_n */
+	{VIN2A_VSYNC0, (M11 | PIN_INPUT_PULLUP)},	/* vin2a_vsync0.pr1_uart0_rts_n */
+	{VIN2A_D0, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d0.pr1_uart0_rxd */
+	{VIN2A_D1, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d1.pr1_uart0_txd */
+	{VIN2A_D2, (M8 | PIN_INPUT_PULLDOWN)},	/* vin2a_d2.uart10_rxd */
+	{VIN2A_D3, (M8 | PIN_INPUT_PULLDOWN)},	/* vin2a_d3.uart10_txd */
+	{VIN2A_D4, (M8 | PIN_INPUT_PULLDOWN)},	/* vin2a_d4.uart10_ctsn */
+	{VIN2A_D5, (M8 | PIN_INPUT_PULLDOWN)},	/* vin2a_d5.uart10_rtsn */
+	{VIN2A_D6, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_d6.gpio4_7 */
+	{VIN2A_D7, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_d7.gpio4_8 */
+	{VIN2A_D8, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_d8.gpio4_9 */
+	{VIN2A_D9, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_d9.gpio4_10 */
+	{VIN2A_D10, (M10 | PIN_INPUT_PULLDOWN)},	/* vin2a_d10.ehrpwm2B */
+	{VIN2A_D11, (M10 | PIN_INPUT_PULLDOWN)},	/* vin2a_d11.ehrpwm2_tripzone_input */
+	{VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d12.rgmii1_txc */
+	{VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d13.rgmii1_txctl */
+	{VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d14.rgmii1_txd3 */
+	{VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d15.rgmii1_txd2 */
+	{VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d16.rgmii1_txd1 */
+	{VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d17.rgmii1_txd0 */
+	{VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d18.rgmii1_rxc */
+	{VIN2A_D19, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d19.rgmii1_rxctl */
+	{VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d20.rgmii1_rxd3 */
+	{VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d21.rgmii1_rxd2 */
+	{VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d22.rgmii1_rxd1 */
+	{VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d23.rgmii1_rxd0 */
+	{VOUT1_CLK, (M0 | PIN_OUTPUT)},		/* vout1_clk.vout1_clk */
+	{VOUT1_DE, (M0 | PIN_OUTPUT)},		/* vout1_de.vout1_de */
+	{VOUT1_FLD, (M14 | PIN_INPUT)},		/* vout1_fld.gpio4_21 */
+	{VOUT1_HSYNC, (M0 | PIN_OUTPUT)},	/* vout1_hsync.vout1_hsync */
+	{VOUT1_VSYNC, (M0 | PIN_OUTPUT)},	/* vout1_vsync.vout1_vsync */
+	{VOUT1_D0, (M0 | PIN_OUTPUT)},		/* vout1_d0.vout1_d0 */
+	{VOUT1_D1, (M0 | PIN_OUTPUT)},		/* vout1_d1.vout1_d1 */
+	{VOUT1_D2, (M0 | PIN_OUTPUT)},		/* vout1_d2.vout1_d2 */
+	{VOUT1_D3, (M0 | PIN_OUTPUT)},		/* vout1_d3.vout1_d3 */
+	{VOUT1_D4, (M0 | PIN_OUTPUT)},		/* vout1_d4.vout1_d4 */
+	{VOUT1_D5, (M0 | PIN_OUTPUT)},		/* vout1_d5.vout1_d5 */
+	{VOUT1_D6, (M0 | PIN_OUTPUT)},		/* vout1_d6.vout1_d6 */
+	{VOUT1_D7, (M0 | PIN_OUTPUT)},		/* vout1_d7.vout1_d7 */
+	{VOUT1_D8, (M0 | PIN_OUTPUT)},		/* vout1_d8.vout1_d8 */
+	{VOUT1_D9, (M0 | PIN_OUTPUT)},		/* vout1_d9.vout1_d9 */
+	{VOUT1_D10, (M0 | PIN_OUTPUT)},		/* vout1_d10.vout1_d10 */
+	{VOUT1_D11, (M0 | PIN_OUTPUT)},		/* vout1_d11.vout1_d11 */
+	{VOUT1_D12, (M0 | PIN_OUTPUT)},		/* vout1_d12.vout1_d12 */
+	{VOUT1_D13, (M0 | PIN_OUTPUT)},		/* vout1_d13.vout1_d13 */
+	{VOUT1_D14, (M0 | PIN_OUTPUT)},		/* vout1_d14.vout1_d14 */
+	{VOUT1_D15, (M0 | PIN_OUTPUT)},		/* vout1_d15.vout1_d15 */
+	{VOUT1_D16, (M0 | PIN_OUTPUT)},		/* vout1_d16.vout1_d16 */
+	{VOUT1_D17, (M0 | PIN_OUTPUT)},		/* vout1_d17.vout1_d17 */
+	{VOUT1_D18, (M0 | PIN_OUTPUT)},		/* vout1_d18.vout1_d18 */
+	{VOUT1_D19, (M0 | PIN_OUTPUT)},		/* vout1_d19.vout1_d19 */
+	{VOUT1_D20, (M0 | PIN_OUTPUT)},		/* vout1_d20.vout1_d20 */
+	{VOUT1_D21, (M0 | PIN_OUTPUT)},		/* vout1_d21.vout1_d21 */
+	{VOUT1_D22, (M0 | PIN_OUTPUT)},		/* vout1_d22.vout1_d22 */
+	{VOUT1_D23, (M0 | PIN_OUTPUT)},		/* vout1_d23.vout1_d23 */
+	{MDIO_MCLK, (M0 | PIN_INPUT_PULLUP)},	/* mdio_mclk.mdio_mclk */
+	{MDIO_D, (M0 | PIN_INPUT_PULLUP)},	/* mdio_d.mdio_d */
+	{RMII_MHZ_50_CLK, (M14 | PIN_INPUT_PULLUP)},	/* RMII_MHZ_50_CLK.gpio5_17 */
+	{UART3_RXD, (M14 | PIN_INPUT_PULLDOWN)},	/* uart3_rxd.gpio5_18 */
+	{UART3_TXD, (M14 | PIN_INPUT_PULLDOWN)},	/* uart3_txd.gpio5_19 */
+	{RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txc.rgmii0_txc */
+	{RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txctl.rgmii0_txctl */
+	{RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd3.rgmii0_txd3 */
+	{RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd2.rgmii0_txd2 */
+	{RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd1.rgmii0_txd1 */
+	{RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd0.rgmii0_txd0 */
+	{RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxc.rgmii0_rxc */
+	{RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxctl.rgmii0_rxctl */
+	{RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd3.rgmii0_rxd3 */
+	{RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd2.rgmii0_rxd2 */
+	{RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd1.rgmii0_rxd1 */
+	{RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd0.rgmii0_rxd0 */
+	{USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)},	/* usb1_drvvbus.usb1_drvvbus */
+	{USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)},	/* usb2_drvvbus.usb2_drvvbus */
+	{GPIO6_14, (M10 | PIN_INPUT_PULLUP)},	/* gpio6_14.timer1 */
+	{GPIO6_15, (M10 | PIN_INPUT_PULLUP)},	/* gpio6_15.timer2 */
+	{GPIO6_16, (M10 | PIN_INPUT_PULLUP)},	/* gpio6_16.timer3 */
+	{XREF_CLK0, (M9 | PIN_INPUT_PULLDOWN)},	/* xref_clk0.clkout2 */
+	{XREF_CLK1, (M14 | PIN_INPUT_PULLDOWN)},	/* xref_clk1.gpio6_18 */
+	{XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)},	/* xref_clk2.gpio6_19 */
+	{XREF_CLK3, (M9 | PIN_INPUT_PULLDOWN)},	/* xref_clk3.clkout3 */
+	{MCASP1_ACLKX, (M10 | PIN_INPUT_PULLUP)},	/* mcasp1_aclkx.i2c3_sda */
+	{MCASP1_FSX, (M10 | PIN_INPUT_PULLUP)},	/* mcasp1_fsx.i2c3_scl */
+	{MCASP1_ACLKR, (M10 | PIN_INPUT_PULLUP)},	/* mcasp1_aclkr.i2c4_sda */
+	{MCASP1_FSR, (M10 | PIN_INPUT_PULLUP)},	/* mcasp1_fsr.i2c4_scl */
+	{MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr0.i2c5_sda */
+	{MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr1.i2c5_scl */
+	{MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr2.gpio5_4 */
+	{MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr3.gpio5_5 */
+	{MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr4.gpio5_6 */
+	{MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr5.gpio5_7 */
+	{MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr6.gpio5_8 */
+	{MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr7.gpio5_9 */
+	{MCASP1_AXR8, (M14 | PIN_INPUT_SLEW)},	/* mcasp1_axr8.gpio5_10 */
+	{MCASP1_AXR9, (M14 | PIN_INPUT_SLEW)},	/* mcasp1_axr9.gpio5_11 */
+	{MCASP1_AXR10, (M14 | PIN_INPUT_SLEW)},	/* mcasp1_axr10.gpio5_12 */
+	{MCASP1_AXR11, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr11.gpio4_17 */
+	{MCASP1_AXR12, (M1 | PIN_INPUT_SLEW)},	/* mcasp1_axr12.mcasp7_axr0 */
+	{MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)},	/* mcasp1_axr13.mcasp7_axr1 */
+	{MCASP1_AXR14, (M1 | PIN_INPUT_SLEW)},	/* mcasp1_axr14.mcasp7_aclkx */
+	{MCASP1_AXR15, (M1 | PIN_INPUT_SLEW)},	/* mcasp1_axr15.mcasp7_fsx */
+	{MCASP2_ACLKX, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp2_aclkx.mcasp2_aclkx */
+	{MCASP2_FSX, (M0 | PIN_INPUT_SLEW)},	/* mcasp2_fsx.mcasp2_fsx */
+	{MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp2_aclkr.mcasp2_aclkr */
+	{MCASP2_FSR, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp2_fsr.mcasp2_fsr */
+	{MCASP2_AXR0, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr0.mcasp2_axr0 */
+	{MCASP2_AXR1, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr1.mcasp2_axr1 */
+	{MCASP2_AXR2, (M0 | PIN_INPUT_SLEW)},	/* mcasp2_axr2.mcasp2_axr2 */
+	{MCASP2_AXR3, (M0 | PIN_INPUT_SLEW)},	/* mcasp2_axr3.mcasp2_axr3 */
+	{MCASP2_AXR4, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr4.mcasp2_axr4 */
+	{MCASP2_AXR5, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr5.mcasp2_axr5 */
+	{MCASP2_AXR6, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr6.mcasp2_axr6 */
+	{MCASP2_AXR7, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr7.mcasp2_axr7 */
+	{MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp3_aclkx.mcasp3_aclkx */
+	{MCASP3_FSX, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp3_fsx.mcasp3_fsx */
+	{MCASP3_AXR0, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp3_axr0.mcasp3_axr0 */
+	{MCASP3_AXR1, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp3_axr1.mcasp3_axr1 */
+	{MCASP4_ACLKX, (M3 | PIN_INPUT_PULLDOWN)},	/* mcasp4_aclkx.uart8_rxd */
+	{MCASP4_FSX, (M3 | PIN_INPUT_PULLDOWN)},	/* mcasp4_fsx.uart8_txd */
+	{MCASP4_AXR0, (M3 | PIN_INPUT_PULLDOWN)},	/* mcasp4_axr0.uart8_ctsn */
+	{MCASP4_AXR1, (M3 | PIN_INPUT_PULLUP)},	/* mcasp4_axr1.uart8_rtsn */
+	{MCASP5_ACLKX, (M3 | PIN_INPUT_PULLDOWN)},	/* mcasp5_aclkx.uart9_rxd */
+	{MCASP5_FSX, (M3 | PIN_INPUT_PULLDOWN)},	/* mcasp5_fsx.uart9_txd */
+	{MCASP5_AXR0, (M3 | PIN_INPUT_PULLDOWN)},	/* mcasp5_axr0.uart9_ctsn */
+	{MCASP5_AXR1, (M3 | PIN_INPUT_PULLUP)},	/* mcasp5_axr1.uart9_rtsn */
+	{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_clk.mmc1_clk */
+	{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_cmd.mmc1_cmd */
+	{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat0.mmc1_dat0 */
+	{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat1.mmc1_dat1 */
+	{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat2.mmc1_dat2 */
+	{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat3.mmc1_dat3 */
+	{MMC1_SDCD, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_sdcd.mmc1_sdcd */
+	{MMC1_SDWP, (M14 | PIN_OUTPUT)},	/* mmc1_sdwp.gpio6_28 */
+	{GPIO6_10, (M10 | PIN_INPUT_PULLDOWN)},	/* gpio6_10.ehrpwm2A */
+	{GPIO6_11, (M14 | PIN_INPUT_PULLUP)},	/* gpio6_11.gpio6_11 */
+	{MMC3_CLK, (M0 | PIN_INPUT_PULLUP)},	/* mmc3_clk.mmc3_clk */
+	{MMC3_CMD, (M0 | PIN_INPUT_PULLUP)},	/* mmc3_cmd.mmc3_cmd */
+	{MMC3_DAT0, (M0 | PIN_INPUT_PULLUP)},	/* mmc3_dat0.mmc3_dat0 */
+	{MMC3_DAT1, (M0 | PIN_INPUT_PULLUP)},	/* mmc3_dat1.mmc3_dat1 */
+	{MMC3_DAT2, (M0 | PIN_INPUT_PULLUP)},	/* mmc3_dat2.mmc3_dat2 */
+	{MMC3_DAT3, (M0 | PIN_INPUT_PULLUP)},	/* mmc3_dat3.mmc3_dat3 */
+	{MMC3_DAT4, (M1 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat4.spi4_sclk */
+	{MMC3_DAT5, (M1 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat5.spi4_d1 */
+	{MMC3_DAT6, (M1 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat6.spi4_d0 */
+	{MMC3_DAT7, (M1 | PIN_INPUT_PULLUP)},	/* mmc3_dat7.spi4_cs0 */
+	{SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_sclk.gpio7_7 */
+	{SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_d1.gpio7_8 */
+	{SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_d0.gpio7_9 */
+	{SPI1_CS0, (M14 | PIN_OUTPUT)},		/* spi1_cs0.gpio7_10 */
+	{SPI1_CS1, (M14 | PIN_OUTPUT_PULLUP)},	/* spi1_cs1.gpio7_11 */
+	{SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_cs2.gpio7_12 */
+	{SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* spi1_cs3.hdmi1_cec */
+	{SPI2_SCLK, (M14 | PIN_INPUT_PULLDOWN)},	/* spi2_sclk.gpio7_14 */
+	{SPI2_D1, (M14 | PIN_INPUT_PULLDOWN)},	/* spi2_d1.gpio7_15 */
+	{SPI2_D0, (M14 | PIN_INPUT_PULLUP)},	/* spi2_d0.gpio7_16 */
+	{SPI2_CS0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* spi2_cs0.gpio7_17 */
+	{DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* dcan1_tx.dcan1_tx */
+	{DCAN1_RX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* dcan1_rx.dcan1_rx */
+	{UART1_RXD, (M0 | PIN_INPUT_SLEW)},	/* uart1_rxd.uart1_rxd */
+	{UART1_TXD, (M0 | PIN_INPUT_SLEW)},	/* uart1_txd.uart1_txd */
+	{UART1_CTSN, (M15 | PIN_INPUT_PULLDOWN)},	/* uart1_ctsn.Driveroff */
+	{UART2_RXD, (M15 | PIN_INPUT_PULLDOWN)},	/* N/A.Driveroff */
+	{UART2_TXD, (M15 | PIN_INPUT_PULLDOWN)},	/* uart2_txd.Driveroff */
+	{UART2_CTSN, (M2 | PIN_INPUT_SLEW)},	/* uart2_ctsn.uart3_rxd */
+	{UART2_RTSN, (M1 | PIN_INPUT_SLEW)},	/* uart2_rtsn.uart3_txd */
+	{I2C2_SDA, (M1 | PIN_INPUT)},		/* i2c2_sda.hdmi1_ddc_scl */
+	{I2C2_SCL, (M1 | PIN_INPUT)},		/* i2c2_scl.hdmi1_ddc_sda */
+	{WAKEUP0, (M0 | PIN_OUTPUT_PULLUP)},	/* Wakeup0.Wakeup0 */
+	{WAKEUP1, (M0 | PIN_OUTPUT_PULLDOWN)},	/* Wakeup1.Wakeup1 */
+	{WAKEUP2, (M0 | PIN_OUTPUT_PULLDOWN)},	/* Wakeup2.Wakeup2 */
+	{WAKEUP3, (M0 | PIN_OUTPUT_PULLUP)},	/* Wakeup3.Wakeup3 */
+	{ON_OFF, (M1 | PIN_OUTPUT_PULLUP)},	/* on_off.on_off */
+	{RTC_PORZ, (M0 | PIN_OUTPUT_PULLDOWN)},	/* rtc_porz.rtc_porz */
+	{RTCK, (M0 | PIN_INPUT_PULLDOWN)},	/* rtck.rtck */
 };
+
+const struct pad_conf_entry early_padconf[] = {
+	{UART2_CTSN, (M2 | PIN_INPUT_SLEW)},	/* uart2_ctsn.uart3_rxd */
+	{UART2_RTSN, (M1 | PIN_INPUT_SLEW)},	/* uart2_rtsn.uart3_txd */
+	{I2C1_SDA, (PIN_INPUT_PULLUP | M0)},	/* I2C1_SDA */
+	{I2C1_SCL, (PIN_INPUT_PULLUP | M0)},	/* I2C1_SCL */
+};
+
+#ifdef CONFIG_IODELAY_RECALIBRATION
+const struct iodelay_cfg_entry iodelay_cfg_array[] = {
+	{0x0114, 2980, 0},	/* CFG_GPMC_A0_IN */
+	{0x0120, 2648, 0},	/* CFG_GPMC_A10_IN */
+	{0x012C, 2918, 0},	/* CFG_GPMC_A11_IN */
+	{0x0198, 2917, 0},	/* CFG_GPMC_A1_IN */
+	{0x0204, 3156, 178},	/* CFG_GPMC_A2_IN */
+	{0x0210, 3109, 246},	/* CFG_GPMC_A3_IN */
+	{0x021C, 3142, 100},	/* CFG_GPMC_A4_IN */
+	{0x0228, 3084, 33},	/* CFG_GPMC_A5_IN */
+	{0x0234, 2778, 0},	/* CFG_GPMC_A6_IN */
+	{0x0240, 3110, 0},	/* CFG_GPMC_A7_IN */
+	{0x024C, 2874, 0},	/* CFG_GPMC_A8_IN */
+	{0x0258, 3072, 0},	/* CFG_GPMC_A9_IN */
+	{0x0264, 2466, 0},	/* CFG_GPMC_AD0_IN */
+	{0x0270, 2523, 0},	/* CFG_GPMC_AD10_IN */
+	{0x027C, 2453, 0},	/* CFG_GPMC_AD11_IN */
+	{0x0288, 2285, 0},	/* CFG_GPMC_AD12_IN */
+	{0x0294, 2206, 0},	/* CFG_GPMC_AD13_IN */
+	{0x02A0, 1898, 0},	/* CFG_GPMC_AD14_IN */
+	{0x02AC, 2473, 0},	/* CFG_GPMC_AD15_IN */
+	{0x02B8, 2307, 0},	/* CFG_GPMC_AD1_IN */
+	{0x02C4, 2691, 0},	/* CFG_GPMC_AD2_IN */
+	{0x02D0, 2384, 0},	/* CFG_GPMC_AD3_IN */
+	{0x02DC, 2462, 0},	/* CFG_GPMC_AD4_IN */
+	{0x02E8, 2335, 0},	/* CFG_GPMC_AD5_IN */
+	{0x02F4, 2370, 0},	/* CFG_GPMC_AD6_IN */
+	{0x0300, 2389, 0},	/* CFG_GPMC_AD7_IN */
+	{0x030C, 2672, 0},	/* CFG_GPMC_AD8_IN */
+	{0x0318, 2334, 0},	/* CFG_GPMC_AD9_IN */
+	{0x06F0, 480, 0},	/* CFG_RGMII0_RXC_IN */
+	{0x06FC, 111, 1641},	/* CFG_RGMII0_RXCTL_IN */
+	{0x0708, 272, 1116},	/* CFG_RGMII0_RXD0_IN */
+	{0x0714, 243, 1260},	/* CFG_RGMII0_RXD1_IN */
+	{0x0720, 0, 1614},	/* CFG_RGMII0_RXD2_IN */
+	{0x072C, 105, 1673},	/* CFG_RGMII0_RXD3_IN */
+	{0x0740, 531, 120},	/* CFG_RGMII0_TXC_OUT */
+	{0x074C, 11, 60},	/* CFG_RGMII0_TXCTL_OUT */
+	{0x0758, 7, 120},	/* CFG_RGMII0_TXD0_OUT */
+	{0x0764, 0, 0},		/* CFG_RGMII0_TXD1_OUT */
+	{0x0770, 276, 120},	/* CFG_RGMII0_TXD2_OUT */
+	{0x077C, 440, 120},	/* CFG_RGMII0_TXD3_OUT */
+	{0x0A70, 1551, 115},	/* CFG_VIN2A_D12_OUT */
+	{0x0A7C, 816, 0},	/* CFG_VIN2A_D13_OUT */
+	{0x0A88, 876, 0},	/* CFG_VIN2A_D14_OUT */
+	{0x0A94, 312, 0},	/* CFG_VIN2A_D15_OUT */
+	{0x0AA0, 58, 0},	/* CFG_VIN2A_D16_OUT */
+	{0x0AAC, 0, 0},		/* CFG_VIN2A_D17_OUT */
+	{0x0AB0, 702, 0},	/* CFG_VIN2A_D18_IN */
+	{0x0ABC, 136, 976},	/* CFG_VIN2A_D19_IN */
+	{0x0AD4, 210, 1357},	/* CFG_VIN2A_D20_IN */
+	{0x0AE0, 189, 1462},	/* CFG_VIN2A_D21_IN */
+	{0x0AEC, 232, 1278},	/* CFG_VIN2A_D22_IN */
+	{0x0AF8, 0, 1397},	/* CFG_VIN2A_D23_IN */
+};
+#endif
 #endif /* _MUX_DATA_BEAGLE_X15_H_ */

board/ti/dra7xx/evm.c

@@ -17,6 +17,7 @@
 #include <usb.h>
 #include <linux/usb/gadget.h>
 #include <asm/arch/gpio.h>
+#include <asm/arch/dra7xx_iodelay.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sata.h>
@@ -40,43 +41,6 @@ const struct omap_sysinfo sysinfo = {
 	"Board: DRA7xx\n"
 };
 
-/*
- * Adjust I/O delays on the Tx control and data lines of each MAC port. This
- * is a workaround in order to work properly with the DP83865 PHYs on the EVM.
- * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we
- * essentially need to counteract the DRA7xx internal delay, and we do this
- * by delaying the control and data lines. If not using this PHY, you probably
- * don't need to do this stuff!
- */
-static void dra7xx_adj_io_delay(const struct io_delay *io_dly)
-{
-	int i = 0;
-	u32 reg_val;
-	u32 delta;
-	u32 coarse;
-	u32 fine;
-
-	writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK);
-
-	while(io_dly[i].addr) {
-		writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK,
-		       io_dly[i].addr);
-		delta = io_dly[i].dly;
-		reg_val = readl(io_dly[i].addr) & 0x3ff;
-		coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
-		coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
-		fine = (reg_val & 0x1F) + (delta & 0x1F);
-		fine = (fine > 0x1F) ? (0x1F) : (fine);
-		reg_val = CFG_IO_DELAY_ACCESS_PATTERN |
-				CFG_IO_DELAY_LOCK_MASK |
-				((coarse << 5) | (fine));
-		writel(reg_val, io_dly[i].addr);
-		i++;
-	}
-
-	writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK);
-}
-
 /**
  * @brief board_init
  *
@@ -107,24 +71,29 @@ int board_late_init(void)
 	return 0;
 }
 
-static void do_set_mux32(u32 base,
-			 struct pad_conf_entry const *array, int size)
-{
-	int i;
-	struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
-
-	for (i = 0; i < size; i++, pad++)
-		writel(pad->val, base + pad->offset);
-}
-
 void set_muxconf_regs_essential(void)
 {
 	do_set_mux32((*ctrl)->control_padconf_core_base,
-		     core_padconf_array_essential,
-		     sizeof(core_padconf_array_essential) /
-		     sizeof(struct pad_conf_entry));
+		     early_padconf, ARRAY_SIZE(early_padconf));
 }
 
+#ifdef CONFIG_IODELAY_RECALIBRATION
+void recalibrate_iodelay(void)
+{
+	if (is_dra72x()) {
+		__recalibrate_iodelay(core_padconf_array_essential,
+				      ARRAY_SIZE(core_padconf_array_essential),
+				      iodelay_cfg_array,
+				      ARRAY_SIZE(iodelay_cfg_array));
+	} else {
+		__recalibrate_iodelay(dra74x_core_padconf_array,
+				      ARRAY_SIZE(dra74x_core_padconf_array),
+				      dra742_iodelay_cfg_array,
+				      ARRAY_SIZE(dra742_iodelay_cfg_array));
+	}
+}
+#endif
+
 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
@@ -257,19 +226,6 @@ int spl_start_uboot(void)
 #endif
 
 #ifdef CONFIG_DRIVER_TI_CPSW
-
-/* Delay value to add to calibrated value */
-#define RGMII0_TXCTL_DLY_VAL		((0x3 << 5) + 0x8)
-#define RGMII0_TXD0_DLY_VAL		((0x3 << 5) + 0x8)
-#define RGMII0_TXD1_DLY_VAL		((0x3 << 5) + 0x2)
-#define RGMII0_TXD2_DLY_VAL		((0x4 << 5) + 0x0)
-#define RGMII0_TXD3_DLY_VAL		((0x4 << 5) + 0x0)
-#define VIN2A_D13_DLY_VAL		((0x3 << 5) + 0x8)
-#define VIN2A_D17_DLY_VAL		((0x3 << 5) + 0x8)
-#define VIN2A_D16_DLY_VAL		((0x3 << 5) + 0x2)
-#define VIN2A_D15_DLY_VAL		((0x4 << 5) + 0x0)
-#define VIN2A_D14_DLY_VAL		((0x4 << 5) + 0x0)
-
 extern u32 *const omap_si_rev;
 
 static void cpsw_control(int enabled)
@@ -317,22 +273,6 @@ int board_eth_init(bd_t *bis)
 	uint8_t mac_addr[6];
 	uint32_t mac_hi, mac_lo;
 	uint32_t ctrl_val;
-	const struct io_delay io_dly[] = {
-		{CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL},
-		{CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL},
-		{CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL},
-		{CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL},
-		{CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL},
-		{CFG_VIN2A_D13, VIN2A_D13_DLY_VAL},
-		{CFG_VIN2A_D17, VIN2A_D17_DLY_VAL},
-		{CFG_VIN2A_D16, VIN2A_D16_DLY_VAL},
-		{CFG_VIN2A_D15, VIN2A_D15_DLY_VAL},
-		{CFG_VIN2A_D14, VIN2A_D14_DLY_VAL},
-		{0}
-	};
-
-	/* Adjust IO delay for RGMII tx path */
-	dra7xx_adj_io_delay(io_dly);
 
 	/* try reading mac address from efuse */
 	mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);

board/ti/dra7xx/mux_data.h

@@ -76,30 +76,30 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
 	{I2C1_SCL, (IEN | PTU | PDIS | M0)},	/* I2C1_SCL */
 	{MDIO_MCLK, (PTU | PEN | M0)},		/* MDIO_MCLK  */
 	{MDIO_D, (IEN | PTU | PEN | M0)},	/* MDIO_D  */
-	{RGMII0_TXC, (M0) },
-	{RGMII0_TXCTL, (M0) },
-	{RGMII0_TXD3, (M0) },
-	{RGMII0_TXD2, (M0) },
-	{RGMII0_TXD1, (M0) },
-	{RGMII0_TXD0, (M0) },
-	{RGMII0_RXC, (IEN | M0) },
-	{RGMII0_RXCTL, (IEN | M0) },
-	{RGMII0_RXD3, (IEN | M0) },
-	{RGMII0_RXD2, (IEN | M0) },
-	{RGMII0_RXD1, (IEN | M0) },
-	{RGMII0_RXD0, (IEN | M0) },
-	{VIN2A_D12, (M3) },
-	{VIN2A_D13, (M3) },
-	{VIN2A_D14, (M3) },
-	{VIN2A_D15, (M3) },
-	{VIN2A_D16, (M3) },
-	{VIN2A_D17, (M3) },
-	{VIN2A_D18, (IEN | M3)},
-	{VIN2A_D19, (IEN | M3)},
-	{VIN2A_D20, (IEN | M3)},
-	{VIN2A_D21, (IEN | M3)},
-	{VIN2A_D22, (IEN | M3)},
-	{VIN2A_D23, (IEN | M3)},
+	{RGMII0_TXC, (PIN_OUTPUT | MANUAL_MODE | M0) },
+	{RGMII0_TXCTL, (PIN_OUTPUT | MANUAL_MODE | M0) },
+	{RGMII0_TXD3, (PIN_OUTPUT | MANUAL_MODE | M0) },
+	{RGMII0_TXD2, (PIN_OUTPUT | MANUAL_MODE | M0) },
+	{RGMII0_TXD1, (PIN_OUTPUT | MANUAL_MODE | M0) },
+	{RGMII0_TXD0, (PIN_OUTPUT | MANUAL_MODE | M0) },
+	{RGMII0_RXC, (PIN_INPUT | MANUAL_MODE | M0) },
+	{RGMII0_RXCTL, (PIN_INPUT | MANUAL_MODE | M0) },
+	{RGMII0_RXD3, (PIN_INPUT | MANUAL_MODE | M0) },
+	{RGMII0_RXD2, (PIN_INPUT | MANUAL_MODE | M0) },
+	{RGMII0_RXD1, (PIN_INPUT | MANUAL_MODE | M0) },
+	{RGMII0_RXD0, (PIN_INPUT | MANUAL_MODE | M0) },
+	{VIN2A_D12, (PIN_OUTPUT | MANUAL_MODE | M3) },
+	{VIN2A_D13, (PIN_OUTPUT | MANUAL_MODE | M3) },
+	{VIN2A_D14, (PIN_OUTPUT | MANUAL_MODE | M3) },
+	{VIN2A_D15, (PIN_OUTPUT | MANUAL_MODE | M3) },
+	{VIN2A_D16, (PIN_OUTPUT | MANUAL_MODE | M3) },
+	{VIN2A_D17, (PIN_OUTPUT | MANUAL_MODE | M3) },
+	{VIN2A_D18, (PIN_INPUT | MANUAL_MODE | M3)},
+	{VIN2A_D19, (PIN_INPUT | MANUAL_MODE | M3)},
+	{VIN2A_D20, (PIN_INPUT | MANUAL_MODE | M3)},
+	{VIN2A_D21, (PIN_INPUT | MANUAL_MODE | M3)},
+	{VIN2A_D22, (PIN_INPUT | MANUAL_MODE | M3)},
+	{VIN2A_D23, (PIN_INPUT | MANUAL_MODE | M3)},
 #if defined(CONFIG_NAND) || defined(CONFIG_NOR)
 	/* NAND / NOR pin-mux */
 	{GPMC_AD0 , M0 | IEN | PDIS}, /* GPMC_AD0  */
@@ -141,4 +141,295 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
 	{USB2_DRVVBUS, (M0 | IEN | FSC) },
 	{SPI1_CS1, (PEN | IDIS | M14) },
 };
+
+const struct pad_conf_entry early_padconf[] = {
+#if (CONFIG_CONS_INDEX == 1)
+	{UART1_RXD, (PIN_INPUT_SLEW | M0)}, /* UART1_RXD */
+	{UART1_TXD, (PIN_INPUT_SLEW | M0)}, /* UART1_TXD */
+#elif (CONFIG_CONS_INDEX == 3)
+	{UART3_RXD, (PIN_INPUT_SLEW | M0)}, /* UART3_RXD */
+	{UART3_TXD, (PIN_INPUT_SLEW | M0)}, /* UART3_TXD */
+#endif
+	{I2C1_SDA, (PIN_INPUT | M0)},	/* I2C1_SDA */
+	{I2C1_SCL, (PIN_INPUT | M0)},	/* I2C1_SCL */
+};
+
+#ifdef CONFIG_IODELAY_RECALIBRATION
+const struct iodelay_cfg_entry iodelay_cfg_array[] = {
+	{0x6F0, 480, 0}, /* RGMMI0_RXC_IN */
+	{0x6FC, 111, 1641}, /* RGMMI0_RXCTL_IN */
+	{0x708, 272, 1116}, /* RGMMI0_RXD0_IN */
+	{0x714, 243, 1260}, /* RGMMI0_RXD1_IN */
+	{0x720, 0, 1614}, /* RGMMI0_RXD2_IN */
+	{0x72C, 105, 1673}, /* RGMMI0_RXD3_IN */
+	{0x740, 531, 120}, /* RGMMI0_TXC_OUT */
+	{0x74C, 11, 60}, /* RGMMI0_TXCTL_OUT */
+	{0x758, 7, 120}, /* RGMMI0_TXD0_OUT */
+	{0x764, 0, 0}, /* RGMMI0_TXD1_OUT */
+	{0x770, 276, 120}, /* RGMMI0_TXD2_OUT */
+	{0x77C, 440, 120}, /* RGMMI0_TXD3_OUT */
+	{0xAB0, 702, 0}, /* CFG_VIN2A_D18_IN */
+	{0xABC, 136, 976}, /* CFG_VIN2A_D19_IN */
+	{0xAD4, 210, 1357}, /* CFG_VIN2A_D20_IN */
+	{0xAE0, 189, 1462}, /* CFG_VIN2A_D21_IN */
+	{0xAEC, 232, 1278}, /* CFG_VIN2A_D22_IN */
+	{0xAF8, 0, 1397}, /* CFG_VIN2A_D23_IN */
+	{0xA70, 1551, 115}, /* CFG_VIN2A_D12_OUT */
+	{0xA7C, 816, 0}, /* CFG_VIN2A_D13_OUT */
+	{0xA88, 876, 0}, /* CFG_VIN2A_D14_OUT */
+	{0xA94, 312, 0}, /* CFG_VIN2A_D15_OUT */
+	{0xAA0, 58, 0}, /* CFG_VIN2A_D16_OUT */
+	{0xAAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
+};
+#endif
+
+const struct pad_conf_entry dra74x_core_padconf_array[] = {
+	{GPMC_AD0, (M3 | PIN_INPUT)},	/* gpmc_ad0.vout3_d0 */
+	{GPMC_AD1, (M3 | PIN_INPUT)},	/* gpmc_ad1.vout3_d1 */
+	{GPMC_AD2, (M3 | PIN_INPUT)},	/* gpmc_ad2.vout3_d2 */
+	{GPMC_AD3, (M3 | PIN_INPUT)},	/* gpmc_ad3.vout3_d3 */
+	{GPMC_AD4, (M3 | PIN_INPUT)},	/* gpmc_ad4.vout3_d4 */
+	{GPMC_AD5, (M3 | PIN_INPUT)},	/* gpmc_ad5.vout3_d5 */
+	{GPMC_AD6, (M3 | PIN_INPUT)},	/* gpmc_ad6.vout3_d6 */
+	{GPMC_AD7, (M3 | PIN_INPUT)},	/* gpmc_ad7.vout3_d7 */
+	{GPMC_AD8, (M3 | PIN_INPUT)},	/* gpmc_ad8.vout3_d8 */
+	{GPMC_AD9, (M3 | PIN_INPUT)},	/* gpmc_ad9.vout3_d9 */
+	{GPMC_AD10, (M3 | PIN_INPUT)},	/* gpmc_ad10.vout3_d10 */
+	{GPMC_AD11, (M3 | PIN_INPUT)},	/* gpmc_ad11.vout3_d11 */
+	{GPMC_AD12, (M3 | PIN_INPUT)},	/* gpmc_ad12.vout3_d12 */
+	{GPMC_AD13, (M3 | PIN_INPUT)},	/* gpmc_ad13.vout3_d13 */
+	{GPMC_AD14, (M3 | PIN_INPUT)},	/* gpmc_ad14.vout3_d14 */
+	{GPMC_AD15, (M3 | PIN_INPUT)},	/* gpmc_ad15.vout3_d15 */
+	{GPMC_A0, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a0.vout3_d16 */
+	{GPMC_A1, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a1.vout3_d17 */
+	{GPMC_A2, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a2.vout3_d18 */
+	{GPMC_A3, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a3.vout3_d19 */
+	{GPMC_A4, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a4.vout3_d20 */
+	{GPMC_A5, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a5.vout3_d21 */
+	{GPMC_A6, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a6.vout3_d22 */
+	{GPMC_A7, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a7.vout3_d23 */
+	{GPMC_A8, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a8.vout3_hsync */
+	{GPMC_A9, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a9.vout3_vsync */
+	{GPMC_A10, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a10.vout3_de */
+	{GPMC_A11, (M14 | PIN_INPUT_PULLDOWN)},	/* gpmc_a11.gpio2_1 */
+	{GPMC_A13, (M1 | PIN_INPUT_PULLDOWN)},	/* gpmc_a13.qspi1_rtclk */
+	{GPMC_A14, (M1 | PIN_INPUT_PULLDOWN)},	/* gpmc_a14.qspi1_d3 */
+	{GPMC_A15, (M1 | PIN_INPUT_PULLDOWN)},	/* gpmc_a15.qspi1_d2 */
+	{GPMC_A16, (M1 | PIN_INPUT_PULLDOWN)},	/* gpmc_a16.qspi1_d0 */
+	{GPMC_A17, (M1 | PIN_INPUT_PULLDOWN)},	/* gpmc_a17.qspi1_d1 */
+	{GPMC_A18, (M1 | PIN_INPUT_PULLDOWN)},	/* gpmc_a18.qspi1_sclk */
+	{GPMC_A19, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a19.mmc2_dat4 */
+	{GPMC_A20, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a20.mmc2_dat5 */
+	{GPMC_A21, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a21.mmc2_dat6 */
+	{GPMC_A22, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a22.mmc2_dat7 */
+	{GPMC_A23, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a23.mmc2_clk */
+	{GPMC_A24, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a24.mmc2_dat0 */
+	{GPMC_A25, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a25.mmc2_dat1 */
+	{GPMC_A26, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a26.mmc2_dat2 */
+	{GPMC_A27, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a27.mmc2_dat3 */
+	{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_cs1.mmc2_cmd */
+	{GPMC_CS2, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_cs2.qspi1_cs0 */
+	{GPMC_CS3, (M3 | PIN_INPUT_PULLUP)},	/* gpmc_cs3.vout3_clk */
+	{VIN1A_CLK0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_clk0.vin1a_clk0 */
+	{VIN1A_DE0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_de0.vin1a_de0 */
+	{VIN1A_FLD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_fld0.vin1a_fld0 */
+	{VIN1A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_hsync0.vin1a_hsync0 */
+	{VIN1A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_vsync0.vin1a_vsync0 */
+	{VIN1A_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d0.vin1a_d0 */
+	{VIN1A_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d1.vin1a_d1 */
+	{VIN1A_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d2.vin1a_d2 */
+	{VIN1A_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d3.vin1a_d3 */
+	{VIN1A_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d4.vin1a_d4 */
+	{VIN1A_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d5.vin1a_d5 */
+	{VIN1A_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d6.vin1a_d6 */
+	{VIN1A_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d7.vin1a_d7 */
+	{VIN1A_D8, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d8.vin1a_d8 */
+	{VIN1A_D9, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d9.vin1a_d9 */
+	{VIN1A_D10, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d10.vin1a_d10 */
+	{VIN1A_D11, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d11.vin1a_d11 */
+	{VIN1A_D12, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d12.vin1a_d12 */
+	{VIN1A_D13, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d13.vin1a_d13 */
+	{VIN1A_D14, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d14.vin1a_d14 */
+	{VIN1A_D15, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d15.vin1a_d15 */
+	{VIN1A_D16, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d16.vin1a_d16 */
+	{VIN1A_D17, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d17.vin1a_d17 */
+	{VIN1A_D18, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d18.vin1a_d18 */
+	{VIN1A_D19, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d19.vin1a_d19 */
+	{VIN1A_D20, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d20.vin1a_d20 */
+	{VIN1A_D21, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d21.vin1a_d21 */
+	{VIN1A_D22, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d22.vin1a_d22 */
+	{VIN1A_D23, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d23.vin1a_d23 */
+	{VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d12.rgmii1_txc */
+	{VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d13.rgmii1_txctl */
+	{VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d14.rgmii1_txd3 */
+	{VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d15.rgmii1_txd2 */
+	{VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d16.rgmii1_txd1 */
+	{VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d17.rgmii1_txd0 */
+	{VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d18.rgmii1_rxc */
+	{VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d19.rgmii1_rxctl */
+	{VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d20.rgmii1_rxd3 */
+	{VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d21.rgmii1_rxd2 */
+	{VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d22.rgmii1_rxd1 */
+	{VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d23.rgmii1_rxd0 */
+	{VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_clk.vout1_clk */
+	{VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_de.vout1_de */
+	{VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_hsync.vout1_hsync */
+	{VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_vsync.vout1_vsync */
+	{VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d0.vout1_d0 */
+	{VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d1.vout1_d1 */
+	{VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d2.vout1_d2 */
+	{VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d3.vout1_d3 */
+	{VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d4.vout1_d4 */
+	{VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d5.vout1_d5 */
+	{VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d6.vout1_d6 */
+	{VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d7.vout1_d7 */
+	{VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d8.vout1_d8 */
+	{VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d9.vout1_d9 */
+	{VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d10.vout1_d10 */
+	{VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d11.vout1_d11 */
+	{VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d12.vout1_d12 */
+	{VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d13.vout1_d13 */
+	{VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d14.vout1_d14 */
+	{VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d15.vout1_d15 */
+	{VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d16.vout1_d16 */
+	{VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d17.vout1_d17 */
+	{VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d18.vout1_d18 */
+	{VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d19.vout1_d19 */
+	{VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d20.vout1_d20 */
+	{VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d21.vout1_d21 */
+	{VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d22.vout1_d22 */
+	{VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d23.vout1_d23 */
+	{MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mdio_mclk.mdio_mclk */
+	{MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mdio_d.mdio_d */
+	{RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txc.rgmii0_txc */
+	{RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txctl.rgmii0_txctl */
+	{RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd3.rgmii0_txd3 */
+	{RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd2.rgmii0_txd2 */
+	{RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd1.rgmii0_txd1 */
+	{RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd0.rgmii0_txd0 */
+	{RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxc.rgmii0_rxc */
+	{RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxctl.rgmii0_rxctl */
+	{RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxd3.rgmii0_rxd3 */
+	{RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxd2.rgmii0_rxd2 */
+	{RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxd1.rgmii0_rxd1 */
+	{RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxd0.rgmii0_rxd0 */
+	{USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)},	/* usb1_drvvbus.usb1_drvvbus */
+	{USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)},	/* usb2_drvvbus.usb2_drvvbus */
+	{GPIO6_14, (M9 | PIN_INPUT_PULLUP)},	/* gpio6_14.i2c3_sda */
+	{GPIO6_15, (M9 | PIN_INPUT_PULLUP)},	/* gpio6_15.i2c3_scl */
+	{GPIO6_16, (M14 | PIN_INPUT_PULLUP)},	/* gpio6_16.gpio6_16 */
+	{XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)},	/* xref_clk2.atl_clk2 */
+	{MCASP1_ACLKX, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp1_aclkx.mcasp1_aclkx */
+	{MCASP1_FSX, (M0 | PIN_INPUT_SLEW)},	/* mcasp1_fsx.mcasp1_fsx */
+	{MCASP1_AXR0, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE15)},	/* mcasp1_axr0.mcasp1_axr0 */
+	{MCASP1_AXR1, (M0 | PIN_INPUT_SLEW)},	/* mcasp1_axr1.mcasp1_axr1 */
+	{MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr2.gpio5_4 */
+	{MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr3.gpio5_5 */
+	{MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr4.gpio5_6 */
+	{MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr5.gpio5_7 */
+	{MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr6.gpio5_8 */
+	{MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr7.gpio5_9 */
+	{MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr12.mcasp7_axr0 */
+	{MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)},	/* mcasp1_axr13.mcasp7_axr1 */
+	{MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr14.mcasp7_aclkx */
+	{MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr15.mcasp7_fsx */
+	{MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp2_aclkr.mcasp2_aclkr */
+	{MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp3_aclkx.mcasp3_aclkx */
+	{MCASP3_FSX, (M0 | PIN_INPUT_SLEW)},	/* mcasp3_fsx.mcasp3_fsx */
+	{MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)},	/* mcasp3_axr0.mcasp3_axr0 */
+	{MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)},	/* mcasp3_axr1.mcasp3_axr1 */
+	{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_clk.mmc1_clk */
+	{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_cmd.mmc1_cmd */
+	{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat0.mmc1_dat0 */
+	{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat1.mmc1_dat1 */
+	{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat2.mmc1_dat2 */
+	{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat3.mmc1_dat3 */
+	{MMC1_SDCD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mmc1_sdcd.mmc1_sdcd */
+	{MMC1_SDWP, (M14 | PIN_INPUT_SLEW)},	/* mmc1_sdwp.gpio6_28 */
+	{GPIO6_11, (M14 | PIN_INPUT_PULLUP)},	/* gpio6_11.gpio6_11 */
+	{SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)},	/* spi1_sclk.spi1_sclk */
+	{SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)},	/* spi1_d1.spi1_d1 */
+	{SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)},	/* spi1_d0.spi1_d0 */
+	{SPI1_CS0, (M0 | PIN_INPUT_PULLUP)},	/* spi1_cs0.spi1_cs0 */
+	{SPI1_CS1, (M14 | PIN_OUTPUT)},		/* spi1_cs1.gpio7_11 */
+	{SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_cs2.gpio7_12 */
+	{SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* spi1_cs3.hdmi1_cec */
+	{SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)},	/* spi2_sclk.uart3_rxd */
+	{SPI2_D1, (M1 | PIN_INPUT_SLEW)},	/* spi2_d1.uart3_txd */
+	{SPI2_D0, (M1 | PIN_INPUT_SLEW)},	/* spi2_d0.uart3_ctsn */
+	{SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* spi2_cs0.uart3_rtsn */
+	{DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* dcan1_tx.dcan1_tx */
+	{DCAN1_RX, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* dcan1_rx.gpio1_15 */
+	{UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* uart1_rxd.uart1_rxd */
+	{UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* uart1_txd.uart1_txd */
+	{UART1_CTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart1_ctsn.mmc4_clk */
+	{UART1_RTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart1_rtsn.mmc4_cmd */
+	{UART2_RXD, (M3 | PIN_INPUT_PULLUP)},	/* N/A.mmc4_dat0 */
+	{UART2_TXD, (M3 | PIN_INPUT_PULLUP)},	/* uart2_txd.mmc4_dat1 */
+	{UART2_CTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart2_ctsn.mmc4_dat2 */
+	{UART2_RTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart2_rtsn.mmc4_dat3 */
+	{I2C2_SDA, (M0 | PIN_INPUT_PULLUP)},	/* i2c2_sda.i2c2_sda */
+	{I2C2_SCL, (M0 | PIN_INPUT_PULLUP)},	/* i2c2_scl.i2c2_scl */
+	{WAKEUP0, (M1 | PIN_OUTPUT)},	/* Wakeup0.dcan1_rx */
+	{WAKEUP2, (M14 | PIN_OUTPUT)},	/* Wakeup2.gpio1_2 */
+};
+
+#ifdef CONFIG_IODELAY_RECALIBRATION
+const struct iodelay_cfg_entry dra742_iodelay_cfg_array[] = {
+	{0x06F0, 480, 0},	/* CFG_RGMII0_RXC_IN */
+	{0x06FC, 111, 1641},	/* CFG_RGMII0_RXCTL_IN */
+	{0x0708, 272, 1116},	/* CFG_RGMII0_RXD0_IN */
+	{0x0714, 243, 1260},	/* CFG_RGMII0_RXD1_IN */
+	{0x0720, 0, 1614},	/* CFG_RGMII0_RXD2_IN */
+	{0x072C, 105, 1673},	/* CFG_RGMII0_RXD3_IN */
+	{0x0740, 0, 0},		/* CFG_RGMII0_TXC_OUT */
+	{0x074C, 1560, 120},	/* CFG_RGMII0_TXCTL_OUT */
+	{0x0758, 1570, 120},	/* CFG_RGMII0_TXD0_OUT */
+	{0x0764, 1500, 120},	/* CFG_RGMII0_TXD1_OUT */
+	{0x0770, 1775, 120},	/* CFG_RGMII0_TXD2_OUT */
+	{0x077C, 1875, 120},	/* CFG_RGMII0_TXD3_OUT */
+	{0x08D0, 0, 0},		/* CFG_VIN1A_CLK0_IN */
+	{0x08DC, 2600, 0},	/* CFG_VIN1A_D0_IN */
+	{0x08E8, 2652, 46},	/* CFG_VIN1A_D10_IN */
+	{0x08F4, 2541, 0},	/* CFG_VIN1A_D11_IN */
+	{0x0900, 2603, 574},	/* CFG_VIN1A_D12_IN */
+	{0x090C, 2548, 443},	/* CFG_VIN1A_D13_IN */
+	{0x0918, 2624, 598},	/* CFG_VIN1A_D14_IN */
+	{0x0924, 2535, 1027},	/* CFG_VIN1A_D15_IN */
+	{0x0930, 2526, 818},	/* CFG_VIN1A_D16_IN */
+	{0x093C, 2623, 797},	/* CFG_VIN1A_D17_IN */
+	{0x0948, 2578, 888},	/* CFG_VIN1A_D18_IN */
+	{0x0954, 2574, 1008},	/* CFG_VIN1A_D19_IN */
+	{0x0960, 2527, 123},	/* CFG_VIN1A_D1_IN */
+	{0x096C, 2577, 737},	/* CFG_VIN1A_D20_IN */
+	{0x0978, 2627, 616},	/* CFG_VIN1A_D21_IN */
+	{0x0984, 2573, 777},	/* CFG_VIN1A_D22_IN */
+	{0x0990, 2730, 67},	/* CFG_VIN1A_D23_IN */
+	{0x099C, 2509, 303},	/* CFG_VIN1A_D2_IN */
+	{0x09A8, 2494, 267},	/* CFG_VIN1A_D3_IN */
+	{0x09B4, 2474, 0},	/* CFG_VIN1A_D4_IN */
+	{0x09C0, 2556, 181},	/* CFG_VIN1A_D5_IN */
+	{0x09CC, 2516, 195},	/* CFG_VIN1A_D6_IN */
+	{0x09D8, 2589, 210},	/* CFG_VIN1A_D7_IN */
+	{0x09E4, 2624, 75},	/* CFG_VIN1A_D8_IN */
+	{0x09F0, 2704, 14},	/* CFG_VIN1A_D9_IN */
+	{0x09FC, 2469, 55},	/* CFG_VIN1A_DE0_IN */
+	{0x0A08, 2557, 264},	/* CFG_VIN1A_FLD0_IN */
+	{0x0A14, 2465, 269},	/* CFG_VIN1A_HSYNC0_IN */
+	{0x0A20, 2411, 348},	/* CFG_VIN1A_VSYNC0_IN */
+	{0x0A70, 150, 0},	/* CFG_VIN2A_D12_OUT */
+	{0x0A7C, 1500, 0},	/* CFG_VIN2A_D13_OUT */
+	{0x0A88, 1600, 0},	/* CFG_VIN2A_D14_OUT */
+	{0x0A94, 900, 0},	/* CFG_VIN2A_D15_OUT */
+	{0x0AA0, 680, 0},	/* CFG_VIN2A_D16_OUT */
+	{0x0AAC, 500, 0},	/* CFG_VIN2A_D17_OUT */
+	{0x0AB0, 702, 0},	/* CFG_VIN2A_D18_IN */
+	{0x0ABC, 136, 976},	/* CFG_VIN2A_D19_IN */
+	{0x0AD4, 210, 1357},	/* CFG_VIN2A_D20_IN */
+	{0x0AE0, 189, 1462},	/* CFG_VIN2A_D21_IN */
+	{0x0AEC, 232, 1278},	/* CFG_VIN2A_D22_IN */
+	{0x0AF8, 0, 1397},	/* CFG_VIN2A_D23_IN */
+};
+#endif
+
 #endif /* _MUX_DATA_DRA7XX_H_ */

board/vscom/baltos/Kconfig

@@ -0,0 +1,24 @@
+if TARGET_AM335X_BALTOS
+
+config SYS_BOARD
+	default "baltos"
+
+config SYS_VENDOR
+	default "vscom"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "baltos"
+
+config CONS_INDEX
+	int "UART used for console"
+	range 1 6
+	default 1
+	help
+	  The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
+	  in documentation, etc) available to it.  Depending on your specific
+	  board you may want something other than UART0.
+
+endif

board/vscom/baltos/Makefile

@@ -0,0 +1,13 @@
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+obj-y	:= mux.o
+endif
+
+obj-y	+= board.o

board/vscom/baltos/README

@@ -0,0 +1 @@
+BSP for VScom OnRISC Balios family devices, like Balios iR 5221.

board/vscom/baltos/board.c

@@ -0,0 +1,474 @@
+/*
+ * board.c
+ *
+ * Board functions for TI AM335X based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <power/tps65217.h>
+#include <power/tps65910.h>
+#include <environment.h>
+#include <watchdog.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPIO that controls power to DDR on EVM-SK */
+#define GPIO_DDR_VTT_EN		7
+#define DIP_S1			44
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+static int baltos_set_console(void)
+{
+	int val, i, dips = 0;
+	char buf[7];
+
+	for (i = 0; i < 4; i++) {
+		sprintf(buf, "dip_s%d", i + 1);
+
+		if (gpio_request(DIP_S1 + i, buf)) {
+			printf("failed to export GPIO %d\n", DIP_S1 + i);
+			return 0;
+		}
+
+		if (gpio_direction_input(DIP_S1 + i)) {
+			printf("failed to set GPIO %d direction\n", DIP_S1 + i);
+			return 0;
+		}
+
+		val = gpio_get_value(DIP_S1 + i);
+		dips |= val << i;
+	}
+
+	printf("DIPs: 0x%1x\n", (~dips) & 0xf);
+
+	if ((dips & 0xf) == 0xe)
+		setenv("console", "ttyUSB0,115200n8");
+
+	return 0;
+}
+
+static int read_eeprom(BSP_VS_HWPARAM *header)
+{
+	i2c_set_bus_num(1);
+
+	/* Check if baseboard eeprom is available */
+	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
+		puts("Could not probe the EEPROM; something fundamentally "
+			"wrong on the I2C bus.\n");
+		return -ENODEV;
+	}
+
+	/* read the eeprom using i2c */
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
+		     sizeof(BSP_VS_HWPARAM))) {
+		puts("Could not read the EEPROM; something fundamentally"
+			" wrong on the I2C bus.\n");
+		return -EIO;
+	}
+
+	if (header->Magic != 0xDEADBEEF) {
+
+		printf("Incorrect magic number (0x%x) in EEPROM\n",
+				header->Magic);
+
+		/* fill default values */
+		header->SystemId = 211;
+		header->MAC1[0] = 0x00;
+		header->MAC1[1] = 0x00;
+		header->MAC1[2] = 0x00;
+		header->MAC1[3] = 0x00;
+		header->MAC1[4] = 0x00;
+		header->MAC1[5] = 0x01;
+
+		header->MAC2[0] = 0x00;
+		header->MAC2[1] = 0x00;
+		header->MAC2[2] = 0x00;
+		header->MAC2[3] = 0x00;
+		header->MAC2[4] = 0x00;
+		header->MAC2[5] = 0x02;
+
+		header->MAC3[0] = 0x00;
+		header->MAC3[1] = 0x00;
+		header->MAC3[2] = 0x00;
+		header->MAC3[3] = 0x00;
+		header->MAC3[4] = 0x00;
+		header->MAC3[5] = 0x03;
+	}
+
+	return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
+
+static const struct ddr_data ddr3_baltos_data = {
+	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
+	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_baltos_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_baltos_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	return (serial_tstc() && serial_getc() == 'c');
+}
+#endif
+
+#define OSC	(V_OSCK/1000000)
+const struct dpll_params dpll_ddr = {
+		266, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_evm_sk = {
+		303, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_baltos = {
+		400, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+	int mpu_vdd;
+	int sil_rev;
+
+	/* Get the frequency */
+	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+
+	/*
+	 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
+	 * MPU frequencies we support we use a CORE voltage of
+	 * 1.1375V.  For MPU voltage we need to switch based on
+	 * the frequency we are running at.
+	 */
+	i2c_set_bus_num(1);
+
+	if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) {
+		puts("i2c: cannot access TPS65910\n");
+		return;
+	}
+
+	/*
+	 * Depending on MPU clock and PG we will need a different
+	 * VDD to drive at that speed.
+	 */
+	sil_rev = readl(&cdev->deviceid) >> 28;
+	mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
+					      dpll_mpu_opp100.m);
+
+	/* Tell the TPS65910 to use i2c */
+	tps65910_set_i2c_control();
+
+	/* First update MPU voltage. */
+	if (tps65910_voltage_update(MPU, mpu_vdd))
+		return;
+
+	/* Second, update the CORE voltage. */
+	if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
+		return;
+
+	/* Set CORE Frequencies to OPP100 */
+	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+	/* Set MPU Frequency to what we detected now that voltages are set */
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+
+	writel(0x000010ff, PRM_DEVICE_INST + 4);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	enable_i2c1_pin_mux();
+	i2c_set_bus_num(1);
+
+	return &dpll_ddr_baltos;
+}
+
+void set_uart_mux_conf(void)
+{
+	enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_board_pin_mux();
+}
+
+const struct ctrl_ioregs ioregs_baltos = {
+	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+void sdram_init(void)
+{
+	gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
+	gpio_direction_output(GPIO_DDR_VTT_EN, 1);
+
+	config_ddr(400, &ioregs_baltos,
+		   &ddr3_baltos_data,
+		   &ddr3_baltos_cmd_ctrl_data,
+		   &ddr3_baltos_emif_reg_data, 0);
+}
+#endif
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+	hw_watchdog_init();
+#endif
+
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
+	gpmc_init();
+#endif
+	return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	int node, ret;
+	unsigned char mac_addr[6];
+	BSP_VS_HWPARAM header;
+
+	/* get production data */
+	if (read_eeprom(&header))
+		return 0;
+
+	/* setup MAC1 */
+	mac_addr[0] = header.MAC1[0];
+	mac_addr[1] = header.MAC1[1];
+	mac_addr[2] = header.MAC1[2];
+	mac_addr[3] = header.MAC1[3];
+	mac_addr[4] = header.MAC1[4];
+	mac_addr[5] = header.MAC1[5];
+
+
+	node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100200");
+	if (node < 0) {
+		printf("no /soc/fman/ethernet path offset\n");
+		return -ENODEV;
+	}
+
+	ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
+	if (ret) {
+		printf("error setting local-mac-address property\n");
+		return -ENODEV;
+	}
+
+	/* setup MAC2 */
+	mac_addr[0] = header.MAC2[0];
+	mac_addr[1] = header.MAC2[1];
+	mac_addr[2] = header.MAC2[2];
+	mac_addr[3] = header.MAC2[3];
+	mac_addr[4] = header.MAC2[4];
+	mac_addr[5] = header.MAC2[5];
+
+	node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100300");
+	if (node < 0) {
+		printf("no /soc/fman/ethernet path offset\n");
+		return -ENODEV;
+	}
+
+	ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
+	if (ret) {
+		printf("error setting local-mac-address property\n");
+		return -ENODEV;
+	}
+
+	printf("\nFDT was successfully setup\n");
+
+	return 0;
+}
+
+static struct module_pin_mux dip_pin_mux[] = {
+	{OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )},	/* GPIO1_12 */
+	{OFFSET(gpmc_ad13), (MODE(7)  | RXACTIVE )},	/* GPIO1_13 */
+	{OFFSET(gpmc_ad14), (MODE(7)  | RXACTIVE )},	/* GPIO1_14 */
+	{OFFSET(gpmc_ad15), (MODE(7)  | RXACTIVE )},	/* GPIO1_15 */
+	{-1},
+};
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	BSP_VS_HWPARAM header;
+	char model[4];
+
+	/* get production data */
+	if (read_eeprom(&header)) {
+		sprintf(model, "211");
+	} else {
+		sprintf(model, "%d", header.SystemId);
+		if (header.SystemId == 215) {
+			configure_module_pin_mux(dip_pin_mux);
+			baltos_set_console();
+		}
+	}
+	setenv("board_name", model);
+#endif
+
+	return 0;
+}
+#endif
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_addr	= 0,
+	},
+	{
+		.slave_reg_ofs	= 0x308,
+		.sliver_reg_ofs	= 0xdc0,
+		.phy_addr	= 7,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 2,
+	.slave_data		= cpsw_slaves,
+	.active_slave		= 1,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+#endif
+
+#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
+		&& defined(CONFIG_SPL_BUILD)) || \
+	((defined(CONFIG_DRIVER_TI_CPSW) || \
+	  defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
+	 !defined(CONFIG_SPL_BUILD))
+int board_eth_init(bd_t *bis)
+{
+	int rv, n = 0;
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+	__maybe_unused struct am335x_baseboard_id header;
+
+	/*
+	 * Note here that we're using CPSW1 since that has a 1Gbit PHY while
+	 * CSPW0 has a 100Mbit PHY.
+	 *
+	 * On product, CPSW1 maps to port labeled WAN.
+	 */
+
+	/* try reading mac address from efuse */
+	mac_lo = readl(&cdev->macid1l);
+	mac_hi = readl(&cdev->macid1h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+	if (!getenv("ethaddr")) {
+		printf("<ethaddr> not set. Validating first E-fuse MAC\n");
+
+		if (is_valid_ethaddr(mac_addr))
+			eth_setenv_enetaddr("ethaddr", mac_addr);
+	}
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+	writel((GMII1_SEL_RMII | GMII2_SEL_RGMII | RGMII2_IDMODE), &cdev->miisel);
+	cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII;
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+	else
+		n += rv;
+#endif
+
+	/*
+	 *
+	 * CPSW RGMII Internal Delay Mode is not supported in all PVT
+	 * operating points.  So we must set the TX clock delay feature
+	 * in the AR8051 PHY.  Since we only support a single ethernet
+	 * device in U-Boot, we only do this for the first instance.
+	 */
+#define AR8051_PHY_DEBUG_ADDR_REG	0x1d
+#define AR8051_PHY_DEBUG_DATA_REG	0x1e
+#define AR8051_DEBUG_RGMII_CLK_DLY_REG	0x5
+#define AR8051_RGMII_TX_CLK_DLY		0x100
+	const char *devname;
+	devname = miiphy_get_current_dev();
+
+	miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_ADDR_REG,
+			AR8051_DEBUG_RGMII_CLK_DLY_REG);
+	miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_DATA_REG,
+			AR8051_RGMII_TX_CLK_DLY);
+#endif
+	return n;
+}
+#endif

board/vscom/baltos/board.h

@@ -0,0 +1,90 @@
+/*
+ * board.h
+ *
+ * TI AM335x boards information header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * TI AM335x parts define a system EEPROM that defines certain sub-fields.
+ * We use these fields to in turn see what board we are on, and what
+ * that might require us to set or not set.
+ */
+#define HDR_NO_OF_MAC_ADDR	3
+#define HDR_ETH_ALEN		6
+#define HDR_NAME_LEN		8
+
+struct am335x_baseboard_id {
+	unsigned int  magic;
+	char name[HDR_NAME_LEN];
+	char version[4];
+	char serial[12];
+	char config[32];
+	char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
+};
+
+typedef struct _BSP_VS_HWPARAM    // v1.0
+{
+	uint32_t Magic;
+	uint32_t HwRev;
+	uint32_t SerialNumber;
+	char PrdDate[11];    // as a string ie. "01.01.2006"
+	uint16_t SystemId;
+	uint8_t MAC1[6];        // internal EMAC
+	uint8_t MAC2[6];        // SMSC9514
+	uint8_t MAC3[6];        // WL1271 WLAN
+} __attribute__ ((packed)) BSP_VS_HWPARAM;
+
+static inline int board_is_bone(struct am335x_baseboard_id *header)
+{
+	return !strncmp(header->name, "A335BONE", HDR_NAME_LEN);
+}
+
+static inline int board_is_bone_lt(struct am335x_baseboard_id *header)
+{
+	return !strncmp(header->name, "A335BNLT", HDR_NAME_LEN);
+}
+
+static inline int board_is_evm_sk(struct am335x_baseboard_id *header)
+{
+	return !strncmp("A335X_SK", header->name, HDR_NAME_LEN);
+}
+
+static inline int board_is_idk(struct am335x_baseboard_id *header)
+{
+	return !strncmp(header->config, "SKU#02", 6);
+}
+
+static inline int board_is_gp_evm(struct am335x_baseboard_id *header)
+{
+	return !strncmp("A33515BB", header->name, HDR_NAME_LEN);
+}
+
+static inline int board_is_evm_15_or_later(struct am335x_baseboard_id *header)
+{
+	return (board_is_gp_evm(header) &&
+		strncmp("1.5", header->version, 3) <= 0);
+}
+
+/*
+ * We have three pin mux functions that must exist.  We must be able to enable
+ * uart0, for initial output and i2c0 to read the main EEPROM.  We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_uart1_pin_mux(void);
+void enable_uart2_pin_mux(void);
+void enable_uart3_pin_mux(void);
+void enable_uart4_pin_mux(void);
+void enable_uart5_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_i2c1_pin_mux(void);
+void enable_board_pin_mux(void);
+#endif

board/vscom/baltos/mux.c

@@ -0,0 +1,194 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart1_pin_mux[] = {
+	{OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART1_RXD */
+	{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},		/* UART1_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart2_pin_mux[] = {
+	{OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)},	/* UART2_RXD */
+	{OFFSET(spi0_d0), (MODE(1) | PULLUDEN)},		/* UART2_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart3_pin_mux[] = {
+	{OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)},	/* UART3_RXD */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)},	/* UART3_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart4_pin_mux[] = {
+	{OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)},	/* UART4_RXD */
+	{OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)},		/* UART4_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart5_pin_mux[] = {
+	{OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)},	/* UART5_RXD */
+	{OFFSET(lcd_data8), (MODE(4) | PULLUDEN)},		/* UART5_TXD */
+	{-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
+	//{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},	/* MMC0_CD */
+	{-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+	{-1},
+};
+
+static struct module_pin_mux i2c1_pin_mux[] = {
+	{OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)},	/* I2C_DATA */
+	{OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)},	/* I2C_SCLK */
+	{-1},
+};
+
+static struct module_pin_mux gpio0_7_pin_mux[] = {
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)},	/* GPIO0_7 */
+	{-1},
+};
+
+static struct module_pin_mux rmii1_pin_mux[] = {
+	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},			/* RGMII1_TCTL */
+	{OFFSET(mii1_txen), MODE(1)},			/* RGMII1_TCTL */
+	{OFFSET(mii1_txd1), MODE(1)},			/* RGMII1_TCTL */
+	{OFFSET(mii1_txd0), MODE(1)},			/* RGMII1_TCTL */
+	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},			/* RGMII1_TCTL */
+	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},			/* RGMII1_TCTL */
+	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},			/* RGMII1_TCTL */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+static struct module_pin_mux rgmii2_pin_mux[] = {
+	{OFFSET(gpmc_a0), MODE(2)},			/* RGMII1_TCTL */
+	{OFFSET(gpmc_a1), MODE(2) | RXACTIVE},	/* RGMII1_RCTL */
+	{OFFSET(gpmc_a2), MODE(2)},			/* RGMII1_TD3 */
+	{OFFSET(gpmc_a3), MODE(2)},			/* RGMII1_TD2 */
+	{OFFSET(gpmc_a4), MODE(2)},			/* RGMII1_TD1 */
+	{OFFSET(gpmc_a5), MODE(2)},			/* RGMII1_TD0 */
+	{OFFSET(gpmc_a6), MODE(2)},			/* RGMII1_TCLK */
+	{OFFSET(gpmc_a7), MODE(2) | RXACTIVE},	/* RGMII1_RCLK */
+	{OFFSET(gpmc_a8), MODE(2) | RXACTIVE},	/* RGMII1_RD3 */
+	{OFFSET(gpmc_a9), MODE(2) | RXACTIVE},	/* RGMII1_RD2 */
+	{OFFSET(gpmc_a10), MODE(2) | RXACTIVE},	/* RGMII1_RD1 */
+	{OFFSET(gpmc_a11), MODE(2) | RXACTIVE},	/* RGMII1_RD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
+	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
+	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
+	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
+	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
+	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
+	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
+	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
+	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
+	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},	/* NAND_CS0 */
+	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
+	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
+	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_uart1_pin_mux(void)
+{
+	configure_module_pin_mux(uart1_pin_mux);
+}
+
+void enable_uart2_pin_mux(void)
+{
+	configure_module_pin_mux(uart2_pin_mux);
+}
+
+void enable_uart3_pin_mux(void)
+{
+	configure_module_pin_mux(uart3_pin_mux);
+}
+
+void enable_uart4_pin_mux(void)
+{
+	configure_module_pin_mux(uart4_pin_mux);
+}
+
+void enable_uart5_pin_mux(void)
+{
+	configure_module_pin_mux(uart5_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_i2c1_pin_mux(void)
+{
+	configure_module_pin_mux(i2c1_pin_mux);
+}
+
+void enable_board_pin_mux()
+{
+	/* Baltos */
+	configure_module_pin_mux(i2c1_pin_mux);
+	configure_module_pin_mux(gpio0_7_pin_mux);
+	configure_module_pin_mux(rgmii2_pin_mux);
+	configure_module_pin_mux(rmii1_pin_mux);
+	configure_module_pin_mux(mmc0_pin_mux);
+
+#if defined(CONFIG_NAND)
+	configure_module_pin_mux(nand_pin_mux);
+#endif
+}

board/vscom/baltos/u-boot.lds

@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		*(.__image_copy_start)
+		*(.vectors)
+		CPUDIR/start.o (.text*)
+		board/vscom/baltos/built-in.o (.text*)
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(4);
+
+	. = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(4);
+
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
+
+	.rel.dyn : {
+		*(.rel*)
+	}
+
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
+	}
+
+	.hash : { *(.hash*) }
+
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
+
+	/*
+	 * Deprecated: this MMU section is used by pxa at present but
+	 * should not be used by new boards/CPUs.
+	 */
+	. = ALIGN(4096);
+	.mmutable : {
+		*(.mmutable)
+	}
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+	.bss_start __rel_dyn_start (OVERLAY) : {
+		KEEP(*(.__bss_start));
+		__bss_base = .;
+	}
+
+	.bss __bss_base (OVERLAY) : {
+		*(.bss*)
+		 . = ALIGN(4);
+		 __bss_limit = .;
+	}
+
+	.bss_end __bss_limit (OVERLAY) : {
+		KEEP(*(.__bss_end));
+	}
+
+	.dynsym _image_binary_end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.gnu.hash : { *(.gnu.hash) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
+}