Prepare v2015.07

Signed-off-by: Tom Rini <trini@konsulko.com>

Makefile

@@ -1,7 +1,7 @@
 VERSION = 2015
 PATCHLEVEL = 07
 SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION =
 NAME =
 
 # *DOCUMENTATION*
@@ -565,6 +565,7 @@ KBUILD_CFLAGS += -DBUILD_TAG='"$(BUILD_TAG)"'
 endif
 
 KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector)
+KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks)
 
 KBUILD_CFLAGS	+= -g
 # $(KBUILD_AFLAGS) sets -g, which causes gcc to pass a suitable -g<format>

README

@@ -1048,9 +1048,7 @@ The following options need to be configured:
 		Monitor commands can be included or excluded
 		from the build by using the #include files
 		<config_cmd_all.h> and #undef'ing unwanted
-		commands, or using <config_cmd_default.h>
-		and augmenting with additional #define's
-		for wanted commands.
+		commands, or adding #define's for wanted commands.
 
 		The default command configuration includes all commands
 		except those marked below with a "*".
@@ -3037,6 +3035,19 @@ CBFS (Coreboot Filesystem) support
 		this is instead controlled by the value of
 		/config/load-environment.
 
+- Parallel Flash support:
+		CONFIG_SYS_NO_FLASH
+
+		Traditionally U-boot was run on systems with parallel NOR
+		flash. This option is used to disable support for parallel NOR
+		flash. This option should be defined if the board does not have
+		parallel flash.
+
+		If this option is not defined one of the generic flash drivers
+		(e.g.  CONFIG_FLASH_CFI_DRIVER or CONFIG_ST_SMI) must be
+		selected or the board must provide an implementation of the
+		flash API (see include/flash.h).
+
 - DataFlash Support:
 		CONFIG_HAS_DATAFLASH
 
@@ -3068,11 +3079,6 @@ CBFS (Coreboot Filesystem) support
 		Define this option to include a destructive SPI flash
 		test ('sf test').
 
-		CONFIG_SPI_FLASH_BAR		Ban/Extended Addr Reg
-
-		Define this option to use the Bank addr/Extended addr
-		support on SPI flashes which has size > 16Mbytes.
-
 		CONFIG_SF_DUAL_FLASH		Dual flash memories
 
 		Define this option to use dual flash support where two flash

arch/Kconfig

@@ -18,13 +18,14 @@ config ARC
 
 config ARM
 	bool "ARM architecture"
-	select HAVE_PRIVATE_LIBGCC
+	select HAVE_PRIVATE_LIBGCC if !ARM64
 	select HAVE_GENERIC_BOARD
 	select SUPPORT_OF_CONTROL
 
 config AVR32
 	bool "AVR32 architecture"
 	select HAVE_GENERIC_BOARD
+	select SYS_GENERIC_BOARD
 
 config BLACKFIN
 	bool "Blackfin architecture"

arch/arc/Kconfig

@@ -4,9 +4,6 @@ menu "ARC architecture"
 config SYS_ARCH
 	default "arc"
 
-config USE_PRIVATE_LIBGCC
-	default y
-
 config SYS_CPU
 	default "arcv1" if ISA_ARCOMPACT
 	default "arcv2" if ISA_ARCV2

arch/arc/include/asm/arcregs.h

@@ -47,9 +47,12 @@
 #endif
 #define ARC_BCR_DC_BUILD	0x72
 #define ARC_BCR_SLC		0xce
-#define ARC_AUX_SLC_CONTROL	0x903
+#define ARC_AUX_SLC_CONFIG	0x901
+#define ARC_AUX_SLC_CTRL	0x903
 #define ARC_AUX_SLC_FLUSH	0x904
 #define ARC_AUX_SLC_INVALIDATE	0x905
+#define ARC_AUX_SLC_IVDL	0x910
+#define ARC_AUX_SLC_FLDL	0x912
 
 #ifndef __ASSEMBLY__
 /* Accessors for auxiliary registers */

arch/arc/include/asm/cache.h

@@ -29,12 +29,7 @@
 
 #ifndef __ASSEMBLY__
 
-#ifdef CONFIG_ISA_ARCV2
-void slc_enable(void);
-void slc_disable(void);
-void slc_flush(void);
-void slc_invalidate(void);
-#endif
+void cache_init(void);
 
 #endif /* __ASSEMBLY__ */
 

arch/arc/lib/bootm.c

@@ -53,6 +53,9 @@ static void boot_prep_linux(bootm_headers_t *images)
 		hang();
 }
 
+__weak void smp_set_core_boot_addr(unsigned long addr, int corenr) {}
+__weak void smp_kick_all_cpus(void) {}
+
 /* Subcommand: GO */
 static void boot_jump_linux(bootm_headers_t *images, int flag)
 {
@@ -80,6 +83,9 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
 		r2 = (unsigned int)getenv("bootargs");
 	}
 
+	smp_set_core_boot_addr((unsigned long)kernel_entry, -1);
+	smp_kick_all_cpus();
+
 	if (!fake)
 		kernel_entry(r0, 0, r2);
 }

arch/arc/lib/cache.c

@@ -5,9 +5,13 @@
  */
 
 #include <config.h>
+#include <linux/compiler.h>
+#include <linux/kernel.h>
 #include <asm/arcregs.h>
 #include <asm/cache.h>
 
+#define CACHE_LINE_MASK		(~(CONFIG_SYS_CACHELINE_SIZE - 1))
+
 /* Bit values in IC_CTRL */
 #define IC_CTRL_CACHE_DISABLE	(1 << 0)
 
@@ -18,60 +22,186 @@
 #define CACHE_VER_NUM_MASK	0xF
 #define SLC_CTRL_SB		(1 << 2)
 
+#define OP_INV		0x1
+#define OP_FLUSH	0x2
+#define OP_INV_IC	0x3
+
+#ifdef CONFIG_ISA_ARCV2
+/*
+ * By default that variable will fall into .bss section.
+ * But .bss section is not relocated and so it will be initilized before
+ * relocation but will be used after being zeroed.
+ */
+int slc_line_sz __section(".data");
+int slc_exists __section(".data");
+
+static unsigned int __before_slc_op(const int op)
+{
+	unsigned int reg = reg;
+
+	if (op == OP_INV) {
+		/*
+		 * IM is set by default and implies Flush-n-inv
+		 * Clear it here for vanilla inv
+		 */
+		reg = read_aux_reg(ARC_AUX_SLC_CTRL);
+		write_aux_reg(ARC_AUX_SLC_CTRL, reg & ~DC_CTRL_INV_MODE_FLUSH);
+	}
+
+	return reg;
+}
+
+static void __after_slc_op(const int op, unsigned int reg)
+{
+	if (op & OP_FLUSH)	/* flush / flush-n-inv both wait */
+		while (read_aux_reg(ARC_AUX_SLC_CTRL) &
+		       DC_CTRL_FLUSH_STATUS)
+			;
+
+	/* Switch back to default Invalidate mode */
+	if (op == OP_INV)
+		write_aux_reg(ARC_AUX_SLC_CTRL, reg | DC_CTRL_INV_MODE_FLUSH);
+}
+
+static inline void __slc_line_loop(unsigned long paddr, unsigned long sz,
+				   const int op)
+{
+	unsigned int aux_cmd;
+	int num_lines;
+
+#define SLC_LINE_MASK	(~(slc_line_sz - 1))
+
+	aux_cmd = op & OP_INV ? ARC_AUX_SLC_IVDL : ARC_AUX_SLC_FLDL;
+
+	sz += paddr & ~SLC_LINE_MASK;
+	paddr &= SLC_LINE_MASK;
+
+	num_lines = DIV_ROUND_UP(sz, slc_line_sz);
+
+	while (num_lines-- > 0) {
+		write_aux_reg(aux_cmd, paddr);
+		paddr += slc_line_sz;
+	}
+}
+
+static inline void __slc_entire_op(const int cacheop)
+{
+	int aux;
+	unsigned int ctrl_reg = __before_slc_op(cacheop);
+
+	if (cacheop & OP_INV)	/* Inv or flush-n-inv use same cmd reg */
+		aux = ARC_AUX_SLC_INVALIDATE;
+	else
+		aux = ARC_AUX_SLC_FLUSH;
+
+	write_aux_reg(aux, 0x1);
+
+	__after_slc_op(cacheop, ctrl_reg);
+}
+
+static inline void __slc_line_op(unsigned long paddr, unsigned long sz,
+				 const int cacheop)
+{
+	unsigned int ctrl_reg = __before_slc_op(cacheop);
+	__slc_line_loop(paddr, sz, cacheop);
+	__after_slc_op(cacheop, ctrl_reg);
+}
+#else
+#define __slc_entire_op(cacheop)
+#define __slc_line_op(paddr, sz, cacheop)
+#endif
+
+static inline int icache_exists(void)
+{
+	/* Check if Instruction Cache is available */
+	if (read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK)
+		return 1;
+	else
+		return 0;
+}
+
+static inline int dcache_exists(void)
+{
+	/* Check if Data Cache is available */
+	if (read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK)
+		return 1;
+	else
+		return 0;
+}
+
+void cache_init(void)
+{
+#ifdef CONFIG_ISA_ARCV2
+	/* Check if System-Level Cache (SLC) is available */
+	if (read_aux_reg(ARC_BCR_SLC) & CACHE_VER_NUM_MASK) {
+#define LSIZE_OFFSET	4
+#define LSIZE_MASK	3
+		if (read_aux_reg(ARC_AUX_SLC_CONFIG) &
+		    (LSIZE_MASK << LSIZE_OFFSET))
+			slc_line_sz = 64;
+		else
+			slc_line_sz = 128;
+		slc_exists = 1;
+	} else {
+		slc_exists = 0;
+	}
+#endif
+}
+
 int icache_status(void)
 {
-	/* If no cache in CPU exit immediately */
-	if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
+	if (!icache_exists())
 		return 0;
 
-	return (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) !=
-	       IC_CTRL_CACHE_DISABLE;
+	if (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE)
+		return 0;
+	else
+		return 1;
 }
 
 void icache_enable(void)
 {
-	/* If no cache in CPU exit immediately */
-	if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
-		return;
-
-	write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
-		      ~IC_CTRL_CACHE_DISABLE);
+	if (icache_exists())
+		write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
+			      ~IC_CTRL_CACHE_DISABLE);
 }
 
 void icache_disable(void)
 {
-	/* If no cache in CPU exit immediately */
-	if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
-		return;
-
-	write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
-		      IC_CTRL_CACHE_DISABLE);
+	if (icache_exists())
+		write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
+			      IC_CTRL_CACHE_DISABLE);
 }
 
+#ifndef CONFIG_SYS_DCACHE_OFF
 void invalidate_icache_all(void)
 {
-	/* If no cache in CPU exit immediately */
-	if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
-		return;
-
 	/* Any write to IC_IVIC register triggers invalidation of entire I$ */
-	write_aux_reg(ARC_AUX_IC_IVIC, 1);
+	if (icache_status()) {
+		write_aux_reg(ARC_AUX_IC_IVIC, 1);
+		read_aux_reg(ARC_AUX_IC_CTRL);	/* blocks */
+	}
 }
+#else
+void invalidate_icache_all(void)
+{
+}
+#endif
 
 int dcache_status(void)
 {
-	/* If no cache in CPU exit immediately */
-	if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
+	if (!dcache_exists())
 		return 0;
 
-	return (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) !=
-		DC_CTRL_CACHE_DISABLE;
+	if (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE)
+		return 0;
+	else
+		return 1;
 }
 
 void dcache_enable(void)
 {
-	/* If no cache in CPU exit immediately */
-	if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
+	if (!dcache_exists())
 		return;
 
 	write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
@@ -80,91 +210,123 @@ void dcache_enable(void)
 
 void dcache_disable(void)
 {
-	/* If no cache in CPU exit immediately */
-	if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
+	if (!dcache_exists())
 		return;
 
 	write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
 		      DC_CTRL_CACHE_DISABLE);
 }
 
-void flush_dcache_all(void)
-{
-	/* If no cache in CPU exit immediately */
-	if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
-		return;
-
-	/* Do flush of entire cache */
-	write_aux_reg(ARC_AUX_DC_FLSH, 1);
-
-	/* Wait flush end */
-	while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
-		;
-}
-
 #ifndef CONFIG_SYS_DCACHE_OFF
-static void dcache_flush_line(unsigned addr)
+/*
+ * Common Helper for Line Operations on {I,D}-Cache
+ */
+static inline void __cache_line_loop(unsigned long paddr, unsigned long sz,
+				     const int cacheop)
 {
+	unsigned int aux_cmd;
 #if (CONFIG_ARC_MMU_VER == 3)
-	write_aux_reg(ARC_AUX_DC_PTAG, addr);
+	unsigned int aux_tag;
 #endif
-	write_aux_reg(ARC_AUX_DC_FLDL, addr);
+	int num_lines;
 
-	/* Wait flush end */
-	while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
-		;
-
-#ifndef CONFIG_SYS_ICACHE_OFF
-	/*
-	 * Invalidate I$ for addresses range just flushed from D$.
-	 * If we try to execute data flushed above it will be valid/correct
-	 */
+	if (cacheop == OP_INV_IC) {
+		aux_cmd = ARC_AUX_IC_IVIL;
 #if (CONFIG_ARC_MMU_VER == 3)
-	write_aux_reg(ARC_AUX_IC_PTAG, addr);
+		aux_tag = ARC_AUX_IC_PTAG;
 #endif
-	write_aux_reg(ARC_AUX_IC_IVIL, addr);
-#endif /* CONFIG_SYS_ICACHE_OFF */
+	} else {
+		/* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
+		aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL;
+#if (CONFIG_ARC_MMU_VER == 3)
+		aux_tag = ARC_AUX_DC_PTAG;
+#endif
+	}
+
+	sz += paddr & ~CACHE_LINE_MASK;
+	paddr &= CACHE_LINE_MASK;
+
+	num_lines = DIV_ROUND_UP(sz, CONFIG_SYS_CACHELINE_SIZE);
+
+	while (num_lines-- > 0) {
+#if (CONFIG_ARC_MMU_VER == 3)
+		write_aux_reg(aux_tag, paddr);
+#endif
+		write_aux_reg(aux_cmd, paddr);
+		paddr += CONFIG_SYS_CACHELINE_SIZE;
+	}
 }
-#endif /* CONFIG_SYS_DCACHE_OFF */
 
-void flush_dcache_range(unsigned long start, unsigned long end)
+static unsigned int __before_dc_op(const int op)
 {
-#ifndef CONFIG_SYS_DCACHE_OFF
-	unsigned int addr;
+	unsigned int reg;
 
-	start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
-	end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
+	if (op == OP_INV) {
+		/*
+		 * IM is set by default and implies Flush-n-inv
+		 * Clear it here for vanilla inv
+		 */
+		reg = read_aux_reg(ARC_AUX_DC_CTRL);
+		write_aux_reg(ARC_AUX_DC_CTRL, reg & ~DC_CTRL_INV_MODE_FLUSH);
+	}
 
-	for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE)
-		dcache_flush_line(addr);
-#endif /* CONFIG_SYS_DCACHE_OFF */
+	return reg;
 }
 
+static void __after_dc_op(const int op, unsigned int reg)
+{
+	if (op & OP_FLUSH)	/* flush / flush-n-inv both wait */
+		while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
+			;
+
+	/* Switch back to default Invalidate mode */
+	if (op == OP_INV)
+		write_aux_reg(ARC_AUX_DC_CTRL, reg | DC_CTRL_INV_MODE_FLUSH);
+}
+
+static inline void __dc_entire_op(const int cacheop)
+{
+	int aux;
+	unsigned int ctrl_reg = __before_dc_op(cacheop);
+
+	if (cacheop & OP_INV)	/* Inv or flush-n-inv use same cmd reg */
+		aux = ARC_AUX_DC_IVDC;
+	else
+		aux = ARC_AUX_DC_FLSH;
+
+	write_aux_reg(aux, 0x1);
+
+	__after_dc_op(cacheop, ctrl_reg);
+}
+
+static inline void __dc_line_op(unsigned long paddr, unsigned long sz,
+				const int cacheop)
+{
+	unsigned int ctrl_reg = __before_dc_op(cacheop);
+	__cache_line_loop(paddr, sz, cacheop);
+	__after_dc_op(cacheop, ctrl_reg);
+}
+#else
+#define __dc_entire_op(cacheop)
+#define __dc_line_op(paddr, sz, cacheop)
+#endif /* !CONFIG_SYS_DCACHE_OFF */
+
 void invalidate_dcache_range(unsigned long start, unsigned long end)
 {
-#ifndef CONFIG_SYS_DCACHE_OFF
-	unsigned int addr;
-
-	start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
-	end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
-
-	for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) {
-#if (CONFIG_ARC_MMU_VER == 3)
-		write_aux_reg(ARC_AUX_DC_PTAG, addr);
+	__dc_line_op(start, end - start, OP_INV);
+#ifdef CONFIG_ISA_ARCV2
+	if (slc_exists)
+		__slc_line_op(start, end - start, OP_INV);
 #endif
-		write_aux_reg(ARC_AUX_DC_IVDL, addr);
-	}
-#endif /* CONFIG_SYS_DCACHE_OFF */
 }
 
-void invalidate_dcache_all(void)
+void flush_dcache_range(unsigned long start, unsigned long end)
 {
-	/* If no cache in CPU exit immediately */
-	if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
-		return;
-
-	/* Write 1 to DC_IVDC register triggers invalidation of entire D$ */
-	write_aux_reg(ARC_AUX_DC_IVDC, 1);
+	__dc_line_op(start, end - start, OP_FLUSH);
+#ifdef CONFIG_ISA_ARCV2
+	if (slc_exists)
+		__slc_line_op(start, end - start, OP_FLUSH);
+#endif
 }
 
 void flush_cache(unsigned long start, unsigned long size)
@@ -172,47 +334,20 @@ void flush_cache(unsigned long start, unsigned long size)
 	flush_dcache_range(start, start + size);
 }
 
+void invalidate_dcache_all(void)
+{
+	__dc_entire_op(OP_INV);
 #ifdef CONFIG_ISA_ARCV2
-void slc_enable(void)
-{
-	/* If SLC ver = 0, no SLC present in CPU */
-	if (!(read_aux_reg(ARC_BCR_SLC) & 0xff))
-		return;
-
-	write_aux_reg(ARC_AUX_SLC_CONTROL,
-		      read_aux_reg(ARC_AUX_SLC_CONTROL) & ~1);
+	if (slc_exists)
+		__slc_entire_op(OP_INV);
+#endif
 }
 
-void slc_disable(void)
+void flush_dcache_all(void)
 {
-	/* If SLC ver = 0, no SLC present in CPU */
-	if (!(read_aux_reg(ARC_BCR_SLC) & 0xff))
-		return;
-
-	write_aux_reg(ARC_AUX_SLC_CONTROL,
-		      read_aux_reg(ARC_AUX_SLC_CONTROL) | 1);
+	__dc_entire_op(OP_FLUSH);
+#ifdef CONFIG_ISA_ARCV2
+	if (slc_exists)
+		__slc_entire_op(OP_FLUSH);
+#endif
 }
-
-void slc_flush(void)
-{
-	/* If SLC ver = 0, no SLC present in CPU */
-	if (!(read_aux_reg(ARC_BCR_SLC) & 0xff))
-		return;
-
-	write_aux_reg(ARC_AUX_SLC_FLUSH, 1);
-
-	/* Wait flush end */
-	while (read_aux_reg(ARC_AUX_SLC_CONTROL) & SLC_CTRL_SB)
-		;
-}
-
-void slc_invalidate(void)
-{
-	/* If SLC ver = 0, no SLC present in CPU */
-	if (!(read_aux_reg(ARC_BCR_SLC) & 0xff))
-		return;
-
-	write_aux_reg(ARC_AUX_SLC_INVALIDATE, 1);
-}
-
-#endif /* CONFIG_ISA_ARCV2 */

arch/arc/lib/cpu.c

@@ -23,6 +23,8 @@ int arch_cpu_init(void)
 	gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
 	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 
+	cache_init();
+
 	return 0;
 }
 

arch/arc/lib/init_helpers.c

@@ -10,16 +10,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int init_cache_f_r(void)
 {
-#ifndef CONFIG_SYS_ICACHE_OFF
-	icache_enable();
-	/* Make sure no stale entries persist from before we disabled cache */
-	invalidate_icache_all();
-#endif
-
 #ifndef CONFIG_SYS_DCACHE_OFF
-	dcache_enable();
-	/* Make sure no stale entries persist from before we disabled cache */
-	invalidate_dcache_all();
+	flush_dcache_all();
 #endif
 	return 0;
 }

arch/arc/lib/start.S

@@ -13,19 +13,47 @@ ENTRY(_start)
 	/* Setup interrupt vector base that matches "__text_start" */
 	sr	__ivt_start, [ARC_AUX_INTR_VEC_BASE]
 
+	; Disable/enable I-cache according to configuration
+	lr	r5, [ARC_BCR_IC_BUILD]
+	breq	r5, 0, 1f		; I$ doesn't exist
+	lr	r5, [ARC_AUX_IC_CTRL]
+#ifndef CONFIG_SYS_ICACHE_OFF
+	bclr	r5, r5, 0		; 0 - Enable, 1 is Disable
+#else
+	bset	r5, r5, 0		; I$ exists, but is not used
+#endif
+	sr	r5, [ARC_AUX_IC_CTRL]
+
+1:
+	; Disable/enable D-cache according to configuration
+	lr	r5, [ARC_BCR_DC_BUILD]
+	breq	r5, 0, 1f		; D$ doesn't exist
+	lr	r5, [ARC_AUX_DC_CTRL]
+	bclr	r5, r5, 6		; Invalidate (discard w/o wback)
+#ifndef CONFIG_SYS_DCACHE_OFF
+	bclr	r5, r5, 0		; Enable (+Inv)
+#else
+	bset	r5, r5, 0		; Disable (+Inv)
+#endif
+	sr	r5, [ARC_AUX_DC_CTRL]
+
+1:
+#ifdef CONFIG_ISA_ARCV2
+	; Disable System-Level Cache (SLC)
+	lr	r5, [ARC_BCR_SLC]
+	breq	r5, 0, 1f		; SLC doesn't exist
+	lr	r5, [ARC_AUX_SLC_CTRL]
+	bclr	r5, r5, 6		; Invalidate (discard w/o wback)
+	bclr	r5, r5, 0		; Enable (+Inv)
+	sr	r5, [ARC_AUX_SLC_CTRL]
+
+1:
+#endif
+
 	/* Setup stack- and frame-pointers */
 	mov	%sp, CONFIG_SYS_INIT_SP_ADDR
 	mov	%fp, %sp
 
-	/* Unconditionally disable caches */
-#ifdef CONFIG_ISA_ARCV2
-	bl	slc_flush
-	bl	slc_disable
-#endif
-	bl	flush_dcache_all
-	bl	dcache_disable
-	bl	icache_disable
-
 	/* Allocate and zero GD, update SP */
 	mov	%r0, %sp
 	bl	board_init_f_mem

arch/arm/Kconfig

@@ -346,8 +346,13 @@ config TARGET_DRACO
 	select CPU_V7
 	select SUPPORT_SPL
 
-config TARGET_DXR2
-	bool "Support dxr2"
+config TARGET_THUBAN
+	bool "Support thuban"
+	select CPU_V7
+	select SUPPORT_SPL
+
+config TARGET_RASTABAN
+	bool "Support rastaban"
 	select CPU_V7
 	select SUPPORT_SPL
 
@@ -369,6 +374,14 @@ config TARGET_PENGWYN
 	select DM_SERIAL
 	select DM_GPIO
 
+config TARGET_AM335X_BALTOS
+	bool "Support am335x_baltos"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
 config TARGET_AM335X_EVM
 	bool "Support am335x_evm"
 	select CPU_V7
@@ -576,10 +589,6 @@ config TARGET_TBS2910
 	bool "Support tbs2910"
 	select CPU_V7
 
-config TARGET_TQMA6
-	bool "TQ Systems TQMa6 board"
-	select CPU_V7
-
 config TARGET_OT1200
 	bool "Bachmann OT1200"
 	select CPU_V7
@@ -657,7 +666,11 @@ config ARCH_ZYNQ
 	bool "Xilinx Zynq Platform"
 	select CPU_V7
 	select SUPPORT_SPL
+	select OF_CONTROL
+	select SPL_DISABLE_OF_CONTROL
 	select DM
+	select DM_SPI
+	select DM_SPI_FLASH
 
 config TARGET_XILINX_ZYNQMP
 	bool "Support Xilinx ZynqMP Platform"
@@ -668,6 +681,7 @@ config TEGRA
 	select SUPPORT_SPL
 	select SPL
 	select OF_CONTROL
+	select SPL_DISABLE_OF_CONTROL
 	select CPU_V7
 	select DM
 	select DM_SPI_FLASH
@@ -794,6 +808,7 @@ config ARCH_UNIPHIER
 	select DM
 	select DM_SERIAL
 	select DM_I2C
+	select SPL_DISABLE_OF_CONTROL
 	help
 	  Support for UniPhier SoC family developed by Socionext Inc.
 	  (formerly, System LSI Business Division of Panasonic Corporation)
@@ -957,11 +972,11 @@ source "board/ti/ti816x/Kconfig"
 source "board/timll/devkit3250/Kconfig"
 source "board/toradex/colibri_pxa270/Kconfig"
 source "board/toradex/colibri_vf/Kconfig"
-source "board/tqc/tqma6/Kconfig"
 source "board/trizepsiv/Kconfig"
 source "board/ttcontrol/vision2/Kconfig"
 source "board/udoo/Kconfig"
 source "board/vpac270/Kconfig"
+source "board/vscom/baltos/Kconfig"
 source "board/wandboard/Kconfig"
 source "board/warp/Kconfig"
 source "board/woodburn/Kconfig"

arch/arm/cpu/armv7/am33xx/ddr.c

@@ -123,30 +123,33 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
 	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 
-	/* Perform hardware leveling. */
-	udelay(1000);
-	writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
-	       0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
-	writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) |
-	       0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
+	/* Perform hardware leveling for DDR3 */
+	if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) {
+		udelay(1000);
+		writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
+		       0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
+		writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) |
+		       0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
 
-	writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
+		writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
 
-	/* Enable read leveling */
-	writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
+		/* Enable read leveling */
+		writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
 
-	/*
-	 * Enable full read and write leveling.  Wait for read and write
-	 * leveling bit to clear RDWRLVLFULL_START bit 31
-	 */
-	while((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000) != 0)
-		;
+		/*
+		 * Enable full read and write leveling.  Wait for read and write
+		 * leveling bit to clear RDWRLVLFULL_START bit 31
+		 */
+		while ((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000)
+		      != 0)
+			;
 
-	/* Check the timeout register to see if leveling is complete */
-	if((readl(&emif_reg[nr]->emif_status) & 0x70) != 0)
-		puts("DDR3 H/W leveling incomplete with errors\n");
+		/* Check the timeout register to see if leveling is complete */
+		if ((readl(&emif_reg[nr]->emif_status) & 0x70) != 0)
+			puts("DDR3 H/W leveling incomplete with errors\n");
 
-	if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) {
+	} else {
+		/* DDR2 */
 		configure_mr(nr, 0);
 		configure_mr(nr, 1);
 	}
@@ -182,10 +185,50 @@ void set_sdram_timings(const struct emif_regs *regs, int nr)
 	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
 }
 
+/*
+ * Configure EXT PHY registers for software leveling
+ */
+static void ext_phy_settings_swlvl(const struct emif_regs *regs, int nr)
+{
+	u32 *ext_phy_ctrl_base = 0;
+	u32 *emif_ext_phy_ctrl_base = 0;
+	__maybe_unused const u32 *ext_phy_ctrl_const_regs;
+	u32 i = 0;
+	__maybe_unused u32 size;
+
+	ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
+	emif_ext_phy_ctrl_base =
+			(u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
+
+	/* Configure external phy control timing registers */
+	for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
+		writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
+		/* Update shadow registers */
+		writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
+	}
+
+#ifdef CONFIG_AM43XX
+	/*
+	 * External phy 6-24 registers do not change with ddr frequency.
+	 * These only need to be set on DDR2 on AM43xx.
+	 */
+	emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
+
+	if (!size)
+		return;
+
+	for (i = 0; i < size; i++) {
+		writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
+		/* Update shadow registers */
+		writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
+	}
+#endif
+}
+
 /*
  * Configure EXT PHY registers for hardware leveling
  */
-static void ext_phy_settings(const struct emif_regs *regs, int nr)
+static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr)
 {
 	/*
 	 * Enable hardware leveling on the EMIF.  For details about these
@@ -256,8 +299,12 @@ void config_ddr_phy(const struct emif_regs *regs, int nr)
 	writel(regs->emif_ddr_phy_ctlr_1,
 		&emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
 
-	if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5)
-		ext_phy_settings(regs, nr);
+	if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5) {
+		if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
+			ext_phy_settings_hwlvl(regs, nr);
+		else
+			ext_phy_settings_swlvl(regs, nr);
+	}
 }
 
 /**

arch/arm/cpu/armv7/am33xx/emif4.c

@@ -124,8 +124,9 @@ void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
 	/* Set CKE to be controlled by EMIF/DDR PHY */
 	writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
 
-	/* Allow EMIF to control DDR_RESET */
-	writel(0x00000000, &ddrctrl->ddrioctrl);
+	if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
+		/* Allow EMIF to control DDR_RESET */
+		writel(0x00000000, &ddrctrl->ddrioctrl);
 #endif
 
 	/* Program EMIF instance */

arch/arm/cpu/armv7/cpu.c

@@ -24,7 +24,7 @@
 
 void __weak cpu_cache_initialization(void){}
 
-int cleanup_before_linux(void)
+int cleanup_before_linux_select(int flags)
 {
 	/*
 	 * this function is called just before we call linux
@@ -42,24 +42,30 @@ int cleanup_before_linux(void)
 	icache_disable();
 	invalidate_icache_all();
 
-	/*
-	 * turn off D-cache
-	 * dcache_disable() in turn flushes the d-cache and disables MMU
-	 */
-	dcache_disable();
-	v7_outer_cache_disable();
+	if (flags & CBL_DISABLE_CACHES) {
+		/*
+		* turn off D-cache
+		* dcache_disable() in turn flushes the d-cache and disables MMU
+		*/
+		dcache_disable();
+		v7_outer_cache_disable();
 
-	/*
-	 * After D-cache is flushed and before it is disabled there may
-	 * be some new valid entries brought into the cache. We are sure
-	 * that these lines are not dirty and will not affect our execution.
-	 * (because unwinding the call-stack and setting a bit in CP15 SCTLR
-	 * is all we did during this. We have not pushed anything on to the
-	 * stack. Neither have we affected any static data)
-	 * So just invalidate the entire d-cache again to avoid coherency
-	 * problems for kernel
-	 */
-	invalidate_dcache_all();
+		/*
+		* After D-cache is flushed and before it is disabled there may
+		* be some new valid entries brought into the cache. We are
+		* sure that these lines are not dirty and will not affect our
+		* execution. (because unwinding the call-stack and setting a
+		* bit in CP15 SCTRL is all we did during this. We have not
+		* pushed anything on to the stack. Neither have we affected
+		* any static data) So just invalidate the entire d-cache again
+		* to avoid coherency problems for kernel
+		*/
+		invalidate_dcache_all();
+	} else {
+		flush_dcache_all();
+		invalidate_icache_all();
+		icache_enable();
+	}
 
 	/*
 	 * Some CPU need more cache attention before starting the kernel.
@@ -68,3 +74,8 @@ int cleanup_before_linux(void)
 
 	return 0;
 }
+
+int cleanup_before_linux(void)
+{
+	return cleanup_before_linux_select(CBL_ALL);
+}

arch/arm/cpu/armv7/exynos/Kconfig

@@ -8,6 +8,7 @@ config TARGET_SMDKV310
 	select SUPPORT_SPL
 	bool "Exynos4210 SMDKV310 board"
 	select OF_CONTROL
+	select SPL_DISABLE_OF_CONTROL
 
 config TARGET_TRATS
 	bool "Exynos4210 Trats board"
@@ -28,6 +29,7 @@ config TARGET_ODROID
 config TARGET_ODROID_XU3
 	bool "Exynos5422 Odroid board"
 	select OF_CONTROL
+	select SPL_DISABLE_OF_CONTROL
 
 config TARGET_ARNDALE
 	bool "Exynos5250 Arndale board"
@@ -35,40 +37,43 @@ config TARGET_ARNDALE
 	select CPU_V7_HAS_VIRT
 	select SUPPORT_SPL
 	select OF_CONTROL
+	select SPL_DISABLE_OF_CONTROL
 
 config TARGET_SMDK5250
 	bool "SMDK5250 board"
 	select SUPPORT_SPL
 	select OF_CONTROL
+	select SPL_DISABLE_OF_CONTROL
 
 config TARGET_SNOW
 	bool "Snow board"
 	select SUPPORT_SPL
 	select OF_CONTROL
+	select SPL_DISABLE_OF_CONTROL
 
 config TARGET_SMDK5420
 	bool "SMDK5420 board"
 	select SUPPORT_SPL
 	select OF_CONTROL
+	select SPL_DISABLE_OF_CONTROL
 
 config TARGET_PEACH_PI
 	bool "Peach Pi board"
 	select SUPPORT_SPL
 	select OF_CONTROL
+	select SPL_DISABLE_OF_CONTROL
 
 config TARGET_PEACH_PIT
 	bool "Peach Pit board"
 	select SUPPORT_SPL
 	select OF_CONTROL
+	select SPL_DISABLE_OF_CONTROL
 
 endchoice
 
 config SYS_SOC
 	default "exynos"
 
-config DM_USB
-	default y
-
 source "board/samsung/smdkv310/Kconfig"
 source "board/samsung/trats/Kconfig"
 source "board/samsung/universal_c210/Kconfig"

arch/arm/cpu/armv7/mx6/Kconfig

@@ -33,11 +33,16 @@ config TARGET_SECOMX6
 	bool "Support secomx6 boards"
 	select CPU_V7
 
+config TARGET_TQMA6
+	bool "TQ Systems TQMa6 board"
+	select CPU_V7
+
 endchoice
 
 config SYS_SOC
 	default "mx6"
 
 source "board/seco/Kconfig"
+source "board/tqc/tqma6/Kconfig"
 
 endif

arch/arm/cpu/armv7/mx6/soc.c

@@ -62,6 +62,7 @@ u32 get_cpu_rev(void)
 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 	u32 reg = readl(&anatop->digprog_sololite);
 	u32 type = ((reg >> 16) & 0xff);
+	u32 major;
 
 	if (type != MXC_CPU_MX6SL) {
 		reg = readl(&anatop->digprog);
@@ -79,8 +80,9 @@ u32 get_cpu_rev(void)
 		}
 
 	}
+	major = ((reg >> 8) & 0xff);
 	reg &= 0xff;		/* mx6 silicon revision */
-	return (type << 12) | (reg + 0x10);
+	return (type << 12) | (reg + (0x10 * (major + 1)));
 }
 
 /*

arch/arm/cpu/armv7/omap-common/clocks-common.c

@@ -372,6 +372,7 @@ static void setup_dplls(void)
 {
 	u32 temp;
 	const struct dpll_params *params;
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
 
 	debug("setup_dplls\n");
 
@@ -382,7 +383,8 @@ static void setup_dplls(void)
 	 * Core DPLL will be locked after setting up EMIF
 	 * using the FREQ_UPDATE method(freq_update_core())
 	 */
-	if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
+	if (emif_sdram_type(readl(&emif->emif_sdram_config)) ==
+	    EMIF_SDRAM_TYPE_LPDDR2)
 		do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
 							DPLL_NO_LOCK, "core");
 	else
@@ -508,6 +510,12 @@ static u32 optimize_vcore_voltage(struct volts const *v)
 	return val;
 }
 
+#ifdef CONFIG_IODELAY_RECALIBRATION
+void __weak recalibrate_iodelay(void)
+{
+}
+#endif
+
 /*
  * Setup the voltages for the main SoC core power domains.
  * We start with the maximum voltages allowed here, as set in the corresponding
@@ -561,6 +569,16 @@ void scale_vcores(struct vcores_data const *vcores)
 
 	debug("cor: %d\n", vcores->core.value);
 	do_scale_vcore(vcores->core.addr, vcores->core.value, vcores->core.pmic);
+	/*
+	 * IO delay recalibration should be done immediately after
+	 * adjusting AVS voltages for VDD_CORE_L.
+	 * Respective boards should call __recalibrate_iodelay()
+	 * with proper mux, virtual and manual mode configurations.
+	 */
+#ifdef CONFIG_IODELAY_RECALIBRATION
+	recalibrate_iodelay();
+#endif
+
 	debug("mpu: %d\n", vcores->mpu.value);
 	do_scale_vcore(vcores->mpu.addr, vcores->mpu.value, vcores->mpu.pmic);
 	/* Configure MPU ABB LDO after scale */
@@ -587,6 +605,16 @@ void scale_vcores(struct vcores_data const *vcores)
 	val = optimize_vcore_voltage(&vcores->core);
 	do_scale_vcore(vcores->core.addr, val, vcores->core.pmic);
 
+	/*
+	 * IO delay recalibration should be done immediately after
+	 * adjusting AVS voltages for VDD_CORE_L.
+	 * Respective boards should call __recalibrate_iodelay()
+	 * with proper mux, virtual and manual mode configurations.
+	 */
+#ifdef CONFIG_IODELAY_RECALIBRATION
+	recalibrate_iodelay();
+#endif
+
 	val = optimize_vcore_voltage(&vcores->mpu);
 	do_scale_vcore(vcores->mpu.addr, val, vcores->mpu.pmic);
 

arch/arm/cpu/armv7/omap-common/emif-common.c

@@ -242,13 +242,122 @@ static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
 	       __udelay(130);
 }
 
-static void ddr3_leveling(u32 base, const struct emif_regs *regs)
+static void update_hwleveling_output(u32 base, const struct emif_regs *regs)
 {
-	if (is_omap54xx())
-		omap5_ddr3_leveling(base, regs);
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+	u32 *emif_ext_phy_ctrl_reg, *emif_phy_status;
+	u32 reg, i;
+
+	emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7];
+
+	/* Update PHY_REG_RDDQS_RATIO */
+	emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7;
+	for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) {
+		reg = readl(emif_phy_status++);
+		writel(reg, emif_ext_phy_ctrl_reg++);
+		writel(reg, emif_ext_phy_ctrl_reg++);
+	}
+
+	/* Update PHY_REG_FIFO_WE_SLAVE_RATIO */
+	emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2;
+	for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) {
+		reg = readl(emif_phy_status++);
+		writel(reg, emif_ext_phy_ctrl_reg++);
+		writel(reg, emif_ext_phy_ctrl_reg++);
+	}
+
+	/* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */
+	emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12;
+	for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) {
+		reg = readl(emif_phy_status++);
+		writel(reg, emif_ext_phy_ctrl_reg++);
+		writel(reg, emif_ext_phy_ctrl_reg++);
+	}
+
+	/* Disable Leveling */
+	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
+	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
+	writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);
 }
 
-static void ddr3_init(u32 base, const struct emif_regs *regs)
+static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	/* Clear Error Status */
+	clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36,
+			EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR,
+			EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
+
+	clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36_shdw,
+			EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR,
+			EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
+
+	/* Disable refreshed before leveling */
+	clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT,
+			EMIF_REG_INITREF_DIS_SHIFT);
+
+	/* Start Full leveling */
+	writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
+
+	__udelay(300);
+
+	/* Check for leveling timeout */
+	if (readl(&emif->emif_status) & EMIF_REG_LEVELING_TO_MASK) {
+		printf("Leveling timeout on EMIF%d\n", emif_num(base));
+		return;
+	}
+
+	/* Enable refreshes after leveling */
+	clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT);
+
+	debug("HW leveling success\n");
+	/*
+	 * Update slave ratios in EXT_PHY_CTRLx registers
+	 * as per HW leveling output
+	 */
+	update_hwleveling_output(base, regs);
+}
+
+static void dra7_ddr3_init(u32 base, const struct emif_regs *regs)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	if (warm_reset())
+		emif_reset_phy(base);
+	do_ext_phy_settings(base, regs);
+
+	writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK,
+	       &emif->emif_sdram_ref_ctrl);
+	/* Update timing registers */
+	writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
+	writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
+	writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
+
+	writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config);
+	writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
+	writel(regs->zq_config, &emif->emif_zq_config);
+	writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
+	writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
+	writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl);
+
+	writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
+	writel(regs->emif_rd_wr_exec_thresh, &emif->emif_rd_wr_exec_thresh);
+
+	writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
+
+	writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
+	writel(regs->sdram_config_init, &emif->emif_sdram_config);
+
+	__udelay(1000);
+
+	writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);
+
+	if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK)
+		dra7_ddr3_leveling(base, regs);
+}
+
+static void omap5_ddr3_init(u32 base, const struct emif_regs *regs)
 {
 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 
@@ -269,25 +378,20 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
 
 	writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
 
-	/*
-	 * The same sequence should work on OMAP5432 as well. But strange that
-	 * it is not working
-	 */
-	if (is_dra7xx()) {
-		do_ext_phy_settings(base, regs);
-		writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);
-		writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
-		writel(regs->sdram_config_init, &emif->emif_sdram_config);
-	} else {
-		writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
-		writel(regs->sdram_config_init, &emif->emif_sdram_config);
-		do_ext_phy_settings(base, regs);
-	}
+	writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
+	writel(regs->sdram_config_init, &emif->emif_sdram_config);
+	do_ext_phy_settings(base, regs);
 
-	/* enable leveling */
 	writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
+	omap5_ddr3_leveling(base, regs);
+}
 
-	ddr3_leveling(base, regs);
+static void ddr3_init(u32 base, const struct emif_regs *regs)
+{
+	if (is_omap54xx())
+		omap5_ddr3_init(base, regs);
+	else
+		dra7_ddr3_init(base, regs);
 }
 
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
@@ -1066,16 +1170,18 @@ static void do_sdram_init(u32 base)
 	 * Changing the timing registers in EMIF can happen(going from one
 	 * OPP to another)
 	 */
-	if (!(in_sdram || warm_reset())) {
-		if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
+	if (!in_sdram && (!warm_reset() || is_dra7xx())) {
+		if (emif_sdram_type(regs->sdram_config) ==
+		    EMIF_SDRAM_TYPE_LPDDR2)
 			lpddr2_init(base, regs);
 		else
 			ddr3_init(base, regs);
 	}
-	if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
+	if (warm_reset() && (emif_sdram_type(regs->sdram_config) ==
+	    EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) {
 		set_lpmode_selfrefresh(base);
 		emif_reset_phy(base);
-		ddr3_leveling(base, regs);
+		omap5_ddr3_leveling(base, regs);
 	}
 
 	/* Write to the shadow registers */
@@ -1294,7 +1400,8 @@ static void do_bug0039_workaround(u32 base)
 void sdram_init(void)
 {
 	u32 in_sdram, size_prog, size_detect;
-	u32 sdram_type = emif_sdram_type();
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
+	u32 sdram_type = emif_sdram_type(emif->emif_sdram_config);
 
 	debug(">>sdram_init()\n");
 

arch/arm/cpu/armv7/omap5/Makefile

@@ -11,3 +11,4 @@ obj-y	+= sdram.o
 obj-y	+= prcm-regs.o
 obj-y	+= hw_data.o
 obj-y	+= abb.o
+obj-$(CONFIG_IODELAY_RECALIBRATION) += dra7xx_iodelay.o

arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c

@@ -0,0 +1,238 @@
+/*
+ * (C) Copyright 2015
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/utils.h>
+#include <asm/arch/dra7xx_iodelay.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mux_dra7xx.h>
+#include <asm/omap_common.h>
+
+static int isolate_io(u32 isolate)
+{
+	if (isolate) {
+		clrsetbits_le32((*ctrl)->control_pbias, SDCARD_PWRDNZ,
+				SDCARD_PWRDNZ);
+		clrsetbits_le32((*ctrl)->control_pbias, SDCARD_BIAS_PWRDNZ,
+				SDCARD_BIAS_PWRDNZ);
+	}
+
+	/* Override control on ISOCLKIN signal to IO pad ring. */
+	clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK,
+			PMCTRL_ISOCLK_OVERRIDE_CTRL);
+	if (!wait_on_value(PMCTRL_ISOCLK_STATUS_MASK, PMCTRL_ISOCLK_STATUS_MASK,
+			   (u32 *)(*prcm)->prm_io_pmctrl, LDELAY))
+		return ERR_DEISOLATE_IO << isolate;
+
+	/* Isolate/Deisolate IO */
+	clrsetbits_le32((*ctrl)->ctrl_core_sma_sw_0, CTRL_ISOLATE_MASK,
+			isolate << CTRL_ISOLATE_SHIFT);
+	/* Dummy read to add delay t > 10ns */
+	readl((*ctrl)->ctrl_core_sma_sw_0);
+
+	/* Return control on ISOCLKIN to hardware */
+	clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK,
+			PMCTRL_ISOCLK_NOT_OVERRIDE_CTRL);
+	if (!wait_on_value(PMCTRL_ISOCLK_STATUS_MASK,
+			   0 << PMCTRL_ISOCLK_STATUS_SHIFT,
+			   (u32 *)(*prcm)->prm_io_pmctrl, LDELAY))
+		return ERR_DEISOLATE_IO << isolate;
+
+	return 0;
+}
+
+static int calibrate_iodelay(u32 base)
+{
+	u32 reg;
+
+	/* Configure REFCLK period */
+	reg = readl(base + CFG_REG_2_OFFSET);
+	reg &= ~CFG_REG_REFCLK_PERIOD_MASK;
+	reg |= CFG_REG_REFCLK_PERIOD;
+	writel(reg, base + CFG_REG_2_OFFSET);
+
+	/* Initiate Calibration */
+	clrsetbits_le32(base + CFG_REG_0_OFFSET, CFG_REG_CALIB_STRT_MASK,
+			CFG_REG_CALIB_STRT << CFG_REG_CALIB_STRT_SHIFT);
+	if (!wait_on_value(CFG_REG_CALIB_STRT_MASK, CFG_REG_CALIB_END,
+			   (u32 *)(base + CFG_REG_0_OFFSET), LDELAY))
+		return ERR_CALIBRATE_IODELAY;
+
+	return 0;
+}
+
+static int update_delay_mechanism(u32 base)
+{
+	/* Initiate the reload of calibrated values. */
+	clrsetbits_le32(base + CFG_REG_0_OFFSET, CFG_REG_ROM_READ_MASK,
+			CFG_REG_ROM_READ_START);
+	if (!wait_on_value(CFG_REG_ROM_READ_MASK, CFG_REG_ROM_READ_END,
+			   (u32 *)(base + CFG_REG_0_OFFSET), LDELAY))
+		return ERR_UPDATE_DELAY;
+
+	return 0;
+}
+
+static u32 calculate_delay(u32 base, u16 offset, u16 den)
+{
+	u16 refclk_period, dly_cnt, ref_cnt;
+	u32 reg, q, r;
+
+	refclk_period = readl(base + CFG_REG_2_OFFSET) &
+			      CFG_REG_REFCLK_PERIOD_MASK;
+
+	reg = readl(base + offset);
+	dly_cnt = (reg & CFG_REG_DLY_CNT_MASK) >> CFG_REG_DLY_CNT_SHIFT;
+	ref_cnt = (reg & CFG_REG_REF_CNT_MASK) >> CFG_REG_REF_CNT_SHIFT;
+
+	if (!dly_cnt || !den)
+		return 0;
+
+	/*
+	 * To avoid overflow and integer truncation, delay value
+	 * is calculated as quotient + remainder.
+	 */
+	q = 5 * ((ref_cnt * refclk_period) / (dly_cnt * den));
+	r = (10 * ((ref_cnt * refclk_period) % (dly_cnt * den))) /
+		(2 * dly_cnt * den);
+
+	return q + r;
+}
+
+static u32 get_cfg_reg(u16 a_delay, u16 g_delay, u32 cpde, u32 fpde)
+{
+	u32 g_delay_coarse, g_delay_fine;
+	u32 a_delay_coarse, a_delay_fine;
+	u32 c_elements, f_elements;
+	u32 total_delay, reg = 0;
+
+	g_delay_coarse = g_delay / 920;
+	g_delay_fine = ((g_delay % 920) * 10) / 60;
+
+	a_delay_coarse = a_delay / cpde;
+	a_delay_fine = ((a_delay % cpde) * 10) / fpde;
+
+	c_elements = g_delay_coarse + a_delay_coarse;
+	f_elements = (g_delay_fine + a_delay_fine) / 10;
+
+	if (f_elements > 22) {
+		total_delay = c_elements * cpde + f_elements * fpde;
+
+		c_elements = total_delay / cpde;
+		f_elements = (total_delay % cpde) / fpde;
+	}
+
+	reg = (c_elements << CFG_X_COARSE_DLY_SHIFT) & CFG_X_COARSE_DLY_MASK;
+	reg |= (f_elements << CFG_X_FINE_DLY_SHIFT) & CFG_X_FINE_DLY_MASK;
+	reg |= CFG_X_SIGNATURE << CFG_X_SIGNATURE_SHIFT;
+	reg |= CFG_X_LOCK << CFG_X_LOCK_SHIFT;
+
+	return reg;
+}
+
+static int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array,
+			   int niodelays)
+{
+	struct iodelay_cfg_entry *iodelay = (struct iodelay_cfg_entry *)array;
+	u32 reg, cpde, fpde, i;
+
+	if (!niodelays)
+		return 0;
+
+	cpde = calculate_delay((*ctrl)->iodelay_config_base, CFG_REG_3_OFFSET,
+			       88);
+	if (!cpde)
+		return ERR_CPDE;
+
+	fpde = calculate_delay((*ctrl)->iodelay_config_base, CFG_REG_4_OFFSET,
+			       264);
+	if (!fpde)
+		return ERR_FPDE;
+
+	for (i = 0; i < niodelays; i++, iodelay++) {
+		reg = get_cfg_reg(iodelay->a_delay, iodelay->g_delay, cpde,
+				  fpde);
+		writel(reg, base + iodelay->offset);
+	}
+
+	return 0;
+}
+
+void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
+			   struct iodelay_cfg_entry const *iodelay,
+			   int niodelays)
+{
+	int ret = 0;
+
+	/* IO recalibration should be done only from SRAM */
+	if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) {
+		puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n");
+		return;
+	}
+
+	/* unlock IODELAY CONFIG registers */
+	writel(CFG_IODELAY_UNLOCK_KEY, (*ctrl)->iodelay_config_base +
+	       CFG_REG_8_OFFSET);
+
+	ret = calibrate_iodelay((*ctrl)->iodelay_config_base);
+	if (ret)
+		goto err;
+
+	ret = isolate_io(ISOLATE_IO);
+	if (ret)
+		goto err;
+
+	ret = update_delay_mechanism((*ctrl)->iodelay_config_base);
+	if (ret)
+		goto err;
+
+	/* Configure Mux settings */
+	do_set_mux32((*ctrl)->control_padconf_core_base, pad, npads);
+
+	/* Configure Manual IO timing modes */
+	ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
+	if (ret)
+		goto err;
+
+	ret = isolate_io(DEISOLATE_IO);
+
+err:
+	/* lock IODELAY CONFIG registers */
+	writel(CFG_IODELAY_LOCK_KEY, (*ctrl)->iodelay_config_base +
+	       CFG_REG_8_OFFSET);
+	/*
+	 * UART cannot be used during IO recalibration sequence as IOs are in
+	 * isolation. So error handling and debug prints are done after
+	 * complete IO delay recalibration sequence
+	 */
+	switch (ret) {
+	case ERR_CALIBRATE_IODELAY:
+		puts("IODELAY: IO delay calibration sequence failed\n");
+		break;
+	case ERR_ISOLATE_IO:
+		puts("IODELAY: Isolation of Device IOs failed\n");
+		break;
+	case ERR_UPDATE_DELAY:
+		puts("IODELAY: Delay mechanism update with new calibrated values failed\n");
+		break;
+	case ERR_DEISOLATE_IO:
+		puts("IODELAY: De-isolation of Device IOs failed\n");
+		break;
+	case ERR_CPDE:
+		puts("IODELAY: CPDE calculation failed\n");
+		break;
+	case ERR_FPDE:
+		puts("IODELAY: FPDE calculation failed\n");
+		break;
+	default:
+		debug("IODELAY: IO delay recalibration successfully completed\n");
+	}
+}

arch/arm/cpu/armv7/omap5/hw_data.c

@@ -534,6 +534,9 @@ void enable_basic_clocks(void)
 void enable_basic_uboot_clocks(void)
 {
 	u32 const clk_domains_essential[] = {
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+		(*prcm)->cm_ipu_clkstctrl,
+#endif
 		0
 	};
 
@@ -547,7 +550,11 @@ void enable_basic_uboot_clocks(void)
 		(*prcm)->cm_l4per_i2c2_clkctrl,
 		(*prcm)->cm_l4per_i2c3_clkctrl,
 		(*prcm)->cm_l4per_i2c4_clkctrl,
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+		(*prcm)->cm_ipu_i2c5_clkctrl,
+#else
 		(*prcm)->cm_l4per_i2c5_clkctrl,
+#endif
 		(*prcm)->cm_l3init_hsusbhost_clkctrl,
 		(*prcm)->cm_l3init_fsusb_clkctrl,
 		0
@@ -592,8 +599,8 @@ const struct ctrl_ioregs ioregs_dra7xx_es1 = {
 	.ctrl_ddrch = 0x40404040,
 	.ctrl_lpddr2ch = 0x40404040,
 	.ctrl_ddr3ch = 0x80808080,
-	.ctrl_ddrio_0 = 0xA2084210,
-	.ctrl_ddrio_1 = 0x84210840,
+	.ctrl_ddrio_0 = 0x00094A40,
+	.ctrl_ddrio_1 = 0x04A52000,
 	.ctrl_ddrio_2 = 0x84210000,
 	.ctrl_emif_sdram_config_ext = 0x0001C1A7,
 	.ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
@@ -604,8 +611,8 @@ const struct ctrl_ioregs ioregs_dra72x_es1 = {
 	.ctrl_ddrch = 0x40404040,
 	.ctrl_lpddr2ch = 0x40404040,
 	.ctrl_ddr3ch = 0x60606080,
-	.ctrl_ddrio_0 = 0xA2084210,
-	.ctrl_ddrio_1 = 0x84210840,
+	.ctrl_ddrio_0 = 0x00094A40,
+	.ctrl_ddrio_1 = 0x04A52000,
 	.ctrl_ddrio_2 = 0x84210000,
 	.ctrl_emif_sdram_config_ext = 0x0001C1A7,
 	.ctrl_emif_sdram_config_ext_final = 0x0001C1A7,

arch/arm/cpu/armv7/omap5/hwinit.c

@@ -40,6 +40,15 @@ static struct gpio_bank gpio_bank_54xx[8] = {
 
 const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
 
+void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size)
+{
+	int i;
+	struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
+
+	for (i = 0; i < size; i++, pad++)
+		writel(pad->val, base + pad->offset);
+}
+
 #ifdef CONFIG_SPL_BUILD
 /* LPDDR2 specific IO settings */
 static void io_settings_lpddr2(void)
@@ -75,16 +84,20 @@ static void io_settings_ddr3(void)
 
 	writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
 	writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
-	writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
+
+	if (!is_dra7xx()) {
+		writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
+		writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
+	}
 
 	/* omap5432 does not use lpddr2 */
 	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
-	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
 
 	writel(ioregs->ctrl_emif_sdram_config_ext,
 	       (*ctrl)->control_emif1_sdram_config_ext);
-	writel(ioregs->ctrl_emif_sdram_config_ext,
-	       (*ctrl)->control_emif2_sdram_config_ext);
+	if (!is_dra72x())
+		writel(ioregs->ctrl_emif_sdram_config_ext,
+		       (*ctrl)->control_emif2_sdram_config_ext);
 
 	if (is_omap54xx()) {
 		/* Disable DLL select */
@@ -109,6 +122,7 @@ static void io_settings_ddr3(void)
 void do_io_settings(void)
 {
 	u32 io_settings = 0, mask = 0;
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
 
 	/* Impedance settings EMMC, C2C 1,2, hsi2 */
 	mask = (ds_mask << 2) | (ds_mask << 8) |
@@ -164,7 +178,7 @@ void do_io_settings(void)
 		       (sc_fast << 17) | (sc_fast << 14);
 	writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
 
-	if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
+	if (emif_sdram_type(emif->emif_sdram_config) == EMIF_SDRAM_TYPE_LPDDR2)
 		io_settings_lpddr2();
 	else
 		io_settings_ddr3();

arch/arm/cpu/armv7/omap5/prcm-regs.c

@@ -378,6 +378,7 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
 	.control_status				= 0x4A002134,
 	.control_phy_power_usb			= 0x4A002370,
 	.control_phy_power_sata			= 0x4A002374,
+	.ctrl_core_sma_sw_0			= 0x4A0023FC,
 	.control_core_mac_id_0_lo		= 0x4A002514,
 	.control_core_mac_id_0_hi		= 0x4A002518,
 	.control_core_mac_id_1_lo		= 0x4A00251C,
@@ -457,6 +458,7 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
 	.control_efuse_3			= 0x4AE0C5D0,
 	.control_efuse_4			= 0x4AE0C5D4,
 	.control_efuse_13			= 0x4AE0C5F0,
+	.iodelay_config_base			= 0x4844A000,
 };
 
 struct prcm_regs const omap5_es2_prcm = {
@@ -815,6 +817,10 @@ struct prcm_regs const dra7xx_prcm = {
 	.cm_dsp_clkstctrl			= 0x4a005400,
 	.cm_dsp_dsp_clkctrl			= 0x4a005420,
 
+	/* cm IPU */
+	.cm_ipu_clkstctrl			= 0x4a005540,
+	.cm_ipu_i2c5_clkctrl			= 0x4a005578,
+
 	/* prm irqstatus regs */
 	.prm_irqstatus_mpu_2			= 0x4ae06014,
 
@@ -976,6 +982,7 @@ struct prcm_regs const dra7xx_prcm = {
 	.prm_rstctrl				= 0x4ae07d00,
 	.prm_rstst				= 0x4ae07d04,
 	.prm_rsttime				= 0x4ae07d08,
+	.prm_io_pmctrl				= 0x4ae07d20,
 	.prm_vc_val_bypass			= 0x4ae07da0,
 	.prm_vc_cfg_i2c_mode			= 0x4ae07db4,
 	.prm_vc_cfg_i2c_clk			= 0x4ae07db8,

arch/arm/cpu/armv7/omap5/sdram.c

@@ -146,18 +146,18 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
 	.sdram_tim1                     = 0xCCCF36B3,
 	.sdram_tim2                     = 0x308F7FDA,
 	.sdram_tim3                     = 0x027F88A8,
-	.read_idle_ctrl                 = 0x00050001,
+	.read_idle_ctrl                 = 0x00050000,
 	.zq_config                      = 0x0007190B,
 	.temp_alert_config              = 0x00000000,
-	.emif_ddr_phy_ctlr_1_init       = 0x0E24400A,
-	.emif_ddr_phy_ctlr_1            = 0x0E24400A,
+	.emif_ddr_phy_ctlr_1_init       = 0x0024400B,
+	.emif_ddr_phy_ctlr_1            = 0x0E24400B,
 	.emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 	.emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 	.emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 	.emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
 	.emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
-	.emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 	.emif_rd_wr_lvl_ctl             = 0x00000000,
 	.emif_rd_wr_exec_thresh         = 0x00000305
 };
@@ -171,18 +171,18 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
 	.sdram_tim1                     = 0xCCCF36B3,
 	.sdram_tim2                     = 0x308F7FDA,
 	.sdram_tim3                     = 0x027F88A8,
-	.read_idle_ctrl                 = 0x00050001,
+	.read_idle_ctrl                 = 0x00050000,
 	.zq_config                      = 0x0007190B,
 	.temp_alert_config              = 0x00000000,
-	.emif_ddr_phy_ctlr_1_init       = 0x0E24400A,
-	.emif_ddr_phy_ctlr_1            = 0x0E24400A,
+	.emif_ddr_phy_ctlr_1_init       = 0x0024400B,
+	.emif_ddr_phy_ctlr_1            = 0x0E24400B,
 	.emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 	.emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 	.emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 	.emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
 	.emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
-	.emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 	.emif_rd_wr_lvl_ctl             = 0x00000000,
 	.emif_rd_wr_exec_thresh         = 0x00000305
 };
@@ -191,15 +191,15 @@ const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
 	.sdram_config_init              = 0x61862B32,
 	.sdram_config                   = 0x61862B32,
 	.sdram_config2			= 0x08000000,
-	.ref_ctrl                       = 0x0000493E,
+	.ref_ctrl                       = 0x0000514C,
 	.ref_ctrl_final			= 0x0000144A,
 	.sdram_tim1                     = 0xD113781C,
-	.sdram_tim2                     = 0x308F7FE3,
-	.sdram_tim3                     = 0x009F86A8,
+	.sdram_tim2                     = 0x305A7FDA,
+	.sdram_tim3                     = 0x409F86A8,
 	.read_idle_ctrl                 = 0x00050000,
-	.zq_config                      = 0x0007190B,
+	.zq_config                      = 0x5007190B,
 	.temp_alert_config              = 0x00000000,
-	.emif_ddr_phy_ctlr_1_init       = 0x0E24400D,
+	.emif_ddr_phy_ctlr_1_init       = 0x0024400D,
 	.emif_ddr_phy_ctlr_1            = 0x0E24400D,
 	.emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 	.emif_ddr_ext_phy_ctrl_2        = 0x00A400A4,
@@ -207,7 +207,7 @@ const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
 	.emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
 	.emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
 	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
-	.emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 	.emif_rd_wr_lvl_ctl             = 0x00000000,
 	.emif_rd_wr_exec_thresh         = 0x00000305
 };
@@ -421,8 +421,14 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
 	0x0
 };
 
+/* Ext phy ctrl 1-35 regs */
 const u32
 dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
+	0x10040100,
+	0x00910091,
+	0x00950095,
+	0x009B009B,
+	0x009E009E,
 	0x00980098,
 	0x00340034,
 	0x00350035,
@@ -441,17 +447,28 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
 	0x00500050,
 	0x00000000,
 	0x00600020,
-	0x40010080,
+	0x40011080,
 	0x08102040,
 	0x0,
 	0x0,
 	0x0,
 	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
 	0x0
 };
 
+/* Ext phy ctrl 1-35 regs */
 const u32
 dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
+	0x10040100,
+	0x00910091,
+	0x00950095,
+	0x009B009B,
+	0x009E009E,
 	0x00980098,
 	0x00330033,
 	0x00330033,
@@ -470,17 +487,28 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
 	0x00500050,
 	0x00000000,
 	0x00600020,
-	0x40010080,
+	0x40011080,
 	0x08102040,
 	0x0,
 	0x0,
 	0x0,
 	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
 	0x0
 };
 
+/* Ext phy ctrl 1-35 regs */
 const u32
 dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = {
+	0x10040100,
+	0x00A400A4,
+	0x00A900A9,
+	0x00B000B0,
+	0x00B000B0,
 	0x00A400A4,
 	0x00390039,
 	0x00320032,
@@ -505,6 +533,11 @@ dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = {
 	0x0,
 	0x0,
 	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
 	0x0
 };
 
@@ -562,7 +595,7 @@ void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
 	*regs = &mr_regs;
 }
 
-void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
+static void do_ext_phy_settings_omap5(u32 base, const struct emif_regs *regs)
 {
 	u32 *ext_phy_ctrl_base = 0;
 	u32 *emif_ext_phy_ctrl_base = 0;
@@ -601,6 +634,58 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
 	}
 }
 
+static void do_ext_phy_settings_dra7(u32 base, const struct emif_regs *regs)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+	u32 *emif_ext_phy_ctrl_base = 0;
+	u32 emif_nr;
+	const u32 *ext_phy_ctrl_const_regs;
+	u32 i, hw_leveling, size;
+
+	emif_nr = (base == EMIF1_BASE) ? 1 : 2;
+
+	hw_leveling = regs->emif_rd_wr_lvl_rmp_ctl >> EMIF_REG_RDWRLVL_EN_SHIFT;
+
+	emif_ext_phy_ctrl_base = (u32 *)&(emif->emif_ddr_ext_phy_ctrl_1);
+
+	emif_get_ext_phy_ctrl_const_regs(emif_nr,
+					 &ext_phy_ctrl_const_regs, &size);
+
+	writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[0]);
+	writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[1]);
+
+	if (!hw_leveling) {
+		/*
+		 * Copy the predefined PHY register values
+		 * in case of sw leveling
+		 */
+		for (i = 1; i < 25; i++) {
+			writel(ext_phy_ctrl_const_regs[i],
+			       &emif_ext_phy_ctrl_base[i * 2]);
+			writel(ext_phy_ctrl_const_regs[i],
+			       &emif_ext_phy_ctrl_base[i * 2 + 1]);
+		}
+	} else {
+		/*
+		 * Write the init value for HW levling to occur
+		 */
+		for (i = 21; i < 35; i++) {
+			writel(ext_phy_ctrl_const_regs[i],
+			       &emif_ext_phy_ctrl_base[i * 2]);
+			writel(ext_phy_ctrl_const_regs[i],
+			       &emif_ext_phy_ctrl_base[i * 2 + 1]);
+		}
+	}
+}
+
+void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
+{
+	if (is_omap54xx())
+		do_ext_phy_settings_omap5(base, regs);
+	else
+		do_ext_phy_settings_dra7(base, regs);
+}
+
 #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
 	.max_freq	= 532000000,

arch/arm/cpu/armv7/s5pc1xx/Kconfig

@@ -7,10 +7,12 @@ choice
 config TARGET_S5P_GONI
 	bool "S5P Goni board"
 	select OF_CONTROL
+	select SPL_DISABLE_OF_CONTROL
 
 config TARGET_SMDKC100
 	bool "Support smdkc100 board"
 	select OF_CONTROL
+	select SPL_DISABLE_OF_CONTROL
 
 endchoice
 

arch/arm/cpu/armv7/start.S

@@ -22,10 +22,9 @@
  *
  * Startup Code (reset vector)
  *
- * do important init only if we don't start from memory!
- * setup Memory and board specific bits prior to relocation.
- * relocate armboot to ram
- * setup stack
+ * Do important init only if we don't start from memory!
+ * Setup memory and board specific bits prior to relocation.
+ * Relocate armboot to ram. Setup stack.
  *
  *************************************************************************/
 

arch/arm/cpu/armv7/sunxi/board.c

@@ -45,11 +45,11 @@ static int gpio_init(void)
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
 #endif
 #if defined(CONFIG_MACH_SUN8I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0_TX);
-	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0_RX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
 #else
-	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0_TX);
-	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0_RX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
 #endif
 	sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
 #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
@@ -64,6 +64,10 @@ static int gpio_init(void)
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
 	sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
+	sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
@@ -119,20 +123,11 @@ void s_init(void)
 #ifdef CONFIG_SPL_BUILD
 /* The sunxi internal brom will try to loader external bootloader
  * from mmc0, nand flash, mmc2.
- *
- * Unfortunately we can't check how SPL was loaded so assume it's
- * always the first SD/MMC controller, unless it was explicitly
- * stated that SPL is on nand flash.
+ * Unfortunately we can't check how SPL was loaded so assume
+ * it's always the first SD/MMC controller
  */
 u32 spl_boot_device(void)
 {
-#if defined(CONFIG_SPL_NAND_SUPPORT)
-	/*
-	 * This is compile time configuration informing SPL, that it
-	 * was loaded from nand flash.
-	 */
-	return BOOT_DEVICE_NAND;
-#else
 	/*
 	 * When booting from the SD card, the "eGON.BT0" signature is expected
 	 * to be found in memory at the address 0x0004 (see the "mksunxiboot"
@@ -153,7 +148,6 @@ u32 spl_boot_device(void)
 		return BOOT_DEVICE_MMC1;
 	else
 		return BOOT_DEVICE_BOARD;
-#endif
 }
 
 /* No confirmation data available in SPL yet. Hardcode bootmode */
@@ -202,6 +196,7 @@ void reset_cpu(ulong addr)
 	writel(WDT_CFG_RESET, &wdog->cfg);
 	writel(WDT_MODE_EN, &wdog->mode);
 	writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
+	while (1) { }
 #endif
 }
 
@@ -223,6 +218,7 @@ int cpu_eth_init(bd_t *bis)
 	__maybe_unused int rc;
 
 #ifdef CONFIG_MACPWR
+	gpio_request(CONFIG_MACPWR, "macpwr");
 	gpio_direction_output(CONFIG_MACPWR, 1);
 	mdelay(200);
 #endif

arch/arm/cpu/armv7/sunxi/rsb.c

@@ -60,11 +60,12 @@ int rsb_init(void)
 	struct sunxi_rsb_reg * const rsb =
 		(struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
 
-	rsb_cfg_io();
-
 	/* Enable RSB and PIO clk, and de-assert their resets */
 	prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
 
+	/* Setup external pins */
+	rsb_cfg_io();
+
 	writel(RSB_CTRL_SOFT_RST, &rsb->ctrl);
 	rsb_set_clk();
 

arch/arm/dts/Makefile

@@ -128,7 +128,8 @@ dtb-$(CONFIG_MACH_SUN8I_A23) += \
 dtb-$(CONFIG_MACH_SUN8I_A33) += \
 	sun8i-a33-et-q8-v1.6.dtb \
 	sun8i-a33-ga10h-v1.1.dtb \
-	sun8i-a33-ippo-q8h-v1.2-lcd1024x600.dtb
+	sun8i-a33-ippo-q8h-v1.2.dtb \
+	sun8i-a33-sinlinx-sina33.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
 	sun9i-a80-optimus.dtb \
 	sun9i-a80-cubieboard4.dtb
@@ -138,7 +139,8 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
 
 targets += $(dtb-y)
 
-DTC_FLAGS += -R 4 -p 0x1000
+# Add any required device tree compiler flags here
+DTC_FLAGS +=
 
 PHONY += dtbs
 dtbs: $(addprefix $(obj)/, $(dtb-y))

arch/arm/dts/exynos4412-odroid.dts

@@ -43,140 +43,102 @@
 
 			voltage-regulators {
 				ldo1_reg: ldo1 {
-					regulator-compatible = "LDO1";
 					regulator-name = "VDD_ALIVE_1.0V";
 					regulator-min-microvolt = <1000000>;
 					regulator-max-microvolt = <1000000>;
 				};
 
 				ldo2_reg: ldo2 {
-					regulator-compatible = "LDO2";
 					regulator-name = "VDDQ_VM1M2_1.2V";
 					regulator-min-microvolt = <1200000>;
 					regulator-max-microvolt = <1200000>;
 				};
 
 				ldo3_reg: ldo3 {
-					regulator-compatible = "LDO3";
 					regulator-name = "VCC_1.8V_AP";
 					regulator-min-microvolt = <1800000>;
 					regulator-max-microvolt = <1800000>;
 				};
 
 				ldo4_reg: ldo4 {
-					regulator-compatible = "LDO4";
 					regulator-name = "VDDQ_MMC2_2.8V";
 					regulator-min-microvolt = <2800000>;
 					regulator-max-microvolt = <2800000>;
 				};
 
 				ldo5_reg: ldo5 {
-					regulator-compatible = "LDO5";
 					regulator-name = "VDDQ_MMC0/1/3_1.8V";
 					regulator-min-microvolt = <1800000>;
 					regulator-max-microvolt = <1800000>;
 				};
 
 				ldo6_reg: ldo6 {
-					regulator-compatible = "LDO6";
 					regulator-name = "VMPLL_1.0V";
 					regulator-min-microvolt = <1100000>;
 					regulator-max-microvolt = <1100000>;
 				};
 
 				ldo7_reg: ldo7 {
-					regulator-compatible = "LDO7";
 					regulator-name = "VPLL_1.1V";
 					regulator-min-microvolt = <1100000>;
 					regulator-max-microvolt = <1100000>;
 				};
 
 				ldo8_reg: ldo8 {
-					regulator-compatible = "LDO8";
 					regulator-name = "VDD_MIPI/HDMI_1.0V";
 					regulator-min-microvolt = <1000000>;
 					regulator-max-microvolt = <1000000>;
 				};
 
-				ldo9_reg: ldo9 {
-					regulator-compatible = "LDO9";
-					regulator-name = "nc";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-				};
-
 				ldo10_reg: ldo10 {
-					regulator-compatible = "LDO10";
 					regulator-name = "VDD_MIPI/HDMI_1.8V";
 					regulator-min-microvolt = <1800000>;
 					regulator-max-microvolt = <1800000>;
 				};
 
 				ldo11_reg: ldo11 {
-					regulator-compatible = "LDO11";
 					regulator-name = "VDD_ABB1_1.8V";
 					regulator-min-microvolt = <1800000>;
 					regulator-max-microvolt = <1800000>;
 				};
 
 				ldo12_reg: ldo12 {
-					regulator-compatible = "LDO12";
 					regulator-name = "VDD_UOTG_3.0V";
 					regulator-min-microvolt = <3000000>;
 					regulator-max-microvolt = <3000000>;
 				};
 
 				ldo13_reg: ldo13 {
-					regulator-compatible = "LDO13";
 					regulator-name = "VDD_C2C_1.8V";
 					regulator-min-microvolt = <1800000>;
 					regulator-max-microvolt = <1800000>;
 				};
 
 				ldo14_reg: ldo14 {
-					regulator-compatible = "LDO14";
 					regulator-name = "VDD_ABB02_1.8V";
 					regulator-min-microvolt = <1800000>;
 					regulator-max-microvolt = <1800000>;
 				};
 
 				ldo15_reg: ldo15 {
-					regulator-compatible = "LDO15";
 					regulator-name = "VDD_HSIC/OTG_1.0V";
 					regulator-min-microvolt = <1000000>;
 					regulator-max-microvolt = <1000000>;
 				};
 
 				ldo16_reg: ldo16 {
-					regulator-compatible = "LDO16";
 					regulator-name = "VDD_HSIC_1.8V";
 					regulator-min-microvolt = <1800000>;
 					regulator-max-microvolt = <1800000>;
 				};
 
 				ldo17_reg: ldo17 {
-					regulator-compatible = "LDO17";
 					regulator-name = "VDDQ_CAM_1.2V";
 					regulator-min-microvolt = <1200000>;
 					regulator-max-microvolt = <1200000>;
 				};
 
-				ldo18_reg: ldo18 {
-					regulator-compatible = "LDO18";
-					regulator-name = "nc";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-				};
-
-				ldo19_reg: ldo19 {
-					regulator-compatible = "LDO19";
-					regulator-name = "nc";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-				};
-
 				ldo20_reg: ldo20 {
-					regulator-compatible = "LDO20";
 					regulator-name = "VDDQ_EMMC_1.8V";
 					regulator-min-microvolt = <1800000>;
 					regulator-max-microvolt = <1800000>;
@@ -185,7 +147,6 @@
 				};
 
 				ldo21_reg: ldo21 {
-					regulator-compatible = "LDO21";
 					regulator-name = "TFLASH_2.8V";
 					regulator-min-microvolt = <2800000>;
 					regulator-max-microvolt = <2800000>;
@@ -194,7 +155,6 @@
 				};
 
 				ldo22_reg: ldo22 {
-					regulator-compatible = "LDO22";
 					regulator-name = "VDDQ_EMMC_2.8V";
 					regulator-min-microvolt = <2800000>;
 					regulator-max-microvolt = <2800000>;
@@ -202,20 +162,6 @@
 					regulator-boot-on;
 				};
 
-				ldo23_reg: ldo23 {
-					regulator-compatible = "LDO23";
-					regulator-name = "nc";
-					regulator-min-microvolt = <3300000>;
-					regulator-max-microvolt = <3300000>;
-				};
-
-				ldo24_reg: ldo24 {
-					regulator-compatible = "LDO24";
-					regulator-name = "nc";
-					regulator-min-microvolt = <3000000>;
-					regulator-max-microvolt = <3000000>;
-				};
-
 				ldo25_reg: ldo25 {
 					regulator-compatible = "LDO25";
 					regulator-name = "VDDQ_LCD_3.0V";
@@ -223,75 +169,53 @@
 					regulator-max-microvolt = <3000000>;
 				};
 
-				ldo26_reg: ldo26 {
-					regulator-compatible = "LDO26";
-					regulator-name = "nc";
-					regulator-min-microvolt = <3000000>;
-					regulator-max-microvolt = <3000000>;
-				};
-
-				buck1_reg: buck@1 {
-					regulator-compatible = "BUCK1";
+				buck1_reg: buck1 {
 					regulator-name = "VDD_MIF_1.0V";
 					regulator-min-microvolt = <8500000>;
 					regulator-max-microvolt = <1100000>;
 				};
 
-				buck2_reg: buck@2 {
-					regulator-compatible = "BUCK2";
+				buck2_reg: buck2 {
 					regulator-name = "VDD_ARM_1.0V";
 					regulator-min-microvolt = <850000>;
 					regulator-max-microvolt = <1500000>;
 				};
 
 				buck3_reg: buck3 {
-					regulator-compatible = "BUCK3";
 					regulator-name = "VDD_INT_1.1V";
 					regulator-min-microvolt = <850000>;
 					regulator-max-microvolt = <1150000>;
 				};
 
 				buck4_reg: buck4 {
-					regulator-compatible = "BUCK4";
 					regulator-name = "VDD_G3D_1.0V";
 					regulator-min-microvolt = <850000>;
 					regulator-max-microvolt = <1150000>;
 				};
 
 				buck5_reg: buck5 {
-					regulator-compatible = "BUCK5";
 					regulator-name = "VDDQ_AP_1.2V";
 					regulator-min-microvolt = <1200000>;
 					regulator-max-microvolt = <1200000>;
 				};
 
 				buck6_reg: buck6 {
-					regulator-compatible = "BUCK6";
 					regulator-name = "VCC_INL1/7_1.35V";
 					regulator-min-microvolt = <1350000>;
 					regulator-max-microvolt = <1350000>;
 				};
 
 				buck7_reg: buck7 {
-					regulator-compatible = "BUCK7";
 					regulator-name = "VCC_INL2/3/5_2.0V";
 					regulator-min-microvolt = <2000000>;
 					regulator-max-microvolt = <2000000>;
 				};
 
 				buck8_reg: buck8 {
-					regulator-compatible = "BUCK8";
 					regulator-name = "VCC_P3V3_2.85V";
 					regulator-min-microvolt = <2850000>;
 					regulator-max-microvolt = <3300000>;
 				};
-
-				buck9_reg: buck9 {
-					regulator-compatible = "BUCK9";
-					regulator-name = "nc";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <1200000>;
-				};
 			};
 		};
 	};

arch/arm/dts/ls1021a-qds.dts

@@ -30,7 +30,7 @@
 	dspiflash: at45db021d@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "spi-flash";
+		compatible = "atmel,dataflash";
 		spi-max-frequency = <16000000>;
 		spi-cpol;
 		spi-cpha;

arch/arm/dts/sun8i-a23-a33.dtsi

@@ -366,6 +366,16 @@
 				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 			};
 
+			mmc2_8bit_pins: mmc2_8bit {
+				allwinner,pins = "PC5", "PC6", "PC8",
+						 "PC9", "PC10", "PC11",
+						 "PC12", "PC13", "PC14",
+						 "PC15";
+				allwinner,function = "mmc2";
+				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
 			i2c0_pins_a: i2c0@0 {
 				allwinner,pins = "PH2", "PH3";
 				allwinner,function = "i2c0";

arch/arm/dts/sun8i-a33-sinlinx-sina33.dts

@@ -0,0 +1,129 @@
+/*
+ * Copyright 2015 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a33.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+	model = "Sinlinx SinA33";
+	compatible = "sinlinx,sina33", "allwinner,sun8i-a33";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&lradc {
+	vref-supply = <&reg_vcc3v0>;
+	status = "okay";
+
+	button@200 {
+		label = "Volume Up";
+		linux,code = <KEY_VOLUMEUP>;
+		channel = <0>;
+		voltage = <191011>;
+	};
+
+	button@400 {
+		label = "Volume Down";
+		linux,code = <KEY_VOLUMEDOWN>;
+		channel = <0>;
+		voltage = <391304>;
+	};
+
+	button@600 {
+		label = "Home";
+		linux,code = <KEY_HOME>;
+		channel = <0>;
+		voltage = <600000>;
+	};
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_sina33>;
+	vmmc-supply = <&reg_vcc3v0>;
+	bus-width = <4>;
+	cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
+	cd-inverted;
+	status = "okay";
+};
+
+&mmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_8bit_pins>;
+	vmmc-supply = <&reg_vcc3v0>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&mmc2_8bit_pins {
+	/* eMMC is missing pull-ups */
+	allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
+
+&pio {
+	mmc0_cd_pin_sina33: mmc0_cd_pin@0 {
+		allwinner,pins = "PB4";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_b>;
+	status = "okay";
+};

arch/arm/dts/sun8i-a33.dtsi

@@ -86,4 +86,12 @@
 	compatible = "allwinner,sun8i-a33-pinctrl";
 	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 		     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+
+	uart0_pins_b: uart0@1 {
+		allwinner,pins = "PB0", "PB1";
+		allwinner,function = "uart0";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+
 };

arch/arm/dts/tegra124-nyan-big.dts

@@ -163,12 +163,15 @@
 
 	spi@7000d400 {
 		status = "okay";
+		spi-deactivate-delay = <200>;
+		spi-max-frequency = <3000000>;
 
 		cros_ec: cros-ec@0 {
 			compatible = "google,cros-ec-spi";
 			spi-max-frequency = <3000000>;
 			interrupt-parent = <&gpio>;
 			interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
+			ec-interrupt = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
 			reg = <0>;
 
 			google,cros-ec-spi-msg-delay = <2000>;

arch/arm/dts/uniphier-ph1-ld4-ref.dts

@@ -5,7 +5,7 @@
  * Copyright (C) 2015      Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
 /dts-v1/;

arch/arm/dts/uniphier-ph1-ld4.dtsi

@@ -1,11 +1,9 @@
 /*
  * Device Tree Source for UniPhier PH1-LD4 SoC
  *
- * Copyright (C) 2014-2015 Panasonic Corporation
- * Copyright (C) 2015      Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
 /include/ "skeleton.dtsi"
@@ -24,11 +22,26 @@
 		};
 	};
 
+	clocks {
+		arm_timer_clk: arm_timer_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <50000000>;
+		};
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;
+		interrupt-parent = <&intc>;
+
+		extbus: extbus {
+			compatible = "simple-bus";
+			#address-cells = <2>;
+			#size-cells = <1>;
+		};
 
 		uart0: serial@54006800 {
 			compatible = "socionext,uniphier-uart";
@@ -94,6 +107,12 @@
 			status = "disabled";
 		};
 
+		system-bus-controller-misc@59800000 {
+			compatible = "socionext,uniphier-system-bus-controller-misc",
+				     "syscon";
+			reg = <0x59800000 0x2000>;
+		};
+
 		usb0: usb@5a800100 {
 			compatible = "socionext,uniphier-ehci", "generic-ehci";
 			status = "disabled";
@@ -112,6 +131,28 @@
 			reg = <0x5a820100 0x100>;
 		};
 
+		timer@60000200 {
+			compatible = "arm,cortex-a9-global-timer";
+			reg = <0x60000200 0x20>;
+			interrupts = <1 11 0x104>;
+			clocks = <&arm_timer_clk>;
+		};
+
+		timer@60000600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0x60000600 0x20>;
+			interrupts = <1 13 0x104>;
+			clocks = <&arm_timer_clk>;
+		};
+
+		intc: interrupt-controller@60001000 {
+			compatible = "arm,cortex-a9-gic";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			reg = <0x60001000 0x1000>,
+			      <0x60000100 0x100>;
+		};
+
 		nand: nand@68000000 {
 			compatible = "denali,denali-nand-dt";
 			reg = <0x68000000 0x20>, <0x68100000 0x1000>;

arch/arm/dts/uniphier-ph1-pro4-ref.dts

@@ -5,7 +5,7 @@
  * Copyright (C) 2015      Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
 /dts-v1/;

arch/arm/dts/uniphier-ph1-pro4.dtsi

@@ -1,11 +1,9 @@
 /*
  * Device Tree Source for UniPhier PH1-Pro4 SoC
  *
- * Copyright (C) 2014-2015 Panasonic Corporation
- * Copyright (C) 2015      Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
 /include/ "skeleton.dtsi"
@@ -16,6 +14,7 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		enable-method = "socionext,uniphier-smp";
 
 		cpu@0 {
 			device_type = "cpu";
@@ -30,11 +29,26 @@
 		};
 	};
 
+	clocks {
+		arm_timer_clk: arm_timer_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <50000000>;
+		};
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;
+		interrupt-parent = <&intc>;
+
+		extbus: extbus {
+			compatible = "simple-bus";
+			#address-cells = <2>;
+			#size-cells = <1>;
+		};
 
 		uart0: serial@54006800 {
 			compatible = "socionext,uniphier-uart";
@@ -120,6 +134,12 @@
 			status = "ok";
 		};
 
+		system-bus-controller-misc@59800000 {
+			compatible = "socionext,uniphier-system-bus-controller-misc",
+				     "syscon";
+			reg = <0x59800000 0x2000>;
+		};
+
 		usb2: usb@5a800100 {
 			compatible = "socionext,uniphier-ehci", "generic-ehci";
 			status = "disabled";
@@ -144,6 +164,28 @@
 			reg = <0x65c00000 0x100>;
 		};
 
+		timer@60000200 {
+			compatible = "arm,cortex-a9-global-timer";
+			reg = <0x60000200 0x20>;
+			interrupts = <1 11 0x304>;
+			clocks = <&arm_timer_clk>;
+		};
+
+		timer@60000600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0x60000600 0x20>;
+			interrupts = <1 13 0x304>;
+			clocks = <&arm_timer_clk>;
+		};
+
+		intc: interrupt-controller@60001000 {
+			compatible = "arm,cortex-a9-gic";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			reg = <0x60001000 0x1000>,
+			      <0x60000100 0x100>;
+		};
+
 		nand: nand@68000000 {
 			compatible = "denali,denali-nand-dt";
 			reg = <0x68000000 0x20>, <0x68100000 0x1000>;

arch/arm/dts/uniphier-ph1-sld3-ref.dts

@@ -5,7 +5,7 @@
  * Copyright (C) 2015      Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
 /dts-v1/;

arch/arm/dts/uniphier-ph1-sld3.dtsi

@@ -1,11 +1,9 @@
 /*
  * Device Tree Source for UniPhier PH1-sLD3 SoC
  *
- * Copyright (C) 2014-2015 Panasonic Corporation
- * Copyright (C) 2015      Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
 /include/ "skeleton.dtsi"
@@ -16,6 +14,7 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		enable-method = "socionext,uniphier-smp";
 
 		cpu@0 {
 			device_type = "cpu";
@@ -30,11 +29,48 @@
 		};
 	};
 
+	clocks {
+		arm_timer_clk: arm_timer_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <50000000>;
+		};
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;
+		interrupt-parent = <&intc>;
+
+		extbus: extbus {
+			compatible = "simple-bus";
+			#address-cells = <2>;
+			#size-cells = <1>;
+		};
+
+		timer@20000200 {
+			compatible = "arm,cortex-a9-global-timer";
+			reg = <0x20000200 0x20>;
+			interrupts = <1 11 0x304>;
+			clocks = <&arm_timer_clk>;
+		};
+
+		timer@20000600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0x20000600 0x20>;
+			interrupts = <1 13 0x304>;
+			clocks = <&arm_timer_clk>;
+		};
+
+		intc: interrupt-controller@20001000 {
+			compatible = "arm,cortex-a9-gic";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			reg = <0x20001000 0x1000>,
+			      <0x20000100 0x100>;
+		};
 
 		uart0: serial@54006800 {
 			compatible = "socionext,uniphier-uart";
@@ -93,6 +129,12 @@
 			status = "disabled";
 		};
 
+		system-bus-controller-misc@59800000 {
+			compatible = "socionext,uniphier-system-bus-controller-misc",
+				     "syscon";
+			reg = <0x59800000 0x2000>;
+		};
+
 		usb0: usb@5a800100 {
 			compatible = "socionext,uniphier-ehci", "generic-ehci";
 			status = "disabled";

arch/arm/dts/uniphier-ph1-sld8-ref.dts

@@ -5,7 +5,7 @@
  * Copyright (C) 2015      Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
 /dts-v1/;

arch/arm/dts/uniphier-ph1-sld8.dtsi

@@ -1,11 +1,9 @@
 /*
  * Device Tree Source for UniPhier PH1-sLD8 SoC
  *
- * Copyright (C) 2014-2015 Panasonic Corporation
- * Copyright (C) 2015      Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
 /include/ "skeleton.dtsi"
@@ -24,11 +22,26 @@
 		};
 	};
 
+	clocks {
+		arm_timer_clk: arm_timer_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <50000000>;
+		};
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;
+		interrupt-parent = <&intc>;
+
+		extbus: extbus {
+			compatible = "simple-bus";
+			#address-cells = <2>;
+			#size-cells = <1>;
+		};
 
 		uart0: serial@54006800 {
 			compatible = "socionext,uniphier-uart";
@@ -94,6 +107,12 @@
 			status = "disabled";
 		};
 
+		system-bus-controller-misc@59800000 {
+			compatible = "socionext,uniphier-system-bus-controller-misc",
+				     "syscon";
+			reg = <0x59800000 0x2000>;
+		};
+
 		usb0: usb@5a800100 {
 			compatible = "socionext,uniphier-ehci", "generic-ehci";
 			status = "disabled";
@@ -112,6 +131,28 @@
 			reg = <0x5a820100 0x100>;
 		};
 
+		timer@60000200 {
+			compatible = "arm,cortex-a9-global-timer";
+			reg = <0x60000200 0x20>;
+			interrupts = <1 11 0x104>;
+			clocks = <&arm_timer_clk>;
+		};
+
+		timer@60000600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0x60000600 0x20>;
+			interrupts = <1 13 0x104>;
+			clocks = <&arm_timer_clk>;
+		};
+
+		intc: interrupt-controller@60001000 {
+			compatible = "arm,cortex-a9-gic";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			reg = <0x60001000 0x1000>,
+			      <0x60000100 0x100>;
+		};
+
 		nand: nand@68000000 {
 			compatible = "denali,denali-nand-dt";
 			reg = <0x68000000 0x20>, <0x68100000 0x1000>;

arch/arm/dts/uniphier-ref-daughter.dtsi

@@ -1,11 +1,9 @@
 /*
  * Device Tree Source for UniPhier Reference Daughter Board
  *
- * Copyright (C) 2014-2015 Panasonic Corporation
- * Copyright (C) 2015      Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
 &i2c0 {

arch/arm/dts/zynq-7000.dtsi

@@ -109,6 +109,32 @@
 			interrupts = <0 50 4>;
 		};
 
+		spi0: spi@e0006000 {
+			compatible = "xlnx,zynq-spi";
+			reg = <0xe0006000 0x1000>;
+			status = "disabled";
+			interrupt-parent = <&intc>;
+			interrupts = <0 26 4>;
+			clocks = <&clkc 25>, <&clkc 34>;
+			clock-names = "ref_clk", "pclk";
+			spi-max-frequency = <166666700>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		spi1: spi@e0007000 {
+			compatible = "xlnx,zynq-spi";
+			reg = <0xe0007000 0x1000>;
+			status = "disabled";
+			interrupt-parent = <&intc>;
+			interrupts = <0 49 4>;
+			clocks = <&clkc 26>, <&clkc 35>;
+			clock-names = "ref_clk", "pclk";
+			spi-max-frequency = <166666700>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		gem0: ethernet@e000b000 {
 			compatible = "cdns,gem";
 			reg = <0xe000b000 0x4000>;

arch/arm/dts/zynq-zc770-xm010.dts

@@ -14,6 +14,7 @@
 
 	aliases {
 		serial0 = &uart1;
+		spi1 = &spi1;
 	};
 
 	memory {
@@ -21,3 +22,7 @@
 		reg = <0 0x40000000>;
 	};
 };
+
+&spi1 {
+	status = "okay";
+};

arch/arm/imx-common/timer.c

@@ -44,8 +44,8 @@ static inline int gpt_has_clk_source_osc(void)
 {
 #if defined(CONFIG_MX6)
 	if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
-	     (is_soc_rev(CHIP_REV_1_0) > 0)) || is_cpu_type(MXC_CPU_MX6DL) ||
-	      is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX))
+	    (soc_rev() > CHIP_REV_1_0)) || is_cpu_type(MXC_CPU_MX6DL) ||
+	     is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX))
 		return 1;
 
 	return 0;

arch/arm/include/asm/arch-exynos/cpu.h

@@ -167,6 +167,7 @@
 #define EXYNOS5420_USB_HOST_EHCI_BASE	0x12110000
 #define EXYNOS5420_MMC_BASE		0x12200000
 #define EXYNOS5420_SROMC_BASE		0x12250000
+#define EXYNOS5420_USB3PHY_BASE	0x12500000
 #define EXYNOS5420_UART_BASE		0x12C00000
 #define EXYNOS5420_I2C_BASE		0x12C60000
 #define EXYNOS5420_I2C_8910_BASE	0x12E00000
@@ -187,7 +188,6 @@
 #define EXYNOS5420_FIMD_BASE		DEVICE_NOT_AVAILABLE
 #define EXYNOS5420_ADC_BASE		DEVICE_NOT_AVAILABLE
 #define EXYNOS5420_MODEM_BASE		DEVICE_NOT_AVAILABLE
-#define EXYNOS5420_USB3PHY_BASE		DEVICE_NOT_AVAILABLE
 #define EXYNOS5420_USB_HOST_XHCI_BASE	DEVICE_NOT_AVAILABLE
 
 

arch/arm/include/asm/arch-mx5/imx-regs.h

@@ -9,6 +9,8 @@
 
 #define ARCH_MXC
 
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
 #if defined(CONFIG_MX51)
 #define IRAM_BASE_ADDR		0x1FFE0000	/* internal ram */
 #define IPU_SOC_BASE_ADDR	0x40000000

arch/arm/include/asm/arch-mx6/imx-regs.h

@@ -312,6 +312,7 @@
 #define CHIP_REV_1_0                 0x10
 #define CHIP_REV_1_2                 0x12
 #define CHIP_REV_1_5                 0x15
+#define CHIP_REV_2_0                 0x20
 #ifndef CONFIG_MX6SX
 #define IRAM_SIZE                    0x00040000
 #else

arch/arm/include/asm/arch-mx6/sys_proto.h

@@ -12,7 +12,7 @@
 #include "../arch-imx/cpu.h"
 
 #define soc_rev() (get_cpu_rev() & 0xFF)
-#define is_soc_rev(rev)        (soc_rev() - rev)
+#define is_soc_rev(rev) (soc_rev() == rev)
 
 u32 get_nr_cpus(void);
 u32 get_cpu_rev(void);
@@ -20,7 +20,7 @@ u32 get_cpu_speed_grade_hz(void);
 u32 get_cpu_temp_grade(int *minc, int *maxc);
 
 /* returns MXC_CPU_ value */
-#define cpu_type(rev) (((rev) >> 12)&0xff)
+#define cpu_type(rev) (((rev) >> 12) & 0xff)
 
 /* both macros return/take MXC_CPU_ constants */
 #define get_cpu_type()	(cpu_type(get_cpu_rev()))
@@ -30,6 +30,10 @@ const char *get_imx_type(u32 imxtype);
 unsigned imx_ddr_size(void);
 void set_chipselect_size(int const);
 
+#define is_mx6dqp() ((is_cpu_type(MXC_CPU_MX6Q) || \
+		     is_cpu_type(MXC_CPU_MX6D)) && \
+		     (soc_rev() >= CHIP_REV_2_0))
+
 /*
  * Initializes on-chip ethernet controllers.
  * to override, implement board_eth_init()

arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h

@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2015
+ * Texas Instruments Incorporated
+ *
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DRA7_IODELAY_H_
+#define _DRA7_IODELAY_H_
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+
+/* CONFIG_REG_0 */
+#define CFG_REG_0_OFFSET		0xC
+#define CFG_REG_ROM_READ_SHIFT		1
+#define CFG_REG_ROM_READ_MASK		(1 << 1)
+#define CFG_REG_CALIB_STRT_SHIFT	0
+#define CFG_REG_CALIB_STRT_MASK		(1 << 0)
+#define CFG_REG_CALIB_STRT		1
+#define CFG_REG_CALIB_END		0
+#define CFG_REG_ROM_READ_START		(1 << 1)
+#define CFG_REG_ROM_READ_END		(0 << 1)
+
+/* CONFIG_REG_2 */
+#define CFG_REG_2_OFFSET		0x14
+#define CFG_REG_REFCLK_PERIOD_SHIFT	0
+#define CFG_REG_REFCLK_PERIOD_MASK	(0xFFFF << 0)
+#define CFG_REG_REFCLK_PERIOD		0x2EF
+
+/* CONFIG_REG_8 */
+#define CFG_REG_8_OFFSET		0x2C
+#define CFG_IODELAY_UNLOCK_KEY		0x0000AAAA
+#define CFG_IODELAY_LOCK_KEY		0x0000AAAB
+
+/* CONFIG_REG_3/4 */
+#define CFG_REG_3_OFFSET	0x18
+#define CFG_REG_4_OFFSET	0x1C
+#define CFG_REG_DLY_CNT_SHIFT	16
+#define CFG_REG_DLY_CNT_MASK	(0xFFFF << 16)
+#define CFG_REG_REF_CNT_SHIFT	0
+#define CFG_REG_REF_CNT_MASK	(0xFFFF << 0)
+
+/* CTRL_CORE_SMA_SW_0 */
+#define CTRL_ISOLATE_SHIFT		2
+#define CTRL_ISOLATE_MASK		(1 << 2)
+#define ISOLATE_IO			1
+#define DEISOLATE_IO			0
+
+/* PRM_IO_PMCTRL */
+#define PMCTRL_ISOCLK_OVERRIDE_SHIFT	0
+#define PMCTRL_ISOCLK_OVERRIDE_MASK	(1 << 0)
+#define PMCTRL_ISOCLK_STATUS_SHIFT	1
+#define PMCTRL_ISOCLK_STATUS_MASK	(1 << 1)
+#define PMCTRL_ISOCLK_OVERRIDE_CTRL	1
+#define PMCTRL_ISOCLK_NOT_OVERRIDE_CTRL	0
+
+#define ERR_CALIBRATE_IODELAY		0x1
+#define ERR_DEISOLATE_IO		0x2
+#define ERR_ISOLATE_IO			0x4
+#define ERR_UPDATE_DELAY		0x8
+#define ERR_CPDE			0x3
+#define ERR_FPDE			0x5
+
+/* CFG_XXX */
+#define CFG_X_SIGNATURE_SHIFT		12
+#define CFG_X_SIGNATURE_MASK		(0x3F << 12)
+#define CFG_X_LOCK_SHIFT		10
+#define CFG_X_LOCK_MASK			(0x1 << 10)
+#define CFG_X_COARSE_DLY_SHIFT		5
+#define CFG_X_COARSE_DLY_MASK		(0x1F << 5)
+#define CFG_X_FINE_DLY_SHIFT		0
+#define CFG_X_FINE_DLY_MASK		(0x1F << 0)
+#define CFG_X_SIGNATURE			0x29
+#define CFG_X_LOCK			1
+
+void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
+			   struct iodelay_cfg_entry const *iodelay,
+			   int niodelays);
+
+#endif

arch/arm/include/asm/arch-omap5/mux_dra7xx.h

@@ -26,6 +26,21 @@
 #define WKEN	(1 << 24)
 #define WKDIS	(0 << 24)
 
+#define PULL_ENA		(0 << 16)
+#define PULL_DIS		(1 << 16)
+#define PULL_UP			(1 << 17)
+#define INPUT_EN		(1 << 18)
+#define SLEWCONTROL		(1 << 19)
+
+/* Active pin states */
+#define PIN_OUTPUT		(0 | PULL_DIS)
+#define PIN_OUTPUT_PULLUP	(PULL_UP)
+#define PIN_OUTPUT_PULLDOWN	(0)
+#define PIN_INPUT		(INPUT_EN | PULL_DIS)
+#define PIN_INPUT_SLEW		(INPUT_EN | SLEWCONTROL)
+#define PIN_INPUT_PULLUP	(PULL_ENA | INPUT_EN | PULL_UP)
+#define PIN_INPUT_PULLDOWN	(PULL_ENA | INPUT_EN)
+
 #define M0	0
 #define M1	1
 #define M2	2
@@ -43,6 +58,28 @@
 #define M14	14
 #define M15	15
 
+#define MODE_SELECT		(1 << 8)
+#define DELAYMODE_SHIFT		4
+
+#define MANUAL_MODE	MODE_SELECT
+
+#define VIRTUAL_MODE0	(MODE_SELECT | (0x0 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE1	(MODE_SELECT | (0x1 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE2	(MODE_SELECT | (0x2 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE3	(MODE_SELECT | (0x3 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE4	(MODE_SELECT | (0x4 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE5	(MODE_SELECT | (0x5 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE6	(MODE_SELECT | (0x6 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE7	(MODE_SELECT | (0x7 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE8	(MODE_SELECT | (0x8 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE9	(MODE_SELECT | (0x9 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE10	(MODE_SELECT | (0xa << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE11	(MODE_SELECT | (0xb << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE12	(MODE_SELECT | (0xc << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE13	(MODE_SELECT | (0xd << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE14	(MODE_SELECT | (0xe << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE15	(MODE_SELECT | (0xf << DELAYMODE_SHIFT))
+
 #define SAFE_MODE	M15
 
 #define GPMC_AD0	0x000

arch/arm/include/asm/arch-omap5/omap.h

@@ -216,27 +216,6 @@ struct s32ktimer {
 #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK	(0x1 << 10)
 #define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK	(0x1f << 0)
 
-/* IO Delay module defines */
-#define CFG_IO_DELAY_BASE		0x4844A000
-#define CFG_IO_DELAY_LOCK		(CFG_IO_DELAY_BASE + 0x02C)
-
-/* CPSW IO Delay registers*/
-#define CFG_RGMII0_TXCTL		(CFG_IO_DELAY_BASE + 0x74C)
-#define CFG_RGMII0_TXD0			(CFG_IO_DELAY_BASE + 0x758)
-#define CFG_RGMII0_TXD1			(CFG_IO_DELAY_BASE + 0x764)
-#define CFG_RGMII0_TXD2			(CFG_IO_DELAY_BASE + 0x770)
-#define CFG_RGMII0_TXD3			(CFG_IO_DELAY_BASE + 0x77C)
-#define CFG_VIN2A_D13			(CFG_IO_DELAY_BASE + 0xA7C)
-#define CFG_VIN2A_D17			(CFG_IO_DELAY_BASE + 0xAAC)
-#define CFG_VIN2A_D16			(CFG_IO_DELAY_BASE + 0xAA0)
-#define CFG_VIN2A_D15			(CFG_IO_DELAY_BASE + 0xA94)
-#define CFG_VIN2A_D14			(CFG_IO_DELAY_BASE + 0xA88)
-
-#define CFG_IO_DELAY_UNLOCK_KEY		0x0000AAAA
-#define CFG_IO_DELAY_LOCK_KEY		0x0000AAAB
-#define CFG_IO_DELAY_ACCESS_PATTERN	0x00029000
-#define CFG_IO_DELAY_LOCK_MASK		0x400
-
 #ifndef __ASSEMBLY__
 struct srcomp_params {
 	s8 divide_factor;
@@ -255,9 +234,5 @@ struct ctrl_ioregs {
 	u32 ctrl_ddr_ctrl_ext_0;
 };
 
-struct io_delay {
-	u32 addr;
-	u32 dly;
-};
 #endif /* __ASSEMBLY__ */
 #endif

arch/arm/include/asm/arch-omap5/sys_proto.h

@@ -18,6 +18,18 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/*
+ * Structure for Iodelay configuration registers.
+ * Theoretical max for g_delay is 21560 ps.
+ * Theoretical max for a_delay is 1/3rd of g_delay max.
+ * So using u16 for both a/g_delay.
+ */
+struct iodelay_cfg_entry {
+	u16 offset;
+	u16 a_delay;
+	u16 g_delay;
+};
+
 struct pad_conf_entry {
 	u32 offset;
 	u32 val;
@@ -32,6 +44,7 @@ void gpmc_init(void);
 void watchdog_init(void);
 u32 get_device_type(void);
 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
+void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size);
 void set_muxconf_regs_essential(void);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);

arch/arm/include/asm/arch-sunxi/gpio.h

@@ -156,8 +156,7 @@ enum sunxi_gpio_number {
 #define SUN4I_GPB_UART0		2
 #define SUN5I_GPB_UART0		2
 #define SUN8I_GPB_UART2		2
-
-#define SUNXI_GPC_NAND		2
+#define SUN8I_A33_GPB_UART0	3
 
 #define SUNXI_GPC_SDC2		3
 #define SUN6I_GPC_SDC3		4

arch/arm/include/asm/arch-sunxi/nand.h

@@ -1,67 +0,0 @@
-/*
- * (C) Copyright 2015 Roy Spliet <rspliet@ultimaker.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _SUNXI_NAND_H
-#define _SUNXI_NAND_H
-
-#include <linux/types.h>
-
-struct sunxi_nand
-{
-	u32 ctl;		/* 0x000 Configure and control */
-	u32 st;			/* 0x004 Status information */
-	u32 intr;		/* 0x008 Interrupt control */
-	u32 timing_ctl;		/* 0x00C Timing control */
-	u32 timing_cfg;		/* 0x010 Timing configure */
-	u32 addr_low;		/* 0x014 Low word address */
-	u32 addr_high;		/* 0x018 High word address */
-	u32 block_num;		/* 0x01C Data block number */
-	u32 data_cnt;		/* 0x020 Data counter for transfer */
-	u32 cmd;		/* 0x024 NDFC commands */
-	u32 rcmd_set;		/* 0x028 Read command set for vendor NAND mem */
-	u32 wcmd_set;		/* 0x02C Write command set */
-	u32 io_data;		/* 0x030 IO data */
-	u32 ecc_ctl;		/* 0x034 ECC configure and control */
-	u32 ecc_st;		/* 0x038 ECC status and operation info */
-	u32 efr;		/* 0x03C Enhanced feature */
-	u32 err_cnt0;		/* 0x040 Corrected error bit counter 0 */
-	u32 err_cnt1;		/* 0x044 Corrected error bit counter 1 */
-	u32 user_data[16];	/* 0x050[16] User data field */
-	u32 efnand_st;		/* 0x090 EFNAND status */
-	u32 res0[3];
-	u32 spare_area;		/* 0x0A0 Spare area configure */
-	u32 pat_id;		/* 0x0A4 Pattern ID register */
-	u32 rdata_sta_ctl;	/* 0x0A8 Read data status control */
-	u32 rdata_sta_0;	/* 0x0AC Read data status 0 */
-	u32 rdata_sta_1;	/* 0x0B0 Read data status 1 */
-	u32 res1[3];
-	u32 mdma_addr;		/* 0x0C0 MBUS DMA Address */
-	u32 mdma_cnt;		/* 0x0C4 MBUS DMA data counter */
-};
-
-#define SUNXI_NAND_CTL_EN			(1 << 0)
-#define SUNXI_NAND_CTL_RST			(1 << 1)
-#define SUNXI_NAND_CTL_PAGE_SIZE(a)		((fls(a) - 11) << 8)
-#define SUNXI_NAND_CTL_RAM_METHOD_DMA		(1 << 14)
-
-#define SUNXI_NAND_ST_CMD_INT			(1 << 1)
-#define SUNXI_NAND_ST_DMA_INT			(1 << 2)
-#define SUNXI_NAND_ST_FIFO_FULL			(1 << 3)
-
-#define SUNXI_NAND_CMD_ADDR_CYCLES(a)		((a - 1) << 16);
-#define SUNXI_NAND_CMD_SEND_CMD1		(1 << 22)
-#define SUNXI_NAND_CMD_WAIT_FLAG		(1 << 23)
-#define SUNXI_NAND_CMD_ORDER_INTERLEAVE		0
-#define SUNXI_NAND_CMD_ORDER_SEQ		(1 << 25)
-
-#define SUNXI_NAND_ECC_CTL_ECC_EN		(1 << 0)
-#define SUNXI_NAND_ECC_CTL_PIPELINE		(1 << 3)
-#define SUNXI_NAND_ECC_CTL_BS_512B		(1 << 5)
-#define SUNXI_NAND_ECC_CTL_RND_EN		(1 << 9)
-#define SUNXI_NAND_ECC_CTL_MODE(a)		((a) << 12)
-#define SUNXI_NAND_ECC_CTL_RND_SEED(a)		((a) << 16)
-
-#endif /* _SUNXI_NAND_H */

arch/arm/include/asm/arch-tegra/clock.h

@@ -336,4 +336,12 @@ void arch_timer_init(void);
 
 void tegra30_set_up_pllp(void);
 
+/**
+ * Enable output clock for external peripherals
+ *
+ * @param clk_id	Clock ID to output (1, 2 or 3)
+ * @return 0 if OK. -ve on error
+ */
+int clock_external_output(int clk_id);
+
 #endif  /* _TEGRA_CLOCK_H_ */

arch/arm/include/asm/arch-tegra/sys_proto.h

@@ -25,4 +25,11 @@ int tegra_board_id(void);
  */
 int tegra_lcd_pmic_init(int board_id);
 
+/**
+ * nvidia_board_init() - perform any board-specific init
+ *
+ * @return 0 if OK, -ve on error
+ */
+int nvidia_board_init(void);
+
 #endif

arch/arm/include/asm/arch-tegra124/clock-tables.h

@@ -285,12 +285,12 @@ enum periph_id {
 	/* 184 */
 	PERIPH_ID_GPU,
 	PERIPH_ID_AMX1,
-	PERIPH_ID_X_RESERVED26,
-	PERIPH_ID_X_RESERVED27,
-	PERIPH_ID_X_RESERVED28,
-	PERIPH_ID_X_RESERVED29,
-	PERIPH_ID_X_RESERVED30,
-	PERIPH_ID_X_RESERVED31,
+	PERIPH_ID_AFC5,
+	PERIPH_ID_AFC4,
+	PERIPH_ID_AFC3,
+	PERIPH_ID_AFC2,
+	PERIPH_ID_AFC1,
+	PERIPH_ID_AFC0,
 
 	PERIPH_ID_COUNT,
 	PERIPH_ID_NONE = -1,

arch/arm/include/asm/arch-tegra124/flow.h

@@ -26,6 +26,12 @@ struct flow_ctlr {
 	u32 cpu_pwr_csr;	/* offset 0x38 */
 	u32 mpid;		/* offset 0x3c */
 	u32 ram_repair;		/* offset 0x40 */
+	u32 flow_dbg_sel;	/* offset 0x44 */
+	u32 flow_dbg_cnt0;	/* offset 0x48 */
+	u32 flow_dbg_cnt1;	/* offset 0x4c */
+	u32 flow_dbg_qual;	/* offset 0x50 */
+	u32 flow_ctlr_spare;	/* offset 0x54 */
+	u32 ram_repair_cluster1;/* offset 0x58 */
 };
 
 /* HALT_COP_EVENTS_0, 0x04 */
@@ -43,4 +49,10 @@ struct flow_ctlr {
 #define CSR_WAIT_WFI_SHIFT	8
 #define CSR_PWR_OFF_STS		(1 << 16)
 
+/* RAM_REPAIR, 0x40, 0x58 */
+enum {
+	RAM_REPAIR_REQ = 0x1 << 0,
+	RAM_REPAIR_STS = 0x1 << 1,
+};
+
 #endif	/*  _TEGRA124_FLOW_H_ */

arch/arm/include/asm/emif.h

@@ -44,6 +44,8 @@
 #define EMIF_REG_DUAL_CLK_MODE_MASK			(1 << 30)
 #define EMIF_REG_FAST_INIT_SHIFT			29
 #define EMIF_REG_FAST_INIT_MASK			(1 << 29)
+#define EMIF_REG_LEVLING_TO_SHIFT		4
+#define EMIF_REG_LEVELING_TO_MASK		(7 << 4)
 #define EMIF_REG_PHY_DLL_READY_SHIFT		2
 #define EMIF_REG_PHY_DLL_READY_MASK			(1 << 2)
 
@@ -509,6 +511,13 @@
 #define EMIF_REG_RDWRLVLINC_RMP_WIN_SHIFT	0
 #define EMIF_REG_RDWRLVLINC_RMP_WIN_MASK	(0x1FFF << 0)
 
+/* EMIF_PHY_CTRL_36 */
+#define EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR	(1 << 8)
+
+#define PHY_RDDQS_RATIO_REGS		5
+#define PHY_FIFO_WE_SLAVE_RATIO_REGS	5
+#define PHY_REG_WR_DQ_SLAVE_RATIO_REGS	10
+
 /*Leveling Fields */
 #define DDR3_WR_LVL_INT		0x73
 #define DDR3_RD_LVL_INT		0x33
@@ -1200,12 +1209,10 @@ static inline u32 get_emif_rev(u32 base)
  * which is typically the case. So it is sufficient to get
  * SDRAM type from EMIF1.
  */
-static inline u32 emif_sdram_type(void)
+static inline u32 emif_sdram_type(u32 sdram_config)
 {
-	struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
-
-	return (readl(&emif->emif_sdram_config) &
-		EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
+	return (sdram_config & EMIF_REG_SDRAM_TYPE_MASK)
+	       >> EMIF_REG_SDRAM_TYPE_SHIFT;
 }
 
 /* assert macros */
@@ -1235,6 +1242,5 @@ extern u32 *const T_den;
 #endif
 
 void config_data_eye_leveling_samples(u32 emif_base);
-u32 emif_sdram_type(void);
 const struct read_write_regs *get_bug_regs(u32 *iterations);
 #endif

arch/arm/include/asm/omap_common.h

@@ -313,6 +313,7 @@ struct prcm_regs {
 	u32 prm_rstctrl;
 	u32 prm_rstst;
 	u32 prm_rsttime;
+	u32 prm_io_pmctrl;
 	u32 prm_vc_val_bypass;
 	u32 prm_vc_cfg_i2c_mode;
 	u32 prm_vc_cfg_i2c_clk;
@@ -344,6 +345,10 @@ struct prcm_regs {
 	/* GMAC Clk Ctrl */
 	u32 cm_gmac_gmac_clkctrl;
 	u32 cm_gmac_clkstctrl;
+
+	/* IPU */
+	u32 cm_ipu_clkstctrl;
+	u32 cm_ipu_i2c5_clkctrl;
 };
 
 struct omap_sys_ctrl_regs {
@@ -455,6 +460,8 @@ struct omap_sys_ctrl_regs {
 	u32 control_efuse_12;
 	u32 control_efuse_13;
 	u32 control_padconf_wkup_base;
+	u32 iodelay_config_base;
+	u32 ctrl_core_sma_sw_0;
 };
 
 struct dpll_params {
@@ -583,6 +590,7 @@ s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
 
 void usb_fake_mac_from_die_id(u32 *id);
 void usb_set_serial_num_from_die_id(u32 *id);
+void recalibrate_iodelay(void);
 
 void omap_smc1(u32 service, u32 val);
 
@@ -622,12 +630,19 @@ static inline u8 is_omap54xx(void)
 }
 
 #define DRA7XX		0x07000000
+#define DRA72X		0x07200000
 
 static inline u8 is_dra7xx(void)
 {
 	extern u32 *const omap_si_rev;
 	return ((*omap_si_rev & 0xFF000000) == DRA7XX);
 }
+
+static inline u8 is_dra72x(void)
+{
+	extern u32 *const omap_si_rev;
+	return (*omap_si_rev & 0xFFF00000) == DRA72X;
+}
 #endif
 
 /*

arch/arm/include/asm/u-boot.h

@@ -49,8 +49,4 @@ typedef struct bd_info {
 #define IH_ARCH_DEFAULT IH_ARCH_ARM64
 #endif
 
-#if defined(CONFIG_USE_PRIVATE_LIBGCC) && defined(CONFIG_SYS_THUMB_BUILD)
-#error Thumb build does not work with private libgcc.
-#endif
-
 #endif	/* _U_BOOT_H_ */

arch/arm/lib/_ashldi3.S

@@ -4,6 +4,8 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <linux/linkage.h>
+
 #ifdef __ARMEB__
 #define al r1
 #define ah r0
@@ -13,9 +15,8 @@
 #endif
 
 .globl __ashldi3
-.globl	__aeabi_llsl
 __ashldi3:
-__aeabi_llsl:
+ENTRY(__aeabi_llsl)
 
 	subs	r3, r2, #32
 	rsb	ip, r2, #32
@@ -24,3 +25,4 @@ __aeabi_llsl:
 	orrmi	ah, ah, al, lsr ip
 	mov	al, al, lsl r2
 	mov	pc, lr
+ENDPROC(__aeabi_llsl)

arch/arm/lib/_ashrdi3.S

@@ -4,6 +4,8 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <linux/linkage.h>
+
 #ifdef __ARMEB__
 #define al r1
 #define ah r0
@@ -13,9 +15,8 @@
 #endif
 
 .globl __ashrdi3
-.globl __aeabi_lasr
 __ashrdi3:
-__aeabi_lasr:
+ENTRY(__aeabi_lasr)
 
 	subs	r3, r2, #32
 	rsb	ip, r2, #32
@@ -24,3 +25,4 @@ __aeabi_lasr:
 	orrmi	al, al, ah, lsl ip
 	mov	ah, ah, asr r2
 	mov	pc, lr
+ENDPROC(__aeabi_lasr)

arch/arm/lib/_divsi3.S

@@ -1,3 +1,5 @@
+#include <linux/linkage.h>
+
 .macro ARM_DIV_BODY dividend, divisor, result, curbit
 
 #if __LINUX_ARM_ARCH__ >= 5
@@ -95,9 +97,8 @@
 
 	.align	5
 .globl __divsi3
-.globl __aeabi_idiv
 __divsi3:
-__aeabi_idiv:
+ENTRY(__aeabi_idiv)
 	cmp	r1, #0
 	eor	ip, r0, r1			@ save the sign of the result.
 	beq	Ldiv0
@@ -139,3 +140,4 @@ Ldiv0:
 	bl	__div0
 	mov	r0, #0			@ About as wrong as it could be.
 	ldr	pc, [sp], #4
+ENDPROC(__aeabi_idiv)

arch/arm/lib/_lshrdi3.S

@@ -4,6 +4,8 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <linux/linkage.h>
+
 #ifdef __ARMEB__
 #define al r1
 #define ah r0
@@ -13,9 +15,8 @@
 #endif
 
 .globl __lshrdi3
-.globl __aeabi_llsr
 __lshrdi3:
-__aeabi_llsr:
+ENTRY(__aeabi_llsr)
 
 	subs	r3, r2, #32
 	rsb	ip, r2, #32
@@ -24,3 +25,4 @@ __aeabi_llsr:
 	orrmi	al, al, ah, lsl ip
 	mov	ah, ah, lsr r2
 	mov	pc, lr
+ENDPROC(__aeabi_llsr)

arch/arm/lib/_modsi3.S

@@ -1,3 +1,5 @@
+#include <linux/linkage.h>
+
 .macro ARM_MOD_BODY dividend, divisor, order, spare
 
 #if __LINUX_ARM_ARCH__ >= 5
@@ -69,8 +71,7 @@
 .endm
 
 	.align	5
-.globl __modsi3
-__modsi3:
+ENTRY(__modsi3)
 	cmp	r1, #0
 	beq	Ldiv0
 	rsbmi	r1, r1, #0			@ loops below use unsigned.
@@ -88,7 +89,7 @@ __modsi3:
 10:	cmp	ip, #0
 	rsbmi	r0, r0, #0
 	mov	pc, lr
-
+ENDPROC(__modsi3)
 
 Ldiv0:
 

arch/arm/lib/_udivsi3.S

@@ -1,3 +1,5 @@
+#include <linux/linkage.h>
+
 /* # 1 "libgcc1.S" */
 @ libgcc1 routines for ARM cpu.
 @ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)
@@ -72,8 +74,7 @@ Ldiv0:
 	ldmia	sp!, {pc}
 	.size  __udivsi3       , . -  __udivsi3
 
-.globl __aeabi_uidivmod
-__aeabi_uidivmod:
+ENTRY(__aeabi_uidivmod)
 
 	stmfd	sp!, {r0, r1, ip, lr}
 	bl	__aeabi_uidiv
@@ -81,9 +82,9 @@ __aeabi_uidivmod:
 	mul	r3, r0, r2
 	sub	r1, r1, r3
 	mov	pc, lr
+ENDPROC(__aeabi_uidivmod)
 
-.globl __aeabi_idivmod
-__aeabi_idivmod:
+ENTRY(__aeabi_idivmod)
 
 	stmfd	sp!, {r0, r1, ip, lr}
 	bl	__aeabi_idiv
@@ -91,3 +92,4 @@ __aeabi_idivmod:
 	mul	r3, r0, r2
 	sub	r1, r1, r3
 	mov	pc, lr
+ENDPROC(__aeabi_idivmod)

arch/arm/lib/_umodsi3.S

@@ -1,3 +1,5 @@
+#include <linux/linkage.h>
+
 /* # 1 "libgcc1.S" */
 @ libgcc1 routines for ARM cpu.
 @ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)
@@ -11,10 +13,9 @@ curbit		.req	r3
 /* lr		.req	r14	*/
 /* pc		.req	r15	*/
 	.text
-	.globl	 __umodsi3
 	.type  __umodsi3       ,function
 	.align 0
- __umodsi3      :
+ ENTRY(__umodsi3)
 	cmp	divisor, #0
 	beq	Ldiv0
 	mov	curbit, #1
@@ -86,3 +87,4 @@ Ldiv0:
 /* # 456 "libgcc1.S" */
 /* # 500 "libgcc1.S" */
 /* # 580 "libgcc1.S" */
+ENDPROC(__umodsi3)

arch/arm/mach-bcm283x/Kconfig

@@ -15,9 +15,6 @@ config TARGET_RPI_2
 
 endchoice
 
-config PHYS_TO_BUS
-	default y
-
 config SYS_BOARD
 	default "rpi" if TARGET_RPI
 	default "rpi_2" if TARGET_RPI_2

arch/arm/mach-keystone/clock.c

@@ -246,18 +246,18 @@ static inline u32 read_efuse_bootrom(void)
 }
 #endif
 
-inline int get_max_dev_speed(void)
-{
-	return get_max_speed(read_efuse_bootrom() & 0xffff, dev_speeds);
-}
-
 #ifndef CONFIG_SOC_K2E
 inline int get_max_arm_speed(void)
 {
-	return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, arm_speeds);
+	return get_max_speed(read_efuse_bootrom() & 0xffff, arm_speeds);
 }
 #endif
 
+inline int get_max_dev_speed(void)
+{
+	return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, dev_speeds);
+}
+
 void pass_pll_pa_clk_enable(void)
 {
 	u32 reg;

arch/arm/mach-mvebu/cpu.c

@@ -6,9 +6,13 @@
 
 #include <common.h>
 #include <netdev.h>
+#include <ahci.h>
+#include <linux/mbus.h>
 #include <asm/io.h>
+#include <asm/pl310.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/soc.h>
+#include <sdhci.h>
 
 #define DDR_BASE_CS_OFF(n)	(0x0000 + ((n) << 3))
 #define DDR_SIZE_CS_OFF(n)	(0x0004 + ((n) << 3))
@@ -160,10 +164,17 @@ static void update_sdram_window_sizes(void)
 }
 
 #ifdef CONFIG_ARCH_CPU_INIT
+static void set_cbar(u32 addr)
+{
+	asm("mcr p15, 4, %0, c15, c0" : : "r" (addr));
+}
+
+
 int arch_cpu_init(void)
 {
 	/* Linux expects the internal registers to be at 0xf1000000 */
 	writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
+	set_cbar(SOC_REGS_PHY_BASE + 0xC000);
 
 	/*
 	 * We need to call mvebu_mbus_probe() before calling
@@ -237,9 +248,79 @@ int cpu_eth_init(bd_t *bis)
 }
 #endif
 
+#ifdef CONFIG_MV_SDHCI
+int board_mmc_init(bd_t *bis)
+{
+	mv_sdh_init(MVEBU_SDIO_BASE, 0, 0,
+		    SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SCSI_AHCI_PLAT
+#define AHCI_VENDOR_SPECIFIC_0_ADDR	0xa0
+#define AHCI_VENDOR_SPECIFIC_0_DATA	0xa4
+
+#define AHCI_WINDOW_CTRL(win)		(0x60 + ((win) << 4))
+#define AHCI_WINDOW_BASE(win)		(0x64 + ((win) << 4))
+#define AHCI_WINDOW_SIZE(win)		(0x68 + ((win) << 4))
+
+static void ahci_mvebu_mbus_config(void __iomem *base)
+{
+	const struct mbus_dram_target_info *dram;
+	int i;
+
+	dram = mvebu_mbus_dram_info();
+
+	for (i = 0; i < 4; i++) {
+		writel(0, base + AHCI_WINDOW_CTRL(i));
+		writel(0, base + AHCI_WINDOW_BASE(i));
+		writel(0, base + AHCI_WINDOW_SIZE(i));
+	}
+
+	for (i = 0; i < dram->num_cs; i++) {
+		const struct mbus_dram_window *cs = dram->cs + i;
+
+		writel((cs->mbus_attr << 8) |
+		       (dram->mbus_dram_target_id << 4) | 1,
+		       base + AHCI_WINDOW_CTRL(i));
+		writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i));
+		writel(((cs->size - 1) & 0xffff0000),
+		       base + AHCI_WINDOW_SIZE(i));
+	}
+}
+
+static void ahci_mvebu_regret_option(void __iomem *base)
+{
+	/*
+	 * Enable the regret bit to allow the SATA unit to regret a
+	 * request that didn't receive an acknowlegde and avoid a
+	 * deadlock
+	 */
+	writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR);
+	writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA);
+}
+
+void scsi_init(void)
+{
+	printf("MVEBU SATA INIT\n");
+	ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE);
+	ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE);
+	ahci_init((void __iomem *)MVEBU_SATA0_BASE);
+}
+#endif
+
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
 {
+	struct pl310_regs *const pl310 =
+		(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+
+	/* First disable L2 cache - may still be enable from BootROM */
+	if (mvebu_soc_family() == MVEBU_SOC_A38X)
+		clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
 	/* Avoid problem with e.g. neta ethernet driver */
 	invalidate_dcache_all();
 

arch/arm/mach-mvebu/include/mach/cpu.h

@@ -114,6 +114,8 @@ void mvebu_sdram_size_adjust(enum memory_bank bank);
 int mvebu_mbus_probe(struct mbus_win windows[], int count);
 int mvebu_soc_family(void);
 
+int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);
+
 /*
  * Highspeed SERDES PHY config init, ported from bin_hdr
  * to mainline U-Boot

arch/arm/mach-mvebu/include/mach/gpio.h

@@ -0,0 +1,10 @@
+/*
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#ifndef __MACH_MVEBU_GPIO_H
+#define __MACH_MVEBU_GPIO_H
+
+/* Empty file - sdhci requires this. */
+
+#endif

arch/arm/mach-mvebu/include/mach/soc.h

@@ -49,8 +49,11 @@
 #define MVEBU_EGIGA2_BASE	(MVEBU_REGISTER(0x30000))
 #define MVEBU_EGIGA3_BASE	(MVEBU_REGISTER(0x34000))
 #define MVEBU_REG_PCIE_BASE	(MVEBU_REGISTER(0x40000))
+#define MVEBU_USB20_BASE	(MVEBU_REGISTER(0x58000))
 #define MVEBU_EGIGA0_BASE	(MVEBU_REGISTER(0x70000))
 #define MVEBU_EGIGA1_BASE	(MVEBU_REGISTER(0x74000))
+#define MVEBU_SATA0_BASE	(MVEBU_REGISTER(0xa8000))
+#define MVEBU_SDIO_BASE		(MVEBU_REGISTER(0xd8000))
 
 #define SDRAM_MAX_CS		4
 #define SDRAM_ADDR_MASK		0xFF000000

arch/arm/mach-tegra/Kconfig

@@ -21,12 +21,6 @@ endchoice
 config SYS_MALLOC_F_LEN
 	default 0x1800
 
-config USE_PRIVATE_LIBGCC
-	default y
-
-config SPL_DM
-	default y
-
 source "arch/arm/mach-tegra/tegra20/Kconfig"
 source "arch/arm/mach-tegra/tegra30/Kconfig"
 source "arch/arm/mach-tegra/tegra114/Kconfig"

arch/arm/mach-tegra/board2.c

@@ -107,6 +107,11 @@ __weak int tegra_lcd_pmic_init(int board_it)
 	return 0;
 }
 
+__weak int nvidia_board_init(void)
+{
+	return 0;
+}
+
 /*
  * Routine: board_init
  * Description: Early hardware init.
@@ -156,7 +161,6 @@ int board_init(void)
 
 #ifdef CONFIG_USB_EHCI_TEGRA
 	pin_mux_usb();
-	usb_process_devicetree(gd->fdt_blob);
 #endif
 
 #ifdef CONFIG_LCD
@@ -180,8 +184,7 @@ int board_init(void)
 	/* prepare the WB code to LP0 location */
 	warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
 #endif
-
-	return 0;
+	return nvidia_board_init();
 }
 
 #ifdef CONFIG_BOARD_EARLY_INIT_F

arch/arm/mach-tegra/clock.c

@@ -17,11 +17,13 @@
 /* Tegra SoC common clock control functions */
 
 #include <common.h>
+#include <errno.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/tegra.h>
 #include <asm/arch-tegra/ap.h>
 #include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
 #include <asm/arch-tegra/timer.h>
 #include <div64.h>
 #include <fdtdec.h>
@@ -82,7 +84,7 @@ static struct clk_pll *get_pll(enum clock_id clkid)
 
 	assert(clock_id_is_pll(clkid));
 	if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) {
-		debug("%s: Invalid PLL\n", __func__);
+		debug("%s: Invalid PLL %d\n", __func__, clkid);
 		return NULL;
 	}
 	return &clkrst->crc_pll[clkid];
@@ -118,9 +120,12 @@ int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
 		u32 divp, u32 cpcon, u32 lfcon)
 {
-	struct clk_pll *pll = get_pll(clkid);
+	struct clk_pll *pll = NULL;
 	u32 misc_data, data;
 
+	if (clkid < (enum clock_id)TEGRA_CLK_PLLS)
+		pll = get_pll(clkid);
+
 	/*
 	 * We cheat by treating all PLL (except PLLU) in the same fashion.
 	 * This works only because:
@@ -702,3 +707,18 @@ void tegra30_set_up_pllp(void)
 
 	set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4);
 }
+
+int clock_external_output(int clk_id)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+	if (clk_id >= 1 && clk_id <= 3) {
+		setbits_le32(&pmc->pmc_clk_out_cntrl,
+			     1 << (2 + (clk_id - 1) * 8));
+	} else {
+		printf("%s: Unknown output clock id %d\n", __func__, clk_id);
+		return -EINVAL;
+	}
+
+	return 0;
+}

arch/arm/mach-tegra/powergate.c

@@ -9,7 +9,7 @@
 
 #include <asm/io.h>
 #include <asm/types.h>
-
+#include <asm/arch/flow.h>
 #include <asm/arch/powergate.h>
 #include <asm/arch/tegra.h>
 
@@ -75,11 +75,29 @@ static int tegra_powergate_remove_clamping(enum tegra_powergate id)
 	return 0;
 }
 
+static void tegra_powergate_ram_repair(void)
+{
+#ifdef CONFIG_TEGRA124
+	struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+
+	/* Request RAM repair for cluster 0 and wait until complete */
+	setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ);
+	while (!(readl(&flow->ram_repair) & RAM_REPAIR_STS))
+		;
+
+	/* Same for cluster 1 */
+	setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ);
+	while (!(readl(&flow->ram_repair_cluster1) & RAM_REPAIR_STS))
+		;
+#endif
+}
+
 int tegra_powergate_sequence_power_up(enum tegra_powergate id,
 				      enum periph_id periph)
 {
 	int err;
 
+	tegra_powergate_ram_repair();
 	reset_set_enable(periph, 1);
 
 	err = tegra_powergate_power_on(id);

arch/arm/mach-tegra/tegra124/Kconfig

@@ -10,7 +10,7 @@ config TARGET_JETSON_TK1
 	select CPU_V7_HAS_VIRT if !SPL_BUILD
 
 config TARGET_NYAN_BIG
-	bool "Google/NVIDIA Nyan-big Chrombook"
+	bool "Google/NVIDIA Nyan-big Chromebook"
 	help
 	  Nyan Big is a Tegra124 clamshell board that is very similar
 	  to venice2, but it has a different panel, the sdcard CD and WP

arch/arm/mach-tegra/tegra124/clock.c

@@ -475,7 +475,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
 	PERIPHC_ACTMON,
 
 	/* 120 */
-	NONE(EXTPERIPH1),
+	PERIPHC_EXTPERIPH1,
 	NONE(EXTPERIPH2),
 	NONE(EXTPERIPH3),
 	NONE(OOB),

arch/arm/mach-uniphier/cpu_info.c

@@ -34,6 +34,15 @@ int print_cpuinfo(void)
 	case 0x29:
 		puts("PH1-sLD8 (MN2WS0270)");
 		break;
+	case 0x2A:
+		puts("PH1-Pro5 (MN2WS0300)");
+		break;
+	case 0x2E:
+		puts("ProXstream2 (MN2WS0310)");
+		break;
+	case 0x2F:
+		puts("PH1-LD6b (MN2WS0320)");
+		break;
 	default:
 		printf("Unknown Processor ID (0x%x)\n", revision);
 		return -1;

arch/avr32/Kconfig

@@ -17,35 +17,14 @@ config TARGET_ATNGW100MKII
 config TARGET_ATSTK1002
 	bool "Support atstk1002"
 
-config TARGET_ATSTK1003
-	bool "Support atstk1003"
-
-config TARGET_ATSTK1004
-	bool "Support atstk1004"
-
-config TARGET_ATSTK1006
-	bool "Support atstk1006"
-
-config TARGET_FAVR_32_EZKIT
-	bool "Support favr-32-ezkit"
-
 config TARGET_GRASSHOPPER
 	bool "Support grasshopper"
 
-config TARGET_MIMC200
-	bool "Support mimc200"
-
-config TARGET_HAMMERHEAD
-	bool "Support hammerhead"
-
 endchoice
 
 source "board/atmel/atngw100/Kconfig"
 source "board/atmel/atngw100mkii/Kconfig"
 source "board/atmel/atstk1000/Kconfig"
-source "board/earthlcd/favr-32-ezkit/Kconfig"
 source "board/in-circuit/grasshopper/Kconfig"
-source "board/mimc/mimc200/Kconfig"
-source "board/miromico/hammerhead/Kconfig"
 
 endmenu

arch/avr32/lib/Makefile

@@ -8,9 +8,6 @@
 #
 
 obj-y	+= memset.o
-ifndef CONFIG_SYS_GENERIC_BOARD
-obj-y	+= board.o
-endif
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-y	+= interrupts.o
 obj-y	+= dram_init.o

arch/avr32/lib/board.c

@@ -1,256 +0,0 @@
-/*
- * Copyright (C) 2004-2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <stdio_dev.h>
-#include <version.h>
-#include <net.h>
-
-#ifdef CONFIG_BITBANGMII
-#include <miiphy.h>
-#endif
-
-#include <asm/sections.h>
-#include <asm/arch/mmu.h>
-#include <asm/arch/hardware.h>
-
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-#include <mmc.h>
-#endif
-DECLARE_GLOBAL_DATA_PTR;
-
-unsigned long monitor_flash_len;
-
-__weak void dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size =  gd->ram_size;
-}
-
-/* Weak aliases for optional board functions */
-static int __do_nothing(void)
-{
-	return 0;
-}
-int board_postclk_init(void) __attribute__((weak, alias("__do_nothing")));
-int board_early_init_r(void) __attribute__((weak, alias("__do_nothing")));
-
-static int init_baudrate(void)
-{
-	gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
-	return 0;
-}
-
-static int display_banner (void)
-{
-	printf ("\n\n%s\n\n", version_string);
-	printf ("U-Boot code: %08lx -> %08lx  data: %08lx -> %08lx\n",
-		(unsigned long)_text, (unsigned long)_etext,
-		(unsigned long)_data, (unsigned long)(&__bss_end));
-	return 0;
-}
-
-static int display_dram_config (void)
-{
-	int i;
-
-	puts ("DRAM Configuration:\n");
-
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		printf ("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
-		print_size (gd->bd->bi_dram[i].size, "\n");
-	}
-
-	return 0;
-}
-
-static void display_flash_config (void)
-{
-	puts ("Flash: ");
-	print_size(gd->bd->bi_flashsize, " ");
-	printf("at address 0x%08lx\n", gd->bd->bi_flashstart);
-}
-
-void board_init_f(ulong board_type)
-{
-	gd_t gd_data;
-	gd_t *new_gd;
-	bd_t *bd;
-	unsigned long *new_sp;
-	unsigned long monitor_len;
-	unsigned long monitor_addr;
-	unsigned long addr;
-
-	/* Initialize the global data pointer */
-	memset(&gd_data, 0, sizeof(gd_data));
-	gd = &gd_data;
-
-	/* Perform initialization sequence */
-	board_early_init_f();
-	arch_cpu_init();
-	board_postclk_init();
-	env_init();
-	init_baudrate();
-	serial_init();
-	console_init_f();
-	display_banner();
-	dram_init();
-
-	/* If we have no SDRAM, we can't go on */
-	if (gd->ram_size <= 0)
-		panic("No working SDRAM available\n");
-
-	/*
-	 * Now that we have DRAM mapped and working, we can
-	 * relocate the code and continue running from DRAM.
-	 *
-	 * Reserve memory at end of RAM for (top down in that order):
-	 *  - u-boot image
-	 *  - heap for malloc()
-	 *  - board info struct
-	 *  - global data struct
-	 *  - stack
-	 */
-	addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
-	monitor_len = (char *)(&__bss_end) - _text;
-
-	/*
-	 * Reserve memory for u-boot code, data and bss.
-	 * Round down to next 4 kB limit.
-	 */
-	addr -= monitor_len;
-	addr &= ~(4096UL - 1);
-	monitor_addr = addr;
-
-	/* Reserve memory for malloc() */
-	addr -= CONFIG_SYS_MALLOC_LEN;
-
-#ifdef CONFIG_LCD
-#ifdef CONFIG_FB_ADDR
-	printf("LCD: Frame buffer allocated at preset 0x%08x\n",
-	       CONFIG_FB_ADDR);
-	gd->fb_base = CONFIG_FB_ADDR;
-#else
-	addr = lcd_setmem(addr);
-	printf("LCD: Frame buffer allocated at 0x%08lx\n", addr);
-	gd->fb_base = addr;
-#endif /* CONFIG_FB_ADDR */
-#endif /* CONFIG_LCD */
-
-	/* Allocate a Board Info struct on a word boundary */
-	addr -= sizeof(bd_t);
-	addr &= ~3UL;
-	gd->bd = bd = (bd_t *)addr;
-
-	/* Allocate a new global data copy on a 8-byte boundary. */
-	addr -= sizeof(gd_t);
-	addr &= ~7UL;
-	new_gd = (gd_t *)addr;
-
-	/* And finally, a new, bigger stack. */
-	new_sp = (unsigned long *)addr;
-	gd->start_addr_sp = addr;
-	*(--new_sp) = 0;
-	*(--new_sp) = 0;
-
-	dram_init_banksize();
-
-	memcpy(new_gd, gd, sizeof(gd_t));
-
-	relocate_code((unsigned long)new_sp, new_gd, monitor_addr);
-}
-
-void board_init_r(gd_t *new_gd, ulong dest_addr)
-{
-#ifndef CONFIG_ENV_IS_NOWHERE
-	extern char * env_name_spec;
-#endif
-	bd_t *bd;
-
-	gd = new_gd;
-	bd = gd->bd;
-
-	gd->flags |= GD_FLG_RELOC;
-	gd->reloc_off = dest_addr - CONFIG_SYS_MONITOR_BASE;
-
-	/* Enable the MMU so that we can keep u-boot simple */
-	mmu_init_r(dest_addr);
-
-	board_early_init_r();
-
-	monitor_flash_len = _edata - _text;
-
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
-	/*
-	 * We have to relocate the command table manually
-	 */
-	fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
-			ll_entry_count(cmd_tbl_t, cmd));
-#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
-
-	/* there are some other pointer constants we must deal with */
-#ifndef CONFIG_ENV_IS_NOWHERE
-	env_name_spec += gd->reloc_off;
-#endif
-
-	timer_init();
-
-	/* The malloc area is right below the monitor image in RAM */
-	mem_malloc_init(CONFIG_SYS_MONITOR_BASE + gd->reloc_off -
-			CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN);
-
-	enable_interrupts();
-
-	bd->bi_flashstart = 0;
-	bd->bi_flashsize = 0;
-	bd->bi_flashoffset = 0;
-
-#ifndef CONFIG_SYS_NO_FLASH
-	bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
-	bd->bi_flashsize = flash_init();
-	bd->bi_flashoffset = (unsigned long)_edata - (unsigned long)_text;
-
-	if (bd->bi_flashsize)
-		display_flash_config();
-#endif
-
-	if (bd->bi_dram[0].size)
-		display_dram_config();
-
-	gd->bd->bi_boot_params = malloc(CONFIG_SYS_BOOTPARAMS_LEN);
-	if (!gd->bd->bi_boot_params)
-		puts("WARNING: Cannot allocate space for boot parameters\n");
-
-	/* initialize environment */
-	env_relocate();
-
-	stdio_init();
-	jumptable_init();
-	console_init_r();
-
-	/* Initialize from environment */
-	load_addr = getenv_ulong("loadaddr", 16, load_addr);
-
-#ifdef CONFIG_BITBANGMII
-	bb_miiphy_init();
-#endif
-#if defined(CONFIG_CMD_NET)
-	puts("Net:   ");
-	eth_initialize();
-#endif
-
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-	mmc_initialize(gd->bd);
-#endif
-	for (;;) {
-		main_loop();
-	}
-}

arch/mips/Kconfig

@@ -8,9 +8,6 @@ config SYS_CPU
 	default "mips32" if CPU_MIPS32_R1 || CPU_MIPS32_R2
 	default "mips64" if CPU_MIPS64_R1 || CPU_MIPS64_R2
 
-config USE_PRIVATE_LIBGCC
-	default y
-
 choice
 	prompt "Target select"
 	optional

arch/mips/include/asm/cacheops.h

@@ -18,7 +18,7 @@ static inline void mips_cache(int op, const volatile void *addr)
 #ifdef __GCC_HAVE_BUILTIN_MIPS_CACHE
 	__builtin_mips_cache(op, addr);
 #else
-	__asm__ __volatile__("cache %0, %1" : : "i"(op), "R"(addr))
+	__asm__ __volatile__("cache %0, %1" : : "i"(op), "R"(addr));
 #endif
 }
 

arch/mips/include/asm/io.h

@@ -117,7 +117,7 @@ static inline void set_io_port_base(unsigned long base)
  * Change virtual addresses to physical addresses and vv.
  * These are trivial on the 1:1 Linux/MIPS mapping
  */
-extern inline phys_addr_t virt_to_phys(volatile void * address)
+static inline phys_addr_t virt_to_phys(volatile void * address)
 {
 #ifndef CONFIG_64BIT
 	return CPHYSADDR(address);
@@ -126,7 +126,7 @@ extern inline phys_addr_t virt_to_phys(volatile void * address)
 #endif
 }
 
-extern inline void * phys_to_virt(unsigned long address)
+static inline void * phys_to_virt(unsigned long address)
 {
 #ifndef CONFIG_64BIT
 	return (void *)KSEG0ADDR(address);
@@ -138,7 +138,7 @@ extern inline void * phys_to_virt(unsigned long address)
 /*
  * IO bus memory addresses are also 1:1 with the physical address
  */
-extern inline unsigned long virt_to_bus(volatile void * address)
+static inline unsigned long virt_to_bus(volatile void * address)
 {
 #ifndef CONFIG_64BIT
 	return CPHYSADDR(address);
@@ -147,7 +147,7 @@ extern inline unsigned long virt_to_bus(volatile void * address)
 #endif
 }
 
-extern inline void * bus_to_virt(unsigned long address)
+static inline void * bus_to_virt(unsigned long address)
 {
 #ifndef CONFIG_64BIT
 	return (void *)KSEG0ADDR(address);
@@ -165,12 +165,12 @@ extern unsigned long isa_slot_offset;
 extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
 
 #if 0
-extern inline void *ioremap(unsigned long offset, unsigned long size)
+static inline void *ioremap(unsigned long offset, unsigned long size)
 {
 	return __ioremap(offset, size, _CACHE_UNCACHED);
 }
 
-extern inline void *ioremap_nocache(unsigned long offset, unsigned long size)
+static inline void *ioremap_nocache(unsigned long offset, unsigned long size)
 {
 	return __ioremap(offset, size, _CACHE_UNCACHED);
 }

arch/mips/include/asm/system.h

@@ -22,7 +22,7 @@
 #include <linux/kernel.h>
 #endif
 
-extern __inline__ void
+static __inline__ void
 __sti(void)
 {
 	__asm__ __volatile__(
@@ -46,7 +46,7 @@ __sti(void)
  * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
  * no nops at all.
  */
-extern __inline__ void
+static __inline__ void
 __cli(void)
 {
 	__asm__ __volatile__(
@@ -207,7 +207,7 @@ do { \
  * For 32 and 64 bit operands we can take advantage of ll and sc.
  * FIXME: This doesn't work for R3000 machines.
  */
-extern __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val)
+static __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val)
 {
 #ifdef CONFIG_CPU_HAS_LLSC
 	unsigned long dummy;

arch/sandbox/cpu/cpu.c

@@ -52,6 +52,11 @@ int cleanup_before_linux(void)
 	return 0;
 }
 
+int cleanup_before_linux_select(int flags)
+{
+	return 0;
+}
+
 void *map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
 {
 #ifdef CONFIG_PCI

arch/sh/Kconfig

@@ -125,9 +125,6 @@ config SYS_CPU
 	default "sh3" if CPU_SH3
 	default "sh4" if CPU_SH4
 
-config USE_PRIVATE_LIBGCC
-	default y
-
 source "board/alphaproject/ap_sh4a_4a/Kconfig"
 source "board/espt/Kconfig"
 source "board/mpr2/Kconfig"

arch/x86/Kconfig

@@ -4,12 +4,6 @@ menu "x86 architecture"
 config SYS_ARCH
 	default "x86"
 
-config USE_PRIVATE_LIBGCC
-	default y
-
-config SYS_VSNPRINTF
-	default y
-
 choice
 	prompt "Mainboard vendor"
 	default VENDOR_EMULATION
@@ -335,13 +329,4 @@ config PCIE_ECAM_BASE
 	  assigned to PCI devices - i.e. the memory and prefetch regions, as
 	  passed to pci_set_region().
 
-config BOOTSTAGE
-	default y
-
-config BOOTSTAGE_REPORT
-	default y
-
-config CMD_BOOTSTAGE
-	default y
-
 endmenu

board/Arcturus/ucp1020/Kconfig

@@ -12,14 +12,6 @@ config SYS_CONFIG_NAME
 	string
 	default "UCP1020"
 
-config SPI_FLASH
-	bool
-	default y
-
-config SPI_PCI
-	bool
-	default y
-
 choice
 	prompt "Target image select"
 

board/BuR/common/common.c

@@ -64,14 +64,21 @@ void lcdbacklight(int on)
 	unsigned int pwmfrq = getenv_ulong("ds1_pwmfreq", 10, ~0UL);
 #endif
 	unsigned int tmp;
-
-	struct gptimer *const timerhw = (struct gptimer *)DM_TIMER6_BASE;
+	struct gptimer *timerhw;
 
 	if (on)
 		bright = bright != ~0UL ? bright : 50;
 	else
 		bright = 0;
 
+	switch (driver) {
+	case 2:
+		timerhw = (struct gptimer *)DM_TIMER5_BASE;
+		break;
+	default:
+		timerhw = (struct gptimer *)DM_TIMER6_BASE;
+	}
+
 	switch (driver) {
 	case 0:	/* PMIC LED-Driver */
 		/* brightness level */
@@ -83,7 +90,8 @@ void lcdbacklight(int on)
 				   bright != 0 ? 0x0A : 0x02,
 				   0xFF);
 		break;
-	case 1: /* PWM using timer6 */
+	case 1:
+	case 2: /* PWM using timer */
 		if (pwmfrq != ~0UL) {
 			timerhw->tiocp_cfg = TCFG_RESET;
 			udelay(10);

board/Marvell/db-88f6820-gp/MAINTAINERS

@@ -0,0 +1,6 @@
+DB_88F6820_GP BOARD
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/Marvell/db-88f6820-gp/
+F:	include/configs/db-88f6820-gp.h
+F:	configs/db-88f6820-gp_defconfig