Prepare v2015.07

Signed-off-by: Tom Rini <trini@konsulko.com>

Makefile

@@ -1,7 +1,7 @@
 VERSION = 2015
 PATCHLEVEL = 07
 SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION =
 NAME =
 
 # *DOCUMENTATION*
@@ -565,6 +565,7 @@ KBUILD_CFLAGS += -DBUILD_TAG='"$(BUILD_TAG)"'
 endif
 
 KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector)
+KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks)
 
 KBUILD_CFLAGS	+= -g
 # $(KBUILD_AFLAGS) sets -g, which causes gcc to pass a suitable -g<format>

README

@@ -3079,26 +3079,12 @@ CBFS (Coreboot Filesystem) support
 		Define this option to include a destructive SPI flash
 		test ('sf test').
 
-		CONFIG_SPI_FLASH_BAR		Ban/Extended Addr Reg
-
-		Define this option to use the Bank addr/Extended addr
-		support on SPI flashes which has size > 16Mbytes.
-
 		CONFIG_SF_DUAL_FLASH		Dual flash memories
 
 		Define this option to use dual flash support where two flash
 		memories can be connected with a given cs line.
 		Currently Xilinx Zynq qspi supports these type of connections.
 
-		CONFIG_SPI_FLASH_MTD		spi-flash MTD layer
-
-		Define this option to use mtd support for spi flash layer, this
-		adapter is for translating mtd_read/mtd_write commands into
-		spi_flash_read/spi_flash_write commands. It is not intended to
-		use it within sf_cmd or the SPI flash subsystem. Such an adapter
-		is needed for subsystems like UBI which can only operate on top
-		of the MTD layer.
-
 - SystemACE Support:
 		CONFIG_SYSTEMACE
 

arch/Kconfig

@@ -18,7 +18,7 @@ config ARC
 
 config ARM
 	bool "ARM architecture"
-	select HAVE_PRIVATE_LIBGCC
+	select HAVE_PRIVATE_LIBGCC if !ARM64
 	select HAVE_GENERIC_BOARD
 	select SUPPORT_OF_CONTROL
 

arch/arc/include/asm/arcregs.h

@@ -47,9 +47,12 @@
 #endif
 #define ARC_BCR_DC_BUILD	0x72
 #define ARC_BCR_SLC		0xce
-#define ARC_AUX_SLC_CONTROL	0x903
+#define ARC_AUX_SLC_CONFIG	0x901
+#define ARC_AUX_SLC_CTRL	0x903
 #define ARC_AUX_SLC_FLUSH	0x904
 #define ARC_AUX_SLC_INVALIDATE	0x905
+#define ARC_AUX_SLC_IVDL	0x910
+#define ARC_AUX_SLC_FLDL	0x912
 
 #ifndef __ASSEMBLY__
 /* Accessors for auxiliary registers */

arch/arc/include/asm/cache.h

@@ -29,12 +29,7 @@
 
 #ifndef __ASSEMBLY__
 
-#ifdef CONFIG_ISA_ARCV2
-void slc_enable(void);
-void slc_disable(void);
-void slc_flush(void);
-void slc_invalidate(void);
-#endif
+void cache_init(void);
 
 #endif /* __ASSEMBLY__ */
 

arch/arc/lib/bootm.c

@@ -53,6 +53,9 @@ static void boot_prep_linux(bootm_headers_t *images)
 		hang();
 }
 
+__weak void smp_set_core_boot_addr(unsigned long addr, int corenr) {}
+__weak void smp_kick_all_cpus(void) {}
+
 /* Subcommand: GO */
 static void boot_jump_linux(bootm_headers_t *images, int flag)
 {
@@ -80,6 +83,9 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
 		r2 = (unsigned int)getenv("bootargs");
 	}
 
+	smp_set_core_boot_addr((unsigned long)kernel_entry, -1);
+	smp_kick_all_cpus();
+
 	if (!fake)
 		kernel_entry(r0, 0, r2);
 }

arch/arc/lib/cache.c

@@ -5,9 +5,13 @@
  */
 
 #include <config.h>
+#include <linux/compiler.h>
+#include <linux/kernel.h>
 #include <asm/arcregs.h>
 #include <asm/cache.h>
 
+#define CACHE_LINE_MASK		(~(CONFIG_SYS_CACHELINE_SIZE - 1))
+
 /* Bit values in IC_CTRL */
 #define IC_CTRL_CACHE_DISABLE	(1 << 0)
 
@@ -18,60 +22,186 @@
 #define CACHE_VER_NUM_MASK	0xF
 #define SLC_CTRL_SB		(1 << 2)
 
+#define OP_INV		0x1
+#define OP_FLUSH	0x2
+#define OP_INV_IC	0x3
+
+#ifdef CONFIG_ISA_ARCV2
+/*
+ * By default that variable will fall into .bss section.
+ * But .bss section is not relocated and so it will be initilized before
+ * relocation but will be used after being zeroed.
+ */
+int slc_line_sz __section(".data");
+int slc_exists __section(".data");
+
+static unsigned int __before_slc_op(const int op)
+{
+	unsigned int reg = reg;
+
+	if (op == OP_INV) {
+		/*
+		 * IM is set by default and implies Flush-n-inv
+		 * Clear it here for vanilla inv
+		 */
+		reg = read_aux_reg(ARC_AUX_SLC_CTRL);
+		write_aux_reg(ARC_AUX_SLC_CTRL, reg & ~DC_CTRL_INV_MODE_FLUSH);
+	}
+
+	return reg;
+}
+
+static void __after_slc_op(const int op, unsigned int reg)
+{
+	if (op & OP_FLUSH)	/* flush / flush-n-inv both wait */
+		while (read_aux_reg(ARC_AUX_SLC_CTRL) &
+		       DC_CTRL_FLUSH_STATUS)
+			;
+
+	/* Switch back to default Invalidate mode */
+	if (op == OP_INV)
+		write_aux_reg(ARC_AUX_SLC_CTRL, reg | DC_CTRL_INV_MODE_FLUSH);
+}
+
+static inline void __slc_line_loop(unsigned long paddr, unsigned long sz,
+				   const int op)
+{
+	unsigned int aux_cmd;
+	int num_lines;
+
+#define SLC_LINE_MASK	(~(slc_line_sz - 1))
+
+	aux_cmd = op & OP_INV ? ARC_AUX_SLC_IVDL : ARC_AUX_SLC_FLDL;
+
+	sz += paddr & ~SLC_LINE_MASK;
+	paddr &= SLC_LINE_MASK;
+
+	num_lines = DIV_ROUND_UP(sz, slc_line_sz);
+
+	while (num_lines-- > 0) {
+		write_aux_reg(aux_cmd, paddr);
+		paddr += slc_line_sz;
+	}
+}
+
+static inline void __slc_entire_op(const int cacheop)
+{
+	int aux;
+	unsigned int ctrl_reg = __before_slc_op(cacheop);
+
+	if (cacheop & OP_INV)	/* Inv or flush-n-inv use same cmd reg */
+		aux = ARC_AUX_SLC_INVALIDATE;
+	else
+		aux = ARC_AUX_SLC_FLUSH;
+
+	write_aux_reg(aux, 0x1);
+
+	__after_slc_op(cacheop, ctrl_reg);
+}
+
+static inline void __slc_line_op(unsigned long paddr, unsigned long sz,
+				 const int cacheop)
+{
+	unsigned int ctrl_reg = __before_slc_op(cacheop);
+	__slc_line_loop(paddr, sz, cacheop);
+	__after_slc_op(cacheop, ctrl_reg);
+}
+#else
+#define __slc_entire_op(cacheop)
+#define __slc_line_op(paddr, sz, cacheop)
+#endif
+
+static inline int icache_exists(void)
+{
+	/* Check if Instruction Cache is available */
+	if (read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK)
+		return 1;
+	else
+		return 0;
+}
+
+static inline int dcache_exists(void)
+{
+	/* Check if Data Cache is available */
+	if (read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK)
+		return 1;
+	else
+		return 0;
+}
+
+void cache_init(void)
+{
+#ifdef CONFIG_ISA_ARCV2
+	/* Check if System-Level Cache (SLC) is available */
+	if (read_aux_reg(ARC_BCR_SLC) & CACHE_VER_NUM_MASK) {
+#define LSIZE_OFFSET	4
+#define LSIZE_MASK	3
+		if (read_aux_reg(ARC_AUX_SLC_CONFIG) &
+		    (LSIZE_MASK << LSIZE_OFFSET))
+			slc_line_sz = 64;
+		else
+			slc_line_sz = 128;
+		slc_exists = 1;
+	} else {
+		slc_exists = 0;
+	}
+#endif
+}
+
 int icache_status(void)
 {
-	/* If no cache in CPU exit immediately */
-	if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
+	if (!icache_exists())
 		return 0;
 
-	return (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) !=
-	       IC_CTRL_CACHE_DISABLE;
+	if (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE)
+		return 0;
+	else
+		return 1;
 }
 
 void icache_enable(void)
 {
-	/* If no cache in CPU exit immediately */
-	if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
-		return;
-
-	write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
-		      ~IC_CTRL_CACHE_DISABLE);
+	if (icache_exists())
+		write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
+			      ~IC_CTRL_CACHE_DISABLE);
 }
 
 void icache_disable(void)
 {
-	/* If no cache in CPU exit immediately */
-	if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
-		return;
-
-	write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
-		      IC_CTRL_CACHE_DISABLE);
+	if (icache_exists())
+		write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
+			      IC_CTRL_CACHE_DISABLE);
 }
 
+#ifndef CONFIG_SYS_DCACHE_OFF
 void invalidate_icache_all(void)
 {
-	/* If no cache in CPU exit immediately */
-	if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
-		return;
-
 	/* Any write to IC_IVIC register triggers invalidation of entire I$ */
-	write_aux_reg(ARC_AUX_IC_IVIC, 1);
+	if (icache_status()) {
+		write_aux_reg(ARC_AUX_IC_IVIC, 1);
+		read_aux_reg(ARC_AUX_IC_CTRL);	/* blocks */
+	}
 }
+#else
+void invalidate_icache_all(void)
+{
+}
+#endif
 
 int dcache_status(void)
 {
-	/* If no cache in CPU exit immediately */
-	if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
+	if (!dcache_exists())
 		return 0;
 
-	return (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) !=
-		DC_CTRL_CACHE_DISABLE;
+	if (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE)
+		return 0;
+	else
+		return 1;
 }
 
 void dcache_enable(void)
 {
-	/* If no cache in CPU exit immediately */
-	if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
+	if (!dcache_exists())
 		return;
 
 	write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
@@ -80,91 +210,123 @@ void dcache_enable(void)
 
 void dcache_disable(void)
 {
-	/* If no cache in CPU exit immediately */
-	if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
+	if (!dcache_exists())
 		return;
 
 	write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
 		      DC_CTRL_CACHE_DISABLE);
 }
 
-void flush_dcache_all(void)
-{
-	/* If no cache in CPU exit immediately */
-	if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
-		return;
-
-	/* Do flush of entire cache */
-	write_aux_reg(ARC_AUX_DC_FLSH, 1);
-
-	/* Wait flush end */
-	while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
-		;
-}
-
 #ifndef CONFIG_SYS_DCACHE_OFF
-static void dcache_flush_line(unsigned addr)
+/*
+ * Common Helper for Line Operations on {I,D}-Cache
+ */
+static inline void __cache_line_loop(unsigned long paddr, unsigned long sz,
+				     const int cacheop)
 {
+	unsigned int aux_cmd;
 #if (CONFIG_ARC_MMU_VER == 3)
-	write_aux_reg(ARC_AUX_DC_PTAG, addr);
+	unsigned int aux_tag;
 #endif
-	write_aux_reg(ARC_AUX_DC_FLDL, addr);
+	int num_lines;
 
-	/* Wait flush end */
-	while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
-		;
-
-#ifndef CONFIG_SYS_ICACHE_OFF
-	/*
-	 * Invalidate I$ for addresses range just flushed from D$.
-	 * If we try to execute data flushed above it will be valid/correct
-	 */
+	if (cacheop == OP_INV_IC) {
+		aux_cmd = ARC_AUX_IC_IVIL;
 #if (CONFIG_ARC_MMU_VER == 3)
-	write_aux_reg(ARC_AUX_IC_PTAG, addr);
+		aux_tag = ARC_AUX_IC_PTAG;
 #endif
-	write_aux_reg(ARC_AUX_IC_IVIL, addr);
-#endif /* CONFIG_SYS_ICACHE_OFF */
+	} else {
+		/* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
+		aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL;
+#if (CONFIG_ARC_MMU_VER == 3)
+		aux_tag = ARC_AUX_DC_PTAG;
+#endif
+	}
+
+	sz += paddr & ~CACHE_LINE_MASK;
+	paddr &= CACHE_LINE_MASK;
+
+	num_lines = DIV_ROUND_UP(sz, CONFIG_SYS_CACHELINE_SIZE);
+
+	while (num_lines-- > 0) {
+#if (CONFIG_ARC_MMU_VER == 3)
+		write_aux_reg(aux_tag, paddr);
+#endif
+		write_aux_reg(aux_cmd, paddr);
+		paddr += CONFIG_SYS_CACHELINE_SIZE;
+	}
 }
-#endif /* CONFIG_SYS_DCACHE_OFF */
 
-void flush_dcache_range(unsigned long start, unsigned long end)
+static unsigned int __before_dc_op(const int op)
 {
-#ifndef CONFIG_SYS_DCACHE_OFF
-	unsigned int addr;
+	unsigned int reg;
 
-	start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
-	end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
+	if (op == OP_INV) {
+		/*
+		 * IM is set by default and implies Flush-n-inv
+		 * Clear it here for vanilla inv
+		 */
+		reg = read_aux_reg(ARC_AUX_DC_CTRL);
+		write_aux_reg(ARC_AUX_DC_CTRL, reg & ~DC_CTRL_INV_MODE_FLUSH);
+	}
 
-	for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE)
-		dcache_flush_line(addr);
-#endif /* CONFIG_SYS_DCACHE_OFF */
+	return reg;
 }
 
+static void __after_dc_op(const int op, unsigned int reg)
+{
+	if (op & OP_FLUSH)	/* flush / flush-n-inv both wait */
+		while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
+			;
+
+	/* Switch back to default Invalidate mode */
+	if (op == OP_INV)
+		write_aux_reg(ARC_AUX_DC_CTRL, reg | DC_CTRL_INV_MODE_FLUSH);
+}
+
+static inline void __dc_entire_op(const int cacheop)
+{
+	int aux;
+	unsigned int ctrl_reg = __before_dc_op(cacheop);
+
+	if (cacheop & OP_INV)	/* Inv or flush-n-inv use same cmd reg */
+		aux = ARC_AUX_DC_IVDC;
+	else
+		aux = ARC_AUX_DC_FLSH;
+
+	write_aux_reg(aux, 0x1);
+
+	__after_dc_op(cacheop, ctrl_reg);
+}
+
+static inline void __dc_line_op(unsigned long paddr, unsigned long sz,
+				const int cacheop)
+{
+	unsigned int ctrl_reg = __before_dc_op(cacheop);
+	__cache_line_loop(paddr, sz, cacheop);
+	__after_dc_op(cacheop, ctrl_reg);
+}
+#else
+#define __dc_entire_op(cacheop)
+#define __dc_line_op(paddr, sz, cacheop)
+#endif /* !CONFIG_SYS_DCACHE_OFF */
+
 void invalidate_dcache_range(unsigned long start, unsigned long end)
 {
-#ifndef CONFIG_SYS_DCACHE_OFF
-	unsigned int addr;
-
-	start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
-	end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
-
-	for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) {
-#if (CONFIG_ARC_MMU_VER == 3)
-		write_aux_reg(ARC_AUX_DC_PTAG, addr);
+	__dc_line_op(start, end - start, OP_INV);
+#ifdef CONFIG_ISA_ARCV2
+	if (slc_exists)
+		__slc_line_op(start, end - start, OP_INV);
 #endif
-		write_aux_reg(ARC_AUX_DC_IVDL, addr);
-	}
-#endif /* CONFIG_SYS_DCACHE_OFF */
 }
 
-void invalidate_dcache_all(void)
+void flush_dcache_range(unsigned long start, unsigned long end)
 {
-	/* If no cache in CPU exit immediately */
-	if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
-		return;
-
-	/* Write 1 to DC_IVDC register triggers invalidation of entire D$ */
-	write_aux_reg(ARC_AUX_DC_IVDC, 1);
+	__dc_line_op(start, end - start, OP_FLUSH);
+#ifdef CONFIG_ISA_ARCV2
+	if (slc_exists)
+		__slc_line_op(start, end - start, OP_FLUSH);
+#endif
 }
 
 void flush_cache(unsigned long start, unsigned long size)
@@ -172,47 +334,20 @@ void flush_cache(unsigned long start, unsigned long size)
 	flush_dcache_range(start, start + size);
 }
 
+void invalidate_dcache_all(void)
+{
+	__dc_entire_op(OP_INV);
 #ifdef CONFIG_ISA_ARCV2
-void slc_enable(void)
-{
-	/* If SLC ver = 0, no SLC present in CPU */
-	if (!(read_aux_reg(ARC_BCR_SLC) & 0xff))
-		return;
-
-	write_aux_reg(ARC_AUX_SLC_CONTROL,
-		      read_aux_reg(ARC_AUX_SLC_CONTROL) & ~1);
+	if (slc_exists)
+		__slc_entire_op(OP_INV);
+#endif
 }
 
-void slc_disable(void)
+void flush_dcache_all(void)
 {
-	/* If SLC ver = 0, no SLC present in CPU */
-	if (!(read_aux_reg(ARC_BCR_SLC) & 0xff))
-		return;
-
-	write_aux_reg(ARC_AUX_SLC_CONTROL,
-		      read_aux_reg(ARC_AUX_SLC_CONTROL) | 1);
+	__dc_entire_op(OP_FLUSH);
+#ifdef CONFIG_ISA_ARCV2
+	if (slc_exists)
+		__slc_entire_op(OP_FLUSH);
+#endif
 }
-
-void slc_flush(void)
-{
-	/* If SLC ver = 0, no SLC present in CPU */
-	if (!(read_aux_reg(ARC_BCR_SLC) & 0xff))
-		return;
-
-	write_aux_reg(ARC_AUX_SLC_FLUSH, 1);
-
-	/* Wait flush end */
-	while (read_aux_reg(ARC_AUX_SLC_CONTROL) & SLC_CTRL_SB)
-		;
-}
-
-void slc_invalidate(void)
-{
-	/* If SLC ver = 0, no SLC present in CPU */
-	if (!(read_aux_reg(ARC_BCR_SLC) & 0xff))
-		return;
-
-	write_aux_reg(ARC_AUX_SLC_INVALIDATE, 1);
-}
-
-#endif /* CONFIG_ISA_ARCV2 */

arch/arc/lib/cpu.c

@@ -23,6 +23,8 @@ int arch_cpu_init(void)
 	gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
 	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 
+	cache_init();
+
 	return 0;
 }
 

arch/arc/lib/init_helpers.c

@@ -10,16 +10,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int init_cache_f_r(void)
 {
-#ifndef CONFIG_SYS_ICACHE_OFF
-	icache_enable();
-	/* Make sure no stale entries persist from before we disabled cache */
-	invalidate_icache_all();
-#endif
-
 #ifndef CONFIG_SYS_DCACHE_OFF
-	dcache_enable();
-	/* Make sure no stale entries persist from before we disabled cache */
-	invalidate_dcache_all();
+	flush_dcache_all();
 #endif
 	return 0;
 }

arch/arc/lib/start.S

@@ -13,19 +13,47 @@ ENTRY(_start)
 	/* Setup interrupt vector base that matches "__text_start" */
 	sr	__ivt_start, [ARC_AUX_INTR_VEC_BASE]
 
+	; Disable/enable I-cache according to configuration
+	lr	r5, [ARC_BCR_IC_BUILD]
+	breq	r5, 0, 1f		; I$ doesn't exist
+	lr	r5, [ARC_AUX_IC_CTRL]
+#ifndef CONFIG_SYS_ICACHE_OFF
+	bclr	r5, r5, 0		; 0 - Enable, 1 is Disable
+#else
+	bset	r5, r5, 0		; I$ exists, but is not used
+#endif
+	sr	r5, [ARC_AUX_IC_CTRL]
+
+1:
+	; Disable/enable D-cache according to configuration
+	lr	r5, [ARC_BCR_DC_BUILD]
+	breq	r5, 0, 1f		; D$ doesn't exist
+	lr	r5, [ARC_AUX_DC_CTRL]
+	bclr	r5, r5, 6		; Invalidate (discard w/o wback)
+#ifndef CONFIG_SYS_DCACHE_OFF
+	bclr	r5, r5, 0		; Enable (+Inv)
+#else
+	bset	r5, r5, 0		; Disable (+Inv)
+#endif
+	sr	r5, [ARC_AUX_DC_CTRL]
+
+1:
+#ifdef CONFIG_ISA_ARCV2
+	; Disable System-Level Cache (SLC)
+	lr	r5, [ARC_BCR_SLC]
+	breq	r5, 0, 1f		; SLC doesn't exist
+	lr	r5, [ARC_AUX_SLC_CTRL]
+	bclr	r5, r5, 6		; Invalidate (discard w/o wback)
+	bclr	r5, r5, 0		; Enable (+Inv)
+	sr	r5, [ARC_AUX_SLC_CTRL]
+
+1:
+#endif
+
 	/* Setup stack- and frame-pointers */
 	mov	%sp, CONFIG_SYS_INIT_SP_ADDR
 	mov	%fp, %sp
 
-	/* Unconditionally disable caches */
-#ifdef CONFIG_ISA_ARCV2
-	bl	slc_flush
-	bl	slc_disable
-#endif
-	bl	flush_dcache_all
-	bl	dcache_disable
-	bl	icache_disable
-
 	/* Allocate and zero GD, update SP */
 	mov	%r0, %sp
 	bl	board_init_f_mem

arch/arm/Kconfig

@@ -589,10 +589,6 @@ config TARGET_TBS2910
 	bool "Support tbs2910"
 	select CPU_V7
 
-config TARGET_TQMA6
-	bool "TQ Systems TQMa6 board"
-	select CPU_V7
-
 config TARGET_OT1200
 	bool "Bachmann OT1200"
 	select CPU_V7
@@ -670,7 +666,11 @@ config ARCH_ZYNQ
 	bool "Xilinx Zynq Platform"
 	select CPU_V7
 	select SUPPORT_SPL
+	select OF_CONTROL
+	select SPL_DISABLE_OF_CONTROL
 	select DM
+	select DM_SPI
+	select DM_SPI_FLASH
 
 config TARGET_XILINX_ZYNQMP
 	bool "Support Xilinx ZynqMP Platform"
@@ -972,7 +972,6 @@ source "board/ti/ti816x/Kconfig"
 source "board/timll/devkit3250/Kconfig"
 source "board/toradex/colibri_pxa270/Kconfig"
 source "board/toradex/colibri_vf/Kconfig"
-source "board/tqc/tqma6/Kconfig"
 source "board/trizepsiv/Kconfig"
 source "board/ttcontrol/vision2/Kconfig"
 source "board/udoo/Kconfig"

arch/arm/cpu/armv7/mx6/Kconfig

@@ -33,11 +33,16 @@ config TARGET_SECOMX6
 	bool "Support secomx6 boards"
 	select CPU_V7
 
+config TARGET_TQMA6
+	bool "TQ Systems TQMa6 board"
+	select CPU_V7
+
 endchoice
 
 config SYS_SOC
 	default "mx6"
 
 source "board/seco/Kconfig"
+source "board/tqc/tqma6/Kconfig"
 
 endif

arch/arm/cpu/armv7/mx6/soc.c

@@ -62,6 +62,7 @@ u32 get_cpu_rev(void)
 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 	u32 reg = readl(&anatop->digprog_sololite);
 	u32 type = ((reg >> 16) & 0xff);
+	u32 major;
 
 	if (type != MXC_CPU_MX6SL) {
 		reg = readl(&anatop->digprog);
@@ -79,8 +80,9 @@ u32 get_cpu_rev(void)
 		}
 
 	}
+	major = ((reg >> 8) & 0xff);
 	reg &= 0xff;		/* mx6 silicon revision */
-	return (type << 12) | (reg + 0x10);
+	return (type << 12) | (reg + (0x10 * (major + 1)));
 }
 
 /*

arch/arm/cpu/armv7/start.S

@@ -22,10 +22,9 @@
  *
  * Startup Code (reset vector)
  *
- * do important init only if we don't start from memory!
- * setup Memory and board specific bits prior to relocation.
- * relocate armboot to ram
- * setup stack
+ * Do important init only if we don't start from memory!
+ * Setup memory and board specific bits prior to relocation.
+ * Relocate armboot to ram. Setup stack.
  *
  *************************************************************************/
 

arch/arm/cpu/armv7/sunxi/board.c

@@ -45,11 +45,11 @@ static int gpio_init(void)
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
 #endif
 #if defined(CONFIG_MACH_SUN8I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0_TX);
-	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0_RX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
 #else
-	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0_TX);
-	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0_RX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
 #endif
 	sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
 #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
@@ -64,6 +64,10 @@ static int gpio_init(void)
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
 	sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
+	sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);

arch/arm/cpu/armv7/sunxi/rsb.c

@@ -60,11 +60,12 @@ int rsb_init(void)
 	struct sunxi_rsb_reg * const rsb =
 		(struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
 
-	rsb_cfg_io();
-
 	/* Enable RSB and PIO clk, and de-assert their resets */
 	prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
 
+	/* Setup external pins */
+	rsb_cfg_io();
+
 	writel(RSB_CTRL_SOFT_RST, &rsb->ctrl);
 	rsb_set_clk();
 

arch/arm/dts/Makefile

@@ -128,7 +128,8 @@ dtb-$(CONFIG_MACH_SUN8I_A23) += \
 dtb-$(CONFIG_MACH_SUN8I_A33) += \
 	sun8i-a33-et-q8-v1.6.dtb \
 	sun8i-a33-ga10h-v1.1.dtb \
-	sun8i-a33-ippo-q8h-v1.2-lcd1024x600.dtb
+	sun8i-a33-ippo-q8h-v1.2.dtb \
+	sun8i-a33-sinlinx-sina33.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
 	sun9i-a80-optimus.dtb \
 	sun9i-a80-cubieboard4.dtb

arch/arm/dts/sun8i-a23-a33.dtsi

@@ -366,6 +366,16 @@
 				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 			};
 
+			mmc2_8bit_pins: mmc2_8bit {
+				allwinner,pins = "PC5", "PC6", "PC8",
+						 "PC9", "PC10", "PC11",
+						 "PC12", "PC13", "PC14",
+						 "PC15";
+				allwinner,function = "mmc2";
+				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
 			i2c0_pins_a: i2c0@0 {
 				allwinner,pins = "PH2", "PH3";
 				allwinner,function = "i2c0";

arch/arm/dts/sun8i-a33-sinlinx-sina33.dts

@@ -0,0 +1,129 @@
+/*
+ * Copyright 2015 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a33.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+	model = "Sinlinx SinA33";
+	compatible = "sinlinx,sina33", "allwinner,sun8i-a33";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&lradc {
+	vref-supply = <&reg_vcc3v0>;
+	status = "okay";
+
+	button@200 {
+		label = "Volume Up";
+		linux,code = <KEY_VOLUMEUP>;
+		channel = <0>;
+		voltage = <191011>;
+	};
+
+	button@400 {
+		label = "Volume Down";
+		linux,code = <KEY_VOLUMEDOWN>;
+		channel = <0>;
+		voltage = <391304>;
+	};
+
+	button@600 {
+		label = "Home";
+		linux,code = <KEY_HOME>;
+		channel = <0>;
+		voltage = <600000>;
+	};
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_sina33>;
+	vmmc-supply = <&reg_vcc3v0>;
+	bus-width = <4>;
+	cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
+	cd-inverted;
+	status = "okay";
+};
+
+&mmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_8bit_pins>;
+	vmmc-supply = <&reg_vcc3v0>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&mmc2_8bit_pins {
+	/* eMMC is missing pull-ups */
+	allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
+
+&pio {
+	mmc0_cd_pin_sina33: mmc0_cd_pin@0 {
+		allwinner,pins = "PB4";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_b>;
+	status = "okay";
+};

arch/arm/dts/sun8i-a33.dtsi

@@ -86,4 +86,12 @@
 	compatible = "allwinner,sun8i-a33-pinctrl";
 	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 		     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+
+	uart0_pins_b: uart0@1 {
+		allwinner,pins = "PB0", "PB1";
+		allwinner,function = "uart0";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+
 };

arch/arm/dts/uniphier-ph1-ld4-ref.dts

@@ -5,7 +5,7 @@
  * Copyright (C) 2015      Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
 /dts-v1/;

arch/arm/dts/uniphier-ph1-ld4.dtsi

@@ -1,11 +1,9 @@
 /*
  * Device Tree Source for UniPhier PH1-LD4 SoC
  *
- * Copyright (C) 2014-2015 Panasonic Corporation
- * Copyright (C) 2015      Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
 /include/ "skeleton.dtsi"
@@ -24,11 +22,26 @@
 		};
 	};
 
+	clocks {
+		arm_timer_clk: arm_timer_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <50000000>;
+		};
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;
+		interrupt-parent = <&intc>;
+
+		extbus: extbus {
+			compatible = "simple-bus";
+			#address-cells = <2>;
+			#size-cells = <1>;
+		};
 
 		uart0: serial@54006800 {
 			compatible = "socionext,uniphier-uart";
@@ -94,6 +107,12 @@
 			status = "disabled";
 		};
 
+		system-bus-controller-misc@59800000 {
+			compatible = "socionext,uniphier-system-bus-controller-misc",
+				     "syscon";
+			reg = <0x59800000 0x2000>;
+		};
+
 		usb0: usb@5a800100 {
 			compatible = "socionext,uniphier-ehci", "generic-ehci";
 			status = "disabled";
@@ -112,6 +131,28 @@
 			reg = <0x5a820100 0x100>;
 		};
 
+		timer@60000200 {
+			compatible = "arm,cortex-a9-global-timer";
+			reg = <0x60000200 0x20>;
+			interrupts = <1 11 0x104>;
+			clocks = <&arm_timer_clk>;
+		};
+
+		timer@60000600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0x60000600 0x20>;
+			interrupts = <1 13 0x104>;
+			clocks = <&arm_timer_clk>;
+		};
+
+		intc: interrupt-controller@60001000 {
+			compatible = "arm,cortex-a9-gic";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			reg = <0x60001000 0x1000>,
+			      <0x60000100 0x100>;
+		};
+
 		nand: nand@68000000 {
 			compatible = "denali,denali-nand-dt";
 			reg = <0x68000000 0x20>, <0x68100000 0x1000>;

arch/arm/dts/uniphier-ph1-pro4-ref.dts

@@ -5,7 +5,7 @@
  * Copyright (C) 2015      Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
 /dts-v1/;

arch/arm/dts/uniphier-ph1-pro4.dtsi

@@ -1,11 +1,9 @@
 /*
  * Device Tree Source for UniPhier PH1-Pro4 SoC
  *
- * Copyright (C) 2014-2015 Panasonic Corporation
- * Copyright (C) 2015      Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
 /include/ "skeleton.dtsi"
@@ -16,6 +14,7 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		enable-method = "socionext,uniphier-smp";
 
 		cpu@0 {
 			device_type = "cpu";
@@ -30,11 +29,26 @@
 		};
 	};
 
+	clocks {
+		arm_timer_clk: arm_timer_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <50000000>;
+		};
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;
+		interrupt-parent = <&intc>;
+
+		extbus: extbus {
+			compatible = "simple-bus";
+			#address-cells = <2>;
+			#size-cells = <1>;
+		};
 
 		uart0: serial@54006800 {
 			compatible = "socionext,uniphier-uart";
@@ -120,6 +134,12 @@
 			status = "ok";
 		};
 
+		system-bus-controller-misc@59800000 {
+			compatible = "socionext,uniphier-system-bus-controller-misc",
+				     "syscon";
+			reg = <0x59800000 0x2000>;
+		};
+
 		usb2: usb@5a800100 {
 			compatible = "socionext,uniphier-ehci", "generic-ehci";
 			status = "disabled";
@@ -144,6 +164,28 @@
 			reg = <0x65c00000 0x100>;
 		};
 
+		timer@60000200 {
+			compatible = "arm,cortex-a9-global-timer";
+			reg = <0x60000200 0x20>;
+			interrupts = <1 11 0x304>;
+			clocks = <&arm_timer_clk>;
+		};
+
+		timer@60000600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0x60000600 0x20>;
+			interrupts = <1 13 0x304>;
+			clocks = <&arm_timer_clk>;
+		};
+
+		intc: interrupt-controller@60001000 {
+			compatible = "arm,cortex-a9-gic";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			reg = <0x60001000 0x1000>,
+			      <0x60000100 0x100>;
+		};
+
 		nand: nand@68000000 {
 			compatible = "denali,denali-nand-dt";
 			reg = <0x68000000 0x20>, <0x68100000 0x1000>;

arch/arm/dts/uniphier-ph1-sld3-ref.dts

@@ -5,7 +5,7 @@
  * Copyright (C) 2015      Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
 /dts-v1/;

arch/arm/dts/uniphier-ph1-sld3.dtsi

@@ -1,11 +1,9 @@
 /*
  * Device Tree Source for UniPhier PH1-sLD3 SoC
  *
- * Copyright (C) 2014-2015 Panasonic Corporation
- * Copyright (C) 2015      Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
 /include/ "skeleton.dtsi"
@@ -16,6 +14,7 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		enable-method = "socionext,uniphier-smp";
 
 		cpu@0 {
 			device_type = "cpu";
@@ -30,11 +29,48 @@
 		};
 	};
 
+	clocks {
+		arm_timer_clk: arm_timer_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <50000000>;
+		};
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;
+		interrupt-parent = <&intc>;
+
+		extbus: extbus {
+			compatible = "simple-bus";
+			#address-cells = <2>;
+			#size-cells = <1>;
+		};
+
+		timer@20000200 {
+			compatible = "arm,cortex-a9-global-timer";
+			reg = <0x20000200 0x20>;
+			interrupts = <1 11 0x304>;
+			clocks = <&arm_timer_clk>;
+		};
+
+		timer@20000600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0x20000600 0x20>;
+			interrupts = <1 13 0x304>;
+			clocks = <&arm_timer_clk>;
+		};
+
+		intc: interrupt-controller@20001000 {
+			compatible = "arm,cortex-a9-gic";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			reg = <0x20001000 0x1000>,
+			      <0x20000100 0x100>;
+		};
 
 		uart0: serial@54006800 {
 			compatible = "socionext,uniphier-uart";
@@ -93,6 +129,12 @@
 			status = "disabled";
 		};
 
+		system-bus-controller-misc@59800000 {
+			compatible = "socionext,uniphier-system-bus-controller-misc",
+				     "syscon";
+			reg = <0x59800000 0x2000>;
+		};
+
 		usb0: usb@5a800100 {
 			compatible = "socionext,uniphier-ehci", "generic-ehci";
 			status = "disabled";

arch/arm/dts/uniphier-ph1-sld8-ref.dts

@@ -5,7 +5,7 @@
  * Copyright (C) 2015      Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
 /dts-v1/;

arch/arm/dts/uniphier-ph1-sld8.dtsi

@@ -1,11 +1,9 @@
 /*
  * Device Tree Source for UniPhier PH1-sLD8 SoC
  *
- * Copyright (C) 2014-2015 Panasonic Corporation
- * Copyright (C) 2015      Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
 /include/ "skeleton.dtsi"
@@ -24,11 +22,26 @@
 		};
 	};
 
+	clocks {
+		arm_timer_clk: arm_timer_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <50000000>;
+		};
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;
+		interrupt-parent = <&intc>;
+
+		extbus: extbus {
+			compatible = "simple-bus";
+			#address-cells = <2>;
+			#size-cells = <1>;
+		};
 
 		uart0: serial@54006800 {
 			compatible = "socionext,uniphier-uart";
@@ -94,6 +107,12 @@
 			status = "disabled";
 		};
 
+		system-bus-controller-misc@59800000 {
+			compatible = "socionext,uniphier-system-bus-controller-misc",
+				     "syscon";
+			reg = <0x59800000 0x2000>;
+		};
+
 		usb0: usb@5a800100 {
 			compatible = "socionext,uniphier-ehci", "generic-ehci";
 			status = "disabled";
@@ -112,6 +131,28 @@
 			reg = <0x5a820100 0x100>;
 		};
 
+		timer@60000200 {
+			compatible = "arm,cortex-a9-global-timer";
+			reg = <0x60000200 0x20>;
+			interrupts = <1 11 0x104>;
+			clocks = <&arm_timer_clk>;
+		};
+
+		timer@60000600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0x60000600 0x20>;
+			interrupts = <1 13 0x104>;
+			clocks = <&arm_timer_clk>;
+		};
+
+		intc: interrupt-controller@60001000 {
+			compatible = "arm,cortex-a9-gic";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			reg = <0x60001000 0x1000>,
+			      <0x60000100 0x100>;
+		};
+
 		nand: nand@68000000 {
 			compatible = "denali,denali-nand-dt";
 			reg = <0x68000000 0x20>, <0x68100000 0x1000>;

arch/arm/dts/uniphier-ref-daughter.dtsi

@@ -1,11 +1,9 @@
 /*
  * Device Tree Source for UniPhier Reference Daughter Board
  *
- * Copyright (C) 2014-2015 Panasonic Corporation
- * Copyright (C) 2015      Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
 &i2c0 {

arch/arm/dts/zynq-7000.dtsi

@@ -109,6 +109,32 @@
 			interrupts = <0 50 4>;
 		};
 
+		spi0: spi@e0006000 {
+			compatible = "xlnx,zynq-spi";
+			reg = <0xe0006000 0x1000>;
+			status = "disabled";
+			interrupt-parent = <&intc>;
+			interrupts = <0 26 4>;
+			clocks = <&clkc 25>, <&clkc 34>;
+			clock-names = "ref_clk", "pclk";
+			spi-max-frequency = <166666700>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		spi1: spi@e0007000 {
+			compatible = "xlnx,zynq-spi";
+			reg = <0xe0007000 0x1000>;
+			status = "disabled";
+			interrupt-parent = <&intc>;
+			interrupts = <0 49 4>;
+			clocks = <&clkc 26>, <&clkc 35>;
+			clock-names = "ref_clk", "pclk";
+			spi-max-frequency = <166666700>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		gem0: ethernet@e000b000 {
 			compatible = "cdns,gem";
 			reg = <0xe000b000 0x4000>;

arch/arm/dts/zynq-zc770-xm010.dts

@@ -14,6 +14,7 @@
 
 	aliases {
 		serial0 = &uart1;
+		spi1 = &spi1;
 	};
 
 	memory {
@@ -21,3 +22,7 @@
 		reg = <0 0x40000000>;
 	};
 };
+
+&spi1 {
+	status = "okay";
+};

arch/arm/imx-common/timer.c

@@ -44,8 +44,8 @@ static inline int gpt_has_clk_source_osc(void)
 {
 #if defined(CONFIG_MX6)
 	if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
-	     (is_soc_rev(CHIP_REV_1_0) > 0)) || is_cpu_type(MXC_CPU_MX6DL) ||
-	      is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX))
+	    (soc_rev() > CHIP_REV_1_0)) || is_cpu_type(MXC_CPU_MX6DL) ||
+	     is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX))
 		return 1;
 
 	return 0;

arch/arm/include/asm/arch-mx5/imx-regs.h

@@ -9,6 +9,8 @@
 
 #define ARCH_MXC
 
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
 #if defined(CONFIG_MX51)
 #define IRAM_BASE_ADDR		0x1FFE0000	/* internal ram */
 #define IPU_SOC_BASE_ADDR	0x40000000

arch/arm/include/asm/arch-mx6/imx-regs.h

@@ -312,6 +312,7 @@
 #define CHIP_REV_1_0                 0x10
 #define CHIP_REV_1_2                 0x12
 #define CHIP_REV_1_5                 0x15
+#define CHIP_REV_2_0                 0x20
 #ifndef CONFIG_MX6SX
 #define IRAM_SIZE                    0x00040000
 #else

arch/arm/include/asm/arch-mx6/sys_proto.h

@@ -12,7 +12,7 @@
 #include "../arch-imx/cpu.h"
 
 #define soc_rev() (get_cpu_rev() & 0xFF)
-#define is_soc_rev(rev)        (soc_rev() - rev)
+#define is_soc_rev(rev) (soc_rev() == rev)
 
 u32 get_nr_cpus(void);
 u32 get_cpu_rev(void);
@@ -20,7 +20,7 @@ u32 get_cpu_speed_grade_hz(void);
 u32 get_cpu_temp_grade(int *minc, int *maxc);
 
 /* returns MXC_CPU_ value */
-#define cpu_type(rev) (((rev) >> 12)&0xff)
+#define cpu_type(rev) (((rev) >> 12) & 0xff)
 
 /* both macros return/take MXC_CPU_ constants */
 #define get_cpu_type()	(cpu_type(get_cpu_rev()))
@@ -30,6 +30,10 @@ const char *get_imx_type(u32 imxtype);
 unsigned imx_ddr_size(void);
 void set_chipselect_size(int const);
 
+#define is_mx6dqp() ((is_cpu_type(MXC_CPU_MX6Q) || \
+		     is_cpu_type(MXC_CPU_MX6D)) && \
+		     (soc_rev() >= CHIP_REV_2_0))
+
 /*
  * Initializes on-chip ethernet controllers.
  * to override, implement board_eth_init()

arch/arm/include/asm/arch-sunxi/gpio.h

@@ -156,6 +156,7 @@ enum sunxi_gpio_number {
 #define SUN4I_GPB_UART0		2
 #define SUN5I_GPB_UART0		2
 #define SUN8I_GPB_UART2		2
+#define SUN8I_A33_GPB_UART0	3
 
 #define SUNXI_GPC_SDC2		3
 #define SUN6I_GPC_SDC3		4

arch/arm/include/asm/u-boot.h

@@ -49,8 +49,4 @@ typedef struct bd_info {
 #define IH_ARCH_DEFAULT IH_ARCH_ARM64
 #endif
 
-#if defined(CONFIG_USE_PRIVATE_LIBGCC) && defined(CONFIG_SYS_THUMB_BUILD)
-#error Thumb build does not work with private libgcc.
-#endif
-
 #endif	/* _U_BOOT_H_ */

arch/arm/lib/_ashldi3.S

@@ -4,6 +4,8 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <linux/linkage.h>
+
 #ifdef __ARMEB__
 #define al r1
 #define ah r0
@@ -13,9 +15,8 @@
 #endif
 
 .globl __ashldi3
-.globl	__aeabi_llsl
 __ashldi3:
-__aeabi_llsl:
+ENTRY(__aeabi_llsl)
 
 	subs	r3, r2, #32
 	rsb	ip, r2, #32
@@ -24,3 +25,4 @@ __aeabi_llsl:
 	orrmi	ah, ah, al, lsr ip
 	mov	al, al, lsl r2
 	mov	pc, lr
+ENDPROC(__aeabi_llsl)

arch/arm/lib/_ashrdi3.S

@@ -4,6 +4,8 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <linux/linkage.h>
+
 #ifdef __ARMEB__
 #define al r1
 #define ah r0
@@ -13,9 +15,8 @@
 #endif
 
 .globl __ashrdi3
-.globl __aeabi_lasr
 __ashrdi3:
-__aeabi_lasr:
+ENTRY(__aeabi_lasr)
 
 	subs	r3, r2, #32
 	rsb	ip, r2, #32
@@ -24,3 +25,4 @@ __aeabi_lasr:
 	orrmi	al, al, ah, lsl ip
 	mov	ah, ah, asr r2
 	mov	pc, lr
+ENDPROC(__aeabi_lasr)

arch/arm/lib/_divsi3.S

@@ -1,3 +1,5 @@
+#include <linux/linkage.h>
+
 .macro ARM_DIV_BODY dividend, divisor, result, curbit
 
 #if __LINUX_ARM_ARCH__ >= 5
@@ -95,9 +97,8 @@
 
 	.align	5
 .globl __divsi3
-.globl __aeabi_idiv
 __divsi3:
-__aeabi_idiv:
+ENTRY(__aeabi_idiv)
 	cmp	r1, #0
 	eor	ip, r0, r1			@ save the sign of the result.
 	beq	Ldiv0
@@ -139,3 +140,4 @@ Ldiv0:
 	bl	__div0
 	mov	r0, #0			@ About as wrong as it could be.
 	ldr	pc, [sp], #4
+ENDPROC(__aeabi_idiv)

arch/arm/lib/_lshrdi3.S

@@ -4,6 +4,8 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <linux/linkage.h>
+
 #ifdef __ARMEB__
 #define al r1
 #define ah r0
@@ -13,9 +15,8 @@
 #endif
 
 .globl __lshrdi3
-.globl __aeabi_llsr
 __lshrdi3:
-__aeabi_llsr:
+ENTRY(__aeabi_llsr)
 
 	subs	r3, r2, #32
 	rsb	ip, r2, #32
@@ -24,3 +25,4 @@ __aeabi_llsr:
 	orrmi	al, al, ah, lsl ip
 	mov	ah, ah, lsr r2
 	mov	pc, lr
+ENDPROC(__aeabi_llsr)

arch/arm/lib/_modsi3.S

@@ -1,3 +1,5 @@
+#include <linux/linkage.h>
+
 .macro ARM_MOD_BODY dividend, divisor, order, spare
 
 #if __LINUX_ARM_ARCH__ >= 5
@@ -69,8 +71,7 @@
 .endm
 
 	.align	5
-.globl __modsi3
-__modsi3:
+ENTRY(__modsi3)
 	cmp	r1, #0
 	beq	Ldiv0
 	rsbmi	r1, r1, #0			@ loops below use unsigned.
@@ -88,7 +89,7 @@ __modsi3:
 10:	cmp	ip, #0
 	rsbmi	r0, r0, #0
 	mov	pc, lr
-
+ENDPROC(__modsi3)
 
 Ldiv0:
 

arch/arm/lib/_udivsi3.S

@@ -1,3 +1,5 @@
+#include <linux/linkage.h>
+
 /* # 1 "libgcc1.S" */
 @ libgcc1 routines for ARM cpu.
 @ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)
@@ -72,8 +74,7 @@ Ldiv0:
 	ldmia	sp!, {pc}
 	.size  __udivsi3       , . -  __udivsi3
 
-.globl __aeabi_uidivmod
-__aeabi_uidivmod:
+ENTRY(__aeabi_uidivmod)
 
 	stmfd	sp!, {r0, r1, ip, lr}
 	bl	__aeabi_uidiv
@@ -81,9 +82,9 @@ __aeabi_uidivmod:
 	mul	r3, r0, r2
 	sub	r1, r1, r3
 	mov	pc, lr
+ENDPROC(__aeabi_uidivmod)
 
-.globl __aeabi_idivmod
-__aeabi_idivmod:
+ENTRY(__aeabi_idivmod)
 
 	stmfd	sp!, {r0, r1, ip, lr}
 	bl	__aeabi_idiv
@@ -91,3 +92,4 @@ __aeabi_idivmod:
 	mul	r3, r0, r2
 	sub	r1, r1, r3
 	mov	pc, lr
+ENDPROC(__aeabi_idivmod)

arch/arm/lib/_umodsi3.S

@@ -1,3 +1,5 @@
+#include <linux/linkage.h>
+
 /* # 1 "libgcc1.S" */
 @ libgcc1 routines for ARM cpu.
 @ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)
@@ -11,10 +13,9 @@ curbit		.req	r3
 /* lr		.req	r14	*/
 /* pc		.req	r15	*/
 	.text
-	.globl	 __umodsi3
 	.type  __umodsi3       ,function
 	.align 0
- __umodsi3      :
+ ENTRY(__umodsi3)
 	cmp	divisor, #0
 	beq	Ldiv0
 	mov	curbit, #1
@@ -86,3 +87,4 @@ Ldiv0:
 /* # 456 "libgcc1.S" */
 /* # 500 "libgcc1.S" */
 /* # 580 "libgcc1.S" */
+ENDPROC(__umodsi3)

arch/arm/mach-mvebu/cpu.c

@@ -6,10 +6,13 @@
 
 #include <common.h>
 #include <netdev.h>
+#include <ahci.h>
+#include <linux/mbus.h>
 #include <asm/io.h>
 #include <asm/pl310.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/soc.h>
+#include <sdhci.h>
 
 #define DDR_BASE_CS_OFF(n)	(0x0000 + ((n) << 3))
 #define DDR_SIZE_CS_OFF(n)	(0x0004 + ((n) << 3))
@@ -245,6 +248,69 @@ int cpu_eth_init(bd_t *bis)
 }
 #endif
 
+#ifdef CONFIG_MV_SDHCI
+int board_mmc_init(bd_t *bis)
+{
+	mv_sdh_init(MVEBU_SDIO_BASE, 0, 0,
+		    SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SCSI_AHCI_PLAT
+#define AHCI_VENDOR_SPECIFIC_0_ADDR	0xa0
+#define AHCI_VENDOR_SPECIFIC_0_DATA	0xa4
+
+#define AHCI_WINDOW_CTRL(win)		(0x60 + ((win) << 4))
+#define AHCI_WINDOW_BASE(win)		(0x64 + ((win) << 4))
+#define AHCI_WINDOW_SIZE(win)		(0x68 + ((win) << 4))
+
+static void ahci_mvebu_mbus_config(void __iomem *base)
+{
+	const struct mbus_dram_target_info *dram;
+	int i;
+
+	dram = mvebu_mbus_dram_info();
+
+	for (i = 0; i < 4; i++) {
+		writel(0, base + AHCI_WINDOW_CTRL(i));
+		writel(0, base + AHCI_WINDOW_BASE(i));
+		writel(0, base + AHCI_WINDOW_SIZE(i));
+	}
+
+	for (i = 0; i < dram->num_cs; i++) {
+		const struct mbus_dram_window *cs = dram->cs + i;
+
+		writel((cs->mbus_attr << 8) |
+		       (dram->mbus_dram_target_id << 4) | 1,
+		       base + AHCI_WINDOW_CTRL(i));
+		writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i));
+		writel(((cs->size - 1) & 0xffff0000),
+		       base + AHCI_WINDOW_SIZE(i));
+	}
+}
+
+static void ahci_mvebu_regret_option(void __iomem *base)
+{
+	/*
+	 * Enable the regret bit to allow the SATA unit to regret a
+	 * request that didn't receive an acknowlegde and avoid a
+	 * deadlock
+	 */
+	writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR);
+	writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA);
+}
+
+void scsi_init(void)
+{
+	printf("MVEBU SATA INIT\n");
+	ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE);
+	ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE);
+	ahci_init((void __iomem *)MVEBU_SATA0_BASE);
+}
+#endif
+
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
 {

arch/arm/mach-mvebu/include/mach/cpu.h

@@ -114,6 +114,8 @@ void mvebu_sdram_size_adjust(enum memory_bank bank);
 int mvebu_mbus_probe(struct mbus_win windows[], int count);
 int mvebu_soc_family(void);
 
+int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);
+
 /*
  * Highspeed SERDES PHY config init, ported from bin_hdr
  * to mainline U-Boot

arch/arm/mach-mvebu/include/mach/gpio.h

@@ -0,0 +1,10 @@
+/*
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#ifndef __MACH_MVEBU_GPIO_H
+#define __MACH_MVEBU_GPIO_H
+
+/* Empty file - sdhci requires this. */
+
+#endif

arch/arm/mach-mvebu/include/mach/soc.h

@@ -49,8 +49,11 @@
 #define MVEBU_EGIGA2_BASE	(MVEBU_REGISTER(0x30000))
 #define MVEBU_EGIGA3_BASE	(MVEBU_REGISTER(0x34000))
 #define MVEBU_REG_PCIE_BASE	(MVEBU_REGISTER(0x40000))
+#define MVEBU_USB20_BASE	(MVEBU_REGISTER(0x58000))
 #define MVEBU_EGIGA0_BASE	(MVEBU_REGISTER(0x70000))
 #define MVEBU_EGIGA1_BASE	(MVEBU_REGISTER(0x74000))
+#define MVEBU_SATA0_BASE	(MVEBU_REGISTER(0xa8000))
+#define MVEBU_SDIO_BASE		(MVEBU_REGISTER(0xd8000))
 
 #define SDRAM_MAX_CS		4
 #define SDRAM_ADDR_MASK		0xFF000000

arch/arm/mach-uniphier/cpu_info.c

@@ -34,6 +34,15 @@ int print_cpuinfo(void)
 	case 0x29:
 		puts("PH1-sLD8 (MN2WS0270)");
 		break;
+	case 0x2A:
+		puts("PH1-Pro5 (MN2WS0300)");
+		break;
+	case 0x2E:
+		puts("ProXstream2 (MN2WS0310)");
+		break;
+	case 0x2F:
+		puts("PH1-LD6b (MN2WS0320)");
+		break;
 	default:
 		printf("Unknown Processor ID (0x%x)\n", revision);
 		return -1;

arch/mips/include/asm/cacheops.h

@@ -18,7 +18,7 @@ static inline void mips_cache(int op, const volatile void *addr)
 #ifdef __GCC_HAVE_BUILTIN_MIPS_CACHE
 	__builtin_mips_cache(op, addr);
 #else
-	__asm__ __volatile__("cache %0, %1" : : "i"(op), "R"(addr))
+	__asm__ __volatile__("cache %0, %1" : : "i"(op), "R"(addr));
 #endif
 }
 

arch/mips/include/asm/io.h

@@ -117,7 +117,7 @@ static inline void set_io_port_base(unsigned long base)
  * Change virtual addresses to physical addresses and vv.
  * These are trivial on the 1:1 Linux/MIPS mapping
  */
-extern inline phys_addr_t virt_to_phys(volatile void * address)
+static inline phys_addr_t virt_to_phys(volatile void * address)
 {
 #ifndef CONFIG_64BIT
 	return CPHYSADDR(address);
@@ -126,7 +126,7 @@ extern inline phys_addr_t virt_to_phys(volatile void * address)
 #endif
 }
 
-extern inline void * phys_to_virt(unsigned long address)
+static inline void * phys_to_virt(unsigned long address)
 {
 #ifndef CONFIG_64BIT
 	return (void *)KSEG0ADDR(address);
@@ -138,7 +138,7 @@ extern inline void * phys_to_virt(unsigned long address)
 /*
  * IO bus memory addresses are also 1:1 with the physical address
  */
-extern inline unsigned long virt_to_bus(volatile void * address)
+static inline unsigned long virt_to_bus(volatile void * address)
 {
 #ifndef CONFIG_64BIT
 	return CPHYSADDR(address);
@@ -147,7 +147,7 @@ extern inline unsigned long virt_to_bus(volatile void * address)
 #endif
 }
 
-extern inline void * bus_to_virt(unsigned long address)
+static inline void * bus_to_virt(unsigned long address)
 {
 #ifndef CONFIG_64BIT
 	return (void *)KSEG0ADDR(address);
@@ -165,12 +165,12 @@ extern unsigned long isa_slot_offset;
 extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
 
 #if 0
-extern inline void *ioremap(unsigned long offset, unsigned long size)
+static inline void *ioremap(unsigned long offset, unsigned long size)
 {
 	return __ioremap(offset, size, _CACHE_UNCACHED);
 }
 
-extern inline void *ioremap_nocache(unsigned long offset, unsigned long size)
+static inline void *ioremap_nocache(unsigned long offset, unsigned long size)
 {
 	return __ioremap(offset, size, _CACHE_UNCACHED);
 }

arch/mips/include/asm/system.h

@@ -22,7 +22,7 @@
 #include <linux/kernel.h>
 #endif
 
-extern __inline__ void
+static __inline__ void
 __sti(void)
 {
 	__asm__ __volatile__(
@@ -46,7 +46,7 @@ __sti(void)
  * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
  * no nops at all.
  */
-extern __inline__ void
+static __inline__ void
 __cli(void)
 {
 	__asm__ __volatile__(
@@ -207,7 +207,7 @@ do { \
  * For 32 and 64 bit operands we can take advantage of ll and sc.
  * FIXME: This doesn't work for R3000 machines.
  */
-extern __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val)
+static __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val)
 {
 #ifdef CONFIG_CPU_HAS_LLSC
 	unsigned long dummy;

board/Marvell/db-88f6820-gp/MAINTAINERS

@@ -0,0 +1,6 @@
+DB_88F6820_GP BOARD
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/Marvell/db-88f6820-gp/
+F:	include/configs/db-88f6820-gp.h
+F:	configs/db-88f6820-gp_defconfig

board/quipos/cairo/MAINTAINERS

@@ -0,0 +1,6 @@
+CAIRO BOARD
+M:	Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
+S:	Maintained
+F:	board/quipos/cairo/
+F:	include/configs/omap3_cairo.h
+F:	configs/cairo_defconfig

board/samsung/smdk5420/MAINTAINERS

@@ -14,3 +14,4 @@ M:	Przemyslaw Marczak <p.marczak@samsung.com>
 S:	Maintained
 F:	board/samsung/smdk5420/
 F:	include/configs/odroid_xu3.h
+F:	configs/odroid-xu3_defconfig

board/solidrun/mx6cuboxi/mx6cuboxi.c

@@ -536,7 +536,7 @@ static const struct mx6_mmdc_calibration mx6dl_1g_mmcd_calib = {
 	.p0_mpdgctrl0 =    0x023C0224,
 	.p0_mpdgctrl1 =    0x02000220,
 	.p1_mpdgctrl0 =    0x02200220,
-	.p1_mpdgctrl1 =    0x02000220,
+	.p1_mpdgctrl1 =    0x02040208,
 	.p0_mprddlctl =    0x44444846,
 	.p1_mprddlctl =    0x4042463C,
 	.p0_mpwrdlctl =    0x32343032,
@@ -627,7 +627,7 @@ static void spl_dram_init(int width)
 	else if (is_cpu_type(MXC_CPU_MX6Q))
 		mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
 	else if (is_cpu_type(MXC_CPU_MX6DL))
-		mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g);
+		mx6_dram_cfg(&sysinfo, &mx6dl_1g_mmcd_calib, &mem_ddr_2g);
 	else if (is_cpu_type(MXC_CPU_MX6SOLO))
 		mx6_dram_cfg(&sysinfo, &mx6dl_512m_mmcd_calib, &mem_ddr_2g);
 }

board/st/stm32f429-discovery/MAINTAINERS

@@ -1,3 +1,4 @@
+STM32F429-DISCOVERY BOARD
 M:	Kamil Lulko <rev13@wp.pl>
 S:	Maintained
 F:	board/st/stm32f429-discovery/

board/sunxi/MAINTAINERS

@@ -162,6 +162,12 @@ M:	Siarhei Siamashka <siarhei.siamashka@gmail.com>
 S:	Maintained
 F:	configs/MSI_Primo81_defconfig
 
+SINLINX SINA33 BOARD
+M:	Chen-Yu Tsai <wens@csie.org>
+S:	Maintained
+F:	configs/Sinlinx_SinA33_defconfig
+W:	http://linux-sunxi.org/Sinlinx_SinA33
+
 TZX-Q8-713B7 BOARD
 M:	Paul Kocialkowski <contact@paulk.fr>
 S:	Maintained

board/synopsys/axs101/MAINTAINERS

@@ -4,3 +4,4 @@ S:	Maintained
 F:	board/synopsys/axs101/
 F:	include/configs/axs101.h
 F:	configs/axs101_defconfig
+F:	configs/axs103_defconfig

board/synopsys/axs101/axs101.c

@@ -56,3 +56,33 @@ int board_early_init_f(void)
 
 	return 0;
 }
+
+#ifdef CONFIG_ISA_ARCV2
+#define RESET_VECTOR_ADDR	0x0
+
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+	/* All cores have reset vector pointing to 0 */
+	writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
+
+	/* Make sure other cores see written value in memory */
+	flush_dcache_range(RESET_VECTOR_ADDR, RESET_VECTOR_ADDR + sizeof(int));
+}
+
+void smp_kick_all_cpus(void)
+{
+/* CPU start CREG */
+#define AXC003_CREG_CPU_START	0xF0001400
+
+/* Bits positions in CPU start CREG */
+#define BITS_START	0
+#define BITS_POLARITY	8
+#define BITS_CORE_SEL	9
+#define BITS_MULTICORE	12
+
+#define CMD	(1 << BITS_MULTICORE) | (1 << BITS_CORE_SEL) | \
+		(1 << BITS_POLARITY) | (1 << BITS_START)
+
+	writel(CMD, (void __iomem *)AXC003_CREG_CPU_START);
+}
+#endif

board/ti/am43xx/MAINTAINERS

@@ -5,3 +5,5 @@ F:	board/ti/am43xx/
 F:	include/configs/am43xx_evm.h
 F:	configs/am43xx_evm_defconfig
 F:	configs/am43xx_evm_qspiboot_defconfig
+F:	configs/am43xx_evm_ethboot_defconfig
+F:	configs/am43xx_evm_usbhost_boot_defconfig

board/ti/beagle_x15/mux_data.h

@@ -244,8 +244,8 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
 	{SPI2_D1, (M14 | PIN_INPUT_PULLDOWN)},	/* spi2_d1.gpio7_15 */
 	{SPI2_D0, (M14 | PIN_INPUT_PULLUP)},	/* spi2_d0.gpio7_16 */
 	{SPI2_CS0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* spi2_cs0.gpio7_17 */
-	{DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* dcan1_tx.dcan1_tx */
-	{DCAN1_RX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* dcan1_rx.dcan1_rx */
+	{DCAN1_TX, (M15 | PULL_UP)},	/* dcan1_tx.safe for dcan1_tx */
+	{DCAN1_RX, (M15 | PULL_UP)},	/* dcan1_rx.safe for dcan1_rx */
 	{UART1_RXD, (M0 | PIN_INPUT_SLEW)},	/* uart1_rxd.uart1_rxd */
 	{UART1_TXD, (M0 | PIN_INPUT_SLEW)},	/* uart1_txd.uart1_txd */
 	{UART1_CTSN, (M15 | PIN_INPUT_PULLDOWN)},	/* uart1_ctsn.Driveroff */

board/ti/dra7xx/mux_data.h

@@ -156,30 +156,31 @@ const struct pad_conf_entry early_padconf[] = {
 
 #ifdef CONFIG_IODELAY_RECALIBRATION
 const struct iodelay_cfg_entry iodelay_cfg_array[] = {
-	{0x6F0, 480, 0}, /* RGMMI0_RXC_IN */
-	{0x6FC, 111, 1641}, /* RGMMI0_RXCTL_IN */
-	{0x708, 272, 1116}, /* RGMMI0_RXD0_IN */
-	{0x714, 243, 1260}, /* RGMMI0_RXD1_IN */
-	{0x720, 0, 1614}, /* RGMMI0_RXD2_IN */
-	{0x72C, 105, 1673}, /* RGMMI0_RXD3_IN */
-	{0x740, 531, 120}, /* RGMMI0_TXC_OUT */
-	{0x74C, 11, 60}, /* RGMMI0_TXCTL_OUT */
-	{0x758, 7, 120}, /* RGMMI0_TXD0_OUT */
-	{0x764, 0, 0}, /* RGMMI0_TXD1_OUT */
-	{0x770, 276, 120}, /* RGMMI0_TXD2_OUT */
-	{0x77C, 440, 120}, /* RGMMI0_TXD3_OUT */
-	{0xAB0, 702, 0}, /* CFG_VIN2A_D18_IN */
-	{0xABC, 136, 976}, /* CFG_VIN2A_D19_IN */
-	{0xAD4, 210, 1357}, /* CFG_VIN2A_D20_IN */
-	{0xAE0, 189, 1462}, /* CFG_VIN2A_D21_IN */
-	{0xAEC, 232, 1278}, /* CFG_VIN2A_D22_IN */
-	{0xAF8, 0, 1397}, /* CFG_VIN2A_D23_IN */
-	{0xA70, 1551, 115}, /* CFG_VIN2A_D12_OUT */
-	{0xA7C, 816, 0}, /* CFG_VIN2A_D13_OUT */
-	{0xA88, 876, 0}, /* CFG_VIN2A_D14_OUT */
-	{0xA94, 312, 0}, /* CFG_VIN2A_D15_OUT */
-	{0xAA0, 58, 0}, /* CFG_VIN2A_D16_OUT */
-	{0xAAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
+	{0x6F0, 359, 0}, /* RGMMI0_RXC_IN */
+	{0x6FC, 129, 1896}, /* RGMMI0_RXCTL_IN */
+	{0x708, 80, 1391}, /* RGMMI0_RXD0_IN */
+	{0x714, 196, 1522}, /* RGMMI0_RXD1_IN */
+	{0x720, 40, 1860}, /* RGMMI0_RXD2_IN */
+	{0x72C, 0, 1956}, /* RGMMI0_RXD3_IN */
+	{0x740, 0, 220}, /* RGMMI0_TXC_OUT */
+	{0x74C, 1820, 180}, /* RGMMI0_TXCTL_OUT */
+	{0x758, 1740, 440}, /* RGMMI0_TXD0_OUT */
+	{0x764, 1740, 240}, /* RGMMI0_TXD1_OUT */
+	{0x770, 1680, 380}, /* RGMMI0_TXD2_OUT */
+	{0x77C, 1740, 440}, /* RGMMI0_TXD3_OUT */
+	/* These values are for using RGMII1 configuration on VIN2a_x pins. */
+	{0xAB0, 596, 0}, /* CFG_VIN2A_D18_IN */
+	{0xABC, 314, 980}, /* CFG_VIN2A_D19_IN */
+	{0xAD4, 241, 1536}, /* CFG_VIN2A_D20_IN */
+	{0xAE0, 103, 1689}, /* CFG_VIN2A_D21_IN */
+	{0xAEC, 161, 1563}, /* CFG_VIN2A_D22_IN */
+	{0xAF8, 0, 1613}, /* CFG_VIN2A_D23_IN */
+	{0xA70, 0, 200}, /* CFG_VIN2A_D12_OUT */
+	{0xA7C, 1560, 140}, /* CFG_VIN2A_D13_OUT */
+	{0xA88, 1700, 0}, /* CFG_VIN2A_D14_OUT */
+	{0xA94, 1260, 0}, /* CFG_VIN2A_D15_OUT */
+	{0xAA0, 1400, 0}, /* CFG_VIN2A_D16_OUT */
+	{0xAAC, 1290, 0}, /* CFG_VIN2A_D17_OUT */
 };
 #endif
 
@@ -358,7 +359,7 @@ const struct pad_conf_entry dra74x_core_padconf_array[] = {
 	{SPI2_D1, (M1 | PIN_INPUT_SLEW)},	/* spi2_d1.uart3_txd */
 	{SPI2_D0, (M1 | PIN_INPUT_SLEW)},	/* spi2_d0.uart3_ctsn */
 	{SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* spi2_cs0.uart3_rtsn */
-	{DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* dcan1_tx.dcan1_tx */
+	{DCAN1_TX, (M15 | PULL_UP)},	/* dcan1_tx.safe for dcan1_tx */
 	{DCAN1_RX, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* dcan1_rx.gpio1_15 */
 	{UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* uart1_rxd.uart1_rxd */
 	{UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* uart1_txd.uart1_txd */
@@ -370,7 +371,7 @@ const struct pad_conf_entry dra74x_core_padconf_array[] = {
 	{UART2_RTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart2_rtsn.mmc4_dat3 */
 	{I2C2_SDA, (M0 | PIN_INPUT_PULLUP)},	/* i2c2_sda.i2c2_sda */
 	{I2C2_SCL, (M0 | PIN_INPUT_PULLUP)},	/* i2c2_scl.i2c2_scl */
-	{WAKEUP0, (M1 | PIN_OUTPUT)},	/* Wakeup0.dcan1_rx */
+	{WAKEUP0, (M15 | PULL_UP)},	/* Wakeup0.safe for dcan1_rx */
 	{WAKEUP2, (M14 | PIN_OUTPUT)},	/* Wakeup2.gpio1_2 */
 };
 

board/tqc/tqma6/Kconfig

@@ -12,4 +12,62 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "tqma6"
 
+choice
+	prompt "TQMa6 SoC variant"
+	default TQMA6Q
+	help
+	  select the TQMa6 module variant. The variants differing in the used
+	  i.MX6 CPU type and DRAM
+
+config TQMA6Q
+	bool "TQMa6Q / TQMa6D"
+	select MX6Q
+	help
+	  select TQMa6Q / TQMa6D with i.MX6Q/D and 1GiB DRAM
+
+config TQMA6S
+	bool "TQMa6S"
+	select MX6S
+	help
+	  select TQMa6S with i.MX6S and 512 MiB DRAM
+
+endchoice
+
+choice
+	prompt "TQMa6 boot configuration"
+	default TQMA6X_MMC_BOOT
+	help
+	  Configure boot device. This is also used to implement environment
+	  location.
+
+config TQMA6X_MMC_BOOT
+	bool "MMC / SD Boot"
+	help
+	  Boot from eMMC / SD Card
+
+config TQMA6X_SPI_BOOT
+	bool "SPI NOR Boot"
+	help
+	  Boot from on board SPI NOR flash
+
+endchoice
+
+choice
+	prompt "TQMa6 base board variant"
+	default MBA6
+	help
+	  Select base board for TQMa6
+
+config MBA6
+	bool "TQMa6 on MBa6 Starterkit"
+	help
+	  Select the MBa6 starterkit. This features a GigE Phy, USB, SD-Card
+	  etc.
+
+endchoice
+
+config IMX_CONFIG
+	default "board/tqc/tqma6/tqma6q.cfg" if TQMA6Q
+	default "board/tqc/tqma6/tqma6s.cfg" if TQMA6S
+
 endif

board/vscom/baltos/MAINTAINERS

@@ -0,0 +1,6 @@
+BALTOS BOARD
+M:	Yegor Yefremov <yegorslists@googlemail.com>
+S:	Maintained
+F:	board/vscom/baltos/
+F:	include/configs/baltos.h
+F:	configs/am335x_baltos_defconfig

board/vscom/baltos/board.c

@@ -184,6 +184,8 @@ void am33xx_spl_board_init(void)
 	 */
 	i2c_set_bus_num(1);
 
+	printf("I2C speed: %d Hz\n", CONFIG_SYS_OMAP24_I2C_SPEED);
+
 	if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) {
 		puts("i2c: cannot access TPS65910\n");
 		return;

common/Kconfig

@@ -311,6 +311,11 @@ config CMD_NAND
 	help
 	  NAND support.
 
+config CMD_SF
+	bool "sf"
+	help
+	  SPI Flash support
+
 config CMD_SPI
 	bool "sspi"
 	help

common/cmd_scsi.c

@@ -368,7 +368,7 @@ static ulong scsi_read(int device, lbaint_t blknr, lbaint_t blkcnt,
 {
 	lbaint_t start, blks;
 	uintptr_t buf_addr;
-	unsigned short smallblks;
+	unsigned short smallblks = 0;
 	ccb* pccb=(ccb *)&tempccb;
 	device&=0xff;
 	/* Setup  device
@@ -391,7 +391,7 @@ static ulong scsi_read(int device, lbaint_t blknr, lbaint_t blkcnt,
 			scsi_setup_read16(pccb, start, blocks);
 			start += blocks;
 			blks -= blocks;
-		} else 
+		} else
 #endif
 		if (blks > SCSI_MAX_READ_BLK) {
 			pccb->datalen=scsi_dev_desc[device].blksz * SCSI_MAX_READ_BLK;

configs/Ippo_q8h_v1_2_a33_1024x600_defconfig

@@ -12,7 +12,7 @@ CONFIG_VIDEO_LCD_POWER="PH7"
 CONFIG_VIDEO_LCD_BL_EN="PH6"
 CONFIG_VIDEO_LCD_BL_PWM="PH0"
 CONFIG_USB_MUSB_SUNXI=y
-CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-ippo-q8h-v1.2-lcd1024x600"
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-ippo-q8h-v1.2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"

configs/Sinlinx_SinA33_defconfig

@@ -0,0 +1,16 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_A33=y
+CONFIG_DRAM_CLK=552
+CONFIG_DRAM_ZQ=15291
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
+CONFIG_AXP221_ALDO1_VOLT=3000
+CONFIG_USB=y
+CONFIG_DM_USB=y

configs/alt_defconfig

@@ -17,4 +17,5 @@ CONFIG_TARGET_ALT=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_MISC is not set
 CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_SH_SDHI=y

configs/am335x_baltos_defconfig

@@ -3,9 +3,9 @@ CONFIG_TARGET_AM335X_BALTOS=y
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
-CONFIG_CONS_INDEX=1
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set

configs/am43xx_evm_defconfig

@@ -5,4 +5,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH=y

configs/bf533-stamp_defconfig

@@ -2,4 +2,5 @@ CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF533_STAMP=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
+# CONFIG_REGEX is not set
 CONFIG_LIB_RAND=y

configs/bf538f-ezkit_defconfig

@@ -2,4 +2,5 @@ CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF538F_EZKIT=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
+# CONFIG_REGEX is not set
 CONFIG_LIB_RAND=y

configs/bg0900_defconfig

@@ -4,3 +4,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y

configs/cm-bf548_defconfig

@@ -2,4 +2,5 @@ CONFIG_BLACKFIN=y
 CONFIG_TARGET_CM_BF548=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
+# CONFIG_REGEX is not set
 CONFIG_LIB_RAND=y

configs/dra7xx_evm_defconfig

@@ -8,3 +8,4 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
 CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y

configs/gose_defconfig

@@ -17,4 +17,5 @@ CONFIG_TARGET_GOSE=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_MISC is not set
 CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_SH_SDHI=y

configs/koelsch_defconfig

@@ -17,4 +17,5 @@ CONFIG_TARGET_KOELSCH=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_MISC is not set
 CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_SH_SDHI=y

configs/lager_defconfig

@@ -17,4 +17,5 @@ CONFIG_TARGET_LAGER=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_MISC is not set
 CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_SH_SDHI=y

configs/maxbcm_defconfig

@@ -5,3 +5,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y

configs/mx6sxsabresd_defconfig

@@ -5,3 +5,4 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg,M
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y

configs/ph1_ld4_defconfig

@@ -7,10 +7,6 @@ CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_HUSH_PARSER=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_DELAY_STR="d"
-CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_ENV_EXISTS is not set
 CONFIG_CMD_NAND=y

configs/ph1_pro4_defconfig

@@ -6,10 +6,6 @@ CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_HUSH_PARSER=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_DELAY_STR="d"
-CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_ENV_EXISTS is not set
 CONFIG_CMD_NAND=y

configs/ph1_sld8_defconfig

@@ -7,10 +7,6 @@ CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld8-ref"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_HUSH_PARSER=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_DELAY_STR="d"
-CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_ENV_EXISTS is not set
 CONFIG_CMD_NAND=y

configs/porter_defconfig

@@ -17,4 +17,5 @@ CONFIG_TARGET_PORTER=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_MISC is not set
 CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_SH_SDHI=y

configs/silk_defconfig

@@ -17,4 +17,5 @@ CONFIG_TARGET_SILK=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_MISC is not set
 CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_SH_SDHI=y

configs/tbs2910_defconfig

@@ -3,3 +3,5 @@ CONFIG_TARGET_TBS2910=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_DM=y
+CONFIG_DM_THERMAL=y

configs/tqma6q_mba6_mmc_defconfig

@@ -1,6 +1,6 @@
 CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TQMA6=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/tqc/tqma6/tqma6q.cfg,MX6Q,MBA6,TQMA6X_MMC_BOOT"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y

configs/tqma6q_mba6_spi_defconfig

@@ -1,6 +1,7 @@
 CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TQMA6=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/tqc/tqma6/tqma6q.cfg,MX6Q,MBA6,TQMA6X_SPI_BOOT"
+CONFIG_TQMA6X_SPI_BOOT=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y

configs/tqma6s_mba6_mmc_defconfig

@@ -1,6 +1,7 @@
 CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TQMA6=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/tqc/tqma6/tqma6s.cfg,MX6S,MBA6,TQMA6X_MMC_BOOT"
+CONFIG_TQMA6S=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y

configs/tqma6s_mba6_spi_defconfig

@@ -1,6 +1,8 @@
 CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TQMA6=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/tqc/tqma6/tqma6s.cfg,MX6S,MBA6,TQMA6X_SPI_BOOT"
+CONFIG_TQMA6S=y
+CONFIG_TQMA6X_SPI_BOOT=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y

configs/zynq_microzed_defconfig

@@ -10,5 +10,3 @@ CONFIG_FIT_SIGNATURE=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_DISABLE_OF_CONTROL=y

configs/zynq_zc702_defconfig

@@ -10,4 +10,3 @@ CONFIG_FIT_SIGNATURE=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y

configs/zynq_zc706_defconfig

@@ -10,4 +10,3 @@ CONFIG_FIT_SIGNATURE=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y

configs/zynq_zc70x_defconfig

@@ -10,5 +10,3 @@ CONFIG_FIT_SIGNATURE=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_DISABLE_OF_CONTROL=y

configs/zynq_zc770_xm010_defconfig

@@ -11,6 +11,4 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_DISABLE_OF_CONTROL=y
 CONFIG_SPI_FLASH=y

configs/zynq_zc770_xm012_defconfig

@@ -9,5 +9,3 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012"
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_DISABLE_OF_CONTROL=y