Prepare v2016.01

Signed-off-by: Tom Rini <trini@konsulko.com>

.mailmap

@@ -12,7 +12,7 @@ Allen Martin <amartin@nvidia.com>
 Andreas Bießmann <andreas.devel@googlemail.com>
 Aneesh V <aneesh@ti.com>
 Dirk Behme <dirk.behme@googlemail.com>
-Fabio Estevam <fabio.estevam@freescale.com>
+Fabio Estevam <fabio.estevam@nxp.com>
 Jagan Teki <402jagan@gmail.com>
 Jagan Teki <jaganna@gmail.com>
 Jagan Teki <jaganna@xilinx.com>
@@ -28,4 +28,5 @@ Stefano Babic <sbabic@denx.de>
 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Wolfgang Denk <wdenk>
 York Sun <yorksun@freescale.com>
+York Sun <york.sun@nxp.com>
 Łukasz Majewski <l.majewski@samsung.com>

MAINTAINERS

@@ -161,7 +161,7 @@ M:	Masahiro Yamada <yamada.masahiro@socionext.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-uniphier.git
 F:	arch/arm/mach-uniphier/
-F:	configs/ph1_*_defconfig
+F:	configs/uniphier_*_defconfig
 N:	uniphier
 
 ARM ZYNQ
@@ -239,7 +239,7 @@ S:	Maintained
 T:	git git://git.denx.de/u-boot-freebsd.git
 
 FREESCALE QORIQ
-M:	York Sun <yorksun@freescale.com>
+M:	York Sun <york.sun@nxp.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-fsl-qoriq.git
 
@@ -308,13 +308,13 @@ F:	arch/powerpc/cpu/mpc83xx/
 F:	arch/powerpc/include/asm/arch-mpc83xx/
 
 POWERPC MPC85XX
-M:	York Sun <yorksun@freescale.com>
+M:	York Sun <york.sun@nxp.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-mpc85xx.git
 F:	arch/powerpc/cpu/mpc85xx/
 
 POWERPC MPC86XX
-M:	York Sun <yorksun@freescale.com>
+M:	York Sun <york.sun@nxp.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-mpc86xx.git
 F:	arch/powerpc/cpu/mpc86xx/

Makefile

@@ -5,7 +5,7 @@
 VERSION = 2016
 PATCHLEVEL = 01
 SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION =
 NAME =
 
 # *DOCUMENTATION*
@@ -1136,7 +1136,7 @@ spl/u-boot-spl.pbl: spl/u-boot-spl.bin FORCE
 	$(call if_changed,mkimage)
 
 ifeq ($(ARCH),arm)
-ifdef CONFIG_DM
+ifdef CONFIG_OF_CONTROL
 UBOOT_BINLOAD := u-boot-dtb.img
 else
 UBOOT_BINLOAD := u-boot.img

README

@@ -34,12 +34,14 @@ In general, all boards for which a configuration option exists in the
 Makefile have been tested to some extent and can be considered
 "working". In fact, many of them are used in production systems.
 
-In case of problems see the CHANGELOG and CREDITS files to find out
-who contributed the specific port. The boards.cfg file lists board
-maintainers.
+In case of problems see the CHANGELOG file to find out who contributed
+the specific port. In addition, there are various MAINTAINERS files
+scattered throughout the U-Boot source identifying the people or
+companies responsible for various boards and subsystems.
 
-Note: There is no CHANGELOG file in the actual U-Boot source tree;
-it can be created dynamically from the Git log using:
+Note: As of August, 2010, there is no longer a CHANGELOG file in the
+actual U-Boot source tree; however, it can be created dynamically
+from the Git log using:
 
 	make CHANGELOG
 
@@ -48,7 +50,7 @@ Where to get help:
 ==================
 
 In case you have questions about, problems with or contributions for
-U-Boot you should send a message to the U-Boot mailing list at
+U-Boot, you should send a message to the U-Boot mailing list at
 <u-boot@lists.denx.de>. There is also an archive of previous traffic
 on the mailing list - please search the archive before asking FAQ's.
 Please see http://lists.denx.de/pipermail/u-boot and
@@ -58,7 +60,7 @@ http://dir.gmane.org/gmane.comp.boot-loaders.u-boot
 Where to get source code:
 =========================
 
-The U-Boot source code is maintained in the git repository at
+The U-Boot source code is maintained in the Git repository at
 git://www.denx.de/git/u-boot.git ; you can browse it online at
 http://www.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=summary
 
@@ -133,79 +135,24 @@ Directory Hierarchy:
 
 /arch			Architecture specific files
   /arc			Files generic to ARC architecture
-    /cpu		CPU specific files
-      /arc700		Files specific to ARC 700 CPUs
-    /lib		Architecture specific library files
   /arm			Files generic to ARM architecture
-    /cpu		CPU specific files
-      /arm720t		Files specific to ARM 720 CPUs
-      /arm920t		Files specific to ARM 920 CPUs
-	/at91		Files specific to Atmel AT91RM9200 CPU
-	/imx		Files specific to Freescale MC9328 i.MX CPUs
-	/s3c24x0	Files specific to Samsung S3C24X0 CPUs
-      /arm926ejs	Files specific to ARM 926 CPUs
-      /arm1136		Files specific to ARM 1136 CPUs
-      /pxa		Files specific to Intel XScale PXA CPUs
-      /sa1100		Files specific to Intel StrongARM SA1100 CPUs
-    /lib		Architecture specific library files
   /avr32		Files generic to AVR32 architecture
-    /cpu		CPU specific files
-    /lib		Architecture specific library files
   /blackfin		Files generic to Analog Devices Blackfin architecture
-    /cpu		CPU specific files
-    /lib		Architecture specific library files
   /m68k			Files generic to m68k architecture
-    /cpu		CPU specific files
-      /mcf52x2		Files specific to Freescale ColdFire MCF52x2 CPUs
-      /mcf5227x		Files specific to Freescale ColdFire MCF5227x CPUs
-      /mcf532x		Files specific to Freescale ColdFire MCF5329 CPUs
-      /mcf5445x		Files specific to Freescale ColdFire MCF5445x CPUs
-      /mcf547x_8x	Files specific to Freescale ColdFire MCF547x_8x CPUs
-    /lib		Architecture specific library files
   /microblaze		Files generic to microblaze architecture
-    /cpu		CPU specific files
-    /lib		Architecture specific library files
   /mips			Files generic to MIPS architecture
-    /cpu		CPU specific files
-      /mips32		Files specific to MIPS32 CPUs
-      /mips64		Files specific to MIPS64 CPUs
-    /lib		Architecture specific library files
   /nds32		Files generic to NDS32 architecture
-    /cpu		CPU specific files
-      /n1213		Files specific to Andes Technology N1213 CPUs
-    /lib		Architecture specific library files
   /nios2		Files generic to Altera NIOS2 architecture
-    /cpu		CPU specific files
-    /lib		Architecture specific library files
   /openrisc		Files generic to OpenRISC architecture
-    /cpu		CPU specific files
-    /lib		Architecture specific library files
   /powerpc		Files generic to PowerPC architecture
-    /cpu		CPU specific files
-      /mpc5xx		Files specific to Freescale MPC5xx CPUs
-      /mpc5xxx		Files specific to Freescale MPC5xxx CPUs
-      /mpc8xx		Files specific to Freescale MPC8xx CPUs
-      /mpc8260		Files specific to Freescale MPC8260 CPUs
-      /mpc85xx		Files specific to Freescale MPC85xx CPUs
-      /ppc4xx		Files specific to AMCC PowerPC 4xx CPUs
-    /lib		Architecture specific library files
+  /sandbox		Files generic to HW-independent "sandbox"
   /sh			Files generic to SH architecture
-    /cpu		CPU specific files
-      /sh2		Files specific to sh2 CPUs
-      /sh3		Files specific to sh3 CPUs
-      /sh4		Files specific to sh4 CPUs
-    /lib		Architecture specific library files
   /sparc		Files generic to SPARC architecture
-    /cpu		CPU specific files
-      /leon2		Files specific to Gaisler LEON2 SPARC CPU
-      /leon3		Files specific to Gaisler LEON3 SPARC CPU
-    /lib		Architecture specific library files
   /x86			Files generic to x86 architecture
-    /cpu		CPU specific files
-    /lib		Architecture specific library files
 /api			Machine/arch independent API for external apps
 /board			Board dependent files
 /common			Misc architecture independent functions
+/configs		Board default configuration files
 /disk			Code for disk drive partition handling
 /doc			Documentation (don't expect too much)
 /drivers		Commonly used device drivers
@@ -213,13 +160,12 @@ Directory Hierarchy:
 /examples		Example code for standalone applications, etc.
 /fs			Filesystem code (cramfs, ext2, jffs2, etc.)
 /include		Header Files
-/lib			Files generic to all architectures
-  /libfdt		Library files to support flattened device trees
-  /lzma			Library files to support LZMA decompression
-  /lzo			Library files to support LZO decompression
+/lib			Library routines generic to all architectures
+/Licenses		Various license files
 /net			Networking code
 /post			Power On Self Test
-/spl			Secondary Program Loader framework
+/scripts		Various build scripts and Makefiles
+/test			Various unit test files
 /tools			Tools to build S-Record or U-Boot images, etc.
 
 Software Configuration:
@@ -239,11 +185,11 @@ There are two classes of configuration variables:
   you don't know what you're doing; they have names beginning with
   "CONFIG_SYS_".
 
-Later we will add a configuration tool - probably similar to or even
-identical to what's used for the Linux kernel. Right now, we have to
-do the configuration by hand, which means creating some symbolic
-links and editing some configuration files. We use the TQM8xxL boards
-as an example here.
+Previously, all configuration was done by hand, which involved creating
+symbolic links and editing configuration files manually. More recently,
+U-Boot has added the Kbuild infrastructure used by the Linux kernel,
+allowing you to use the "make menuconfig" command to configure your
+build.
 
 
 Selection of Processor Architecture and Board Type:
@@ -257,10 +203,9 @@ Example: For a TQM823L module type:
 	cd u-boot
 	make TQM823L_defconfig
 
-For the Cogent platform, you need to specify the CPU type as well;
-e.g. "make cogent_mpc8xx_defconfig". And also configure the cogent
-directory according to the instructions in cogent/README.
-
+Note: If you're looking for the default configuration file for a board
+you're sure used to be there but is now missing, check the file
+doc/README.scrapyard for a list of no longer supported boards.
 
 Sandbox Environment:
 --------------------
@@ -277,13 +222,25 @@ Board Initialisation Flow:
 --------------------------
 
 This is the intended start-up flow for boards. This should apply for both
-SPL and U-Boot proper (i.e. they both follow the same rules). At present SPL
-mostly uses a separate code path, but the funtion names and roles of each
-function are the same. Some boards or architectures may not conform to this.
-At least most ARM boards which use CONFIG_SPL_FRAMEWORK conform to this.
+SPL and U-Boot proper (i.e. they both follow the same rules).
 
-Execution starts with start.S with three functions called during init after
-that. The purpose and limitations of each is described below.
+Note: "SPL" stands for "Secondary Program Loader," which is explained in
+more detail later in this file.
+
+At present, SPL mostly uses a separate code path, but the function names
+and roles of each function are the same. Some boards or architectures
+may not conform to this.  At least most ARM boards which use
+CONFIG_SPL_FRAMEWORK conform to this.
+
+Execution typically starts with an architecture-specific (and possibly
+CPU-specific) start.S file, such as:
+
+	- arch/arm/cpu/armv7/start.S
+	- arch/powerpc/cpu/mpc83xx/start.S
+	- arch/mips/cpu/start.S
+
+and so on. From there, three functions are called; the purpose and
+limitations of each of these functions are described below.
 
 lowlevel_init():
 	- purpose: essential init to permit execution to reach board_init_f()
@@ -6630,7 +6587,8 @@ it:
 
 * A CHANGELOG entry as plaintext (separate from the patch)
 
-* For major contributions, your entry to the CREDITS file
+* For major contributions, add a MAINTAINERS file with your
+  information and associated file and directory references.
 
 * When you add support for a new board, don't forget to add a
   maintainer e-mail address to the boards.cfg file, too.

arch/arm/cpu/arm926ejs/mxs/spl_power_init.c

@@ -247,6 +247,39 @@ static void mxs_power_setup_5v_detect(void)
 			POWER_5VCTRL_PWRUP_VBUS_CMPS);
 }
 
+/**
+ * mxs_power_switch_dcdc_clocksource() - Switch PLL clock for DC-DC converters
+ * @freqsel:	One of the POWER_MISC_FREQSEL_xxx defines to select the clock
+ *
+ * This function configures and then enables an alternative PLL clock source
+ * for the DC-DC converters.
+ */
+void mxs_power_switch_dcdc_clocksource(uint32_t freqsel)
+{
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+
+	/* Select clocksource for DC-DC converters */
+	clrsetbits_le32(&power_regs->hw_power_misc,
+			POWER_MISC_FREQSEL_MASK,
+			freqsel);
+	setbits_le32(&power_regs->hw_power_misc,
+			POWER_MISC_SEL_PLLCLK);
+}
+
+/**
+ * mxs_power_setup_dcdc_clocksource() - Setup PLL clock source for DC-DC converters
+ *
+ * Normally, there is no need to switch DC-DC clocksource. This is the reason,
+ * why this function is a stub and does nothing. However, boards can implement
+ * this function when required and call mxs_power_switch_dcdc_clocksource() to
+ * switch to an alternative clock source.
+ */
+__weak void mxs_power_setup_dcdc_clocksource(void)
+{
+	debug("SPL: Using default DC-DC clocksource\n");
+}
+
 /**
  * mxs_src_power_init() - Preconfigure the power block
  *
@@ -872,6 +905,7 @@ static void mxs_power_configure_power_source(void)
 
 	debug("SPL: Configuring power source\n");
 
+	mxs_power_setup_dcdc_clocksource();
 	mxs_src_power_init();
 
 	if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {

arch/arm/cpu/armv7/am33xx/board.c

@@ -64,8 +64,31 @@ U_BOOT_DEVICES(am33xx_uarts) = {
 #   endif
 #  endif
 };
-#endif
 
+#ifdef CONFIG_DM_GPIO
+static const struct omap_gpio_platdata am33xx_gpio[] = {
+	{ 0, AM33XX_GPIO0_BASE },
+	{ 1, AM33XX_GPIO1_BASE },
+	{ 2, AM33XX_GPIO2_BASE },
+	{ 3, AM33XX_GPIO3_BASE },
+#ifdef CONFIG_AM43XX
+	{ 4, AM33XX_GPIO4_BASE },
+	{ 5, AM33XX_GPIO5_BASE },
+#endif
+};
+
+U_BOOT_DEVICES(am33xx_gpios) = {
+	{ "gpio_omap", &am33xx_gpio[0] },
+	{ "gpio_omap", &am33xx_gpio[1] },
+	{ "gpio_omap", &am33xx_gpio[2] },
+	{ "gpio_omap", &am33xx_gpio[3] },
+#ifdef CONFIG_AM43XX
+	{ "gpio_omap", &am33xx_gpio[4] },
+	{ "gpio_omap", &am33xx_gpio[5] },
+#endif
+};
+#endif
+#endif
 
 #ifndef CONFIG_DM_GPIO
 static const struct gpio_bank gpio_bank_am33xx[] = {

arch/arm/cpu/armv7/mx6/clock.c

@@ -727,6 +727,8 @@ int enable_lcdif_clock(u32 base_addr)
 	reg = readl(&imx_ccm->CCGR2);
 	reg |= MXC_CCM_CCGR2_LCD_MASK;
 	writel(reg, &imx_ccm->CCGR2);
+
+	return 0;
 }
 #endif
 

arch/arm/cpu/armv7/mx6/ddr.c

@@ -796,7 +796,6 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	debug("Rtt_wr=%d\n", sysinfo->rtt_wr);
 	debug("Rtt_nom=%d\n", sysinfo->rtt_nom);
 	debug("SRT=%d\n", ddr3_cfg->SRT);
-	debug("tcl=%d\n", tcl);
 	debug("twr=%d\n", twr);
 
 	/*

arch/arm/dts/socfpga_cyclone5_socdk.dts

@@ -34,6 +34,10 @@
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 	};
+
+	soc {
+		u-boot,dm-pre-reloc;
+	};
 };
 
 &gmac1 {

arch/arm/dts/uniphier-common32.dtsi

@@ -0,0 +1,105 @@
+/*
+ * Device Tree Source commonly used by UniPhier ARM SoCs
+ *
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+	X11
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	soc: soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		interrupt-parent = <&intc>;
+
+		extbus: extbus {
+			compatible = "simple-bus";
+			#address-cells = <2>;
+			#size-cells = <1>;
+		};
+
+		serial0: serial@54006800 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006800 0x40>;
+			interrupts = <0 33 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart0>;
+			clocks = <&uart_clk>;
+		};
+
+		serial1: serial@54006900 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006900 0x40>;
+			interrupts = <0 35 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart1>;
+			clocks = <&uart_clk>;
+		};
+
+		serial2: serial@54006a00 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006a00 0x40>;
+			interrupts = <0 37 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart2>;
+			clocks = <&uart_clk>;
+		};
+
+		serial3: serial@54006b00 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006b00 0x40>;
+			interrupts = <0 177 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart3>;
+			clocks = <&uart_clk>;
+		};
+
+		system-bus-controller@58c00000 {
+			compatible = "socionext,uniphier-system-bus-controller";
+			reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
+		};
+
+		timer@60000200 {
+			compatible = "arm,cortex-a9-global-timer";
+			reg = <0x60000200 0x20>;
+			interrupts = <1 11 0x104>;
+			clocks = <&arm_timer_clk>;
+		};
+
+		timer@60000600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0x60000600 0x20>;
+			interrupts = <1 13 0x104>;
+			clocks = <&arm_timer_clk>;
+		};
+
+		intc: interrupt-controller@60001000 {
+			compatible = "arm,cortex-a9-gic";
+			reg = <0x60001000 0x1000>,
+			      <0x60000100 0x100>;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+		};
+
+		pinctrl: pinctrl@5f801000 {
+			/* specify compatible in each SoC DTSI */
+			reg = <0x5f801000 0xe00>;
+		};
+
+		nand: nand@68000000 {
+			compatible = "denali,denali-nand-dt";
+			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+			reg-names = "nand_data", "denali_reg";
+		};
+	};
+};
+
+/include/ "uniphier-pinctrl.dtsi"

arch/arm/dts/uniphier-ph1-ld4-ref.dts

@@ -20,8 +20,7 @@
 	};
 
 	chosen {
-		bootargs = "console=ttyS0,115200";
-		stdout-path = &serial0;
+		stdout-path = "serial0:115200n8";
 	};
 
 	aliases {

arch/arm/dts/uniphier-ph1-ld4.dtsi

@@ -6,7 +6,7 @@
  * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
-/include/ "skeleton.dtsi"
+/include/ "uniphier-common32.dtsi"
 
 / {
 	compatible = "socionext,ph1-ld4";
@@ -19,6 +19,7 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <0>;
+			next-level-cache = <&l2>;
 		};
 	};
 
@@ -41,183 +42,117 @@
 			clock-frequency = <100000000>;
 		};
 	};
+};
 
-	soc {
-		compatible = "simple-bus";
+&soc {
+	l2: l2-cache@500c0000 {
+		compatible = "socionext,uniphier-system-cache";
+		reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
+		interrupts = <0 174 4>, <0 175 4>;
+		cache-unified;
+		cache-size = <(512 * 1024)>;
+		cache-sets = <256>;
+		cache-line-size = <128>;
+		cache-level = <2>;
+	};
+
+	i2c0: i2c@58400000 {
+		compatible = "socionext,uniphier-i2c";
+		status = "disabled";
+		reg = <0x58400000 0x40>;
 		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-		interrupt-parent = <&intc>;
+		#size-cells = <0>;
+		interrupts = <0 41 1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_i2c0>;
+		clocks = <&iobus_clk>;
+		clock-frequency = <100000>;
+	};
 
-		extbus: extbus {
-			compatible = "simple-bus";
-			#address-cells = <2>;
-			#size-cells = <1>;
-		};
+	i2c1: i2c@58480000 {
+		compatible = "socionext,uniphier-i2c";
+		status = "disabled";
+		reg = <0x58480000 0x40>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <0 42 1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_i2c1>;
+		clocks = <&iobus_clk>;
+		clock-frequency = <100000>;
+	};
 
-		serial0: serial@54006800 {
-			compatible = "socionext,uniphier-uart";
-			status = "disabled";
-			reg = <0x54006800 0x40>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart0>;
-			interrupts = <0 33 4>;
-			clocks = <&uart_clk>;
-			clock-frequency = <36864000>;
-		};
+	/* chip-internal connection for DMD */
+	i2c2: i2c@58500000 {
+		compatible = "socionext,uniphier-i2c";
+		reg = <0x58500000 0x40>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <0 43 1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_i2c2>;
+		clocks = <&iobus_clk>;
+		clock-frequency = <400000>;
+	};
 
-		serial1: serial@54006900 {
-			compatible = "socionext,uniphier-uart";
-			status = "disabled";
-			reg = <0x54006900 0x40>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart1>;
-			interrupts = <0 35 4>;
-			clocks = <&uart_clk>;
-			clock-frequency = <36864000>;
-		};
+	i2c3: i2c@58580000 {
+		compatible = "socionext,uniphier-i2c";
+		status = "disabled";
+		reg = <0x58580000 0x40>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <0 44 1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_i2c3>;
+		clocks = <&iobus_clk>;
+		clock-frequency = <100000>;
+	};
 
-		serial2: serial@54006a00 {
-			compatible = "socionext,uniphier-uart";
-			status = "disabled";
-			reg = <0x54006a00 0x40>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart2>;
-			interrupts = <0 37 4>;
-			clocks = <&uart_clk>;
-			clock-frequency = <36864000>;
-		};
+	usb0: usb@5a800100 {
+		compatible = "socionext,uniphier-ehci", "generic-ehci";
+		status = "disabled";
+		reg = <0x5a800100 0x100>;
+		interrupts = <0 80 4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usb0>;
+	};
 
-		serial3: serial@54006b00 {
-			compatible = "socionext,uniphier-uart";
-			status = "disabled";
-			reg = <0x54006b00 0x40>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart3>;
-			interrupts = <0 29 4>;
-			clocks = <&uart_clk>;
-			clock-frequency = <36864000>;
-		};
+	usb1: usb@5a810100 {
+		compatible = "socionext,uniphier-ehci", "generic-ehci";
+		status = "disabled";
+		reg = <0x5a810100 0x100>;
+		interrupts = <0 81 4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usb1>;
+	};
 
-		i2c0: i2c@58400000 {
-			compatible = "socionext,uniphier-i2c";
-			status = "disabled";
-			reg = <0x58400000 0x40>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_i2c0>;
-			interrupts = <0 41 1>;
-			clocks = <&iobus_clk>;
-			clock-frequency = <100000>;
-		};
-
-		i2c1: i2c@58480000 {
-			compatible = "socionext,uniphier-i2c";
-			status = "disabled";
-			reg = <0x58480000 0x40>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_i2c1>;
-			interrupts = <0 42 1>;
-			clocks = <&iobus_clk>;
-			clock-frequency = <100000>;
-		};
-
-		/* chip-internal connection for DMD */
-		i2c2: i2c@58500000 {
-			compatible = "socionext,uniphier-i2c";
-			reg = <0x58500000 0x40>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_i2c2>;
-			interrupts = <0 43 1>;
-			clocks = <&iobus_clk>;
-			clock-frequency = <400000>;
-		};
-
-		i2c3: i2c@58580000 {
-			compatible = "socionext,uniphier-i2c";
-			status = "disabled";
-			reg = <0x58580000 0x40>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_i2c3>;
-			interrupts = <0 44 1>;
-			clocks = <&iobus_clk>;
-			clock-frequency = <100000>;
-		};
-
-		system-bus-controller-misc@59800000 {
-			compatible = "socionext,uniphier-system-bus-controller-misc",
-				     "syscon";
-			reg = <0x59800000 0x2000>;
-		};
-
-		usb0: usb@5a800100 {
-			compatible = "socionext,uniphier-ehci", "generic-ehci";
-			status = "disabled";
-			reg = <0x5a800100 0x100>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_usb0>;
-			interrupts = <0 80 4>;
-		};
-
-		usb1: usb@5a810100 {
-			compatible = "socionext,uniphier-ehci", "generic-ehci";
-			status = "disabled";
-			reg = <0x5a810100 0x100>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_usb1>;
-			interrupts = <0 81 4>;
-		};
-
-		usb2: usb@5a820100 {
-			compatible = "socionext,uniphier-ehci", "generic-ehci";
-			status = "disabled";
-			reg = <0x5a820100 0x100>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_usb2>;
-			interrupts = <0 82 4>;
-		};
-
-		pinctrl: pinctrl@5f801000 {
-			compatible = "socionext,ph1-ld4-pinctrl",
-				     "syscon";
-			reg = <0x5f801000 0xe00>;
-		};
-
-		timer@60000200 {
-			compatible = "arm,cortex-a9-global-timer";
-			reg = <0x60000200 0x20>;
-			interrupts = <1 11 0x104>;
-			clocks = <&arm_timer_clk>;
-		};
-
-		timer@60000600 {
-			compatible = "arm,cortex-a9-twd-timer";
-			reg = <0x60000600 0x20>;
-			interrupts = <1 13 0x104>;
-			clocks = <&arm_timer_clk>;
-		};
-
-		intc: interrupt-controller@60001000 {
-			compatible = "arm,cortex-a9-gic";
-			#interrupt-cells = <3>;
-			interrupt-controller;
-			reg = <0x60001000 0x1000>,
-			      <0x60000100 0x100>;
-		};
-
-		nand: nand@68000000 {
-			compatible = "denali,denali-nand-dt";
-			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
-			reg-names = "nand_data", "denali_reg";
-		};
+	usb2: usb@5a820100 {
+		compatible = "socionext,uniphier-ehci", "generic-ehci";
+		status = "disabled";
+		reg = <0x5a820100 0x100>;
+		interrupts = <0 82 4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usb2>;
 	};
 };
 
-/include/ "uniphier-pinctrl.dtsi"
+&serial0 {
+	clock-frequency = <36864000>;
+};
+
+&serial1 {
+	clock-frequency = <36864000>;
+};
+
+&serial2 {
+	clock-frequency = <36864000>;
+};
+
+&serial3 {
+	interrupts = <0 29 4>;
+	clock-frequency = <36864000>;
+};
+
+&pinctrl {
+	compatible = "socionext,ph1-ld4-pinctrl", "syscon";
+};

arch/arm/dts/uniphier-ph1-ld6b-ref.dts

@@ -20,8 +20,7 @@
 	};
 
 	chosen {
-		bootargs = "console=ttyS0,115200";
-		stdout-path = &serial0;
+		stdout-path = "serial0:115200n8";
 	};
 
 	aliases {

arch/arm/dts/uniphier-ph1-pro4-ref.dts

@@ -20,8 +20,7 @@
 	};
 
 	chosen {
-		bootargs = "console=ttyS0,115200";
-		stdout-path = &serial0;
+		stdout-path = "serial0:115200n8";
 	};
 
 	aliases {

arch/arm/dts/uniphier-ph1-pro4.dtsi

@@ -6,7 +6,7 @@
  * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
-/include/ "skeleton.dtsi"
+/include/ "uniphier-common32.dtsi"
 
 / {
 	compatible = "socionext,ph1-pro4";
@@ -20,12 +20,14 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <0>;
+			next-level-cache = <&l2>;
 		};
 
 		cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <1>;
+			next-level-cache = <&l2>;
 		};
 	};
 
@@ -48,216 +50,149 @@
 			clock-frequency = <50000000>;
 		};
 	};
+};
 
-	soc {
-		compatible = "simple-bus";
+&soc {
+	l2: l2-cache@500c0000 {
+		compatible = "socionext,uniphier-system-cache";
+		reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
+		interrupts = <0 174 4>, <0 175 4>;
+		cache-unified;
+		cache-size = <(768 * 1024)>;
+		cache-sets = <256>;
+		cache-line-size = <128>;
+		cache-level = <2>;
+	};
+
+	i2c0: i2c@58780000 {
+		compatible = "socionext,uniphier-fi2c";
+		status = "disabled";
+		reg = <0x58780000 0x80>;
 		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-		interrupt-parent = <&intc>;
+		#size-cells = <0>;
+		interrupts = <0 41 4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_i2c0>;
+		clocks = <&i2c_clk>;
+		clock-frequency = <100000>;
+	};
 
-		extbus: extbus {
-			compatible = "simple-bus";
-			#address-cells = <2>;
-			#size-cells = <1>;
-		};
+	i2c1: i2c@58781000 {
+		compatible = "socionext,uniphier-fi2c";
+		status = "disabled";
+		reg = <0x58781000 0x80>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <0 42 4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_i2c1>;
+		clocks = <&i2c_clk>;
+		clock-frequency = <100000>;
+	};
 
-		serial0: serial@54006800 {
-			compatible = "socionext,uniphier-uart";
-			status = "disabled";
-			reg = <0x54006800 0x40>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart0>;
-			interrupts = <0 33 4>;
-			clocks = <&uart_clk>;
-			clock-frequency = <73728000>;
-		};
+	i2c2: i2c@58782000 {
+		compatible = "socionext,uniphier-fi2c";
+		status = "disabled";
+		reg = <0x58782000 0x80>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <0 43 4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_i2c2>;
+		clocks = <&i2c_clk>;
+		clock-frequency = <100000>;
+	};
 
-		serial1: serial@54006900 {
-			compatible = "socionext,uniphier-uart";
-			status = "disabled";
-			reg = <0x54006900 0x40>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart1>;
-			interrupts = <0 35 4>;
-			clocks = <&uart_clk>;
-			clock-frequency = <73728000>;
-		};
+	i2c3: i2c@58783000 {
+		compatible = "socionext,uniphier-fi2c";
+		status = "disabled";
+		reg = <0x58783000 0x80>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <0 44 4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_i2c3>;
+		clocks = <&i2c_clk>;
+		clock-frequency = <100000>;
+	};
 
-		serial2: serial@54006a00 {
-			compatible = "socionext,uniphier-uart";
-			status = "disabled";
-			reg = <0x54006a00 0x40>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart2>;
-			interrupts = <0 37 4>;
-			clocks = <&uart_clk>;
-			clock-frequency = <73728000>;
-		};
+	/* i2c4 does not exist */
 
-		serial3: serial@54006b00 {
-			compatible = "socionext,uniphier-uart";
-			status = "disabled";
-			reg = <0x54006b00 0x40>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart3>;
-			interrupts = <0 29 4>;
-			clocks = <&uart_clk>;
-			clock-frequency = <73728000>;
-		};
+	/* chip-internal connection for DMD */
+	i2c5: i2c@58785000 {
+		compatible = "socionext,uniphier-fi2c";
+		reg = <0x58785000 0x80>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <0 25 4>;
+		clocks = <&i2c_clk>;
+		clock-frequency = <400000>;
+	};
 
-		i2c0: i2c@58780000 {
-			compatible = "socionext,uniphier-fi2c";
-			status = "disabled";
-			reg = <0x58780000 0x80>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_i2c0>;
-			interrupts = <0 41 4>;
-			clocks = <&i2c_clk>;
-			clock-frequency = <100000>;
-		};
+	/* chip-internal connection for HDMI */
+	i2c6: i2c@58786000 {
+		compatible = "socionext,uniphier-fi2c";
+		reg = <0x58786000 0x80>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <0 26 4>;
+		clocks = <&i2c_clk>;
+		clock-frequency = <400000>;
+	};
 
-		i2c1: i2c@58781000 {
-			compatible = "socionext,uniphier-fi2c";
-			status = "disabled";
-			reg = <0x58781000 0x80>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_i2c1>;
-			interrupts = <0 42 4>;
-			clocks = <&i2c_clk>;
-			clock-frequency = <100000>;
-		};
+	usb2: usb@5a800100 {
+		compatible = "socionext,uniphier-ehci", "generic-ehci";
+		status = "disabled";
+		reg = <0x5a800100 0x100>;
+		interrupts = <0 80 4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usb2>;
+	};
 
-		i2c2: i2c@58782000 {
-			compatible = "socionext,uniphier-fi2c";
-			status = "disabled";
-			reg = <0x58782000 0x80>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_i2c2>;
-			interrupts = <0 43 4>;
-			clocks = <&i2c_clk>;
-			clock-frequency = <100000>;
-		};
+	usb3: usb@5a810100 {
+		compatible = "socionext,uniphier-ehci", "generic-ehci";
+		status = "disabled";
+		reg = <0x5a810100 0x100>;
+		interrupts = <0 81 4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usb3>;
+	};
 
-		i2c3: i2c@58783000 {
-			compatible = "socionext,uniphier-fi2c";
-			status = "disabled";
-			reg = <0x58783000 0x80>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_i2c3>;
-			interrupts = <0 44 4>;
-			clocks = <&i2c_clk>;
-			clock-frequency = <100000>;
-		};
+	usb0: usb@65a00000 {
+		compatible = "socionext,uniphier-xhci", "generic-xhci";
+		status = "disabled";
+		reg = <0x65a00000 0x100>;
+		interrupts = <0 134 4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usb0>;
+	};
 
-		/* i2c4 does not exist */
-
-		/* chip-internal connection for DMD */
-		i2c5: i2c@58785000 {
-			compatible = "socionext,uniphier-fi2c";
-			reg = <0x58785000 0x80>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <0 25 4>;
-			clocks = <&i2c_clk>;
-			clock-frequency = <400000>;
-		};
-
-		/* chip-internal connection for HDMI */
-		i2c6: i2c@58786000 {
-			compatible = "socionext,uniphier-fi2c";
-			reg = <0x58786000 0x80>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <0 26 4>;
-			clocks = <&i2c_clk>;
-			clock-frequency = <400000>;
-		};
-
-		system-bus-controller-misc@59800000 {
-			compatible = "socionext,uniphier-system-bus-controller-misc",
-				     "syscon";
-			reg = <0x59800000 0x2000>;
-		};
-
-		usb2: usb@5a800100 {
-			compatible = "socionext,uniphier-ehci", "generic-ehci";
-			status = "disabled";
-			reg = <0x5a800100 0x100>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_usb2>;
-			interrupts = <0 80 4>;
-		};
-
-		usb3: usb@5a810100 {
-			compatible = "socionext,uniphier-ehci", "generic-ehci";
-			status = "disabled";
-			reg = <0x5a810100 0x100>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_usb3>;
-			interrupts = <0 81 4>;
-		};
-
-		usb0: usb@65a00000 {
-			compatible = "socionext,uniphier-xhci", "generic-xhci";
-			status = "disabled";
-			reg = <0x65a00000 0x100>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_usb0>;
-			interrupts = <0 134 4>;
-		};
-
-		usb1: usb@65c00000 {
-			compatible = "socionext,uniphier-xhci", "generic-xhci";
-			status = "disabled";
-			reg = <0x65c00000 0x100>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_usb1>;
-			interrupts = <0 137 4>;
-		};
-
-		pinctrl: pinctrl@5f801000 {
-			compatible = "socionext,ph1-pro4-pinctrl",
-				     "syscon";
-			reg = <0x5f801000 0xe00>;
-		};
-
-		timer@60000200 {
-			compatible = "arm,cortex-a9-global-timer";
-			reg = <0x60000200 0x20>;
-			interrupts = <1 11 0x304>;
-			clocks = <&arm_timer_clk>;
-		};
-
-		timer@60000600 {
-			compatible = "arm,cortex-a9-twd-timer";
-			reg = <0x60000600 0x20>;
-			interrupts = <1 13 0x304>;
-			clocks = <&arm_timer_clk>;
-		};
-
-		intc: interrupt-controller@60001000 {
-			compatible = "arm,cortex-a9-gic";
-			#interrupt-cells = <3>;
-			interrupt-controller;
-			reg = <0x60001000 0x1000>,
-			      <0x60000100 0x100>;
-		};
-
-		nand: nand@68000000 {
-			compatible = "denali,denali-nand-dt";
-			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
-			reg-names = "nand_data", "denali_reg";
-		};
+	usb1: usb@65c00000 {
+		compatible = "socionext,uniphier-xhci", "generic-xhci";
+		status = "disabled";
+		reg = <0x65c00000 0x100>;
+		interrupts = <0 137 4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usb1>;
 	};
 };
 
-/include/ "uniphier-pinctrl.dtsi"
+&serial0 {
+	clock-frequency = <73728000>;
+};
+
+&serial1 {
+	clock-frequency = <73728000>;
+};
+
+&serial2 {
+	clock-frequency = <73728000>;
+};
+
+&serial3 {
+	clock-frequency = <73728000>;
+};
+
+&pinctrl {
+	compatible = "socionext,ph1-pro4-pinctrl", "syscon";
+};

arch/arm/dts/uniphier-ph1-pro5-4kbox.dts

@@ -19,8 +19,7 @@
 	};
 
 	chosen {
-		bootargs = "console=ttyS1,115200";
-		stdout-path = &serial1;
+		stdout-path = "serial1:115200n8";
 	};
 
 	aliases {

arch/arm/dts/uniphier-ph1-pro5.dtsi

@@ -6,7 +6,7 @@
  * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
-/include/ "skeleton.dtsi"
+/include/ "uniphier-common32.dtsi"
 
 / {
 	compatible = "socionext,ph1-pro5";
@@ -20,12 +20,14 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <0>;
+			next-level-cache = <&l2>;
 		};
 
 		cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <1>;
+			next-level-cache = <&l2>;
 		};
 	};
 
@@ -48,187 +50,143 @@
 			clock-frequency = <50000000>;
 		};
 	};
+};
 
-	soc {
-		compatible = "simple-bus";
+&soc {
+	l2: l2-cache@500c0000 {
+		compatible = "socionext,uniphier-system-cache";
+		reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
+		interrupts = <0 190 4>, <0 191 4>;
+		cache-unified;
+		cache-size = <(2 * 1024 * 1024)>;
+		cache-sets = <512>;
+		cache-line-size = <128>;
+		cache-level = <2>;
+		next-level-cache = <&l3>;
+	};
+
+	l3: l3-cache@500c8000 {
+		compatible = "socionext,uniphier-system-cache";
+		reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
+		interrupts = <0 174 4>, <0 175 4>;
+		cache-unified;
+		cache-size = <(2 * 1024 * 1024)>;
+		cache-sets = <512>;
+		cache-line-size = <256>;
+		cache-level = <3>;
+	};
+
+	i2c0: i2c@58780000 {
+		compatible = "socionext,uniphier-fi2c";
+		status = "disabled";
+		reg = <0x58780000 0x80>;
 		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-		interrupt-parent = <&intc>;
+		#size-cells = <0>;
+		interrupts = <0 41 4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_i2c0>;
+		clocks = <&i2c_clk>;
+		clock-frequency = <100000>;
+	};
 
-		extbus: extbus {
-			compatible = "simple-bus";
-			#address-cells = <2>;
-			#size-cells = <1>;
-		};
+	i2c1: i2c@58781000 {
+		compatible = "socionext,uniphier-fi2c";
+		status = "disabled";
+		reg = <0x58781000 0x80>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <0 42 4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_i2c1>;
+		clocks = <&i2c_clk>;
+		clock-frequency = <100000>;
+	};
 
-		serial0: serial@54006800 {
-			compatible = "socionext,uniphier-uart";
-			status = "disabled";
-			reg = <0x54006800 0x40>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart0>;
-			interrupts = <0 33 4>;
-			clocks = <&uart_clk>;
-		};
+	i2c2: i2c@58782000 {
+		compatible = "socionext,uniphier-fi2c";
+		status = "disabled";
+		reg = <0x58782000 0x80>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <0 43 4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_i2c2>;
+		clocks = <&i2c_clk>;
+		clock-frequency = <100000>;
+	};
 
-		serial1: serial@54006900 {
-			compatible = "socionext,uniphier-uart";
-			status = "disabled";
-			reg = <0x54006900 0x40>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart1>;
-			interrupts = <0 35 4>;
-			clocks = <&uart_clk>;
-		};
+	i2c3: i2c@58783000 {
+		compatible = "socionext,uniphier-fi2c";
+		status = "disabled";
+		reg = <0x58783000 0x80>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <0 44 4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_i2c3>;
+		clocks = <&i2c_clk>;
+		clock-frequency = <100000>;
+	};
 
-		serial2: serial@54006a00 {
-			compatible = "socionext,uniphier-uart";
-			status = "disabled";
-			reg = <0x54006a00 0x40>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart2>;
-			interrupts = <0 37 4>;
-			clocks = <&uart_clk>;
-		};
+	/* i2c4 does not exist */
 
-		serial3: serial@54006b00 {
-			compatible = "socionext,uniphier-uart";
-			status = "disabled";
-			reg = <0x54006b00 0x40>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart3>;
-			interrupts = <0 177 4>;
-			clocks = <&uart_clk>;
-		};
+	/* chip-internal connection for DMD */
+	i2c5: i2c@58785000 {
+		compatible = "socionext,uniphier-fi2c";
+		reg = <0x58785000 0x80>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <0 25 4>;
+		clocks = <&i2c_clk>;
+		clock-frequency = <400000>;
+	};
 
-		i2c0: i2c@58780000 {
-			compatible = "socionext,uniphier-fi2c";
-			status = "disabled";
-			reg = <0x58780000 0x80>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_i2c0>;
-			interrupts = <0 41 4>;
-			clocks = <&i2c_clk>;
-			clock-frequency = <100000>;
-		};
+	/* chip-internal connection for HDMI */
+	i2c6: i2c@58786000 {
+		compatible = "socionext,uniphier-fi2c";
+		reg = <0x58786000 0x80>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <0 26 4>;
+		clocks = <&i2c_clk>;
+		clock-frequency = <400000>;
+	};
 
-		i2c1: i2c@58781000 {
-			compatible = "socionext,uniphier-fi2c";
-			status = "disabled";
-			reg = <0x58781000 0x80>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_i2c1>;
-			interrupts = <0 42 4>;
-			clocks = <&i2c_clk>;
-			clock-frequency = <100000>;
-		};
+	usb0: usb@65a00000 {
+		compatible = "socionext,uniphier-xhci", "generic-xhci";
+		status = "disabled";
+		reg = <0x65a00000 0x100>;
+		interrupts = <0 134 4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usb0>;
+	};
 
-		i2c2: i2c@58782000 {
-			compatible = "socionext,uniphier-fi2c";
-			status = "disabled";
-			reg = <0x58782000 0x80>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_i2c2>;
-			interrupts = <0 43 4>;
-			clocks = <&i2c_clk>;
-			clock-frequency = <100000>;
-		};
-
-		i2c3: i2c@58783000 {
-			compatible = "socionext,uniphier-fi2c";
-			status = "disabled";
-			reg = <0x58783000 0x80>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_i2c3>;
-			interrupts = <0 44 4>;
-			clocks = <&i2c_clk>;
-			clock-frequency = <100000>;
-		};
-
-		/* i2c4 does not exist */
-
-		/* chip-internal connection for DMD */
-		i2c5: i2c@58785000 {
-			compatible = "socionext,uniphier-fi2c";
-			reg = <0x58785000 0x80>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <0 25 4>;
-			clocks = <&i2c_clk>;
-			clock-frequency = <400000>;
-		};
-
-		/* chip-internal connection for HDMI */
-		i2c6: i2c@58786000 {
-			compatible = "socionext,uniphier-fi2c";
-			reg = <0x58786000 0x80>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <0 26 4>;
-			clocks = <&i2c_clk>;
-			clock-frequency = <400000>;
-		};
-
-		system-bus-controller-misc@59800000 {
-			compatible = "socionext,uniphier-system-bus-controller-misc",
-				     "syscon";
-			reg = <0x59800000 0x2000>;
-		};
-
-		pinctrl: pinctrl@5f801000 {
-			compatible = "socionext,ph1-pro5-pinctrl", "syscon";
-			reg = <0x5f801000 0xe00>;
-		};
-
-		timer@60000200 {
-			compatible = "arm,cortex-a9-global-timer";
-			reg = <0x60000200 0x20>;
-			interrupts = <1 11 0x304>;
-			clocks = <&arm_timer_clk>;
-		};
-
-		timer@60000600 {
-			compatible = "arm,cortex-a9-twd-timer";
-			reg = <0x60000600 0x20>;
-			interrupts = <1 13 0x304>;
-			clocks = <&arm_timer_clk>;
-		};
-
-		intc: interrupt-controller@60001000 {
-			compatible = "arm,cortex-a9-gic";
-			#interrupt-cells = <3>;
-			interrupt-controller;
-			reg = <0x60001000 0x1000>,
-			      <0x60000100 0x100>;
-		};
-
-		usb0: usb@65a00000 {
-			compatible = "socionext,uniphier-xhci", "generic-xhci";
-			status = "disabled";
-			reg = <0x65a00000 0x100>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_usb0>;
-			interrupts = <0 134 4>;
-		};
-
-		usb1: usb@65c00000 {
-			compatible = "socionext,uniphier-xhci", "generic-xhci";
-			status = "disabled";
-			reg = <0x65c00000 0x100>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
-			interrupts = <0 137 4>;
-		};
+	usb1: usb@65c00000 {
+		compatible = "socionext,uniphier-xhci", "generic-xhci";
+		status = "disabled";
+		reg = <0x65c00000 0x100>;
+		interrupts = <0 137 4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
 	};
 };
 
-/include/ "uniphier-pinctrl.dtsi"
+&serial0 {
+	clock-frequency = <73728000>;
+};
+
+&serial1 {
+	clock-frequency = <73728000>;
+};
+
+&serial2 {
+	clock-frequency = <73728000>;
+};
+
+&serial3 {
+	clock-frequency = <73728000>;
+};
+
+&pinctrl {
+	compatible = "socionext,ph1-pro5-pinctrl", "syscon";
+};

arch/arm/dts/uniphier-ph1-sld3-ref.dts

@@ -21,8 +21,7 @@
 	};
 
 	chosen {
-		bootargs = "console=ttyS0,115200";
-		stdout-path = &serial0;
+		stdout-path = "serial0:115200n8";
 	};
 
 	aliases {

arch/arm/dts/uniphier-ph1-sld8-ref.dts

@@ -20,8 +20,7 @@
 	};
 
 	chosen {
-		bootargs = "console=ttyS0,115200";
-		stdout-path = &serial0;
+		stdout-path = "serial0:115200n8";
 	};
 
 	aliases {

arch/arm/dts/uniphier-ph1-sld8.dtsi

@@ -6,7 +6,7 @@
  * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
-/include/ "skeleton.dtsi"
+/include/ "uniphier-common32.dtsi"
 
 / {
 	compatible = "socionext,ph1-sld8";
@@ -19,6 +19,7 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <0>;
+			next-level-cache = <&l2>;
 		};
 	};
 
@@ -41,183 +42,117 @@
 			clock-frequency = <100000000>;
 		};
 	};
+};
 
-	soc {
-		compatible = "simple-bus";
+&soc {
+	l2: l2-cache@500c0000 {
+		compatible = "socionext,uniphier-system-cache";
+		reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
+		interrupts = <0 174 4>, <0 175 4>;
+		cache-unified;
+		cache-size = <(256 * 1024)>;
+		cache-sets = <256>;
+		cache-line-size = <128>;
+		cache-level = <2>;
+	};
+
+	i2c0: i2c@58400000 {
+		compatible = "socionext,uniphier-i2c";
+		status = "disabled";
+		reg = <0x58400000 0x40>;
 		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-		interrupt-parent = <&intc>;
+		#size-cells = <0>;
+		interrupts = <0 41 1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_i2c0>;
+		clocks = <&iobus_clk>;
+		clock-frequency = <100000>;
+	};
 
-		extbus: extbus {
-			compatible = "simple-bus";
-			#address-cells = <2>;
-			#size-cells = <1>;
-		};
+	i2c1: i2c@58480000 {
+		compatible = "socionext,uniphier-i2c";
+		status = "disabled";
+		reg = <0x58480000 0x40>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <0 42 1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_i2c1>;
+		clocks = <&iobus_clk>;
+		clock-frequency = <100000>;
+	};
 
-		serial0: serial@54006800 {
-			compatible = "socionext,uniphier-uart";
-			status = "disabled";
-			reg = <0x54006800 0x40>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart0>;
-			interrupts = <0 33 4>;
-			clocks = <&uart_clk>;
-			clock-frequency = <80000000>;
-		};
+	/* chip-internal connection for DMD */
+	i2c2: i2c@58500000 {
+		compatible = "socionext,uniphier-i2c";
+		reg = <0x58500000 0x40>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <0 43 1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_i2c2>;
+		clocks = <&iobus_clk>;
+		clock-frequency = <400000>;
+	};
 
-		serial1: serial@54006900 {
-			compatible = "socionext,uniphier-uart";
-			status = "disabled";
-			reg = <0x54006900 0x40>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart1>;
-			interrupts = <0 35 4>;
-			clocks = <&uart_clk>;
-			clock-frequency = <80000000>;
-		};
+	i2c3: i2c@58580000 {
+		compatible = "socionext,uniphier-i2c";
+		status = "disabled";
+		reg = <0x58580000 0x40>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <0 44 1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_i2c3>;
+		clocks = <&iobus_clk>;
+		clock-frequency = <100000>;
+	};
 
-		serial2: serial@54006a00 {
-			compatible = "socionext,uniphier-uart";
-			status = "disabled";
-			reg = <0x54006a00 0x40>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart2>;
-			interrupts = <0 37 4>;
-			clocks = <&uart_clk>;
-			clock-frequency = <80000000>;
-		};
+	usb0: usb@5a800100 {
+		compatible = "socionext,uniphier-ehci", "generic-ehci";
+		status = "disabled";
+		reg = <0x5a800100 0x100>;
+		interrupts = <0 80 4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usb0>;
+	};
 
-		serial3: serial@54006b00 {
-			compatible = "socionext,uniphier-uart";
-			status = "disabled";
-			reg = <0x54006b00 0x40>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart3>;
-			interrupts = <0 29 4>;
-			clocks = <&uart_clk>;
-			clock-frequency = <80000000>;
-		};
+	usb1: usb@5a810100 {
+		compatible = "socionext,uniphier-ehci", "generic-ehci";
+		status = "disabled";
+		reg = <0x5a810100 0x100>;
+		interrupts = <0 81 4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usb1>;
+	};
 
-		i2c0: i2c@58400000 {
-			compatible = "socionext,uniphier-i2c";
-			status = "disabled";
-			reg = <0x58400000 0x40>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_i2c0>;
-			interrupts = <0 41 1>;
-			clocks = <&iobus_clk>;
-			clock-frequency = <100000>;
-		};
-
-		i2c1: i2c@58480000 {
-			compatible = "socionext,uniphier-i2c";
-			status = "disabled";
-			reg = <0x58480000 0x40>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_i2c1>;
-			interrupts = <0 42 1>;
-			clocks = <&iobus_clk>;
-			clock-frequency = <100000>;
-		};
-
-		/* chip-internal connection for DMD */
-		i2c2: i2c@58500000 {
-			compatible = "socionext,uniphier-i2c";
-			reg = <0x58500000 0x40>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_i2c2>;
-			interrupts = <0 43 1>;
-			clocks = <&iobus_clk>;
-			clock-frequency = <400000>;
-		};
-
-		i2c3: i2c@58580000 {
-			compatible = "socionext,uniphier-i2c";
-			status = "disabled";
-			reg = <0x58580000 0x40>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_i2c3>;
-			interrupts = <0 44 1>;
-			clocks = <&iobus_clk>;
-			clock-frequency = <100000>;
-		};
-
-		system-bus-controller-misc@59800000 {
-			compatible = "socionext,uniphier-system-bus-controller-misc",
-				     "syscon";
-			reg = <0x59800000 0x2000>;
-		};
-
-		usb0: usb@5a800100 {
-			compatible = "socionext,uniphier-ehci", "generic-ehci";
-			status = "disabled";
-			reg = <0x5a800100 0x100>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_usb0>;
-			interrupts = <0 80 4>;
-		};
-
-		usb1: usb@5a810100 {
-			compatible = "socionext,uniphier-ehci", "generic-ehci";
-			status = "disabled";
-			reg = <0x5a810100 0x100>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_usb1>;
-			interrupts = <0 81 4>;
-		};
-
-		usb2: usb@5a820100 {
-			compatible = "socionext,uniphier-ehci", "generic-ehci";
-			status = "disabled";
-			reg = <0x5a820100 0x100>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_usb2>;
-			interrupts = <0 82 4>;
-		};
-
-		pinctrl: pinctrl@5f801000 {
-			compatible = "socionext,ph1-sld8-pinctrl",
-				     "syscon";
-			reg = <0x5f801000 0xe00>;
-		};
-
-		timer@60000200 {
-			compatible = "arm,cortex-a9-global-timer";
-			reg = <0x60000200 0x20>;
-			interrupts = <1 11 0x104>;
-			clocks = <&arm_timer_clk>;
-		};
-
-		timer@60000600 {
-			compatible = "arm,cortex-a9-twd-timer";
-			reg = <0x60000600 0x20>;
-			interrupts = <1 13 0x104>;
-			clocks = <&arm_timer_clk>;
-		};
-
-		intc: interrupt-controller@60001000 {
-			compatible = "arm,cortex-a9-gic";
-			#interrupt-cells = <3>;
-			interrupt-controller;
-			reg = <0x60001000 0x1000>,
-			      <0x60000100 0x100>;
-		};
-
-		nand: nand@68000000 {
-			compatible = "denali,denali-nand-dt";
-			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
-			reg-names = "nand_data", "denali_reg";
-		};
+	usb2: usb@5a820100 {
+		compatible = "socionext,uniphier-ehci", "generic-ehci";
+		status = "disabled";
+		reg = <0x5a820100 0x100>;
+		interrupts = <0 82 4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usb2>;
 	};
 };
 
-/include/ "uniphier-pinctrl.dtsi"
+&serial0 {
+	clock-frequency = <80000000>;
+};
+
+&serial1 {
+	clock-frequency = <80000000>;
+};
+
+&serial2 {
+	clock-frequency = <80000000>;
+};
+
+&serial3 {
+	interrupts = <0 29 4>;
+	clock-frequency = <80000000>;
+};
+
+&pinctrl {
+	compatible = "socionext,ph1-sld8-pinctrl", "syscon";
+};

arch/arm/dts/uniphier-pinctrl.dtsi

@@ -7,6 +7,11 @@
  */
 
 &pinctrl {
+	pinctrl_emmc: emmc_grp {
+		groups = "emmc", "emmc_dat8";
+		function = "emmc";
+	};
+
 	pinctrl_i2c0: i2c0_grp {
 		groups = "i2c0";
 		function = "i2c0";
@@ -27,6 +32,16 @@
 		function = "i2c3";
 	};
 
+	pinctrl_sd: sd_grp {
+		groups = "sd";
+		function = "sd";
+	};
+
+	pinctrl_sd1: sd1_grp {
+		groups = "sd1";
+		function = "sd1";
+	};
+
 	pinctrl_uart0: uart0_grp {
 		groups = "uart0";
 		function = "uart0";

arch/arm/dts/uniphier-proxstream2-gentil.dts

@@ -19,8 +19,7 @@
 	};
 
 	chosen {
-		bootargs = "console=ttyS2,115200";
-		stdout-path = &serial2;
+		stdout-path = "serial2:115200n8";
 	};
 
 	aliases {

arch/arm/dts/uniphier-proxstream2-vodka.dts

@@ -19,8 +19,7 @@
 	};
 
 	chosen {
-		bootargs = "console=ttyS2,115200";
-		stdout-path = &serial2;
+		stdout-path = "serial2:115200n8";
 	};
 
 	aliases {

arch/arm/dts/uniphier-proxstream2.dtsi

@@ -6,7 +6,7 @@
  * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
-/include/ "skeleton.dtsi"
+/include/ "uniphier-common32.dtsi"
 
 / {
 	compatible = "socionext,proxstream2";
@@ -20,24 +20,28 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <0>;
+			next-level-cache = <&l2>;
 		};
 
 		cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <1>;
+			next-level-cache = <&l2>;
 		};
 
 		cpu@2 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <2>;
+			next-level-cache = <&l2>;
 		};
 
 		cpu@3 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <3>;
+			next-level-cache = <&l2>;
 		};
 	};
 
@@ -60,200 +64,140 @@
 			clock-frequency = <50000000>;
 		};
 	};
+};
 
-	soc {
-		compatible = "simple-bus";
+&soc {
+	l2: l2-cache@500c0000 {
+		compatible = "socionext,uniphier-system-cache";
+		reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
+		interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
+		cache-unified;
+		cache-size = <(1280 * 1024)>;
+		cache-sets = <512>;
+		cache-line-size = <128>;
+		cache-level = <2>;
+	};
+
+	i2c0: i2c@58780000 {
+		compatible = "socionext,uniphier-fi2c";
+		status = "disabled";
+		reg = <0x58780000 0x80>;
 		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-		interrupt-parent = <&intc>;
+		#size-cells = <0>;
+		interrupts = <0 41 4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_i2c0>;
+		clocks = <&i2c_clk>;
+		clock-frequency = <100000>;
+	};
 
-		extbus: extbus {
-			compatible = "simple-bus";
-			#address-cells = <2>;
-			#size-cells = <1>;
-		};
+	i2c1: i2c@58781000 {
+		compatible = "socionext,uniphier-fi2c";
+		status = "disabled";
+		reg = <0x58781000 0x80>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <0 42 4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_i2c1>;
+		clocks = <&i2c_clk>;
+		clock-frequency = <100000>;
+	};
 
-		serial0: serial@54006800 {
-			compatible = "socionext,uniphier-uart";
-			status = "disabled";
-			reg = <0x54006800 0x40>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart0>;
-			interrupts = <0 33 4>;
-			clocks = <&uart_clk>;
-			clock-frequency = <88900000>;
-		};
+	i2c2: i2c@58782000 {
+		compatible = "socionext,uniphier-fi2c";
+		status = "disabled";
+		reg = <0x58782000 0x80>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_i2c2>;
+		interrupts = <0 43 4>;
+		clocks = <&i2c_clk>;
+		clock-frequency = <100000>;
+	};
 
-		serial1: serial@54006900 {
-			compatible = "socionext,uniphier-uart";
-			status = "disabled";
-			reg = <0x54006900 0x40>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart1>;
-			interrupts = <0 35 4>;
-			clocks = <&uart_clk>;
-			clock-frequency = <88900000>;
-		};
+	i2c3: i2c@58783000 {
+		compatible = "socionext,uniphier-fi2c";
+		status = "disabled";
+		reg = <0x58783000 0x80>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <0 44 4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_i2c3>;
+		clocks = <&i2c_clk>;
+		clock-frequency = <100000>;
+	};
 
-		serial2: serial@54006a00 {
-			compatible = "socionext,uniphier-uart";
-			status = "disabled";
-			reg = <0x54006a00 0x40>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart2>;
-			interrupts = <0 37 4>;
-			clocks = <&uart_clk>;
-			clock-frequency = <88900000>;
-		};
+	/* chip-internal connection for DMD */
+	i2c4: i2c@58784000 {
+		compatible = "socionext,uniphier-fi2c";
+		reg = <0x58784000 0x80>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <0 45 4>;
+		clocks = <&i2c_clk>;
+		clock-frequency = <400000>;
+	};
 
-		serial3: serial@54006b00 {
-			compatible = "socionext,uniphier-uart";
-			status = "disabled";
-			reg = <0x54006b00 0x40>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart3>;
-			interrupts = <0 177 4>;
-			clocks = <&uart_clk>;
-			clock-frequency = <88900000>;
-		};
+	/* chip-internal connection for STM */
+	i2c5: i2c@58785000 {
+		compatible = "socionext,uniphier-fi2c";
+		reg = <0x58785000 0x80>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <0 25 4>;
+		clocks = <&i2c_clk>;
+		clock-frequency = <400000>;
+	};
 
-		i2c0: i2c@58780000 {
-			compatible = "socionext,uniphier-fi2c";
-			status = "disabled";
-			reg = <0x58780000 0x80>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_i2c0>;
-			interrupts = <0 41 4>;
-			clocks = <&i2c_clk>;
-			clock-frequency = <100000>;
-		};
+	/* chip-internal connection for HDMI */
+	i2c6: i2c@58786000 {
+		compatible = "socionext,uniphier-fi2c";
+		reg = <0x58786000 0x80>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <0 26 4>;
+		clocks = <&i2c_clk>;
+		clock-frequency = <400000>;
+	};
 
-		i2c1: i2c@58781000 {
-			compatible = "socionext,uniphier-fi2c";
-			status = "disabled";
-			reg = <0x58781000 0x80>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_i2c1>;
-			interrupts = <0 42 4>;
-			clocks = <&i2c_clk>;
-			clock-frequency = <100000>;
-		};
+	usb0: usb@65a00000 {
+		compatible = "socionext,uniphier-xhci", "generic-xhci";
+		status = "disabled";
+		reg = <0x65a00000 0x100>;
+		interrupts = <0 134 4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
+	};
 
-		i2c2: i2c@58782000 {
-			compatible = "socionext,uniphier-fi2c";
-			status = "disabled";
-			reg = <0x58782000 0x80>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_i2c2>;
-			interrupts = <0 43 4>;
-			clocks = <&i2c_clk>;
-			clock-frequency = <100000>;
-		};
-
-		i2c3: i2c@58783000 {
-			compatible = "socionext,uniphier-fi2c";
-			status = "disabled";
-			reg = <0x58783000 0x80>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_i2c3>;
-			interrupts = <0 44 4>;
-			clocks = <&i2c_clk>;
-			clock-frequency = <100000>;
-		};
-
-		/* chip-internal connection for DMD */
-		i2c4: i2c@58784000 {
-			compatible = "socionext,uniphier-fi2c";
-			reg = <0x58784000 0x80>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <0 45 4>;
-			clocks = <&i2c_clk>;
-			clock-frequency = <400000>;
-		};
-
-		/* chip-internal connection for STM */
-		i2c5: i2c@58785000 {
-			compatible = "socionext,uniphier-fi2c";
-			reg = <0x58785000 0x80>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <0 25 4>;
-			clocks = <&i2c_clk>;
-			clock-frequency = <400000>;
-		};
-
-		/* chip-internal connection for HDMI */
-		i2c6: i2c@58786000 {
-			compatible = "socionext,uniphier-fi2c";
-			reg = <0x58786000 0x80>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <0 26 4>;
-			clocks = <&i2c_clk>;
-			clock-frequency = <400000>;
-		};
-
-		system-bus-controller-misc@59800000 {
-			compatible = "socionext,uniphier-system-bus-controller-misc",
-				     "syscon";
-			reg = <0x59800000 0x2000>;
-		};
-
-		pinctrl: pinctrl@5f801000 {
-			compatible = "socionext,proxstream2-pinctrl", "syscon";
-			reg = <0x5f801000 0xe00>;
-		};
-
-		timer@60000200 {
-			compatible = "arm,cortex-a9-global-timer";
-			reg = <0x60000200 0x20>;
-			interrupts = <1 11 0xf04>;
-			clocks = <&arm_timer_clk>;
-		};
-
-		timer@60000600 {
-			compatible = "arm,cortex-a9-twd-timer";
-			reg = <0x60000600 0x20>;
-			interrupts = <1 13 0xf04>;
-			clocks = <&arm_timer_clk>;
-		};
-
-		intc: interrupt-controller@60001000 {
-			compatible = "arm,cortex-a9-gic";
-			#interrupt-cells = <3>;
-			interrupt-controller;
-			reg = <0x60001000 0x1000>,
-			      <0x60000100 0x100>;
-		};
-
-		usb0: usb@65a00000 {
-			compatible = "socionext,uniphier-xhci", "generic-xhci";
-			status = "disabled";
-			reg = <0x65a00000 0x100>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
-			interrupts = <0 134 4>;
-		};
-
-		usb1: usb@65c00000 {
-			compatible = "socionext,uniphier-xhci", "generic-xhci";
-			status = "disabled";
-			reg = <0x65c00000 0x100>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
-			interrupts = <0 137 4>;
-		};
+	usb1: usb@65c00000 {
+		compatible = "socionext,uniphier-xhci", "generic-xhci";
+		status = "disabled";
+		reg = <0x65c00000 0x100>;
+		interrupts = <0 137 4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
 	};
 };
 
-/include/ "uniphier-pinctrl.dtsi"
+&serial0 {
+	clock-frequency = <88900000>;
+};
+
+&serial1 {
+	clock-frequency = <88900000>;
+};
+
+&serial2 {
+	clock-frequency = <88900000>;
+};
+
+&serial3 {
+	clock-frequency = <88900000>;
+};
+
+&pinctrl {
+	compatible = "socionext,proxstream2-pinctrl", "syscon";
+};

arch/arm/imx-common/spl.c

@@ -20,7 +20,15 @@ u32 spl_boot_device(void)
 	struct src *psrc = (struct src *)SRC_BASE_ADDR;
 	unsigned int gpr10_boot = readl(&psrc->gpr10) & (1 << 28);
 	unsigned reg = gpr10_boot ? readl(&psrc->gpr9) : readl(&psrc->sbmr1);
+	unsigned int bmode = readl(&psrc->sbmr2);
 
+	/*
+	 * Check for BMODE if serial downloader is enabled
+	 * BOOT_MODE - see IMX6DQRM Table 8-1
+	 */
+	if ((((bmode >> 24) & 0x03)  == 0x01) || /* Serial Downloader */
+		(gpr10_boot && (reg == 1)))
+		return BOOT_DEVICE_UART;
 	/* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */
 	switch ((reg & 0x000000FF) >> 4) {
 	 /* EIM: See 8.5.1, Table 8-9 */

arch/arm/include/asm/arch-mx6/imx-regs.h

@@ -335,10 +335,10 @@
 #include <asm/types.h>
 
 /* only for i.MX6SX/UL */
-#define WDOG3_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL) ?	\
-			 MX6UL_WDOG3_BASE_ADDR :  MX6SX_WDOG3_BASE_ADDR)
-#define LCDIF1_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL)) ?	\
-			  MX6UL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR
+#define WDOG3_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL) ?	\
+			 MX6UL_WDOG3_BASE_ADDR :  MX6SX_WDOG3_BASE_ADDR))
+#define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL)) ?	\
+			  MX6UL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)
 
 
 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);

arch/arm/include/asm/arch-mxs/sys_proto.h

@@ -25,6 +25,8 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int));
 void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
 			 const iomux_cfg_t *iomux_setup,
 			 const unsigned int iomux_size);
+
+void mxs_power_switch_dcdc_clocksource(uint32_t freqsel);
 #endif
 
 struct mxs_pair {

arch/arm/mach-socfpga/include/mach/reset_manager.h

@@ -65,12 +65,13 @@ struct socfpga_reset_manager {
  */
 #define RSTMGR_EMAC0		RSTMGR_DEFINE(1, 0)
 #define RSTMGR_EMAC1		RSTMGR_DEFINE(1, 1)
+#define RSTMGR_NAND		RSTMGR_DEFINE(1, 4)
+#define RSTMGR_QSPI		RSTMGR_DEFINE(1, 5)
 #define RSTMGR_L4WD0		RSTMGR_DEFINE(1, 6)
 #define RSTMGR_OSC1TIMER0	RSTMGR_DEFINE(1, 8)
 #define RSTMGR_UART0		RSTMGR_DEFINE(1, 16)
 #define RSTMGR_SPIM0		RSTMGR_DEFINE(1, 18)
 #define RSTMGR_SPIM1		RSTMGR_DEFINE(1, 19)
-#define RSTMGR_QSPI		RSTMGR_DEFINE(1, 5)
 #define RSTMGR_SDMMC		RSTMGR_DEFINE(1, 22)
 #define RSTMGR_DMA		RSTMGR_DEFINE(1, 28)
 #define RSTMGR_SDR		RSTMGR_DEFINE(1, 29)

arch/arm/mach-socfpga/misc.c

@@ -54,14 +54,23 @@ void enable_caches(void)
 
 void v7_outer_cache_enable(void)
 {
-	/* disable the L2 cache */
-	writel(0, &pl310->pl310_ctrl);
+	/* Disable the L2 cache */
+	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 
 	/* enable BRESP, instruction and data prefetch, full line of zeroes */
 	setbits_le32(&pl310->pl310_aux_ctrl,
 		     L310_AUX_CTRL_DATA_PREFETCH_MASK |
 		     L310_AUX_CTRL_INST_PREFETCH_MASK |
 		     L310_SHARED_ATT_OVERRIDE_ENABLE);
+
+	/* Enable the L2 cache */
+	setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
+
+void v7_outer_cache_disable(void)
+{
+	/* Disable the L2 cache */
+	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 }
 
 /*
@@ -350,6 +359,10 @@ int arch_early_init_r(void)
 	socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
 #endif
 
+#ifdef CONFIG_NAND_DENALI
+	socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
+#endif
+
 	return 0;
 }
 

arch/arm/mach-socfpga/spl.c

@@ -40,6 +40,7 @@ u32 spl_boot_device(void)
 		return BOOT_DEVICE_RAM;
 	case 0x2:	/* NAND Flash (1.8V) */
 	case 0x3:	/* NAND Flash (3.0V) */
+		socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
 		return BOOT_DEVICE_NAND;
 	case 0x4:	/* SD/MMC External Transceiver (1.8V) */
 	case 0x5:	/* SD/MMC Internal Transceiver (3.0V) */

arch/arm/mach-uniphier/Makefile

@@ -6,9 +6,8 @@ ifdef CONFIG_SPL_BUILD
 
 obj-y += lowlevel_init.o
 obj-y += init_page_table.o
-obj-y += boards.o
 
-obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/ umc/ ddrphy/
+obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/ dram/
 obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/
 
 obj-$(CONFIG_DEBUG_LL) += debug_ll.o
@@ -33,6 +32,7 @@ obj-y += pinctrl/ clk/
 endif
 
 obj-y += timer.o
+obj-y += boards.o
 obj-y += soc_info.o
 obj-y += boot-mode/
 

arch/arm/mach-uniphier/board_late_init.c

@@ -6,6 +6,7 @@
 
 #include <common.h>
 #include <spl.h>
+#include <libfdt.h>
 #include <nand.h>
 #include <linux/io.h>
 #include <../drivers/mtd/nand/denali.h>
@@ -25,6 +26,38 @@ static void nand_denali_wp_disable(void)
 #endif
 }
 
+struct uniphier_fdt_file {
+	const char *compatible;
+	const char *file_name;
+};
+
+static const struct uniphier_fdt_file uniphier_fdt_files[] = {
+	{ "socionext,ph1-ld4-ref", "uniphier-ph1-ld4-ref.dtb", },
+	{ "socionext,ph1-ld6b-ref", "uniphier-ph1-ld6b-ref.dtb", },
+	{ "socionext,ph1-ld10-ref", "uniphier-ph1-ld10-ref.dtb", },
+	{ "socionext,ph1-pro4-ref", "uniphier-ph1-pro4-ref.dtb", },
+	{ "socionext,ph1-pro5-4kbox", "uniphier-ph1-pro5-4kbox.dtb", },
+	{ "socionext,ph1-sld3-ref", "uniphier-ph1-sld3-ref.dtb", },
+	{ "socionext,ph1-sld8-ref", "uniphier-ph1-sld8-ref.dtb", },
+	{ "socionext,proxstream2-gentil", "uniphier-proxstream2-gentil.dtb", },
+	{ "socionext,proxstream2-vodka", "uniphier-proxstream2-vodka.dtb", },
+};
+
+static void uniphier_set_fdt_file(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	int i;
+
+	/* lookup DTB file name based on the compatible string */
+	for (i = 0; i < ARRAY_SIZE(uniphier_fdt_files); i++) {
+		if (!fdt_node_check_compatible(gd->fdt_blob, 0,
+					uniphier_fdt_files[i].compatible)) {
+			setenv("fdt_file", uniphier_fdt_files[i].file_name);
+			return;
+		}
+	}
+}
+
 int board_late_init(void)
 {
 	puts("MODE:  ");
@@ -48,5 +81,7 @@ int board_late_init(void)
 		return -1;
 	}
 
+	uniphier_set_fdt_file();
+
 	return 0;
 }

arch/arm/mach-uniphier/boards.c

@@ -4,10 +4,13 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <common.h>
 #include <libfdt.h>
 #include <linux/kernel.h>
 #include <mach/init.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
 static const struct uniphier_board_data ph1_sld3_data = {
 	.dram_ch0_base	= 0x80000000,
@@ -71,9 +74,23 @@ static const struct uniphier_board_data ph1_pro5_data = {
 };
 #endif
 
-#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) || \
-	defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
 static const struct uniphier_board_data proxstream2_data = {
+	.dram_ch0_base  = 0x80000000,
+	.dram_ch0_size  = 0x40000000,
+	.dram_ch0_width = 32,
+	.dram_ch1_base  = 0xc0000000,
+	.dram_ch1_size  = 0x20000000,
+	.dram_ch1_width = 32,
+	.dram_ch2_base  = 0xe0000000,
+	.dram_ch2_size  = 0x20000000,
+	.dram_ch2_width = 16,
+	.dram_freq      = 2133,
+};
+#endif
+
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+static const struct uniphier_board_data ph1_ld6b_data = {
 	.dram_ch0_base  = 0x80000000,
 	.dram_ch0_size  = 0x40000000,
 	.dram_ch0_width = 32,
@@ -112,16 +129,16 @@ static const struct uniphier_board_id uniphier_boards[] = {
 	{ "socionext,proxstream2", &proxstream2_data, },
 #endif
 #if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
-	{ "socionext,ph1-ld6b", &proxstream2_data, },
+	{ "socionext,ph1-ld6b", &ph1_ld6b_data, },
 #endif
 };
 
-const struct uniphier_board_data *uniphier_get_board_param(const void *fdt)
+const struct uniphier_board_data *uniphier_get_board_param(void)
 {
 	int i;
 
 	for (i = 0; i < ARRAY_SIZE(uniphier_boards); i++) {
-		if (!fdt_node_check_compatible(fdt, 0,
+		if (!fdt_node_check_compatible(gd->fdt_blob, 0,
 					       uniphier_boards[i].compatible))
 			return uniphier_boards[i].param;
 	}

arch/arm/mach-uniphier/cmd_ddrphy.c

@@ -50,7 +50,7 @@ static void __wbdl_dump(struct ddrphy_datx8 __iomem *dx)
 	printf(FS "(+" PRINTF_FORMAT ")", readl(&dx->lcdlr[1]) & 0xff);
 }
 
-void wbdl_dump(void)
+static void wbdl_dump(void)
 {
 	printf("\n--- Write Bit Delay Line ---\n");
 	printf("           DQ0  DQ1  DQ2  DQ3  DQ4  DQ5  DQ6  DQ7   DM  DQS  (WDQD)\n");
@@ -68,7 +68,7 @@ static void __rbdl_dump(struct ddrphy_datx8 __iomem *dx)
 	printf(FS "(+" PRINTF_FORMAT ")", (readl(&dx->lcdlr[1]) >> 8) & 0xff);
 }
 
-void rbdl_dump(void)
+static void rbdl_dump(void)
 {
 	printf("\n--- Read Bit Delay Line ---\n");
 	printf("           DQ0  DQ1  DQ2  DQ3  DQ4  DQ5  DQ6  DQ7   DM  (RDQSD)\n");
@@ -91,7 +91,7 @@ static void __wld_dump(struct ddrphy_datx8 __iomem *dx)
 	}
 }
 
-void wld_dump(void)
+static void wld_dump(void)
 {
 	printf("\n--- Write Leveling Delay ---\n");
 	printf("            Rank0   Rank1   Rank2   Rank3\n");
@@ -113,7 +113,7 @@ static void __dqsgd_dump(struct ddrphy_datx8 __iomem *dx)
 	}
 }
 
-void dqsgd_dump(void)
+static void dqsgd_dump(void)
 {
 	printf("\n--- DQS Gating Delay ---\n");
 	printf("            Rank0   Rank1   Rank2   Rank3\n");
@@ -129,7 +129,7 @@ static void __mdl_dump(struct ddrphy_datx8 __iomem *dx)
 		printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
 }
 
-void mdl_dump(void)
+static void mdl_dump(void)
 {
 	printf("\n--- Master Delay Line ---\n");
 	printf("          IPRD TPRD MDLD\n");
@@ -141,7 +141,7 @@ void mdl_dump(void)
 	{ u32 __iomem *p = &phy->x; printf("%3d: %-10s: %p : %08x\n", \
 					p - (u32 *)phy, #x, p, readl(p)); }
 
-void reg_dump(void)
+static void reg_dump(void)
 {
 	int ch, p;
 	struct ddrphy __iomem *phy;

arch/arm/mach-uniphier/cpu_info.c

@@ -43,13 +43,18 @@ int print_cpuinfo(void)
 	case 0x2F:
 		puts("PH1-LD6b (MN2WS0320)");
 		break;
+	case 0x31:
+		puts("PH1-sLD11 ()");
+		break;
+	case 0x32:
+		puts("PH1-LD10 ()");
+		break;
 	default:
 		printf("Unknown Processor ID (0x%x)\n", revision);
 		return -1;
 	}
 
-	if (model > 1)
-		printf(" model %d", model);
+	printf(" model %d", model);
 
 	printf(" (rev. %d)\n", rev);
 

arch/arm/mach-uniphier/ddrphy/Makefile

@@ -1,7 +0,0 @@
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4)	+= ddrphy-training.o ddrphy-ph1-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4)	+= ddrphy-training.o ddrphy-ph1-pro4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8)	+= ddrphy-training.o ddrphy-ph1-sld8.o

arch/arm/mach-uniphier/dram/Makefile

@@ -0,0 +1,10 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4)	+= umc-ph1-ld4.o \
+					   ddrphy-training.o ddrphy-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4)	+= umc-ph1-pro4.o \
+					   ddrphy-training.o ddrphy-ph1-pro4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8)	+= umc-ph1-sld8.o \
+					   ddrphy-training.o ddrphy-ph1-sld8.o

arch/arm/mach-uniphier/dram/ddrphy-training.c

@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <linux/err.h>
 #include <linux/io.h>
 #include <mach/ddrphy-regs.h>
 
@@ -32,8 +33,8 @@ void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank)
 	/* Use Multi-Purpose Register for DQS gate training */
 	tmp |= DTCR_DTMPR;
 	/* Specify the rank enabled for data-training */
-	tmp &= ~DTCR_RNKEN_MASK;
-	tmp |= (1 << (DTCR_RNKEN_SHIFT + rank)) & DTCR_RNKEN_MASK;
+	tmp &= ~DTCR_RANKEN_MASK;
+	tmp |= (1 << (DTCR_RANKEN_SHIFT + rank)) & DTCR_RANKEN_MASK;
 	writel(tmp, p);
 }
 
@@ -44,7 +45,7 @@ struct ddrphy_init_sequence {
 	u32 err_flag;
 };
 
-static struct ddrphy_init_sequence init_sequence[] = {
+static const struct ddrphy_init_sequence init_sequence[] = {
 	{
 		"DRAM Initialization",
 		PIR_DRAMRST | PIR_DRAMINIT,
@@ -117,7 +118,7 @@ int ddrphy_training(struct ddrphy __iomem *phy)
 		if (--timeout < 0) {
 			printf("%s: error: timeout during DDR training\n",
 								__func__);
-			return -1;
+			return -ETIMEDOUT;
 		}
 		udelay(1);
 		pgsr0 = readl(&phy->pgsr[0]);
@@ -127,7 +128,7 @@ int ddrphy_training(struct ddrphy __iomem *phy)
 		if (pgsr0 & init_sequence[i].err_flag) {
 			printf("%s: error: %s failed\n", __func__,
 						init_sequence[i].description);
-			return -1;
+			return -EIO;
 		}
 	}
 

arch/arm/mach-uniphier/include/mach/ddrphy-regs.h

@@ -9,6 +9,7 @@
 #ifndef ARCH_DDRPHY_REGS_H
 #define ARCH_DDRPHY_REGS_H
 
+#include <linux/bitops.h>
 #include <linux/compiler.h>
 
 #ifndef __ASSEMBLY__
@@ -79,52 +80,52 @@ struct ddrphy {
 
 #endif /* __ASSEMBLY__ */
 
-#define PIR_INIT		(1 <<  0)	/* Initialization Trigger */
-#define PIR_ZCAL		(1 <<  1)	/* Impedance Calibration */
-#define PIR_PLLINIT		(1 <<  4)	/* PLL Initialization */
-#define PIR_DCAL		(1 <<  5)	/* DDL Calibration */
-#define PIR_PHYRST		(1 <<  6)	/* PHY Reset */
-#define PIR_DRAMRST		(1 <<  7)	/* DRAM Reset */
-#define PIR_DRAMINIT		(1 <<  8)	/* DRAM Initialization */
-#define PIR_WL			(1 <<  9)	/* Write Leveling */
-#define PIR_QSGATE		(1 << 10)	/* Read DQS Gate Training */
-#define PIR_WLADJ		(1 << 11)	/* Write Leveling Adjust */
-#define PIR_RDDSKW		(1 << 12)	/* Read Data Bit Deskew */
-#define PIR_WRDSKW		(1 << 13)	/* Write Data Bit Deskew */
-#define PIR_RDEYE		(1 << 14)	/* Read Data Eye Training */
-#define PIR_WREYE		(1 << 15)	/* Write Data Eye Training */
-#define PIR_LOCKBYP		(1 << 28)	/* PLL Lock Bypass */
-#define PIR_DCALBYP		(1 << 29)	/* DDL Calibration Bypass */
-#define PIR_ZCALBYP		(1 << 30)	/* Impedance Calib Bypass */
-#define PIR_INITBYP		(1 << 31)	/* Initialization Bypass */
+#define PIR_INIT		BIT(0)		/* Initialization Trigger */
+#define PIR_ZCAL		BIT(1)		/* Impedance Calibration */
+#define PIR_PLLINIT		BIT(4)		/* PLL Initialization */
+#define PIR_DCAL		BIT(5)		/* DDL Calibration */
+#define PIR_PHYRST		BIT(6)		/* PHY Reset */
+#define PIR_DRAMRST		BIT(7)		/* DRAM Reset */
+#define PIR_DRAMINIT		BIT(8)		/* DRAM Initialization */
+#define PIR_WL			BIT(9)		/* Write Leveling */
+#define PIR_QSGATE		BIT(10)		/* Read DQS Gate Training */
+#define PIR_WLADJ		BIT(11)		/* Write Leveling Adjust */
+#define PIR_RDDSKW		BIT(12)		/* Read Data Bit Deskew */
+#define PIR_WRDSKW		BIT(13)		/* Write Data Bit Deskew */
+#define PIR_RDEYE		BIT(14)		/* Read Data Eye Training */
+#define PIR_WREYE		BIT(15)		/* Write Data Eye Training */
+#define PIR_LOCKBYP		BIT(28)		/* PLL Lock Bypass */
+#define PIR_DCALBYP		BIT(29)		/* DDL Calibration Bypass */
+#define PIR_ZCALBYP		BIT(30)		/* Impedance Calib Bypass */
+#define PIR_INITBYP		BIT(31)		/* Initialization Bypass */
 
-#define PGSR0_IDONE		(1 <<  0)	/* Initialization Done */
-#define PGSR0_PLDONE		(1 <<  1)	/* PLL Lock Done */
-#define PGSR0_DCDONE		(1 <<  2)	/* DDL Calibration Done */
-#define PGSR0_ZCDONE		(1 <<  3)	/* Impedance Calibration Done */
-#define PGSR0_DIDONE		(1 <<  4)	/* DRAM Initialization Done */
-#define PGSR0_WLDONE		(1 <<  5)	/* Write Leveling Done */
-#define PGSR0_QSGDONE		(1 <<  6)	/* DQS Gate Training Done */
-#define PGSR0_WLADONE		(1 <<  7)	/* Write Leveling Adjust Done */
-#define PGSR0_RDDONE		(1 <<  8)	/* Read Bit Deskew Done */
-#define PGSR0_WDDONE		(1 <<  9)	/* Write Bit Deskew Done */
-#define PGSR0_REDONE		(1 << 10)	/* Read Eye Training Done */
-#define PGSR0_WEDONE		(1 << 11)	/* Write Eye Training Done */
-#define PGSR0_IERR		(1 << 16)	/* Initialization Error */
-#define PGSR0_PLERR		(1 << 17)	/* PLL Lock Error */
-#define PGSR0_DCERR		(1 << 18)	/* DDL Calibration Error */
-#define PGSR0_ZCERR		(1 << 19)	/* Impedance Calib Error */
-#define PGSR0_DIERR		(1 << 20)	/* DRAM Initialization Error */
-#define PGSR0_WLERR		(1 << 21)	/* Write Leveling Error */
-#define PGSR0_QSGERR		(1 << 22)	/* DQS Gate Training Error */
-#define PGSR0_WLAERR		(1 << 23)	/* Write Leveling Adj Error */
-#define PGSR0_RDERR		(1 << 24)	/* Read Bit Deskew Error */
-#define PGSR0_WDERR		(1 << 25)	/* Write Bit Deskew Error */
-#define PGSR0_REERR		(1 << 26)	/* Read Eye Training Error */
-#define PGSR0_WEERR		(1 << 27)	/* Write Eye Training Error */
+#define PGSR0_IDONE		BIT(0)		/* Initialization Done */
+#define PGSR0_PLDONE		BIT(1)		/* PLL Lock Done */
+#define PGSR0_DCDONE		BIT(2)		/* DDL Calibration Done */
+#define PGSR0_ZCDONE		BIT(3)		/* Impedance Calibration Done */
+#define PGSR0_DIDONE		BIT(4)		/* DRAM Initialization Done */
+#define PGSR0_WLDONE		BIT(5)		/* Write Leveling Done */
+#define PGSR0_QSGDONE		BIT(6)		/* DQS Gate Training Done */
+#define PGSR0_WLADONE		BIT(7)		/* Write Leveling Adjust Done */
+#define PGSR0_RDDONE		BIT(8)		/* Read Bit Deskew Done */
+#define PGSR0_WDDONE		BIT(9)		/* Write Bit Deskew Done */
+#define PGSR0_REDONE		BIT(10)		/* Read Eye Training Done */
+#define PGSR0_WEDONE		BIT(11)		/* Write Eye Training Done */
+#define PGSR0_IERR		BIT(16)		/* Initialization Error */
+#define PGSR0_PLERR		BIT(17)		/* PLL Lock Error */
+#define PGSR0_DCERR		BIT(18)		/* DDL Calibration Error */
+#define PGSR0_ZCERR		BIT(19)		/* Impedance Calib Error */
+#define PGSR0_DIERR		BIT(20)		/* DRAM Initialization Error */
+#define PGSR0_WLERR		BIT(21)		/* Write Leveling Error */
+#define PGSR0_QSGERR		BIT(22)		/* DQS Gate Training Error */
+#define PGSR0_WLAERR		BIT(23)		/* Write Leveling Adj Error */
+#define PGSR0_RDERR		BIT(24)		/* Read Bit Deskew Error */
+#define PGSR0_WDERR		BIT(25)		/* Write Bit Deskew Error */
+#define PGSR0_REERR		BIT(26)		/* Read Eye Training Error */
+#define PGSR0_WEERR		BIT(27)		/* Write Eye Training Error */
 #define PGSR0_DTERR_SHIFT	28		/* Data Training Error Status*/
 #define PGSR0_DTERR		(7 << (PGSR0_DTERR_SHIFT))
-#define PGSR0_APLOCK		(1 << 31)	/* AC PLL Lock */
+#define PGSR0_APLOCK		BIT(31)		/* AC PLL Lock */
 
 #define DXCCR_DQSRES_OPEN	(0 << 5)
 #define DXCCR_DQSRES_688_OHM	(1 << 5)
@@ -146,9 +147,9 @@ struct ddrphy {
 
 #define DTCR_DTRANK_SHIFT	4		/* Data Training Rank */
 #define DTCR_DTRANK_MASK	(0x3 << (DTCR_DTRANK_SHIFT))
-#define DTCR_DTMPR		(1 << 6)	/* Data Training using MPR */
-#define DTCR_RNKEN_SHIFT	24		/* Rank Enable */
-#define DTCR_RNKEN_MASK		(0xf << (DTCR_RNKEN_SHIFT))
+#define DTCR_DTMPR		BIT(6)		/* Data Training using MPR */
+#define DTCR_RANKEN_SHIFT	24		/* Rank Enable */
+#define DTCR_RANKEN_MASK	(0xf << (DTCR_RANKEN_SHIFT))
 
 #define DXGCR_WLRKEN_SHIFT	26		/* Write Level Rank Enable */
 #define DXGCR_WLRKEN_MASK	(0xf << (DXGCR_WLRKEN_SHIFT))

arch/arm/mach-uniphier/include/mach/init.h

@@ -20,7 +20,7 @@ struct uniphier_board_data {
 	unsigned int  dram_freq;
 };
 
-const struct uniphier_board_data *uniphier_get_board_param(const void *fdt);
+const struct uniphier_board_data *uniphier_get_board_param(void);
 
 int ph1_sld3_init(const struct uniphier_board_data *bd);
 int ph1_ld4_init(const struct uniphier_board_data *bd);

arch/arm/mach-uniphier/include/mach/soc_info.h

@@ -15,6 +15,8 @@ enum uniphier_soc_id {
 	SOC_UNIPHIER_PH1_PRO5,
 	SOC_UNIPHIER_PROXSTREAM2,
 	SOC_UNIPHIER_PH1_LD6B,
+	SOC_UNIPHIER_PH1_SLD11,
+	SOC_UNIPHIER_PH1_LD10,
 	SOC_UNIPHIER_UNKNOWN,
 };
 
@@ -25,7 +27,9 @@ enum uniphier_soc_id {
 	IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD8) +	\
 	IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_PRO5) +	\
 	IS_ENABLED(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) +	\
-	IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+	IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD6B) + \
+	IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD11) + \
+	IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD10)
 
 #define UNIPHIER_MULTI_SOC	((UNIPHIER_NR_ENABLED_SOCS) > 1)
 
@@ -55,9 +59,18 @@ static inline enum uniphier_soc_id uniphier_get_soc_type(void)
 #if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
 	return SOC_UNIPHIER_PH1_LD6B;
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD11)
+	return SOC_UNIPHIER_PH1_SLD11;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD10)
+	return SOC_UNIPHIER_PH1_LD10;
+#endif
 
 	return SOC_UNIPHIER_UNKNOWN;
 }
 #endif
 
+int uniphier_get_soc_model(void);
+int uniphier_get_soc_revision(void);
+
 #endif /* __MACH_SOC_INFO_H__ */

arch/arm/mach-uniphier/init/init.c

@@ -9,13 +9,11 @@
 #include <mach/init.h>
 #include <mach/soc_info.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 void spl_board_init(void)
 {
 	const struct uniphier_board_data *param;
 
-	param = uniphier_get_board_param(gd->fdt_blob);
+	param = uniphier_get_board_param();
 	if (!param)
 		hang();
 

arch/arm/mach-uniphier/soc_info.c

@@ -50,6 +50,16 @@ enum uniphier_soc_id uniphier_get_soc_type(void)
 	case 0x2F:
 		ret = SOC_UNIPHIER_PH1_LD6B;
 		break;
+#endif
+#ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD11
+	case 0x31:
+		ret = SOC_UNIPHIER_PH1_SLD11;
+		break;
+#endif
+#ifdef CONFIG_ARCH_UNIPHIER_PH1_LD10
+	case 0x32:
+		ret = SOC_UNIPHIER_PH1_LD10;
+		break;
 #endif
 	default:
 		ret = SOC_UNIPHIER_UNKNOWN;
@@ -59,3 +69,15 @@ enum uniphier_soc_id uniphier_get_soc_type(void)
 	return ret;
 }
 #endif
+
+int uniphier_get_soc_model(void)
+{
+	return (readl(SG_REVISION) & SG_REVISION_MODEL_MASK) >>
+						SG_REVISION_MODEL_SHIFT;
+}
+
+int uniphier_get_soc_revision(void)
+{
+	return (readl(SG_REVISION) & SG_REVISION_REV_MASK) >>
+						SG_REVISION_REV_SHIFT;
+}

arch/arm/mach-uniphier/umc/Makefile

@@ -1,7 +0,0 @@
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4)	+= umc-ph1-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4)	+= umc-ph1-pro4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8)	+= umc-ph1-sld8.o

arch/powerpc/cpu/mpc5xxx/start.S

@@ -91,6 +91,7 @@ _start:
 	li	r5,GD_SIZE	/* parameter 3:	 count			*/
 	bl	memset
 
+	li	r3, 0		/* parameter 1:	 bootflag		*/
 	bl	board_init_f	/* run 1st part of board init code (in Flash)*/
 	/* NOTREACHED - board_init_f() does not return */
 #else
@@ -169,6 +170,7 @@ lowboot_reentry:
 	/* r3: IMMR */
 	bl	cpu_init_f	/* run low-level CPU init code (in Flash)*/
 
+	li	r3, 0		/* parameter 1:	 bootflag		*/
 	bl	board_init_f	/* run 1st part of board init code (in Flash)*/
 
 	/* NOTREACHED - board_init_f() does not return */

arch/powerpc/cpu/mpc83xx/ecc.c

@@ -37,7 +37,7 @@ void ecc_print_status(void)
 	printf("Memory Error Disable:\n");
 	printf("  Multiple-Bit Error Disable: %d\n",
 	       (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
-	printf("  Sinle-Bit Error Disable: %d\n",
+	printf("  Single-Bit Error Disable: %d\n",
 	       (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
 	printf("  Memory Select Error Disable: %d\n\n",
 	       (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
@@ -273,7 +273,7 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 			count = simple_strtoul(argv[3], NULL, 16);
 
 			if ((u32) addr % 8) {
-				printf("Address not alligned on "
+				printf("Address not aligned on "
 				       "double word boundary\n");
 				return 1;
 			}
@@ -312,7 +312,7 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 			count = simple_strtoul(argv[3], NULL, 16);
 
 			if ((u32) addr % 8) {
-				printf("Address not alligned on "
+				printf("Address not aligned on "
 				       "double word boundary\n");
 				return 1;
 			}

arch/powerpc/cpu/mpc83xx/pci.c

@@ -123,7 +123,7 @@ void mpc83xx_pci_init(int num_buses, struct pci_region **reg)
 	int i;
 
 	if (num_buses > MAX_BUSES) {
-		printf("%d PCI buses requsted, %d supported\n",
+		printf("%d PCI buses requested, %d supported\n",
 		       num_buses, MAX_BUSES);
 
 		num_buses = MAX_BUSES;

arch/powerpc/cpu/mpc83xx/qe_io.c

@@ -23,7 +23,7 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
 	volatile immap_t	*im = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile qepio83xx_t	*par_io = (volatile qepio83xx_t *)&im->qepio;
 
-	/* Caculate pin location and 2bit mask and dir */
+	/* Calculate pin location and 2bit mask and dir */
 	pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
 	pin_2bit_dir = (u32)(dir << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
 

arch/powerpc/cpu/mpc83xx/spd_sdram.c

@@ -599,7 +599,7 @@ long int spd_sdram()
 
 	/*
 	 * Empirically set ~MCAS-to-preamble override for DDR 2.
-	 * Your milage will vary.
+	 * Your mileage will vary.
 	 */
 	cpo = 0;
 	if (spd.mem_type == SPD_MEMTYPE_DDR2) {
@@ -843,7 +843,7 @@ long int spd_sdram()
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 /*
- * Use timebase counter, get_timer() is not availabe
+ * Use timebase counter, get_timer() is not available
  * at this point of initialization yet.
  */
 static __inline__ unsigned long get_tbms (void)

arch/powerpc/cpu/mpc83xx/speed.c

@@ -170,7 +170,7 @@ int get_clocks(void)
 		tsec1_clk = csb_clk / 3;
 		break;
 	default:
-		/* unkown SCCR_TSEC1CM value */
+		/* unknown SCCR_TSEC1CM value */
 		return -2;
 	}
 #endif
@@ -191,7 +191,7 @@ int get_clocks(void)
 		usbdr_clk = csb_clk / 3;
 		break;
 	default:
-		/* unkown SCCR_USBDRCM value */
+		/* unknown SCCR_USBDRCM value */
 		return -3;
 	}
 #endif
@@ -212,7 +212,7 @@ int get_clocks(void)
 		tsec2_clk = csb_clk / 3;
 		break;
 	default:
-		/* unkown SCCR_TSEC2CM value */
+		/* unknown SCCR_TSEC2CM value */
 		return -4;
 	}
 #elif defined(CONFIG_MPC8313)
@@ -239,7 +239,7 @@ int get_clocks(void)
 		usbmph_clk = csb_clk / 3;
 		break;
 	default:
-		/* unkown SCCR_USBMPHCM value */
+		/* unknown SCCR_USBMPHCM value */
 		return -5;
 	}
 
@@ -266,7 +266,7 @@ int get_clocks(void)
 		enc_clk = csb_clk / 3;
 		break;
 	default:
-		/* unkown SCCR_ENCCM value */
+		/* unknown SCCR_ENCCM value */
 		return -7;
 	}
 #endif
@@ -286,7 +286,7 @@ int get_clocks(void)
 		sdhc_clk = csb_clk / 3;
 		break;
 	default:
-		/* unkown SCCR_SDHCCM value */
+		/* unknown SCCR_SDHCCM value */
 		return -8;
 	}
 #endif
@@ -305,7 +305,7 @@ int get_clocks(void)
 		tdm_clk = csb_clk / 3;
 		break;
 	default:
-		/* unkown SCCR_TDMCM value */
+		/* unknown SCCR_TDMCM value */
 		return -8;
 	}
 #endif
@@ -345,7 +345,7 @@ int get_clocks(void)
 		pciexp1_clk = csb_clk / 3;
 		break;
 	default:
-		/* unkown SCCR_PCIEXP1CM value */
+		/* unknown SCCR_PCIEXP1CM value */
 		return -9;
 	}
 
@@ -363,7 +363,7 @@ int get_clocks(void)
 		pciexp2_clk = csb_clk / 3;
 		break;
 	default:
-		/* unkown SCCR_PCIEXP2CM value */
+		/* unknown SCCR_PCIEXP2CM value */
 		return -10;
 	}
 #endif
@@ -383,7 +383,7 @@ int get_clocks(void)
 		sata_clk = csb_clk / 3;
 		break;
 	default:
-		/* unkown SCCR_SATACM value */
+		/* unknown SCCR_SATA1CM value */
 		return -11;
 	}
 #endif
@@ -413,7 +413,7 @@ int get_clocks(void)
 
 	corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
 	if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) {
-		/* corecnf_tab_index is too high, possibly worng value */
+		/* corecnf_tab_index is too high, possibly wrong value */
 		return -11;
 	}
 	switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
@@ -435,7 +435,7 @@ int get_clocks(void)
 		core_clk = 3 * csb_clk;
 		break;
 	default:
-		/* unkown core to csb ratio */
+		/* unknown core to csb ratio */
 		return -13;
 	}
 

arch/powerpc/cpu/mpc83xx/spl_minimal.c

@@ -47,7 +47,7 @@ void cpu_init_f (volatile immap_t * im)
 			   (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT);
 #endif
 
-	/* Enable Time Base & Decrimenter (so we will have udelay()) */
+	/* Enable Time Base & Decrementer (so we will have udelay()) */
 	im->sysconf.spcr |= SPCR_TBEN;
 
 	/* DDR control driver register */

arch/sandbox/dts/test.dts

@@ -279,6 +279,11 @@
 			0x38 8>;
 	};
 
+	timer {
+		compatible = "sandbox,timer";
+		clock-frequency = <1000000>;
+	};
+
 	uart0: serial {
 		compatible = "sandbox,serial";
 		u-boot,dm-pre-reloc;

board/altera/cyclone5-socdk/qts/pinmux_config.h

@@ -9,19 +9,19 @@
 
 const u8 sys_mgr_init_table[] = {
 	3, /* EMACIO0 */
-	3, /* EMACIO1 */
-	3, /* EMACIO2 */
-	3, /* EMACIO3 */
-	3, /* EMACIO4 */
-	3, /* EMACIO5 */
-	3, /* EMACIO6 */
-	3, /* EMACIO7 */
-	3, /* EMACIO8 */
+	2, /* EMACIO1 */
+	2, /* EMACIO2 */
+	2, /* EMACIO3 */
+	2, /* EMACIO4 */
+	2, /* EMACIO5 */
+	2, /* EMACIO6 */
+	2, /* EMACIO7 */
+	2, /* EMACIO8 */
 	3, /* EMACIO9 */
-	3, /* EMACIO10 */
-	3, /* EMACIO11 */
-	3, /* EMACIO12 */
-	3, /* EMACIO13 */
+	2, /* EMACIO10 */
+	2, /* EMACIO11 */
+	2, /* EMACIO12 */
+	2, /* EMACIO13 */
 	0, /* EMACIO14 */
 	0, /* EMACIO15 */
 	0, /* EMACIO16 */
@@ -55,8 +55,8 @@ const u8 sys_mgr_init_table[] = {
 	0, /* GENERALIO12 */
 	2, /* GENERALIO13 */
 	2, /* GENERALIO14 */
-	0, /* GENERALIO15 */
-	0, /* GENERALIO16 */
+	3, /* GENERALIO15 */
+	3, /* GENERALIO16 */
 	2, /* GENERALIO17 */
 	2, /* GENERALIO18 */
 	0, /* GENERALIO19 */
@@ -72,27 +72,27 @@ const u8 sys_mgr_init_table[] = {
 	0, /* GENERALIO29 */
 	0, /* GENERALIO30 */
 	0, /* GENERALIO31 */
-	0, /* MIXED1IO0 */
-	1, /* MIXED1IO1 */
-	1, /* MIXED1IO2 */
-	1, /* MIXED1IO3 */
-	1, /* MIXED1IO4 */
-	0, /* MIXED1IO5 */
-	0, /* MIXED1IO6 */
-	0, /* MIXED1IO7 */
-	1, /* MIXED1IO8 */
-	1, /* MIXED1IO9 */
-	1, /* MIXED1IO10 */
-	1, /* MIXED1IO11 */
-	0, /* MIXED1IO12 */
-	0, /* MIXED1IO13 */
+	2, /* MIXED1IO0 */
+	2, /* MIXED1IO1 */
+	2, /* MIXED1IO2 */
+	2, /* MIXED1IO3 */
+	2, /* MIXED1IO4 */
+	2, /* MIXED1IO5 */
+	2, /* MIXED1IO6 */
+	2, /* MIXED1IO7 */
+	2, /* MIXED1IO8 */
+	2, /* MIXED1IO9 */
+	2, /* MIXED1IO10 */
+	2, /* MIXED1IO11 */
+	2, /* MIXED1IO12 */
+	2, /* MIXED1IO13 */
 	0, /* MIXED1IO14 */
-	1, /* MIXED1IO15 */
-	1, /* MIXED1IO16 */
-	1, /* MIXED1IO17 */
-	1, /* MIXED1IO18 */
-	0, /* MIXED1IO19 */
-	0, /* MIXED1IO20 */
+	3, /* MIXED1IO15 */
+	3, /* MIXED1IO16 */
+	3, /* MIXED1IO17 */
+	3, /* MIXED1IO18 */
+	3, /* MIXED1IO19 */
+	3, /* MIXED1IO20 */
 	0, /* MIXED1IO21 */
 	0, /* MIXED2IO0 */
 	0, /* MIXED2IO1 */

board/altera/cyclone5-socdk/qts/pll_config.h

@@ -14,7 +14,7 @@
 #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
 #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
 #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
@@ -31,7 +31,7 @@
 #define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79
 #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
 #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
 #define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
 #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
 #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4

board/congatec/cgtqmx6eval/MAINTAINERS

@@ -3,4 +3,4 @@ M:	Otavio Salvador <otavio@ossystems.com.br>
 S:	Maintained
 F:	board/congatec/cgtqmx6eval/
 F:	include/configs/cgtqmx6eval.h
-F:	configs/cgtqmx6qeval_defconfig
+F:	configs/cgtqmx6eval_defconfig

board/congatec/cgtqmx6eval/README

@@ -25,11 +25,15 @@ host PC (/tftpboot , for example).
 
 => sf probe
 
+=> setenv serverip <server_ip_address>
+
+=> setenv ipaddr <board_ip_address>
+
 => tftp 0x12000000 SPL
 
 => sf erase 0x0 0x10000
 
-=> sf write 0x12000000 0x400 0x100
+=> sf write 0x12000000 0x400 0x10000
 
 => tftp 0x12000000 u-boot.img
 

board/congatec/cgtqmx6eval/cgtqmx6eval.c

@@ -404,7 +404,7 @@ static void setup_iomux_uart(void)
 #ifdef CONFIG_MXC_SPI
 static void setup_spi(void)
 {
-	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+	SETUP_IOMUX_PADS(ecspi1_pads);
 	gpio_direction_output(IMX_GPIO_NR(3, 19), 0);
 }
 #endif

board/freescale/common/pfuze.c

@@ -13,7 +13,8 @@
 int pfuze_mode_init(struct pmic *p, u32 mode)
 {
 	unsigned char offset, i, switch_num;
-	u32 id, ret;
+	u32 id;
+	int ret;
 
 	pmic_reg_read(p, PFUZE100_DEVICEID, &id);
 	id = id & 0xf;

board/freescale/ls2080a/MAINTAINERS

@@ -1,5 +1,5 @@
 LS2080A BOARD
-M:	York Sun <yorksun@freescale.com>
+M:	York Sun <york.sun@nxp.com>
 S:	Maintained
 F:	board/freescale/ls2080a/
 F:	include/configs/ls2080a_emu.h

board/freescale/mpc8572ds/MAINTAINERS

@@ -1,5 +1,5 @@
 MPC8572DS BOARD
-M:	York Sun <yorksun@freescale.com>
+M:	York Sun <york.sun@nxp.com>
 S:	Maintained
 F:	board/freescale/mpc8572ds/
 F:	include/configs/MPC8572DS.h

board/freescale/mx25pdk/MAINTAINERS

@@ -1,5 +1,5 @@
 MX25PDK BOARD
-M:	Fabio Estevam <fabio.estevam@freescale.com>
+M:	Fabio Estevam <fabio.estevam@nxp.com>
 S:	Maintained
 F:	board/freescale/mx25pdk/
 F:	include/configs/mx25pdk.h

board/freescale/mx28evk/MAINTAINERS

@@ -1,5 +1,5 @@
 MX28EVK BOARD
-M:	Fabio Estevam <fabio.estevam@freescale.com>
+M:	Fabio Estevam <fabio.estevam@nxp.com>
 S:	Maintained
 F:	board/freescale/mx28evk/
 F:	include/configs/mx28evk.h

board/freescale/mx53ard/MAINTAINERS

@@ -1,5 +1,5 @@
 MX53ARD BOARD
-M:	Fabio Estevam <fabio.estevam@freescale.com>
+M:	Fabio Estevam <fabio.estevam@nxp.com>
 S:	Maintained
 F:	board/freescale/mx53ard/
 F:	include/configs/mx53ard.h

board/freescale/mx53smd/MAINTAINERS

@@ -1,5 +1,5 @@
 MX53SMD BOARD
-M:	Fabio Estevam <fabio.estevam@freescale.com>
+M:	Fabio Estevam <fabio.estevam@nxp.com>
 S:	Maintained
 F:	board/freescale/mx53smd/
 F:	include/configs/mx53smd.h

board/freescale/mx6qsabreauto/MAINTAINERS

@@ -1,5 +1,5 @@
 MX6QSABREAUTO BOARD
-M:	Fabio Estevam <fabio.estevam@freescale.com>
+M:	Fabio Estevam <fabio.estevam@nxp.com>
 M:	Peng Fan <Peng.Fan@freescale.com>
 S:	Maintained
 F:	board/freescale/mx6qsabreauto/

board/freescale/mx6qsabreauto/mx6qsabreauto.c

@@ -412,12 +412,42 @@ u32 get_board_rev(void)
 }
 
 #if defined(CONFIG_VIDEO_IPUV3)
+static void disable_lvds(struct display_info_t const *dev)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	clrbits_le32(&iomux->gpr[2],
+		     IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
+		     IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
+}
+
 static void do_enable_hdmi(struct display_info_t const *dev)
 {
+	disable_lvds(dev);
 	imx_enable_hdmi_phy();
 }
 
 struct display_info_t const displays[] = {{
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB666,
+	.detect	= NULL,
+	.enable	= NULL,
+	.mode	= {
+		.name           = "Hannstar-XGA",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
 	.bus	= -1,
 	.addr	= 0,
 	.pixfmt	= IPU_PIX_FMT_RGB24,
@@ -440,18 +470,69 @@ struct display_info_t const displays[] = {{
 } } };
 size_t display_count = ARRAY_SIZE(displays);
 
+iomux_v3_cfg_t const backlight_pads[] = {
+	MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_backlight(void)
+{
+	gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
+	imx_iomux_v3_setup_multiple_pads(backlight_pads,
+					 ARRAY_SIZE(backlight_pads));
+}
+
 static void setup_display(void)
 {
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 	int reg;
 
+	setup_iomux_backlight();
 	enable_ipu_clock();
 	imx_setup_hdmi();
 
+	/* Turn on LDB_DI0 and LDB_DI1 clocks */
+	reg = readl(&mxc_ccm->CCGR3);
+	reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
+	writel(reg, &mxc_ccm->CCGR3);
+
+	/* Set LDB_DI0 and LDB_DI1 clk select to 3b'011 */
+	reg = readl(&mxc_ccm->cs2cdr);
+	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
+		 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+	reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
+	       (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->cs2cdr);
+
+	reg = readl(&mxc_ccm->cscmr2);
+	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
+	writel(reg, &mxc_ccm->cscmr2);
+
 	reg = readl(&mxc_ccm->chsccdr);
 	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
+		MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
 	writel(reg, &mxc_ccm->chsccdr);
+
+	reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
+	      IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
+	      IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
+	      IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
+	      IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
+	      IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
+	      IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
+	      IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED;
+	writel(reg, &iomux->gpr[2]);
+
+	reg = readl(&iomux->gpr[3]);
+	reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
+		 IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
+	reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+		IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
+	       (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+		IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET);
+	writel(reg, &iomux->gpr[3]);
 }
 #endif /* CONFIG_VIDEO_IPUV3 */
 
@@ -467,9 +548,6 @@ int overwrite_console(void)
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
-#ifdef CONFIG_VIDEO_IPUV3
-	setup_display();
-#endif
 
 #ifdef CONFIG_NAND_MXS
 	setup_gpmi_nand();
@@ -494,6 +572,9 @@ int board_init(void)
 	gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
 	imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
 
+#ifdef CONFIG_VIDEO_IPUV3
+	setup_display();
+#endif
 	setup_iomux_eimnor();
 	return 0;
 }

board/freescale/mx6sabresd/MAINTAINERS

@@ -1,5 +1,5 @@
 MX6SABRESD BOARD
-M:	Fabio Estevam <fabio.estevam@freescale.com>
+M:	Fabio Estevam <fabio.estevam@nxp.com>
 S:	Maintained
 F:	board/freescale/mx6sabresd/
 F:	include/configs/mx6sabresd.h

board/freescale/mx6sabresd/mx6sabresd.c

@@ -94,8 +94,9 @@ static void setup_iomux_enet(void)
 
 	/* Reset AR8031 PHY */
 	gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
-	udelay(500);
+	mdelay(10);
 	gpio_set_value(IMX_GPIO_NR(1, 25), 1);
+	udelay(100);
 }
 
 static iomux_v3_cfg_t const usdhc2_pads[] = {
@@ -340,39 +341,6 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
-int mx6_rgmii_rework(struct phy_device *phydev)
-{
-	unsigned short val;
-
-	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-
-	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
-	val &= 0xffe3;
-	val |= 0x18;
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
-
-	/* introduce tx clock delay */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
-	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
-	val |= 0x0100;
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
-
-	return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
-	mx6_rgmii_rework(phydev);
-
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
-
-	return 0;
-}
-
 #if defined(CONFIG_VIDEO_IPUV3)
 static void disable_lvds(struct display_info_t const *dev)
 {

board/freescale/mx6slevk/MAINTAINERS

@@ -1,5 +1,5 @@
 MX6SLEVK BOARD
-M:	Fabio Estevam <fabio.estevam@freescale.com>
+M:	Fabio Estevam <fabio.estevam@nxp.com>
 M:	Peng Fan <Peng.Fan@freescale.com>
 S:	Maintained
 F:	board/freescale/mx6slevk/

board/freescale/mx6sxsabresd/MAINTAINERS

@@ -1,5 +1,5 @@
 MX6SXSABRESD BOARD
-M:	Fabio Estevam <fabio.estevam@freescale.com>
+M:	Fabio Estevam <fabio.estevam@nxp.com>
 S:	Maintained
 F:	board/freescale/mx6sxsabresd/
 F:	include/configs/mx6sxsabresd.h

board/freescale/mx6sxsabresd/mx6sxsabresd.c

@@ -150,11 +150,15 @@ static int setup_fec(void)
 {
 	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
-	int reg;
+	int reg, ret;
 
 	/* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
 	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
 
+	ret = enable_fec_anatop_clock(0, ENET_125MHZ);
+	if (ret)
+		return ret;
+
 	imx_iomux_v3_setup_multiple_pads(phy_control_pads,
 					 ARRAY_SIZE(phy_control_pads));
 
@@ -163,14 +167,14 @@ static int setup_fec(void)
 
 	/* Reset AR8031 PHY */
 	gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
-	udelay(500);
+	mdelay(10);
 	gpio_set_value(IMX_GPIO_NR(2, 7), 1);
 
 	reg = readl(&anatop->pll_enet);
 	reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
 	writel(reg, &anatop->pll_enet);
 
-	return enable_fec_anatop_clock(0, ENET_125MHZ);
+	return 0;
 }
 
 int board_eth_init(bd_t *bis)

board/freescale/qemu-ppce500/qemu-ppce500.c

@@ -81,7 +81,7 @@ static int pci_map_region(void *fdt, int pci_node, int range_id,
 	ulong map_addr;
 	int r;
 
-	r = fdt_read_range(fdt, pci_node, 0, NULL, &addr, &size);
+	r = fdt_read_range(fdt, pci_node, range_id, NULL, &addr, &size);
 	if (r)
 		return r;
 

board/solidrun/mx6cuboxi/MAINTAINERS

@@ -1,5 +1,5 @@
 MX6CUBOXI BOARD
-M:	Fabio Estevam <fabio.estevam@freescale.com>
+M:	Fabio Estevam <fabio.estevam@nxp.com>
 S:	Maintained
 F:	board/solidrun/mx6cuboxi/
 F:	include/configs/mx6cuboxi.h

board/solidrun/mx6cuboxi/mx6cuboxi.c

@@ -143,8 +143,9 @@ static void setup_iomux_enet(void)
 	SETUP_IOMUX_PADS(enet_pads);
 
 	gpio_direction_output(ETH_PHY_RESET, 0);
-	mdelay(2);
+	mdelay(10);
 	gpio_set_value(ETH_PHY_RESET, 1);
+	udelay(100);
 }
 
 int board_phy_config(struct phy_device *phydev)
@@ -594,10 +595,6 @@ static void gpr_init(void)
 	writel(0x007F007F, &iomux->gpr[7]);
 }
 
-/*
- * This section requires the differentiation between Solidrun mx6 boards, but
- * for now, it will configure only for the mx6dual hummingboard version.
- */
 static void spl_dram_init(int width)
 {
 	struct mx6_ddr_sysinfo sysinfo = {

board/spear/spear600/spear600.c

@@ -48,9 +48,6 @@ int board_eth_init(bd_t *bis)
 
 #if defined(CONFIG_ETH_DESIGNWARE)
 	u32 interface = PHY_INTERFACE_MODE_MII;
-#if defined(CONFIG_DW_AUTONEG)
-	interface = PHY_INTERFACE_MODE_GMII;
-#endif
 	if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
 		ret++;
 #endif

board/udoo/MAINTAINERS

@@ -1,5 +1,5 @@
 UDOO BOARD
-M:	Fabio Estevam <fabio.estevam@freescale.com>
+M:	Fabio Estevam <fabio.estevam@nxp.com>
 S:	Maintained
 F:	board/udoo/
 F:	include/configs/udoo.h

board/wandboard/MAINTAINERS

@@ -1,5 +1,5 @@
 WANDBOARD BOARD
-M:	Fabio Estevam <fabio.estevam@freescale.com>
+M:	Fabio Estevam <fabio.estevam@nxp.com>
 S:	Maintained
 F:	board/wandboard/
 F:	include/configs/wandboard.h

board/wandboard/wandboard.c

@@ -121,8 +121,9 @@ static void setup_iomux_enet(void)
 
 	/* Reset AR8031 PHY */
 	gpio_direction_output(ETH_PHY_RESET, 0);
-	udelay(500);
+	mdelay(10);
 	gpio_set_value(ETH_PHY_RESET, 1);
+	udelay(100);
 }
 
 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
@@ -187,39 +188,6 @@ int board_mmc_init(bd_t *bis)
 	return 0;
 }
 
-static int mx6_rgmii_rework(struct phy_device *phydev)
-{
-	unsigned short val;
-
-	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-
-	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
-	val &= 0xffe3;
-	val |= 0x18;
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
-
-	/* introduce tx clock delay */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
-	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
-	val |= 0x0100;
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
-
-	return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
-	mx6_rgmii_rework(phydev);
-
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
-
-	return 0;
-}
-
 #if defined(CONFIG_VIDEO_IPUV3)
 struct i2c_pads_info mx6q_i2c2_pad_info = {
 	.scl = {

common/cli.c

@@ -103,9 +103,9 @@ int run_command_list(const char *cmd, int len, int flag)
 	 * is pretty rare.
 	 */
 	rcode = cli_simple_run_command_list(buff, flag);
+#endif
 	if (need_buff)
 		free(buff);
-#endif
 
 	return rcode;
 }

common/cmd_mem.c

@@ -931,7 +931,7 @@ static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr,
 		addr[offset] = 0;
 	}
 
-	return 0;
+	return errs;
 }
 
 static ulong mem_test_quick(vu_long *buf, ulong start_addr, ulong end_addr,
@@ -990,7 +990,7 @@ static ulong mem_test_quick(vu_long *buf, ulong start_addr, ulong end_addr,
 		val += incr;
 	}
 
-	return 0;
+	return errs;
 }
 
 /*

common/cmd_nvedit.c

@@ -595,7 +595,7 @@ static int do_env_edit(cmd_tbl_t *cmdtp, int flag, int argc,
 	/* Set read buffer to initial value or empty sting */
 	init_val = getenv(argv[1]);
 	if (init_val)
-		sprintf(buffer, "%s", init_val);
+		snprintf(buffer, CONFIG_SYS_CBSIZE, "%s", init_val);
 	else
 		buffer[0] = '\0';
 

common/env_callback.c

@@ -97,6 +97,7 @@ static int set_callback(const char *name, const char *value, void *priv)
 
 	e.key	= name;
 	e.data	= NULL;
+	e.callback = NULL;
 	hsearch_r(e, FIND, &ep, &env_htab, 0);
 
 	/* does the env variable actually exist? */

common/env_flags.c

@@ -455,6 +455,7 @@ static int set_flags(const char *name, const char *value, void *priv)
 
 	e.key	= name;
 	e.data	= NULL;
+	e.callback = NULL;
 	hsearch_r(e, FIND, &ep, &env_htab, 0);
 
 	/* does the env variable actually exist? */

common/fdt_support.c

@@ -952,8 +952,7 @@ void fdt_del_node_and_alias(void *blob, const char *alias)
 /* Max address size we deal with */
 #define OF_MAX_ADDR_CELLS	4
 #define OF_BAD_ADDR	FDT_ADDR_T_NONE
-#define OF_CHECK_COUNTS(na, ns)	((na) > 0 && (na) <= OF_MAX_ADDR_CELLS && \
-			(ns) > 0)
+#define OF_CHECK_COUNTS(na)	((na) > 0 && (na) <= OF_MAX_ADDR_CELLS)
 
 /* Debug utility */
 #ifdef DEBUG
@@ -1121,7 +1120,7 @@ static u64 __of_translate_address(void *blob, int node_offset, const fdt32_t *in
 
 	/* Cound address cells & copy address locally */
 	bus->count_cells(blob, parent, &na, &ns);
-	if (!OF_CHECK_COUNTS(na, ns)) {
+	if (!OF_CHECK_COUNTS(na)) {
 		printf("%s: Bad cell count for %s\n", __FUNCTION__,
 		       fdt_get_name(blob, node_offset, NULL));
 		goto bail;
@@ -1148,7 +1147,7 @@ static u64 __of_translate_address(void *blob, int node_offset, const fdt32_t *in
 		/* Get new parent bus and counts */
 		pbus = &of_busses[0];
 		pbus->count_cells(blob, parent, &pna, &pns);
-		if (!OF_CHECK_COUNTS(pna, pns)) {
+		if (!OF_CHECK_COUNTS(pna)) {
 			printf("%s: Bad cell count for %s\n", __FUNCTION__,
 				fdt_get_name(blob, node_offset, NULL));
 			break;

common/usb.c

@@ -566,13 +566,12 @@ static int usb_get_descriptor(struct usb_device *dev, unsigned char type,
 }
 
 /**********************************************************************
- * gets configuration cfgno and store it in the buffer
+ * gets len of configuration cfgno
  */
-int usb_get_configuration_no(struct usb_device *dev,
-			     unsigned char *buffer, int cfgno)
+int usb_get_configuration_len(struct usb_device *dev, int cfgno)
 {
 	int result;
-	unsigned int length;
+	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, 9);
 	struct usb_config_descriptor *config;
 
 	config = (struct usb_config_descriptor *)&buffer[0];
@@ -586,17 +585,23 @@ int usb_get_configuration_no(struct usb_device *dev,
 				"(expected %i, got %i)\n", 9, result);
 		return -EIO;
 	}
-	length = le16_to_cpu(config->wTotalLength);
+	return le16_to_cpu(config->wTotalLength);
+}
 
-	if (length > USB_BUFSIZ) {
-		printf("%s: failed to get descriptor - too long: %d\n",
-			__func__, length);
-		return -EIO;
-	}
+/**********************************************************************
+ * gets configuration cfgno and store it in the buffer
+ */
+int usb_get_configuration_no(struct usb_device *dev, int cfgno,
+			     unsigned char *buffer, int length)
+{
+	int result;
+	struct usb_config_descriptor *config;
 
+	config = (struct usb_config_descriptor *)&buffer[0];
 	result = usb_get_descriptor(dev, USB_DT_CONFIG, cfgno, buffer, length);
-	debug("get_conf_no %d Result %d, wLength %d\n", cfgno, result, length);
-	config->wTotalLength = length; /* validated, with CPU byte order */
+	debug("get_conf_no %d Result %d, wLength %d\n", cfgno, result,
+	      le16_to_cpu(config->wTotalLength));
+	config->wTotalLength = result; /* validated, with CPU byte order */
 
 	return result;
 }
@@ -1070,7 +1075,7 @@ static int usb_prepare_device(struct usb_device *dev, int addr, bool do_read,
 
 int usb_select_config(struct usb_device *dev)
 {
-	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, tmpbuf, USB_BUFSIZ);
+	unsigned char *tmpbuf = 0;
 	int err;
 
 	err = get_descriptor_len(dev, USB_DT_DEVICE_SIZE, USB_DT_DEVICE_SIZE);
@@ -1084,14 +1089,23 @@ int usb_select_config(struct usb_device *dev)
 	le16_to_cpus(&dev->descriptor.bcdDevice);
 
 	/* only support for one config for now */
-	err = usb_get_configuration_no(dev, tmpbuf, 0);
+	err = usb_get_configuration_len(dev, 0);
+	if (err >= 0) {
+		tmpbuf = (unsigned char *)malloc_cache_aligned(err);
+		if (!tmpbuf)
+			err = -ENOMEM;
+		else
+			err = usb_get_configuration_no(dev, 0, tmpbuf, err);
+	}
 	if (err < 0) {
 		printf("usb_new_device: Cannot read configuration, " \
 		       "skipping device %04x:%04x\n",
 		       dev->descriptor.idVendor, dev->descriptor.idProduct);
+		free(tmpbuf);
 		return err;
 	}
 	usb_parse_config(dev, tmpbuf, 0);
+	free(tmpbuf);
 	usb_set_maxpacket(dev);
 	/*
 	 * we set the default configuration here
@@ -1200,4 +1214,60 @@ bool usb_device_has_child_on_port(struct usb_device *parent, int port)
 #endif
 }
 
+#ifdef CONFIG_DM_USB
+void usb_find_usb2_hub_address_port(struct usb_device *udev,
+			       uint8_t *hub_address, uint8_t *hub_port)
+{
+	struct udevice *parent;
+	struct usb_device *uparent, *ttdev;
+
+	/*
+	 * When called from usb-uclass.c: usb_scan_device() udev->dev points
+	 * to the parent udevice, not the actual udevice belonging to the
+	 * udev as the device is not instantiated yet. So when searching
+	 * for the first usb-2 parent start with udev->dev not
+	 * udev->dev->parent .
+	 */
+	ttdev = udev;
+	parent = udev->dev;
+	uparent = dev_get_parent_priv(parent);
+
+	while (uparent->speed != USB_SPEED_HIGH) {
+		struct udevice *dev = parent;
+
+		if (device_get_uclass_id(dev->parent) != UCLASS_USB_HUB) {
+			printf("Error: Cannot find high speed parent of usb-1 device\n");
+			*hub_address = 0;
+			*hub_port = 0;
+			return;
+		}
+
+		ttdev = dev_get_parent_priv(dev);
+		parent = dev->parent;
+		uparent = dev_get_parent_priv(parent);
+	}
+	*hub_address = uparent->devnum;
+	*hub_port = ttdev->portnr;
+}
+#else
+void usb_find_usb2_hub_address_port(struct usb_device *udev,
+			       uint8_t *hub_address, uint8_t *hub_port)
+{
+	/* Find out the nearest parent which is high speed */
+	while (udev->parent->parent != NULL)
+		if (udev->parent->speed != USB_SPEED_HIGH) {
+			udev = udev->parent;
+		} else {
+			*hub_address = udev->parent->devnum;
+			*hub_port = udev->portnr;
+			return;
+		}
+
+	printf("Error: Cannot find high speed parent of usb-1 device\n");
+	*hub_address = 0;
+	*hub_port = 0;
+}
+#endif
+
+
 /* EOF */

common/usb_kbd.c

@@ -611,6 +611,41 @@ static int usb_kbd_probe(struct udevice *dev)
 	return ret;
 }
 
+static int usb_kbd_remove(struct udevice *dev)
+{
+	struct usb_device *udev = dev_get_parent_priv(dev);
+	struct usb_kbd_pdata *data;
+	struct stdio_dev *sdev;
+	int ret;
+
+	sdev = stdio_get_by_name(DEVNAME);
+	if (!sdev) {
+		ret = -ENXIO;
+		goto err;
+	}
+	data = udev->privptr;
+	if (stdio_deregister_dev(sdev, true)) {
+		ret = -EPERM;
+		goto err;
+	}
+#ifdef CONFIG_CONSOLE_MUX
+	if (iomux_doenv(stdin, getenv("stdin"))) {
+		ret = -ENOLINK;
+		goto err;
+	}
+#endif
+#ifdef CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
+	destroy_int_queue(udev, data->intq);
+#endif
+	free(data->new);
+	free(data);
+
+	return 0;
+err:
+	printf("%s: warning, ret=%d", __func__, ret);
+	return ret;
+}
+
 static const struct udevice_id usb_kbd_ids[] = {
 	{ .compatible = "usb-keyboard" },
 	{ }
@@ -621,6 +656,7 @@ U_BOOT_DRIVER(usb_kbd) = {
 	.id	= UCLASS_KEYBOARD,
 	.of_match = usb_kbd_ids,
 	.probe = usb_kbd_probe,
+	.remove = usb_kbd_remove,
 };
 
 static const struct usb_device_id kbd_id_table[] = {

common/usb_storage.c

@@ -65,7 +65,7 @@ static const unsigned char us_direction[256/8] = {
 static ccb usb_ccb __attribute__((aligned(ARCH_DMA_MINALIGN)));
 static __u32 CBWTag;
 
-#define USB_MAX_STOR_DEV 5
+#define USB_MAX_STOR_DEV 7
 static int usb_max_devs; /* number of highest available usb device */
 
 static block_dev_desc_t usb_dev_desc[USB_MAX_STOR_DEV];

configs/chromebook_jerry_defconfig

@@ -27,7 +27,9 @@ CONFIG_RESET=y
 CONFIG_DM_MMC=y
 CONFIG_ROCKCHIP_DWMMC=y
 CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_FULL is not set
 CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_FULL is not set
 CONFIG_ROCKCHIP_PINCTRL=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_ACT8846=y
@@ -41,5 +43,7 @@ CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550=y
 CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
+CONFIG_ROCKCHIP_SPI=y

configs/orangepi_pc_defconfig

@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_MACH_SUN8I_H3=y
-CONFIG_DRAM_CLK=672
+CONFIG_DRAM_CLK=624
 CONFIG_DRAM_ZQ=3881979
 CONFIG_DRAM_ODT_EN=y
 # CONFIG_VIDEO is not set

configs/ph1_sld8_defconfig

@@ -1,30 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_UNIPHIER=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_ARCH_UNIPHIER_PH1_SLD8=y
-CONFIG_MICRO_SUPPORT_CARD=y
-CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld8-ref"
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-CONFIG_CMD_NAND=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TIME=y
-# CONFIG_CMD_MISC is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_SIMPLE_BUS=y
-CONFIG_NAND_DENALI=y
-CONFIG_SYS_NAND_DENALI_64BIT=y
-CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
-CONFIG_SPL_NAND_DENALI=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
-CONFIG_UNIPHIER_SERIAL=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y

configs/socfpga_arria5_defconfig

@@ -11,6 +11,7 @@ CONFIG_SPL_STACK_R=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
+CONFIG_SPL_SIMPLE_BUS=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -23,3 +24,4 @@ CONFIG_DESIGNWARE_SPI=y
 CONFIG_DM_MMC=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set

configs/socfpga_cyclone5_defconfig

@@ -11,6 +11,7 @@ CONFIG_SPL_STACK_R=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
+CONFIG_SPL_SIMPLE_BUS=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -23,3 +24,4 @@ CONFIG_DESIGNWARE_SPI=y
 CONFIG_DM_MMC=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set

configs/socfpga_sr1500_defconfig

@@ -17,3 +17,4 @@ CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_MMC=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set

configs/uniphier_ld4_sld8_defconfig

@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_UNIPHIER=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ARCH_UNIPHIER_PH1_LD4=y
+CONFIG_ARCH_UNIPHIER_PH1_SLD8=y
 CONFIG_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x84000000
 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref"