Prepare v2017.03

Signed-off-by: Tom Rini <trini@konsulko.com>

.travis.yml

@@ -28,11 +28,12 @@ addons:
     - grub-efi-ia32-bin
     - rpm2cpio
     - wget
+    - device-tree-compiler
 
 install:
  # install latest device tree compiler
- - git clone --depth=1 git://git.kernel.org/pub/scm/utils/dtc/dtc.git /tmp/dtc
- - make -j4 -C /tmp/dtc
+ #- git clone --depth=1 git://git.kernel.org/pub/scm/utils/dtc/dtc.git /tmp/dtc
+ #- make -j4 -C /tmp/dtc
  # Clone uboot-test-hooks
  - git clone --depth=1 git://github.com/swarren/uboot-test-hooks.git /tmp/uboot-test-hooks
  - ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`

Makefile

@@ -5,7 +5,7 @@
 VERSION = 2017
 PATCHLEVEL = 03
 SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION =
 NAME =
 
 # *DOCUMENTATION*
@@ -371,7 +371,7 @@ export ARCH CPU BOARD VENDOR SOC CPUDIR BOARDDIR
 export CONFIG_SHELL HOSTCC HOSTCFLAGS HOSTLDFLAGS CROSS_COMPILE AS LD CC
 export CPP AR NM LDR STRIP OBJCOPY OBJDUMP
 export MAKE AWK PERL PYTHON
-export HOSTCXX HOSTCXXFLAGS DTC CHECK CHECKFLAGS
+export HOSTCXX HOSTCXXFLAGS CHECK CHECKFLAGS DTC DTC_FLAGS
 
 export KBUILD_CPPFLAGS NOSTDINC_FLAGS UBOOTINCLUDE OBJCOPYFLAGS LDFLAGS
 export KBUILD_CFLAGS KBUILD_AFLAGS

README

@@ -600,21 +600,6 @@ The following options need to be configured:
 		Thumb2 this flag will result in Thumb2 code generated by
 		GCC.
 
-		CONFIG_ARM_ERRATA_716044
-		CONFIG_ARM_ERRATA_742230
-		CONFIG_ARM_ERRATA_743622
-		CONFIG_ARM_ERRATA_751472
-		CONFIG_ARM_ERRATA_761320
-		CONFIG_ARM_ERRATA_773022
-		CONFIG_ARM_ERRATA_774769
-		CONFIG_ARM_ERRATA_794072
-
-		If set, the workarounds for these ARM errata are applied early
-		during U-Boot startup. Note that these options force the
-		workarounds to be applied; no CPU-type/version detection
-		exists, unlike the similar options in the Linux kernel. Do not
-		set these options unless they apply!
-
 		COUNTER_FREQUENCY
 		Generic timer clock source frequency.
 
@@ -623,15 +608,6 @@ The following options need to be configured:
 		different from COUNTER_FREQUENCY, and can only be determined
 		at run time.
 
-		NOTE: The following can be machine specific errata. These
-		do have ability to provide rudimentary version and machine
-		specific checks, but expect no product checks.
-		CONFIG_ARM_ERRATA_430973
-		CONFIG_ARM_ERRATA_454179
-		CONFIG_ARM_ERRATA_621766
-		CONFIG_ARM_ERRATA_798870
-		CONFIG_ARM_ERRATA_801819
-
 - Tegra SoC options:
 		CONFIG_TEGRA_SUPPORT_NON_SECURE
 

arch/arm/Kconfig

@@ -19,6 +19,72 @@ config HAS_VBAR
 config HAS_THUMB2
 	bool
 
+# If set, the workarounds for these ARM errata are applied early during U-Boot
+# startup. Note that in general these options force the workarounds to be
+# applied; no CPU-type/version detection exists, unlike the similar options in
+# the Linux kernel. Do not set these options unless they apply!  Also note that
+# the following can be machine specific errata. These do have ability to
+# provide rudimentary version and machine specific checks, but expect no
+# product checks:
+# CONFIG_ARM_ERRATA_430973
+# CONFIG_ARM_ERRATA_454179
+# CONFIG_ARM_ERRATA_621766
+# CONFIG_ARM_ERRATA_798870
+# CONFIG_ARM_ERRATA_801819
+config ARM_ERRATA_430973
+	bool
+
+config ARM_ERRATA_454179
+	bool
+
+config ARM_ERRATA_621766
+	bool
+
+config ARM_ERRATA_716044
+	bool
+
+config ARM_ERRATA_742230
+	bool
+
+config ARM_ERRATA_743622
+	bool
+
+config ARM_ERRATA_751472
+	bool
+
+config ARM_ERRATA_761320
+	bool
+
+config ARM_ERRATA_773022
+	bool
+
+config ARM_ERRATA_774769
+	bool
+
+config ARM_ERRATA_794072
+	bool
+
+config ARM_ERRATA_798870
+	bool
+
+config ARM_ERRATA_801819
+	bool
+
+config ARM_ERRATA_826974
+	bool
+
+config ARM_ERRATA_828024
+	bool
+
+config ARM_ERRATA_829520
+	bool
+
+config ARM_ERRATA_833069
+	bool
+
+config ARM_ERRATA_833471
+	bool
+
 config CPU_ARM720T
 	bool
 	select SYS_CACHE_SHIFT_5
@@ -569,16 +635,56 @@ config TARGET_MX53SMD
 config OMAP34XX
 	bool "OMAP34XX SoC"
 	select ARCH_OMAP2
+	select ARM_ERRATA_430973
+	select ARM_ERRATA_454179
+	select ARM_ERRATA_621766
 	select USE_TINY_PRINTF
+	imply SPL_EXT_SUPPORT
+	imply SPL_FAT_SUPPORT
+	imply SPL_GPIO_SUPPORT
+	imply SPL_I2C_SUPPORT
+	imply SPL_LIBCOMMON_SUPPORT
+	imply SPL_LIBDISK_SUPPORT
+	imply SPL_LIBGENERIC_SUPPORT
+	imply SPL_MMC_SUPPORT
+	imply SPL_NAND_SUPPORT
+	imply SPL_POWER_SUPPORT
+	imply SPL_SERIAL_SUPPORT
 
 config OMAP44XX
 	bool "OMAP44XX SoC"
 	select ARCH_OMAP2
 	select USE_TINY_PRINTF
+	imply SPL_DISPLAY_PRINT
+	imply SPL_EXT_SUPPORT
+	imply SPL_FAT_SUPPORT
+	imply SPL_GPIO_SUPPORT
+	imply SPL_I2C_SUPPORT
+	imply SPL_LIBCOMMON_SUPPORT
+	imply SPL_LIBDISK_SUPPORT
+	imply SPL_LIBGENERIC_SUPPORT
+	imply SPL_MMC_SUPPORT
+	imply SPL_NAND_SUPPORT
+	imply SPL_POWER_SUPPORT
+	imply SPL_SERIAL_SUPPORT
 
 config OMAP54XX
 	bool "OMAP54XX SoC"
 	select ARCH_OMAP2
+	select ARM_ERRATA_798870
+	imply SPL_DISPLAY_PRINT
+	imply SPL_ENV_SUPPORT
+	imply SPL_EXT_SUPPORT
+	imply SPL_FAT_SUPPORT
+	imply SPL_GPIO_SUPPORT
+	imply SPL_I2C_SUPPORT
+	imply SPL_LIBCOMMON_SUPPORT
+	imply SPL_LIBDISK_SUPPORT
+	imply SPL_LIBGENERIC_SUPPORT
+	imply SPL_MMC_SUPPORT
+	imply SPL_NAND_SUPPORT
+	imply SPL_POWER_SUPPORT
+	imply SPL_SERIAL_SUPPORT
 
 config AM43XX
 	bool "AM43XX SoC"
@@ -633,6 +739,7 @@ config ARCH_SOCFPGA
 	select ENABLE_ARM_SOC_BOOT0_HOOK
 	select ARCH_EARLY_INIT_R
 	select ARCH_MISC_INIT
+	select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
 
 config TARGET_CM_T43
 	bool "Support cm_t43"

arch/arm/cpu/armv7/mx6/Kconfig

@@ -3,6 +3,10 @@ if ARCH_MX6
 config MX6
 	bool
 	default y
+	select ARM_ERRATA_743622 if !MX6UL
+	select ARM_ERRATA_751472 if !MX6UL
+	select ARM_ERRATA_761320 if !MX6UL
+	select ARM_ERRATA_794072 if !MX6UL
 
 config MX6D
 	bool

arch/arm/cpu/armv8/fsl-layerscape/Kconfig

@@ -49,6 +49,10 @@ config ARCH_LS1046A
 config ARCH_LS2080A
 	bool
 	select ARMV8_SET_SMPEN
+	select ARM_ERRATA_826974
+	select ARM_ERRATA_828024
+	select ARM_ERRATA_829520
+	select ARM_ERRATA_833471
 	select FSL_LSCH3
 	select SYS_FSL_DDR
 	select SYS_FSL_DDR_LE

arch/arm/dts/uniphier-ld11-ref.dts

@@ -71,7 +71,3 @@
 &pinctrl_uart0 {
 	u-boot,dm-pre-reloc;
 };
-
-&pinctrl_system_bus {
-	u-boot,dm-pre-reloc;
-};

arch/arm/dts/uniphier-ld20-ref.dts

@@ -59,7 +59,3 @@
 &pinctrl_uart0 {
 	u-boot,dm-pre-reloc;
 };
-
-&pinctrl_system_bus {
-	u-boot,dm-pre-reloc;
-};

arch/arm/imx-common/Kconfig

@@ -28,6 +28,7 @@ config USE_IMXIMG_PLUGIN
 config SECURE_BOOT
 	bool "Support i.MX HAB features"
 	depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5
+	select FSL_CAAM
 	help
 	  This option enables the support for secure boot (HAB).
 	  See doc/README.mxc_hab for more details.

arch/arm/include/asm/arch-am33xx/sys_proto.h

@@ -29,7 +29,7 @@ void sdelay(unsigned long);
 void gpmc_init(void);
 void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs, u32 base,
 			u32 size);
-void omap_nand_switch_ecc(uint32_t, uint32_t);
+int omap_nand_switch_ecc(uint32_t, uint32_t);
 
 void set_uart_mux_conf(void);
 void set_mux_conf_regs(void);

arch/arm/include/asm/arch-fsl-layerscape/config.h

@@ -114,12 +114,6 @@
 
 #define CONFIG_SYS_FSL_ERRATUM_A008751
 
-/* ARM A57 CORE ERRATA */
-#define CONFIG_ARM_ERRATA_826974
-#define CONFIG_ARM_ERRATA_828024
-#define CONFIG_ARM_ERRATA_829520
-#define CONFIG_ARM_ERRATA_833471
-
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
 #elif defined(CONFIG_FSL_LSCH2)
 #define CONFIG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial RAM */

arch/arm/include/asm/arch-omap3/sys_proto.h

@@ -68,7 +68,7 @@ u32 wait_on_value(u32, u32, void *, u32);
 void cancel_out(u32 *num, u32 *den, u32 den_limit);
 void sdelay(unsigned long);
 void make_cs1_contiguous(void);
-void omap_nand_switch_ecc(uint32_t, uint32_t);
+int omap_nand_switch_ecc(uint32_t, uint32_t);
 void power_init_r(void);
 void do_omap3_emu_romcode_call(u32 service_id, u32 parameters);
 void omap3_set_aux_cr_secure(u32 acr);

arch/arm/include/asm/arch-omap5/omap.h

@@ -188,7 +188,7 @@ struct s32ktimer {
 #if defined(CONFIG_DRA7XX)
 #define NON_SECURE_SRAM_START	0x40300000
 #define NON_SECURE_SRAM_END	0x40380000	/* Not inclusive */
-#define NON_SECURE_SRAM_IMG_END	0x4037E000
+#define NON_SECURE_SRAM_IMG_END	0x4037C000
 #else
 #define NON_SECURE_SRAM_START	0x40300000
 #define NON_SECURE_SRAM_END	0x40320000	/* Not inclusive */

arch/arm/include/asm/assembler.h

@@ -59,7 +59,7 @@
 
 	.irp	c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
 	.macro	ret\c, reg
-#if defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__)
+#if defined(__ARM_ARCH_5E__)
 	mov\c	pc, \reg
 #else
 	.ifeqs	"\reg", "lr"

arch/arm/include/asm/fsl_secure_boot.h

@@ -12,11 +12,6 @@
 #define CONFIG_FSL_SEC_MON
 #define CONFIG_SHA_HW_ACCEL
 #define CONFIG_SHA_PROG_HW_ACCEL
-#define CONFIG_RSA_FREESCALE_EXP
-
-#ifndef CONFIG_FSL_CAAM
-#define CONFIG_FSL_CAAM
-#endif
 
 #define CONFIG_SPL_BOARD_INIT
 #ifdef CONFIG_SPL_BUILD

arch/arm/lib/crt0_64.S

@@ -109,8 +109,18 @@ relocation_return:
  */
 	bl	c_runtime_cpu_setup		/* still call old routine */
 #endif /* !CONFIG_SPL_BUILD */
-
-/* TODO: For SPL, call spl_relocate_stack_gd() to alloc stack relocation */
+#if defined(CONFIG_SPL_BUILD)
+	bl	spl_relocate_stack_gd           /* may return NULL */
+	/*
+	 * Perform 'sp = (x0 != NULL) ? x0 : sp' while working
+	 * around the constraint that conditional moves can not
+	 * have 'sp' as an operand
+	 */
+	mov	x1, sp
+	cmp	x0, #0
+	csel	x0, x0, x1, ne
+	mov	sp, x0
+#endif
 
 /*
  * Clear BSS section

arch/arm/lib/semihosting.c

@@ -186,7 +186,7 @@ static int do_smhload(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	if (argc == 3 || argc == 4) {
 		ulong load_addr;
 		ulong end_addr = 0;
-		ulong ret;
+		int ret;
 		char end_str[64];
 
 		load_addr = simple_strtoul(argv[2], NULL, 16);
@@ -195,7 +195,7 @@ static int do_smhload(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 		ret = smh_load_file(argv[1], load_addr, &end_addr);
 		if (ret < 0)
-			return 1;
+			return CMD_RET_FAILURE;
 
 		/* Optionally save returned end to the environment */
 		if (argc == 4) {

arch/arm/mach-exynos/Kconfig

@@ -82,6 +82,8 @@ config TARGET_ODROID_XU3
 
 config TARGET_ARNDALE
 	bool "Exynos5250 Arndale board"
+	select ARM_ERRATA_773022
+	select ARM_ERRATA_774769
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select SUPPORT_SPL

arch/arm/mach-omap2/am33xx/Kconfig

@@ -15,6 +15,20 @@ config TARGET_AM335X_EVM
 	select DM_SERIAL
 	select DM_GPIO
 	select TI_I2C_BOARD_DETECT
+	imply SPL_ENV_SUPPORT
+	imply SPL_EXT_SUPPORT
+	imply SPL_FAT_SUPPORT
+	imply SPL_GPIO_SUPPORT
+	imply SPL_I2C_SUPPORT
+	imply SPL_LIBCOMMON_SUPPORT
+	imply SPL_LIBDISK_SUPPORT
+	imply SPL_LIBGENERIC_SUPPORT
+	imply SPL_MMC_SUPPORT
+	imply SPL_NAND_SUPPORT
+	imply SPL_POWER_SUPPORT
+	imply SPL_SERIAL_SUPPORT
+	imply SPL_WATCHDOG_SUPPORT
+	imply SPL_YMODEM_SUPPORT
 	help
 	  This option specifies support for the AM335x
 	  GP and HS EVM development platforms. The AM335x
@@ -101,19 +115,24 @@ endif
 
 if AM43XX
 
-config SPL_EXT_SUPPORT
-	default y
-
-config SPL_GPIO_SUPPORT
-	default y
-
-config SPL_I2C_SUPPORT
-	default y
-
 config TARGET_AM43XX_EVM
 	bool "Support am43xx_evm"
 	select BOARD_LATE_INIT
 	select TI_I2C_BOARD_DETECT
+	imply SPL_ENV_SUPPORT
+	imply SPL_EXT_SUPPORT
+	imply SPL_FAT_SUPPORT
+	imply SPL_GPIO_SUPPORT
+	imply SPL_I2C_SUPPORT
+	imply SPL_LIBCOMMON_SUPPORT
+	imply SPL_LIBDISK_SUPPORT
+	imply SPL_LIBGENERIC_SUPPORT
+	imply SPL_MMC_SUPPORT
+	imply SPL_NAND_SUPPORT
+	imply SPL_POWER_SUPPORT
+	imply SPL_SERIAL_SUPPORT
+	imply SPL_WATCHDOG_SUPPORT
+	imply SPL_YMODEM_SUPPORT
 	help
 	  This option specifies support for the AM43xx
 	  GP and HS EVM development platforms.The AM437x

arch/arm/mach-omap2/emif-common.c

@@ -1195,7 +1195,7 @@ static void do_sdram_init(u32 base)
 			ddr3_init(base, regs);
 #endif
 	}
-#ifdef CONFIG_OMAP54X
+#ifdef CONFIG_OMAP54XX
 	if (warm_reset() && (emif_sdram_type(regs->sdram_config) ==
 	    EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) {
 		set_lpmode_selfrefresh(base);

arch/arm/mach-omap2/omap3/Kconfig

@@ -1,38 +1,5 @@
 if OMAP34XX
 
-config SPL_EXT_SUPPORT
-	default y
-
-config SPL_FAT_SUPPORT
-	default y
-
-config SPL_GPIO_SUPPORT
-	default y
-
-config SPL_I2C_SUPPORT
-	default y
-
-config SPL_LIBCOMMON_SUPPORT
-	default y
-
-config SPL_LIBDISK_SUPPORT
-	default y
-
-config SPL_LIBGENERIC_SUPPORT
-	default y
-
-config SPL_MMC_SUPPORT
-	default y
-
-config SPL_NAND_SUPPORT
-	default y
-
-config SPL_POWER_SUPPORT
-	default y
-
-config SPL_SERIAL_SUPPORT
-	default y
-
 choice
 	prompt "OMAP3 board select"
 	optional

arch/arm/mach-omap2/omap3/board.c

@@ -269,38 +269,34 @@ void abort(void)
  *****************************************************************************/
 static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 {
+	int hw, strength = 1;
+
 	if (argc < 2 || argc > 3)
 		goto usage;
 
 	if (strncmp(argv[1], "hw", 2) == 0) {
-		if (argc == 2) {
-			omap_nand_switch_ecc(1, 1);
-		} else {
-			if (strncmp(argv[2], "hamming", 7) == 0)
-				omap_nand_switch_ecc(1, 1);
-			else if (strncmp(argv[2], "bch8", 4) == 0)
-				omap_nand_switch_ecc(1, 8);
+		hw = 1;
+		if (argc == 3) {
+			if (strncmp(argv[2], "bch8", 4) == 0)
+				strength = 8;
 			else if (strncmp(argv[2], "bch16", 5) == 0)
-				omap_nand_switch_ecc(1, 16);
-			else
+				strength = 16;
+			else if (strncmp(argv[2], "hamming", 7) != 0)
 				goto usage;
 		}
 	} else if (strncmp(argv[1], "sw", 2) == 0) {
-		if (argc == 2) {
-			omap_nand_switch_ecc(0, 1);
-		} else {
-			if (strncmp(argv[2], "hamming", 7) == 0)
-				omap_nand_switch_ecc(0, 1);
-			else if (strncmp(argv[2], "bch8", 4) == 0)
-				omap_nand_switch_ecc(0, 8);
-			else
+		hw = 0;
+		if (argc == 3) {
+			if (strncmp(argv[2], "bch8", 4) == 0)
+				strength = 8;
+			else if (strncmp(argv[2], "hamming", 7) != 0)
 				goto usage;
 		}
 	} else {
 		goto usage;
 	}
 
-	return 0;
+	return -omap_nand_switch_ecc(hw, strength);
 
 usage:
 	printf ("Usage: nandecc %s\n", cmdtp->usage);

arch/arm/mach-omap2/omap4/Kconfig

@@ -1,41 +1,5 @@
 if OMAP44XX
 
-config SPL_EXT_SUPPORT
-	default y
-
-config SPL_FAT_SUPPORT
-	default y
-
-config SPL_GPIO_SUPPORT
-	default y
-
-config SPL_I2C_SUPPORT
-	default y
-
-config SPL_LIBCOMMON_SUPPORT
-	default y
-
-config SPL_LIBDISK_SUPPORT
-	default y
-
-config SPL_LIBGENERIC_SUPPORT
-	default y
-
-config SPL_MMC_SUPPORT
-	default y
-
-config SPL_NAND_SUPPORT
-	default y
-
-config SPL_POWER_SUPPORT
-	default y
-
-config SPL_SERIAL_SUPPORT
-	default y
-
-config SPL_DISPLAY_PRINT
-	default y
-
 choice
 	prompt "OMAP4 board select"
 	optional

arch/arm/mach-omap2/omap5/Kconfig

@@ -1,41 +1,5 @@
 if OMAP54XX
 
-config SPL_EXT_SUPPORT
-	default y
-
-config SPL_FAT_SUPPORT
-	default y
-
-config SPL_GPIO_SUPPORT
-	default y
-
-config SPL_I2C_SUPPORT
-	default y
-
-config SPL_LIBCOMMON_SUPPORT
-	default y
-
-config SPL_LIBDISK_SUPPORT
-	default y
-
-config SPL_LIBGENERIC_SUPPORT
-	default y
-
-config SPL_MMC_SUPPORT
-	default y
-
-config SPL_NAND_SUPPORT
-	default y
-
-config SPL_POWER_SUPPORT
-	default y
-
-config SPL_SERIAL_SUPPORT
-	default y
-
-config SPL_DISPLAY_PRINT
-	default y
-
 choice
 	prompt "OMAP5 board select"
 	optional

arch/arm/mach-omap2/omap5/fdt.c

@@ -161,6 +161,7 @@ static int ft_hs_fixup_dram(void *fdt, bd_t *bd)
 	u32 sec_mem_start = CONFIG_TI_SECURE_EMIF_REGION_START;
 	u32 sec_mem_size = CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE;
 	fdt64_t temp[2];
+	fdt32_t two;
 
 	/* If start address is zero, place at end of DRAM */
 	if (0 == sec_mem_start)
@@ -181,7 +182,7 @@ static int ft_hs_fixup_dram(void *fdt, bd_t *bd)
 		debug("Node %s not found\n", path);
 		path = "/";
 		subpath = "reserved-memory";
-		fdt_path_offset(fdt, path);
+		offs = fdt_path_offset(fdt, path);
 		offs = fdt_add_subnode(fdt, offs, subpath);
 		if (offs < 0) {
 			printf("Could not create %s%s node.\n", path, subpath);
@@ -189,6 +190,10 @@ static int ft_hs_fixup_dram(void *fdt, bd_t *bd)
 		}
 		path = "/reserved-memory";
 		offs = fdt_path_offset(fdt, path);
+		two = cpu_to_fdt32(2);
+		fdt_setprop(fdt, offs, "#address-cells", &two, sizeof(two));
+		fdt_setprop(fdt, offs, "#size-cells", &two, sizeof(two));
+		fdt_setprop(fdt, offs, "ranges", NULL, 0);
 	}
 
 	subpath = "secure_reserved";

arch/arm/mach-omap2/sec-common.c

@@ -120,6 +120,12 @@ int secure_boot_verify_image(void **image, size_t *size)
 	result = secure_rom_call(
 		API_HAL_KM_VERIFYCERTIFICATESIGNATURE_INDEX, 0, 0,
 		4, cert_addr, cert_size, sig_addr, 0xFFFFFFFF);
+
+	/* Perform cache writeback on output buffer */
+	flush_dcache_range(
+		(u32)*image,
+		(u32)*image + roundup(*size, ARCH_DMA_MINALIGN));
+
 auth_exit:
 	if (result != 0) {
 		printf("Authentication failed!\n");

arch/arm/mach-socfpga/Kconfig

@@ -27,6 +27,12 @@ config SPL_SPI_SUPPORT
 config SPL_WATCHDOG_SUPPORT
 	default y
 
+config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
+	default y
+
+config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
+	default 0xa2
+
 config TARGET_SOCFPGA_ARRIA5
 	bool
 	select TARGET_SOCFPGA_GEN5

arch/arm/mach-tegra/Kconfig

@@ -65,10 +65,15 @@ choice
 
 config TEGRA20
 	bool "Tegra20 family"
+	select ARM_ERRATA_716044
+	select ARM_ERRATA_742230
+	select ARM_ERRATA_751472
 	select TEGRA_ARMV7_COMMON
 
 config TEGRA30
 	bool "Tegra30 family"
+	select ARM_ERRATA_743622
+	select ARM_ERRATA_751472
 	select TEGRA_ARMV7_COMMON
 
 config TEGRA114

arch/arm/mach-uniphier/Makefile

@@ -8,6 +8,7 @@ obj-y += boards.o
 obj-y += spl_board_init.o
 obj-y += memconf.o
 obj-y += bcu/
+obj-$(CONFIG_SPL_MMC_SUPPORT) += mmc-boot-mode.o
 
 else
 
@@ -19,11 +20,12 @@ obj-y += reset.o
 
 obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/ micro-support-card.o
 obj-y += pinctrl-glue.o
+obj-$(CONFIG_MMC) += mmc-first-dev.o
 
 endif
 
 obj-y += soc-info.o
-obj-y += boot-mode/
+obj-y += boot-device/
 obj-y += clk/
 obj-y += dram/
 

arch/arm/mach-uniphier/bcu/bcu-ld4.c

@@ -24,7 +24,7 @@ void uniphier_ld4_bcu_init(const struct uniphier_board_data *bd)
 	writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */
 
 	/* Specify DDR channel */
-	shift = (bd->dram_ch[1].base - bd->dram_ch[0].base) / 0x04000000 * 4;
+	shift = bd->dram_ch[0].size / 0x04000000 * 4;
 	writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
 
 	shift -= 32;

arch/arm/mach-uniphier/bcu/bcu-sld3.c

@@ -28,7 +28,7 @@ void uniphier_sld3_bcu_init(const struct uniphier_board_data *bd)
 	writel(0x24440000, BCSCR5);
 
 	/* Specify DDR channel */
-	shift = (bd->dram_ch[1].base - bd->dram_ch[0].base) / 0x04000000 * 4;
+	shift = bd->dram_ch[0].size / 0x04000000 * 4;
 	writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
 
 	shift -= 32;

arch/arm/mach-uniphier/board_init.c

@@ -165,6 +165,7 @@ static const struct uniphier_initdata uniphier_initdata[] = {
 		.nand_2cs = false,
 		.sbc_init = uniphier_ld11_sbc_init,
 		.pll_init = uniphier_ld20_pll_init,
+		.clk_init = uniphier_ld20_clk_init,
 		.misc_init = uniphier_ld20_misc_init,
 	},
 #endif

arch/arm/mach-uniphier/board_late_init.c

@@ -13,7 +13,7 @@
 #include <linux/io.h>
 #include <../drivers/mtd/nand/denali.h>
 
-#include "boot-mode/boot-device.h"
+#include "init.h"
 
 static void nand_denali_wp_disable(void)
 {
@@ -62,7 +62,7 @@ int board_late_init(void)
 {
 	puts("MODE:  ");
 
-	switch (spl_boot_device_raw()) {
+	switch (uniphier_boot_device_raw()) {
 	case BOOT_DEVICE_MMC1:
 		printf("eMMC Boot\n");
 		setenv("bootmode", "emmcboot");

arch/arm/mach-uniphier/boards.c

@@ -16,36 +16,30 @@ DECLARE_GLOBAL_DATA_PTR;
 #if defined(CONFIG_ARCH_UNIPHIER_SLD3)
 static const struct uniphier_board_data uniphier_sld3_data = {
 	.dram_freq = 1600,
-	.dram_nr_ch = 3,
 	.dram_ch[0] = {
-		.base = 0x80000000,
 		.size = 0x20000000,
 		.width = 32,
 	},
 	.dram_ch[1] = {
-		.base = 0xc0000000,
 		.size = 0x20000000,
 		.width = 16,
 	},
 	.dram_ch[2] = {
-		.base = 0xc0000000,
 		.size = 0x10000000,
 		.width = 16,
 	},
+	.flags = UNIPHIER_BD_DRAM_SPARSE,
 };
 #endif
 
 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
 static const struct uniphier_board_data uniphier_ld4_data = {
 	.dram_freq = 1600,
-	.dram_nr_ch = 2,
 	.dram_ch[0] = {
-		.base = 0x80000000,
 		.size = 0x10000000,
 		.width = 16,
 	},
 	.dram_ch[1] = {
-		.base = 0x90000000,
 		.size = 0x10000000,
 		.width = 16,
 	},
@@ -57,14 +51,11 @@ static const struct uniphier_board_data uniphier_ld4_data = {
 /* 1GB RAM board */
 static const struct uniphier_board_data uniphier_pro4_data = {
 	.dram_freq = 1600,
-	.dram_nr_ch = 2,
 	.dram_ch[0] = {
-		.base = 0x80000000,
 		.size = 0x20000000,
 		.width = 32,
 	},
 	.dram_ch[1] = {
-		.base = 0xa0000000,
 		.size = 0x20000000,
 		.width = 32,
 	},
@@ -73,14 +64,11 @@ static const struct uniphier_board_data uniphier_pro4_data = {
 /* 2GB RAM board */
 static const struct uniphier_board_data uniphier_pro4_2g_data = {
 	.dram_freq = 1600,
-	.dram_nr_ch = 2,
 	.dram_ch[0] = {
-		.base = 0x80000000,
 		.size = 0x40000000,
 		.width = 32,
 	},
 	.dram_ch[1] = {
-		.base = 0xc0000000,
 		.size = 0x40000000,
 		.width = 32,
 	},
@@ -90,14 +78,11 @@ static const struct uniphier_board_data uniphier_pro4_2g_data = {
 #if defined(CONFIG_ARCH_UNIPHIER_SLD8)
 static const struct uniphier_board_data uniphier_sld8_data = {
 	.dram_freq = 1333,
-	.dram_nr_ch = 2,
 	.dram_ch[0] = {
-		.base = 0x80000000,
 		.size = 0x10000000,
 		.width = 16,
 	},
 	.dram_ch[1] = {
-		.base = 0x90000000,
 		.size = 0x10000000,
 		.width = 16,
 	},
@@ -108,14 +93,11 @@ static const struct uniphier_board_data uniphier_sld8_data = {
 #if defined(CONFIG_ARCH_UNIPHIER_PRO5)
 static const struct uniphier_board_data uniphier_pro5_data = {
 	.dram_freq = 1866,
-	.dram_nr_ch = 2,
 	.dram_ch[0] = {
-		.base = 0x80000000,
 		.size = 0x20000000,
 		.width = 32,
 	},
 	.dram_ch[1] = {
-		.base = 0xa0000000,
 		.size = 0x20000000,
 		.width = 32,
 	},
@@ -125,19 +107,15 @@ static const struct uniphier_board_data uniphier_pro5_data = {
 #if defined(CONFIG_ARCH_UNIPHIER_PXS2)
 static const struct uniphier_board_data uniphier_pxs2_data = {
 	.dram_freq = 2133,
-	.dram_nr_ch = 3,
 	.dram_ch[0] = {
-		.base = 0x80000000,
 		.size = 0x40000000,
 		.width = 32,
 	},
 	.dram_ch[1] = {
-		.base = 0xc0000000,
 		.size = 0x20000000,
 		.width = 32,
 	},
 	.dram_ch[2] = {
-		.base = 0xe0000000,
 		.size = 0x20000000,
 		.width = 16,
 	},
@@ -147,19 +125,15 @@ static const struct uniphier_board_data uniphier_pxs2_data = {
 #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
 static const struct uniphier_board_data uniphier_ld6b_data = {
 	.dram_freq = 1866,
-	.dram_nr_ch = 3,
 	.dram_ch[0] = {
-		.base = 0x80000000,
 		.size = 0x40000000,
 		.width = 32,
 	},
 	.dram_ch[1] = {
-		.base = 0xc0000000,
 		.size = 0x20000000,
 		.width = 32,
 	},
 	.dram_ch[2] = {
-		.base = 0xe0000000,
 		.size = 0x20000000,
 		.width = 16,
 	},
@@ -169,14 +143,11 @@ static const struct uniphier_board_data uniphier_ld6b_data = {
 #if defined(CONFIG_ARCH_UNIPHIER_LD11)
 static const struct uniphier_board_data uniphier_ld11_data = {
 	.dram_freq = 1600,
-	.dram_nr_ch = 2,
 	.dram_ch[0] = {
-		.base = 0x80000000,
 		.size = 0x20000000,
 		.width = 16,
 	},
 	.dram_ch[1] = {
-		.base = 0xa0000000,
 		.size = 0x20000000,
 		.width = 16,
 	},
@@ -186,19 +157,15 @@ static const struct uniphier_board_data uniphier_ld11_data = {
 #if defined(CONFIG_ARCH_UNIPHIER_LD20)
 static const struct uniphier_board_data uniphier_ld20_ref_data = {
 	.dram_freq = 1866,
-	.dram_nr_ch = 3,
 	.dram_ch[0] = {
-		.base = 0x80000000,
 		.size = 0x40000000,
 		.width = 32,
 	},
 	.dram_ch[1] = {
-		.base = 0xc0000000,
 		.size = 0x40000000,
 		.width = 32,
 	},
 	.dram_ch[2] = {
-		.base = 0x100000000UL,
 		.size = 0x40000000,
 		.width = 32,
 	},
@@ -207,19 +174,15 @@ static const struct uniphier_board_data uniphier_ld20_ref_data = {
 
 static const struct uniphier_board_data uniphier_ld20_data = {
 	.dram_freq = 1866,
-	.dram_nr_ch = 3,
 	.dram_ch[0] = {
-		.base = 0x80000000,
 		.size = 0x40000000,
 		.width = 32,
 	},
 	.dram_ch[1] = {
-		.base = 0xc0000000,
 		.size = 0x40000000,
 		.width = 32,
 	},
 	.dram_ch[2] = {
-		.base = 0x100000000UL,
 		.size = 0x40000000,
 		.width = 32,
 	},
@@ -228,14 +191,11 @@ static const struct uniphier_board_data uniphier_ld20_data = {
 
 static const struct uniphier_board_data uniphier_ld21_data = {
 	.dram_freq = 1866,
-	.dram_nr_ch = 2,
 	.dram_ch[0] = {
-		.base = 0x80000000,
 		.size = 0x20000000,
 		.width = 32,
 	},
 	.dram_ch[1] = {
-		.base = 0xc0000000,
 		.size = 0x40000000,
 		.width = 32,
 	},

arch/arm/mach-uniphier/boot-device/Makefile

@@ -0,0 +1,19 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y					+= boot-device.o
+
+obj-$(CONFIG_ARCH_UNIPHIER_SLD3)	+= boot-device-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD4)		+= boot-device-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO4)	+= boot-device-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= boot-device-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= boot-device-pro5.o
+obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= boot-device-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= boot-device-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= boot-device-ld11.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= boot-device-ld11.o
+
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_BOARD_LOAD_IMAGE)	+= spl_board.o
+endif

arch/arm/mach-uniphier/boot-device/boot-device-ld11.c

@@ -8,12 +8,11 @@
 #include <common.h>
 #include <spl.h>
 #include <linux/io.h>
+#include <linux/kernel.h>
 
-#include "../sg-regs.h"
-#include "../soc-info.h"
 #include "boot-device.h"
 
-static struct boot_device_info boot_device_table[] = {
+const struct uniphier_boot_device uniphier_ld11_boot_device_table[] = {
 	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 128KB, Addr 4)"},
 	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
 	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 128KB, Addr 5)"},
@@ -48,48 +47,23 @@ static struct boot_device_info boot_device_table[] = {
 	{BOOT_DEVICE_NOR,  "NOR  (XECS1)"},
 };
 
-static int get_boot_mode_sel(void)
+const unsigned uniphier_ld11_boot_device_count =
+				ARRAY_SIZE(uniphier_ld11_boot_device_table);
+
+int uniphier_ld11_boot_device_is_usb(u32 pinmon)
 {
-	return (readl(SG_PINMON0) >> 1) & 0x1f;
+	return !!(~pinmon & 0x00000080);
 }
 
-u32 uniphier_ld20_boot_device(void)
+int uniphier_ld20_boot_device_is_usb(u32 pinmon)
 {
-	int boot_mode;
-	u32 usb_boot_mask;
-
-	switch (uniphier_get_soc_id()) {
-#if defined(CONFIG_ARCH_UNIPHIER_LD11)
-	case UNIPHIER_LD11_ID:
-		usb_boot_mask = 0x00000080;
-		break;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD20)
-	case UNIPHIER_LD20_ID:
-		usb_boot_mask = 0x00000780;
-		break;
-#endif
-	default:
-		BUG();
-	}
-
-	if (~readl(SG_PINMON0) & usb_boot_mask)
-		return BOOT_DEVICE_USB;
-
-	boot_mode = get_boot_mode_sel();
-
-	return boot_device_table[boot_mode].type;
+	return !!(~pinmon & 0x00000780);
 }
 
-void uniphier_ld20_boot_mode_show(void)
+unsigned int uniphier_ld11_boot_device_fixup(unsigned int mode)
 {
-	int mode_sel, i;
+	if (mode == BOOT_DEVICE_MMC1 || mode == BOOT_DEVICE_USB)
+		mode = BOOT_DEVICE_BOARD;
 
-	mode_sel = get_boot_mode_sel();
-
-	puts("Boot Mode Pin:\n");
-
-	for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
-		printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
-		       boot_device_table[i].info);
+	return mode;
 }

arch/arm/mach-uniphier/boot-device/boot-device-ld4.c

@@ -1,5 +1,7 @@
 /*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014      Panasonic Corporation
+ * Copyright (C) 2015-2017 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -7,11 +9,11 @@
 #include <common.h>
 #include <spl.h>
 #include <linux/io.h>
+#include <linux/kernel.h>
 
-#include "../sg-regs.h"
 #include "boot-device.h"
 
-struct boot_device_info boot_device_table[] = {
+const struct uniphier_boot_device uniphier_ld4_boot_device_table[] = {
 	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 128KB, Addr 4)"},
 	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 128KB, Addr 5)"},
 	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
@@ -46,29 +48,5 @@ struct boot_device_info boot_device_table[] = {
 	{BOOT_DEVICE_NOR,  "NOR  (XECS0)"},
 };
 
-static int get_boot_mode_sel(void)
-{
-	return (readl(SG_PINMON0) >> 1) & 0x1f;
-}
-
-u32 uniphier_ld4_boot_device(void)
-{
-	int boot_mode;
-
-	boot_mode = get_boot_mode_sel();
-
-	return boot_device_table[boot_mode].type;
-}
-
-void uniphier_ld4_boot_mode_show(void)
-{
-	int mode_sel, i;
-
-	mode_sel = get_boot_mode_sel();
-
-	puts("Boot Mode Pin:\n");
-
-	for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
-		printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
-		       boot_device_table[i].info);
-}
+const unsigned uniphier_ld4_boot_device_count =
+				ARRAY_SIZE(uniphier_ld4_boot_device_table);

arch/arm/mach-uniphier/boot-device/boot-device-pro5.c

@@ -1,5 +1,6 @@
 /*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2017 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -7,11 +8,11 @@
 #include <common.h>
 #include <spl.h>
 #include <linux/io.h>
+#include <linux/kernel.h>
 
-#include "../sg-regs.h"
 #include "boot-device.h"
 
-static struct boot_device_info boot_device_table[] = {
+const struct uniphier_boot_device uniphier_pro5_boot_device_table[] = {
 	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, EraseSize 128KB, Addr 5)"},
 	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
 	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, EraseSize 256KB, Addr 5)"},
@@ -44,32 +45,7 @@ static struct boot_device_info boot_device_table[] = {
 	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
 	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 256KB, Addr 5)"},
 	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
-	{ /* sentinel */ }
 };
 
-static int get_boot_mode_sel(void)
-{
-	return (readl(SG_PINMON0) >> 1) & 0x1f;
-}
-
-u32 uniphier_pro5_boot_device(void)
-{
-	int boot_mode;
-
-	boot_mode = get_boot_mode_sel();
-
-	return boot_device_table[boot_mode].type;
-}
-
-void uniphier_pro5_boot_mode_show(void)
-{
-	int mode_sel, i;
-
-	mode_sel = get_boot_mode_sel();
-
-	puts("Boot Mode Pin:\n");
-
-	for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
-		printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
-		       boot_device_table[i].info);
-}
+const unsigned uniphier_pro5_boot_device_count =
+				ARRAY_SIZE(uniphier_pro5_boot_device_table);

arch/arm/mach-uniphier/boot-device/boot-device-pxs2.c

@@ -1,5 +1,6 @@
 /*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2017 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -7,11 +8,11 @@
 #include <common.h>
 #include <spl.h>
 #include <linux/io.h>
+#include <linux/kernel.h>
 
-#include "../sg-regs.h"
 #include "boot-device.h"
 
-static struct boot_device_info boot_device_table[] = {
+const struct uniphier_boot_device uniphier_pxs2_boot_device_table[] = {
 	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 128KB, Addr 4)"},
 	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 128KB, Addr 5)"},
 	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
@@ -46,32 +47,18 @@ static struct boot_device_info boot_device_table[] = {
 	{BOOT_DEVICE_NONE, "Reserved"},
 };
 
-static int get_boot_mode_sel(void)
+const unsigned uniphier_pxs2_boot_device_count =
+				ARRAY_SIZE(uniphier_pxs2_boot_device_table);
+
+int uniphier_pxs2_boot_device_is_usb(u32 pinmon)
 {
-	return (readl(SG_PINMON0) >> 1) & 0x1f;
+	return !!(pinmon & 0x00000040);
 }
 
-u32 uniphier_pxs2_boot_device(void)
+unsigned int uniphier_pxs2_boot_device_fixup(unsigned int mode)
 {
-	int boot_mode;
+	if (mode == BOOT_DEVICE_USB)
+		return BOOT_DEVICE_NOR;
 
-	if (readl(SG_PINMON0) & BIT(6))
-		return BOOT_DEVICE_USB;
-
-	boot_mode = get_boot_mode_sel();
-
-	return boot_device_table[boot_mode].type;
-}
-
-void uniphier_pxs2_boot_mode_show(void)
-{
-	int mode_sel, i;
-
-	mode_sel = get_boot_mode_sel();
-
-	puts("Boot Mode Pin:\n");
-
-	for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
-		printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
-		       boot_device_table[i].info);
+	return mode;
 }

arch/arm/mach-uniphier/boot-device/boot-device-sld3.c

@@ -1,5 +1,7 @@
 /*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014      Panasonic Corporation
+ * Copyright (C) 2015-2017 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -7,11 +9,11 @@
 #include <common.h>
 #include <spl.h>
 #include <linux/io.h>
+#include <linux/kernel.h>
 
-#include "../sg-regs.h"
 #include "boot-device.h"
 
-static struct boot_device_info boot_device_table[] = {
+const struct uniphier_boot_device uniphier_sld3_boot_device_table[] = {
 	{BOOT_DEVICE_NOR,  "NOR  (XECS0)"},
 	{BOOT_DEVICE_NONE, "External Master"},
 	{BOOT_DEVICE_NONE, "Reserved"},
@@ -78,29 +80,5 @@ static struct boot_device_info boot_device_table[] = {
 	{BOOT_DEVICE_NONE, "Reserved"},
 };
 
-static int get_boot_mode_sel(void)
-{
-	return readl(SG_PINMON0) & 0x3f;
-}
-
-u32 uniphier_sld3_boot_device(void)
-{
-	int boot_mode;
-
-	boot_mode = get_boot_mode_sel();
-
-	return boot_device_table[boot_mode].type;
-}
-
-void uniphier_sld3_boot_mode_show(void)
-{
-	int mode_sel, i;
-
-	mode_sel = get_boot_mode_sel();
-
-	puts("Boot Mode Pin:\n");
-
-	for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
-		printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
-		       boot_device_table[i].info);
-}
+const unsigned uniphier_sld3_boot_device_count =
+				ARRAY_SIZE(uniphier_sld3_boot_device_table);

arch/arm/mach-uniphier/boot-device/boot-device.c

@@ -0,0 +1,206 @@
+/*
+ * Copyright (C) 2015-2017 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/log2.h>
+
+#include "../init.h"
+#include "../sbc/sbc-regs.h"
+#include "../sg-regs.h"
+#include "../soc-info.h"
+#include "boot-device.h"
+
+struct uniphier_boot_device_info {
+	unsigned int soc_id;
+	unsigned int boot_device_sel_shift;
+	const struct uniphier_boot_device *boot_device_table;
+	const unsigned int *boot_device_count;
+	int (*boot_device_is_usb)(u32 pinmon);
+	unsigned int (*boot_device_fixup)(unsigned int mode);
+};
+
+static const struct uniphier_boot_device_info uniphier_boot_device_info[] = {
+#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
+	{
+		.soc_id = UNIPHIER_SLD3_ID,
+		.boot_device_sel_shift = 0,
+		.boot_device_table = uniphier_sld3_boot_device_table,
+		.boot_device_count = &uniphier_sld3_boot_device_count,
+	},
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD4)
+	{
+		.soc_id = UNIPHIER_LD4_ID,
+		.boot_device_sel_shift = 1,
+		.boot_device_table = uniphier_ld4_boot_device_table,
+		.boot_device_count = &uniphier_ld4_boot_device_count,
+	},
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
+	{
+		.soc_id = UNIPHIER_PRO4_ID,
+		.boot_device_sel_shift = 1,
+		.boot_device_table = uniphier_ld4_boot_device_table,
+		.boot_device_count = &uniphier_ld4_boot_device_count,
+	},
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
+	{
+		.soc_id = UNIPHIER_SLD8_ID,
+		.boot_device_sel_shift = 1,
+		.boot_device_table = uniphier_ld4_boot_device_table,
+		.boot_device_count = &uniphier_ld4_boot_device_count,
+	},
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
+	{
+		.soc_id = UNIPHIER_PRO5_ID,
+		.boot_device_sel_shift = 1,
+		.boot_device_table = uniphier_pro5_boot_device_table,
+		.boot_device_count = &uniphier_pro5_boot_device_count,
+	},
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
+	{
+		.soc_id = UNIPHIER_PXS2_ID,
+		.boot_device_sel_shift = 1,
+		.boot_device_table = uniphier_pxs2_boot_device_table,
+		.boot_device_count = &uniphier_pxs2_boot_device_count,
+		.boot_device_is_usb = uniphier_pxs2_boot_device_is_usb,
+		.boot_device_fixup = uniphier_pxs2_boot_device_fixup,
+	},
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
+	{
+		.soc_id = UNIPHIER_LD6B_ID,
+		.boot_device_sel_shift = 1,
+		.boot_device_table = uniphier_pxs2_boot_device_table,
+		.boot_device_count = &uniphier_pxs2_boot_device_count,
+		.boot_device_is_usb = uniphier_pxs2_boot_device_is_usb,
+		.boot_device_fixup = uniphier_pxs2_boot_device_fixup,
+	},
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+	{
+		.soc_id = UNIPHIER_LD11_ID,
+		.boot_device_sel_shift = 1,
+		.boot_device_table = uniphier_ld11_boot_device_table,
+		.boot_device_count = &uniphier_ld11_boot_device_count,
+		.boot_device_is_usb = uniphier_ld11_boot_device_is_usb,
+		.boot_device_fixup = uniphier_ld11_boot_device_fixup,
+	},
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+	{
+		.soc_id = UNIPHIER_LD20_ID,
+		.boot_device_sel_shift = 1,
+		.boot_device_table = uniphier_ld11_boot_device_table,
+		.boot_device_count = &uniphier_ld11_boot_device_count,
+		.boot_device_is_usb = uniphier_ld20_boot_device_is_usb,
+		.boot_device_fixup = uniphier_ld11_boot_device_fixup,
+	},
+#endif
+};
+UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_boot_device_info,
+			     uniphier_boot_device_info)
+
+static unsigned int __uniphier_boot_device_raw(
+				const struct uniphier_boot_device_info *info)
+{
+	u32 pinmon;
+	unsigned int boot_sel;
+
+	if (boot_is_swapped())
+		return BOOT_DEVICE_NOR;
+
+	pinmon = readl(SG_PINMON0);
+
+	if (info->boot_device_is_usb && info->boot_device_is_usb(pinmon))
+		return BOOT_DEVICE_USB;
+
+	boot_sel = pinmon >> info->boot_device_sel_shift;
+
+	BUG_ON(!is_power_of_2(*info->boot_device_count));
+	boot_sel &= *info->boot_device_count - 1;
+
+	return info->boot_device_table[boot_sel].boot_device;
+}
+
+unsigned int uniphier_boot_device_raw(void)
+{
+	const struct uniphier_boot_device_info *info;
+
+	info = uniphier_get_boot_device_info();
+	if (!info) {
+		pr_err("unsupported SoC\n");
+		return BOOT_DEVICE_NONE;
+	}
+
+	return __uniphier_boot_device_raw(info);
+}
+
+u32 spl_boot_device(void)
+{
+	const struct uniphier_boot_device_info *info;
+	u32 raw_mode;
+
+	info = uniphier_get_boot_device_info();
+	if (!info) {
+		pr_err("unsupported SoC\n");
+		return BOOT_DEVICE_NONE;
+	}
+
+	raw_mode = __uniphier_boot_device_raw(info);
+
+	return info->boot_device_fixup ?
+				info->boot_device_fixup(raw_mode) : raw_mode;
+}
+
+#ifndef CONFIG_SPL_BUILD
+
+static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	const struct uniphier_boot_device_info *info;
+	u32 pinmon;
+	unsigned int boot_device_count, boot_sel;
+	int i;
+
+	info = uniphier_get_boot_device_info();
+	if (!info) {
+		pr_err("unsupported SoC\n");
+		return CMD_RET_FAILURE;
+	}
+
+	printf("Boot Swap: %s\n\n", boot_is_swapped() ? "ON" : "OFF");
+
+	pinmon = readl(SG_PINMON0);
+
+	if (info->boot_device_is_usb)
+		printf("USB Boot: %s\n\n",
+		       info->boot_device_is_usb(pinmon) ? "ON" : "OFF");
+
+	boot_device_count = *info->boot_device_count;
+
+	boot_sel = pinmon >> info->boot_device_sel_shift;
+	boot_sel &= boot_device_count - 1;
+
+	printf("Boot Mode Sel:\n");
+	for (i = 0; i < boot_device_count; i++)
+		printf(" %c %02x %s\n", i == boot_sel ? '*' : ' ', i,
+		       info->boot_device_table[i].desc);
+
+	return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+	pinmon,	1,	1,	do_pinmon,
+	"pin monitor",
+	""
+);
+
+#endif /* !CONFIG_SPL_BUILD */

arch/arm/mach-uniphier/boot-device/boot-device.h

@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2017 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _UNIPHIER_BOOT_DEVICE_H_
+#define _UNIPHIER_BOOT_DEVICE_H_
+
+struct uniphier_boot_device {
+	unsigned int boot_device;
+	const char *desc;
+};
+
+extern const struct uniphier_boot_device uniphier_sld3_boot_device_table[];
+extern const struct uniphier_boot_device uniphier_ld4_boot_device_table[];
+extern const struct uniphier_boot_device uniphier_pro5_boot_device_table[];
+extern const struct uniphier_boot_device uniphier_pxs2_boot_device_table[];
+extern const struct uniphier_boot_device uniphier_ld11_boot_device_table[];
+
+extern const unsigned int uniphier_sld3_boot_device_count;
+extern const unsigned int uniphier_ld4_boot_device_count;
+extern const unsigned int uniphier_pro5_boot_device_count;
+extern const unsigned int uniphier_pxs2_boot_device_count;
+extern const unsigned int uniphier_ld11_boot_device_count;
+
+int uniphier_pxs2_boot_device_is_usb(u32 pinmon);
+int uniphier_ld11_boot_device_is_usb(u32 pinmon);
+int uniphier_ld20_boot_device_is_usb(u32 pinmon);
+
+unsigned int uniphier_pxs2_boot_device_fixup(unsigned int mode);
+unsigned int uniphier_ld11_boot_device_fixup(unsigned int mode);
+
+#endif /* _UNIPHIER_BOOT_DEVICE_H_ */

arch/arm/mach-uniphier/boot-device/spl_board.c

@@ -0,0 +1,262 @@
+/*
+ * Copyright (C) 2017 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/bitops.h>
+#include <linux/compat.h>
+#include <linux/io.h>
+#include <asm/processor.h>
+
+#include "../soc-info.h"
+
+#define MMC_CMD_SWITCH			6
+#define MMC_CMD_SELECT_CARD		7
+#define MMC_CMD_SEND_CSD		9
+#define MMC_CMD_READ_MULTIPLE_BLOCK	18
+
+#define EXT_CSD_PART_CONF		179	/* R/W */
+
+#define MMC_RSP_PRESENT BIT(0)
+#define MMC_RSP_136	BIT(1)		/* 136 bit response */
+#define MMC_RSP_CRC	BIT(2)		/* expect valid crc */
+#define MMC_RSP_BUSY	BIT(3)		/* card may send busy */
+#define MMC_RSP_OPCODE	BIT(4)		/* response contains opcode */
+
+#define MMC_RSP_NONE	(0)
+#define MMC_RSP_R1	(MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
+#define MMC_RSP_R1b	(MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | \
+			MMC_RSP_BUSY)
+#define MMC_RSP_R2	(MMC_RSP_PRESENT | MMC_RSP_136 | MMC_RSP_CRC)
+#define MMC_RSP_R3	(MMC_RSP_PRESENT)
+#define MMC_RSP_R4	(MMC_RSP_PRESENT)
+#define MMC_RSP_R5	(MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
+#define MMC_RSP_R6	(MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
+#define MMC_RSP_R7	(MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
+
+#define SDHCI_DMA_ADDRESS	0x00
+#define SDHCI_BLOCK_SIZE	0x04
+#define  SDHCI_MAKE_BLKSZ(dma, blksz) ((((dma) & 0x7) << 12) | ((blksz) & 0xFFF))
+#define SDHCI_BLOCK_COUNT	0x06
+#define SDHCI_ARGUMENT		0x08
+#define SDHCI_TRANSFER_MODE	0x0C
+#define  SDHCI_TRNS_DMA		BIT(0)
+#define  SDHCI_TRNS_BLK_CNT_EN	BIT(1)
+#define  SDHCI_TRNS_ACMD12	BIT(2)
+#define  SDHCI_TRNS_READ	BIT(4)
+#define  SDHCI_TRNS_MULTI	BIT(5)
+#define SDHCI_COMMAND		0x0E
+#define  SDHCI_CMD_RESP_MASK	0x03
+#define  SDHCI_CMD_CRC		0x08
+#define  SDHCI_CMD_INDEX	0x10
+#define  SDHCI_CMD_DATA		0x20
+#define  SDHCI_CMD_ABORTCMD	0xC0
+#define  SDHCI_CMD_RESP_NONE	0x00
+#define  SDHCI_CMD_RESP_LONG	0x01
+#define  SDHCI_CMD_RESP_SHORT	0x02
+#define  SDHCI_CMD_RESP_SHORT_BUSY 0x03
+#define  SDHCI_MAKE_CMD(c, f) ((((c) & 0xff) << 8) | ((f) & 0xff))
+#define SDHCI_RESPONSE		0x10
+#define SDHCI_HOST_CONTROL	0x28
+#define  SDHCI_CTRL_DMA_MASK	0x18
+#define   SDHCI_CTRL_SDMA	0x00
+#define SDHCI_BLOCK_GAP_CONTROL	0x2A
+#define SDHCI_SOFTWARE_RESET	0x2F
+#define  SDHCI_RESET_CMD	0x02
+#define  SDHCI_RESET_DATA	0x04
+#define SDHCI_INT_STATUS	0x30
+#define  SDHCI_INT_RESPONSE	BIT(0)
+#define  SDHCI_INT_DATA_END	BIT(1)
+#define  SDHCI_INT_ERROR	BIT(15)
+#define SDHCI_SIGNAL_ENABLE	0x38
+
+/* RCA assigned by Boot ROM */
+#define UNIPHIER_EMMC_RCA	0x1000
+
+struct uniphier_mmc_cmd {
+	unsigned int cmdidx;
+	unsigned int resp_type;
+	unsigned int cmdarg;
+	unsigned int is_data;
+};
+
+static int uniphier_emmc_send_cmd(void __iomem *host_base,
+				  struct uniphier_mmc_cmd *cmd)
+{
+	u32 mode = 0;
+	u32 mask = SDHCI_INT_RESPONSE;
+	u32 stat, flags;
+
+	writel(U32_MAX, host_base + SDHCI_INT_STATUS);
+	writel(0, host_base + SDHCI_SIGNAL_ENABLE);
+	writel(cmd->cmdarg, host_base + SDHCI_ARGUMENT);
+
+	if (cmd->is_data)
+		mode = SDHCI_TRNS_DMA | SDHCI_TRNS_BLK_CNT_EN |
+			SDHCI_TRNS_ACMD12 | SDHCI_TRNS_READ |
+			SDHCI_TRNS_MULTI;
+
+	writew(mode, host_base + SDHCI_TRANSFER_MODE);
+
+	if (!(cmd->resp_type & MMC_RSP_PRESENT))
+		flags = SDHCI_CMD_RESP_NONE;
+	else if (cmd->resp_type & MMC_RSP_136)
+		flags = SDHCI_CMD_RESP_LONG;
+	else if (cmd->resp_type & MMC_RSP_BUSY)
+		flags = SDHCI_CMD_RESP_SHORT_BUSY;
+	else
+		flags = SDHCI_CMD_RESP_SHORT;
+
+	if (cmd->resp_type & MMC_RSP_CRC)
+		flags |= SDHCI_CMD_CRC;
+	if (cmd->resp_type & MMC_RSP_OPCODE)
+		flags |= SDHCI_CMD_INDEX;
+	if (cmd->is_data)
+		flags |= SDHCI_CMD_DATA;
+
+	if (cmd->resp_type & MMC_RSP_BUSY || cmd->is_data)
+		mask |= SDHCI_INT_DATA_END;
+
+	writew(SDHCI_MAKE_CMD(cmd->cmdidx, flags), host_base + SDHCI_COMMAND);
+
+	do {
+		stat = readl(host_base + SDHCI_INT_STATUS);
+		if (stat & SDHCI_INT_ERROR)
+			return -EIO;
+
+	} while ((stat & mask) != mask);
+
+	return 0;
+}
+
+static int uniphier_emmc_switch_part(void __iomem *host_base, int part_num)
+{
+	struct uniphier_mmc_cmd cmd = {};
+
+	cmd.cmdidx = MMC_CMD_SWITCH;
+	cmd.resp_type = MMC_RSP_R1b;
+	cmd.cmdarg = (EXT_CSD_PART_CONF << 16) | (part_num << 8) | (3 << 24);
+
+	return uniphier_emmc_send_cmd(host_base, &cmd);
+}
+
+static int uniphier_emmc_is_over_2gb(void __iomem *host_base)
+{
+	struct uniphier_mmc_cmd cmd = {};
+	u32 csd40, csd72;	/* CSD[71:40], CSD[103:72] */
+	int ret;
+
+	cmd.cmdidx = MMC_CMD_SEND_CSD;
+	cmd.resp_type = MMC_RSP_R2;
+	cmd.cmdarg = UNIPHIER_EMMC_RCA << 16;
+
+	ret = uniphier_emmc_send_cmd(host_base, &cmd);
+	if (ret)
+		return ret;
+
+	csd40 = readl(host_base + SDHCI_RESPONSE + 4);
+	csd72 = readl(host_base + SDHCI_RESPONSE + 8);
+
+	return !(~csd40 & 0xffc00380) && !(~csd72 & 0x3);
+}
+
+static int uniphier_emmc_load_image(void __iomem *host_base, u32 dev_addr,
+				    unsigned long load_addr, u32 block_cnt)
+{
+	struct uniphier_mmc_cmd cmd = {};
+	u8 tmp;
+
+	WARN_ON(load_addr >> 32);
+
+	writel(load_addr, host_base + SDHCI_DMA_ADDRESS);
+	writew(SDHCI_MAKE_BLKSZ(7, 512), host_base + SDHCI_BLOCK_SIZE);
+	writew(block_cnt, host_base + SDHCI_BLOCK_COUNT);
+
+	tmp = readb(host_base + SDHCI_HOST_CONTROL);
+	tmp &= ~SDHCI_CTRL_DMA_MASK;
+	tmp |= SDHCI_CTRL_SDMA;
+	writeb(tmp, host_base + SDHCI_HOST_CONTROL);
+
+	tmp = readb(host_base + SDHCI_BLOCK_GAP_CONTROL);
+	tmp &= ~1;		/* clear Stop At Block Gap Request */
+	writeb(tmp, host_base + SDHCI_BLOCK_GAP_CONTROL);
+
+	cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
+	cmd.resp_type = MMC_RSP_R1;
+	cmd.cmdarg = dev_addr;
+	cmd.is_data = 1;
+
+	return uniphier_emmc_send_cmd(host_base, &cmd);
+}
+
+static int spl_board_load_image(struct spl_image_info *spl_image,
+				struct spl_boot_device *bootdev)
+{
+	u32 dev_addr = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
+	void __iomem *host_base = (void __iomem *)0x5a000200;
+	struct uniphier_mmc_cmd cmd = {};
+	int ret;
+
+	/*
+	 * deselect card before SEND_CSD command.
+	 * Do not check the return code.  It fails, but it is OK.
+	 */
+	cmd.cmdidx = MMC_CMD_SELECT_CARD;
+	cmd.resp_type = MMC_RSP_R1;
+
+	uniphier_emmc_send_cmd(host_base, &cmd); /* CMD7 (arg=0) */
+
+	/* reset CMD Line */
+	writeb(SDHCI_RESET_CMD | SDHCI_RESET_DATA,
+	       host_base + SDHCI_SOFTWARE_RESET);
+	while (readb(host_base + SDHCI_SOFTWARE_RESET))
+		cpu_relax();
+
+	ret = uniphier_emmc_is_over_2gb(host_base);
+	if (ret < 0)
+		return ret;
+	if (ret) {
+		debug("card is block addressing\n");
+	} else {
+		debug("card is byte addressing\n");
+		dev_addr *= 512;
+	}
+
+	cmd.cmdarg = UNIPHIER_EMMC_RCA << 16;
+
+	/* select card again */
+	ret = uniphier_emmc_send_cmd(host_base, &cmd);
+	if (ret)
+		printf("failed to select card\n");
+
+	/* Switch to Boot Partition 1 */
+	ret = uniphier_emmc_switch_part(host_base, 1);
+	if (ret)
+		printf("failed to switch partition\n");
+
+	ret = uniphier_emmc_load_image(host_base, dev_addr,
+				       CONFIG_SYS_TEXT_BASE, 1);
+	if (ret) {
+		printf("failed to load image\n");
+		return ret;
+	}
+
+	ret = spl_parse_image_header(spl_image, (void *)CONFIG_SYS_TEXT_BASE);
+	if (ret)
+		return ret;
+
+	ret = uniphier_emmc_load_image(host_base, dev_addr,
+				       spl_image->load_addr,
+				       spl_image->size / 512);
+	if (ret) {
+		printf("failed to load image\n");
+		return ret;
+	}
+
+	return 0;
+}
+SPL_LOAD_IMAGE_METHOD("eMMC", 0, BOOT_DEVICE_BOARD, spl_board_load_image);

arch/arm/mach-uniphier/boot-mode/Makefile

@@ -1,21 +0,0 @@
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y					+= boot-mode.o
-
-obj-$(CONFIG_ARCH_UNIPHIER_SLD3)	+= boot-mode-sld3.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD4)		+= boot-mode-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PRO4)	+= boot-mode-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= boot-mode-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= boot-mode-pro5.o
-obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= boot-mode-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= boot-mode-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= boot-mode-ld20.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= boot-mode-ld20.o
-
-ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_SPL_BOARD_LOAD_IMAGE)	+= spl_board.o
-else
-obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
-endif

arch/arm/mach-uniphier/boot-mode/boot-device.h

@@ -1,29 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ASM_BOOT_DEVICE_H_
-#define _ASM_BOOT_DEVICE_H_
-
-struct boot_device_info {
-	u32 type;
-	char *info;
-};
-
-u32 uniphier_sld3_boot_device(void);
-u32 uniphier_ld4_boot_device(void);
-u32 uniphier_pro5_boot_device(void);
-u32 uniphier_pxs2_boot_device(void);
-u32 uniphier_ld20_boot_device(void);
-
-void uniphier_sld3_boot_mode_show(void);
-void uniphier_ld4_boot_mode_show(void);
-void uniphier_pro5_boot_mode_show(void);
-void uniphier_pxs2_boot_mode_show(void);
-void uniphier_ld20_boot_mode_show(void);
-
-u32 spl_boot_device_raw(void);
-
-#endif /* _ASM_BOOT_DEVICE_H_ */

arch/arm/mach-uniphier/boot-mode/boot-mode.c

@@ -1,140 +0,0 @@
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mmc.h>
-#include <spl.h>
-#include <linux/errno.h>
-
-#include "../sbc/sbc-regs.h"
-#include "../soc-info.h"
-#include "boot-device.h"
-
-u32 spl_boot_device_raw(void)
-{
-	if (boot_is_swapped())
-		return BOOT_DEVICE_NOR;
-
-	switch (uniphier_get_soc_id()) {
-#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
-	case UNIPHIER_SLD3_ID:
-		return uniphier_sld3_boot_device();
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD4) || defined(CONFIG_ARCH_UNIPHIER_PRO4) || \
-	defined(CONFIG_ARCH_UNIPHIER_SLD8)
-	case UNIPHIER_LD4_ID:
-	case UNIPHIER_PRO4_ID:
-	case UNIPHIER_SLD8_ID:
-		return uniphier_ld4_boot_device();
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
-	case UNIPHIER_PRO5_ID:
-		return uniphier_pro5_boot_device();
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B)
-	case UNIPHIER_PXS2_ID:
-	case UNIPHIER_LD6B_ID:
-		return uniphier_pxs2_boot_device();
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
-	case UNIPHIER_LD11_ID:
-	case UNIPHIER_LD20_ID:
-		return uniphier_ld20_boot_device();
-#endif
-	default:
-		return BOOT_DEVICE_NONE;
-	}
-}
-
-u32 spl_boot_device(void)
-{
-	u32 mode;
-
-	mode = spl_boot_device_raw();
-
-	switch (uniphier_get_soc_id()) {
-#if defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B)
-	case UNIPHIER_PXS2_ID:
-	case UNIPHIER_LD6B_ID:
-		if (mode == BOOT_DEVICE_USB)
-			mode = BOOT_DEVICE_NOR;
-		break;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
-	case UNIPHIER_LD11_ID:
-	case UNIPHIER_LD20_ID:
-		if (mode == BOOT_DEVICE_MMC1 || mode == BOOT_DEVICE_USB)
-			mode = BOOT_DEVICE_BOARD;
-		break;
-#endif
-	default:
-		break;
-	}
-
-	return mode;
-}
-
-u32 spl_boot_mode(const u32 boot_device)
-{
-	struct mmc *mmc;
-
-	/*
-	 * work around a bug in the Boot ROM of PH1-sLD3, LD4, Pro4, and sLD8:
-	 *
-	 * The boot ROM in these SoCs breaks the PARTITION_CONFIG [179] of
-	 * Extended CSD register; when switching to the Boot Partition 1, the
-	 * Boot ROM should issue the SWITCH command (CMD6) with Set Bits for
-	 * the Access Bits, but in fact it uses Write Byte for the Access Bits.
-	 * As a result, the BOOT_PARTITION_ENABLE field of the PARTITION_CONFIG
-	 * is lost.  This bug was fixed for PH1-Pro5 and later SoCs.
-	 *
-	 * Fixup mmc->part_config here because it is used to determine the
-	 * partition which the U-Boot image is read from.
-	 */
-	mmc = find_mmc_device(0);
-	mmc->part_config &= ~EXT_CSD_BOOT_PART_NUM(PART_ACCESS_MASK);
-	mmc->part_config |= EXT_CSD_BOOT_PARTITION_ENABLE;
-
-	return MMCSD_MODE_EMMCBOOT;
-}
-
-#if defined(CONFIG_DM_MMC) && !defined(CONFIG_SPL_BUILD)
-static int find_first_mmc_device(void)
-{
-	struct mmc *mmc;
-	int i;
-
-	for (i = 0; (mmc = find_mmc_device(i)); i++) {
-		if (!mmc_init(mmc) && IS_MMC(mmc))
-			return i;
-	}
-
-	return -ENODEV;
-}
-
-int mmc_get_env_dev(void)
-{
-	return find_first_mmc_device();
-}
-
-static int do_mmcsetn(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int dev;
-
-	dev = find_first_mmc_device();
-	if (dev < 0)
-		return CMD_RET_FAILURE;
-
-	setenv_ulong("mmc_first_dev", dev);
-	return CMD_RET_SUCCESS;
-}
-
-U_BOOT_CMD(
-	   mmcsetn,	1,	1,	do_mmcsetn,
-	"Set the first MMC (not SD) dev number to \"mmc_first_dev\" environment",
-	""
-);
-#endif

arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c

@@ -1,59 +0,0 @@
-/*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-
-#include "../sbc/sbc-regs.h"
-#include "../soc-info.h"
-#include "boot-device.h"
-
-static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	printf("Boot Swap: %s\n\n", boot_is_swapped() ? "ON" : "OFF");
-
-	switch (uniphier_get_soc_id()) {
-#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
-	case UNIPHIER_SLD3_ID:
-		uniphier_sld3_boot_mode_show();
-		break;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD4) || defined(CONFIG_ARCH_UNIPHIER_PRO4) || \
-	defined(CONFIG_ARCH_UNIPHIER_SLD8)
-	case UNIPHIER_LD4_ID:
-	case UNIPHIER_PRO4_ID:
-	case UNIPHIER_SLD8_ID:
-		uniphier_ld4_boot_mode_show();
-		break;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
-	case UNIPHIER_PRO5_ID:
-		uniphier_pro5_boot_mode_show();
-		break;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B)
-	case UNIPHIER_PXS2_ID:
-	case UNIPHIER_LD6B_ID:
-		uniphier_pxs2_boot_mode_show();
-		break;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
-	case UNIPHIER_LD11_ID:
-	case UNIPHIER_LD20_ID:
-		uniphier_ld20_boot_mode_show();
-		break;
-#endif
-	default:
-		break;
-	}
-
-	return 0;
-}
-
-U_BOOT_CMD(
-	pinmon,	1,	1,	do_pinmon,
-	"pin monitor",
-	""
-);

arch/arm/mach-uniphier/boot-mode/spl_board.c

@@ -1,125 +0,0 @@
-/*
- * Copyright (C) 2016 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <linux/io.h>
-#include <asm/processor.h>
-
-#include "../soc-info.h"
-
-struct uniphier_romfunc_table {
-	void *mmc_send_cmd;
-	void *mmc_card_blockaddr;
-	void *mmc_switch_part;
-	void *mmc_load_image;
-};
-
-static const struct uniphier_romfunc_table uniphier_ld11_romfunc_table = {
-	.mmc_send_cmd = (void *)0x20d8,
-	.mmc_card_blockaddr = (void *)0x1b68,
-	.mmc_switch_part = (void *)0x1c38,
-	.mmc_load_image = (void *)0x2e48,
-};
-
-static const struct uniphier_romfunc_table uniphier_ld20_romfunc_table = {
-	.mmc_send_cmd = (void *)0x2130,
-	.mmc_card_blockaddr = (void *)0x1ba0,
-	.mmc_switch_part = (void *)0x1c70,
-	.mmc_load_image = (void *)0x2ef0,
-};
-
-int uniphier_rom_get_mmc_funcptr(int (**send_cmd)(u32, u32),
-				 int (**card_blockaddr)(u32),
-				 int (**switch_part)(int),
-				 int (**load_image)(u32, uintptr_t, u32))
-{
-	const struct uniphier_romfunc_table *table;
-
-	switch (uniphier_get_soc_id()) {
-	case UNIPHIER_LD11_ID:
-		table = &uniphier_ld11_romfunc_table;
-		break;
-	case UNIPHIER_LD20_ID:
-		table = &uniphier_ld20_romfunc_table;
-		break;
-	default:
-		printf("unsupported SoC\n");
-		return -EINVAL;
-	}
-
-	*send_cmd = table->mmc_send_cmd;
-	*card_blockaddr = table->mmc_card_blockaddr;
-	*switch_part = table->mmc_switch_part;
-	*load_image = table->mmc_load_image;
-
-	return 0;
-}
-
-static int spl_board_load_image(struct spl_image_info *spl_image,
-				struct spl_boot_device *bootdev)
-{
-	int (*send_cmd)(u32 cmd, u32 arg);
-	int (*card_blockaddr)(u32 rca);
-	int (*switch_part)(int part);
-	int (*load_image)(u32 dev_addr, uintptr_t load_addr, u32 block_cnt);
-	u32 dev_addr = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
-	const u32 rca = 0x1000; /* RCA assigned by Boot ROM */
-	int ret;
-
-	ret = uniphier_rom_get_mmc_funcptr(&send_cmd, &card_blockaddr,
-					   &switch_part, &load_image);
-	if (ret)
-		return ret;
-
-	/*
-	 * deselect card before SEND_CSD command.
-	 * Do not check the return code.  It fails, but it is OK.
-	 */
-	(*send_cmd)(0x071a0000, 0); /* CMD7 (arg=0) */
-
-	/* reset CMD Line */
-	writeb(0x6, 0x5a00022f);
-	while (readb(0x5a00022f))
-		cpu_relax();
-
-	ret = (*card_blockaddr)(rca);
-	if (ret) {
-		debug("card is block addressing\n");
-	} else {
-		debug("card is byte addressing\n");
-		dev_addr *= 512;
-	}
-
-	ret = (*send_cmd)(0x071a0000, rca << 16); /* CMD7: select card again */
-	if (ret)
-		printf("failed to select card\n");
-
-	ret = (*switch_part)(1); /* Switch to Boot Partition 1 */
-	if (ret)
-		printf("failed to switch partition\n");
-
-	ret = (*load_image)(dev_addr, CONFIG_SYS_TEXT_BASE, 1);
-	if (ret) {
-		printf("failed to load image\n");
-		return ret;
-	}
-
-	ret = spl_parse_image_header(spl_image, (void *)CONFIG_SYS_TEXT_BASE);
-	if (ret)
-		return ret;
-
-	ret = (*load_image)(dev_addr, spl_image->load_addr,
-			    spl_image->size / 512);
-	if (ret) {
-		printf("failed to load image\n");
-		return ret;
-	}
-
-	return 0;
-}
-SPL_LOAD_IMAGE_METHOD("eMMC", 0, BOOT_DEVICE_BOARD, spl_board_load_image);

arch/arm/mach-uniphier/clk/Makefile

@@ -24,7 +24,7 @@ obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= clk-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= clk-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= clk-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= clk-ld11.o pll-ld11.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= pll-ld20.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= clk-ld20.o pll-ld20.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS3)	+= pll-pxs3.o
 
 endif

arch/arm/mach-uniphier/clk/clk-ld11.c

@@ -9,16 +9,17 @@
 #include <linux/bitops.h>
 #include <linux/io.h>
 
-#include "../boot-mode/boot-device.h"
 #include "../init.h"
 #include "../sc64-regs.h"
 #include "../sg-regs.h"
 
+#define SDCTRL_EMMC_HW_RESET	0x59810280
+
 void uniphier_ld11_clk_init(void)
 {
 	/* if booted from a device other than USB, without stand-by MPU */
 	if ((readl(SG_PINMON0) & BIT(27)) &&
-	    spl_boot_device_raw() != BOOT_DEVICE_USB) {
+	    uniphier_boot_device_raw() != BOOT_DEVICE_USB) {
 		writel(1, SG_ETPHYPSHUT);
 		writel(1, SG_ETPHYCNT);
 
@@ -29,6 +30,9 @@ void uniphier_ld11_clk_init(void)
 		writel(7, SG_ETPHYCNT);
 	}
 
+	/* TODO: use "mmc-pwrseq-emmc" */
+	writel(1, SDCTRL_EMMC_HW_RESET);
+
 #ifdef CONFIG_USB_EHCI
 	{
 		/* FIXME: the current clk driver can not handle parents */

arch/arm/mach-uniphier/clk/clk-ld20.c

@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2017 Socionext Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+
+#define SDCTRL_EMMC_HW_RESET	0x59810280
+
+void uniphier_ld20_clk_init(void)
+{
+	/* TODO: use "mmc-pwrseq-emmc" */
+	writel(1, SDCTRL_EMMC_HW_RESET);
+}

arch/arm/mach-uniphier/clk/pll-base-ld20.c

@@ -18,6 +18,8 @@
 #define SC_PLLCTRL_SSC_EN		BIT(31)
 #define SC_PLLCTRL2_NRSTDS		BIT(28)
 #define SC_PLLCTRL2_SSC_JK_MASK		GENMASK(26, 0)
+#define SC_PLLCTRL3_REGI_SHIFT		16
+#define SC_PLLCTRL3_REGI_MASK		GENMASK(19, 16)
 
 /* PLL type: VPLL27 */
 #define SC_VPLL27CTRL_WP		BIT(0)
@@ -77,6 +79,25 @@ int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base)
 	return 0;
 }
 
+int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi)
+{
+	void __iomem *base;
+	u32 tmp;
+
+	base = ioremap(reg_base, SZ_16);
+	if (!base)
+		return -ENOMEM;
+
+	tmp = readl(base + 8);	/* SSCPLLCTRL */
+	tmp &= ~SC_PLLCTRL3_REGI_MASK;
+	tmp |= regi << SC_PLLCTRL3_REGI_SHIFT;
+	writel(tmp, base + 8);
+
+	iounmap(base);
+
+	return 0;
+}
+
 int uniphier_ld20_vpll27_init(unsigned long reg_base)
 {
 	void __iomem *base;

arch/arm/mach-uniphier/clk/pll-ld11.c

@@ -18,6 +18,8 @@ void uniphier_ld11_pll_init(void)
 	uniphier_ld20_sscpll_init(SC_MPLLCTRL, 1600, 1, 2);	/* 1500MHz -> 1600MHz */
 	uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
 
+	uniphier_ld20_sscpll_set_regi(SC_MPLLCTRL, 5);
+
 	mdelay(1);
 
 	uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL);

arch/arm/mach-uniphier/clk/pll.h

@@ -15,6 +15,7 @@ void uniphier_ld4_dpll_ssc_en(void);
 int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
 			      unsigned int ssc_rate, unsigned int divn);
 int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base);
+int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi);
 int uniphier_ld20_vpll27_init(unsigned long reg_base);
 int uniphier_ld20_dspll_init(unsigned long reg_base);
 

arch/arm/mach-uniphier/dram/umc-ld11.c

@@ -471,7 +471,7 @@ int uniphier_ld11_umc_init(const struct uniphier_board_data *bd)
 
 	ddrphy_init(phy_base, freq);
 
-	for (ch = 0; ch < bd->dram_nr_ch; ch++) {
+	for (ch = 0; ch < DRAM_CH_NR; ch++) {
 		unsigned long size = bd->dram_ch[ch].size;
 		unsigned int width = bd->dram_ch[ch].width;
 

arch/arm/mach-uniphier/dram/umc-ld20.c

@@ -1,7 +1,7 @@
 /*
  * Copyright (C) 2016-2017 Socionext Inc.
  *
- * based on commit e732175d0b0dbc2a3855cb8ac791c538666b6fd4 of Diag
+ * based on commit 5ffd75ecd4929f22361ef65a35f0331d2fbc0f35 of Diag
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -177,12 +177,18 @@ static void ddrphy_select_lane(void __iomem *phy_base, unsigned int lane,
 	       phy_base + PHY_LANE_SEL);
 }
 
+#define DDRPHY_EFUSEMON		(void *)0x5f900118
+
 static void ddrphy_init(void __iomem *phy_base, enum dram_board board, int ch)
 {
 	writel(0x0C001001, phy_base + PHY_UNIQUIFY_TSMC_IO_1);
 	while (!(readl(phy_base + PHY_UNIQUIFY_TSMC_IO_1) & BIT(1)))
 		cpu_relax();
-	writel(0x0C001000, phy_base + PHY_UNIQUIFY_TSMC_IO_1);
+
+	if (readl(DDRPHY_EFUSEMON) & BIT(ch))
+		writel(0x00000000, phy_base + PHY_UNIQUIFY_TSMC_IO_1);
+	else
+		writel(0x0C001000, phy_base + PHY_UNIQUIFY_TSMC_IO_1);
 
 	writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_3);
 	writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_1);
@@ -606,15 +612,18 @@ int uniphier_ld20_umc_init(const struct uniphier_board_data *bd)
 		return -EINVAL;
 	}
 
-	for (ch = 0; ch < bd->dram_nr_ch; ch++) {
+	for (ch = 0; ch < DRAM_CH_NR; ch++) {
 		unsigned long size = bd->dram_ch[ch].size;
 		unsigned int width = bd->dram_ch[ch].width;
 
-		ret = umc_ch_init(umc_ch_base, phy_ch_base, board,
-				  bd->dram_freq, size / (width / 16), ch);
-		if (ret) {
-			pr_err("failed to initialize UMC ch%d\n", ch);
-			return ret;
+		if (size) {
+			ret = umc_ch_init(umc_ch_base, phy_ch_base, board,
+					  bd->dram_freq, size / (width / 16),
+					  ch);
+			if (ret) {
+				pr_err("failed to initialize UMC ch%d\n", ch);
+				return ret;
+			}
 		}
 
 		umc_ch_base += 0x00200000;

arch/arm/mach-uniphier/dram/umc-pxs2.c

@@ -619,15 +619,17 @@ int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd)
 		return -EINVAL;
 	}
 
-	for (ch = 0; ch < bd->dram_nr_ch; ch++) {
+	for (ch = 0; ch < DRAM_CH_NR; ch++) {
 		unsigned long size = bd->dram_ch[ch].size;
 		unsigned int width = bd->dram_ch[ch].width;
 
-		ret = umc_ch_init(umc_ch_base, freq, size / (width / 16),
-				  width, ch);
-		if (ret) {
-			pr_err("failed to initialize UMC ch%d\n", ch);
-			return ret;
+		if (size) {
+			ret = umc_ch_init(umc_ch_base, freq,
+					  size / (width / 16), width, ch);
+			if (ret) {
+				pr_err("failed to initialize UMC ch%d\n", ch);
+				return ret;
+			}
 		}
 
 		umc_ch_base += 0x00200000;

arch/arm/mach-uniphier/dram_init.c

@@ -11,10 +11,12 @@
 #include <linux/errno.h>
 #include <linux/sizes.h>
 
-#include "init.h"
 #include "sg-regs.h"
 #include "soc-info.h"
 
+#define pr_warn(fmt, args...)	printf(fmt, ##args)
+#define pr_err(fmt, args...)	printf(fmt, ##args)
+
 DECLARE_GLOBAL_DATA_PTR;
 
 struct uniphier_memif_data {
@@ -76,7 +78,12 @@ static const struct uniphier_memif_data uniphier_memif_data[] = {
 };
 UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_memif_data, uniphier_memif_data)
 
-static int uniphier_memconf_decode(struct uniphier_dram_ch *dram_ch)
+struct uniphier_dram_map {
+	unsigned long base;
+	unsigned long size;
+};
+
+static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map)
 {
 	const struct uniphier_memif_data *data;
 	unsigned long size;
@@ -91,7 +98,7 @@ static int uniphier_memconf_decode(struct uniphier_dram_ch *dram_ch)
 	val = readl(SG_MEMCONF);
 
 	/* set up ch0 */
-	dram_ch[0].base = CONFIG_SYS_SDRAM_BASE;
+	dram_map[0].base = CONFIG_SYS_SDRAM_BASE;
 
 	switch (val & SG_MEMCONF_CH0_SZ_MASK) {
 	case SG_MEMCONF_CH0_SZ_64M:
@@ -110,27 +117,27 @@ static int uniphier_memconf_decode(struct uniphier_dram_ch *dram_ch)
 		size = SZ_1G;
 		break;
 	default:
-		pr_err("error: invald value is set to MEMCONF ch0 size\n");
+		pr_err("error: invalid value is set to MEMCONF ch0 size\n");
 		return -EINVAL;
 	}
 
 	if ((val & SG_MEMCONF_CH0_NUM_MASK) == SG_MEMCONF_CH0_NUM_2)
 		size *= 2;
 
-	dram_ch[0].size = size;
+	dram_map[0].size = size;
 
 	/* set up ch1 */
-	dram_ch[1].base = dram_ch[0].base + size;
+	dram_map[1].base = dram_map[0].base + size;
 
 	if (val & SG_MEMCONF_SPARSEMEM) {
-		if (dram_ch[1].base > data->sparse_ch1_base) {
+		if (dram_map[1].base > data->sparse_ch1_base) {
 			pr_warn("Sparse mem is enabled, but ch0 and ch1 overlap\n");
 			pr_warn("Only ch0 is available\n");
-			dram_ch[1].base = 0;
+			dram_map[1].base = 0;
 			return 0;
 		}
 
-		dram_ch[1].base = data->sparse_ch1_base;
+		dram_map[1].base = data->sparse_ch1_base;
 	}
 
 	switch (val & SG_MEMCONF_CH1_SZ_MASK) {
@@ -150,20 +157,20 @@ static int uniphier_memconf_decode(struct uniphier_dram_ch *dram_ch)
 		size = SZ_1G;
 		break;
 	default:
-		pr_err("error: invald value is set to MEMCONF ch1 size\n");
+		pr_err("error: invalid value is set to MEMCONF ch1 size\n");
 		return -EINVAL;
 	}
 
 	if ((val & SG_MEMCONF_CH1_NUM_MASK) == SG_MEMCONF_CH1_NUM_2)
 		size *= 2;
 
-	dram_ch[1].size = size;
+	dram_map[1].size = size;
 
-	if (!data->have_ch2)
+	if (!data->have_ch2 || val & SG_MEMCONF_CH2_DISABLE)
 		return 0;
 
 	/* set up ch2 */
-	dram_ch[2].base = dram_ch[1].base + size;
+	dram_map[2].base = dram_map[1].base + size;
 
 	switch (val & SG_MEMCONF_CH2_SZ_MASK) {
 	case SG_MEMCONF_CH2_SZ_64M:
@@ -182,32 +189,32 @@ static int uniphier_memconf_decode(struct uniphier_dram_ch *dram_ch)
 		size = SZ_1G;
 		break;
 	default:
-		pr_err("error: invald value is set to MEMCONF ch2 size\n");
+		pr_err("error: invalid value is set to MEMCONF ch2 size\n");
 		return -EINVAL;
 	}
 
 	if ((val & SG_MEMCONF_CH2_NUM_MASK) == SG_MEMCONF_CH2_NUM_2)
 		size *= 2;
 
-	dram_ch[2].size = size;
+	dram_map[2].size = size;
 
 	return 0;
 }
 
 int dram_init(void)
 {
-	struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH] = {};
+	struct uniphier_dram_map dram_map[3] = {};
 	int ret, i;
 
 	gd->ram_size = 0;
 
-	ret = uniphier_memconf_decode(dram_ch);
+	ret = uniphier_memconf_decode(dram_map);
 	if (ret)
 		return ret;
 
-	for (i = 0; i < ARRAY_SIZE(dram_ch); i++) {
+	for (i = 0; i < ARRAY_SIZE(dram_map); i++) {
 
-		if (!dram_ch[i].size)
+		if (!dram_map[i].size)
 			break;
 
 		/*
@@ -215,11 +222,11 @@ int dram_init(void)
 		 * but it does not expect sparse memory.  We use the first
 		 * contiguous chunk here.
 		 */
-		if (i > 0 &&
-		    dram_ch[i - 1].base + dram_ch[i - 1].size < dram_ch[i].base)
+		if (i > 0 && dram_map[i - 1].base + dram_map[i - 1].size <
+							dram_map[i].base)
 			break;
 
-		gd->ram_size += dram_ch[i].size;
+		gd->ram_size += dram_map[i].size;
 	}
 
 	return 0;
@@ -227,17 +234,17 @@ int dram_init(void)
 
 void dram_init_banksize(void)
 {
-	struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH] = {};
+	struct uniphier_dram_map dram_map[3] = {};
 	int i;
 
-	uniphier_memconf_decode(dram_ch);
+	uniphier_memconf_decode(dram_map);
 
-	for (i = 0; i < ARRAY_SIZE(dram_ch); i++) {
+	for (i = 0; i < ARRAY_SIZE(dram_map); i++) {
 		if (i >= ARRAY_SIZE(gd->bd->bi_dram))
 			break;
 
-		gd->bd->bi_dram[i].start = dram_ch[i].base;
-		gd->bd->bi_dram[i].size = dram_ch[i].size;
+		gd->bd->bi_dram[i].start = dram_map[i].base;
+		gd->bd->bi_dram[i].size = dram_map[i].size;
 	}
 }
 
@@ -256,6 +263,9 @@ int ft_board_setup(void *fdt, bd_t *bd)
 		return 0;
 
 	for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) {
+		if (!gd->bd->bi_dram[i].size)
+			continue;
+
 		rsv_addr = gd->bd->bi_dram[i].start + gd->bd->bi_dram[i].size;
 		rsv_addr -= rsv_size;
 

arch/arm/mach-uniphier/init.h

@@ -13,18 +13,17 @@
 #define UNIPHIER_MAX_NR_DRAM_CH		3
 
 struct uniphier_dram_ch {
-	unsigned long base;
 	unsigned long size;
 	unsigned int width;
 };
 
 struct uniphier_board_data {
 	unsigned int dram_freq;
-	unsigned int dram_nr_ch;
 	struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH];
 	unsigned int flags;
 
-#define UNIPHIER_BD_DDR3PLUS			BIT(2)
+#define UNIPHIER_BD_DRAM_SPARSE			BIT(9)
+#define UNIPHIER_BD_DDR3PLUS			BIT(8)
 
 #define UNIPHIER_BD_BOARD_GET_TYPE(f)		((f) & 0x7)
 #define UNIPHIER_BD_BOARD_LD20_REF		0	/* LD20 reference */
@@ -119,12 +118,16 @@ void uniphier_pro4_clk_init(void);
 void uniphier_pro5_clk_init(void);
 void uniphier_pxs2_clk_init(void);
 void uniphier_ld11_clk_init(void);
+void uniphier_ld20_clk_init(void);
 
+unsigned int uniphier_boot_device_raw(void);
 int uniphier_pin_init(const char *pinconfig_name);
 void uniphier_smp_kick_all_cpus(void);
 void cci500_init(int nr_slaves);
 
+#undef pr_warn
 #define pr_warn(fmt, args...)	printf(fmt, ##args)
+#undef pr_err
 #define pr_err(fmt, args...)	printf(fmt, ##args)
 
 #endif /* __MACH_INIT_H */

arch/arm/mach-uniphier/memconf.c

@@ -93,7 +93,7 @@ static int __uniphier_memconf_init(const struct uniphier_board_data *bd,
 	}
 
 	/* is sparse mem? */
-	if (bd->dram_ch[0].base + bd->dram_ch[0].size < bd->dram_ch[1].base)
+	if (bd->flags & UNIPHIER_BD_DRAM_SPARSE)
 		val |= SG_MEMCONF_SPARSEMEM;
 
 	if (!have_ch2)

arch/arm/mach-uniphier/micro-support-card.c

@@ -43,18 +43,13 @@ static int support_card_show_revision(void)
 	revision &= 0xff;
 
 	/* revision 3.6.x card changed the revision format */
-	printf("(CPLD version %s%d.%d)\n", revision >> 4 == 6 ? "3." : "",
+	printf("SC:    Micro Support Card (CPLD version %s%d.%d)\n",
+	       revision >> 4 == 6 ? "3." : "",
 	       revision >> 4, revision & 0xf);
 
 	return 0;
 }
 
-int checkboard(void)
-{
-	printf("SC:    Micro Support Card ");
-	return support_card_show_revision();
-}
-
 void support_card_init(void)
 {
 	support_card_reset();
@@ -64,6 +59,8 @@ void support_card_init(void)
 	 */
 	udelay(200);
 	support_card_reset_deassert();
+
+	support_card_show_revision();
 }
 
 #if defined(CONFIG_SMC911X)

arch/arm/mach-uniphier/mmc-boot-mode.c

@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <spl.h>
+
+u32 spl_boot_mode(const u32 boot_device)
+{
+	struct mmc *mmc;
+
+	/*
+	 * work around a bug in the Boot ROM of PH1-sLD3, LD4, Pro4, and sLD8:
+	 *
+	 * The boot ROM in these SoCs breaks the PARTITION_CONFIG [179] of
+	 * Extended CSD register; when switching to the Boot Partition 1, the
+	 * Boot ROM should issue the SWITCH command (CMD6) with Set Bits for
+	 * the Access Bits, but in fact it uses Write Byte for the Access Bits.
+	 * As a result, the BOOT_PARTITION_ENABLE field of the PARTITION_CONFIG
+	 * is lost.  This bug was fixed for PH1-Pro5 and later SoCs.
+	 *
+	 * Fixup mmc->part_config here because it is used to determine the
+	 * partition which the U-Boot image is read from.
+	 */
+	mmc = find_mmc_device(0);
+	mmc->part_config &= ~EXT_CSD_BOOT_PART_NUM(PART_ACCESS_MASK);
+	mmc->part_config |= EXT_CSD_BOOT_PARTITION_ENABLE;
+
+	return MMCSD_MODE_EMMCBOOT;
+}

arch/arm/mach-uniphier/mmc-first-dev.c

@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <linux/errno.h>
+
+static int find_first_mmc_device(void)
+{
+	struct mmc *mmc;
+	int i;
+
+	for (i = 0; (mmc = find_mmc_device(i)); i++) {
+		if (!mmc_init(mmc) && IS_MMC(mmc))
+			return i;
+	}
+
+	return -ENODEV;
+}
+
+int mmc_get_env_dev(void)
+{
+	return find_first_mmc_device();
+}
+
+static int do_mmcsetn(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int dev;
+
+	dev = find_first_mmc_device();
+	if (dev < 0)
+		return CMD_RET_FAILURE;
+
+	setenv_ulong("mmc_first_dev", dev);
+	return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+	   mmcsetn,	1,	1,	do_mmcsetn,
+	"Set the first MMC (not SD) dev number to \"mmc_first_dev\" environment",
+	""
+);

arch/arm/mach-uniphier/spl_board_init.c

@@ -168,4 +168,8 @@ void spl_board_init(void)
 		pr_err("failed to init DRAM\n");
 		hang();
 	}
+
+#ifdef CONFIG_ARM64
+	dcache_disable();
+#endif
 }

arch/powerpc/include/asm/fsl_secure_boot.h

@@ -103,11 +103,6 @@
 #define CONFIG_CMD_BLOB
 #define CONFIG_FSL_SEC_MON
 #define CONFIG_SHA_PROG_HW_ACCEL
-#define CONFIG_RSA_FREESCALE_EXP
-
-#ifndef CONFIG_FSL_CAAM
-#define CONFIG_FSL_CAAM
-#endif
 
 #ifndef CONFIG_SPL_BUILD
 /*

arch/x86/Kconfig

@@ -80,6 +80,20 @@ config VENDOR_INTEL
 
 endchoice
 
+# subarchitectures-specific options below
+config INTEL_MID
+	bool "Intel MID platform support"
+	help
+	  Select to build a U-Boot capable of supporting Intel MID
+	  (Mobile Internet Device) platform systems which do not have
+	  the PCI legacy interfaces.
+
+	  If you are building for a PC class system say N here.
+
+	  Intel MID platforms are based on an Intel processor and
+	  chipset which consume less power than most of the x86
+	  derivatives.
+
 # board-specific options below
 source "board/advantech/Kconfig"
 source "board/congatec/Kconfig"

arch/x86/cpu/i386/interrupt.c

@@ -28,7 +28,7 @@ DECLARE_GLOBAL_DATA_PTR;
 	".type irq_"#x", @function\n" \
 	"irq_"#x":\n" \
 	"pushl $"#x"\n" \
-	"jmp irq_common_entry\n"
+	"jmp.d32 irq_common_entry\n"
 
 static char *exceptions[] = {
 	"Divide Error",

arch/x86/cpu/mp_init.c

@@ -248,7 +248,8 @@ static int load_sipi_vector(atomic_t **ap_countp, int num_cpus)
 	if (!stack)
 		return -ENOMEM;
 	params->stack_top = (u32)(stack + size);
-#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP)
+#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP) && \
+	!defined(CONFIG_INTEL_MID)
 	params->microcode_ptr = ucode_base;
 	debug("Microcode at %x\n", params->microcode_ptr);
 #endif

arch/x86/lib/zimage.c

@@ -246,6 +246,10 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
 			hdr->setup_move_size = 0x9100;
 		}
 
+#if defined(CONFIG_INTEL_MID)
+		hdr->hardware_subarch = X86_SUBARCH_INTEL_MID;
+#endif
+
 		/* build command line at COMMAND_LINE_OFFSET */
 		build_command_line(cmd_line, auto_boot);
 	}

board/davinci/da8xxevm/README.da850

@@ -47,6 +47,29 @@ U-Boot > sf erase 0 +320000
 U-Boot > tftp u-boot.ais
 U-Boot > sf write c0700000 0 $filesize
 
+Flashing the images to MMC
+==========================
+If the boot pins are set to boot from mmc, the RBL will try to load the
+next boot stage form the first couple of sectors of an external mmc card.
+As sector 0 is usually used for storing the partition information, the
+AIS image should be written at least after the first sector, but before the
+first partition begins. (e.g: make sure to leave at least 500KB of unallocated
+space at the start of the mmc when creating the partitions)
+
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR is used by SPL, and should
+point to the sector were the u-boot image is located. (eg. After SPL)
+
+There are 2 ways to copy the AIS image to the mmc card:
+
+ 1 - Using the TI tool "uflash"
+	$ uflash -d /dev/mmcblk0  -b ./u-boot.ais -p OMAPL138  -vv
+
+ 2 - using the "dd" command
+	$ dd if=u-boot.ais of=/dev/mmcblk0 seek=117 bs=512 conv=fsync
+
+uflash writes the AIS image at offset 117. For compatibility with uflash,
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR is set to take into account this
+offset, and the dd command is adjusted accordingly.
 
 Recovery
 ========

board/freescale/common/Kconfig

@@ -1,4 +1,5 @@
 config CHAIN_OF_TRUST
 	depends on !FIT_SIGNATURE && SECURE_BOOT
+	select FSL_CAAM
 	bool
 	default y

board/ti/am335x/Kconfig

@@ -1,14 +1,5 @@
 if TARGET_AM335X_EVM
 
-config SPL_ENV_SUPPORT
-	default y
-
-config SPL_WATCHDOG_SUPPORT
-	default y
-
-config SPL_YMODEM_SUPPORT
-	default y
-
 config SYS_BOARD
 	default "am335x"
 

board/ti/am57xx/board.c

@@ -487,6 +487,8 @@ int board_late_init(void)
 	palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
 			    val);
 
+	omap_die_id_serial();
+
 	return 0;
 }
 

board/ti/common/Kconfig

@@ -1,41 +1,5 @@
-config SPL_ENV_SUPPORT
-	default y
-
 config TI_I2C_BOARD_DETECT
 	bool "Support for Board detection for TI platforms"
 	help
 	   Support for detection board information on Texas Instrument's
 	   Evaluation Boards which have I2C based EEPROM detection
-
-config SPL_EXT_SUPPORT
-	default y
-
-config SPL_FAT_SUPPORT
-	default y
-
-config SPL_GPIO_SUPPORT
-	default y
-
-config SPL_I2C_SUPPORT
-	default y
-
-config SPL_LIBCOMMON_SUPPORT
-	default y
-
-config SPL_LIBDISK_SUPPORT
-	default y
-
-config SPL_LIBGENERIC_SUPPORT
-	default y
-
-config SPL_MMC_SUPPORT
-	default y
-
-config SPL_NAND_SUPPORT
-	default y
-
-config SPL_POWER_SUPPORT
-	default y
-
-config SPL_SERIAL_SUPPORT
-	default y

common/spl/Kconfig

@@ -96,6 +96,36 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
 	  Address on the MMC to load U-Boot from, when the MMC is being used
 	  in raw mode. Units: MMC sectors (1 sector = 512 bytes).
 
+config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
+	bool "MMC Raw mode: by partition"
+	depends on SPL
+	help
+	  Use a partition for loading U-Boot when using MMC/SD in raw mode.
+
+config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
+	hex "Partition to use to load U-Boot from"
+	depends on SPL && SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
+	default 1
+	help
+	  Partition on the MMC to load U-Boot from when the MMC is being
+	  used in raw mode
+
+config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
+	bool "MMC raw mode: by partition type"
+	depends on SPL && DOS_PARTITION && \
+		SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
+	help
+	  Use partition type for specifying U-Boot partition on MMC/SD in
+	  raw mode. U-Boot will be loaded from the first partition of this
+	  type to be found.
+
+config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
+	hex "Partition Type on the MMC to load U-Boot from"
+	depends on SPL && SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
+	help
+	  Partition Type on the MMC to load U-Boot from, when the MMC is being
+	  used in raw mode.
+
 config TPL
 	bool
 	depends on SPL && SUPPORT_TPL

common/spl/spl_mmc.c

@@ -150,13 +150,28 @@ static int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)
 	return 0;
 }
 
-#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
+#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
 static int mmc_load_image_raw_partition(struct spl_image_info *spl_image,
 					struct mmc *mmc, int partition)
 {
 	disk_partition_t info;
 	int err;
 
+#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
+	int type_part;
+	/* Only support MBR so DOS_ENTRY_NUMBERS */
+	for (type_part = 1; type_part <= DOS_ENTRY_NUMBERS; type_part++) {
+		err = part_get_info(mmc_get_blk_desc(mmc), type_part, &info);
+		if (err)
+			continue;
+		if (info.sys_ind == 
+			CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE) {
+			partition = type_part;
+			break;
+		}
+	}
+#endif
+
 	err = part_get_info(mmc_get_blk_desc(mmc), partition, &info);
 	if (err) {
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
@@ -172,13 +187,6 @@ static int mmc_load_image_raw_partition(struct spl_image_info *spl_image,
 	return mmc_load_image_raw_sector(spl_image, mmc, info.start);
 #endif
 }
-#else
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION -1
-static int mmc_load_image_raw_partition(struct spl_image_info *spl_image,
-					struct mmc *mmc, int partition)
-{
-	return -ENOSYS;
-}
 #endif
 
 #ifdef CONFIG_SPL_OS_BOOT
@@ -326,11 +334,12 @@ int spl_mmc_load_image(struct spl_image_info *spl_image,
 			if (!err)
 				return err;
 		}
-
+#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
 		err = mmc_load_image_raw_partition(spl_image, mmc,
 			CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION);
 		if (!err)
 			return err;
+#endif
 #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
 		err = mmc_load_image_raw_sector(spl_image, mmc,
 			CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);

common/splash_source.c

@@ -216,6 +216,7 @@ static int splash_load_fs(struct splash_location *location, u32 bmp_load_addr)
 {
 	int res = 0;
 	loff_t bmp_size;
+	loff_t actread;
 	char *splash_file;
 
 	splash_file = getenv("splashfile");
@@ -251,7 +252,7 @@ static int splash_load_fs(struct splash_location *location, u32 bmp_load_addr)
 	}
 
 	splash_select_fs_dev(location);
-	res = fs_read(splash_file, bmp_load_addr, 0, 0, NULL);
+	res = fs_read(splash_file, bmp_load_addr, 0, 0, &actread);
 
 out:
 	if (location->ubivol != NULL)

configs/A10-OLinuXino-Lime_defconfig

@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=480
 CONFIG_DRAM_EMR1=4
@@ -11,6 +10,7 @@ CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,SATAPWR=SUNXI_GPC(3)"
 CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set

configs/A10s-OLinuXino-M_defconfig

@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_MACH_SUN5I=y
 CONFIG_DRAM_CLK=432
 CONFIG_MMC0_CD_PIN="PG1"
@@ -11,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-olinuxino-micro"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
 CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set

configs/A13-OLinuXino_defconfig

@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_MACH_SUN5I=y
 CONFIG_DRAM_CLK=408
 CONFIG_DRAM_EMR1=0
@@ -17,6 +16,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_DFU=y

configs/A20-OLinuXino-Lime2_defconfig

@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
@@ -11,6 +10,7 @@ CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,SATAPWR=SUNXI_GPC(3)"
 CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_DFU=y
@@ -20,7 +20,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_SPL_ISO_PARTITION is not set
 # CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_DFU_RAM=y
-CONFIG_RTL8211X_PHY_FORCE_MASTER=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800

configs/A20-OLinuXino-Lime_defconfig

@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
@@ -9,6 +8,7 @@ CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,SATAPWR=SUNXI_GPC(3)"
 CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set

configs/A20-OLinuXino_MICRO_defconfig

@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
@@ -12,6 +11,7 @@ CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,SATAPWR=SUNXI_GPB(8)"
 CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set

configs/A20-Olimex-SOM-EVB_defconfig

@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
@@ -14,13 +13,13 @@ CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,SATAPWR=SUNXI_GPC(3)"
 CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_ISO_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_RTL8211X_PHY_FORCE_MASTER=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800

configs/Ainol_AW1_defconfig

@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=432
 CONFIG_DRAM_ZQ=123
@@ -15,6 +14,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ainol-aw1"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set

configs/Ampe_A76_defconfig

@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_MACH_SUN5I=y
 CONFIG_DRAM_CLK=432
 CONFIG_MMC0_CD_PIN="PG0"
@@ -17,6 +16,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-ampe-a76"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set

configs/Auxtek-T003_defconfig

@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_MACH_SUN5I=y
 CONFIG_DRAM_CLK=408
 CONFIG_DRAM_EMR1=0
@@ -9,6 +8,7 @@ CONFIG_VIDEO_COMPOSITE=y
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t003"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set

configs/Auxtek-T004_defconfig

@@ -1,12 +1,12 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_MACH_SUN5I=y
 CONFIG_DRAM_CLK=432
 CONFIG_USB1_VBUS_PIN="PG13"
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t004"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set

configs/B4420QDS_NAND_defconfig

@@ -1,12 +1,9 @@
 CONFIG_PPC=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-# CONFIG_MMC is not set
+CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_B4420QDS=y
 CONFIG_FIT=y
@@ -17,6 +14,8 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_BOOTDELAY=10
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
@@ -27,6 +26,8 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
+CONFIG_FSL_CAAM=y
+# CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y

configs/B4420QDS_SPIFLASH_defconfig

@@ -1,5 +1,4 @@
 CONFIG_PPC=y
-# CONFIG_MMC is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_B4420QDS=y
 CONFIG_FIT=y
@@ -18,6 +17,8 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
+CONFIG_FSL_CAAM=y
+# CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y

configs/B4420QDS_defconfig

@@ -1,5 +1,4 @@
 CONFIG_PPC=y
-# CONFIG_MMC is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_B4420QDS=y
 CONFIG_FIT=y
@@ -17,6 +16,8 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
+CONFIG_FSL_CAAM=y
+# CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y

configs/B4860QDS_NAND_defconfig

@@ -1,12 +1,9 @@
 CONFIG_PPC=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-# CONFIG_MMC is not set
+CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_B4860QDS=y
 CONFIG_FIT=y
@@ -17,6 +14,8 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_BOOTDELAY=10
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
@@ -27,6 +26,8 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
+CONFIG_FSL_CAAM=y
+# CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y

configs/B4860QDS_SECURE_BOOT_defconfig

@@ -31,4 +31,5 @@ CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
 CONFIG_OF_LIBFDT=y

configs/B4860QDS_SPIFLASH_defconfig

@@ -1,5 +1,4 @@
 CONFIG_PPC=y
-# CONFIG_MMC is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_B4860QDS=y
 CONFIG_FIT=y
@@ -18,6 +17,8 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
+CONFIG_FSL_CAAM=y
+# CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y

configs/B4860QDS_SRIO_PCIE_BOOT_defconfig

@@ -1,5 +1,4 @@
 CONFIG_PPC=y
-# CONFIG_MMC is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_B4860QDS=y
 CONFIG_FIT=y
@@ -20,6 +19,8 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
+CONFIG_FSL_CAAM=y
+# CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y

configs/B4860QDS_defconfig

@@ -1,5 +1,4 @@
 CONFIG_PPC=y
-# CONFIG_MMC is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_B4860QDS=y
 CONFIG_FIT=y
@@ -17,6 +16,8 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
+CONFIG_FSL_CAAM=y
+# CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y

configs/BSC9131RDB_NAND_SYSCLK100_defconfig

@@ -1,7 +1,6 @@
 CONFIG_PPC=y
-CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
-# CONFIG_MMC is not set
+CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9131RDB=y
 CONFIG_FIT=y
@@ -23,6 +22,8 @@ CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
+# CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_PCI is not set

configs/BSC9131RDB_NAND_defconfig

@@ -1,7 +1,6 @@
 CONFIG_PPC=y
-CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
-# CONFIG_MMC is not set
+CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9131RDB=y
 CONFIG_FIT=y
@@ -23,6 +22,8 @@ CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
+# CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_PCI is not set

configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig

@@ -1,5 +1,4 @@
 CONFIG_PPC=y
-# CONFIG_MMC is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9131RDB=y
 CONFIG_FIT=y
@@ -20,6 +19,8 @@ CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
+# CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_PCI is not set

configs/BSC9131RDB_SPIFLASH_defconfig

@@ -1,5 +1,4 @@
 CONFIG_PPC=y
-# CONFIG_MMC is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9131RDB=y
 CONFIG_FIT=y
@@ -20,6 +19,8 @@ CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
+# CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_PCI is not set