If the value of either "nand options" or "bbt options" has a zero in
the most significant nibble, the '0x' prefix will be isolated from the
value like shown below:
|Device 0: nand0, sector size 128 KiB
| Page size 2048 b
| OOB size 64 b
| Erase size 131072 b
| subpagesize 2048 b
| options 0x40000200
| bbt options 0x 60000
Change the format string to produce leading zeroes filling the gap.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
This error code has not been upstreamed and is not really needed since it
is unlikely to be triggered. Drop it to maintain compatability with
upstream.
Reported-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
It's been a while since I've touched U-Boot on the Raspberry Pi and
other things have been taking my time. Drop my maintainership for this
port.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
CS Systemes d'Information (CSSI) manufactures two boards, named MCR3000
and CMPC885 which are respectively based on MPC866 and MPC885 processors.
This patch adds support for the first board.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
For processors whose core runs at twice the bus frequency,
the fallback frequency calculation in Linux provides a wrong
result. Therefore, U-boot needs to pass the correct value.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Reviewed-by: Heiko Schocher <hs@denx.de>
immap.c used to be common to several CPUs. It is now
only linked to the 8xx, so this patch moves it into
arch/powerpc/cpu/mpc8xx/
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Reviewed-by: Heiko Schocher <hs@denx.de>
CS Systemes d'Information (CSSI) manufactures 8xx boards for
critical communication systems. Those boards have been
running U-Boot since 2010 and will have to be maintained
until at least 2027.
commit 5b8e76c35e
("powerpc, 8xx: remove support for 8xx") orphaned those boards
by removing support for the mpc8xx CPU.
This commit partially restores support for the 8xx, with the
following limitations:
- Restores support for MPC866 and MPC885 only
- Does not restore IDE, PCMCIA, I2C, USB
- Does not restore examples
- Does not restore POST
- Does not restore Ethernet on SCC
- Does not restore console on SCC
- Does not restore bedbug and kgdb support
As the 866 and 885 do not support the following features,
they are not restored either:
- VIDEO / LCD
- RTC clock
The CPM uCODE patch is not restored either, because:
- 866 and 885 already have support for I2C and SPI relocation
without a uCODE patch
- relocation of SMC, I2C or SPI is only needed for using SCCs
for Ethernet or QMC
The dynamic setup/calculation of clocks is removed, we
expect the target being use with the clock and PLPRCR register
defined in the configuration.
All the clock settings for 8xx prior to 866 is removed as
well as we now only support 866 and 885.
This code is mature and addresses mature boards. Therefore
all code enclosed in '#if 0/#endif' and '#if XX_DEBUG/#endif'
is unneeded.
The following files are not restored by this patch:
- arch/powerpc/cpu/mpc8xx/bedbug_860.c
- arch/powerpc/cpu/mpc8xx/fec.h
- arch/powerpc/cpu/mpc8xx/kgdb.S
- arch/powerpc/cpu/mpc8xx/plprcr_write.S
- arch/powerpc/cpu/mpc8xx/scc.c
- arch/powerpc/cpu/mpc8xx/upatch.c
- arch/powerpc/cpu/mpc8xx/video.c
- arch/powerpc/include/asm/status_led.h
- arch/powerpc/lib/ide.c
- arch/powerpc/lib/ide.h
- doc/README.MPC866
- drivers/pcmcia/mpc8xx_pcmcia.c
- drivers/rtc/mpc8xx.c
- drivers/usb/gadget/mpc8xx_udc.c
- drivers/video/mpc8xx_lcd.c
- examples/standalone/test_burst.c
- examples/standalone/test_burst.h
- examples/standalone/test_burst_lib.S
- examples/standalone/timer.c
- include/mpc823_lcd.h
- include/usb/mpc8xx_udc.h
- post/cpu/mpc8xx/Makefile
- post/cpu/mpc8xx/cache.c
- post/cpu/mpc8xx/cache_8xx.S
- post/cpu/mpc8xx/ether.c
- post/cpu/mpc8xx/spr.c
- post/cpu/mpc8xx/uart.c
- post/cpu/mpc8xx/usb.c
- post/cpu/mpc8xx/watchdog.c
Some of the restored files are not located in a proper location.
In order to keep traceability of the changes, they will be
moved to their correct location and moved to Kconfig in a
followup patch.
This patch also declares CSSI as point of contact for the update
of the 8xx platform, as those boards are the only ones still
being maintained on the 8xx area. A later patch will add
those boards to the tree.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
On startup the SL50 board halt at U-Boot prompt. Use CONFIG_AUTOBOOT_KEYED
to enable autoboot for this board and define the <SPACE> key to get the
U-Boot prompt.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
since commit
'd5abcf94c7123167725fc22ace342f0d455093c1' -
ti: boot: Register the MMC controllers in SPL in the same way as in u-boot
MMC boot on brppt1 board is broken, with this commit we make our board
working again.
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
There is no need to duplicate same option with different name.
Kill HW_WATCHDOG_TIMEOUT_MS in favor of WATCHDOG_TIMEOUT_MSECS.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
AVR32 is gone. It's already more than two years for no support in Buildroot,
even longer there is no support in GCC (last version is heavily patched 4.2.4).
Linux kernel v4.12 got rid of it (and v4.11 didn't build successfully).
There is no good point to keep this support in U-Boot either.
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
The current code gives a warning:
arch/arm/mach-stm32/stm32f7/soc.c: In function 'arch_cpu_init':
arch/arm/mach-stm32/stm32f7/soc.c:38:2: error: 'for' loop initial
declarations are only allowed in C99 or C11 mode
for (int i = 0; i < ARRAY_SIZE(stm32_region_config); i++)
^
arch/arm/mach-stm32/stm32f7/soc.c:38:2: note: use option -std=c99,
-std=gnu99, -std=c11 or -std=gnu11 to compile your code
Fix it by moving the declaration to the top of the function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Series-cc trini
The 82xx board mgcoge3ne was removed from the codebase, so this is dead
code.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
The Odroid C2 comes with several expansion options such as an RTC module.
As these expansions are not considered in the Linux device tree they have
to be enabled via device tree overlays.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Since commit 5b9d44df23 (mkimage: Display a better list of available image
types) mkimage usage text suggest to "use -T to see a list of available image
types". Unfortunately, commit 02221f29deb8 (mkimage: Convert to use getopt())
broke that feature, because getopt() fails when -T has no option argument.
Add a pseudo image type name 'list' that lists all image types. Update the
usage text accordingly.
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
CHIP and CHIP Pro devices have options of DIP addon boards some of which need
overlays from the beginning so it makes sense to enable device tree overlays.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
96boards CE devices such as the DragonBoard and Hikey devices have numerous
mezzanine options some of which need overlays from the beginning so it makes
sense to enable device tree overlays.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
TI am33xx devices such as the BeagleBone devices have numerous cape options such
as screens some of which need overlays from the beginning so it makes sense to
enable evice tree overlays.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Raspberry Pi has numerous HAT and other HW expansion options such as screens and
cameras some of which need overlays from the beginning so it makes sense to
enable evice tree overlays.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
This actually works on snapdragon.. not sure why we weren't using it.
Fixes reboot/poweroff when using UEFI.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Fastmap significantly reduces flash scan time, enable it by default.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Acked-by: Heiko Schocher <hs@denx.de>
Fastmap was always enabled in ubispl, make it selectable by
CONFIG_MTD_UBI_FASTMAP.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Acked-by: Heiko Schocher <hs@denx.de>
Add missing static to serial_stub_puts().
Unexport serial_stub_{getc,tstc} because they are used locally.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
If a relocation type is not supported loading the EFI binary
should be aborted.
Writing a message only is insufficient.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
[agraf: use a() != b coding style]
Signed-off-by: Alexander Graf <agraf@suse.de>
The efi-next tree lives on github, not the usual denx git.
Reflect this in the MAINTAINERS file so that people can
find it.
Signed-off-by: Alexander Graf <agraf@suse.de>
UEFI spec 2.7 indicates that HandleProtocol can be implemented
by calling OpenProtocol with
attributes = EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL.
Currently we pass attributes = 0 to efi_open_protocol. 0 is not a
valid value when calling OpenProtocol. This does not cause any errors
yet because our implementation of OpenProtocol is incomplete.
We should pass the correct value to enable a fully compliant
implementation of OpenProtocol in the future.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
There was for long time no activity in the 4xx area.
We need to go further and convert to Kconfig, but it
turned out, nobody is interested anymore in 4xx,
so remove it.
Signed-off-by: Heiko Schocher <hs@denx.de>
Add some of the invalid parameter checks described in the UEFI
specification for CreateEvent(). This does not include checking
the validity of the type and tpl parameters.
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Acked-By: Heinrich Schuchardt <xypron.glpk@gmx.de>
[agraf: fix checkpatch.pl indent warning]
Signed-off-by: Alexander Graf <agraf@suse.de>
The UEFI specification states that the tpl, function and context
arguments are to be ignored if neither EVT_NOTIFY_WAIT or
EVT_NOTIFY_SIGNAL are specified. This matches observed behaviour with
an AMI EDK2 based UEFI implementation.
Skip calling the notify function if neither flag is present.
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Acked-By: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
When running bootefi, we allocate new space but never check whether
the allocation succeeded. This patch adds a check so that in case
things go wrong, we at least know they did.
Signed-off-by: Alexander Graf <agraf@suse.de>
doc/README.fsl-clk was removed in commit
5b8e76c35e ("powerpc, 8xx: remove support for 8xx")
allthought CONFIG_SYS_FSL_CLK is defined in
arch/arm/cpu/armv8/fsl-layerscape/Kconfig and still in use
in the following configs:
./include/configs/mx53loco.h:21:#define CONFIG_SYS_FSL_CLK
./include/configs/m53evk.h:16:#define CONFIG_SYS_FSL_CLK
./include/configs/mx25pdk.h:17:#define CONFIG_SYS_FSL_CLK
./include/configs/usbarmory.h:14:#define CONFIG_SYS_FSL_CLK
./include/configs/ls1021aqds.h:14:#define CONFIG_SYS_FSL_CLK
./include/configs/mx53cx9020.h:22:#define CONFIG_SYS_FSL_CLK
./include/configs/colibri_vf.h:17:#define CONFIG_SYS_FSL_CLK
./include/configs/mx35pdk.h:21:#define CONFIG_SYS_FSL_CLK
./include/configs/woodburn_common.h:19:#define CONFIG_SYS_FSL_CLK
./include/configs/mx7_common.h:25:#define CONFIG_SYS_FSL_CLK
./include/configs/ls1021aiot.h:12:#define CONFIG_SYS_FSL_CLK
./include/configs/ls1021atwr.h:14:#define CONFIG_SYS_FSL_CLK
./include/configs/mx53ard.h:21:#define CONFIG_SYS_FSL_CLK
./include/configs/mx53smd.h:21:#define CONFIG_SYS_FSL_CLK
./include/configs/mx51evk.h:16:#define CONFIG_SYS_FSL_CLK
./include/configs/mx6_common.h:31:#define CONFIG_SYS_FSL_CLK
./include/configs/vf610twr.h:14:#define CONFIG_SYS_FSL_CLK
./include/configs/mx53evk.h:21:#define CONFIG_SYS_FSL_CLK
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Reviewed-by: Heiko Schocher <hs@denx.de>
The author of the commit discovered later on that this was already being
done in cleanup_before_linux() on arch/arm/cpu/armv7m/cpu.c.
This reverts commit 8f079cccb3.
Signed-off-by: Tom Rini <trini@konsulko.com>
Discern the SoMs based on the presence of SPI flash to support both
variants of the SoM, one booting from SPI NOR and one booting from
eMMC.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
The redesigned version of the SoM which was released onto the market
does no longer contain SPI flash, but boots from the eMMC. Move the
environment storage to the eMMC.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Continue loading U-Boot from MMC2 when the SPL was loaded using SAM-BA
loader. This allows the board to boot system from the removable media
instead of the eMMC, which is useful for commissioning purposes. When
booting from the eMMC, always boot from it as it is not possible to
boot from the SD interface directly.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
The SoM has been redesigned to work around bug in the SoC and is now
capable of booting from the eMMC. Add support for booting from eMMC.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
The SDHCI1 is the primary boot controller on rev. 2.1 SoM, which
is the version available on the market. Swap the controller order
to match this and future versions of the SoM.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Init the controllers, otherwise the board cannot boot from SD/MMC.
This boot option is new on rev. 2.1 SoM .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
The CAN controllers need slight delay between toggling of their reset
line. Move this action into board_init(), otherwise timer will not be
initialized and the board might hang.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
According to the datasheet, sequential mapping is used for DDR
SDRAM, while interleaved mapping is used for regular SDRAM.
Incorrect configuration of this bit does indeed cause sporadic
memory instability.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Wenyou Yang <wenyou.yang@atmel.com>
ARC HS Development Kit board is a new low-cost
development platform sporting ARC HS38 in real silicon
with nice set of features such as:
* Quad-core ARC HS38 with 512 kB L2 cache and running @1GHz
* 4Gb of DDR (we use only lowest 1Gb out of it now)
* Lots of DesigWare peripherals
* Different connectivity modules:
- Synopsys HAPS HT3
- Arduino-compatible connector
- MikroBUS
This initial commit supports the following peripherals:
* UART (DW 8250)
* Ethernet (DW GMAC)
* SD/MMC (DW Mobile Storage)
* USB 1.1 & 2.0
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
We used to use the same memory layout and size for a couple of
boards and thus we just hardcoding IOC aperture start and size.
Now when we're getting more boards with more memory on board we
need to have an ability to set IOC so it matches real DDR layout
and size.
Even though it is not really a must but for simplicity we assume
IOC covers all the DDR we have, that gives us a chance to not
bother where DMA buffers are allocated - any part of DDR is OK.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
With deprecation of I2C EEPROM we we left without a permamnent
storage for U-Boot environment, but luckily we may simply use SD-card
with FAT partition for that.
Having environment on SD-card is much more convenient as it
allows us to preserve all the settings when moving from one board to
another. Moreover instead of 256 bytes of EEPROM we're now virtually
unlimited in stuff being placed in environment like complicated scripts
etc which are usually required in case of full-scale distros.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
With eb5ba3aefd "i2c: Drop use of CONFIG_I2C_HARD" in place we
cannot use I2C EEPROM any longer so we're dropping all references to
both EEPROM and I2C which was only used for EEPROM.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Simon Glass <sjg@chromium.org>
ARCompact cores are not supposed to be used in SMP designs
(this doesn't stop people from creation of heterogeneous chips,
for an example keep reading) so there's no point in
checking ARCNUM and halting somebody if we build for ARC700.
Moreover on AXS101 board we have ARC770 in the ASIC together with
other ARC cores and ARC770 happens to be the last node in JTAG chain
with ARCNUM = 4. And existing check halts the one and only core we
want keep running.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
since commit: f8b7fff1d5 "serial: atmel_usart: Add clk support"
taurus board comes not up anymore. Fix it.
Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Wenyou Yang <wenyou.yang@microchip.com>
since commit 842778a091 dfu-util shows serial="UNDEFINED".
to see here again a serial number, we have to call
g_dnl_set_serialnumber().
Signed-off-by: Heiko Schocher <hs@denx.de>
since commit: f8b7fff1d5 "serial: atmel_usart: Add clk support"
smartweb board comes not up anymore. Fix it.
Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Wenyou Yang <wenyou.yang@microchip.com>
fix warnings:
drivers/usb/gadget/at91_udc.c:1344:12: warning: 'at91rm9200_udc_init' defined but not used [-Wunused-function]
drivers/usb/gadget/at91_udc.c:1379:13: warning: 'at91rm9200_udc_pullup' defined but not used [-Wunused-function]
drivers/usb/gadget/at91_udc.c:1476:12: warning: 'at91sam9263_udc_init' defined but not used [-Wunused-function]
Signed-off-by: Heiko Schocher <hs@denx.de>
The CONFIG_DEFAULT_FDT_FILE expects just the file not a full path
as that might vary depending on the variant of Linux distro you
might be using.
Cc: Martin Donnelly <martin.donnelly@ge.com>
Cc: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Acked-by: Fabio Estevam <fabio.estevam@nxp.com>
Some Kconfig options are defined in a line with leading spaces/tabs.
Update build-whitelist/check-config scripts to handle such cases.
Generate a new config_whitelist.txt with new scripts.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
The origin SPL_USE_ARCH_MEMSET/MEMCPY use same prompt message
as USE_ARCH_MEMSET/MEMCPY, which makes it's hard to distinguish
them in menuconfig interface. This patch gives them different
prompt messages for spl and none-spl config.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
After the commit SHA1: 842778a091 - the serial number descriptor is only
visible when we have non zero length of g_dnl_serial.
However, on some platforms (e.g. Siemens) the serial number is set at
g_dnl_bind_fixup(), so with the current code we will always omit the
serial (since it is not set).
This commit moves the g_dnl_bind_fixup() call before the g_dnl_serial
length test.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
The ti816x SoC revision of the ethernet IP block is handled by the
"davinci_emac" driver, rather than the "cpsw" driver as done by later
members of the family. Enable the relevant plumbing.
Signed-off-by: Sriramakrishnan <srk@ti.com>
Signed-off-by: Vitaly Wool <vitaly.wool@konsulko.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This reverts commit ddb3ac3c71.
With MMC converted to driver model, SCSI driver is broken due to
zero address access at (ops->read) in block_dread() function.
The fix (SCSI driver converted to DM) is ready in u-boot-dm branch,
but it is too late for this relese to get that in.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Fix warnings reported by sparse:
- ... was not declared. Should it be static?"
- cast to restricted __be32
While fixing those, the type conflict of cci500_init() was found.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
fix menutext for the options SPL_DM_SERIAL and TPL_DM_SERIAL.
Both have the same text as DM_SERIAL, which is
confusing.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
for debugging it is handy to know the fdt_blob
address. So print it in bdinfo.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Otherwise the loaded image would miss the efi_runtime sections, and fall
over hard when grub (for example) tried to call runtime services located
in this section.
Signed-off-by: Rob Clark <robdclark@gmail.com>
commit dfe64e2c89
Author: Sergey Lapin <slapin@ossfans.org>
Date: Mon Jan 14 03:46:50 2013 +0000
mtd: resync with Linux-3.7.1
modified onenand_block_markbad to call mtd_block_markbad,
but as _block_markbad function pointer used by mtd_block_markbad
to do actual job is by default pointing back to
onenand_block_markbad there is no way this function ever
finishes its job.
Fix it by changing function body according current (4.12-rc6)
linux implementation.
Tested on IGEPv2 board with Muxed OneNAND(DDP) 512MB containing
several unerasable blocks this function marked bad.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Current implementation is unable to access second half of
DDP OneNAND flash (reads first half mirrored). Use block
and bufferram address calculations from onenand_base to
fix this.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Define a default number of 1 for mmc max device if board config didn't
specify one.
Signed-off-by: Emmanuel Vadot <manu@bidouilliste.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The variable syndrome_codes is only used when DEBUG is define, add #if
guards around it in the same style as the rest of the file.
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
On the controlcenterd_36BIT_SDCARD config we get a warning about
prg_stage1_prepare being unused. Move the declaration closer to usage
and hide under the existing #if tests.
Cc: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Now that we can specify DT nodes that can be used in spl, mark
all necessary nodes as u-boot,dm-spl.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Now that we can specify DT nodes that can be used in spl, mark
all necessary nodes as u-boot,dm-spl.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
It has been observed that between PG1.0 and PG2.0/2.1 depending on
which device we boot from, we may see a different value here than is
documented in the TRM. Update the values for NAND and MMC1 based on
real life usage on each revision.
Signed-off-by: Tom Rini <trini@konsulko.com>
If north bridge selection register bit1 is clear, pins [10:8] are for
SDIO0 Resetn, Wakeup, and PDN while if bit1 is set, pins [10:8]are for
GPIO; when bit1 is clear, pin 9 and pin 10 can be used for uart2 RTSn
and CTSn, so bit1 should be added to uart2 group and it must be set
for both "gpio" and "uart" functions of uart2 group.
Signed-off-by: Ken Ma <make@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Wilson Ding <dingwei@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
As all x86 boards have been switched over to use DM USB, remove
CONFIG_USB_MAX_CONTROLLER_COUNT which is not used by DM USB.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
GPIO bank E pin 8 & 9 are used to control the on-board two USB ports
VBUS on/off. Let's configure them in the misc_init_r().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Xilinx changes for v2017.07
ZynqMP:
- config cleanup
- SD LS mode support
- psu_init* cleanup
- unmap OCM
- Support for SMC
Zynq:
- add ddrc to Kconfig
- add topic-miamilite board support
On ARCH_SUNXI we've been selecting these targets for a long time if
SUPPORT_SPL is set. However, Lichee Pi Zero is the first platform we've
added that does support SPL but does not build SPL and has exposed a
latent bug. Both of these symbols depend on SPL not SUPPORT_SPL, so we
need to update our select here otherwise we get a Kconfig warning.
Fixes: f02abb0608 ("sunxi: add support for Lichee Pi Zero")
Signed-off-by: Tom Rini <trini@konsulko.com>
The commit "fb82fe385173 configs: Resync defconfigs" resynced all config
files. This exposed two latent issues with the Gen3 boards in that we
had not been setting CONFIG_DEFAULT_FDT_FILE correctly and had not been
setting CONFIG_CMD_MMC. Fix both of these.
Fixes: fb82fe3851 ("configs: Resync defconfigs")
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
endian.h on FreeBSD system exist in sys/ subdirectory.
FreeBSD already have a fls function defined in strings.h which is included
in string.h if __BSD_VISIBLE is defined, as a check for this.
Signed-off-by: Emmanuel Vadot <manu@bidouilliste.com>
The driver currently does not reset bit 5 of the hostctl register even if
the MMC stack requests it. Then means that once a bus width of 8 is
selected it is not possible to change it back to 1. This breaks
'mmc rescan' which needs to start off with a bus width of 1.
The problem was surfaced by enabling CONFIG_DM_MMC_OPS on tegra. Without
this option the MMC stack fully reinits the driver on a 'mmc rescan'.
But with this option driver model does not re-probe a driver once it has
been probed once.
Fix the driver to honour the request.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Peter Chubb <peter.chubb@data61.csiro.au>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The topic-miamilite SoM contains a Zynq xc7z010 SoC, 1GB DDR3L RAM,
64MB dual-parallel QSPI NOR flash and clock sources.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Move the only use of CONFIG_SF_DUAL_FLASH to defconfig. This makes the
associated topic_miamiplus.h header obsolete, so remove that as well.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
If PMUFW version is not v0.3 then panic.
ZynqMP switch to CCF based clock driver which requires
PMUFW to be present at certain version.
This patch ensure that you use correct and tested PMUFW
binary.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reuse invoke_smc() routine which is already defined
instead of duplicating same at multiple places.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Define routines of mmio write and read functionalities
for zynqmp platform.
Also do not call SMC from SPL because SPL is running before ATF in EL3
that's why SMCs can't be called because there is nothing to call.
zynqmp_mmio*() are doing direct read/write accesses and this patch does
the same. PMUFW is up and running at this time and there is a way to talk
to pmufw via IPI but there is no reason to implement IPI stuff in SPL if
we need just simple read for getting clock driver to work.
Also make invoke_smc as global so that it can be reused in
multile places where ever possible.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add Kconfig option for ddr init as this might be required
in cases like ddr less systems where we want to skip ddrc
init and this option is useful for it.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Silicon v1 didn't support SD boot mode with level shifter.
Because system can't boot any error message is not shown
that's why comment is just a record if someone tries to debug it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
psu_init* contain sleep.h header which is not present in u-boot.
Instead of keep comment sleep.h in psu_init* it is easier to add empty
file which is included.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Drop include of netdev.h as it's a SATA driver not a network driver.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Decrease malloc size to 1MB from 256MB. Huge malloc
space is adding huge delay in mem_malloc_init() because
we are enabling CONFIG_SYS_MALLOC_CLEAR_ON_INIT
which clear the whole malloc space.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The boot_device argument to spl_boot_mode was massively added without
actually modifying the existing functions.
This commit actually makes use of the handed value, which is the same.
Signed-off-by: Jean-Francois Dagenais <jeff.dagenais@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
When enabling both SDHCI controllers, spl_mmc.c would actually choose
device sdhci0 even if booted from sdhci1 (boot_device). This is because
spl_mmc_get_device_index(boot_device) expects BOOT_DEVICE_MMC2[_2] in
order to return index 1 instead of 0.
The #if defined(...) statement is copied from board/xilinx/zynqmp/zynqmp.c
So the key to properly enabling both controllers as boot sources is
defining both CONFIG_ZYNQ_SDHCI0 and CONFIG_ZYNQ_SDHCI1 in your board's
include/configs/*.h.
Signed-off-by: Jean-Francois Dagenais <jeff.dagenais@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Adding more targets to repository requires some additional
changes not simply just adding config file, defconfig and dts.
This patch makes this process easier by building only
particular DTB which is selected via defconfig
that Makefile doesn't need to contain all dts files in the repository.
Reported-by: Nathan Rossi <nathan@nathanrossi.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
CPU_RELEASE_ADDR is used only when CONFIG_ARMV8_MULTIENTRY
is enabled. ZynqMP is running ATF which takes care about this
that's why no need to have this macro.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Make do_usb_mass_storage() static to fix the following sparse
warning:
cmd/usb_mass_storage.c:136:5: warning: symbol 'do_usb_mass_storage' was not declared. Should it be static?
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Use NULL for pointer to fix the following sparse warning:
cmd/usb_mass_storage.c:47:15: warning: Using plain integer as NULL pointer
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
With gcc-6 and later we see warnings that at91sam9263_udc_caps and
at91rm9200_udc_caps are unused.
Fixes: 620197670a ("usb: gadget: at91_udc: add at91_udc into U-Boot")
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Heiko Schocher <hs@denx.de>
In current code, after running the command of "usb start", the controller
will keep in otg mode and can't switch to host mode if not support
SNP/SRP capability. So add the property of "hnp-srp-disable" in the DTS
to config the contrller work in force mode of host.
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
There was for long time no activity in the mpx5xxx area.
We need to go further and convert to Kconfig, but it
turned out, nobody is interested anymore in mpc5xxx,
so remove it.
Signed-off-by: Heiko Schocher <hs@denx.de>
Secure boot targets that can be loaded from an SD card FAT partition
need to be called "MLO" on the filesystem, make a copy with this name
to clarify the correct image for SD card booting.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
This define isn't used anymore in the u-boot source tree, so we drop it
from the config header.
We drop it also from the 'config_whitelist.txt'
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
the BMP logo loading has become obsolete and is not used any more. So we
drop the support for it.
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
since commit
'd5abcf94c7123167725fc22ace342f0d455093c1' -
ti: boot: Register the MMC controllers in SPL in the same way as in u-boot
MMC boot on brxre1 board is broken, with this commit we make our board
working again.
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Adds CONFIG_SPL_USB_GADGET_SUPPORT and CONFIG_SPL_USBETH_SUPPORT.
Removes CONFIG_SPL_NAND_SUPPORT, CONFIG_SPL_MTD_SUPPORT, and CONFIG_SPL_YMODEM_SUPPORT
to free up space to fit in RAM.
Signed-off-by: Michael Welling <mwelling@ieee.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Marek Vasut <marex@denx.de>
NanoPi NEO2 is designed and developed by FriendlyElec
using the Allwinner 64-bit H5 SOC.
NanoPi Neo2 key features
- Allwinner H5, Quad-core 64-bit Cortex-A53
- 512MB DDR3 RAM
- microSD slot
- 10/100/1000M Ethernet
- Serial Debug Port
- 5V 2A DC MicroUSB power-supply
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Orangepi Win/WinPlus is an open-source single-board computer
using the Allwinner A64 SOC.
A64 Orangepi Win/WinPlus has
- A64 Quad-core Cortex-A53 64bit
- 1GB(Win)/2GB(Win Plus) DDR3 SDRAM
- Debug TTL UART
- Four USB 2.0
- HDMI
- LCD
- Audio and MIC
- Wifi + BT
- IR receiver
- 5V DC power supply
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Orangepi Zero Plus 2 is an open-source single-board computer
using the Allwinner h5 SOC.
H5 Orangepi Zero Plus 2 has
- Quad-core Cortex-A53
- 512MB DDR3
- micrSD slot and 8GB eMMC
- Debug TTL UART
- HDMI
- Wifi + BT
- OTG+power supply
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Whistler is an ancient Tegra 2 reference board. I may have been the only
person who ever used it with upstream software, and I've just recycled
the board hardware. Hence, it makes sense to remove support from software.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Enable DHCP command by default. Move environmental variable location
to before U-Boot image. Enlarge reserved mem for malloc. Update
maintainer.
Signed-off-by: York Sun <york.sun@nxp.com>
Commit a058052c changed the generic phy_reset() to clear all bits in
BMCR. This inevitably clears the ANEG bit. m88e1145 requires any
change to ANEG bit to be followed by a software reset. This seems to
be different from other PHYs. Implement read-modify-write procedure
for this PHY init.
Signed-off-by: York Sun <york.sun@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
commit 0650798824 ("board: am335x: Introduce scale_vcores")
updated voltages of each board based on efuse. It updated
beagle bone specific voltages under the condition board_is_bone().
But this is true only for BeagleBoneWhite. Due to which voltages
are not configured for BBB, BBW as wrong device is being probed.
So create a common function board_is_beaglebonex() which includes
am335x based beagle family. Use this for updating voltages.
Also remove extra if condition for selecting voltages which is
done later using a switch case and match usb current limit as
before the commit 0650798824.
Fixes: 0650798824 ("board: am335x: Introduce scale_vcores")
Reported-by: Emmanuel Vadot <manu@bidouilliste.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Use eMMC (instead of SD card) to store U-Boot environment. Use
"reserved" partition for U-Boot environment.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Lokesh Vutla <lokeshvuta@ti.com>
Increase the size of u-boot.img, so that it conforms with new DFU
configuration (see commit [1]).
[1] 7a53a1a811 ARM: ti: Update layout for MMC and eMMC (env and dfu)
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Increase the size of u-boot.img, so that it conforms with new DFU
configuration (see commit [1]).
[1] 7a53a1a811 ARM: ti: Update layout for MMC and eMMC (env and dfu)
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
refer in the README to tbots webpage, and delete
the README in tools/tbot, as the latest documentation
for tbot is on this webpage.
Signed-off-by: Heiko Schocher <hs@denx.de>
With Davinci I2C switching to device model, K2HK requires U-boot specific
device tree entries. This is only required for I2C 1 which is needed
extremely early during the boot process.
Fixes: 1743d040b1 ("ARM: keystone: Enable DM_I2C by default")
Reported-by: Yan Liu <yan-liu@ti.com>
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
The list of symbols listed in the error message for missing Kconfig
symbols is out of sync with the symbols actually tested.
Add the missing symbols and reorder their appearance to be in sync
with the #if statement for easier checking.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
commit 06a040a31b ("cmd: mtdparts: fix null pointer dereference in parse_mtdparts")
removed the initialization of a pointer variable, which is
subsequently used in a debug() call. This produces an uninitialized
variable warning, when compiling with DEBUG defined.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
relocate_code() calculates the relocation offset wrt. the symbol
__image_copy_start which happens to have the same value as
CONFIG_TEXT_BASE on most systems.
When creating an i.MX boot image with an integrated IVT it is
convenient to have CONFIG_TEXT_BASE point to the start of the IVT
that is prepended to the actual code. Thus CONFIG_TEXT_BASE will
differ from __image_copy_start, while the calculation
'gd->relocaddr - __image_copy_start' still gives the right relocation
offset.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Create exception stack in IRAM if available to facilitate debugging of
pre-relocation code by catching exceptions rather than stopping dead.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Adjust the program counter register to point to the failing
instruction depending on the exeption type.
This makes it easier to localize the offending instruction leading to
a fatal exception.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
The cp_delay() function was introduced because of a missing 'volatile'
attribute to the 'asm' statement in get_cr() which led to the 'mrc'
instruction in get_cr() being optimised out eventually.
This has been fixed in commit 53fd4b8c22 ("arm: mmu: Add missing volatile for reading SCTLR register")
but the bogus cp_delay() function which was introduced as a workaround
for the malfunctioning get_cr() was never removed.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Simplify baud rate register formula and use the oversampling
uart feature.
This code is aligned with what is implemented in kernel driver
drivers/tty/serial/stm32-usart.c since kernel v4.9.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Christophe KERELLO <christophe.kerello@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
stm32x7.c driver is dedicated for STM32F7.
In kernel, "st,stm32-usart" and "st,stm32-uart" compatible
strings are dedicated for STM32F4.
To keep U-boot and kernel aligned, replace the serial compatible
string from "st,stm32-usart", "st,stm32-uart" to
"st,stm32f7-usart", "st,stm32f7-uart" specific for STM32F7.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Christophe KERELLO <christophe.kerello@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
Assigning a variable to itself is not necessary. Drop this and also add a
check for malloc() failure.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Coverity (CID: 161418)
Fixes: 111bcc4 (rockchip: mkimage: pad the header to 8-bytes (using a 'nop') for RK3399)
The current implementation makes it look like the 'if (from_spl)' part is
dead code because these features are not enabled for sandbox. We could
enable it for sandbox_spl, but this is not done yet (it requires sharing
memory between SPL and U-Boot proper which is in fact supported).
It is probably nicer to avoid #ifdef anyway. Change it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Coverity (CID: 163244)
Fixes: 824bb1b (bootstage: Support SPL)
We know that uclass_get_device() and device_find_child_by_of_offset() do
not return NULL for dev when they succeeds but coverity does not. Add an
extra check to hopefully keep it happy.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Coverity (CID: 163246)
Fixes: 0753bc2 (dm: Simple Watchdog uclass)
We know that uclass_get_device() does not return NULL for dev when it
succeeds but coverity does not. Add an extra check to hopefully keep it
happy.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Coverity (CID: 163247)
Fixes: 0753bc2 (dm: Simple Watchdog uclass)
We know that fdt_getprop() does not return NULL when len is > 0 but
coverity does not. Add an extra check to keep it happy.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Coverity (CID: 163248)
We know that fdt_getprop() does not return NULL when len is > 0 but
coverity does not. Add an extra check to keep it happy.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Coverity (CID: 163249)
Fixes: bc80295b (fdt: Add get commands to fdt)
Since the parameter can be NULL we must be careful not to dereference it
in this case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Coverity (CID: 163250)
Fixes: 1043d0a0 (fdt: Add fdtgrep tool)
We should not use an open-coded value here. Use sizeof() instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Coverity (CID: 163252)
Fixes: 43c6bdd0 (edid: Add HDMI flag to timing info)
We know that uclass_get_device() does not return NULL for dev when it
succeeds but coverity does not. Add an extra check to hopefully keep it
happy.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Coverity (CID: 161690)
Fixes: 43b4156 (dm: sandbox: pwm: Add a basic pwm test)
There was for long time no activity in the 5xx area.
We need to go further and convert to Kconfig, but it
turned out, nobody is interested anymore in 5xx,
so remove it.
Signed-off-by: Heiko Schocher <hs@denx.de>
There was for long time no activity in the 8260 area.
We need to go further and convert to Kconfig, but it
turned out, nobody is interested anymore in 8260,
so remove it.
Signed-off-by: Heiko Schocher <hs@denx.de>
There was for long time no activity in the 8xx area.
We need to go further and convert to Kconfig, but it
turned out, nobody is interested anymore in 8xx,
so remove it (with a heavy heart, knowing that I remove
here the root of U-Boot).
Signed-off-by: Heiko Schocher <hs@denx.de>
One can obtain those variables using next commands:
$ fastboot getvar cpu
$ fastboot getvar secure
$ fastboot getvar board_rev
$ fastboot getvar userdata_size
Those variables are needed for fastboot.sh script.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
One can obtain those variables using next commands:
$ fastboot getvar cpu
$ fastboot getvar secure
$ fastboot getvar board_rev
$ fastboot getvar userdata_size
Those variables are needed for fastboot.sh script.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This patch reuses new option, which allows us to expose variables
from environment to "fastboot getvar" command. Those variables must be
of "fastboot.%s" format.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Using u-boot-2017.05 on i.MX6UL we ran into following problem:
Initially U-Boot could be started normally.
If we added one random command in configuration, the newly generated
image hung at startup (last output was DRAM: 256 MiB).
We tracked this down to a data abort within relocation (relocated_code).
relocated_code in arch/arm/lib/relocate.S copies 8 bytes per loop
iteration until the source pointer is equal to __image_copy_end.
In a good case __image_copy_end was aligned to 8 bytes, so the loop
stopped as suggested, but in an errornous case __image_copy_end was
not aligned to 8 bytes, so the loop ran out of bounds and caused a
data abort exception.
This patches solves the issue by aligning __image_copy_end to 8 byte
using the linker script related to arm.
I don't know if it's the correct way to solve this, so some review would
be very appreciated.
Currently we set the entry address in the psci_cpu_on function.
However R40 has a different register for this. This resulted in
an #ifdef / #else block in psci_cpu_on, which we avoided having
in the first place.
Move this part into a separate function, defined differently for
the R40 as opposed to the other single cluster platforms.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
When we don't have CONFIG_BLK defined we don't have a forward
declaration of struct udevice, and thus get a warning about it on
blk_get_from_parent(), which we only have when CONFIG_BLK is set. Move
the declaration of blk_get_from_parent() to be with the other CONFIG_BLK
parts.
Fixes 9f103b9cb5 ("dm: blk: Add a way to obtain a block device from ...")
Signed-off-by: Tom Rini <trini@konsulko.com>
The kwbimage utility fails to compile when LibreSSL is present on
the host system instead of OpenSSL. This one-line patch resolves
this.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
CONFIG_FAT_WRITE is imply'ed when CONFIG_CMD_FAT
is selected (see CONFIG_TI_COMMON_CMD_OPTIONS).
Dont disable it in defconfig so the imply takes
effect and 'fatwrite' is available for users.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
As only FIT image is supported now, this patch is to support loading
32-bit uImage, dtb and rootfs separately.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Like commit 3337e3af5d this enables suitable commands needed for booting
general purpose Linux distribution. This is required for example if we want
to use PXE or DHCP as default boot targets, symbols no longer enabled by
config_distro_defaults.h.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Update the board pinmux for AM572x-evm using latest PMT[1] and the
board files named am572x_gp_evm_A3a_sr2p0 and am572x_gp_evm_A2b_sr1p1
that were autogenerated on 30th January, 2017 by
"Ahmad Rashed <a-rashed@ti.com>" and "Tom Johnson <thjohnson@ti.com>".
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add poweroff description to Kconfig to make it selectable
via menuconfig.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Disable D-Cache is required when booting nommu Linux kernel.
(please see Linux kernel source "arch/arm/kernel/head-nommu.S")
U-Boot is enabled D-cache and I-Cache at startup.
However, it does not disable D-Cache before
booting nommu Linux kernel.
Therefore, I call dcache_disable()
when the CPU is ARMv7M to fix this problem.
Signed-off-by: Toshifumi NISHINAGA <tnishinaga.dev@gmail.com>
Refactor OMAP3/4/5 code so that we have only one get_device_type()
function for all platforms.
Details:
- Add ctrl variable for AM33xx and OMAP3 platforms (like it's done for
OMAP4/5), so we can obtain status register in common way
- For now ctrl structure for AM33xx/OMAP3 contains only status register
address
- Run hw_data_init() in order to assign ctrl to proper structure
- Remove DEVICE_MASK and DEVICE_GP definitions as they are not used
(DEVICE_TYPE_MASK and GP_DEVICE are used instead)
- Guard structs in omap_common.h with #ifdefs, because otherwise
including omap_common.h on non-omap4/5 board files breaks compilation
Buildman script was run for all OMAP boards. Result output:
arm: (for 38/616 boards)
all +352.5
bss -1.4
data +3.5
rodata +300.0
spl/u-boot-spl:all +284.7
spl/u-boot-spl:data +2.2
spl/u-boot-spl:rodata +252.0
spl/u-boot-spl:text +30.5
text +50.4
(no errors to report)
Tested on AM57x EVM and BeagleBoard xM.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
[trini: Rework the guards as to not break TI81xx]
Signed-off-by: Tom Rini <trini@konsulko.com>
Almost all users of CONFIG_AM33XX/AM43XX have been migrated. Finish
moving the last few over to Kconfig, and put all of the boards under the
appropriate Kconfig chocie now. This board choice is non-optional, so
remove that keyword on am33xx.
Signed-off-by: Tom Rini <trini@konsulko.com>
With this commit we can modify single values within an array of a dts
property.
This is useful if we have for example a pwm-backlight where we want to
modifiy the pwm frequency per u-boot script.
The pwm is described in dts like this:
backlight {
pwms = <0x0000002b 0x00000000 0x004c4b40>;
};
For changing the frequency, here the 3rd parameter, we simply type:
fdt set /backlight pwms <? ? 0x1E8480>;
For doing all this we:
- backup the property content into our 'SCRATCHPAD'
- only modify the array-cell if the new content doesn't start with '?'
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The build output can still produce unicode encoded output. But in
the buildman's log and err files we only want plain ASCII characters.
To handle all situations with unicode and non-unicode output, encode
the stdout and stderr strings to UTF-8 and afterwards to ASCII with
replacing all special characters.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Build tools like Make, gcc or binutils support localized output
or unicode encoded output dependent on the default system locale.
This is not useful for buildman, where we want reproducible
warning or error messages or where the output of binutils is
further processed.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The display on jerry is so fast that this option is not needed. Drop it so
that the display scrolls more smoothly.
Signed-off-by: Simon Glass <sjg@chromium.org>
If U-Boot is chain-loaded from a previous boot loader we must set up the
clocks the way U-Boot wants them. Add code for this. It will do nothing if
SPL has already done the job.
Signed-off-by: Simon Glass <sjg@chromium.org>
Detect with a previous boot loader has already set up the clocks and set
them up again so that U-Boot gets what it expects.
Signed-off-by: Simon Glass <sjg@chromium.org>
Shifted masks are the standard approach with rockchip since it allows
use of the mask without shifting it each time. Update the definitions and
the driver to match.
Signed-off-by: Simon Glass <sjg@chromium.org>
On reset the standby bit is clear, but if U-Boot is chain-loaded from
another boot loader it may be set. Clear it before starting up video so
that it works correctly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Squashed in 'rockchip: video: fix taking the VOP device out of standby':
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Add remove() methods for EDP and VOP so that U-Boot can shut down the
video on exit. This avoids leaving DMA running while booting Linux which
can cause problems if Linux uses the frame buffer for something else.
It also makes it clear what is needed to shut down video.
While we are here, make rkvop_enable() static.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Squashed in 'rockchip: video: fix taking the VOP device out of standby':
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Most Chromebooks support chain-loading U-Boot but instructions are
somewhat scattered. Add a README to hold this information within the
U-Boot tree. Also add the standard developer keys to simplify the
instructions, since they are small.
For now this only supports nyan-big.
Signed-off-by: Simon Glass <sjg@chromium.org>
The clock fix-up for tegra is still present in the code. It causes a
divide-by-zero bug after relocation when chain-loading U-Boot from
coreboot. Fix this by adding a check.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 7468676 (ARM: tegra: fix clock_get_periph_rate() for UART clocks)
At present CP15 init is disabled on tegra. Use the correct option so that
this init is performed on boot. This enables the instruction cache, for
example, which is critical to the machine running at full speed.
Signed-off-by: Simon Glass <sjg@chromium.org>
If U-Boot is the secondary boot loader, or has been run from itself, the
SOR may already be powered up. Powering it up again causes a hang, so
detect this situation and skip it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Enable this so we can roughly measure CPU performance. Also enable the
cache command to allow for timing.
Signed-off-by: Simon Glass <sjg@chromium.org>
For devices that need a delay between SPI transactions we seem to need an
additional delay before the first one if the CPU is running at full speed.
Add this, under control of the existing setting. At present it will only
be enabled with the Chrome OS EC.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present the interrupt does not work and the SPI bus runs much less
quickly than it should. Add settings to fix this.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present early clock init happens in SPL. If SPL did not run (because
for example U-Boot is chain-loaded from another boot loader) then the
clocks are not set as U-Boot expects.
Add a function to detect this and call the early clock init in U-Boot
proper.
Signed-off-by: Simon Glass <sjg@chromium.org>
This file does not report a few possible errors and one message is missing
a newline. Fix these.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
If CONFIG_ARMV7_LPAE is not defined we should make sure that the feature
is disabled. This can happen if U-Boot is chain-loaded from another boot
loader which does enable LPAE.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present if CONFIG_ARMV7_LPAE is defined then mmu_setup() will use
instructions which are invalid on ARMv4T. This happens on Tegra since it
has an ARMv4T boot CPU. Add a check for the architecture version to allow
the code to be built. It will not actually be executed by the boot CPU,
but needs to compile.
Signed-off-by: Simon Glass <sjg@chromium.org>
This option allows skipping the call to lowlevel() while still performing
CP15 init. Support this on ARM720T so it can be used with Tegra.
Signed-off-by: Simon Glass <sjg@chromium.org>
Rename command ls to fsls as its conflicting with
generic file systesm command ls and this is causing
compilation failure as below, if both are enabled
and this patch fixes it.
cmd/jffs2.o:(.u_boot_list_2_cmd_2_ls+0x0):
multiple definition of `_u_boot_list_2_cmd_2_ls'
cmd/fs.o:(.u_boot_list_2_cmd_2_ls+0x0):first defined here
scripts/Makefile.build:359: recipe for target 'cmd/built-in.o'
failed
make[1]: *** [cmd/built-in.o] Error 1
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
There is some inconsistency between uses of CONFIG_RTC_DS13xx and
CONFIG_SYS_RTC_DS13xx. Address this by dropping the "SYS" from
these variables.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
With xip booting configuration, we don't need to copy the next image
(U-Boot or linux xipimage) from flash to sdram area.
Flash memory organization is like this:
spl-U-Boot: u-boot-spl.bin : 0x0800_0000
U-Boot : u-boot-dtb.bin : 0x0800_8000
linux : xipImage : 0x0800_8000
It is also possible to have U-Boot binary & linux binaries configured at
different addresses of flash memory like U-Boot at 0x0800_8000 & linux
xipImage at 0x0800_4000. But in any case, spl-U-Boot needs to be compiled for
U-Boot as next binary with SPL_OS_BOOT option disabled.
By default, spl is configured to boot linux xipImage.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
With overrun enabled, serial port console freezes & stops receiving data with
overun error if we keep sending data.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Enable support for XIP (execute in place) of U-Boot or kernel image. There is
no need to copy image from flash to ram if flash supports execute in place.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Alexandru Gagniuc <alex.g@adaptrum.com>
This commit supports booting from stm32 internal nor flash. spl U-Boot
initializes the sdram memory, copies next image (e.g. standard U-Boot)
to sdram & then jumps to entry point.
Here are the flash memory addresses for U-Boot-spl & standard U-Boot:
- spl U-Boot : 0x0800_0000
- standard U-Boot : 0x0800_8000
To compile u-boot without spl: Remove SUPPORT_SPL configuration
(arch/arm/mach-stm32/Kconfig)
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
[trini: Rework Kconfig logic a bit]
Signed-off-by: Tom Rini <trini@konsulko.com>
Documents the externally visible functions shared between the VOP
drivers for the RK3288 and RK3399.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Documents the externally visible functions shared between the HDMI
drivers for the RK3288 and RK3399.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Fix the warning,
---8<---
CACHE: Misaligned operation at range [3fdffff0, 3fdffffc]
---<8---
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Extend DE2 driver with support for TVE driver, which will be added in
next commit. TVE unit expects data to be in YUV format, so CSC support
is also added here.
Note that HDMI driver has higher priority, so TV out is not probed if
HDMI monitor is detected.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In order to avoid future confusion with similary named files, rename
tve.c to tve_common.c. New name better represents the fact that this file
holds code which can be and will be shared between multiple drivers.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The addresses of the registers in TI TPS65217 are not continuous.
There is a gap between ENABLE(0x16) and DEFUVLO(0x18). No 0x17
register available.
Fixup the enum values by adding a 'reserved' placeholder to correct
the addresses higher than 0x17.
Series-to: Heiko Schocher <hs@denx.de>
Signed-off-by: Brock Zheng Techyauld Ltd <yzheng@techyauld.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
The driver provides regulator set/get voltage
enable/disable functions for lp87565 family of PMICs.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Add support to bind the regulators/child nodes with the pmic.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
We do not need to probe the block device here, so avoid doing so. The MMC
device itself must be active, but the block device can come later.
Signed-off-by: Simon Glass <sjg@chromium.org>
Make sure that we probe the block device before using it when reading
the environment.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Many devices support a child block device (e.g. MMC, USB). Add a
convenient way to get this device given the parent device.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add ddr voltage rail (dcdc3) configuration. Set the dcdc3
DDR supply to 1.35V.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Some boards like am437x-gp-evm require dcdc3 also to be configured
as it feeds on to ddr. Hence add the capability as well.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
R-Car Gen3 series have four SD card interfaces (SDHI0 to SDHI3),
two of which can also be used as MMC interfaces (SDHI2 and SDHI3).
This adds High-speed mode SD clock frequency between 25MHz and 50MHz,
8bit/4bit bus width, high capacity and low voltage device support.
Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
The existing test (patman --test) only covers basic checkpatch output.
We have had some problems with unicode processing and could use test
coverage for the various tags patman supports.
Add a new functional test which runs most of the patman flow on a few
test commits and checks that the results are correct.
See the documentation in the test for a description of what it does.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This is not a good variable name in Python because 'list' is a type. It
shows up highlighted in some editors. Rename it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Allow the add_maintainers parameter to be a list of maintainers, thus
allowing us to simulate calling the script in tests without actually
needing it to work.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
There is no need for this function to return the same object that was
passed in. Drop the return value.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Unicode characters may appear in input patches so we should not warn about
them. Drop this warning.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This is not a good variable name in Python because 'str' is a type. It
shows up highlighted in some editors. Rename it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The communication filter reads data in blocks and converts each block to
unicode (if necessary) one at a time. In the unlikely event that a unicode
character in the input spans a block this will not work. We get an error
like:
UnicodeDecodeError: 'utf8' codec can't decode bytes in position 1022-1023:
unexpected end of data
There is no need to change the input to unicode, so the easiest fix is to
drop this feature.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Don't mess with the email address when outputting them. Just make sure
they are encoded with utf-8.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This change encodes the CC list to UTF-8 to avoid failures on
maintainer-addresses that include non-ASCII characters (observed on
Debian 7.11 with Python 2.7.3).
Without this, I get the following failure:
Traceback (most recent call last):
File "tools/patman/patman", line 159, in <module>
options.add_maintainers)
File "[snip]/u-boot/tools/patman/series.py", line 234, in MakeCcFile
print(commit.patch, ', '.join(set(list)), file=fd)
UnicodeEncodeError: 'ascii' codec can't encode character u'\xfc' in position 81: ordinal not in range(128)
from Heiko's email address:
[..., u'"Heiko St\xfcbner" <heiko@sntech.de>', ...]
While with this change added this encodes to:
"=?UTF-8?q?Heiko=20St=C3=BCbner?= <heiko@sntech.de>"
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
In the case where a new build only decreases sizes and does not increase
any size we still want to report what functions have been dropped when
doing a bloat comparison.
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In os_dirent_get_typename() we are checking that type falls within the
known values of the enum os_dirent_t. With clang-3.8 testing this value
as being >= 0 results in a warning as it will always be true. This
assumes of course that we are only given valid data. Given that we want
to sanity check the input, we change this to check that it falls within
the range of the first to the last entry in the given enum.
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
On ARM v7M, the processor will return to ARM mode when executing blx
instruction with bit 0 of the address == 0. Always set it to 1 to stay in thumb
mode.
At present, it is applied only for raw U-Boot. This patch moves it to just
before booting next image. This way armv7m will be in thumb mode for any image
like raw or image with header like zImage or standard U-Boot.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
The SoPine is a SoM by Pine64, with an Allwinner A64 SoC, a LPDDR3 DRAM
chip, an AXP803 PMIC, a SPI NOR Flash and a MicroSD slot. The card
detect pin of the MicroSD slot is broken, however, it doesn't matter as
the design of SoPine didn't allow hot-swapping the MicroSD card (The
MicroSD slot is at the back of the SoM, and when the SoM is installed on
the baseboard, it's nearly impossible to remove the MicroSD).
The official baseboard of it is a board with nearly the same connectors
with the original Pine64+, with the MicroUSB power jack replaced, and
at the position of MicroSD slot a eMMC module slot is added.
Add support for SoPine with the official baseboard by adding its
defconfig file. It still uses the device tree of Pine64, however, it
will change after a proper device tree of SoPine with baseboard is
accepted by Linux mainline.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
[Update board/sunxi/MAINTAINERS]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
As we added LPDDR3 support in the former patch, we need a set of timing
info to really enable it.
Add the timing info used by stock boot0.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Some A64 boards (SoPine and Pinebook production batch) use LPDDR3 DRAM
chips.
Add support for LPDDR3 DRAM in the DesignWare-like DRAM controller code.
Real LPDDR3 chips' support is not added yet in this commit.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
As we have already support for the DesignWare DRAM controller and the
integrated DDR2 chip of V3s, let's enable the SPL support for V3s.
This patch also contains the default DRAM configuration for V3s.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
The DesignWare-like DRAM code used to set the controller defaultly to
single rank mode, which makes it not able to detect the second rank.
Set the default value to dual rank, thus the rank detection code can
work and finally the rank setting will be the correct value.
Currently we know little about the dual-rank on R40, and the usage
of A15 address line seems to be breaking dual-rank support. The only R40
board currently available (Sinovoip Banana Pi M2 Ultra) uses A15 rather
than dual-rank, thus we cannot do research for it. So dual rank detection
is temporarily disabled on R40.
This change is tested on a Orange Pi One (H3, single rank), a Pine64+
2GiB version (A64, single rank) , a Pinebook early prototype with DDR3
(A64, dual rank) and a SoPine with some LPDDR3 patch (A64, dual CS pins
on one chip).
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
DRAM chip varies, and one code cannot satisfy all DRAMs.
Add options to select a timing set.
Currently only DDR3-1333 (the original set) is added into it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
The DesignWare DRAM controller used by H3 and newer SoCs use a bit to
identify whether the DRAM is half-width.
As H3 itself come with 32-bit DRAM, the two modes of the bit used to be
named "MCTL_CR_32BIT" and "MCTL_CR_16BIT", but for SoCs with 16-bit DRAM
they're really 8-bit and 16-bit.
Rename the bit's macro, and also rename the variable name in
dram_sun8i_h3.c.
This commit do not add 16-bit DRAM controller support, but the support
will be introduced in next commit.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like
DesignWare DRAM controller, which do not have official free DRAM
initialization code, but can use modified dram_sun8i_h3.c.
Add a invisible option for easier DRAM initialization code reuse.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
NanoPi M1 Plus is designed and developed by FriendlyElec
for professionals, enterprise users, makers and hobbyists
using the Allwinner H3 SOC.
NanoPi M1 Plus key features
- Allwinner H3, Quad-core Cortex-A7@1.2GHz
- 1GB DDR3 RAM
- 8GB eMMC
- microSD slot
- 10/100/1000M Ethernet
- Serial Debug Port
- 5V 2A DC power-supply
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Here is additional rk3368 and rk3399 support, rv1108 support,
refactoring HDMI video (brought in from Anatolij's tree to resolve
conflicts), some mkimage fixes and a few other things.
With video output support for the RK3399-Q7 (Puma) available, we want
CMD_BMP enabled and the support for 16bit, 24bit and 32bit BMPs
defined.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Version-changes: 2
- enable SYS_WHITE_ON_BLACK via defconfig
Reviewed-by: Simon Glass <sjg@chromium.org>
The last set of rebases had dropped the 'grf' field from the common
rk_vop. Add this back to un-break the build (and driver).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This commit enables the RK3399 HDMI TX, which is very similar to the
one found on the RK3288. As requested by Simon, this splits the HDMI
driver into a SOC-specific portion (rk3399_hdmi.c, rk3288_hdmi.c) and
a common portion (rk_hdmi.c).
Note that the I2C communication for reading the EDID works well with
the default settings, but does not with the alternate settings used on
the RK3288... this configuration aspect is reflected by the driverdata
for the RK3399 driver.
Having some sort of DTS-based configuration for the regulator
dependencies would be nice for the future, but for now we simply use
lists of regulator names (also via driverdata) that we probe.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
To prepare for the addition of RK3399 HDMI support, the HDMI driver is
refactored and broken into a chip-specific and a generic part. This
change adds the internal interfaces, makes common/reusable functions
externally visible and splits the RK3288 driver into a separate file.
For the probing of regulators, we reuse the infrastructure created
during the VOP refactoring... i.e. we simply call into the helper
function defined for the VOP.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The Linux driver now supports higher mpixelclock settings.
Add these to rockchip_phy_config[] and rockchip_mpll_cfg[].
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit adds a driver for the RK3399 VOPs capable and all the
necessary plumbing to feed the HDMI encoder. For the VOP-big, this
correctly tracks the ability to feed 10bit RGB data to the encoder.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
To prepare for adding the RK3399 VOP driver (which shares most of its
registers and config logic with the RK3228 VOP), this change refactors
the driver and splits the RK3288-specific driver off.
The changes in detail are:
- introduces a data-structure for chip-specific drivers to register
features/callbacks with the common driver: at this time, this is
limited to a callback for setting the pin polarities (between the
VOP and the encoder modules) and a flag to signal 10bit RGB
capability
- refactors the probing of regulators into a helper function that
can take a list of regulator names to probe and autoset
- moves the priv data-structure into a (common) header file to be
used by the chip-specific drivers to provide base addresses to
the common driver
- uses a callback into the chip-specific driver to set pin polarities
(replacing the direct register accesses previously used)
- splits enabling the output (towards an encoder) into a separate
help function withint the common driver
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This introduces two new Kconfig options that configure the maximum
allowable framebuffer size (i.e. the memory reservation/allocation for
the framebuffer):
- VIDEO_ROCKCHIP_MAX_XRES
- VIDEO_ROCKCHIP_MAX_YRES
The resulting memory allocation will cover 4 byte per pixel for these
resolutions.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
For consistency sake (and as we are about to add new options to this
file), reformat the help for VIDEO_ROCKCHIP.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
For the RK3399-Q7, we need spl_board_init to be called during SPL
startup to set up the pinmux for the debug UART. Enable SPL_BOARD_INIT
via defconfig to ensure this function is in fact called.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
RK3288_TXCLK_DLY_ENA_GMAC_ENABLE, in GRF_SOC_CON3, is supposed to be bit
0xe and not 0xf. Otherwise, it is RGMII RX clock delayline enable and
introduces random delays and data lose.
This commit fixes the issue by replacing RK3288_TXCLK_DLY_ENA_GMAC_ENABLE
with the right shift.
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds the DDR3-1866 timing via its own DTS and wires it up. This
(currently) is not the default timing for the RK3399-Q7 and should be
selected explicitly via the config (CONFIG_DEFAULT_DEVICE_TREE).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
This adds the DDR3-1333 timing via its own DTS and wires it up. This
is not the default timing for the RK3399-Q7 and should be selected
explicitly via the config (CONFIG_DEFAULT_DEVICE_TREE).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
To better support different RAM timings (DDR3-1333 and DDR3-1866 are
assembly options for the RK3399-Q7), this refactors the DTS support
and renames the default DTS variant from rk3399-puma to
rk3399-puma-ddr1600:
- changes the rk3399-puma DTS into a board-specific DTSI by removing
the inclusion of the DRAM timings
- adds a new rk3399-puma-ddr1600.dts, which includes the (new) common
board DTSI and the DDR3-1600 timing DTSI
- wires this up from arch/arm/dts/Makefile and configs/puma-rk3399_defconfig
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
The Linux DTS for the RK3399-Q7 has moved with the times... resync
against it to ensure a consistent configuration.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit enables HDMI output in the DTS by adding the necessary
nodes to vopl/vopb and by adding the HDMI node.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The regs_otg field in uintptr_t of the platform data structure for
dwc2-otg has thus far been an unsigned int, but will eventually be
casted into a void*.
This raises the following error with GCC 6.3 and buildman:
../drivers/usb/gadget/dwc2_udc_otg.c: In function 'dwc2_udc_probe':
../drivers/usb/gadget/dwc2_udc_otg.c:821:8: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
reg = (struct dwc2_usbotg_reg *)pdata->regs_otg;
^
This changes regs_otg to a uintptr_t to ensure that it is large enough
to hold any valid pointer (and fix the associated warning).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
With HDMI output for the RK3399 working, this update the RK3399-Q7
(Puma) defconfig for the new functionality:
1. enables PMIC command (to check if the HDMI voltages are correct)
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
2. enables video-output (via HDMI)
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
3. turns on the 'dcache'-command (for a dcache flush) for our QA to
fill the framebuffer using 'mw.l'
+CONFIG_CMD_CACHE=y
4. turns on the 'bmp'-command
+CONFIG_CMD_BMP=y
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
When enabling CONFIG_DISPLAY_ROCKCHIP_HDMI, compile-time warning for
the following implicitly defined functions are raised due to a missing
include directive:
drivers/video/rockchip/rk_hdmi.c: In function 'rk_hdmi_probe':
drivers/video/rockchip/rk_hdmi.c:150:2: warning: implicit declaration of function 'rk_setreg' [-Wimplicit-function-declaration]
rk_setreg(&priv->grf->soc_con6, 1 << 15);
^~~~~~~~~
drivers/video/rockchip/rk_hdmi.c:153:2: warning: implicit declaration of function 'rk_clrsetreg' [-Wimplicit-function-declaration]
rk_clrsetreg(&priv->grf->soc_con6, 1 << 4,
^~~~~~~~~~~~
This change fixes this by including <asm/hardware.h> in rk_hdmi.c.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
The usb_gadget_handle_interrupts()-function is already implemented by
drivers/usb/gadget/dwc2_udc_otg.c, so we need to avoid defining it
in the evb-rk3328.c board-specific file.
This change fixes the following build error (from buildman):
drivers/usb/gadget/built-in.o: In function `usb_gadget_handle_interrupts':
build/../drivers/usb/gadget/dwc2_udc_otg.c:850: multiple definition of `usb_gadget_handle_interrupts'
board/rockchip/evb_rk3328/built-in.o:build/../board/rockchip/evb_rk3328/evb-rk3328.c:37: first defined here
make[1]: *** [u-boot] Error 1
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add the compatible "rockchip,rk3328-xhci" in match table
for rk3328 to probe xhci controller. Use fixed regulator
to control the voltage of vbus and turn off vbus when
usb stop.
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add basic support for rv1108 evb, whith this patch we
can boot into u-boot console.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
RV1108 is embedded with an ARM Cortex-A7 single core and a DSP core
from Rockchip. It is designed for varies application scenario such
as car DVR, sports DV, secure camera and UAV camera.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add support to mkimage for rv1108 soc, the max
spl code size for rv1108 is 6kb, and the spl
code should be packed by rksd, wether boot from
emmc or spi nor flash.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
For the RK3399-Q7 module, we use full OF_CONTROL (i.e. not
OF_PLATDATA) for SPL. In this configuration, the rockchip_dw_mmc
driver retrieves one of its clocks via clk_get_by_name and fails if
this is not possible. For this reason, we can not filter clock-names
from the device-tree nodes used for the configuration of the SPL
stage.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The RK3399-Q7 exposes I2C on its edge connector and uses it as one of
the interfaces towards the on-module STM32 (for the emulated RTC and
fan-controller).
Enable I2C and CMD_I2C support in the defconfig.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
On the RK3399-Q7, we need PMIC support (for the RK808) to enable HDMI
output, as one of the required powerrails is not enabled on boot.
For this, we need to enable the RK808 driver.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Version-changes: 3
- With the recent upstream changes to the RK808 (PMIC) driver, the
associated configuration options have been renamed to RK8XX. Track
this change in the RK3399-Q7 defconfig.
Reviewed-by: Simon Glass <sjg@chromium.org>
On the RK3399-Q7, the on-module USB3 hub is held in reset at boot-up
to save power and needs to be woken up using GPIO4A3.
Note that this is not a negated reset-signal (due to a level shifter
being needed for this signal anyway), but a negated enable-signal:
to enable, we need to output LOW (i.e. 0)... so we mark this as an
ACTIVE_LOW signal.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
With the validation done for DDR3-1866 (i.e. 933 MHz bus clock), we
can now add the timings (rk3399-sdram-ddr3-1866.dtsi) for boards built
with the DDR3-1866 option.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Revise the loop watching for a timeout on obtaining a DRAM PHY lock to
clearly state a timeout in milliseconds and use get_timer (based on
the ARMv8 architected timer) to detect a timeout.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This change restores the earlier setting of init_boot_size to include
the maximum area covered by the the boot ROM of each chip for resolve
issues with back-to-bootrom functionality reported by Kever and Heiko.
To ensure that we don't run into the same issue again in the future,
I have updated the comments accordingly and added a reference to the
mailing list archive (there's some very helpful info from Andy Yan
that provides background on the BootROM requirements regarding these
fields).
See https://lists.denx.de/pipermail/u-boot/2017-May/293267.html for
some background (by Andy Yan) of how the BootROM processes this field.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The rockchip image generation was previously missing the ability to
verify the generated header (and dump the image-type) without having
to resort to hexdump or od. Experience in our testing has showed it
to be very easy to get the rkspi and rksd images mixed up and the
lab... so we add the necessary support to have dumpimage tell us
what image type we're dealing with.
This change set adds the verify_header and print_header capability
to the rksd/rkspi image drivers (through shared code in rkcommon).
As of now, we only support images fully that are not RC4-encoded for
the SPL payload (i.e. header1 and payload). For RC4-encoded payloads,
the outer header (header0) is checked, but no detection of whether
this is a SD/MMC or SPI formatted payload takes place.
The output of dumpsys now prints the image type (spl_hdr), whether it
is a SD/MMC or SPI image, and the (padded) size of the image:
$ ./tools/dumpimage -l ./spl.img
Image Type: Rockchip RK33 (SD/MMC) boot image
^^^^^^ SD/MMC vs. SPI indication
^^^^ spl_hdr indicated by the image
Data Size: 79872 bytes
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Update maintainer to Kever Yang for William Zhang is not
work for this board now.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Directory board/rockchip/ are all boards for Rockchip SoCs,
so add it to maintained entry.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Send patch to Kever Yang instead of Lin Huang for Rockchip patches,
for Lin is not always working on upstream U-Boot.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Changed , to : in subject:
Signed-off-by: Simon Glass <sjg@chromium.org>
Add config of max root ports and add config to enable xhci
controller.
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add defconfig for usb and ehci and ohci controller, config maximal
number of ports of the root hub for ohci driver.
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In rk3328, some function pin may have more than one choice, and muxed
with more than one IO, for example, the UART2 controller IO,
TX and RX, have 3 choice(setting in com_iomux):
- M0 which mux with GPIO1A0/GPIO1A1
- M1 which mux with GPIO2A0/GPIO2A1
- usb2phy which mux with USB2.0 DP/DM pin.
We should not decide which group to use in pinctrl driver,
for it may be different in different board, it should goes to board
file, and the pinctrl file should setting correct iomux depends on
the com_iomux value.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Move GRF register bit definition into GRF header file, remove
'GRF_' prefix and add 'GPIOmXn_' as prefix for bit meaning.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
U-Boot prefer to use MASKs with SHIFT embeded, clean the Macro
definition in grf header file and pinctrl driver.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
- hclk/pclk_div range should use '<=' instead of '<'
- use GPLL for pd_bus clock source
- pd_bus HCLK/PCLK clock rate should not bigger than ACLK
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Embeded the shift in mask MACRO definition in cru header file
and clock driver.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
PX5 EVB is designed by Rockchip for automotive field
with integrated CVBS (TP2825) / MIPI DSI / CSI / LVDS
HDMI video input/output interface, audio codec ES8396,
WIFI / BT (on RTL8723BS), Gsensor BMA250E and light&proximity
sensor STK3410.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The GeekBox is a TV box from GeekBuying, based on an MXM3 module.
The module can be used with base boards such as the GeekBox Landingship.
This adds basic support to chain-load U-Boot from Rockchip's miniloader.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Sheep board is designed by Rockchip as a EVB for rk3368.
Currently it is able to boot a linux kernel and system
to console with the miniloader run as fist level loader.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
The RK3368 is an octa-core Cortex-A53 SoC from Rockchip.
This adds basic support to chain-load U-Boot from Rockchip's
miniloader.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add driver to support iomux setup for the most commonly
used peripherals on rk3368.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add driver to setup the various PLLs and peripheral
clocks on the RK3368.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Since priv->init_voltage is an unsigned integer it can never be
negative. So the current code fails to detect a missing
'regulator-init-microvolt' property and instead misconfigures the
PWM device. Fix this by making the relevant members of
'struct pwm_regulator_info' signed integers.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Till now get_ldo_reg did a return &rk808_ldo[num - 1]; to return
the ldo register offset but didn't take into account that its
calling functions already created the ldo as ldo = dev->driver_data - 1.
This resulted in the setting for ldo8 writing to the register of ldo7
and so on. So fix this and get the correct ldo register data.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
With everything in place (i.e. the new efuse driver, the clk-support
for the non-secure efuse block, and the board-specific functions to
derive 'serial#' from the cpu-id within the efuses), enable this in
the RK3399-Q7 defconfig.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Generate a MAC address based on the cpuid available in the efuse
block: Use the first 6 byte of the cpuid's SHA256 hash and set the
locally administered bits. Also ensure that the multicast bit is
cleared.
The MAC address is only generated and set if there is no ethaddr
present in the saved environment.
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
With our efuse driver for the RK3399 ready, we can add the
board-specific code that consumes the cpuid from the efuse block and
postprocesses it into the system serial (using the same CRC32 based
derivation as in Linux).
We expose the cpuid via two distinct environment variables:
serial# - the serial number, as derived in Linux
cpuid# - the raw 16 byte CPU id field from the fuse block
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
This adds a simple driver for reading the efuse block of the RK3399.
It should be easy enough to add drivers for other devices (e.g. the
RK3328, RK3368, etc.) by passing the device details via driver_data.
Unlike the kernel driver (using the nvmem subsystem), we don't expose
the efuse as multiple named cells, but rather as a linear memory that
can be read using misc_read(...).
The primary use case (as of today) is the generation of a 'serial#'
(and a 'cpuid#') environment variable for the RK3399-Q7 (Puma)
system-on-module.
Note that this adds a debug-only (i.e. only if DEBUG is defined)
command 'rk3399_dump_efuses' that dumps the efuse block's content.
N.B.: The name 'rk3399_dump_efuses' was intentionally chosen to
include a SoC-name (together with a comment in the function) to
remind whoever adds support for additional SoCs that this
function currently makes assumptions regarding the size of the
fuse-box based on the RK3399. The hope is that the function is
adjusted to reflect any changes resulting from generalising the
driver for multiple SoCs and is then renamed.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Some host like SD and eMMC may use DMA to transter data to SRAM,
set memory to non-secure to make sure the address can be accessed.
The security of SRAM in OS suppose to initialized in ATF bl31, and
the SPL is before the bl31.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
The option is named PINCTRL_ROCKCHIP_RK3399 not ROCKCHIP_RK3399_PINCTRL.
Set the correct option.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
This patch fixes the below warning by typecasting it properly
fs/ubifs/ubifs.c: In function 'ubifs_load':
fs/ubifs/ubifs.c:942:29: warning: cast to pointer from integer
of different size [-Wint-to-pointer-cast]
err = ubifs_read(filename, (void *)addr, 0, size, &actread);
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
The branch instruction only has an 11-bit relative target address, which
is sometimes not enough.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Rather than change asm files that come from Linux, add the symbols
to Kconfig. Since one of the symbols is for thumb2 builds, make
CPU_V7M always select them.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
If CONFIG_CLK flag is not set, compilation raises the
following error message:
drivers/ram/stm32_sdram.c: In function 'stm32_fmc_probe':
drivers/ram/stm32_sdram.c:154:2: error: 'ret' undeclared (first use in this function)
ret = stm32_sdram_init(dev);
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
cc: Vikas Manocha <vikas.manocha@st.com>
Mark explicitly bss sections to not be loaded at
run time.
The similar patch was done in past by:
"Fix linker scripts: add NOLOAD atribute to .bss/.sbss sections"
(sha1: 64134f0112)
The problem is related to latest toolchain added to Xilinx
v2017.1 design tools where jtag loader is trying to access
ununitialized memory.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add support for calling poweroff in case of psci is wired.
Based on the same solution as is used for reset.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Move all logic in to fwcall.c as other ARMs implement poweroff
via PMIC]
Signed-off-by: Tom Rini <trini@konsulko.com>
With clang-3.8 we see warnings like:
cmd/ethsw.c:304:6: warning: implicit conversion from
enumeration type 'enum ethsw_keyword_opt_id' to different enumeration type
'enum ethsw_keyword_id' [-Wenum-conversion]
ethsw_id_pvid_no,
^~~~~~~~~~~~~~~~
Because we have one enum for ethsw_keyword_id and a second enum for
ethsw_keyword_opt_id. This ends up being safe as ethsw_keyword_opt_id
explicitly starts after ethsw_keyword_id enum ends. Disable the
warning here rather than collapse these into one enum and rely on
comments to denote where optional keywords begin.
Cc: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Unit tests require mallinfo which in turn requires DEBUG on
dlmalloc to be enabled.
The dependancy on CONFIG_SANDBOX is wrong.
Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The dtb blob section must always be present in the resulting image.
Either if OF_EMBEDED is used or if unit tests include dtb blobs.
Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
We only want to apply files such as 'omap5-u-boot.dtsi', which resides
in arch/arm/dts/ to other files in arch/arm/dts/ and not say
test/overlay/. Rework the make logic to check for -u-boot.dtsi files in
the same directory as their target dts.
Cc: Simon Glass <sjg@chromium.org>
Reported-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The problems with the current DFU layout are:
MMC: The space allocated for u-boot is too small for the latest u-boot
(>750KB). We need to increase it. eMMC uses a much bigger area (2MB).
eMMC: region "u-boot.img.raw" overlaps the environment area and the region
"spl-os-image.raw".
both: region "spl-os-image.raw" is quite small and can't handle android
kernels
Fixing this requires growing some regions and moving others.
Care has been taken to leave some room for further growth of
"spl-os-args.raw".
Also the "env" now appears in the dfu so that it's apparent that the
region is not free space that can be used to grow "u-boot.img.raw".
The MLO region is 0x100 sectors wide but the 0x100 are unused in case the
MLO comes too overflow this areas.
The total space allocated for those raw binaries is 16MB, of which 13+MB
are reserved for the kernel image.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Much of the entries here simply depend on SPL (or TPL). Instead of this
redundancy use if SPL / if TPL to guard the rest of the choices and only
show them when we have the relevant option enabled.
Signed-off-by: Tom Rini <trini@konsulko.com>
At present bootstage only supports U-Boot proper. But SPL can also consume
boot time so it is useful to have the record start there.
Add bootstage support to SPL. Also support stashing the timing information
when SPL finishes so that it can be picked up and reported by U-Boot
proper. This provides a full boot time record, excluding only the time
taken by the boot ROM.
Signed-off-by: Simon Glass <sjg@chromium.org>
There are a few places that should use const *, such as
bootstage_unstash(). Update these to make it clearer when parameters are
changed.
Signed-off-by: Simon Glass <sjg@chromium.org>
We should return a proper error number instead of just -1. This helps the
caller to determine what when wrong. Update a few functions to fix this.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present we don't allow use of bootstage before driver model is running.
This means we cannot time the init of driver model itself.
Now that bootstage requires its own board-specific timer, we can move its
init to earlier in the sequence, both before and after relocation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some boards cannot access pre-relocation data after relocation. Reserve
space for this and copy it during preparation for relocation.
Signed-off-by: Simon Glass <sjg@chromium.org>
We can now use the record count to determine whether a record is valid or
not. Drop the test for a zero time.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present bootstage has a large array with all possible bootstage IDs
recorded. It adds times to the array element indexed by the ID. This is
inefficient because many IDs are not used during boot. We can save space
by only recording those IDs which actually have timestamps.
Update the array to use a record count, which increments with each
addition of a new timestamp. This takes longer to record a time, since it
may involve an array search. Such a search may be particularly expensive
before relocation when the CPU is running slowly or the cache is off. But
at that stage there should be very few records.
Signed-off-by: Simon Glass <sjg@chromium.org>
There are several code style and comment nits. Fix them and also remove
the comment about passing bootstage to the kernel being TBD. This is
already supported.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present bootstage uses the data section of the image to store its
information. There are a few problems with this:
- It does not work on all boards (e.g. those which run from flash before
relocation)
- Allocated strings still point back to the pre-relocation data after
relocation
Now that U-Boot has a pre-relocation malloc() we can use this instead,
with a pointer to the data in global_data. Update bootstage to do this and
set up an init routine to allocate the memory.
Now that we have a real init function, we can drop the fake 'reset' record
and add a normal one instead.
Note that part of the problem with allocated strings remains. They are
reallocated but this will only work where pre-relocation memory is
accessible after relocation.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present we provide a default version of this function for use by
bootstage. However it uses the system timer and therefore likely requires
driver model. This makes it impossible to time driver-model init.
Drop the function and require boards to provide their own. Add a sandbox
version also. There is a default implememtation in lib/time.c for boards
which use CONFIG_SYS_TIMER_COUNTER.
Signed-off-by: Simon Glass <sjg@chromium.org>
The bootelf command could, but does not, pass additional arguments along
on the command line. Make do_bootelf consume bootelf/flags/address as
needed and then pass along anything else to the ELF application we've
launched.
Reported-by: Thomas Doerfler <thomas.doerfler@embedded-brains.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
This deassert counter allow to manage "shared" reset lines
encountered in some specific case. On STiH410 SoC, DWC3,
EHCI and OHCI are all using a respective PHY, but all of
these PHYs shared a "global" reset.
Currently, during command "usb stop", all host controller are
stopped (XHCI, EHCI and OHCI). XHCI is first shutdowned, which
means that PHY global reset is asserted. Then EHCI is shutdowned,
but its PHY reset has already been asserted which make handshake()
call failed in ehci_shutdown().
This counter allows to really assert a reset lines only when the
"last" user is asserting it.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
All tests in test_hush_if_test depends on hush parser to be
present. This patch simplify test dependencies by using global
pytestmark.
Reported-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
The SD card automatic installation system depends on the default
environment of the previous U-Boot.
Add the missing environment variables.
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Reviewed-by: Tom Rini <trini@konsulko.com>
Supported boot devices are raw QSPI and raw SD card.
Add support for a FAT16/32 file system for SD card.
The SOC's boot ROM only supports FAT file system.
Therefore remove the SPL support for the EXT file system.
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Reviewed-by: Tom Rini <trini@konsulko.com>
We should not have an arch-specific header file in common.h. Adjust the
board files a little so it is not needed, and drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
We should not have an arch-specific header file in common.h. Instead, use
the asm/hardware.h header to provide the required declarations, and drop
the common.h changes.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
These declarations should not be in common. Remove those that are not
needed and move the others to an arch-specific location.
Signed-off-by: Simon Glass <sjg@chromium.org>
The declarations should not be in common.h. Move them to the arch-specific
headers.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)]
Signed-off-by: Tom Rini <trini@konsulko.com>
Set up a new asm/ppc.h header file to hold this arch-specific stuff. It
should not be in common.h. It probably should be refactored to use
asm/arch instead, but that is a job for the maintainer.
Signed-off-by: Simon Glass <sjg@chromium.org>
With a small tweak we can avoid including these files for all boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
At present common.h includes various ARM-specific headers. In preparation
for dropping this, add a few explicit declarations.
Signed-off-by: Simon Glass <sjg@chromium.org>
Rather than relying on common.h to provide this include, which is going
away at some point, include it explicitly in each file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Rather than including this arch-specific header file in common.h, include
it from within nds32's u-boot.h header.
Signed-off-by: Simon Glass <sjg@chromium.org>
Rather than including this arch-specific header file in common.h, include
it from within mips's u-boot.h header.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Rather than including this arch-specific header file in common.h, include
it from within arm's u-boot.h header.
Also drop the comment about something to be fixed. It has been there
forever and it is not clear what it means.
Signed-off-by: Simon Glass <sjg@chromium.org>
Rather than including this arch-specific header file in common.h, include
it from within x86's u-boot.h header.
Also drop the comment about something to be fixed. It is not clear what
needs fixing.
Signed-off-by: Simon Glass <sjg@chromium.org>
Rather than including this arch-specific header file in common.h, include
it from within sandbox's u-boot.h header.
Also drop the comment about something to be fixed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Rather than including this arch-specific header file in common.h, include
it from within arc's u-boot.h header.
Signed-off-by: Simon Glass <sjg@chromium.org>
The symbol CONFIG_TI81XX is used for the parts that are common to the
TI816x and TI814x SoCs and are not part of CONFIG_ARCH_OMAP2PLUS nor
CONFIG_AM33XX. It however has so few uses that we can just modify the
code to check for both and drop the symbol. The symbols CONFIG_TI816X
and CONFIG_TI814X are for the repective SoCs.
Signed-off-by: Tom Rini <trini@konsulko.com>
- Switch to using <configs/ti_armv7_omap.h> and family. This lets us
drop lots of custom defines.
- Ensure that our default environment uses DEFAULT_LINUX_BOOT_ENV so
that Linux will boot correctly.
- Enable CONFIG_DISTRO_DEFAULTS
- Switch to using CONFIG_OF_CONTROL
- Various other cleanups to match other SoCs in the family line.
Signed-off-by: Tom Rini <trini@konsulko.com>
On this platform, we can trace a general failure to boot to enabling /
disabling this option. When this is enabled, we go off into the
weeds during SPL and are unable to talk with the SD card and
mmc_initialize() fails.
Signed-off-by: Tom Rini <trini@konsulko.com>
The ti816x/am389x SoC is the first generation in what U-Boot calls the
"am33xx" family. In the first generation of this family the DDR
initialization sequence is quite different from all of the subsequent
generations. Whereas with ti814x (second generation) we can easily work
the minor differenced between that and am33xx (third generation), our
attempts to do this for ti816x weren't sufficient. Rather than add a
large amount of #ifdef logic to make this different sequence work we add
a new file, ti816x_emif4.c to handle the various required undocumented
register writes and sequence and leverage what we can from
arch/arm/mach-omap2/am33xx/ddr.c still. As DDR2 has similar problems
today but I am unable to test it, we drop the DDR2 defines from the code
rather than imply that it works by leaving it. We also remove a bunch
of other untested code about changing the speed the DDR runs at.
Signed-off-by: Tom Rini <trini@konsulko.com>
Rather than have a long and if check in the Makefile, mark the default
lowlevel_init function as weak (as we do on armv8) so that SoCs can
override it if needed, and it will still be discarded if unused.
Provide a weak s_init as well to allow for this to link and be
discarded.
Signed-off-by: Tom Rini <trini@konsulko.com>
Any TFTP or DHCP boot on the Davinci OMAP-L138 LCDK board requires
that the 'ethaddr' variable be defined. There are no e-fuses to store
the ethernet mac address for this platform, and neither is a MAC
address reserved in any format. So enable random MAC address support
so that networking boot can be supported.
Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
We used to have opencoded ehci_readl()/writel() which required no
external functions to be called.
Now with attempt to switch to generic readl()/writel() accessors
we see a missing declaration of those accessors in ehci-ppc4xx.
Something like that happens if applied
http://patchwork.ozlabs.org/patch/726714/:
--------------------------------->8---------------------------
CC drivers/usb/host/ehci-pci.o
In file included from drivers/usb/host/ehci-pci.c:14:0:
drivers/usb/host/ehci-pci.c: In function 'ehci_pci_init':
drivers/usb/host/ehci.h:108:36: warning: implicit declaration of function 'readl' [-Wimplicit-function-declaration]
#define ehci_readl(x) cpu_to_le32(readl(x))
^
drivers/usb/host/ehci.h:23:26: note: in definition of macro 'HC_LENGTH'
#define HC_LENGTH(p) (((p) >> 0) & 0x00ff)
^
include/linux/byteorder/generic.h:89:21: note: in expansion of macro '__cpu_to_le32'
#define cpu_to_le32 __cpu_to_le32
^~~~~~~~~~~~~
drivers/usb/host/ehci-pci.c:33:14: note: in expansion of macro 'ehci_readl'
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
^~~~~~~~~~
--------------------------------->8---------------------------
This the same fix as we have for "ehci-ppc4xx" in
83cb46c286 "ehci-ppc4xx: Prepare for usage of readl()/writel() accessors".
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Remove the CONFIG_I2C_COMPAT, instead enable the CONFIG_SYS_I2C_S3C24X0.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Change the nodes relevant to mmc/sd for using DM.
compatible are also changed to each SoCs.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
First of all, it's inappropriate to call setup_internal_uart() in a
generic API fsp_init(), as CONFIG_INTERNAL_UART is an option that
is only available on BayTrail platform. Secondly even for BayTrail,
there is no need to call setup_internal_uart() at all, as Intel FSP
will do this for us.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
It was observed that when -DDEBUG is used to generate a debug build,
U-Boot does not boot on MinnowMax board. A workaround is to disable
CONFIG_DEBUG_UART. The real issue is that in order to have the debug
uart to work, BayTrail SoC needs to be configured so that its internal
uart is available to be used as the debug uart.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
At present lpe/lpss-sio/scc FSP properties are all boolean, but in
fact for "enable-lpe" it has 3 possible options. This adds macros
for these options and change the property from a boolean type to
an integer type, and change their names to explicitly indicate what
the property is really for.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Introduce various meaningful macros for FSP settings and switch over
to use them instead of magic numbers.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
"serial-debug-port-address" and "serial-debug-port-type" settings
are actually reserved in the FSP UPD data structure. Remove them.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
The default value of "fsp,mrc-init-tseg-size" should be 1 (1MB) per
FSP default settings. 0 is not valid.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Now that these symbols are in Kconfig, migrate all users. Use imply on
a number of platforms that default to having this enabled. As part of
this we must migrate some straglers for CMD_FAT and DOS_PARTITION.
Signed-off-by: Tom Rini <trini@konsulko.com>
Add fallbacks needed to keep all boards building
while they are migrated to use Kconfig symbols
instead of defines in <board>_config.h files for
FAT filesystem.
These should eventually go away once Kconfig select
or imply statements are put in place and duplicated
defines in <board>_config.h removed.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
[trini: Update logic since CMD_FAT / CONFIG_SPL_FAT_SUPPORT are
selecting FS_FAT]
Signed-off-by: Tom Rini <trini@konsulko.com>
Since config fallbacks contained in include/config_fallbacks.h
come into k2g_evm.h file through ti_armv7_keystone2.h, it should
be the last file included.
Without this, #define of FAT_WRITE when environment is in FAT
does not happen as the environment location is decided later
in the file.
Similar issues can come with other config fallbacks implemented.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Not all TI Keystone2 EVMs want environment in NAND flash.
K2G EVM which has an MMC/SD slot, keep environment in a
FAT partition on SD card.
Since ti_armv7_keystone2.h defines environment is in NAND,
boards which do not follow that have to #undef'ine that
configuration. This leads to ugly ordering issues around
where exactly the include of ti_armv7_keystone2.h can come
in within the k2*_evm.h files.
Move environment location to config file of each board.
This should make it easy to change it for any one board
without affecting all other boards.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Add Kconfig symbols for various configurations
supported by FAT filesystem support code.
CONFIG_SUPPORT_VFAT has been left out since its
force enabled in include/fat.h and probably
should get removed at some point.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
[trini: add select FS_FAT for CMD_FAT and SPL_FAT_SUPPORT]
Signed-off-by: Tom Rini <trini@konsulko.com>
On MIPS systems DMA isn't coherent with the CPU caches unless an IOCU is
present. When there is no IOCU we need to writeback or invalidate the
data caches at appropriate points. Perform this cache maintenance in
the pch_gbe driver which is used on the MIPS Boston development board.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Use the virt_to_bus & bus_to_virt functions rather than phys_to_bus &
bus_to_phys, since the addresses accessed by the CPU will be virtual
rather than physical. On MIPS physical & virtual addresses differ as we
use virtual addresses in kseg0, and attempting to use physical addresses
directly caused problems as they're in the user segment which would be
mapped via the uninitialised TLB.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The loop to set up buffer addresses in rx descriptors always operated on
descriptor 0, rather than on each descriptor sequentially. Fix this in
order to setup correct buffer addresses for each descriptor.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Using the EG20T gigabit ethernet controller on the MIPS Boston board, we
find that we have to reset the controller in order for the RGMII link to
the PHY to become functional. Without doing so we constantly time out in
pch_gbe_mdio_ready.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Dont flush dummy descriptors as they are already
allocated from a region with dcache off. Tested
this on Zynq(zc702) and ZynqMP(zcu102) boards.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Use wait_for_bit to be non breakable as using it with
breakable causes issue of un interruptible auto negotiation.
This is due to the ctrlc pressed will taken for wait_for_bit()
abort during phy_read() and hence not coming out of
auto negotiation.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The 88E1518 code is programming the wrong registers for rgmii-id,
rgmii-txid and rgmii-rxid interfaces.
Since the PHY defaults to rgmii-id, it would appear that the code
was previously only used with sgmii and rgmii-id interfaces.
Tested on 88E1512 PHY in rgmii-id mode which is from the same family
as 88E1518.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Checking if dev is NULL after dereferencing it does not make sense.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Abort CPSW driver init when auto-negotiation of link
times out. Currently, the code ignores return status
of phy_startup(), and goes ahead with network operation
(like DHCP) even though the link may be down.
Instead, abort init process if link is down or if there
is another error, so phy_startup() can easily be retried
again. This also helps quick fallback to next network interface
(like USB RNDIS) without inordinate delay.
Tested on AM571x IDK and AM335x BeagleBone black.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Always search the PHY to determine the macb->phy_addr before using
the PHY to fix "No PHY present" error.
Fix the wrong test of the GMAC's phy interface mode, it should be
PHY_INTERFACE_MODE_RGMII.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch fixes some remaining issues in the mvpp2 driver for the 10GB
support on port 0. These changes are:
- Incorrect PCS configuration
- Skip PHY configuration when no PHY is connected
- Skip GMAC configurations if 10G SFI mode set
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The .read_rom_hwaddr net_ops hook does not check the return value, which
is why it was never caught that we are currently returning 0 if the
read_rom_hwaddr function return -ENOSYS and -ENOSYS otherwise.
In this case we can simplify this by just returning the result of the
function.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
This change migrate the following configuration options for Kconfig:
* PHY_GIGE, indicates that a controller (with an appropriate PHY) is
Gigabit capable and enables extra support in the miiutil for
parsing the status of Gigabit PHYs
* adds configuration options for Micrel KSZ9021 and KSZ9031 GbE PHYs,
which previously had to enabled through a board-specific config file
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This file was used to select between the normal and fallback libfdt
implementations. Now that we only have one, it is not needed.
Drop it and fix up all users.
Signed-off-by: Simon Glass <sjg@chromium.org>
Since we only have one Fdt implementation now we don't need to have a base
class. Merge the implementation and the base class together.
Signed-off-by: Simon Glass <sjg@chromium.org>
Previously we were sometimes forced to collate x86 microcode due to not
having access to the offset of each individual piece. Now that we never
use fdt_fallback, we don't have this problem. Drop this special case from
the code.
Signed-off-by: Simon Glass <sjg@chromium.org>
This is needed by binman and dtoc, so if those are being used, check that
the library is present and complain if not. Make sure that any error
appears on stderr so that buildman notices it.
This means that the fallback library (which uses fdtget) will not be used
anymore and swig will need to be installed to use binman / dtoc.
This affects any board which uses binman (currently sunxi and x86) or dtoc
(anything that uses CONFIG_SPL_OF_PLATDATA, currently some rockchip
boards).
Signed-off-by: Simon Glass <sjg@chromium.org>
The tests don't currently cover all the different property types. Add a
new test which checks each property type in turn, to make sure each has
the correct type and value.
Signed-off-by: Simon Glass <sjg@chromium.org>
Since fdt is a module it conflicts with this variable name and prevents it
being used in tests. Rename the variable.
Signed-off-by: Simon Glass <sjg@chromium.org>
Build the upstream python libfdt module. At present the legacy module is
still built and is the one that it used. Future work will switch this
over.
Signed-off-by: Simon Glass <sjg@chromium.org>
Now that this module has been accepted upstream we should stop using the
local U-Boot one. In preparation for this, rename it to indicate it is for
legacy use.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present only a subset of source files are build. Add the rest and
refactor this so that a source file list is available also. This will be
used in later commit.
Signed-off-by: Simon Glass <sjg@chromium.org>
These header files are actually part of libfdt. Move them there to make
it easier to build pylibfdt and easier to merge changes from upstream.
Update the license header to use SPDX at the same time.
Signed-off-by: Simon Glass <sjg@chromium.org>
This gives a warning with some native compilers:
lib/fdtdec.c:1203:8: warning: format ‘%llx’ expects argument of type
‘long long unsigned int’, but argument 3 has type
‘long unsigned int’ [-Wformat=]
Fix it with a cast.
Signed-off-by: Simon Glass <sjg@chromium.org>
This gives a warning with some native compilers:
cmd/pci.c:152:11: warning: format ‘%llx’ expects argument of type
‘long long unsigned int’, but argument 3 has type
‘u64 {aka long unsigned int}’ [-Wformat=]
Fix it with a cast.
Signed-off-by: Simon Glass <sjg@chromium.org>
An early version of this is available upstream. Bring it in as a starting
point. This is from dtc upstream commit e56f2b0.
Future work will plumb it into dtoc and remove the now-unnecessary local
libraries.
Signed-off-by: Simon Glass <sjg@chromium.org>
Orangepi Prime is an open-source single-board computer
using the Allwinner h5 SOC.
H5 Orangepi Prime has
- Quad-core Cortex-A53
- 2GB DDR3
- Debug TTL UART
- 1000M/100M Ethernet RJ45
- Three USB 2.0
- HDMI
- Audio and MIC
- Wifi + BT
- IR receiver
- HDMI
- Wifi + BT
Boot from MMC:
-------------
U-Boot SPL 2017.05-00662-ga3f4c05-dirty (May 25 2017 - 13:30:14)
DRAM: 2048 MiB
Trying to boot from MMC1
NOTICE: BL3-1: Running on H5 (1718) in SRAM A2 (@0x44000)
NOTICE: Configuring SPC Controller
NOTICE: BL3-1: v1.0(debug):aa75c8d
NOTICE: BL3-1: Built : 18:28:27, May 24 2017
INFO: BL3-1: Initializing runtime services
INFO: BL3-1: Preparing for EL3 exit to normal world
INFO: BL3-1: Next image address: 0x4a000000, SPSR: 0x3c9
U-Boot 2017.05-00662-ga3f4c05-dirty (May 25 2017 - 13:30:14 +0000) Allwinner Technology
CPU: Allwinner H5 (SUN50I)
Model: OrangePi Prime
DRAM: 2 GiB
MMC: SUNXI SD/MMC: 0
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: phy interface7
eth0: ethernet@1c30000
starting USB...
USB0: USB EHCI 1.00
USB1: USB OHCI 1.0
scanning bus 0 for devices... 1 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found
Hit any key to stop autoboot: 0
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
CONFIG_SPL_BOARD_INIT is used for SPL boot. It is only enabled for
secure boot at this moment. Enable it in defconfig files for SPL
build.
Signed-off-by: York Sun <york.sun@nxp.com>
Loading PPA in SPL puts the rest of U-Boot (including RAM version
loaded later) in EL2 with MMU and cache enabled. Once PPA is loaded,
PSCI is available.
Signed-off-by: York Sun <york.sun@nxp.com>
When U-Boot boots from EL2, skip some lowlevel init code requiring
EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These
initialization tasks are carried out before U-Boot runs. This applies
to the RAM version image used for SPL boot if PPA is loaded first.
Signed-off-by: York Sun <york.sun@nxp.com>
Add CONFIG_NAND_BOOT config flag to organise
NAND_BOOT specific code in config flag like
-nand-boot specfic errata errata_rcw_src()
-CONFIG_SYS_NAND_U_BOOT_DST,etc
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
modify u_qe_init to upload QE firmware from SD card when it is SD
boot
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Previous to MC v10.x, port mac address was specified via DPL. Since
newer MC versions are compatible with old style DPLs, make the u-boot
env mac addresses visible there. This applies only to DPLs that have
an older version.
DPLs use 32 bit values for specifying MAC addresses. U-boot
environment variables take precedence over the MAC addresses already
visible in the DPL/DPC.
Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
Signed-off-by: Heinz Wrobel <heinz.wrobel@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
DPAA2 platforms boot the Management Complex based on the u-boot env
variable "mcinitcmd". Instead of doing this step on each platform
individually, define a single mc_env_boot function in the MC driver,
since it's semantically tied to it.
Call the function in a per-board reset_phy hook, as it gets called at a
later moment, when all board PHY devices have been initialized.
Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
Signed-off-by: Heinz Wrobel <heinz.wrobel@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The Allwinner H5 SoC is pin-compatible to the H3 SoC,
but uses Cortex-A53 cores instead.
So move the shared cpu based and peripherals nodes into
sun50i-h5.dtsi so, that it can shared among the sun50i-h5
board dts files.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
This updates sandbox to use a live device tree. This means that after
relocation (from board_init_r() onwards) it no-longer uses flat device
tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
This PMIC driver (power and GPIO) is used by the sandbox SPMI tests.
Update the drivers to support a live device tree so that the tests pass.
Signed-off-by: Simon Glass <sjg@chromium.org>
Update the SPI uclass to support a live device tree. Also adjust
spi_slave_ofdata_to_platdata() to accept a device instead of a blob and
offset.
Signed-off-by: Simon Glass <sjg@chromium.org>
Update the PCI uclass to support livetree. This mostly involves fixing
the address decoding from the device tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Use ut_asserteq() to test equality since this gives a better error message
on failure. Also make a few of the tests more specific.
Signed-off-by: Simon Glass <sjg@chromium.org>
We cannot access the device tree via an offset when running in livetree
mode. Separate out that part of the bus' children tests and mark it as
for the flat tree only.
Signed-off-by: Simon Glass <sjg@chromium.org>
Update the xlate() method to use ofnode_phandle_args instead of the fdtdec
variant. This will allow drivers to support a live device tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add an implementation of strcspn() which returns the number of initial
characters that do not match any in a rejection list.
Signed-off-by: Simon Glass <sjg@chromium.org>
This functions works like strchr() but returns the end of the string if
the character is not found. Add an implementation of this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add some definitions and helpers for livetree in the main of.h header
file. These include:
- reading multi-cell integers
- default number of address/size cells
- functions for comparing names
Signed-off-by: Simon Glass <sjg@chromium.org>
These two functions have an of_ prefix which conflicts with naming used
in of_addr. Rename them:
fdt_read_number
fdt_support_bus_default_count_cells
Signed-off-by: Simon Glass <sjg@chromium.org>
The standard sandbox board cannot run the of-platdata test since it needs
SPL. Also, we should test the flat tree version of sandbox.
Add these tests to the default test script.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a sandbox board to test the non-livetree build (i.e. with
CONFIG_OF_FLAT disabled). This increases our build and test coverage.
Signed-off-by: Simon Glass <sjg@chromium.org>
Convert this driver to support the live device tree and remove the old
fdtdec support.
The keyboard is not yet converted.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add support for requesting GPIOs with a live device tree.
This involves adjusting the function signature for the legacy function
gpio_request_by_name_nodev(), so fix up all callers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes to stm32f746-disco.c:
Signed-off-by: Tom Rini <trini@konsulko.com>
Move the main part of the GPIO request function into a separate function
so that it can be used by the live tree function when added. Update the
xlate method to use a node reference.
Update all GPIO drivers to handle the modified xlate() method.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some tests require either livetree or flat tree. Add flags to allow the
tests to specify this. Adjust the test runner to run with livetree (if
supported) and then flat tree.
Some video tests are quite slow and running on flat tree adds little extra
test value, so run these on livetree only.
Signed-off-by: Simon Glass <sjg@chromium.org>
It is useful to run the driver model tests with both livetree and flat
tree in case something is different between the two. Add this feature to
the test runner.
Signed-off-by: Simon Glass <sjg@chromium.org>
We want to run the same test on flat and live trees. In preparation for
this, create a new function which handles running a test.
Signed-off-by: Simon Glass <sjg@chromium.org>
Running a new test should reset the sandbox state to avoid tests
interferring with each other. Move the existing state-reset code into a
function so it can be used from tests.
Also update the code to reset the SPI devices and adjust the test code to
call it.
Signed-off-by: Simon Glass <sjg@chromium.org>
When starting up driver model with a live tree we need to scan the tree
for devices. Add code to handle this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Adjust this function to us an ofnode instead of an offset, so it can be
used with livetree. This involves updating all callers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Adjust this function to use an ofnode instead of an offset, so it can be
used with livetree. This involves updating all callers.
Signed-off-by: Simon Glass <sjg@chromium.org>
When a live tree is being used we need to record the node that was used to
create the device. Update device_bind_with_driver_data() to support this.
Signed-off-by: Simon Glass <sjg@chromium.org>
When the live tree is supported some functions need to change a little.
Add an implementation which is used when not inlining these functions.
Signed-off-by: Simon Glass <sjg@chromium.org>
It is common to read a device-tree property from the node associated with
a device. Add convenience functions to do this so that drivers do not need
to deal with accessing the ofnode from the device.
These functions all start with 'dev_read_' to provide consistent naming
for all functions which read information from a device's device tree node.
These are inlined when using the flat DT to save code size. The live tree
implementation is added in a later commit.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some functions deal with structured data rather than simple data types.
It makes sense to have these in their own file. For now this just has a
function to read a flashmap entry. Move the data types also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add functions to access addresses in the device tree. These are brought
in from Linux 4.10.
Also fix up the header guard for fdtaddr.h to avoid confusion.
Signed-off-by: Simon Glass <sjg@chromium.org>
Since U-Boot supports both a live tree and a flat tree, we need an easy
way to access the tree without worrying about which is currently active.
To support this, U-Boot has the concept of an ofnode, which can refer
either to a live tree node or a flat tree node.
For the live tree, the reference contains a pointer to the node (struct
device_node *) or NULL if the node is invalid. For the flat tree, the
reference contains the node offset or -1 if the node is invalid.
Add a basic set of operations using ofnodes. These are implemented by
using either libfdt functions (in the case of a flat DT reference) or
the live-tree of_...() functions.
Note that it is not possible to have both live and flat references active
at the same time. As soon as the live tree is available, everything in
U-Boot should switch to using that. This avoids confusion and allows us to
assume that the type of a reference is simply based on whether we have a
live tree yet, or not.
Signed-off-by: Simon Glass <sjg@chromium.org>
The of_ prefix conflicts with the livetree version of this function.
Rename it to avoid problems when we add livetree support.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function converts the flat device tree into a hierarchical one with
C structures and pointers. This is easier to access.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a basic assortment of functions to access the live device tree. These
come from Linux v4.9 and are modified for U-Boot to the minimum extent
possible. While these functions are now very stable in Linux, it will be
possible to merge in fixes if needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a Kconfig option to enable a live device tree, built at run time from
the flat tree. Also add structure definitions and a root node.
Signed-off-by: Simon Glass <sjg@chromium.org>
In linux v4.9 this returns a value. This saves checking the warning
condition twice in some code.
Update the U-Boot version to do this also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Enable CONFIG_DM_MMC_OPS and CONFIG_BLK for all Tegra devices. This moves
Tegra to use driver model fully for MMC.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function is called when the MMC block device is being probed. There
is a recursive call in this function since find_mmc_device() itself can
cause the MMC device to be probed.
Admittedly the MMC device should already be probed, since we would not be
probing its child otherwise, but the current code is unnecessarily
convoluted.
Rewrite this to access the MMC structure directly.
Signed-off-by: Simon Glass <sjg@chromium.org>
When binding a new MMC device, make sure that it has the required
operations. Since for now we still support *not* having the operations
(with CONFIG_DM_MMC_OPS not enabled) it makes sense to add this check.
Signed-off-by: Simon Glass <sjg@chromium.org>
The intention with block devices is that the device number (devnum field
in its descriptor) matches the alias of its parent device. For example,
with:
aliases {
mmc0 = "/sdhci@700b0600";
mmc1 = "/sdhci@700b0400";
}
we expect that the block devices for mmc0 and mmc1 would have device
numbers of 0 and 1 respectively.
Unfortunately this does not currently always happen. If there is another
MMC device earlier in the driver model data structures its block device
will be created first. It will therefore get device number 0 and mmc0
will therefore miss out. In this case the MMC device will have sequence
number 0 but its block device will not.
To avoid this, allow a device to request a device number and bump any
existing device number that is using it. This all happens during the
binding phase so it is safe to change these numbers around. This allows
device numbers to match the aliases in all circumstances.
Add a test to verify the behaviour.
Signed-off-by: Simon Glass <sjg@chromium.org>
Sometimes it is useful to be able to find a block device without also
probing it. Add a function for this as well as the associated test.
Signed-off-by: Simon Glass <sjg@chromium.org>
We should not call out to board code from drivers. With driver model,
mmc_power_init() already has code to use a named regulator, but the
legacy code path remains. Update the code to make this clear.
Signed-off-by: Simon Glass <sjg@chromium.org>
This core function will need to work with a live tree also. Update it to
accept an ofnode instead of an offset.
Signed-off-by: Simon Glass <sjg@chromium.org>
With live tree we need a struct device_node * to reference a node. With
the existing flat tree, we need an int offset. We need to unify these into
a single value which can represent both.
Add an ofnode union for this and adjust existing code to move to this.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function is only used in one place. It is better to just declare it
internally since there is a simpler replacement for use outside the
driver-model core code.
Signed-off-by: Simon Glass <sjg@chromium.org>
It is good practice to include common.h as the first header. This ensures
that required features like the DECLARE_GLOBAL_DATA_PTR macro,
configuration options and common types are available.
Fix up some files which currently don't do this. This is necessary because
driver model will soon start using global data and configuration in the
dm/read.h header file, included via dm.h. The gd->fdt_blob value will be
used to access the device tree and CONFIG options will be used to
determine whether to support inline functions in the header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function should not be used outside the core driver-model code.
Update it to use dm_scan_fdt_dev() instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
These support the flat device tree. We want to use the dev_read_..()
prefix for functions that support both flat tree and live tree. So rename
the existing functions to avoid confusion.
In the end we will have:
1. dev_read_addr...() - works on devices, supports flat/live tree
2. devfdt_get_addr...() - current functions, flat tree only
3. of_get_address() etc. - new functions, live tree only
All drivers will be written to use 1. That function will in turn call
either 2 or 3 depending on whether the flat or live tree is in use.
Note this involves changing some dead code - the imx_lpi2c.c file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Move this group of address-related functions into a new file. These use
the flat device tree. Future work will provide new versions of these which
can support the live tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
This header includes things that are needed to make driver build. Adjust
existing users to include that always, even if other dm/ includes are
present
Signed-off-by: Simon Glass <sjg@chromium.org>
BPI-M64 is a 64-bit quad-core mini single board computer
using the Allwinner A64 SOC.
BPI-M64 features
- 1.2 Ghz Quad-Core ARM Cortex A53
- 2GB DDR3 SDRAM with 733MHz
- MicroSD/eMMC(8GB)
- 10/100/1000Mbps ethernet (Realtek RTL8211E/D)
- Wifi + BT
- IR receiver
- Audio In/Out
- Video In/Out
- 5V 2A DC power-supply
For dts file,
Sync with Linux commit 4879b7ae("Merge tag 'dmaengine-4.12-rc1'").
Boot from MMC:
-------------
U-Boot SPL 2017.05-00667-g85dd258-dirty (May 29 2017 - 13:07:31)
DRAM: 2048 MiB
Trying to boot from MMC1
NOTICE: BL3-1: Running on A64/H64 (1689) in SRAM A2 (@0x44000)
NOTICE: Configuring SPC Controller
NOTICE: BL3-1: v1.0(debug):aa75c8d
NOTICE: BL3-1: Built : 18:28:27, May 24 2017
NOTICE: Configuring AXP PMIC
NOTICE: PMIC: setup successful
INFO: BL3-1: Initializing runtime services
INFO: BL3-1: Preparing for EL3 exit to normal world
INFO: BL3-1: Next image address: 0x4a000000, SPSR: 0x3c9
U-Boot 2017.05-00667-g85dd258-dirty (May 29 2017 - 13:07:31 +0000) Allwinner Technology
CPU: Allwinner A64 (SUN50I)
Model: BananaPi-M64
DRAM: 2 GiB
MMC: SUNXI SD/MMC: 0, SUNXI SD/MMC: 1
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: No ethernet found.
starting USB...
No controllers found
Hit any key to stop autoboot: 0
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The Linux device tree for the Allwinner A64 SoC has changed a lot since
the U-Boot version was merged.
Let's replace the current DT with a exact copy of the Linux one as of:
commit c6778ff813d2ca3e3c8733c87dc8b6831a64578b
Merge: 0ff4c01 3c0e3abd
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date: Tue May 9 10:07:33 2017 -0700
This is the DT used in Linux 4.12-rc1.
Since U-Boot has an Ethernet driver (while Linux does not yet), we
provide the required DT nodes for it in an ...-u-boot.dtsi file, to both
mark them as U-Boot specific and to allow easier upgrading once Linux gets
the driver and its own binding later.
Compared to the existing Ethernet DT nodes we just slightly tweak the clock
and reset nodes in there to match the new bindings used by Linux for those.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Currently these (board agnostic) commands cannot be selected using
menuconfig and friends. Fix this the obvious way. As part of this,
don't muddle the meaning of CONFIG_HASH_VERIFY to mean both 'hash -v'
and "we have a hashing command" as this makes the Kconfig logic odd.
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
[trini: Re-apply, add imply for a few cases, run moveconfig.py, also
migrate CRC32_VERIFY]
Signed-off-by: Tom Rini <trini@konsulko.com>
Instead of having a peripheral clock of 50 MHz like the BCM63xx family, it
has a 48 MHz clock.
This fixes uart baud rate calculation for BCM3380.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
It's currently bugged and doesn't work for even cases.
Right shift bits instead of dividing and fix even cases.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
I missed this when I added support for BMIPS UART driver and it's needed to
achieve a real 115200 8N1 setup.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
As far as I know BCM3380 has a fixed CPU frequency since I couldn't find its
PLL registers in any documentation.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This is done in order to reuse ram size calculation for BCM6338/BCM6348
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Use a generic name for cpu_desc functions instead of using a specific SoC one.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This driver allows rebooting the SoC by calling wdt_expire_now op.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This driver allows rebooting the SoC by calling wdt_expire_now op.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This driver allows rebooting the SoC by calling wdt_expire_now op.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add a new sysreset driver that uses the recently added watchdog support.
It performs a full SoC reset by calling wdt_expire_now op.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This driver controls the watchdog present on this SoC.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This driver controls the watchdog present on this SoC.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This driver controls the watchdog present on this SoC.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This driver is a simplified version of linux/drivers/watchdog/bcm63xx_wdt.c
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
As mx6sabresd only supports SPL target now, there is no need to
keep the 'spl' in the name of the target, so simply rename it
to mx6sabresd_defconfig.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Engicam has several SOM's on i.MX6 stream, where each SOM
has one include/configs/*.h file, this patch generate single
config file for all SOM's include/configs/imx6-engicam.h
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Define FDT_ADDR based on the respective SOM, and later patches
will make use of this fdt_addr in single config file.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
- IMX_FEC_BASE: icorem6 using dts, no need for explicit base.
- CONFIG_ETHPRIME: ethprime env not using anywhere in the board.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
nand defconfig is accidentally removed from below
commit, so recover the same.
"icorem6: Make SPL to pick suitable fdt"
(sha1: 15455a6b01)
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
The maximum SD clock frequency in High Speed mode is 50 MHz. This change
makes it possible to get 48 MHz from the USB PLL (240 MHz / 5 / 1)
instead of the previous 33.25 MHz from the AHB clock (133 MHz / 2 / 2).
Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Introduce the imx_set_perclk() function to make it possible to set the
PER clocks.
Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
imx_get_perclk() used the AHB clock as the clock source for all PER
clocks, but the USB PLL output can also be a PER clock source if the
corresponding PER CLK MUX bit is set in CCM.MCR.
Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
On i.MX, SYSCTL.SDCLKFS may be set to 0 in order to make the SD clock
frequency prescaler divide by 1 in SDR mode. In DDR mode, the prescaler
can divide by up to 512. Allow both of these settings.
The maximum SD clock frequency in High Speed mode is 50 MHz. On i.MX25,
this change makes it possible to get 48 MHz from the USB PLL
(240 MHz / 5 / 1) instead of only 40 MHz from the USB PLL
(240 MHz / 3 / 2) or 33.25 MHz from the AHB clock (133 MHz / 2 / 2).
Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
The config variable CONFIG_SPL_NAND_MXS is only set in
include/configs/imx6_spl.h but used nowhere.
Remove it.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
There is no dedicated reset signal wired up for the MX6QDL thus if the
bootloader enables the link we need some special handling to get the core
back into a state where it is safe to touch it for configuration.
While there has been some special handling in the Linux kernel to do this,
it was removed in 4.11 thus we need to do it properly in the bootloader
and therefore without this if you enable PCI in the bootloader you will hang
while booting the 4.11 kernel.
This puts the PCIe controller back into a safe state for the kernel driver
before launching the kernel.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Peter Senna Tschudin <peter.senna@collabora.com>
After running 'saveenv' we can no longer boot.
Adjust CONFIG_ENV_OFFSET so that U-Boot binary and the environment
section do not overlap.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
image_version_file()'s only use is to return the version number of the
specified image, and it's only called by kwbimage_generate(). This
version function mallocs "image_cfg" and reads the contents of the image
into that buffer. Before return to its caller it frees the buffer.
After extracting the version, kwb_image_generate() tries to calculate
the header size by calling image_headersz_v1(). This function now
accesses "image_cfg", which has already been freed.
Since image_version_file() is only used by a single function, inline it
into kwbimage_generate() and only free the buffer after it is no longer
needed. This also improves code readability since the code is mostly
equal to kwbimage_set_header().
Signed-off-by: Patrick Wildt <patrick@blueri.se>
Signed-off-by: Stefan Roese <sr@denx.de>
Use GPIO19 which is wired to the uSOM phy reset signal in order to reset
the uSOM's 1512 Gigabit Ethernet phy.
This GPIO is valid on ClearFog rev 2.1 and newer.
Taken from SolidRun's specialised u-boot, see
f906e3df17
Signed-off-by: Patrick Wildt <patrick@blueri.se>
Signed-off-by: Stefan Roese <sr@denx.de>
The dram_init and dram_init_banksize functions were using a board
specific implementation for decoding the memory banks from the fdt.
This change makes the dram_init* functions use a generic implementation
of decoding and populating memory bank and size data.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nathan Rossi <nathan@nathanrossi.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch enables the mvpp2 port 0 usage on the Armada 7k DB by setting
the correct PHY type (KR / SFI) for the COMPHY driver and enabling the
ethernet0 device node in the dts.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
This patch enable the PINCTRL and GPIO support, including the GPIO
command on the Armada 3720 DB.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
To enable support for the Armada 37xx pinctrl driver, we need to
change the Kconfig symbol for the Armada 7k/8k pinctrl driver and its
dependencies to distinguish between both platforms and drivers.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
GPIO management is pretty simple and is part of the same IP than the pin
controller for the Armada 37xx SoCs. This patch adds the GPIO support to
the pinctrl-armada-37xx.c file, it also allows sharing common functions
between the gpio and the pinctrl drivers.
Ported to U-Boot based on the Linux version by Stefan Roese.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
The Armada 37xx SoC come with 2 pin controllers: one on the south
bridge (managing 28 pins) and one on the north bridge (managing 36 pins).
At the hardware level the controller configure the pins by group and not
pin by pin. This constraint is reflected in the design of the driver:
only the group related functions are implemented.
Ported to U-Boot based on the Linux version by Stefan Roese.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Add the nodes for the two pin controller present in the Armada 37xx SoCs.
Initially the node was named gpio1 using the same name that for the
register range in the datasheet. However renaming it pinctr_nb (nb for
North Bridge) makes more sens.
Minor changes for U-Boot because of the slightly different dts version
done by Stefan Roese.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
NanoPi M1 is a board based on Allwinner H3 CPU.
This commit adds the support for this platform with:
- an include device tree which enables UART, LEDs, GPIO key switch,
1 USB host ports and the SD-card as a dtsi file.
- a device tree specific to this board that enables the
2 additional USB ports
- a defconfig file for minimal support
- a section in MAINTAINERS (add myself)
Synchronized with the kernel device tree, from commits:
sun8i-nanopi.dtsi: 85d2913614d9ab899d23b7ab7d22d23cf45bd1de
sun8i-h3-nanopi-m1.dts: 10efbf5f16336b7540ad6a16aa1cb0b26bab033b
Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
This introduces the ability to override the environment offets from the
device tree by setting the following nodes in '/config':
'u-boot,mmc-env-offset' - overrides CONFIG_ENV_OFFSET
'u-boot,mmc-env-offset-redundant'
- overrides CONFIG_ENV_OFFSET_REDUND
To keep with the previous logic, the CONFIG_* defines still need to
be available and the statically defined values become the defaults,
when the corresponding properties are not set in the device-tree.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Currently while setting the vsel value for dcdc1 and dcdc2
the driver is wrongly masking the entire 8 bits in the process
clearing PFM (bit7) field as well. Hence describe an appropriate
mask for vsel field and modify only those bits in the vsel
mask.
Source: http://www.ti.com/lit/ds/symlink/tps65218.pdf
Signed-off-by: Keerthy <j-keerthy@ti.com>
Fixes: 86db550b38 ("power: Add support for the TPS65218 PMIC")
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Number of blocks is a 9 bit field where 0 stands for a unlimited
number of blocks. Therefore the max number of blocks which can
be set is 511.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Inside of
max77686_buck_volt2hex/max77686_buck_hex2volt/max77686_ldo_volt2hex we
check that the value we calculate is >= 0 however we declare 'hex' as
unsigned int making these always true. Mark these as 'int' instead. We
also move hex_max to int as they are constants that are 0x3f/0xff.
Given that the above functions are marked as returning an int, make the
variables we assign their return value to also be int to be able to
catch the error condition now. Reported by clang-3.8.
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
In some places we check if part_config is set to MMCPART_NOAVAILABLE
(0xff). With part_config being a char this is always false. We should
be using a u8 to store this value instead, after a quick consultation
with the Linux Kernel. Reported by clang-3.8.
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This patch adjusts memory map for secure boot headers on LS2080AQDS
and LS2080ARDB platforms. Secure boot headers are placed on NOR
flash at offset 0x00600000.
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch is to adjust the memory mapping for FLash/SD card on
LS1046AQDS and LS1046ARDB, such as FMAN firmware load address, U-Boot
start address on serial flash and environment address.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch is to adjust the memory mapping for FLash/SD card on
LS1043AQDS and LS1043ARDB, such as PPA firmware load address, FMAN
firmware load address, QE firmware load address, U-Boot start address
on serial flash and environment address.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch is to adjust the memory mapping for FLash/SD card on
LS1021AQDS and LS1021ATWR, such as U-Boot start address on serial
Flash, QE firmware load address and environment address.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
LS2081ARDB board is similar to LS2080ARDB board with few differences
It hosts LS2081A SoC
Default boot source is QSPI-boot
It does not have IFC interface
RTC and QSPI flash device are different
It provides QIXIS access via I2C
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
On the A33, uart0 is muxed on the PB pins. On SBCs these pins may be
available for use. Such is the case on the Sinlinx SinA33.
Set CONS_INDEX=1 to use uart0 as the console, matching the device tree.
Fixes: 7095f86418 ("sunxi: Convert CONS_INDEX to Kconfig")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and
is built on layerscape architecture. It is 40-pin derivative of
LS2084A (non-AIOP personality of LS2088A). So feature-wise it is
same as LS2084A. LS2041A is a 4-core personality of LS2081A.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
QSPI-boot is supported on LS2088ARDB RevF board with LS2088A SoC.
LS2088ARDB RevF Board has limitation that QIXIS can not be accessed.
CONFIG_FSL_QIXIS is not enabled.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Update QIXIS related code to be executed only if CONFIG_FSL_QIXIS
flag is enabled. In case QIXIS code is not enabled, use default
sysclk value as 100MHz per board documentation.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Earlier when MC is loaded but DPL is not deployed results in FDT
fix-up code execution hangs. For this case now print message on
console and return success instead of return -ENODEV. This update
allows fdt fixup to continue execution.
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Priyanka Jain <Priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
ls1012ardb, ls1046ardb, ls2080ardb have S25FS512S flash which does
not support Bank Address Register commands.
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
LS2080ARDB/LS2088ARDB RevF board has smart voltage translator
which needs to be programmed to enable high speed SD interface
by setting GPIO4_10 output to zero.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
In situations like an autobuilder we are likely to not have bl31.bin
present and thus would fail to build and propagate the error upwards.
Instead, print a big warning to stderr so that human will see that
something is wrong but complete the build.
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
trini: Make Kconfig SPL_xxx entires only show if SPL, so that we don't
get Kconfig errors on platforms without SPL, ie sandbox (without SPL).
Signed-off-by: Tom Rini <trini@konsulko.com>
The original commit for the MCF54418TWR ColdFire development board
support defined a 'CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN'
which obviously has a rogue 'CONFIG_SYS_NO_FLASH' embedded in the
intended 'CONFIG_SYS_FAULT_ECHO_LINK_DOWN' define.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Rather than using CMD_JFFS2 for both the filesystem and its command, we
should have a separate option for each. This allows us to enable JFFS2
support without the command, if desired, which reduces U-Boot's size
slightly.
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts the following to Kconfig:
CONFIG_CMD_IMMAP
Also move this command out of the cmd/ directory since it is
PowerPC-specific.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present IDE support is controlled by CONFIG_CMD_IDE. Add a separate
CONFIG_IDE option so that IDE support can be enabled without requiring
the 'ide' command.
Update existing users and move the ide driver into drivers/block since
it should not be in common/.
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts the following to Kconfig:
CONFIG_CMD_HDMIDETECT
Note that we cannot do 'default y if VIDEO' because this option is only
enabled for a small subset of mx6 boards. Also this command is is not a
great implementation (it doesn't use driver model).
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_CMD_HD44760
Also drop CONFIG_CMD_HD44780 which appears to be a typo.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present CONFIG_CMD_HASH enables the 'hash' command which also brings
in the hashing API. Some boards may wish to enable the API without the
command. Add a separate CONFIG to permit this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_CMD_HASH
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Rework slightly, enable on some boards again]
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_CMD_FPGA_LOADBP
CONFIG_CMD_FPGA_LOADFS
CONFIG_CMD_FPGA_LOADMK
CONFIG_CMD_FPGA_LOADP
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts the following to Kconfig:
CONFIG_CMD_ETHSW
Also enable it for sandbox to increase build coverage.
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts the following to Kconfig:
CONFIG_CMD_ESBC_VALIDATE
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_CMD_EEPROM
CONFIG_CMD_EEPROM_LAYOUT
CONFIG_EEPROM_LAYOUT_HELP_STRING
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Rework Kconfig logic slightly, define EEPROM location on TI eval
platforms]
Signed-off-by: Tom Rini <trini@konsulko.com>
This is only used by one board and always set to 0x51. Drop this option.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Now that dtt is gone, this is not used. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
This subsystem is quite old. It has been replaced with a driver-model
version (UCLASS_THERMAL). Boards are free to convert to that if required,
but here is a removal patch that could be applied in the meantime.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
This subsystem has not been converted to driver model, there is only one
driver and only one board that uses it. Drop it and its CONFIG option.
Also drop the rtc4543 RTC driver since it uses TWS.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This option is only defined to a non-default value by canyonlands, which
needs conversion to driver model (where the I2C address would be defined
by the device tree).
Drop this option.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
This converts the following to Kconfig:
CONFIG_DS4510
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
This option enables a command in the driver. But the functions defined by
the driver are not called anywhere else in U-Boot. So it does not seem
useful to have this driver without its commands.
Drop this option, move the header file out of the common include/
directory and make all the function static.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
This option is only used in one driver and is not enabled by any board. It
does not seem worth having the ability to remove this part of the support.
Drop the option.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
This option is only used in one driver and is not enabled by any board. It
does not seem worth having the ability to remove this part of the support.
Drop the option.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
This option is only used in one driver and two boards. It does not seem
worth having the ability to remove this part of the support.
Drop the option.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
We rename CONFIG_FIT_DISABLE_SHA256 to CONFIG_FIT_ENABLE_SHA256_SUPPORT which
is enabled by default and now a positive option. Convert the handful of boards
that were disabling it before to save space.
Cc: Dirk Eibach <eibach@gdsys.de>
Cc: Lukasz Dalek <luk0104@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
There is missing dependency on echo command. Mark tests which requires
echo.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
This converts the following to Kconfig:
CONFIG_SPL_BOARD_INIT
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
[trini: Update the Kconfig logic]
Signed-off-by: Tom Rini <trini@konsulko.com>
The IICDVFS(I2C) set in r8a7796.h is common in rcar-gen3.
This moves CONFIG_SYS_I2C_SH_BASE0 in rcar-gen3-base.h.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The mcs7830_recv() (non-DM) function discards good packets and tries to
process "bad" packets due to incorrect test condition.
Fix the condition and return the proper value as described in function
doc.
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
SDIO is not supported in u-boot, there is no point in enabling mmc3.
For this purpose, add u-boot specific dtsi that this will be included
automatically while building the dtb.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The intention of having a -u-boot.dtsi file is to be able to make
changes to the provided upstream dts files as well as to be able to add
nodes. Change the logic for adding the file from making it the last
included file at the top of the dts to being included at the end of the
file.
Cc: Jean-Jacques Hiblot <jjhiblot@ti.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Update Kconfig and Makefile to enable Arria 10.
Clean up Makefile and sorting *.o alphanumerically.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Restructure misc driver in the preparation to support A10.
Move the Gen5 specific code to gen5 file.
Change all uint32_t_to u32.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Restructure system manager in the preparation to support A10.
No functional change.
Change uint32_t to u32.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Restructure reset manager driver in the preparation to support A10.
Move the Gen5 specific code to gen5 files.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Restructure clock manager driver in the preparation to support A10.
Move the Gen5 specific code to _gen5 files.
- Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
- Check return value from wait_for_bit(). So change return type to int for
cm_write_with_phase() and cm_basic_init().
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Each time set_state is called, a new piece memory will
be allocated for pin_data, but not freed, this will
incur memory leak.
When error, the devm API could not free memory automatically.
So need call devm_kfree when error.
Issue reported by Coverity
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Agner <stefan.agner@toradex.com>
Cc: Stefano Babic <sbabic@denx.de>
Reset ENET_RST_B to make ENET function stable.
Since DM_GPIO enabled, we use "gpio_spi@0_5" which corresponds
to ENET_RST_B.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Enable more DM drivers. The imx I2C/MMC DM drivers needs DM_GPIO
enabled. The 74x164 drivers needs SOFT_SPI and DM_GPIO enabled.
So needs to enable them together.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Add the Kconfig entry for SOFT_SPI which uses gpio to simulate the
SPI signals. We use it for accessing 74x164 on some i.MX boards.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jagan Teki <jagan@openedev.com>
Cc: Stefano Babic <sbabic@denx.de>
Early backports of the imx wdog external reset feature occured before the
property was accepted upstream and used 'ext-reset-output' instead of
'fsl,ext-reset-output'. In order to support older kernels remove both
properties.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Now that mx6sabresd_spl_defconfig can be used to boot all
mx6sabresd variants, the non-SPL targets can be safely removed.
Signed-off-by: Fabio Estevam <fabio.estvam@nxp.com>
Add support for the mx6dlsabresd board in SPL.
Retrieved the DCD table from:
board/freescale/mx6sabresd/mx6dlsabresd.cfg
(NXP U-Boot branch imx_v2015.04_4.1.15_1.0.0_ga)
Flashed SPL and u-boot.img to an SD card and could successfully boot it
on mx6q, mx6qp and mx6dl sabresd boards.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Currently only MX6Q/QP sabresd boards are supported in SPL.
In order to also support MX6DL we need to convert to using
IOMUX_PADS and SETUP_IOMUX_PADS macros.
Other than that move the <asm/arch/mx6-ddr.h> header inclusion to the
SPL code block in order to avoid build error.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Add runtime, modeboot env which is setting mmcboot, or
nandboot based on the bootdevice so-that conditional
macros b/w MMC and NAND for CONFIG_BOOTCOMMAND should
be avoided in config files.
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Add runtime, modeboot env which is setting mmcboot, or
nandboot based on the bootdevice so-that conditional
macros b/w MMC and NAND for CONFIG_BOOTCOMMAND should
be avoided in config files.
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Fix calculation. do_div can not handle negative values.
Use div_s64_rem to handle the calculation.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
>From IC guys:
"
After a thorough accuracy study of the Temp sense circuit,
we found that with our current equation, an average part can
read 7 degrees lower than a known forced temperature.
We also found out that the standard variance was around 2C;
which is the tightest distribution that we could create.
We need to change the temp sense equation to center the average
part around the target temperature.
"
New equation:
Tmeas = (Nmeas - n1) / slope + t1 + offset
n1= fused room count
t1= 25
offset=3.580661
slope= 0.4148468 – 0.0015423*n1
According the new equation, update the thermal driver.
c1 and c2 changed to u64 type and update comments.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Avoid transfer parameter dev_id value with "-1" to .fec_get_hwaddr(),
it should transfer fec->dev_id to get mac address from fuse.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Stefano Babic <sbabic@denx.de>
The MIB RAM and FIFO receive start register does not exist on
i.MX6ULL. Accessing these register will cause enet not work well or
cause system report fault.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
- Add workaround code to make LD20 SoC boot from ARM Trusted Firmware
- Sync DT with Linux to fix DTC warnings
- Add new SoC support code
- Misc fix, updates
After speaking to Hans at FOSDEM, he is fine with transferring the
maintainership of the Pine64 boards over to me.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
With the DRAM init code and the SPL's ability to load the ATF binary as
well, we can now officially get rid of the boot0 boot method, which
involed a closed-source proprietary blob to be used.
Rework the Pine64 README file to document how to build the firmware.
Also since these instructions now cover more boards, rename the
file to README.sunxi64 to reflect this.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Now that we can store a DT name in the SPL header, use this string (if
available) when finding the right DT blob to load for U-Boot proper.
This allows a generic U-Boot (proper) image to be combined with a bunch
of supported DTs, with just the SPL (possibly only that string) to be
different.
Eventually this string can be written after the build process by some
firmware update tool.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This patch updates the mksunxiboot tool to optionally add
the default device tree name string to the SPL header. This
information can be used by the firmware upgrade tools to
protect users from harming themselves by trying to upgrade
to an incompatible bootloader.
The primary use case here is a non-removable bootable media
(such as NAND, eMMC or SPI flash), which already may have
a properly working, but a little bit outdated bootloader
installed. For example, the user may download or build a
new U-Boot image for "Cubieboard", and then attemept to
install it on a "Cubieboard2" hardware by mistake as a
replacement for the already existing bootloader. If this
happens, the flash programming tool can identify this
problem and warn the user.
The size of the SPL header is also increased from 64 bytes
to 96 bytes to provide enough space for the device tree name
string.
[Andre: split patch to remove OF_LIST hash feature]
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The Allwinner SoCs with 64-bit cores use an ARM Trusted Firmware binary,
which needs to be loaded alongside U-Boot proper.
Set the respective Kconfig options to let them select this feature and
also automatically build the FIT image.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
[Rename Kconfig path to arch/arm/mach-sunxi/Kconfig]
Signed-off-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
When a board uses a FIT image to load U-Boot proper, it requires a list
of supported device trees to be supplied in CONFIG_OF_LIST, from which it
chooses the right one at runtime.
For boards with just one possible DT (like the OrangePi PC2) this
defaults to CONFIG_DEFAULT_DEVICE_TREE, but for the Pine64 with its two
possible models we provide all compatible DTs in this config symbol.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@openedev.com>
Now that the Makefile can call a generator script to build a more
advanced FIT image, let's use this feature to address the needs of
Allwinner boards with 64-bit SoCs (A64 and H5).
The (DTB stripped) U-Boot binary and the ATF are static, but we allow
an arbitrary number of supported device trees to be passed.
The script enters both a DT entry in the /images node and the respective
subnode in /configurations to support all listed DTBs.
The location of the bl31.bin image from the ARM Trusted Firmware build
can either by specified via the BL31 environment variable. If this is not
set, the script looks for bl31.bin in U-Boot's build directory (which
could be a symlink as well).
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Some platforms require more complex U-Boot images than we can easily
generate via the mkimage command line, for instance to load additional
image files.
Introduce a CONFIG_SPL_FIT_SOURCE and CONFIG_SPL_FIT_GENERATOR symbol,
which can either hold an .its source file describing the image layout,
or, in the second case, a generator tool (script) to create such
a source file. This script gets passed the list of device tree files
from the CONFIG_OF_LIST variable.
A platform or board can define either of those in their defconfig file
to allow an easy building of such an image.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
For a board or platform to support FIT loading in the SPL, it has to
provide a board_fit_config_name_match() routine, which helps to select
one of possibly multiple DTBs contained in a FIT image.
Provide a simple function which chooses the DT name U-Boot was
configured with.
If the DT name is one of the two Pine64 versions, determine the exact
model by checking the DRAM size.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@openedev.com>
The sunxi SPL was holding the detected RAM size in some local variable
only, so it wasn't accessible for other functions.
Store the value in gd->ram_size instead, so it can be used later on.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The SPL stack is usually located at the end of SRAM A1, where it grows
towards the end of the SPL.
For the really big AArch64 binaries the stack overwrites code pretty
soon, so move the SPL stack to the end of SRAM A2, which is unused at this
time.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Jagan Teki <jagan@openedev.com>
The generic ARMv8 assembly code contains routines for setting up
a CCN interconnect, though the Freescale SoCs are the only user.
Link this code only for Freescale targets, this saves some precious
bytes in the chronically tight SPL.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Not every SoC needs to set up the GIC interrupt controller, so link
think code only when the respective config option is set.
This shaves off some bytes from the SPL code size.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
mksunxiboot limits the size of the resulting SPL binaries to pretty
conservative values to cover all SoCs and all boot media (NAND).
It turns out that we have limit checks in place in the build process,
so mksunxiboot can be relaxed and allow packaging binaries up to the
actual 32KB the mask boot ROM actually imposes.
This allows to have a bigger SPL, which is crucial for AArch64 builds.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
SPL_FIT obviously requires libfdt in SPL, so let Kconfig express that by
selecting SPL_OF_LIBFDT.
Also make the actual options that users want (SPL signature and SPL FIT
loading) visible in the menu and let them select the SPL_FIT as a
requirement.
Also remove the now redundant SPL_OF_LIBFDT from those Kconfigs that had
it in for the SPL FIT loading feature.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[Remove change from configs/evb-rk3399_defconfig]
Signed-off-by: Jagan Teki <jagan@openedev.com>
So far we were not using the FIT image format to its full potential:
The SPL FIT loader was just loading the first image from the /images
node plus one of the listed DTBs.
Now with the refactored loader code it's easy to load an arbitrary
number of images in addition to the two mentioned above.
As described in the FIT image source file format description, iterate
over all images listed at the "loadables" property in the configuration
node and load every image at its desired location.
This allows to load any kind of images:
- firmware images to execute before U-Boot proper (for instance
ARM Trusted Firmware (ATF))
- firmware images for management processors (SCP, arisc, ...)
- firmware images for devices like WiFi controllers
- bit files for FPGAs
- additional configuration data
- kernels and/or ramdisks
The actual usage of this feature would be platform and/or board specific.
Also update the FIT documentation to mention the new SPL feature and
provide an example .its file to demonstrate its features.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Lokesh Vutla <lokeshvuta@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
At the moment we load two images from a FIT image: the actual U-Boot
image and the .dtb file. Both times we have very similar code, that deals
with alignment requirements the media we load from imposes upon us.
Factor out this code into a new function, which we just call twice.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Jagan Teki <jagan@openedev.com>
Currently the SPL FIT loader always looks only for the first image in
the /images node a FIT tree, which it loads and later executes.
Generalize this by looking for a "firmware" property in the matched
configuration subnode, or, if that does not exist, for the first string
in the "loadables" property. Then using the string in that property,
load the image of that name from the /images node.
This still loads only one image at the moment, but refactors the code to
allow extending this in a following patch.
To simplify later re-usage, we also generalize the spl_fit_select_index()
function to not return the image location, but just the node offset.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Lokesh Vutla <lokeshvuta@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Jagan Teki <jagan@openedev.com>
Currently the SPL FIT loader uses the spl_fit_select_fdt() function to
find the offset to the right DTB within the FIT image.
For this it iterates over all subnodes of the /configuration node in
the FIT tree and compares all "description" strings therein using a
board specific matching function.
If that finds a match, it uses the string in the "fdt" property of that
subnode to locate the matching subnode in the /images node, which points
to the DTB data.
Now this works very well, but is quite specific to cover this particular
use case. To open up the door for a more generic usage, let's split this
function into:
1) a function that just returns the node offset for the matching
configuration node (spl_fit_find_config_node())
2) a function that returns the image data any given property in a given
configuration node points to, additionally using a given index into
a possbile list of strings (spl_fit_select_index())
This allows us to replace the specific function above by asking for the
image the _first string of the "fdt" property_ in the matching
configuration subnode points to.
This patch introduces no functional changes, it just refactors the code
to allow reusing it later.
(diff is overly clever here and produces a hard-to-read patch, so I
recommend to throw a look at the result instead).
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Lokesh Vutla <lokeshvuta@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Jagan Teki <jagan@openedev.com>
Reserve enough space below the kernel base.
The assumed address map is:
80000000 - 80ffffff : for IPP
81000000 - 81ffffff : for ARM secure
82000000 - : for Linux
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
When booting from ARM Trusted Firmware, U-Boot runs in EL1-NS.
The boot flow is as follows:
BL1 -> BL2 -> BL31 -> BL33 (i.e. U-Boot)
This boot sequence works fine for LD11 SoC (Cortex-A53), but LD20
SoC (Cortex-A72) hangs in U-Boot. The solution I found is to
read sctlr_el1 and write back the value as-is. This should be
no effect, but surprisingly fixes the problem for LD20 to boot.
I do not know why.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Remove 'pad-offset' of soc_gpio_s5_0, soc_gpio_s5_1, soc_gpio_s5_2,
pin_usb_host_en0 and pin_usb_host_en1. These offsets are actually
wrong. Correct value should be added by 0x2000, but since they
are supposed to be 'mode-gpio', 'pad-offset' is not needed at all.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add a device-tree property use-lvl-write-cache that will cause
writes to lvl to be cached instead of read from lvl before each
write. This is required on some platforms that have the register
implemented as dual read/write (such as Baytrail).
Prior to this fix the blue USB port on the Minnowboard Max was
unusable since USB_HOST_EN0 was set high then immediately set
low when USB_HOST_EN1 was written.
This also resolves the 'gpio clear | set' command warning like:
"Warning: value of pin is still 0"
Signed-off-by: George McCollister <george.mccollister@gmail.com>
<rebased on latest origin/master, fixed all baytrail boards>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds a remove function to the Intel ICH SPI driver, that will
be called upon U-Boot exit, directly before the OS (Linux) is started.
This function takes care of configuring the BIOS registers in the SPI
controller (similar to what a "standard" BIOS or coreboot does), so that
the Linux MTD device driver is able to correctly read/write to the SPI
NOR chip. Without this, the chip is not detected at all.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Jagan Teki <jteki@openedev.com>
This patch adds a call to dm_remove_devices_flags() to
bootm_announce_and_cleanup() so that drivers that have one of the removal
flags set (e.g. DM_FLAG_ACTIVE_DMA_REMOVE) in their driver struct, may
do some last-stage cleanup before the OS is started.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This new flag can be added to DM device drivers, which need to do some
final configuration before U-Boot exits and the OS (e.g. Linux) is
started. The remove functions of those drivers will get called at
this stage to do these last-stage configuration steps.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
On my x86 platform I've noticed, that calling dm_uninit() or the new
function dm_remove_devices_flags() does not remove the desired device at
all. Debugging showed, that the serial uclass returns -EPERM in
serial_pre_remove(). This patch sets the force parameter when calling
stdio_deregister_dev() resulting in a removal of the device.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Convert the pci_mmc driver over to driver model and migrate all x86 boards
that use it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Now that we have ACPI S3 support on Intel MinnowMax board, document
some generic information of S3 and how to test it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
U-Boot sets up the real mode interrupt handler stubs starting from
address 0x1000. In most cases, the first 640K (0x00000 - 0x9ffff)
system memory is reported as system RAM in E820 table to the OS.
(see install_e820_map() implementation for each platform). So OS
can use these memories whatever it wants.
If U-Boot is in an S3 resume path, care must be taken not to corrupt
these memorie otherwise OS data gets lost. Testing shows that, on
Microsoft Windows 10 on Intel Baytrail its wake up vector happens to
be installed at the same address 0x1000. While on Linux its wake up
vector does not overlap this memory range, but after resume kernel
checks low memory range per config option CONFIG_X86_RESERVE_LOW
which is 64K by default to see whether a memory corruption occurs
during the suspend/resume (it's harmless, but warnings are shown
in the kernel dmesg logs).
We cannot simply mark the these memory as reserved in E820 table
because such configuration makes GRUB complain: unable to allocate
real mode page. Hence we choose to back up these memories to the
place where we reserved on our stack for our S3 resume work.
Before jumping to OS wake up vector, we need restore the original
content there.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
Introduce a new CONFIG_S3_VGA_ROM_RUN option so that U-Boot can
bypass executing VGA roms in S3.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
Before jumping to OS waking up vector, we need turn on ACPI mode
for S3, just like what we do for a normal boot.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
To do something more in acpi_resume() like turning on ACPI mode,
we need locate ACPI FADT table pointer first. But currently this
is done in acpi_find_wakeup_vector().
This changes acpi_resume() signature to accept ACPI FADT pointer
as the parameter. A new API acpi_find_fadt() is introduced, and
acpi_find_wakeup_vector() is updated to use FADT pointer as the
parameter as well.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
enter_acpi_mode() is useful on other boot path like S3 resume, so
make it public.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
In enter_acpi_mode() PM1_CNT register is changed to PM1_CNT_SCI_EN
directly without preserving its previous value. Update to change
the register access to read-modify-write (RMW).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
Call board_final_cleanup() before write_tables(), so that anything
done in board_final_cleanup() on a normal boot path is also done
on an S3 resume path.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
When SeaBIOS is being used, U-Boot reserves a memory area to be
used for configuration tables like ACPI. But it should not be
cleared otherwise ACPI table will be missing.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
At the end of pre-relocation phase, save the new stack address
to CMOS and use it as the stack on next S3 boot for fsp_init()
continuation function.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
This adds a library that provides CMOS (inside RTC SRAM) access
at a very early stage when driver model is not available yet.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
In an S3 resume path, U-Boot does everything like a cold boot except
in the last_stage_init() it jumps to the OS resume vector.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
This adds one API acpi_find_wakeup_vector() to locate OS wakeup
vector from the ACPI FACS table, to be used in the S3 boot path.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
This adds a wake up stub before jumping to OS wake up vector.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
U-Boot itself as well as everything that is consumed by U-Boot (like
heap, stack, dtb, etc) needs to be reserved and reported in the E820
table when S3 resume is on.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
When U-Boot is built without ACPI S3 support, it should not report
S3 in the ACPI table otherwise when kernel does STR it won't work.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
Add one member in the global data to store previous sleep state,
and display the state during boot in print_cpuinfo().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
When ACPI S3 resume is turned on, we should pass different boot mode
to FSP init instead of default BOOT_FULL_CONFIG.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
This adds OS_RESUME (0x40) and RESUME_FAILURE (0xed) post codes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
This adds APIs for determining previous sleep state from ACPI I/O
registers, as well as clearing sleep state on BayTrail SoC.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
This introduces a Kconfig option for ACPI S3 resume, as well as a
header file to include anything related to ACPI S3 resume.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
- Add #undef CONFIG_DM_MMC_OPS to omap3_logic in the SPL build case, to
match other TI platforms in the same situation.
Signed-off-by: Tom Rini <trini@konsulko.com>
To fix the timeout of sending the write command, enable the quirk
SDHCI_QUIRK_WAIT_SEND_CMD.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Newer SoCs use same TV encoder unit. Split it out so it can be reused
with new DM video driver.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
Due to a typo, the 24 bit-per-pixel configuration ends in 24BMP
instead of 24BPP. This change renames it throughout the source tree
for consistency and to make moving these options into Kconfig easier
and less error-prone.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Instead of having drivers/video/rockchip/Kconfig point outside of its
hierarchy for dw_hdmi.o, we should use a configuration-option to
include the Designware HDMI support.
This change introduces a new config option (not to be selected via
menuconfig, but to be selected from a dependent video driver's
configuration option) that enables dw_hdmi.o and selects it whenever
the HDMI support for Rockchip SoCs is selected.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Some DVI monitors don't work in HDMI mode. Set it only if edid data
explicitly states that it is supported.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
Some DVI monitors don't show anything in HDMI mode since audio stream
confuses them. To solve this situation, this commit adds HDMI flag in
timing data and sets it accordingly during edid parsing.
First existence of extension block is checked. If it exists and it is
CEA861 extension, then data blocks are checked for presence of HDMI
vendor specific data block. If it is present, HDMI flag is set.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
Timing flags are never set, so they may contain garbage. Since some
drivers check them, video output may be broken on those drivers.
Initialize them to 0 and check for few common flags.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
Recent commits of DTC introduced new warnings checking PCI and simple
buses, unit address formatting, and stricter node and property name
checking. Disable the new DTC warnings by default. As before,
warnings are enabled with W=*. The strict node and property name
checks are a bit subjective, so they are only enabled for W=2.
(This policy reflects the commit 8654cb8d0371 of Linux.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Enable TI_COMMON_CMD_OPTIONS and remove similar options
from the defconfig. Updated with savedefconfig
CMD_USB isn't enabled yet. I have some testing to do with
musb.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Now that CMD_POWEROFF can turn off the twl4030, let's imply that
just incase someone wants to disable it.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Follow the exiting logic for the i.MX options when migrating this
option.
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Marek Vasut <marex@denx.de>
The following options are migrated over fully now:
- USB_EHCI_ATMEL
- USB_EHCI_MARVELL
- USB_EHCI_MX6
- USB_EHCI_MX7
- USB_EHCI_MSM
- USB_EHCI_ZYNQ
- USB_EHCI_GENERIC
This also requires fixing the depends on USB_EHCI_MARVELL as it's used
by Orion5X and Kirkwood as well.
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Migrate the rest of the users of CONFIG_USB_EHCI_HCD over to Kconfig.
For a few SoCs, imply or default y this if USB is enabled. In some
cases we had not already migrated to CONFIG_USB so do that as well.
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Marek Vasut <marex@denx.de>
T1023 and T1024 have 4 SerDes lanes. Fix macro SRDS_MAX_LANES
and use this macro instead of hard-coded value in t1024_serdes.c.
Signed-off-by: Paulo Zaneti <paulo.zaneti@datacom.ind.br>
Signed-off-by: York Sun <york.sun@nxp.com>
In order to be able to migrate the various SoC EHCI CONFIG options we
first need to finish the switch from CONFIG_USB_EHCI to
CONFIG_USB_EHCI_HCD.
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Marek Vasut <marex@denx.de>
The symbol CONFIG_OMAP3_LOGIC_USE_NEW_PRODUCT_ID was recently dropped
from usage and CONFIG_OMAP3_MICRON_DDR is unused in code.
Signed-off-by: Tom Rini <trini@konsulko.com>
The symbol CONFIG_OMAP_VC_I2C_HS_MCODE always uses the default value.
Restructure the comment and code such that if a need arises later to use
another value we can address this then.
Signed-off-by: Tom Rini <trini@konsulko.com>
Move this entry to Kconfig. As it is a hardware watchdog, select
HW_WATCHDOG. While we could default to enabling this for all platforms,
it is currently only enabled by default on AM33XX, so keep that logic
today.
Cc: Roger Meier <r.meier@siemens.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This particular quirk is not enabled in any config files today. It does
however exist and is handled correctly in device trees and via
CONFIG_DM_SPI. So we drop the symbol now and add a comment to indicate
that any (new) boards that require this quirk need to enable DM_SPI
instead.
Signed-off-by: Tom Rini <trini@konsulko.com>
The symbols CONFIG_OMAP3_GPIO_X control if we enable the clocks for a
given GPIO bank in U-Boot. select the required banks for each target.
In some cases we need to also migrate from CONFIG_USB_EHCI (deprecated,
in include/configs/) to CONFIG_USB_EHCI_HCD as we only require the GPIO
bank to be enabled if USB is also enabled.
Signed-off-by: Tom Rini <trini@konsulko.com>
This driver is used often enough such that we want to have this enabled
by default on any ARCH_OMAP2PLUS board, and this only compiles on
ARCH_OMAP2PLUS due to required defines, so mark that as the depends.
Signed-off-by: Tom Rini <trini@konsulko.com>
We no longer have a need for a per-board CONFIG_OMAP3_xxx define (we
have CONFIG_TARGET_xxx when this is required), so drop these unused
references.
Signed-off-by: Tom Rini <trini@konsulko.com>
While there are a few different OMAP4 SoCs, today we always set
CONFIG_OMAP4430 and CONFIG_OMAP44XX. Convert the few test of
CONFIG_OMAP4430 to CONFIG_OMAP44XX.
Cc: Marek Vasut <marex@denx.de>
Cc: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Tom Rini <trini@konsulko.com>
We make use of CONFIG_OMAP3_EVM today to know when to do a specific
tweak in MUSB. This can be tested on via CONFIG_TARGET_OMAP3_EVM
instead, so switch there so we can drop the now unused symbol
CONFIG_OMAP3_EVM. In investigating what to do about the symbol usage we
see that the cairo board defines the same function, but never called it
(as it does not define CONFIG_OMAP3_EVM) and was just returning anyhow,
so drop that function from that board.
Cc: "Albert ARIBAUD (3ADEV)" <albert.aribaud@3adev.fr>
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
While in theory this value could be used in places outside of "omap5"
(such as OMAP4), we only make use of it today in OMAP5, so place the
Kconfig entry there. Given that Kconfig lets us provide a default, we
drop CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC entirely. The contents of
doc/README.omap-reset-time make a good help entry, so adjust them
slightly and delete the file. Move the comment about range to where we
use the value now, and have Kconfig enforce the upper bound.
Signed-off-by: Tom Rini <trini@konsulko.com>
In the two cases in the code where we use CONFIG_OMAP as a useful test
currently we can make use of CONFIG_ARCH_OMAP2PLUS instead. With that
changed we can drop all defines of CONFIG_OMAP. While in here,
CONFIG_OMAP3430 is only defined and then never used, so drop.
Signed-off-by: Tom Rini <trini@konsulko.com>
We have nothing defining CONFIG_OMAP243X since we dropped the omap243x
platforms, drop these tests.
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Heiko Schocher <hs@denx.de>
Drop custom command prompt string in favor
of default used by U-Boot. This helps in
easier automation setup across boards.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Coldfire arch is not happy with timer_init since interrupt handlers
are still not set at that stage, and the boot hangs silently.
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
ATF(ARM Trusted Firmware) is used by ARM arch64 SoCs, find more infomation
about ATF at: https://github.com/ARM-software/arm-trusted-firmware
SPL is considered as BL2 in ATF terminology, it needs to load other parts
of ATF binary like BL31, BL32, SCP-BL30, and BL33(U-Boot). And needs to
prepare the parameter for BL31 which including entry and image information
for all other images. Then the SPL handle PC to BL31 with the parameter,
the BL31 will do the rest of work and at last get into U-Boot(BL33).
This patch needs work with patches from Andre for SPL support multi
binary in FIT.
The entry point of bl31 and bl33 are still using hard code because we
still can not get them from the FIT image information.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This simplifies makefiles. Also, arrange the order of objects in
drivers/mmc/Makefile so that the framework objects are listed before
drivers.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Now CONFIG_GENERIC_MMC and CONFIG_MMC match for all defconfig.
We do not need two options for the same feature. Deprecate the
former.
This commit was generated with the sed script 's/GENERIC_MMC/MMC/'
and manual fixup of drivers/mmc/Kconfig.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
As commit 54925327fa ("mmc: move CONFIG_GENERIC_MMC to Kconfig")
addressed, this is one of the last weird defconfigs that define
CONFIG_GENERIC_MMC without CONFIG_MMC.
Now I took a closer look at this. Given that both CONFIG_CMD_MMC
and CONFIG_GENERIC_MMC are set for this defconfig, CONFIG_MMC should
be enabled.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
As commit 54925327fa ("mmc: move CONFIG_GENERIC_MMC to Kconfig")
addressed, this is one of the last weird defconfigs that define
CONFIG_GENERIC_MMC without CONFIG_MMC.
Now I took a closer look at this. Given that neither CONFIG_CMD_MMC
nor CONFIG_MMC is set for this defconfig, CONFIG_GENERIC_MMC
should be disabled.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This driver is a counterpart of drivers/mmc/host/sdhci-cadence.c
from Linux. Some updates for v4.12-rc1 can be imported to U-Boot.
- Fix value of SDHCI_CDNS_HRS04_RDATA_SHIFT
- Add polling for ACK bit to be sure that data are written to
the PHY register
- Retrieve PHY values from DT properties instead of fixed data
The following is the list of upstream commits:
- Linux commit 4e03f628b464e0580abadf5161eaa38c61d20943
mmc: sdhci-cadence: fix bit shift of read data from PHY port
- Linux commit a0f8243229ed071c8da0ea7cedc1b7bf1b1515da
mmc: sdhci-cadence: Fix writing PHY delay
- Linux commit a89c472d8b55c5afc4c79e6e3d1338730034eb01
mmc: sdhci-cadence: Update PHY delay configuration
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
In the programmable clock mode, the SDCLK frequency is incorrectly
assigned when the maximum clock has been assigned during probe,
this causes the SDHCI not work well.
In the programmable clock mode, when calculating the SDCLK Frequency
Select, when the maximum clock has been assigned, it is the actual
value, should not be multiplied by host->clk_mul. Otherwise, the
maximum clock is multiplied host->clk_mul by the base clock achieved
from the BASECLKF field of the Capabilities 0 Register.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
This option is pretty old. It predates CONFIG_SYS_I2C which is itself
deprecated in favour of driver model. Disable it for all boards.
Also drop I2C options which depend on this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Now that we support using TI_COMMON_CMD_OPTIONS,
we dont have to enable a number of commands explicitly
in the defconfig if we enable TI_COMMON_CMD_OPTIONS.
Enable TI_COMMON_CMD_OPTIONS and regenerate the defconfig
using "make savedefconfig".
CMD_GPIO has been kept disabled because there is no GPIO
support (yet) on OMAP-L138 LCDK.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
OMAP-L138 LCDK board can benefit from using the commonly
used commands enabled by TI_COMMON_CMD_OPTIONS.
Source the relevant Kconfig file so TI_COMMON_CMD_OPTIONS
can be enabled for OMAP-L138 LCDK board in a future patch.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
We will see warnings such as:
net/eth_common.c:57:61: warning: data argument not used by format string [-Wformat-extra-args]
sprintf(enetvar, index ? "%s%daddr" : "%saddr", base_name, index);
~~~~~~~~ ^
With clang. In this case we do not want to re-write our code to be less
compact as the above is intentional and readable. Add a comment above
the disabling so that it's clear why we want that warning off.
Signed-off-by: Tom Rini <trini@konsulko.com>
The function tpm_xfer returns int so make 'err' be int rather than
uint32_t so that we can catch an error condition. Reported by
clang-3.8.
Signed-off-by: Tom Rini <trini@konsulko.com>
We declare that gpio_base (which is the base for counting gpios, not an
address) is unsigned. Therefore the comparison with >= 0 is always
true. As the desire is to allow for this base number to be 0, we can
just drop this check. Reported by clang-3.8.
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
We first check that if argc is less than 2 we return CMD_RET_USAGE. We
then see if argc is greater than 2 and if so call get_led_cmd() to set
'cmd' and otherwise set it to LEDST_COUNT (which will always be positive
as it's an enum with 0 already assigned). Therefore the test on if cmd
is less than 0 will always be false and simply be omitted. Reported by
clang-3.8.
Signed-off-by: Tom Rini <trini@konsulko.com>
The function cmd_get_data_size() returns an int and not unsigned. So we
should assign it to an int rather than unsigned so that we can later
compare the return value. Reported by clang-3.8.
Signed-off-by: Tom Rini <trini@konsulko.com>
On most architectures we do not call print_std_bdinfo() so mark it with
__maybe_unused. Reported by clang-3.8.
Signed-off-by: Tom Rini <trini@konsulko.com>
This particular macro hasn't been used in the code for some time, remove
these references that were missed.
Signed-off-by: Tom Rini <trini@konsulko.com>
Change tbu/l type to unsigned int.
>From the timer file for arm,
"(((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;" is used,
This piece code is based on tbu/tbl is 32bits, so change the type to
unsigned int.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
The function 'spin_wheel' is declared as inline, but not static and thus
we see warnings that 'w' and 'p' are declared static in a non-static
inline function. Correct this by marking spin_wheel as static inline.
Cc: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
With gcc-6 and later we may get a warning such as:
.../common/cli_readline.c:20:21: warning: ‘tab_seq’ defined but not used [-Wunused-const-variable=]
static const char tab_seq[] = " "; /* used to expand TABs */
^~~~~~~
.../common/cli_readline.c:19:19: warning: ‘erase_seq’ defined but not used [-Wunused-const-variable=]
static const char erase_seq[] = "\b \b"; /* erase sequence */
^~~~~~~~~
Because in SPL we're normally not doing interactive commands anyhow, so
lets just not compile this at all in SPL. This also means that we need
to correct the logic (and comment) about what the drivers/ddr/fsl/ and
CONFIG_FSL_DDR_INTERACTIVE requires and this will be included in SPL
there.
Signed-off-by: Tom Rini <trini@konsulko.com>
The variable netdev_ethtool_ops is not referenced, drop it. However
with gcc-6 or later we fail to even compile as we do not have the
required struct definition in U-Boot.
Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
The variables SEQ_SWRESET, SEQ_ELVSS_ON, SEQ_TEMP_SWIRE, SEQ_APON and
SEQ_SLPIN are unreferenced, drop.
Cc: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
The variable nfc_pads is only referenced when CONFIG_CMD_NAND is set,
add a gaurd. The variable gpio_pads is never referenced, drop it. The
variable usdhc4_pads are only referenced when we do not have
CONFIG_CMD_NAND set and we are not doing an SPL build, modify the
existing guard.
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
The variables prg_stage2_prepare, prg_stage2_success and prg_stage_fail
are only referenced when CCDM_SECOND_STAGE is set, move these to be by
the existing guard.
Cc: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
The variable nfc_pads is only referenced when CONFIG_CMD_NAND is set,
move the existing guard and drop a now redundant comment. The variable
gwproto_gpio_pads is never referenced, remove it.
Cc: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
The variable usdhc2_pads is only referenced during SPL builds, add a guard.
Cc: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Tom Rini <trini@konsulko.com>
The variable grf is only referenced if EARLY_DEBUG is defined so move the
declaration to be under the existing guard.
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
With gcc-6 and later we see a warning about the fact that we have a
construct of "if (test);\n\tstatement". Upon reviewing the code, the
intention here is as the compiler suggests, we only want to execute the
indented statement if the test was true.
Cc: Sergei Poselenov <sposelenov@emcraft.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
The value assigned to variable 'value' is never used.
The problem was indicated by clang scan-build.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
The rsa_st struct has been made opaque in 1.1.x, add forward compatible
code to access the n, e, d members of rsa_struct.
EVP_MD_CTX_cleanup has been removed in 1.1.x and EVP_MD_CTX_reset should be
called to reinitialise an already created structure.
Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl>
The rsa_st struct has been made opaque in 1.1.x, add forward compatible
code to access the n, e, d members of rsa_struct.
EVP_MD_CTX_cleanup has been removed in 1.1.x and EVP_MD_CTX_reset should be
called to reinitialise an already created structure.
The value assigned to saved_offset is never used.
The problem was indicated by clang scan-build.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
strdup uses malloc to allocate memory for str.
If we cannot bind to the generic driver we should release
the memory.
The problem was indicated by clang scan-build.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
env_attr_lookup call env_attr_walk with
callback = regex_callback.
In env_attr_walk
attributes = strchr(entry_cpy, ENV_ATTR_SEP)
will return NULL if ENV_ATTR_SEP is not found.
In the aftermath regex_callback may call
strlen(attributes)
with a NULL value which will lead to a failure.
The problem was indicated by scan-clam.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
For early debug, the following configs needs to be enabled:
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_OMAP=y
CONFIG_DEBUG_UART_BASE=0x44e09000
CONFIG_DEBUG_UART_CLOCK=48000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
For early debug, the following configs needs to be enabled:
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_OMAP=y
CONFIG_DEBUG_UART_CLOCK=48000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
For DRA7xx:
CONFIG_DEBUG_UART_BASE=0x4806a000
For AM57xx:
CONFIG_DEBUG_UART_BASE=0x48020000
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
am335x supports various sysclk frequencies which can be determined
using sysboot pins. PLLs should be configures based on this
sysclk frequency. Add PLL configurations for all supported
frequencies.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Update MPU frequencies and voltages as per the latest
DM[1] dated: OCT 2011 Revised APRIL 2016, Section 5.4.
Below is the consolidated data:
MPU values for PG 2.0 and later(Package ZCZ and ZCE):
-------------------------------------------------------
| | ZCZ | ZCE |
|-------------------------------------------------------|
| | VDD[V] | ARM [MHz] | VDD[V] | ARM [MHz] |
|-------|----------|------------|----------|------------|
| NITRO | 1.325 | 1000 | NA | NA |
|-------|----------|------------|----------|------------|
| TURBO | 1.26 | 800 | NA | NA |
|-------|----------|------------|----------|------------|
|OPP120 | 1.20 | 720 | NA | NA |
|-------|----------|------------|----------|------------|
|OPP100 | 1.10 | 600 | 1.10 | 600 |
|-------|----------|------------|----------|------------|
| OPP50 | 0.95 | 300 | 0.95 | 300 |
-------------------------------------------------------
There is no eFuse blown on PG1.0 Silicons due to which there is
no way to detect the maximum frequencies supported. So default
to OPP100 for which both frequency and voltages are common on both
the packages.
[1] http://www.ti.com/lit/ds/symlink/am3356.pdf
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The SPL-DFU feature enable to load and
execute u-boot from RAM over usb from
PC using dfu-util.
Hence dfu-reset should not be issued
when dfu-util -R switch is issued.
Signed-off-by: Ravi Babu <ravibabu@ti.com>
Since SPL_DFU_SUPPORT is depends on SPL_RAM_SUPPORT,
hence select SPL_DFU_SUPPORT only when
SPL_RAM_SUPPORT is chosen.
Signed-off-by: Ravi Babu <ravibabu@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This configuration should be valid for all F7 family devices in general.
Here is the regions info:
- Region0 : 4GB : cacheable & executable.
- Region1 : 512MB : text area : strogly ordered & executable.
- Region2 : 512MB : peripherals : device memory & non-executable.
- Region3 : 512MB : peripherals : device memory & non-executable.
- Region4 : 512MB : cortexM area: strongly ordered & non-executable.
Higher region number overrides the lower region configuration.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Cortex-M archs support option memory protection unit (MPU). MPU is used
to set the memory types, attributes, access permissions for different regions,
cache policies of the device.
e.g. using MPU it is possible to configure memory region as device memory
or strongly ordered, memory attributes like execute never, cache policies
like write-back or write-through.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Data cache memory needs to be disabled before handing over control to
linux kernel. This patch populates the cleanup_before_linux stub.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Add functionality to flush & invalidate all the dcache using the
prototype declared in common header file.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
[trini: Add dummy functions for the not-enabled case]
Signed-off-by: Tom Rini <trini@konsulko.com>
CONFIG_DISTRO_DEFAULTS selects a number of things we want for Boston
defconfigs & generally describes what we want - to be able to boot an
arbitrary Linux distribution. Enable it in order to shorten the
defconfigs & to automatically keep up with any changes in the choice of
Kconfig symbols selected.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The default value of CONFIG_SYS_BOOTM_LEN is too small for typical
boston Linux kernels. Increase the limit to 64MB, which covers current
kernels with plenty of breathing room.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The boston memory map isn't suited to the simple "all memory starting
from 0" approach that the MIPS arch_fixup_fdt() implementation takes.
Instead we need to indicate the first 256MiB of DDR from 0 and the rest
from 0x90000000. Implement ft_board_setup to do that.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move the MIPS Coherence Manager (CM) Global Configuration Registers
(GCRs) away from the region of the physical address space which the
Boston board's parallel flash is found in, such that we can access all
of flash without clobbering GCRs.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Without adding a prompt for CONFIG_MIPS_CM_BASE, Kconfig doesn't allow
defconfigs to set it. Provide the prompt in order to allow for that.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
am335x_evm SPL is very close to its limit in SRAM space.
Switch to use tiny printf to reclaim some size.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
No reason to use a separate load script for am33xx than using
omap-common load script.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
For platforms that don't use device tree in SPL the only
way to mark this driver as 'required by relocation' is
with the DM_FLAG_PRE_RELOC flag. Add this to ensure that
the driver is bound.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add debug UART functions to permit omap specific ns16550 to
provide an early debug UART. This is mostly in common with
DEBUG_UART_NS16550 except for Mode definition register which
is required for selecting UART mode(16x auto-baud or 13x mode).
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Enables the pinctrl-single driver to support 16-bit registers. Only
32-bit registers were supported previously. Reduced width registers are
required for some platforms, such as OMAP.
Signed-off-by: James Balean <james@balean.com.au>
Cc: Felix Brack <fb@ltec.ch>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Felix Brack <fb@ltec.ch>
Tested-by: Felix Brack <fb@ltec.ch>
Reviewed-by: Simon Glass <sjg@chromium.org>
In single stage bootmode or falcon boot mode, the SPL shall update the
device tree that we load with the normal fixups done via
arch_fixup_fdt(), when possible (ie we have enough information in this
restricted environment to be able to do that still). This will include
for example updating them memory nodes.
Signed-off-by: Ravi Babu <ravibabu@ti.com>
[trini: Reword commit message]
Adding support for fdt fixup to update the
memory node in device tree for falcon boot.
This is needed for single stage or falcon
bootmode, to pass memory configuration to
kernel through DT memory node.
Signed-off-by: Ravi Babu <ravibabu@ti.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Declare the size of ddr very early in spl, so that this can be
used to enable cache.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Ravi Babu <ravibabu@ti.com>
Move the assignment of board info to global data a bit early which is
safe,
so that ram details can be used to enable caches.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Ravi Babu <ravibabu@ti.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
When OF control is enabled for the SPL stage, nodes are removed from
the DTB to reduce its size. While /chosen is kept, /config is removed.
There's no reason why /chosen should be kept over /config (and as we
would like to put properties into /config that control the SPL stage),
we add '/config' to the list of nodes to be retained for the SPL stage.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
This adds documentation on the u-boot,spl-payload-offset property
(which overrides CONFIG_SYS_SPI_U_BOOT_OFFS during the SPI loading in
the SPL stage, if present).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
For the RK3399-Q7, we need some flexibility (depending on the feature
set we include in the SPL stage and how large our SPI flash is) in
positioning the SPL payload (i.e. the FIT image containing U-Boot, ATF
and the M0 payload) in our SPI flash.
To avoid having to deal with this through different U-Boot images, we
introduce a the '/config/u-boot,spl-payload-offset' property node
allow it to override the default setting.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
At present there is not operation to invalidate a cache range. This seems
to be needed to fill out the cache operations. Add an implementation based
on the flush operation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
Similar to what blk_get_device_part_str() does, this patch makes
part_get_info_by_name() return the partition number in case of a match.
This is useful when the partition number is needed and not just the
descriptor.
Signed-off-by: Alex Deymo <deymo@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Update the Android image header format to the latest version published
in AOSP. The original code moved to a new repository, so this patch also
updates the reference to that path.
Signed-off-by: Alex Deymo <deymo@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Hi,
A kind reminder to look at this patch (already reviewed by Marek and acked by Lukasz), and if possible to put it in the next pull list, or the one after is timing is too short.
Thanks in advance for your time
Best Regards
Nicolas
-----Original Message-----
From: Nicolas LE BAYON
Sent: mardi 25 avril 2017 10:18
To: Nicolas LE BAYON <nicolas.le.bayon@st.com>; u-boot@lists.denx.de; lukma@denx.de; marex@denx.de
Cc: nlebayon@gmail.com; Patrice CHOTARD <patrice.chotard@st.com>; Jean-philippe ROMAIN <jean-philippe.romain@st.com>
Subject: [U-Boot][PATCH v7] usb: gadget: avoid variable name clipping in cb_getvar
From: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Instead of using a fixed-size array to store variable name, preferring a dynamic allocation treats correctly all variable name lengths.
Variable names are growing through releases and features. By this way, name clipping is prevented.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Lukasz Majewski <lukma@denx.de>
Add runtime, modeboot env which is setting mmcboot, or
nandboot based on the bootdevice so-that conditional
macros b/w MMC and NAND for CONFIG_BOOTCOMMAND should
be avoided in config files.
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Add runtime, modeboot env which is setting mmcboot, or
nandboot based on the bootdevice so-that conditional
macros b/w MMC and NAND for CONFIG_BOOTCOMMAND should
be avoided in config files.
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Fix calculation. do_div can not handle negative values.
Use div_s64_rem to handle the calculation.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
>From IC guys:
"
After a thorough accuracy study of the Temp sense circuit,
we found that with our current equation, an average part can
read 7 degrees lower than a known forced temperature.
We also found out that the standard variance was around 2C;
which is the tightest distribution that we could create.
We need to change the temp sense equation to center the average
part around the target temperature.
"
New equation:
Tmeas = (Nmeas - n1) / slope + t1 + offset
n1= fused room count
t1= 25
offset=3.580661
slope= 0.4148468 – 0.0015423*n1
According the new equation, update the thermal driver.
c1 and c2 changed to u64 type and update comments.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
This adds a new firefly-rk3399 board, MIPI support for rk3399 and
rk3288, rk818 pmic support, mkimage improvements for rockchip and a few
other things.
Enable pwm0 for display of rk3399 evb board. The PWM do not have decicated
interrupt number in dts and can not get periph_id by pinctrl framework. So
init them here.
Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
plat->size here is used to reserve frame buffer space befor relocation.
our mipi panel use 24 bitwidth, and vop require 32bit align. So the frame
buffer size should be at least 1920*1200*32/8.
Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Because the bitwidth is different for different display mode, so we need
to set them according to demand.
Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add mipi display mode for rk3399 vop, so that we can use mipi panel
for display.
Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
It's caused by the difference of clk_set_rate function implement between
rk3288 andd rk3399.
clk_set_rate() of rk3288 return 0 in normal condition.
clk_set_rate() of rk3399 return input parameter in normal condition.
So check clk_set_rate's return value by IS_ERR_VALUE.
Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Since this driver can be used for rk8xx series pmic,
let's rename rk808 to rk8xx, to make it clear.
Configs parts are done by sed -i "s/RK808/RK8XX/g" `grep RK808 -lr ./`
Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Add support for the rk818 regulator. The regulator module consists
of 4 DCDCs, 9 LDOs, 1 switch and 1 BOOST converter which is used to
power OTG and HDMI5V.
Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The RK818 chip is a Power Management IC (PMIC) for multimedia and handheld
devices.
For boards use rk818, the input current should be set in the early stage, before
ddr initialization.
Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Both RK808 and RK818 chips are using a similar register map,
so we can reuse them.
I have also add reg prefix to exist registers, to keep them same style.
Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Set ethernet mac address in late init for Tinker Board,
prevents getting a random mac address each boot.
Read mac address from eeprom, first 6 bytes from m24c08@50.
Same as /etc/init.d/rockchip.sh on Tinker OS.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
To add HDMI support for the RK3399, this commit provides the needed
pinctrl functionality to configure the HDMI I2C pins (used for reading
the screen's EDID).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This allows requests (via the DTS) for PCLK_HDMI_CTRL/PCLK_VIO_GRF,
which are clock gates in the HDMI output path for the RK3399.
As these are enabled by default (i.e. after reset), we don't implement
any logic to actively open/close these clock gates and simply assume
that their reset-default has not been changed.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
With the RK3399 DRAM controller (DMC) driver providing all the
infrastructure, retrieve the DRAM size from the DMC init in the
board-specific code (instead of hard-coding) for the RK3399-Q7 (Puma).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The (non-secure) efuse node in the DTS requests PCLK_EFUSE1024NS.
To allow us to add a efuse-driver (and more importantly, to allow
probes of such a driver to succeed), we need need to accept requests
for PCLK_EFUSE1024NS and return a non-error result.
As PCLK_EFUSE1024NS is enabled by default (i.e. after reset), we don't
implement any logic to manage this clock gate and simply assume that
the reset-default has not been changed.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The file is from evb-rk3399_defconfig with changes:
- use rk3399-firefly dtb
- re-order by make savedefconfig
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add test case for new interface set_invert().
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fix typo in subject and build error in sandbox_pwm_set_invert():
Signed-off-by: Simon Glass <sjg@chromium.org>
Rockchip pwm need to init polarity, implement pwm_set_invert()
to do it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
The latest kernel PWM drivers enable the polarity settings. When system
run from U-Boot to kerenl, if there are differences in polarity set or
duty cycle, the PMW will re-init:
close -> set polarity and duty cycle -> enable the PWM.
The power supply controled by pwm regulator may have voltage shaking,
which lead to the system not stable.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Firefly-rk3399 is a bord from T-Firefly, you can find detail about
it here:
http://en.t-firefly.com/en/firenow/Firefly_RK3399/
This patch add basic node for the board and make it able to bring
up.
Peripheral/interfaces on board:
- usb hub which connect to ehci controller;
- UART2 debug
- eMMC
- PCIe
- USB 3.0 HOST, type-C port
- sdio, sd-card
- HDMI
- Ethernet
- OPTICAL
- WiFi/BT
- MIPI CSI/DSI
- IR
- EDP/DP
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
The kernel dts has update a lot since the first time we commit rk3399.dtsi,
sync with kernel for further development.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
At present dtoc assumes that nodes which are phandles do not themselves
reference other phandle nodes. Unfortunately this is not necessarilly
true. As a result we can currently output C code which does not compile
because a node declaration can be referenced before it is declared.
Adjust the code to explicitly output all phandle nodes needed by node
before the node itself is output.
This fixes building with the latest rk3399-firefly.dts from Linux, which
has reordered the nodes.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
The code to generate the tables is quite long. Move the node-output code
into its own function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
The 'clock-freq-min-max' property was deprecated in the upstream
(i.e. Linux) DTS bindings in favor of the 'max-frequency' property.
With the latest RK3399 DTSI does no longer include the deprecated
property and the rockchip_dw_mmc driver requiring it to be present,
the driver doesn't bind to the node in the RK3399 DTSI any longer
(thus breaking access to the SD card on the RK3399-Q7 board).
To fix this, we implement a similar logic as in the Linux driver: if
the deprecated property is present, we issue a warning (if DEBUG is
enabled); if it is missing, we require 'max-frequency' to be set and
use it to create a min/max value-pair.
See b023030f10
for the deprecation/matching change in Linux.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The clocking of the designware MMC controller in the upstream
(i.e. Linux) RK3399 has changed/does not match what the current DTS in
U-Boot uses: the first clock entry now is HCLK_SDMMC instead of
SCLK_SDMMC.
With the simple clock driver used for the RK3399, this needs a change
in the selector understood by the various case statements in the driver
to ensure that the driver still loads successfully.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
There are 3 regions used by rk3399 ATF:
- bl31 code, located at 0x10000;
- cortex-m0 code and data, located at 0xff8c0000;
- bl31 data, located at 0xff8c1000 ~ 0xff8c4000;
SPL_TEXT_BASE starts from 0xff8c2000, we need to reserve memory
for ATF data, or else there will be memory corrupt after SPL
loads the ATF image.
More detail about cortex-M0 code in ATF:
https://github.com/ARM-software/arm-trusted-firmware/commit/
8382e17c4c6bffd15119dfce1ee4372e3c1a7890
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Since our sdram driver is ready, we can use the actual size
instead of hard code.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
enable debug uart for rk3288 and print something to let people know
where we are
Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The pwm3 on evb-rk3399 is used for pwm regulator, need to invert
the polarity to make it work correctly.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
With the validation done for DDR3-1600 (i.e. 800 MHz bus clock), we
add the timings (rk3399-sdram-ddr3-1600.dtsi) and change rk3399-puma.dts
to use these by default.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Drop blank line at end of file:
Signed-off-by: Simon Glass <sjg@chromium.org>
The DDR3-1333 timings for the RK3399-Q7 (Puma) has some unintended
left-over comments in them. This change cleans the file up.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
The imagetool framework checks whether function pointer for the verify,
print and extract actions are available and will will handle their
absence appropriately.
This change removes the unnecessary functions and uses the driver
structure to convey available functionality to imagetool. This is in
fact better than having verify just return 0 (which previously broke
dumpimage, as dumpimage assumed that we had handled the image and did
not continue to probe further).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Dumpimage (it invoked with "-T rkspi" or "-T rksd") would not work due
to check_params failing. These changes ensure that we can both be called
with an empty imagename.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
This change set adds documentation to the header0 initialisation and
improves readability for the calculations of various offsets/lengths.
As the U-Boot SPL stage doesn't use any payload beyond what is covered
by init_size, we no longer add RK_MAX_BOOT_SIZE to init_boot_size.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
The calculation of the variable header size in rkcommon_vrec_header
had been update twice in the earlier series (introducing boot0-style
images to deal with the alignment of the first instruction in 64bit
binaries). Unfortunately, I didn't update the comment twice (so it
remained out-of-date).
This change brings the comment back in-sync with what the code is
doing.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
In (first) breaking and (then) fixing the rkspi tool, I realised that
the calculation of the required padding (for the header-size and the
2K-in-every-4K SPI layout) was not as self-explainatory as it could
have been. This change rewrites the code (using new, common functions
in rkcommon.c) and adds verbose in-line comments to ensure that we
won't fall into the same pit in the future...
Tested on the RK3399 (with has a boot0-style payload) with SD/MMC and SPI.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Our earlier change broke the generation of SPI images, by excluding the
2K used for header0 from the size-calculation.
This commit makes sure that these are included before calculating the
required total size (including the padding from the 2K-from-every-4K
conversion).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
To include the ability to load from an SPI flash in SPL, it's not
sufficient to define SPL_SPI_SUPPORT and SPL_SPI_FLASH_SUPPORT via
Kconfig... so we conditionally define SPL_SPI_LOAD if SPI support
is already enabled for SPL via Kconfig.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
The existing Rockchip SPI (rk_spi.c) driver also matches the hardware
block found in the RK3399. This has been confirmed both with SPI NOR
flashes and general SPI transfers on the RK3399-Q7 for SPI1 and SPI5.
This change adds the 'rockchip,rk3399-spi' string to its compatible
list to allow reuse of the existing driver.
X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit adds support for the pin-configuration of the SPI5
controller of the RK3399 through the following changes:
* grf_rk3399.h: adds definition for configuring the SPI5 pins
in the GPIO2C group
* periph.h: defines PERIPH_ID_SPI3 through PERIPH_ID_SPI5
* pinctrl_rk3399.c: adds the reverse-mapping from the IRQ# to
PERIPH_ID_SPI5; dispatches PERIPH_ID_SPI3
through SPI5 to the appropriate pin-config
function; implements the pin-configuration
for PERIPH_ID_SPI5 using the GPIO2C group
X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
The baudrate in rkspi was calculated by using an integer division
(which implicitly discarded any fractional result), then rounding to
an even number and finally clamping to 0xfffe using a bitwise AND
operator. This introduced two issues:
1) for very small baudrates (overflowing the 0xfffe range), the
bitwise-AND generates rather random-looking (wildly varying)
actual output bitrates
2) for higher baudrates, the calculation tends to 'err towards a
higher baudrate' with the actual error increasing as the dividers
become very small. E.g., with a 99MHz input clock, a request
for a 20MBit baudrate (99/20 = 4.95), a 24.75 MBit would be use
(which amounts to a 23.75% error)... for a 34 MBit request this
would be an actual outbout of 49.5 Mbit (i.e. a 45% error).
This change rewrites the divider selection (i.e. baudrate calculation)
by making sure that
a) for the normal case: the largest representable baudrate below the
requested rate will be chosen;
b) for the denormal case (i.e. when the divider can no longer be
represented), the lowest representable baudrate is chosen.
Even though the denormal case (b) may be of little concern in real
world applications (even with a 198MHz input clock, this will only
happen at below approx. 3kHz/3kBit), our board-verification team kept
complaining.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
The original clock/bitrate selection code for the rk_spi driver was a
bit limited, as it always selected a 99MHz input clock rate (which
would allow for a maximum bitrate of 49.5MBit/s), but returned -EINVAL
if a bitrate higher than 48MHz was requested.
To give us better control over the bitrate (i.e. add more operating
points, especially at "higher" bitrate---such as above 9MBit/s), we
try to choose 4x the maximum frequency (clamped to 50MBit) from the
DTS instead of 99MHz... for most use-cases this will yield a frequency
of 198MHz, but is flexible to go beyond this in future configurations.
This also rewrites the check to allow frequencies of up to half the
SPI module rate as bitrates and then clamps to whatever the DTS allows
as a maximum (board-specific) frequency and does away with the -EINVAL
when trying to select a bitrate (for cases that exceeded the hard
limit) and instead consistently clamps to the lower of the hard limit,
the soft limit for the SPI bus (from the DTS) or the soft limit for
the SPI slave device.
This replaces
"rockchip: spi: rk_spi: select 198MHz input to the SPI module for the RK3399"
"rockchip: spi: rk_spi: improve clocking code for the RK3399"
from earlier versions of this series.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
For the RK3399, i2c_set_rate (and by extension: our spi_set_rate,
which had been mindlessly following the template of the i2c_set_rate
implementation) miscalculates the rate returned due to a off-by-one
error resulting from the following sequence of events:
1. calculates 'src_div := src_freq / target_freq'
2. stores 'src_div - 1' into the register (the actual divider applied
in hardware is biased by adding 1)
3. returns the result of the DIV_RATE(src_freq, src_div) macro, which
expects the (decremented) divider from the hardware-register and
implictly adds 1 (i.e. 'DIV_RATE(freq, div) := freq / (div + 1)')
This can be observed with the SPI driver, which sets a rate of 99MHz
based on the GPLL frequency of 594MHz: the hardware generates a clock
of 99MHz (src_div is 6, the bitfield in the register correctly reads 5),
but reports a frequency of 84MHz (594 / 7) on return.
To fix, we have two options:
* either we bias (i.e. "DIV_RATE(GPLL, src_div - 1)"), which doesn't
make for a particularily nice read
* we simply call the i2c/spi_get_rate function (introducing additional
overhead for the additional register-read), which reads the divider
from the register and then passes it through the DIV_RATE macro
Given that this code is not time-critical, the more readable solution
(i.e. calling the appropriate get_rate function) is implemented in this
change.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
This change adds support for configuring the module clocks for SPI1 and
SPI5 from the 594MHz GPLL.
Note that the driver (rk_spi.c) always sets this to 99MHz, but the
implemented functionality is more general and will also support
different clock configurations.
X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Modify Makefile for rockchip video driver according to Kconfig, so that
source code will not be compiled if not needed.
Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
1. add Kconfig for rockchip video driver, so that video port can be
selected as needed.
2. move VIDEO_ROCKCHIP option to new Kconfig for concision.
Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Drop indenting in Kconfig:
Signed-off-by: Simon Glass <sjg@chromium.org>
The genunie bus clock is sclk_x for eMMC/SDMMC, add support for it.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for
it.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for
it.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
The genunie bus clock is sclk_x for eMMC/SDIO, add support for it.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
As you know, biu_clk is used for AMBA AHB/APB interface, ciu_clk is
used for communication between host and card devices. The real bus clock
is ciu, so let's rectify it.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Use regulators_enable_boot_on() instead of init regulators one by one,
the interface can init all the regulators with regulator-boot-on property.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
This is a simplified version of linux/arch/mips/bcm63xx/reset.c
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This is a simplified version of linux/arch/mips/bcm63xx/clk.c
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This driver is a simplified version of linux/drivers/leds/leds-bcm6358.c
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This board has several LEDs attached to its BCM6328 led controller.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This board has several LEDs attached to its BCM6328 led controller.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This driver can control up to 24 LEDs and supports HW blinking and serial leds.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This driver can control up to 24 LEDs and supports HW blinking and serial leds.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This driver is a simplified version of linux/drivers/leds/leds-bcm6328.c,
simplified to remove HW leds and blink fallbacks.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This SoC has one gpio bank divided into two 32 bit registers, with a total of
52 GPIOs.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This SoC has one gpio bank with a total of 32 GPIOs.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This SoC has one gpio bank divided into two 32 bit registers, with a total of
40 GPIOs.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This driver is based on linux/arch/mips/bcm63xx/gpio.c, simplified to allow
defining one or two independent banks for each Broadcom SoC.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
CFE checks CPU Thread in a different way (using register $22):
mfc0 t1, C0_BCM_CONFIG, 3 # $22
li t2, CP0_CMT_TPID # (1 << 31)
and t1, t2
bnez t1, 2f # if we are running on thread 1, skip init
nop
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Use uclass_first_device and uclass_next_device in order to avoid exceptions
for drivers that aren't probed when cpu ops are requested.
Improve code style and fix indentations.
Fix incorrect line break when cpu info is not available.
Remove unneeded brackets.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
It is based on linux/drivers/tty/serial/bcm63xx_uart.c
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Avoid duplicating do_reset definition if SYSRESET is enabled for MIPS
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add a new sysreset driver based on linux/drivers/power/reset/syscon-reboot.c,
which provides a generic driver for platforms that only require writing a mask
to a regmap offset.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit 740d5d3 added two new features but only one feature name,
which results in NULL prints when device_id feature is selected.
Before:
HG556a # cpu detail
-1: cpu@0 BCM6358A1
ID = 0, freq = 300 MHz: L1 cache, MMU, NULL
Device ID 0x2a010
-1: cpu@1 BCM6358A1
ID = 1, freq = 300 MHz: L1 cache, MMU, NULL
Device ID 0x2a010
After:
HG556a # cpu detail
-1: cpu@0 BCM6358A1
ID = 0, freq = 300 MHz: L1 cache, MMU, Device ID
Device ID 0x2a010
-1: cpu@1 BCM6358A1
ID = 1, freq = 300 MHz: L1 cache, MMU, Device ID
Device ID 0x2a010
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
All MIPS boards that support debug uart are calling debug_uart_init right at
the beginning of board_early_init_f.
Instead of doing that, let's provide a generic call to debug_uart_init right
before the call to board_init_f if debug uart is enabled for boards without
stack in SRAM.
On the other hand, boards with stack in SRAM can call earlier (right before
low level init).
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
In order to add a generic MIPS debug_uart_init call right before the call to
board_early_init_f, we need to remove all calls to debug_uart_init from every
MIPS boards.
WDR4300 doesn't provide a board_debug_uart_init and configures pinmux in
board_early_init_f instead. Since I have no idead of what's the needed uart
pinmux config, I copied the whole pinmux config to a new function that is
called from board_early_init_f if CONFIG_DEBUG_UART_BOARD_INIT is not enabled.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
In order to add a generic MIPS debug_uart_init call right before the call to
board_early_init_f, we need to remove all calls to debug_uart_init from every
MIPS boards.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
In order to add a generic MIPS debug_uart_init call right before the call to
board_early_init_f, we need to remove all calls to debug_uart_init from every
MIPS boards.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
This way we can see output about u-boot.elf being built or not.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This is needed in order to allow building it for other archs.
Move relocation comment to a better place.
Remove no longer needed dts FIXME.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
With the addition of Kconfig now having CONFIG_TWL4030_POWER and
with that being the default when OMAP34XX is selected, this
is no longer needed in include/configs and can be removed from the
whitelist.
This has only been tested on logic PD DM3730 using ti_omap3_common.h
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
As requested, I added the CONFIG_TWL4030_POWER to Kconfig and made it
the implied default when selecting OMAP34XX as a platform.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
With the addition of twl4030_power_off(), let's allow the 'poweroff' command
to run this function when CONFIG_CMD_POWEROFF is enabled.
Tested on a DM3730 with twl4030 PMIC.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
This patch also removes all the excessive code for NS16550 intiailization
as the device tree can do that now. This also adds DM_I2C and DM_MMC
since the overlying drivers have the built-in support already. The
corresponding include/config/omap3_logic.h also reduced in size
due to the new device tree support.
Signed-off-by: Adam Ford <aford173@gmail.com>
Changes in V2:
Retain Auto-detect ability between SOM-LV and Torpedo
Split this off from the device sub submissions
Previous commit has this combined with SOM-LV. This commit has only
the Torpedo Device Tree.
The device trees were sync'd with 4.9.y stable with two changes:
disable mmc2 and stdout-path = &uart1. Both of those two changes
will be submitted to the linux-omap list
Signed-off-by: Adam Ford <aford173@gmail.com>
Changes in V2:
Split device tree from other board
This adds the device tree. Previous commit added both boards at the
same time.
Signed-off-by: Adam Ford <aford173@gmail.com>
Changes in V2:
Split the SOM-LV from Torpedo
Some OMAP3 devices support an SMSC ethernet PHY connected to the GPMC bus.
This copies this device tree from Linux 4.9.y stable
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Many OMAP3 boards use a TWL4030 PMIC. This brings in the related
device tree information for common TWL4030 and TWL4030 with OMAP3.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4
(4430/60/70), OMAP5 (5430) and AM335X (3359) were added in 960187ffa125(
"ARM: OMAP: I2C: New read, write and probe functions") but not tested
on OMAP3. This patch will allow the updated drivers using device tree and
DM_I2C to operate on OMAP3.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Add device tree support to allow for CONFIG_OF_CONTROL in OMAP3630 boards.
DM3730 can use this same device tree.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Add device tree support to allow for CONFIG_OF_CONTROL in OMAP3 boards.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
This patch changes the way DM_MMC calculates offset to the base register of
MMC. Previously this was through an #ifdef but that wasn't necessary for OMAP3.
This patch will now add in the offset to the base address based on the
.compatible flags.
Signed-off-by: Adam Ford <aford173@gmail.com>
V2: Remove ifdef completely and reference offset from the omap_hsmmc_ids table.
V1: Change ifdef to ignore OMAP3
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In some boards like the Raspberry Pi the initial bootloader will pass
a DT to the kernel. When using U-Boot as such kernel, the board code in
U-Boot should be able to provide U-Boot with this, already assembled
device tree blob.
This patch introduces a new config option CONFIG_OF_BOARD to use instead
of CONFIG_OF_EMBED or CONFIG_OF_SEPARATE which will initialize the DT
from a board-specific funtion instead of bundling one with U-Boot or as
a separated file. This allows boards like the Raspberry Pi to reuse the
device tree passed from the bootcode.bin and start.elf firmware
files, including the run-time selected device tree overlays.
Signed-off-by: Alex Deymo <deymo@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Adjust the video driver to work with driver model and move over existing
baords. There is no need to keep the old code.
We can also drop setting of CONFIG_FB_ADDR since driver model doesn't have
this problem.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Adjust this function so that we can convert it to support CONFIG_DM_VIDEO
without a lot of code duplication.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Add a function to set the video parameters to the msg handler and remove
it from the video driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Add a function to get the video size to the msg handler and remove it from
the video driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
We should not use an embedded device tree on a production board. There
does not seem to be any reason for it in commit 7670909. So drop this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Convert the bcm2835 SDHCI driver over to support CONFIG_DM_MMC and move
all boards over. There is no need to keep the old code since there are no
other users.
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
The bcm283x chips provide a way for the ARM core to communicate with the
graphics processor, which is in charge of many things. This is handled by
way of a message prototcol.
At present the code for sending message (and receiving a reply) is spread
around U-Boot, primarily in the board file. This means that sending a
message from a driver requires duplicating the code.
Create a new message implementation with a function to support powering on
a subsystem as a starting point.
Signed-off-by: Simon Glass <sjg@chromium.org>
Start using driver model for USB on the Raspberry Pi. The dwc2 supports
this now so this is just a config change.
Signed-off-by: Simon Glass <sjg@chromium.org>
A common use of memmove() can be handled by memcpy(). Also memcpy()
includes an optimisation for large sizes: it copies a word at a time. So
we can get a speed-up by calling memcpy() to handle our move in this case.
Update memmove() to call memcpy() if the destination is before the source.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
On further review this returns the wrong packet length from the driver.
It may not be noticed since protocols will take care of it. Fix it by
subtracting the header length from the packet length returned.
Signed-off-by: Simon Glass <sjg@chromium.org>
Enable disk driver model for dra7xx_evm as dwc_ahci supports
driver model. As a consequence we must also enable CONFIG_BLK and
CONFIG_DM_USB.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Dropped CONFIG_SPL_PHY=y in sandbox_spl to fix build error:
Signed-off-by: Simon Glass <sjg@chromium.org>
Implement a sata driver for Synopsys DWC sata device based on
U-boot driver model.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This is needed to probe devices under that bus such as the SATA PHY.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This phy is found on omap platforms with sata capabilities.
Except for the part related to the DM and the PHY framework, the code is
basically a copy paste from arch/arm/mach-omap2/pipe3-phy.c
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Those tests check:
- the ability for a phy-user to get a phy based on its name or its index
- the ability of a phy device (provider) to manage multiple ports
- the ability to perform operations on the phy (init,deinit,on,off)
- the behavior of the uclass when optional operations are not implemented
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The PHY framework provides a set of APIs to control a PHY. This API is
derived from the linux version of the generic PHY framework.
Currently the API supports init(), deinit(), power_on, power_off() and
reset(). The framework provides a way to get a reference to a phy from the
device-tree.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The DM version of scsi_scan() is becoming a bit long, it can be split:
scsi_scan() iterates over the IDs and LUNs and for each id/lun pair calls
do_scsi_scan_one() to do the work of:
- detecting an attached drive
- creating the associated block device if a drive is found.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Because the introduction of the pinctrl and clk drivers and the
device tree files, remove unneeded hard coded related code from
the board file.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Update the configuration files to support the device tree and driver
model. The device clock and pins configuration are handled by the
clock and the pinctrl drivers respectively.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Since the introduction of the pinctrl and clk drivers and the
device tree files, remove unneeded hard coded related code from
the board file.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Update the configuration files to support the device tree and driver
model. The device clock and pins configuration are handled by the
clock and the pinctrl drivers respectively.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Since the introduction of the pinctrl and clk drivers and the
device tree files, remove unneeded hard coded related code from
the board file.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Update the configuration files to support the device tree and driver
model. The device clock and pins configuration are handled by the
clock and the pinctrl drivers respectively.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Since the introduction of the pinctrl and clk drivers and the
device tree files, remove unneeded hard coded related code from
the board file.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Update the configuration files to support the device tree and driver
model. The device clock and pins configuration are handled by the
clock and the pinctrl drivers respectively.
Because the limitation of internal SRAM size, the SPL with driver
model can't be supported, disable the SPL option.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Since the introduction of the pinctrl and clk driver and the device
tree files, remove unneeded related code from the board file.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Update the configuration files to support the device tree and driver
model. The device clock and pins configuration are handled by the
clock and the pinctrl drivers respectively.
Because the limitation of internal SRAM size, the SPL with driver
model can't be supported, disable the SPL option.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Since the introduction of the pinctrl and clock driver and the device
tree files, remove unneeded hard coded related code from the board
file.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Update the configuration files to support the device tree and driver
model. The device clock and pins configuration are handled by the
clock and the pinctrl drivers respectively.
Because the limitation of internal SRAM size, the SPL with driver
model can't be supported, disable the SPL option.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The device tree source files of at91sam9263ek boards are copied from
the Linux v4.10, do the changes as below.
- Add the reg property for the pinctrl node.
- Move the gpio (pioA, pioB, pioC, pioD, pioE) nodes as the pinctrl's
slibling nodes, instead of the child nodes.
- Add the "u-boot,dm-pre-reloc" property for the dbgu node are used
in board_init_f stage.
- Fix the compilation warnings.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The device tree source files of at91sam9rlek boards are copied from
the Linux v4.10, do the changes as below.
- Add the reg property for the pinctrl node.
- Move the gpio (pioA, pioB, pioC, pioD) nodes as the pinctrl's
slibling nodes, instead of the child nodes.
- Add the "u-boot,dm-pre-reloc" property for the dbgu node are used
in board_init_f stage.
- Fix the compilation warnings.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The device tree source files of at91sam9g20ek and at91sam9260ek
boards are copied from the Linux v4.10, do the changes below.
- Fix the build error for the usb0 node.
- Add the reg property for the pinctrl node.
- Move the gpio (pioA, pioB, pioC ...) nodes as the pinctrl's
slibling nodes, instead of the child nodes.
- Add the "u-boot,dm-pre-reloc" property for the dbgu node are used
in board_init_f stage.
- Add the clk pinctrl of the mmc0 node.
- Fix the compilation warnings.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The device tree source files of at91sam9m10g45ek boards are copied
from the Linux v4.10, do the changes as below.
- Add the reg property for the pinctrl node.
- Move the gpio (pioA, pioB, pioC, pioD, pioE) nodes as the pinctrl's
slibling nodes, instead of the child nodes.
- Add the "u-boot,dm-pre-reloc" property to determine which nodes
are used by the board_init_f stage.
- Fix the compilation warnings.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The device tree source files of at91sam9n12ek boards are copied from
the Linux v4.10, do the changes as below.
- Add the reg property for the pinctrl node.
- Move the gpio (pioA, pioB, pioC, pioD) nodes as the pinctrl's
slibling nodes, instead of the child nodes.
- Change the compatible of the spi flash to "spi-flash".
- Add the spi0 aliases.
- Fix the pinctrl-names of mmc0 node.
- Add the "u-boot,dm-pre-reloc" property to determine which nodes
are used by the board_init_f stage.
- Fix the compilation warnings.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The device tree source files of at91sam9x5ek board are copied from
the Linux v4.10, do the changes below.
- Add the reg property for the pinctrl node.
- Move the gpio (pioA, pioB, pioC ...) nodes as the pinctrl's
slibling nodes, instead of the child nodes.
- Add the "u-boot,dm-pre-reloc" property to determine which nodes
are used by the board_init_f stage.
- Change the compatible of the spi flash to "spi-flash".
- Add the spi0 aliases.
- Fix the compilation warnings.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add the clock support.
Note that the clock handling of the DBGU peripheral is different
from the USART.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add the uart init function to be used on both probe and the early
debug uart init. For the latter, the input clock should be from
CONFIG_DEBUG_UART_CLOCK.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add the compatible "atmel,at91rm9200-clk-master" to align with
the kernel.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Enhance the peripheral clock to support both at9sam9x5's and
at91rm9200's peripheral clock via the different compatibles.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
To avoid the failure of mdio_register(), add the remove callback
to unregister the mii_dev when removing the ethernet device.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Fixed up unused variable warning, e.g. for gurnard:
Signed-off-by: Simon Glass <sjg@chromium.org>
The sama5d36ek CMP board is the variant of sama5d3xek board.
It is equipped with the low-power DDR2 SDRAM, PMIC ACT8865, and
some power rails. The board is mainly used to measure the power
consumption. As all those changes are done in at91bootstrap,
in U-Boot, only use another device tree file, no code needed
to change.
As there is additional power consumption when enbling the USB
Host and USB device, for the power consumption measurement
intention, disable the USB host and device.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Enable config options to support the SPL, increase the malloc
memory size for the SPL and board_init_f stage and increase
the memory space for the SPL binary.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Due to the pin configuration and clock enabling is handling by the
driver, remove the unneeded hardcode uart1 init during
board_early_init_f stage.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Because the MACB driver supports the driver model and device tree,
the pins configuration and clock enabling are handled by the
pinctrl driver and clock driver, remove this hardcoded init code.
The USB Ether init code is removed as well.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Enable CONFIG_DM_ETH to make MACB to support driver model.
Because the USB Ether doesn't support driver model so far,
remove this feature.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Add the "u-boot,dm-pre-reloc" property to determine which nodes
which are needed by SPL and by the board_init_f stage.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
- Remove "probe" function from sandbox wdt driver
- Fix include order
Fixes: 0753bc2d30 ("dm: Simple Watchdog uclass")
Signed-off-by: Maxim Sloyko <maxims@google.com>
[trini: Create as the delta between v1 (applied) and v2 (should have
applied)].
Signed-off-by: Tom Rini <trini@konsulko.com>
Move existing configuration from header file to defconfig or dts as
appropriate.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Add PCIE analog parameters initialization values according to
latest ETP.
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
No functional change.
The variable name "comphy_index" is misleading, it represents
cp index and not comphy index.
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Add SFI analog parameters initialization values according to
latest ETP.
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
since now the COMPHY can also be ignored, we must know the
state of the COMPHY. we cannot assume anymore that a missing
COMPHY is unconnected.
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
The comphy configuration is incorrect.
Set the correct values for SGMII.
In addition, remove xaui from the comment as it is not supported.
Signed-off-by: Yoav Gvili <ygvili@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This patch adds the option to configure a comphy to 5G XFI mode.
In order to configure the comphy to 5G XFI, update
the comphy node in the device-tree:
phy2 {
phy-type = <PHY_TYPE_SFI>;
phy-speed = <PHY_SPEED_5_15625G>;
};
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Align PHY selectors register with Armada-CP-110 functional SPEC
update all relevant device trees with this change.
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Add SATA analog parameters initialization values according to
latest ETP.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This patch fixes the following:
1. KR/SFI on lane #4 mux selector is 0x2 and not 0x1
2. Comment typo
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This type tells u-boot to preserve the COMPHY settings as is
it is usefull in situations where the COMPHY was initialized by
earlier firmware.
Note that IGNORE is different from UNCONNECTED since setting
UNCONNECTED type will disconnect the COMPHY in the COMPHY MUX
which is a desired behaviour
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
UTMI_PHY_TO_USB_HOST was used in USB3 UTMI dts node only, but there will
be USB2 UTMI dts node for some SoCs that have got USB2 controller, so rename
TO_USB_HOST to TO_USB3_HOST to distinguish TO_USB2_HOST in later on patches.
Signed-off-by: zachary <zhangzg@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
The serdes was always configured in root complex mode.
this patch add new entry in device tree (per serdes)
which indicates whether the serdes is in end point mode.
if so, it skips the root complex configuration.
Signed-off-by: Haim Boot <hayim@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Use correct naming as done in the latest Marvell U-Boot version as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Use local static counter for maintaining the COMPHY chip-ID
upon its initialization.
The dev->seq originally used as the COMPHY chip-ID depends
on the device tree scan order and produces wrong results
that breaks the deficated PHYs init flow, which in turn
breaks the USB support.
Change-Id: I4e3f7ec36590a7f95dc94d9269a3c47fb708c4a9
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
- Fix spelling error of SERDES_VERSION
- Remove superfluous definition of this macro
- Remove unnecessary include of i2c.h
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Add NAND configuration parameters to A8K shared config file.
Add defconfig for db-88f7040 board with boot from NAND setup.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Add NAND to CP master device tree. Add armada-7040-db-nand
device tree for the board configured with NAND boot device.
Add comment about boot device ID to armada-7040-db DTS.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Implement mvebu_get_nand_clock call for A8K family.
This function is used by PXA3XX NAND driver.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Add PCIe initialization at early init stage.
This operation has a side effect of detecting all PCIe
plug-in cards, so the operator is not obligated to issue
"pci enum" command though CLI for this purpose.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Sync the default configuration of Armada-8040-DB with
Marvell u-boot-2015 standard configuration "A" for the same board.
The standard configuration "A" enables 2 PCIe slots on CP0
and 3 PCIe slots on CP1.
This is the main configuration used for u-boot and Linux tests.
This patch also re-arranges the DTS file entries by grouping
all nodes related to CP0 and CP1.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This patch allows probing all PCIe nodes defined in DTS
even if there no device connected to such node (no link).
Without this fix the driver returns -ENODEV when the PCIe
link is down. As result the pci_init function stops
scanning bus on first empty PCIe slot and all devices
located in higher numbered buses are not discovered.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This patch adds a remove function to the mvpp2 ethernet driver which is
called before the OS is started, doing:
- Allocate the used buffers back from the buffer manager
- Stop the BM activity
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Enable by default DM_I2C for all Texas Instruments Keystone 2 based
evms.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Enable I2C0 and I2C1 which is needed to enable usage of DM I2C.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Add aliases for I2C nodes required for the DM framework to probe the
davinci-i2c driver.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Add I2C nodes to the 66AK2Gx dtsi.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
In non DM I2C read operations the address length passed in during a read
operation will be used automatically. However, in DM I2C the address length
is set to a default value of one which causes problems when trying to
perform a read with a differing alen. Therefore, before the first read in a
series of read operations set the alen to the correct value.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reading from the I2C EEPROM used typically requires using an address length
of 2. However, when using DM for I2C the default address length used is 1.
To fix this introduce a new function that allows the address length to be
changed. The logic to do so was copied from cmd/i2c.c.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Convert davinci i2c driver to driver model.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
The i2c driver will be converted to support device model. In preparation
for that change split the various functions into two parts. This will
allow device model specific driver to reuse the majority of the code from
the non device model implementation.
Also rename the probe function to probe_chip to better reflect its
purpose.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
One some keystone2 platforms like K2G ICE, there is an option
to switch between 24MHz or 25MHz as sysclk. But the existing
driver assumes it is always 24MHz. Add support for getting
all reference clocks dynamically by reading boot pins.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
K2G supports various sysclk frequencies which can be
determined using sysboot pins. PLLs should be configured
based on this sysclock frequency. Add PLL configurations
for all supported sysclk frequencies.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Enable TI_COMMON_CMD_OPTIONS on all am335x platforms.
Also sync with savedefconfig.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[trini: Re-sync, add in boneblack*, evm_hs_{norboot,spiboot,usbspl} configs]
Signed-off-by: Tom Rini <trini@konsulko.com>
Instead of defining command options in every defconfig,
define a common Kconfig symbol that consolidates all command
options that are supported by any TI platform. Also use imply
keyword so that that specific option can be disabled if
not required.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
ARM errata 852421 and 852423 applies to r1p0, r1p1 and r1p2
revisions of Cortex-A17 processors. These workarounds
exist in Linux kernel and I thought it would be better
to add them in to U-Boot.
Signed-off-by: Nisal Menuka <nisalmenuka23@gmail.com>
Remove unnecessary apb and ahb nodes and just override necessary
nodes/values.
Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Refactor SCU header to use consistent Mask & Shift values.
Now, consistently, to read value from SCU register, mask needs
to be applied before shift.
Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add support for clocks needed by MACs to ast2500 clock driver.
The clocks are D2-PLL, which is used by both MACs and PCLK_MAC1 and
PCLK_MAC2 for MAC1 and MAC2 respectively.
The rate of D2-PLL is hardcoded to 250MHz -- the value used in Aspeed
SDK. It is not entirely clear from the datasheet how this clock is used
by MACs, so not clear if the rate would ever need to be different. So,
for now, hardcoding it is probably safer.
The rate of PCLK_MAC{1,2} is chosen based on MAC speed selected through
hardware strapping.
So, the network driver would only need to enable these clocks, no need
to configure the rate.
Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add Device Model based I2C driver for ast2500/ast2400 SoCs.
The driver is very limited, it only supports master mode and
synchronous byte-by-byte reads/writes, no DMA or Pool Buffers.
Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Add P-Bus Clock support to ast2500 clock driver.
This is the clock used by I2C devices.
Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This driver uses Generic Pinctrl framework and is compatible with
the Linux driver for ast2500: it uses the same device tree
configuration.
Not all pins are supported by the driver at the moment, so it actually
compatible with ast2400. In general, however, there are differences that
in the future would be easier to maintain separately.
Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This change switches all existing users of ast2500 Watchdog to Driver
Model based Watchdog driver.
To perform system reset Sysreset Driver uses first Watchdog device found
via uclass_first_device call. Since the system is going to be reset
anyway it does not make much difference which watchdog is used.
Instead of using Watchdog to reset itself, SDRAM driver now uses Reset
driver to do that.
These were the only users of the old Watchdog API, so that API is
removed.
This all is done in one change to avoid having to maintain dual API for
watchdog in between.
Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add Reset Driver configuration to ast2500 SoC Device Tree and bindings
for various reset signals
Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add Reset Driver for ast2500 SoC. This driver uses Watchdog Timer to
perform resets and thus depends on it. The actual Watchdog device used
needs to be configured in Device Tree using "aspeed,wdt" property, which
must be WDT phandle, for example:
rst: reset-controller {
compatible = "aspeed,ast2500-reset";
aspeed,wdt = <&wdt1>;
}
Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Make functions for locking and unlocking SCU part of SCU API.
Many drivers need to modify settings in SCU and thus need to unlock it
first. This change makes it possible.
Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This driver supports ast2500 and ast2400 SoCs.
Only ast2500 supports reset_mask and thus the option of resettting
individual peripherals using WDT.
Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This is a simple uclass for Watchdog Timers. It has four operations:
start, restart, reset, stop. Drivers must implement start, restart and
stop operations, while implementing reset is optional: It's default
implementation expires watchdog timer in one clock tick.
Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch is required for correct SPL device tree creation by fdtgrep
as fdtgrep looks for u-boot,dm-pre-reloc property of the node to include
it in the spl device tree.
Not adding it in these subnodes ignores the pin muxing of peripherals
which is almost always in the subnodes.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
CONFIG_CMD_DATE was recently moved to Kconfig. Remove the now duplicate
description of the option.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The Kconfig description replaces the description in the README file so
as options are migrated they can be removed from the README.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
After moving to KConfig and removing from all headers options should be
removed from config_whitelist.txt so the build starts complaining if
someone adds them back.
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Avoid repetitive code dealing with asking the user for confirmation.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add an implementation of the ds1307 driver that uses the driver model
i2c APIs.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The IGEP SMARC AM335x is an industrial processor module with
following highlights:
o AM3352 TI processor (Up to AM3359)
o Cortex-A8 ARM CPU
o SMARC form factor module
o Up to 512 MB DDR3 SDRAM / 512 MB FLASH
o WiFi a/b/g/n and Bluetooth v4.0 on-board
o Ethernet 10/100/1000 Mbps and 10/100 Mbps controller on-board
o JTAG debug connector available
o Designed for industrial range purposes
Signed-off-by: Pau Pajuelo <ppajuelo@iseebcn.com>
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tested-by: Pau Pajuelo <ppajuel@gmail.com>
Convert IGEP board to use UBI volumes for U-Boot, its environment and
kernel. With exception of first four sectors read by SoC BootROM whole
NAND is UBI managed.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Heiko Schocher<hs@denx.de>
Tested-by: Pau Pajuelo <ppajuel@gmail.com>
Rename igep0033 to igep003x as IGEP SMARC AM335x module (igep0034)
can use the same source files.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tested-by: Pau Pajuelo <ppajuel@gmail.com>
nand_spl_load_image implementation was copied over into three
different drivers and now with nand_spl_read_block used for
ubispl situation gets even worse. For now use least intrusive
solution and #include the same implementation to nand drivers.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tested-by: Pau Pajuelo <ppajuel@gmail.com>
am33xx does not support OneNAND, but we need this define anyway
to let UBI SPL code compile.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tested-by: Pau Pajuelo <ppajuel@gmail.com>
This patch removes:
- CONFIG_CMD_MEM: enabled by default
- CONFIG_DESIGNWARE_ETH : not being used anywhere.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
This board support stm32f7 family device stm32f769-I with 2MB internal Flash &
512KB RAM.
STM32F769 lines offer the performance of the Cortex-M7 core (with double
precision floating point unit) running up to 216 MHz.
To compile for stm32f769 board, use same defconfig as stm32f746-disco,
the only difference is to pass "DEVICE_TREE=stm32f769-disco".
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
The number of pins to be configured could be more than 50 e.g. in case
of sdram controller, there are about 56 pins (32 data lines, 12 address
& some control signals).
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
Actually the sdram memory on stm32f746 discovery board is micron part
MT48LC_4M32_B2B5_6A. This patch does the modification required in the
device tree node & driver for the same.
Also we are passing here all the timing parameters in terms of clock
cycles, so no need to convert time(ns or ms) to cycles.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
All discovery boards have one user button & one user LED. Here we are
just reading the button status & switching ON the user LED.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
With this gpio driver supporting DM, there is no need to enable clocks
for different gpios (for pin muxing) in the board specific code.
Need to increase the allocatable area required before relocation from 0x400 to
0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Also created alias for gpios for stm32f7 discovery board. Based on these
aliases, it would be possible to get gpio devices by sequence.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
As driver model takes care of pin control configuraion, this patch also
removes the sdram/fmc pin configuration.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
At present fdt blob or argument address being passed to kernel is fixed at
compile time using macro CONFIG_SYS_SPL_ARGS_ADDR. FDT blob from
different media like nand, nor flash are copied to the address pointed
by the macro.
The problem is, it makes args/fdt blob compulsory to copy which is not required
in cases like for NOR Flash. This patch removes this limitation.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Invoke enable_usb_clocks during board_usb_init and disable_usb_clocks
during board_usb_exit to enable and disable clocks respectively.
Modifications:
* Enable USB clocks in the OMAP version of the function
board_usb_init.
* Disable USB clocks in the OMAP version of the function
board_usb_cleanup.
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
A weak version of the function board_usb_init is implemented in:
common/usb.c
drivers/usb/host/xhci-omap.c
To fix the double implementations:
* Convert the board_usb_init function in drivers/usb/host/xhci-omap.c
normal (not weak).
* The function board_usb_init in drivers/usb/host/xhci-omap.c calls to
the weak function omap_xhci_board_usb_init.
* Rename board version of the function board_usb_init to
omap_xhci_board_usb_init.
Done only for boards that defines CONFIG_USB_XHCI_OMAP.
To achieve the same flexibility with the function board_usb_cleanup:
* Add a normal (not weak) implementation of the function
board_usb_cleanup in drivers/usb/host/xhci-omap.c
* The function board_usb_cleanup in drivers/usb/host/xhci-omap.c calls
to the weak function omap_xhci_board_usb_cleanup.
* Rename board version of the function board_usb_cleanup to
omap_xhci_board_usb_cleanup.
Done only for boards that defines CONFIG_USB_XHCI_OMAP.
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Roger Quadros <rogerq@ti.com>
The logical expression to check the dtb is incorrect in
load_devicetree.
The problem was indicated by cppcheck.
The inconsistent variable name dtppart is changed to dtbpart.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Acked-by: Hannes Schmelzer <oe5hpm@oevsv.at>
The evaluation of option -c is incorrect:
According to the C99 standard endptr in the first strtol is always
set as &endptr is not NULL.
So the first part of the or condition is always true.
If all digits in optarg are valid endptr will point to the closing \0
and the second strtol will read beyond the end of the string optarg
points to.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
We should not first dereference p and afterwards assert that is
was not NULL. Instead do the assert first.
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
In dram_init_banksize there seems to be a typo concerning
a plausibility check of the fdt.
Testing sc > 2 twice does not make any sense.
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
A feature rich Linux kernel needs more than 8 MiB.
Hence enlarge CONFIG_SYS_BOOTM_LEN to 64 MiB for the GXBB systems.
As all known GXBB systems have at least 512 MiB of RAM this poses no problem.
Cc: Andreas Färber <afaerber@suse.de>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Banana Pi M2 Plus is an Allwinner H3-based SBC by Sinovoip, which has
already mainline device tree file that have landed into U-Boot source
tree.
Add a defconfig file for it and add the MAINTAINERS items.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
.probe method has been assigned twice when declaring
a driver with U_BOOT_DRIVER(). Removed one of them.
Here is the last commit which had the duplicate entry:
"spi: omap3: Convert to driver model"
(sha1: 77b8d04854)
Signed-off-by: Suniel Mahesh <suniel.spartan@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
setup_flash_device selects one of two code paths depending on the driver
model being used (=CONFIG_DM_SPI_FLASH). env_relocate_spec only used
the non driver-model code path. I'm unsure why, either none of the
platforms that need relocation use the driver model, or - worse - the
driver model is not yet usable when relocating.
Signed-off-by: Andreas Fenkart <afenkart@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@openedev.com>
This is not currently implemented. Add support for this so that the
Chrome OS EC can be used reliably.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Before using the cs_gpio, check if the GPIO is valid or not.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Banana Pi M2 Ultra has a SATA port connected to the internal SATA
controller of R40 SoC. The controller's 1.2v VDD is connected to ELDO3
and the 2.5v VDD is connected to DLDO4.
Enable these regulators as well as the SATA support of Banana Pi M2
Ultra, by adding needed config lines into its defconfig.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
R40 has a similar SATA controller with the ones on A10/A20, but with a
reset line added (like other peripherals on sun6i+), and two extra VDD
pins added (1.2v and 2.5v).
Add clock configuration of R40 SATA.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Mention eMMC and microSD as supported devices.
They have been enabled with patch
d0c5c8d529
odroid-c2: enable new Meson GX MMC driver in board defconfig
which was accepted for u-boot-mmc.git.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
To enable automatic booting from SD card or eMMC the MMC
devices 0, 1, and 2 are added to the BOOT_TARGET_DEVICES.
Booting from SD card, eMMC, and DHCP are tried in sequence.
A missing or failing device is gracefully handled.
Cc: Andreas Färber <afaerber@suse.de>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Tested-by: Andreas Färber <afaerber@suse.de>
Add warp7_secure_defconfig entry to avoid the following warning:
WARNING: no maintainers for 'warp7_secure'
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
With 3f66149d9f we no longer have a common call fdt_fixup_ethernet.
This was fine to do on PowerPC as they largely had calls already in
ft_cpu_fixup. On ARM however we largely relied on this call. Rather
than introduce a large number of changes to ft_cpu_fixup /
ft_board_fixup we recognize that this is a common enough call that we
should be doing it in a central location. Do it early enough that we
can do any further updates in ft_cpu_fixup / ft_board_fixup.
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Thomas Chou <thomas@wytron.com.tw> (maintainer:NIOS)
Cc: York Sun <york.sun@nxp.com> (maintainer:POWERPC MPC85XX)
Cc: Stefan Roese <sr@denx.de> (maintainer:POWERPC PPC4XX)
Cc: Simon Glass <sjg@chromium.org>
Cc: Joakim Tjernlund <Joakim.Tjernlund@infinera.com>
Fixes: 3f66149d9f ("Remove extra fdt_fixup_ethernet() call")
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This converts the following to Kconfig:
CONFIG_CMD_DIAG
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: imply CMD_DIAG on some keymile configs]
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_CMD_DEKBLOB
Note: This option does not seem to actually be enabled by any board.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: imply under SECURE_BOOT for mx5/6/7]
Signed-off-by: Tom Rini <trini@konsulko.com>
Rather than using CMD_CRAMFS for both the filesystem and its command, we
should have a separate option for each. This allows us to enable CRAMFS
support without the command, if desired, which reduces U-Boot's size
slightly.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: imply FS_CRAMFS for keymile]
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_CMD_CRAMFS
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: imply CMD_CRAMFS for keymile]
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_CMD_CLK
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: imply CMD_CLK on ARCH_ZYNQ]
Signed-off-by: Tom Rini <trini@konsulko.com>
Rather than using CMD_CBFS for both the filesystem and its command, we
should have a separate option for each. This allows us to enable CBFS
support without the command, if desired, which reduces U-Boot's size
slightly.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: imply FS_CBFS on SYS_COREBOOT]
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_CMD_CBFS
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: imply CMD_CBFS on SYS_COREBOOT]
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_SYS_WHITE_ON_BLACK
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Make this default y on various SoCs]
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_CMD_BMP
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Add depends on LCD || DM_VIDEO || VIDEO]
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_CMD_BMODE
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Make this default y and depend on mx5/6/7]
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_CMD_BLOB
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Add imply CMD_BLOB under CHAIN_OF_TRUST]
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_CMD_AES
CONFIG_AES
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Add select AES to CMD_AES]
Signed-off-by: Tom Rini <trini@konsulko.com>
This is only used by one board and should not be a CONFIG option. Instead
it should use the driver model pmic framework. For now, just move the
setting into the only board that uses it.
Signed-off-by: Simon Glass <sjg@chromium.org>
A few boards had not been fully re-synced with CONFIG_ARCH_MX5 / CONFIG_MX51 /
CONFIG_MX53 being in Kconfig. Do so now.
Signed-off-by: Tom Rini <trini@konsulko.com>
This commits enable DM I2C support for A64/H3/H5 SoCs.
It is not enabled globaly for all sunxi SoCs, because some boards use
PMICs which are connected through I2C. In order to keep same
functionality, PMIC drivers needs to be ported to DM too.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit adds support for DM I2C on sunxi platform. It can coexist
with old style sunxi I2C driver, because it is still used in SPL and
by some SoCs.
Because sunxi platform doesn't yet support DM clk, reset and pinctrl
driver, workaround is needed to enable clocks and set resets and
pinctrls. This is done by calling i2c_init_board() in board_init().
This means that CONFIG_I2Cx_ENABLE options needs to be correctly set
in order to use needed I2C controller.
Commit is based on the previous patch made by Philipp Tomsich
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit only moves i2c_init_board() function almost to the top and
doesn't have any functional changes.
This is needed for a temporary workaround in next commit when support
for DM I2C will be introduced.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Driver for that regulator is used only in SPL and it uses old I2C
interface. If we want to use DM I2C in U-Boot proper, compilation of
this driver has to be limited only to SPL.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
In file ext4fs.c funtion ext4fs_read_file() compares an
unsigned expression with < 0 like below
lbaint_t blknr;
blknr = read_allocated_block(&(node->inode), i);
if (blknr < 0)
return -1;
blknr is of type ulong/uint64_t. read_allocated_block() returns
long int. So comparing blknr with < 0 will always be false. Instead
declare blknr as long int.
Similarly ext4/dev.c does a similar comparison. Drop the redundant
comparison.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Update Keystone2 secure device configs under
"TI SYSTEM SECURITY". Without this buildman keeps complaining
about the status of these boards.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Andrew F. Davis <afd@ti.com>
On ARM v7M, the processor will return to ARM mode when executing
a blx instruction with bit 0 of the address == 0. Always set it
to 1 to stay in thumb mode.
Tested on STM32f746-disco board
Similar commit:
f99993c108
Author: Matt Porter <mporter@konsulko.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
In Linux, CONFIG_ARCH_OMAP2PLUS is used for OMAP2 or later SoCs.
Rename CONFIG_ARCH_OMAP2 to CONFIG_ARCH_OMAP2PLUS to follow this
naming.
Move the OMAP2+ board/SoC choice down to mach-omap2/Kconfig to slim
down the arch/arm/Kconfig level.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
CONFIG_CMD_FS_UUID was neither whitelisted, nor was it declared in
Kconfig.
Now it can be enabled in .config and defconfig as expected.
Signed-off-by: Josua Mayer <josua.mayer97@gmail.com>
Almost all TI defconfigs enable this already, add this as a default
and remove the explicit assignment.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Finally adding support for ARC boards in TravisCI.
To build for ARC boards we need to install Synopsys prebuilt toolchain
which we do here.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
As per the DM[1] Dated June 2016–Revised February 2017, Table 5-3,
DRA71 supports the following OPPs for various voltage domains:
VDD_MPU: OPP_NOM
VDD_CORE: OPP_NOM
VDD_GPU: OPP_NOM
VDD_DSPEVE: OPP_NOM, OPP_HIGH
VDD_IVA: OPP_NOM, OPP_HIGH
This patch add support for selection of the above OPPs instead of
using OPP_NOM for all voltage domains.
[1] http://www.ti.com/lit/ds/symlink/dra718.pdf
Reported-by: Vishal Mahaveer <vishalm@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This originally started out as
"pinctrl: Kconfig: reorder to keep Rockchip options together"
and tried to keep the Rockchip-related config options together.
However, we now rewrite all chip-specific driver selections to start
with CONFIG_PINCTRL_ (with the inadvertent changes to related
Makefiles) and sort those alphabetically. And as this already means
touching most of the file, we also reformat the help text to not exceed
80 characters (but make full use of those 80 characters).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
An assignment (of a value to itself) was left over (after removing and
addition from the line) from moving the common padding code into
rkcommon_vrec_header.
This change removes this to avoid a spurious warning in static code
analysis (i.e. Coverity).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reported-by: Coverity (CID: 161418)
Reviewed-by: Tom Rini <trini@konsulko.com>
There are more and more cases where if we do not use gcc-6.0 or later we
run into problems where our binaries are too large for the targets.
Given the prevalence of gcc-6.0 or later toolchains at this point in
time, we give notice now that starting with v2018.01 we will require
gcc-6 (or later) for ARM.
Signed-off-by: Tom Rini <trini@konsulko.com>
Unfortunately a test for the PWM uclass was not included when it was
submitted. This was noticed when trying to add more functionality:
http://patchwork.ozlabs.org/patch/748172/
Add a simple test to get us started.
Signed-off-by: Simon Glass <sjg@chromium.org>
Standardise U-Boot prompt on all keystone2 platforms
instead of platform specific prompt.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The name of the gpio bank under DM_GPIO appear to be a copy-paste error.
This changes the name of the gpio bank from am33xx_gpios to omap34xx_gpios.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The register names and offset were not correct as per the TRM for OMAP3530
and OMAP3630. Correct the naing and offsets per the documentation
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Remove option which depends on MMC controller which is disabled for dc2.
Savedefconfig is removing it because of new dependencies.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Fixes the following problem:
zynq-uboot> run dfu_ram
Setting bus to 1
g_dnl_register: failed!, error: -19
The cause appears to be that the USB framework is looking for a usbotg aliases,
so add the alias to point to our USB device.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
We used to have opencoded ehci_readl()/writel() which required no
external functions to be called.
Now with attempt to switch to generic readl()/writel() accessors
we see a missing declaration of those accessors in ehci-ppc4xx.
Something like that happens if applied
http://patchwork.ozlabs.org/patch/726714/:
---------------->8---------------
CC drivers/usb/host/ehci-ppc4xx.o
drivers/usb/host/ehci-ppc4xx.c: In function 'ehci_hcd_init':
drivers/usb/host/ehci-ppc4xx.c:23:3: warning: implicit declaration of function 'readl' [-Wimplicit-function-declaration]
HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
^
---------------->8---------------
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
For id = 15 an out of bound access occurs in udc_setup_ep().
Increase the size of epinfo[] from 30 to 32 to encompass
ids 0..15.
The problem was highlighted by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
We want to check the result of musb_init_controller
and not the address were the result is stored.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Add support for the Terasic DE10-Nano board. The board
is based on the DE0-Nano-Soc board but adds a larger FPGA
and an HDMI output.
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Only A23/A33 in SUN8I want a default value of CONS_INDEX of 5, for other
chips the default value is 1 like other Allwinner SoCs.
Fix this default value.
The original wrong value has lead to wrong console on H3 Orange Pi
boards.
Fixes: 7095f86418 ("sunxi: Convert CONS_INDEX to Kconfig")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Commit 088454cd dropped return value from initram(), setting
gd->ram_size directly. Three boards were missed for SPL boot.
Signed-off-by: York Sun <york.sun@nxp.com>
PSCI can be used on both multiple and single core socs. Current
implementation only allows PSCI to work on multiple core socs.
This patch removes this restriction so that PSCI can work on
single core socs as well.
Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The PPA is a EL3 firmware, which support PSCI, hotplug,
power-management features etc.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The PPA is a EL3 firmware, which support PSCI, hotplug,
power-management features etc.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Since commit ce412b7, RGMII TX clock internal delay is not enabled
for AR8033 unconditionally. On LS1021ATWR board, the third port
eTSEC3 uses AR8033 in RGMII mode. The TX/RX internal delay needs to
be enabled.
This patch will set PHY_INTERFACE_MODE_RGMII_ID to enable RGMII TX/RX
clock internal delay for AR8033 on the third port.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Currently $fdtfile is constructed from CONFIG_DEFAULT_TREE, containing
the filename. However on arm64 that file is located in an allwinner
subdirectory.
To avoid the need for users/distros symlinking the .dtb files, prepend
the vendor directory for ARM64.
This aligns Pine64 with other boards such as Raspberry Pi 3.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Before this patch, CONFIG_SYS_BOOTPARAMS_LEN was the same size as
CONFIG_SYS_MALLOC_LEN. So, if malloc() had previously been called, and
initr_malloc_bootparams() was called, it would fail with an out-of-
memory error. This patch fixes this issue by expanding the malloc pool
to 256KB.
Signed-off-by: Kyle Edwards <kyleedwardsny@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This fixes an issue with the saveenv command causing U-Boot to no
longer work on the QEMU Mips pseudoboard. Because the offset of the
environment was being determined by CONFIG_SYS_MONITOR_LEN, and this
value was less than the actual size of U-Boot, saveenv was overwriting
parts of the U-Boot code. Because CONFIG_SYS_MONITOR_LEN is no longer
used on MIPS, this patch removes it and places the environment at the
end of the pseudoboard's 4MB flash.
Signed-off-by: Kyle Edwards <kyleedwardsny@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Lichee Pi Zero is a development board with a V3s SoC, which features
64MiB DRAM co-packaged within the SoC, a TF slot, a SPI NOR slot (not
soldered in production batch), a 40-pin RGB LCD connector and some extra
pins available as 2.54mm pins or stamp holes.
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Basic U-Boot support is now present for V3s.
Some memory addresses are changed specially for V3s, as the original
address map cannot fit into a so small DRAM.
As the DRAM controller code needs a big refactor, the SPL support is
disabled in this version.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
- Use - instead of @ for OPP tables
- Add input-delay properties to Cadence eMMC nodes
- Restore full license text because code-diff is annoying
- Fix NAND compatible strings
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The SCP (System Control Processor) or what we call STM (Stand-by
MPU) is integrated in LD4, Pro4, sLD8, LD6b, LD11, and LD20.
For these SoCs, show the information if STM is enabled.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This configuration is supposed to be used with ARM Trusted Firmware,
so the SYSTEM_RESET is implemented in BL31. Invoke PSCI instead of
U-Boot's own reset code because we need to coordinate with SCP
(System Control Processor) for the system-level power management.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Video driver for older Allwinner SoCs uses cfb console framework which
in turn uses struct ctfb_res_modes to hold timing informations. However,
DM video framework uses different structure - struct display_timing.
It makes more sense to convert lcdc to use new timing structure because
all new drivers should use DM video framework and older drivers might be
rewritten to use new framework too.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The Bananapi M2 Ultra is the first publicly available development board
featuring the R40 SoC.
This patch add barebone dtsi/dts files for the R40 and Bananapi M2 Ultra,
as well as a defconfig for it.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The R40's CPU controls are a combination of sun6i and sun7i.
All controls are in the CPUCFG block, and it seems the R40 does not
have a PRCM block. The core reset, power gating and clamp controls
are grouped like sun6i.
Last, the R40 does not have a secure SRAM block.
This patch adds a PSCI implementation for CPU bring-up and hotplug
for the R40.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Now that we can do DRAM initialization for the R40, we can enable
SPL support for it.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The R40 seems to have a variant of the memory controller found in
the H3 and A64 SoCs. Adapt the code for use on the R40. The changes
are based on released DRAM code and comparing register dumps from
boot0.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The PIO on the R40 SoC is mostly compatible with the A20.
Only a few pin functions for mmc2 were added to the PC
pingroup, to support 8 bit eMMCs.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
These values were taken from the Banana Pi M2 Ultra fex file
found in the released vendor BSP. This is the only publicly
available R40 device at the time of this writing.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
According to the BSP released by Banana Pi, the R40 (sun8iw11p1) has
an extra "PLL lock control" register in the CCU, which controls whether
the individual PLL lock status bits in each PLL's control register work
or not.
This patch enables it for all the PLLs.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The PIO is generally compatible with the A20, except that it routes the
full 8 bits and eMMC reset pins for mmc2.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The watchdog found on the R40 SoC is the older variant found on the A20.
Add the proper "#if defines" to make it work.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The R40 SoC uses the AXP221s in I2C mode to supply power.
Some regulator's common usages have changed, and also the recommended
voltage for existing usages have changed. Update the defaults to match.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The R40 is the successor to the A20. It is a hybrid of the A20, A33
and the H3.
The R40's PIO controller is compatible with the A20,
Reuse the A20 UART and I2C muxing code by adding the R40's macro.
The display pipeline is the newer DE 2.0 variant.
Block enabling video on R40 for now.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Currently we have some lines in board/sunxi/Kconfig that are very long.
These line either provide default values for a set of SoCs, or limit
some option to a subset of sunxi SoCs.
Fortunately Kconfig makes it easy to split them. The Kconfig language
document states
If multiple dependencies are defined, they are connected with '&&'.
This means we can split existing dependencies at "&&" symbols. This
applies to both the "depends on" lines and "if" expressions.
This patch splits them up to one symbol per line. This will make it
easier to add, remove, or modify one item at a time.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Convert the CONS_INDEX configuration to Kconfig.
Update sunxi's defconfigs to remove SYS_EXTRA_OPTIONS variable not
needed anymore.
Default value is 1 except for sun5i (equals 2) and sun8i (equals 5).
Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
[Maxime: Added a depends on ARCH_SUNXI to avoid build breakages]
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Convert CONFIG_RGMII to Kconfig. Thanks to that, it is possible to
update defconfig files of SYS_EXTRA_OPTIONS accordingly and
remove it when it is possible.
Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Convert the SUNXI_EMAC config to Kconfig. Remove it from SYS_EXTRA_OPTIONS
from many sunxi defconfig and renamed it into SUN4I_EMAC to not confuse it
with SUN8I_EMAC.
Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The USB_EHCI configuration is already set in this defconfig
using kconfig's config. This configuration in SYS_EXTRA_OPTIONS
must be removed and so the SYS_EXTRA_OPTIONS.
Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Remove the AXP209_POWER option from SYS_EXTRA_OPTIONS.
As this configuration already exists on Kconfig, we just need
to remove it from defconfig.
Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
At present if the return to bootrom fails (e.g. because you are not using
the Rockchip's bootrom's pointer table in MMC) then the board prints
SPL message and hangs. Print a message first if we can, to help in
understanding what happened when it hangs.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Heiko Stuebner <heiko@sntech.de>
'A || (!A && B)' is equivalent to 'A || B'.
Let's reduce the complexity of the statement in start_jr0().
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
After allocating sata->cmd_hdr_tbl_offset we have to check
this variable and not variable sata.
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
(pdimm[0].data_width >= 32) || (pdimm[0].data_width <= 40)
is always true.
We should use && here.
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The number of arguments for printf does not match the
format string.
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
If current_urb is NULL it should not be dereferenced.
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
If !parent, the changed line is not reached.
So there is no need to check the value again.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Each call of va_start must be matched by a call of va_end.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Linaro provides a number of pre-built GCC toolchains for both 32 and
64bit ARM. Switch to their 2017.02 release of gcc-6.3.1 for both.
Cc: Koen Kooi <koen.kooi@linaro.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Many toolchains for ARM use the 'gnueabihf' suffix rather than just
'gnueabi', so allow these to be used, but with a lower priority than
'gnueabi' ones.
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
If the system is running PSCI firmware, the System Reset function
(func ID: 0x80000009) is supposed to be handled by PSCI, that is,
the SoC/board specific reset implementation should be moved to PSCI.
U-Boot should call the PSCI service according to the arm-smccc
manner.
The arm-smccc is supported on ARMv7 or later. Especially, ARMv8
generation SoCs are likely to run ARM Trusted Firmware BL31. In
this case, U-Boot is a non-secure world boot loader, so it should
not be able to reset the system directly.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Imports ARM SMC Calling Convention code from Linux 4.11-rc6.
The files have been copied as follows:
[Linux] [U-Boot]
arch/arm/kernel/smccc-call.S -> arch/arm/cpu/armv7/smccc-call.S
arch/arm64/kernel/smccc-call.S -> arch/arm/cpu/armv8/smccc-call.S
arch/arm/include/asm/opcodes* -> arch/arm/include/asm/opcodes*
include/linux/arm-smccc.h -> include/linux/arm-smccc.h
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Handle symlinks to files in the current directory. Other cases could be
handled with additional code, but this is a start.
Add explicit errors for absolute paths and links found in the middle of
a path (directories). Other cases like '..' or '.' will result with the
file not being found as when those path components are explicitly
provided.
Add a helper to decompress a null-terminated link name which is shared
with cramfs_list_inode.
Signed-off-by: Tyler Hall <tylerwhall@gmail.com>
Using a variably-sized type is incorrect here since we're reading a
fixed file format. Fixes cramfs on 64-bit platforms.
Signed-off-by: Tyler Hall <tylerwhall@gmail.com>
As with most other commands, this needs to factor in the sysmem offset
in the sandbox or it will try to dereference the simulated physical
address directly.
Signed-off-by: Tyler Hall <tylerwhall@gmail.com>
Avoid transfer parameter dev_id value with "-1" to .fec_get_hwaddr(),
it should transfer fec->dev_id to get mac address from fuse.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Stefano Babic <sbabic@denx.de>
The MIB RAM and FIFO receive start register does not exist on
i.MX6ULL. Accessing these register will cause enet not work well or
cause system report fault.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Enable this command so we can get an approximate performance measurement.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present on a cold reboot we must reset the CPU to get it to full speed.
With 64-bit U-Boot this happens in SPL. At present we print the banner
before doing this, the end result being that we print the banner twice.
Print the banner a little later (after the CPU is ready) to avoid this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
The Intel CPU name can have leading spaces. Remove them since they are not
useful.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
A size_t variable can never be negative.
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
As board-specific reset logic, it needs to issue reset signal
via CPLD when issuing 'reset' command in u-boot, this patch
solves the issue of reset command not working on T1024RDB.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
For E6500 cores, L2 cache has been used as init_ram. L1 cache is a
write through cache on E6500.If lines are not locked in both L1 and
L2 caches, crashes are observed during secure boot. This patch locks/
unlocks both L1 and L2 cache to prevent the crash.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Current sysclk fixing would fix all clocks with 'fixed-clock' compatible.
This patch is to fix sysclk by path to avoid any incorrect fixing.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Number of TZASC instances may vary across NXP SoCs.
So put TZASC configuration under instance specific defines.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
- Add SD secure boot target for ls1046ardb.
- Change the u-boot size defined by a macro for copying the main
U-Boot by SPL to also include the u-boot Secure Boot header size
as header is appended to u-boot image. So header will also be
copied from SD to DDR.
- CONFIG_MAX_SPL_SIZE is limited to 90KB. SPL is copied to OCRAM
(128K) where 32K are reserved for use by boot ROM and 6K for the
header.
- Reduce the size of CAAM driver for SPL Blobification functions
and descriptors, that are not required at the time of SPL are
disabled. Further error code conversion to strings is disabled
for SPL build.
Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Add NAND secure boot target for ls1043ardb.
- Change the u-boot size defined by a macro for copying the main
U-Boot by SPL to also include the u-boot Secure Boot header size as
header is appended to u-boot image. So header will also be copied
from SD to DDR.
- MACRO for CONFIG_BOOTSCRIPT_COPY_RAM is enabled to copy Bootscript
from NAND to DDR. Offsets for Bootscript on NAND and DDR have been
also defined.
Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
- Add SD secure boot target for ls1043ardb.
- Implement FSL_LSCH2 specific spl_board_init() to setup CAAM stream
ID and corresponding stream ID in SMMU.
- Change the u-boot size defined by a macro for copying the main
U-Boot by SPL to also include the u-boot Secure Boot header size as
header is appended to u-boot image. So header will also be copied
from SD to DDR.
- CONFIG_MAX_SPL_SIZE is limited to 90KB. SPL is copied to OCRAM
(128K) where 32K are reserved for use by boot ROM and 6K for secure
boto header.
- Error messages during SPL boot are limited to error code numbers
instead of strings to reduce the size of SPL image.
Signed-off-by: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Define bootscript and its header addresses for QSPI target
Also add PPA header address in Kconfig
Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Using changes in this patch we were able to reduce approx 4k
size of u-boot-spl.bin image. Following is breif description of
changes to reduce SPL size:
1. Changes in board/freescale/ls1046ardb/Makefile to remove
compilation of eth.c and cpld.c in case of SPL build.
2. Changes in board/freescale/ls1046ardb/ls1046ardb.c to keep
only ddr_init and board_early_init_f funcations in case of SPL
build.
3. Changes in ls1046a_common.h & ls1046ardb.h to remove driver
specific macros due to which static data was being compiled in
case of SPL build.
4. Disable MMC driver from bieng compiled in case of SPL NAND
build and NAND driver from bieng compiled in case of SPL MMC build.
Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Using changes in this patch we were able to reduce approx 10k
size of u-boot-spl.bin image. Following is breif description of
changes to reduce SPL size:
1. Changes in board/freescale/ls1043ardb/Makefile to remove
compilation of eth.c and cpld.c in case of SPL build.
2. Changes in board/freescale/ls1043ardb/ls1043ardb.c to keep
only ddr_init and board_early_init_f funcations in case of SPL
build.
3. Changes in ls1043a_common.h & ls1043ardb.h to remove driver
specific macros due to which static data was being compiled in
case of SPL build.
4. Disable MMC driver from bieng compiled in case of SPL NAND
build and NAND driver from bieng compiled in case of SPL MMC build.
5. Remove I2C driver support from SPL in case of LS1043ARDB.
Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Depending on DDR configuration, gcc-6.x will show up unused-const-
variable messages. Use __maybe_unused specifier for all dynamic_odt
variable definitions to remove these warnings.
Memory footprint will not increase as gcc will optimize out unused
constants.
Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com>
Signed-off-by: York Sun <york.sun@nxp.com>
The RK3399-Q7 ("Puma") SoM exposes UART0 as the Qseven UART (i.e. the
serial line available via standardised pins on the edge connector and
available on a RS232 connector).
To support boards (such as the RK3399-Q7) that require UART0 as a
debug console, we match CONFIG_DEBUG_UART_BASE and add the appropriate
iomux setup to the rk3399 SPL code.
As we are already touching this code, we also move the board-specific
UART setup (i.e. iomux setup) into board_debug_uart_init(). This will
be called from the debug UART init when CONFIG_DEBUG_UART_BOARD_INIT
is set.
As the RK3399 needs to use its board_debug_uart_init() function, we
have Kconfig enable it by default for RK3399 builds.
With everything set up to define CONFIG_BAUDRATE via defconfig and
with to have the SPL debug UART either on UART0 or UART2, the configs
for the RK3399 EVB are then update (the change for the RK3399-Q7 is
left for later to not cause issues on applying the change).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
For using mipi display, we need to enable lcd3v3
which supplied by rk808,so enable rk808 first.
Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
To enable mipi display, we need to enable pmic
rk808 first for lcd3v3 power,which use i2c0 to
communicate with soc. So enable i2c0.
Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
when enable PMIC rk808,the system will halt at very
early stage,log is shown as bellow.
INFO: plat_rockchip_pmu_init(1211): pd status 3e
INFO: BL31: Initializing runtime services
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x200000
INFO: SPSR = 0x3c9
time 44561b, 0 (<<----Just stop here)
It's caused by the absence of "{ }" in syscon_rk3399.c
,which will lead to memory overflow like below.According
to Sysmap file ,we can find the function buck_get_value
of rk808 is just follow the compatible struct,the pointer
"of_match" point to "buck_get_value",but it is not a
struct and don't have member of compatible, In this case,
system crash. So,on the face, it looks like that rk808 is
guilty.but he is really innocent.
while (of_match->compatible) { <<----------
if (!strcmp(of_match->compatible, compat)) {
*of_idp = of_match;
return 0;
}
of_match++;
}
Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
The RK3399-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230
connector) system-on-module from Theobroma Systems, featuring the
Rockchip RK3399.
It provides the following feature set:
* up to 4GB DDR3
* on-module SPI-NOR flash
* on-module eMMC (with 8-bit interace)
* SD card (on a baseboad) via edge connector
* Gigabit Ethernet w/ on-module Micrel KSZ9031 GbE PHY
* HDMI/eDP/MIPI displays
* 2x MIPI-CSI
* USB
- 1x USB 3.0 dual-role (direct connection)
- 2x USB 3.0 host + 1x USB 2.0 (on-module USB 3.0 hub)
* on-module STM32 Cortex-M0 companion controller, implementing:
- low-power RTC functionality (ISL1208 emulation)
- fan controller (AMC6821 emulation)
- USB<->CAN bridge controller
Note that we use a multi-payload FIT image for booting and have
Cortex-M0 payload in a separate subimage: we thus rely on the FIT
image loader to put it into the SRAM region that ATF expects it in.
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Fixed build warning on puma-rk3399:
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
The RK3399-Q7 (Puma) DTS should (of course) be dual-licensed.
This updates the licensing info in the rk3399-puma.dts.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The warm-reset of rk3188 socs keeps the remap setting as it was, so if
it was enabled, the cpu would start from address 0x0 of the sram instead
of address 0x0 of the bootrom, thus making the reset hang.
Therefore make sure the remap is disabled before attempting a warm reset.
Cold reset is not affected by this at all.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Most Rockchip socs have the ability to either map the bootrom or a sram
area to the starting address of the cpu by flipping a bit in the GRF.
Newer socs leave this untouched and mapped to the bootrom but the legacy
loaders on rk3188 and before enabled the remap functionality and the
current smp implementation in the Linux kernel also requires it to be
enabled, to bring up secondary cpus.
So to keep smp working in the kernel, mimic the behaviour of the legacy
bootloaders and enable the remap functionality.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Somehow 43b5c78d8d ("rockchip: cosmetic: Sort RK3288 boards") moved
the rock board in between some rk3288 board, probably as a result of
rebasing.
So move it back to its original position above all rk3288 boards.
Fixes: 43b5c78d8d ("rockchip: cosmetic: Sort RK3288 boards")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Now that most rockchip SoC based board have usb host support, enable
USB boot targets by default.
Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fixed build errors when CONFIG_CMD_USB not defined:
Signed-off-by: Simon Glass <sjg@chromium.org>
tinker board support ethernet and usb host, so enable USB, PXE and DHCP support.
Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
The RK3399 hangs during DMA of the Designware MMC controller, when
performing DMA-based transactions in SPL due to the DDR security settings
left behind by the BootROM (i.e. accesses to the first MB of DRAM are
restricted... however, the DMA is likely to target this first MB, as it
transfers from/to the stack).
System security is not affected, as the final security configuration is
performed by the ATF, which is executed after the SPL stage.
With this fix in place, we can now drop 'fifo-mode' in the DTS for the
RK3399-Q7 (Puma).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Due to the introduction of the pinctrl and clk driver, and using
device tree files, remove the unneeded hardcoded pin configuration
and clock enabling code from the board file.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Update the configuration files to support the device tree and driver
model, so do SPL. The device clock and pins configuration are handled
by the clock and the pinctrl drivers respectively.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Fix build error with sama5d3_xplained_mmc:
Signed-off-by: Simon Glass <sjg@chromium.org>
Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Due to the introduction of the pinctrl and clk driver, and using
device tree files, remove the unneeded hardcoded pin configuration
and clock enabling code from the board file.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Remove CONFIG_PHY_MICREL as per previous patch:
Signed-off-by: Simon Glass <sjg@chromium.org>
Update the configuration files to support the device tree and
driver model, so do SPL. The device clock and pins configuration
are handled by the clock and the pinctrl drivers respectively.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Add back CONFIG_PHY_MICREL to prevent a build error:
Signed-off-by: Simon Glass <sjg@chromium.org>
When driver model is used for LEDs, provide a command to allow LED access.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ziping Chen <techping.chan@gmail.com>
The existing 'led' command does not support driver model. Rename it to
indicate that it is legacy code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ziping Chen <techping.chan@gmail.com>
Allow LEDs to be blinked if the driver supports it. Enable this for
sandbox so that the tests run.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ziping Chen <techping.chan@gmail.com>
Add support for toggling an LED into the uclass interface. This can be
efficiently implemented by the driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ziping Chen <techping.chan@gmail.com>
It is useful to be able to read the LED as well as write it. Add this to
the uclass and update the GPIO driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ziping Chen <techping.chan@gmail.com>
At present this is very simple, supporting only on and off. We want to
also support toggling and blinking. As a first step, change the name of
the main method and use an enum to indicate the state.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ziping Chen <techping.chan@gmail.com>
These structures are normally named with 'uc' instead of 'uclass'. Change
this one for consistency.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ziping Chen <techping.chan@gmail.com>
There should be a blank line between each option. Add one before LED_GPIO.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ziping Chen <techping.chan@gmail.com>
With DM_SCSI enabled, blk_create_devicef() is called with blkz = 0, leading
to a divide-by-0 exception.
scsi_detect_dev() can be used to get the required parameters (block size
and number of blocks) from the drive before calling blk_create_devicef().
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
We might want to get information about the scsi device without initializing the partition.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This is a cosmetic change. target and LUN have kind of the same role in
this function. One of them was passed as a parameter and the other was
embedded in a structure. For consistency, pass both of them as parameters.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When CONFIG_DM_SCSI is defined, the SATA initialization will be implemented
in the scsi-uclass driver.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
All the clocks which has to be enabled has to be done in
enable_basic_clocks(), so moving enable sata clock to common
clocks enable function.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
When writing out some of our results we may now have UTF-8 characters
in there as well. Translate these to latin-1 and ignore any errors (as
this is for diagnostic and given the githash anything else can be
reconstructed by the user.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
This fixes a regression caused by
commit 07b2b78ce4
dm: usb: Convert USB storage to use driver-model for block devs
which caused part_init to be called when it was not previously.
Without this patch, the following happens when a USB sd card reader is used.
=> usb start
starting USB...
USB0: Port not available.
USB1: USB EHCI 1.00
scanning bus 1 for devices... 3 USB Device(s) found
scanning usb for storage devices... Device NOT ready
Request Sense returned 02 3A 00
### ERROR ### Please RESET the board ###
This happens because dev_desc->blksz is 0.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
We should invalidate the dcache before starting the DMA. In case there are
any dirty lines from the DMA buffer in the cache, subsequent cache-line
replacements may corrupt the buffer in memory while the DMA is still going on.
Cache-line replacement can happen if the CPU tries to bring some other memory
locations into the cache while the DMA is going on.
Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Reviewed-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Merely using dma_alloc_coherent does not ensure that there is no stale
data left in the caches for the allocated DMA buffer (i.e. that the
affected cacheline may still be dirty).
The original code was doing the following (on AArch64, which
translates a 'flush' into a 'clean + invalidate'):
# during initialisation:
1. allocate buffers via memalign
=> buffers may still be modified (cached, dirty)
# during interrupt processing
2. clean + invalidate buffers
=> may commit stale data from a modified cacheline
3. read from buffers
This could lead to garbage info being written to buffers before
reading them during even-processing.
To make the event processing more robust, we use the following sequence
for the cache-maintenance:
# during initialisation:
1. allocate buffers via memalign
2. clean + invalidate buffers
(we only need the 'invalidate' part, but dwc3_flush_cache()
always performs a 'clean + invalidate')
# during interrupt processing
3. read the buffers
(we know these lines are not cached, due to the previous
invalidation and no other code touching them in-between)
4. clean + invalidate buffers
=> writes back any modification we may have made during event
processing and ensures that the lines are not in the cache
the next time we enter interrupt processing
Note that with the original sequence, we observe reproducible
(depending on the cache state: i.e. running dhcp/usb start before will
upset caches to get us around this) issues in the event processing (a
fatal synchronous abort in dwc3_gadget_uboot_handle_interrupt on the
first time interrupt handling is invoked) when running USB mass
storage emulation on our RK3399-Q7 with data-caches on.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The dwc3_flush_cache() call was declared and used inconsistently:
* The declaration assumed 'int' for addresses (a potential issue
when running in a LP64 memory model).
* The invocation cast the address to 'long'.
This change ensures that both the declaration and usage of this
function consistently uses 'uintptr_t' for correct behaviour even
when the allocated buffers (to be flushed) reside outside of the
lower 32bits of memory.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Both these numbers are calculated in runtime and dynamically assigned
to the device descriptor during bind().
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
We don't want to claim that we support a serial number string and
later return nothing. Because of that, if g_dnl_serial is an empty
string, let's skip setting iSerialNumber to a valid number.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
A USB String descriptor can be up to 255 characters long and it's not
NULL terminated according to the USB spec. This means our
MAX_STRING_SERIAL should be 256 (to cope with NULL terminator).
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
After enabling log printing to lcd, when the screen starts
scrolling, system crashes. Log is shown as bellow:
"Synchronous Abort" handler, esr 0x96000045
"Synchronous Abort" handler, esr 0x96000045
Checking the source code, we found that the variable "pixels"
gets a wrong value:
int pixels = VIDEO_FONT_HEIGHT * vid_priv->line_length;
"pixels" here means the value of pixels for a character, rather
than the bytes for a character. So the variable "pixels" is 4
times bigger than it's exact value, which will cause the memory
overflow when the cpu runs the following code:
for (i = 0; i < pixels; i++)
*dst++ = clr; <<----
Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Some board do not use the dwc2 internal VBUS_DRV signal, but
use a gpio pin to enable the 5.0V VBUS power, add interface to
enable the power in dwc2 driver.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
This removes the default environment from the sr1500 header
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.
This board has no upstream devicetree in the kernel source,
so set to socfpga_cyclone5_sr1500.dtb.
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
--
Changes in v2:
- Remove unneeded CONFIG_BOOTFILE
- set devicetree name to match socfpga_{fpga model}_{board model}.dts
pattern
This removes the default environment from the socrates headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.
Change default devicetree name to match devicetree name in
upstream kernel source.
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
--
Changes in v2:
- Remove unneeded CONFIG_BOOTFILE
This removes the default environment from the SoCKit headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.
Change default devicetree name to match devicetree name in
upstream kernel source.
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
--
Changes in v2:
- Remove unneeded CONFIG_BOOTFILE
This removes the default environment from the de1 headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.
This board does not have a devicetree in the upstream kernel
source so set devicetree to socfpga_cyclone5_de1_soc.dtb.
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
--
Changes in V2:
- Remove unneeded CONFIG_BOOTFILE
- set devicetree name to match socfpga_{fpga model}_{board model}.dts
pattern
This removes the default environment from the C5 SoCDK headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.
In addition to the above, add support to boot from the custom
a2 type partition.
Change default devicetree name to match devicetree name in
upstream kernel source.
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
--
Changes in v2:
- Remove unneeded CONFIG_BOOTFILE
This removes the default environment from the A5 socdk headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.
Add support to boot from the custom a2 type partition.
Change default devicetree name to match devicetree name in
upstream kernel source.
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
--
Changes in v3:
- Fix small typo in defconfig, missing "C"
Changes in v2:
- Remove unneeded CONFIG_BOOTFILE
- Fix dtb name
a5config test
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
This removes the default environment from the de0 headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.
In addition to the above, add support to boot from the custom
a2 type partition
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
--
Changes in v2:
- Remove unneeded CONFIG_BOOTFILE
This adds a common environment and support for distro boot
in the common socfpga header.
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
--
Changes in v5:
- Per Frank, to support OpenSuse the ENV must be after the GPT
Changes in v4:
- Move env back to being right after the MBR
Changes in v3:
- fix spacing between asterix
- remove verify=n as a default setting
Changes in v2:
- Remove unneeded CONFIG_BOOTFILE and fdt_addr
- cleanup spacing in MMC env size
common
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Convert Altera DDR SDRAM driver to use Kconfig method.
Enable ALTERA_SDRAM by default if it is on Gen5 target.
Arria 10 will have different driver.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Disable the OC test on MCVEVK as the old PHY version does not provide
this information. This fixes the USB OTG operation.
Signed-off-by: Marek Vasut <marex@denx.de>
There is no point in having such gargantuan buffer, it only requires
huge malloc area. Reduce the DFU buffer size.
Signed-off-by: Marek Vasut <marex@denx.de>
Commit ce62e57fc5 ("ARM: boot0 hook: remove macro, include whole
header file") miss out cleaning macro in this header file, and this
has broken implementation of a boot header capability in socfpga
SPL. Remove the macro in this file, and recovering it back
to proper functioning.
Fixes: ce62e57fc5 ("ARM: boot0 hook: remove macro, include whole
header file")
Signed-off-by: Chee, Tien Fong <tien.fong.chee@intel.com>
With the port C enabled, we can read the GPI input state of:
* the DIP switches (USER_DIPSW_HPS[3:0]/HPS_GPI[7:4])
* the push buttons (USER_PB_HPS[3:0]/HPS_GPI[11:8])
Signed-off-by: Georges Savoundararadj <savoundg@gmail.com>
Signed-off by: Sid-Ali Teir <git.syedelec@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Marek Vasut <marex@denx.de>
This patch adds the steps to manually (re)build a Quartus FPGA project,
generate the required BSP glue, and update u-boot handoff files for
mainline SPL support. Requires Quartus toolchain and current U-Boot.
Signed-off-by: Steve Arnold <stephen.arnold42@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
The Vybrid SoC family has the same display controller unit (DCU)
like the LS1021A SoC. This patch adds platform data, pinmux defines
and clock control to enable the driver for Toradex Colibri Vybrid
module.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
DCU_LAYER_MAX_NUM is currently used for DCU_MODE_BLEND_ITER and it
actually overflows the maximum value of BLEND_ITER for Vybrid and
LS102XA. Fix this by using a default value of 2.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
When enabling the DCU and pixel clock, the test mode is activated
since this is the reset configuration. The test mode immediately
shows a red screen on a LCD. A moment later, the DCU gets
initialized properly.
This patch enables the pixel clock after initialization of the DCU
control register. This avoids this initial flicker on LCD screens.
While at it change the polarity of pixel clock to display samples
data on the rising edge.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Reviewed-by: Alison Wang <alison.wang@nxp.com>
Fix the framebuffer location to the very end of the available memory.
This allows to remove the area from available memory for the kernel,
which in turn allows to display the splash screen through the Linux
kernel boot process.
Ideas has been taken from the sunxi display driver, e.g.
20779ec3a5 ("sunxi: video: Dynamically reserve framebuffer memory")
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
sdhci_transfer_data() function transfers the blocks passed up to the
number of blocks defined in mmc_data, but returns immediately once all
the blocks are transferred, even if the loop exit condition is not met
(bit SDHCI_INT_DATA_END set in the STATUS word).
When doing multiple writes to mmc, returning right after the last block
is transferred can cause the write to fail when sending the
MMC_CMD_STOP_TRANSMISSION command right after the
MMC_CMD_WRITE_MULTIPLE_BLOCK command, leaving the mmc driver in an
unconsistent state until reboot. This error was observed in the rpi3
board.
This patch waits for the SDHCI_INT_DATA_END bit to be set even after
sending all the blocks.
Test: Reliably wrote 2GiB of data to mmc in a rpi3.
Signed-off-by: Alex Deymo <deymo@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The linux kernel driver for this module does not use a delay when
writing to the SDHCI_BUFFER register. This patch mimics that behavior
in order to speed up the mmc writes on the Raspberry Pi.
Signed-off-by: Alex Deymo <deymo@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add the driver model support for Atmel mci while retaining the
existing legacy code. This allows the driver to support boards
that have converted to driver model as well as those that have not.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This driver implements MMC support on Meson GX (S905) based systems.
It's based on Carlo Caione's work, changes:
- BLK support added
- general refactoring
Signed-off-by: Carlo Caione <carlo@caione.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
As a prerequisite for adding a Meson GX MMC driver update the
Meson GXBB / Odroid-C2 device tree in Uboot with the latest
version from Linux.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Due to the introduction of the pinctrl and clk driver, and using
device tree files, remove the unneeded hardcoded pin configuration
and clock enabling code from the board file.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Update the configuration files to support the device tree and driver
model, so do SPL. The device clock and pins configuration are handled
by the clock and the pinctrl drivers respectively.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Due to the introduction of the pinctrl and clk driver, and using
device tree files, remove the unneeded hardcoded pin configuration
and clock enabling code from the board file.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Update the configuration files to support the device tree and
driver model, so do SPL. The device clock and pins configuration
are handled by the clock and the pinctrl drivers respectively.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Add #ifndef CONFIG_DM_GPIO for CONFIG_AT91_GPIO define to avoid
the redefine compilation error.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
The MMC SPL locates the BSS section to a different memory region
from text, then use "_image_binary_end" variable to point to the
correct device tree location.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Because the MMC SPL puts the bbs section in the ddr memory, move
calling mem_init() before calling spl_init().
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
When OF_CONTROL is enabled, MMC boot device should not be detected
automatically, it should be MMC1 fixedly only the status "enabled"
is available.
Add NAND Flash boot device as well.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Add the device tree file for sama5d4ek board.
The dts file is copied from Linux-4.4, do the following changes.
- add the "u-boot,dm-pre-reloc" property to determine which nodes
which are needed by SPL and by the board_init_f stage.
- fix the compilation warning.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Add the device tree files for sama5d4 Xplained board.
The dts files are copied from Linux-4.4, do the following changes.
- add reg property for pinctrl node.
- move the gpio nodes(pioA, pioB, pioC ...) from the pinctrl child's
nodes to its slibling nodes.
- add the "u-boot,dm-pre-reloc" property to determine which nodes
which are needed by SPL and by the board_init_f stage.
- fix the compilation warnings.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Add the device tree file for sama5d3 Xplained board.
The dts files are copied from the Linux-4.9, do changes as below.
- add the "u-boot,dm-pre-reloc" property to determine which nodes
which are needed by SPL and by the board_init_f stage.
- fix the compile warning.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Add the device tree files for sama5d3xek board.
The dts files are copied from Linux-4.9, do the changes as below.
- add reg property for the pinctrl node.
- move the gpio nodes (pioA, pioB, pioC ...) as the pinctrl's
slibling nodes.
- add the "u-boot,dm-pre-reloc" property to determine which nodes
which are needed by SPL and by the board_init_f stage.
- fix the compile warning.
- add spi0 node aliases.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
AT91 PIO controller is a combined gpio-controller, pin-mux and
pin-config module. The peripheral's pins are assigned through
per-pin based muxing logic.
Each SoC will have to describe the its limitation and pin
configuration via device tree. This will allow to do not need
to touch the C code when adding new SoC if the IP version is
supported.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The intention of the removal is the preparation to introduce the
new AT91 PIO pinctrl driver.
Use the union to make the PIO3 and PIO2's registers be together
and make their offset aligned.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Because there isn't the implementation of gpio_set/get_value()
and gpio_set/get_value() after the at91 gpio driver is converted
to support the driver model, use at91_set_gpio_value() and
at91_get_gpio_value()
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When the CONFIG_ATMEL_LEGACY is undefined, according to the following
defines, at91_set_gpio_value() references to at91_set_pio_value(x, y)
with two parameters.
#define at91_set_gpio_value(x, y) at91_set_pio_value(x, y)
#define at91_get_gpio_value(x) at91_get_pio_value(x)
But there isn't the implementation of at91_set_pio_value(x, y) with
two parameters in U-Boot. This is an error.
Same as at91_get_gpio_value(x) define.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
One of these has crept in in this commit:
40a808f1 ARCv2: SLC: Make sure busy bit is set properly on SLC flushing
Adjust buildman to handle it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Not force to use python from PATH. Issue was noted when building with
Yocto, because python from the distro is always taken instead of
python-native built during Yocto process.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
There is a strange interaction with drivers which use DMA if the cache
starts off in a dirty state. Buffer space which the driver reads (but has
not previously written) can contain zero bytes from alloc_priv(). This can
cause corruption of the memory used by DMA for incoming data.
Fix this and add a comment to explain the problem.
This allows the dwc2 driver to work correctly with driver model, for
example.
Signed-off-by: Simon Glass <sjg@chromium.org>
uclass_find_device_by_seq() prints seq and req_seq when debugging is
enabled, but this information is not very useful by itself. Add the
name of he driver to this information. This improves debugging as it
shows which devices are being considered.
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Acked-by: Simon Glass <sjg@chromium.org>
With skeleton.dtsi being dropped it is more likely that the /aliases node
will be last in the device tree. Update fdtgrep to handle this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com>
With Python 3.5.2 encode will throw an exception if val is a byte array.
Decode it to a string first. This assumes it's utf-8, if it's not valid
utf-8 it will throw an exception.
Signed-off-by: George McCollister <george.mccollister@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
os.read() returns a byte array in Python 3.5.2 and needs to be converted
into a string. Check if the returned value is an instance of bytes and
if it is decode it as a utf-8 string. If it is not a utf-8 encoded string
the decoding may fail with an exception.
Prior to this fix the comparisions check data == "" would fail when data
was b'' and would cause an infinite memory leaking loop. joins would
also fail with an exception below but due to the infinite loop it never
made it that far.
Signed-off-by: George McCollister <george.mccollister@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Do not condition the compilation of the U_BOOT_DRIVER by !OF_PLATDATA.
This is inconsistent with the majority of other drivers. This also
blocks OF_PLATDATA boards with an 16550-compatible serial from using
serial in SPL.
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Added tweak for rock to avoid a TPL build failure:
Signed-off-by: Simon Glass <sjg@chromium.org>
Instead of having CONFIG_SANDBOX_BITS_PER_LONG in sandbox.h set to 64
with a comment to change to 32 on a 32bit host, simply set this to 64 in
asm/types.h and have the comment be there.
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Add support for %p, %pa[p], %pM, %pm and %pI4 formats to tiny-printf.
%pM and %pI4 are widely used by SPL networking stack and is required if
networking support is desired in SPL.
%p, %pa and %pap are mostly used by debug prints and hence supported
only when DEBUG is enabled.
Before this patch:
$ size spl/u-boot-spl
text data bss dec hex filename
99325 4899 218584 322808 4ecf8 spl/u-boot-spl
After this patch (with CONFIG_SPL_NET_SUPPORT):
$ size spl/u-boot-spl
text data bss dec hex filename
99666 4899 218584 323149 4ee4d spl/u-boot-spl
So, this patch adds ~350 bytes to code size.
If CONFIG_SPL_NET_SUPPORT is not enabled, this adds ~25 bytes.
If CONFIG_USE_TINY_PRINTF is disabled then:
$ size spl/u-boot-spl
text data bss dec hex filename
101116 4899 218584 324599 4f3f7 spl/u-boot-spl
So, there is still ~1.4K space saved even with support for %pM/%pI4.
Compiler used is to build is:
arm-linux-gnueabihf-gcc (Linaro GCC 6.2-2016.11) 6.2.1 20161016
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
I don't have the hardware test this, but it is almost certainly a typo
in the code dating back to at least 2004.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This allows us to use the same DRAM init function on all archs. Add a
dummy function for arc, which does not use DRAM init here.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Dummy function on nios2]
Signed-off-by: Tom Rini <trini@konsulko.com>
This function name shadows a global name but is in fact different. This
is very confusing. Rename it to help with the following refactoring.
Signed-off-by: Simon Glass <sjg@chromium.org>
Spam detection software, running on the system "lists.denx.de",
has identified this incoming email as possible spam. The original
message has been attached to this so you can view it or label
similar future email. If you have any questions, see
@@CONTACT_ADDRESS@@ for details.
Content preview: Previous change to create _printch causes the stack to be
used, breaking printch before stack is available. Inline _printch to prevent
this happening. Signed-off-by: Tim Chick <tim.chick@mediatek.com> --- [...]
Content analysis details: (6.3 points, 5.0 required)
pts rule name description
---- ---------------------- --------------------------------------------------
0.7 RCVD_IN_XBL RBL: Received via a relay in Spamhaus XBL
[188.29.165.105 listed in zen.spamhaus.org]
3.6 RCVD_IN_PBL RBL: Received via a relay in Spamhaus PBL
1.6 RCVD_IN_BRBL_LASTEXT RBL: No description available.
[188.29.165.105 listed in bb.barracudacentral.org]
0.4 RDNS_DYNAMIC Delivered to internal network by host with
dynamic-looking rDNS
Previous change to create _printch causes the stack to be used,
breaking printch before stack is available. Inline _printch to
prevent this happening.
Signed-off-by: Tim Chick <tim.chick@mediatek.com>
fw_env_open allocates buffers to store the environment, but these
buffers are never freed. This becomes quite nasty using the fw_ tools as
library, because each access to the environment (even just reading a
variable) generates a memory leak equal to the size of the environment.
Fix this renaming fw_env_close() as fw_env_flush(), because the function
really flushes the environment from RAM to storage, and add a
fw_env_close function to free the allocated resources.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Changes in the environment library are difficult to tracked by programs
using the library. Add simply an API version number that must be
increased each time when the API is changed.
This can be detected and a program can work with different versions of
the library.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Move U-Boot private data into a separate file. This
lets export fw_env.h to be used by external programs
that want to change the environment using the library
built in tools/env.
Signed-off-by: Stefano Babic <sbabic@denx.de>
aes.h is a too generic name if this file can
be exported and used by a program.
Rename it to avoid any conflicts with
other files (for example, from openSSL).
Signed-off-by: Stefano Babic <sbabic@denx.de>
Logic PD has an i.MX6Q system on module (SOM) with a development kit. The
SOM has a built-in microSD socket, DDR and NAND flash. The development kit
has an SMSC Ethernet PHY, serial debug port and a variety of peripherals.
This have been verified to boot the i.MX6Q version over either SD
on the development kit or NAND built into the SOM. Items in the dtsi file
are specific to the SOM itself. Items in the dts file are in the baseboard.
Future versions of the SOM will come out supporting the same basebord and
potentially future base boards will come out supporting the same SOM.
Signed-off-by: Adam Ford <aford173@gmail.com>
The handler do_setdsr receives only the dsr parameter,
the action is parsed before.
Error was introduced when restructuring the mmc command
implementation in commit 1fd93c6e7d.
Reported-by: Michael Krummsdorf <Michael.Krummsdorf@tq-group.com>
Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
The num/denom is a float value, but in the calculation it is convert
to integer 0, and wrong result.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
By default, u-boot itself outputs on the serial console at 115200, so
it may as well pass the same value to the booted operating system as
well.
Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Apply the proper setting for the reserved bits in SetDes Test and System Mode Control register
to avoid the voltage peak issue while we do the IEEE PHY comformance test
Signed-off-by: Ken Lin <yungching0725@gmail.com>
Acked-by: Akshay Bhat <akshay.bhat@timesys.com>
Add the delay (10ms) to ensure the clock is stable and to meet the clock-to-reset(1ms) requirement recommended in the AR8033 datasheet
Signed-off-by: Ken Lin <yungching0725@gmail.com>
Acked-by: Akshay Bhat <akshay.bhat@timesys.com>
Change the PMIC bulk configuration from auto mode to sync mode to avoid the voltage shutdown issue
Signed-off-by: Ken Lin <yungching0725@gmail.com>
Acked-by: Akshay Bhat <akshay.bhat@timesys.com>
Add the configuration options for display initialization in case we need to
do the display initialization in kernel to support different timing settings
Signed-off-by: Ken Lin <yungching0725@gmail.com>
Acked-by: Akshay Bhat <akshay.bhat@timesys.com>
- Remove arch/arm/cpu/arm926ejs/imx/ which is not available
- arch/arm/cpu/imx-common/ => arch/arm/imx-common/
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
As reported in STAR 9001165532, an SLC control reg read (for checking
busy state) right after SLC invalidate command may incorrectly return
NOT busy causing software to NOT spin-wait while operation is underway.
(and for some reason this only happens if L1 cache is also disabled - as
required by IOC programming model)
Suggested workaround is to do an additional Control Reg read, which
ensures the 2nd read gets the right status.
Same fix made in Linux kernel:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c70c473396cbdec1168a6eff60e13029c0916854
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
For some reason Python 3 seems to think it does not need to build
the library. Using the --force parameter makes sure that the library
gets built always. This is especially important since we move the
library in the next step of the Makefile, hence forcing a rebuild
every time the higher level Makefile triggers a rebuild is required
to make sure the library is always there.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Simon Glass <sjg@chromium.org>
Since Binutils 1a9ccd70f9a7[1] u-boot will not link targets that set
CONFIG_SYS_TEXT_BASE=0 with the following error:
LD u-boot
arm-linux-gnueabi-ld.bfd: u-boot: Not enough room for program headers, try
linking with -N
arm-linux-gnueabi-ld.bfd: final link failed: Bad value
The issue can be reproduced with the bad binutils and the rock2_defconfig
target.
This issue was also encountered by the powerpc kernel[2], with the fix
being to pass --no-dynamic-linker for linkers newer than 2.26 when this
flag was introduced. The option tells ld that the PIE or shared lib does
not need loaded program headers.
Ubuntu Zesty's Binutils 2.27.51.20161202 hits this error.
[1] https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commit;h=1a9ccd70f9a7
[2] https://git.kernel.org/cgit/linux/kernel/git/powerpc/linux.git/commit/?h=next&id=ff45000fcb56b5b0f1a14a865d3541746d838a0a
Signed-off-by: Joel Stanley <joel@jms.id.au>
[AF: Apply to LDFLAGS_$(SPL_BIN) as well, suggested by Tom Rini]
Signed-off-by: Andreas Färber <afaerber@suse.de>
This simple PMU driver allows to tyrn power on and off for selected
devices. In particularly Intel Tangier needs to power on SDHCI
controllers in order to access to them during board initialization.
In the future it might be expanded to cover other Intel MID platforms,
that's why it's located under arch/x86/lib and called pmu.c.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add a specific serial driver for Intel MID platforms.
It has special fractional divider which can be programmed via UART_PS,
UART_MUL, and UART_DIV registers.
The UART clock is calculated as
UART clock = XTAL * UART_MUL / UART_DIV
The baudrate is calculated as
baud rate = UART clock / UART_PS / DLAB
Initialize fractional divider correctly for Intel Edison platform.
For backward compatibility we have to set initial DLAB value to 16
and speed to 115200 baud, where initial frequency is 29491200Hz, and
XTAL frequency is 38.4MHz.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
With recent changes, some x86-specific rom tests of binman fail to
run. Fix it by adding missing filenames in corresponding entries.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Checking 'is_zimage' at this time will always fail and therefore booting
a FIT style image will always lead to this error message:
"## Kernel loading failed (missing x86 kernel setup) ..."
This change now removes this check and booting of FIT images works just
fine.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Now that we have added file names from Kconfig in x86 u-boot.dtsi,
update binman to avoid using hard-coded names.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Since we now have the file names configurable via Kconfig for the flash
descriptor and intel-me files, add these from Kconfig in the corresponding
dts nodes.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This introduces two Kconfig options to enable board specific filenames
for the Intel binary blobs to be used to generate the SPI flash image.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present there are only 8-bit and 32-bit read/write routines in
the rtc uclass driver. This adds the 16-bit support.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move the OPTEE load address to 0xbdb00000 in order to avoid
overlap with the memory regions used in radio and RVC usecases.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Move the OPTEE load address to 0xbdb00000 in order to avoid
overlap with the memory regions used in radio and RVC usecases.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Enable SPL_USB_HOST_SUPPORT in the default defconfig to allow
booting from USB peripherals. Unlike the non-HS boards, we
already load SPL to a 0x4030_0000+ address, so no other changes
are needed.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Additions have been made to the non-HS defconfig without the same
being made to the HS defconfig, sync them.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Additions have been made to the non-HS defconfig without the same
being made to the HS defconfig, sync them.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Additions have been made to the non-HS defconfig without the same
being made to the HS defconfig, sync them.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Sync new additions to non-HS defconfig with HS defconfig. Also add SPL
NAND support, this was disabled before due to size constraints, enable
this now at the expense of the less used GPT partition support.
Signed-off-by: Andrew F. Davis <afd@ti.com>
FIT support in the net boot case is much like the RAM boot case in that
we load our image to "load_addr" and pass a dummy read function into
"spl_load_simple_fit()". As the load address is no longer hard-coded to
the final execution address, legacy image loading will require load_addr
to be set correctly in the image header.
Signed-off-by: Andrew F. Davis <afd@ti.com>
TI K2G secure devices have to be built with TI_SECURE_DEVICE, FIT, and
FIT_IMAGE_POST_PROCESS enabled. Add a dedicated defconfig for this.
Signed-off-by: Andrew F. Davis <afd@ti.com>
TI K2HK secure devices have to be built with TI_SECURE_DEVICE, FIT, and
FIT_IMAGE_POST_PROCESS enabled. Add a dedicated defconfig for this.
Signed-off-by: Andrew F. Davis <afd@ti.com>
TI K2E secure devices have to be built with TI_SECURE_DEVICE, FIT, and
FIT_IMAGE_POST_PROCESS enabled. Add a dedicated defconfig for this.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch makes SYS_TEXT_BASE a config option for Keystone2
so that it can be used to load u-boot at different addresses
on secure and non-secure Keystone2 devices.
Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Add a section describing the secure boot image used on
Keystone2 secure devices.
Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Adds an additional image type needed for supporting secure keystone
devices. The build generates u-boot_HS_MLO which can be used to boot
from all media on secure keystone devices.
Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
As K2 can directly boot U-Boot, add u-boot_HS_MLO as the secure image
name for secure K2 devices, for all boot modes other than SPI flash.
Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Like the OMAP54xx, AM43xx, & AM33xx family SoCs, the keystone family
of SoCs also have high security enabled models. Allow K2E devices to
be built with HS Device Type Support.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit implements the board_fit_image_post_process() function for
the keystone architecture. This function calls into the secure boot
monitor for secure authentication/decryption of the image. All needed
work is handled by the boot monitor and, depending on the keystone
platform, the security functions may be offloaded to other secure
processing elements in the SoC.
The boot monitor acts as the gateway to these secure functions and the
boot monitor for secure devices is available as part of the SECDEV
package for KS2. For more details refer doc/README.ti-secure
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
The function 'board_fit_image_post_process' is defined only when the
config option CONFIG_FIT_IMAGE_POST_PROCESS is enabled. For secure
systems that do not use SPL but do use FIT kernel images, only
CONFIG_FIT_IMAGE_POST_PROCESS will be defined, which will result in an
implicit declaration of function 'board_fit_image_post_process' warning
while building u-boot. Fix this warning.
Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
The most common name for a FIT image containing a bootable kernel is
"fitImage", as our builds now use this name also, change this to the
default in our U-Boot environment.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Various commands to NAND flash results in the NAND flash becoming busy.
For those commands the SoC should wait until the NAND indicates it is
no longer busy before sending further commands. However, there is a delay
between the time the SoC sends its last command and when the NAND flash
sets its Ready/Busy Pin. This delay (tWB) must be respected or the SoC may
falsely assume the flash is ready when in reality it just hasn't had enough
time to indicate that it is busy.
Properly delaying by tWB is already done for nand_command/nand_command_lp
in nand_base.c including the version of it in the Linux kernel. Therefore,
this patch brings the handling of tWB delay inline to nand_base.c
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
[trini: Reformat comments slightly]
Signed-off-by: Tom Rini <trini@konsulko.com>
Now that we have common MMC/SD boot environment
variables that can be used across TI platforms,
switch OMAP-L138 LCDK to use them.
As a nice side-effect, we get support for using
uEnv.txt on this platform.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Introduce include/environment/ti/mmc.h that
consolidates environment variable definitions
for various TI boards that support MMC/SD.
This allows reuse of same environment variables
on non-ARMv7 TI platforms like OMAP-L138 for
example.
While at it, move DFU-related environment variable
includes to only non-SPL builds for AM335x and
AM437x since they are not really used for SPL
today.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Use environment variables for various memory addresses
used on OMAP-L138 LCDK board. This makes it easy to
customize the boot process.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Enable some generic filesystem commands as
well as disk partition related commands for
OMAP-L138 LCDK board.
These help in booting Linux from MMC/SD, for
example.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
OMAP-L138 LCDK board does not have a SPI flash.
Remove spiboot related environment variable
definitions.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Up till this commit passing NULL as input parameter was allowed, but not
handled properly.
When one passed NULL to one of this function parameters, the code was
executed causing data abort.
However, what is more interesting, the abort was not caught because of code
execution in HYP mode with masked CPSR A bit ("Imprecise Data Abort mask bit).
The TI's AM57xx SoC switch to HYP mode with A bit masked in lowlevel_init.S
due to SMC call. Such operation (by default) is performed in SoC ROM code.
The problem would pop up when one:
- Switch back to SVC mode after disabling LPAE support
- Somebody enables A bit (by executing cpsie a asm instruction)
and then the previously described exception would be caught.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
The OMAP WDT IP block requires to be stopped before any write to its
registers is performed.
This problem has been thoroughly described in Linux kernel:
"watchdog: omap: assert the counter being stopped before reprogramming:
SHA1: 530c11d432727c697629ad5f9d00ee8e2864d453
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Under the plethora of #ifdefs, the xyzModem code hid this pearl:
static char *zm_out = (char *) 0x00380000;
This was only enabled when DEBUG is defined, so it's probably why it
went unnoticed for so long. No idea what platform had memory at that
exact location, but the this approach is extremely hacky.
Use a static buffer instead.
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
spl_mmc.c calls mmc_initialize(). This symbol is provided in
drivers/mmc/mmc.c when CONFIG_GENERIC_MMC is enabled.
The sunxi Kconfig case is an oddball because it redefines
SPL_MMC_SUPPORT.
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
[trini: Update arch/arm/cpu/armv8/zynqmp/Kconfig]
Signed-off-by: Tom Rini <trini@konsulko.com>
The default value of BOOTSTAGE_STASH_SIZE should be set to hexadecimal,
but an integer value is set. This fixes the BOOTSTAGE_STASH_SIZE number
from hexadecimal to integer.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
On ARM v7M, the processor will return to ARM mode when executing blx
instruction with bit 0 of the address == 0. Always set it to 1 to stay
in thumb mode.
Similar commit:
f99993c108
Author: Matt Porter <mporter@konsulko.com>
Date: Tue May 5 15:00:23 2015 -0400
common/cmd_boot: keep ARM v7M in thumb mode during do_go_exec()
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
ft_cpu_setup() already calls fdt_fixup_ethernet(), calling it
in image_setup_libfdt() is both redundant and breaks any modifications
done by ft_board_setup(). Restore the old behavior by removing
the call in image_setup_libfdt()
Fixes: 13d06981a9 ("image: Add device tree setup to image library")
Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com>
The env command 'args_fit' does not define a root path, this forces us to
embed the rootfs into the FIT image. FIT images do not need to contain a
rootfs, when they do not the kernel will fall-back to the kernel argument
'root', if this is not defined the kernel will not boot. It is safe to
add this as when we do have the rootfs in FIT this argument is ignored.
As 'loadfit' is only called from the MMC boot path, use 'args_mmc' to
correctly populate 'bootargs'.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Good evening,
I am trying to port FreeBSD to the ASUS Tinker Board, a computer based
on the Rockchip 3288 SoC. FreeBSD's boot loader (named loader(8)) needs
CONFIG_API to be enabled, but trying to build an U-Boot from trunk with
both CONFIG_API and CONFIG_BLK (as required for Rockchip SoC's?) leads
to the following build failure:
$ CROSS_COMPILE=arm-none-eabi- gmake tinker-rk3288_defconfig all
...
CC api/api_storage.o
api/api_storage.c: In function 'dev_read_stor':
api/api_storage.c:334:9: error: 'struct blk_desc' has no member named 'block_read'
if ((dd->block_read) == NULL) {
^~
api/api_storage.c:339:11: error: 'struct blk_desc' has no member named 'block_read'
return dd->block_read(dd, start, len, buf);
^~
api/api_storage.c:340:1: warning: control reaches end of non-void function [-Wreturn-type]
}
^
gmake[2]: *** [scripts/Makefile.build:281: api/api_storage.o] Fehler 1
gmake[1]: *** [Makefile:1229: api] Fehler 2
gmake: *** [Makefile:460: __build_one_by_one] Error 2
I applied the following fix, but the product doesn't boot. Perhaps
that's not a property of the fix though:
Yours,
Robert Clausecker
As per the latest pinmux data available for AM572x EVM,
rev A3, input should be enabled on MMC clock lines for
MMC2/2/3 for stable operation.
Further, AM572x TRM, SPRUHZ6, Revised June 2016, in
section 18.4.6.1.1 "Pad Configuration Registers" states
that input should be enabled for MMC 2/3/4 clock lines.
Enable input on MMC1 and MMC3 clock to match the latest
pinmux data. Input is already enabled on MMC2 clock for
BeagleBoard x15. Further, input is already enabled on all
MMCx clocks for other AM57xx boards (AM572x and AM571x
IDK).
Tested with HS and UHS SD card on AM572x EVM Rev A3.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
SPI U-Boot image for K2 boards have now exceeded 512K partition
allocated to it and no longer fit the partitions defined in kernel DTS
file. Therefore, pass an updated MTD partition table from U-Boot as
kernel command line arguments to avoid kernel from accidentally
modifying boot loader image that has overflowed to next user partition.
To do is, introduce a common environment file for declaring SPI
partition so that each individual boards need not repeat the same.
Choose appropriate SPI bus from board config file and pass it as command
line argument to kernel.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Recent Linux distributions (e.g. Debian 9) include cross-compilers for
AArch64, but only for the aarch64-linux-gnu triplet only. It can thus
be expected that users will attempt to use the system cross-compiler
(instead of an aarch64-elf variant) to compile U-Boot for their ARMv8
target systems.
One key differences between an aarch64-linux-gnu and an aarch64-elf
compiler are the default settings regarding position-independent: with
the aarch64-linux-gnu compiler, the default will create and use the
global offset table.
This change-set adjusts the list of sections copied on ARMv8 to include
the GOT sections. With this added, the list matches the previous setup
for AArch32 closely.
Note that this is not an 'academic' issue, but was in fact encountered
by our QA during testing of the RK3399-Q7 BSP and resulted in an
early failure of the SPL stage during FDT setup.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
SPL has been restricted to use only dev 0 based on the assumption that only
one MMC device is registered. This is not always the case and many
platforms now register several devices as expected by the spl mmc boot code
For those platform SPL_ENV_SUPPORT is broken if dev is forced to 0.
A word of warning: this commit may break SPL_ENV_SUPPORT on platforms that
do not register the same MMC controllers in SPL and in u-boot (mostly iMX6
based platforms). Fortunately none of those activate SPL_ENV_SUPPORT in
their default configuration.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
This enables the support for the Allwinner A23 Evaluation Board (EVB),
that already had a device tree (from Linux) but no defconfig.
This board has an AXP223 PMIC, some NAND, Audio out and in plugs, an
accelerometer and light sensor, as well as a USB HSIC hub and a USB
OTG mini-USB connector. It also has a Wifi/BT chip.
Access to the other buses (LCD, MIPI DSI, LVDS, etc) can be done
through dedicated pin headers.
Signed-off-by: Florent Jacquet <florent.jacquet@free-electrons.com>
Cc: Jagan Teki <jagan@openedev.com>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
On boards that defines ENV_IS_NOWHERE, such as the NES classic, commit
19dbe7d1a3f7 ("common: Move environment choice to Kconfig") broke the build
because of a missing environment size.
Reintroduce a default environment size consistent with what we had before.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
If we depend on the ARCH_SUNXI configuration option, the boards that do not
have NAND support enabled (with the associated options) will not compile
anymore.
Depend on the NAND driver configuration option to make sure that is not the
case.
Reported-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
CMD_UBIFS can't compile without CMD_UBI enabled. Make sure we can't end up
in that case.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Heiko Schocher <hs@denx.de>
Recently some sunxi related code was moved to arch/arm/mach-sunxi, but
the MAINTAINERS entry was not updated to reflect this. Add this, and
the board level boards/sunxi directory to our entry.
While at it, also update its status, to reflect the current active
maintainership.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The Sunchip CX-A99 is a board used in some media players. It features:
An Allwinner A80 ARM SoC (4 * Cortex-A7 + 4 * Cortex-A15 cores)
2 GiB or 4 GiB DDR3 DRAM
AXP808 PMIC
16 GB or 32 GB eMMC
SDIO Wifi/Bluetooth/FM module
SD card slot
1 USB 3.0 connector
2 USB 2.0 connectors
SATA connector
UART connector (internally) for serial console
Ethernet connector (10/100/1000 Mbit/s)
HDMI connector
Composite video and analog audio connector
S/PDIF connector
IR remote control receiver
This patch adds a defconfig for the board. The DRAM settings are as found
in the vendor sys_config.fex file.
It has a preliminary device tree for use until a device tree is accepted
upstream, after which it can be replaced by the upstream version.
Signed-off-by: Rask Ingemann Lambertsen <rask@formelder.dk>
[squash commits, and edited new meanful commit message]
Signed-off-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
commit 56b0730157f70dc23d6caff9e7ceb8b377b96b9f upstream.
On the A80, mmc1 is available on pingroup G. Designs mostly use this
to connect to an SDIO WiFi chip.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Rask Ingemann Lambertsen <rask@formelder.dk>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The CHIP Pro is a SoM that features the GR8 SIP, an AXP209, a BT/WiFi chip
and a 512MiB SLC NAND.
This it's an SLC NAND, it doesn't suffer the same drawbacks than found on
the MLC NANDs, and we can enable it right away.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Introduce a new sunxi-spl-with-ecc.bin image with already the right header,
ECC, randomizer and padding for the BROM to be able to read it.
It needs to be flashed using a raw access to the NAND so that the
controller doesn't change a thing to it, since we already have all the
right parameters.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
The default U-Boot offset for the Allwinner SoCs was set to 32kB.
This was probably to try to maintain some compatibility with the current
image that we build for the MMC where the U-Boot binary is also located at
a 32kB offset.
However, this causes a number of issues. The first one is that it prevents
us from using a backup SPL entirely, which is troublesome in case where the
first would be corrupt (especially on MLC which have a higher number of
bitflips).
We also cannot use the original MMC image on the NAND, because we need to
prepare the SPL image to include the ECCs and randomizer settings, which
reduces the interest of setting it at that particular offset.
It also prevents us from upgrading and flashing the U-Boot and SPLs
independantly, since it's very likely that it will fall in the same erase
block.
Since that default wasn't used by any board, change it for 8MB, which will
be in an erase block of its own, all the erase blocks being multiple of
two. The highest erase block size we encountered is 4MB, which means that
in this particular setup, the first and second erase blocks will be for the
SPL and its backup, and the third for U-Boot.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
CMD_MTDPARTS is something the user might or might not want to select, and
might depends on (or be selected by) other options too.
This is even truer for the MTDIDS_DEFAULT and MTDPARTS_DEFAULT options that
might change from one board to another, or from one user to the other,
depending on what it expects and what storage devices are available.
In order to ease that configuration, add those options to Kconfig.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The environment location is something that might change per board
(depending on what storage options are availaible there) or depending on
the user choice (when we have several options).
Instead of hardcoding it in our configuration header, create a Kconfig
choice with the options we use for now, and the symbols that depend on it.
Once done, also remove the irrelevant sunxi defines.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
We will need the bch functions in the tool to generate the SPL images for
the Allwinner SoCs.
Do the needed adjustments so that we can use it on the host.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
When trying to autodetect the ECC and randomization configurations, the
driver starts with a randomization disabled and no seeds.
In this case, the number of seeds is obviously 0, and the randomize boolean
is set to false.
However, the logic that retrieves the seed for a given page offset will
blindly use the number of seeds, without testing if the randomization is
enabled, basically doing a modulo by 0.
As it turns out, the libgcc in the common toolchain returns 0 here, which
was our expected value in such a case, and why we would not detect it.
However, U-Boot's libgcc will for some reason return from the function
instead, resulting in an error to load the U-Boot binary in the SPL.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Scott Wood <oss@buserror.net>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Add support for the NanoPi NEO Air H3 board from friendlyarm.com . This
board contains WiFi, Bluetooth, 8GB eMMC storage and 512 MB DDR3 ram.
Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
[Rebase on master]
Signed-off-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This ports the support for configuring a GPIO for resetting the
Ethernet PHY (incl. such details as the reset polarity and
pulse-length) from the Designware driver.
X-AffectedPlatforms: A64-uQ7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Remove the board_power_init() function.
It will be initialized with device-tree.
In future, it will be controlled with regulator API.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Remove the unused functions.
Never call the get_soft_i2c_scl/sda_pin() aynwhere.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Remove the board_i2c_init() function.
i2c should be initialized with device-tree file.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add the i2c-gpio nodes for fuelgauge and max77693.
There are i2c8 and i2c9.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
With d53ecad92f some unused interrupt related code was removed.
However all of these options are currently unused. Rather than migrate
some of these options to Kconfig we just remove the code in question.
The only related code changes here are that in some cases we use
CONFIG_STACKSIZE in non-IRQ related context. In these cases we rename
and move the value local to the code in question.
Fixes: d53ecad92f ("Merge branch 'master' of git://git.denx.de/u-boot-sunxi")
Signed-off-by: Tom Rini <trini@konsulko.com>
Add separate enable/disable controls for driver-model serial. While this
is generally enabled in SPL it may not be in TPL, since serial output can
be obtained with the debug UART with minimal code size.
Signed-off-by: Simon Glass <sjg@chromium.org>
Since TPL often needs to be very very small it may not make sense to
enable driver model. Add an option for this.
This changes brings the 'rock' board under the TPL limit with gcc 4.9.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present we have SPL_ which can be used in Makefiles to select between
normal and SPL CONFIGs like this:
obj-$(CONFIG_$(SPL_)DM) += core/
When TPL is being built, SPL_ has the value 'SPL' which is generally a
good idea since they tend to follow each other. But in extreme situations
we may want to distinugish between SPL and TPL. For example we may not
want to enable CONFIG_DM with TPL.
Add a new SPL_TPL_ variable which is set to either empty (for U-Boot
proper), 'SPL' or 'TPL'. This may prove useful with TPL-specific options.
Signed-off-by: Simon Glass <sjg@chromium.org>
These includes don't seem to be needed now. Drop them. Reserve the
mp.h header for PowerPC for now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: York Sun <york.sun@nxp.com>
This header file is used by three archs. It could be used by all of them
since relocation is a common function. Move it into a generic file.
Signed-off-by: Simon Glass <sjg@chromium.org>
This header file is used by two archs. It could be used by all of them
since it allows the cache to be on during relocation. Move it into a
generic file.
Signed-off-by: Simon Glass <sjg@chromium.org>
We don't need this PPC-specific function in generic code. Move it to
the powerpc directory.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Drop headers which are not used or needed in this file. The compiler.h
header is included by common.h.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
This is an weak function present on all archs so we should have it in the
common header file. Remove it from arch-specific headers and add a
function comment.
Signed-off-by: Simon Glass <sjg@chromium.org>
By making dram_init_banksize() return an error code we can drop the
wrapper. Adjust this and clean up all implementations.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Move the ugly #ifdefs inside the reserve_video() function so we can
collect all this init into one place.
Signed-off-by: Simon Glass <sjg@chromium.org>
The arch-specific details of the cache being off are best handled inside
the reserve_mmu(). This cleans up the init sequence a little.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
CONFIG_ALT_LB_ADDR is really a detail of how this logbuffer is allocated
rather than whether to do it at all. So move the #ifdef into the function.
Signed-off-by: Simon Glass <sjg@chromium.org>
All archs put U-Boot at the bottom of the relocated region. Xtensa does
not, but perhaps not for any good reason. Adjust it to see if things
still work OK.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present we cannot use this function as an init sequence call without a
wrapper, since it returns the RAM size. Adjust it to set the RAM size in
global_data instead, and return 0 on success.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
It looks like only cm5200 and tqm8xx use this feature, so we don't really
need it in generic code. Drop it and have the users access gd->board_type
directly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
This is not used by any board. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Clean up board_f sequence a little
This series tries to remove #ifdefs from the board_f init sequence. It
gets as far as I2C and then we need to discuss whether we can start to
remove the old I2C framework.
I think that ideally each entry in the init sequence should be enabled by
at most one CONFIG, which is in Kconfig and is not arch-specific.
END
Acked-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
At present we misuse print_cpuinfo() do so CPU init on x86. This is done
because it is the next available call after the console is enabled. But
several arches use checkcpu() instead. Despite the horrible name (which
we can fix), it seems a better choice.
Adjust the various x86 CPU implementations to move their init code into
checkcpu() and use print_cpuinfo() only for printing CPU info.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Move these two function calls into checkcpu(), which is called on this
arch immediately after these two.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
We don't need a special hook for sandbox as one of the later ones will do
just as well. We can print error messages about bad options after we
print the banner. In fact, it seems better.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Combine the conditions so this appears in the init list only once.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
More than half of the architectures use this function so let's make them
all use it.
For those which don't actually define it, we can rely on the weak function
in lib/time.c
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
There is no good reason to use a different name on PowerPC. Change it to
timer_init() like the others.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Now that both branches of the #if do the same thing, we can unify them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
We really don't need to have a name like this in the generic init
sequence. Use the generic get_clocks() name so that we can merge these
two at some point.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
We have two chunks of code which depend on this CONFIG options. There is
likely no need to keep them apart, so join them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
While x86 is the only user and this could in principle be moved to
arch_cpu_init() there is some justification for this being a separate
call. It provides a way to handle init which is not CPU-specific, but
must happen before the CPU can be set up.
Rename the function to be more generic.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
There is no need to have this call in the generic init sequence and no
other architecture has needed it in the time it has been there. Move it
into sandbox's private code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
When this board was switched to using more DM drivers we didn't disable
the legacy PCA953X driver. This in turn learn to a build time warning
about implicit functions as i2c.h would not say anything about
'i2c_read' nor 'i2c_write'. But this was not a fatal error as none of
the legacy driver would be linked in either.
Fixes: e389033f72 ("imx: mx6sxsabreauto: enable more dm drivers")
Reviewed-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
The OrangePi PC 2 is a typical SBC with the 64-bit Allwinner H5 SoC.
Add a (64-bit only) defconfig defining the required options to build
the U-Boot proper.
Create a new .dts file for it by including the (32-bit) H3 SoC .dtsi
and changing the differing components accordingly.
This is a preliminary device tree mostly for U-Boot's own sake, it
is expected to be updated once the official DT gets accepted upstream.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
[squash the commits, update the commit message]
Signed-off-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The Allwinner H5 Soc is bascially an H3 with high SRAM and ARMv8 cores.
As the peripherals and the pinmuxing are almost identical, we piggy
back on the shared MACH_SUN8I_H3_H5 config symbol.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores.
To allow sharing the clocks, GPIO and driver code easily, create an
architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol.
Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and
let it be selected by a new shared Kconfig option.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The DRAM controller in the Allwinner H5 SoC is again very similar to
the one in the H3 and A64.
Based on the existing socid parameter, add support for this controller
by reusing the bulk of the code and only deviating where needed.
These new bits set or cleared here and there have been mostly found by
looking at DRAM register dumps after using the H5 boot0 and comparing
them to what we set in the code. So for now it's mostly unclear what
those bits actually mean - hence the missing names and comments.
Also add the delay line parameters taken from the boot0 and libdram
disassembly.
Register setup differences between H5 and H3 are courtesy of Jens Kuske.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Addresses passed on to readl and writel are expected to be of the same
size as a pointer. Change the parameter types of sunxi_spi0_read_data()
to make the compiler happy and allow a warning-free aarch64 compile.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Traditionally Allwinner SoCs have their boot ROM mapped just below 4GB,
while the first SRAM region is mapped at address 0.
With the extended physical memory support of the A80 this was changed,
so the BROM is now at address 0 and the SRAM region starts right behind
this at 64KB. This configuration seems to be called "high SRAM".
Instead of enumerating the SoCs which have copied this configuration,
let's call a spade a spade and introduce a Kconfig option for this setup.
SoCs implementing this (A80, A64 and H5, so far), can then select this
configuration.
Simplify the config header definition on the way.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
For some reason we were pretty conservative when defining the maximum
SPL size for the Allwinner A80(sun9i) SoC.
According to the manual the SRAM A1 is even 40KB, but the BROM
probably still has the 32 KiB load limit. For the sake of simplicity,
merge the SPL memory definitions for the A64 and A80 SoCs, since both
SoC share the BROM/SRAM A1 memory layout.
This helps to further simplify this is in the next patch.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Instead of enumerating all SoC families that need that bit set, let's
just express this more clearly: The SMP bits needs to be set on
SMP capable ARMv7 CPUs. It's much easier in Kconfig to express it the
other way round, so we use ! CPU_IS_UP and ! ARM64.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Some Freescale boards used an extra version of the constant to hold the
Generic Timer frequency. This can easily be covered by the now unified
COUNTER_FREQUENCY constant, so remove this extra variable from those
boards.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Many ARMv8 boards define a constant COUNTER_FREQUENCY to specify the
frequency of the ARM Generic Timer (aka. arch timer).
ARMv7 boards traditionally used CONFIG_TIMER_CLK_FREQ for the same
purpose. It seems useful to unify them.
Since there are less occurences of the latter version, lets convert all
users over to COUNTER_FREQUENCY.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
If we take the liberty to use register r0 to perform our bit set, we
should be nice enough to tell the compiler about it.
Add r0 to the clobber list to avoid potential mayhem.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Jagan Teki <jagan@openedev.com>
This patch replaces SPL_PINCTRL_FULL with SPL_PINCNTRL. It is to avoid removal
of pin control properties in case of SPL_PINCTRL. No impact in case of
SPL_PINCTRL_FULL as it depends on SPL_PINCTRL.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add a test for the correct device removal. Currently two different ways
for device removal are supported:
- Normal device removal via the device_remove() API
- Removal via selective device driver flags (DM_FLAG_ACTIVE_DMA)
This new test "remove_active_dma" adds tests cases for those both ways
of removal. This is done by adding a new test driver, which has this
flag set.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
This patch adds a call to dm_remove_devices_flags() to
announce_and_cleanup() so that drivers that have one of the removal flags
set (e.g. DM_FLAG_ACTIVE_DMA_REMOVE) in their driver struct, may do some
last-stage cleanup before the OS is started.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
The new function dm_remove_devices_flags() is intented for driver specific
last-stage cleanup operations before the OS is started. This patch adds
this functionality and hooks it into the common device_remove()
function.
Drivers wanting to use this feature for some last-stage removal calls,
need to add one of the DM_REMOVE_xx flags to their driver .flags.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds the flags parameter to device_remove() and changes all
calls to this function to provide the default value of DM_REMOVE_NORMAL
for "normal" device removal.
This is in preparation for the driver specific pre-OS (e.g. DMA
cancelling) remove support.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
MiQi is rk3288 based development board with 1 or 2 GB SDRAM, 16 GB eMMC,
micro SD card interface, 4 USB 2.0 ports, HDMI, gigabit Ethernet and
expansion ports.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Eddie Cai <eddie.cai.linux@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
The (shared) rk3399.dtsi had defined the 'rockchip,vbus-gpio'
properties for each USB 3.0 controller.
As the GPIO usage will vary (e.g. one of those GPIOs shuts down one of
the regulators on the RK3399-Q7) between boards, we move this from the
shared dtsi into the device tree file for the EVB board which these
GPIO definitions match.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit adds the baseline defconfig for the RK3399-Q7 (Puma) SoM
(under the name 'puma-rk3399_defconfig') featuring the Rockchip RK3399
in a Qseven compatible module.
This subsumes the following changes:
* defconfig: rk3399: migrate CONFIG_SPL_LIBCOMMON_SUPPORT/CONFIG_SPL_LIBGENERIC_SUPPORT
* defconfig: rk3399-puma: add CONFIG_MMC_DW_ROCKCHIP
* defconfig: rk3399-puma: disable CONFIG_SPL_OF_PLATDATA
* defconfig: rk3399-puma: don't USE_TINY_PRINTF
* defconfig: rk3399-puma: set up CONFIG_SYS_BOARD for the RK3399-Q7
* defconfig: rk3399-puma: enable the multi-image loading via CONFIG_SPL_FIT
* defconfig: rk3399-puma: SPL should be able to boot from MMC/SD card
* defconfig: rk3399-puma: enable GMAC support
* defconfig: rk3399-puma: enable support for SPI and Winbond SPI flash
* defconfig: rk3399-puma: enable SPI as a boot-source in SPL
* defconfig: rk3399-puma: disallow non-FIT images from being loaded
* defconfig: rk3399-puma: rename to puma-rk3399
* rockchip: config: rk3399: update defconfigs and rk3399_common
For the RK3399-Q7, we want a default boot-order of SPI -> MMC -> uSD.
This both follows how the BootROM probes devices and is a sane default
for customers in device-personalisation (e.g. it allows for quick and
easy factory programming of unpersonalised devices using an SD card)
and field usage (with customer devices expected to have their firmware
either in SPI or MMC).
However, when probing multiple interfaces (according to the result
from the board_boot_order function), we need to ensure that only valid
FIT images are considered and disable the fallback to assuming that a
raw (binary-only) U-Boot image is loaded (to avoid hangs/crashes from
jumping to random content loaded from devices that are probed, but
don't contain valid image content).
By disabling the SPL_RAW_IMAGE_SUPPORT and SPL_LEGACY_IMAGE_SUPPORT
options, we ensure that raw images (indistinguishable from random
data) are not considered for booting.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Drop CONFIG_DEBUG_UART_BOARD_INIT:
Signed-off-by: Simon Glass <sjg@chromium.org>
The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399
in a Qseven-compatible form-factor.
These changes add a device-tree describing the board and its
interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card).
This includes the following changes from the original development:
* dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile
* dts: rk3399-puma: add gmac for the RK3399-Q7
This change enables the Gigabit Ethernet support on the RK3399-Q7.
* dts: rk3399-puma: use serial0 for stdout
* dts: rk3399-puma: prepare the sdmmc node for SPL booting
* dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash
The RK3399-Q7 (Puma) unsually (this is a build-time option for
customised boards) has an on-module SPI-flash connected to SPI1.
As of today, this is a Winbond W25Q32DW (32MBit) device.
The SPI5 controller is routed to the Q7 edge connector and provides
general-purpose SPI connectivity for customer base-boards.
With some minor improvements on integration into our outbound tree
- explicitly modelled the SPI flash as 'spiflash' under spi0
[dts: rk3399-puma: explicitly model spi-flash under spi1]
- renamed the aliases to spi0 and spi1 to allow easier use of
commands and legacy (SPL) infrastructure... i.e. the controllers
will be 0 and 1 for 'sf probe', 'sspi', etc.
[dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands]
* dts: rk3399-puma: include SPI in the spl-boot-order property
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
On the RK3399-Q7 we need to enable a number of configuration options
(e.g. CONFIG_SPI_FLASH_WINBND) dependent on Kconfig seeing CONFIG_SPI
and CONFIG_SPI_FLASH active.
To allow for these being defined in Kconfig (e.g. via defconfig) and
to avoid a warning on having the macro defined multiple times, we
remove them from the common header file.
Note that the rk3399-evb does not currently have the rk_spi.c driver
active (i.e. CONFIG_ROCKCHIP_SPI), so there's no change to the
evb-rk3399_defconfig as part of this change.
X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
For the initial validation of the RK3399-Q7 (Puma), the DDR3 has been
clocked at 666MHz (i.e. DDR3-1333) using the same (safe) settings as
used in Rockchip's MiniLoader.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
The RK3399 does not have any boot selection pins and the BootROM probes
the boot interfaces using the following boot-order:
1. SPI
2. eMMC (sdhci in DTS)
3. SD card (sdmmc in DTS)
4. USB loader
For ease of deployment, the SPL stage should mirror the boot order of
the ROM and use the same probing order (assuming that valid images can
be detected by SPL) unless instructed otherwise. The boot-order can
then be configured via the 'u-boot,spl-boot-order' property in the
chosen-node of the DTS.
While this approach is easily extensible to other boards, it is only
implemented for the RK3399 for now, as the large SRAM on the RK3399
makes this easy to fit the needed infrastructure into SPL and our
production setup already runs with DM, OF_CONTROL and BLK in SPL.
The new boot-order property is expected to be used in conjunction with
FIT images (and all legacy image formats disabled via Kconfig).
A boot-sequence with probing and fallthroughs from SPI via eMMC to SD
card (i.e. &spiflash, &sdhci, &sdmmc) has been validated on the RK3399-Q7.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
The Rock is a RK3188 based single board computer by Radxa.
Currently it still relies on the proprietary DDR init and
cannot use the generic SPL, but at least is able to boot
a linux kernel and system up to a regular login prompt.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fix sort order in defconfig, enable CONFIG_SPL_TINY_MEMSET:
Signed-off-by: Simon Glass <sjg@chromium.org>
Most of the time the optimised memset() is what we want. For extreme
situations such as TPL it may be too large. For example on the 'rock'
board, using a simple loop saves a useful 48 bytes. With gcc 4.9 and
the rodata bug, this patch is enough to reduce the TPL image below the
limit.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
At present we sometimes see the following build error when building on a
machine with multiple cores.
+make[2]: *** No rule to make target 'dts/dt.dtb', needed by 'tpl/u-boot-tpl.dtb'. Stop.
Add a dependency to correct this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Commit 3a649407a4 ("arm: Migrate SYS_THUMB_BUILD to Kconfig, introduce
SPL_SYS_THUMB_BUILD") moved the THUMB_BUILD symbols from the header to
Kconfig symbols. With it still defined in the rk3188 header we end up
with a duplicate symbol and compile errors, so fix that.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
The clock driver for the RK3399 mistakenly used (24 * 2^20) where it
should have used (24 * 10^6) in a few calculations.
This commits fixes this.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
The GMAC in the RK3399 is very similar to the RK3288 variant (i.e. it
is a Designware GMAC core and requires similar configuration as the
RK3288 to switch it to RGMII and set up the TX/RX delays for Gigabit).
The key difference is that the register offsets (within the GRF block)
and bit-offsets (within those registers) used to hold the configuration
differ between the various RK32/33 CPUs.
This change refactors the gmac_rockchip.c driver to use a function
table (selected via driver_data) to factor out these differences. Each
function's implementation then matches the underlying processor.
Some collateral changes are needed in the definitions describing the
bits and offsets in the GRF are needed to prefix each set of symbolic
constants with the SoC name to avoid name clashes... and in doing so,
the shifts for masks and constants have been moved into the header
files for readability (and to make it easier to stay below 80 chars).
X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fixed commit message typo s/factor our/factor out/:
Signed-off-by: Simon Glass <sjg@chromium.org>
The Ethernet driver for the RK3288/3399 GMAC makes sure that the clock
is ungated through a call to clk_set_rate(...). Even though nothing
needs to be done on the RK3399 (the clock gates are open and the clock
is external), we need to implement enough support to at least return
success to enable driver probing.
X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Due to differences in the code paths for SPL and non-SPL, some static
constant structures remain unused in each build variant. This raises
warnings with recent GCC versions (we currently use GCC-6.3).
The warnings addressed in this commit (by matching #if conditions for
the variable definition with their uses) are:
* for the SPL build:
drivers/clk/rockchip/clk_rk3399.c:53:29: warning: 'cpll_init_cfg' defined but not used [-Wunused-const-variable=]
static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
^~~~~~~~~~~~~
drivers/clk/rockchip/clk_rk3399.c:52:29: warning: 'gpll_init_cfg' defined but not used [-Wunused-const-variable=]
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
^~~~~~~~~~~~~
* for the non-SPL build:
drivers/clk/rockchip/clk_rk3399.c:54:29: warning: 'ppll_init_cfg' defined but not used [-Wunused-const-variable=]
static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
^~~~~~~~~~~~~
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
To add GMAC (Gigabit Ethernet) support (limited to RGMII only at this
point), we need support for additional pin-configuration. This commit
adds the pinctrl support for GMAC in RGMII signalling mode:
* adds a PERIPH_ID_GMAC and the mapping from IRQ number to PERIPH_ID
* adds the required defines (in the GRF support) for configuring the
GPIOC pins for RGMII
* configures the RGMII pins (in GPIOC) when requested via pinctrl
X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
An earlier upstream change contained an unconditional debug message
which would show up as a message similar to the following in the
U-Boot startup (after the ATF and before the U-Boot banner):
time 159f019, 0
This commit removes this message (instead of making if conditional on
being a debug-build), as it doesn't pertain to any initialisation done
in this file.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
The BootROM of the RK3399 SoC does not initialise the cntfrq_el0 (which
holds the value 0 (zero) on entry into the SPL. This causes the timebase
for U-Boot not to advance (and will cause a hang where a timeout would
be expected... e.g. if something goes wrong during MMC/SD card startup).
This change defines COUNTER_FREQUENCY, which is used by the AArch64 init
code in arch/arm/cpu/armv8/start.S to set up cntfrq_el0 (if necessary).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Designware HDMI controller and phy are used in other SoCs as well. Split
out platform independent code.
DW HDMI has 8 bit registers but they can be represented as 32 bit
registers as well. Add support to select access mode.
EDID reading code use reading by blocks which is not supported by other
SoCs in general. Make it more general using byte by byte approach, which
is also used in Linux driver.
Finally, not all DW HDMI controllers are accompanied with DW HDMI phy.
Support custom phys by making controller code independent from phy code.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Tested-by: Nickey Yang <nickey.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The Cortex-A9 socs rk3066 and rk3188 share the IP but have their own
compatible values, so add them to make the i2c on these platforms accessible.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
The armclk starts in slow mode (24MHz) on the rk3188, which results in U-Boot
startup taking a lot of time (U-Boot itself, but also the rc4 decoding done
in the bootrom).
With default pmic settings we can always reach a safe frequency of 600MHz
which is also the frequency the proprietary loader left the armclk at,
without needing access to the systems pmic.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
The armclk starts in slow mode (24MHz) on the rk3188, which makes the whole
startup take a lot of time. We therefore want to at least move to the safe
600MHz value we can use with default pmic settings.
This is also the freqency the proprietary sdram-init leaves the cpu at.
For boards that have pmic control later in u-boot, we also add the option
to set the maximum frequency of 1.6GHz, if they so desire.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
In the beginning, we did SPL -> TPL -> U-Boot, but after clarification
of the real ordering swapped SPL and TPL.
It seems some renames were forgotten and may confuse future readers, so
also swap these to reflect the actual ordering.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
There was still a static ram value set in the rk3188-board from the
time where we didn't have actual sdram init code.
Now the sdram init leaves the ram information in SYS_REG2 and we can
decode it similarly to the rk3288.
Right now we have two duplicates of that code, which is still ok and
doesn't really count as common code yet, but if we get a third copy
at some point from a newer soc, we should think about moving that to
a more general position.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Right now we're setting the wrong value of 0 as base in the ram_info struct,
which is obviously wrong for the rk3188. So instead set the correct value
we already have in CONFIG_SYS_SDRAM_BASE.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Building sd images for rk3188 requires more steps due to the needed split
into TPL and SPL as loaders. Describe how to build an image for it in a
separate paragraph in the READER.rockchip file.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Commit c67c8c604b ("board_init.c: Always use memset()") dropped the naive
memset alternative from board_init_f_init_reserve.
So activate CONFIG_TPL_LIBGENERIC for that common memset implementation.
We cannot use the ARCH-specific memset, as that would incur 200bytes of
additional TPL size, space we do not have.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The config options for pinctrl on the RK3188, RK3288, RK3328 and
RK3399 previously showed up in menuconfig with the generic string
descriptor "Rockchip pin control driver" requiring one to look through
the help/full description to identify which chip each menu entry was
for.
This change renames each option with the chip-name in the description
string to make it easy to identify the configuration options in
menuconfig.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
To simplify the creation of AArch64 SPL images for the RK3399, we
use the ENABLE_ARM_SOC_BOOT0_HOOK option and prepend 4 bytes of
padding at the start of the text section. This makes it easy for
mkimage to rewrite this word with the 'RK33' boot magic.
This change brings logic to calculate the header size and allocate
the header back in sync. For the RK3399 we now limit the header to
before the payload (i.e. the 'header0' and the padding up to the
actual image) and overwrite the first word (inserted by the
boot0-hook for this purpose) with the 'RK33' magic in-place.
X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
The SPL binary needs to be prefixed with the boot magic ('RK33' for
the RK3399) on the Rockchip platform and starts execution of the
instruction word following immediately after this boot magic.
This poses a challenge for AArch64 (ARMv8) binaries, as the .text
section would need to start on the odd address, violating natural
alignment (and potentially triggering a fault for any code that
tries to access 64bit values embedded in the .text section).
A quick and easy fix is to have the .text section include the 'RK33'
magic and pad it with a boot0 hook to insert 4 bytes of padding at the
start of the section (with the intention of having mkimage overwrite
this padding with the appropriate boot magic). This avoids having to
modify the linker scripts or more complex logic in mkimage.
X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
The RK3399 boot code (running as AArch64) poses a bit of a challenge
for SPL image generation:
* The BootROM will start execution right after the 4-byte header (at
the odd instruction word loaded into SRAM at 0xff8c2004, with the
'RK33' boot magic residing at 0xff8c2000).
* The default padding (during ELF generation) for AArch64 is 0x0,
which is an illegal instruction and the .text section needs to be
naturally aligned (someone might locate a 64bit constant relative
to the section start and unaligned loads trigger a fault for all
privileged modes of an ARMv8)... so we can't simply define the
CONFIG_SPL_TEXT_BASE option to the odd address (0xff8c2004).
* Finally, we don't want to change the values used for padding of
the SPL .text section for all ARMv8 targets to the instruction
word encoding 'nop', as this would affect all padding in this
section and might hide errors that would otherwise quickly trigger
an illegal insn exception.
To deal with this situation, we modify the rkimage generation to
- understand the fact that the RK3399 needs to pad the header to an
8 byte boundary using an AArch64 'nop'
- the necessary logic to adjust the header_size (which controls the
location where the payload is copied into the image) and to insert
this padding (AArch64 insn words are always little-endian) into
the image following the 4-byte header magic.
X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
The RC4 encoding works on full blocks, but the calculation of the
starting offset and size are needlessly complicated by using a
reference value known to be offset into a block by the size of the
header and then correcting for the (hard-coded) size of the header
(i.e. 4 bytes).
We change this over to use the RK_SPL_HDR_START directly (which is
known to be on a block boundary).
X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
we are using mmc alias , so mmc index have been changed.
now mmc dev 0 is emmc and mmc dev 1 is sdmmc.
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
This includes Marvell mvpp2 patches with the ethernet support for the
ARMv8 Armada 7k/8k platforms. The ethernet patches are all acked by Joe
and he is okay with me pushing them via the Marvell tree.
Change the buck8's min-microvolt to 750000.
Whent thor protocol is used, board_usb_init() should be tried to set to
750000. But it was returned -EINVAL, because '750000' too lower than
2850000. (thor command doesn't work fine because of this problem.)
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Trats has the i2c gpio for fuel-gaugge.
This patch s for preparing to use the fuel-gauge.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
These codes are unnecessary, because max8997 should be initialized with
dt-file.
Remove max8997_init() function.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Enable the CONFIG_DM_PMIC and PMIC_MAX8997.
Also use the CONFIG_SYS_I2C_S3C24X0 for using I2C.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Introduce CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK to disable the external clock
loopback and use the internal one on SDMMC3 as per the SDMMC_VENDOR_MISC_CNTRL_0
register's SDMMC_SPARE1 bits being set to 0xfffd according to the TRM.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This patch adds board support for the Toradex Apalis TK1 a computer on
module which can be used on different carrier boards.
The module consists of a Tegra TK1 SoC, a PMIC solution, 2 GB of DDR3L
RAM, a bunch of level shifters, an eMMC, a TMP451 temperature sensor
chip, an I210 gigabit Ethernet controller and a SGTL5000 audio codec.
Furthermore, there is a Kinetis MK20DN512 companion micro controller for
analogue, CAN and resistive touch functionality.
For the sake of ease of use we do not distinguish between different
carrier boards for now as the base module features are deemed
sufficient enough for regular booting.
The following functionality is working so far:
- eMMC boot, environment storage and Toradex factory config block
- Gigabit Ethernet
- MMC/SD cards (both MMC1 as well as SD1 slot)
- USB client/host (dual role OTG port as client e.g. for DFU/UMS or host,
other two ports as host)
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Even though we expect only master core to execute U-Boot code
let's make sure even if for some reason slave cores attempt to
execute U-Boot in parallel with master they get halted very early.
If platform wants it may kick-start slave cores before passing control
to say Linux kernel or any other application that want to see all cores
of SMP SoC up and running.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
In axs103 v1.1 procedure to kick-start slave cores has changed quite a bit
compared t previous implementation.
In particular:
* We used to have a generic START bit for all cores selected by CORE_SEL
mask. But now we don't touch CORE_SEL at all because we have a dedicated
START bit for each core:
bit 0: Core 0 (master)
bit 1: Core 1 (slave)
* Now there's no need to select "manual" mode of core start
Additional challenge for us is how to tell which axs103 firmware we're
dealing with. For now we'll rely on ARC core version which was bumped
from 2.1c to 3.0.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* Rely on default pulse polarity value
* Don't mess with "multicore" value as it doesn't affect execution
In essence we now do a bare minimal stuff:
1) Select HS38x2_1 with CORE_SEL=1 bits
2) Select "manual" core start (via CREG) with START_MODE=0
3) Generate cpu_start pulse with START=1
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This is a preparation work for the support of CONFIG_BLK.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
For consistency, use an accessor to access the private data. Also for the
same reason, rename all priv_data to priv.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The Marvell PHY support is needed espescially for the A7040-DB with the
SGMII port (port 2). As without the marvell PHY driver configuration
for SGMII, ethernet won't work.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The default configuration for the COMPHY-0 port should be 1G, as its
used as 1G SGMII connection. This change is necessary to get the
MAC2 port (SGMII) working on this DB.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
As pointed out by Stefan Chulski, this variable is unused and should be
removed.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Testing shows, that PHY polling needs to be enabled on Armada 7k/8k.
Otherwise ethernet transfers will not work correctly. PHY polling
is enabled per default after reset, so we do not need to specifically
enable it, but this makes it clearer.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to
the Marvell mvpp2 ethernet driver for the missing port 0. This code is
mostly copied from the Marvell U-Boot version and was written by Stefan
Chulski. Please note that only SFI support have been added, as this
is the only interface that this code has been tested with. XAUI and
RXAUI support might follow at a later stage.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to
the Marvell mvpp2 ethernet driver. This code is mostly copied from the
Marvell U-Boot version and was written by Stefan Chulski. Please
note that only RGMII and SGMII support have been added, as these are
the only interfaces that this code has been tested with.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Read the "phy-speed" DT property to differentiate between 1 and 2.5GB
SGMII operations. Please note that its unclear right now, if this
DT property will be accepted in mainline Linux. If not, we need to
revisit this code and change it to use the accepted property.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch does a bit of restructuring of the probe / init functions,
mainly to allow earlier register access as it is needed for the upcoming
GoP (Group of Ports) and NetC (Net Complex) code.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch adds the new PHY interface modes XAUI, RXAUI and SFI that will
be used by the PPv2.2 support in the Marvell mvpp2 ethernet driver.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch adds the PPv2.2 specific FIFO configuration to the mvpp2
driver. The RX FIFO packet data size is changed to the recommended
FIFO sizes. The TX FIFO configuration is newly added.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Currently, the naming of the ethernet ports is not handled correctly in
the multi-CP (Communication Processor) case. On Armada 8k, the slave-CP
also instantiates an ethernet controller with the same device ID's.
This patch now takes this into account and adds the required base-id
so that the slave-CP ethernet devices will be named "mvpp2-3 ...".
This patch also updates my Copyright notice to include 2017 as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Since we've now integrated the A7k/8k support in the mvpp2 ethernet
driver, lets enable the support for both Marvell developments boards.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit adds the description of the PPv2.2 hardware block for the
Marvell Armada 7K and Armada 8K processors, and their corresponding Armada
7040 and 8040 Development boards.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Since Armada 7K/8K is also equipped with a newer version of the MVPP2
ethernet controller, lets enable compilation of this driver for these
platforms.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This fixes problems noticed with the PPv2.2 A7k/8k port, when not all
elements of the descriptors had been cleared before use.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch moves the base_probe function mvpp2_base_probe() from the
MISC driver to the ETH driver. When integrated in the MISC driver,
probe is called too early before the U-Boot ethernet infrastructure
(especially the MDIO / PHY interface) has been initialized. Resulting
in errors in mdio_register().
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
In U-Boot the MDIO / SMI support is integrated in the mvpp2 driver,
currently only supporting the 32bit platforms (Armada 37x). This patch
now adds the A7k/8k PPv2.2 MDIO support to that the phy / mii IF
can be used as well on these platforms.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Now that the mvpp2 driver has been modified to accommodate the support
for PPv2.2, we can finally advertise this support by adding the
appropriate compatible string.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
In PPv2.1, we have a maximum of 8 RXQs per port, with a default of 4
RXQs per port, and we were assigning RXQs 0->3 to the first port, 4->7
to the second port, 8->11 to the third port, etc.
In PPv2.2, we have a maximum of 32 RXQs per port, and we must allocate
RXQs from the range of 32 RXQs available for each port. So port 0 must
use RXQs in the range 0->31, port 1 in the range 32->63, etc.
This commit adapts the mvpp2 to this difference between PPv2.1 and
PPv2.2:
- The constant definition MVPP2_MAX_RXQ is replaced by a new field
'max_port_rxqs' in 'struct mvpp2', which stores the maximum number of
RXQs per port. This field is initialized during ->probe() depending
on the IP version.
- MVPP2_RXQ_TOTAL_NUM is removed, and instead we calculate the total
number of RXQs by multiplying the number of ports by the maximum of
RXQs per port. This was anyway used in only one place.
- In mvpp2_port_probe(), the calculation of port->first_rxq is adjusted
to cope with the different allocation strategy between PPv2.1 and
PPv2.2. Due to this change, the 'next_first_rxq' argument of this
function is no longer needed and is removed.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit adjusts how the MVPP2_ISR_RXQ_GROUP_REG register is
configured, since it changed between PPv2.1 and PPv2.2.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The PPv2.2 unit is connected to an AXI bus on Armada 7K/8K, so this
commit adds the necessary initialization of the AXI bridge.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit handles a few miscellaneous differences between PPv2.1 and
PPv2.2 in different areas, where code done for PPv2.1 doesn't apply for
PPv2.2 or needs to be adjusted (getting the MAC address, disabling PHY
polling, etc.).
Changed by Stefan for U-Boot:
Since mvpp2_port_power_up() has multiple callers in U-Boot, the U-Boot
version of this patch does not remove this function but simply adds the
check for MVPP21 before the mvpp2_port_fc_adv_enable() call.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit adjusts the mvpp2 driver register mapping and access logic
to support PPv2.2, to handle a number of differences.
Due to how the registers are laid out in memory, the Device Tree binding
for the "reg" property is different:
- On PPv2.1, we had a first area for the common registers, and then one
area per port.
- On PPv2.2, we have a first area for the common registers, and a
second area for all the per-ports registers.
In addition, on PPv2.2, the area for the common registers is split into
so-called "address spaces" of 64 KB each. They allow to access the same
registers, but from different CPUs. Hence the introduction of cpu_base[]
in 'struct mvpp2', and the modification of the mvpp2_write() and
mvpp2_read() register accessors. For PPv2.1, the compatibility is
preserved by using an "address space" size of 0.
Changed by Stefan for U-Boot:
Since we don't support multiple CPUs in U-Boot, I've removed all the
code, macros and variables introduced in the Linux patch version for this.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
In PPv2.2, the MVPP2_RXQ_DESC_ADDR_REG and MVPP2_TXQ_DESC_ADDR_REG
registers have a slightly different layout, because they need to contain
a 64-bit address for the RX and TX descriptor arrays. This commit
adjusts those functions accordingly.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit modifies the mvpp2_defaults_set() function to not do the
loopback and FIFO threshold initialization, which are not needed for
PPv2.2.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The MVPP2_RXQ_CONFIG_REG register has a slightly different layout
between PPv2.1 and PPv2.2, so this commit adapts the functions modifying
this register to accommodate for both the PPv2.1 and PPv2.2 cases.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit adjusts the allocation and freeing of BM pools to support
PPv2.2. This involves:
- Checking that the number of buffer pointers is a multiple of 16, as
required by the hardware.
- Adjusting the size of the DMA coherent area allocated for buffer
pointers. Indeed, PPv2.2 needs space for 2 pointers of 64-bits per
buffer, as opposed to 2 pointers of 32-bits per buffer in
PPv2.1. The size in bytes is now stored in a new field of the
mvpp2_bm_pool structure.
- On PPv2.2, getting the physical and virtual address of each buffer
requires reading the MVPP2_BM_ADDR_HIGH_ALLOC to get the high order
bits of those addresses. A new utility function
mvpp2_bm_bufs_get_addrs() is introduced to handle this.
- On PPv2.2, releasing a buffer requires writing the high order 32 bits
of the physical address to MVPP2_BM_PHY_VIRT_HIGH_RLS_REG. We no
longer need to write the virtual address to MVPP2_BM_VIRT_RLS_REG.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit adds the definition of the PPv2.2 HW descriptors, adjusts
the mvpp2_tx_desc and mvpp2_rx_desc structures accordingly, and adapts
the accessors to work on both PPv2.1 and PPv2.2.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Since the format of the HW descriptors is different between PPv2.1 and
PPv2.2, this commit introduces an intermediate union, with for now
only the PPv2.1 descriptors. The bulk of the driver code only
manipulates opaque mvpp2_tx_desc and mvpp2_rx_desc pointers, and the
descriptors can only be accessed and modified through the accessor
functions. A follow-up commit will add the descriptor definitions for
PPv2.2.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
In preparation to the introduction for the support of PPv2.2 in the
mvpp2 driver, this commit adds a hw_version field to the struct
mvpp2, and uses the .data field of the DT match table to fill it in.
Having the MVPP21 and MVPP22 definitions available will allow to start
adding the necessary conditional code to support PPv2.2.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The PPv2.2 IP has a different TX and RX descriptor layout compared to
PPv2.1. In order to prepare for the introduction of PPv2.2 support in
mvpp2, this commit adds accessors for the different fields of the TX
and RX descriptors, and changes the code to use them.
For now, the mvpp2_port argument passed to the accessors is not used,
but it will be used in follow-up to update the descriptor according to
the version of the IP being used.
Apart from the mechanical changes to use the newly introduced
accessors, a few other changes, needed to use the accessors, are made:
- The mvpp2_txq_inc_put() function now takes a mvpp2_port as first
argument, as it is needed to use the accessors.
- Similarly, the mvpp2_bm_cookie_build() gains a mvpp2_port first
argument, for the same reason.
- In mvpp2_rx_error(), instead of accessing the RX descriptor in each
case of the switch, we introduce a local variable to store the
packet size.
- Similarly, in mvpp2_buff_hdr_rx(), we introduce a local "cookie"
variable to store the RX descriptor cookie, rather than accessing
it from the descriptor each time.
- In mvpp2_tx_frag_process() and mvpp2_tx() instead of accessing the
packet size from the TX descriptor, we use the actual value
available in the function, which is used to set the TX descriptor
packet size a few lines before.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
As indicated by Russell King, the mvpp2 driver currently uses a lot
"phys" or "phys_addr" to store what really is a DMA address. This commit
clarifies this by using "dma" or "dma_addr" where appropriate.
This is especially important as we are going to introduce more changes
where the distinction between physical address and DMA address will be
key.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Some more U-Boot specific 64bit support changes, mostly changing u32
to unsigned long.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The mvpp2 is going to be extended to support the Marvell Armada 7K/8K
platform, which is ARM64. As a preparation to this work, this commit
enables building the mvpp2 driver on ARM64, by:
- Adjusting the Kconfig dependency
- Fixing the types used in the driver so that they are 32/64-bits
compliant. We use dma_addr_t for DMA addresses, and unsigned long
for virtual addresses.
It is worth mentioning that after this commit, the driver is for now
still only used on 32-bits platforms, and will only work on 32-bits
platforms.
Changed by Stefan for U-Boot:
Removed the Kconfig change as it does not apply to U-Boot this way.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Some of the MVPP2_PRS_RI_* definitions use the ~(value) syntax, which
doesn't compile nicely on 64-bit. Moreover, those definitions are in
fact unneeded, since they are always used in combination with a bit
mask that ensures only the appropriate bits are modified.
Therefore, such definitions should just be set to 0x0. In addition, as
suggested by Russell King, we change the _MASK definitions to also use
the BIT() macro so that it is clear they are related to the values
defined afterwards.
For example:
#define MVPP2_PRS_RI_L2_CAST_MASK 0x600
#define MVPP2_PRS_RI_L2_UCAST ~(BIT(9) | BIT(10))
#define MVPP2_PRS_RI_L2_MCAST BIT(9)
#define MVPP2_PRS_RI_L2_BCAST BIT(10)
becomes
#define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10))
#define MVPP2_PRS_RI_L2_UCAST 0x0
#define MVPP2_PRS_RI_L2_MCAST BIT(9)
#define MVPP2_PRS_RI_L2_BCAST BIT(10)
Because the values (MVPP2_PRS_RI_L2_UCAST, MVPP2_PRS_RI_L2_MCAST and
MVPP2_PRS_RI_L2_BCAST) are always applied with
MVPP2_PRS_RI_L2_CAST_MASK, and therefore there is no need for
MVPP2_PRS_RI_L2_UCAST to be defined as ~(BIT(9) | BIT(10)).
It fixes the following warnings when building the driver on a 64-bit
platform (which is not possible as of this commit, but will be enabled
in a follow-up commit):
drivers/net/ethernet/marvell/mvpp2.c: In function ‘mvpp2_prs_mac_promisc_set’:
drivers/net/ethernet/marvell/mvpp2.c:524:33: warning: large integer implicitly truncated to unsigned type [-Woverflow]
#define MVPP2_PRS_RI_L2_UCAST ~(BIT(9) | BIT(10))
^
drivers/net/ethernet/marvell/mvpp2.c:1459:33: note: in expansion of macro ‘MVPP2_PRS_RI_L2_UCAST’
mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST,
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The mvpp2_bm_bufs_add() currently creates a fake cookie by calling
mvpp2_bm_cookie_pool_set(), just to be able to call
mvpp2_pool_refill(). But all what mvpp2_pool_refill() does is extract
the pool ID from the cookie, and call mvpp2_bm_pool_put() with this ID.
Instead of doing this convoluted thing, just call mvpp2_bm_pool_put()
directly, since we have the BM pool ID.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
check_cache_range() warns that the top boundaries are not properly
aligned when flushing or invalidating the buffers and make these
operations fail.
This gets rid of the warnings:
CACHE: Misaligned operation at range ...
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The macro GENMASK_ULL needs the BITS_PER_LONG_LONG macro which is
defined in the bitsperlong.h header. Lets include this header as
the upcoming A7k/8k support in the Marvell mvpp2 ethernet driver
uses this macro.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
This commit replaces legacy timer code with usage of arc timer
driver.
It removes arch/arc/lib/time.c file and selects CONFIG_CLK,
CONFIG_TIMER and CONFIG_ARC_TIMER options for all ARC boards by default.
Therefore we remove CONFIG_CLK option from less common axs101 and
axs103 defconfigs.
Also it removes legacy CONFIG_SYS_TIMER_RATE config symbol from
axs10x.h, tb100.h and nsim.h configs files as it is no longer required.
Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
We want to use the same device tree blobs in both Linux and U-Boot for
ARC boards.
Earlier device tree sources in U-Boot were very simplified and hadn't been
updated for quite a long period of time.
So this commit is the first step on the road to unified device tree blobs.
First of all we re-organize device tree sources for AXS10X boards.
As AXS101 and AXS103 boards consist of AXS10X motherboard and AXC001 and
AXC003 cpu tiles respectively we add corresponding device tree source
files: axs10x_mb.dtsi for motherboard, axc001.dtsi and axc003.dtsi for
cpu tiles and axs101.dts and axs103.dts to represent actual boards.
Also we delete axs10x.dts as it is no longer used.
One more important change - we add timer device to ARC skeleton device
tree sources as both ARC700 and ARCHS cores contain such timer.
We add core_clk nodes to abilis_tb100, nsim, axc001 and axc003 device tree
sources as it is referenced via phandle from timer node in common
skeleton.dtsi file.
Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit introduces timer driver for ARC.
ARC timers are configured via ARC AUX registers so we use special
functions to access timer control registers.
This driver allows utilization of either timer0 or timer1
depending on which one is available in real hardware. Essentially
only existing timers should be mentioned in board's Device Tree
description.
Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The gdsys ControlCenter Digital board is based on a Marvell Armada 38x
SOC.
It boots from SPI-Flash but can be configured to boot from SD-card for
factory programming and testing.
On board peripherals include:
- 2 x GbE
- Xilinx Kintex-7 FPGA connected via PCIe
- mSATA
- USB3 host
- Atmel TPM
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
Certain boards come in different variations by way of utilizing daughter
boards, for example. These boards might contain additional chips, which
are added to the main board's busses, e.g. I2C.
The device tree support for such boards would either, quite naturally,
employ the overlay mechanism to add such chips to the tree, or would use
one large default device tree, and delete the devices that are actually
not present.
Regardless of approach, even on the U-Boot level, a modification of the
device tree is a prerequisite to have such modular families of boards
supported properly.
Therefore, we add an option to make the U-Boot device tree (the actual
copy later used by the driver model) writeable, and add a callback
method that allows boards to modify the device tree at an early stage,
at which, hopefully, also the application of device tree overlays will
be possible.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
This board specific command tests for the presence of a specified PCIe
device (via vendor-ID and device-ID). If the device is not detected,
this will get printed. If the device is detected, the board will get
resetted so that an easy loop test can be done. The board will reboot
until the PCIe device is not detected.
Signed-off-by: Stefan Roese <sr@denx.de>
Define a board-specific detection pulse-width array for the SerDes PCIe
interfaces. If not defined in the board code, the default of currently 2
is used. Values from 0...3 are possible (2 bits).
In this case of the theadorable board, PEX interface 0 needs a value
of 0 for the detection pulse width so that the PCIe device (Atheros
WLAN PCIe device) is consistantly detected.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Adam Shobash <adams@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Tests have shown that on some boards the default width of the
configuration pulse for the PEX link detection might lead to
non-established PCIe links (link down). Especially under certain
conditions (higher temperature) and with specific PCIe devices
(in the case on the theadorable board its a Atheros PCIe WLAN
device). To enable a board-specific detection pulse width this weak
array "serdes_pex_pulse_width[4]" is introduced which can be
overwritten if needed by a board-specific version. If the board
code does not provide a non-weak version of this variable, the
default value will be used. So nothing is changed from the
current setup on the supported board.
Many thanks to Adam from Marvell for all his insights here and
his suggestion about testing with a changed detection pulse width.
Signed-off-by: Stefan Roese <sr@denx.de>
Suggested-by: Adam Shobash <adams@marvell.com>
Cc: Adam Shobash <adams@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Remove DM_I2C_COMPAT from the board configurations for
Armada 37xx platform boards for supressing the buid tim
warning.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Bypass XHCI and AHCi board configuration flow on ESPRESSOBin
community board.
The community board does not have i2c expander and USB VBUS
is always on, so the scan for AHCi and USB devices can be
faster without unneded configurations.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Add initial default configuration for Marvell ESPRESSOBin
community board based on Aramda-3720 SoC
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Initial DTS file for Marvell ESPRESSOBin comunity board
based on Armada-3720 SoC.
The Marvell ESPRESSOBin is a tiny board made by Globalscale
and available on KickStarter site. It has dual core Armv8
Marvell SoC (Armada-3720) with 512MB/1GB/2GB DDR3 RAM,
mini-PCIe 2.0 slot, single SATA-3 port, USB 2.0 and USB 3.0
interfaces, Gigabit Ethernet switch with 3 ports, micro-SD
socket and two 46-pin GPIO connectors.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Implement the board-specific network init function for
ESPRESSOBin community board, setting the on-board Topaz
switch port to forward mode and allow network connection
through any of the available Etherenet ports.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Add support for fixed link to NETA driver.
This feature requreed for proper support of SFP modules
and onboard connected devices like Ethernet switches
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Terry Zhou <bjzhou@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Add ability to use board-specific initialization flow
to NETA driver (for instance Ethernet switch bring-up)
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Fix the default pin control values in a board-specific
function on early board init stage.
This fix allows the NETA driver to work in RGMII
mode until the full-featured pin control driver gets
introduced.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Modify the file names and deifinitions relater to Marvell
db-77f3720 board support. Convert these names to more generic
armada-37xx platform for future addition of more boards
based on the same SoC family.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The USB device should linked to VBUS regulator through "vbus-supply"
DTS property.
This patch adds handling for "vbus-supply" property inside the USB
device entry for turning on the VBUS regulator upon the host adapter probe.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Added A8040 dts file for community board MACCHIATIBin.
The patch includes the following features:
AP - Serial console (connected to onboard FTDI usb to serial)
CP0 - PCIe x4, SATA, I2C and 10G KR
(connected to Marvell 3310 10G copper / SFP+ phy)
CP1 - Boot SPI, USB3 host, 2xSATA, 10G KR
(connected to Marvell 3310 10G copper / SFP+ phy),
SGMII connected to onboard 1512 1Gbps copper phy,
and additional SGMII connected to SFP
(default 1Gbps can be configured to 2.5Gbps).
Network interface naming -
egiga0 - CP0 KR
egiga1 - CP1 KR
egiga2 - CP1 RJ45 1Gbps connector (recommended for TFTP boot)
egiga3 - CP1 SFP default 1Gbps and can be modified to 2.5Gbps
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Previously, dtoc could only process the top-level nodes which led to
device nodes in hierarchical trees to be ignored. E.g. the mmc0 node
in the following example would be ignored, as only the soc node was
processed:
/ {
soc {
mmc0 {
/* ... */
};
};
};
This introduces a recursive helper method ScanNode, which is used by
ScanTree to recursively parse the entire tree hierarchy.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
We used to get the address of the optionnal ctrl_mod_mmap register as the
third memory range of the "reg" property. the linux driver moved to use a
syscon instead. In order to keep the DTS as close as possible to that of
linux, we move to using a syscon as well.
If SYSCON is not supported, the driver reverts to the old way of getting
the address from the 3rd memory range
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
In the DTS, the addresses are defined relative to the parent bus. We need
to translate them to get the address as seen by the CPU core.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
commit 2f11cd9121 ("dm: core: Handle global_data moving in SPL")
handles relocation of GD in SPL if spl_init() is called before
board_init_r(). So, uclass_root.next need not be initialized always
and accessing uclass_root.next->prev gives an abort. Update the
uclass_root only if it is available.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The Xenon SDHCI driver just missed the integration of this patch:
git ID 6d0e34bf
mmc: sdhci: Distinguish between base clock and maximum peripheral frequency
With this patch applied, the SDHCI subsystem complains now with this warning
while probing:
sdhci_setup_cfg: Hardware doesn't specify base clock frequency
This patch fixes this issue, by providing the missing host->max_clk
variable to the SDHCI subsystem.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Hu Ziji <huziji@marvell.com>
Cc: Victor Gu <xigu@marvell.com>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
It's redundant to send cmd13 after cmd9 whose response is not R1b. The
card devices will not be busy w/ cmd9.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
This patch adds Intel Tangier eMMC/SDHCI driver.
Intel Tangier SoC contains a hybrid of PCI and non-PCI devices. SDHCI
controller is one of the devices which are *not* on a PCI and, hence,
cannot be enumerated by standard PCI means. This driver, allows for
SDHCI controller on Tangier SoC to work in U-Boot.
Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We don't want pci_mmc to compile every time x86 compiles, only when
there's a platform that needs it. For that reason, we're adding a new
CONFIG_MMC_PCI which platforms can choose to enable.
Suggested-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
This patch fixup iommu-map property on pci node to have a valid
mapping of requester-id to stream-id. The requester-id to stream-id
mapping is based on PCI-LUT table initialization.
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Layerscape Chasis-2 also uses same PCIe controller as Chasis-3
and have similar PCI-Lut.
Signed-off-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
LS1012A is Chassis-2 type SOC and shares same streamid definition.
This patch adds using streamids for ls1012a
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
LS1046A is Chassis-2 type SOC and shares same streamid definition,
this patch adds using streamids for LS1046A.
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Layerscape Chassis-2 have PCIe device, some platform devices and
DPAA1 devices which will use stream-ids for iommu level isolation
as they are behind SMMU.
This patch defines the stream-ids for Chassis-2 devices. DPAA1 is
reserved for future use.
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
LS2080a, LS1088a and LS2088a SOCs are based on Chassis-3 and shared
same stream-id partitioning. This patch rewords the definition to
support all these SOCs.
Also have changes in description about iommu-map property updates
in PCI node.
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The stream ID allocation for Chasis 3.0 devices can be shared among
LS1088, LS2088 and LS2080.
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Add nand_size() function to move the nand size print into initr_nand().
Remove nand size print from nand_init() to allow other function to call
nand_init() without printing nand size.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Add initialization flag to avoid initializing NAND Flash multiple
times, otherwise it will calculate a wrong total size.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
USB requires 100MHz clock. On LS1012A, a dedicated 100MHz is provided
instead of SYSCLK (125MHz). Skipping checking SYSCLK for FDT fixup.
Signed-off-by: Yingxi Yu <yingxi.yu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Fix the offsets of MTD partitions on Nor flash on ls1043ardb,
ls1043aqds and ls1046aqds boards. Delete the rcw, uboot env and fman
partitions. Add user partitions for general usage.
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
LS2088A and its variants have different PCIe node than LS2080A.
The compatible string is updated accordingly.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The LS2088A series SoCs has different physical memory map address and
CCSR registers address against LS2080A series SoCs.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This i2c errata only applies to LS2080A and its variants, namely
LS2080A, LS2085A and LS2088A.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
SOC’s like LS1012A has only one chip select signal for QSPI flash.
Avoid scanning other flash.
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
SerDes information is not necessary to be present in RCWSR29 register.
It may vary from SoC to SoC.
So Avoid RCWSR28 register hard-coding.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
MAC number used per QSGMII is not fixed. It may wary from SoC to SoC.
So move QSGMII wriop_init_dpmac() to SoC file.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Erratum A009635 is valid only for LS2080A SoC and its
personality. Add SoC svr check.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
In EP mode, to enable accesses from the Root Complex, the
CONFIG_READY bit must be set, otherwise any config attempts
from the Root Complex will be returned with config retry
status (CRS).
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
For validating images from uboot (Such as Kernel Image), either keys
from SoC fuses can be used or keys from a verified table of public
keys can be used. The latter feature is called IE Key Extension
Feature.
For Layerscape Chasis 3 based platforms, IE table is validated by
Bootrom and address of this table is written in scratch registers 13
and 14 via PBI commands.
Following are the steps describing usage of this feature:
1) Verify IE Table in ISBC phase using keys stored in fuses.
2) Install IE table. (To be used across verification of multiple
images stored in a static global structure.)
3) Use keys from IE table, to verify further images.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Moved the ifdef into ppa.h and removed the duplicated macros.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Moves sec_init to board_init rather than in misc_init function beacuse
PPA will be initialised in board_init function and for PPA validation
sec_init has to be done prior to PPA init.
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Add header address for PPA to be validated during ESBC phase for LS2080A
platform based on Layescape Chasis 3.
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch allows using i2c commands (e.g. "i2c probe", "i2c md", etc)
without the need to first select the bus number with e.g. "i2c dev 0".
This is the "i2c" command behavior similar to the one from pre DM, where
by default bus 0 was immediately accessible.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This patch updates the way in which psc, sscl and ssch I2C parameters are
calculated to be in sync with v4.9 Linux kernel
SHA1: 69973b830859bc6529a7a0468ba0d80ee5117826
in the ./drivers/i2c/busses/i2c-omap.c
The previous method was causing several issues:
- The internal I2C frequency (after prescaler) was far above recommended
one (7 - 12 MHz [*]) - the current approach brings better noise suppression
(as stated in Linux commit: SHA1: 84bf2c868f3ca996e5bb)
- The values calculated (psc, sscl and ssch) were far from optimal, which
caused on the test platform (AM57xx) the I2C0 SCL signal low time (Fast
Mode) of ~1.0us (the standard requires > 1.3 us).
[*] for AM57xx TRM SPRUHZ6G, Table 24,7
"HS I2C Register Values for Maximum I2C Bit Rates in I2C F/S, I2C HS Modes"
Signed-off-by: Lukasz Majewski <lukma@denx.de>
v4.9 Linux release:
SHA1: 69973b830859bc6529a7a0468ba0d80ee5117826
in the ./drivers/i2c/busses/i2c-omap.c
recommends to use SCLH=5 and SCLL=7 values.
This patch sets them to default.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Normally, this would probably be done by adding devicetree aliases
to the main dtsi file for the lpc32xx and using bus->req_seq instead.
Since we want to have consistent i2c numbering, we cannot force the
bus->req_seq because. If for instance we have 3 buses numbered
from 0 to 2 with i2c0 enabled, i2c1 disabled and i2c2 enabled;
i2c2 can be selected using 'i2c dev 1' and 'i2c dev 2' commands
because a bus can be probed using req_seq or seq interchangeably.
Signed-off-by: Liam Beguin <lbeguin@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Since the lpc32xx i2c driver does not yet support the devicetree bindings,
this structure is also needed by the board file as the hardware description
is done there.
Signed-off-by: Liam Beguin <lbeguin@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
This is part of the prep work for the migration to the driver model.
It will enable the driver to support DM and non-DM configurations
using the same functions.
Signed-off-by: Liam Beguin <lbeguin@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
This is part of the prep work for the migration to the driver model.
Signed-off-by: Liam Beguin <lbeguin@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
This is part of the prep work for the migration to the driver model.
What used to be the probe function is now called probe_chip.
Signed-off-by: Liam Beguin <lbeguin@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
This patch adds a reset controller implementation for STMicroelectronics
STi family SoCs; it allows a group of related reset like controls found
in multiple system configuration registers to be represented by a single
controller device.
Driver code has been mainly extracted from kernel
drivers/reset/sti/reset-stih407.c
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
In the description of function pci_match_one_id(), there are some
problems on arguments list and return value description, so correct
them.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
It is sometimes convenient to know how many and/or which resources are
currently loaded into a TPG, e.g. to test is a flush operation succeeded.
Hence, we add a command that lists the resources of a given type currently
loaded into the TPM.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit 7690be35de ("lib: tpm: Add command to flush resources") added a command
to flush resources from a TPM.
However, a previous development version was accidentially used to generate the
patch, resulting in a non-functional command.
This patch fixes the flush command.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
If we want to load a key into a TPM, we need to know the designated parent
key's handle, so that the TPM is able to insert the key at the correct place in
the key hierarchy.
However, if we want to load a key whose designated parent key we also
previously loaded ourselves, we first need to memorize this parent key's handle
(since the handles for the key are chosen at random when they are inserted into
the TPM). If we are, however, unable to do so, for example if the parent key is
loaded into the TPM during production, and its child key during the actual
boot, we must find a different mechanism to identify the parent key.
To solve this problem, we add a function that allows U-Boot to load a key into
the TPM using their designated parent key's SHA1 hash, and the corresponding
auth data.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Use CONFIG_IS_ENABLED() macro to check whether OF_TRANSLATE is enabled, so
that code block is compiled irrespective of SPL or U-Boot build
and fdt address translation is used.
Signed-off-by: Vignesh R <vigneshr@ti.com>
This patch adds support for having a "fixed-link" to some other MAC
(like some embedded switch-device).
For this purpose we introduce a new phy-driver, called "Fixed PHY".
Fixed PHY works only with CONFIG_DM_ETH enabled, since the fixed-link is
described with a subnode below ethernet interface.
Most ethernet drivers (unfortunately not all are following same scheme
for searching/attaching phys) are calling "phy_connect(...)" for getting
a phy-device.
At this point we link in, we search here for a subnode called "fixed-
link", once found we start phy_device_create(...) with the special phy-
id PHY_FIXED_ID (0xa5a55a5a).
During init the "Fixed PHY" driver has registered with this id and now
gets probed, during probe we get all the details about fixed-link out of
dts, later on the phy reports this values.
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
The Raspberry Pi device tree files since Linux v4.9 have a "ethernet"
alias pointing to the on-board Ethernet device node. However,
U-Boot's fdt_fixup_ethernet() only looks at ethernet aliases ending
in digits.
As the spec doesn't mandate that aliases must end in numbers and there
have been much older uses of an "ethernet" aliases in the wild
(according to Tom Rini), change the code to accept "ethernet" as well.
Without this Linux isn't told of the MAC address provided by the
RPI firmware and the ethernet interface is always assigned a random MAC
address.
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The network mask must be stored in network order when in a
'struct in_addr'.
This fix removes the "gatewayip needed but not set" message on the
console when using a link-local IP setup.
Signed-off-by: Alexandre Messier <amessier@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Apply the proper setting for the reserved bits in SetDes Test and System Mode Control register
to avoid the voltage peak issue while we do the IEEE PHY comformance test
Signed-off-by: Ken Lin <yungching0725@gmail.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Acked-by: Ian Ray <ian.ray@ge.com>
Add the delay (10ms) to ensure the clock is stable and to meet the clock-to-reset(1ms) requirement recommended in the AR8033 datasheet
Signed-off-by: Ken Lin <yungching0725@gmail.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Acked-by: Ian Ray <ian.ray@ge.com>
This patch enables the I2C EEPROM to be probed for a MAC address on the
OLinuXino Lime1 and Lime2 boards. Other boards surely qualify as well
but were not tested yet.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Currently the mac address is programmed directly in _sunxi_emac_eth_init
making it a one time inflexible operation. By moving it into a separate
function, we can now use this more flexibly.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This replaces legacy arch/arc/lib/timer.c implementation and allows us
to describe ARC Timers in Device Tree. Among other things that way we
may properly inherit Timer's clock from CPU's clock s they really run
synchronously.
This commit replaces legacy timer code with usage of arc timer
driver.
It removes arch/arc/lib/time.c file and selects CONFIG_CLK,
CONFIG_TIMER and CONFIG_ARC_TIMER options for all ARC boards by default.
Therefore we remove CONFIG_CLK option from less common axs101 and
axs103 defconfigs.
Also it removes legacy CONFIG_SYS_TIMER_RATE config symbol from
axs10x.h, tb100.h and nsim.h configs files as it is no longer required.
Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
We want to use the same device tree blobs in both Linux and U-Boot for
ARC boards.
Earlier device tree sources in U-Boot were very simplified and hadn't been
updated for quite a long period of time.
So this commit is the first step on the road to unified device tree blobs.
First of all we re-organize device tree sources for AXS10X boards.
As AXS101 and AXS103 boards consist of AXS10X motherboard and AXC001 and
AXC003 cpu tiles respectively we add corresponding device tree source
files: axs10x_mb.dtsi for motherboard, axc001.dtsi and axc003.dtsi for
cpu tiles and axs101.dts and axs103.dts to represent actual boards.
Also we delete axs10x.dts as it is no longer used.
One more important change - we add timer device to ARC skeleton device
tree sources as both ARC700 and ARCHS cores contain such timer.
We add core_clk nodes to abilis_tb100, nsim, axc001 and axc003 device tree
sources as it is referenced via phandle from timer node in common
skeleton.dtsi file.
Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit introduces timer driver for ARC.
ARC timers are configured via ARC AUX registers so we use special
functions to access timer control registers.
This driver allows utilization of either timer0 or timer1
depending on which one is available in real hardware. Essentially
only existing timers should be mentioned in board's Device Tree
description.
Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The gdsys ControlCenter Digital board is based on a Marvell Armada 38x
SOC.
It boots from SPI-Flash but can be configured to boot from SD-card for
factory programming and testing.
On board peripherals include:
- 2 x GbE
- Xilinx Kintex-7 FPGA connected via PCIe
- mSATA
- USB3 host
- Atmel TPM
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
Certain boards come in different variations by way of utilizing daughter
boards, for example. These boards might contain additional chips, which
are added to the main board's busses, e.g. I2C.
The device tree support for such boards would either, quite naturally,
employ the overlay mechanism to add such chips to the tree, or would use
one large default device tree, and delete the devices that are actually
not present.
Regardless of approach, even on the U-Boot level, a modification of the
device tree is a prerequisite to have such modular families of boards
supported properly.
Therefore, we add an option to make the U-Boot device tree (the actual
copy later used by the driver model) writeable, and add a callback
method that allows boards to modify the device tree at an early stage,
at which, hopefully, also the application of device tree overlays will
be possible.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
This board specific command tests for the presence of a specified PCIe
device (via vendor-ID and device-ID). If the device is not detected,
this will get printed. If the device is detected, the board will get
resetted so that an easy loop test can be done. The board will reboot
until the PCIe device is not detected.
Signed-off-by: Stefan Roese <sr@denx.de>
Define a board-specific detection pulse-width array for the SerDes PCIe
interfaces. If not defined in the board code, the default of currently 2
is used. Values from 0...3 are possible (2 bits).
In this case of the theadorable board, PEX interface 0 needs a value
of 0 for the detection pulse width so that the PCIe device (Atheros
WLAN PCIe device) is consistantly detected.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Adam Shobash <adams@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Tests have shown that on some boards the default width of the
configuration pulse for the PEX link detection might lead to
non-established PCIe links (link down). Especially under certain
conditions (higher temperature) and with specific PCIe devices
(in the case on the theadorable board its a Atheros PCIe WLAN
device). To enable a board-specific detection pulse width this weak
array "serdes_pex_pulse_width[4]" is introduced which can be
overwritten if needed by a board-specific version. If the board
code does not provide a non-weak version of this variable, the
default value will be used. So nothing is changed from the
current setup on the supported board.
Many thanks to Adam from Marvell for all his insights here and
his suggestion about testing with a changed detection pulse width.
Signed-off-by: Stefan Roese <sr@denx.de>
Suggested-by: Adam Shobash <adams@marvell.com>
Cc: Adam Shobash <adams@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Remove DM_I2C_COMPAT from the board configurations for
Armada 37xx platform boards for supressing the buid tim
warning.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Bypass XHCI and AHCi board configuration flow on ESPRESSOBin
community board.
The community board does not have i2c expander and USB VBUS
is always on, so the scan for AHCi and USB devices can be
faster without unneded configurations.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Add initial default configuration for Marvell ESPRESSOBin
community board based on Aramda-3720 SoC
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Initial DTS file for Marvell ESPRESSOBin comunity board
based on Armada-3720 SoC.
The Marvell ESPRESSOBin is a tiny board made by Globalscale
and available on KickStarter site. It has dual core Armv8
Marvell SoC (Armada-3720) with 512MB/1GB/2GB DDR3 RAM,
mini-PCIe 2.0 slot, single SATA-3 port, USB 2.0 and USB 3.0
interfaces, Gigabit Ethernet switch with 3 ports, micro-SD
socket and two 46-pin GPIO connectors.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Implement the board-specific network init function for
ESPRESSOBin community board, setting the on-board Topaz
switch port to forward mode and allow network connection
through any of the available Etherenet ports.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Add support for fixed link to NETA driver.
This feature requreed for proper support of SFP modules
and onboard connected devices like Ethernet switches
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Terry Zhou <bjzhou@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Add ability to use board-specific initialization flow
to NETA driver (for instance Ethernet switch bring-up)
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Fix the default pin control values in a board-specific
function on early board init stage.
This fix allows the NETA driver to work in RGMII
mode until the full-featured pin control driver gets
introduced.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Modify the file names and deifinitions relater to Marvell
db-77f3720 board support. Convert these names to more generic
armada-37xx platform for future addition of more boards
based on the same SoC family.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The USB device should linked to VBUS regulator through "vbus-supply"
DTS property.
This patch adds handling for "vbus-supply" property inside the USB
device entry for turning on the VBUS regulator upon the host adapter probe.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Added A8040 dts file for community board MACCHIATIBin.
The patch includes the following features:
AP - Serial console (connected to onboard FTDI usb to serial)
CP0 - PCIe x4, SATA, I2C and 10G KR
(connected to Marvell 3310 10G copper / SFP+ phy)
CP1 - Boot SPI, USB3 host, 2xSATA, 10G KR
(connected to Marvell 3310 10G copper / SFP+ phy),
SGMII connected to onboard 1512 1Gbps copper phy,
and additional SGMII connected to SFP
(default 1Gbps can be configured to 2.5Gbps).
Network interface naming -
egiga0 - CP0 KR
egiga1 - CP1 KR
egiga2 - CP1 RJ45 1Gbps connector (recommended for TFTP boot)
egiga3 - CP1 SFP default 1Gbps and can be modified to 2.5Gbps
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Previously, dtoc could only process the top-level nodes which led to
device nodes in hierarchical trees to be ignored. E.g. the mmc0 node
in the following example would be ignored, as only the soc node was
processed:
/ {
soc {
mmc0 {
/* ... */
};
};
};
This introduces a recursive helper method ScanNode, which is used by
ScanTree to recursively parse the entire tree hierarchy.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
We used to get the address of the optionnal ctrl_mod_mmap register as the
third memory range of the "reg" property. the linux driver moved to use a
syscon instead. In order to keep the DTS as close as possible to that of
linux, we move to using a syscon as well.
If SYSCON is not supported, the driver reverts to the old way of getting
the address from the 3rd memory range
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
In the DTS, the addresses are defined relative to the parent bus. We need
to translate them to get the address as seen by the CPU core.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
commit 2f11cd9121 ("dm: core: Handle global_data moving in SPL")
handles relocation of GD in SPL if spl_init() is called before
board_init_r(). So, uclass_root.next need not be initialized always
and accessing uclass_root.next->prev gives an abort. Update the
uclass_root only if it is available.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The Xenon SDHCI driver just missed the integration of this patch:
git ID 6d0e34bf
mmc: sdhci: Distinguish between base clock and maximum peripheral frequency
With this patch applied, the SDHCI subsystem complains now with this warning
while probing:
sdhci_setup_cfg: Hardware doesn't specify base clock frequency
This patch fixes this issue, by providing the missing host->max_clk
variable to the SDHCI subsystem.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Hu Ziji <huziji@marvell.com>
Cc: Victor Gu <xigu@marvell.com>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
It's redundant to send cmd13 after cmd9 whose response is not R1b. The
card devices will not be busy w/ cmd9.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
This patch adds Intel Tangier eMMC/SDHCI driver.
Intel Tangier SoC contains a hybrid of PCI and non-PCI devices. SDHCI
controller is one of the devices which are *not* on a PCI and, hence,
cannot be enumerated by standard PCI means. This driver, allows for
SDHCI controller on Tangier SoC to work in U-Boot.
Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We don't want pci_mmc to compile every time x86 compiles, only when
there's a platform that needs it. For that reason, we're adding a new
CONFIG_MMC_PCI which platforms can choose to enable.
Suggested-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Enable DM_I2C/SPI/ETH for all AM43XX based boards.
Enable it using imply keyword so that a user can
disable this when not needed.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add u-boot specific dtsi for am43xx-gp-evm so
that it will be used for SPL.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add u-boot specific dtsi so that this will be
included automatically while building dts.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
To make SPL_OF_CONTROL work on OMAP2+ SoCs, _image_binary_end must be
defined in the linker script along with CONFIG_SPL_SEPARATE_BSS.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Calls to IS_ENABLED() on a non-y/n option will always be false, even
when set. We can correct this by adding a new bool value that is set
based on the conditions required for SPL_STACK_R_MALLOC_SIMPLE_LEN to be
set instead.
Fixes: 340f418acd ("spl: Add spl_early_init()")
Reported-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
Changes in v2:
- Fix thinko pointed out by Lokesh
Add support for the Broadcom Northstar2 SoC and SVK (bcm958712k). The
BCM5871X is a series of quad-core 64-bit 2GHz ARMv8 Cortex-A57
processors targeting a broad range of networking applications.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
When building u-boot tools in cross-build environment CFLAGS environment
variable set up for target is taken into an account when building code
for host. Make it empty on invocation of python.
This fixes the following build errors when cross-compiling for xtensa:
cc1: error: unrecognized command line option "-mlongcalls"
cc1: error: unrecognized command line option "-mauto-litpools"
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
The CAAM in IMX parts doesn't support public key hardware acceleration
(PKHA), so don't use RSA_FREESCALE_EXP. If you try to use it on IMX
(assuming you have the clocks enabled first) you will get back an
"Invalid KEY Command" error since PKHA isn't a valid key destination for
these parts.
Signed-off-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Currently, AM43xx just re-uses the version strings from AM33xx which is
wrong; the actual values for AM43xx are different. Fix this by adding
a separate version string array for AM43xx and use this instead.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reported-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
* Add note that execution needs Python development package installed
* Standardize on upper case "FIT", "FDT" as necessary for clarity
* Fix "tempoerary", "linex" typos
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
This adds documentation on the u-boot,efi-partition-entries-offset
property (which overrides CONFIG_EFI_PARTITION_ENTRIES_OFF, if
present).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This moves the description of the /config node from README.fdt-control
into a separate file doc/device-tree-bindings/config.txt.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Some architectures require their SPL loader at a fixed address within
the first 16KB of the disk. To avoid an overlap with the partition
entries of the EFI partition table, the first safe offset (in bytes,
from the start of the device) for the entries can be set through
CONFIG_EFI_PARTITION_ENTRIES_OFF (via Kconfig)
When formatting a device with an EFI partition table, we may need to
leave a gap between the GPT header (always in LBA 1) and the partition
entries. The GPT header already contains a field to specify the
on-disk location, which has so far always been set to LBA 2. With this
change, a configurable offset will be translated into a LBA address
indicating where to put the entries.
Now also allows an override via device-tree using a config-node (see
doc/device-tree-bindings/config.txt for documentation).
Tested (exporting an internal MMC formatted with this) against Linux,
MacOS X and Windows.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: __maybe_unused on config_offset to avoid warning]
Signed-off-by: Tom Rini <trini@konsulko.com>
If the ethernet address environment is set with a valid
ethernet address prevent overriding it as it is most likely
set by the user and he/she doesn't want board code to
automatically override it whatsoever.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
PRU ethernet MAC address range is present in the
board EEPROM. Parse it and setup eth?addr
environment variables.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
In stead of defining the board EEPROM address in the board headers
let's define them in the board config files and make them
configurable by Kconfig.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
AM571x IDK and AM572x IDK have optional LCD Kits that can be purchased.
These can be one of OSD101T2045 or the newer OSD101T2587. The LCD panel
itself has no registers that can be used to identify the panel, however,
the touchscreen controllers on the panels are different.
Hence to ease user experience, we can use the touch screen controller's
ID information to detect what kind of panel we use and select the
appropriate kernel dtb for the platform configuration.
NOTE: AM572x IDK default configuration is for LCD Connectivity, however
the AM571x IDK has a jumper (J51) that needs to be mounted for the IDK
to operate with LCD (Vs two PRUSS ethernet port option).
Touchscreen ID information is documented in:
http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Use the same convention that was used for ICSS1 Ethernet
- If pin is output, set as PIN_OUTPUT
- If pin is input and external pull resistor present set as PIN_INPUT
- If pin is input and external pull resistor absent, set pull to same
as that of the external PHY's internall pull.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
The board can support either ICSS1 Ethernet ports or LCD
based on J51 jumper. Factory default is ICSS1 Ethernet ports
(i.e. Jumper not populated).
Use the GPIO to detect the jumper setting and configure the
pinmux accordingly. Also select the right DT blob based on
the chosen configuration.
J51 absent -> ICSS1 Ethernet, no LCD on VOUT -> am571x-idk.dtb
J51 present -> LCD on VOUT, no ICSS1 Ethernet -> am571x-idk-lcd-osd.dtb
At present we only support the assume it is the Legacy LCD.
LCD detection mechanism needs to be added later to differentiate
between legacy vs new LCD.
For ICSS1 Ethernet pins use the following convention to set the pinmux
as PMT data is not yet finalized.
- If pin is output, set as PIN_OUTPUT
- If pin is input and external pull resistor present set as PIN_INPUT
- If pin is input and external pull resistor absent, set pull to same
as that of the external PHY's internall pull.
- Do not use SLEW_CONTROLon any pin.
Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Keystone and OMAP platforms will need this to set ethernet
MAC addresses from board EEPROM.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Scratch space can be used for features such as board detection. Define
an area within SRAM that can be used for this purpose.
[rogerq@ti.com] Rename EEPROM macro
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Non OMAP platforms i.e. Keystone will also need to use the board
EEPROM helpers so let's make the macro platform independent.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
GPIO_TO_PIN(bank, bank_gpio) returns the GPIO index
from the GPIO bank number and bank's GPIO offset number.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Enable more DM drivers. The imx I2C/MMC DM drivers needs DM_GPIO
enabled. So needs to enable them together.
DM FEC and SPI are not enabled, but they use gpio in board code.
So use gpio_request first to request the gpio, because DM_GPIO
is enabled.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Introduce device tree support.
dts from kernel commit c4f3f22edd Merge tag 'linux-kselftest-4.11-rc1'
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
- The catch-all i.MX6 job has been exceeding the time limit again so
split this up further. We now have an i.MX6 job and an
everything-else job.
- The logic we use to say "Freescale and AArch64" can be more clearly
expressed with '&' rather than excluding various other things, so
clear that up.
Signed-off-by: Tom Rini <trini@konsulko.com>
To keep a consistent MMC device mapping in SPL and in u-boot, let's
register the MMC controllers the same way in u-boot and in the SPL.
In terms of boot time, it doesn't hurt to register more controllers than
needed because the MMC device is initialized only prior being accessed for
the first time.
Having the same device mapping in SPL and u-boot allows us to use the
environment in SPL whatever the MMC boot device.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Move Freescale/NXP Vybrid to a standard arch/board approach, similar
to what has been done to i.MX 6 earlier in commit 89ebc82137 ("ARM:
mx6: move to a standard arch/board approach").
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Use two separate partitions for the two firmware instances. Also
resize them to be of the same size which also makes the start of
the UBI partition nicely aligned to 0x400000.
In order to detect the new MTD layout and whether we run a U-Boot
with the new BCB format or not, introduce a variable called
"updlevel" which we can use in update/upgrade scripts.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
Use device-tree fixup to communicate the MTD partitions to the
kernel. Remove mtdparts from the kernel command line.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Implement board level USB PHY mode callback. On USB OTG Port 1
the Colibri standard foresees GPIO USBC_DET to decide whether the
port should run in Host or Device mode.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Limit memory used for relocation of FDT or initrd. This is
required to make sure that relocated artifacts are within lowmem.
If fdt_high or initrd_high are not set, U-Boot automatically
relocates artifacts to the end of memory. But this area won't
be part of lowmem and hence will not be accessible by the kernel
during early boot.
With VM split set to 2G/2G (i.MX default), only the 2GB Apalis
iMX6 is affected by that issue. With VM split set to 3G/1G (ARM
default) also modules with 1GB of memory are affected. With the
latter the amount of lowmem will be 760MiB.
The value must also not exceed available memory! Use a safe value
of 512MiB for Apalis and 256MiB for Colibri.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Device tree overlays might prove useful in the future, enable it
by default on all Toradex modules.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
All modules use the common g_dnl_bind_fixup implementaton which
calculates the PID according to product id (read from the config
block) plus offset of 0x4000. In case there is no config block
support (e.g. SPL) or in case the config block is not readable,
fall back to a generic product id (product id 0, which can be
interpreted as "Unknown Module").
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
According to the MX7D fuse map the following speed grades are available:
800 MHz
500 MHz
1000 MHz
1200 MHz
So simply return the real frequency that corresponds to the speed grade.
With this change we see on boot:
CPU: Freescale i.MX7D rev1.2 1000 MHz (running at 792 MHz)
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
According to the MX7D fuse map the speed grade of the parts, which
return '1' is 500MHz instead of 850MHz, so fix it accordingly.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
This is needed to make the UMS command work again as it fails with the
following error:
BIOS> ums 0 mmc 0
UMS: LUN 0, dev 0, hwpart 0, sector 0x0, count 0x748000
g_dnl_register: failed!, error: -19
ERROR: g_dnl_register failed
at cmd/usb_mass_storage.c:179/do_usb_mass_storage()
That's because usb_setup_ehci_gadget() function is looking for the usb
device using the req_sed number.
This change makes the usb device have a req_seq number and the UMS
command work again:
BIOS> ums 0 mmc 0
UMS: LUN 0, dev 0, hwpart 0, sector 0x0, count 0x748000
CTRL+C - Operation aborted
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
OPOS6UL is an i.MX6UL based SoM with 256MB RAM, 4GB eMMC and an ethernet
phy. OPOS6ULDev is carrier board for the OPOS6UL.
U-Boot SPL 2017.03-rc3-00002-g5085c26 (Mar 07 2017 - 09:48:09)
Trying to boot from MMC1
U-Boot 2017.03-rc3-00002-g5085c26 (Mar 07 2017 - 09:48:09 +0100)
CPU: Freescale i.MX6UL rev1.0 528 MHz (running at 396 MHz)
CPU: Industrial temperature grade (-40C to 105C) at 40C
Reset cause: POR
Model: Armadeus Systems OPOS6UL SoM on OPOS6ULDev board
DRAM: 256 MiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
Video: 800x480x18
In: serial
Out: serial
Err: serial
Net: FEC [PRIME]
Hit any key to stop autoboot: 0
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Today, we have cases where we wish to build all of U-Boot in Thumb2 mode for
various reasons. We also have cases where we only build SPL in Thumb2 mode due
to size constraints and wish to build the rest of the system in ARM mode. So
in this migration we introduce a new symbol as well, SPL_SYS_THUMB_BUILD to
control if we build everything or just SPL (or in theory, just U-Boot) in
Thumb2 mode.
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Non-FIT SPL image loading support should be disabled for TI secure
devices as the image handlers for those image types do not follow
our secure boot flow.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add a Kconfig option that enables Legacy image support, this allows
boards to explicitly disable this, for instance when needed for
security reasons.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Move to common/spl/Kconfig]
Signed-off-by: Tom Rini <trini@konsulko.com>
CONFIG_SPL_ABORT_ON_RAW_IMAGE causes SPL to abort and move on when it
encounters RAW images, express this same functionality as a positive
option enabling support for RAW images: CONFIG_SPL_RAW_IMAGE_SUPPORT
Also move uses of this to defconfigs.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Rework Kconfig logic a little, move to common/spl/Kconfig]
Signed-off-by: Tom Rini <trini@konsulko.com>
This includes support for rk3188 from Heiko Stübner and and rk3328 from
Kever Yang. Also included is SPL support for rk3399 and a fix for
rk3288 to get it booting again (spl_early_init()).
This driver uses the same pin control binding as that of linux, binding
document of this patch is copied from linux. One addition done is for
GPIO input and output mode configuration which was missing.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Before clock driver availability it was required to enable usart1 clock
for serial init but now with clock driver is taking care of usart1 clock.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
add basic clock driver support for stm32f7 to enable clocks required by
the peripherals.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds device tree support for stm32f7 serial driver & removes serial
platform data structure.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch cleans the code by using instructions allowed for armv7m as well as
other Arm archs.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
We only support cores that do Thumb-1 or later. So we add a comment to
explain this and remove the architecture test.
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Mans Rullgard <mans@mansr.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Change GPT UUID string format from UUID to GUID per specification.
Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
itest shell command doesn't work correctly in long format when
doing comparaison due to wrong mask value calculus that overflow
on 32 bits values.
Signed-off-by: Sebastien Colleur <sebastienx.colleur@intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Boards with an apparent need for the md5sum command had the connected
config symbol defined in their board header file.
Move this over to the respective defconfig files now that md5sum is
configured via Kconfig.
(This is a manual effort, which differs from moveconfig.py, not sure
who is right here. Boards except sandbox loose the md5sum command with
moveconfig.py, though it was explicitly mentioned in their config.h's)
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: migrate stih410-b2260]
Signed-off-by: Tom Rini <trini@konsulko.com>
FIT images require MD5 support to verify image checksums. So far this
was expressed by defining a CPP symbol in image.h. Since MD5 is now a
first class Kconfig citizen, express that in Kconfig instead.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
So far CONFIG_MD5SUM would need to be set by a board's include file.
Since the command is really generic, move it over to Kconfig to allow
it to be defined by either a board's defconfig, menuconfig or some
config snippet merged via mergeconfig.sh.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit 19a5944fcd ("mvgbe: remove setting of ethaddr within the
driver") removed the usage of get_random_hex() from the mvgbe driver
about six years ago. However the prototype of that function survived
till today in some kirkwood header file.
Remove that prototype and the CONFIG_MD5 dependency triggered by that.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
This adds support for TQMa6DL using i.MX6DL and 1GiB DRAM
Since The module will use the same devicetree, we patch
the ram size in ft_board_setup.
Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
We have a Kconfig name for the module types. Let's Use it.
Some feature selections and configurations are based on the
module. Module selection selects the CPU type.
Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
Add board_mmc_get_env_dev
Switch the mmc env based on the mmc devno, instead of separately
defining a config item in include/configs using board_mmc_get_env_dev
- devno 0: sd/esd
- devno 1: mmc/emmc
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Boot from eMMC:
--------------
U-Boot SPL 2017.01-00318-g8e243f8 (Jan 26 2017 - 11:53:21)
Trying to boot from MMC2
U-Boot 2017.01-00318-g8e243f8 (Jan 26 2017 - 11:53:21 +0100)
CPU: Freescale i.MX6D rev1.2 at 792 MHz
Reset cause: POR
Model: Engicam i.CoreM6 Quad/Dual RQS Starter Kit
DRAM: 512 MiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
switch to partitions #0, OK
mmc1(part 0) is current device
Net: No ethernet found.
Hit any key to stop autoboot: 0
Booting from mmc ...
switch to partitions #0, OK
mmc1(part 0) is current device
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Since the CS are not in use, do not map them. User of starterkit
mainboard is free to use them otherwise. When using these pins later
in the OS for instance as GPIO IRQ pin, they need to be input.
Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
The current driver stength is too high, leading to spec violations
on the falling edge. Fix it with values from HW
Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
SPL mmc device index is get based on the boot device, like
- BOOT_DEVICE_MMC1 for mmc device 0
- BOOT_DEVICE_MMC2 for mmc device 1
Currently BOOT_DEVICE_MMC1 is setting both SD/eSD and MMC/eMMC
boot devices in i.MX, So u-boot is loading from mmc device 0 even
"if the board booting from SD/eSD or MMC/eMMC"
So, this patch set BOOT_DEVICE_MMC2 for MMC/eMMC so for MMC/eMMC
the u-boot is loading from mmc device 1 and the board file need to
take care if the board have different mmc device order intialization.
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Add board_mmc_get_env_dev
Switch the mmc env based on the mmc devno, instead of separately
defining a config item in include/configs using board_mmc_get_env_dev
- devno 0: sd/esd
- devno 1: mmc/emmc
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Let the runtime code can set the mmcdev and mmcroot based
on the devno using mmc_get_env_dev instead of defining
separately in build-time configs using mmc_late_init func.
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Add runtime, modeboot env which is setting mmcboot, or
nandboot based on the bootdevice so-that conditional
macros b/w MMC and NAND for CONFIG_BOOTCOMMAND should
be avoided in config files.
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
SPL mmc device index is get based on the boot device, like
- BOOT_DEVICE_MMC1 for mmc device 0
- BOOT_DEVICE_MMC2 for mmc device 1
Currently BOOT_DEVICE_MMC1 is setting both SD/eSD and MMC/eMMC
boot devices in i.MX, So u-boot is loading from mmc device 0 even
"if the board booting from SD/eSD or MMC/eMMC"
So, this patch set BOOT_DEVICE_MMC2 for MMC/eMMC so for MMC/eMMC
the u-boot is loading from mmc device 1 and the board file need to
take care if the board have different mmc device order intialization.
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Instead of initializing 'struct src' to SRC_BASE_ADDR on
every function better to have global define macro.
Reviewed by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@openedev.com>
Use meaningful macros IMX6_BMODE_*, instead of numerical
number in boot mode detection code.
Cc: Tim Harvey <tharvey@gateworks.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@openedev.com>
BOOT_CFG1[7:4] the NAND boot mode selection is done
only when BOOT_CFG1[7] is 1 hence update the NAND
boot mode detection bit case. This information available
on Table 8-11. NAND Boot eFUSE Descriptions, from IMX6DQRM.
Cc: Tim Harvey <tharvey@gateworks.com>
Reviewed by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@openedev.com>
For i.MX6, the bootmode determine code is part of spl_boot_device,
but there is might be a possibility for other part the code need to
check the desired boot mode for adding new functionalities like
modeboot env variable, or changing boot order etc.
So introduced imx6_src_get_boot_mode which actually reading the
boot mode register for desired modes.
More cleanup will be add in future patches.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Boot from MMC:
-------------
U-Boot SPL 2017.01-rc2-gba3c151-dirty (Jan 02 2017 - 16:59:33)
Trying to boot from MMC1
U-Boot 2017.01-rc2-gba3c151-dirty (Jan 02 2017 - 16:59:33 +0100)
CPU: Freescale i.MX6UL rev1.1 528 MHz (running at 396 MHz)
CPU: Industrial temperature grade (-40C to 105C) at 33C
Reset cause: POR
Model: Engicam Is.IoT MX6UL Starterkit
DRAM: 512 MiB
MMC: FSL_SDHC: 0
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot: 0
isiotmx6ul>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Enable MMC support.
The fsl sdhc driver needs regulator to enable power, so enable
regulator support.
And bootcmd and more env.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Add compatible property for i.MX7ULP.
Add a weak init_usdhc_clk function, i.MX7ULP use this to init the clock.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by : Stefano Babic <sbabic@denx.de>
Add CAAM clock functions, SEC_CONFIG[1] fuse checking, and default CSF
size for HAB support boot on mx7ulp.
Users need to uncomment the CONFIG_SECURE_BOOT in mx7ulp_evk.h to build
secure uboot.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by : Stefano Babic <sbabic@denx.de>
Drop CONFIG_LPUART_32B_REG.
Move the register structure to a common file include/fsl_lpuart.h
Define lpuart_serial_platdata structure which includes the reg base and flags.
For 32Bit register access, use lpuart_read32/lpuart_write32 which handles
big/little endian.
For 8Bit register access, still use the orignal code.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by : Stefano Babic <sbabic@denx.de>
Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Shaohui Xie <Shaohui.Xie@nxp.com>
Cc: Alison Wang <b18965@freescale.com>
Add lpi2c driver for i.MX7ULP.
Need to enable the two options to use this driver:
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Heiko Schocher <hs@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Add i.MX7ULP pinctrl driver.
Select CONFIG_PINCTRL_IMX7ULP to use this driver.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by : Stefano Babic <sbabic@denx.de>
This driver implements the HW WATCHDOG functions. Which needs
to set CONFIG_HW_WATCHDOG to use them. This is disabled by default for
mx7ulp.
Use watchdog for reset cpu. Implement this in the driver.
Need to define CONFIG_ULP_WATCHDOG to build it.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Add the iomux pins header file from iomux tool team. Change the IOMUXC0 pins
to add IOMUX_CONFIG_MPORTS flags.
Note: The IOMUXC0 offset provided in this file is from 0xD000, this is not
aligned with IOMUXC0 base address. We have adjusted the IOMUXC0 base address
to aligin with it.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Update the mxc_ocotp driver to support i.MX7ULP.
The read/write sequence has some changes due to
PDN and OUT_STATUS registers added and TIME register is
removed. Also update the bank size and number.
Add is_mx7ulp macro in sys_proto.h
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by : Stefano Babic <sbabic@denx.de>
Add the imx_rgpio2p driver for Rapid GPIO2P controllers on i.MX7ULP.
Have added all ports on RGPIO2P_0 and RGPIO2P_1.
The configurations CONFIG_IMX_RGPIO2P and CONFIG_DM_GPIO must be set
to y to enable the drivers.
To use the GPIO function, the IBE and OBE needs to set in IOMUXC.
We did not set the bits in driver, but leave them to IOMUXC settings
of the GPIO pins. User should use IMX_GPIO_NR to generate the GPIO number
for gpio APIs access.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by : Stefano Babic <sbabic@denx.de>
Implement the i2c clock enable and get function for mx7ulp. These
functions are required by imx_lpi2c driver.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Implement soc level functions to get cpu rev, reset cause, enable cache,
etc. We will disable the wdog and init clocks in s_init at very early u-boot
phase.
Since the we are seeking the way to get chip id for mx7ulp, the get_cpu_rev
is hard coded to a fixed value. This may change in future.
Reuse some code in imx-common.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Add a clock framework to support SCG1/PCC2/PCC3 for A7 to support get/set
clock source, divider, clock rate and parent source.
Users need to include pcc.h to use the APIs to for peripherals clock. Each
peripheral clock is defined in enum pcc_clk type.
SCG relevants APIs are defined in scg.h which supports clock rate get, PLL/PFD
enablement and settings, and all SCG clock initialization. User need use enum
scg_clk to access each clock source.
In clock.c, we initialize necessary clocks at u-boot s_init and implement the
clock functions used by driver modules to operate clocks dynamically.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Add a new driver under ULP directory to support its IOMUXC
controllers. The ULP has two IOMUXC, the IOMUXC0 is used
for M4 domain, while IOMUXC1 is for A7. We set IOMUXC1 as
the default IOMUX in this driver. Any pins in IOMUXC0 needs
to configure with IOMUX_CONFIG_MPORTS in its mux_mode field.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by : Stefano Babic <sbabic@denx.de>
Add imx-regs.h for i.MX7ULP registers addresses definitions and some
registers structures.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by : Stefano Babic <sbabic@denx.de>
i.MX7ULP is a new series SoC which has different architecture
from previous i.MX platforms. Create a new cpu folder for it,
and add it to Kconfig.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by : Stefano Babic <sbabic@denx.de>
Despite the comment in the code, CSC unit is never used. According to
the only public description of DW HDMI controller (i.MX6 manual), CSC
unit is bypassed in MC_FLOWCTRL register and then actually powered
down in MC_CLKDIS register.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
Function hdmi_lookup_n_cts() is feed with clock in Hz, which gets
compared with clocks in kHz. Fix that by converting all clocks to Hz.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
RK3288 using the dwc2 USB host controller, enable it and other usb host
funtion like storage and ethernet.
Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tinker board have a usb host. add dts node to provide power supply.
Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit e856bdcfb4 ("flash: complete CONFIG_SYS_NO_FLASH move with renaming")
obsoleted the CONFIG_SYS_NO_FLASH option, which still is in our
rk3188_common.h header, resulting in warnings like
The following new ad-hoc CONFIG options were detected:
CONFIG_SYS_NO_FLASH
So also drop it from the rk3188 header.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Documentation says that we're returning true/false, not 1/0 so adapt
the function to return actual booleans.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
At current, only firefly and rock2 have network enabled.
Let's enable other boards.
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Enable board config for evb-rk3328.
SDcard and eMMC boot is OK in this initial version,
USB and EMAC function is not available now, will comes later.
Signed-off-by: William Zhang <william.zhang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
evb-rk3328 is an evb from Rockchip based on rk3328 SoC:
- 2 USB2.0 Host port;
- 1 USB3.0 Host port;
- 1 HDMI port;
- 2 10/100M eth port;
- 2GB ddr;
- 16GB eMMC;
- UART to USB debug port;
Signed-off-by: William Zhang <william.zhang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
RK3328 is a SoC from Rockchip with quad-core Cortex-A53 CPU.
It supports two USB2.0 EHCI ports. Other interfaces are very
much like RK3288, the DRAM are 32bit width address and support
address from 0 to 4GB-16MB range.
Signed-off-by: William Zhang <william.zhang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add empty arch/arm/mach-rockchip/rk3328/Kconfig to avoid build error:
Signed-off-by: Simon Glass <sjg@chromium.org>
Enable all the CONFIGs which need by SPL.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag:
Drop CONFIG_ROCKCHIP_DWMMC for now due to build error:
Move changes to arch/arm/mach-rockchip/Kconfig to this patch:
Signed-off-by: Simon Glass <sjg@chromium.org>
Add SPL support for rk3399, default with of-platdata enabled.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Drop Kconfig changes to fix build error:
Signed-off-by: Simon Glass <sjg@chromium.org>
Add syscon and dmc node, and 'u-boot,dm-pre-reloc' option for
required driver.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag:
Signed-off-by: Simon Glass <sjg@chromium.org>
RK3399 support DDR3, LPDDR3, DDR4 sdram, this patch is porting from
coreboot, support 4GB lpddr3 in this version.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Added rockchip: tag:
Signed-off-by: Simon Glass <sjg@chromium.org>
We are using wrong mmc instance as boot target device now. below Jaehoon Chung's
patch use mmc alias which correct it. That make tinker board can not find mmc
device. So give it correct mmc device instance.
commit 02ad33aa3a
Author: Jaehoon Chung <jh80.chung@samsung.com>
Date: Thu Feb 2 13:41:14 2017 +0900
mmc: mmc-uclass: use the fixed devnum with alias node
Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
We should remove config_spl_of_platdata to build u-boot-spl-dtb.bin rather than u-boot-spl-nodtb.bin
since we use spl_back_to_brom.
I miss it because i forget to clean build-dir..
Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Acked-by: Simon Glass <sjg@chromium.org>
The rk3188 needs 3 U-Boot stages: a tpl living in 1KB of sram, a spl
the resides in the rest of the sram and loads the regular U-Boot living
in regular ram.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
The sdram controller blocks are very similar to the rk3288 in utilizing
memory scheduler, Designware uPCTL and Designware PUBL blocks, only
limited to one bank instead of two.
There are some minimal differences when setting up the ram, so it gets
a separate driver for the rk3188 but reuses the driver structs, as there
is no need to define the same again.
More optimization can happen when the modelling of the controller parts
in the dts actually follow the hardware layout hopefully at some point
in the future.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Add the core architecture code for the rk3188.
It doesn't support the SPL yet, as because of some
unknown error it doesn't start yet.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Drop these defines from rk3188_common.h
CONFIG_GENERIC_MMC, CONFIG_BOUNCE_BUFFER, CONFIG_DOS_PARTITION
CONFIG_PARTITION_UUIDS, CONFIG_CMD_PART:
Signed-off-by: Simon Glass <sjg@chromium.org>
The rk3188 shares a lot of peripherals with the rk3066 and thus
has a common include called rk3xxx.dtsi. Add both this one and
the specialized rk3188 on top of it.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Add a driver for setting up and modifying the various PLLs and peripheral
clocks on the RK3188.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Bring in required device clock binding files from Linux.
The clock trees for rk3066 and rk3188 are largely similar, which makes
them share the common parts in a shared header. While we focus on rk3188
for now, bring in both headers already for completeness sake.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Add a driver which supports pin multiplexing setup for the most commonly
used peripherals.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
PMU is the power management unit and GRF is the general register file. Both
are heavily used in U-Boot. Add header files with register definitions.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Rockchip SoCs allow the spl code to be rc4-encoded, not only the
image header, but only newer SoCs allow this encoding to be disabled.
The rk3188 is not part of those and requires its boot code to be
rc4-encoded with the regular key. So add the ability to do this
encoding via a setting on a per-soc basis when building spl images.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
So far spl-boards have declared the back_to_brom() function as simple
extern in the files themself. That doesn't scale well if every boards
defines this on its own.
Therefore move the declarations to a bootrom header.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Right now the ROCKCHIP_SPL_BACK_TO_BROM option both triggers
compilation of the bootrom hook-code as well as enabling the
behaviour of loading the full U-Boot via the boot.
New added socs may always need the bootrom code, while still
being able to decide between loading U-Boot regularly or via
the bootrom separately.
So move the compilation of the bootrom code to a hidden option
that gets selected by ROCKCHIP_SPL_BACK_TO_BROM, but can also
be selected by other parts.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
The sdram IP blocks used on rk3066, rk3188 and rk3288 are very similar
and we want to unify things once all 3 work as expected.
Therefore try to keep the rk3288 sdram driver in line by applying the
general review comments received for the rk3188 variant to it as well.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Use defines to describe the bit shifts used to create the
table for ddrconf register values.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
The gpll and cpll init values are only used in rk_clk_init in the SPL
and therefore produce compile time warnings in regular uboot builds.
Fix that with an #ifdef.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Added rockchip tag:
Signed-off-by: Simon Glass <sjg@chromium.org>
Right now the u-boot,dm-pre-reloc flag will make each marked node
always appear in both spl and tpl. But systems needing an additional
tpl might have special constraints for each, like the spl needing to
be very tiny.
So introduce two additional flags to mark nodes for only spl or tpl
environments and introduce a function dm_fdt_pre_reloc to automate
the necessary checks in code instances checking for pre-relocation
flags.
The behaviour of the original flag stays untouched and still marks
a node for both spl and tpl.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
rk3399 has different syscon registers which may used in spl,
add to support rk3399 spl.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag:
Signed-off-by: Simon Glass <sjg@chromium.org>
rk3399 grf register bit defenitions should locate in header
file, so that not only pinctrl can use it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag:
Signed-off-by: Simon Glass <sjg@chromium.org>
Use spl_early_init() to make sure that early malloc() is initialised. This
fixes booting on firefly-rk3288, for example.
Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Eddie Cai <eddie.cai.linux@gmail.com>
At present malloc_base/_limit/_ptr are not initialised in spl_init() when
we call spl_init() in board_init_f(). This is due to a recent change aimed
at avoiding overwriting the malloc area set up on some boards by
spl_relocate_stack_gd().
However if CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN is not defined, we now
skip setting up the memory area in spl_init() which is obviously wrong.
To fix this, add a new function spl_early_init() which can be called in
board_init_f().
Fixes: b3d2861e (spl: Remove overwrite of relocated malloc limit)
Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Rewrote spl_{,early_}init() to avoid duplicate code:
Rewrite/expand commit message:
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Eddie Cai <eddie.cai.linux@gmail.com>
At first, the ARM64 Linux booting requirement recommended that the
kernel image be placed text_offset bytes from 2MB aligned base near
the start of usable system RAM because memory below that base address
was unusable at that time.
This requirement was relaxed by Linux commit a7f8de168ace ("arm64:
allow kernel Image to be loaded anywhere in physical memory").
Since then, the bit 3 of the flags field indicates the tolerance
of the kernel physical placement. If this bit is set, the 2MB
aligned base may be anywhere in physical memory. For details, see
Documentation/arm64/booting.txt of Linux.
The booti command should be also relaxed. If the bit 3 is set,
images->ep is respected, and the image is placed at the nearest
bootable location. Otherwise, it is relocated to the start of the
system RAM to keep the original behavior.
Another wrinkle we need to take care of is the unknown endianness of
text_offset for a kernel older than commit a2c1d73b94ed (i.e. v3.16).
We can detect this based on the image_size field. If the field is
zero, just use a fixed offset 0x80000.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Richard reported U-Boot tools issues in OpenEmbedded/Yocto project.
OE needs to be able to change the default compiler. If we pass in
HOSTCC through the make command, it overwrites all HOSTCC instances,
including ones in tools/Makefile and tools/env/Makefile, which breaks
"make cross_tools" and "make env", respectively.
Add "override" directives to avoid overriding HOSTCC instances that
really need to point to the cross-compiler.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reported-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Leave only detected flash type enabled in FTD as otherwise GPMC CS is
claimed (and never freed) by Linux, causing 'concurent' flash type
not to be probed.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
ISEE's U-Boot and Linux are using 1bit ECC scheme, while we
switched to 8bit ECC to fullfill flash specification requirements.
However when trying to run U-Boot on board with 1bit ECC'd data
on flash, UBI code takes several minutes to pass scan as reading
of every block ends with ecc error (which is also printed on
console).
So, until proper solution is developed, disable environment
alltogether.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
This is a 96Board compliant board based on STiH410 SoC:
- 1GB DDR
- On-Board USB combo WiFi/Bluetooth RTL8723BU
with PCB soldered antenna
- Ethernet 1000-BaseT
- SATA
- HDMI
- 2 x USB2.0 type A
- 1 x USB2.0 type micro-AB
- SD card slot
- High speed connector (SD/I2C/USB interfaces)
- Low speed connector (UART/I2C/GPIO/SPI/PCM interfaces)
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add SDHCI host controller found on STMicroelectronics SoCs
On some ST SoCs, i.e. STiH407/STiH410, the MMC devices can live
inside a dedicated flashSS sub-system that provides an extend subset
of registers that can be used to configure the Arasan MMC/SD Host
Controller.
This means, that the SDHCI Arasan Controller can be configured to be
eMMC4.5 or 4.3 spec compliant.
W/o these settings the SDHCI will configure and use the MMC/SD
controller with limited features e.g. PIO mode, no DMA, no HS etc.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
As no gpio.h is defined in arch/arm/include/asm/arch-stih410,
to avoid compilation failure, do not include asm/arch/gpio.h.
This is needed for example when including sdhci.h, which include
asm/gpio.h>.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds support to ASC (asynchronous serial controller)
driver, which is basically a standard serial driver. This IP
is common across other STMicroelectronics SoCs
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The STiH410 is an advanced multi-HD AVC processor with 3D
graphics acceleration and 1.5-GHz ARM Cortex-A9 SMP CPU
part of the STiH407 family.
It has wide connectivity including USB 3.0, PCI-e, SATA
and gigabit ethernet.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
The SysTick is a 24-bit down counter that is found on all ARM Cortex
M3, M4, M7 devices and is always located at a fixed address.
The number of reference clock ticks that correspond to 10ms is normally
defined in the SysTick Calibration register's TENMS field. However, on some
devices this is wrong, so this driver allows the clock rate to be defined
using CONFIG_SYS_HZ_CLOCK.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Vikas MANOCHA <vikas.manocha@st.com>
The size field in GP header that is expected by ROM is size of the
image + size of the header. But omapimage generates a gp header
only with size of the image as size field. Fix it
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The workaround for ARM errata 725233 had been lost since
commit 45bf05854b (armv7: adapt omap3 to the new cache
maintenance framework). Bring it back in order to avoid
very difficult to reproduce, but actually encountered in
the wild CPU deadlocks when running software rendered
X11 desktop on OMAP3530 hardware.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Migrate to Kconfig]
Signed-off-by: Tom Rini <trini@konsulko.com>
Boards with OMAP3530 SoC fail to boot since commit bd2c4522c2
("ti: armv7: enable EXT support in SPL (using ti_armv7_common.h)")
because it enabled the use of Thumb2 for the SPL.
Experiments have shown that the deadlock happens in the
prcm_init() function from 'arch/arm/mach-omap2/omap3/clock.c'.
This patch enforces the compilation of clock.c source file in
ARM mode and makes the deadlock disappear. We are yet to figure
out the root cause of the problem. Still this is somewhat
better than having non-bootable boards for years.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Borrowing from omap3_logic, switch to SPL_SYS_MALLOC_SIMPLE and moving
the stack to DDR as soon as we're able.
Signed-off-by: Tom Rini <trini@konsulko.com>
Raw uboot image is used in place of FIT image in secure boot.
The maximum allocated size of raw u-boot bin is 1MB in memory map.
Hence , CONFIG_SYS_MONITOR_LEN has been modified to 1 MB.
The bootscript (BS_ADDR) and its header (BS_HDR_ADDR) offset on
MMC have also been modified to accommodate the increase in uboot size.
Signed-off-by: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com>
Reviewed-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
VID support in NXP layerscape Chassis-3 (lsch3) compilant SoCs like
LS2088A, LS2080A differs from existing logic.
-VDD voltage array is different
-Registers are different
-VDD calculation logic is different
Add new function adjust_vdd() for LSCH3 compliant SoCs
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Arpit Goel <arpit.goel@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Remove the DDR interactive debugging to reduce the size of spl image.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Read DMA operations causes CRC error on armv8 chassis 2 platforms
due to the erratum A-010635.
In order to support sata on these platforms, ECC needs to be disabled.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
In early MMU table, DDR has to be mapped as device memory to avoid
speculative access. After DDR is initialized, it needs to be updated
to normal memory to allow code execution. To simplify the code,
dram_init() is moved into a common file as a weak function.
Signed-off-by: York Sun <york.sun@nxp.com>
Function mmu_change_region_attr() is added to change existing mapping
with updated PXN, UXN and memory type. This is a break-before-make
process during which the mapping becomes fault (invalid) before final
attributres are set.
Signed-off-by: York Sun <york.sun@nxp.com>
Early MMU improves performance especially on emulators. However, the
early MMU is left enabled after the first stage of SPL boot. Instead
of flushing D-cache and dealing with re-enabling MMU for the second
stage U-Boot, disabling it for SPL build simplifies the process. The
performance penalty is unnoticeable on the real hardware. As of now,
SPL boot is not supported by existing emulators. So this should have
no impact on emulators.
Signed-off-by: York Sun <york.sun@nxp.com>
This patch follows the break-before-make process when making changes
to MMU table. MMU is disabled before changing TTBR to avoid any
potential race condition.
Signed-off-by: York Sun <york.sun@nxp.com>
Update mapping with actual DDR size. Non-existing memory should not
be mapped as "normal" memory to avoid speculative access.
Signed-off-by: York Sun <york.sun@nxp.com>
Since the reserved RAM is tracked by gd->arch.resv_ram, calculation
of MC memory blocks can be simplified. The MC RAM is guaranteed to be
aligned by the reservation process.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Priyanka Jain <priyanka.jain@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved
at the end of DDR. DDR is spit into two or three banks. This patch
reverts commit aabd7ddb and simplifies the calculation of reserved
memory, and moves the code into common SoC file. Secure memory is
carved out first. DDR bank size is reduced. Reserved memory is then
allocated on the top of available memory. U-Boot still has access
to reserved memory as data transferring is needed. Device tree is
fixed with reduced memory size to hide the reserved memory from OS.
The same region is reserved for efi_loader.
Signed-off-by: York Sun <york.sun@nxp.com>
Instead of adding all memory banks, add a hook so individual SoC/board
can has its own implementation.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Alexander Graf <agraf@suse.de>
Reviewed-by: Alexander Graf <agraf@suse.de>
Fix warnings reported when built with W=1, by DTC 1.4.2 or later:
Node /memory has a reg or ranges property, but no unit name
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Linux Commit 9c0da3cc61f1 ("ARM: dts: explicitly mark skeleton.dtsi
as deprecated") declared that skeleton.dtsi was deprecated.
Move the memory node below to suppress warnings of FDTGREP.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Commit 04cd4e7215 ("ARM: uniphier: remove DRAM base address from
board parameters") accidentally unset the DRAM_SPARSE flag, and
changed the physical map of the DRAM channels. Revive the original
behavior.
Fixes: 04cd4e7215 ("ARM: uniphier: remove DRAM base address from board parameters")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reported-by: Shunji Sato <sato.shunji@socionext.com>
The maximum supported peripheral clock frequency of the zynq depends on
the IO routing. The MIO and EMIO support a maximum frequency of 50 MHz
respectively 25 MHz. Use the max-frequency value of the device tree to
determine the maximal supported peripheral clock frequency.
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The zynq_sdhci controller driver use CONFIG_ZYNQ_SDHCI_MAX_FREQ as base
clock frequency but this clock is not fixed and depends on the hardware
configuration. Additionally the value of CONFIG_ZYNQ_SDHCI_MAX_FREQ
doesn't match the real base clock frequency of SDIO_FREQ. Use the clock
framework to determine the frequency at run time.
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Move the zynq to clock framework and remove unused functions as well as
the CONFIG_ZYNQ_PS_CLK_FREQ configuration.
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add a clock framework driver for the zynq platform. The driver is based
on the platform zynq clock driver but reworked to use static functions
instead of run-time generated objects even for unused clocks.
Additionally the CONFIG_ZYNQ_PS_CLK_FREQ is replaced by the
ps-clk-frequency from the device tree.
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The gem[0-1]_rclk_ctrl registers control the source of the rx clock,
control and data signals and configure via ps7_init function. Don't
overwrite the register with the default value.
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-02-17 10:22:46 +01:00
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