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573 Commits

Author SHA1 Message Date
Tom Rini
6364a5d4bd Prepare v2017.09-rc1
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-31 20:37:25 -04:00
Tom Rini
eddc7dabe0 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-31 18:59:01 -04:00
Tom Rini
8f1a80e99e configs: Migrate CMD_NAND*
Migrate all remaining instances of CMD_NAND, CMD_NAND_TRIMFFS
CMD_NAND_LOCK_UNLOCK and CMD_NAND_TORTURE from the headers into the
defconfig files.

Tested-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-31 12:21:40 -04:00
Simon Glass
7b3c4c3a53 dm: console: Check for serial devices properly
With driver model the serial device is often not called "serial". Mark
driver-model stdio devices so that they can be detected and we can look up
the uclass. This is a more reliable way of finding out whether the console
is connected to a serial device or not.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-31 12:21:40 -04:00
Simon Glass
42f9f915c2 console: Unify the check for a serial console
Put the check for whether a console is a serial device in a function so
that we can share the code in the two places that use it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-31 12:21:40 -04:00
Andrew F. Davis
ef3fc42ded arm: mach-omap2: Align image address before cache operations
The image address passed to secure_boot_verify_image() may not be
cacheline aligned, round the address down to the nearest cacheline.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-07-31 12:21:39 -04:00
Tom Rini
c826d17286 ti: Default to ENV_IS_IN_FAT if MMC_OMAP_HS
When we have MMC available we assume that we want to put the env as a
file on FAT.

Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-31 12:21:25 -04:00
Tom Rini
3c7be0c91a am335x_hs_evm: Disable CONFIG_SPL_ENV_SUPPORT
The main uses of CONFIG_SPL_ENV_SUPPORT are for network support and for
disabling "Falcon Mode" support at run-time.  As this build enables
neither, remove this feature.

Cc: Andrew F. Davis <afd@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-31 11:22:56 -04:00
Tom Rini
43ba3c59cb env: Migrate CONFIG_ENV_IS_IN_FAT options to Kconfig
We rename the various FAT_ENV_xxx options to CONFIG_ENV_FAT_xxx so that
they can be modified via Kconfig.  Migrate all existing users to the new
values.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-31 11:22:56 -04:00
Adam Ford
3158eebd21 Remove unused CONFIG_TWL4030_PWM
CONFIG_TWL4030_PWM is not being used by any source, so let's remove the #define
and the whitelist entry

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-31 11:22:55 -04:00
Patrice Chotard
84e9dcc120 serial: stm32x7: Convert CONFIG_STM32X7_SERIAL to Kconfig
Add CONFIG_STM32X7_SERIAL as a Kconfig option.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-07-31 11:22:54 -04:00
Philipp Tomsich
0fa0abecfc dm: Kconfig: fix typo in help for SPL_PINCTRL
Changes 'controlloers' to 'controllers' in the help-text for
SPL_PINCTRL.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-31 11:22:53 -04:00
Alexander Graf
c1ae1a1608 efi_loader: Fix warning in efi_gop
Commit ca9193d2b1 ("efi_loader: gop: fixes for CONFIG_DM_VIDEO without
CONFIG_LCD") dropped the explicit (void*) cast for fb_base in efi gop support
for CONFIG_LCD without DM. This patch adds it back, eliminating the now occuring
warning again

Fixes: ca9193d2b1 ("efi_loader: gop: fixes for CONFIG_DM_VIDEO without CONFIG_LCD")
Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-31 07:28:13 -04:00
Tom Rini
2218b32d88 Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot
Patch queue for efi - 2017-07-29

A lot of EFI greatness this time around. Thanks a lot to the
two amazing new contributors

  Heinrich Schuchardt and
  Rob Clark

we now gain

  - stable objects across multiple bootefi invocations
  - fixes for shim
  - fixes for ipxe
  - protocol installation
  - device path conversion to/from text
  - working "lsefi" support in grub
  - working notifiers
  - various bug fixes
2017-07-31 07:27:45 -04:00
Bin Meng
55f228b07e x86: minnowmax: Remove CONFIG_SMSC_LPC47M
There is no SMSC LPC47M Super I/O chipset on the MinnowMax board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-30 10:30:25 +08:00
Andy Shevchenko
382fabb297 x86: acpi: Don't touch hardware on HW reduced platforms
If ACPI HW reduced bit in FADT is set we should ignore any ACPI hardware
communications.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-30 10:30:25 +08:00
Andy Shevchenko
ace7762b28 x86: acpi: Export acpi_fill_mcfg() with __weak attribute
Some platforms might require different approach when filling memory
mappings configuration table.

Allow them to override the common method.

At the same time export acpi_create_mcfg_mmconfig().

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-30 10:30:25 +08:00
Andy Shevchenko
b156da91fb x86: acpi: Deduplicate acpi_fill_madt() implementation
In Baytrail and Quark support code acpi_fill_madt() is identical.

Deduplicate its implementation by moving to lib/acpi_tables.c.

At the same time mark acpi_fill_madt() with __weak attribute to keep a
possibility to override it in platform code

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-30 10:30:25 +08:00
Andy Shevchenko
2dcbef6f6c x86: acpi: Name fields in FADT in accordance with specification
ACPI specification defines FADT fields marked as reserved in U-Boot.

Name these fields in accordance with ACPI specification.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-30 10:30:25 +08:00
Andy Shevchenko
684c4cd011 x86: acpi: Fill OEM revision
Fill OEM revision field in the tables by U-Boot build date.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-30 10:30:25 +08:00
Andy Shevchenko
e7aa9c2947 Makefile: Export build date as integer
In some cases we would need build date as integer value.
Export U_BOOT_BUILD_DATE as %Y%m%d integer value.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-30 10:30:25 +08:00
Andy Shevchenko
06054b1a62 Makefile: Don't shadow actual error when compile ASL
If ASL compiler failed by any reason do not produce output C file.
Otherwise sequential run of make will shadow the actual error in ASL,
i.e.

  CC      board/intel/edison/dsdt.o
board/intel/edison/dsdt.c:1:1: error: unterminated comment
 /*

and user has to remove dsdt.c and run make in order to see the error again.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-30 10:30:25 +08:00
Stefan Roese
66712c298d x86: conga-qeval20-qa3-e3845.dts: Enable xHCI support in dts
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-30 10:30:25 +08:00
Stefan Roese
1f4e25780a x86: dfi-bt700: Add xHCI USB support
Change from EHCI to xHCI on the DFI BayTrail SoM.

The xHCI USB hub is connected to an GPIO on the DFI BayTrail SoM. For
correct operation, it needs to get reset upon power-up. Otherwise it
may happen that the hub is not detected after a software reboot. This
patch also configures this GPIO in the dts for correct operation.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-30 10:30:25 +08:00
Stefan Roese
db1d20a904 x86: conga-qeval20-qa3-e3845: Select CONFIG_BOARD_LATE_INIT
This config option is needed on the congatec x86 BayTrail board, as
otherwise the USB hub will not get initialized correctly. This
patch selects this Kconfig option again.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-30 10:30:25 +08:00
Stefan Roese
68b3f8d8c4 x86: theadorable-x86-dfi-bt700: Add Spansion SPI support and move VIDEO blob
To support the Spansion SPI NOR flashes, this patch enables the support in
defconfig. This increases the U-Boot binary too much so that it does
not fit into its area in the ROM. So also move the VIDEO BIOS blob
a bit to make some space here.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-30 10:30:25 +08:00
Andy Shevchenko
495f3774be x86: Add Intel Edison board files
Add Intel Edison board which is using U-Boot.

The patch is based on work done by the following people (in alphabetical
order):
	Aiden Park <aiden.park@intel.com>
	Dukjoon Jeon <dukjoon.jeon@intel.com>
	eric.park <eric.park@intel.com>
	Fabien Chereau <fabien.chereau@intel.com>
	Felipe Balbi <felipe.balbi@linux.intel.com>
	Scott D Phillips <scott.d.phillips@intel.com>
	Sebastien Colleur <sebastienx.colleur@intel.com>
	Steve Sakoman <steve.sakoman@intel.com>
	Vincent Tinelli <vincent.tinelli@intel.com>

In case we're building for Intel Edison, we must have 4096 bytes of
zeroes in the beginning on u-boot.bin. This is done in
board/intel/edison/config.mk.

First run sets hardware_id environment variable which is read from
System Controller Unit (SCU).

Serial number (serial# environment variable) is generated based on eMMC
CID.

MAC address on USB network interface is unique to the board but kept the
same all over the time.

Set mac address from U-Boot using following scheme:
	OUI = 02:00:86
	next 3 bytes of MAC address set from eMMC serial number

This allows to have a unique mac address across reboot and flashing.

Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[bmeng: Add MAINTAINERS file for Intel Edison board]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-30 10:30:25 +08:00
Felipe Balbi
e71de54a49 x86: Add Intel Tangier support
Add Intel Tangier SoC support.

Intel Tangier SoC is a core part of Intel Merrifield platform. For
example, Intel Edison board is based on such platform.

The patch is based on work done by the following people (in alphabetical
order):
	Aiden Park <aiden.park@intel.com>
	Dukjoon Jeon <dukjoon.jeon@intel.com>
	eric.park <eric.park@intel.com>
	Fabien Chereau <fabien.chereau@intel.com>
	Scott D Phillips <scott.d.phillips@intel.com>
	Sebastien Colleur <sebastienx.colleur@intel.com>
	Steve Sakoman <steve.sakoman@intel.com>
	Vincent Tinelli <vincent.tinelli@intel.com>

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2017-07-30 10:30:25 +08:00
Andy Shevchenko
b7026b0c98 x86: Add dma-mapping.h to architectural code
Some cross-platform drivers rely on this header present.
Make it so for x86.

It's just a copy'n'paste of arch/arm/include/asm/dma-mapping.h.

Suggested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2017-07-30 10:30:25 +08:00
Felipe Balbi
8f8a12d1e7 watchdog: Introduce watchdog driver for Intel Tangier
Add watchdog driver for Intel Tangier based platforms.

Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-30 10:30:25 +08:00
Andy Shevchenko
611dbb7f95 arch/x86: Select USB before selecting host driver
Kbuild complains if USB is not selected before any of host driver.

warning: (X86) selects USB_EHCI_HCD which has unmet direct dependencies (USB)
warning: (X86) selects USB_EHCI_HCD which has unmet direct dependencies (USB)

Select it for X86.

Fixes: 64d6ac5bc4 ("Kconfig: USB: Migrate CONFIG_USB_EHCI_HCD users to Kconfig")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
[bmeng: Update all x86 boards' defconfig files to remove CONFIG_USB]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-30 10:30:25 +08:00
Tom Rini
19d1f1a2f3 Merge git://git.denx.de/u-boot-socfpga 2017-07-29 11:44:08 -04:00
Tom Rini
211aaf309c Merge git://git.denx.de/u-boot-usb 2017-07-29 11:43:51 -04:00
Rob Clark
af65db85b8 efi_loader: indent entry/exit prints to show nesting level
This should make it easier to see when a callback back to UEFI world
calls back in to the u-boot world, and generally match up EFI_ENTRY()
and EFI_EXIT() calls.

Signed-off-by: Rob Clark <robdclark@gmail.com>
[agraf: remove static from const var]
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-29 00:18:46 +02:00
Rob Clark
c160d2f5ec efi_loader: add checking for incorrect use of EFI_ENTRY/EXIT
Missing an EFI_ENTRY() or doubling up EFI_EXIT() leads to non-obvious
crashes.  Let's add some error checking.

Signed-off-by: Rob Clark <robdclark@gmail.com>
[agraf: fix bogus assert() and fix app_gd breakage]
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-29 00:18:24 +02:00
Patrice Chotard
b108d8a0de clk: fix compilation errors for poplar platform
Move clk_release_all() prototype and definition inside
OF_CONTROL flag to avoid following compilation error for
poplar platform:

aarch64:  +   poplar
+drivers/usb/host/built-in.o: In function `ehci_usb_remove':
+drivers/usb/host/ehci-generic.c:159: undefined reference to `clk_release_all'
+drivers/usb/host/built-in.o: In function `ehci_usb_probe':
+drivers/usb/host/ehci-generic.c:133: undefined reference to `clk_release_all'
+make[1]: *** [u-boot] Error 139
+make: *** [sub-make] Error 2

Introduced by 4e542c4 clk: add clk_release_all()

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-07-28 23:34:46 +02:00
Patrice Chotard
d38a8ea19c usb: host: xhci-dxc3: fix compilation warnings
Fix following warnings encountered with platforms
dra7xx_evm and dra7xx_hs_evm :

       arm:  +   dra7xx_evm
+  hccr = (struct xhci_hccr *)devfdt_get_addr(dev);
+         ^
+  hcor = (struct xhci_hcor *)((phys_addr_t)hccr +
+                              ^
w+drivers/usb/host/xhci-dwc3.c: In function 'xhci_dwc3_probe':
w+drivers/usb/host/xhci-dwc3.c:124:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
w+drivers/usb/host/xhci-dwc3.c:125:30: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
w+drivers/usb/host/xhci-dwc3.c:125:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
       arm:  +   dra7xx_hs_evm
+  hccr = (struct xhci_hccr *)devfdt_get_addr(dev);
+         ^
+  hcor = (struct xhci_hcor *)((phys_addr_t)hccr +
+                              ^
w+drivers/usb/host/xhci-dwc3.c: In function 'xhci_dwc3_probe':
w+drivers/usb/host/xhci-dwc3.c:124:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
w+drivers/usb/host/xhci-dwc3.c:125:30: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
w+drivers/usb/host/xhci-dwc3.c:125:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]

Introduced by 7e65e84 usb: host: xhci-dwc3: Convert driver to DM

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-07-28 23:34:45 +02:00
Jean-Jacques Hiblot
3b63db37ad phy: add a NO-OP phy driver
This driver is used to stub PHY operations in a driver (USB, SATA).
This is useful when the 'client' driver (USB, SATA, ...) uses the PHY
framework and there is no actual PHY harwdare to drive.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2017-07-28 23:34:44 +02:00
Patrice Chotard
2080d023d9 usb: host: ohci-generic: initialize PHY only when found
Call generic_phy_init() only when a PHY was found.
This will avoid a crash if no "phys" property is found in DT.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reported-by: Patrick Delaunay <patrick.delaunay@st.com>
2017-07-28 23:34:43 +02:00
Patrice Chotard
4b3928a08f usb: host: ehci-generic: initialize PHY only when found
Call generic_phy_init() only when a PHY was found.
This will avoid a crash if no "phys" property is found in DT.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reported-by: Patrick Delaunay <patrick.delaunay@st.com>
2017-07-28 23:34:43 +02:00
Patrice Chotard
623b7aca1f dm: usb: host: xhci-dwc3: add missing #ifdef CONFIG_DM_USB
Add CONFIG_DM_USB flag to avoid following compilation errors
detected by buildman :
+drivers/usb/host/built-in.o: In function `xhci_dwc3_remove':
+drivers/usb/host/xhci-dwc3.c:168: undefined reference to `xhci_deregister'
+drivers/usb/host/built-in.o: In function `xhci_dwc3_probe':
+drivers/usb/host/xhci-dwc3.c:145: undefined reference to `usb_get_dr_mode'
+drivers/usb/host/xhci-dwc3.c:152: undefined reference to `xhci_register'

introduced by patch d5c3f014da3 "usb: host: xhci-dwc3: Convert driver to DM"

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reported-by: Ran Wang <ran.wang_1@nxp.com>
2017-07-28 23:34:42 +02:00
Patrice Chotard
d9fb7bece0 dm: phy: add missing #ifdef CONFIG_PHY
To avoid compilation breakage on platform that doesn't
support DM PHY but uses xhci-dwc3 driver, add the missing
CONFIG_PHY flag.

Introduced by patch :
84e53877 "usb: host: xhci-dwc3: Add generic PHY support"

Cc: Ran Wang <ran.wang_1@nxp.com>
Cc: Bin Meng <bmeng.cn@gmail.com>

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reported-by: Ran Wang <ran.wang_1@nxp.com>
2017-07-28 23:34:41 +02:00
Patrick Delaunay
6fa8dddd06 dfu: add common function to initiate transaction
- factorize code between read and write transaction
- always use dfu_transaction_cleanup() to initialize
  the internal variable: easy maintenance
- replace direct access by dfu_get_buf() and dfu_get_buf_size()

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2017-07-28 23:34:40 +02:00
Patrick Delaunay
57da060755 dfu: factorize transaction cleanup
rename cleanup function, as now called by read

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2017-07-28 23:34:40 +02:00
Patrick Delaunay
15970d871c dfu: remove limitation on partition size
Change long (32 bits on arm) to u64 (same type than offset)
for size and read offset r_left

So partition and device used for DFU can be greater than 4GB

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2017-07-28 23:34:39 +02:00
Patrick Delaunay
4de512018b dfu: allow dfu read on partition greater than 2GB
solve issue on get_medium_size() function
the detection of error is a simple test < 0
but for ARM platform, long is 32bits and 2GB = 0x80000000
is seen as error.

I solve the issue by changing the prototype fo the function
to separate size and result.
This patch prepare the next patch with size change to u64.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2017-07-28 23:34:38 +02:00
Siva Durga Prasad Paladugu
bab0146ea9 usb: gadget: f_thor: Free the allocated out request buffer
Fix the memory leak by freeing the allocated out request buffer

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-07-28 23:34:38 +02:00
Bin Meng
78e3098752 usb: xhci: Enable TT to support LS/FS devices behind a HS hub
So far LS/FS devices directly attached to xHC root port can be
successfully enumerated by xHCI driver, but if they are connected
behind a hub, the enumeration process fails to address the device.

It turns out xHCI driver still misses a part that in the device's
input slot context, all Transaction Translator (TT) related fields
are not programmed. The xHCI spec defines how to enable TT.

Now LS/FS devices like USB keyboard/mouse can be enumerated behind
a high speed hub.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:37 +02:00
Bin Meng
196ef8323c usb: xhci: Correct TT_SLOT and TT_PORT macros
These two macros really need a parameter to make them useful.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:36 +02:00
Bin Meng
d228ca362b usb: xhci: Implement update_hub_device() operation
There is no way to know whether the attached device is a hub or
not in advance before the device's descriptor is fetched. But
once we know it's a high speed hub, per the xHCI spec, we need
to tell xHC it's a hub device by initializing hub-related fields
in the input slot context.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:36 +02:00
Bin Meng
81060bb1c0 usb: hub: Call usb_update_hub_device() after hub descriptor is fetched
After fetching hub descriptor, we need to call USB uclass operation
update_hub_device() to notify HCD to do some preparation work.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:35 +02:00
Bin Meng
9ca1b4bab1 dm: usb: Add a new USB controller operation 'update_hub_device'
For USB host controllers like xHC, its internal representation of
hub needs to be updated after the hub descriptor is fetched. This
adds a new op that does this.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:35 +02:00
Bin Meng
5624dfd5aa usb: hub: Parse and save TT details from device descriptor
A high speed hub has a special responsibility to handle full speed/
low speed devices connected on downstream ports. In this case, the
hub must isolate the high speed signaling environment from the full
speed/low speed signaling environment with the help of Transaction
Translator (TT). TT details are provided by hub descriptors and we
parse and save it to hub uclass_priv for later use.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:34 +02:00
Bin Meng
493b8dd070 usb: xhci: Program 'route string' in the input slot context
xHCI spec says: the values of the 'route string' field shall be
initialized by the first 'Address Device' command issued to a
device slot, and shall not be modified by any other command.

So far U-Boot does not program this field, and it does not prevent
SS device directly attached to root port, or HS device behind an HS
hub, from working, due to the fact that 'route string' is used by
the xHC to target SS packets. But in order to enumerate devices
behind an SS hub, this field must be programmed.

With this commit and along with previous commits, now SS & HS devices
attached to a USB 3.0 hub can be enumerated by U-Boot.

As usual, this new feature is only available when DM is on.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:33 +02:00
Bin Meng
daec469144 usb: xhci: Change xhci_setup_addressable_virt_dev() signature
For future extension, change xhci_setup_addressable_virt_dev()
signature to accept a pointer to 'struct usb_device', instead
of its members slot_id & speed, as the struct already contains
these two plus some other useful information of the device.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:33 +02:00
Bin Meng
bbc6f06c00 usb: hub: Support 'set hub depth' request for USB 3.0 hubs
USB 3.0 hub uses a hub depth value multiplied by four as an offset
into the 'route string' to locate the bits it uses to determine the
downstream port number. We shall set the hub depth value of a USB
3.0 hub after it is configured.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:32 +02:00
Bin Meng
74ffc7cbb1 usb: hub: Translate USB 3.0 hub port status into old version
USB 3.0 hub port status field has different bit positions from 2.0
hubs. Since U-Boot only understands the old version, translate the
new one into the old one.

Since we are going to add USB 3.0 hub support, this feature is only
available with driver model USB.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:31 +02:00
Bin Meng
46c1d49330 usb: hub: Add a new API to test if a hub device is root hub
Sometimes we need know if a given hub device is root hub or not.
Add a new API to test this. This removes the xHCI driver's own
version is_root_hub() and change to use the new API.

While we are here, remove the unused/commented out get_usb_device()
in the xHCI driver too.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-28 23:34:30 +02:00
Bin Meng
a199a72448 usb: hub: Remove hub_port_reset()
At present hub_port_reset() is defined in DM USB, but it is never
called hence remove it (removing another ifdefs).

While we are here, change legacy_hub_port_reset() name to
usb_hub_port_reset() to better match other function names in the
same hub module.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:30 +02:00
Bin Meng
dfa96e0676 usb: hub: Use 'struct usb_hub_device' as hub device's uclass_priv
Use USB hub device's dev->uclass_priv to point to 'usb_hub_device'
so that with driver model usb_hub_reset() and usb_hub_allocate()
are no longer needed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:29 +02:00
Bin Meng
5e941943d8 usb: xhci-pci: Clean up the driver a little bit
This cleans up the driver a little bit.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:29 +02:00
Bin Meng
978f6a3b14 usb: xhci-pci: Drop non-DM version of xhci-pci driver
As there is no board that currently uses xhci-pci driver without DM
USB, drop its support and leave only DM support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:28 +02:00
Bin Meng
c9621012a6 x86: minnowmax: Enable USB xHCI support
BayTrail SoC supports both EHCI and xHCI controllers. However only
one host controller (either EHCI or xHCI) can be used. To enable
HSIC and SS ports, xHCI must be used. This turns on xHCI support on
Intel MinnowMax board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:27 +02:00
Bin Meng
6e4d039aaa x86: minnowmax: Add a environment variable for USB power-on delay
Occasionally it was observed that on Intel MinnowMax board, with a
USB 2.0 device connected to the bottom port, when doing 'usb start'
on the xHCI controller:

  scanning bus 0 for devices... cannot reset port 3!?

But neither of the two USB ports is routed to xHCI root port 3.
Adding some debug information shows that xHCI port 3 PORTSC register
mysteriously reports both CCS = 1 and CSC = 1.

This is not seen every time. After increasing the timeout to wait
for power to become stable, the issue is gone. So this indicates
current default USB power-on delay (20ms) might be at a critical
region where power is stable/unstable. U-Boot provides a mechanism
to have a environment variable to override the default one. Add
one for MinnowMax.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:27 +02:00
Bin Meng
d7cde28113 usb: xhci: Convert CONFIG_USB_XHCI_PCI to Kconfig
Add CONFIG_USB_XHCI_PCI as a Kconfig option.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:26 +02:00
Bin Meng
78abf14fc2 usb: cmd: Print actual packet size for super speed devices
USB 3.0 defines bMaxPacketSize0 field in the device descriptor as
the exponent of 2, so let's print the calculated actual size.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:25 +02:00
Bin Meng
cbb89ed026 configs: Remove CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS in all boards
Now that EHCD does not use CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS,
remove it in all boards' config files.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:24 +02:00
Bin Meng
99c2255688 usb: ehci: Get rid of CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS
EHC reports supported maximum number of ports in the HCSPARAMS
register, so it's unnecessary to use a hardcoded config option
CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:23 +02:00
Bin Meng
2931342874 configs: Remove CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS in all boards
Now that xHCD does not use CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS,
remove it in all boards' config files.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:23 +02:00
Bin Meng
7274671e04 usb: xhci: Get rid of CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS
xHC reports supported maximum number of ports in the HCSPARAMS1
register, so it's unnecessary to use a hardcoded config option
CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:22 +02:00
Bin Meng
1bdcd9019d usb: xhci: Change MAX_HC_PORTS to 255
HCSPARAMS1:MaxPorts field specifies the maximum port number value,
and its valid values are in the range of 1 to 255.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:21 +02:00
Bin Meng
98ba3d6c23 usb: hub: Add 3.0 hub port status mask of 2.0 hub
USB 3.0 hub port status has different bit position regarding to
port power, port speed, etc. But others are the same as 2.0 hubs.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:21 +02:00
Bin Meng
337fc7e665 usb: hub: Change USB hub descriptor to match USB 3.0 hubs
USB 3.0 hubs have a slightly different hub descriptor than USB 2.0
hubs, with a fixed (rather than variable length) size. Change the
host controller drivers that access those last two fields
(DeviceRemovable and PortPowerCtrlMask) to use the union.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:20 +02:00
Bin Meng
53771a490e usb: hub: Revise wLength for 'get port status' request
For accuracy, we should use 'sizeof(struct usb_port_status)' as the
wLength for 'get port status' request, although it happens to be
equal to 'sizeof(struct usb_hub_status)'.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:19 +02:00
Bin Meng
f342119602 usb: hub: Send correct wValue to get hub descriptor of a USB 3.0 hub
Testing a USB 3.0 hub by connecting it to the xHCI port on Intel
MinnowMax, when issuing 'get hub descriptor' to the hub, xHCI
reports a transfer event TRB with a completion code 6 which means
'Stall Error'.

In fact super speed USB hub descriptor type is 0x2a, not 0x29.
Sending correct SETUP packet to the hub makes it not stall anymore.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:18 +02:00
Bin Meng
f7a9e5dd03 usb: hub: Update handling connect status/change in usb_scan_port()
It was observed that on Intel MinnowMax board, when xHCI is enabled
in the BayTrail SoC, with a USB 3.0 device connected to the bottom
USB 3.0 port (mapped to xHCI root port #7), its PORTSC register is
always 0x201203 (CCS = 1, CSC = 0). The root cause of such behavior
is unknown yet. Connect status change bit is set on the same port
with a USB 2.0 device (mapped to xHCI port #1, which is a different
port on the root hub).

With current logic in usb_scan_port(), the enumeration process will
abort if it does not detect a connect status change on a hub port.
However since a device connection status is correctly reported, the
enumeration process can still continue.

With this change, USB device connected to the bottom blue port on
MinnowMax board can be enumerated under either SS or HS mode.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Dinh Nguyen <dinguyen@kernel.org>
2017-07-28 23:34:18 +02:00
Bin Meng
aab0db08c0 usb: xhci: Add input slot context in xhci_set_configuration()
A valid input slot context for a 'configure endpoint' command requires
the 'Context Entries' field to be initialized to the index of the last
valid endpoint context that is defined by the target configuration. We
set up the 'Context Entries' field, but we forget to include the input
slot context in the input control context 'Add Context flags' bitmap.
So xHC will simply ignore input slot context and continue using its own
which contains old information of the device.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:17 +02:00
Bin Meng
209b98de01 usb: xhci: Initialize scratchpad buffer array and scratchpad buffers
The scratchpad buffer array is used to define the locations of
statically allocated memory pages that are available for the
private use of the xHC. The xHCI spec explicitly mentions that
system software shall allocate the scratchpad buffers before
placing the xHC in to Run mode (Run/Stop (R/S) = ‘1’), however
U-Boot is missing this part.

This causes xHC on Intel platform does not respond the very first
'enable slot' command that is given to xHC and the 'enable slot'
command completion event TRB is never generated and xHC seems to
hang forever.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:16 +02:00
Bin Meng
43eb0d4488 usb: xhci: Correct command TRB 4th dword initialization
In xhci_queue_command(), when the command is not 'reset endpoint',
'stop endpoint' or 'set TR dequeue pointer', endpoint ID should not
be encoded in the TRB.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:15 +02:00
Bin Meng
f2e0315e9d usb: xhci: Remove incorrect comments for struct xhci_container_ctx
There is no member called 'dma' in struct xhci_container_ctx. Remove
the comments that mentions it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:14 +02:00
Patrice Chotard
28df1cfddd usb: host: ohci-generic: add generic PHY support
Extend ohci-generic driver with generic PHY framework

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:14 +02:00
Patrice Chotard
8a51b4b3da usb: host: ohci-generic: add RESET support
use array to save deasserted resets reference in order to
assert them in case of error during probe() or during driver
removal.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:13 +02:00
Patrice Chotard
155d9f65d3 usb: host: ohci-generic: add CLOCK support
use array to save enabled clocks reference in order to
disabled them in case of error during probe() or during
driver removal.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:11 +02:00
Patrice Chotard
0d0ba1a73d usb: host: ehci-generic: add generic PHY support
Extend ehci-generic driver with generic PHY framework

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:10 +02:00
Patrice Chotard
a1cee8e808 usb: host: ehci-generic: add error path and .remove callback
Use an array to save enabled clocks reference and deasserted resets
in order to respectively disabled and asserted them in case of error
during probe() or during driver removal.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:09 +02:00
Patrice Chotard
10bb775e92 usb: host: ehci-generic: replace printf() by error()
this allows to get file, line and function location
of the current error message.

Signed-off-by: patrice chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:09 +02:00
Patrice Chotard
642346ae26 dm: core: add ofnode_count_phandle_with_args()
This function is usefull to get phandle number contained
in a property list.
For example,  this allows to allocate the right amount
of memory to keep clock's reference contained into the
"clocks" property.

To implement it, either of_count_phandle_with_args() or
fdtdec_parse_phandle_with_args() are used respectively
for live tree and flat tree.
By passing index = -1, these 2 functions returns the
number of phandle contained into the property list.

Add also the dev_count_phandle_with_args() based on
ofnode_count_phandle_with_args()

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:08 +02:00
Patrice Chotard
82a8a669b4 clk: add clk_release_all()
Add clk_release_all() method which Disable/Free an
array of clocks that has been previously requested by
clk_request/get_by_*()

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:08 +02:00
Patrice Chotard
3b9d1bdd4e reset: add reset_release_all()
Add reset_release_all() method which Assert/Free an
array of resets signal that has been previously successfully
requested by reset_get_by_*()

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:07 +02:00
Patrice Chotard
9bd5cdf6b6 reset: add reset_request()
This is needed in error path to assert previously deasserted
reset by using a saved reset_ctl reference.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:06 +02:00
Patrice Chotard
f56db163ad usb: host: xhci-dwc3: Add generic PHY support
Add support of generic PHY framework support

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:05 +02:00
Patrice Chotard
b94888b4c0 drivers: phy: add generic_phy_valid() method
This allow to check if a PHY has been correctly
initialised and avoid to get access to phy struct.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-07-28 23:34:05 +02:00
Patrice Chotard
b9688df3cb drivers: phy: Set phy->dev to NULL when generic_phy_get_by_index() fails
phy->dev need to be set to NULL in case of generic_phy_get_by_index()
fails. Then phy->dev can be used to check if the phy is valid

Reported-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:04 +02:00
Patrice Chotard
576e3cc700 usb: host: xhci-dwc3: Add dual role mode support from DT
DWC3 dual role mode is selected using DT "dr_mode"
property. If not found, DWC3 controller is configured
in HOST mode by default

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:03 +02:00
Patrice Chotard
b7c1c7d2ba usb: host: xhci-dwc3: Convert driver to DM
Add Driver Model support with use of generic DT
compatible string "snps,dwc3"

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-28 23:34:02 +02:00
Masahiro Yamada
121a4d13e6 usb: add static to local symbols
Sparse reports "... was not declared. Should it be static?"

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-07-28 23:34:01 +02:00
Simon Glass
32ca40bf8b dm: tegra: Move nyan-big, jetson-tk1/tx1, beaver to livetree
Change these board to use a live device tree after relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:48 -06:00
Simon Glass
f6a4093ba0 fdtdec: Drop old compatible values
These are not needed now since the drivers now use driver model. Drop
them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:48 -06:00
Simon Glass
e3f44f5c89 dm: power: Convert as3722 to driver model
Convert this PMIC driver to driver model and fix up other users. The
regulator and GPIO functions are now handled by separate drivers.

Update nyan-big to work correct. Three boards will need to be updated by
the maintainers: apalis-tk1, cei-tk1-som. Also the TODO in the code re
as3722_sd_set_voltage() needs to be completed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
c2012cb47c power: Add a GPIO driver for the as3722 PMIC
This pmic includes GPIOs which should have their own driver. Add
a driver to support these.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
deea211aec power: Add a regulator driver for the as3722 PMIC
This pmic includes regulators which should have their own driver. Add
a driver to support these.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
68f0081139 dm: tegra: pci: Convert to livetree
Update the tegra pci driver to support a live device tree. Fix the check
for nvidia,num-lanes so that an error will actually be detected.

Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
49cb9308c4 dm: tegra: mmc: Convert to livetree
Update the tegra mmc driver to support a live device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
4b0f21cf50 dm: tegra: pwm: Convert to livetree
Update the tegra pwm driver to support a live device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
d8554d0853 dm: tegra: i2c: Convert to livetree
Update the tegra i2c driver to support a live device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
28a3e5a864 dm: tegra: spi: Convert to livetree
Update the tegra114 spi driver to support a live device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
5ae28c0a60 dm: tegra: usb: Convert to livetree
Update the Tegra EHCI driver to support a live device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
56f5c40ad9 dm: tegra: gpio: Convert to support livetree
Update the GPIO driver to support a live device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
e93812e81c tegra: dts: Move stdout-path to /chosen
This property should be in the /chosen node, not /aliases.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
079ff3b902 dm: video: tegra124: Convert to livetree
Update these drives to support a live device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
000f15fa15 dm: tegra: Convert clock_decode_periph_id() to support livetree
Adjust this to take a device as a parameter instead of a node.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
be7890927a dm: tegra: Convert USB setup to livetree
Adjust this code to support a live device tree. This should be implemented
as a PHY driver but that is left as an exercise for the maintainer.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
66de3eee79 tegra: tegra124: Add a PMC syscon driver
The PMC can be modelled as a syscon peripheral. Add a driver for this
so that it can be accessed by drivers when needed. Enable it for tegra124
boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
9b6b3c1b50 tegra: spl: Enable debug UART
Enable the debug UART in SPL to allow early serial output even if the
standard UART does not work (e.g. due to driver model problem).

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
0f6507a7e4 dm: core: Fix up ofnode_get_addr_index() for 64-bit values
At present this function only supports 32-bit (single-cell) values. Update
it to support two-cell values also.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
dcf988525f dm: core: Add ofnode_read_resource()
We sometimes need to read a resource from an arbitrary node. In any case
for consistency we should not put the live-tree switching code in
a dev_read_...() function. Update this to suit.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Masahiro Yamada
c61d0009fe console: simplify puts()
Current puts() and putc() have similar #ifdef / if() conditionals.
Make puts() iterate over putc() to avoid code duplication.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 12:02:47 -06:00
Masahiro Yamada
47b98ad0f6 sandbox: remove os_putc() and os_puts()
They are unused since commit d8c6fb8ced ("sandbox: Drop special
case console code for sandbox").

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-07-28 12:02:47 -06:00
Masahiro Yamada
fd73621cba dm: ofnode: change return type of dev_read_prop() to opaque pointer
DT property values can be strings as well as integers.  This is why
of_get_property/fdt_getprop returns an opaque pointer.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-07-28 12:02:47 -06:00
Philipp Tomsich
00b26f7cdb dm: Fix typo in include-guard for dm-structs.h
The include-guard for dm-structs.h was misspelled as __DT_STTUCTS.
Change it.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 12:02:47 -06:00
Bin Meng
db13a768a0 cmd: scsi: Fix null pointer dereference in 'scsi reset'
During 'scsi reset', scsi_bus_reset() is called with udevice pointed
to NULL, which causes exception. As a temporary fix, disable the call
for DM SCSI for now.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 12:02:47 -06:00
Bin Meng
9c1390d4b9 dm: ahci: Avoid scsi_scan_dev() in ahci_probe_scsi()
Running 'scsi scan' command causes scsi_scan_dev() to be called,
from which device_probe() is called and consequently AHCI driver
probe routine will be called as SCSI driver's parent, and finally
ahci_probe_scsi() calls scsi_scan_dev() again.

Remove the call to scsi_scan_dev() in ahci_probe_scsi().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 12:02:47 -06:00
Rob Clark
a095aadffa efi_loader: Add an EFI_CALL() macro
Rather than open-coding EFI_EXIT() + callback + EFI_ENTRY(), introduce
an EFI_CALL() macro.  This makes callbacks into UEFI world (of which
there will be more in the future) more concise and easier to locate in
the code.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-28 09:15:45 +02:00
Rob Clark
3f1aa97577 efi_loader: only evaluate EFI_EXIT()'s ret once
There are a couple spots doing things like:

   return EFI_EXIT(some_fxn(...));

which I handn't noticed before.  With addition of printing return value
in the EFI_EXIT() macro, now the fxn call was getting evaluated twice.
Which we didn't really want.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-28 09:14:01 +02:00
Rob Clark
6cfd5f133a efi_loader: add some missing breaks
Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-28 09:13:17 +02:00
Kever Yang
2672233525 rockchip: puma-rk3399: remove duplicate code (merge artifact)
A few lines (defines and declarations) had been duplicated when the
puma-rk3399 board was initially merged.  This removes the duplicates
and changes the style to use local constants instead of pasted
literals.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[fixed up commit-message & converted to use 'const u32':]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:04 +02:00
Andy Yan
86b1122a84 rockchip: add u-boot specific dts for rk3036 sdk
Add this dts to enable debug uart releated devices
before relocation.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:04 +02:00
Andy Yan
77c17f4354 rockchip: use puts instead of printf when back to bootrom
printf will increase the code size more than 1kb, but platform
like rk3036 has no enough space for it.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:04 +02:00
Andy Yan
d26bfa73ed rockchip: enable SPL_LIBGENERIC for rk3036 based boards
function board_init_f_init_reserve will call memset, which
is implemented in lib, and enabled by CONFIG_SPL_LIBGENERIC_SUPPORT
in spl stage.
To reduce the code size, also enable SPL_TINY_MEMSET.
As rk3036 will return to bootrom immediately after dram
initialization, there is no need to run DM, so disable
SPL_DM_SERIAL.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:04 +02:00
Andy Yan
8b154ed61c rockchip: disable SPL_ARCH_MEMCPY/MEMSET for rk3036
RK3036 has no enough sapce use ARCH_MEMCPY/MEMSET in spl stage

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:04 +02:00
Andy Yan
7f38025824 rockchip: set malloc pool size to 0 before relocation in spl state on rk3036 based board
RK3036 only has 4kb sram, the spl code will use
3.4 ~ 3.5 kb, the last 0.5kb are used for SP and
GD, so there is no space for malloc. Also, the spl
will directly return to bootrom after dram initialized,
they never need the space for malloc.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:04 +02:00
Andy Yan
1fc50d727f sandbox: use CONFIG_VAL(SYS_MALLOC_F_LEN) to distinguish malloc pool size before relocation
SPL and normal u-boot stage use different malloc pool size
configuration before relocation, so use CONFIG_VAL(SYS_MALLOC_F_LEN)
to fit different boot stage.

Signed-off-by: Andy Yan <andyshrk@gmail.com>

Changes in v3:
- use CONFIG_VAL(), which suggested by Simon

Changes in v2: None

 arch/sandbox/cpu/start.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:04 +02:00
Andy Yan
9eea50162c microblaze: spl: configure SYS_MALLOC_F_LEN independently for SPL and full U-Boot
Some platforms have very limited SRAM to run SPL code, so there may
not be the same amount space for a malloc pool before relocation in
the SPL stage as the normal U-Boot stage.

Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN,
so the size of pre-relocation malloc pool can be configured memory
space independently.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up commit-message:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:03 +02:00
Andy Yan
2b71d098ee powerpc: spl: configure SYS_MALLOC_F_LEN independently for SPL and full U-Boot
Some platforms have very limited SRAM to run SPL code, so there may
not be the same amount space for a malloc pool before relocation in
the SPL stage as the normal U-Boot stage.

Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN,
so the size of pre-relocation malloc pool can be configured memory
space independently.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up commit-message:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:03 +02:00
Andy Yan
f5868a5da1 mips: spl: configure SYS_MALLOC_F_LEN independently for SPL and full U-Boot
Some platforms have very limited SRAM to run SPL code, so there may
not be the same amount space for a malloc pool before relocation in
the SPL stage as the normal U-Boot stage.

Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN,
so the size of pre-relocation malloc pool can be configured memory
space independently.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up commit-message:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:03 +02:00
Andy Yan
f1896c45cb spl: make SPL and normal u-boot stage use independent SYS_MALLOC_F_LEN
Some platforms have very limited SRAM to run SPL code, so there may
not be the same amount space for a malloc pool before relocation in
the SPL stage as the normal U-Boot stage.

Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN,
so the size of pre-relocation malloc pool can be configured memory
space independently.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up commit-message:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:03 +02:00
Leo Wen
a1903c18db rockchip: firefly: Add "usb start" to auto-start USB device
Add "preboot=usb start" to ROCKCHIP_DEVICE_SETTINGS,you don't
need to input "usb start" in command line of u-boot console,it
can auto-start the USB device,after that usb keyboard can work.

Signed-off-by: Leo Wen <leo.wen@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:03 +02:00
Leo Wen
af83064769 rockchip: firefly: Set the environment variable 'usbkbd' to the stdin
Add the 'usbkbd' environment variable to the 'stdin', the contents of
the keyboard input can be auto-displayed on the serial terminal,so
you don't need to manually set the environment variable 'stdin'.

Signed-off-by: Leo Wen <leo.wen@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:03 +02:00
Leo Wen
73f255b7dc rockchip: firefly: Add some macros to enable the usb keyboard
Add four macros of CONFIG_USB_KEYBOARD,CONFIG_DM_KEYBOARD,etc in the
firefly-rk3288_defconfig,can support usb keyboard device when these four
macros are enabled.

Signed-off-by: Leo Wen <leo.wen@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:03 +02:00
Philipp Tomsich
c0508e427f rockchip: rk3399: enable SPL_SERIAL_SUPPORT and SPL_DRIVERS_MISC_SUPPORT via Kconfig
SPL_SERIAL_SUPPORT and SPL_DRIVERS_MISC_SUPPORT were previously
enabled through rk3399_common.h.  This change implies these options
through Kconfig.

These need to always be active for the RK3399, as follows:
 - SPL_SERIAL_SUPPORT is needed to pass the SPL build
 - SPL_DRIVERS_MISC_SUPPORT is needed to pass the SPL build

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:02 +02:00
Romain Perier
478e6f2e94 rockchip: rk3288: Add support for drive-strength in PINCTRL
Currently, drive-strenght to 12ma are described and supposed to be used
on RK3288. However, the pinctrl driver for this SoC only handles muxing
and pull up/pull down via PU/PD control registers. So complex IPs like
GMAC are working in normal ethernet 100mbps, but not at 1gbps typically.

This commit adds support for handling drive-strength of 12ma, when it's
defined in the DT.

Signed-off-by: Romain Perier <romain.perier@collabora.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:02 +02:00
Kever Yang
42ec247e69 rockchip: use UUID for root partitions
We use to use /dev/mmcbl0p7 as root partition, and pass it
to kernel by cmdline, but the mmc number in kernel in not
fixed, we need to change the bootargs to adapt it from time
to time.
We can use the UUID to fix it, the ID is from:
https://www.freedesktop.org/wiki/Specifications/DiscoverablePartitionsSpec/
ARM 32bit: 69dad710-2ce4-4e3c-b16c-21a1d49abed3
ARM 64bit: b921b045-1df0-41c3-af44-4c6f280d3fae

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:02 +02:00
Philipp Tomsich
4436c5db05 rockchip: dts: rk3399-puma: put EFI partition entries at 2MB
When creating a EFI/GUID partition map for the RK3399-Q7 through
U-Boot, the partition entries should be places at a 1MB offset from
the start of the device to give us space for the environment (at 16KB
on SD/MMC devices), the SPL stage (at 32KB on SD/MMC devices) and the
image payload (at 256KB on SD/MMC devices).

This change sets this up through the u-boot,efi-partition-entries-offset
/config property in the RK3399-Q7 DTSI.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:02 +02:00
Philipp Tomsich
56f580d3eb rockchip: dts: rk3399-puma: put environment (in MMC/SD configurations) before SPL
As our SPL stage can grow quite large (80KB+ are not unusual) on the
RK3399-Q7, the default setting for the environment location (in
include/configs/rockchip-common.h) can overlap our SPL.

This change finally makes use of the 'u-boot,mmc-env-offset' DTS
property to override the environment location and put it at 16KB into
the device, which is right before the SPL (located at 32KB).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:02 +02:00
Philipp Tomsich
01106571ad rockchip: clk: rk3399: remove unused fields from priv-structures
This removes the unused 'rate' field from both rk3399_pmuclk_priv and
rk3399_clk_priv. I didn't bother to check where this came from (i.e.
what the historical context of these was), but only verified that
these are indeed unused across all code-paths.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-27 14:59:02 +02:00
Philipp Tomsich
80c83e8190 rockchip: clk: rk3368: remove unused fields from rk3368_clk_priv
The rk3368_clk_priv has two unused fields: rate, has_bwadj. This
removes them as there's no need for either (i.e. has_bwadj is always
true for the RK3368, according to its TRM).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-27 14:59:02 +02:00
Philipp Tomsich
cdc6080a28 rockchip: clk: rk3368: use correct (i.e. 'rk3368_clk_priv') structure for auto-alloc
The clk driver for the RK3368 picked the wrong data structure's size
for its auto-alloc size: the size was calculated on the structure
representing the CRU hardware block instead of the priv structure.
As the CRU's register file is much larger than the driver's priv,
this did not cause any pain (except wasting memory).

Fix this by using the correct data structure's size.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-27 14:59:02 +02:00
Philipp Tomsich
700f3108d3 rockchip: spl: make boot0 hook TPL safe
When building for a TPL/SPL setup (e.g. on the RK3368), we need the
TPL stage to have the extra space for for the 'Rockchip SPL name'
(i.e. 'RK33' word).  Yet, the SPL will start execution at its first
word (i.e. the first word in the SPL binary needs to be a valid
instruction).  To make things a bit more involved, CONFIG_SPL_BUILD
is defined both for the SPL and the TPL stage.

To avoid having to explicitly test for the first stage (TPL, if and
only if TPL and SPL are built, SPL otherwise), this commit modifies
the sequence to repeat the 'b reset' (instead of reserving 4 bytes
of undefined space) at the start of the boot0 hook: if overwritten
(and execution starts at the second word), the first instruction is
still a 'b reset'... if not overwritten, we start on a 'b reset' as
well.

This solution wouldn't even require the check whether we are in the
SPL/TPL build (i.e. CONFIG_SPL_BUILD), but we leave this check in for
documentation purposes.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-27 14:59:02 +02:00
Kever Yang
06f4e36baf rockchip: pwm: add mask for config setting
Use mask to clear old setting before direct set the new config,
or else there it will mess up the config when it's not the same
with default value.

Fixes: 3851059 rockchip: Setup default PWM flags
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:01 +02:00
Kever Yang
3030c951f1 power: pwm_regulator: remove redundant code
The regulator_enable() should be called from upper layer like
regulators_enable_boot_on(), remove it from pwm regulator driver.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up typo in commit message:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:01 +02:00
Kever Yang
f339bca248 power: pwm_regulator: fix the pwm_set_config parameter order
The rkpwm reg order has fixed by below patch:
e3ef41d rockchip: pwm: fix the register layout for the PWM controller

We need to correct the parameter order for pwm_set_config() to make
the pwm regulator works correctly.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:01 +02:00
Kever Yang
7ba3182e2d rockchip: dts: correct vdd_log setting for firefly-rk3399
Add regulator-init-microvolt for driver to init the regulator,
and the min output value is not 800000mV for the PWM2 io domain has
changed to VCC3V0 instead of VCC1V8 in rockchip evb, we need to
correct it with the value measured when PWM2 output HIGH.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:01 +02:00
Kever Yang
56f2dd0aed rockchip: dts: firefly using ddr3 1600
According to my test, some of firefly-rk3399 hang after dram init
when using ddr3-1333 config, while using ddr3-1600 config works
for all the board I have test.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:01 +02:00
Wadim Egorov
c03635c3d1 rockchip: phycore: Add ID page of M24C32-D EEPROM
The Identification Page (32 byte) is an additional page which can be written
and (later) permanently locked in Read-only mode.

phyCORE-RK3288 SoMs are using this page to describe the module variant.
This page also contains a MAC.

Our boards can be equipped with a different amount of EEPROMs. To make
this more transparent let's add an alias for the eeprom which stores the
module variant.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:01 +02:00
Romain Perier
3641d346ea rockchip: rk3288: Revert MAC_TXCLK in pinctrl for GMAC
This reverts TXCLK toggling that was accidently dropped while reworking
commit 2454b719fb ("rockchip: rk3288: Add pinctrl support for the gmac
ethernet interface"). So the TX clock is enabled and we can use
GMAC_ROCKCHIP in 1Gbps when basic PINCTRL support is enabled
(!PINTRL_FULL).

Fixes: 2454b719fb ("rockchip: rk3288: Add pinctrl support for the...")
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:01 +02:00
Romain Perier
a98fc4325e rockchip: rk3288: Remove phy reset GPIO pull up
We should not handle this pin explicitly from pinctrl. GMAC driver takes
care of it by using a "reset-gpio" in the DT.

This commit removes pull up for GPIO4B0.

Fixes: 2454b719fb ("rockchip: rk3288: Add pinctrl support for the...")
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:01 +02:00
Philipp Tomsich
928979cb2b rockchip: efuse: dm: change to use dev_read_addr
This changes the rockchip-efuse driver to use dev_read_addr instead of
devfdt_get_addr.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:00 +02:00
Philipp Tomsich
cb91173a7f rockchip: timer: make register sizes explicit
We are about to reuse the rockchip timer (header file) for 64bit ARMv8
chips, so it seems a good time to make the register sizes explicit by
changing from 'unsigned int' to 'u32'.

Reorders the header-includes in rk_timer.c to ensure that 'u32' is
definded before it is used by 'asm/arch/timer.h'.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:00 +02:00
Meng Dongyang
0124062853 rockchip: dts: rk3229: add dwc2 node for fastboot
Add dwc2 node for fastboot to init dwc2 controller.

Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:00 +02:00
Rob Clark
a1b24823b6 efi_loader: fix bug in efi_get_memory_map
When booting shim -> fallback -> shim -> grub -> linux the memory map is
a bit larger than the size linux passes in on the first call.  But in
the EFI_BUFFER_TOO_SMALL case we were not passing back the updated size
to linux so it would loop forever.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-26 22:09:49 +02:00
Tom Rini
f19955a014 Merge git://git.denx.de/u-boot-uniphier 2017-07-26 11:29:25 -04:00
Tom Rini
0ddc9c1722 Merge git://git.denx.de/u-boot-mips 2017-07-26 11:29:20 -04:00
Bin Meng
dc5210a20d MAINTAINERS: Update maintainer for x86
This adds myself as one of the x86 maintainers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-26 11:29:16 -04:00
Tom Rini
25fa0b930f FIT: List kernel_noload in the list of types
In the source_file_format.txt file we talk about how to construct a
valid FIT image.  While it already says to look at the source for the
full list, add kernel_noload to the explicit list of types.  This is
arguably the most important type to use as most often we are including a
kernel that will run from wherever it is loaded into memory and execute.

This for example, allows you to create a single FIT image for Linux that
can be used on both OMAP and i.MX devices as the kernel will not need to
be moved in memory.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-26 11:29:15 -04:00
Patrice Chotard
7016651eac ram: stm32: add stm32h7 support
STM32F7 and H7 shared the same SDRAM control block.
On STM32H7 few control bits has been added.
The current driver need some minor adaptation as FMC block
enable/disable for H7.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-07-26 11:29:15 -04:00
Patrice Chotard
4eefb0070d ARM: DTS: stm32: remove useless mr-nbanks property
FMC driver is now able to discover the bank number by
parsing bank subnodes.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-26 11:29:15 -04:00
Patrice Chotard
f303aaf21b ram: stm32: add second SDRAM bank management
FMC is able to manage 2 SDRAM banks, but the current driver
implementation is only able to manage the first SDRAM bank.

Even if only bank2 is used, some bank1 registers must be
configured.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-26 11:29:15 -04:00
Patrice Chotard
f39b90dc8c ram: stm32: replace fdtdec_get by ofnode calls
Replace all fdtdec_get..() calls by ofnode_read...() or dev_read..().
This will allow drivers to support a live device tree.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-26 11:29:14 -04:00
Patrice Chotard
1421e0a375 ram: stm32: get base address from DT
Retrieve RAM base address from DT instead of using STM32_SDRAM_FMC

For STM32F7, FMC block base address is 0xA0000000, but SDRAM
registers are located at offset 0x140 inside FMC block.
Update the stm32_fmc_regs fields with all FMC registers
to map SDRAM registers at the right address.

These additionals registers will be used later.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-07-26 11:29:14 -04:00
Patrice Chotard
9242ece12b ram: stm32: migrate fmc defines in driver file
Migrate all FMC defines from arch/arm/include/asm/arch-stm32f7/fmc.h
to drivers/ram/stm32_sdram.c

This will avoid to add an additionnal arch-stm32xx/fmc.h file when
a new stm32 family soc will be introduced.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-26 11:29:07 -04:00
Patrice Chotard
81d0128d2b clk: stm32f7: remove clock_get()
All drivers which was using clock_get() are now using
clk_get_rate() from clock framework, now it's safe to
remove clock_get().

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26 11:28:08 -04:00
Patrice Chotard
541cd6e54e spi: stm32_qspi: add clk_get_rate() support
Replace proprietary clock_get() by clk_get_rate()
The stm32_qspi is now "generic" and can be used
by other STM32 SoCs.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26 11:28:08 -04:00
Patrice Chotard
27265cee76 serial: stm32x7: add clk_get_rate() support
Replace proprietary clock_get() by clk_get_rate()
The stm32x7 serial driver is now "generic" and can be used
by other STM32 SoCs.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26 11:28:08 -04:00
Patrice Chotard
122b2d4763 serial: stm32x7: migrate serial struct to driver
This allow to remove include/dm/platform_data/serial_stm32x7.h
which was included in the past by stm32x7 driver and by
stm32f746-disco.c board file.
Since patch 42bf5e7c27 "serial: stm32f7: add device tree support"
this file is no more needed in board file.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26 11:26:54 -04:00
Patrice Chotard
b9e86511d1 clk: stm32f7: cleanup clocks unused definitions
clean the code by removing unused enums, structs and
defines related to clocks

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26 11:26:54 -04:00
Patrice Chotard
288f17e648 clk: stm32f7: add clock .get_rate() callback
Add clock framework .get_rate callback.
This step will allow to convert all drivers which was using
proprietary clock_get() to use clock framework .get_rate().

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26 11:26:53 -04:00
Patrice Chotard
199a2178fe clk: stm32f7: get RCC base address from DT
Retrieve RCC base address from DT, this will prepare
the ground for future STM32 SoCs support.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26 11:26:53 -04:00
Patrice Chotard
704e954cee clk: stm32f7: add static for configure_clocks()
Also remove its declaration from stm32.h which
is no more needed.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26 11:26:53 -04:00
Patrice Chotard
fa87abb6b6 ARM: DTS: stm32: align DT clock declaration with kernel
Use the same clocks macro than the one used by kernel DT.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26 11:26:52 -04:00
Srinivas, Madan
94f536fc4f arm: mach-keystone: Fixes issue with return values in inline assembly
The inline assembly functions in mon.c assume that the caller will
check for the return value in r0 according to regular ARM calling
conventions.

However, this assumption breaks down if the compiler inlines the
functions. The caller is then under no obligation to use r0 for the
result.

To fix this disconnect, we must explicitly move the return value
from the smc/bl call to the variable that the function returns.

Signed-off-by: Madan Srinivas <madans@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-26 11:26:52 -04:00
Madan Srinivas
1a7c159a8d configs: ti: armv7: Fixes bug in fit_loadaddr for ramfs boot
The load address of ramdisk, rdaddr is 0x88080000 and fit_loadaddr
is defined as 0x88000000. This leaves only 512Kbytes for the
fit image. When the FIT images are larger than this, it will
overwite the ramdisk and cause the boot to fail.

For eg, The K2 HS fit images are a few MB and end up overwriting
the ramdsk. This patch moves the fit_loadaddr to 0x87000000,
leaving a 16MB window for the fit image. This memory can be
reclaimed once the kernel starts running.

Signed-off-by: Madan Srinivas <madans@ti.com>
2017-07-26 11:26:51 -04:00
Madan Srinivas
1d73ce6f68 arm: mach-keystone: Updates mon_install for K2G HS
On early K2 devices (eg. K2HK) the secure ROM code does not support
loading secure code to firewall protected memory, before decrypting,
authenticating and executing it.

To load the boot monitor on these devices, it is necessary to first
authenticate and run a copy loop from non-secure memory that copies
the boot monitor behind firewall protected memory, before decrypting
and executing it.

On K2G, the secure ROM does not allow secure code executing from
unprotected memory. Further, ROM first copies the signed and encrypted
image into firewall protected memory, then decrypts, authenticates
and executes it.

As a result of this, we cannot use the copy loop for K2G. The
mon_install has to be modified to pass the address the signed and
encrypted secure boot monitor image to the authentication API.

For backward compatibility with other K2 devices and K2G GP,
the mon_install API still supports a single argument. In this case
the second argument is set to 0 by u-boot and is ignored by ROM

Signed-off-by: Thanh Tran <thanh-tran@ti.com>
Signed-off-by: Madan Srinivas <madans@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-26 11:26:51 -04:00
Andrew F. Davis
3f5651a724 configs: k2x_evm: Reorder default boot command
We first split the CONFIG_BOOTCOMMAND into its components to improve
readability. We then make the following order changes:

 - Run findfdt first so the fdt name can be used in envboot like OMAP
 - Install the boot monitor before running the PMMC so we can make any
     needed secure changes before PMMC, do this on both HS and non-HS
 - Move set_name_pmmc to just before get_pmmc_${boot}

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-26 11:26:50 -04:00
Madan Srinivas
08d06310f4 configs: k2x_evm: Adds environment variables for secure devices
Updates the default u-boot environment variables to support secure
boot. On secure devices, a secure boot monitor (sec-bm) needs to
be installed by u-boot.

Signed-off-by: Madan Srinivas <madans@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-26 11:26:50 -04:00
Andrew F. Davis
881261c82e configs: k2x_evm: Adds FIT loading environment variables
Updates the default u-boot environment variables to support FIT image
loading.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-26 11:26:50 -04:00
Lokesh Vutla
f70a427268 board: ti: x15: Add support for beagle_X15 revC
BeagleBoard X15 revC board is similar to X15 revB1 except
with a SR2.0 where revB1 uses a SR1.1. Add board detection
support for revC.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-26 11:26:49 -04:00
Lokesh Vutla
7087922477 board: ti: am57xx: Fix detection of board version
board_is*("rev", board_ti_get_rev()) uses strncmp() for
revison detection and assumes it is success if return value
is <= 0. This will fail in case of multiple versions, as
revb will be true for board_is_*revb() and board_is_*reva().
Fix it by looking for exact match of the string.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-26 11:26:49 -04:00
Beniamino Galvani
9cb1c49afb odroid-c2: enable GPIO
GPIOs are now supported on Meson GXBB, enable driver and command in
the config.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-26 11:26:49 -04:00
Beniamino Galvani
2009a8d03f pinctrl: meson: add GPIO support
This commit adds GPIO support to the Amlogic Meson pin controller
driver, based on code from Linux kernel.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
2017-07-26 11:26:48 -04:00
Beniamino Galvani
4a63a75c83 arm: dts: meson: import dts files from Linux 4.12
Import Amlogic Meson DTS files from Linux kernel version 4.12

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-26 11:26:48 -04:00
Masahiro Yamada
a3f54bc74f ARM: uniphier: enable CONFIG_CMD_FS_GENERIC
Enable file system commands such as load, ls.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-07-26 22:27:15 +09:00
Masahiro Yamada
b8faf5f12b ARM: uniphier: remove part number info from the boot log
As is often the case with SoC development, slightly different
products (i.e. different part number) are developed based on the
same silicon-die.  Such fine grained information is unmaintainable.

Also, "SoC:" is a better fit that "CPU:".

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-07-26 22:27:15 +09:00
Masahiro Yamada
673ac334fc doc: uniphier: rework README.uniphier
Rework the readme to reflect the latest boot mechanism on ARMv8 SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-07-26 22:27:15 +09:00
Masahiro Yamada
ee8d037ce7 ARM: uniphier: remove SPL support for ARMv8 SoCs
It has been a while since ARM Trusted Firmware supported UniPhier SoC
family.  U-Boot SPL was intended as a temporary loader that runs in
secure world.  It is a maintenance headache to support two different
boot mechanisms.  Secure firmware is realm of ARM Trusted Firmware
and now U-Boot only serves as a non-secure boot loader for UniPhier
ARMv8 SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-07-26 22:27:15 +09:00
Alexander Graf
f4f9993f7e efi_loader: Fix configuration table override
Before commit 7cbc12415d ("efi_loader: initalize EFI object list
only once") we recreated the world on every bootefi invocation.

That included the object tree as well as the configuration tables.

Now however we don't recreate them, which means we must not explicitly
override the configuration tables, as otherwise we may lose our SMBIOS
table from the configuration table list on second bootefi invocation.

This patch makes bootefi call our normal configuration table modification
APIs to add/remove the FDT instead of recreating all tables from scratch.
That way the SMBIOS table gets preserved across multiple invocations.

Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-26 15:24:47 +02:00
Alexander Graf
d98cdf6a92 efi_loader: Improve install_configuration_table
The INSTALL_CONFIGURATION_TABLE callback also provides the ability to
remove table entries. This patch adds that functionality.

Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-26 15:23:54 +02:00
Tien Fong Chee
9af91b7c40 arm: socfpga: Enable all FPGA config support for Arria 10
Enable all FPGA config support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-07-26 10:31:44 +02:00
Tien Fong Chee
2baa997240 arm: socfpga: Add FPGA driver support for Arria 10
Add FPGA driver support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-07-26 10:31:44 +02:00
Tien Fong Chee
812dfdd4f7 configs: Add FPGA driver config for Arria 10
Add FPGA driver config for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-07-26 10:31:44 +02:00
Tien Fong Chee
386c65e556 drivers: Enable FPGA driver build on SPL
Enable FPGA driver build for Arria 10 SPL because FPGA driver is
needed by Arria 10 SPL to configure and getting DDR up before
loading U-boot into DDR and booting from there.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-07-26 10:31:44 +02:00
Tien Fong Chee
fa23ba1aa5 kconfig: Convert FPGA_SOCFPGA configuration to Kconfig
This converts the following to Kconfig:
   CONFIG_FPGA_SOCFPGA

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-07-26 10:31:44 +02:00
Tien Fong Chee
c2caaee73e kconfig: Convert FPGA and FPGA_ALTERA configuration to Kconfig
This converts the following to Kconfig:
   CONFIG_FPGA
   CONFIG_FPGA_ALTERA

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-07-26 10:31:44 +02:00
Tien Fong Chee
6867e19a43 arm: socfpga: Restructure FPGA driver in the preparation to support A10
Move FPGA driver which is Gen5 specific code into Gen5 driver file
and keeping common FPGA driver intact. All the changes are still keeping
in driver/fpga/ and no functional change. Subsequent patch would move
FPGA manager driver from arch/arm into driver/fpga/.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-07-26 10:31:44 +02:00
Tien Fong Chee
6a34af5b41 arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset
Remove parameter from socfpga_bridges_reset(), and keeping this function
for single purpose which is just triggering reset on bridges.
socfpga_reset_deassert_bridges_handoff() can be called for releasing reset
on any bridges based on the bridge setting defined in fdt.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-07-26 10:31:43 +02:00
Rob Clark
3304990ba4 efi_loader: remove more double EFI_EXIT() in efi_disk.c
Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-26 08:56:15 +02:00
Rob Clark
b5104821c1 efi_loader: remove double EFI_EXIT() with efi_unsupported
Probably this went unnoticed before, but it causes problems with
addition of 804b1d73 ("efi_loader: log EFI return values too")

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-26 08:56:03 +02:00
Simon Glass
609bf92411 Convert CONFIG_ENV_IS_IN_ONENAND to Kconfig
This converts the following to Kconfig:
   CONFIG_ENV_IS_IN_ONENAND

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-25 21:34:39 -04:00
Simon Glass
b31e065f89 Convert CONFIG_ENV_IS_IN_FAT to Kconfig
This converts the following to Kconfig:
   CONFIG_ENV_IS_IN_FAT

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-25 21:34:15 -04:00
Simon Glass
337cd3f211 Convert CONFIG_ENV_IS_IN_REMOTE to Kconfig
This converts the following to Kconfig:
   CONFIG_ENV_IS_IN_REMOTE

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-25 21:33:22 -04:00
Simon Glass
91c868fe7c Convert CONFIG_ENV_IS_IN_SPI_FLASH to Kconfig
This converts the following to Kconfig:
   CONFIG_ENV_IS_IN_SPI_FLASH

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-25 21:31:03 -04:00
Simon Glass
ef6253d7b3 Convert CONFIG_ENV_IS_IN_DATAFLASH to Kconfig
This converts the following to Kconfig:
   CONFIG_ENV_IS_IN_DATAFLASH

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-25 21:24:09 -04:00
Simon Glass
f0bc2b542b Convert CONFIG_ENV_IS_IN_EEPROM to Kconfig
This converts the following to Kconfig:
   CONFIG_ENV_IS_IN_EEPROM

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-25 21:22:56 -04:00
Simon Glass
88b233a347 Convert CONFIG_ENV_IS_IN_NVRAM to Kconfig
This converts the following to Kconfig:
   CONFIG_ENV_IS_IN_NVRAM

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-25 21:21:24 -04:00
Simon Glass
85fc970d74 Convert CONFIG_ENV_IS_IN_FLASH to Kconfig
This converts the following to Kconfig:
   CONFIG_ENV_IS_IN_FLASH

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-25 21:20:02 -04:00
Simon Glass
e73496d08e env: Move help from README to Kconfig
The CONFIG_ENV_IS_IN_... options which have already been converted to
Kconfig only have a small amount of help. Move the rest of it over from
the README.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-25 21:08:07 -04:00
Simon Glass
2be296538e Convert CONFIG_ENV_IS_IN_MMC/NAND/UBI and NOWHERE to Kconfig
This converts the following to Kconfig:
   CONFIG_ENV_IS_IN_MMC
   CONFIG_ENV_IS_IN_NAND
   CONFIG_ENV_IS_IN_UBI
   CONFIG_ENV_IS_NOWHERE

In fact this already exists for sunxi as a 'choice' config. However not
all the choices are available in Kconfig yet so we cannot use that. It
would lead to more than one option being set.

In addition, one purpose of this series is to allow the environment to be
stored in more than one place. So the existing choice is converted to a
normal config allowing each option to be set independently.

There are not many opportunities for Kconfig updates to reduce the size of
this patch. This was tested with

   ./tools/moveconfig.py -i CONFIG_ENV_IS_IN_MMC

And then manual updates.  This is because for CHAIN_OF_TRUST boards they
can only have ENV_IS_NOWHERE set, so we enforce that via Kconfig logic
now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-25 21:08:01 -04:00
Paul Burton
e94136bd87 mips-relocs: Fix warning from gcc 6.3
It seems that gcc 6.3 at least is smart enough to warn about the _val
variable being unassigned in the default case in the set_hdr_field()
macro, but not smart enough to figure out that the default case is never
taken. This results in warnings such as the following:

  pfx##hdr32[idx].field = _val;   \
                          ^
 ../tools/mips-relocs.c:51:11: note: _val was declared here
   uint64_t _val;      \
            ^
 ../tools/mips-relocs.c:88:2: note: in expansion of macro set_hdr_field
   set_hdr_field(p, idx, field, val)
   ^~~~~~~~~~~~~
 ../tools/mips-relocs.c:408:3: note: in expansion of macro set_phdr_field
    set_phdr_field(i, p_filesz, load_sz);
    ^~~~~~~~~~~~~~
 ../tools/mips-relocs.c: In function main:
 ../tools/mips-relocs.c:77:25: warning: _val may be used uninitialized
    in this function [-Wmaybe-uninitialized]

Avoid this by assigning _val = 0 in the default case, and asserting that
we didn't actually hit it for good measure.

For reference gcc 7.1.1 seems to be smart enough to not hit the above
warning without this patch.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fixes: 011dd93ca97a ("MIPS: Stop building position independent code")
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: u-boot@lists.denx.de
2017-07-25 20:44:38 +02:00
Zubair Lutfullah Kakakhel
48bfc31b64 MIPS: bootm: Fix broken boot_env_legacy codepath
This patch fixes 2 bugs introduced by the following commit

2bb5b63 MIPS: bootm: rework and fix broken bootm code

The CONFIG_IS_ENABLED macro prepends 'CONFIG_' Hence, remove CONFIG_
from CONFIG_MIPS_BOOT_ENV_LEGACY usage.

Also, 2bb5b63 reworks bootm so that linux_env_legacy runs before
linux_cmdline_legacy. However, linux_env_legacy depends on
linux_cmdline_legacy running first as linux_cmdline_init initialilzes
linux_argp which linux_env_legacy later depends on during its
initialization.

Reorder the code so that linux_cmdline_legacy runs before
linux_env_legacy.

Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
2017-07-25 20:44:00 +02:00
Paul Burton
703ec9ddf9 MIPS: Stop building position independent code
U-Boot has up until now built with -fpic for the MIPS architecture,
producing position independent code which uses indirection through a
global offset table, making relocation fairly straightforward as it
simply involves patching up GOT entries.

Using -fpic does however have some downsides. The biggest of these is
that generated code is bloated in various ways. For example, function
calls are indirected through the GOT & the t9 register:

  8f998064   lw     t9,-32668(gp)
  0320f809   jalr   t9

Without -fpic the call is simply:

  0f803f01   jal    be00fc04 <puts>

This is more compact & faster (due to the lack of the load & the
dependency the jump has on its result). It is also easier to read &
debug because the disassembly shows what function is being called,
rather than just an offset from gp which would then have to be looked up
in the ELF to discover the target function.

Another disadvantage of -fpic is that each function begins with a
sequence to calculate the value of the gp register, for example:

  3c1c0004   lui    gp,0x4
  279c3384   addiu  gp,gp,13188
  0399e021   addu   gp,gp,t9

Without using -fpic this sequence no longer appears at the start of each
function, reducing code size considerably.

This patch switches U-Boot from building with -fpic to building with
-fno-pic, in order to gain the benefits described above. The cost of
this is an extra step during the build process to extract relocation
data from the ELF & write it into a new .rel section in a compact
format, plus the added complexity of dealing with multiple types of
relocation rather than the single type that applied to the GOT. The
benefit is smaller, cleaner, more debuggable code. The relocate_code()
function is reimplemented in C to handle the new relocation scheme,
which also makes it easier to read & debug.

Taking maltael_defconfig as an example the size of u-boot.bin built
using the Codescape MIPS 2016.05-06 toolchain (gcc 4.9.2, binutils
2.24.90) shrinks from 254KiB to 224KiB.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tested-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2017-07-25 20:44:00 +02:00
Paul Burton
09bebb8397 Makefile: Allow arch post-link hook
This commit allows an architecture to provide a Makefile.postlink whose
u-boot target gets invoked after the u-boot ELF is linked. This will be
of use for MIPS in a following commit.

This mirrors Linux commit fbe6e37dab97 ("kbuild: add arch specific
post-link Makefile").

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: u-boot@lists.denx.de
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tested-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2017-07-25 20:44:00 +02:00
Tom Rini
5785e51940 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-25 13:52:46 -04:00
Rob Clark
a17e62cc53 efi_loader: expose protocols via GUID
shim.efi (or rather gnu-efi's LibLocateProtocol() which shim.efi uses)
resolves protocols via efi_locate_handle() so the console protocols
need to be added to the efi object list.

Signed-off-by: Rob Clark <robdclark@gmail.com>
[agraf: whitespace fixes]
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-25 10:58:07 +02:00
Rob Clark
641833db4a efi_loader: add helper macro to construct protocol objects
There are a bunch of protocols which should be exposed by GUID but are
not.  Add a helper macro to create an efi_object, to avoid much typing.

Note that using the pointer for efiobj->handle is semi-arbitrary.  We
just need a unique value to match the efiobj supporting the protocol
with the handle that LocateHandle() returns..

See LibLocateProtocol() in gnu-efi.  It does LocateHandle() to find all
the handles, and then loops over them calling HandleProtocol() with the
GUID of the protocol it is trying to find.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-25 10:55:51 +02:00
Rob Clark
804b1d737a efi_loader: log EFI return values too
Turns out this is rather useful to tracking down where things fail.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-25 10:29:46 +02:00
xypron.glpk@gmx.de
c0ebfc8664 efi_loader: implement ProtocolsPerHandle
Boot service ProtocolsPerHandle is implemented in
efi_protocols_per_handle.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-25 10:03:50 +02:00
Tom Rini
d56b4b1974 configs: Migrate RBTREE, LZO, CMD_MTDPARTS, CMD_UBI and CMD_UBIFS
The above CONFIG options are in Kconfig, and now have correct depends and
inter-dependencies.  Migrate these to configs/ from include/configs/.  In the
case of CMD_UBIFS also change it to be a default y if CMD_UBI.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-24 20:35:55 -04:00
xypron.glpk@gmx.de
b521d29eb1 efi_loader: parameter types for CreateEvent, SetTimer
The first argument 'type' of CreateEvent is an 32bit unsigned
integer bitmap and not an enum.

The second argument 'type' of SetTimer take values of an
enum which is called EFI_TIMER_DELAY in the UEFI standard.
To avoid confusion rename efi_event_type to efi_timer_delay.

Reported-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-24 14:54:29 +02:00
Heinrich Schuchardt
7cbc12415d efi_loader: initalize EFI object list only once
If several EFI applications are executed in sequence we want
to keep the content of the EFI object list.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-24 14:53:32 +02:00
xypron.glpk@gmx.de
ff925938c8 efi_console: use EFIAPI for callback functions
The call to efi_create_event requires notification functions
flagged as EFIAPI.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-24 14:48:09 +02:00
Rob Clark
661c8327a6 efi_loader: workaround for grub lsefi bug
Patch has also been sent to fix grub to not ignore the error returned
and treat protocol_buffer_count as valid.  But that that might take a
while to trickle into distro's, so this workaround might be useful.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-24 14:47:36 +02:00
xypron.glpk@gmx.de
09c5ab909c efi_loader: implement ConvertDeviceNodeToText
Move the logic for converting a node to text from
efi_convert_device_path_to_text to convert_device_node_to_text.

Provide a wrapper function convert_device_node_to_text_ext.

As we use only shallow device paths so we can call
directly call efi_device_node_to_text from efi_device_path_to_text.

Add output for MAC addresses.

Add output for not yet supported types/subtypes.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-24 14:47:04 +02:00
xypron.glpk@gmx.de
c6e3c3e68a efi_memory: return MapKey
efi_get_memory_map should set a defined value for map_key.

We later can introduce the test against this value in
efi_exit_boot_services as required by the UEFI standard.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-24 14:46:13 +02:00
xypron.glpk@gmx.de
0ecba5db85 efi_memory: do parameter checks first
The parameter checks should be done first.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-24 14:46:01 +02:00
Rob Clark
ca9193d2b1 efi_loader: gop: fixes for CONFIG_DM_VIDEO without CONFIG_LCD
Make EFI GOP support work with DM_VIDEO but without legacy LCD.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-24 14:43:40 +02:00
Rob Clark
3e094c592b efi_loader: move guidcmp to header
Want to re-use this for file protocol, which I'm working on.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-24 14:38:21 +02:00
Rob Clark
3e433e9608 efi_loader: EFI file paths should be DOS style
shim.efi, for example, actually tries to parse this, but is expecting
backslashes.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-24 14:33:32 +02:00
Karl Beldan
24fc9531a1 cmd: Kconfig: Fix CMD_UBIFS dependencies
Remove the ARCH_SUNXI and RBTREE dependencies.
CMD_UBIFS already gets RBTREE from CMD_UBI (from MTD_UBI), and should
the first become independant from the latter, there would likely be a
dependency on MTD_UBI anyway.

Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Jagan Teki <jagan@openedev.com>
Signed-off-by: Karl Beldan <karl.beldan-ext@sagemcom.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-24 07:33:34 -04:00
Karl Beldan
22cf953a40 cmd: Kconfig: Make CMD_UBI select CMD_MTDPARTS
Many configs still define CMD_MTDPARTS in their non-Kconfig but
CMD_MTDPARTS has now moved to Kconfig.

Signed-off-by: Karl Beldan <karl.beldan-ext@sagemcom.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-24 07:33:34 -04:00
Karl Beldan
f8dc5a0f9b ubi: Kconfig: Make MTD_UBI select MTD_PARTITIONS
This missing dependency has probably remained under the radar because
MTD_PARTITIONS is still whitelisted.

Signed-off-by: Karl Beldan <karl.beldan-ext@sagemcom.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-24 07:33:34 -04:00
Karl Beldan
b2237a4f5d cmd: Kconfig: Fix a dependency of CMD_MTDPARTS
Remove the ARCH_SUNXI dependency.

Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Jagan Teki <jagan@openedev.com>
Signed-off-by: Karl Beldan <karl.beldan-ext@sagemcom.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-24 07:33:33 -04:00
Karl Beldan
fc94f209a8 ubi: Kconfig: Fix MTD_UBI selection dependency
Remove the ARCH_SUNXI dependency on selection of RBTREE.

Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Jagan Teki <jagan@openedev.com>
Signed-off-by: Karl Beldan <karl.beldan-ext@sagemcom.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-24 07:33:33 -04:00
Tom Rini
92c05d9d6c xilinx-ppc.h: Drop
With PowerPC 4xx support removed, we have removed xilinx-ppc support as
well, remove this file now.

Fixes 98f705c9ce ("powerpc: remove 4xx support")
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-23 17:04:50 -04:00
Stefan Roese
6822cf3ec7 serial: ns16550: Add RX interrupt buffer support
Pasting longer lines into the U-Boot console prompt sometimes leads to
characters missing. One problem here is the small 16-byte FIFO of the
legacy NS16550 UART, e.g. on x86 platforms.

This patch now introduces a Kconfig option to enable RX interrupt
buffer support for NS16550 style UARTs. With this option enabled, I was
able paste really long lines into the U-Boot console, without any
characters missing.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
[trini: Guard ns16550_serial_remove with
CONFIG_IS_ENABLED(SERIAL_PRESENT) to match struct assignment]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-23 17:04:46 -04:00
Adam Ford
c3bec5478f arm: omap3: Detect boot mode very early
Fixes 4bd754d8ab ("arm: omap: Detect boot mode very early") where
the intent was to store the boot params information in a known
location and pass it to SPL very early. Unfortunately it didn't
account for OMAP3 boards.

This patch adds adds this functionality back into OMAP3 boards.

Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
2017-07-23 09:24:47 -04:00
Christophe Leroy
72281c5c46 powerpc: Remove 8260 remainders
commit 2eb48ff7a2 ("powerpc, 8260: remove support for mpc8260")
removed support for 8260 CPU.

This patch remove some remainders.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2017-07-23 09:24:47 -04:00
Christophe Leroy
08dd988be5 powerpc, 8xx: fix missing function declarations.
Add missing .h and add missing declarations in .h
Declare local functions as static.  Make interrupt_init_cpu function
signatures consistent with how decrementer_count is declared.

Based on warnings reported by 'make C=2'

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
[trini: drop cpu_init_f as 8xx/83xx are different from the rest, rework
interrupt_init_cpu/decrementer_count]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-23 09:23:29 -04:00
Christophe Leroy
ba2c5a5c9d powerpc: move get_pvr() and get_svr() into C
Avoid unnecessary assembly functions when they can easily be written
in C.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2017-07-22 22:22:51 -04:00
Christophe Leroy
506cb8be7e powerpc, 8xx: move cache helper into C
Avoid unnecessary assembly functions when they can easily be written
in C.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2017-07-22 22:22:51 -04:00
Christophe Leroy
7fd697fd54 powerpc, 8xx: move get_immr() into C
Avoid unnecessary assembly functions when they can easily be written
in C.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2017-07-22 22:22:50 -04:00
Christophe Leroy
1e7cefef58 powerpc, 8xx: Move cache function into C files
Avoid unnecessary assembly functions when they can easily be written
in C.

Also remove dc_read() as it is nowhere referenced

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2017-07-22 22:22:50 -04:00
Christophe Leroy
36d3260756 powerpc, 8xx: Simplifying check_CPU()
All complex case have been removed and we now only support
MPC866 and MPC885 families.

So check_CPU() can be made a lot simpler.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2017-07-22 22:22:50 -04:00
Christophe Leroy
f3603b4382 powerpc: Remove unneccessary #ifdefs in reginfo
reginfo command is calling mpc8xx_reginfo(), mpc85xx_reginfo()
or mpc86xx_reginfo() based on CONFIG_ symbol.
As those 3 functions can't me defined at the same time, let's
rename them print_reginfo() to avoid the #ifdefs
The name is kept generic as it is not at all dependent on
powerpc arch and any other arch could want to also print
such information.

In addition, as the Makefile compiles cmd/reginfo.c only when
CONFIG_CMD_REGINFO is set, there is no need to enclose the U_BOOT_CMD
definition inside a #ifdef CONFIG_CMD_REGINFO

Lets all remove the #ifdefs around the U_BOOT_CMD as this
file is only compiled when CONFIG_CMD_REGINFO is defined

Finally, this is a PowerPC-only command, disable it on a number of
non-PowerPC platforms.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-22 22:22:49 -04:00
Christophe Leroy
f1cd73674f powerpc: move set_msr() and get_msr() into .h
set_msr() and get_msr() are defined and used twice.
This patch moves them into ppc.h

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2017-07-22 22:22:49 -04:00
Christophe Leroy
f0eda3cb89 power, timer: reset TBL before TBU
In order to avoid TBU increment due to TBL reaching its max
and wrapping, reset TBL before resetting TBU

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2017-07-22 22:22:48 -04:00
Christophe Leroy
93e85d02b2 powerpc, timer: Does 8xx specific actions in 8xx cpu_init
The actions inside #ifdef CONFIG_8xx in arch/powerpc/lib/time.c
can be performed before, in a 8xx dedicated function.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2017-07-22 22:22:48 -04:00
Christophe Leroy
0819450fdd powerpc: get rid of addr_probe()
This function has never been used, at least since the beginning
of the git repository

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2017-07-22 22:22:48 -04:00
Christophe Leroy
7a0a550c7f powerpc, 8xx: Simplify brgclk calculation and remove get_brgclk()
divider is calculated based on SCCR_DFBRG, with:
SCCR_DFBRG 00 => divider 1  = 1 << 0
SCCR_DFBRG 01 => divider 4  = 1 << 2
SCCR_DFBRG 10 => divider 16 = 1 << 4
SCCR_DFBRG 11 => divider 64 = 1 << 6

This can be easily converted to a single shift operation:
divider = 1 << (SCCR_DFBRG * 2)

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2017-07-22 22:22:47 -04:00
Holger Brunck
b2f2c7be34 km/ivm: allow to set locally administred MAC addresses
It is possible to flag MAC addresses as locally administred. In this
case they don't need to be unique. This is only allowed for interfaces
which have no connection to the outside. For the TEGR1 board we use
this feature.

Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
2017-07-22 22:22:47 -04:00
Holger Brunck
b63d4f34d0 km/ivm: always set ethaddr after reading IVM
If we rebrand the IVM and ethaddr was set previously we need to change
ethaddr. Otherwise we end up with a wrong MAC adress for the ethernet
interface.

Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
2017-07-22 22:22:46 -04:00
Simon Glass
6821a7457c RFC: moveconfig: Use toolchains from buildman
It is annoying to have to set up and maintain two sets of toolchains, one
for buildman and one for moveconfig.

Adjust moveconfig to make use to buildman's toolchains. This should make
things easier.

One missing feature is the ability to specify the toolchain on the command
line with a special environment variable, e.g. CROSS_COMPILE_ARM. I'm not
sure if that is useful, but if it is it could be implemented in buildman.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-22 22:22:46 -04:00
Simon Glass
dee36c74ea moveconfig: Tidy up imply flag parsing
Add an option to specify 'all' to enable all flags. Also print an error
if an unrecognised flag is used. At present it just prints usage
information which is not very helpful.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-22 22:22:46 -04:00
Andrew F. Davis
7fe463f54f board: ti: am43xx: Add FDT fixup for HS devices
Disable RNG and add TEE to FDT used on HS devices.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2017-07-22 22:22:45 -04:00
Andrew F. Davis
3630094cf9 board: ti: am43xx: Add TEE loading and firewall setup
Add support for loading a TEE and setting up firewalled regions to
AM43xx HS boards.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2017-07-22 22:22:45 -04:00
Andrew F. Davis
ddf013458d arm: mach-omap2: am33xx: Add FDT fixup suport for AM33xx/AM43xx boards
Similar to what is done with OMAP5 class boards we need to
perform fixups common to this SoC class, add support for this here
and add HS fixups.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2017-07-22 22:22:44 -04:00
Andrew F. Davis
137ae0c4b1 arm: mach-omap2: fdt-common: Add OP-TEE node when firmware node is defined
If a firmware node is already present in the FDT we will fail to create
one and so fail to add our OP-TEE node, make this fixup first check for
a firmware node and then only try to add one if it is not found.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2017-07-22 22:22:44 -04:00
Andrew F. Davis
03750231a8 arm: mach-omap2: Factor out common FDT fixup suport
Some of the fixups currently done for OMAP5 class boards are common to
other OMAP family devices, move these to fdt-common.c.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2017-07-22 22:22:43 -04:00
Andrew F. Davis
3348e0c0a6 arm: mach-omap2: Move omap5/sec-fxns.c into sec-common.c
TEE loading and firewall setup are common to all omap2 devices, move
these function out of omap5 and into mach-omap2. This allows us
to use these functions from other omap class devices.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2017-07-22 22:22:42 -04:00
Philipp Tomsich
0d982c5853 Makefile: add dependencies to regenerate u-boot.cfg when lost
When running a 'make clean' or carelessly removing u-boot.cfg, all
future make invocations (until autoconf is regenerated) will print
an error for a missing u-boot.cfg due to missing rules and dependencies.

This commit adds (i) an explicit rule dependency from all (which will
invokes the configuration checker) to cfg, and (b) adds a rule to
invoke scripts/Makefile.autoconf to regenerate u-boot.cfg.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-22 15:36:19 -04:00
Emmanuel Vadot
47a52cd1e4 dtc: mkimage: Add the possibility to specify DTC
FreeBSD recently switch to it's BSDL dtc. While it support most of the
features of the GPL one it still lacks the incbin directive.
Add the possibility to specify which dtc we want to use for compiling dts
and generating fit image.

Signed-off-by: Emmanuel Vadot <manu@bidouilliste.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-07-22 15:36:19 -04:00
xypron.glpk@gmx.de
e42f096f78 meson-gx: reserved memory regions
The Odroid C2 has two GiB of memory with two reserved regions.
reg = <0x0 0x0 0x0 0x1000000>;
reg = <0x0 0x10000000 0x0 0x200000>;

Patch
bfcef28ae4 (arm: add initial support for Amlogic Meson and
ODROID-C2) provided function dram_init_banksize to reserve the
first 16 MiB of RAM for firmware in function dram_init_banksize
in arch/arm/mach-meson/board.c and defined
CONFIG_NR_DRAM_BANKS = 1.

With this patch dram_init_banksize is changed to additionally
reserve the 2MiB region for the ARM Trusted Firmware (BL31).
CONFIG_NR_DRAM_BANKS is set to 2.

Cc: Andreas Färber <afaerber@suse.de>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-07-22 15:36:18 -04:00
Fiach Antaw
9d364af23e env: Switch env_nand, env_mmc and env_ubi to env_import_redund
The env_nand, env_mmc and env_ubi implementations all implement
redundancy using an identical serial-number scheme. This commit
migrates them to use the implementation in env_common, which is
functionally identical.

Signed-off-by: Fiach Antaw <fiach.antaw@uqconnect.edu.au>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-22 15:36:17 -04:00
Fiach Antaw
76768f5f08 env: Add generic redundant environment implementation
All current environments that implement redundancy use almost
identical implementations. This patch implements the env_nand
implementation as a function in env_common, and updates the
env_export function to export an env_nand-style 'flags' field by
default.

Signed-off-by: Fiach Antaw <fiach.antaw@uqconnect.edu.au>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-22 15:36:17 -04:00
Tom Rini
845e10d165 tests: test_dfu.py: Add example udev rule for host_usb_dev_node
If one does not already have a rule to create a custom device node when
a given device enumerates it can be useful to have udev create a
bus path based node to the entry in /dev/bus/usb that was just
enumerated.  Given that DFU itself does not require a /dev entry it is a
good idea to provide a rule that will generate one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-22 15:36:16 -04:00
Michael Heimpold
7e99e14d4b tools/fw_env: use fsync to ensure that data is physically stored
Closing a file descriptor does not guarantee that the data has been
successfully saved to disk, as the kernel might defer the write.

Signed-off-by: Michael Heimpold <mhei@heimpold.de>
2017-07-22 15:36:16 -04:00
xypron.glpk@gmx.de
8787b02e32 efi_loader: correctly implement 100ns conversion
In efi_set_timer we receive the trigger time in intervals of 100 ns.
We should convert it to intervals of 1000 ns by 64bit division.

The patch supplies function efi_div10 that uses multiplication to
implement the missing 64 bit division.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:36:14 +02:00
xypron.glpk@gmx.de
91be9a77b7 efi_console: set up events
Set up a timer event and the WaitForKey event.
In the notify function of the timer event check for console input
and signal the WaitForKey event accordingly.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:36:04 +02:00
xypron.glpk@gmx.de
bfc724625f efi_loader: refactor efi_set_timer
efi_set_timer is refactored to make the function callable internally.
Wrapper function efi_set_timer_ext is provided for EFI applications.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:31:40 +02:00
xypron.glpk@gmx.de
49deb455e6 efi_loader: refactor efi_create_event
efi_create_event is refactored to make it possible to call it
internally. For EFI applications wrapper function
efi_create_event_ext is created.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:31:35 +02:00
xypron.glpk@gmx.de
503f269554 efi_loader: correct size for tpl level
The UEFI standard defines the type for the tpl level as EFI_TPL
alias UINTN.

UINTN is an integer is defined as an unsigned integer of native
width. So we can use size_t for the definition.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:31:04 +02:00
xypron.glpk@gmx.de
c68415922b efi_loader: implement multiple event support
Up to now the boot time supported only a single event.
This patch now allows four events.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:26:09 +02:00
xypron.glpk@gmx.de
2fd945fe72 efi_loader: use struct efi_event * instead of void *
In our implementation the internal structure of events is known.
So use the known type instead of void.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:26:01 +02:00
xypron.glpk@gmx.de
71275a3e98 efi_memory: avoid NULL dereference in efi_free_pool
If efi_free_pool is called with argument NULL an illegal memory
access occurs.

So let's check the parameter on entry.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:41 +02:00
xypron.glpk@gmx.de
70bfcdc6bb efi_loader: disk: iterate only over valid block devices
The efi_loader currently stops iterating over the available
block devices stopping at the first device that fails.
This may imply that no block device is found.

With the patch efi_loader only iterates over valid devices.

It is based on patch
06d592bf52f6 (dm: core: Add uclass_first/next_device_check())
which is currently in u-boot-dm.git.

For testing I used an odroid-c2 with a dts including
&sd_emmc_a {
	status = "okay";
};
This device does not exist on the board and cannot be initialized.

Without the patch:

=> bootefi hello
## Starting EFI application at 01000000 ...
WARNING: Invalid device tree, expect boot to fail
mmc_init: -95, time 1806
Found 0 disks
Hello, world!
## Application terminated, r = 0

With the patch:

=> bootefi hello
## Starting EFI application at 01000000 ...
WARNING: Invalid device tree, expect boot to fail
mmc_init: -95, time 1806
Scanning disk mmc@70000.blk...
Scanning disk mmc@72000.blk...
Card did not respond to voltage select!
mmc_init: -95, time 9
Scanning disk mmc@74000.blk...
Found 3 disks
Hello, world!
## Application terminated, r = 0

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:41 +02:00
xypron.glpk@gmx.de
1da1bac477 efi_loader: provide meaningful status code
Currenty any EFI status other than EFI_SUCCESS is reported as
Application terminated, r = -22

With the patch the status code returned by the EFI application
is printed.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:41 +02:00
xypron.glpk@gmx.de
3c8ffb6875 efi_loader: define all known status codes
efi.h held only a few EFI status codes.

The patch adds the missing definitions for later usage.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:40 +02:00
xypron.glpk@gmx.de
b06d8ac39e bootefi: allow return without EFI_BOOT_SERVICES.Exit
The Unified Extensible Firmware Interface Specification, version 2.7,
defines in chapter 2.1.2 - UEFI Application that an EFI application may
either directly return or call EFI_BOOT_SERVICES.Exit().

Unfortunately U-Boot makes the incorrect assumption that
EFI_BOOT_SERVICES.Exit() is always called.

So the following application leads to a memory exception on the aarch64
architecture when returning:

EFI_STATUS efi_main(
  EFI_HANDLE handle,
  EFI_SYSTEM_TABlE systable) {
	return EFI_SUCCESS;
}

With this patch the entry point is stored in the image handle.

The new wrapper function do_enter is used to call the EFI entry point.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:40 +02:00
xypron.glpk@gmx.de
cc5b70812f efi_loader: implement EFI_DEVICE_PATH_TO_TEXT_PROTOCOL
ConvertPathToText is implemented for
* type 4    - media device path
* subtype 4 - file path

This is the kind of device path we hand out for block devices.

All other cases may be implemented later.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
[agraf: fix whitespace]
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:40 +02:00
xypron.glpk@gmx.de
88adae5ef0 efi_loader: reimplement efi_locate_protocol
The UEFI specification requires that LocateProtol finds the first
handle supporting the protocol and to return a pointer to its
interface.

So we have to assign the protocols to an efi_object and not use
any separate storage.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:40 +02:00
xypron.glpk@gmx.de
011f432745 efi_loader: provide a sufficient number of protocols
Four protocols per object is too few to run iPXE.

Let's raise the number of protocols per object to eight.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:39 +02:00
xypron.glpk@gmx.de
c2e703f903 efi_loader: implement LocateHandleBuffer
UEFI boot service LocateHandleBuffer is implemented by calling
efi_allocate_handle and efi_locate_handle.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:39 +02:00
xypron.glpk@gmx.de
26329584f3 efi_loader: refactor efi_locate_handle
To implement LocateHandleBuffer we need to call efi_locate_handle
internally without running through EFI_EXIT.

So put EFI_ENTRY and EFI_EXIT into a new wrapper function
efi_locate_handle_ext.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:39 +02:00
xypron.glpk@gmx.de
58b8358606 efi_loader: implement InstallMultipleProtocolInterfaces
Implement InstallMultipleProtocolInterfaces in function
efi_install_multiple_protocol_interfaces by repeatedly
calling efi_install_protocol_interface.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:39 +02:00
xypron.glpk@gmx.de
3d8e145608 efi_loader: refactor efi_uninstall_protocol_interface
For the implementation of UninstallMultipleProtocolInterfaces we
need to call efi_uninstall_protocol_interface. In internal calls
we should not pass through EFI_EXIT.

The patch introduces a wrapper function
efi_uninstall_protocol_interface_ext.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:39 +02:00
xypron.glpk@gmx.de
8bee5a3c13 efi_loader: refactor efi_install_protocol_interface
For the implementation of InstallMultipleProtocolInterfaces we
need to call efi_install_protocol_interface. In internal calls
we should not pass through EFI_EXIT.

The patch introduces a wrapper function
efi_install_protocol_interface_ext.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:38 +02:00
xypron.glpk@gmx.de
4b6ed0d7a1 efi_loader: implement UninstallProtocolInterface
Without the patch efi_uninstall_protocol_interface always returns an
error.

With the patch protocols without interface can be uninstalled.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:38 +02:00
xypron.glpk@gmx.de
e0549f8a17 efi_loader: implement InstallProtocolInterface
efi_install_protocol_interface up to now only returned an error code.

The patch implements the UEFI specification for InstallProtocolInterface
with the exception that it will not create new handles.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:38 +02:00
xypron.glpk@gmx.de
69baec6781 efi_loader: efi_open_protocol: parameter checks
Add all parameter checks for function efi_open_protocol that do not
depend on a locking table.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:38 +02:00
xypron.glpk@gmx.de
b5349f742a efi_loader: refactor efi_open_protocol
efi_open_protocol was implemented to call a protocol specific open
function to retrieve the protocol interface.

The UEFI specification does not know of such a function.

It is not possible to implement InstallProtocolInterface with the
current design.

With the patch the protocol interface itself is stored in the list
of installed protocols of an efi_object instead of an open function.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
[agraf: fix efi gop support]
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:23 +02:00
Masahiro Yamada
aae6f016a7 mmc: cadence: use fdt32_t for DT property value to fix sparse warning
DTB is encoded in big endian.  When we retrieve property values,
we need to use fdt32_to_cpu (aka be32_to_cpu) for endian conversion.
This is a bit error-prone, but sparse is useful to detect endian
mismatch.

We need to use (fdt32_t *) instead of (u32 *) for a pointer of a
property value.  Otherwise sparse warns "cast to restricted __be32".

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-07-19 19:13:59 +09:00
Masahiro Yamada
207d8b3533 mmc: add static to spl_mmc_get_device_index()
This function is only used in common/spl/spl_mmc.c[

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-07-19 19:13:59 +09:00
Keerthy
a79e8dfed6 power: regulator: lp87565: get_enable should return integer
get_enable should be able to return error values. Hence change
the return type to integer.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-19 19:13:59 +09:00
Keerthy
43d0247e3e power: regulator: lp873x: get_enable should return integer
get_enable should be able to return error values. Hence change
the return type to integer.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-19 19:13:59 +09:00
Keerthy
4e98a140c8 power: regulator: s5m8767: get_enable should return integer
get_enable should be able to return error values. Hence change
the return type to integer.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-19 19:13:59 +09:00
Keerthy
3bbe7c136b power: sandbox: fixed: get_enable should return integer
get_enable should be able to return error values. Hence change
the return type to integer.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-19 19:13:59 +09:00
Keerthy
585c7032bf power: regulator: rk8xx: get_enable should return integer
get_enable should be able to return error values. Hence change
the return type to integer.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-19 19:13:59 +09:00
Keerthy
2a4747d3cd power: regulator: tps65090: get_enable should return integer
get_enable should be able to return error values. Hence change
the return type to integer.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-19 19:13:59 +09:00
Keerthy
117daa8220 power: regulator: pfuze100: get_enable should return integer
get_enable should be able to return error values. Hence change
the return type to integer.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-19 19:13:59 +09:00
Keerthy
5c3195c61b power: regulator: palmas: get_enable should return integer
get_enable should be able to return error values. Hence change
the return type to integer.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-19 19:13:59 +09:00
Keerthy
b616835ddf power: regulator: max77686: get_enable should return integer
get_enable should be able to return error values. Hence change
the return type to integer.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-19 19:13:59 +09:00
Keerthy
85f87de313 power: regulator: act8846: get_enable should return integer
get_enable should be able to return error values. Hence change
the return type to integer.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-19 19:13:59 +09:00
Keerthy
0f2194d825 power: regulator: fixed: get_enable should return integer
get_enable should be able to return error values. Hence change
the return type to integer.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-19 19:13:59 +09:00
Keerthy
06bdf6003b regulator: Change get_enable return type to integer from bool
Change get_enable return type to int so errors can be returned.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-19 19:13:59 +09:00
Kever Yang
343749c425 mmc: rpmb: update size format for write_counter
According to MMC spec, the write_counter is 4-byte length,
use 'int' instead of 'long' type for the 'long' is not 4-byte
in 64 bit CPU.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-07-19 19:13:59 +09:00
Kever Yang
4dc80c8732 mmc: use new hwpart API when CONFIG_BLK enabled
When CONFIG_BLK is enabled, the hwpart id is different with legacy
interface, update it to kame driver work with CONFIG_BLK.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-07-19 19:13:59 +09:00
Marek Vasut
2710d54f54 ARM: Mark AE boards orphan
I no longer have any of these boards, mark boards orphan.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
2017-07-18 15:21:30 -04:00
Tom Rini
39632b4a01 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2017-07-18 08:42:48 -04:00
Fabio Estevam
651782a08b mx6cuboxi: Move CONFIG_CMD_SATA to Kconfig
Move CONFIG_CMD_SATA option to Kconfig to fix the following build
error:

In file included from include/configs/mx6cuboxi.h:137:0,
                 from include/config.h:7,
                 from include/common.h:21,
                 from common/env_common.c:11:
include/config_distro_bootcmd.h:161:2: error: expected '}' before 'BOOT_TARGET_DEVICES_references_SATA_without_CONFIG_SATA'
  BOOT_TARGET_DEVICES_references_SATA_without_CONFIG_SATA

Reported-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-14 15:16:01 +02:00
Fabio Estevam
3f0a1042bb mx6sabreauto: Make Ethernet functional again
Since commit ce412b79e7 ("drivers: net: phy: atheros: add separate
config for AR8031") Ethernet does not work on mx6sabreauto.

This commit correctly assigns ar8031_config() as the configuration
function for AR8031 in the same way as done in the Linux kernel.

However, on mx6sabreauto design we need some additional configurations,
such as enabling the 125 MHz AR8031 output and setting the TX clock
delay that need to be done in the board file.

This is the equivalent fix from commit 4b6035da48 ("mx6sabresd: Make
Ethernet functional again").

Reported-by: Miquel RAYNAL <miquel.raynal@free-electrons.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-13 15:05:49 +02:00
Tom Rini
e14b1169c0 Merge git://www.denx.de/git/u-boot-marvell 2017-07-12 08:16:41 -04:00
Patrick Bruenn
bc104a7066 imx: cx9020: try pxe boot, if no vmlinuz on mmc
If no vmlinuz is found on mmc, try to boot from pxe.

Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
2017-07-12 10:29:57 +02:00
Patrick Bruenn
f8e63850c2 imx: cx9020: use fdt_addr_r and ramdisk_addr_r
Replace fdtaddr and rdaddr variable names with u-boot standard names
fdt_addr_r and ramdisk_addr_r.
This will make the use of pxe boot more easy.

Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
2017-07-12 10:29:40 +02:00
Diego Dorta
07f6ddb67a mx6sabreauto: Add Falcon mode support
Add support for Falcon mode and explain in the README the steps to
boot the kernel directly without loading the full U-Boot.

Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
Acked-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-12 10:28:19 +02:00
Fabio Estevam
283c2a6553 warp: Use PARTUUID to specify the rootfs location
warp can run different kernel versions, such as NXP 4.1 or
mainline.

Currently the rootfs location is passed via mmcblk number and the
problem with this approach is that the mmcblk number for the eMMC
changes depending on the kernel version.

In order to avoid such issue, use UUID method to specify the rootfs
location.

Succesfully tested booting a NXP 4.1 and also a mainline 4.12 kernel.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2017-07-12 10:25:52 +02:00
Fabio Berton
0f29a61c53 embestmx6boards: Use PARTUUID to specify the rootfs location
Currently the rootfs location is passed via mmcblk number and the
problem with this approach is that the mmcblk number for the eMMC
changes depending on the kernel version.

In order to avoid such issue, use UUID method to specify the rootfs
location.

Also add CONFIG_BOOTCOMMAND to run finduuid function and distro_bootcmd.

This change was made based on U-Boot commit:

  - ca4f338e2e

Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-12 10:25:04 +02:00
Fabio Berton
35ba390d62 mx6cuboxi: Use PARTUUID to specify the rootfs location
Currently the rootfs location is passed via mmcblk number and the
problem with this approach is that the mmcblk number for the eMMC
changes depending on the kernel version.

In order to avoid such issue, use UUID method to specify the rootfs
location.

This change was made based on U-Boot commit:

  - ca4f338e2e

Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-12 10:24:48 +02:00
Fabio Berton
84b4690f26 wandboard: Use PARTUUID to specify the rootfs location
Currently the rootfs location is passed via mmcblk number and the
problem with this approach is that the mmcblk number for the eMMC
changes depending on the kernel version.

In order to avoid such issue, use UUID method to specify the rootfs
location.

This change was made based on U-Boot commit:

  - ca4f338e2e

Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-12 10:24:34 +02:00
Fabio Estevam
00f43e51c5 mx6sabre: Use PARTUUID to specify the rootfs location
mx6sabre boards can run different kernel versions, such as NXP 4.1 or
mainline.

Currently the rootfs location is passed via mmcblk number and the
problem with this approach is that the mmcblk number for the eMMC
changes depending on the kernel version.

In order to avoid such issue, use UUID method to specify the rootfs
location.

Succesfully tested booting a NXP 4.1 and also a mainline kernel on a
mx6qsabresd and mx6dlsabreauto.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-12 10:23:37 +02:00
Fabio Estevam
ca62e5d043 mx6sabreauto: Do not enable WEIM by default
WEIM cannot be used when I2C3 is enabled due to pin conflict, so keep
WEIM disabled by default.

I2C3 controls GPIO I2C expander (USB host and OTG have VBUS controlled by
the GPIO I2C expander), magnetometer, accelerometer.

Not disabling WEIM in U-Boot causes I2C3 to behave badly when booting
a NXP 4.1 kernel, which leads to probe failure on several devices,
including the lack of USB:

imx_usb 2184000.usb: Can't register ci_hdrc platform device, err=-517

By keeping WEIM disabled in U-Boot these kernel issues are gone.

Reported-by: Takashi Matsuzawa <tmatsuzawa@xevo.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-12 10:21:10 +02:00
Stefano Babic
552a848e4f imx: reorganize IMX code as other SOCs
Change is consistent with other SOCs and it is in preparation
for adding SOMs. SOC's related files are moved from cpu/ to
mach-imx/<SOC>.

This change is also coherent with the structure in kernel.

Signed-off-by: Stefano Babic <sbabic@denx.de>

CC: Fabio Estevam <fabio.estevam@nxp.com>
CC: Akshay Bhat <akshaybhat@timesys.com>
CC: Ken Lin <Ken.Lin@advantech.com.tw>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: Heiko Schocher <hs@denx.de>
CC: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com>
CC: Christian Gmeiner <christian.gmeiner@gmail.com>
CC: Stefan Roese <sr@denx.de>
CC: Patrick Bruenn <p.bruenn@beckhoff.com>
CC: Troy Kisky <troy.kisky@boundarydevices.com>
CC: Nikita Kiryanov <nikita@compulab.co.il>
CC: Otavio Salvador <otavio@ossystems.com.br>
CC: "Eric Bénard" <eric@eukrea.com>
CC: Jagan Teki <jagan@amarulasolutions.com>
CC: Ye Li <ye.li@nxp.com>
CC: Peng Fan <peng.fan@nxp.com>
CC: Adrian Alonso <adrian.alonso@nxp.com>
CC: Alison Wang <b18965@freescale.com>
CC: Tim Harvey <tharvey@gateworks.com>
CC: Martin Donnelly <martin.donnelly@ge.com>
CC: Marcin Niestroj <m.niestroj@grinn-global.com>
CC: Lukasz Majewski <lukma@denx.de>
CC: Adam Ford <aford173@gmail.com>
CC: "Albert ARIBAUD (3ADEV)" <albert.aribaud@3adev.fr>
CC: Boris Brezillon <boris.brezillon@free-electrons.com>
CC: Soeren Moch <smoch@web.de>
CC: Richard Hu <richard.hu@technexion.com>
CC: Wig Cheng <wig.cheng@technexion.com>
CC: Vanessa Maegima <vanessa.maegima@nxp.com>
CC: Max Krummenacher <max.krummenacher@toradex.com>
CC: Stefan Agner <stefan.agner@toradex.com>
CC: Markus Niebel <Markus.Niebel@tq-group.com>
CC: Breno Lima <breno.lima@nxp.com>
CC: Francesco Montefoschi <francesco.montefoschi@udoo.org>
CC: Jaehoon Chung <jh80.chung@samsung.com>
CC: Scott Wood <oss@buserror.net>
CC: Joe Hershberger <joe.hershberger@ni.com>
CC: Anatolij Gustschin <agust@denx.de>
CC: Simon Glass <sjg@chromium.org>
CC: "Andrew F. Davis" <afd@ti.com>
CC: "Łukasz Majewski" <l.majewski@samsung.com>
CC: Patrice Chotard <patrice.chotard@st.com>
CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Hans de Goede <hdegoede@redhat.com>
CC: Masahiro Yamada <yamada.masahiro@socionext.com>
CC: Stephen Warren <swarren@nvidia.com>
CC: Andre Przywara <andre.przywara@arm.com>
CC: "Álvaro Fernández Rojas" <noltari@gmail.com>
CC: York Sun <york.sun@nxp.com>
CC: Xiaoliang Yang <xiaoliang.yang@nxp.com>
CC: Chen-Yu Tsai <wens@csie.org>
CC: George McCollister <george.mccollister@gmail.com>
CC: Sven Ebenfeld <sven.ebenfeld@gmail.com>
CC: Filip Brozovic <fbrozovic@gmail.com>
CC: Petr Kulhavy <brain@jikos.cz>
CC: Eric Nelson <eric@nelint.com>
CC: Bai Ping <ping.bai@nxp.com>
CC: Anson Huang <Anson.Huang@nxp.com>
CC: Sanchayan Maity <maitysanchayan@gmail.com>
CC: Lokesh Vutla <lokeshvutla@ti.com>
CC: Patrick Delaunay <patrick.delaunay@st.com>
CC: Gary Bisson <gary.bisson@boundarydevices.com>
CC: Alexander Graf <agraf@suse.de>
CC: u-boot@lists.denx.de
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-07-12 10:17:44 +02:00
Peng Fan
f34ccce50a mmc: fsl_esdhc: drop CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT is not the correct method
to set I/O to 1.8. To boards that does not support vqmmc-supply,
use vs18_enable in fsl_esdhc_cfg. If regulator is supported,
use fixed 1.8V regulator for vqmmc-supply.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2017-07-12 09:44:22 +02:00
Peng Fan
4483b7eb88 dm: mmc: fsl_esdhc: handle vqmmc supply
Handle vqmmc supply. Some boards have a fixed I/O voltage
at 1.8V for emmc, so the usdhc also needs to be configured
as 1.8V by setting VSELECT bit. The vs18_enable is the one
that used to checking whether setting VSELECT or not in
the driver. So if vqmmc supply is 1.8V, set vs18_enable,
the driver will set VSELECT.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-07-12 09:44:22 +02:00
Peng Fan
32a9179f3a mmc: fsl_esdhc: introduce vs18_enable for 1.8V fix I/O
When using eMMC with 1.8V I/O, the VSELECT bit need to be set in
the USDHC controller when init.

This patch adds a parameter "vs18_enable" in fsl_esdhc_cfg
structure and priv data, so each controller can have different
settings.

We could not use CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT, it has problem
that it will apply to all USDHC controllers and it only set the 1.8V
at init phase. So if user does not select to the eMMC device,
the voltage on the I/O pins are not correct.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2017-07-12 09:44:22 +02:00
Peng Fan
15a91651bf mmc: fsl_esdhc: correct type of wp_enable
The type should be int, not u8. cfg->wp_enable will finally be
assigned to priv->wp_enable whose type is int.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2017-07-12 09:44:22 +02:00
Jagan Teki
ed2d02d4ce imx6_spl: Add u-boot-dtb.img for SPL payload
Add u-boot-dtb.img for SPL_FS_LOAD_PAYLOAD_NAME when
OF_CONTROL used.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-07-12 09:44:22 +02:00
Vanessa Maegima
d7c11502df mx6sabreauto: Update to SPL only mode
As mx6sabreauto supports SPL now, all variants can boot using the same
defconfig.

This patch:
- Removes non-SPL targets.
- Renames target to mx6sabreauto_defconfig.
- Renames folder and board files to mx6sabreauto.
- Updates MAINTAINERS, Makefile and Kconfig accordingly.
- Removes .cfg files.
- Adds a README with instructions to build and flash SPL and u-boot.img.

Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-07-12 09:44:22 +02:00
Vanessa Maegima
823dff9d02 mx6qsabreauto: Add SPL support
Add support for mx6q, mx6dl and mx6qp sabreauto boards in SPL.

Retrieved the mx6q DCD table from:
board/freescale/mx6qsabreauto/imximage.cfg

Retrieved the mx6dl DCD table from:
board/freescale/mx6qsabreauto/mx6dl.cfg

Retrieved the mx6qp DCD table from:
board/freescale/mx6qsabreauto/mx6qp.cfg

Flashed SPL and u-boot.img to an SD card and could successfully boot it
on mx6q, mx6qp and mx6dl sabreauto boards.

Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-07-12 09:44:22 +02:00
Peter Robinson
ff18156325 mx6cuboxi: Add support for sata
The Cubox-i and Hummingboard series of devices have an option of
SATA on board, and depending on how the fuses are blown even the
option to boot SPL from SATA. So enable support for it so it can
be used to boot the OS from if people desire.

Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Acked-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-12 09:44:22 +02:00
Gautam Bhat
d8fab10cb4 mx7dsabresd: Set VLD04 output to 2.8V in PMIC initialization.
This change sets the VLDO4 settings output to 2.8V in PMIC
initialization so that the MIPI DSI/CSI input voltage is 2.8V
as per the schematics. The original code provides an output of
3.3V which violates the voltage mentioned in the schematics.

Signed-off-by: Gautam Bhat <mindentropy@gmail.com>
Acked-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-12 09:44:22 +02:00
Fabio Estevam
a1d1fdc920 mx6: soc: Move mxs_dma_init() into the mxs nand driver
Currently the following build error is seen when a board using MMC SPL
is built and the MXS nand driver is also selected:

arch/arm/cpu/armv7/built-in.o: In function `arch_cpu_init':
arch/arm/cpu/armv7/mx6/soc.c:432: undefined reference to 'mxs_dma_init'

On mx6 the only user of mxs_dma_init() is the mxs nand driver, so
move it there.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-12 09:44:22 +02:00
Lothar Waßmann
306dd7dabd net: fec_mxc: fix PHY initialization bug with CONFIG_DM_ETH
When CONFIG_DM_ETH is set, the FEC ethernet controller is reset after
the PHY has been set up and initialzed. This breaks the communication
with the PHY and results in an inoperable ethernet interface.

Do the initialization with CONFIG_DM_ETH in the same order as with
legacy ETH support to fix this.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-07-12 09:44:22 +02:00
Jagan Teki
34d45d123a icorem6_rqs: Rename icorem6_rqs config file
imx6qdl_icore_mmc_defconfig => imx6qdl_icore_rqs_defconfig
Since icorem6_rqs support MMC/eMMC boot, so doesn't need
to name it explicitly.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-07-12 09:44:22 +02:00
Florian Fainelli
022b7fb515 dt-bindings: Document the Broadcom STB wake-up timer node
Document the binding for the Broadcom STB SoCs wake-up timer node
allowing the system to generate alarms and exit low power states.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2017-07-12 09:44:22 +02:00
Jagan Teki
61366b71a8 serial: mxc: Add debug uart support
Add support for the debug UART to assist with early debugging.
Enable it for i.CoreM6 as an example.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-12 09:44:22 +02:00
Jagan Teki
52c14cabda serial: mxc: Code cleanup
- Remove space between #define to macro
- Add tab between macro and value

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-12 09:42:33 +02:00
Jagan Teki
45d97511a9 serial: mxc: Move common baud gen into _mxc_serial_setbrg
Move the common baud generation code into _mxc_serial_setbrg
so-that dm and non-dm can call this func.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-12 09:42:33 +02:00
Jagan Teki
97548d5947 serial: mxc: Move common init into _mxc_serial_init
Move the common initialization code into _mxc_serial_init
so-that dm and non-dm can call this func.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-12 09:42:33 +02:00
Jagan Teki
57d3e98f57 serial: mxc: Move cr1 and cr2 write to mxc_serial_setbrg
Control reg write should be part of setbrg for better
buadrate generation, so move cr1 and cr2 write to
mxc_serial_setbrg

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-12 09:42:33 +02:00
Jagan Teki
62af03ee97 serial: mxc: Use RFDIV in dm-code
Use RFDIV in dm-code instead of numeric value, so-that
it can be common for dm and non-dm.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-12 09:42:33 +02:00
Jagan Teki
ffa8bcd7f1 serial: mxc: Add common mxc_uart reg space
This patch will add common reg space for non-dm and
dm code and non-dm reg space can be accessed using
mxc_base.

This will
- get rid of __REG volatile assignments
- Make common reg_space by removing unneeded macros

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-12 09:42:33 +02:00
Stefan Agner
3fd9579085 imx: mx6ull: fix USB bmode for i.MX 6UL and 6ULL
i.MX 6UL and 6ULL have different boot device capabilities and
use therefor use a different boot device selection table than
other i.MX 6 devices. Particularly, the value which has been
used so far (b0001) is assigned to QSPI boot for these two
devices.

There is no common reserved value for all i.MX 6devices. Use
b0010 for i.MX 6UL and 6ULL via compile time ifdef.

Reported-by: Joël Esponde <joel.esponde@honeywell.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Joël Esponde <joel.esponde@honeywell.com>
2017-07-12 09:42:33 +02:00
Christian Gmeiner
8be70bb4aa ot1200: enable CONFIG_IMX_THERMAL for detailed thermal information
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-07-12 09:42:33 +02:00
Fabio Estevam
258f76fd21 mx6sabresd: Fix guard file symbol
Remove the "Q" from the file guard symbol, so that it matches
the file name.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-12 09:42:33 +02:00
Fabio Estevam
b8b9790e23 wandboard: Remove unnecessary delay
There is no need to add a 100us delay after the DDR initialization.

Other imx6 boards do not have such delay either, so simply remove it.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-12 09:42:33 +02:00
Fabio Estevam
dfa33fbe48 cm_fx6: Remove SPL entry from CONFIG_SYS_EXTRA_OPTIONS
SPL is already selected via CONFIG_SPL=y, so there is no need
to pass it inside CONFIG_SYS_EXTRA_OPTIONS.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-12 09:42:33 +02:00
Fabio Estevam
d84a8c5b28 cgtqmx6eval: Remove SPL entry from CONFIG_SYS_EXTRA_OPTIONS
SPL is already selected via CONFIG_SPL=y, so there is no need
to pass it inside CONFIG_SYS_EXTRA_OPTIONS.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-12 09:42:33 +02:00
Fabio Estevam
7f27eec72e mx6slevk_spl: Remove SPL entry from CONFIG_SYS_EXTRA_OPTIONS
SPL is already selected via CONFIG_SPL=y, so there is no need
to pass it inside CONFIG_SYS_EXTRA_OPTIONS.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-12 09:42:33 +02:00
Fabio Estevam
41857231d5 mx6sabresd: Remove SPL entry from CONFIG_SYS_EXTRA_OPTIONS
SPL is already selected via CONFIG_SPL=y, so there is no need
to pass it inside CONFIG_SYS_EXTRA_OPTIONS.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-12 09:42:33 +02:00
Baruch Siach
172b2e0b56 arm: mvebu: clearfog: fix chip name comment
The clearfog uses Armada 388.

Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-07-12 06:57:55 +02:00
Baruch Siach
db7cd4ed33 tools/kwbimage: fix v1 header verification
The verify_header callback in kwbimage.c only verifies v0 headers checksum.
Running 'mkimage -l' on a v1 image gives the following misleading output:

GP Header: Size ae000000 LoadAddr 34160600

Implement support for v1 headers. For that, factor out the header checksum code
to a separate main_hdr_checksum_ok() routine. This routine relies on the fact
that the checksum field offset is the same in both v0 and v1 headers. With this
patch applied 'mkimage -l' correctly identifies the image:

Image Type:   MVEBU Boot from sdio Image
Image version:1
Data Size:    398904 Bytes = 389.55 KiB = 0.38 MiB
Load Address: 007fffc0
Entry Point:  00800000

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-07-12 06:57:55 +02:00
Baruch Siach
37d108b64f tools/kwbimage.h: make offset marks style consistent
The offset marking in kwbimage.h is inconsistent. main_hdr_v0 uses decimals,
main_hdr_v1 uses hex without '0x' prefix, secure_hdr_v1 uses hex with '0x'
prefix. Make all offset marks hex with '0x' prefix.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-07-12 06:57:55 +02:00
Baruch Siach
ed72741d9f tools/kwbimage: update the list of SoCs using v1 header
Armada 38x also uses image header v1.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-07-12 06:57:55 +02:00
Igal Liberman
b6518b1ea3 arm64: mvebu: use single defconfig for Armada8K development boards
Currently, Marvell Armada8k development board use 3 different
defconfigs:
        mvebu_db-88f7040-nand_defconfig
        mvebu_db-88f7040_defconfig
        mvebu_db-88f8040_defconfig
Having 3 different defconfigs makes maintenance difficult.

This patch removes the defconfigs mentioned above and introduce
a new defconfig which represents the Armada8k family.

NOTE:
In order not to break automatic tools compilation,
a default device-tree is set in the defconfig (armada-8040-db).
However, when compiling u-boot, the user MUST explicitly export
the DEVICE_TREE for the requested board because using A80x0
device-tree on A70x0 might break the device.

For more information, refer to "doc/README.marvell" (intoduced
in this patch).

Change-Id: I98515b6306498358f3722ecf7ac4c87f236ebbd8
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-07-12 06:57:55 +02:00
Marek Behún
b6ee860b87 marvell: armada385: Add the Turris Omnia board
The Turris Omnia is a open-source router created by CZ.NIC.

The code is based on the Marvell/db-88f6820-gp by Stefan Roese
with modifications from Tomas Hlavacek in the CZ.NIC turris-omnia-uboot
repository, which can be found at
https://gitlab.labs.nic.cz/turris/turris-omnia-uboot

By default, the Turris Omnia uses btrfs as the main and only filesystem,
and also loads kernel and device tree from this filesystem. Since U-Boot
does not yet support btrfs, you should not flash your Turris Omnia board
with this unless you know what you are doing.

Signed-off-by: Tomas Hlavacek <tomas.hlavacek@nic.cz>
Signed-off-by: Marek Behun <marek.behun@nic.cz>

 create mode 100644 board/CZ.NIC/turris_omnia/Makefile
 create mode 100644 board/CZ.NIC/turris_omnia/kwbimage.cfg
 create mode 100644 board/CZ.NIC/turris_omnia/turris_omnia.c
 create mode 100644 configs/turris_omnia_defconfig
 create mode 100644 include/configs/turris_omnia.h
Signed-off-by: Stefan Roese <sr@denx.de>
2017-07-12 06:57:38 +02:00
Marek Behún
aa5eb9a3ac drivers/misc: Add basic support for ATSHA204A Crypto module
This module can be found on the Turris Omnia board connected
via the I2C interface.

Among some cryptographic functions, the chip has a 512 bit
One Time Programmable memory, 88 byte configuration memory
and 512 byte general purpose memory.

The Turris Omnia stores serial number and device MAC address in
the OTP memory.

This commit adds basic support for reading the EEPROM and also
exposes the chips Random Number Generator.

The driver is based on code by
  Josh Datko, Cryptotronix, jbd@cryptotronix.com
and also
  Tomas Hlavacek, CZ.NIC, tomas.hlavacek@nic.cz

Signed-off-by: Tomas Hlavacek <tomas.hlavacek@nic.cz>
Signed-off-by: Marek Behun <marek.behun@nic.cz>

 create mode 100644 drivers/misc/atsha204a-i2c.c
 create mode 100644 include/atsha204a-i2c.h
Signed-off-by: Stefan Roese <sr@denx.de>
2017-07-12 06:57:38 +02:00
Marek Behún
8e6eda7cda drivers/i2c/muxes/pca954x: Add pca9547 I2C mux support
This I2C mux is found, for example, on the Turris Omnia board.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-07-12 06:56:48 +02:00
Marek Behún
c2502e7b82 arch/arm/dts: Add Turris Omnia device tree
This device tree is taken from mainline Linux kernel commit
7b7db5ab. Added is also a -u-boot.dtsi file with these additions:

  - aliases for I2C and SPI devices are added, because i2cmux and
    SPI flash doesn't work otherwise
  - spi_flash node has been added so that the new DM API works
  - the ATSHA204A node is added in the i2c@5 node
  - "u-boot,dm-pre-reloc"s are added in needed nodes for SPL
    build to work correctly

Signed-off-by: Marek Behun <marek.behun@nic.cz>

 create mode 100644 arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi
 create mode 100644 arch/arm/dts/armada-385-turris-omnia.dts
Signed-off-by: Stefan Roese <sr@denx.de>
2017-07-12 06:56:48 +02:00
Marek Behún
2ab7704a6d orion_wdt: Support for the Orion Watchdog
The Orion watchdog can be found on some Marvell Armada chips.

This driver is based on the code by Tomas Hlavacek in the CZ.NIC
turris-omnia-uboot repository, which can be found at
https://gitlab.labs.nic.cz/turris/turris-omnia-uboot, and that
one is based on code by Sylver Bruneau. His code is already in
mainline Linux kernel.

The code uses the new driver model API.

Signed-off-by: Tomas Hlavacek <tomas.hlavacek@nic.cz>
Signed-off-by: Marek Behun <marek.behun@nic.cz>

 create mode 100644 drivers/watchdog/orion_wdt.c
Signed-off-by: Stefan Roese <sr@denx.de>
2017-07-12 06:56:48 +02:00
Marek Behún
90bcc3d38d driver/ddr: Add support for setting timing in hws_topology_map
The DDR3 training code for Marvell A38X currently computes 1t timing
when given board topology map of the Turris Omnia, but Omnia needs 2t.

This patch adds support for enforcing the 2t timing in struct
hws_topology_map, through a new enum hws_timing, which can assume
following values:
  HWS_TIM_DEFAULT - default behaviour, compute whether to enable 2t
                    from the number of CSs
  HWS_TIM_1T      - enforce 1t
  HWS_TIM_2T      - enforce 2t

This patch also sets all the board topology maps (db-88f6820-amc,
db-88f6820-gp, controlcenterdc and clearfog) to have timing set to
HWS_TIM_DEFAULT.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-07-12 06:56:48 +02:00
Alexandru Gagniuc
409a81ddd4 am33xx: board: Refactor USB initialization into separate function
The declaration of otg*_plat and otg*_board_data is guarded by
CONFIG_USB_MUSB_*, but their use in arch_misc_init is not. The
ifdef flow goes something like:

if (CONFIG_USB_MUSB_* && other_conditions)
	declare usb_data
if (other_conditions)
	use usb_data

Thus when CONFIG_USB_MUSB_* is not declared, we try to use the
data structures, but these structures aren't defined.

To fix this, move the USB initialization code into the same #ifdef
which guards the declaration of the data structures. Since the DM_USB
vs legacy cases are completely different, use two versions of
arch_misc_init(), for readability.

Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-11 22:49:39 -04:00
Alexandru Gagniuc
17a21e206a configs: am335x_evm: Enable FASTBOOT based on kconfig
When CONFIG_CMD_FASTBOOT or CONFIG_USB_FUNCTION_FASTBOOT are defined
in am335x_evm.h, a dependency on g_dnl.c is created. This in turn
creates a dependency on having USB gadget enabled.
As a result we can't create configs with USB gadget disabled.

Since these CONFIG_ variables are now part of kconfig, move them to
the board defconfigs, and out of am335x_evm.h. This both preserves
current defaults, and allows creating configs with USB gadget off.

Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-11 22:49:38 -04:00
Tom Rini
ab86dc7948 ARM: ti816x: Fix enabling GPIO0, enable GPIO1 as well
The TI816x has 2 GPIO banks.  For bank 0 we had been clearing the enable
bit when setting BIT(8).  Correct this by setting it to BIT(1) | BIT(8)
after we set and wait for BIT(1) (aka PRCM_MOD_EN).  Enable GPIO1 as
well so that when CMD_GPIO is enabled it won't crash probing the second
bank.  Enable CMD_GPIO on ti816x_evm.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-11 22:41:56 -04:00
Tom Rini
39b4f6bce3 ti816x: Enable ethernet support
The ti816x SoC revision of the ethernet IP block is handled by the
"davinci_emac" driver, rather than the "cpsw" driver as done by later
members of the family.  Enable the relevant plumbing.

Signed-off-by: Sriramakrishnan <srk@ti.com>
Signed-off-by: Vitaly Wool <vitaly.wool@konsulko.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-11 22:41:56 -04:00
Grygorii Strashko
7a9dfe75cf mtd: nand: make nand_info array static
Make make nand_info array static, since all direct users of nand_info array
have been converted to use get_nand_dev_by_index() API.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:54 -04:00
Grygorii Strashko
8a049dd642 armv8: fsl-layerscape: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly.

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: York Sun <york.sun@nxp.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:53 -04:00
Grygorii Strashko
bf264cd0f6 board: toradex: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly.

Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:52 -04:00
Grygorii Strashko
573cc46c65 board: BuR: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by:  Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11 22:41:52 -04:00
Grygorii Strashko
2ecba112d7 board: ronetix: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:51 -04:00
Grygorii Strashko
31f8d39e2a board: atmel: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:51 -04:00
Grygorii Strashko
7021c7e6f2 cmd: mvebu: bubt: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:49 -04:00
Grygorii Strashko
88b81bf792 mtd: nand: drv: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:49 -04:00
Grygorii Strashko
750b34c9ae net: fm: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2017-07-11 22:41:48 -04:00
Grygorii Strashko
1ceac70080 net: phy: cortina: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2017-07-11 22:41:48 -04:00
Grygorii Strashko
6308e71be4 cmd: nand: remove direct access to struct mtd_info->priv
Replace direct access to struct mtd_info->priv with proper
accessor mtd_to_nand().

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:47 -04:00
Grygorii Strashko
eb6a5c3c02 fs: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:47 -04:00
Grygorii Strashko
edba8cc4f3 common: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:46 -04:00
Grygorii Strashko
bfdba68eac cmd: jffs2: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:46 -04:00
Grygorii Strashko
f370b51510 cmd: bootm: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:45 -04:00
Grygorii Strashko
1652018991 dfu: dfu_nand: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:45 -04:00
Grygorii Strashko
a94a261939 common: env_nand: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:44 -04:00
Mugunthan V N
ad92dff28c cmd: nand: abstract global variable usage for dm conversion
nand_info is used all over the file so abstract it with
get_nand_dev_by_index() which will help for DM conversion.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:44 -04:00
Tom Rini
8d3a25685e Merge git://git.denx.de/u-boot-dm 2017-07-11 20:28:46 -04:00
Tom Rini
d43ef73bf2 Merge branch 'master' of git://git.denx.de/u-boot-rockchip 2017-07-11 14:21:50 -04:00
Masahiro Yamada
8c9eaadaaa dm: ofnode: use fdt32_t for DT property value to fix sparse warning
DTB is encoded in big endian.  When we retrieve property values,
we need to use fdt32_to_cpu (aka be32_to_cpu) for endian conversion.
This is a bit error-prone, but sparse is useful to detect endian
mismatch.

We need to use (fdt32_t *) instead of (u32 *) for a pointer of a
property value.  Otherwise sparse warns "cast to restricted __be32".

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Masahiro Yamada
fce136aafe dm: include <dm/util.h> from driver/core/dump.c
Include <dm/util.h> to fix sparse warnings:
symbol 'dm_dump_all' was not declared. Should it be static?
symbol 'dm_dump_uclass' was not declared. Should it be static?

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Masahiro Yamada
b2ec7ea731 dm: ofnode: simplify ofnode_read_bool()
Reuse ofnode_get_property() to simplify the implementation.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Masahiro Yamada
61e51babdb dm: ofnode: rename ofnode_read_prop() to ofnode_get_property()
This function returns the pointer to the value of a node property.
The current name ofnode_read_prop() is confusing.  Follow the naming
of_get_property() from Linux.

The return type (const u32 *) is wrong.  DT property values can be
strings as well as integers.  This is why of_get_property/fdt_getprop
returns an opaque pointer.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Masahiro Yamada
cb7dbe1fb0 dm: ofnode: simplify ofnode_read_prop()
The code inside the if-block is the same as of_get_property().

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Masahiro Yamada
252510ac69 dm: ofnode: use ofnode_read_bool() to check property existence
This will clarify the code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Masahiro Yamada
766c28a548 dm: include <dm/util.h> from drivers/core/util.c
Fix sparse warnings "... was not declared. Should it be static?"

Also, fix redefinition of dm_warn/dm_dbg.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:20 -06:00
Tom Rini
99bb38e2cc fdt: Check for NULL return from fdt_getprop in 'fdt set'
While the previous pass through fixed one place where we knew that
fdt_getprop would be given a positive len, in the case of 'fdt set' we
do not, so check that we did no get NULL from fdt_getprop().

Cc: Simon Glass <sjg@chromium.org>
Reported-by: Coverity (CID: 163249)
Fixes 72c98ed1ab ("fdt: Add a check to do_fdt() for coverity")
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Simon Glass
f53dcc0e35 tegra: fdt: Ensure that the console UART is enabled
Many tegra boards have the console UART node disabled. With livetree this
prevents serial from working since it does not 'force' the console to be
bound. Updates the affected boards to fix this error.

The boards were checked with:

for b in $(grep  tegra boards.cfg  |grep -v integrator | \
		awk '{print $7}' | sort); do
	echo $b;
	fdtgrep -c nvidia,tegra20-uart b/$b/u-boot.dtb |grep okay;
done

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
50d8c4a465 tegra: Show a debug message if the LCD PMIC fails to start
This error condition should have a debug() message. Add it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
f93472a022 dm: serial: Add livetree support
Add support for a live device tree to the core serial uclass.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
d09608534c dm: serial: Separate out the core serial-device finding code
This function is quite long. Move the core code into a separate function
in preparation for adding livetree support.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
db9f8f6ad5 dm: serial: ns16550: Convert to livetree
Update this driver to support a live device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
03bc3f18b7 tegra: Fix up include file ordering
Update these two files so include files in the right order.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
1a9f3da917 video: simple-panel: Add a little more debugging
Add some debugging to show when the backlight is enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
7cf208d73b dm: video: Update pwm_backlight to support livetree
Update this driver to support a live device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
fb0b709eff dm: video: Sync display on backspace
We should sync the display (e.g. flush cache) when backspace is pressed
to ensure that the character is erased correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
2f0dd5cafe tegra: nyan-big: Enable bootstage
Enable full bootstage support so we can time SPL and U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
c1eb3d5966 dm: Fix error handling when unflattening the DT
The error handling code does not current detect an error right away.
Adjust it to return immediately.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
0be3a3b473 tegra: nyan-big: Enable the debug UART
Enable this to allow debugging when the serial UART driver is
misconfigured.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
23acc48d84 tegra: video: Time the LCD init
Calculate the time taken to set up the LCD.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
878d68c0c3 dm: core: Add functions to obtain node's address/size cells
The of_n_addr_cells() and of_n_size_cells() functions are useful for
getting the size of addresses in a node, but in a few places U-Boot needs
to obtain the actual property value for a node without walking up the
stack. Add functions for this and just the existing code to use it.

Add a comment to the existing ofnode functions which do not do the right
thing with a flat tree.

This fixes a problem reading PCI addresses.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
f7d6fcf7ae dm: core: Add dev_read_enabled() to check if a device is enabled
This function allows a device's status to be read. This indicates whether
the device should be enabled or disabled.

Note: In normal operation disabled devices will not be present in the
driver-model tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
a44810123f dm: core: Add dev_read_resource() to read device resources
Add a function which reads resources from a device, such as the device
hardware address. This uses the "reg" property in the device.

Unlike other functions there is little sense in inlining this when
livetree is not being used because it has some logic in it and this would
just bloat the code size.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
8c293d6ac9 dm: core: Add ofnode_read_string_count()
This provides a way to find the number of strings in a string list. Add it
and also fix up the comment for ofnode_read_string_index().

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
7feccfdc45 binman: Put our local modules ahead of system modules
If a system module is named the same as one of those used by binman we
currently pick the system module. Adjust the ordering so that our modules
are chosen instead.

The module conflict reported was 'tools' from jira-python. I cannot access
that package to test it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
2017-07-11 10:08:20 -06:00
Simon Glass
c07919281c dtoc: Add tests
Add some tests of dtoc's functionality to make it easier to expand and
enhance the tool.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Simon Glass
2028cc59f7 sandbox: Stop printing platdata at the start of SPL
Currently we have code which prints out platform data at the start of SPL.
Now that we have tests for dtoc this is probably not necessary. Drop it.
Update test_ofplatdata to check for empty output since it is useful to
check that sandbox_spl works as expected.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Simon Glass
30107b08d7 dtoc: Add a comment about string replace in conv_name_to_c()
This function uses several separate string replaces where a regular
expression might seem more reasonable. Add a comment justifying the way it
is currently done.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Simon Glass
fa0ea5b09e dtoc: Move the main logic into the dtb_platdata file
Collect the main logic of dtoc into a function and put it into
dtb_platdata. This will allow tests to use this function instead of
duplicating the code themselves.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Simon Glass
56e0bbe057 dtoc: Move static functions out of the class
Rather than using static functions within the class, move them out of the
class. This will make it slightly easier for tests to call them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Simon Glass
e36024b05f dtoc: Pass include_disabled explicitly
This option is the only one actually used by the dtb_platdata class. Pass
it explicitly to avoid needing to pass the whole option object to the
constructor.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Simon Glass
86290ce40e dtoc: Don't handle properties with / in them
This conversion appears to not be needed as it does not occur in practice.
Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Simon Glass
2be282ca01 dtoc: Fix pylint warnings
Unfortunately I neglected to run pylint on this tool with its initial
submission. Fix the warnings.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Simon Glass
7581c01a15 dtoc: Split out the main class into its own file
To simplify running tests we should move this class into its own file.
This allows the tests to import it without having to import dtoc.py, which
runs the tests.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Simon Glass
14f5acfc5b dtoc: Add a comment at the top
Add a description of the dtoc tool at the top of the file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Simon Glass
418355cbaa dtoc: Use self._options instead of the global options
This class should use the options object passed to it rather than finding
the global one. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Simon Glass
cb008830aa moveconfig: Allow automatic location and adding of 'imply'
By using a Kconfig parser we can find the location of each option in the
Kconfig tree. Using the information from the database we can then
automatically add an 'imply' option into the right place if requested by
the user.

Add a -a option to support adding 'imply' options. Display the location of
any existing 'imply' option so that progress can be examined. Add a -A
option to hide any existing 'imply' options so that already-completed
additions need not be considered further.

Also add documentation for this feature.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Simon Glass
9b2a2e87d2 moveconfig: Allow control of which implying configs are shown
Sometimes it is useful to display CONFIG_TARGET or CONFIG_CMD configs. Add
an option to control this.

Also we generally ignore implying configs which affect fewer than 5
boards. But sometimes it is useful to show those those, so add an option
that reduces the minimum to two.

ERRATUM configs are never useful for implying things, so ignore those.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Simon Glass
2ddd85dc34 moveconfig: Allow piping in 'git show --stat' output
It is useful to be able to process only a subset of boards to save time.
Often that subset is defined by the defconfig files in a git commit. This
change allows things like:

   # Build the database
   ./tools.moveconfig.py -b

   # Find some implying configs
   ./tools/moveconfig.py -i CONFIG_X

   # Add some 'imply' statements to Kconfig files
   ./tools/moveconfig.py -i CONFIG_X -a CONFIG_A,CONFIG_B

   # Reprocess the defconfig files to see if we can drop some changes
   git show --stat | ./tools/moveconfig.py -s -d -

   # Update the commit, with fewer defconfig changes
   gii commit -au

Where the commit contains defconfig files, this will reprocess them to
take account of the imply statements that you added.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Simon Glass
d8c6fb8ced sandbox: Drop special case console code for sandbox
At present sandbox has a special case where it directly calls os_putc()
when it does not have a console yet.

Now that we have the pre-console buffer enabled we can drop this. Any
early characters will be buffered and output later.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-11 10:08:20 -06:00
Simon Glass
d63b5b4fbb sandbox: Enable more console options
Enable the pre-console buffer, displaying the model and post-relocation
console announce on sandbox. Also add a model name to the device tree.
This allows testing of these features.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-11 10:08:20 -06:00
Simon Glass
4e6bafa568 console: Use map_sysmem() for the pre-relocation console
At present this feature casts the address to a pointer. Use the
map_sysmem() function so that it will work correctly on sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-11 10:08:19 -06:00
Simon Glass
e5a9d27fdb test: Add a test for snprintf() and the banner/version
Add a simple test to make sure that these functions obey the buffer size
passed into them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-11 10:08:19 -06:00
Simon Glass
b0895384be Allow displaying the U-Boot banner on a video display
At present the U-Boot banner is only displayed on the serial console. If
this is not visible to the user, the banner does not show. Some devices
have a video display which can usefully display this information.

Add a banner which is printed after relocation only on non-serial devices
if CONFIG_DISPLAY_BOARDINFO_LATE is defined.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-11 10:08:19 -06:00
Simon Glass
6c519f2dc4 display_options: Refactor to allow obtaining the banner
Move the display options code into a separate function so that the U-Boot
banner can be obtained from other code. Adjust the 'version' command to
use it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-11 10:08:19 -06:00
Simon Glass
32e9ec1f88 x86: Move link to use driver model for SCSI
As a demonstration of how to use SCSI with driver model, move link over
to use this. This patch needs more work, but illustrates the concept.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
7337fcd8c0 dm: scsi: Drop scsi_init() when driver model is used
This function should not be used with driver model. Update the code to
reflect this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
681357ffd9 dm: ahci: Add a driver for SCSI on AHCI
Some AHCI drivers use SCSI under the hood. Rather than making the AHCI
driver be in the SCSI uclass it makes sense to have the AHCI device create
a SCSI device as a child. That way we can handle any AHCI-specific
operations rather than trying to pretend tha the device is just SCSI.

To handle this we need to provide a way for AHCI drivers to bind a SCSI
device as its child, and probe it. Add functions for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
5c56176318 dm: scsi: Split out the bus scanning code
Split out the code that scans a single SCSI bus into a separate function.
This will allow it to be used from driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
f6580ef39b dm: scsi: Adjust return value of scsi_exec()
Change this function to return an error number instead of true/false.
This allows us to return a proper error number.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
f6ab5a92ac dm: scsi: Add operations for SCSI devices
The SCSI uclass currently has no operations. It just uses the global SCSI
functions. Fix this by adding operations to the only two drivers that use
the uclass, and replacing the global functions with those defined locally
in the SCSI code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
4e74901458 dm: ahci: Create a local version of two SCSI functions
With driver model we need to define implementations of exec() and
bus_reset() separately for each SCSI driver. As a first step, create a
local version of each function in the AHCI driver and call each from its
global version.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
8eab1a58dd dm: scsi: Document and rename the scsi_scan() parameter
The 'mode' parameter is actually a flag to determine whether to display
a list of devices found during the scan. Rename it to reflect this, add a
function comment and adjust callers to use a boolean.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
4682c8a19b dm: scsi: Add a device pointer to scan_exec(), scsi_bus_reset()
With driver model these functions need a device pointer. Add one even
when CONFIG_DM_SCSI is not defined. This avoids having ugly conditional
function prototypes, When CONFIG_DM_SCSI is not defined we can just ignore
the pointer.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
322f73f473 dm: scsi: Add operations
Add operations for SCSI. These are not yet implemented, but we have the
struct.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
4279efc4c9 dm: ahci: Drop use of probe_ent
With driver model we cannot have static data or assume that there is only
one device of each time. Adjust the code so that 'probe_ent' is not needed
with driver model. Add a new ahci_init_dm() function which can init AHCI
for driver model without re-allocating the uclass data. Move over the only
existing driver to use this new function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
7cf1afce7f dm: ahci: Unwind the confusing init code
Two AHCI drivers use SCSI with CONFIG_DM_SCSI. The SCSI uclass calls
scsi_low_level_init() which is implemented by ahci.c. If
CONFIG_SCSI_AHCI_PLAT is defined it does one thing and if it is not
it does something else.

We don't need to call through scsi_low_level_init() to get the init
completed. Instead, adjust the two drivers to call into AHCI directly.
Drop the post-probe init in the SCSI uclass. This means that driver model
doesn't need to use scsi_low_level_init(). It is a legacy function and
driver model should use a driver's probe() method instead.

While we are here, add a comment to the top of the file explaining what
ahci.c does.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
62b4ec8e30 dm: ahci: Move common code for starting ports into a function
This code is duplicated. Create a ahci_start_ports() function to handle
this and call it from both places.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
099c239d68 dm: scsi: Indent the confusing #ifdefs
These are very confusing without some sort of indentation. At some point
we will be able to remove them, but for now, indent them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
225b1da7bf dm: ahci: Refactor to avoid static variables
With driver model we need each device to have its own state. As a step
towards this, restrict use of the global 'probe_ent' to just a few places
in the file. This will allow us to add driver-model functions which can
pass the correct data around.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
4b62b2ff53 dm: sata: Move ataid into struct ahci_uc_priv
This array relates to the AHCI controller so should be exist out on its
own in the file. Move it into the structure. Adjust functions that need
access to this to take the structure as a parameter.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
2c9f9efb3d dm: ahci: Rename struct ahci_probe_ent
This is not a very useful name since once it is probed it still hangs
around. With driver model we will use uclass data for this, so rename the
struct.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
1dc64f6c00 dm: scsi: Use the uclass platform data
At present the two driver-model SCSI drivers use device platform data to
store information that relates to the uclass. It is better to use uclass
platform data in this situation. Update the code to do this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
b9560ad649 dm: scsi: Drop the ccb typedef
We should not be using typedefs in U-Boot and 'ccb' is a pretty short
name. It is also used with variables. Drop the typedef and use 'struct'
instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
aae5ec3403 dm: scsi: Rename struct SCSI_cmd_block to struct scsi_cmd
This name should be lower case. Also the _block suffix is superfluous.
Rename it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
043682422c dm: scsi: Rearrange header file for driver model
Put the driver-model declarations first since we are migrating to that.
Also drop scsi_init() when driver model is used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
0fcd48fe00 scsi: Move drivers into new drivers/scsi directory
At present we have the SCSI drivers in the drivers/block and common/
directories. It is better to split them out into their own place. Use
drivers/scsi which is what Linux does.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
f2105c6182 sata: Move drivers into new drivers/ata directory
At present we have the SATA and PATA drivers mixed up in the drivers/block
directory. It is better to split them out into their own place. Use
drivers/ata which is what Linux does.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
10e40d54b3 Kconfig: Add CONFIG_SATA to enable SATA
At present CONFIG_CMD_SATA enables the 'sata' command which also brings
in SATA support. Some boards may wish to enable SATA without the command.
Add a separate CONFIG to permit this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
3bf926c0dd Convert CONFIG_CMD_SATA to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_SATA

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
a6fb185c70 scsi: Drop scsi_print_error()
This function is only defined by one driver and is empty. Move it into
the SCSI implementation itself. We could remove it, but it should be
useful for debugging.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
b8beb6b463 scsi: Drop sym53c8xx driver
This driver is for a PowerPC board that will likely be removed soon.
Rather than converting it to driver model, drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
fedb428c5b Convert CONFIG_SCSI to Kconfig
This converts the following to Kconfig:
   CONFIG_SCSI

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
2cce586651 dtoc: Support multiple compatible strings in a node
Sometimes a node will have multiple compatible strings. Drivers may use
one or the other so the best approach seems to be to #define them to be
equivalent.

Update dtoc to support this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-07-11 10:08:19 -06:00
Alison Chaiken
564cf25d5b cmd gpt: test in sandbox
Make minor changes to README.gpt and sandbox_defconfig to support
testing of the gpt command's functionality in the sandbox.

Signed-off-by: Alison Chaiken <alison@peloton-tech.com>
2017-07-11 10:08:19 -06:00
Alison Chaiken
6b20c347a0 sandbox: README: fix partition command invocation
The instructions for creating a disk image that are presently in
README.sandbox fail because sfdisk doesn't know about GPT.

Signed-off-by: Alison Chaiken <alison@peloton-tech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:19 -06:00
Simon Glass
99b66605f0 moveconfig: Support looking for implied CONFIG options
Some CONFIG options can be implied by others and this can help to reduce
the size of the defconfig files. For example, CONFIG_X86 implies
CONFIG_CMD_IRQ, so we can put 'imply CMD_IRQ' under 'config X86' and
all x86 boards will have that option, avoiding adding CONFIG_CMD_IRQ to
each of the x86 defconfig files.

Add a -i option which searches for such options.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2017-07-11 10:08:19 -06:00
Simon Glass
d73fcb12e2 moveconfig: Support building a simple config database
Add a -b option which scans all the defconfigs and builds a database of
all the CONFIG options used by each. This is useful for querying later.

At present this only works with the separate -b option, which does not
move any configs. It would be possible to adjust the script to build the
database automatically when moving configs, but this might not be useful
as the database does not change that often.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:19 -06:00
Simon Glass
f3b8e6470c moveconfig: Add a constant for auto.conf
This filename is used a few times. Move it to a constant before adding
further uses.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:19 -06:00
Simon Glass
ddf91c6423 moveconfig: Tidy up the documentation and add hints
The newest clean-up features are not mentioned in the docs. Fix this and
add a few hints for particular workflows that are hopefully helpful.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:19 -06:00
Simon Glass
ee4e61bda4 moveconfig: Allow reading the defconfig list from stdin
Support passes in a defconfig filename of '-' to read the list from stdin
instead of from a file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:19 -06:00
Simon Glass
25f978cb1c moveconfig: Support providing a path to the defconfig files
It is convenient to provide the full patch to the defconfig files in some
situations, e.g. when the file was generated by a shell command (e.g.
'ls configs/zynq*').

Add support for this, and move the globbing code into a function with its
own documentation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:19 -06:00
Kever Yang
69aaec0bca rockchip: dts: rk3328: add aliases for mmc controller
Add aliases for mmc controller to get a fixed order with
emmc at index 0 and sdmmc at index 1.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:19 -06:00
Simon Glass
95ce385a4a dm: core: Add uclass_first/next_device_check()
Sometimes it is useful to iterate through all devices in a uclass and
skip over those which do not work correctly (e.g fail to probe). Add two
new functions to provide this feature.

The caller must check the return value each time to make sure that the
device is valid. But the device pointer is always returned.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:19 -06:00
Simon Glass
9856157259 dm: core: Test uclass_first/next_device() on probe failure
Add some tests which check the behaviour of uclass_first_device() and
uclass_next_device() when probing of a device fails.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:19 -06:00
Simon Glass
30a570a983 dm: core: Clarify uclass_first/next_device() comments
These are not as clear as they could be. Tidy them up a bit. Also fix a
tiny code-style nit.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:19 -06:00
Sjoerd Simons
2454b719fb rockchip: rk3288: Add pinctrl support for the gmac ethernet interface
Add support for the gmac ethernet interface to pinctrl. This hardcodes
the setup to match that of the firefly and Radxa Rock2 boards, using the
RGMII phy mode for gmac interface and GPIO4B0 as the phy reset GPIO.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 15:23:38 +02:00
Kever Yang
cc93c090d0 rockchip: evb-rk3328: enable boot on regulator
Enable all the boot-on regulator in default.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 15:23:38 +02:00
Kever Yang
df813322e5 rockchip: dts: rk3328-evb: add sdmmc-pwren regulator
Use fixed regulator for sdmmc-pwren for sdmmc power.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 15:23:38 +02:00
Kever Yang
fe450895ff rockchip: pinctrl: rk3328: use gpio instead of sdmmc-pwren
SDMMC-PWREN is a pin to control voltage for SDMMC IO, it may
be high active or low active, the dwmmc driver always assume
the sdmmc-pwren as high active.

Kernel treat this pin as fixed regulator instead of a pin from
controller, and then it can set in dts file upon board schematic,
that's a good solution, we can also do this in u-boot.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 15:23:38 +02:00
Wadim Egorov
a84b589e5d doc: rockchip: Add phyCORE-RK3288 RDK to board list
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 15:23:38 +02:00
Wadim Egorov
bafcf2db41 rockchip: Add basic support for phyCORE-RK3288 SoM based carrier board
The phyCORE-RK3288 is a SoM (System on Module) containing a RK3288 SoC.
The module can be connected to different carrier boards.
It can be also equipped with different RAM, SPI flash and eMMC variants.
The Rapid Development Kit option is using the following setup:

  - 1 GB DDR3 RAM (2 Banks)
  - 1x 4 KB EEPROM
  - DP83867 Gigabit Ethernet PHY
  - 16 MB SPI Flash
  - 4 GB eMMC Flash

Add basic support for the PCM-947 carrier board, a RK3288 based development
board made by PHYTEC. This board works in a combination with
the phyCORE-RK3288 System on Module.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 15:23:38 +02:00
Wadim Egorov
ad98f882e8 power: regulator: rk8xx: Allow input current/charger shutdown configuration
The RK818 PMIC contains a charger. Add very basic charger functionality
to be able to regulate the USB input current and charger shutdown limits.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 15:23:38 +02:00
Wadim Egorov
8926c2f584 power: regulator: rk8xx: Build get_ldo_reg only for SPL
Enabling CONFIG_SPL_POWER_SUPPORT will cause a compiler warning:
  ‘get_ldo_reg’ defined but not used [-Wunused-function]

Let's wrap get_ldo_reg(), rk808_ldo and rk818_ldo with ENABLE_DRIVER
which is only set for non SPL builds.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 15:23:37 +02:00
Meng Dongyang
f6f47c2ee1 rockchip: dts: rk3399: control vbus of typec by fixed regulator
Add fixed regulator for the port of typec0 and typec1 to control vbus
instead of gpio.

Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:49 +02:00
Meng Dongyang
863456ade3 rockchip: dts: rk3328: support and enable dwc2
Enable dwc2 controller and add fixed regulator for dwc2 controller to
control vbus.

Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:49 +02:00
Meng Dongyang
c93bef9323 rockchip: rk3328: board: add support of dwc2 gadget
Probe dwc2 udc in the function of board_usb_start to enable
usb gadget function.

Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:49 +02:00
Meng Dongyang
dd22bace7a usb: dwc2: use dev_read_bool() instead of fdt_getprop()
Use dev_read_bool() instead of fdt_getprop() to get the property
from DTS. And add a comment for "hnp-srp-disable" property to
fully describe its effect.

Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:49 +02:00
Meng Dongyang
6424de9303 rockchip: dts: rk3328: add fixed regulator node for xhci
The driver changes gpio to fixed regulator to control vbus, so add
fixed regulator node in DTS for xhci driver.

Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:49 +02:00
Philipp Tomsich
4ac72f5c5b usb: Kconfig: migrate USB_DWC2 to Kconfig
This change migrates the USB_DWC2 configuration item to Kconfig
and runs moveconfig to adjust header files and defconfig.

Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Split off into a separate patch:
Ran moveconfig to migrate other boards:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:49 +02:00
Meng Dongyang
296bd19e4e rockchip: dts: rk3328: add fixed regulator node for xhci
The driver changes gpio to fixed regulator to control vbus, so add
fixed regulator node in DTS for xhci driver.

Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:48 +02:00
Meng Dongyang
26a8b80fac usb: host: xhci-rockchip: use fixed regulator to control vbus
Use fixed regulator to control the voltage of vbus. Enable vbus
supply when usb start and disable vbus supply when usb stop.

Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:48 +02:00
Meng Dongyang
e85f00abda usb: Kconfig: config USB_XHCI_ROCKCHIP depends on DM_REGULATOR and DM_USB
The xhci-rockchip driver depends on DM_REGULATOR and DM_USB.
So add dependent features for xhci-rockchip driver in Kconfig.

Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:48 +02:00
Kever Yang
64a524b08a rockchip: rk3036: sync os_reg2 define with other soc
Rockchip using the same bit definition for dram info and write
to os_reg, the col and bw info is not correct and let's fix it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:48 +02:00
Kever Yang
d59b9dd397 rockchip: rk3036 remove CONFIG_RAM from defconfig
rk3036 sdram driver does not use DM, remove CONFIG_RAM first.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:48 +02:00
eric.gao@rock-chips.com
0c6d52bc4b rockchip: video: mipi: Modify format type for debug message
Modify format type for debug message.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
2017-07-11 12:13:48 +02:00
eric.gao@rock-chips.com
0c9eceb7af rockchip: video: mipi: Modify variable type for arm32 compatibility
Some address relevant varibable is defined originally as u64. To
compatible with arm32, this patch change them to uintptr_t type.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11 12:13:47 +02:00
eric.gao@rock-chips.com
e3ef41df48 rockchip: pwm: fix the register layout for the PWM controller
According to rk3288 spec, the pwm register order is:
    PWM_PWM0_CNT,
    PWM_PWM0_PERIOD_HPR,
    PWM_PWM0_DUTY_LPR,
    PWM_PWM0_CTRL
but the source code's order is:
  struct rk3288_pwm {
    u32 cnt;
    u32 duty_lpr;
    u32 period_hpr;
    u32 ctrl;
  };

So, correct it here. It is the same as RK3399.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Edited the commit message:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:47 +02:00
Kever Yang
419b08012a Revert "mmc: dw_mmc: rockchip: select proper card clock"
The origin patch get rockchip dwmmc by name 'ciu', which lead
to the SPL not able to remove 'clock-names' node in dts.
I'm not saying this is not correct, but I would prefer to handle
this in dts or clock driver to save memory for SPL.
For example the rk3288 SPL size has out of memory if not enable
BACK_TO_BROM option, there are many other SoCs has less internal
memory than rk3288.

This reverts commit 480a9b834c.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:47 +02:00
Kever Yang
d9379b1a89 rockchip: firefly-rk3399: enable dwmmc driver for the board
Enable mmc_dw_rockchip driver, disable CONFIG_SPL_OF_PLATDATA
first for some dependence patches still not merged.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11 12:13:47 +02:00
Kever Yang
522cd58077 rockchip: firefly-rk3399: dts: enable sdmmc device
Enable sdmmc device and add the spl boot device sequence.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:47 +02:00
Kever Yang
8093529809 rockchip: dwmmc: use max-frequency when OF_PLATDATA enabled
Since the 'clock-freq-min-max' is deprecated, we use max-frequency for
all rockchip SoC dwmmc controller.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:47 +02:00
Kever Yang
ebac2cf084 rockchip: rk3328: dtsi use max-frequency for mmc node
Since the 'clock-freq-min-max' is deprecated, we use max-frequency.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:47 +02:00
Kever Yang
16e358ac32 rockchip: rk3288: dtsi use max-frequency for mmc node
Since the 'clock-freq-min-max' is deprecated, we use max-frequency.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:47 +02:00
Kever Yang
3f7a725598 rockchip: rk3036: dtsi use max-frequency for mmc node
Since the 'clock-freq-min-max' is deprecated, we use max-frequency.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:46 +02:00
Kever Yang
b24a8ec15c rockchip: add evb_rk3229 board
evb_rk3229 is a RK3229 based board, with:
- 8GB eMMC;
- 1GB DDR SDRAM;
- 2 USB2.0 HOST port;
- 1 MAC port;
- 1 HDMI port;
- IR;
- WiFi;

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:46 +02:00
Kever Yang
a21e132894 rockchip: rk322x: add sysreset driver
Rockchip rk322x sysreset is much like rk3036 and other Rockchip SoCs,
only difference is that the target register address is different.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:46 +02:00
Kever Yang
168eef7ada rockchip: rk322x: add basic soc support
Enable soc support for SPL and U-boot skeleton.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:46 +02:00
Kever Yang
b647442ce8 rockchip: rk322x: add dts file
The dts files are from kernel and with modify to adapt U-Boot.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:46 +02:00
Kever Yang
5cc9d31a79 rockchip: rk322x: add pinctrl driver
Add init pinctrl driver support for:
- i2c;
- spi;
- uart;
- pwm;
- emmc/sdmmc;

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:46 +02:00
Kever Yang
045029cbd1 rockchip: rk322x: add clock driver
Add clock driver init support for:
- cpu, bus clock init;
- emmc, sdmmc clock;
- ddr clock;

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Fixed format specified (%x -> %p) in clk_rk322x.c:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:45 +02:00
Kever Yang
236776d63f rockchip: mkimage: add support for rk322x soc
Add support for rk322x package header in mkimage tool.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:45 +02:00
Kever Yang
3ee7e68739 rockchip: rv1108: disable CONFIG_RAM before we have driver
The rv1108 do not have DRAM driver now, so disable it first,
or else it will get conflict with the sdram common code.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:45 +02:00
Kever Yang
975e4abad2 rockchip: correct the bank0 ram size
The bank0 ram size should be the DRAM size minus reserved size,
the DRAM size may be 1GB, 2GB, 4GB, we can not hard code it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Added DECLARE_GLOBAL_DATA_PTR for RK3328, RK3368 and RK3399:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:45 +02:00
Kever Yang
c541a7a12a rockchip: dts: rk3368: add dmc node
Add dmc node to enable sdram driver.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:45 +02:00
Kever Yang
8f313328e5 rockchip: dts: rk3328: add dmc node
Add a dmc node for sdram driver.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:45 +02:00
Kever Yang
cc89369fb0 rockchip: rk3368: add sdram driver for U-Boot
Add sdram driver in U-Boot for get the correct sdram size from
sys_reg, so that U-Boot can co-work with Rockchip loader or SPL
to get different dram capability and then tell the kernel.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:45 +02:00
Kever Yang
39648e6167 rockchip: rk3328: add sdram driver in U-Boot
Add sdram driver in U-Boot for get the correct sdram size from
sys_reg, so that U-Boot can co-work with Rockchip loader or SPL
to get different dram capability and then tell the kernel.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:44 +02:00
Kever Yang
7805cdf494 rockchip: use common sdram function
Replace the sdram_init() in board init and rockchip_sdram_size() in
sdram driver for all the Rockchip SoCs which enable CONFIG_RAM.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Make dram_init() in rk3036-board.c conditional on CONFIG_RAM:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:44 +02:00
Kever Yang
6d1970fa8a rockchip: add sdram_common for common functions
There are some functions like sdram_size_mb can be re-used for
different rockchip SoCs, just put them into common file.
Add board_get_usable_ram_top() for ram_top init base on
SDRAM_MAX_SIZE.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Added SDRAM_MAX_SIZE definition for RK3036:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

fixup: 3036 fix for sdram_common
2017-07-11 12:13:44 +02:00
Kever Yang
be8da534e2 rockchip: rk3328: correct mem_region
According to rk3328 TRM:
0~0xff000000 is ddr space;
0xff000000~0xffffffff is device space.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:44 +02:00
Philipp Tomsich
8f1034e627 rockchip: dm: convert fdt_get to dev_read
With the new dev_read functions available, we can convert the rockchip
architecture-specific drivers and common drivers used by these devices
over to the dev_read family of calls.

This covers the DRAM controller initialisation for the RK3188, RK3288
and RK3399... all of these read some of the tuning/setup/timing
parameters from the device-tree.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11 12:13:44 +02:00
Philipp Tomsich
3d40479f00 rockchip: ns16550: dm: convert fdt_get to dev_read
With the new dev_read functions available, we can convert the rockchip
architecture-specific drivers and common drivers used by these devices
over to the dev_read family of calls.

This covers the serial driver (ns16550 and compatible) used for the
Rockchip devices.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11 12:13:44 +02:00
Philipp Tomsich
7ad326a905 rockchip: net: dm: convert fdt_get to dev_read
With the new dev_read functions available, we can convert the rockchip
architecture-specific drivers and common drivers used by these devices
over to the dev_read family of calls.

This covers the Gigabit Ethernet MAC (i.e. common designware driver and
rockchip-specific wrapper).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11 12:13:43 +02:00
Philipp Tomsich
fd1bf8df25 rockchip: mmc: dm: convert fdt_get to dev_read
With the new dev_read functions available, we can convert the rockchip
architecture-specific drivers and common drivers used by these devices
over to the dev_read family of calls.

This covers the dw_mmc and sdhci wrapper drivers for Rockchip.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11 12:13:43 +02:00
Philipp Tomsich
f2708c97c2 rockchip: xhci: dm: convert fdt_get to dev_read
With the new dev_read functions available, we can convert the rockchip
architecture-specific drivers and common drivers used by these devices
over to the dev_read family of calls.

This change covers the USB3 (xhci) driver for the Rockchip devices.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11 12:13:43 +02:00
Philipp Tomsich
6c65577ce6 rockchip: spi: dm: convert fdt_get to dev_read
With the new dev_read functions available, we can convert the rockchip
architecture-specific drivers and common drivers used by these devices
over to the dev_read family of calls.

This change covers the rk_spi.c (SPI driver) used in Rockchip devices.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11 12:13:43 +02:00
Philipp Tomsich
9f4f914d7f rockchip: pinctrl: dm: convert fdt_get to dev_read
With the new dev_read functions available, we can convert the rockchip
architecture-specific drivers and common drivers used by these devices
over to the dev_read family of calls.

This change covers the pinctrl drivers for the Rockchip devices.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11 12:13:43 +02:00
Jean-Jacques Hiblot
6b26aaef08 pipe3: Fix broken dependency
ARCH_OMAP2 has been renamed ARCH_OMAP2PLUS in commit a93fbf4a78
("ARM: omap2+: rename config to ARCH_OMAP2PLUS and consolidate Kconfig")

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:26:05 -04:00
Patrice Chotard
c5c1756c68 mtd: stm32: use parameter instead of default value
To set wait state, a hard coded value is used instead of using
latency parameter. stm32_flash_latency_cfg() is currently used
in arch/arm/mach-stm32/stm32f4/clock.c and in
drivers/clk/clk_stm32f7.c with, in both case, "5" as parameter.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-07-10 14:26:05 -04:00
Andrew F. Davis
9e58d4dbe3 arm: mach-keystone: Modify secure image size before copy
The size of the secure image does not include the size of the
header, subtract this out before we move the image or we grab
extra data after the image.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-07-10 14:26:05 -04:00
Lokesh Vutla
7bdc6947d2 ARM: dts: OMAP5+: Enable gpio in SPL
gpio2 is used to detect lcd based on which pin mux is done in SPL.
gpio7 is used to enable vtt regulator. Enable these two gpio nodes
in SPL.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:26:04 -04:00
Lokesh Vutla
3c9c4a2c50 arm: omap4+: Enable spl_early_init()
Enable spl_early_init() so that spl can use
DT very early during boot.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:26:04 -04:00
Lokesh Vutla
4bd754d8ab arm: omap: Detect boot mode very early
ROM stores the boot params information in a known location
and passes it to SPL. This information needs to be copied
very early during boot or else there is a chance of getting
corrupted by SPL. So move this boot device detection very early
during boot.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:26:04 -04:00
Jorge Ramirez-Ortiz
d754254f20 ARM64: poplar: hi3798cv200: u-boot support for Poplar 96Boards
This port adds support for:
        1) Serial
        2) eMMC
        3) USB

It has been tested with ARM TRUSTED FIRMWARE running u-boot as the
BL33 executable [see board's README]

eMMC has been tested for reading and booting the loader and linux
kernels as well as saving the u-boot environment.

USB has been tested with ASIX networking adapter and SanDisk 7.4GB
drive.

PSCI has been tested via the reset call (PSCI executes from DDR)

The firwmare upgrade process has been tested via TFTP and USB FAT
filesystem containing the fastboot.bin image in one of the partitions.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
2017-07-10 14:26:03 -04:00
Jorge Ramirez-Ortiz
fc50a6cbc0 driver: mmc: update debug info
This driver is used in another board; remove board information from
the driver debug log.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-10 14:26:03 -04:00
Jorge Ramirez-Ortiz
ccaa83f802 ARM64: dts: hi3798cv200-poplar: add device tree bindings
Pulled from Linux 4.12-rc3

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-10 14:26:02 -04:00
Christophe Kerello
bb44b96803 pinctrl: stm32: add set_state ops
set_state_ops is kept under PINCTRL_FULL flag in order
to decrease memory footprint in some configuration.
PINCTRL_FULL can be enabled for debug purpose.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-07-10 14:26:02 -04:00
Christophe Kerello
ad0376e093 pinctrl: stm32: handle a configuration list
This patch handles a configuration list behind pinctrl-0
like pinctrl-0 = <&qspi_clk_a &qspi_bk1_a &qspi_bk2_a>;

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-10 14:26:02 -04:00
Cooper Jr., Franklin
82f40f3e8b defconfig: k2g_evm_defconfig: Add K2G ICE to OF_LIST
Include K2G ICE to OF_LIST so it can be used for runtime board
detection.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:26:01 -04:00
Cooper Jr., Franklin
bc420967be ARM: k2g: Add K2G ICE DTB to the list of possible DTBs
K2G ICE evm will have its own dtb. Therefore, add it to the list of dtbs
located in the appended U-boot dtb FIT image. Therefore, when swapping out
dtbs K2G ICE boards can grab the correct one.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:26:01 -04:00
Cooper Jr., Franklin
6aba890eb6 ARM: dts: k2g: Add DT support for K2G Industrial Communication Engine evm
Add basic DT support for K2G ICE evm. Only minimal peripherals are
supported to allow console output and MMC boot.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:26:01 -04:00
Cooper Jr., Franklin
42468c8b77 ARM: dts: k2g: Disable netcp by default
Disable netcp by default like all other peripherals in the dtsi file.
Enable the peripheral explicitly in the board specific dts file.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:26:00 -04:00
Cooper Jr., Franklin
0d3f97db71 ARM: dts: keystone-k2g-evm: Add unit address to memory node
Upstream Linux has the unit address being added to the various 66AK2Gx
boards dts. Therefore, update the dts to mimic this change.

Also remove memory node from the base K2G dtsi file.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:26:00 -04:00
Cooper Jr., Franklin
df5ec72d7a ARM: dts: keystone-k2g: Remove skeleton.dtsi
Adding the unit address to the memory node was causing the below error:
Warning (reg_format): "reg" property in /memory has invalid length
(8 bytes) (#address-cells == 2, #size-cells == 2)

Further debugging showed that this was due to the memory node added by
default to skeleton.dtsi which was being included in keystone-k2g.dtsi.
Adding a missing node was all that was needed to remove this deprecated
dtsi file from the SoC dtsi. With skeleton.dtsi removed the dtc compiler
no longer complained about including the unit address for the memory node.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:26:00 -04:00
Cooper Jr., Franklin
92761fcc2f ARM: k2g: Update board_name u-boot env variable at runtime
Enable CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG to allow "board_name" to
be set depending on the board it is being ran on.

Update findfdt to use this new dynamic board_name value to determine
which dtb should be used.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:59 -04:00
Cooper Jr., Franklin
4f490402c4 ARM: k2g: Use board detection to wrap K2G GP specific calls
Certain peripherals used by K2G GP aren't used on K2G ICE evm. Or
configuration is slightly different. Therefore, use board detection to
deal with these variations.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:59 -04:00
Cooper Jr., Franklin
e66a5da3f9 board: ks2: Use board detection to wrap code not specific to K2G ICE evm
Some code doesn't apply to K2G ICE evm. Therefore, use board detection to
wrap these calls.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:59 -04:00
Cooper Jr., Franklin
652606eccf ARM: k2g: Add DDR3 configuration for K2G ICE evm
Add configuration settings used by the K2G ICE evm. Also use board
detection to determine which DDR3 configuration to use.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:58 -04:00
Cooper Jr., Franklin
b9b342eaec ARM: k2g: Add pinmux support for K2G ICE evm
Add basic pinmux data for new K2G ICE evm. Also add pinmuxing for a
generic K2G evm which includes I2C 0 and 1 used for board detection
purposes.

Since multiple K2G boards are supported that means initially generic
pinmuxing should be used when board detection hasn't ran. Once board
detection runs the proper pinmuxing can be reran to match the board
being ran on.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:58 -04:00
Cooper Jr., Franklin
e6e2435f39 ks2_evm: Add EEPROM based board detection helper functions
Add a function that can be used to determine if the board being ran on is
a K2G Industrial Communication Engine EVM or K2G General Purpose EVM based
on values programmed on the EEPROM.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:58 -04:00
Cooper Jr., Franklin
e5e546aad1 ARM: k2g: Program DDRPHY_DATX8 registers via mask and value variables
Different K2G evms may need to program the various
KS2_DDRPHY_DATX8_X_OFFSET registers in different ways. Therefore, use
the mask and val registers for each KS2_DDRPHY_DATAX_X_OFFSET to
properly program the register.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:57 -04:00
Cooper Jr., Franklin
a76a6f3e04 ARM: k2g: Program DDR PHY MR2 register with the default value
K2G GP doesn't require the MR2 register to be programed since the
default is good enough. However, newer K2G boards do need to change
this register value. Therefore, instead of not writing this register if
ran on a K2G board just program the value to be written to match the
default/reset value.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:57 -04:00
Cooper Jr., Franklin
f8b4a2d7e2 ARM: keystone2: Add additional fields used for DDR3 configuration
Future boards will need to configure DDR3 registers in a slightly
different manner. Support this by defining additional variables and
defines that will be utilized later.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:56 -04:00
Cooper Jr., Franklin
3107696784 defconfig: keystone2: Enable U-boot runtime DTB detection
Enable various config options to allow U-boot at runtime to select the
proper dtb to use from the list of dtb's within the FIT image.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:56 -04:00
Cooper Jr., Franklin
e820f523d8 ks2_evm: Add EEPROM based board detection
Some K2G evms have their EEPROM programming while most do not. Therefore,
add EEPROM board detection to be used as the default method and fall back
to the alternative board detection when needed.

Also reorder board configuration. Perform bare minimal configuration
initially since board detection hasn't ran. Finish board configuration
once the board has been identified.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:56 -04:00
Cooper Jr., Franklin
7234f215cc ARM: keystone2: Define board_fit_config_name_match for Keystone 2 boards
Now with support for U-boot runtime dtb selection each board needs to
define board_fit_config_name_match so U-boot can determine what the
correct dtb is within the FIT blob.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:55 -04:00
Cooper Jr., Franklin
5f48da9a98 ARM: k2g: Define embedded_dtb_select for runtime DTB selection in U-boot
For K2G, runtime DTB selection utilizes the embedded_dtb_select function.
Therefore, define the function which will perform a EEPROM read and then
retries selecting the correct dtb now that it can detect which board its
on. For other Keystone devices use an empty function since they will still
use the embedded FIT functionality but their FIT will only contain a single
dtb.

Most production K2G boards do not have their EEPROM programmed. Therefore,
perform a test to verify a K2G GP is currently being used and if it is then
set the values normally set by a EEPROM read.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:55 -04:00
Cooper Jr., Franklin
85bfe48b0a ARM: keystone2: Allow to build with all image formats
u-boot.bin is a copy of:
u-boot-fit-dtb.bin if CONFIG_FIT_EMBED is enabled,
u-boot-dtb.bin if CONFIG_OF_SEPARATE is enabled,
u-boot-nodtb.bin if DT is not enabled.
So, use u-boot.bin to to generate keystone images instead of
u-boot-dtb.bin

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:55 -04:00
Cooper Jr., Franklin
6f59fb07f4 Makefile: Build additional binaries for dtb FIT blobs appended to U-boot
Add additional make targets and options for building embedded FIT U-boot
images.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:54 -04:00
Cooper Jr., Franklin
af9e6ad4ab board_f: Add new function to allow runtime DTB selection
Runtime U-boot dtb selection is generally a two step process. First step
is to simply use an initial generic dtb. The second step is to select
the dtb and perhaps execute additional code ones U-boot knows what board
it is running on. Embedded_dtb_select handles the second step by allowing
board specific code to run and perform what ever necessary configuration
that is needed.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:54 -04:00
Cooper Jr., Franklin
80364a42c1 arm: dts: Add new "generic" 66AK2Gx device tree file.
With U-boot runtime board detect for DTB selection a "default" dtb needs
to be created. This will be used temporarily until the "proper" dtb is
selected.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:54 -04:00
Cooper Jr., Franklin
e0f3a3dc4f ARM: dts: k2g: Introduce U-boot specific dtsi file
Introduce K2G evm specific dtsi file for U-boot specific configurations.
This will help seperate U-boot only configurations thus making it easier to
keep device tree files synced between U-boot and Linux.

For now only add nodes to allow i2c drivers to be probed early during
the boot process.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:53 -04:00
Cooper Jr., Franklin
d97974099b dts: Allow OF_LIST to depend on FIT_EMBED
OF_LIST will be useable by SPL and U-boot. Therefore, update its
dependency to allow it to be enable by either SPL or U-boot specific
config option.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Andrew F. Davis <afd@ti.com>
2017-07-10 14:25:53 -04:00
Cooper Jr., Franklin
69e8d4ba7f ti: common: board_detect: Add function to determine if EEPROM was read
When the EEPROM is first read its contents are stored in memory as a
cache to avoid further I2C operations. To determine if the EEPROM was
previously read the easiest way is to check the memory to see if the
EEPROM's magic header value is set. Create a new function that can
determine if the EEPROM was previously read or not without having to
perform a I2C transaction.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:53 -04:00
Cooper Jr., Franklin
2059ecf30f fdt: Enable selecting correct DTB from appended FIT Image
This patch gives U-boot the runtime support to have the board specific
code decide which FDT to use. This is especially useful for devices
that need this type of runtime determination and also doesn't use SPL.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:52 -04:00
Cooper Jr., Franklin
92926bc80c boot_fit: Create helper functions that can be used to select DTB out of FIT
Some platforms may append a FIT image to the U-boot image. This function
aids in parsing the FIT image and selecting the correct DTB at runtime.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:50 -04:00
Cooper Jr., Franklin
3863f840fa spl: fit: Break out some functions into a common file
Some of the functions within spl_fit will be used for non spl purposes.
Instead of duplicating functions simply break the functions to be reused
into its own file.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Only add the new define to image.h, otherwise we see breakage
due to massive include leakage into host tools in some cases]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:24:39 -04:00
Nishanth Menon
e936f997a9 ti: common: board_detect: Allow settings board detection variables manually
In some situations the EEPROM used for board detection may not be
programmed or simply programmed incorrectly. Therefore, it may be
necessary to "simulate" reading the contents of the EEPROM to set
appropriate variables used in the board detection code.

This may also be helpful in certain boot modes where doing i2c reads
may be costly and the config supports running only a specific board.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Franklin S Cooper Jr. <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 13:45:35 -04:00
Cooper Jr., Franklin
a75df9aef0 ARM: dts: keystone-k2e-evm: Add U-boot specific dtsi file
With Davinci I2C switching to device model, K2E requires U-boot specific
device tree entries. This is only required for I2C 1 which is needed
extremely early during the boot process.

Fixes: 1743d040b1 ("ARM: keystone: Enable DM_I2C by default")
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
2017-07-10 13:45:34 -04:00
2302 changed files with 24959 additions and 12494 deletions

1
.gitignore vendored
View File

@@ -30,6 +30,7 @@
#
# Top-level generic files
#
fit-dtb.blob
/MLO*
/SPL*
/System.map

View File

@@ -0,0 +1,16 @@
NOP PHY driver
This driver is used to stub PHY operations in a driver (USB, SATA).
This is useful when the 'client' driver (USB, SATA, ...) uses the PHY framework
and there is no actual PHY harwdare to drive.
Required properties:
- compatible : must contain "nop-phy"
- #phy-cells : must contain <0>
Example:
nop_phy {
compatible = "nop-phy";
#phy-cells = <0>;
};

View File

@@ -0,0 +1,22 @@
Broadcom STB wake-up Timer
The Broadcom STB wake-up timer provides a 27Mhz resolution timer, with the
ability to wake up the system from low-power suspend/standby modes.
Required properties:
- compatible : should contain "brcm,brcmstb-waketimer"
- reg : the register start and length for the WKTMR block
- interrupts : The TIMER interrupt
- interrupt-parent: The phandle to the Always-On (AON) Power Management (PM) L2
interrupt controller node
- clocks : The phandle to the UPG fixed clock (27Mhz domain)
Example:
waketimer@f0411580 {
compatible = "brcm,brcmstb-waketimer";
reg = <0xf0411580 0x14>;
interrupts = <0x3>;
interrupt-parent = <&aon_pm_l2_intc>;
clocks = <&upg_fixed>;
};

10
Kconfig
View File

@@ -95,6 +95,16 @@ config SYS_MALLOC_F_LEN
particular needs this to operate, so that it can allocate the
initial serial device and any others that are needed.
config SPL_SYS_MALLOC_F_LEN
hex "Size of malloc() pool in spl before relocation"
depends on SYS_MALLOC_F
default SYS_MALLOC_F_LEN
help
Before relocation, memory is very limited on many platforms. Still,
we can provide a small malloc() pool if needed. Driver model in
particular needs this to operate, so that it can allocate the
initial serial device and any others that are needed.
menuconfig EXPERT
bool "Configure standard U-Boot features (expert users)"
default y

View File

@@ -96,11 +96,11 @@ F: arch/arm/cpu/arm1136/mx*/
F: arch/arm/cpu/arm926ejs/mx*/
F: arch/arm/cpu/armv7/mx*/
F: arch/arm/cpu/armv7/vf610/
F: arch/arm/imx-common/
F: arch/arm/mach-imx/
F: arch/arm/include/asm/arch-imx/
F: arch/arm/include/asm/arch-mx*/
F: arch/arm/include/asm/arch-vf610/
F: arch/arm/include/asm/imx-common/
F: arch/arm/include/asm/mach-imx/
F: board/freescale/*mx*/
ARM HISILICON
@@ -324,12 +324,6 @@ S: Maintained
T: git git://git.denx.de/u-boot-mpc8xx.git
F: arch/powerpc/cpu/mpc8xx/
POWERPC MPC82XX
M: Wolfgang Denk <wd@denx.de>
S: Maintained
T: git git://git.denx.de/u-boot-mpc82xx.git
F: arch/powerpc/cpu/mpc82*/
POWERPC MPC83XX
M: Mario Six <mario.six@gdsys.cc>
S: Maintained
@@ -458,6 +452,7 @@ F: drivers/video/
X86
M: Simon Glass <sjg@chromium.org>
M: Bin Meng <bmeng.cn@gmail.com>
S: Maintained
T: git git://git.denx.de/u-boot-x86.git
F: arch/x86/

View File

@@ -3,9 +3,9 @@
#
VERSION = 2017
PATCHLEVEL = 07
PATCHLEVEL = 09
SUBLEVEL =
EXTRAVERSION =
EXTRAVERSION = -rc1
NAME =
# *DOCUMENTATION*
@@ -349,7 +349,7 @@ OBJDUMP = $(CROSS_COMPILE)objdump
AWK = awk
PERL = perl
PYTHON ?= python
DTC = dtc
DTC ?= dtc
CHECK = sparse
CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
@@ -516,6 +516,9 @@ include/config/%.conf: $(KCONFIG_CONFIG) include/config/auto.conf.cmd
@# Otherwise, 'make silentoldconfig' would be invoked twice.
$(Q)touch include/config/auto.conf
u-boot.cfg spl/u-boot.cfg tpl/u-boot.cfg: include/config.h FORCE
$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.autoconf $(@)
-include include/autoconf.mk
-include include/autoconf.mk.dep
@@ -851,7 +854,7 @@ quiet_cmd_cfgcheck = CFGCHK $2
cmd_cfgcheck = $(srctree)/scripts/check-config.sh $2 \
$(srctree)/scripts/config_whitelist.txt $(srctree)
all: $(ALL-y)
all: $(ALL-y) cfg
ifeq ($(CONFIG_DM_I2C_COMPAT)$(CONFIG_SANDBOX),y)
@echo "===================== WARNING ======================"
@echo "This board uses CONFIG_DM_I2C_COMPAT. Please remove"
@@ -873,7 +876,21 @@ dts/dt.dtb: checkdtc u-boot
quiet_cmd_copy = COPY $@
cmd_copy = cp $< $@
ifeq ($(CONFIG_OF_SEPARATE),y)
ifeq ($(CONFIG_FIT_EMBED),y)
fit-dtb.blob: dts/dt.dtb FORCE
$(call if_changed,mkimage)
MKIMAGEFLAGS_fit-dtb.blob = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
-a 0 -e 0 -E \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) -d /dev/null
u-boot-fit-dtb.bin: u-boot-nodtb.bin fit-dtb.blob
$(call if_changed,cat)
u-boot.bin: u-boot-fit-dtb.bin FORCE
$(call if_changed,copy)
else ifeq ($(CONFIG_OF_SEPARATE),y)
u-boot-dtb.bin: u-boot-nodtb.bin dts/dt.dtb FORCE
$(call if_changed,cat)
@@ -885,7 +902,7 @@ u-boot.bin: u-boot-nodtb.bin FORCE
endif
%.imx: %.bin
$(Q)$(MAKE) $(build)=arch/arm/imx-common $@
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
%.vyb: %.imx
$(Q)$(MAKE) $(build)=arch/arm/cpu/armv7/vf610 $@
@@ -1050,10 +1067,10 @@ tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE
$(call if_changed,pad_cat)
SPL: spl/u-boot-spl.bin FORCE
$(Q)$(MAKE) $(build)=arch/arm/imx-common $@
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL u-boot.bin FORCE
$(Q)$(MAKE) $(build)=arch/arm/imx-common $@
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
MKIMAGEFLAGS_u-boot.ubl = -n $(UBL_CONFIG) -T ublimage -e $(CONFIG_SYS_TEXT_BASE)
@@ -1215,13 +1232,16 @@ u-boot.elf: u-boot.bin
$(Q)$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< u-boot-elf.o
$(call if_changed,u-boot-elf)
ARCH_POSTLINK := $(wildcard $(srctree)/arch/$(ARCH)/Makefile.postlink)
# Rule to link u-boot
# May be overridden by arch/$(ARCH)/config.mk
quiet_cmd_u-boot__ ?= LD $@
cmd_u-boot__ ?= $(LD) $(LDFLAGS) $(LDFLAGS_u-boot) -o $@ \
-T u-boot.lds $(u-boot-init) \
--start-group $(u-boot-main) --end-group \
$(PLATFORM_LIBS) -Map u-boot.map
$(PLATFORM_LIBS) -Map u-boot.map; \
$(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true)
quiet_cmd_smap = GEN common/system_map.o
cmd_smap = \
@@ -1231,7 +1251,7 @@ cmd_smap = \
-c $(srctree)/common/system_map.c -o common/system_map.o
u-boot: $(u-boot-init) $(u-boot-main) u-boot.lds FORCE
$(call if_changed,u-boot__)
+$(call if_changed,u-boot__)
ifeq ($(CONFIG_KALLSYMS),y)
$(call cmd,smap)
$(call cmd,u-boot__) common/system_map.o
@@ -1338,6 +1358,7 @@ define filechk_timestamp.h
LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TIME "%T"'; \
LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TZ "%z"'; \
LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \
LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \
else \
return 42; \
fi; \
@@ -1346,6 +1367,7 @@ define filechk_timestamp.h
LC_ALL=C date +'#define U_BOOT_TIME "%T"'; \
LC_ALL=C date +'#define U_BOOT_TZ "%z"'; \
LC_ALL=C date +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \
LC_ALL=C date +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \
fi)
endef
@@ -1473,7 +1495,7 @@ CLEAN_DIRS += $(MODVERDIR) \
$(filter-out include, $(shell ls -1 $d 2>/dev/null))))
CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \
boot* u-boot* MLO* SPL System.map
boot* u-boot* MLO* SPL System.map fit-dtb.blob
# Directories & files removed with 'make mrproper'
MRPROPER_DIRS += include/config include/generated spl tpl \

379
README
View File

@@ -810,8 +810,6 @@ The following options need to be configured:
CONFIG_CMD_MISC Misc functions like sleep etc
CONFIG_CMD_MMC * MMC memory mapped support
CONFIG_CMD_MII * MII utility commands
CONFIG_CMD_MTDPARTS * MTD partition support
CONFIG_CMD_NAND * NAND support
CONFIG_CMD_NET bootp, tftpboot, rarpboot
CONFIG_CMD_NFS NFS support
CONFIG_CMD_PCA953X * PCA953x I2C gpio commands
@@ -826,7 +824,6 @@ The following options need to be configured:
CONFIG_CMD_RUN run command in env variable
CONFIG_CMD_SANDBOX * sb command to access sandbox features
CONFIG_CMD_SAVES * save S record dump
CONFIG_SCSI * SCSI Support
CONFIG_CMD_SDRAM * print SDRAM configuration information
(requires CONFIG_CMD_I2C)
CONFIG_CMD_SF * Read/write/erase SPI NOR flash
@@ -1043,16 +1040,11 @@ The following options need to be configured:
Default is 32bit.
- SCSI Support:
At the moment only there is only support for the
SYM53C8XX SCSI controller; define
CONFIG_SCSI_SYM53C8XX to enable it.
CONFIG_SYS_SCSI_MAX_LUN [8], CONFIG_SYS_SCSI_MAX_SCSI_ID [7] and
CONFIG_SYS_SCSI_MAX_DEVICE [CONFIG_SYS_SCSI_MAX_SCSI_ID *
CONFIG_SYS_SCSI_MAX_LUN] can be adjusted to define the
maximum numbers of LUNs, SCSI ID's and target
devices.
CONFIG_SYS_SCSI_SYM53C8XX_CCF to fix clock timing (80Mhz)
The environment variable 'scsidevs' is set to the number of
SCSI devices found during the last scan.
@@ -1626,11 +1618,6 @@ The following options need to be configured:
the malloc area (as defined by CONFIG_SYS_MALLOC_LEN) should
be at least 4MB.
CONFIG_LZO
If this option is set, support for LZO compressed images
is included.
- MII/PHY support:
CONFIG_PHY_ADDR
@@ -2802,13 +2789,6 @@ FIT uImage format:
kernel. Needed for UBI support.
- UBI support
CONFIG_CMD_UBI
Adds commands for interacting with MTD partitions formatted
with the UBI flash translation layer
Requires also defining CONFIG_RBTREE
CONFIG_UBI_SILENCE_MSG
Make the verbose messages from UBI stop printing. This leaves
@@ -2877,13 +2857,6 @@ FIT uImage format:
default: 0
- UBIFS support
CONFIG_CMD_UBIFS
Adds commands for interacting with UBI volumes formatted as
UBIFS. UBIFS is read-only in u-boot.
Requires UBI support as well as CONFIG_LZO
CONFIG_UBIFS_SILENCE_MSG
Make the verbose messages from UBIFS stop printing. This leaves
@@ -3438,90 +3411,6 @@ following configurations:
Builds up envcrc with the target environment so that external utils
may easily extract it and embed it in final U-Boot images.
- CONFIG_ENV_IS_IN_FLASH:
Define this if the environment is in flash memory.
a) The environment occupies one whole flash sector, which is
"embedded" in the text segment with the U-Boot code. This
happens usually with "bottom boot sector" or "top boot
sector" type flash chips, which have several smaller
sectors at the start or the end. For instance, such a
layout can have sector sizes of 8, 2x4, 16, Nx32 kB. In
such a case you would place the environment in one of the
4 kB sectors - with U-Boot code before and after it. With
"top boot sector" type flash chips, you would put the
environment in one of the last sectors, leaving a gap
between U-Boot and the environment.
- CONFIG_ENV_OFFSET:
Offset of environment data (variable area) to the
beginning of flash memory; for instance, with bottom boot
type flash chips the second sector can be used: the offset
for this sector is given here.
CONFIG_ENV_OFFSET is used relative to CONFIG_SYS_FLASH_BASE.
- CONFIG_ENV_ADDR:
This is just another way to specify the start address of
the flash sector containing the environment (instead of
CONFIG_ENV_OFFSET).
- CONFIG_ENV_SECT_SIZE:
Size of the sector containing the environment.
b) Sometimes flash chips have few, equal sized, BIG sectors.
In such a case you don't want to spend a whole sector for
the environment.
- CONFIG_ENV_SIZE:
If you use this in combination with CONFIG_ENV_IS_IN_FLASH
and CONFIG_ENV_SECT_SIZE, you can specify to use only a part
of this flash sector for the environment. This saves
memory for the RAM copy of the environment.
It may also save flash memory if you decide to use this
when your environment is "embedded" within U-Boot code,
since then the remainder of the flash sector could be used
for U-Boot code. It should be pointed out that this is
STRONGLY DISCOURAGED from a robustness point of view:
updating the environment in flash makes it always
necessary to erase the WHOLE sector. If something goes
wrong before the contents has been restored from a copy in
RAM, your target system will be dead.
- CONFIG_ENV_ADDR_REDUND
CONFIG_ENV_SIZE_REDUND
These settings describe a second storage area used to hold
a redundant copy of the environment data, so that there is
a valid backup copy in case there is a power failure during
a "saveenv" operation.
BE CAREFUL! Any changes to the flash layout, and some changes to the
source code will make it necessary to adapt <board>/u-boot.lds*
accordingly!
- CONFIG_ENV_IS_IN_NVRAM:
Define this if you have some non-volatile memory device
(NVRAM, battery buffered SRAM) which you want to use for the
environment.
- CONFIG_ENV_ADDR:
- CONFIG_ENV_SIZE:
These two #defines are used to determine the memory area you
want to use for environment. It is assumed that this memory
can just be read and written to, without any special
provision.
BE CAREFUL! The first access to the environment happens quite early
in U-Boot initialization (when we try to get the setting of for the
console baudrate). You *MUST* have mapped your NVRAM area then, or
@@ -3532,285 +3421,17 @@ environment in RAM: we could work on NVRAM directly, but we want to
keep settings there always unmodified except somebody uses "saveenv"
to save the current settings.
- CONFIG_ENV_IS_IN_EEPROM:
Use this if you have an EEPROM or similar serial access
device and a driver for it.
- CONFIG_ENV_OFFSET:
- CONFIG_ENV_SIZE:
These two #defines specify the offset and size of the
environment area within the total memory of your EEPROM.
- CONFIG_SYS_I2C_EEPROM_ADDR:
If defined, specified the chip address of the EEPROM device.
The default address is zero.
- CONFIG_SYS_I2C_EEPROM_BUS:
If defined, specified the i2c bus of the EEPROM device.
- CONFIG_SYS_EEPROM_PAGE_WRITE_BITS:
If defined, the number of bits used to address bytes in a
single page in the EEPROM device. A 64 byte page, for example
would require six bits.
- CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS:
If defined, the number of milliseconds to delay between
page writes. The default is zero milliseconds.
- CONFIG_SYS_I2C_EEPROM_ADDR_LEN:
The length in bytes of the EEPROM memory array address. Note
that this is NOT the chip address length!
- CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW:
EEPROM chips that implement "address overflow" are ones
like Catalyst 24WC04/08/16 which has 9/10/11 bits of
address and the extra bits end up in the "chip address" bit
slots. This makes a 24WC08 (1Kbyte) chip look like four 256
byte chips.
Note that we consider the length of the address field to
still be one byte because the extra address bits are hidden
in the chip address.
- CONFIG_SYS_EEPROM_SIZE:
The size in bytes of the EEPROM device.
- CONFIG_ENV_EEPROM_IS_ON_I2C
define this, if you have I2C and SPI activated, and your
EEPROM, which holds the environment, is on the I2C bus.
- CONFIG_I2C_ENV_EEPROM_BUS
if you have an Environment on an EEPROM reached over
I2C muxes, you can define here, how to reach this
EEPROM. For example:
#define CONFIG_I2C_ENV_EEPROM_BUS 1
EEPROM which holds the environment, is reached over
a pca9547 i2c mux with address 0x70, channel 3.
- CONFIG_ENV_IS_IN_DATAFLASH:
Define this if you have a DataFlash memory device which you
want to use for the environment.
- CONFIG_ENV_OFFSET:
- CONFIG_ENV_ADDR:
- CONFIG_ENV_SIZE:
These three #defines specify the offset and size of the
environment area within the total memory of your DataFlash placed
at the specified address.
- CONFIG_ENV_IS_IN_SPI_FLASH:
Define this if you have a SPI Flash memory device which you
want to use for the environment.
- CONFIG_ENV_OFFSET:
- CONFIG_ENV_SIZE:
These two #defines specify the offset and size of the
environment area within the SPI Flash. CONFIG_ENV_OFFSET must be
aligned to an erase sector boundary.
- CONFIG_ENV_SECT_SIZE:
Define the SPI flash's sector size.
- CONFIG_ENV_OFFSET_REDUND (optional):
This setting describes a second storage area of CONFIG_ENV_SIZE
size used to hold a redundant copy of the environment data, so
that there is a valid backup copy in case there is a power failure
during a "saveenv" operation. CONFIG_ENV_OFFSET_REDUND must be
aligned to an erase sector boundary.
- CONFIG_ENV_SPI_BUS (optional):
- CONFIG_ENV_SPI_CS (optional):
Define the SPI bus and chip select. If not defined they will be 0.
- CONFIG_ENV_SPI_MAX_HZ (optional):
Define the SPI max work clock. If not defined then use 1MHz.
- CONFIG_ENV_SPI_MODE (optional):
Define the SPI work mode. If not defined then use SPI_MODE_3.
- CONFIG_ENV_IS_IN_REMOTE:
Define this if you have a remote memory space which you
want to use for the local device's environment.
- CONFIG_ENV_ADDR:
- CONFIG_ENV_SIZE:
These two #defines specify the address and size of the
environment area within the remote memory space. The
local device can get the environment from remote memory
space by SRIO or PCIE links.
BE CAREFUL! For some special cases, the local device can not use
"saveenv" command. For example, the local device will get the
environment stored in a remote NOR flash by SRIO or PCIE link,
but it can not erase, write this NOR flash by SRIO or PCIE interface.
- CONFIG_ENV_IS_IN_NAND:
Define this if you have a NAND device which you want to use
for the environment.
- CONFIG_ENV_OFFSET:
- CONFIG_ENV_SIZE:
These two #defines specify the offset and size of the environment
area within the first NAND device. CONFIG_ENV_OFFSET must be
aligned to an erase block boundary.
- CONFIG_ENV_OFFSET_REDUND (optional):
This setting describes a second storage area of CONFIG_ENV_SIZE
size used to hold a redundant copy of the environment data, so
that there is a valid backup copy in case there is a power failure
during a "saveenv" operation. CONFIG_ENV_OFFSET_REDUND must be
aligned to an erase block boundary.
- CONFIG_ENV_RANGE (optional):
Specifies the length of the region in which the environment
can be written. This should be a multiple of the NAND device's
block size. Specifying a range with more erase blocks than
are needed to hold CONFIG_ENV_SIZE allows bad blocks within
the range to be avoided.
- CONFIG_ENV_OFFSET_OOB (optional):
Enables support for dynamically retrieving the offset of the
environment from block zero's out-of-band data. The
"nand env.oob" command can be used to record this offset.
Currently, CONFIG_ENV_OFFSET_REDUND is not supported when
using CONFIG_ENV_OFFSET_OOB.
- CONFIG_NAND_ENV_DST
Defines address in RAM to which the nand_spl code should copy the
environment. If redundant environment is used, it will be copied to
CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE.
- CONFIG_ENV_IS_IN_UBI:
Define this if you have an UBI volume that you want to use for the
environment. This has the benefit of wear-leveling the environment
accesses, which is important on NAND.
- CONFIG_ENV_UBI_PART:
Define this to a string that is the mtd partition containing the UBI.
- CONFIG_ENV_UBI_VOLUME:
Define this to the name of the volume that you want to store the
environment in.
- CONFIG_ENV_UBI_VOLUME_REDUND:
Define this to the name of another volume to store a second copy of
the environment in. This will enable redundant environments in UBI.
It is assumed that both volumes are in the same MTD partition.
- CONFIG_UBI_SILENCE_MSG
- CONFIG_UBIFS_SILENCE_MSG
You will probably want to define these to avoid a really noisy system
when storing the env in UBI.
- CONFIG_ENV_IS_IN_FAT:
Define this if you want to use the FAT file system for the environment.
- FAT_ENV_INTERFACE:
Define this to a string that is the name of the block device.
- FAT_ENV_DEVICE_AND_PART:
Define this to a string to specify the partition of the device. It can
be as following:
"D:P", "D:0", "D", "D:" or "D:auto" (D, P are integers. And P >= 1)
- "D:P": device D partition P. Error occurs if device D has no
partition table.
- "D:0": device D.
- "D" or "D:": device D partition 1 if device D has partition
table, or the whole device D if has no partition
table.
- "D:auto": first partition in device D with bootable flag set.
If none, first valid partition in device D. If no
partition table then means device D.
- FAT_ENV_FILE:
It's a string of the FAT file name. This file use to store the
environment.
- CONFIG_FAT_WRITE:
This must be enabled. Otherwise it cannot save the environment file.
- CONFIG_ENV_IS_IN_MMC:
Define this if you have an MMC device which you want to use for the
environment.
- CONFIG_SYS_MMC_ENV_DEV:
Specifies which MMC device the environment is stored in.
- CONFIG_SYS_MMC_ENV_PART (optional):
Specifies which MMC partition the environment is stored in. If not
set, defaults to partition 0, the user area. Common values might be
1 (first MMC boot partition), 2 (second MMC boot partition).
- CONFIG_ENV_OFFSET:
- CONFIG_ENV_SIZE:
These two #defines specify the offset and size of the environment
area within the specified MMC device.
If offset is positive (the usual case), it is treated as relative to
the start of the MMC partition. If offset is negative, it is treated
as relative to the end of the MMC partition. This can be useful if
your board may be fitted with different MMC devices, which have
different sizes for the MMC partitions, and you always want the
environment placed at the very end of the partition, to leave the
maximum possible space before it, to store other data.
These two values are in units of bytes, but must be aligned to an
MMC sector boundary.
- CONFIG_ENV_OFFSET_REDUND (optional):
Specifies a second storage area, of CONFIG_ENV_SIZE size, used to
hold a redundant copy of the environment data. This provides a
valid backup copy in case the other copy is corrupted, e.g. due
to a power failure during a "saveenv" operation.
This value may also be positive or negative; this is handled in the
same way as CONFIG_ENV_OFFSET.
This value is also in units of bytes, but must also be aligned to
an MMC sector boundary.
- CONFIG_ENV_SIZE_REDUND (optional):
This value need not be set, even when CONFIG_ENV_OFFSET_REDUND is
set. If this value is set, it must be set to the same value as
CONFIG_ENV_SIZE.
Please note that the environment is read-only until the monitor
has been relocated to RAM and a RAM copy of the environment has been
created; also, when using EEPROM you will have to use getenv_f()

View File

@@ -63,7 +63,7 @@ void dev_stor_init(void)
specs[ENUM_MMC].type = DEV_TYP_STOR | DT_STOR_MMC;
specs[ENUM_MMC].name = "mmc";
#endif
#if defined(CONFIG_CMD_SATA)
#if defined(CONFIG_SATA)
specs[ENUM_SATA].max_dev = CONFIG_SYS_SATA_MAX_DEVICE;
specs[ENUM_SATA].enum_started = 0;
specs[ENUM_SATA].enum_ended = 0;

View File

@@ -66,6 +66,7 @@ config SANDBOX
select DM_SPI
select DM_GPIO
select DM_MMC
select LZO
imply CMD_GETTIME
imply CMD_HASH
imply CMD_IO
@@ -75,6 +76,8 @@ config SANDBOX
imply FAT_WRITE
imply HASH_VERIFY
imply LZMA
imply SCSI
imply CMD_SATA
config SH
bool "SuperH architecture"
@@ -91,6 +94,7 @@ config X86
select DM_GPIO
select DM_SPI
select DM_SPI_FLASH
select USB
select USB_EHCI_HCD
imply CMD_FPGA_LOADMK
imply CMD_GETTIME

View File

@@ -488,6 +488,7 @@ config ARCH_BCM283X
select DM_GPIO
select OF_CONTROL
imply FAT_WRITE
imply ENV_IS_IN_FAT
config TARGET_VEXPRESS_CA15_TC2
bool "Support vexpress_ca15_tc2"
@@ -569,6 +570,7 @@ config ARCH_KEYSTONE
select SUPPORT_SPL
select SYS_THUMB_BUILD
select CMD_POWEROFF
imply CMD_MTDPARTS
imply FIT
config ARCH_OMAP2PLUS
@@ -649,6 +651,7 @@ config ARCH_SOCFPGA
select ARCH_MISC_INIT
select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
select SYS_THUMB_BUILD
imply CMD_MTDPARTS
imply CRC32_VERIFY
imply FAT_WRITE
@@ -693,6 +696,7 @@ config ARCH_VF610
bool "Freescale Vybrid"
select CPU_V7
select SYS_FSL_ERRATUM_ESDHC111
imply CMD_MTDPARTS
config ARCH_ZYNQ
bool "Xilinx Zynq Platform"
@@ -792,6 +796,7 @@ config TARGET_LS2080AQDS
select BOARD_LATE_INIT
select SUPPORT_SPL
select ARCH_MISC_INIT
imply SCSI
help
Support for Freescale LS2080AQDS platform
The LS2080A Development System (QDS) is a high-performance
@@ -806,6 +811,7 @@ config TARGET_LS2080ARDB
select BOARD_LATE_INIT
select SUPPORT_SPL
select ARCH_MISC_INIT
imply SCSI
help
Support for Freescale LS2080ARDB platform.
The LS2080A Reference design board (RDB) is a high-performance
@@ -837,6 +843,19 @@ config TARGET_HIKEY
Support for HiKey 96boards platform. It features a HI6220
SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
config TARGET_POPLAR
bool "Support Poplar 96boards Enterprise Edition Platform"
select ARM64
select DM
select OF_CONTROL
select DM_SERIAL
select DM_USB
help
Support for Poplar 96boards EE platform. It features a HI3798cv200
SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
making it capable of running any commercial set-top solution based on
Linux or Android.
config TARGET_LS1012AQDS
bool "Support ls1012aqds"
select ARCH_LS1012A
@@ -853,6 +872,7 @@ config TARGET_LS1012ARDB
select ARCH_LS1012A
select ARM64
select BOARD_LATE_INIT
imply SCSI
help
Support for Freescale LS1012ARDB platform.
The LS1012A Reference design board (RDB) is a high-performance
@@ -881,6 +901,7 @@ config TARGET_LS1021AQDS
select LS1_DEEP_SLEEP
select SYS_FSL_DDR
select BOARD_EARLY_INIT_F
imply SCSI
config TARGET_LS1021ATWR
bool "Support ls1021atwr"
@@ -893,6 +914,7 @@ config TARGET_LS1021ATWR
select ARCH_SUPPORT_PSCI
select LS1_DEEP_SLEEP
select BOARD_EARLY_INIT_F
imply SCSI
config TARGET_LS1021AIOT
bool "Support ls1021aiot"
@@ -903,6 +925,7 @@ config TARGET_LS1021AIOT
select SUPPORT_SPL
select ARCH_LS1021A
select ARCH_SUPPORT_PSCI
imply SCSI
help
Support for Freescale LS1021AIOT platform.
The LS1021A Freescale board (IOT) is a high-performance
@@ -917,6 +940,7 @@ config TARGET_LS1043AQDS
select BOARD_LATE_INIT
select SUPPORT_SPL
select BOARD_EARLY_INIT_F
imply SCSI
help
Support for Freescale LS1043AQDS platform.
@@ -928,6 +952,7 @@ config TARGET_LS1043ARDB
select BOARD_LATE_INIT
select SUPPORT_SPL
select BOARD_EARLY_INIT_F
imply SCSI
help
Support for Freescale LS1043ARDB platform.
@@ -940,6 +965,7 @@ config TARGET_LS1046AQDS
select SUPPORT_SPL
select DM_SPI_FLASH if DM_SPI
select BOARD_EARLY_INIT_F
imply SCSI
help
Support for Freescale LS1046AQDS platform.
The LS1046A Development System (QDS) is a high-performance
@@ -956,6 +982,7 @@ config TARGET_LS1046ARDB
select DM_SPI_FLASH if DM_SPI
select POWER_MC34VR500
select BOARD_EARLY_INIT_F
imply SCSI
help
Support for Freescale LS1046ARDB platform.
The LS1046A Reference Design Board (RDB) is a high-performance
@@ -996,6 +1023,7 @@ config ARCH_UNIPHIER
select SPL_PINCTRL if SPL
select SUPPORT_SPL
imply FAT_WRITE
imply ENV_IS_IN_MMC
help
Support for UniPhier SoC family developed by Socionext Inc.
(formerly, System LSI Business Division of Panasonic Corporation)
@@ -1075,13 +1103,13 @@ source "arch/arm/mach-mvebu/Kconfig"
source "arch/arm/cpu/armv7/ls102xa/Kconfig"
source "arch/arm/cpu/armv7/mx7ulp/Kconfig"
source "arch/arm/mach-imx/mx7ulp/Kconfig"
source "arch/arm/cpu/armv7/mx7/Kconfig"
source "arch/arm/mach-imx/mx7/Kconfig"
source "arch/arm/cpu/armv7/mx6/Kconfig"
source "arch/arm/mach-imx/mx6/Kconfig"
source "arch/arm/cpu/armv7/mx5/Kconfig"
source "arch/arm/mach-imx/mx5/Kconfig"
source "arch/arm/mach-omap2/Kconfig"
@@ -1121,7 +1149,7 @@ source "arch/arm/cpu/armv8/zynqmp/Kconfig"
source "arch/arm/cpu/armv8/Kconfig"
source "arch/arm/imx-common/Kconfig"
source "arch/arm/mach-imx/Kconfig"
source "board/aries/m28evk/Kconfig"
source "board/bosch/shc/Kconfig"
@@ -1165,6 +1193,7 @@ source "board/grinn/chiliboard/Kconfig"
source "board/gumstix/pepper/Kconfig"
source "board/h2200/Kconfig"
source "board/hisilicon/hikey/Kconfig"
source "board/hisilicon/poplar/Kconfig"
source "board/imx31_phycore/Kconfig"
source "board/isee/igep003x/Kconfig"
source "board/olimex/mx23_olinuxino/Kconfig"

View File

@@ -96,11 +96,11 @@ libs-y += arch/arm/lib/
ifeq ($(CONFIG_SPL_BUILD),y)
ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35))
libs-y += arch/arm/imx-common/
libs-y += arch/arm/mach-imx/
endif
else
ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs vf610))
libs-y += arch/arm/imx-common/
libs-y += arch/arm/mach-imx/
endif
endif

View File

@@ -12,7 +12,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/imx-common/sys_proto.h>
#include <asm/mach-imx/sys_proto.h>
#ifdef CONFIG_MMC_MXC
#include <asm/arch/mxcmmc.h>
#endif

View File

@@ -14,7 +14,7 @@
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/imx-common/dma.h>
#include <asm/mach-imx/dma.h>
#include <asm/arch/gpio.h>
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>

View File

@@ -33,10 +33,6 @@ obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/
obj-$(if $(filter mx5,$(SOC)),y) += mx5/
obj-$(CONFIG_MX6) += mx6/
obj-$(CONFIG_MX7) += mx7/
obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
obj-$(CONFIG_RMOBILE) += rmobile/
obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/

View File

@@ -14,6 +14,7 @@ config ARCH_LS1021A
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_LE
imply SCSI
menu "LS102xA architecture"
depends on ARCH_LS1021A

View File

@@ -36,7 +36,7 @@ int ls1021a_sata_init(void)
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
ahci_init((void __iomem *)AHCI_BASE_ADDR);
scsi_scan(0);
scsi_scan(false);
return 0;
}

View File

@@ -9,7 +9,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/imx-common/sys_proto.h>
#include <asm/mach-imx/sys_proto.h>
#include <netdev.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>

View File

@@ -26,6 +26,7 @@ config ARCH_LS1043A
select SYS_FSL_HAS_DDR4
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
imply SCSI
config ARCH_LS1046A
bool
@@ -46,6 +47,7 @@ config ARCH_LS1046A
select SYS_FSL_SRDS_2
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
imply SCSI
config ARCH_LS2080A
bool

View File

@@ -173,8 +173,9 @@ int ppa_init(void)
debug("%s: PPA image load from NAND\n", __func__);
nand_init();
ret = nand_read(nand_info[0], (loff_t)CONFIG_SYS_LS_PPA_FW_ADDR,
&fdt_header_len, (u_char *)&fit);
ret = nand_read(get_nand_dev_by_index(0),
(loff_t)CONFIG_SYS_LS_PPA_FW_ADDR,
&fdt_header_len, (u_char *)&fit);
if (ret == -EUCLEAN) {
printf("NAND read of PPA FIT header at offset 0x%x failed\n",
CONFIG_SYS_LS_PPA_FW_ADDR);
@@ -196,8 +197,9 @@ int ppa_init(void)
fw_length = CONFIG_LS_PPA_ESBC_HDR_SIZE;
ret = nand_read(nand_info[0], (loff_t)CONFIG_SYS_LS_PPA_ESBC_ADDR,
&fw_length, (u_char *)ppa_hdr_ddr);
ret = nand_read(get_nand_dev_by_index(0),
(loff_t)CONFIG_SYS_LS_PPA_ESBC_ADDR,
&fw_length, (u_char *)ppa_hdr_ddr);
if (ret == -EUCLEAN) {
free(ppa_hdr_ddr);
printf("NAND read of PPA firmware at offset 0x%x failed\n",
@@ -221,8 +223,9 @@ int ppa_init(void)
return -ENOMEM;
}
ret = nand_read(nand_info[0], (loff_t)CONFIG_SYS_LS_PPA_FW_ADDR,
&fw_length, (u_char *)ppa_fit_addr);
ret = nand_read(get_nand_dev_by_index(0),
(loff_t)CONFIG_SYS_LS_PPA_FW_ADDR,
&fw_length, (u_char *)ppa_fit_addr);
if (ret == -EUCLEAN) {
free(ppa_fit_addr);
printf("NAND read of PPA firmware at offset 0x%x failed\n",

View File

@@ -225,7 +225,7 @@ int sata_init(void)
out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
ahci_init((void __iomem *)CONFIG_SYS_SATA1);
scsi_scan(0);
scsi_scan(false);
return 0;
}
@@ -244,7 +244,7 @@ int sata_init(void)
out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
ahci_init((void __iomem *)CONFIG_SYS_SATA);
scsi_scan(0);
scsi_scan(false);
return 0;
}

View File

@@ -34,6 +34,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-fennec.dtb \
rk3288-firefly.dtb \
rk3288-miqi.dtb \
rk3288-phycore-rdk.dtb \
rk3288-popmetal.dtb \
rk3288-rock2-square.dtb \
rk3288-tinker.dtb \
@@ -372,7 +373,9 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
keystone-k2l-evm.dtb \
keystone-k2e-evm.dtb \
keystone-k2g-evm.dtb
keystone-k2g-evm.dtb \
keystone-k2g-generic.dtb \
keystone-k2g-ice.dtb
dtb-$(CONFIG_TARGET_AT91SAM9263EK) += at91sam9263ek.dtb

View File

@@ -0,0 +1,55 @@
/*
* Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/ {
aliases {
i2c0 = &i2c0;
i2c1 = &i2cmux;
spi0 = &spi0;
};
};
&i2c0 {
u-boot,dm-pre-reloc;
i2cmux: i2cmux@70 {
u-boot,dm-pre-reloc;
i2c@0 {
u-boot,dm-pre-reloc;
};
i2c@1 {
u-boot,dm-pre-reloc;
};
i2c@5 {
u-boot,dm-pre-reloc;
/* ATSHA204A at address 0x64 */
atsha204a@64 {
u-boot,dm-pre-reloc;
compatible = "atmel,atsha204a";
reg = <0x64>;
};
};
};
};
&spi0 {
u-boot,dm-pre-reloc;
spi-flash@0 {
compatible = "spi-flash";
reg = <0>;
spi-max-frequency = <40000000>;
u-boot,dm-pre-reloc;
};
};
&uart0 {
u-boot,dm-pre-reloc;
};

View File

@@ -0,0 +1,392 @@
/*
* Device Tree file for the Turris Omnia
*
* Copyright (C) 2016 Uwe Kleine-König <uwe@kleine-koenig.org>
* Copyright (C) 2016 Tomas Hlavacek <tmshlvkc@gmail.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "armada-385.dtsi"
/ {
model = "Turris Omnia";
compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380";
chosen {
stdout-path = &uart0;
};
memory {
device_type = "memory";
reg = <0x00000000 0x40000000>; /* 1024 MB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
internal-regs {
/* USB part of the PCIe2/USB 2.0 port */
usb@58000 {
status = "okay";
};
sata@a8000 {
status = "okay";
};
sdhci@d8000 {
pinctrl-names = "default";
pinctrl-0 = <&sdhci_pins>;
status = "okay";
bus-width = <8>;
no-1-8-v;
non-removable;
};
usb3@f0000 {
status = "okay";
};
usb3@f8000 {
status = "okay";
};
};
pcie-controller {
status = "okay";
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
pcie@3,0 {
/* Port 2, Lane 0 */
status = "okay";
};
};
};
};
/* Connected to 88E6176 switch, port 6 */
&eth0 {
pinctrl-names = "default";
pinctrl-0 = <&ge0_rgmii_pins>;
status = "okay";
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
/* Connected to 88E6176 switch, port 5 */
&eth1 {
pinctrl-names = "default";
pinctrl-0 = <&ge1_rgmii_pins>;
status = "okay";
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
/* WAN port */
&eth2 {
status = "okay";
phy-mode = "sgmii";
phy = <&phy1>;
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
i2cmux@70 {
compatible = "nxp,pca9547";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
status = "okay";
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
/* STM32F0 command interface at address 0x2a */
/* leds device (in STM32F0) at address 0x2b */
eeprom@54 {
compatible = "at,24c64";
reg = <0x54>;
/* The EEPROM contains data for bootloader.
* Contents:
* struct omnia_eeprom {
* u32 magic; (=0x0341a034 in LE)
* u32 ramsize; (in GiB)
* char regdomain[4];
* u32 crc32;
* };
*/
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
/* routed to PCIe0/mSATA connector (CN7A) */
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
/* routed to PCIe1/USB2 connector (CN61A) */
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
/* routed to PCIe2 connector (CN62A) */
};
i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
/* routed to SFP+ */
};
i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
/* ATSHA204A at address 0x64 */
};
i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
/* exposed on pin header */
};
i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
pcawan: gpio@71 {
/*
* GPIO expander for SFP+ signals and
* and phy irq
*/
compatible = "nxp,pca9538";
reg = <0x71>;
pinctrl-names = "default";
pinctrl-0 = <&pcawan_pins>;
interrupt-parent = <&gpio1>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
gpio-controller;
#gpio-cells = <2>;
};
};
};
};
&mdio {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
status = "okay";
phy1: phy@1 {
status = "okay";
compatible = "ethernet-phy-id0141.0DD1", "ethernet-phy-ieee802.3-c22";
reg = <1>;
/* irq is connected to &pcawan pin 7 */
};
/* Switch MV88E6176 at address 0x10 */
switch@10 {
compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
dsa,member = <0 0>;
reg = <0x10>;
ports {
#address-cells = <1>;
#size-cells = <0>;
ports@0 {
reg = <0>;
label = "lan0";
};
ports@1 {
reg = <1>;
label = "lan1";
};
ports@2 {
reg = <2>;
label = "lan2";
};
ports@3 {
reg = <3>;
label = "lan3";
};
ports@4 {
reg = <4>;
label = "lan4";
};
ports@5 {
reg = <5>;
label = "cpu";
ethernet = <&eth1>;
phy-mode = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
/* port 6 is connected to eth0 */
};
};
};
&pinctrl {
pcawan_pins: pcawan-pins {
marvell,pins = "mpp46";
marvell,function = "gpio";
};
spi0cs0_pins: spi0cs0-pins {
marvell,pins = "mpp25";
marvell,function = "spi0";
};
spi0cs1_pins: spi0cs1-pins {
marvell,pins = "mpp26";
marvell,function = "spi0";
};
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
status = "okay";
spi-nor@0 {
compatible = "spansion,s25fl164k", "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <40000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x0 0x00100000>;
label = "U-Boot";
};
partition@100000 {
reg = <0x00100000 0x00700000>;
label = "Rescue system";
};
};
};
/* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */
};
&uart0 {
/* Pin header CN10 */
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&uart1 {
/* Pin header CN11 */
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};

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@@ -0,0 +1,162 @@
/*
* DTS File for HiSilicon Poplar Development Board
*
* Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
*
* Released under the GPLv2 only.
* SPDX-License-Identifier: GPL-2.0
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "hi3798cv200.dtsi"
/ {
model = "HiSilicon Poplar Development Board";
compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200";
aliases {
serial0 = &uart0;
serial2 = &uart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
leds {
compatible = "gpio-leds";
user-led0 {
label = "USER-LED0";
gpios = <&gpio6 3 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
user-led1 {
label = "USER-LED1";
gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
linux,default-trigger = "mmc0";
default-state = "off";
};
user-led2 {
label = "USER-LED2";
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
linux,default-trigger = "none";
default-state = "off";
};
user-led3 {
label = "USER-LED3";
gpios = <&gpio10 6 GPIO_ACTIVE_LOW>;
linux,default-trigger = "cpu0";
default-state = "off";
};
};
};
&gmac1 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
phy-handle = <&eth_phy1>;
phy-mode = "rgmii";
hisilicon,phy-reset-delays-us = <10000 10000 30000>;
eth_phy1: phy@3 {
reg = <3>;
};
};
&gpio1 {
status = "okay";
gpio-line-names = "LS-GPIO-E", "",
"", "",
"", "LS-GPIO-F",
"", "LS-GPIO-J";
};
&gpio2 {
status = "okay";
gpio-line-names = "LS-GPIO-H", "LS-GPIO-I",
"LS-GPIO-L", "LS-GPIO-G",
"LS-GPIO-K", "",
"", "";
};
&gpio3 {
status = "okay";
gpio-line-names = "", "",
"", "",
"LS-GPIO-C", "",
"", "LS-GPIO-B";
};
&gpio4 {
status = "okay";
gpio-line-names = "", "",
"", "",
"", "LS-GPIO-D",
"", "";
};
&gpio5 {
status = "okay";
gpio-line-names = "", "USER-LED-1",
"USER-LED-2", "",
"", "LS-GPIO-A",
"", "";
};
&gpio6 {
status = "okay";
gpio-line-names = "", "",
"", "USER-LED-0",
"", "",
"", "";
};
&gpio10 {
status = "okay";
gpio-line-names = "", "",
"", "",
"", "",
"USER-LED-3", "";
};
&i2c0 {
status = "okay";
label = "LS-I2C0";
};
&i2c2 {
status = "okay";
label = "LS-I2C1";
};
&ir {
status = "okay";
};
&spi0 {
status = "okay";
label = "LS-SPI0";
};
&uart0 {
status = "okay";
};
&uart2 {
status = "okay";
label = "LS-UART0";
};
/* No optional LS-UART1 on Low Speed Expansion Connector. */

View File

@@ -0,0 +1,29 @@
/*
* U-Boot addition to:
* 1) use platform data for the console
* 2) provide support for the generic-ehci USB driver currently not available
* in the linux kernel (8/May/2017).
*
* (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
&soc {
usb2: ehci@9890000 {
compatible = "generic-ehci";
reg = <0x9890000 0x100>;
status = "okay";
};
};
&uart0 {
status = "disabled";
};
/{
chosen {
stdout-path = "";
};
};

View File

@@ -0,0 +1,411 @@
/*
* DTS File for HiSilicon Hi3798cv200 SoC.
*
* Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
*
* Released under the GPLv2 only.
* SPDX-License-Identifier: GPL-2.0
*/
#include <dt-bindings/clock/histb-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/ti-syscon.h>
/ {
compatible = "hisilicon,hi3798cv200";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x0>;
enable-method = "psci";
};
cpu@1 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x1>;
enable-method = "psci";
};
cpu@2 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x2>;
enable-method = "psci";
};
cpu@3 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x3>;
enable-method = "psci";
};
};
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */
<0x0 0xf1002000 0x0 0x100>; /* GICC */
#address-cells = <0>;
#interrupt-cells = <3>;
interrupt-controller;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>;
};
soc: soc@f0000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xf0000000 0x10000000>;
crg: clock-reset-controller@8a22000 {
compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";
reg = <0x8a22000 0x1000>;
#clock-cells = <1>;
#reset-cells = <2>;
gmacphyrst: reset-controller {
compatible = "ti,syscon-reset";
#reset-cells = <1>;
ti,reset-bits =
<0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR |
DEASSERT_SET|STATUS_NONE)>,
<0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR |
DEASSERT_SET|STATUS_NONE)>;
};
};
sysctrl: system-controller@8000000 {
compatible = "hisilicon,hi3798cv200-sysctrl", "syscon";
reg = <0x8000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <2>;
};
uart0: serial@8b00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x8b00000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysctrl HISTB_UART0_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
uart2: serial@8b02000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x8b02000 0x1000>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_UART2_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
i2c0: i2c@8b10000 {
compatible = "hisilicon,hix5hd2-i2c";
reg = <0x8b10000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
clocks = <&crg HISTB_I2C0_CLK>;
status = "disabled";
};
i2c1: i2c@8b11000 {
compatible = "hisilicon,hix5hd2-i2c";
reg = <0x8b11000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
clocks = <&crg HISTB_I2C1_CLK>;
status = "disabled";
};
i2c2: i2c@8b12000 {
compatible = "hisilicon,hix5hd2-i2c";
reg = <0x8b12000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
clocks = <&crg HISTB_I2C2_CLK>;
status = "disabled";
};
i2c3: i2c@8b13000 {
compatible = "hisilicon,hix5hd2-i2c";
reg = <0x8b13000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
clocks = <&crg HISTB_I2C3_CLK>;
status = "disabled";
};
i2c4: i2c@8b14000 {
compatible = "hisilicon,hix5hd2-i2c";
reg = <0x8b14000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
clocks = <&crg HISTB_I2C4_CLK>;
status = "disabled";
};
spi0: spi@8b1a000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x8b1a000 0x1000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
num-cs = <1>;
cs-gpios = <&gpio7 1 0>;
clocks = <&crg HISTB_SPI0_CLK>;
clock-names = "apb_pclk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
emmc: mmc@9830000 {
compatible = "snps,dw-mshc";
reg = <0x9830000 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_MMC_CIU_CLK>,
<&crg HISTB_MMC_BIU_CLK>;
clock-names = "ciu", "biu";
};
gpio0: gpio@8b20000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b20000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio1: gpio@8b21000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b21000 0x1000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio2: gpio@8b22000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b22000 0x1000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio3: gpio@8b23000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b23000 0x1000>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio4: gpio@8b24000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b24000 0x1000>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio5: gpio@8004000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8004000 0x1000>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio6: gpio@8b26000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b26000 0x1000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio7: gpio@8b27000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b27000 0x1000>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio8: gpio@8b28000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b28000 0x1000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio9: gpio@8b29000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b29000 0x1000>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio10: gpio@8b2a000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b2a000 0x1000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio11: gpio@8b2b000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b2b000 0x1000>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio12: gpio@8b2c000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b2c000 0x1000>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gmac0: ethernet@9840000 {
compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
reg = <0x9840000 0x1000>,
<0x984300c 0x4>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_ETH0_MAC_CLK>,
<&crg HISTB_ETH0_MACIF_CLK>;
clock-names = "mac_core", "mac_ifc";
resets = <&crg 0xcc 8>,
<&crg 0xcc 10>,
<&gmacphyrst 0>;
reset-names = "mac_core", "mac_ifc", "phy";
status = "disabled";
};
gmac1: ethernet@9841000 {
compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
reg = <0x9841000 0x1000>,
<0x9843010 0x4>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_ETH1_MAC_CLK>,
<&crg HISTB_ETH1_MACIF_CLK>;
clock-names = "mac_core", "mac_ifc";
resets = <&crg 0xcc 9>,
<&crg 0xcc 11>,
<&gmacphyrst 1>;
reset-names = "mac_core", "mac_ifc", "phy";
status = "disabled";
};
ir: ir@8001000 {
compatible = "hisilicon,hix5hd2-ir";
reg = <0x8001000 0x1000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysctrl HISTB_IR_CLK>;
status = "disabled";
};
};
};

View File

@@ -0,0 +1,15 @@
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
/{
soc {
u-boot,dm-pre-reloc;
};
};
&i2c1 {
u-boot,dm-pre-reloc;
};

View File

@@ -0,0 +1,19 @@
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
/{
soc {
u-boot,dm-pre-reloc;
};
};
&i2c0 {
u-boot,dm-pre-reloc;
};
&i2c1 {
u-boot,dm-pre-reloc;
};

View File

@@ -18,6 +18,11 @@
chosen {
stdout-path = &uart0;
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
};
&mdio {
@@ -32,6 +37,10 @@
phy-handle = <&ethphy0>;
};
&netcp {
status = "okay";
};
&spi1 {
status = "okay";

View File

@@ -0,0 +1,19 @@
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
/{
soc {
u-boot,dm-pre-reloc;
};
};
&i2c0 {
u-boot,dm-pre-reloc;
};
&i2c1 {
u-boot,dm-pre-reloc;
};

View File

@@ -0,0 +1,28 @@
/*
* Device Tree Source for Generic 66AK2G0X EVM
*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "keystone-k2g.dtsi"
/ {
compatible = "ti,k2g-generic", "ti,k2g", "ti,keystone";
model = "Texas Instruments 66AK2G02 Generic";
chosen {
stdout-path = &uart0;
};
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
};

View File

@@ -0,0 +1,19 @@
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
/{
soc {
u-boot,dm-pre-reloc;
};
};
&i2c0 {
u-boot,dm-pre-reloc;
};
&i2c1 {
u-boot,dm-pre-reloc;
};

View File

@@ -0,0 +1,36 @@
/*
* Device Tree Source for K2G Industrial Communication Engine EVM
*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "keystone-k2g.dtsi"
/ {
compatible = "ti,k2g-ice", "ti,k2g", "ti,keystone";
model = "Texas Instruments K2G Industrial Communication EVM";
chosen {
stdout-path = &uart0;
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>;
};
};
&mmc1 {
status = "okay";
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
};

View File

@@ -99,6 +99,7 @@ netcp: netcp@4000000 {
reg = <0x2620110 0x8>;
reg-names = "efuse";
compatible = "ti,netcp-1.0";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
/* power-domains = <&k2g_pds K2G_DEV_NSS0>; */

View File

@@ -9,7 +9,6 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"
/ {
model = "Texas Instruments K2G SoC";
@@ -17,6 +16,8 @@
#size-cells = <1>;
interrupt-parent = <&gic>;
chosen { };
aliases {
serial0 = &uart0;
spi0 = &spi0;
@@ -29,11 +30,6 @@
i2c2 = &i2c2;
};
memory {
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;

View File

@@ -71,6 +71,14 @@
reg = <0x0 0x10000000 0x0 0x200000>;
no-map;
};
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0xbc00000>;
alignment = <0x0 0x400000>;
linux,cma-default;
};
};
cpus {
@@ -233,7 +241,7 @@
};
i2c_A: i2c@8500 {
compatible = "amlogic,meson-gxbb-i2c";
compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
reg = <0x0 0x08500 0x0 0x20>;
interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
@@ -255,6 +263,14 @@
status = "disabled";
};
saradc: adc@8680 {
compatible = "amlogic,meson-saradc";
reg = <0x0 0x8680 0x0 0x34>;
#io-channel-cells = <1>;
interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
pwm_ef: pwm@86c0 {
compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
reg = <0x0 0x086c0 0x0 0x10>;
@@ -271,7 +287,7 @@
};
i2c_B: i2c@87c0 {
compatible = "amlogic,meson-gxbb-i2c";
compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
reg = <0x0 0x087c0 0x0 0x20>;
interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
@@ -280,7 +296,7 @@
};
i2c_C: i2c@87e0 {
compatible = "amlogic,meson-gxbb-i2c";
compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
reg = <0x0 0x087e0 0x0 0x20>;
interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
@@ -288,6 +304,14 @@
status = "disabled";
};
spifc: spi@8c80 {
compatible = "amlogic,meson-gx-spifc", "amlogic,meson-gxbb-spifc";
reg = <0x0 0x08c80 0x0 0x80>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
watchdog@98d0 {
compatible = "amlogic,meson-gx-wdt", "amlogic,meson-gxbb-wdt";
reg = <0x0 0x098d0 0x0 0x10>;
@@ -309,7 +333,7 @@
};
sram: sram@c8000000 {
compatible = "amlogic,meson-gxbb-sram", "mmio-sram";
compatible = "amlogic,meson-gx-sram", "amlogic,meson-gxbb-sram", "mmio-sram";
reg = <0x0 0xc8000000 0x0 0x14000>;
#address-cells = <1>;
@@ -317,12 +341,12 @@
ranges = <0 0x0 0xc8000000 0x14000>;
cpu_scp_lpri: scp-shmem@0 {
compatible = "amlogic,meson-gxbb-scp-shmem";
compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
reg = <0x13000 0x400>;
};
cpu_scp_hpri: scp-shmem@200 {
compatible = "amlogic,meson-gxbb-scp-shmem";
compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
reg = <0x13400 0x400>;
};
};
@@ -334,6 +358,13 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
clkc_AO: clock-controller@040 {
compatible = "amlogic,gx-aoclkc", "amlogic,gxbb-aoclkc";
reg = <0x0 0x00040 0x0 0x4>;
#clock-cells = <1>;
#reset-cells = <1>;
};
uart_AO: serial@4c0 {
compatible = "amlogic,meson-uart";
reg = <0x0 0x004c0 0x0 0x14>;
@@ -350,8 +381,24 @@
status = "disabled";
};
i2c_AO: i2c@500 {
compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
reg = <0x0 0x500 0x0 0x20>;
interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pwm_AO_ab: pwm@550 {
compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
reg = <0x0 0x00550 0x0 0x10>;
#pwm-cells = <3>;
status = "disabled";
};
ir: ir@580 {
compatible = "amlogic,meson-gxbb-ir";
compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir";
reg = <0x0 0x00580 0x0 0x40>;
interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
@@ -365,13 +412,12 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
rng {
hwrng: rng {
compatible = "amlogic,meson-rng";
reg = <0x0 0x0 0x0 0x4>;
};
};
hiubus: hiubus@c883c000 {
compatible = "simple-bus";
reg = <0x0 0xc883c000 0x0 0x2000>;
@@ -395,7 +441,6 @@
0x0 0xc8834540 0x0 0x4>;
interrupts = <0 8 1>;
interrupt-names = "macirq";
phy-mode = "rgmii";
status = "disabled";
};
@@ -442,6 +487,38 @@
cvbs_vdac_port: port@0 {
reg = <0>;
};
/* HDMI-TX output port */
hdmi_tx_port: port@1 {
reg = <1>;
hdmi_tx_out: endpoint {
remote-endpoint = <&hdmi_tx_in>;
};
};
};
hdmi_tx: hdmi-tx@c883a000 {
compatible = "amlogic,meson-gx-dw-hdmi";
reg = <0x0 0xc883a000 0x0 0x1c>;
interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
/* VPU VENC Input */
hdmi_tx_venc_port: port@0 {
reg = <0>;
hdmi_tx_in: endpoint {
remote-endpoint = <&hdmi_tx_out>;
};
};
/* TMDS Output */
hdmi_tx_tmds_port: port@1 {
reg = <1>;
};
};
};
};

View File

@@ -50,7 +50,7 @@
/ {
compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
model = "Hardkernel ODROID-C2";
aliases {
serial0 = &uart_AO;
};
@@ -96,7 +96,7 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio_ao GPIOAO_12 GPIO_ACTIVE_HIGH>;
gpio = <&gpio GPIOY_12 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
@@ -152,6 +152,13 @@
pinctrl-0 = <&eth_rgmii_pins>;
pinctrl-names = "default";
phy-handle = <&eth_phy0>;
phy-mode = "rgmii";
snps,reset-gpio = <&gpio GPIOZ_14 0>;
snps,reset-delays-us = <0 10000 1000000>;
snps,reset-active-low;
amlogic,tx-delay-ns = <2>;
mdio {
compatible = "snps,dwmac-mdio";
@@ -165,6 +172,57 @@
};
};
&pinctrl_aobus {
gpio-line-names = "UART TX", "UART RX", "VCCK En", "TF 3V3/1V8 En",
"USB HUB nRESET", "USB OTG Power En",
"J7 Header Pin2", "IR In", "J7 Header Pin4",
"J7 Header Pin6", "J7 Header Pin5", "J7 Header Pin7",
"HDMI CEC", "SYS LED";
};
&pinctrl_periphs {
gpio-line-names = /* Bank GPIOZ */
"Eth MDIO", "Eth MDC", "Eth RGMII RX Clk",
"Eth RX DV", "Eth RX D0", "Eth RX D1", "Eth RX D2",
"Eth RX D3", "Eth RGMII TX Clk", "Eth TX En",
"Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3",
"Eth PHY nRESET", "Eth PHY Intc",
/* Bank GPIOH */
"HDMI HPD", "HDMI DDC SDA", "HDMI DDC SCL", "",
/* Bank BOOT */
"eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", "eMMC D4",
"eMMC D5", "eMMC D6", "eMMC D7", "eMMC Clk",
"eMMC Reset", "eMMC CMD",
"", "", "", "", "", "", "",
/* Bank CARD */
"SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
"SDCard D3", "SDCard D2", "SDCard Det",
/* Bank GPIODV */
"", "", "", "", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "", "",
"I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK",
"PWM D", "PWM B",
/* Bank GPIOY */
"Revision Bit0", "Revision Bit1", "",
"J2 Header Pin35", "", "", "", "J2 Header Pin36",
"J2 Header Pin31", "", "", "", "TF VDD En",
"J2 Header Pin32", "J2 Header Pin26", "", "",
/* Bank GPIOX */
"J2 Header Pin29", "J2 Header Pin24",
"J2 Header Pin23", "J2 Header Pin22",
"J2 Header Pin21", "J2 Header Pin18",
"J2 Header Pin33", "J2 Header Pin19",
"J2 Header Pin16", "J2 Header Pin15",
"J2 Header Pin12", "J2 Header Pin13",
"J2 Header Pin8", "J2 Header Pin10",
"", "", "", "", "",
"J2 Header Pin11", "", "J2 Header Pin7",
/* Bank GPIOCLK */
"", "", "", "",
/* GPIO_TEST_N */
"";
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
@@ -177,6 +235,21 @@
pinctrl-names = "default";
};
&gpio_ao {
/*
* WARNING: The USB Hub on the Odroid-C2 needs a reset signal
* to be turned high in order to be detected by the USB Controller
* This signal should be handled by a USB specific power sequence
* in order to reset the Hub when USB bus is powered down.
*/
usb-hub {
gpio-hog;
gpios = <GPIOAO_4 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "usb-hub-reset";
};
};
&usb0_phy {
status = "okay";
phy-supply = <&usb_otg_pwr>;
@@ -194,6 +267,11 @@
status = "okay";
};
&saradc {
status = "okay";
vref-supply = <&vcc1v8>;
};
/* SD */
&sd_emmc_b {
status = "okay";

View File

@@ -97,17 +97,6 @@
};
};
&cbus {
spifc: spi@8c80 {
compatible = "amlogic,meson-gxbb-spifc";
reg = <0x0 0x08c80 0x0 0x80>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_SPI>;
status = "disabled";
};
};
&ethmac {
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
@@ -129,6 +118,7 @@
reg-names = "mux", "pull", "gpio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_aobus 0 0 14>;
};
uart_ao_a_pins: uart_ao_a {
@@ -203,30 +193,62 @@
function = "pwm_ao_b";
};
};
};
clkc_AO: clock-controller@040 {
compatible = "amlogic,gxbb-aoclkc";
reg = <0x0 0x00040 0x0 0x4>;
#clock-cells = <1>;
#reset-cells = <1>;
};
i2s_am_clk_pins: i2s_am_clk {
mux {
groups = "i2s_am_clk";
function = "i2s_out_ao";
};
};
pwm_ab_AO: pwm@550 {
compatible = "amlogic,meson-gxbb-pwm";
reg = <0x0 0x0550 0x0 0x10>;
#pwm-cells = <3>;
status = "disabled";
};
i2s_out_ao_clk_pins: i2s_out_ao_clk {
mux {
groups = "i2s_out_ao_clk";
function = "i2s_out_ao";
};
};
i2c_AO: i2c@500 {
compatible = "amlogic,meson-gxbb-i2c";
reg = <0x0 0x500 0x0 0x20>;
interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_AO_I2C>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
i2s_out_lr_clk_pins: i2s_out_lr_clk {
mux {
groups = "i2s_out_lr_clk";
function = "i2s_out_ao";
};
};
i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
mux {
groups = "i2s_out_ch01_ao";
function = "i2s_out_ao";
};
};
i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
mux {
groups = "i2s_out_ch23_ao";
function = "i2s_out_ao";
};
};
i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
mux {
groups = "i2s_out_ch45_ao";
function = "i2s_out_ao";
};
};
spdif_out_ao_6_pins: spdif_out_ao_6 {
mux {
groups = "spdif_out_ao_6";
function = "spdif_out_ao";
};
};
spdif_out_ao_13_pins: spdif_out_ao_13 {
mux {
groups = "spdif_out_ao_13";
function = "spdif_out_ao";
};
};
};
};
@@ -245,6 +267,7 @@
reg-names = "mux", "pull", "pull-enable", "gpio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_periphs 0 14 120>;
};
emmc_pins: emmc {
@@ -467,6 +490,34 @@
function = "hdmi_i2c";
};
};
i2sout_ch23_y_pins: i2sout_ch23_y {
mux {
groups = "i2sout_ch23_y";
function = "i2s_out";
};
};
i2sout_ch45_y_pins: i2sout_ch45_y {
mux {
groups = "i2sout_ch45_y";
function = "i2s_out";
};
};
i2sout_ch67_y_pins: i2sout_ch67_y {
mux {
groups = "i2sout_ch67_y";
function = "i2s_out";
};
};
spdif_out_y_pins: spdif_out_y {
mux {
groups = "spdif_out_y";
function = "spdif_out";
};
};
};
};
@@ -478,10 +529,51 @@
};
};
&apb {
mali: gpu@c0000 {
compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
reg = <0x0 0xc0000 0x0 0x40000>;
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gp", "gpmmu", "pp", "pmu",
"pp0", "ppmmu0", "pp1", "ppmmu1",
"pp2", "ppmmu2";
clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
clock-names = "bus", "core";
/*
* Mali clocking is provided by two identical clock paths
* MALI_0 and MALI_1 muxed to a single clock by a glitch
* free mux to safely change frequency while running.
*/
assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
<&clkc CLKID_MALI_0>,
<&clkc CLKID_MALI>; /* Glitch free mux */
assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
<0>, /* Do Nothing */
<&clkc CLKID_MALI_0>;
assigned-clock-rates = <0>, /* Do Nothing */
<666666666>,
<0>; /* Do Nothing */
};
};
&i2c_A {
clocks = <&clkc CLKID_I2C>;
};
&i2c_AO {
clocks = <&clkc CLKID_AO_I2C>;
};
&i2c_B {
clocks = <&clkc CLKID_I2C>;
};
@@ -490,6 +582,16 @@
clocks = <&clkc CLKID_I2C>;
};
&saradc {
compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
clocks = <&xtal>,
<&clkc CLKID_SAR_ADC>,
<&clkc CLKID_SANA>,
<&clkc CLKID_SAR_ADC_CLK>,
<&clkc CLKID_SAR_ADC_SEL>;
clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
};
&sd_emmc_a {
clocks = <&clkc CLKID_SD_EMMC_A>,
<&xtal>,
@@ -511,6 +613,27 @@
clock-names = "core", "clkin0", "clkin1";
};
&spifc {
clocks = <&clkc CLKID_SPI>;
};
&vpu {
compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
};
&hwrng {
clocks = <&clkc CLKID_RNG0>;
clock-names = "core";
};
&hdmi_tx {
compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
resets = <&reset RESET_HDMITX_CAPB3>,
<&reset RESET_HDMI_SYSTEM_RESET>,
<&reset RESET_HDMI_TX>;
reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
clocks = <&clkc CLKID_HDMI_PCLK>,
<&clkc CLKID_CLK81>,
<&clkc CLKID_GCLK_VENCI_INT0>;
clock-names = "isfr", "iahb", "venci";
};

View File

@@ -52,3 +52,11 @@
u-boot,dm-spl;
};
};
&gpio2 {
u-boot,dm-spl;
};
&gpio7 {
u-boot,dm-spl;
};

View File

@@ -0,0 +1,11 @@
&uart2 {
u-boot,dm-pre-reloc;
};
&grf {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};

View File

@@ -244,7 +244,7 @@
emmc: dwmmc@1021c000 {
compatible = "rockchip,rk3288-dw-mshc";
clock-frequency = <37500000>;
clock-freq-min-max = <400000 37500000>;
max-frequency = <37500000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";

View File

@@ -0,0 +1,81 @@
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
#include "rk322x.dtsi"
/ {
model = "Rockchip RK3229 Evaluation board";
compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
chosen {
stdout-path = &uart2;
};
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x40000000>;
};
ext_gmac: ext_gmac {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "ext_gmac";
#clock-cells = <0>;
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
enable-active-high;
regulator-name = "vcc_phy";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
};
&dmc {
rockchip,sdram-channel = /bits/ 8 <1 10 3 2 1 0 15 15>;
rockchip,pctl-timing = <0x96 0xC8 0x1F3 0xF 0x8000004D 0x4 0x4E 0x6 0x3
0x0 0x6 0x5 0xC 0x10 0x6 0x4 0x4
0x5 0x4 0x200 0x3 0xA 0x40 0x0 0x1
0x5 0x5 0x3 0xC 0x1E 0x100 0x0 0x4
0x0 0x924>;
rockchip,phy-timing = <0x220 0x1 0x0 0x0 0x0 0x4 0x60>;
rockchip,sdram-params = <0x428B188 0x0 0x21 0x472 0x15
0 300 3 0 120>;
};
&gmac {
assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>;
assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>;
clock_in_out = "input";
phy-supply = <&vcc_phy>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
tx_delay = <0x30>;
rx_delay = <0x10>;
status = "okay";
};
&emmc {
u-boot,dm-pre-reloc;
status = "okay";
};
&uart2 {
status = "okay";
};
&usb20_otg {
status = "okay";
};

720
arch/arm/dts/rk322x.dtsi Normal file
View File

@@ -0,0 +1,720 @@
/*
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3228-cru.h>
#include <dt-bindings/thermal/thermal.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@f00 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf00>;
resets = <&cru SRST_CORE0>;
operating-points = <
/* KHz uV */
816000 1000000
>;
#cooling-cells = <2>; /* min followed by max */
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
};
cpu1: cpu@f01 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf01>;
resets = <&cru SRST_CORE1>;
};
cpu2: cpu@f02 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf02>;
resets = <&cru SRST_CORE2>;
};
cpu3: cpu@f03 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf03>;
resets = <&cru SRST_CORE3>;
};
};
amba {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
pdma: pdma@110f0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x110f0000 0x4000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
clocks = <&cru ACLK_DMAC>;
clock-names = "apb_pclk";
};
};
arm-pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
timer {
compatible = "arm,armv7-timer";
arm,cpu-registers-not-fw-configured;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clock-frequency = <24000000>;
};
xin24m: oscillator {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xin24m";
#clock-cells = <0>;
};
bus_intmem@10080000 {
compatible = "mmio-sram";
reg = <0x10080000 0x9000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x10080000 0x9000>;
smp-sram@0 {
compatible = "rockchip,rk322x-smp-sram";
reg = <0x00 0x10>;
};
ddr_sram: ddr-sram@1000 {
compatible = "rockchip,rk322x-ddr-sram";
reg = <0x1000 0x8000>;
};
};
i2s1: i2s1@100b0000 {
compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
reg = <0x100b0000 0x4000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
dmas = <&pdma 14>, <&pdma 15>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&i2s1_bus>;
status = "disabled";
};
i2s0: i2s0@100c0000 {
compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
reg = <0x100c0000 0x4000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
dmas = <&pdma 11>, <&pdma 12>;
dma-names = "tx", "rx";
status = "disabled";
};
i2s2: i2s2@100e0000 {
compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
reg = <0x100e0000 0x4000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
dmas = <&pdma 0>, <&pdma 1>;
dma-names = "tx", "rx";
status = "disabled";
};
grf: syscon@11000000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3228-grf", "syscon";
reg = <0x11000000 0x1000>;
};
uart0: serial@11010000 {
compatible = "snps,dw-apb-uart";
reg = <0x11010000 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart1: serial@11020000 {
compatible = "snps,dw-apb-uart";
reg = <0x11020000 0x100>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart2: serial@11030000 {
compatible = "snps,dw-apb-uart";
reg = <0x11030000 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart2_xfer>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
i2c0: i2c@11050000 {
compatible = "rockchip,rk3228-i2c";
reg = <0x11050000 0x1000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_xfer>;
status = "disabled";
};
i2c1: i2c@11060000 {
compatible = "rockchip,rk3228-i2c";
reg = <0x11060000 0x1000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C1>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_xfer>;
status = "disabled";
};
i2c2: i2c@11070000 {
compatible = "rockchip,rk3228-i2c";
reg = <0x11070000 0x1000>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C2>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_xfer>;
status = "disabled";
};
i2c3: i2c@11080000 {
compatible = "rockchip,rk3228-i2c";
reg = <0x11080000 0x1000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C3>;
pinctrl-names = "default";
pinctrl-0 = <&i2c3_xfer>;
status = "disabled";
};
pwm0: pwm@110b0000 {
compatible = "rockchip,rk3288-pwm";
reg = <0x110b0000 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
status = "disabled";
};
pwm1: pwm@110b0010 {
compatible = "rockchip,rk3288-pwm";
reg = <0x110b0010 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm1_pin>;
status = "disabled";
};
pwm2: pwm@110b0020 {
compatible = "rockchip,rk3288-pwm";
reg = <0x110b0020 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm2_pin>;
status = "disabled";
};
pwm3: pwm@110b0030 {
compatible = "rockchip,rk3288-pwm";
reg = <0x110b0030 0x10>;
#pwm-cells = <2>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm3_pin>;
status = "disabled";
};
timer: timer@110c0000 {
compatible = "rockchip,rk3288-timer";
reg = <0x110c0000 0x20>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&xin24m>, <&cru PCLK_TIMER>;
clock-names = "timer", "pclk";
};
cru: clock-controller@110e0000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3228-cru";
reg = <0x110e0000 0x1000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks = <&cru PLL_GPLL>;
assigned-clock-rates = <594000000>;
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <100>; /* milliseconds */
polling-delay = <5000>; /* milliseconds */
thermal-sensors = <&tsadc 0>;
trips {
cpu_alert0: cpu_alert0 {
temperature = <70000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
cpu_alert1: cpu_alert1 {
temperature = <75000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
cpu_crit: cpu_crit {
temperature = <90000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert0>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT 6>;
};
map1 {
trip = <&cpu_alert1>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
tsadc: tsadc@11150000 {
compatible = "rockchip,rk3228-tsadc";
reg = <0x11150000 0x100>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
clock-names = "tsadc", "apb_pclk";
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
pinctrl-names = "init", "default", "sleep";
pinctrl-0 = <&otp_gpio>;
pinctrl-1 = <&otp_out>;
pinctrl-2 = <&otp_gpio>;
#thermal-sensor-cells = <0>;
rockchip,hw-tshut-temp = <95000>;
status = "disabled";
};
emmc: dwmmc@30020000 {
compatible = "rockchip,rk3288-dw-mshc";
reg = <0x30020000 0x4000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <37500000>;
max-frequency = <37500000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
bus-width = <8>;
default-sample-phase = <158>;
num-slots = <1>;
fifo-depth = <0x100>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
resets = <&cru SRST_EMMC>;
reset-names = "reset";
status = "disabled";
};
usb20_otg: usb@30040000 {
compatible = "rockchip,rk3229-usb", "rockchip,rk3288-usb",
"snps,dwc2";
reg = <0x30040000 0x40000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
hnp-srp-disable;
dr_mode = "otg";
status = "disabled";
};
gmac: ethernet@30200000 {
compatible = "rockchip,rk3228-gmac";
reg = <0x30200000 0x10000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
<&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
<&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
<&cru PCLK_GMAC>;
clock-names = "stmmaceth", "mac_clk_rx",
"mac_clk_tx", "clk_mac_ref",
"clk_mac_refout", "aclk_mac",
"pclk_mac";
resets = <&cru SRST_GMAC>;
reset-names = "stmmaceth";
rockchip,grf = <&grf>;
status = "disabled";
};
gic: interrupt-controller@32010000 {
compatible = "arm,gic-400";
interrupt-controller;
#interrupt-cells = <3>;
#address-cells = <0>;
reg = <0x32011000 0x1000>,
<0x32012000 0x2000>,
<0x32014000 0x2000>,
<0x32016000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
pinctrl: pinctrl {
compatible = "rockchip,rk3228-pinctrl";
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio0: gpio0@11110000 {
compatible = "rockchip,gpio-bank";
reg = <0x11110000 0x100>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO0>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio1@11120000 {
compatible = "rockchip,gpio-bank";
reg = <0x11120000 0x100>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio2@11130000 {
compatible = "rockchip,gpio-bank";
reg = <0x11130000 0x100>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio3@11140000 {
compatible = "rockchip,gpio-bank";
reg = <0x11140000 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pcfg_pull_up: pcfg-pull-up {
bias-pull-up;
};
pcfg_pull_down: pcfg-pull-down {
bias-pull-down;
};
pcfg_pull_none: pcfg-pull-none {
bias-disable;
};
pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
drive-strength = <12>;
};
emmc {
emmc_clk: emmc-clk {
rockchip,pins = <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>;
};
emmc_cmd: emmc-cmd {
rockchip,pins = <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none>;
};
emmc_bus8: emmc-bus8 {
rockchip,pins = <1 RK_PD0 RK_FUNC_2 &pcfg_pull_none>,
<1 RK_PD1 RK_FUNC_2 &pcfg_pull_none>,
<1 RK_PD2 RK_FUNC_2 &pcfg_pull_none>,
<1 RK_PD3 RK_FUNC_2 &pcfg_pull_none>,
<1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>,
<1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
<1 RK_PD6 RK_FUNC_2 &pcfg_pull_none>,
<1 RK_PD7 RK_FUNC_2 &pcfg_pull_none>;
};
};
gmac {
rgmii_pins: rgmii-pins {
rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<2 RK_PC6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<2 RK_PC7 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<2 RK_PB1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>,
<2 RK_PC4 RK_FUNC_2 &pcfg_pull_none>,
<2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>;
};
rmii_pins: rmii-pins {
rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>;
};
phy_pins: phy-pins {
rockchip,pins = <2 RK_PB6 RK_FUNC_2 &pcfg_pull_none>,
<2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>;
};
};
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 RK_PA0 RK_FUNC_1 &pcfg_pull_none>,
<0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>;
};
};
i2c1 {
i2c1_xfer: i2c1-xfer {
rockchip,pins = <0 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
<0 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
};
};
i2c2 {
i2c2_xfer: i2c2-xfer {
rockchip,pins = <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
};
};
i2c3 {
i2c3_xfer: i2c3-xfer {
rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
<0 RK_PA7 RK_FUNC_1 &pcfg_pull_none>;
};
};
i2s1 {
i2s1_bus: i2s1-bus {
rockchip,pins = <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
<0 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
<0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
<0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
<0 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
<0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
<1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
<1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,
<1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
};
};
pwm0 {
pwm0_pin: pwm0-pin {
rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
};
};
pwm1 {
pwm1_pin: pwm1-pin {
rockchip,pins = <0 RK_PD6 RK_FUNC_2 &pcfg_pull_none>;
};
};
pwm2 {
pwm2_pin: pwm2-pin {
rockchip,pins = <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none>;
};
};
pwm3 {
pwm3_pin: pwm3-pin {
rockchip,pins = <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none>;
};
};
tsadc {
otp_gpio: otp-gpio {
rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
otp_out: otp-out {
rockchip,pins = <0 RK_PD0 RK_FUNC_2 &pcfg_pull_none>;
};
};
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PD3 RK_FUNC_1 &pcfg_pull_none>;
};
uart0_cts: uart0-cts {
rockchip,pins = <2 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
};
uart0_rts: uart0-rts {
rockchip,pins = <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>;
};
};
uart1 {
uart1_xfer: uart1-xfer {
rockchip,pins = <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
<1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>;
};
uart1_cts: uart1-cts {
rockchip,pins = <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>;
};
uart1_rts: uart1-rts {
rockchip,pins = <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;
};
};
uart2 {
uart2_xfer: uart2-xfer {
rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
<1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>;
};
uart2_cts: uart2-cts {
rockchip,pins = <0 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
};
uart2_rts: uart2-rts {
rockchip,pins = <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
};
};
};
dmc: dmc@11200000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3228-dmc", "syscon";
rockchip,cru = <&cru>;
rockchip,grf = <&grf>;
rockchip,msch = <&service_msch>;
reg = <0x11200000 0x3fc
0x12000000 0x400>;
rockchip,sram = <&ddr_sram>;
};
service_msch: syscon@31090000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3228-msch", "syscon";
reg = <0x31090000 0x2000>;
};
};

View File

@@ -0,0 +1,294 @@
/*
* Device tree file for Phytec PCM-947 carrier board
* Copyright (C) 2017 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "rk3288-phycore-som.dtsi"
/ {
model = "Phytec RK3288 PCM-947";
compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288";
chosen {
stdout-path = &uart2;
};
config {
u-boot,dm-pre-reloc;
u-boot,boot0 = &emmc;
};
user_buttons: user-buttons {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&user_button_pins>;
button@0 {
label = "home";
linux,code = <KEY_HOME>;
gpios = <&gpio8 0 GPIO_ACTIVE_HIGH>;
wakeup-source;
};
button@1 {
label = "menu";
linux,code = <KEY_MENU>;
gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>;
wakeup-source;
};
};
vcc_host0_5v: usb-host0-regulator {
compatible = "regulator-fixed";
gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host0_vbus_drv>;
regulator-name = "vcc_host0_5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
vin-supply = <&vdd_in_otg_out>;
};
vcc_host1_5v: usb-host1-regulator {
compatible = "regulator-fixed";
gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host1_vbus_drv>;
regulator-name = "vcc_host1_5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
vin-supply = <&vdd_in_otg_out>;
};
vcc_otg_5v: usb-otg-regulator {
compatible = "regulator-fixed";
gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&otg_vbus_drv>;
regulator-name = "vcc_otg_5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
vin-supply = <&vdd_in_otg_out>;
};
};
&dmc {
rockchip,num-channels = <2>;
rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
0x5 0x0>;
rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
0xa60 0x40 0x10 0x0>;
rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xe 0xe>;
rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 5 1>;
};
&gmac {
status = "okay";
};
&hdmi {
status = "okay";
};
&i2c1 {
status = "okay";
touchscreen@44 {
compatible = "st,stmpe811";
reg = <0x44>;
};
adc@64 {
compatible = "maxim,max1037";
reg = <0x64>;
};
i2c_rtc: rtc@68 {
compatible = "rv4162";
reg = <0x68>;
pinctrl-names = "default";
pinctrl-0 = <&i2c_rtc_int>;
interrupt-parent = <&gpio5>;
interrupts = <10 0>;
};
};
&i2c3 {
status = "okay";
i2c_eeprom_cb: eeprom@51 {
compatible = "atmel,24c32";
reg = <0x51>;
pagesize = <32>;
};
};
&i2c4 {
status = "okay";
};
&i2c5 {
status = "okay";
};
&pinctrl {
u-boot,dm-pre-reloc;
pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma {
bias-pull-up;
drive-strength = <12>;
};
buttons {
user_button_pins: user-button-pins {
/* button 1 */
rockchip,pins = <8 3 RK_FUNC_GPIO &pcfg_pull_up>,
/* button 2 */
<8 0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
rv4162 {
i2c_rtc_int: i2c-rtc-int {
rockchip,pins = <5 10 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
sdmmc {
/*
* Default drive strength isn't enough to achieve even
* high-speed mode on pcm-947 board so bump up to 12 mA.
*/
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
<6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
<6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
<6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>;
};
sdmmc_clk: sdmmc-clk {
rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>;
};
sdmmc_cmd: sdmmc-cmd {
rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>;
};
sdmmc_pwr: sdmmc-pwr {
rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
touchscreen {
ts_irq_pin: ts-irq-pin {
rockchip,pins = <5 15 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb_host {
host0_vbus_drv: host0-vbus-drv {
rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
};
host1_vbus_drv: host1-vbus-drv {
rockchip,pins = <2 0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb_otg {
otg_vbus_drv: otg-vbus-drv {
rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&sdmmc {
u-boot,dm-pre-reloc;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
card-detect-delay = <200>;
disable-wp;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
vmmc-supply = <&vdd_io_sd>;
vqmmc-supply = <&vdd_io_sd>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
status = "okay";
};
&uart2 {
u-boot,dm-pre-reloc;
status = "okay";
};
&usbphy {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host1 {
status = "okay";
};
&usb_otg {
status = "okay";
};

View File

@@ -0,0 +1,514 @@
/*
* Device tree file for Phytec phyCORE-RK3288 SoM
* Copyright (C) 2017 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/net/ti-dp83867.h>
#include "rk3288.dtsi"
/ {
model = "Phytec RK3288 phyCORE";
compatible = "phytec,rk3288-phycore-som", "rockchip,rk3288";
/*
* Set the minimum memory size here and
* let the bootloader set the real size.
*/
memory {
device_type = "memory";
reg = <0 0x8000000>;
};
aliases {
rtc0 = &i2c_rtc;
rtc1 = &rk818;
eeprom0 = &i2c_eeprom_id;
};
ext_gmac: external-gmac-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
clock-output-names = "ext_gmac";
};
io_domains: io_domains {
compatible = "rockchip,rk3288-io-voltage-domain";
status = "okay";
sdcard-supply = <&vdd_io_sd>;
flash0-supply = <&vdd_emmc_io>;
flash1-supply = <&vdd_misc_1v8>;
gpio1830-supply = <&vdd_3v3_io>;
gpio30-supply = <&vdd_3v3_io>;
bb-supply = <&vdd_3v3_io>;
dvp-supply = <&vdd_3v3_io>;
lcdc-supply = <&vdd_3v3_io>;
wifi-supply = <&vdd_3v3_io>;
audio-supply = <&vdd_3v3_io>;
};
leds: user-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&user_led>;
user {
label = "green_led";
gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
default-state = "keep";
};
};
vdd_emmc_io: vdd-emmc-io {
compatible = "regulator-fixed";
regulator-name = "vdd_emmc_io";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vdd_3v3_io>;
};
vdd_in_otg_out: vdd-in-otg-out {
compatible = "regulator-fixed";
regulator-name = "vdd_in_otg_out";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vdd_misc_1v8: vdd-misc-1v8 {
compatible = "regulator-fixed";
regulator-name = "vdd_misc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
&cpu0 {
cpu0-supply = <&vdd_cpu>;
operating-points = <
/* KHz uV */
1800000 1400000
1608000 1350000
1512000 1300000
1416000 1200000
1200000 1100000
1008000 1050000
816000 1000000
696000 950000
600000 900000
408000 900000
312000 900000
216000 900000
126000 900000
>;
};
&emmc {
status = "okay";
u-boot,dm-pre-reloc;
bus-width = <8>;
cap-mmc-highspeed;
disable-wp;
non-removable;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
vmmc-supply = <&vdd_3v3_io>;
vqmmc-supply = <&vdd_emmc_io>;
};
&gmac {
assigned-clocks = <&cru SCLK_MAC>;
assigned-clock-parents = <&ext_gmac>;
clock_in_out = "input";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins &phy_rst &phy_int>;
phy-handle = <&phy0>;
phy-supply = <&vdd_eth_2v5>;
phy-mode = "rgmii-id";
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
tx_delay = <0x0>;
rx_delay = <0x0>;
mdio0 {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
interrupt-parent = <&gpio4>;
interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
enet-phy-lane-no-swap;
};
};
};
&hdmi {
ddc-i2c-bus = <&i2c5>;
};
&i2c0 {
status = "okay";
u-boot,dm-pre-reloc;
clock-frequency = <400000>;
rk818: pmic@1c {
status = "okay";
compatible = "rockchip,rk818";
reg = <0x1c>;
interrupt-parent = <&gpio0>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
u-boot,dm-pre-reloc;
vcc1-supply = <&vdd_sys>;
vcc2-supply = <&vdd_sys>;
vcc3-supply = <&vdd_sys>;
vcc4-supply = <&vdd_sys>;
boost-supply = <&vdd_in_otg_out>;
vcc6-supply = <&vdd_sys>;
vcc7-supply = <&vdd_misc_1v8>;
vcc8-supply = <&vdd_misc_1v8>;
vcc9-supply = <&vdd_3v3_io>;
vddio-supply = <&vdd_3v3_io>;
regulators {
u-boot,dm-pre-reloc;
vdd_log: DCDC_REG1 {
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1250000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vdd_3v3_io: DCDC_REG4 {
regulator-name = "vdd_3v3_io";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vdd_sys: DCDC_BOOST {
regulator-name = "vdd_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <5000000>;
};
};
/* vcc9 */
vdd_sd: SWITCH_REG {
regulator-name = "vdd_sd";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
/* vcc6 */
vdd_eth_2v5: LDO_REG2 {
regulator-name = "vdd_eth_2v5";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <2500000>;
};
};
/* vcc7 */
vdd_1v0: LDO_REG3 {
regulator-name = "vdd_1v0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
/* vcc8 */
vdd_1v8_lcd_ldo: LDO_REG4 {
regulator-name = "vdd_1v8_lcd_ldo";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
/* vcc8 */
vdd_1v0_lcd: LDO_REG6 {
regulator-name = "vdd_1v0_lcd";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
/* vcc7 */
vdd_1v8_ldo: LDO_REG7 {
regulator-name = "vdd_1v8_ldo";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
/* vcc9 */
vdd_io_sd: LDO_REG9 {
regulator-name = "vdd_io_sd";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
};
};
/* M24C32-D */
i2c_eeprom: eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
};
/* M24C32-D Identification page */
i2c_eeprom_id: eeprom@58 {
compatible = "atmel,24c32";
reg = <0x58>;
pagesize = <32>;
};
vdd_cpu: regulator@60 {
compatible = "fcs,fan53555";
reg = <0x60>;
fcs,suspend-voltage-selector = <1>;
regulator-always-on;
regulator-boot-on;
regulator-enable-ramp-delay = <300>;
regulator-name = "vdd_cpu";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1430000>;
regulator-ramp-delay = <8000>;
vin-supply = <&vdd_sys>;
};
};
&pinctrl {
pcfg_output_high: pcfg-output-high {
output-high;
};
emmc {
/*
* We run eMMC at max speed; bump up drive strength.
* We also have external pulls, so disable the internal ones.
*/
emmc_clk: emmc-clk {
rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_12ma>;
};
emmc_cmd: emmc-cmd {
rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_12ma>;
};
emmc_bus8: emmc-bus8 {
rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_12ma>,
<3 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
<3 2 RK_FUNC_2 &pcfg_pull_none_12ma>,
<3 3 RK_FUNC_2 &pcfg_pull_none_12ma>,
<3 4 RK_FUNC_2 &pcfg_pull_none_12ma>,
<3 5 RK_FUNC_2 &pcfg_pull_none_12ma>,
<3 6 RK_FUNC_2 &pcfg_pull_none_12ma>,
<3 7 RK_FUNC_2 &pcfg_pull_none_12ma>;
};
};
gmac {
phy_int: phy-int {
rockchip,pins = <4 2 RK_FUNC_GPIO &pcfg_pull_up>;
};
phy_rst: phy-rst {
rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>;
};
};
leds {
user_led: user-led {
rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_output_high>;
};
};
pmic {
pmic_int: pmic-int {
rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
};
/* Pin for switching state between sleep and non-sleep state */
pmic_sleep: pmic-sleep {
rockchip,pins = <RK_GPIO0 0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&pwm1 {
status = "okay";
};
&saradc {
status = "okay";
vref-supply = <&vdd_1v8_ldo>;
};
&spi2 {
status = "okay";
serial_flash: flash@0 {
compatible = "micron,n25q128a13", "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <50000000>;
m25p,fast-read;
#address-cells = <1>;
#size-cells = <1>;
status = "okay";
};
};
&tsadc {
status = "okay";
rockchip,hw-tshut-mode = <0>;
rockchip,hw-tshut-polarity = <0>;
};
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};
&vopl {
status = "okay";
};
&vopl_mmu {
status = "okay";
};
&wdt {
status = "okay";
};

View File

@@ -167,7 +167,7 @@
sdmmc: dwmmc@ff0c0000 {
compatible = "rockchip,rk3288-dw-mshc";
clock-freq-min-max = <400000 150000000>;
max-frequency = <150000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
@@ -179,7 +179,7 @@
sdio0: dwmmc@ff0d0000 {
compatible = "rockchip,rk3288-dw-mshc";
clock-freq-min-max = <400000 150000000>;
max-frequency = <150000000>;
clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
<&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
@@ -191,7 +191,7 @@
sdio1: dwmmc@ff0e0000 {
compatible = "rockchip,rk3288-dw-mshc";
clock-freq-min-max = <400000 150000000>;
max-frequency = <150000000>;
clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
<&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
@@ -203,7 +203,7 @@
emmc: dwmmc@ff0f0000 {
compatible = "rockchip,rk3288-dw-mshc";
clock-freq-min-max = <400000 150000000>;
max-frequency = <150000000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";

View File

@@ -14,6 +14,32 @@
chosen {
stdout-path = &uart2;
};
vcc3v3_sdmmc: sdmmc-pwren {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
regulator-always-on;
regulator-boot-on;
};
vcc5v0_otg: vcc5v0-otg-drv {
compatible = "regulator-fixed";
enable-active-high;
regulator-name = "vcc5v0_otg";
gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc5v0_host_xhci: vcc5v0-host-xhci-drv {
compatible = "regulator-fixed";
enable-active-high;
regulator-name = "vcc5v0_host_xhci";
gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
&uart2 {
@@ -52,7 +78,12 @@
status = "okay";
};
&usb_host0_xhci {
rockchip,vbus-gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
&usb20_otg {
vbus-supply = <&vcc5v0_otg>;
status = "okay";
};
&usb_host0_xhci {
vbus-supply = <&vcc5v0_host_xhci>;
status = "okay";
};

View File

@@ -25,6 +25,9 @@
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
mmc0 = &emmc;
mmc1 = &sdmmc;
mmc2 = &sdmmc_ext;
};
cpus {
@@ -184,6 +187,7 @@
};
grf: syscon@ff100000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
reg = <0x0 0xff100000 0x0 0x1000>;
#address-cells = <1>;
@@ -350,6 +354,12 @@
status = "disabled";
};
dmc: dmc@ff400000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3328-dmc", "syscon";
reg = <0x0 0xff400000 0x0 0x1000>;
};
cru: clock-controller@ff440000 {
compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
reg = <0x0 0xff440000 0x0 0x1000>;
@@ -415,7 +425,7 @@
sdmmc: rksdmmc@ff500000 {
compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff500000 0x0 0x4000>;
clock-freq-min-max = <400000 150000000>;
max-frequency = <150000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
clock-names = "biu", "ciu";
fifo-depth = <0x100>;
@@ -426,7 +436,7 @@
sdio: dwmmc@ff510000 {
compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff510000 0x0 0x4000>;
clock-freq-min-max = <400000 150000000>;
max-frequency = <150000000>;
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
@@ -438,7 +448,7 @@
emmc: rksdmmc@ff520000 {
compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff520000 0x0 0x4000>;
clock-freq-min-max = <400000 150000000>;
max-frequency = <150000000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
clock-names = "biu", "ciu";
fifo-depth = <0x100>;
@@ -460,10 +470,20 @@
status = "disabled";
};
usb20_otg: usb@ff580000 {
compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
"snps,dwc2";
reg = <0x0 0xff580000 0x0 0x40000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
hnp-srp-disable;
dr_mode = "otg";
status = "disabled";
};
sdmmc_ext: rksdmmc@ff5f0000 {
compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff5f0000 0x0 0x4000>;
clock-freq-min-max = <400000 150000000>;
max-frequency = <150000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
clock-names = "biu", "ciu";
fifo-depth = <0x100>;

View File

@@ -546,6 +546,12 @@
status = "disabled";
};
dmc: dmc@ff610000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3368-dmc", "syscon";
reg = <0x0 0xff610000 0x0 0x1000>;
};
i2c0: i2c@ff650000 {
compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
reg = <0x0 0xff650000 0x0 0x1000>;
@@ -641,6 +647,7 @@
};
pmugrf: syscon@ff738000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3368-pmugrf", "syscon";
reg = <0x0 0xff738000 0x0 0x1000>;
};

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@@ -60,6 +60,18 @@
gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
};
vcc5v0_typec0: vcc5v0-typec0-en {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_typec0";
gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
};
vcc5v0_typec1: vcc5v0-typec1-en {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_typec1";
gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
};
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
@@ -163,7 +175,7 @@
};
&dwc3_typec0 {
rockchip,vbus-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
vbus-supply = <&vcc5v0_typec0>;
status = "okay";
};
@@ -176,7 +188,7 @@
};
&dwc3_typec1 {
rockchip,vbus-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
vbus-supply = <&vcc5v0_typec1>;
status = "okay";
};

View File

@@ -8,7 +8,7 @@
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3399.dtsi"
#include "rk3399-sdram-ddr3-1333.dtsi"
#include "rk3399-sdram-ddr3-1600.dtsi"
/ {
model = "Firefly-RK3399 Board";
@@ -16,6 +16,7 @@
chosen {
stdout-path = &uart2;
u-boot,spl-boot-order = &sdhci, &sdmmc;
};
backlight: backlight {
@@ -156,8 +157,9 @@
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-min-microvolt = <430000>;
regulator-max-microvolt = <1400000>;
regulator-init-microvolt = <950000>;
};
vccadc_ref: vccadc-ref {
@@ -590,6 +592,12 @@
status = "okay";
};
&sdmmc {
u-boot,dm-pre-reloc;
bus-width = <4>;
status = "okay";
};
&sdhci {
bus-width = <8>;
keep-power-in-suspend;

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@@ -12,7 +12,9 @@
compatible = "tsd,rk3399-q7", "tsd,puma", "rockchip,rk3399";
config {
u-boot,spl-payload-offset = <0x40000>; /* 256kbyte */
u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */
u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */
u-boot,efi-partition-entries-offset = <0x200000>; /* 2MB */
u-boot,boot-led = "module_led";
};

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@@ -195,7 +195,6 @@
pinctrl-names = "default";
status = "okay";
mr-nbanks = <1>;
/* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
bank1: bank@0 {
st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_4

View File

@@ -47,6 +47,8 @@
#include "armv7-m.dtsi"
#include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
#include <dt-bindings/clock/stm32fx-clock.h>
#include <dt-bindings/mfd/stm32f7-rcc.h>
/ {
clocks {
@@ -74,7 +76,7 @@
fmc: fmc@A0000000 {
compatible = "st,stm32-fmc";
reg = <0xA0000000 0x1000>;
clocks = <&rcc 0 64>;
clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
u-boot,dm-pre-reloc;
};
@@ -86,14 +88,14 @@
reg-names = "QuadSPI", "QuadSPI-memory";
interrupts = <92>;
spi-max-frequency = <108000000>;
clocks = <&rcc 0 65>;
clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
status = "disabled";
};
usart1: serial@40011000 {
compatible = "st,stm32f7-usart", "st,stm32f7-uart";
reg = <0x40011000 0x400>;
interrupts = <37>;
clocks = <&rcc 0 164>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
status = "disabled";
u-boot,dm-pre-reloc;
};
@@ -119,7 +121,7 @@
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x0 0x400>;
clocks = <&rcc 0 0>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
st,bank-name = "GPIOA";
u-boot,dm-pre-reloc;
};
@@ -129,7 +131,7 @@
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x400 0x400>;
clocks = <&rcc 0 1>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
st,bank-name = "GPIOB";
u-boot,dm-pre-reloc;
};
@@ -140,7 +142,7 @@
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x800 0x400>;
clocks = <&rcc 0 2>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
st,bank-name = "GPIOC";
u-boot,dm-pre-reloc;
};
@@ -150,7 +152,7 @@
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0xc00 0x400>;
clocks = <&rcc 0 3>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
st,bank-name = "GPIOD";
u-boot,dm-pre-reloc;
};
@@ -160,7 +162,7 @@
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x1000 0x400>;
clocks = <&rcc 0 4>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
st,bank-name = "GPIOE";
u-boot,dm-pre-reloc;
};
@@ -170,7 +172,7 @@
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x1400 0x400>;
clocks = <&rcc 0 5>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
st,bank-name = "GPIOF";
u-boot,dm-pre-reloc;
};
@@ -180,7 +182,7 @@
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x1800 0x400>;
clocks = <&rcc 0 6>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
st,bank-name = "GPIOG";
u-boot,dm-pre-reloc;
};
@@ -190,7 +192,7 @@
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x1c00 0x400>;
clocks = <&rcc 0 7>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
st,bank-name = "GPIOH";
u-boot,dm-pre-reloc;
};
@@ -200,7 +202,7 @@
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x2000 0x400>;
clocks = <&rcc 0 8>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
st,bank-name = "GPIOI";
u-boot,dm-pre-reloc;
};
@@ -210,7 +212,7 @@
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x2400 0x400>;
clocks = <&rcc 0 9>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
st,bank-name = "GPIOJ";
u-boot,dm-pre-reloc;
};
@@ -220,7 +222,7 @@
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x2800 0x400>;
clocks = <&rcc 0 10>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
st,bank-name = "GPIOK";
u-boot,dm-pre-reloc;
};

View File

@@ -209,7 +209,6 @@
pinctrl-names = "default";
status = "okay";
mr-nbanks = <1>;
/* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
bank1: bank@0 {
st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_32 BANKS_4

View File

@@ -93,3 +93,7 @@
};
};
};
&uartd {
status = "okay";
};

View File

@@ -475,3 +475,7 @@
};
};
};
&uartd {
status = "okay";
};

View File

@@ -480,3 +480,7 @@
};
};
};
&uartd {
status = "okay";
};

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@@ -8,7 +8,6 @@
aliases {
console = &uarta;
stdout-path = &uarta;
i2c0 = "/i2c@7000d000";
i2c1 = "/i2c@7000c000";
i2c2 = "/i2c@7000c400";
@@ -26,6 +25,10 @@
usb2 = "/usb@7d004000";
};
chosen {
stdout-path = &uarta;
};
host1x@50000000 {
dc@54200000 {
display-timings {

View File

@@ -109,3 +109,7 @@
};
};
&uarta {
status = "okay";
};

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@@ -76,3 +76,7 @@
};
};
};
&uarta {
status = "okay";
};

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@@ -162,3 +162,7 @@
};
};
};
&uarta {
status = "okay";
};

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@@ -812,3 +812,7 @@
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};
&uartd {
status = "okay";
};

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@@ -129,3 +129,7 @@
};
};
&uarta {
status = "okay";
};

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@@ -57,3 +57,7 @@
};
};
};
&uarta {
status = "okay";
};

View File

@@ -58,3 +58,7 @@
};
};
};
&uarta {
status = "okay";
};

View File

@@ -109,3 +109,7 @@
};
};
};
&uarta {
status = "okay";
};

View File

@@ -105,3 +105,7 @@
};
};
};
&uarta {
status = "okay";
};

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@@ -332,3 +332,7 @@
};
};
};
&uarta {
status = "okay";
};

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@@ -346,3 +346,7 @@
};
};
};
&uarta {
status = "okay";
};

View File

@@ -451,3 +451,7 @@
};
};
};
&uarta {
status = "okay";
};

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@@ -106,3 +106,7 @@
};
};
};
&uarta {
status = "okay";
};

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@@ -20,3 +20,7 @@
status = "okay";
};
};
&uartd {
status = "okay";
};

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@@ -68,12 +68,3 @@
&usb2 {
status = "okay";
};
/* for U-Boot only */
&serial0 {
u-boot,dm-pre-reloc;
};
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
};

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@@ -62,12 +62,3 @@
&usb2 {
status = "okay";
};
/* for U-Boot only */
&serial0 {
u-boot,dm-pre-reloc;
};
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
};

View File

@@ -109,7 +109,6 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
u-boot,dm-pre-reloc;
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
@@ -343,11 +342,9 @@
compatible = "socionext,uniphier-ld11-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
u-boot,dm-pre-reloc;
pinctrl: pinctrl {
compatible = "socionext,uniphier-ld11-pinctrl";
u-boot,dm-pre-reloc;
};
};

View File

@@ -50,12 +50,3 @@
&i2c0 {
status = "okay";
};
/* for U-Boot only */
&serial0 {
u-boot,dm-pre-reloc;
};
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
};

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@@ -50,12 +50,3 @@
&i2c0 {
status = "okay";
};
/* for U-Boot only */
&serial0 {
u-boot,dm-pre-reloc;
};
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
};

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@@ -178,7 +178,6 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
u-boot,dm-pre-reloc;
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
@@ -378,11 +377,9 @@
compatible = "socionext,uniphier-ld20-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
u-boot,dm-pre-reloc;
pinctrl: pinctrl {
compatible = "socionext,uniphier-ld20-pinctrl";
u-boot,dm-pre-reloc;
};
};

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@@ -0,0 +1,13 @@
/*
* (C) Copyright 2017 Linaro
* Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _HI3798cv200_DWMMC_H_
#define _HI3798cv200_DWMMC_H_
int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width);
#endif /* _HI3798cv200_DWMMC_H_ */

View File

@@ -0,0 +1,50 @@
/*
* (C) Copyright 2017 Linaro
* Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __HI3798cv200_H__
#define __HI3798cv200_H__
#define REG_BASE_PERI_CTRL 0xF8A20000
#define REG_BASE_CRG 0xF8A22000
/* DEVICES */
#define REG_BASE_MCI 0xF9830000
#define REG_BASE_UART0 0xF8B00000
/* PERI control registers (4KB) */
/* USB2 PHY01 configuration register */
#define PERI_CTRL_USB0 (REG_BASE_PERI_CTRL + 0x120)
/* PERI CRG registers (4KB) */
/* USB2 CTRL0 clock and soft reset */
#define PERI_CRG46 (REG_BASE_CRG + 0xb8)
#define USB2_BUS_CKEN (1<<0)
#define USB2_OHCI48M_CKEN (1<<1)
#define USB2_OHCI12M_CKEN (1<<2)
#define USB2_OTG_UTMI_CKEN (1<<3)
#define USB2_HST_PHY_CKEN (1<<4)
#define USB2_UTMI0_CKEN (1<<5)
#define USB2_BUS_SRST_REQ (1<<12)
#define USB2_UTMI0_SRST_REQ (1<<13)
#define USB2_HST_PHY_SYST_REQ (1<<16)
#define USB2_OTG_PHY_SYST_REQ (1<<17)
#define USB2_CLK48_SEL (1<<20)
/* USB2 PHY clock and soft reset */
#define PERI_CRG47 (REG_BASE_CRG + 0xbc)
#define USB2_PHY01_REF_CKEN (1 << 0)
#define USB2_PHY2_REF_CKEN (1 << 2)
#define USB2_PHY01_SRST_REQ (1 << 4)
#define USB2_PHY2_SRST_REQ (1 << 6)
#define USB2_PHY01_SRST_TREQ0 (1 << 8)
#define USB2_PHY01_SRST_TREQ1 (1 << 9)
#define USB2_PHY2_SRST_TREQ (1 << 10)
#define USB2_PHY01_REFCLK_SEL (1 << 12)
#define USB2_PHY2_REFCLK_SEL (1 << 14)
#endif

View File

@@ -81,7 +81,6 @@
/* SATA */
#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
#define CONFIG_SCSI
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT

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@@ -0,0 +1,11 @@
/*
* (C) Copyright 2017 - Beniamino Galvani <b.galvani@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_MESON_GPIO_H
#define __ASM_ARCH_MESON_GPIO_H
#endif /* __ASM_ARCH_MESON_GPIO_H */

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@@ -9,6 +9,6 @@
#ifndef __ASM_ARCH_MX25_GPIO_H
#define __ASM_ARCH_MX25_GPIO_H
#include <asm/imx-common/gpio.h>
#include <asm/mach-imx/gpio.h>
#endif

View File

@@ -16,7 +16,7 @@
#ifndef __IOMUX_MX25_H__
#define __IOMUX_MX25_H__
#include <asm/imx-common/iomux-v3.h>
#include <asm/mach-imx/iomux-v3.h>
/* Pad control groupings */
#define MX25_KPP_ROW_PAD_CTRL PAD_CTL_PUS_100K_UP

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@@ -9,6 +9,6 @@
#ifndef __ASM_ARCH_MX31_GPIO_H
#define __ASM_ARCH_MX31_GPIO_H
#include <asm/imx-common/gpio.h>
#include <asm/mach-imx/gpio.h>
#endif

View File

@@ -8,7 +8,7 @@
#ifndef _MX31_SYS_PROTO_H_
#define _MX31_SYS_PROTO_H_
#include <asm/imx-common/sys_proto.h>
#include <asm/mach-imx/sys_proto.h>
struct mxc_weimcs {
u32 upper;

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@@ -9,6 +9,6 @@
#ifndef __ASM_ARCH_MX35_GPIO_H
#define __ASM_ARCH_MX35_GPIO_H
#include <asm/imx-common/gpio.h>
#include <asm/mach-imx/gpio.h>
#endif

View File

@@ -11,7 +11,7 @@
#ifndef __IOMUX_MX35_H__
#define __IOMUX_MX35_H__
#include <asm/imx-common/iomux-v3.h>
#include <asm/mach-imx/iomux-v3.h>
/*
* The naming convention for the pad modes is MX35_PAD_<padname>__<padmode>

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@@ -8,7 +8,7 @@
#ifndef _MX35_SYS_PROTO_H_
#define _MX35_SYS_PROTO_H_
#include <asm/imx-common/sys_proto.h>
#include <asm/mach-imx/sys_proto.h>
void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config, u32 row,
u32 col, u32 dsize, u32 refresh);

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@@ -9,6 +9,6 @@
#ifndef __ASM_ARCH_MX5_GPIO_H
#define __ASM_ARCH_MX5_GPIO_H
#include <asm/imx-common/gpio.h>
#include <asm/mach-imx/gpio.h>
#endif

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@@ -19,7 +19,7 @@
#ifndef __IOMUX_MX51_H__
#define __IOMUX_MX51_H__
#include <asm/imx-common/iomux-v3.h>
#include <asm/mach-imx/iomux-v3.h>
/* Pad control groupings */
#define MX51_UART_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \

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@@ -11,7 +11,7 @@
#ifndef __IOMUX_MX53_H__
#define __IOMUX_MX53_H__
#include <asm/imx-common/iomux-v3.h>
#include <asm/mach-imx/iomux-v3.h>
/* Pad control groupings */
#define MX53_UART_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \

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@@ -5,4 +5,4 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/imx-common/sys_proto.h>
#include <asm/mach-imx/sys_proto.h>

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@@ -9,6 +9,6 @@
#ifndef __ASM_ARCH_MX6_GPIO_H
#define __ASM_ARCH_MX6_GPIO_H
#include <asm/imx-common/gpio.h>
#include <asm/mach-imx/gpio.h>
#endif /* __ASM_ARCH_MX6_GPIO_H */

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@@ -359,7 +359,7 @@
#endif
#define FEC_QUIRK_ENET_MAC
#include <asm/imx-common/regs-lcdif.h>
#include <asm/mach-imx/regs-lcdif.h>
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>

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@@ -6,7 +6,7 @@
#ifndef __ASM_ARCH_MX6_PINS_H__
#define __ASM_ARCH_MX6_PINS_H__
#include <asm/imx-common/iomux-v3.h>
#include <asm/mach-imx/iomux-v3.h>
#define MX6_PAD_DECLARE(prefix, name, pco, mc, mm, sio, si, pc) \
prefix##name = IOMUX_PAD(pco, mc, mm, sio, si, pc)

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@@ -7,7 +7,7 @@
#ifndef __ASM_ARCH_MX6_MX6SL_PINS_H__
#define __ASM_ARCH_MX6_MX6SL_PINS_H__
#include <asm/imx-common/iomux-v3.h>
#include <asm/mach-imx/iomux-v3.h>
enum {
MX6_PAD_ECSPI1_MISO__ECSPI_MISO = IOMUX_PAD(0x0358, 0x0068, 0, 0x0684, 0, 0),

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@@ -7,7 +7,7 @@
#ifndef __ASM_ARCH_IMX6SLL_PINS_H__
#define __ASM_ARCH_IMX6SLL_PINS_H__
#include <asm/imx-common/iomux-v3.h>
#include <asm/mach-imx/iomux-v3.h>
enum {
MX6_PAD_WDOG_B__WDOG1_B = IOMUX_PAD(0x02DC, 0x0014, 0, 0x0000, 0, 0),

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@@ -7,7 +7,7 @@
#ifndef __ASM_ARCH_MX6_MX6_PINS_H__
#define __ASM_ARCH_MX6_MX6_PINS_H__
#include <asm/imx-common/iomux-v3.h>
#include <asm/mach-imx/iomux-v3.h>
enum {
MX6_PAD_GPIO1_IO00__I2C1_SCL = IOMUX_PAD(0x035C, 0x0014, IOMUX_CONFIG_SION | 0, 0x07A8, 1, 0),

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