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1361 Commits

Author SHA1 Message Date
Tom Rini
c98ac3487e Prepare v2017.09
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-11 14:10:40 -04:00
Jorge Ramirez-Ortiz
bbfbdb5722 MAINTAINERS: board: qcom: db410c: Maintainer changed
Replacing original author Mateusz Kulikowski
<mateusz.kulikowski@gmail.com> as db410c maintainer

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
2017-09-11 13:34:31 -04:00
Bin Meng
584f316f11 cmd: ide: Make the first device the default one
At present the IDE device number is initialized to -1, which means
we cannot type "ide read" command before setting the device number
via "ide device #".

For convenience, let's set the first device as the default one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-10 12:27:43 -04:00
Bin Meng
1f4adab873 block: ide: Don't bother to create BLK device if no CDROM inserted
When there is no CDROM inserted, the block size is zero hence there
is no need to create a BLK device for it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-10 12:27:40 -04:00
Bin Meng
68e6f221ed block: ide: Fix block read/write with driver model
This converts the IDE driver to driver model so that block read and
write are fully functional.

Fixes: b7c6baef ("x86: Convert MMC to driver model")
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-09-10 12:27:37 -04:00
Bin Meng
eb81b1a4d3 blk: Use macros for block device vendor/product/rev string size
So far these are using magic numbers. Replace them with macros.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-10 12:27:32 -04:00
Tom Rini
4ccceefb7f edison: Disable CONFIG_USB_HOST_ETHER
This board does dwc3 gadget, not host, so we cannot have host support or
we will fail to link.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-08 16:43:24 -04:00
Tom Rini
5eb35220b2 env: Migrate CONFIG_ENV_AES to Kconfig and deprecate
The underlying implementation for ENV_AES has security complications and
is not recommended for use.  Please see CVE-2017-3225 and CVE-2017-3226
for more details.  Mark this as deprecated now and delete this in the
medium term if no one comes forward to re-work the support.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-08 13:12:16 -04:00
Chris Packham
0683fb7242 usb: doc: update README.usb for new config options
A number of the config options for USB networking have been migrated to
Kconfig. Update README.usb to reflect this.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
2017-09-08 10:23:01 -04:00
Chris Packham
f58ad98a62 usb: net: migrate USB Ethernet adapters to Kconfig
This migrates ASIX, ASIX88179, MCS7830, RTL8152 and SMSC95XX to Kconfig.
Update defconfigs.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-08 10:23:00 -04:00
Chris Packham
ae3584498b usb: net: migrate CONFIG_USB_HOST_ETHER to Kconfig
CONFIG_USB_HOST_ETHER is the framework that the drivers are dependent on
USB_HOST_ETHER. Use this as a menu and move the existing LAN75XX and
LAN78XX options under new menu. Finally update the defconfigs that need
CONFIG_USB_HOST_ETHER.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-08 10:21:46 -04:00
Chris Packham
8ffb23cbf5 Kconfig: drop CONFIG_USB_ETHER_RNDIS
This is not a valid option. Drop it.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-08 10:17:17 -04:00
Chris Packham
9272c7b160 Kconfig: drop CONFIG_USB_ETHER_DM9601
This is not a valid option. Drop it.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-08 10:15:47 -04:00
Nobuhiro Iwamatsu
eb3eb6020f README: Fix typo in description of CONFIG_OF_EMBED
The correct name is 'gd->fdt_blob', not 'gd->blob'.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-08 10:15:47 -04:00
Tom Rini
df35f4530b configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-08 10:14:49 -04:00
Kever Yang
0532ceef30 rockchip: enable SPL_SYSRESET config for all Rockchip SoCs
With Makefiles testing for $(SPL_TPL_)SYSRESET, we need SPL_SYSRESET
for do_reset() in SPL for Rockchip SoCs.

References: 87c16d4 "drivers: spl: consistently use the $(SPL_TPL_) macro"
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-08 11:45:19 +02:00
Kever Yang
e1f6881367 rockchip: rk3328: fix syscon id table
syscon id table need a dummy member as NULL ending, or else system
will panic while try to match a compatible in this table as a list.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-08 11:44:51 +02:00
Marek Vasut
25f840d7ef ARM: rmobile: Disable CONFIG_ARCH_FIXUP_FDT_MEMORY
Disable CONFIG_ARCH_FIXUP_FDT_MEMORY to prevent U-Boot from modifying
the memory {} nodes in the DT passed to the Linux kernel. The R8A779x
DT contains multiple memory {} nodes, while U-Boot only modifies the
first one and stuffs all the memory entries into it, which is wrong.
Disabling CONFIG_ARCH_FIXUP_FDT_MEMORY is the least intrusive way to
fix the issue this close to the release, while the real fix is to
extend the fdt_fixup_memory_banks() to handle multiple memory nodes
in DT.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-07 20:04:41 -04:00
Marek Vasut
183f5fd3ca ARM: rmobile: Fix SD divider settings on Gen3
On RCar M3 and on RCar H3 newer than and not including ES1.0, the SD clock
must be divided by 4 rather than 2 because a hardware workaround present
only in the H3 ES1.0 has been removed from these chips. U-Boot currently
only supports M3 and H3 ES 2.0 and newer, so configure the SD pre-divider
to 4 to prevent SD instability.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-07 20:04:40 -04:00
Tom Rini
ec6bc928bb Merge git://git.denx.de/u-boot-net 2017-09-07 14:48:23 -04:00
Heinrich Schuchardt
e4691564cc net: fix typos
%s/Desriptor/Descriptor/g

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-09-07 13:23:52 -05:00
Madalin Bucur
10710b4ec5 armv8: ls1043/ls1046aqds: add support for RGMII_TXID
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: York Sun <york.sun@nxp.com>
2017-09-07 13:23:52 -05:00
Tom Rini
0b1e580672 net: nfs: Drop CONFIG_NFS_READ_SIZE
In the general case, CONFIG_NFS_READ_SIZE is unchanged from the default
of 1024.  There are in fact no in-tree users that increase this size.
Adjust the comment to reflect what could be done in the future in
conjunction with CONFIG_IP_DEFRAG.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-09-07 13:23:52 -05:00
Madalin Bucur
05b29aa0cb net: phy: realtek: fix enabling of the TX-delay for RTL8211F
The old logic always enabled the TX-delay when the phy-mode was set to
PHY_INTERFACE_MODE_RGMII. With this patch we enable the TX delay for
PHY_INTERFACE_MODE_RGMII_ID and PHY_INTERFACE_MODE_RGMII_TXID and
disable it for PHY_INTERFACE_MODE_RGMII.

Based on a similar change made in the Linux Realtek PHY driver
by Martin Blumenstingl <martin.blumenstingl@googlemail.com>.

Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: York Sun <york.sun@nxp.com>
2017-09-07 13:23:52 -05:00
Kever Yang
b5b82abcf5 spl: typo fix for SPL_ATF_SUPPORT description
Delete one redundant 'which' for SPL_ATF_SUPPORT description.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2017-09-07 10:44:38 -04:00
Heinrich Schuchardt
d72fd7b340 linker_lists: remove incorrect comment
Remove a comment line refering to a non-existent file.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-09-07 10:44:37 -04:00
Heinrich Schuchardt
de2de3192f vsprintf: vsprintf does not have parameter size
The inline documentation of vsprintf mentions a parameter size
which does not exist in the function declaration.

int vsprintf(char *buf, const char *fmt, va_list args);

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-09-07 10:44:37 -04:00
Paul Barker
2d0cf3b2ae Revert "dm: arm: rpi: Drop CONFIG_OF_EMBED"
This reverts commit 25877d4e4c.

This is a workaround for Raspberry Pi boot failures seen when passing on
the device tree provided by the Raspberry Pi firmware at boot. Without
CONFIG_OF_EMBED, we just get stuck at "Starting kernel ..." when we try
to boot Linux with this device tree.

Signed-off-by: Paul Barker <pbarker@toganlabs.com>
Cc: Simon Glass <sjg@chromium.org>
Tested-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-07 10:44:36 -04:00
Bin Meng
eab44c93eb tools: .gitignore: Add libfdt related files
Some files are generated during libfdt build. Ignore them.

This was wrongly put in the .gitignore in the root directory before.
Now let's remove entries there and put them in the right place.

Fixes: 34e2c285 ("gitignore: add intermediates from libfdt build")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-07 10:44:35 -04:00
Bin Meng
d11d3b2fa6 tools: .gitignore: Sort in alphabetical order
These are currently out of alphabetical order.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-07 10:44:34 -04:00
Alison Chaiken
2105f34843 doc: remove duplicate text in README.gpt
Signed-off-by: Alison Chaiken <alison@she-devel.com>
2017-09-07 10:44:34 -04:00
Bin Meng
337e3b897d part: mac: Suppress the error message after reading ddb
Change to use 'debug' to output the error message if it fails to
read the driver descriptor block.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-07 10:44:33 -04:00
Simon Glass
84a42069f2 env: Add 'envtools' target to 'make help'
The target is not currently mentioned anywhere. Add it to the help so
people can find it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-09-05 20:34:09 -04:00
Simon Glass
5733295714 env: Fix operation of 'make environ'
This was broken by the recent environment refactoring. Specifically:

$  make environ
scripts/Makefile.build:59: tools/environ/Makefile: No such file or directory
make[1]: *** No rule to make target 'tools/environ/Makefile'.  Stop.
make: *** [Makefile:1469: environ] Error 2

Fix this by updating the Makefile and adjusting the #include filesnames in
two C files.

Fixes: ec74f5f (Makefile: Rename 'env' target to 'environ')
Reported-by: Måns Rullgård <mans@mansr.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-09-05 20:34:08 -04:00
Sam Protsenko
de4e4edaff usb: gadget: g_dnl: Sync internal SN variable with env
Since commit 842778a091 ("usb: gadget: g_dnl: only set iSerialNumber
if we have a serial#") "fastboot devices" stopped to show correct device
serial number for TI boards, showing this line instead:

    ????????????	fastboot

This is because serial# env variable could be set after g_dnl gadget was
initialized (e.g. by using env_set() in the board file).

To fix this, let's update internal serial number variable (g_dnl_serial)
when "serial#" env var is changed.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Cc: Felipe Balbi <felipe.balbi@linux.intel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Acked-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
2017-09-05 20:17:08 -04:00
Tom Rini
2d3229bea2 env: Fix out of tree building of tools-all
With the move of environment code from common/ to env/ a number of
changes needed to be made to various make targets.  We missed updating
some of the files required for out of tree builds of the tools.  Correct
the 'environ' target to know that we need to work under tools/env/ still
(not tools/environ/) and then update the wrappers in env_attr.c and
env_flags.c to point to the new correct file.

Reported-by: Peter Robinson <pbrobinson@gmail.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-05 15:59:47 -04:00
Tom Rini
8dcb6f1f81 Merge git://git.denx.de/u-boot-video 2017-09-05 08:54:55 -04:00
Tom Rini
08d0c53d6b Merge git://git.denx.de/u-boot-rockchip 2017-09-05 07:11:46 -04:00
Anatolij Gustschin
c967fb78e4 MAINTAINERS: add lcd files to video section
LCD drivers are video related, so add them to video section.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-09-05 11:17:31 +02:00
Wadim Egorov
5deaa53028 rockchip: i2c: fix >32 byte reads
The hw can read up to 32 bytes at a time. If we need
more than one chunk, we have to enter the plain RX mode.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-05 11:13:36 +02:00
Kever Yang
313bbcf0ea rockchip: firefly-rk3399: enable ATF and dwmmc
enable the ATF option and SDCard in defconfig.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-05 11:04:35 +02:00
Philipp Tomsich
5798d503fc rockchip: timer: fix U_BOOT_DRIVER name
When I originally added this driver, I did some careless (and in
retrospect: mindless) copy & paste for the U_BOOT_DRIVER structure
skeletion... unfortunately, the 'arc_timer' string was committed
and slipped through all reviews.

This fixes the U_BOOT_DRIVER name to read 'rockchip_rk3368_timer'
(as originally intended).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reported-by: Artturi Alm <artturi.alm@gmail.com>
2017-09-05 11:04:35 +02:00
Wadim Egorov
40d4f79b81 rockchip: rk3288: Add reset reason detection
Sometimes it's helpful to know the reset reason caused in the SoC.
Add reset reason detection for the RK3288 SoC.
This will set an environment variable which represents the reset reason.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-05 11:04:35 +02:00
Wadim Egorov
32191a3912 rockchip: phycore: Read configuration EEPROM & set ethaddr in late init
Read SoM information from EEPROM and set ethaddr in late init.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-05 11:04:34 +02:00
Tom Rini
a0e80c97c9 Merge branch 'rmobile' of git://git.denx.de/u-boot-sh 2017-09-04 22:17:59 -04:00
Marek Vasut
0d0915bef7 ARM: rmobile: Add missing IPSR18 bits to R8A7795 PFC
The IPSR18 register bits were missing from the R8A7795 ES2.0+ PFC
tables, which triggered a BUG() in sh_pfc driver. This is because
of an out-of-bounds access to the pinmux_gpios[] array in the PFC
tables, which was too short due to the missing IPSR18 bits.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-05 07:51:39 +09:00
Marek Vasut
8212f56347 ARM: rmobile: Drop board_mmc_init
The board_mmc_init() is no longer invoked when DM is used, so move
all the pinmux config into board_init() instead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-05 07:51:39 +09:00
Marek Vasut
3158b6f606 ARM: rmobile: Replace CONFIG_RAVB with CONFIG_RENESAS_RAVB in boards
The configuration option name is the later, so replace usage of
CONFIG_RAVB in board files with CONFIG_RENESAS_RAVB , otherwise
the RAVB pinmux is not set and ethernet does not work.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-05 07:51:39 +09:00
Niko Mauno
a7126edcb3 splash_source: Verify FIT magic
Before reading entire FIT image, add sanity check by testing image
header against FDT_MAGIC. This should help avoid problems in situations
where FIT is not yet available from storage device, for example when
performing initial programming of device.

Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: Tomas Melin <tomas.melin@vaisala.com>
2017-09-04 23:53:47 +02:00
Anatolij Gustschin
f8ba7f2774 video: ipuv3_fb: skip IPU shutdown if IPU was not enabled before
Boards can skip display interface init using board_video_skip().
If display interface was not initialized (e.g. no ipuv3 framebuffer
registered or IPU clock disabled), booting Linux stops due to the
crash in IPU shutdown function, when accessing IPU registers.
Check IPU clock and skip shutdown if clock is not enabled.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-09-04 23:33:45 +02:00
Tom Rini
ced0fd938d Merge git://git.denx.de/u-boot-dm 2017-09-04 14:56:45 -04:00
Tom Rini
0e88cdd17d Prepare v2017.09-rc4
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-04 09:02:48 -04:00
Clemens Gruber
4c2cf973aa crypto/fsl: fix obj-yy in Makefile
When enabling CONFIG_CMD_BLOB and/or CONFIG_CMD_DEKBLOB, the build fails
with a linker error:
  ...
  LD      u-boot
arch/arm/mach-imx/built-in.o: In function `blob_encap_dek':
/home/clemens/dev/u-boot/arch/arm/mach-imx/cmd_dek.c:46: undefined
reference to `blob_dek'

This is due to an error in the Makefile, resulting in obj-yy/obj-yn/..
and fsl_blob.o is therefore not linked.

Fix it by splitting it up into two obj-y lines.

Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-09-04 09:02:07 -04:00
Lukasz Majewski
4b51a89170 git: mailrc: Update e-mail address
Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-09-04 09:02:06 -04:00
Simon Glass
d944bf6b5e dm: core: Add livetree documentation
Add some documentation for the live device tree support in U-Boot. This
was missing from the initial series.

Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
2017-09-04 02:10:06 -06:00
Philipp Tomsich
34e2c285da gitignore: add intermediates from libfdt build
Since ee95d10 (fdt: Build the new python libfdt module), a number of
additional files are auto-generated/installed into the tools directory.
List these in .gitignore to suppress having them listed as untracked.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
References: ee95d10 (fdt: Build the new python libfdt module)
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-04 02:10:06 -06:00
Hannes Schmelzer
cee8c35d1b fdt: fix 'prop (...) not found!' error in 'fdt set' command
This commit brings things back to the well known working state of the
command.
-
With commit 9620d87259
(cmd/fdt: support single value replacement within an array)

there was an error introduced modifying (inserting) a property to a
device-tree node.
fdt_getprop(...) returnes a len with -1 for a non-existing property, but
a memcpy with len -1 isn't a good idea and things went wrong (crash).
-
Some times later Tom did repair this
with commit 99bb38e2cc
(fdt: Check for NULL return from fdt_getprop in 'fdt set')

This repairs the crash but the behaviour of the command isn't like
before, it makes it impossible to insert a property.
-

Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Acked-by: Simon Glass <sjg@chromium.org>
2017-09-04 02:10:06 -06:00
Simon Glass
302466d07f dm: Add migration plan for CONFIG_BLK
The CONFIG_BLK conversion involves quite invasive changes in the U-Boot
code, with #ifdefs and different code paths. We should try to move over to
this soon so we can drop the old code.

Set a deadline of 9 months for this work, rounded up to the next release.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-04 02:10:06 -06:00
Bin Meng
6935aec0e3 Makefile: Suppress output of python libfdt build command
This should not be printed by default. Prefix it with $(Q).

Fixes ee95d10b: ("fdt: Build the new python libfdt module")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-03 15:30:37 -04:00
Bin Meng
a5ab5c771b Makefile: Quiesce libfdt build
Since commit 3809e302 "Makefile: honor PYTHON configuration properly",
the build commands of libfdt are printed while previously were not.

This adds the missing '--quiet' back.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-03 15:30:36 -04:00
Derald D. Woods
c257c96d9b omap3: evm: Fixes for CONFIG_NAND, SPL_OS_BOOT, USB, and environment
- Pass MTDPARTS kernel arguments to kernel
- Use Kconfig CONFIG_NAND instead of CONFIG_SYS_EXTRA_OPTIONS="NAND"
- Call 'usb_stop' on kernel start
- Update Falcon mode setup to match other OMAP3 boards
- Use "uEnv.txt" as boot script instead of "boot.scr"
2017-09-03 15:30:36 -04:00
Bin Meng
2c3b68081a block: Drop the ftide020 driver
This is not used in U-Boot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-03 15:30:35 -04:00
Bin Meng
caa8bfbc45 block: ide: Drop CONFIG_IDE_LED
This is actually not used. Drop it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-03 15:30:35 -04:00
Bin Meng
f1823d3aaa block: ide: Drop CONFIG_IDE_INIT_POSTRESET
This is not referenced anywhere. Drop it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-03 15:30:34 -04:00
Bin Meng
9e18eae276 nvme: Remove dead codes in nvme_setup_io_queues()
Execution cannot reach this statement: "nr_io_queues = result;"

Reported-by: Coverity (CID: 166731)
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 15:30:34 -04:00
Bin Meng
52a5690efb nvme: Fix potential sign extension issue in nvme_blk_rw()
"lbas" with type "u16" (16 bits, unsigned) is promoted in
"lbas << ns->lba_shift" to type "int" (32 bits, signed), then
sign-extended to type "unsigned long long" (64 bits, unsigned).
If "lbas << ns->lba_shift" is greater than 0x7FFFFFFF, the upper
bits of the result will all be 1.

Fix it by casting "lbas" to "u32".

Reported-by: Coverity (CID: 166730)
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 15:30:33 -04:00
Bin Meng
37d46870b3 nvme: Fix wrong ndev->queues memset
memset() was given a sizeof(NVME_Q_NUM * sizeof(struct nvme_queue *)
to clear, which is wrong.

Reported-by: Coverity (CID: 166729)
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 15:30:32 -04:00
Heinrich Schuchardt
5eae466ea1 disk: part: fix typo
%s/Desriptor/Descriptor/g

Fix lines over 80 characters with said typo.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-09-03 15:30:32 -04:00
Lukasz Majewski
40fe89c6e8 fix: fw_env: Prevent writing error message on special files, which don't support fsync
According to fsync specification [1] some special files (e.g., a pipe, FIFO,
or socket) don't support synchronization and return either EROFS or EINVAL.

On the linux side the sys_fsync -> do_fsync() checks if the requested file
has f_op->fsync defined. If not it returns EINVAL [2].

This commit prevents writing error messages for files (devices), which
do not support fsync().

[1] - http://man7.org/linux/man-pages/man2/fsync.2.html
[2] - http://elixir.free-electrons.com/linux/v4.13-rc6/source/fs/sync.c#L183

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Michael Heimpold <mhei@heimpold.de>
2017-09-03 15:30:31 -04:00
Jonathan Gray
8f1603bd78 bch: don't use __BSD_VISIBLE to test for fls
Commit 4ecc988301 assumes fls is in libc
if __BSD_VISIBLE is defined.  This appears to only be true on FreeBSD
and DragonFlyBSD.  OpenBSD defines __BSD_VISIBLE and does not have fls
in strings.h/libc.

Switch the test for __BSD_VISIBLE to one for __DragonFly__ and
__FreeBSD__ to unbreak the build on OpenBSD.

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
2017-09-03 15:30:31 -04:00
Thomas Petazzoni
e090579d0a include/configs: remove numerous CONFIG_SYS_BARGSIZE definitions
This commit removes definitions of CONFIG_SYS_BARGSIZE defined to be
equal to CONFIG_SYS_CBSIZE in numerous configuration files.

We remove such definitions in two situations:

 - CONFIG_SYS_CBSIZE is otherwise not defined in the board
   configuration file, which means the default value of
   CONFIG_SYS_CBSIZE == 256 applies. In this case, the default value
   of CONFIG_SYS_BARGSIZE == 512 (common/image.c) is suitable, as it is
   larger.

 - CONFIG_SYS_CBSIZE is defined in the board configuration file, but
   to a value equal or less than 512. In this case, the default value
   of CONFIG_SYS_BARGSIZE == 512 (common.image.c) is suitable, as it
   is equal or larger.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 15:30:30 -04:00
Thomas Petazzoni
8a7507a8a3 include/configs: remove default values of CONFIG_SYS_BARGSIZE
CONFIG_SYS_BARGSIZE is already defined to 512 in common/image.c when
not defined. Therefore, there is no point in having board
configuration files define it to 512.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 15:30:30 -04:00
Thomas Petazzoni
1f20fc53b3 include/configs: drop default definitions of CONFIG_SYS_MAXARGS
Now that include/config_fallbacks.h define a sane fallback for
CONFIG_SYS_MAXARGS, we can drop the definition of this constant in all
configurations that were using the default value.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 15:30:29 -04:00
Thomas Petazzoni
bb939d7a6d include/config_fallbacks.h: add default for CONFIG_SYS_MAXARGS
CONFIG_SYS_MAXARGS contains the maximum number of arguments accepted
by U-Boot commands. Since the vast majority of the platforms define it
to 16, it makes sense to have a default definition to 16, which will
allow to remove this definition from a significant number of
platforms.

It will allow to remove the default definition from 216 platform .h
files, leaving only 56 platforms with non-default values (15, 24, 32,
48, 64, 96, 128 or 256).

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 15:30:29 -04:00
Thomas Petazzoni
432e398068 include/configs: drop default definitions of CONFIG_SYS_PBSIZE
Now that the fallback value of CONFIG_SYS_PBSIZE in
include/config_fallbacks.h has been adjusted, remove its definition
from a large number of board configuration files.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 15:30:28 -04:00
Thomas Petazzoni
80c914f1bb include/config_fallbacks.h: change fallback for CONFIG_SYS_PBSIZE
Most of the platforms are using CONFIG_SYS_CBSIZE +
sizeof(CONFIG_SYS_PROMPT) + 16 as their value for CONFIG_SYS_PBSIZE,
so let's adopt this for the fallback value of CONFIG_SYS_PBSIZE.

This will allow us to drop an explicit definition of CONFIG_SYS_PBSIZE
from a large number of platforms.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 15:30:27 -04:00
Thomas Petazzoni
3784c789e7 include/configs: remove CONFIG_SYS_CBSIZE when the default value is used
Now that include/config_fallbacks.h define a sane fallback for
CONFIG_SYS_CBSIZE, we can drop the definition of this constant in all
configurations that were using the default value.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Drop <config.h> from stih410-b2260.h]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-03 15:30:06 -04:00
Thomas Petazzoni
72f09606d8 include/config_fallbacks.h: add default for CONFIG_SYS_CBSIZE
CONFIG_SYS_CBSIZE contains the buffer size for input for the
console. The vast majority of platforms define them to some reasonable
value (256, 512 or 1024 bytes), and it is quite annoying to repeat
this definition for all platforms while it isn't really HW-related.

Therefore, let's provide a sane fallback value in config_fallbacks.h,
so that platforms can rely on it instead of having to explicitly
define it.

We use 1024 when KGDB is enabled, and 256 otherwise, which is what the
majority of the platforms are doing.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 11:04:52 -04:00
Maxime Ripard
79c5912e8d part: efi: Disable overlap check
The current code checks that no partitions overlap with the GPT partition
table using the offset of the first LBA usable for that partition.

This works fine, unless you have a partition entry that is further away
than it usually is and you want to create partitions in the gap between the
GPT header and the GPT partition entries, for example to reflash a
bootloader that needs to be set there.

Rework the test to something a bit smarter that checks whether a partition
would overlap with either the GPT header or the partition entries, no
matter where it is on the disk.

Partitions that do not have a start LBA specified will still start at the
first LBA usable set in the GPT header, to avoid weird behaviours.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 11:04:51 -04:00
Maxime Ripard
47d7ee47ba part: efi: make gpt_fill_pte take the device descriptor
The gpt_fill_pte will need to access the device block size. Let's pass the
device descriptor as an argument.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 11:04:51 -04:00
Maxime Ripard
5276e8b62d part: efi: rework the partition start and size in gpt_fill_pte
The start variable is only used inside a loop, and is never affected inside
it, so it's a purely local variable.

In the same way the partition size is accessed several times, so we can
store it in a variable.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 11:04:48 -04:00
Maxime Ripard
89d33a2c0d part: efi: Fix offset
Both the config option and the DT options specify the offset to set the GPT
at in bytes, yet the code treats those values as block numbers.

Fix that.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-03 11:04:47 -04:00
Tom Rini
41a85fe3b9 Merge git://git.denx.de/u-boot-x86 2017-09-02 20:50:59 -04:00
Adam Ford
e3f24d4f2c Kconfig: Add EEPROM options to Kconfig when I2C_EEPROM is set
Add the following options to drivers/misc/Kconfig:
	SYS_I2C_EEPROM_ADDR
	SYS_I2C_EEPROM_BUS
	SYS_EEPROM_SIZE
	SYS_EEPROM_PAGE_WRITE_BITS
	SYS_EEPROM_PAGE_WRITE_DELAY_MS
	SYS_I2C_EEPROM_ADDR_LEN
	SYS_I2C_EEPROM_ADDR_OVERFLOW

This does not migrate any boards, but provides a foundations for
those who want/need these options

Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Migrate uniphier]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-02 15:50:30 -04:00
Stefan Roese
f04034cba4 x86: theadorable-x86-common: Remove "ip=dhcp" from default environment
Without ethernet cable plugged, "ip=dhcp" leads to a complete hangup in
Linux booting and the system does not boot into userland at all. Since
its not required to have an active network connection on these board,
lets remove this statement from the default environment.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-02 23:49:34 +08:00
Bin Meng
3fe6e6e2aa x86: baytrail: acpi: Add full reset bit to the reset register value in FADT
It was noticed a few times, that the reboot from Linux (reboot command)
is different from the reboot (reset command) under U-Boot. The U-Boot
version does seem to reset the board more deeply (PCI cards etc) than
the Linux reboot.

This is actually caused by missing full reset bit in the reset register
value in the ACPI FADT table.

Reported-by: Stefan Roese <sr@denx.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
2017-09-02 23:35:55 +08:00
Bin Meng
d2ca80c3d7 x86: ich-spi: Clear atomic preop only when SPI settings are not locked
The atomic preop register can only be written when SPI settings are
not locked, otherwise it's read-only.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-09-02 23:35:55 +08:00
Bin Meng
52dd56ba84 x86: ich-spi: Remove useless assignment in ich_spi_xfer()
In ich_spi_xfer() when the driver presets control fields, control
variable gets assigned twice. Apparently only the last assignment
takes effect. Remove the other one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-09-02 23:35:55 +08:00
Adam Ford
db35573a71 omap3_logic: Move CONFIG_SYS_NAND_U_BOOT_OFFS to Kconfig
Manually enable SYS_NAND_U_BOOT_LOCATIONS.
Set CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 and remove it from header

Signed-off-by: Adam Ford <aford173@gmail.com>
2017-09-02 10:45:24 -04:00
Adam Ford
6ef2f90108 Convert CONFIG_BCH to Kconfig
This converts the following to Kconfig:
   CONFIG_BCH

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-01 20:45:26 -04:00
Adam Ford
edd1653f04 Convert CONFIG_SPL_OMAP3_ID_NAND to Kconfig
This converts the following to Kconfig:
   CONFIG_SPL_OMAP3_ID_NAND

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-01 20:45:26 -04:00
Adam Ford
fc760cc6e8 Convert CONFIG_SYS_I2C_BUS_MAX to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_I2C_BUS_MAX

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
[trini: Fix AM43XX drop AM44XX]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-01 20:44:30 -04:00
Adam Ford
ac1d8ac871 Configs: Migrate I2C_BUS_MAX to CONFIG_SYS_I2C_BUS_MAX
For consistency with other platforms and in preparation of Kconfig
migration, let's change Several TI platforms that use I2C_BUS_MAX
to CONFIG_SYS_I2C_BUS_MAX

Signed-off-by: Adam Ford <aford173@gmail.com>
2017-09-01 17:56:20 -04:00
Tom Rini
48f6232e58 Kconfig: Migrate all of cmd/fastboot/Kconfig to defconfigs
- Move ANDROID_IMAGE_SUPPORT to top level Kconfig under images as it's
  not strictly part of fastboot.
- Add some defaults for the fastboot buffer location and size
- Migrate all options listed in cmd/fastboot/Kconfig
- Cleanup the README

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-01 16:18:21 -04:00
Tom Rini
ecad7051b0 configs: Migrate all of the existing USB symbols, except fastboot
This syncs all of the currently Kconfig'd symbols out of the headers and
into the defconfig files.  This has two exceptions, first am335x_evm
needs to be converted to DM in SPL and then it can stop undef'ing
CONFIG_DM_USB.  Leaving this as-is results in a build failure, and
without work, run time failure.  The other case is am43xx_evm.h and in
turn am43xx_evm_usbhost_boot.  The problem here is that we need DWC3 USB
host mode in SPL, but still desire to have gadget mode in U-Boot proper.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-01 16:18:20 -04:00
Tom Rini
9493d05a41 Revert "Merge git://git.denx.de/u-boot-video"
This reverts commit 1d20170467, reversing
changes made to 6aee2ab68c.

The mxc_ipuv3_fb.c changes introduce build failures on some targets.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-01 16:17:17 -04:00
Tom Rini
0b6e5b2c48 Merge git://git.denx.de/u-boot-sunxi 2017-09-01 13:30:19 -04:00
Tom Rini
1d20170467 Merge git://git.denx.de/u-boot-video 2017-09-01 12:57:03 -04:00
Dave Prue
6ff005cf19 sunxi: Fix CONFIG_SUNXI_GMAC references
SUNXI_GMAC was still used to configure the code where as the
same has been renamed and moved to Kconfig in below commit
"sunxi: Move SUNXI_GMAC to Kconfig"
(sha1: 4d43d065db)

Signed-off-by: Dave Prue <dave@prue.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Tested-by: Mark Kettenis <kettenis@openbsd.org>
[Tweek commit message, config_whitelist.txt, build-whitelist.sh]
Signed-off-by: Jagan Teki <jagan@openedev.com>
2017-09-01 20:48:27 +05:30
Tom Rini
6aee2ab68c Merge git://git.denx.de/u-boot-imx
Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	configs/imx6qdl_icore_mmc_defconfig
	configs/imx6qdl_icore_rqs_defconfig
2017-09-01 10:40:59 -04:00
Tom Rini
4109d70293 Merge git://git.denx.de/u-boot-marvell 2017-09-01 10:33:21 -04:00
Tom Rini
e4adc8ed3c Merge git://git.denx.de/u-boot-uniphier
- add {ofnode,dev}_read_resource_byname
- provide DT probe hook to Denali NAND driver
- update clk/reset driver
- update DT
- misc cleanups
2017-09-01 10:32:35 -04:00
Tom Rini
9ec61dbc80 Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2017-09-01 10:31:07 -04:00
Chen-Yu Tsai
8a647fc3ca mmc: sunxi: Only update timing mode bit when enabling new timing mode
When enabling the new mmc timing mode, we inadvertently clear all the
remaining bits in the new timing mode register. The bits cleared
include a default phase delay on the output clock. The BSP kernel
states that the default values are supposed to be used. Clearing them
results in decreased performance or transfer errors on some boards.

Fixes: de9b1771c3 ("mmc: sunxi: Support new mode")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-09-01 19:49:47 +05:30
Jagan Teki
63af4b0ad0 i.MX6Q: icorem6: Add falcon mode
Add Falcon mode support in Engicam i.CoreM6 board.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-08-30 12:18:41 +02:00
Jagan Teki
46668df5d0 i.MX6Q: spl: Fix falcon to use dram_init_banksize
Memory dt node update introduced by spl_fixup_fdt() in below
commit was making DDR configuration in-appropriate
to boot falcon mode. Hence added dram_init_banksize for
explicit assignment of  proper base and size of DDR.

"boot: fdt: Perform arch_fixup_fdt() on the given device tree for falcon boot"
(sha1: 6e7585bb64)

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-08-30 12:18:26 +02:00
Stefan Agner
624da53ca8 imx: remove SATA boot mode for i.MX 6UL and 6ULL
The NXP i.MX 6UL and 6ULL do not support SATA and have no SATA
boot mode, hence remove it from the boot device detecion. This
fixes a build error introduced with 3bd1642d4d ("imx: fix USB
boot mode detection for i.MX 6UL and 6ULL")

Fixes: 3bd1642d4d ("imx: fix USB boot mode detection for i.MX 6UL and 6ULL")
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-30 12:17:53 +02:00
Chris Packham
dbc3e64fd1 ARM: mvebu: add "spi-flash" compatible string
U-boots spi-nor support is currently considered a work in progress. For
now to avoid issues it is necessary to add a "spi-flash" compatible
string. Eventually the "jedec,spi-nor" will be sufficient when the core
U-boot code is updated to support it.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-30 10:03:35 +02:00
Masahiro Yamada
0cc0c544bc ARM: uniphier: enable Denali NAND driver for 64bit SoCs
Now the entry to the NAND driver init can be is controlled by DT;
it should not hurt to compile the driver all the time.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Masahiro Yamada
d8a10e7fac ARM: uniphier: set system bus pinmux for PXs3
The system bus is not enabled by default for NAND, eMMC boot
etc. of PXs3.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Masahiro Yamada
b173c19663 ARM: uniphier: move CONFIG_NAND to defconfig
This imply was added when the option was moved by the moveconfig tool,
but the intention is not clear.  Move it to defconfig.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Masahiro Yamada
31c86aa7fd ARM: dts: uniphier: update PXs3 SoC/board DT
Support PXs3 SoC and its reference development board.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Masahiro Yamada
6c9e46efae ARM: dts: uniphier: sync with Linux
Import updates queued up for Linux 4.14-rc1.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Masahiro Yamada
111689e744 reset: uniphier: add PXs3 support
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Masahiro Yamada
1fc84d6be2 reset: uniphier: fix compatible for SD reset node for LD11/LD20
LD20 has SD ctrl instead of MIO ctrl.  LD11 has both of them.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Masahiro Yamada
d7505752bb clk: uniphier: add System clock support
Support system clocks for LD4, Pro4, sLD8, Pro5, PXs2/LD6b, LD11, LD20.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Dai Okamura
4013bbb1f3 ARM: uniphier: fix DSPLL init code for LD20 SoC
Signed-off-by: Dai Okamura <okamura.dai@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Masahiro Yamada
e0daca7de5 ARM: uniphier: remove ad-hoc pin settings for NAND
This is now set up by the pinctrl driver when the NAND driver is
probed.  Remove the legacy code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:06:57 +09:00
Masahiro Yamada
e2f87de0f8 ARM: uniphier: enable CONFIG_NAND_DENALI_DT
Migrate to the DT-based NAND init entry.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:03:11 +09:00
Masahiro Yamada
8de11a5eef ARM: uniphier: remove unneeded NAND config options
CONFIG_NAND_DENALI select's CONFIG_SYS_NAND_SELF_INIT, so the
NAND initialization process is driven by the driver itself.
CONFIG_SYS_NAND_MAX_CHIPS and CONFIG_SYS_NAND_BASE are unused.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:03:11 +09:00
Masahiro Yamada
4914a68de7 ARM: uniphier: add PLL settings for PXs3
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:03:11 +09:00
Masahiro Yamada
a55957b9ad ARM: uniphier: move PLLCTRL register macros to each SoC .c file
The new SoC PXs3 changed the address of PLL, but still uses the
same PLL name.  We can not define SC_*PLLCTRL in the common header.
Move them to per-SoC .c file.  Also, fix some PLL comments.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:03:11 +09:00
Masahiro Yamada
546197b986 ARM: uniphier: replace <common.h> with <linux/delay.h> in pll settings
The #include <common.h> was added for mdelay().  Later, the declaration
of mdelay was moved to <linux/delay.h> by commit 5bc516ed66 ("delay:
collect {m, n, u}delay declarations to include/linux/delay.h").

There is no need to include <common.h> now.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:03:11 +09:00
Masahiro Yamada
1d9654dc43 mtd: nand: denali_dt: add a DT driver
A patch for NAND uclass support was proposed about half a year ago:
https://patchwork.ozlabs.org/patch/722282/

It was not merged and I do not see on-going work for this.

Without DM-based probing, we need to set up pinctrl etc. in an ad-hoc
way and give lots of crappy CONFIG options for base addresses and
properties, which are supposed to be specified by DT.  This is painful.

This commit just provides a probe hook to retrieve "reg" from DT and
allocate private data in a DM manner.  This DT driver is not essentially
a NAND driver, in fact it is (ab)using UCLASS_MISC.  Once UCLASS_NAND is
supported, it would be possible to migrate to it.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:03:11 +09:00
Masahiro Yamada
7b8b47bd29 ofnode: add {ofnode, dev}_read_resource_byname()
Linux supports platform_get_resource_byname() to look up a resource
by name.

We want a similar helper.  It is useful when a device node has named
register regions.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-29 23:56:17 +09:00
Anatolij Gustschin
0d1ae97c02 video: ipuv3_fb: skip IPU shutdown if IPU was not enabled before
Boards can skip display interface init using board_video_skip().
If display interface was not initialized (e.g. no ipuv3 framebuffer
registered or IPU clock disabled), booting Linux stops due to the
crash in IPU shutdown function, when accessing IPU registers.
Check IPU clock and skip shutdown if clock is not enabled.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-08-29 15:23:55 +02:00
Jagan Teki
a2b137b38d icorem6: Fix to find MMC devices
U-Boot proper is using DM_MMC so, enable CONFIG_BLK otherwise
find_mmc_device failed to detect MMC device.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-08-29 09:50:40 +02:00
Anatolij Gustschin
ffc36f57bc imx6: don't include unneeded boot_mode array in SPL
The soc_boot_modes array is only used by bmode command
and not needed in SPL. Don't include it into SPL.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-08-29 09:49:51 +02:00
Anatolij Gustschin
f9d42d821c spl: do not repeat timer init on i.MX6
The GPT timer was already initialised in board_init_f() as
it is needed in dram init. Do not repeat timer init in
board_init_r().

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2017-08-29 09:48:37 +02:00
Anatolij Gustschin
ae64226dbe imx: timer: don't clear the GPT control register multiple times
There is no need to clear the control register 100 times in a
loop, a single zero write clears the register. I didn't find any
justification why clearing this register in a loop is needed
(no info in i.MX6 errata or GPT timer linux driver, linux driver
uses single write to clear this control register).

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2017-08-29 09:47:28 +02:00
Stefano Babic
cb40adff8f pfla02: Fix RAM detection and support 1 bank SOM
In case of 2 banks, the address space of the first CS must be defined
and not let to the higher value.

Add support for SOM with a single bank of RAM. It was tested with i.MX6Q
modules in the following configurations:

- 2 Banks, 4 GB
- 2 Banks, 1 GB
- 1 Bank,  1 GB

Signed-off-by: Stefano Babic <sbabic@denx.de>
2017-08-29 09:46:32 +02:00
Tom Rini
c92ccdd4dc Prepare v2017.09-rc3
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-28 22:42:44 -04:00
Tom Rini
95431aa54c Merge branch 'master' of git://git.denx.de/u-boot-usb 2017-08-28 22:42:12 -04:00
Niko Mauno
22aa21dba4 splash_source: Verify FIT magic
Before reading entire FIT image, add sanity check by testing image
header against FDT_MAGIC. This should help avoid problems in situations
where FIT is not yet available from storage device, for example when
performing initial programming of device.

Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: Tomas Melin <tomas.melin@vaisala.com>
2017-08-29 00:20:16 +02:00
Masahiro Yamada
6ea247d137 usb: dwc3: fix Kconfig dependency to accept host driver in drivers/usb/dwc3
We see the choice of USB_DWC3_HOST / _GADGET in drivers/usb/dwc3/Kconfig,
but we can not choose USB_DWC3_HOST unless USB_GADGET is defined.
This is strange.

Loosen the "depends on" and also move "select USB_GADGET_DUALSPEED" to
the correct place.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-28 22:32:34 +02:00
Maxime Ripard
ead3697d7e mmc: sunxi: fix legacy MMC initialisation
The driver-model rework changed, among other things, the way the private
data were moved around. It now uses the private field in the struct mmc.

However, the mmc_create argument was changed in the process to always pass
the array we used to have to store our private structures.

The basically means that all the MMC driver instances will now have the
private data of the first instance, which obviously doesn't work very well.

Pass the proper pointer to mmc_create.

Fixes: 034e226bc7 ("dm: mmc: sunxi: Pass private data around explicitly")
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-28 22:38:05 +05:30
Jagan Teki
c9319b3f20 sunxi: bpi-m3: Enable eMMC
Add CONFIG_MMC_SUNXI_SLOT_EXTRA=2 to use eMMC on
BPI_M3 board.

Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-08-28 22:36:52 +05:30
Maxime Ripard
343ff16106 sunxi: Enable MMC new mode for A83T
The eMMC controller for the A83T uses the new operating mode. Enable it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-28 22:36:48 +05:30
Maxime Ripard
de9b1771c3 mmc: sunxi: Support new mode
Almost all of the newer Allwinner SoCs have a new operating mode for the
eMMC clocks that needs to be enabled in both the clock and the MMC
controller.

Details about that mode are sparse, and the name itself (new mode vs old
mode) doesn't give much details, but it seems that the it changes the
sampling of the MMC clock. One side effect is also that it divides the
parent clock rate by 2.

Add support for it through a Kconfig option.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-28 22:36:44 +05:30
Hannes Schmelzer
a223e2bc10 bootvx_fdt: fix missing 'fdt_fixup_ethernet(...)' on vxWorks boot
Before commit 26d6119 (fdt: Move fdt_fixup_ethernet to a common place)
the fdt_fixup_ethernet(...) was called during do_bootvx_fdt(...).

Afterwards the only (common) place for this fixup is during
image_setup_libfdt(...) and this is only called, at least on ARM
platform, from image_setup_linux(...).

All this ends up in the fact, that the fdt_fixup_ethernet(...) is only
called on booting a linux image and not on booting a vxWorks image.

We fix this with adding the fdt_fixup_ethernet(...) call again to
do_bootvx_fdt(...)

Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:19:13 -04:00
Wilson Lee
5daf6e56d3 common: console: Fix duplicated CONFIG in silent env callback
The silent environment callback function does not update the silent
flag during silent env set or unset. That is because of duplicated
CONFIG keyword at preprocessor condition in silent environment
callback function and cause silent env callback unable to work.

This patch is to remove the duplicated CONFIG keywork in silent
environment callback function.

Signed-off-by: Wilson Lee <wilson.lee@ni.com>
Cc: Keng Soon Cheah <keng.soon.cheah@ni.com>
Cc: Chen Yee Chew <chen.yee.chew@ni.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2017-08-28 07:19:12 -04:00
Bin Meng
dd027dde75 sandbox: Enable NVMe driver for build testing
This enables NVMe driver on sandbox for build testing.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:17 -04:00
Bin Meng
0d1414bd97 sandbox: Add a dummy invalidate_dcache_range() function
This adds invalidate_dcache_range() so that some drivers can build
without error on sandbox.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:16 -04:00
Bin Meng
fceadc1459 nvme: Adjust the 'nvme' command to use blk_common_cmd()
Instead of having separate code in the 'nvme' command, adjust it to use
the common function.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:15 -04:00
Bin Meng
18aa5a4134 nvme: Get rid of the global variable nvme_info
At present the NVMe uclass driver uses a global variable nvme_info
to store global information like namespace id, and NVMe controller
driver's priv struct has a blk_dev_start that is used to calculate
the namespace id based on the global information from nvme_info.

This is not a good design in the DM world and can be replaced with
the following changes:

- Encode the namespace id in the NVMe block device name during
  the NVMe uclass post probe
- Extract the namespace id from the device name during the NVMe
  block device probe
- Let BLK uclass calculate the devnum for us by passing -1 to
  blk_create_devicef() as the devnum

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:14 -04:00
Bin Meng
d5b7ee9c6e nvme: Use blk_create_devicef() API
The codes in nvme_uclass_post_probe() can be replaced to call the
blk_create_devicef() API directly.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:14 -04:00
Bin Meng
704e040a51 nvme: Apply cache operations on the DMA buffers
So far cache operations are only applied on the submission queue and
completion queue, but they are missing in other places like identify
and block read/write routines.

In order to correctly operate on the caches, the DMA buffer passed
to identify routine must be allocated properly on the stack with the
existing macro ALLOC_CACHE_ALIGN_BUFFER().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:13 -04:00
Bin Meng
625a483cea nvme: Consolidate block read and write routines
The NVMe block read and write routines are almost the same except
the command opcode. Let's consolidate them to avoid duplication.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:13 -04:00
Bin Meng
722e668db2 nvme: Use macros to access NVMe queues
NVMe driver only uses two queues. The first one is allocated to do
admin stuff, while the second one is for IO stuff. So far the driver
uses magic number (0/1) to access them. Change to use macros.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:12 -04:00
Bin Meng
04d2a38401 nvme: Respect timeout when en/disabling the controller
So far the driver unconditionally delays 10ms when en/disabling the
controller and still return 0 if 10ms times out. In fact, spec defines
a timeout value in the CAP register that is the worst case time that
host software shall wait for the controller to become ready.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:12 -04:00
Bin Meng
b65c692143 nvme: Cache controller's capabilities
Capabilities register is RO and accessed at various places in the
driver. Let's cache it in the controller driver's priv struct.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:11 -04:00
Bin Meng
3e18562961 nvme: Fix endianness assignment to prp2 in nvme_identify()
So far this is not causing any issue due to NVMe and x86 are using
the same endianness, but for correctness, it should be fixed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:11 -04:00
Bin Meng
099c2015b0 nvme: Fix ndev->queues allocation
ndev->queues is a pointer to pointer, but the allocation wrongly
requests sizeof(struct nvme_queue). Fix it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:11 -04:00
Bin Meng
e5dc2d2665 nvme: Fix getting PCI vendor id of the NVMe block device
The codes currently try to read PCI vendor id of the NVMe block
device by dm_pci_read_config16() with its parameter set as its
root complex controller (ndev->pdev) instead of itself. This is
seriously wrong. We can read the vendor id by passing the correct
udevice parameter to the dm_pci_read_config16() API, however there
is a shortcut by reading the cached vendor id from the PCI device's
struct pci_child_platdata.

While we are here fixing this bug, apparently the quirk stuff handle
codes in nvme_get_info_from_identify() never takes effect since its
logic has never been true at all. Remove these codes completely.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:10 -04:00
Bin Meng
abe25db611 nvme: Remove useless defines
These are leftover when the driver was ported from Linux and are not
used by the U-Boot driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:10 -04:00
Tom Rini
5dc4dfd2a9 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-28 07:16:32 -04:00
Breno Lima
3aa4b703b4 imx: imx6: Move gpr_init() function to soc.c
Since the gpr_init() function is common for boards using MX6S, MX6DL, MX6D,
MX6Q and MX6QP processors move it to the soc.c file.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-08-28 09:48:53 +02:00
Tom Rini
34f98a3d2e sh: Fix linking of ms7722se
While it is true that we no longer have 'ppcenv' and similar sections,
including env/embedded.o at all results in the text/etc sections being
available for the rest of the link.  This in turn is required for the
setup used on ms7722se.  This also, likely, needs further fine-tuning.

Fixes: f40ad66fa0 ("arch/sh: don't bring common/env_embedded.o into the link")
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-27 11:50:16 -04:00
Tom Rini
c3b572c4e2 cmd/spl.c: Include <libfdt.h> for fdt_totalsize
In order to be able to reliably use fdt_totalsize, we must have
<libfdt.h> included.

Fixes: 767cb74a00 ("cmd: spl: provide address and size of prepared FDT ...")
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-26 21:17:05 -04:00
Tom Rini
8b3cec7da1 mtdparts: Fix uninitialized scalar usage
When reworking this code to fix other issues found by Coverity, I forgot
to ensure tmp_ep was always cleared before use.

Reported-by: Coverity (CID: 166612)
Fixes: bc028345ac ("mtdparts: Fix final outstanding issue reported by Coverity")
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-26 16:59:24 -04:00
Tom Rini
bd95e655b2 Merge git://git.denx.de/u-boot-sh 2017-08-26 15:10:49 -04:00
Tom Rini
f72b96ec8f Merge branch 'rmobile' of git://git.denx.de/u-boot-sh 2017-08-26 15:10:46 -04:00
Tom Rini
0031af9ce7 Merge git://git.denx.de/u-boot-x86 2017-08-26 15:10:40 -04:00
Tom Rini
cc0427d269 Merge git://git.denx.de/u-boot-i2c 2017-08-26 15:10:38 -04:00
Tom Rini
c2150e4dc1 Merge git://www.denx.de/git/u-boot-cfi-flash 2017-08-26 15:10:35 -04:00
Stefan Agner
5c27535dc9 disk: part: align buffer so it can be used with DMA enabled drivers
When using ISO partitions with a DMA enabled block device driver
reading the ISO partition leads to unaligned DMA operations:
  CACHE: Misaligned operation at range [bffb7da8, bffb85a8]

Align the buffer to make sure we pass a buffer which works for
DMA operations.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-26 14:56:15 -04:00
Stephen Boyd
527d86558e scripts: objdiff: Ignore debug info when comparing
If the kernel is configured to be built with debug symbols, or
has bug tables, comparing files may not work if line numbers
change. This makes comparing object files with these options
harder to do. Let's strip out the debug info and drop the
__bug_table here so that we don't see false positives. There may
be other things to drop later, and it may be architecture
specific, but this works for me with my ARM64 build.

[ Import Linux commit: 65ba6fa439e7c3cbf97de9dce9e7a3390ae2638c ]

Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Reviewed-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-26 14:56:14 -04:00
Masahiro Yamada
e43f74ac0b doc: verified-boot: fix typos
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-26 14:56:14 -04:00
Tom Rini
10b078d836 fs: ext4: Fix journal overrun issue reported by Coverity
While &p_jdb[fs->blksz] is a valid expression (it points *one* char
sized element past the end of the array, e.g. &p_jdb[fs->blksz + 1] is
invalid (according to the C standard (C99/C11)).

Changing this to tag = (struct ext3_journal_block_tag *)(p_jdb + ofs);

Cc: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Suggested-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Reported-by: Coverity (CID: 165117, 165110)
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
2017-08-26 14:56:13 -04:00
Tom Rini
bc028345ac mtdparts: Fix final outstanding issue reported by Coverity
As part of fixing the previously reported issues, it was missed that in
the case of mtdparts_init() we need to make sure that tmp_ep is long
enough to contain PARTITION_MAXLEN and a NULL termination.  Then, to be
sure the buffer is NULL terminated, zero the entire buffer rather than
just ensuring the first character is NULL.

Cc: Lothar Waßmann <LW@KARO-electronics.de>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Reported-by: Coverity (CID: 166329)
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-26 14:56:13 -04:00
Vikas Manocha
1e87f9ced4 spl: stm32: make falcon mode activation configurable
With this change, it will be possible to de-select falcon mode & spl
will only boot U-Boot.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Suggested-by: Bo Shen <voice.shen@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-26 14:56:13 -04:00
Anatolij Gustschin
767cb74a00 cmd: spl: provide address and size of prepared FDT in environment
Writing prepared FDT to persistent storage should be possible in
scripts. Create environment variables containing address and size
of the updated FDT. Scripts can use these variables after running
'spl export fdt ...' command to write the new blob to persistent
storage.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-08-26 14:56:12 -04:00
Pau Pajuelo
195dc23185 igep00x0: merge igep0020 and igep0030 defconfigs to igep00x0_defconfig
Update igep00x0 code with the following features:
- Add board and revision detection for the boards:
  - IGEP0020-RF
  - IGEP0020-RC
  - IGEP0030-RG
  - IGEP0030-RE
- Merge IGEP0020 and IGEP0030 mux tables
- Add suport to use GPIO_126, GPIO_127 and GPIO_129
- board_name and board_rev environment variables display board and
  revision informations
- Move dtb name selection from code to boot script

Signed-off-by: Pau Pajuelo <ppajuel@gmail.com>
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tested-by: Pau Pajuelo <ppajuel@gmail.com>
2017-08-26 14:56:12 -04:00
Ladislav Michl
4c699a4747 igep00x0: move SPL routines into separate file
Avoid cluttering board file with CONFIG_SPL_BUILD ifdefs
by moving SPL related functions into separate file.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tested-by: Pau Pajuelo <ppajuel@gmail.com>
Acked-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
2017-08-26 14:56:12 -04:00
Semen Protsenko
ea8c7fcacc arm: dra7xx: Define Android boot arguments
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
2017-08-26 14:56:11 -04:00
Semen Protsenko
49c7d0ac14 arm: am57xx: Define Android boot arguments
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
2017-08-26 14:56:11 -04:00
Semen Protsenko
a17c8b1844 arm: omap: Define command for booting Android from eMMC
If SD card is present -- try to boot from it first. If no -- try to boot
Android from eMMC.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
2017-08-26 14:56:11 -04:00
Ruchika Gupta
a797f274d7 ARMv8/sec_firmware : Update chosen/kaslr-seed with random number
kASLR support in kernel requires a random number to be passed via
chosen/kaslr-seed propert. sec_firmware generates this random seed
which can then be passed in the device tree node.

sec_firmware reserves JR3 for it's own usage. Node for JR3 is
removed from device-tree.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
2017-08-26 14:56:11 -04:00
Thomas Petazzoni
225bfd3906 arch/arm/cpu/arm926ejs/spear/cpu.c: guard do_switch_ecc() with CONFIG_NAND_FSMC
do_switch_ecc() calls fsmc_nand_switch_ecc(), which is a direct
function call into drivers/mtd/nand/fsmc_nand.c. However, this
function is not guarded by CONFIG_NAND_FSMC, which results to a build
failure if CONFIG_NAND_FSMC is disabled.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2017-08-26 14:56:10 -04:00
Thomas Petazzoni
c25c4fd010 board/spear/common: move code to arch/arm/cpu/arm926ejs/spear/
The code in board/spear/common/ is not board-specific but
SoC-specific. Therefore, boards from other vendors than "spear" may
want to re-use this code, which is currently difficult with the code
being placed in board/spear/common/.

Since this code really is SoC-specific, this commit moves it to
arch/arm/cpu/arm926ejs/spear/, with the rest of the SPEAr related
code.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2017-08-26 14:56:10 -04:00
Wenyou.Yang@microchip.com
fc6adebbc1 board: atmel: Use the new PIT timer driver
Use the Atmel PIT timer driver which supports the driver model
and device tree.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-08-26 14:56:09 -04:00
Wenyou.Yang@microchip.com
47edaea494 driver: timer: Add the Atmel PIT timer driver
Add the new Atmel PIT timer driver, which supports the driver model
and device tree.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-08-26 14:56:08 -04:00
Tom Rini
deff9b1d2a powerpc: Rework interrupt_init_cpu()
The function interrupt_init_cpu() is given an int return type but does
not return anything but 0.  Rework this to be a void function.

Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Mario Six <mario.six@gdsys.cc>
2017-08-26 14:56:08 -04:00
Reno Farnesi
76216211f8 fs: fat: fix fatwrite overflow calculation
The overflow calculation was incorrect. Adding the start block of the
partition is not needed because the sectors are already relative to the
beginning of the partition. If you attempted to write a file smaller
than cur_part_info.start blocks on a full partition the old calculation
fails to catch the overflow. This would cause an infinite loop in the
determine_fatent function.

Old, incorrect calculation:

ending sector of new file = start sector + file size (in sectors)
last sector = partition start + total sectors on the partition

Adding the partition start block number is not needed because sectors
are already relative to the start of the partition.

New calculation:

ending sector of new file = start sector + file size (in sectors)
last sector = total sectors on the partition

Signed-off-by: Reno Farnesi <nfarnesi4@gmail.com>
2017-08-26 14:56:07 -04:00
Suniel Mahesh
528f2b66dc arm: dts: am33xx: sync DTS with Linux 4.13-rc4
This re-syncs AM33xx DTS file with current file from
Linux v4.13-rc4 to ensure a consistent configuration. Upstream
Linux removed the redundant Interrupt-parent property from mmc,
mac, lcdc and tscadc sub nodes.

Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-26 14:56:07 -04:00
Jagan Teki
93fd5b0ac1 ram: kconfig: s/SPL/TPL/ in TPL_RAM help text
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-08-26 14:56:06 -04:00
Simon Glass
e5ec12bbe1 rpi: Enable USB keyboard support
This is currently disabled, so USB keyboards are not detected in U-Boot.
Enable this option to fix that.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Paul Barker <pbarker@toganlabs.com>
2017-08-26 14:55:49 -04:00
Thomas Petazzoni
f40ad66fa0 arch/sh: don't bring common/env_embedded.o into the link
The linker script for SuperH brings the .ppcenv and .ppcenvr section
of common/env_embedded.o into the .text section. However, the .ppcenv
section is only ever filled in by env_embedded.o when
CONFIG_SYS_USE_PPCENV is defined, but no platforms in mainline U-Boot
use this.

In addition, common/env_embedded.o is not always built (when you use
CONFIG_ENV_IS_NOWHERE for example), which causes the following build
failure:

Fixes:

  LD      u-boot
/home/thomas/sh4aeb-linux-musl/bin/sh4aeb-linux-ld.bfd: cannot find common/env_embedded.o

We fix this by no longer adding the .ppcenv and .ppcenvr sections from
common/env_embedded.o into the .text section.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:40:36 +09:00
Thomas Petazzoni
90340c87e5 arch/sh: allow building in big-endian mode
The SuperH architecture allows to be run in either little or big
endian mode. Some SuperH SoCs get the little vs. big endian decision
through mode pins sampled at reset, so if big endian has been choosen
by HW designers, it cannot be easily changed.

Therefore, it makes sense to allow building U-Boot for SuperH in big
endian mode. To allow this, the only change needed is to adjust the
OUTPUT_FORMAT() in the linker script.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2017-08-26 07:38:39 +09:00
Marek Vasut
f7f79b4493 ARM: rmobile: Enable MMC and USB DM on ULCB
Enable the MMC and USB DM on the board since it's the modern method
and now supported by the drivers.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
3345ca21a1 ARM: rmobile: Enable MMC and USB DM on Salvator-X
Enable the MMC and USB DM on the board since it's the modern method
and now supported by the drivers.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
6f38085492 ARM: rmobile: Remove SH SDHI probing from ULCB board
Drop the SH SDHI bit from the board since SD now probes from DT instead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
ddb39a075b ARM: rmobile: Remove SH SDHI probing from Salvator-X board
Drop the SH SDHI bit from the board since SD now probes from DT instead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
3f63551471 ARM: rmobile: Remove Serial SH probing from ULCB board
Drop the Serial SH bit from the board since UART now probes from DT instead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
1c30aea5b1 ARM: rmobile: Remove Serial SH probing from Salvator-X board
Drop the Serial SH bit from the board since UART now probes from DT instead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
75ba2bf99f ARM: rmobile: Remove RAVB probing from ULCB board
Drop the RAVB bit from the board since RAVB now probes from DT instead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
a88026c51d ARM: rmobile: Remove RAVB probing from Salvator-X board
Drop the RAVB bit from the board since RAVB now probes from DT instead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
d47f356cde ARM: rmobile: Enable HUSH parser
The HUSH parser was disabled somewhere along the way, reenable it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alexandru Gagniuc <alex.g@adaptrum.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
c4464e163e ARM: rmobile: Enable KSZ90X1 PHY on Salvator-X
Commit da3b9e7fd6 (Move PHY_MICREL and PHY_MICREL_KSZ90X1 to Kconfig)
broke ethernet support on R8A779x Salvator-X boards by disabling the
KSZ90x1 PHY in Kconfig. Reenable it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alexandru Gagniuc <alex.g@adaptrum.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
46933dfbe1 ARM: rmobile: Add u-boot, dm-pre-reloc to clock nodes on Gen3
We need the clock available very early, add the u-boot,dm-pre-reloc
DT property on those nodes, so they come up very in the process.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
fd8692b8ff clk: rmobile: Split R8A7795 and R8A7796 core clock tables
The R8A7795 and R8A7796 tables use different constants to identify
clock in DT, so split the tables and use the correct constants on
R8A7795. This fixes UART clock misconfiguration on R8A7795.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Stefan Agner
962c78b1df imx: use BOOT_DEVICE_BOARD instead of UART
i.MX 6 serial downloader is not necessarily booting via UART but can
also boot from USB. In fact only some i.MX chips have serial
downloader support via UART (e.g. 6UL/ULL and Vybrid) but all of
them have serial downloader support via USB. Use the more appropriate
BOOT_DEVICE_BOARD define which is used for ROM provided recovery
mechanisms in general.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2017-08-25 13:31:47 +02:00
Stefan Agner
3bd1642d4d imx: fix USB boot mode detection for i.MX 6UL and 6ULL
Add the reserved boot mode used in the bmode command for i.MX 6UL
and 6ULL as introduced in commit 3fd9579085 ("imx: mx6ull: fix USB
bmode for i.MX 6UL and 6ULL").

Also replace BMODE_UART with BMODE_RESERVED, which is more appropriate.
Commit 96aac843b6 ("imx: Use IMX6_BMODE_* macros instead of numericals")
added macros for boot modes, in the process the reserved boot mode got
named BMODE_UART. We use the reserved boot mode in the bmode command to
let the boot ROM enter serial downloader recovery mode. But this is only
a side effect, the actual boot mode is reserved...

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2017-08-25 13:31:31 +02:00
Bin Meng
438505fe69 x86: tangier: kconfig: Guard tangier-specific options
These options should not be exposed to other platforms.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2017-08-24 11:00:47 +08:00
Bin Meng
207d532bef x86: bayleybay: Adjust VGA rom address
Adjust VGA rom address to 0xfffb0000 so that u-boot.rom image can be
built again.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-24 11:00:47 +08:00
Bin Meng
81c727d86c x86: baytrail: Fix turbo enable
CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED must be turned on for Baytrail.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-24 11:00:47 +08:00
Bin Meng
2ddb1a177a x86: Convert CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED to Kconfig
This converts CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED to a Kconfig option.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-24 11:00:47 +08:00
Stefan Roese
5091a8b04d x86: dfi-bt700: Select SERIAL_RX_BUFFER via Kconfig
To support more input characters (longer stings pasted into the U-Boot
prompt) without dropping, lets selects the recently added UART RX
buffer for these boards.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-24 11:00:47 +08:00
Stefan Roese
b48dcd3751 x86: conga-qeval20-qa3-e3845: Select SERIAL_RX_BUFFER via Kconfig
To support more input characters (longer stings pasted into the U-Boot
prompt) without dropping, lets selects the recently added UART RX
buffer for these boards.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-24 11:00:47 +08:00
Stefan Roese
3ca7a06afb serial: serial-uclass: Add generic serial RX buffer support
Pasting longer lines into the U-Boot console prompt sometimes leads to
characters missing. One problem here is the small 16-byte FIFO of the
legacy NS16550 UART, e.g. on x86 platforms.

This patch now introduces a Kconfig option to enable RX buffer support
for all DM based serial drivers. With this option enabled, I was
able paste really long lines into the U-Boot console, without any
characters missing.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-24 11:00:47 +08:00
Stefan Roese
7fded0ce0f Revert "serial: ns16550: Add RX interrupt buffer support"
This reverts commit 6822cf3ec7.

As Bin Meng has tested and pointed out, we don't need the RX interrupt
for the RX buffer support at all. Just reading all available characters
into a buffer is sufficient to solve the problem with the dropped
characters upon long lines pasted into the U-Boot prompt. Since this
RX buffer support can be implemented in a generic way, without any
device specifica (e.g. for the ns16550), I'll post a new patch with
a new serial RX buffer support for DM, which all DM based serial
drivers can use.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-24 11:00:47 +08:00
Bin Meng
76e726502e vbe: Drop vbe_get_video_info()
With DM video, this is not used any more. Drop it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-24 11:00:47 +08:00
Bin Meng
c11b17c6bf x86: kconfig: Imply CMD_PCI
Let's imply the 'pci' command to access the de facto interconnect
bus in an x86 system.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24 11:00:47 +08:00
Bin Meng
1e6ebee667 x86: fsp: Configure SPI opcode registers before SPI is locked down
Some Intel FSP (like Braswell) does SPI lock-down during the call
to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done,
it's bootloader's responsibility to configure the SPI controller's
opcode registers properly otherwise SPI controller driver doesn't
know how to communicate with the SPI flash device.

This introduces a Kconfig option CONFIG_FSP_LOCKDOWN_SPI for such
FSPs. When it is on, U-Boot will configure the SPI opcode registers
before the lock-down.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24 11:00:47 +08:00
Bin Meng
b42711f90c x86: ich-spi: Move opcode registers configuration to another routine
At present the ICH SPI opcode registers configuration is done in the
ich_spi_remove() routine, a little bit weird but that's how current.
Linux MTD driver works. This changes to move the opcode registers
configuration to a separate routine ich_spi_config_opcode() which
might be called by U-Boot itself as well.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24 11:00:47 +08:00
Bin Meng
3e79141684 x86: ich-spi: Don't read cached lock status
At present the ICH SPI controller driver reads the controller lock
status from its register in the probe routine and saves the lock
status to a member of priv. Later the driver uses the cached status
from priv to judge whether the controller setting is locked and do
different setup.

But such logic is only valid when there is only the SPI controller
driver that touches the SPI hardware. In fact the lock status change
can be trigged outside the driver, eg: during the fsp_notify() call
when Intel FSP is used.

This changes the driver to read the lock status every time when an
SPI transfer is initiated instead of reading the cached one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24 11:00:47 +08:00
Bin Meng
7d82978927 x86: ich-spi: Remove unnecessary assignment in ich_init_controller()
There is no need to do another assignment to ich7_spi.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24 11:00:47 +08:00
Bin Meng
94bc9177ca x86: ich-spi: Remove spi_write_protect_region()
This routine is not called anywhere.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24 11:00:47 +08:00
Peng Fan
7a7bfec39e pinctrl: imx7ulp: Add new info instance for iomuxc1
To i.MX7ULP, we need to create two info instances for
iomux0 and iomux1 respectively, otherwise iomuxc0/1 will
share one info instance and use one base, because imx_pinctrl_probe
will use info to store base address and etc. But iomuxc0/1
actually have different base address.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
2017-08-23 10:48:15 +02:00
Peng Fan
63fbc59b4f pinctrl: imx: Fix mask when SHARE_MUX_CONF_REG is set
when using SHARE_MUX_CONF_REG, wrong mask is used for
writing config value, which causes mux value is cleared.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
2017-08-23 10:47:00 +02:00
Stefano Babic
7c09cbf68b imx: fix licensing in i.MX files
Some files for i.MX do not yet have the SPDX ID to reference the correct
license.

Signed-off-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Wolfgang Denk <wd@denx.de>
2017-08-23 10:45:45 +02:00
Peng Fan
fa85b0217d imx: mx7: psci: add copyright and license
Add copyright and license header.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2017-08-23 10:45:25 +02:00
Stefan Agner
f0e0698cee apalis/colibri_imx6: enable SDP by default
Enable Serial Download Protocol (SDP) in SPL and U-Boot. This is
useful to make use of imx_usb to download the complete U-Boot
(u-boot.img) after SPL has been downloaded. The U-Boot command
sdp allows to enumerate as SDP capable device again, e.g. to
download a Linux kernel and/or U-Boot script.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
2017-08-23 10:41:58 +02:00
Stefan Agner
2b2f678280 apalis/colibri_imx6: use independent USB PID for SPL
Use a completely independent USB Product ID for SPL. This allows
to differentiate a SDP running in SPL and SDP running in a U-Boot
which could not read the config block successfully.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
2017-08-23 10:41:58 +02:00
Stefan Agner
f9c39d95f1 doc: add Serial Download Protocol documentation
Document the U-Boot Serial Download Protocol implementation and
some typical use cases.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
2017-08-23 10:41:58 +02:00
Stefan Agner
a3774c1c3c spl: add serial download protocol (SDP) support
Add USB serial download protocol support to SPL. If the SoC started
in recovery mode the SPL will immediately switch to SDP and wait for
further downloads/commands from the host side.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
2017-08-23 10:41:58 +02:00
Stefan Agner
2f005695df cmd: add sdp command
Add a new command to start USB Serial Download Protocol (SDP)
state machine.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-08-23 10:41:58 +02:00
Stefan Agner
ccd7a4d2f4 usb: gadget: sdp: extend images compatible for jumps
Support U-Boot images in SPL so that u-boot.img files can be
directly downloaded and executed. Furthermore support U-Boot
scripts download and execution in full U-Boot so that custom
recovery actions can be downloaded from the host in a third
step.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-08-23 10:41:58 +02:00
Stefan Agner
5661f08a71 usb: gadget: add SDP driver
Add SDP (Serial Downloader Protocol) implementation for U-Boot. The
protocol is used in NXP SoC's boot ROM and allows to download program
images. Beside that, it can also be used to read/write registers and
download complete Device Configuration Data (DCD) sets. This basic
implementation supports downloading images with the imx header format
reading and writing registers.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
2017-08-23 10:41:58 +02:00
Stefan Agner
4e76c0774a imx: move imximage header to common location
Move the imximage.h header file to a common location so we can make
use of it from U-Boot too.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
2017-08-23 10:41:58 +02:00
Peng Fan
a430556ecb i2c: muxes: add i2c gpio multiplexer driver
Add an i2c mux driver providing access to i2c bus segments using a
hardware MUX sitting on a master bus and controlled through gpio pins.

E.G. something like:

         ----------              ----------  Bus segment 1   - - - - -
        |          | SCL/SDA    |          |-------------- |           |
        |          |------------|          |
        |          |            |          | Bus segment 2 |           |
        |  Linux   | GPIO 1..N  |   MUX    |---------------   Devices
        |          |------------|          |               |           |
        |          |            |          | Bus segment M
        |          |            |          |---------------|           |
         ----------              ----------                  - - - - -

SCL/SDA of the master I2C bus is multiplexed to bus segment 1..M
according to the settings of the GPIO pins 1..N.

Note commit log from kernel
commit 92ed1a76("i2c: Add generic I2C multiplexer using GPIO API")

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Peng Fan <peng.fan@nxp.com> (i.MX6QP-Sabreauto)
Cc: Heiko Schocher <hs@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Simon Glass <sjg@chromium.org>
2017-08-23 07:04:56 +02:00
Patrice Chotard
4fadcaf097 i2c: add i2c driver for stm32
Add i2c driver which can be used on both STM32F7 and STM32H7.
This I2C block supports the following features:
 _ Slave and master modes
 _ Multimaster capability
 _ Standard-mode (up to 100 kHz)
 _ Fast-mode (up to 400 kHz)
 _ Fast-mode Plus (up to 1 MHz)
 _ 7-bit and 10-bit addressing mode
 _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
 _ All 7-bit addresses acknowledge mode
 _ General call
 _ Programmable setup and hold times
 _ Easy to use event management
 _ Optional clock stretching
 _ Software reset

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-23 07:04:40 +02:00
Tom Rini
90ae53ce1a fastboot: Ensure we treat CONFIG_FASTBOOT_BUF_ADDR as long
Otherwise:
drivers/usb/gadget/f_fastboot.c:564:32: warning: format "%lx" expects
argument of type "long unsigned int", but argument 3 has type "unsigned
int" [-Wformat=]

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-22 08:20:02 -04:00
Marek Vasut
236c49a1c8 mtd: cfi: staticize functions
Staticize a few functions and variables which are no longer exposed.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-22 09:56:09 +02:00
Tom Rini
ad8afeaee0 Merge git://www.denx.de/git/u-boot-marvell 2017-08-21 07:17:15 -04:00
Tom Rini
09b6a6dd01 Merge git://git.denx.de/u-boot-usb 2017-08-21 07:16:56 -04:00
Tom Rini
8197d92843 Merge git://git.denx.de/u-boot-uniphier
- Fix unmet direct dependencies warning
 - Remove old sLD3 SoC support
 - Update reset data
 - Add dr_mode DT property to avoid warning
2017-08-21 07:16:16 -04:00
Chris Packham
6ab09b05f3 ARM: mvebu: set correct mem_size for db-88f6820-amc
The db-88f6820-amc has four chips with 2Gb density giving a total of 1GB
DRAM. Update the board_topology_map to reflect the correct
configuration.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-21 11:40:49 +02:00
Lukasz Majewski
5bf4475f1d doc: license: Add license header to the README.dfutftp file
Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-08-21 11:31:11 +02:00
Tom Rini
6bafa5a4bd fb_mmc.c: Correct blk_dread() return value checks
The function blk_dread will return -ENOSYS on failure or on success the
number of blocks read, which must be the number asked to read (otherwise
it failed somewhere).  Correct this check.

Cc: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-21 11:31:11 +02:00
Tom Rini
2341c80cd2 common/fb_mmc.c: Fix warnings about casts
When building the flash zImage code on aarch64 we see warnings about
pointer size casts.  Use uintptr_t instead to correct these.

Cc: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-By: Sam Protsenko <semen.protsenko@linaro.org>
2017-08-21 11:31:10 +02:00
John Keeping
7715dea48b fastboot: avoid printing invalid data
There is no guarantee that commands are null-terminated in the USB
request buffer, so limit the length of data that is printed.

Signed-off-by: John Keeping <john@metanate.com>
Tested-by: Steve Rae <steve.rae@raedomain.com>
2017-08-21 11:31:10 +02:00
Peter Chubb
d331084298 Fix fastboot boot address
Fastboot loads an image at CONFIG_FASTBOOT_BUF_ADDR, but currently
tells do_bootm() to look for an image at $loadaddr.  This breaks if
CONFIG_FASTBOOT_BUF_ADDR is different from the current user-set
loadaddr.

Instead, tell do_bootm() to pick up the image where it was laoded.

Signed-off-by: Peter Chubb <peter.chubb@data61.csiro.au>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Steve Rae <steve.rae@raedomain.com>
2017-08-21 11:31:10 +02:00
Bin Meng
a11a5b8ad9 usb: ehci: Convert CONFIG_USB_EHCI_PCI to Kconfig
This converts CONFIG_USB_EHCI_PCI to a Kconfig option, and updates
all boards that use it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-21 11:30:44 +02:00
Simon Glass
2d7cb5b426 env: Replace all open-coded gd->env_valid values with ENV_ flags
Some of these were missed in the conversion.
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-20 19:27:44 -04:00
Simon Glass
c55d8b9400 env: Allow env_load() to detect errors
Now that we have errors available in the environment driver's load()
method, check the return valid.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-20 19:27:43 -04:00
Tom Rini
eeba55cb4a env: Correct case of no sub-init function
With the change to the environment code to remove the common init stage
of pointing to the default environment and setting it as valid, combined
with the change to switch gd->env_valid from 0/1/2 to an enum we now
must set env_valid to one of the enum values rather than an int.  And in
this case, not only was setting it to an int wrong, it was now the wrong
value.  Finally, in the case of ENV_IS_NOWHERE we must still say that
our envionrment is invalid after init for things to continue to
function.

Fixes: 7938822a6b ("env: Drop common init() functions")
Tested-by: Marek Vasut <marek.vasut@gmail.com>
Reported-by: Marek Vasut <marek.vasut@gmail.com>
Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
Changes in v3:
- Actually include changes for env/nowhere.c
2017-08-20 19:27:28 -04:00
Masahiro Yamada
3444d1d40e ARM: dts: uniphier: add dr_mode property to dwc3 node
Since commit 576e3cc700 ("usb: host: xhci-dwc3: Add dual role mode
support from DT"), warning is displayed if dr_mode is not specified.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-20 23:07:02 +09:00
Masahiro Yamada
6584b1ea10 reset: uniphier: refactor reset data and add NAND/eMMC reset lines
- Merge sys_reset data of LD4, Pro4, sLD8 and Pro5

  - Merge sys_reset data of LD11 and LD20

  - Use primitive UNIPHIER_RESETX() macro because bit assignments for
    system reset will be changed for every SoC in the future

  - Add NAND and eMMC resets

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-20 23:06:20 +09:00
Masahiro Yamada
c5161eee38 Revert "ARM: uniphier: fix ROM boot mode for PH1-sLD3"
This reverts commit 82d075e79f.

Commit 82d075e79f ("ARM: uniphier: fix ROM boot mode for PH1-sLD3")
was a workaround for sLD3.  Now the sLD3 SoC support has been removed.

Revert it to allow to simplify the init code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-20 23:05:39 +09:00
Masahiro Yamada
0aa8b2c3e0 Revert "ARM: uniphier: move lowlevel debug init code after page table switch"
This reverts commit bcc51c1512.

Commit bcc51c1512 ("ARM: uniphier: move lowlevel debug init code
after page table switch") was intended to support lowlevel debug for
sLD3.  Now the sLD3 SoC support has been removed.

Revert it to allow to enable lowlevel debug earlier.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-20 23:05:39 +09:00
Masahiro Yamada
00aa453ebf ARM: uniphier: remove sLD3 SoC support
This SoC is too old.  It is difficult to maintain any longer.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-20 23:05:39 +09:00
Masahiro Yamada
213fcabdfd clk: uniphier: fix unmet direct dependencies warning
Since commit f0776a5517 ("spl: dm: Kconfig: SPL_CLK depends on
SPL_DM"), the following warning is displayed:

  $ make uniphier_v8_defconfig
  warning: (ARCH_ZYNQ && ARCH_ZYNQMP && STM32F7 && CLK_UNIPHIER) selects
  SPL_CLK which has unmet direct dependencies (CLK && SPL_DM)

While I am here, I am removing the prompt to make it user-unconfigurable
option so that "select CLK_UNIPHIER" can be omitted.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-20 23:05:39 +09:00
Anatolij Gustschin
f1a7ba1da5 Fix 'notes' typos
s/notes/nodes

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-08-20 09:54:34 -04:00
Andy Shevchenko
e94c1268f2 env: Sort selection of default choices
It would be easier to catch out which platform is using which default.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2017-08-20 09:54:33 -04:00
Heiko Schocher
79c85f7115 arm, at91: fix taurus board
since commit: b529993e02 "spl: add hierarchical defaults for SPL_LDSCRIPT"

taurus board stopped working. Use the ldscript from
arch/arm/cpu/u-boot-spl.lds (as before this patch) fixed it.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-20 09:54:33 -04:00
Thomas Petazzoni
c1ee8936bf common/board_f.c: remove CONFIG_SYS_GENERIC_GLOBAL_DATA
CONFIG_SYS_GENERIC_GLOBAL_DATA is no longer used by any board or
platform, so support for it can be dropped.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-20 09:54:32 -04:00
Peter Griffin
fb53e7eb60 ARM: hisilicon: hikey: Fix eMMC with latest ATF & U-Boot
ATF can leave the MMC IP in a state where U-Boot mmc driver
can't enumerate the eMMC.

This patch provides a mmc0_reset_clk() function like we
already so do sd card controller which resets the IP
when entering U-Boot.

With this patch applied eMMC partitions are successfully
enumerated again.

=> mmc dev 0
switch to partitions #0, OK
mmc0(part 0) is current device
=> mmc part

Partition Map for MMC device 0  --   Partition Type: EFI

Part	Start LBA	End LBA		Name
	Attributes
	Type GUID
	Partition GUID
  1	0x00000800	0x00000fff	"vrl"
	attrs:	0x0000000000000000
	type:	ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
	guid:	496847ab-56a1-4cd5-a1ad-47f4acf055c9
  2	0x00001000	0x000017ff	"vrl_backup"
	attrs:	0x0000000000000000
	type:	ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
	guid:	61a36fc1-8efb-4899-84d8-b61642efa723
  3	0x00001800	0x00001fff	"mcuimage"
<snip>

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
2017-08-20 09:54:31 -04:00
Tom Rini
42a9f147d8 fs/fat: Correct blk_dread() return value check
The function blk_dread will return -ENOSYS on failure or on success the
number of blocks read, which must be the number asked to read (otherwise
it failed somewhere).  Correct this check.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-20 09:54:31 -04:00
Tom Rini
9585dd3fff spl: spl_mmc.c Correct blk_dread() return value check
The function blk_dread will return -ENOSYS on failure or on success the
number of blocks read, which must be the number asked to read (otherwise
it failed somewhere).  Correct this check.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-20 09:54:30 -04:00
Tom Rini
d03618d5cb cmd/read.c: Fix checking blk_dread return value
The function blk_dread will return -ENOSYS on failure or on success the
number of blocks read, which must be the number asked to read (otherwise
it failed somewhere).  Correct this check.

Reported-by: Coverity (CID: 166335)
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-20 09:54:30 -04:00
Tom Rini
54f1792c8d mtdparts: Fix various issues reported by Coverity
Now that sandbox is building cmd/mtdparts.c Coverity has looked at the
code and found a number of issues.  In index_partitions() it is possible
that part will be NULL, so re-work the checks and debug statements to
take this into account.  We have a number of string buffers that we
print to in the exact size of, and use string functions on, so we need
to ensure they are large enough to be NULL terminated.  In
device_parse() it is not possible for num_partitions to be 0 (we would
have hit a different error first) so remove logically dead code.
Finally, in parse_mtdparts() if we have an error we need to free the
memory allocated to dev.

Cc: Lothar Waßmann <LW@KARO-electronics.de>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Reported-by: Coverity (CID: 166334, 166333, 166332, 166329, 166328)
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-20 09:54:29 -04:00
Tom Rini
78eda89e9a hash: Compile only hardware or software versions of SHA algorithms
Commit 089df18bfe ("lib: move hash CONFIG options to Kconfig") moved
CONFIG_SHA1, CONFIG_SHA256, CONFIG_SHA_HW_ACCEL, and
CONFIG_SHA_PROG_HW_ACCEL config options to Kconfig. So in the case of
SPL, CONFIG_SPL_HASH_SUPPORT enables CONFIG_SHA1 and CONFIG_SHA256 which
enables SHA SW library by default.  But in the case of platforms with
SHA HW library support, SHA SW library becomes redundant and increases
size of SPL by approx 18K.  Rework the code so that we have named
members and only have either software or hardware versions of the
algorithm, depending on the relevant config options.  Update the comment
around hash_algo to reflect this as well.

Reported-by: Sumit Garg <sumit.garg@nxp.com>
Cc: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Sumit Garg <sumit.garg@nxp.com>
2017-08-20 09:53:13 -04:00
Clément Bœsch
3809e30273 Makefile: honor PYTHON configuration properly
On some systems `python` is `python3` (for instance, Archlinux). The
`PYTHON` variable can be used to point to `python2` to have a successful
build.

The use of `PYTHON` is currently limited in the Makefile and needs to be
extended in other places:

First, pylibfdt is required to be a Python 2 binding (binman imports
pylibfdt and is only compatible Python 2), so its setup.py needs to be
called accordingly. An alternative would be to change the libfdt
setup.py shebang to python2, but the binding is actually portable. Also,
it would break on system where there is no such thing as `python2`.

Secondly, the libfdt import checks need to be done against Python 2 as
well since the Python 2 compiled modules (in this case _libdft.so) can
not be imported from Python 3.

Note on the libfdt imports: "@if ! PYTHONPATH=tools $(PYTHON) -c 'import
libfdt'; then..." is probably simpler than the currently sub-optimal
pipe.
Reviewed-by: Jonathan Gray <jsg@jsg.id.au>
2017-08-20 09:53:13 -04:00
Tom Rini
2629a21e20 Merge git://git.denx.de/u-boot-video 2017-08-19 22:11:05 -04:00
xypron.glpk@gmx.de
021414a332 lcd: avoid possible NULL dereference
Do not dereference bmp before the check if it is NULL.

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-19 20:42:20 +02:00
Tom Rini
5619295995 Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot
EFI Fixes for 2017.09:
  - Fix GOP w/o display
  - Fix LocateHandle
  - Fix exit return value truncation
  - Fix missing EFIAPI in efi_locate_handle (for x86)
2017-08-18 18:24:58 -04:00
Tom Rini
1fdafb2e3d Merge branch 'master' of git://git.denx.de/u-boot-mmc 2017-08-18 18:24:36 -04:00
Tom Rini
a6dd10c70b Merge branch 'master' of git://git.denx.de/u-boot-coldfire 2017-08-18 18:24:08 -04:00
Tom Rini
804f1d9938 Merge branch 'master' of git://git.denx.de/u-boot-rockchip 2017-08-18 18:23:58 -04:00
Kever Yang
957b4ee3f3 rockchip: rk322x: pinctrl: fix IO MASK error on sdcard pin
Fix the IOMUX setting for SDcard CMD pin at the same time.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-18 18:00:46 +02:00
Kever Yang
a634236b8d rockchip: rk322x: pinctrl: using compatible name same with dts
The dts from kernel is using rk3228-pinctrl as compatible name,
need to sync with it to make the driver work.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-18 18:00:29 +02:00
Kever Yang
a80b3b0378 rockchip: rk322x: update MACRO for mmc clksel reg
The description for eMMC/SDIO/SDMMC src is not correct,
update the CRU_CLKSEL11_CON value definition according to TRM.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-18 17:52:47 +02:00
Kever Yang
44c5ba557b rockchip: rk322x: update dram bank size
The DRAM start address is not 0, so need to update the last bank size
as:
DRAM start addr + DRAM_SIZE - last bank start addr

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-18 16:55:25 +02:00
Philipp Tomsich
a299a4879e rockchip: rk3399: spl: remove unused header inclusion
fdtdec.h is included, but not used in rk3399-board-spl.c: remove the
'#include'-statement.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-18 16:55:15 +02:00
Kever Yang
caa6b3b530 rockchip: dts: rk3399-evb: remove redundant gmac node
There are two same gmac node, remove one.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-18 16:54:39 +02:00
xypron.glpk@gmx.de
c81883dfce efi_loader: do not cast return value in EFI_EXIT
UEFI API functions have different return types.
Some return a value of type EFI_STATUS other don't.

We therefore should not cast the return value of EFI_EXIT
to another type than the expression passed to EFI_EXIT.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-08-18 10:53:23 +02:00
Bin Meng
a191ccaf12 mmc: Support generic PCI SD host controller
This changes pci_mmc driver to use PCI_CLASS_SYSTEM_SDHCI instead of
individual vendor id & device id pair to support generic PCI SD host
controller.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-18 15:37:38 +09:00
Angelo Dureghello
a373024e7f m68k: add board stmark2, mcf5441x based
Sysam stmark2 board is a generic and fully (hw and sw) open board, with
a mcf54415 Coldfire CPU, 128MB of DDR2, 16MB of SPI flash and SD card
as non volatile memories, and a wifi module included on-board.
The board is actually used mainly for Coldfire custodian testing activity
related to the mcf5441x Coldfire family.

For further information please see: http://sysam.it/cff_stmark2.html

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
---

Changes in v2:
 - remove CMD_REGINFO
 - add board information in commit message
2017-08-18 01:26:52 +02:00
Angelo Dureghello
02a6eddaba m68k: mcf5445x: allow CS0 to be undefined
On some boards, CONFIG_SYS_CS0_BASE can be undefined, since
CS0 is not connected to any signal.

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
2017-08-18 01:26:39 +02:00
Angelo Dureghello
c533cfcd93 m68k: fix cache.c for Coldfire V4E
- fix cache.c CONFIG_CF_V4e to CONFIG_CF_V4E
- fix cache.c to properly enable/disable cache for V4E

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
2017-08-18 01:26:17 +02:00
Angelo Dureghello
c74dda8b44 m68k: mcf5445x: move early ddr init as board-specific
For certain boot types and sbf, for V4 cpu's, an early ddr/sdram init
is required. This patch moves this ddr/sdram early initalization
away from start.S (to be board related).

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
2017-08-18 01:26:08 +02:00
Philipp Tomsich
b5c4d81b35 spl: fix Makefile for NOR, XIP and YMODEM
During the the conversion to $(SPL_TPL_), the SPL_ fragment was
left over for the NOR, XIP and YMODEM boot methods in SPL, making
these unselectable.

This commit fixes this by dropping the spurious 'SPL_' fragment
from each line.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reported-by: Bo Shen <voice.shen@gmail.com>
Fixes: f94e643 (spl: consistently use $(SPL_TPL_) to select features for SPL and TPL builds)
2017-08-17 10:15:24 +02:00
Kever Yang
1ade3a9013 rockchip: dts: rk3399-firefly: update gmac parameter
Update the tx_delay and rx_delay to match the timing for
rk3399-firefly board to improve the stability of gmac data
transfer.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-17 10:11:18 +02:00
Angelo Dureghello
bdb6099666 cmd: mmc: add mmc partconf read capability
This patch allows to show the EXT_CSD[179] partition_config
register info, just by specifying the dev param:

  U-Boot> mmc partconf 0
  EXT_CSD[179], PARTITION_CONFIG:
  BOOT_ACK: 0x0
  BOOT_PARTITION_ENABLE: 0x0
  PARTITION_ACCESS: 0x0

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-08-17 17:00:11 +09:00
Simon Glass
e7881d85a9 dm: mmc: Drop CONFIG_DM_MMC_OPS
All boards which use DM_MMC have now been converted to use DM_MMC_OPS.
Drop the option and good riddance.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:59:55 +09:00
Simon Glass
b9a40c0c0a dm: mmc: Correct Kconfig condition for SPL_DM_MMC_OPS
This should depend on SPL_DM_MMC, not SPL_DM. For it and update the only
affected board's defconfig.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:18 +09:00
Simon Glass
2088747743 dm: imx: Move i.MX devices to use CONFIG_DM_MMC_OPS
Now that the driver supports it, move these boards over to use driver
model fully for MMC.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
5248930ebf dm: imx: cm_fx6: Enable more driver model support
Enable driver model for MMC (including BLK), SATA and USB. Note that USB
does not yet work correctly since the nodes are disabled. Hopefully this
can be resolved by the maintainer.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
4f6478d646 dm: imx: cm_fx6: Add MMC support for CONFIG_BLK
When CONFIG_BLK is enabled our weak board_mmc_init() will not be called.
Since there is no clock driver for MX6 yet, we must manually enable the
clocks.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
5ec1f560f3 dm: imx: cm_fx6: Add device tree for cm_fx6
Add this file so we can use device-tree control for cm_fx6. It comes from
linux 4.12.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
8d331e38e0 dm: imx: cm_fx6: Support driver model for SATA
Add support for using driver model for SATA with the cm_fx6 board. The old
code remains for now to permit testing.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
653282b567 dm: mmc: fsl_esdhc: Update to support MMC operations
This driver does not currently support CONFIG_DM_MMC_OPS. Update it to
fully convert it to driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
4aac33f510 dm: mmc: fsl_esdhc: Update to support livetree
Update this driver to support a live device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
d6eb25e987 dm: mmc: fsl_esdhc: Drop mmc_init() call from fsl_esdhc_init()
We want to use fsl_esdhc_init() with driver model. Move the mmc_init() out
of this function so that we can use it for our common init.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
e88e1d9c04 dm: mmc: fsl_esdhc: Set up platform data
With driver model we want to store the mmc and configuration structure in
platform data. Set up structure up and use it for non-DM as well.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
201e828b22 dm: mmc: fsl_esdhc: Detect init failure
Since esdhc_init_common() can fail it should return an error code. Update
this and also adjust the timeout mechanism to use get_timer(), which is a
more common approach.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
446e077a21 dm: mmc: fsl_esdhc: Detect reset failure
Since esdhc_reset() can fail it should return an error code. Update this
and also adjust the timeout mechanism to use get_timer(), which is a more
common approach.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
9586aa6ea3 dm: mmc: fsl_esdhc: Set up common versions of operations
Driver model wants to use the core functions in this file but accesses the
driver-private data in a different way. Move the code into new 'common'
functions and set up stubs to call these. Also sort the operations into
alphabetical order for consistency.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
09b465fd0f dm: mmc: fsl_esdhc: Pass private data to internal functions
With driver model we will not use mmc->priv to access driver-private data.
To accomodate this, update internal functions so that we can pass the
private data directly. This will allow the caller to obtain it as it
prefers.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
c893f1e6e5 dm: sata: dwc_ahsata: Add support for driver model
Update this driver to support driver model. This involves implementing the
AHCI operations and reusing existing common code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
b8341f1c39 dm: sata: Update the AHCI uclass to support operations
At present the AHCI uclass is just a shell and we still use the global
functions to access SATA. Fix this by adding operations to the uclass.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
7e0712b26e dm: sata: imx: Allow driver model to be used for sata
Update the sata call to work with driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
f19f1ecb60 dm: sata: Support driver model with the 'sata' command
Update this command to support driver model. This has a different way of
starting and stopping SATA.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
752126a05a dm: sata: dw_sata: Set up common versions of operations
Driver model wants to use the core functions in this file but accesses the
uclass-private data in a different way. Move the code into new 'common'
functions and set up stubs to call these.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
036a803e1b dm: sata: dw_sata: More ahci_init_one() futher down
This function will not be used with driver model and it relates to the
other exported functions. Move it down next to them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
5908d85eb7 dm: sata: dw_sata: Drop is_ready
This variable is set but never used. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
90abb28fcf dm: sata: dw_sata: Rename the dwc_ahsata private header
Rename dwc_ahsata.h to indicate that it is a private header file. We plan
to create another header with some public functions.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
0f07df4301 dm: sata: dw_sata: Sort #include directives
Sort the header file inclusions into the correct order.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
3e59c30fcf dm: sata: dw_sata: Drop unnecessary brackets
There is a strange &(var) coding style in this driver. Adjust it to use
&var instead, which is more usual.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
47c0f3692d dm: sata: dw_sata: Pass uc_priv to internal functions
With driver model sata_dev_desc[] does not exist. We still want to use the
common code of this driver so update it to pass struct ahci_uc_priv * to
each of these functions, instead of an integer which must be looked up in
sata_dev_desc[].

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
4b640dbcac dm: sata: dw_sata: Drop unnecessary casts
Most of the casts in this driver are not necessary. With driver model we
do not cast from void *. Update the driver to follow this rule.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
09bb951bf3 dm: sata: dw_sata: Rename 'probe_ent' to uc_priv
With driver model this becomes uclass-private data. Rename the parameter
varable to reflect this.

With the driver model conversion we will not have any exported functions.
Move all exported functions to be together at the end of the file so that
we can deal with them in one #ifdef block.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:16 +09:00
Simon Glass
c5273acf5c dm: sata: dw_sata: Move exported functions to the end
With the driver model conversion we will not have any exported functions.
Move all exported functions to be together at the end of the file so that
we can deal with them in one #ifdef block.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:16 +09:00
Simon Glass
1dae3b06b7 dm: sata: dw_sata: Drop dwc_ahsata_rw_ncq_cmd()
This function is not called from anywhere. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:16 +09:00
Simon Glass
d7f094354c dm: sata: dwc_ahsata: Make functions static
Some functions are not called from outside this file. Make these static
to make that obvious.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:16 +09:00
Simon Glass
e88afccc44 dm: core: Add a comment about the device_remove() flags
We should explain which flags are used for this function. Update the
comment to indicate this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:16 +09:00
Simon Glass
7074b2a364 dm: blk: Update return value in blk_create_devicef()
This returns 'ret' but the value is always zero. Update it to simply
return 0, for clarity.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:16 +09:00
Simon Glass
c16ad675d5 dm: usb: Adjust the 'usb' command to use blk_common_cmd()
Instead of having separate code in the 'usb' command, adjust it to use
the common function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-17 16:44:16 +09:00
Simon Glass
09ed0d616d dm: ide: Adjust the 'ide' command to use blk_common_cmd()
Instead of having separate code in the 'ide' command, adjust it to use
the common function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-17 16:44:16 +09:00
Simon Glass
1eaadd3423 dm: scsi: Adjust the 'scsi' command to use blk_common_cmd()
Instead of having separate code in the 'scsi' command, adjust it to use
the common function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-17 16:44:16 +09:00
Simon Glass
e29e71e93a dm: sata: Adjust the 'sata' command to use blk_common_cmd()
Instead of having separate code in the 'sata' command, adjust it to use
the common function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-17 16:44:16 +09:00
Simon Glass
4395f66739 dm: blk: Add a generic function for block device commands
Most block devices provide a command (e.g. 'sata', 'scsi', 'ide') and
these commands generally do the same thing. This makes it harder to
maintain this code and keep it consistent.

We now have a block device interface which is either implemented by driver
model (when CONFIG_BLK is enabled) or with a legacy interface. Therefore
it is possible to handle most of what these commands do with generic code.

Add a new generic function to process block-device commands using the
interface type and the current device number for that type.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:16 +09:00
Simon Glass
6faa4ed74d dm: blk: Add a function to find an interface-type name
Add a function to find the name of an interface type (e.g. "sata", "scsi")
from the interface type enum.

This is useful for generic code (not specific to SATA or SCSI, for
example) that wants to display the type of interface it is dealing with.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:16 +09:00
Simon Glass
745fb9c25e dm: core: Avoid calling dm_scan_fdt_dev() with of-platdata
We cannot call dm_scan_fdt_dev() with of-platdata since there is no device
tree. Fix this with an #if check.

Fixes: 3be9a37 (dm: syscon: scan sub-nodes of the syscon node)
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:16 +09:00
Wenyou.Yang@microchip.com
722b150e6f mmc: gen_atmel_mci: Fix wrong arguments used of bind()
The bind() method is called before the device is probed and so the
device has no private data, should use the platform data, and set up
a new struct to hold the mmc and cfg members.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:12 +09:00
Marek Vasut
8cd46cba53 mmc: sd_sdhi: Enable clock using clock framework
Since we now have clock driver for the RCar Gen3 , add support for
enabling the clock into the SH SDHI driver to prevent hacks in the
board files.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-17 14:38:18 +09:00
Marek Vasut
a3f0a7d5b5 mmc: sh_sdhi: Fix the ACMD handling
The command handling in this driver is awful, esp. because the driver
depends on command numbers to determine whether this is APPCMD or not.
Also, handling of command RSP response types is totally wrong.

This patch at least plucks out some of the custom command encoding and
fixes the APPCMD handling. The RSP handling still needs work, yet that
might not be needed as it turns out the uniphier-sd.c driver is in much
better shape and supports the same IP, so we might be able to just drop
this driver in favor of the uniphier one.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-17 14:38:02 +09:00
Marek Vasut
d1c18ca110 mmc: sh_sdhi: Add DM and DT probing support
Add MMC DM and DT probing support into the SH SDHI driver.
This patch abstracts out the common bits of the send command
and set ios functions, so they can be used both by DM and non
DM setups and adds the DM probe support.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-17 14:37:45 +09:00
Marek Vasut
ac5efc358b mmc: uniphier-sd: Fix long response processing
The long response entry 0..3 LSByte comes from the next response
register MSByte, not from the next response register LSByte. Fix
this to make the driver report correct values in response 136 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-17 14:36:05 +09:00
Tom Rini
336aee50cf Merge git://git.denx.de/u-boot-tegra 2017-08-16 18:12:58 -04:00
Tom Rini
ceff355a5f Merge git://git.denx.de/u-boot-sunxi
Update A20-OLinuXino-Lime2-eMMC_defconfig to include CONFIG_SCSI

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-16 18:12:40 -04:00
Tom Rini
470135be27 Merge git://www.denx.de/git/u-boot-imx
Update pfla02 for setenv changes and PHYLIB/etc migration to Kconfig.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-16 18:12:00 -04:00
Tom Rini
390194d43f Merge git://git.denx.de/u-boot-spi 2017-08-16 18:07:15 -04:00
Bin Meng
294f2050c4 sf: Preserve QE bit when clearing BP# bits for Macronix flash
On some flash (like Macronix), QE (quad enable) bit is in the same
status register as BP# bits, and we need preserve its original value
during a reboot cycle as this is required by some platforms (like
Intel ICH SPI controller working under descriptor mode).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
[Refined code for readability]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-08-16 18:21:50 +05:30
Simon Glass
c595199194 env: Adjust the load() method to return an error
The load() methods have inconsistent behaviour on error. Some of them load
an empty default environment. Some load an environment containing an error
message. Others do nothing.

As a step in the right direction, have the method return an error code.
Then the caller could handle this itself in a consistent way.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:31:24 -04:00
Simon Glass
21f639446d env: Adjust the get_char() method to return an int
In principle this can fail, e.g. if the index is out of range. Adjust the
driver signature to allow returning an error code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-16 08:31:24 -04:00
Simon Glass
723806cc5b env: Rename some other getenv()-related functions
We are now using an env_ prefix for environment functions. Rename these
other functions as well, for consistency:

   getenv_vlan()
   getenv_bootm_size()
   getenv_bootm_low()
   getenv_bootm_mapsize()
   env_get_default()

Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:31:11 -04:00
Simon Glass
35affd7a2f env: Rename eth_getenv_enetaddr() to eth_env_get_enetaddr()
Rename this function for consistency with env_get().

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:30:44 -04:00
Simon Glass
bfebc8c965 env: Rename getenv_hex(), getenv_yesno(), getenv_ulong()
We are now using an env_ prefix for environment functions. Rename these
for consistency. Also add function comments in common.h.

Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:30:32 -04:00
Simon Glass
00caae6d47 env: Rename getenv/_f() to env_get()
We are now using an env_ prefix for environment functions. Rename these
two functions for consistency. Also add function comments in common.h.

Quite a few places use getenv() in a condition context, provoking a
warning from checkpatch. These are fixed up in this patch also.

Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:30:24 -04:00
Simon Glass
fd1e959e91 env: Rename eth_setenv_enetaddr() to eth_env_set_enetaddr()
Rename this function for consistency with env_set().

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:23:56 -04:00
Simon Glass
018f530323 env: Rename common functions related to setenv()
We are now using an env_ prefix for environment functions. Rename these
commonly used functions, for consistency. Also add function comments in
common.h.

Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:23:32 -04:00
Simon Glass
382bee57f1 env: Rename setenv() to env_set()
We are now using an env_ prefix for environment functions. Rename setenv()
for consistency. Also add function comments in common.h.

Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:22:18 -04:00
Peng Fan
e872f27a02 imx: mx7: fix build warning when CONFIG_IMX_RDC not enabled
Fix build warning when CONFIG_IMX_RDC not defined in defconfig.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
2017-08-16 12:43:09 +02:00
Peng Fan
9402cafb23 imx: mx6sl: simplify code using setbits_le32
Simplify code by removing set_preclk_from_osc with directly setbits_le32.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
2017-08-16 12:43:09 +02:00
Peng Fan
7236297aee imx: mx6sx: select OSC as uart's clk parent
As M4 is sourcing UART clk from OSC, to make UART work
when M4 is enabled, need to select OSC as clk parent,
24M OSC is enough for debug UART in uboot.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
2017-08-16 12:43:04 +02:00
Peng Fan
79a57b5ae1 imx: mx6: soc: fix mx6sll settings
There is not LDO_SOC/PU/ARM/MMDC1 on i.MX6SLL, also no need to gate/ungate
all PFDs to make PFD working.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
2017-08-16 11:56:22 +02:00
Peng Fan
3d3598d0f6 imx: mx6: select ARM_ERRATA_845369
Select ARM_ERRATA_845369 for i.MX6DQ/DL/QP.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-08-16 11:51:00 +02:00
Peng Fan
11d94319c3 arm: Implement workaround for Cortex-A9 errata 845369
Under very rare timing circumstances, transitioning into streaming
mode might create a data corruption. Present on Two or more processors
or 1 core with ACP, all revisions. This erratum can be worked round
by setting bit[22] of the undocumented Diagnostic Control Register to 1.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-08-16 11:50:51 +02:00
Peng Fan
91435cd40d ARM: i.MX6: exclude the ARM errata from i.MX6 UP system
The ARM errata 751472, 794072, 761320 only applied
to the following configuration:

This erratum affects configurations with either:
- One processor if the ACP is present
- Two or more processors

i.MX6 family does not have the ACP and thus only the MPCore system
will be impacted, which are the i.MX6DQ, i.MX6DL, and i.MX6QP.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
2017-08-16 11:50:40 +02:00
Sébastien Szymanski
0c7c6fb764 imx: imx6ull: correct get_cpu_speed_grade_hz
i.MX6ULL has different speed grades than i.MX6UL.

Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
2017-08-16 11:45:10 +02:00
Sébastien Szymanski
44e670532d imx: imx6ul: correct get_cpu_speed_grade_hz on 696MHz SoCs
Return the correct value when the speed grade is 696MHz.

Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
2017-08-16 11:44:57 +02:00
Breno Lima
6efb613373 mx6sabreauto: Fix IOMUXC_GPR6 and IOMUXC_GPR7 values
The IPU AXI QoS for the i.MX6QP and i.MX6DP processors have to be set as
commented in the code:
/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */

Set IOMUXC_GPR6 and IOMUXC_GPR7 to 0x77177717 instead of 0x007F007F.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
2017-08-16 11:44:18 +02:00
Breno Lima
a500a33115 mx6sabresd: Fix IOMUXC_GPR6 and IOMUXC_GPR7 values
The IPU AXI QoS for the i.MX6QP and i.MX6DP processors have to be set as
commented in the code:
/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */

Set IOMUXC_GPR6 and IOMUXC_GPR7 to 0x77177717 instead of 0x007F007F.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
2017-08-16 11:43:15 +02:00
Anatolij Gustschin
ff3a5fc46d imx6: clock: correct comment for PLL_VIDEO
This appear to be a copy-paste error, clean it up.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-08-16 11:38:27 +02:00
Anatolij Gustschin
557b9b7250 imx6: use SION macro in SDn_CMD mux mode bitfield arguments
Select SION by appropriate macro instead of constant.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-08-16 11:36:05 +02:00
Simon Glass
01510091de env: Drop saveenv() in favour of env_save()
Use the env_save() function directly now that there is only one
implementation of saveenv().

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Denk <wd@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 20:50:30 -04:00
Simon Glass
310fb14b26 env: Drop env_relocate_spec() in favour of env_load()
This is a strange name for a function that loads the environment. There is
now only one implementation of this function, so use the new env_load()
function directly instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 20:50:29 -04:00
Simon Glass
a69d0f60e5 env: Drop env_get_char_spec()
We only have a single implementation of this function now and it is called
env_get_char(). Drop the old function and the weak version.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-15 20:50:29 -04:00
Simon Glass
6eeae42469 env: Drop env_init_new()
Now that env_init() is only defined once we can drop the env_init_new()
name and just use env_init().

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 20:50:29 -04:00
Simon Glass
98b5755fb0 env: Drop unused env_ptr variables
This variable is declared as a global in most environment location
drivers. But it is not used outside the drivers and most of the
declarations are unnecessary.

Also some drivers call free() on env_ptr which seems wrong since it is
not in the heap.

Drop the variable where possible, and all calls to free().

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 20:50:28 -04:00
Simon Glass
ac358beb85 env: Drop the env_name_spec global
Add a name to the driver and use that instead of the global variable
declared by each driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 20:50:28 -04:00
Simon Glass
7938822a6b env: Drop common init() functions
Most of the init() implementations just use the default environment.
Adjust env_init_new() to do this automatically, and drop the redundant
code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 20:50:27 -04:00
Simon Glass
e5bce247b0 env: Switch over to use environment location drivers
Move over to use a the master implementation of the location drivers, with
each method calling out to the appropriate driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 20:50:27 -04:00
Simon Glass
c9d728dd33 env: Add a new implementation of environment access
We plan to move to a environment access via drivers for each location
where the environment can be stored. Add an implementation for this. So
far it is not used, but will be pressed into service in a future patch.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-15 20:50:26 -04:00
Simon Glass
c1c3fe2307 env: Convert CONFIG_ENV_IS_IN... to a choice
At present we support multiple environment drivers but there is not way to
select between them at run time. Also settings related to the position and
size of the environment area are global (i.e. apply to all locations).

Until these limitations are removed we cannot really support more than one
environment location. Adjust the location to be a choice so that only one
can be selected. By default the environment is 'nowhere', meaning that the
environment exists only in memory and cannot be saved.

Also expand the help for the 'nowhere' option and move it to the top since
it is the default.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Move all of the imply logic to default X if Y so it works again]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-15 20:50:01 -04:00
Marcel Ziswiler
33848eb53e apalis_t30/tk1, colibri_t20/t30: fix i2c bus frequencies
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2017-08-15 14:51:18 -07:00
Marcel Ziswiler
8b733af831 apalis-tk1: remove duplicate hdmi_ddc device tree node
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2017-08-15 14:51:18 -07:00
Marcel Ziswiler
ceef960812 dm: tegra: move apalis t30/tk1, colibri t20/t30 to livetree
Change these board to use a live device tree after relocation.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2017-08-15 14:51:18 -07:00
Marcel Ziswiler
9a50b6fc81 apalis_t30: fix usb otg power enable
Fix USB OTG power enable aka USBO1_EN which on Apalis T30 is connected
to the T30 ball GEN2_I2C_SCL.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2017-08-15 14:51:18 -07:00
Simon Glass
4415f1d1f1 env: Create a location driver for each location
Set up a location driver for each supported environment location. At
present this just points to the global functions and is not used. A
later patch will switch this over to use private functions in each driver.

There are several special cases here in various drivers to handle
peculiarities of certain boards:

1. Some boards define CONFIG_ENV_IS_IN_FAT and CONFIG_SPL_ENV_SUPPORT but
do not actually load the environment in SPL. The env load code was
optimised out before but with the driver, it is not. Therefore a special
case is added to env/fat.c. The correct fix (depending on board testing
might be to disable CONFIG_SPL_ENV_SUPPORT.

2. A similar situations happens with CONFIG_ENV_IS_IN_FLASH. Some boards
do not actually load the environment in SPL, so to reduce code size we
need to drop that code. A similar fix may be possible with these boards,
or it may be possible to adjust the environment CONFIG settings.

Added to the above is that the CONFIG_SPL_ENV_SUPPORT option does not
apply when the environment is in flash.

Obviously the above has been discovered through painful and time-consuming
trial and error. Hopefully board maintainers can take a look and figure
out what is actually needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-15 08:18:53 -04:00
Simon Glass
42a8180d19 env: Rename nand env_location to nand_env_location
We want to use this name for all environment drivers. Update the nand
driver to use a more specific name.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 08:18:51 -04:00
Simon Glass
203e94f6c9 env: Add an enum for environment state
At present we have three states for the environment, numbered 0, 1 and 2.
Add an enum to record this to avoid open-coded values.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 08:18:51 -04:00
Simon Glass
75de597d2d env: common: Drop env_get_char_memory()
This function is the same as env_get_char_spec() apart from dropping the
brackets. Drop the brackets from env_get_char_spec() and use that instead
of env_get_char_memory().

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 08:18:47 -04:00
Simon Glass
81a4dea228 env: common: Drop env_get_char_init()
This function does nothing but call env_get_char_spec(). Drop it and
adjust its only caller.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 08:18:47 -04:00
Simon Glass
5fc5254084 env: common: Factor out the common env_valid check
The check for gd->env_valid is used in both the 'if' and 'else' part of
env_get_char(). Move it into that function instead for simplicity. Drop
that code from the two leaf functions.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 08:18:46 -04:00
Simon Glass
0219fb61c1 env: common: Drop env_get_addr()
This function is not used anywhere other than env_get_char(). Move the
code into that function.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-15 08:18:46 -04:00
Simon Glass
bcdfb8d5a5 env: common: Make env_get_addr/get_char_memory() static
These functions are not used outside this file. Make them static and order
them to avoid forward declarations.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 08:18:46 -04:00
Simon Glass
91d3aa05d0 env: Use tabs in ENV_IS_IN_FAT
Tidy up the formatting of this option.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-15 08:18:46 -04:00
Simon Glass
0649cd0d49 Move environment files from common/ to env/
About a quarter of the files in common/ relate to the environment. It
seems better to put these into their own subdirectory and remove the
prefix.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 08:18:45 -04:00
Simon Glass
ec74f5f9c3 Makefile: Rename 'env' target to 'environ'
This target stops us using 'env' as a subdirectory. It is not mentioned in
the help so seems to be an internal target. Rename it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 08:18:42 -04:00
Jagan Teki
585bf8ae6f sun50i: a64: Add A64-OLinuXino initial support
OLimex A64-OLinuXino is an open-source hardware board
using the Allwinner A64 SOC.

OLimex A64-OLinuXino has
- A64 Quad-core Cortex-A53 64bit
- 1GB or 2GB RAM DDR3L @ 672Mhz
- microSD slot and 4/8/16GB eMMC
- Debug TTL UART
- HDMI
- LCD
- IR receiver
- 5V DC power supply

Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-08-15 11:30:59 +05:30
Jagan Teki
f322657204 sun50i: a64: Add initial NanoPi A64 support
NanoPi A64 is a new board of high performance with low cost
designed by FriendlyElec., using the Allwinner A64 SOC.

Nanopi A64 features
- Allwinner A64, 64-bit Quad-core Cortex-A53@648MHz to 1.152GHz, DVFS
- 1GB DDR3 RAM
- MicroSD
- Gigabit Ethernet (RTL8211E)
- Wi-Fi 802.11b/g/n
- IR receiver
- Audio In/Out
- Video In/Out
- Serial Debug Port
- microUSB 5V 2A DC power-supply

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-08-15 11:30:19 +05:30
Tom Rini
2d3c4ae350 Prepare v2017.09-rc2
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-14 20:02:11 -04:00
Tom Rini
88663126a0 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-14 20:00:40 -04:00
Tom Rini
248a3f6c7c Merge git://git.denx.de/u-boot-net 2017-08-14 17:06:58 -04:00
Sam Protsenko
5abc1a4523 common: Move CONFIG_BOOTARGS to Kconfig
Also introduce CONFIG_USE_BOOTARGS option so we can control if
CONFIG_BOOTARGS defined at all.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
[trini: Resync r8a779[56]_ulcb, various ls10xx targets]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-14 17:06:06 -04:00
Prabhakar Kushwaha
a5fe87e829 driver: net: ldpaa: Update priv->phydev after free()
Even after memory free of phydev, priv is still pointing to the
obsolete address.
So update priv->phydev as NULL after memory free.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-14 12:47:33 -05:00
Yuiko Oshino
d2c3197922 usb: net: Add support for Microchip LAN75xx and LAN78xx
Add support for Microchip LAN7500, LAN7800 and LAN7850,
USB to 10/100/1000 Ethernet Controllers.

Signed-off-by: Yuiko Oshino <yuiko.oshino@microchip.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-14 12:47:33 -05:00
Yuiko Oshino
1c1e370033 net: Add mii_resolve_flowctrl_fdx()
Add an mii helper function to resolve flow control status per
IEEE 802.3-2005 table 28B-3.
This function was taken from the Linux source tree.

Signed-off-by: Yuiko Oshino <yuiko.oshino@microchip.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-14 12:47:32 -05:00
Madalin Bucur
3f8f1410b5 net: fman: add support RGMII_TXID to memac
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-14 12:47:32 -05:00
Tom Rini
aa6aaf9321 ARM: rockchip: rock: Correct test to use CONFIG_IS_ENABLED not defined
While it is likely that this entire case is superfluous and can be
removed, correct the test now to match what is in rockchip-common.h and
makes sense based on context of the code.  Otherwise we get a large
number of warnings.

Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-14 13:33:07 -04:00
Tom Rini
c1b62ba9ca Merge branch 'master' of git://git.denx.de/u-boot-rockchip 2017-08-14 10:40:01 -04:00
Patrice Chotard
bc5d038445 stm32f1: remove stm32f1 support
A few years ago STM32F1 SoCs support has been added :
0144caf22c  gpio: stm32: add stm32f1 support
2d18ef2364  ARMv7M: add STM32F1 support

But neither STM32F1 dedicated defconfig nor board was
associated to these commits.

Got confirmation from Tom Rini and Matt Porter to remove
all this code [1]

[1] http://u-boot.10912.n7.nabble.com/Remove-STM32F1-support-td301603.html

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13 15:17:37 -04:00
Chris Packham
7b07a20c5e cmd/bdinfo: correct comment in board_detail
This appears to be a simple typo that dates back to the original
implementation of board_detail in commit e79394643b ("common: Update
cmd_bdinfo for PPC").

Signed-off-by: Chris Packham <judge.packham@gmail.com>
2017-08-13 15:17:37 -04:00
Simon Glass
3a37aee30f test: Move the FIT test into the correct place
Move this test so that it will run when 'make tests' is used.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-13 15:17:36 -04:00
Simon Glass
77b426703d test: Convert the FIT test to test/py
Convert this test to use the pytest framework.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-13 15:17:36 -04:00
Simon Glass
bde671237f test: Indent test-fit.py to match the next patch
We plan to rewrite this script to use the pytest framework. To make it
easier to review the changes, indent the code to match the next patch.
This gets all of the whitespace changes out of the way.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-13 15:17:36 -04:00
Nishanth Menon
0459bc30b6 ARM: OMAP5: Enable support for AVS0 for OMAP5 production devices
OMAP5432 did go into production with AVS class0 registers which were
mutually exclusive from AVS Class 1.5 registers.

Most OMAP5-uEVM boards use the pre-production Class1.5 which has
production efuse registers set to 0. However on production devices,
these are set to valid data.

scale_vcore logic is already smart enough to detect this and use the
"Nominal voltage" on devices that do not have efuse registers populated.

On a test production device populated as follows:
MPU OPP_NOM:
=> md.l 0x04A0021C4 1
4a0021c4: 03a003e9                               ....
(0x3e9 = 1.01v) vs nom voltage of 1.06v
MPU OPP_HIGH:
=> md.l 0x04A0021C8 1
4a0021c8: 03400485                               ..@.

MM OPP_NOM:
=> md.l 0x04A0021A4 1
4a0021a4: 038003d4                               ....
(0x3d4 = 980mV) vs nom voltage of 1.025v
MM OPP_OD:
=> md.l 0x04A0021A8 1
4a0021a8: 03600403                               ..`.

CORE OPP_NOM:
=> md.l 0x04A0021D8 1
4a0021d8: 000003cf                               ....
(0x3cf = 975mV) vs nom voltage of 1.040v

Since the efuse values are'nt currently used, we do not regress on
existing pre-production samples (they continue to use nominal voltage).

But on boards that do have production samples populated, we can leverage
the optimal voltages necessary for proper operation.

Tested on:
a) 720-2644-001 OMAP5UEVM with production sample.
b) 750-2628-222(A) UEVM5432G-02 with pre-production sample.

Data based on OMAP5432 Technical reference Manual SWPU282AF (May
2012-Revised Aug 2016)

NOTE: All collaterals on OMAP5432 silicon itself seems to have been
removed from ti.com, though EVM details are still available:
http://www.ti.com/tool/OMAP5432-EVM

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-08-13 15:17:35 -04:00
Nishanth Menon
5796b66651 ARM: OMAP5: Remove OPP_LOW Definitions for ES2.0
ES2.0 descopes OPP_LOW definition. So remove it from macros defined.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-08-13 15:17:35 -04:00
Simon Glass
010ad8c34a test: Fix FIT test to pass again
A recent change adjusted a test string so that the test no-longer passes.
Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Heiko Schocher <hs@denx.de>
Fixes: b28c5fcc (test-fit.py: Minor grammar/spelling/clarification tweaks)
2017-08-13 15:17:35 -04:00
Andy Shevchenko
ffdec3000a wdt: Update uclass to make clear that the timeout is in ms
Convert name to show explicitly that we are using milliseconds. For a
watchdog timer this is precise enough.

No functional change intended.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-13 15:17:34 -04:00
Nobuhiro Iwamatsu
160cfc4b5a boot_fit: Change return value from FDT_ERROR to -EINVAL in fdt_offset()
FDT_ERROR is defined as unsigned long. However, since the return value of
fdt_offset() is int, a warning will occur when compiling. Also, it is better
to use -EINVAL than FDT_ERROR.
This fixes this problem by change return value from FDT_ERROR to -EINVAL.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Franklin S Cooper Jr <fcooper@ti.com>
2017-08-13 15:17:34 -04:00
Bin Meng
7088a36598 x86: qemu: Enable NVMe driver
QEMU supports NVMe emulation. Enable the NVMe driver on QEMU x86.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13 15:17:33 -04:00
Bin Meng
beb5f52139 nvme: Handle zero Maximum Data Transfer Size (MDTS)
Maximum Data Transfer Size (MDTS) field indicates the maximum
data transfer size between the host and the controller. The
host should not submit a command that exceeds this transfer
size. The value is in units of the minimum memory page size
and is reported as a power of two (2^n).

The spec also says: a value of 0h indicates no restrictions
on transfer size. On the real NVMe card this is normally not
0 due to hardware restrictions, but with QEMU emulated NVMe
device it reports as 0. In nvme_blk_read/write() below we
have the following algorithm for maximum number of logic
blocks per transfer:

u16 lbas = 1 << (dev->max_transfer_shift - ns->lba_shift);

dev->max_transfer_shift being 0 will for sure cause lbas to
overflow. Let's use 20. With this fix, the NVMe driver works
on QEMU emulated NVMe device.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13 15:17:33 -04:00
Jon Nettleton
f81d83d534 nvme: Fix number of blocks detection
NVMe should use the nsze value from the queried device. This will
reflect the total number of blocks of the device and fix detecting
my Samsung 960 EVO 256GB.

Original:
Capacity: 40386.6 MB = 39.4 GB (82711872 x 512)

Fixed:
Capacity: 238475.1 MB = 232.8 GB (488397168 x 512)

Signed-off-by: Jon Nettleton <jon@solid-run.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13 15:17:32 -04:00
Jon Nettleton
0deb91318b nvme: Detect devices that are class Storage Express
This adds support to detect the catchall PCI class for NVMe devices.
It allows the drivers to work with most NVMe devices that don't need
specific detection due to quirks etc.

Tested against a Samsung 960 EVO drive.

Signed-off-by: Jon Nettleton <jon@solid-run.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13 15:17:32 -04:00
Zhikang Zhang
0adc38be3d nvme: Add nvme commands
Add nvme commands in U-Boot command line.

1. "nvme scan" - scan NVMe blk devices
2. "nvme list" - show all available NVMe blk devices
3. "nvme info" - show current or a specific NVMe blk device
4. "nvme device" - show or set current device
5. "nvme part" - print partition table
6. "nvme read" - read data from NVMe blk device
7. "nvme write" - write data to NVMe blk device

Signed-off-by: Zhikang Zhang <zhikang.zhang@nxp.com>
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13 15:17:32 -04:00
Zhikang Zhang
f6aa61d599 nvme: Add show routine to print detailed information
This adds nvme_print_info() to show detailed NVMe controller and
namespace information.

Signed-off-by: Zhikang Zhang <zhikang.zhang@nxp.com>
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13 15:17:31 -04:00
Zhikang Zhang
982388eaa9 nvme: Add NVM Express driver support
NVM Express (NVMe) is a register level interface that allows host
software to communicate with a non-volatile memory subsystem. This
interface is optimized for enterprise and client solid state drives,
typically attached to the PCI express interface.

This adds a U-Boot driver support of devices that follow the NVMe
standard [1] and supports basic read/write operations.

Tested with a 400GB Intel SSD 750 series NVMe card with controller
id 8086:0953.

[1] http://www.nvmexpress.org/resources/specifications/

Signed-off-by: Zhikang Zhang <zhikang.zhang@nxp.com>
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13 15:17:31 -04:00
Zhikang Zhang
ffab6945ec dm: blk: part: Add UCLASS_NVME and IF_TYPE_NVME
This adds a new uclass id and block interface type for NVMe.

Signed-off-by: Zhikang Zhang <zhikang.zhang@nxp.com>
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jon Nettleton <jon@solid-run.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13 15:17:30 -04:00
xypron.glpk@gmx.de
1b69ce2fc0 arm: mvebu: ddr3_debug: remove self assignments
Remove superfluous self assignements.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-13 15:17:30 -04:00
xypron.glpk@gmx.de
a21d6363cc arm: mvebu: remove self assignment
Assigning dev_num to itself is superfluous.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-13 15:17:30 -04:00
xypron.glpk@gmx.de
36d35345b1 tpm: add missing va_end
va_start must always be matched by va_end.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 15:17:29 -04:00
xypron.glpk@gmx.de
2d5e86b110 ARM: hisilicon: hikey: do not rely on random stack value
If CONFIG_MMC_DW is not defined the return value of
init_dwmmc should not rely on a random stack value.

Instead indicate that no error occured.

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-08-13 15:17:29 -04:00
xypron.glpk@gmx.de
d1fe19766b stm32: remove redundant 'else if'
The if in the else branch is superfluous.
We can use a simple if.

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-08-13 15:17:28 -04:00
xypron.glpk@gmx.de
a22bbfda6e arm: mvebu: avoid possible NULL dereference
It does not make sense to check if info is NULL after
dereferencing it.

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-13 15:17:28 -04:00
xypron.glpk@gmx.de
a5981734a4 armv7m: mpu_config add missing break
For DEVICE_NON_SHARED the newly assigned value of attr
is overwritten due to a missing break.

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-08-13 15:17:28 -04:00
xypron.glpk@gmx.de
6def7de37b bcm281xx: clock: avoid possible NULL dereference
It does not make sense first to dereference c and then
to check if it is NULL.

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-08-13 15:17:27 -04:00
xypron.glpk@gmx.de
65e8ce29e4 arm: bcm235xx: clk_set_rate avoid possible NULL deref
It does not make sense first to dereference c and then
to check if it is NULL.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-08-13 15:17:27 -04:00
xypron.glpk@gmx.de
b69a0849e7 arm: bcm235xx: avoid possible NULL dereference
It does not make sense to first dereference c and then
check if it is NULL.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-08-13 15:17:26 -04:00
xypron.glpk@gmx.de
9730bcdc2f arm: spear: do not return random value from stack
If the NOR device is not available do not return
a random value from the stack.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-08-13 15:17:26 -04:00
xypron.glpk@gmx.de
5cc9e6b7fa api: remove superfluous assignment
No need to assign a value to sig if the next statement using sig
is itself an assignment of a value to sig.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 15:17:25 -04:00
Adam Ford
ebb3e43de4 Convert CONFIG_OMAP3_SPI to Kconfig
This converts the following to Kconfig:
   CONFIG_OMAP3_SPI

Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Minor comment tweaks]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-13 15:17:10 -04:00
Kever Yang
217273cd44 rockchip: clk: remove RATE_TO_DIV
Use DIV_ROUND_UP instead RATE_TO_DIV for all Rockchip SoC
clock driver.
Add or fix the div-field overflow check at the same time.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-13 17:15:09 +02:00
Kever Yang
3a94d75d0e rockchip: clk: update dwmmc clock div
dwmmc controller has default internal divider by 2,
and we always provide double of the clock rate request by
dwmmc controller. Sync code for all Rockchip SoC with:
4055b46 rockchip: clk: rk3288: fix mmc clock setting

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixup for 'missing DIV_ROUND_UP' conflict for clk_rk3288.c:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-13 17:15:09 +02:00
Kever Yang
95ca100ba7 rockchip: rk322x: update max-frequency for mmc node
mmc using 150000000 as max-frequency like what rk3288 sets.
This can speed up the mmc read/write, the actual mmc clock is:
Before this patch: 37.125M
After this patch: 49.5M

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-13 17:15:09 +02:00
Kever Yang
a2a1bfe175 rockchip: dts: rk322x: add sdmmc device node
add node for sdmmc in dts and rk3229-evb.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-13 17:15:08 +02:00
Philipp Tomsich
81630a3b38 scripts: setlocalversion: safely extract variables from auto.conf using awk
Moving SPL_LDSCRIPT to Kconfig triggered an unfortunate attempt of
command substitution, as the sourced auto.conf may include $(ARCH)
which tries to execute a command 'ARCH'.
This showed up as a warning similar to the following:
  include/config/auto.conf: line 209: ARCH: command not found

This change does no longer attempt to source auto.conf, but rather
passes it through awk to retrieve the values for CONFIG_LOCALVERSION
and CONFIG_LOCALVERSION_AUTO.  This will also mitigate the risk of
unintended command substitution.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reported-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Reviewed-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
2017-08-13 17:15:08 +02:00
Kever Yang
18d38d3a94 rockchip: rk322x: set the DDR region as non-secure in SPL
Disable the ddr secure region setting in SPL and the ddr memory
becomes non-secure, every one can access it. the trust firmware
like OPTEE should have the correct setting for it after SPL if
there is one.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-13 17:15:08 +02:00
Kever Yang
bf82e200a9 rockchip: rk3288: fix EMMC_DIV_MASK definition in header
It should be '<<' instead of '<' for _MASK definition, fix it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:15:08 +02:00
Philipp Tomsich
e8f9ad94bf rockchip: rk3368: spl: move SPL_LDSCRIPT to Kconfig
With the new way of doing things (i.e. the hierarchical selection of
SPL_LDSCRIPT via Kconfig) in place, this moves the SPL_LDSCRIPT setting
for the RK3368 from defconfig back into Kconfig.

With this done, there should be no lingering cases of SPL_LDSCRIPT
outside of Kconfig files.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:15:08 +02:00
Philipp Tomsich
0ee89f2daf spl: moveconfig: remove SPL_LDSCRIPT definitions for header-files
With the hierarchical defaults set up, we remove these from the header
files.  To do so, I've run moveconfig on SPL_LDSCRIPT and this commits
the changes.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:15:08 +02:00
Philipp Tomsich
b529993e02 spl: add hierarchical defaults for SPL_LDSCRIPT
With SPL_LDSCRIPT moved to Kconfig (and this being a 'string' config
node), all the lingering definitions in header files will cause
warnings/errors due to the redefinition of the configuration item.

As we don't want to pollute the defconfig files (and values should
usually be identical for entire architectures), the defaults are moved
into Kconfig.  Kconfig will always pick the first default that
matches, so please keep these values at the end of each file (to allow
any board-specific Kconfig, which will be included earlier) to
override with an unconditional default setting.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:37 +02:00
Philipp Tomsich
96b9082c64 rockchip: rk3188: rock: adjust for SPL/TPL split
With the changes to split SPL/TPL for the RK3368, I apparently missed
some needed adjustments to the RK3188 Kconfig and rock_defconfig.

This fixes build-issues for the rock board after applying the RK3368
enablement (and SPL/TPL) set that resulted from TPL_SERIAL_SUPPORT,
TPL_ROCKCHIP_BACK_TO_BROM and TPL_TINY_MEMSET being separate symbols
now.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:37 +02:00
Andy Yan
c72c161bc0 rockchip: remove the hard coded uart iomux setting for px5 evb
As the debug uart is marked as dm-pre-reloc, the pinctrl driver
will handle the correct iomux setting.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:37 +02:00
Andy Yan
d6d26e7641 rockchip: set Pre-reloc malloc pool size to 4kb for rk3368 based boards
The default 1kb pre-reloc malloc pool is not enough for dm
core to enable the dm-pre-reloc device drivers.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-13 17:12:36 +02:00
Andy Yan
bfc2ed5c22 rockchip: add u-boot specific dts for rk3368 based boards
Device drivers like debug serial, dmc should be enabled before
relocation, so add u-boot.dtsi files to contain devices that
should be marked as dm-pre-reloc.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:36 +02:00
Philipp Tomsich
3159a6fc39 rockchip: rk3368: remove setup of secure timer from TPL/SPL
When using DM timers w/ the timer0 block within the RK3368, we no
longer depend on the ARMv8 generic timer counting.  This allows us to
drop the secure timer initialisation from the TPL and SPL stages.

The secure timer will later be set up by ATF, which starts the ARMv8
generic timer.  Thus, there will be a dependency from Linux to the ATF
through the ARMv8 generic timer... this seems reasonable, as Linux
will require the ATF (and PSCI) to start up the secondary cores anyway
(in other words: we don't add any new dependencies).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:36 +02:00
Philipp Tomsich
fe1c3cd3af rockchip: lion-rk3368: defconfig: enable DM timer for all stages
There is no reasonably robust way (this will be needed so early that
diagnostics will be limited) to specify the base-address of the secure
timer through the DTS for TPL and SPL.  In order to allow us a cleaner
way to structure our SPL and TPL stage, we now move to a DM timer
driver.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:36 +02:00
Philipp Tomsich
bc824cc03a dts: rk3368: make timer0 accessible for SPL and TPL
To use it with the DM timer driver in SPL and TPL, timer0 needs to be
marked as pre-reloc.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:36 +02:00
Philipp Tomsich
1168d2dd4b rockchip: timer: add device-model timer driver for RK3368 (and similar)
This adds a device-model driver for the timer block in the RK3368 (and
similar devices that share the same timer block, such as the RK3288) for
the down-counting (i.e. non-secure) timers.

This allows us to configure U-Boot for the RK3368 in such a way that
we can run with the secure timer inaccessible or uninitialised (note
that the ARMv8 generic timer does not count, if the secure timer is
not enabled).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:36 +02:00
Philipp Tomsich
e9e5d9d29f dm: timer: normalise SPL and TPL support
To fully support DM timer in SPL and TPL, we need a few things cleaned
up and normalised:
- inclusion of the uclass and drivers should be an all-or-nothing
  decision for each stage and under control of $(SPL_TPL_)TIMER
  instead of having the two-level configuration with TIMER and
  $(SPL_TPL_)TIMER_SUPPORT
- when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can
  not be compiled in

This normalises configuration to $(SPL_TPL_)TIMER and moves the config
options to drivers/timer/Kconfig (and cleans up the collateral damage
to some defconfigs that had SPL_TIMER_SUPPORT enabled).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:36 +02:00
Philipp Tomsich
b1a16002f2 timer: add OF_PLATDATA support for timer-uclass
The timer-uclass depends on full OF_CONTROL through its interrogation
of /chosen and the code to determine the clock-frequency.

For the OF_PLATDATA case, these code-paths are disabled and it becomes
the timer driver's responsibility to correctly set the clock-frequency
in the uclass priv-data.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:36 +02:00
Philipp Tomsich
b65236ae3a configs: mpc85xx: fix fallout from SPL/TPL changes
Splitting the feature selection for SPL and TPL, caused a few build
failures to mpx85xx boards.  This fixes the fallout by adding the
needed new option names to the respective defconfig files.

Signed-off-byL Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-13 17:12:35 +02:00
Klaus Goger
4ce8b4d6a7 rockchip: board: puma_rk3399: rename ATF firmware
prefix the bl31 firmware needed to build uboot.itb so it can coexist in
the build area with ATFs from other boards (i.e. lion_rk3368)

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:35 +02:00
Philipp Tomsich
12760080bc rockchip: board: puma-rk3399: fix warnings in puma_rk3399/fit_spl_atf.its
The ITS file generated warnings due to @<num> designations in the naming
which cause DTC to complain as follows:
  Warning (unit_address_vs_reg): Node /images/uboot@1 has a unit name, but no reg property
  Warning (unit_address_vs_reg): Node /images/atf@1 has a unit name, but no reg property
  Warning (unit_address_vs_reg): Node /images/pmu@1 has a unit name, but no reg property
  Warning (unit_address_vs_reg): Node /images/fdt@1 has a unit name, but no reg property
  Warning (unit_address_vs_reg): Node /configurations/conf@1 has a unit name, but no reg property

This removes the @<num> part from the names, as we only have a single
image for each payload aspect (and only a single configuration) anyway.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:35 +02:00
Philipp Tomsich
5aa49af311 moveconfig: migrate TPL_STACK, TPL_TEXT_BASE and TPL_MAX_SIZE
We can finally drop TPL_STACK, TPL_TEXT_BASE and TPL_MAX_SIZE off the
whitelist (this time it's really happening!) and migrate the setting
(only used on the RK3368-uQ7 so far) into Kconfig.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:35 +02:00
Philipp Tomsich
4cf4378ed0 rockchip: rk3368: mark TPL as not inheriting its stack, text-base and size from SPL
The RK3368 needs to have a different base-address and stack-pointer
for its TPL stage.  Now that we want to do this via Kconfig, we need
to tick the appropriate 'TPL_NEEDS_...' boxes.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:35 +02:00
Philipp Tomsich
faa18dbe25 armv8: TPL_STACK will always be defined, so test CONFIG_TPL_NEEDS_SEPARATE_STACK
Now that TPL_STACK has been moved off the whitelist (ok, I'm lying:
the 'moving off the whitelist' part comes in once moveconfig
runs... which will be a few commits down the line) and added to
Kconfig, we need to test CONFIG_TPL_NEEDS_SEPARATE_STACK to see
whether the value from TPL_STACK should be used or whether we try to
inherit whatever SPL uses.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:35 +02:00
Philipp Tomsich
b3ed6ce780 spl: support TPL_STACK, TPL_MAX_SIZE and TPL_TEXT_BASE via Kconfig
Let's clean up behind ourselves and move the (newly defined)
TPL_STACK, TPL_MAX_SIZE and TPL_TEXT_BASE into Kconfig.  Given that
0x0 might be considered to be valid values for TPL_TEXT_BASE and
TPL_STACK, we need to introduce helper config options
("TPL_NEEDS_SEPARATE_...") to indicate that these symbols are used
(and not inherited from their SPL variants) for any given
target-platform.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:34 +02:00
Philipp Tomsich
d9d1242b82 rockchip: Kconfig: preset TPL_LDSCRIPT via Kconfig for the RK3368
Set TPL_LDSCRIPT in Kconfig, so we don't have to pollute our
header file.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-13 17:12:34 +02:00
Philipp Tomsich
dd6fbcb938 spl: Kconfig: migrate $(SPL_TPL_)LDSCRIPT to Kconfig
Now that we have split up SPL_LDSCRIPT into a SPL and TPL variant and
have started to use the TPL-variant for the RK3368, it's time to clean
up behind ourselves: move both variants into Kconfig and remove them
from the whitelist.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:34 +02:00
Philipp Tomsich
4d02d20605 rockchip: board: lion-rk3368: add support for the RK3368-uQ7
The RK3368-uQ7 (codenamed 'Lion') is a micro-Qseven (40mm x 70mm,
MXM-230 edge connector compatible with the Qseven specification)
form-factor system-on-module based on the octo-core Rockchip RK3368.
It is designed, supported and manufactured by Theobroma Systems.

It provides the following features:
 - 8x Cortex-A53 (in 2 clusters of 4 cores each)
 - (on-module) up to 4GB of DDR3 memory
 - (on-module) SPI-NOR flash
 - (on-module) eMMC
 - Gigabit Ethernet (with an on-module KSZ9031 PHY)
 - USB
 - HDMI
 - MIPI-DSI/single-channel LVDS (muxed on the 'LVDS-A' pin-group)
 - various 'slow' interfaces (e.g. UART, SPI, I2C, I2S, ...)

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:34 +02:00
Philipp Tomsich
d16120a6de rockchip: spi: enable support for the rk_spi driver for the RK3368
For the RK3368, we can reuse the SPI driver (although we'll have to
eventually investigate whether it can be merged with the
designware_spi.c driver) also used for the RK3288 and RK3399.
This adds the necessary compatible string to support the RK3368.

Note that the assumption that GPLL will be clocked at 594MHz is not
true for the RK3368, but this will not lead to incorrect functioning
(just to a lower-than-expected SPI operating frequency): this has been
documented in the driver, so it doesn't cause any headaches when
someone next needs to touch the clock code of this driver.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:34 +02:00
Philipp Tomsich
5071457e44 rockchip: rk3368: spl: mark SPL and TPL as supported for ROCKCHIP_RK3368
With SPL and TPL support for the RK3368 in place, mark SPL and TPL as
supported from Kconfig for the RK3368.  As this is primarily tested on
the RK3368-uQ7, we'll leave it to board's individual defconfig to
enable.

Also enable DEBUG_UART_BOARD_INIT for the RK3368, so we get output
during the early boot-up, as we turn on TPL and SPL.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:34 +02:00
Philipp Tomsich
fbbd38001f rockchip: rk3368: spl: add SPL support
Adds SPL support for the RK3368 (assuming that our TPL stage has
initialised DRAM and set up the memory firewall).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:34 +02:00
Philipp Tomsich
9b0bc59366 rockchip: spl: make spl-boot-order code reusable (split from rk3399)
In order to reuse the support for the u-boot,spl-boot-order property
from the rk3399, we split it into a reusable module that can be
included by the SPL code for any of our boards.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:34 +02:00
Philipp Tomsich
a55e497156 rockchip: rk3368: spl: add TPL support
This adds the TPL support for the RK3368, including the u-boot-tpl.lds.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:33 +02:00
Philipp Tomsich
1c78740285 rockchip: rk3368: spl: enable SPL_FRAMEWORK in rk3368_common.h
To build TPL and SPL stages for the RK3368, we will also need to
enable the SPL_FRAMEWORK.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:33 +02:00
Philipp Tomsich
1ac973a193 rockchip: rk3368: dts: add DMC node in rk3368.dtsi
For full SPL support, including DRAM initialisation, we need a few
nodes from the DTS: this commit adds the DMC (DRAM controller) node,
the service_msch (memory scheduler) node and marks GRF, PMUGRF and CRU
as 'u-boot,dm-pre-reloc'.  In addition to this, we also include the
dt-binding for the DMC to allow DTS files including this DTSI to refer
to the symbolic constants for the DDR3 bin and for the
memory-schedule.

Note that the DMC contains both the memory regions for the
(Designware) protocol controller as well as the DDR PHY.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:33 +02:00
Philipp Tomsich
403e9cbcd5 rockchip: rk3368: add DRAM controller driver with DRAM initialisation
This adds a DRAM controller driver for the RK3368 and places it in
drivers/ram/rockchip (where the other DM-enabled DRAM controller
drivers for rockchip devices should also be moved eventually).

At this stage, only the following feature-set is supported:
 - DDR3
 - 32-bit configuration (i.e. fully populated)
 - dual-rank (i.e. no auto-detection of ranks)
 - DDR3-1600K speed-bin

This driver expects to run from a TPL stage that will later return to
the RK3368 BROM.  It communicates with later stages through the
os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR
init code).

Unlike other DMC drivers for RK32xx and RK33xx parts, the required
timings are calculated within the driver based on a target frequency
and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this
time).

The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0)
register for controlling the operation of its (single-channel) DRAM
controller in the GRF block.  This provides for selecting DDR3, mobile
DDR modes, and control low-power operation.
As part of this change, DDRC0_CON0 is also added to the GRF structure
definition (at offset 0x600).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:33 +02:00
Philipp Tomsich
832567d5aa rockchip: Makefile: streamline SPL/TPL configuration
Handling TPL and SPL in the Makefile for mach-rockchip was based on
nested if checks and/or if-else-if paths.  This can be simplified and
made more readable by using $(SPL_TPL_) and by introducing
intermediate variables for the aggregation of SPL and TPL features.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:33 +02:00
Philipp Tomsich
793f2fd2dc net: gmac_rockchip: Add support for the RK3368 GMAC
The GMAC in the RK3368 once again is identical to the incarnation in
the RK3288 and the RK3399, except for where some of the configuration
and control registers are located in the GRF.

This adds the RK3368-specific logic necessary to reuse this driver.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-13 17:12:33 +02:00
Philipp Tomsich
cf8aceb1c9 rockchip: clk: rk3368: add support for configuring the SPI clocks
As SPI support may be useful in the boot-flow, this adds support for
configuring the SPI controller's clocks in the RK3368 clock driver.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:33 +02:00
Philipp Tomsich
4e4c40df30 rockchip: clk: rk3368: mark 'priv' __maybe_unused in rk3368_clk_set_rate()
With the clock support in rk3368_clk_set_rate() conditionalized on
various feature definitions, 'priv' can remain unused (e.g. in the
SPL build when only MMC is enabled).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:32 +02:00
Philipp Tomsich
df0ae00041 rockchip: clk: rk3368: add support for GMAC (SLCK_MAC) clock
To enable the GMAC on the RK3368, we need to set up the clocking
appropriately to generate a tx_clk for the MAC.

This adds an implementation that implements the use of the <&ext_gmac>
clock (i.e. an external 125MHz clock for RGMII provided by the PHY).
This is the clock setup used by the boards currently supported by
U-Boot (i.e. Geekbox, Sheep and RK3368-uQ7).

This includes the change from commit
 - rockchip: clk: rk3368: define GMAC_MUX_SEL_EXTCLK

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:32 +02:00
Philipp Tomsich
6292469073 rockchip: clk: rk3368: support configuring the DRAM PLL (from TPL)
As part of the DRAM initialisation process (running as part of the TPL
stage) on the RK3368, we need to set up the DRAM PLL.

This implements support for configuring the PLL to for 1200, 1332 or
1600 MHz (i.e. for DDR3-1200, DDR3-1333, DDR3-1600 operating modes).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:32 +02:00
Philipp Tomsich
f5a432959a rockchip: clk: rk3368: implement MMC/SD clock reparenting
The original clock support for MMC/SD cards on the RK3368 suffered
from a tendency to select a divider less-or-equal to the the one
giving the requested clock-rate: this can lead to higher-than-expected
(or rather: higher than supported) clock rates for the MMC/SD
communiction.

This change rewrites the MMC/SD clock generation to:
 * always generate a clock less-than-or-equal to the requested clock
 * support reparenting among the CPLL, GPLL and OSC24M parents to
   generate the highest clock that does not exceed the requested rate

In addition to this, the Linux DTS uses HCLK_MMC/HCLK_SDMMC instead of
SCLK_MMC/SCLK_SDMMC: to match this (and to ensure that clock setup
always works), we adjust the driver appropriately.

This includes the changes from:
 - rockchip: clk: rk3368: convert MMC_PLL_SEL_* definitions to shifted-value form

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:32 +02:00
Philipp Tomsich
05c57e12d1 rockchip: clk: rk3368: define DMA1_SRST_REQ and DMA2_SRST_REQ
On he RK3368, we need to temporarily disable security on the DMA
engines during TPL and SPL to allow the MMC host to DMA into DRAM.  To
do so, we need to reset the two DMA engines, which in turn requires
the DMA1_SRST_REQ and DMA2_SRST_REQ constants to refer to the
appropriate bits in the CRU.

As the ATF correctly initialises security (and only leaves EL3 after
doing so), this can not pose a security issue.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:32 +02:00
Philipp Tomsich
a00dfa042d rockchip: clk: rk3368: implement DPLL (DRAM PLL) support
To implement a TPL stage (incl. its DRAM controller setup) for the
RK3368, we'll want to configure the DPLL (DRAM PLL).

This commit implements setting the DPLL (CLK_DDR) and provides PLL
configuration details for the common DRAM operating speeds found on
RK3368 boards.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:32 +02:00
Philipp Tomsich
4bebf94e85 rockchip: clk: rk3368: do not change CPLL/GPLL before returning to BROM
The RK3368 has a somewhat temperamental BootROM (which I learned the
hard way) when it comes to reconfiguring the CPLL and GPLL (in fact,
experiments show that changing the GPLL broke things for me, while
changing the CPLL seems to be more benign).  These should not be
modified by the SPL stage, if we intend to return to the BootROM for
chain booting the next stage.

This commit changes the clock initialisation to not change CPLL/GPLL
before returning to the BootROM (i.e. in TPL).  As it's safe to change
these settings if we no longer intend to return to U-Boot, we'll run
the full PLL setup a little later (i.e. in SPL).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:32 +02:00
Philipp Tomsich
bee6180126 rockchip: clk: rk3368: support OF_PLATDATA for the RK3368 clk driver
With the RK3368's limited TPL size, we'll want to use OF_PLATFDATA for
the SPL stage.  This implements support for OF_PLATDATA in the clock
driver for the RK3368.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:30 +02:00
Philipp Tomsich
ddfe77df15 rockchip: clk: rk3368: implement bandwidth adjust for PLLs
The RK3368 TRM recommends to configure the bandwith adjustment (CON2)
for PLLs to NF/2.  This implements this for all reconfigurations of
PLLs and removes the 'has_bwadj' flag (as the RK3368 always has the
bandwidth-adjustment feature according to its manual).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:28 +02:00
Philipp Tomsich
e95b6312e5 rockchip: pinctrl: rk3368: add SPI support
To implement pinctrl support for the RK3368, we need to add the
bit-definitions to configure the IOMUX and tie these into the
pinctrl framework. This also adds the mapping from the IRQ# back
onto the periheral id for the SPI devices.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:25 +02:00
Philipp Tomsich
a49773d6cf rockchip: pinctrl: rk3368: move IOMUX bit-definitions to pinctrl driver
There is no real reason to keep the bit-definitions for the IOMUX in
the grf header file (which defines the register layout of the GRF block):
these should only be used by our pinctrl driver (with the possible
exception of early debug-init code in TPL/SPL).

This moves the relevant definitions from the grf_rk3368.h header
into the pinctrl driver pinctrl_rk3368.c.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:24 +02:00
Philipp Tomsich
abcde4751e rockchip: pinctrl: rk3368: add support for configuring the MMC pins
The RK3368 has two SD/MMC controllers that can be used from U-Boot
both during SPL and for booting an OS from the full bootloader stage.
While both are configured to (mostly) sensible settings from the BROM,
additional configuration for the MMC controller is needed to configure
it to 8bit mode.

This adds pinctrl support for the MMC controller.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:23 +02:00
Philipp Tomsich
5282a3f162 rockchip: pinctrl: rk3368: add GMAC (RGMII only) support
To add GMAC (Gigabit Ethernet) support (limited to RGMII only at this
point), we need support for additional pin-configuration.  This commit
adds the pinctrl support for GMAC in RGMII mode:
 * adds a PERIPH_ID_GMAC and the mapping from IRQ number to PERIPH_ID
 * configures the RGMII pins

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:23 +02:00
Philipp Tomsich
8f362dbb41 rockchip: rk3368: dts: add sgrf node
We will to drop device security temporarily (until the ATF initialises
it fully) from the TPL/SPL stage: this requires access to some
registers in the SGRF.

This adds the sgrf node to the rk3368.dtsi, so we can then bind a
syscon device onto it and access its memory ranges.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:23 +02:00
Philipp Tomsich
c1828cf7ab rockchip: rk3368: grf: use shifted-constants
The RK3368 GRF header was still defines with a shifted-mask but with
non-shifted function selectors for the IOMUX defines.  As the RK3368
support is still fresh enough to allow a quick change, we do this now
before having more code use this.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-13 17:12:23 +02:00
Philipp Tomsich
81bd0ad07c rockchip: rk3368: syscon: SGRF support for OF_PLATDATA
In TPL we will need to configure security in the SGRF of the RK3368.
This change adds support for the SGRF as a syscon device, so we can
retrieve its address range through the syscon API in TPL (and can
avoid having to hard-code the address).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:22 +02:00
Philipp Tomsich
66a63fec81 rockchip: rk3368: syscon: MSCH/PMUGRF/GRF support for OF_PLATDATA
The RK3368 has both a limited TPL size (just 0x7000 bytes) and the
added challenge of booting in AArch64, which increases the code size
for TPL (particularily when using the LP64 programming model).  For
this reason we expect the RK3368 to always use OF_PLATDATA for its
TPL stage.

This change adds support for the MSCH, PMUGRF and GRF register regions
in syscon, which are necessary for initialising the RK3368's DRAM
controller.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:22 +02:00
Philipp Tomsich
c61177aa10 rockchip: rk3368: spl: add memory layout for TPL and SPL
For the RK3368, we use a multi-stage boot-process consisting of the
following:
  1.  TPL: initalises DRAM, returns to boot-ROM (which then loads
           the next stage and transfers control to it)
  2.  SPL: a full-features SPL stage including OF_CONTROL and FIT
           image loading, which fetches the ATF, DTB and full U-Boot
	   and then transfers control to the ATF (using the BL31
	   parameter block to indicate the location of BL33/U-Boot)
  3.  ATF: sets up the secure world and exits to BL33 (i.e. a full
           U-Boot) in the normal world
  4.  full U-Boot

TPL/SPL and the full U-Boot are built from this tree and need to
run from distinct text addresses and with distinct initial stack
pointer addresses.

This commit sets up the configuration to run:
  -  TPL from the SRAM at 0xff8c0000 (note that the first 0x1000
     	 are reserved for use by the boot-ROM and contain the SP
	 when the TPL is entered)
  -  SPL from DRAM at 0x0
  -  U-Boot from DRAM at 0x200000

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:22 +02:00
Philipp Tomsich
e78b04f9d5 rockchip: rk3368: spl: define COUNTER_FREQUENCY to 24MHz
The BootROM of the RK3368 Boot ROM does not initialise cntfrq_el0.
This change defines COUNTER_FREQUENCY, which is used by the AArch64 init
code in arch/arm/cpu/armv8/start.S to set up cntfrq_el0.

If the counter-frequency is not correctly set up, the calculation of
delays using the ARMv8 generic timer can not work correctly.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:22 +02:00
Philipp Tomsich
525a8c8f2c rockchip: rk3368: pmugrf: add definitions for os_reg[0..3]
On the RK3368 we use a TPL-stage similar to Rockchip's DDR init
(i.e. it initialises DRAM, leaves some info for the next stage and
returns to the BootROM).  To allow compatibility with Rockchip's DDR
init code, we use the same register os_reg2 in pmugrf for passing
this info (i.e. DRAM size and configuration) between stages.

This change adds the definitions for os_reg[0] through os_reg[3] to
the pmugrf structure for the RK3368.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:22 +02:00
Philipp Tomsich
0da5c2e779 rockchip: rk3368: mkimage: add support for the RK3368
This commit adds support for RK3368 SoC in mkimage.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:22 +02:00
Philipp Tomsich
9a8f009f24 rockchip: rk3368: improve Kconfig text for the RK3368
The RK3368 option in Kconfig referred to the RK3328 (copy-and-paste)
and had a few typos and unnecessarily used UTF-8 characters.  While
fixing this, I also reformatted and further clarified the text
(e.g. made the grouping into a a big and little cluster of 4 cores
each explicit).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:22 +02:00
Philipp Tomsich
9e27c816a8 rockchip: Makefile: allow selective inclusion of sdram_common.o from TPL/SPL/U-Boot
The utility functions in sdram_common.c will be useful both for some
SPL implementations (and if unused, the linked will discard these
anyway) and for the full U-Boot stage.

This changes selects sdram_common.o through the $(SPL_TPL_) macro to
allow better control of its inclusion through the CONFIG_ROM,
CONFIG_SPL_RAM or CONFIG_TPL_RAM options.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:22 +02:00
Philipp Tomsich
87c16d49a6 drivers: spl: consistently use the $(SPL_TPL_) macro
To simplify drivers/Makefile a bit when using TPL/SPL, we consistently
use the $(SPL_TPL_) macro to test for drivers that have separate
configuration symbols for the full U-boot, SPL and TPL stages.
Instead of explicitly repeating them in two separate if-guarded
sections of the Makefile, we can now simply list these options once.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13 17:12:21 +02:00
Philipp Tomsich
c3916e7bdb spl: add TPL_DRIVER_MISC_SUPPORT option
This adds the TPL_DRIVER_MISC_SUPPORT option to allow activation of
DRIVER_MISC_SUPPORT for devices that need it in the TPL stage.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13 17:12:21 +02:00
Philipp Tomsich
f94e643ef9 spl: consistently use $(SPL_TPL_) to select features for SPL and TPL builds
To allow for a finer-grained control of features for TPL and SPL
builds all modules/boot-methods/etc. need to be consistently selected
based on the $(SPL_TPL_) macros.

This allows splitting the associated config-options in Kconfig: we
don't split the Kconfig options here and now, as this should happen on
an as-needed basis, whenever someone needs a feature/boot-method/etc.
in their TPL.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13 17:12:21 +02:00
Philipp Tomsich
6dced7dffc lib: spl: differentiate between TPL and SPL for libfdt/of_control/of_platdata
This splits the compilation of code modules for TPL and SPL for
OF_CONTROL (and related) features between TPL and SPL.  The typical
use-case of this is a TPL stage that uses OF_PLATDATA at TPL and
provides full OF_CONTROL at SPL (e.g. on the RK3368).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13 17:12:21 +02:00
Philipp Tomsich
d60b5f74fd spl: Kconfig: split SYS_MALLOC_SIMPLE for TPL and SPL
As include/malloc.h already checks for SYS_MALLOC_SIMPLE using the
CONFIG_IS_ENABLED macro, we need to move to having separate entries
as we switch to fully separate configuration for SPL and TPL.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13 17:12:21 +02:00
Philipp Tomsich
1749858a64 spl: allow a separate TEXT_BASE, LDSCRIPT and MAX_SIZE for TPL
For the bringup of the RK3368, we need to support TPL and SPL running
from different addresses... which requires both stages to use a
distinct TEXT_BASE.

This commit adds support for having a separate LDSCRIPT for TPL (which
is expected to make use of the TPL_MAX_SIZE define) and for having a
the option of defining TPL_TEXT_BASE and having the TPL stage linked
against this address.

Note that the handling of the TEXT_BASE is designed to not interfere
with the previous assumption that SPL_TEXT_BASE should be used for TPL
as well, unless TPL_TEXT_BASE is defined.  For this reason, the test
in Makefile.spl uses the following (seemingly redundant checks):
 1. looks for $(SPL_TPL_)TEXT_BASE
 2. looks for SPL_TEXT_BASE (even when building in TPL)

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:21 +02:00
Philipp Tomsich
c3be6190f9 armv8: spl: Support separate stack for TPL
To allow a TPL and SPL to run from different addresses/memories, we
need to split setup of the TPL and SPL stacks.  To do so, we introduce
CONFIG_TPL_STACK (not listed in Kconfig) which can be used to override
the initial stack pointer for TPL.

To provide backward compatibility for existing boards, this is added
as an optional configuration item and the normal search order (i.e.
SPL_STACK, then SYS_STACK) apply if not defined.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13 17:12:21 +02:00
Philipp Tomsich
e6a0586277 armv8: move low-level assembly functions into function-sections
TPL builds today don't need to call into firmware or set up the MMU
(if this changes, it should be controlled through a config option
whether to include this or not), but include the needed support code
for this anyway.  By moving these unused low-level functions into
seperate function-sections, the linker can garbage-collect the unused
sections.

Note that (if DM support is enabled), there will be a call to the
cache-flushing code from alloc_priv(...) in drivers/core/device.c.
This then add 52 bytes of binary size (an increase from 20589 to 20641
bytes) compared to completely removing this code.

Even for a feature-rich TPL (including DM support as for the RK3368),
this equates to a size difference of significantly more than 10% in
TPL binary size.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:21 +02:00
Philipp Tomsich
f1c6e1922e spl: dm: use CONFIG_IS_ENABLED to test for the DM option
Even though there's now a TPL_DM configuration option, the spl logic
still checks for SPL_DM and thus does not pick up the proper config
option.

This introduces the use of CONFIG_IS_ENABLED(DM) in spl.c to always
pick up the desired configuration option instead of having a
hard-coded check for the SPL variant.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13 17:12:20 +02:00
Philipp Tomsich
f291ce1298 spl: dm: Kconfig: split OF_CONTROL and OF_PLATDATA between SPL and TPL
For the RK3368, we want to use OF_PLATDATA in TPL, but full OF_CONTROL
in SPL: this requires the introduction of a new family of
configuration options to decouple SPL_OF_CONTROL and SPL_OF_PLATDATA
from TPL.

Consequently, Makefile.spl needs to be adjusted to test for these
configuration items through the $(SPL_TPL_) macro instead of
hard-coding the SPL variant.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13 17:12:20 +02:00
Philipp Tomsich
7c819e7f22 spl: dm: Kconfig: split CLK support for SPL and TPL
Introduce TPL_CLK to allow finer-grained selection of TPL features
for feature-rich (i.e. DM-based) TPL stages.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13 17:12:20 +02:00
Philipp Tomsich
f0776a5517 spl: dm: Kconfig: SPL_CLK depends on SPL_DM
SPL_CLK should also depend on SPL_DM (and not just on CLK).
Add the additional dependency.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13 17:12:20 +02:00
Philipp Tomsich
c336c3c35f spl: dm: Kconfig: introduce TPL_RAM (in analogy to SPL_RAM)
To allow finer grained selection of features for TPL, we introduce
TPL_RAM (in analogy to SPL_RAM).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13 17:12:20 +02:00
Philipp Tomsich
45233301b6 spl: dm: Kconfig: SPL_RAM depends on SPL_DM
This commit models the dependency from SPL_RAM to SPL_DM in Kconfig.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13 17:12:20 +02:00
Philipp Tomsich
c6ac6c1bd4 spl: dm: Kconfig: split REGMAP/SYSCON support for TPL from SPL
This change introduces TPL variants of the REGMAP and SYSCON config
options (i.e. TPL_REGMAP and TPL_SYSCON in analogy to SPL_REGMAP and
SPL_SYSCON) in preparation of a finer-grained feature selection for
building feature-rich TPL variants.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13 17:12:20 +02:00
Philipp Tomsich
9c447370c1 spl: dm: Kconfig: use more specific prereqs for SPL_REGMAP and SPL_SYSCON
SPL_REGMAP and SPL_SYSCON were marked as depending on DM, when a
stricter dependency of SPL_DM was possible.  This commit makes the
prereq more specific.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13 17:12:20 +02:00
Philipp Tomsich
616bd09e79 spl: dm: Kconfig: fix help text for SPL/TPL confusion
TPL_NAND_SUPPORT, TPL_SERIAL_SUPPORT, TPL_SPI_FLASH_SUPPORT and
TPL_SPI_SUPPORT refer to SPL in their help text.  This fixes up
the description to correctly reference TPL.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:20 +02:00
Philipp Tomsich
ae2cee2e34 spl: use TPL_SYS_MALLOC_F_LEN for TPL
The (upstream) changes to break up SYS_MALLOC_F_LEN for the full
U-Boot and the SPL stage, break TPL (if simple malloc is enabled in
TPL).

This adds support for a TPL-variant of SYS_MALLOC_F_LEN:
- adds TPL_SYS_MALLOC_F_LEN
- rewrites a test for CONFIG_SPL_SYS_MALLOC_F_LEN to access
  CONFIG_VAL(SYS_MALLOC_F_LEN)

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:19 +02:00
Philipp Tomsich
19b68fb280 rockchip: back-to-bootrom: simplify the #ifdef-check for LIBCOMMON in TPL/SPL
With the finer-grained control over LIBCOMMON_SUPPORT for TPL/SPL (i.e.
with the newly introduced distinction between TPL_LIBCOMMON_SUPPORT and
SPL_LIBCOMMON_SUPPORT), we can simplify the #ifdef-check to simply use
CONFIG_IS_ENABELD.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up to use 'puts' and LIBCOMMON:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13 17:12:19 +02:00
Philipp Tomsich
ee14d29db0 rockchip: back-to-bootrom: split BACK_TO_BOOTROM for TPL/SPL
The back-to-bootrom option is rather unfortunately named
  CONFIG_ROCKCHIP_SPL_BACK_TO_BOOTROM
instead of
  CONFIG_SPL_ROCKCHIP_BACK_TO_BOOTROM

To make is selectable through CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BOOTROM),
we need to rename it.  At the same time, we introduce a TPL_ variant of
the option to give us finer-grained control over when it should be used.

This change is motivated by our RK3368 boot process, which returns to
the boot ROM only from the TPL stage, but not from the SPL stage.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[added fix-up for evb-rk3229_defconfig and phycore-rk3288_defconfig:]
[fixed inverted CONFIG_IS_ENABLED test for rk3288:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

include/configs/rock.h: undef
2017-08-13 17:12:19 +02:00
Philipp Tomsich
36979c7e56 rockchip: back-to-bootrom: add 'back-to-bootrom' support for AArch64
The back-to-bootrom support for Rockchip is equivalent to an
(assembly) implementation of setjmp/longjmp (i.e. it saves the
stack-pointer, link-register and callee-saved registers). Up until
now, this had only been implemented for AArch32 (i.e. ARMv7 or older),
which puts the new ARMv8 devices (which boot in AArch64 mode) at a
slight disadvantage.

To allow use of the 'back-to-bootrom' feature on new devices (e.g. the
RK3368), this commit adds an implementation for AArch64.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13 17:12:19 +02:00
Philipp Tomsich
a954fa3203 spl: configure 'return to bootrom' separately for SPL and TPL
On the RK3368, we want our TPL to use the 'return to bootrom' boot
method (to have the bootrom load up the SPL stage) and then continue
with different boot methods (MMC, SPI, etc.) from SPL.

This adds the config option needed to control the availabily of the
'return to bootrom' boot-method separately for the TPL stage.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13 17:12:19 +02:00
Philipp Tomsich
225d30b708 spl: add a 'return to bootrom' boot method
Some devices (e.g. the RK3368) have only limited SRAM, but provide
support for loading the next boot stage after our SPL performs basic
setup (e.g. DRAM).

For target systems like these, we add a boot device BOOTROM that will
invoke a board-specific hook to return to the bootrom (if supported).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:19 +02:00
Adam Ford
a41e3e1480 OMAP3_SPI: Kconfig: move OMAP3_SPI out of DM_SPI section.
The OMAP3_SPI driver can work with or without DM_SPI.  Moving this
outside of the #if DM_SPI section allows us to include it on boards
that don't support DM_SPI yet.

Signed-off-by: Adam Ford <aford173@gmail.com>
2017-08-12 19:17:20 -04:00
xypron.glpk@gmx.de
b730ff3fd6 omap3: incorrect logical check in do_emif4_init
((readl(&emif4_base->sdram_iodft_tlgc) & (1<<10)) == 0x01)
is always false.
This does not match the comment
/*Wait till that bit clears*/

The problem was indicated by cppcheck.

I do not have the hardware to test if the code change below
leads to a correct system behavior.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-12 19:17:20 -04:00
Derald D. Woods
da0227f7d2 arm: omap: Fix 'get_device_type()' for OMAP34XX
Fixes: 00bbe96eba ("arm: omap: Unify get_device_type() function")

The control status register value is embedded in a structure somewhere
in SRAM, with the last refactoring effort. This patch allows OMAP3 EVM
(TMDSEVM3530) to boot again using the known control register base and
offset for 'readl', for the OMAP34XX case.

Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
[trini: Change to if/else, add comment about it.]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-12 18:56:26 -04:00
Adam Ford
5bbc265bec Convert CONFIG_NAND to Kconfig
This converts the following to Kconfig:
   CONFIG_NAND

Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Sync up a few more, add imply's]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-12 09:18:47 -04:00
xypron.glpk@gmx.de
a44bffcc95 efi_loader: use EFI_PAGE_SIZE instead of 4096
We should use constant EFI_PAGE_SIZE instead of 4096 where the
coding relies on 4096 being EFI_PAGE_SIZE.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-08-12 14:06:23 +02:00
xypron.glpk@gmx.de
aee4f06dff efi_loader: use EFI_PAGE_MASK instead of EFI_PAGE_SIZE - 1
We should be consistent in the way we calculate page sizes.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-08-12 14:05:45 +02:00
Derald D. Woods
0d43fded20 omap3: evm: Update board, defconfig, and maintainer file
This patch brings the OMAP3 EVM to a bootable state, on master, as of
v2017.09-rc1.

Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-11 17:44:54 -04:00
Simon Glass
00fd59dd1a README: Drop information about commands
Most of this is duplicated in Kconfig help. Add some of that which is not,
and remove the help from the README.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 17:44:54 -04:00
Simon Glass
e188eee7a4 Drop config_cmd_all.h
This file does not include all commands and has not for a while. Let's
drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 17:44:53 -04:00
Simon Glass
54feea17d6 Convert CONFIG_CMD_ZFS to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_ZFS

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 17:44:53 -04:00
Simon Glass
e7a815f32e Convert CONFIG_CMD_ZBOOT to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_ZBOOT

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 17:44:53 -04:00
Simon Glass
1aa4e8d0de Convert CONFIG_CMD_UUID to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_UUID

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 17:44:52 -04:00
Simon Glass
2a242e3e80 Convert CONFIG_CMD_UNIVERSE to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_UNIVERSE

Since no board uses this, perhaps we should drop this command?

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 17:44:52 -04:00
Simon Glass
5605aa8ab6 Convert CONFIG_CMD_TSI148 to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_TSI148

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 17:44:51 -04:00
Simon Glass
ce058ae5f2 Convert CONFIG_CMD_TRACE to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_TRACE

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 17:44:51 -04:00
Simon Glass
7a76431845 Convert CONFIG_CMD_YAFFS2 to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_YAFFS2

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 17:44:50 -04:00
Simon Glass
9b92a8d76a Convert CONFIG_CMD_THOR_DOWNLOAD to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_THOR_DOWNLOAD

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 17:44:46 -04:00
Simon Glass
78d11b7040 Kconfig: Drop CONFIG_CMD_TFTP
This is not a valid CONFIG option. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 15:42:01 -04:00
Simon Glass
3cef3b3185 Convert CONFIG_CMD_TERMINAL to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_TERMINAL

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 15:42:00 -04:00
Simon Glass
90d99e5936 Convert CONFIG_CMD_TCA642X to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_TCA642X

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 15:42:00 -04:00
Simon Glass
1c27a4c949 gpio: Drop sx151x driver
This driver is not used in U-Boot. Drop it and its associated CONFIG
options.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 15:42:00 -04:00
Simon Glass
00805d7ad8 Convert CONFIG_CMD_STRINGS to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_STRINGS

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 15:41:59 -04:00
Simon Glass
ba71be547c Kconfig: Sort the memory commands
These are currently not quite in alphabetical order. Before adding more,
sort them. Not all options have a CMD_ prefix, so ignore that when
sorting.

Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 15:41:59 -04:00
Simon Glass
3a91a25376 Convert CONFIG_CMD_SPL_WRITE_SIZE to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_SPL_WRITE_SIZE

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 15:41:58 -04:00
Simon Glass
203dc1b3a8 Convert CONFIG_CMD_SPL_NAND_OFS to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_SPL_NAND_OFS

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 15:41:58 -04:00
Simon Glass
72c3033fd1 Convert CONFIG_CMD_SPL to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_SPL

Note that trats does not actually use SPL, so this option can no-longer be
set.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 15:41:57 -04:00
Simon Glass
2a728f3a1e Convert CONFIG_CMD_SH_ZIMAGEBOOT to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_SH_ZIMAGEBOOT

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 15:41:57 -04:00
Simon Glass
719d36ee36 Convert CONFIG_CMD_SF_TEST to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_SF_TEST

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 15:41:56 -04:00
Simon Glass
efce2442d3 Convert CONFIG_CMD_SDRAM to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_SDRAM

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 15:41:56 -04:00
Simon Glass
0941f597a2 Convert CONFIG_CMD_SCSI to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_SCSI

Also update the Makefile to use CONFIG_CMD_SCSI instead of CONFIG_SCSI to
enable the command, fixing an earlier error.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[trini: Rework to default y if SCSI, drop cl-som-am57x which did not use
CMD_SCSI for real]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-11 15:41:55 -04:00
Simon Glass
15dc63d646 Convert CONFIG_CMD_SAVES to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_SAVES

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 15:41:55 -04:00
Simon Glass
5d47099fea Kconfig: sandbox: Drop CONFIG_CMD_SANDBOX option
This is no-longer used. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 15:41:54 -04:00
Simon Glass
f8803a99fe Convert CONFIG_CMD_REISER to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_REISER

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 15:41:54 -04:00
Christophe Leroy
fa379223cd Convert CONFIG_CMD_REGINFO to Kconfig
This patch converts CONFIG_CMD_REGINFO to Kconfig

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 15:41:53 -04:00
Simon Glass
b75dfd2d46 Kconfig: Convert CMD_READ to Kconfig
Convert this option and enable it in sandbox. Also correct a bug which
was introduced with the block-device driver model conversion.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 15:41:53 -04:00
Simon Glass
6f62d7c4f7 Kconfig: Drop CONFIG_CMD_PORTIO and associated command
This command is not used by any board. It also looks quite similar to the
'iod' and 'iow' commands which use the correct I/O macros.

Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 15:41:52 -04:00
Simon Glass
7f6665554a Convert CONFIG_CMD_PCMCIA to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_PCMCIA

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 15:41:52 -04:00
Simon Glass
3abe4e6d9c Kconfig; Drop CONFIG_IDE_TI_CARDBUS and associated driver
This driver is not used by any board. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 15:41:51 -04:00
Simon Glass
186424248d Kconfig: Drop CONFIG_CMD_PCI_ENUM
This option enables the 'pci enum' command. It is only enabled by a few
board and these have not yet been converted to driver model, which always
enables this command. It seems easiest to just remove this option.

The affected boards can be converted to use driver model for PCI if
needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 15:41:51 -04:00
Simon Glass
6500ec7a5a Convert CONFIG_CMD_PCI to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_PCI

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 15:41:50 -04:00
Simon Glass
ba7cc6c6c5 Kconfig: Drop CONFIG_CMD_PCA953X_INFO
It does not seem worth having an option to enable another sub-command in
this legacy driver. Drop this option so that the sub-command is always
available.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 15:41:50 -04:00
Simon Glass
0091362ce5 Convert CONFIG_CMD_PCA953X to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_PCA953X

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 15:41:50 -04:00
Simon Glass
978f0854da Convert CONFIG_CMD_ONENAND to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_ONENAND

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 15:41:49 -04:00
Simon Glass
cb70e6cb8d Convert CONFIG_CMD_MTDPARTS_SPREAD to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_MTDPARTS_SPREAD

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[trini: Make this a bool not a string]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-11 15:41:30 -04:00
Jagan Teki
7e4bef711e sun50i: a64: Sync Linux [oe]hci0 nodes
Synced ohci0 and ehci0 nodes from Linux for sun50i-a64.dtsi

Here is the Linux last merge tag details:
Merge: 0e91f43d e5770b7
Author: Stephen Rothwell <sfr@canb.auug.org.au>
Date:   Fri Jun 9 14:59:55 2017 +1000

    Merge remote-tracking branch 'staging/staging-next'

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-08-11 21:51:43 +05:30
Simon Glass
f38c5f526c Convert CONFIG_CMD_MMC_SPI to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_MMC_SPI

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 11:36:00 -04:00
Simon Glass
0c19b4d180 Kconfig: Sort the device-access commands
These are currently not quite in alphabetical order. Before adding more,
sort them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 11:35:59 -04:00
Simon Glass
493f420e14 Kconfig: Drop CONFIG_CMD_MEM
This is not actually used in U-Boot. Most likely it means
CONFIG_CMD_MEMORY so change all occurences to that.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 11:34:15 -04:00
Simon Glass
241d281853 Convert CONFIG_CMD_MAX6957 to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_MAX6957

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 11:34:14 -04:00
Cooper Jr., Franklin
b7695c0e59 board: ks2: README: Update NAND wording
Traditional KS2 devices supported NAND via the AEMIF peripheral. However,
66AK2G doesn't use the AEMIF but rather the GPMC for NAND. Therefore,
clarify some statements to indicate only certain devices have AEMIF and
in other places just say NAND instead of AEMIF NAND

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
2017-08-11 11:34:13 -04:00
Heiko Schocher
21fd01b8b5 at91, smartweb: use SPL_SYS_MALLOC_F_LEN
commit f1896c45cb: spl: make SPL and normal u-boot stage use independent SYS_MALLOC_F_LEN
introduced independent SYS_MALLOC_F_LEN for SPL and U-Boot.

Use it on the smartweb board, as above commit broke
the smartweb board.

Signed-off-by: Heiko Schocher <hs@denx.de>
2017-08-11 11:34:12 -04:00
Adam Ford
f07515578b OMAP3: omap3logic: Fix DDR Pin Mux
The 512 MB DDR version of SOM's use CS0 and CS1.  CS1 is not correctly
setup in the pin muxing.  This causes erratic behavior on suspend/resume

This fix has been tested on both 256 and 512 MB DDR versions.

Signed-off-by: Adam Ford <aford173@gmail.com>
2017-08-11 11:34:10 -04:00
Tom Rini
40c8d26a4d travis-ci: Emulate 'make tests'
The 'tests' target will run sandbox, sandbox_spl and sandbox_flattree in
test.py and in the case of sandbox_spl ensure that we just run the
specific tests for that build.  Update our matrix to perform similar
test.py runs.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-11 11:34:09 -04:00
Tom Rini
877a1a35b3 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-11 11:20:19 -04:00
Rob Clark
3d9880784e efi_loader: GOP fix for no display
uclass_first_device() returns 0 if there is no device, but error if
there is a device that failed to probe.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-08-11 13:49:23 +02:00
Tom Rini
7f513e8196 Merge git://git.denx.de/u-boot-fsl-qoriq 2017-08-11 07:10:18 -04:00
Icenowy Zheng
a8df97d0da sunxi: add MACPWR in Orange Pi PC2 defconfig
The Ethernet function is enabled in the Orange Pi PC2 device tree and
defconfig, however, CONFIG_MACPWR is not properly set, which left the
PHY being disabled when booting, which makes the Ethernet function not
usable.

Add the proper value of this option in the PC2 defconfig.

Fixes: e7bd15ea15 ("sunxi: Add OrangePi PC 2 initial support")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-11 15:53:27 +05:30
Icenowy Zheng
e37a1b17e7 sunxi: switch PRCM to non-secure on H3/H5 SoCs
The PRCM of H3/H5 SoCs have a secure/non-secure switch, which controls
the access to some clock/power related registers in PRCM.

Current Linux kernel will access the CPUS (AR100) clock in the PRCM
block, so the PRCM should be switched to non-secure.

Add code to switch the PRCM to non-secure.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-11 15:49:39 +05:30
Icenowy Zheng
39858b12cc sunxi: add PRCM secure switch register definition
Some new Allwinner SoCs' PRCM has a secure switch register, which
controls the access to some clock and power registers in PRCM block.

Add the definition of this register and its bits in the PRCM header
file.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Tested-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-11 15:49:39 +05:30
Clément Bœsch
8792a64d87 sunxi: reduce Orange Pi Zero DRAM clock speed
Using `fel-boot-lima-memtester-on-orange-pi-pc 672` on an Orange Pi
without heatsink results in the following error after a few minutes:
  WRITE FAILURE: 0x00200000 != 0xffdfffff at offset 0x0137f47c (bitflip).

Also, the constructor repository (github/orangepi-xunlong) seems to
contain that 624 Mhz clock speed in its u-boot fork. It may be that 672
Mhz is the advertized overclocked speed.

According to http://linux-sunxi.org/Orange_Pi_PC#DRAM_clock_speed_limit
it may be worth decreasing that value with other Orange Pi boards.

See also e7d6aa0b74.

Signed-off-by: Clément Bœsch <u@pkh.me>
[Add s-o-b line]
Signed-off-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-11 15:43:44 +05:30
Olliver Schinagl
335d30050b sun7i: Add support for Olimex A20-OLinuXino-LIME2-eMMC
This patch adds support for the Olimex OLinuXino Lime2 with eMMC flash
storage.
https://www.olimex.com/Products/OLinuXino/A20/A20-OLinuXino-LIME2-eMMC/

It is a assembly variant of the regular Lime2 but featuring eMMC for
storage.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-11 15:16:39 +05:30
Emmanuel Vadot
fb7fe04da2 ARM: dts: sunxi: Change node name for pwrseq pin on Olinuxino-lime2-emmc
The node name for the power seq pin is mmc2@0 like the mmc2_pins_a one.
This makes the original node (mmc2_pins_a) scrapped out of the dtb and
result in a unusable eMMC if U-Boot didn't configured the pins to the
correct functions.

Signed-off-by: Emmanuel Vadot <manu@bidouilliste.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-11 15:16:39 +05:30
Rob Clark
796a78cbe5 efi_loader: LocateHandle should return EFI_NOT_FOUND if none found
Spotted this debugging OpenBSD's bootloader in qemu.  (Wouldn't really
fix anything, the problem was not having any disks, but we should
probably return the correct error code.)

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-08-11 11:08:33 +02:00
xypron.glpk@gmx.de
ebf199b92f efi_loader: attribute EFIAPI of efi_locate handle()
efi_locate_handle is called internally so it should not be
marked as EFIAPI.

The external function is efi_locate_handle_ext.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-08-11 10:57:10 +02:00
Tom Rini
b24065c4ef Merge git://git.denx.de/u-boot-i2c 2017-08-10 07:22:59 -04:00
Tom Rini
4edc31c593 Merge git://www.denx.de/git/u-boot-marvell 2017-08-10 07:22:56 -04:00
Marek Vasut
014e47f028 i2c: designware: Allow sending restart conditions
Allow sending restart conditions upon direction change as this is
required by some chips.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Heiko Schocher <hs@denxx.de>
2017-08-10 12:02:50 +02:00
Adam Ford
daa0f0500f Convert CONFIG_SYS_I2C_OMAP24XX to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_I2C_OMAP24XX

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2017-08-10 12:02:32 +02:00
Stefan Chulski
ceec6c48a4 net: mvpp2x: Set BM poll size once during priv probe
Set BM poll size once during priv probe and do not
overwrite it during port probe procedure. Pool is common for
all CP ports.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-10 08:33:02 +02:00
Stefan Chulski
a25962c417 net: mvpp2x: remove TX drain from transmit routine
TX drain in transmit procedure could cause issues due
to race between drain procedure and transmition of descriptor
between AGGR TXQ and physical TXQ.
TXQ will be cleared before moving to Linux by stop procedure.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-10 08:33:02 +02:00
Stefan Chulski
783e78562d net: mvpp2x: Set BM pool high address
MVPP22 driver support 64 Bit arch and require BM pool
high address configuration.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-10 08:33:02 +02:00
Stefan Chulski
16f18d2a4d net: mvpp2x: Remove IRQ configuration from U-Boot
Remove IRQ configuration from U-Boot PP driver.
U-Boot don't use interrupts and configuration of IRQ in U-Boot
caused crashes in Linux shared interrupt mode.
Also interrupt use is redundant in RX routine since a single RX
queue is used.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-10 08:33:02 +02:00
Stefan Chulski
d4b0e00829 net: mvpp2x: remove MBUS configurations from MvPP22 driver
MBUS driver were replaced by AXI in PPv22 and relevant
only for PPv21.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-10 08:33:02 +02:00
Stefan Chulski
f0e970fd2a net: mvpp2x: decrease size of AGGR_TXQ and CPU_DESC_CHUNK
U-boot use single physical tx queue with size 16 descriptors.
So aggregated tx queue size should be equal to physical tx queue
and cpu descriptor chunk(number of descriptors delivered from
physical tx queue to aggregated tx queue by one chunk) shouldn't be
larger than physical tx queue.

Fix:
Set AGGR_TXQ and CPU_DESC_CHUNK to be 16 descriptors, same as
physical TXQ.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-10 08:33:02 +02:00
Stefan Chulski
bb915c843f net: mvpp2x: fix BM configuration overrun issue
Issue:
BM counters were overrun by probe that called per Network interface and
caused release of wrong number of buffers during remove procedure.

Fix:
Use probe_done and num_ports to call init and remove procedure
once per communication controller.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-10 08:33:02 +02:00
Stefan Chulski
73f592fb72 net: mvpp2x: Enable GoP packet padding in TX
This patch enables padding of packets shorter than 64B in TX(set by default).
Disabling of padding causes crashes on MACCIATO board.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-10 08:33:02 +02:00
Stefan Chulski
377883f16d net: mvpp2x: fix phy connected to wrong mdio issue
A8K marvell SoC has two South Bridge communication controllers(CP0 and CP1).
Each communication controller has packet processor ports and MDIO.
On MACHIATOBin board ports from CP1 are connected to mdio on CP0.

Issue:
Wrong base address is assigned to MDIO interface during probe.

Fix:
Get MDIO address from PHY handler parent base address.

This should be refined in the future when MDIO driver is implemented.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-10 08:33:02 +02:00
Stefan Chulski
4189373a3d net: mvpp2x: Add GPIO configuration support
This patch add GPIO configuration support in mvpp2x driver.
Driver will handle 10G SFP gpio reset and SFP TX disable. GPIO pins should
be set in device tree.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-10 08:33:02 +02:00
Santan Kumar
1c83df6f3f armv8: ls2080a: Increase env sector size for qspi boot
Increase env sector size from 64kb to 256kb for qspi boot.

Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-09 09:57:33 -07:00
Hou Zhiqiang
acb90e8338 fsl-lsch2: csu: correct the workaround A-010315
The implementation of function set_pcie_ns_access() uses a wrong
argument. The structure array ns_dev has a member 'ind' which is
initialized by CSU_CSLX_*. It should use the 'ind' directly to
address the PCIe's CSL register (CSL_base + CSU_CSLX_PCIE*).

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[YS: Revise commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-09 09:57:33 -07:00
Santan Kumar
06651b9456 driver: net: fsl-mc: fsl_mc_ldpaa_exit exit earlier if dpl applied
In fsl_mc_ldpaa_exit(), in case of mc is booted and dpl is applied,
it should return earlier without executing dpbp_exit().

Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Acked-by: Priyanka Jain <priyanka.jain@nxp.com>
Acked-by: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-09 09:57:33 -07:00
Santan Kumar
7794d9ab29 board: ls2080ardb: Add fsl_fdt_fixup_flash
IFC and QSPI are muxed on board. Add fsl_fdt_fixup_flash() to disable
IFC node in dts if QSPI is enabled, or disable QSPI node in dts if
otherwise.

Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
[YS: Revise commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-09 09:57:32 -07:00
Rajesh Bhagat
a8ecb39e9e config: ls1012aqds: Enable USB EHCI support for ls1012aqds
Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
[YS: Revise subject, remove commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-09 09:57:32 -07:00
Yang Li
590e87d1a6 mmc: fsl_esdhc: not always setting esdhc fdt status to okay
We shouldn't always change the status to okay.  There could be
situations that the esdhc is intentionally disabled in the device
tree.

Signed-off-by: Li Yang <leoyang.li@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-09 09:57:32 -07:00
Hou Zhiqiang
89d8e1313f PCI: layerscape: Fix assigning wrong address to LS2088A pcie cfg1 space
This bug is brought by the commit 3d8553f0a3 (pci: layerscape: add
LS2088A series SoC pcie support), which only updated cfg_res.start
and did not update the .end field. This causes fdt_resource_size()
getting wrong value when calculate the cfg1 space address.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[YS: Revise subject and commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-09 09:57:32 -07:00
Alison Wang
563ac65a1a dm: arm: ls1021a: Move to driver model for USB
This patch enables driver model for USB in defconfigs for LS1021A
platforms.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-09 09:57:32 -07:00
Hou Zhiqiang
e4b5143eb6 fsl-lsch2: csu: remove multiple calling function
Function enable_layerscape_ns_access() is alreayd called soc-wide.
Remove duplicated calling from individual boards.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[YS: Add commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-09 09:57:32 -07:00
Hou Zhiqiang
bf7aecce04 armv8/fsl-lsch2: correct the config description of DSPI clock divider
It is derived from Platform clock instead of Platform PLL frequency.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-09 09:57:32 -07:00
Santan Kumar
263536a693 board:ls2080ardb: Update execution of config_board_mux
Function config_board_mux() reads env variable 'hwconfig' which is
only available after relocation for QSPI boot. Move calling
config_board_mux() to misc_init_r().

Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
[YS: Revise commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-09 09:55:02 -07:00
Santan Kumar
6cc914efd2 board/ls2080ardb: Disable SD-related GPIO programming
Smart voltage translator is removed from LS2080ARDB/LS2088ARDB
RevF boards. It is only used on LS2081ARDB. Programming GPIO
is only required for LS2081ARDB.

Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
[YS: Revise commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-09 09:54:43 -07:00
Qianyu Gong
3016084b38 armv8: ls1046ardb: update core frequency to 1800MHZ
Update the default core frequency to 1800MHZ for best performance under
SD boot and eMMC boot.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-09 09:11:34 -07:00
York Sun
9bb272e90a driver: mmc: fsl_esdhc: Fix compiling warning
Commit 4483b7eb added variable vqmmc_dev but only uses it under
CONFIG_DM_REGULATOR. Add the same macro to variable declaration to
get rid of compiling warning.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-08-09 09:11:29 -07:00
Adam Ford
94d50bed65 Configs: Migrate CONFIG_SYS_I2C_OMAP34XX to CONFIG_SYS_I2C_OMAP24XX
The driver is for all boards 24XX and up, so let's eliminate the
extra option called CONFIG_SYS_I2C_OMAP34XX since the driver checks
for CONFIG_OMAP34XX we don't need CONFIG_SYS_I2C_OMAP34XX.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2017-08-09 06:14:13 +02:00
Wenyou.Yang@microchip.com
0bc8f640a4 i2c: at91: Add missing probe function to device driver
Add missing probe function to the device driver to active a device.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2017-08-09 06:13:53 +02:00
Tom Rini
d529124fdc Merge git://git.denx.de/u-boot-x86 2017-08-08 17:06:19 -04:00
Tom Rini
f0ca30fa19 Merge git://www.denx.de/git/u-boot-cfi-flash 2017-08-08 17:05:47 -04:00
Tom Rini
1f032ce23a Merge git://www.denx.de/git/u-boot-marvell 2017-08-08 17:05:33 -04:00
Tom Rini
1989374b21 configs: Finish migration of PHY_GIGE
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-08 17:02:31 -04:00
Stefan Roese
6a5691e297 x86: Add defconfig for theadorable-x86-conga with PCIe x4 blobs
This defconfig uses the PCIe x4 binary blobs from the congatec BIOS.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-08 21:13:07 +08:00
Stefan Roese
2efd877b0c x86: conga: theadorable-x86-conga-qa3-e3845_defconfig: Misc defconfig updates
- Disable debug UART
- Enable more partition support

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-08 21:13:07 +08:00
Stefan Roese
3038d5c656 x86: conga: conga-qeval20-qa3-e3845_defconfig: Misc defconfig updates
- Enable ACPI resume support
- Disable debug UART
- Enable Spansion and Winbond SPI flash support
- Move VGA BIOS binary address to enable bigger U-Boot images

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-08 21:13:06 +08:00
Stefan Roese
489b51da68 x86: theadorable-x86: Add header file for common defines and env
This patch adds the common header include file theadorable-x86-common.h
for the theadorable-x86 targets to define all common options and the
default environment.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-08 21:13:06 +08:00
Stefan Roese
14a937ffb9 x86: conga: Add option to select different config headers for baseboards
This patch adds the infrastructure to define different config headers
with different configurations and default environment for the baseboards
that can now be selected via Kconfig. The new configuration for the
theadorable-x86-conga-qa3-e3845 is also added. Also the new defconfig
file for this new target is added.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-08 21:13:06 +08:00
Stefan Roese
6b08679328 x86: dfi: Add option to select different config headers for baseboards
This patch adds the infrastructure to define different config headers
with different configurations and default environment for the baseboards
that can now be selected via Kconfig. The new configuration for the
theadorable-x86-dfi-bt700 is also added.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-08 21:13:06 +08:00
Bin Meng
323a6d6910 x86: acpi: Fix build error with certain configuration
When CONFIG_EFI_PARTITION is not set, the following build error is
seen in arch/x86/lib/acpi_s3.c:

  error: expected declaration specifiers or '...' before '*' token
  static void asmlinkage (*acpi_do_wakeup)(void *vector) = (void*)WAKEUP_BASE;

This is actually caused by missing asmlinkage declaration, but with
CONFIG_EFI_PARTITION on, the declaration comes from part.h which
is included from common.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-08 21:13:05 +08:00
Marek Vasut
bd2d489e24 mtd: cfi: Zap CFI_FLASH_SHIFT_WIDTH redefinition
This is defined twice in the same file, with the same value, likely
because of some patch merge issue. Pick the uglier one and nuke it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-08 14:29:48 +02:00
Marek Behún
8daa3468b5 mvebu: turris_omnia: Fix PEX vs SATA detection for board topology
The I2C reading in the PEX vs SATA detection code often fails on the
first try. Try three times, as the code for EEPROM reading does.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-08 14:20:26 +02:00
Bin Meng
091e51d20f x86: Remove dead ISA related codes
Neither new design uses ISA bus, nor does any U-Boot codes use these
codes. Remove them.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-08 16:46:32 +08:00
Wenyou.Yang@microchip.com
8fc2faefdd mtd: spi: sf_dataflash: Add print message while erase error
Add the print message to tell us why the erase operation doesn't work.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-08 12:34:27 +05:30
Bin Meng
ac6777b1e3 sf: Add Macronix MX25U6435F device parameters
This adds support for Macronix flash MX25U6435F (device ID 0xc22537).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-08 12:26:05 +05:30
Tom Rini
6e7adf7037 Merge branch 'master' of git://git.denx.de/u-boot-net 2017-08-07 17:37:56 -04:00
Alexandru Gagniuc
da3b9e7fd6 Move PHY_MICREL and PHY_MICREL_KSZ90X1 to Kconfig
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-07 15:22:29 -05:00
Alexandru Gagniuc
3146f0c017 Move PHYLIB to Kconfig
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-07 15:22:28 -05:00
Sebastien Bourdelin
ef1f61aa03 net: phy: micrel: add an option to disable gigabit for the KSZ9031
The environment variable "disable_giga" can now be used to disable
1000baseTx on the Micrel's KSZ9031.

Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-07 15:18:31 -05:00
Denis Pynkin
704f3acfcf net: Use packed structures for networking
PXE boot is broken with GCC 7.1 due option '-fstore-merging' enabled
by default for '-O2':

BOOTP broadcast 1
data abort
pc : [<8ff8bb30>]          lr : [<00004f1f>]
reloc pc : [<17832b30>]    lr : [<878abf1f>]
sp : 8f558bc0  ip : 00000000     fp : 8ffef5a4
r10: 8ffed248  r9 : 8f558ee0     r8 : 8ffef594
r7 : 0000000e  r6 : 8ffed700     r5 : 00000000  r4 : 8ffed74e
r3 : 00060101  r2 : 8ffed230     r1 : 8ffed706  r0 : 00000ddd
Flags: nzcv  IRQs off  FIQs off  Mode SVC_32
Resetting CPU ...

Core reason is usage of structures for network headers without packed
attribute.

Reviewed-by: Yauheni Kaliuta <yauheni.kaliuta@redhat.com>
Signed-off-by: Denis Pynkin <denis.pynkin@collabora.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-07 15:18:31 -05:00
Holger Dengler
66c89ee31b net: Fix compile failure in net.c
Add missing "defined" statement to fix the compile failures.

Signed-off-by: Holger Dengler <dengler@linutronix.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-07 15:18:31 -05:00
Arun Parameswaran
d7e8ac6f45 net: phy: Add AFE settings to the Broadcom Cygnus phy
Added the AFE (Analog Front End) settings for stability to the
Broadcom Cygnus phy. This improves the time take to perform
auto negotiation.

Signed-off-by: Arun Parameswaran <arun.parameswaran@broadcom.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-07 15:18:31 -05:00
Suji Velupillai
c89782dcac net: move Broadcom SF2 driver to Kconfig
move to Kconfig:
	CONFIG_BCM_SF2_ETH
	CONFIG_BCM_SF2_ETH_DEFAULT_PORT
	CONFIG_BCM_SF2_ETH_GMAC

Also modified defconfigs of all platforms that use these configs.

Signed-off-by: Suji Velupillai <suji.velupillai@broadcom.com>
Tested-by: Suji Velupillai <suji.velupillai@broadcom.com>
Reviewed-by: JD Zheng <jiandong.zheng@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
Signed-off-by: Steve Rae <steve.rae@raedomain.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-07 15:18:30 -05:00
Alexandru Gagniuc
9a31c739d2 net: phy: Hide Micrel KSZ9021 and KSZ9031 Kconfig options
The correct option is PHY_MICREL_KSZ90X1, but some configs still
select the 9021 and 9031 options, which are deprecated.

Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-07 15:18:30 -05:00
Alexandru Gagniuc
fbc120e668 net: phy: micrel: Remove ksz90x1 drivers from micrel_ksz8xxx
There should be no longer be any ksz9000 users that pick up the PHY
driver from ksz8xxx, so remove ksz9000 remnants from there.

Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-07 15:18:30 -05:00
Alexandru Gagniuc
fb92bc8852 configs: Replace deprecated Micrel defines with PHY_MICREL_KSZ90X1
These boards will now use the ksz90x1 driver instead of the mess in
ksz8xxx. This change is needed before the two drivers can be fully
separated.

Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-07 15:18:30 -05:00
Alexandru Gagniuc
d397f7c45b net: phy: micrel: Separate KSZ9000 drivers from KSZ8000 drivers
The KS8721BL and KSZ9021 PHYs are software-incompatible, yet they
share the same ID. Drivers for bothe PHYs cannot safely coexist, so
the solution was to use #ifdefs to select between the two drivers.

As a result KSZ9031, which has a unique ID, is now caught in the
crossfire. Unless CONFIG_PHY_MICREL_KSZ9031 is defined, the KSZ9031
will not function properly, as some essential configuration code is
ifdef'd-out.

To prevent such situations, move the KSZ9000 drivers to a separate
file, and place them under a separate Kconfig option. While it is
possible to enable both KSZ8000 and KSZ9000 drivers at the same time,
the assumption is that it is highly unlikely for a system to contain
both a KSZ8000 and a KSZ9000 PHY, and that only one of the drivers
will be enabled at any given time.

Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-07 15:18:30 -05:00
Alexandru Gagniuc
cb543d30df net: phy: Remove duplicate Kconfig selection for Micrel KSZ9021
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-07 15:18:29 -05:00
Vladimir Zapolskiy
0c17b1b79c net: tftp: silence a subscript above array bounds compile time warning
For strncpy() select a minimal string length of destination and source
strings, here DEFAULT_NAME_LEN is preferable to MAX_LEN.

Due to the NUL-terminated contents of default_string the change is
a noop, however it removes a compilation warning if SH2/3/4 platform
specific strncpy() function is used:

  In file included from include/linux/string.h:21:0,
                   from include/common.h:28,
                   from net/tftp.c:9:

  net/tftp.c: In function 'tftp_start':
  arch/sh/include/asm/string.h:52:42: warning: array subscript is above array bounds [-Warray-bounds]
     : "0" (__dest), "1" (__src), "r" (__src+__n)

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-07 15:18:29 -05:00
Joe Hershberger
2fd519f777 net: ag7xxx: Propagate errors on phy access
Don't wait forever.
Pass errors back to the caller.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Marek Vasut <marex@denx.de>
2017-08-07 15:18:29 -05:00
Joe Hershberger
9240a2f5f1 net: ag7xxx: Comment register names
The register constants don't use the exact names that are used in the
TRM, so add comments that use the exact names so that it is clear what
register is being referred to.

https://www.atheros-drivers.com/qualcomm-atheros-datasheets-for-AR9331.html

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Marek Vasut <marex@denx.de>
2017-08-07 15:18:29 -05:00
Philipp Tomsich
734f9abd17 net: usb: r8152: fix "duplicate 'const' declaration specifier"
After upgrading to GCC 7.1, the duplicate const specifies in the
r8152 driver trigger the following build warnings with buildman
(observed on a 'buildman rockchip' test)::
  ../drivers/usb/eth/r8152.c:62:35: warning: duplicate 'const' declaration specifier [-Wduplicate-decl-specifier]
   static const struct r8152_version const r8152_versions[] = {
                                     ^~~~~

This commit fixes these by removing the duplicate 'const' specifier
from the declarations.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-07 15:18:29 -05:00
Masahiro Yamada
0c1b869b2e net: add static to do_tftpput()
This is only used in cmd/net.c

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-07 15:18:29 -05:00
Jimmy Du
b044cc1dee net: Get mac address from driver as seed
Previously seeded by obtaining mac addr from env. If mac addr was
never set, rand would output 0. This fix obtains the mac addr
from driver instead.

Signed-off-by: Jimmy Du <jimmy.du@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-07 15:18:28 -05:00
Christian Gmeiner
8f0b169382 drivers/net/phy/fixed: do not overwrite addr
phy_device_create(..) sets the addr of phy_device with a sane value.
There is no need overwrite it.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-07 15:18:28 -05:00
eric.gao@rock-chips.com
b713bc8a2d rockchip: video: defconfig: Add mipi dsi support for evb-rk3288
Add support for rk3288 mipi dsi.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-07 21:38:47 +02:00
eric.gao@rock-chips.com
fcc1d05098 rockchip: video: Makefile: Add soc specific driver for rk3288 mipi dsi
Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-07 21:32:11 +02:00
eric.gao@rock-chips.com
f680a91d5c rockchip: video: mipi: Add rk3288 soc specific driver for mipi dsi
Add rk3288 soc specific driver for mipi dsi.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-07 21:16:22 +02:00
eric.gao@rock-chips.com
e9037fb3ad rockchop: video: mipi: Makefile: Add soc specfic driver for rk3399 mipi dsi
Add Makefile item for soc specific driver for rk3399 mipi dsi.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-07 20:45:08 +02:00
eric.gao@rock-chips.com
36602eba80 rockchip: video: mipi: Split mipi driver into common and specific parts
To compatible with different rockchip soc, we split the mipi dirver into
common and soc specific parts, and all the soc share the common
functions from common driver part.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[agust: fix build breakage and warnings]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-08-07 20:44:01 +02:00
eric.gao@rock-chips.com
c83e835966 rockchip: defconfig: Increase max video resolution for mipi panel
The mipi panel used on evb-rk3399 has a 1920x1200 resolution. But now
the max resolution is 1920x1080. So increase it.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-07 19:01:08 +02:00
Bin Meng
c674e00b8a video: Drop the ct69000 driver
This is not used in U-Boot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-07 18:15:19 +02:00
Bin Meng
aa82f935ab video: Drop the sm501 driver
This is not used in U-Boot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-07 18:14:36 +02:00
Bin Meng
5ec94cdf8e video: Drop the sed156x driver
This is not used in U-Boot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-07 18:12:23 +02:00
Bin Meng
0778d0c2d8 video: Drop the l5f31188 driver
This is not used in U-Boot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-07 18:10:14 +02:00
Thomas Petazzoni
eaa90e5df2 common/env_embedded.c: rename PPCENV/PPCTEXT macros
The environment has pretty much nothing to do with just "PPC", so
rename the macros to just __UBOOT_ENV_SECTION__ which is more
readable.

In addition, only a single macro is needed: the environment now goes
either to the default section (USE_HOSTCC is defined) or in the .text
section.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2017-08-04 20:38:39 -04:00
Thomas Petazzoni
7653942b10 common/env_embedded.c: drop support for CONFIG_SYS_USE_PPCENV
CONFIG_SYS_USE_PPCENV is no longer used anywhere. It was used to put
the environment in the special .ppcenv section, but the last
architecture using this section (SuperH) has been changed to not use
it.

Therefore, this commit drops support for CONFIG_SYS_USE_PPCENV
entirely. We only handle two cases:

 - We're building the host tool tools/envcrc, in which case the
   environment is place with no special section attribute (so it
   depends up in .data)

 - We're building U-Boot itself, in which case the environnement is
   placed in the .text section.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2017-08-04 20:38:39 -04:00
Adam Ford
7e0ed13f47 Convert ARCH_OMAP2PLUS boards' CONFIG_SYS_TEXT_BASE to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_TEXT_BASE

The includes, whitelist, etc. were left for now but I don't get any
build errors or warnings on the omap3_logic_defconfig or
am3517_evm_defconfig builds I tried.

Signed-off-by: Adam Ford <aford173@gmail.com>
2017-08-04 20:38:39 -04:00
Patrice Chotard
679590ebc0 stmf32f4: soc: fix buildman compilation error
fix the following compilation error reported by buidlman:

       arm:  +   stm32f429-discovery
+arch/arm/mach-stm32/stm32f4/soc.c: In function 'arch_cpu_init':
+arch/arm/mach-stm32/stm32f4/soc.c:30:2: error: 'for' loop initial declarations are only allowed in C99 or C11 mode
+  for (int i = 0; i < ARRAY_SIZE(stm32_region_config); i++)
+  ^
+arch/arm/mach-stm32/stm32f4/soc.c:30:2: note: use option -std=c99, -std=gnu99, -std=c11 or -std=gnu11 to compile your code
+make[3]: *** [arch/arm/mach-stm32/stm32f4/soc.o] Error 1
+make[2]: *** [arch/arm/mach-stm32/stm32f4] Error 2
+make[1]: *** [arch/arm/mach-stm32] Error 2
+make: *** [sub-make] Error 2

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas Manocha <vikas.manocha@st.com>
2017-08-04 20:38:38 -04:00
Wenyou.Yang@microchip.com
c0667d6c49 configs: sama5d4_xplained: Fix input clock for debug UART
Fix the UART input clock for the early debug UART, it should be
100MHz, instead of 88MHz.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-08-04 20:38:38 -04:00
Wenyou.Yang@microchip.com
fdc7718999 board: usb_a9263: Update to support DT and DM
Add the dts files to support deivce tree, update the configuration
files to support the device tree and driver model. The peripheral
clock and pins configuration are handled by the clock and the pinctrl
drivers respectively.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-04 20:38:38 -04:00
Wenyou.Yang@microchip.com
a818704b2e board: meesc: Update to support DT and DM
Add the dts files to support deivce tree, update the configuration
files to support the device tree and driver model. The peripheral
clock and pins configuration are handled by the clock and the pinctrl
drivers respectively.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-04 20:38:37 -04:00
Wenyou.Yang@microchip.com
c53a825e15 board: pm9261: Update to support DT and DM
Add the dts files to support deivce tree, update the configuration
files to support the device tree and driver model. The peripheral
clock and pins configuration are handled by the clock and the pinctrl
drivers respectively.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-04 20:38:37 -04:00
Wenyou.Yang@microchip.com
94db5120d8 board: ethernut5: Update to support DT and DM
Add the dts files to support deivce tree, update the configuration
files to support the device tree and driver model. The peripheral
clock and pins configuration are handled by the clock and the pinctrl
drivers respectively.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-04 20:38:37 -04:00
Wenyou.Yang@microchip.com
0dfe3ffe0b board: pm9263: Update to support DT and DM
Update the configuration files to support the device tree and driver
model. The peripheral clock and pins configuration are handled by
the clock and the pinctrl drivers respectively.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-04 20:38:36 -04:00
Wenyou.Yang@microchip.com
f166af88a8 board: at91sam9260ek: Use SPI-flash-based AT45xxx DataFlash
To support driver model and device tree, use the SPI-flash-based
AT45xxx DataFlash driver, DataFlash is a kind of SPI flash.
Instead of ATMEL_DATAFLASH_SPI DataFlash older driver that will
be removed in the future.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-04 20:38:36 -04:00
Wenyou.Yang@microchip.com
56a61e5e27 board: at91sam9rlek: Use SPI-flash-based AT45xxx DataFlash
To support driver model and device tree, use the SPI-flash-based
AT45xxx DataFlash driver, DataFlash is a kind of SPI flash.
Instead of ATMEL_DATAFLASH_SPI DataFlash older driver that will
be removed in the future.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-04 20:38:35 -04:00
Wenyou.Yang@microchip.com
eab36f6d7b board: at91sam9263ek: Use SPI-flash-based AT45xxx DataFlash
To support driver model and device tree, use the SPI-flash-based
AT45xxx DataFlash driver, DataFlash is a kind of SPI flash.
Instead of ATMEL_DATAFLASH_SPI DataFlash older driver that will
be removed in the future.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-04 20:38:35 -04:00
Wenyou.Yang@microchip.com
324873e7c2 board: at91sam9261ek: Update to support DT and DM
Add the dts files to support deivce tree, update the configuration
files to support the device tree and driver model. The peripheral
clock and pins configuration are handled by the clock and the pinctrl
drivers respectively.

Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-04 20:38:35 -04:00
Alison Chaiken
2fcaa413b3 gpt: harden set_gpt_info() against non NULL-terminated strings
Strings read from devices may sometimes fail to be
NULL-terminated.   The functions in lib/string.c are subject to
failure in this case.   Protect against observed failures in
set_gpt_info() by switching to length-checking variants with a length
limit of the maximum possible partition table length.  At the same
time, add a few checks for NULL string pointers.

Here is an example as observed in sandbox under GDB:

    => gpt verify host 0 $partitions
    Program received signal SIGSEGV, Segmentation fault.
    0x0000000000477747 in strlen (s=0x0) at lib/string.c:267
    267             for (sc = s; *sc != '\0'; ++sc)
    (gdb) bt
    #0  0x0000000000477747 in strlen (s=0x0) at lib/string.c:267
    #1  0x00000000004140b2 in set_gpt_info (str_part=<optimized out>,
    str_disk_guid=str_disk_guid@entry=0x7fffffffdbe8, partitions=partitions@entry=0x7fffffffdbd8,
    parts_count=parts_count@entry=0x7fffffffdbcf "", dev_desc=<optimized out>) at cmd/gpt.c:415
    #2  0x00000000004145b9 in gpt_verify (str_part=<optimized out>, blk_dev_desc=0x7fffef09a9d0) at cmd/gpt.c:580
    #3  do_gpt (cmdtp=<optimized out>, flag=<optimized out>, argc=<optimized out>, argv=0x7fffef09a8f0)
    at cmd/gpt.c:783
    #4  0x00000000004295b0 in cmd_call (argv=0x7fffef09a8f0, argc=0x5, flag=<optimized out>,
    cmdtp=0x714e20 <_u_boot_list_2_cmd_2_gpt>) at common/command.c:500
    #5  cmd_process (flag=<optimized out>, argc=0x5, argv=0x7fffef09a8f0,
    repeatable=repeatable@entry=0x726c04 <flag_repeat>, ticks=ticks@entry=0x0) at common/command.c:539

Suggested-by: Lothar Waßmann <LW@karo-electronics.de>
Signed-off-by: Alison Chaiken <alison@peloton-tech.com>
2017-08-04 20:38:32 -04:00
Alison Chaiken
203f9b48ad GPT: provide commands to selectively rename partitions
This patch provides support in u-boot for renaming GPT
partitions.  The renaming is accomplished via new 'gpt swap'
and 'gpt rename' commands.

The 'swap' mode returns an error if no matching partition names
are found, or if the number of partitions with one name does not equal
the number with the second name.   The 'rename' variant always
succeeds as long as a partition with the provided number exists.

Rewriting the partition table has the side-effect that all partitions
end up with "msftdata" flag set.  The reason is that partition type
PARTITION_BASIC_DATA_GUID is hard-coded in the gpt_fill_pte()
function.  This does not appear to cause any harm.

Signed-off-by: Alison Chaiken <alison@peloton-tech.com>
2017-08-04 20:35:27 -04:00
Alison Chaiken
09a49930e4 GPT: read partition table from device into a data structure
Make the partition table available for modification by reading it from
the user-specified device into a linked list.   Provide an accessor
function for command-line testing.

Signed-off-by: Alison Chaiken <alison@peloton-tech.com>
[trini: Make this depend on CMD_GPT_RENAME, as it is the user of this
code]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-04 20:34:04 -04:00
Alison Chaiken
73d6d18b71 GPT: add accessor function for disk GUID
In order to read the GPT, modify the partition name strings, and then
write out a new GPT, the disk GUID is needed.  While there is an
existing accessor for the partition UUIDs, there is none yet for the
disk GUID.

Changes since v6: none.

Signed-off-by: Alison Chaiken <alison@peloton-tech.com>
2017-08-04 09:56:04 -04:00
Alison Chaiken
e6faf21f25 partitions: increase MAX_SEARCH_PARTITIONS and move to part.h
Move MAX_SEARCH_PARTITIONS to part.h so that functions in cmd
directory can find it.  At the same time, increase the value to
64 since some operating systems use many, and the resources
consumed by a larger value are minimal.

Changes since v6: none.

Signed-off-by: Alison Chaiken <alison@peloton-tech.com>
2017-08-04 09:56:03 -04:00
Alison Chaiken
52791db74f cmd gpt: test in sandbox
Make minor changes to README.gpt and sandbox_defconfig to support
testing of the gpt command's functionality in the sandbox.

Changes since v6: none.

Signed-off-by: Alison Chaiken <alison@peloton-tech.com>
2017-08-04 09:56:02 -04:00
Alison Chaiken
0a24238625 GPT: fix error in partitions string doc
The existing partitions-list parsing in cmd/gpt.c passes a value
from gpt_default() to set_gpt_info() that README.gpt suggests
should begin with 'partitions='.  Partition-list strings should
in fact begin with 'uuid_disk', as otherwise the call from
set_gpt_info() to extract_val() to find 'uuid_disk' will fail.
Change README.gpt accordingly.

Changes since v6: none.

Signed-off-by: Alison Chaiken <alison@peloton-tech.com>
2017-08-04 09:55:30 -04:00
Alison Chaiken
92856b489b disk_partition: introduce macros for description string lengths
Changes since v6: none.

Signed-off-by: Alison Chaiken <alison@peloton-tech.com>
2017-08-04 09:55:29 -04:00
Alison Chaiken
db9b6200a4 EFI: replace number with UUID_STR_LEN macro
Changes since v6: none.

Signed-off-by: Alison Chaiken <alison@peloton-tech.com>
2017-08-04 09:55:29 -04:00
Tom Rini
fe84c48eeb Merge tag 'xilinx-for-v2017.09' of git://www.denx.de/git/u-boot-microblaze
Xilinx changes for v2017.09

Zynq:
- Add Z-Turn board support

fpga:
- Remove intermediate buffer from code

Zynqmp:
- dts cleanup
- change psu_init handling
- Add options to get silicon version
- Fix time handling
- Map OCM/TCM via MMU
- Add new clock driver
2017-08-04 07:23:32 -04:00
Tom Rini
217324b23c PowerPC: mpc85xx: Update ft_verify_fdt
With the changes to fdt_get_base_address() we need to modify the logic
in ft_verify_fdt() for how we check the validity of the CCSR address.

Tested-on: qemu-ppce500 -M mpc8544ds
Fixes: 336a44877a ("fdt: Correct fdt_get_base_address()")
Cc: York Sun <york.sun@nxp.com>
Cc: Wolfgang Denk <wd@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-03 14:48:53 -04:00
Tom Rini
9f841559a5 qemu-ppce500: Update get_phys_ccsrbar_addr_early()
The logic of what fdt_get_base_address() will search for and return has
changed.  Rework get_phys_ccsrbar_addr_early() to perform the logic that
fdt_get_base_address used to perform.

Fixes: 336a44877a ("fdt: Correct fdt_get_base_address()")
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Alexander Graf <agraf@suse.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-03 14:48:52 -04:00
Bin Meng
7b9c88bfca ahci-pci: Update call to ahci_probe_scsi_pci()
ahci_probe_scsi() now takes a 'base' argument, and there is an API
that prepares base address for us: ahci_probe_scsi_pci().

Reported-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-03 14:48:48 -04:00
Tom Rini
a89302cc79 Merge branch 'rmobile' of git://git.denx.de/u-boot-sh 2017-08-02 19:30:27 -04:00
Nobuhiro Iwamatsu
9c552db619 ARM: rmobile: Update defconfig of R-Car Gen3
This updates defconfig of R-Car Gen3 to keep with the latest Kconfig.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-03 04:29:23 +09:00
Marek Vasut
1fea9e25fa net: ravb: Add clock handling support
Add support for enabling and disabling the clock using the clock
framework based on the content of OF instead of doing it manually
in the board file.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-03 04:26:25 +09:00
Marek Vasut
e821a7bdb1 net: ravb: Detect PHY correctly
The order of parameters passed to the phy_connect() was wrong.
Moreover, only PHY address 0 was used. Replace this with code
capable of detecting the PHY address.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-03 04:26:25 +09:00
Marek Vasut
5ee8b4d7f5 net: ravb: Add OF probing support
Add support for probing the RAVB Ethernet block from device tree.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-03 04:26:25 +09:00
Marek Vasut
8171499df9 serial: sh: Use the clock framework to obtain clock config
Since we now have clock driver on the RCar Gen3 , obtain the clock
configuration using the clock framework functions. In case this
fails, fall back to the original code for pulling the clock config
directly out of OF.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-03 04:26:25 +09:00
Marek Vasut
03a38a3972 serial: sh: Convert to Kconfig
Convert the SH Serial to Kconfig using tools/moveconfig.py tool
and a bit of manual adjustment to cater for failed conversions.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-03 04:26:24 +09:00
Marek Vasut
7ee0283d05 ARM: rmobile: Enable clock framework on ULCB
Since there is now a clock driver for RCar Gen3, enable it on this board.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-03 04:26:24 +09:00
Marek Vasut
9a86226e27 ARM: rmobile: Enable clock framework on Salvator-X
Since there is now a clock driver for RCar Gen3, enable it on this board.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-03 04:26:24 +09:00
Marek Vasut
36c2ee4ce5 clk: rmobile: Add RCar Gen3 clock driver
Add clock driver for the RCar Gen3 R8A7795 and R8A7796 SoCs .
This driver allows reading out the clock configuration set by
previous boot stages and enabling and disabling clock using
the MSTP registers. Setting clock is not supported thus far.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-03 04:26:24 +09:00
Marek Vasut
86fa69072d ARM: rmobile: Enable OF_CONTROL on RCar Gen3
Since the DTs are now in place, enable OF control so that they get
bundled into the U-Boot.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-03 04:26:18 +09:00
Marek Vasut
4157c472c3 ARM: dts: rmobile: Import DTS from Linux 4.12
Import the RCar Gen3 DTS and headers from upstream Linux kernel v4.12-rc6,
commit 6f7da290413ba713f0cdd9ff1a2a9bb129ef4f6c . This includes both M3
and H3 ULCB and Salvator-X boards.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-03 03:50:03 +09:00
Marek Vasut
48aa812676 ARM: rmobile: Increase console buffer sizes
Allow pasting extra long lines into the U-Boot console on RCar Gen3.
This is OK since we have plenty of resources and it's convenient.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-03 03:50:03 +09:00
Marek Vasut
bd39050cb2 ARM: rmobile: ulcb: Add ULCB board support
Add initial support for the R8A7795 and R8A7796 based ULCB board.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-03 03:50:03 +09:00
Marek Vasut
c65e46dab0 ARM: rmobile: Add PFC PUEN bank 5 address
Add the PFC5 PUEN address and SSI SDATA4 bit offset into the
rcar-gen3-base.h .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-03 03:50:03 +09:00
Tom Rini
ec7483e34e Merge git://git.denx.de/u-boot-fsl-qoriq
Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	include/configs/ls1046aqds.h
	include/configs/ls1046ardb.h
2017-08-02 10:52:26 -04:00
Stefano Babic
83605d37b0 mx6: Add support for Phytec pfla02 (NAND)
Add support for Phytec pfla02, equipped with NAND.

CPU:   Freescale i.MX6Q rev1.5 996 MHz (running at 792 MHz)
CPU:   Automotive temperature grade (-40C to 125C) at 31C
Reset cause: POR
I2C:   ready
DRAM:  1 GiB
NAND:  2048 MiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
SF: Detected n25q128 with page size 256 Bytes, erase size 64 KiB, total
16 MiB
In:    serial
Out:   serial
Err:   serial
Net:   FEC [PRIME]
Hit any key to stop autoboot:  0

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Stefan Christ <s.christ@phytec.de>
CC: Stefan Müller-Klieser <S.Mueller-Klieser@phytec.de>
CC: Christian Hemp <C.Hemp@phytec.de>
2017-08-02 11:45:27 +02:00
Heinrich Schuchardt
df1cd46fb8 arm64: zynqmp: avoid out of buffer access
strncat(a, b, c) appends a maximum of c characters plus the 0 byte
to a.

In board_init we first write 4 characters plus 0 byte to version.
So only ZYNQMP_VERSION_SIZE - 5 additional characters fit into
version.

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-02 09:11:52 +02:00
Siva Durga Prasad Paladugu
74ba69db35 arm64: zynqmp: Make chip_id routine to handle based on el.
Modify chip_id() routine such that to handle based on
the current el. Also make it available even if FPGA is
not enabled in system such it can be used always.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-02 09:11:52 +02:00
Siva Durga Prasad Paladugu
f52bf5a3dd arm64: zynqmp: Make chip_id a global routine()
This patch makes chip_id() as a global routine so that
it can be used in other places as required.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-02 09:11:52 +02:00
Siva Durga Prasad Paladugu
db3123b40d arm64: zynqmp: Modify chip_id routine to get either idcode or version
This patch modifies the chip_id routine to get either idcode or
silicon version based on the argument received.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-02 09:11:52 +02:00
Michal Simek
be4634511a arm64: zynqmp: Move dts zcu102 to zcu102-revA
Not using board revision is causing confusion about which board is
supported and tested. Mark dts files exactly with board revision which
was tested. When new board revision arives it can be symlink if SW view
is the same. Also add -revX suffix to compatible string because user space
tools are parsing this string and can change behavior depends of board
revision.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-02 09:11:52 +02:00
Siva Durga Prasad Paladugu
4b5b0fcd21 arm64: zynqmp: Dont write to system timestamp generator
Remove incorrect code of writing to system timestamp
counter registers. This register writes does nothing
and can be removed.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-02 09:11:52 +02:00
Michal Simek
90a35db410 arm64: zynqmp: Do not setup time if already setup
Newer psu_init_gpl.c/h contain clock setup. Detect if
reference clock is active. If yes, skip timer setup.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-02 09:11:52 +02:00
Michal Simek
926870478d arm64: zynqmp: Fix SVD mask for getting chip ID
Mask should start from the first bit - using 0xe is just wrong.
3bits are used that's why 0x7 mask is correct.
This patch is fixing silicon ID code detection. Previous behavior was
that bit0 was completely ignored.
Issue was found on 2eg chip detection.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-02 09:11:52 +02:00
Michal Simek
fd1b635c06 arm64: zynqmp: Add Kconfig option for adding psu_init to binary
There is a need to include psu_init also in mini u-boot configuration
that's why handle psu_init via Kconfig property.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-02 09:11:52 +02:00
Michal Simek
55de09292f arm64: zynqmp: Call psu_init from board_early_init_f
For some mini platforms there could be a need to include psu_init.
That's why move it to board file instead of spl only file.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-02 09:11:52 +02:00
Siva Durga Prasad Paladugu
cb186e74fb arm64: zynqmp: Remove ifdef around zynqmp mmio read and write rotuines
This patch removes ifdef around mmio read and write rotuines
and make them a single routine by checking the current el.
This patch helps to remove ifdef around invoke_smc as well.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-02 09:11:52 +02:00
Siva Durga Prasad Paladugu
a076789efe arm64: zynqmp: Define a way to intialize TCM
TCM on ZynqMP needs to be intialized in a sequence
and this patch provides a global routine to perform
this as per requirement.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-02 09:11:52 +02:00
Siva Durga Prasad Paladugu
189bec47ab arm64: zynqmp: Provide a Kconfig option to define OCM and TCM in MMU
This patch provides an option to include OCM and TCM memory
into MMU table with corresponding memory attributes.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-02 09:11:52 +02:00
Siva Durga Prasad Paladugu
d863909f36 fpga: xilinx: Avoid using local intermediate buffer
Dont use local temporary buffer for printing out the
info instead use directly from memroy. This fixes the
issue of stack corruprion due to local buffer overflow.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-02 09:11:52 +02:00
Michal Simek
cf772e9690 clk: zynqmp: Remove unused macros/variables
These macros and one variable is not used anywhere that's why
they should be removed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-02 09:11:52 +02:00
Siva Durga Prasad Paladugu
154799ac95 clk: zynqmp: Dont panic incase of mmio write/read failures
Dont panic incase of mmio write/read failures instead return
error and let the peripheral driver take care of clock get
and set failures.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-02 09:11:52 +02:00
Siva Durga Prasad Paladugu
ad76f8cedf clk: zynqmp: Add support for CCF driver
Add support for CCF, this CCF reads the ref clocks
from dt and checks all the required clock control
registers for its source , divisors and calculates
the clock from them. This supports clock and set
functions.

Panic when read/write fails.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-02 09:11:52 +02:00
Siva Durga Prasad Paladugu
60873f736e common: board_f: Make reserve_mmu a weak function
Make reserve_mmu a weak so that it provides an option
to customize this routine as per platform need

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-02 09:11:52 +02:00
Alexander Graf
584dc4095e zynq: Add Z-Turn board
The Z-Turn board is a low cost development board based on the
Xilinx Zynq SoC. While it's powerful and quite versatile, it
so far lacked upstream support.

This patch adds basic support for the Z-Turn. It does however
for now miss enablement for MIO51 reset which means that USB
and ethernet don't work. For that either FSBL or SPL need to
be adjusted. The SPL part will follow later.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-02 09:11:51 +02:00
Alexander Graf
61d8eeb0bc zynq: Enable distro boot
Distro boot allows devices to boot using standardized boot methods by
default. This can be very handy for distributions that want to run on
different platforms.

This patch moves the zynq platform to use its old, zynq specific boot
method first and then fall back to distro boot. That way supporting
Linux distributions like openSUSE is much easier.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-02 09:11:51 +02:00
Alexander Graf
f5e46b4919 zynq: Add EFI runtime sections to linker script
When using EFI_LOADER, we add a few special sections for runtime code and
data which get relocated on demand when executing a target OS.

These runtime structures need to get annotated properly in the linker script.
While we do that properly in the generic one, we missed out on the zynq
specific linker script.

This patch adds the EFI runtime section annotations into the zynq linker script
so that the efi loader code actually works on that platform.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-02 09:11:51 +02:00
Michal Simek
0b180d02a3 arm: zynq: Label whole PL part as fpga_full region
This will simplify dt overlay structure for the whole PL.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
2017-08-02 09:11:51 +02:00
Tom Rini
07d7783822 Merge git://git.denx.de/u-boot-x86 2017-08-01 15:38:32 -04:00
Tom Rini
5c6631beb2 Merge git://git.denx.de/u-boot-mmc 2017-08-01 15:38:23 -04:00
VINITHA PILLAI
ec85721c8b arm64: ls2088ardb: Add distro secure boot support
Enable validation of boot.scr script prior to its execution dependent
on "secureboot" flag in environment. Also enable "secureboot=y"
flag in environment for ARM based platforms instead of bootcmd.

Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-01 08:28:57 -07:00
Zhang Ying-22455
0a09d20b29 arm64: ls2088ardb: Add distro boot support
Include common config_distro_defaults.h and config_distro_bootcmd.h
for u-boot enviroments to support automatical distro boot which
scan boot.scr from external storage devices(e.g. SD/USB/SATA/SCSI disk)
and execute autoboot script. Tested on ls2088ardb with automatically
boot Ubuntu from SD card or USB disk, if it fails to detect external
storage disk, fall back to nor/qspi boot.

Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-01 08:28:57 -07:00
Sumit Garg
b8ae67981f arm: ls1021atwr: Add distro secure boot support
Enable validation of boot.scr script prior to its execution dependent
on "secureboot" flag in environment. Disable fall back option to
qspi boot in case of secure boot. Also enable "secureboot=y" flag
in environment for ARM based platforms instead of bootcmd.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-01 08:28:57 -07:00
Sumit Garg
f7b75f8b34 arm64: ls1046ardb: Add distro secure boot support
Enable validation of boot.scr script prior to its execution dependent
on "secureboot" flag in environment. Disable fall back option to
qspi boot in case of secure boot. Also enable "secureboot=y" flag
in environment for ARM based platforms instead of bootcmd.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-01 08:28:57 -07:00
Sumit Garg
76bbf1c634 arm64: ls1043ardb: Add distro secure boot support
Enable validation of boot.scr script prior to its execution dependent
on "secureboot" flag in environment. Disable fall back option to
nor/qspi boot in case of secure boot. Also enable "secureboot=y"
flag in environment for ARM based platforms instead of bootcmd.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-01 08:28:57 -07:00
Qianyu Gong
8de227ee0b arm64: ls1046ardb: Add distro boot support
Tested on ls1046ardb with automatically boot Ubuntu from SD card or
USB disk, if it fails to detect external storage disk, fall back to
qspi boot.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-01 08:28:57 -07:00
Qianyu Gong
b171cd9f96 armv8: ls1046a: move CONFIG_CMD_USB to defconfig
Move the macro to defconfig to take effect globally.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-01 08:28:56 -07:00
Shengzhou Liu
5ba909f426 arm64: ls1043ardb: Add distro boot support
Include common config_distro_defaults.h and config_distro_bootcmd.h
for u-boot enviroments to support automatical distro boot which
scan boot.scr from external storage devices(e.g. SD/USB/SATA/SCSI disk)
and execute autoboot script. Tested on ls1043ardb with automatically
boot Ubuntu from SD card or USB disk, if it fails to detect external
storage disk, fall back to nor/qspi boot.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-01 08:28:56 -07:00
Santan Kumar
ec8a7d7743 soc/fsl-layerscape: Update SVR number for LS2081A and LS2041A
Update SVR as per the SOC document.
 -LS2081A: 0x870919 -> 0x870918
 -LS2041A: 0x870915 -> 0x870914

Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-01 08:28:56 -07:00
Santan Kumar
e478307918 fsl/usb: enable errata-a010151 for ls2088a and ls2081a
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-01 08:28:56 -07:00
Santan Kumar
0f4e1ace27 board/ls2080aqds, SD-boot: Update env offset
As per new memory layout, Update env offset
from 0x200000 to 0x300000

Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-01 08:28:56 -07:00
Alison Wang
020b3ce8ae armv8: Remove duplicate definition for IH_ARCH_ARM and IH_ARCH_ARM64
The duplicate definitions for IH_ARCH_ARM and IH_ARCH_ARM64 are removed.
The definitions in <image.h> are used.

According to this modification, the comparison between os arch and cpu
arch is done in C programming instead of ASM programming.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-01 08:28:56 -07:00
Alexander Stein
4df24f2c40 spi: fsl_qspi: Pet watchdog even more
Pet the watchdog once upon each command call (qspi_xfer) and during
each loop iteration in several commands.

This fixes a watchdog reset especially during erase command.

Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-01 08:28:56 -07:00
Alison Wang
a65d740821 arm: ls1021atwr: Add distro boot support
This patch includes common config_distro_defaults.h and
config_distro_bootcmd.h for u-boot enviroments to support distro boot
which automatically scan boot.scr from storage devices(e.g.
SD/USB/SATA/SCSI disk) and execute autoboot script on LS1021ATWR board.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-01 08:28:55 -07:00
Bin Meng
24357dfd2a x86: Switch all boards to use DM SCSI
After MMC is converted to DM, convert to use DM SCSI as well for all
x86 boards and imply BLK for both MMC and SCSI drivers.

CONFIG_SCSI_DEV_LIST is no longer used. Clean them up.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Simon Glass
b7c6baef28 x86: Convert MMC to driver model
Convert the pci_mmc driver over to driver model and migrate all x86 boards
that use it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: remove DM_MMC from edison_defconfig]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-01 20:17:02 +08:00
Bin Meng
52a1c2c68b block: ide: Fix build error when CONFIG_BLK is on
Add missing #ifndef CONFIG_BLK to wrap dev_desc->block_read.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Bin Meng
a5c680fe10 dm: scsi: Add a generic PCI-based AHCI driver
This adds support for PCI-based AHCI controller based on DM SCSI.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
xypron.glpk@gmx.de
6461f45b71 x86: ivybridge: remove unused uma_memory_size
The value of uma_memory_size depends on an undefined value
from the stack. The value of uma_memory_size is changed but
never used.

So simply remove this superfluous code.

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Bin Meng
724368928c x86: Convert INTEL_ICH6_GPIO to Kconfig
This converts Intel ICH6 GPIO driver to Kconfig, and add it to the
imply list of platform drivers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Bin Meng
b9342b2cc6 x86: kconfig: Move USB to platform Kconfig
Like other peripheral drivers, move USB related drivers to platform
Kconfig as well.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Bin Meng
1df7f0b6a0 x86: kconfig: Let board select SPI flash
Only a specific type of SPI flash exists on a board, having board
Kconfig to select the SPI flash seems to make more sense. Other
flash types are not necessary except coreboot, which implies all
available flash drivers there.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Bin Meng
31ba86e8d0 x86: qemu: Remove SPI flash from defconfigs
QEMU does not support ICH SPI controller yet. It's meaningless to
include SPI flash support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Bin Meng
97e12b06af x86: qemu: kconfig: Imply platform specific drivers
Imply Qemu-specific drivers in the platform Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Bin Meng
b0e3adf669 x86: quark: kconfig: Imply platform specific drivers
Imply Quark-specific drivers in the platform Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Bin Meng
71305b4478 x86: tangier: kconfig: Imply platform specific drivers
Imply Tangier-specific drivers in the platform Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Bin Meng
a65ae28618 x86: queensbay: kconfig: Imply platform specific drivers
Imply drivers that work with Intel Queensbay platform.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Bin Meng
08fb85b2a4 x86: coreboot: kconfig: Imply drivers that are useful
U-Boot as coreboot payload can run on any x86 hardware ideally.
Let's imply some common drivers that are useful.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Bin Meng
1b15ef9cd2 x86: broadwell: kconfig: Imply platform specific drivers
Imply Broadwell-specific drivers in the platform Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Bin Meng
a5b212942b x86: ivybridge: kconfig: Imply platform specific drivers
Imply drivers that are working with Ivybridge platform in the
platform Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Bin Meng
e88e1ef550 x86: baytrail: kconfig: Imply platform specific drivers
BayTrail integrates lots of peripherals that have U-Boot drivers.
Imply those in the platform Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Bin Meng
4f0faacb42 x86: kconfig: Imply DM uclass drivers
Now that all x86 boards have been converted to use DM, we can imply
these uclass drivers (DM_ETH, DM_RTC, DM_USB, DM_VIDEO) from the
top level.

Previously DM_GPIO, DM_KEYBOARD, DM_SERIAL, DM_SPI, DM_SPI_FLASH
are selected. Change to use 'imply' to allow them to be removed.

Note with this change, chromebook_link64 build fails:

common/built-in.o:(.data.env_htab+0xc): undefined reference to 'env_flags_validate'
lib/built-in.o: In function `hsearch_r':
lib/hashtable.c:380: undefined reference to 'env_callback_init'
lib/hashtable.c:382: undefined reference to 'env_flags_init'
make[1]: *** [spl/u-boot-spl] Error 1

CONFIG_SPL_ENV_SUPPORT is required for chromebook_link64 to build
again. This is just a workaround as it is not needed at all. See
commit bda40d5 "x86: qemu: Add a config for 64-bit U-Boot" for
the same issue seen on QEMU 64-bit target.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Bin Meng
263252c762 x86: kconfig: Select OF_CONTROL
This is a must have for all x86 boards.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Bin Meng
67f99f970f x86: kconfig: Imply ENABLE_MRC_CACHE in the platform Kconfig
Platform knows whether MRC cache is implemented, but using it can
be a choice of a specific board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Bin Meng
5d89b37f71 x86: kconfig: Select ARCH_EARLY_INIT_R in the platform Kconfig
This is architecture-dependent early initialization hence should
be put in the platform Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Bin Meng
3612b1efeb x86: kconfig: Select ARCH_MISC_INIT in the platform Kconfig
arch_misc_init() is intended to do architecture-dependent stuff.
This is required by each platform.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Bin Meng
30b1ecd265 x86: kconfig: Let board select BOARD_EARLY_INIT_F
CONFIG_BOARD_EARLY_INIT_F literally indicates board-specific codes
and should be not 'default y' for all x86 boards.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Bin Meng
1e452b4686 x86: kconfig: Imply HAVE_INTEL_ME in the platform Kconfig
Intel Management Engine is required by the platform, however it's
not a must have when building a U-Boot image. For example, during
development normally programming ME firmware is a one-time effort.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Bin Meng
6bf89de7e1 x86: kconfig: Select PCI and DM_PCI
PCI is the de facto interconnect bus in an x86 system.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Bin Meng
e28497bf4a x86: kconfig: Select USE_PRIVATE_LIBGCC
x86 is using the built-in libgcc implementation and this cannot be
turned off.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Bin Meng
0ce9c57620 x86: kconfig: Select TIMER and X86_TSC_TIMER
Without a timer, U-Boot just doesn't boot. This is not something
we can turn off.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Andy Shevchenko
c3df28f6e2 x86: Make table address selectable
Some firmwares might have another window for generated tables.

So, introduce two configuration options to select start address and
maximum length for the generated tables.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-01 20:17:02 +08:00
Bin Meng
167a40166b x86: tsc: Rename try_msr_calibrate_tsc() to cpu_mhz_from_msr()
Rename try_msr_calibrate_tsc() to cpu_mhz_from_msr(), as that
better describes what the routine does.

This keeps in sync with Linux kernel commit:
  02c0cd2: x86/tsc_msr: Remove irqoff around MSR-based TSC enumeration

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Bin Meng
f5757154bb x86: tsc: Correct Silvermont reference clock values
Atom processors use a 19.2 MHz crystal oscillator.

Early processors generate 100 MHz via 19.2 MHz * 26 / 5 = 99.84 MHz.

Later processors generate 100 MHz via 19.2 MHz * 125 / 24 = 100 MHz.

Update the Silvermont-based tables accordingly, matching the Software
Developers Manual.

Also, correct a 166 MHz entry that should have been 116 MHz, and add
a missing 80 MHz entry for VLV2.

This keeps in sync with Linux kernel commit:
  05680e7: x86/tsc_msr: Correct Silvermont reference clock values

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Bin Meng
c636774848 x86: tsc: Update comments and expand definitions in freq_desc_tables[]
Some processor abbreviations in the comments of freq_desc_tables[]
are obscure. This updates part of these to mention processors
that are known to us. Also expand frequency definitions.

This keeps in sync with Linux kernel commit:
  9e0cae9: x86/tsc_msr: Update comments, expand definitions

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Bin Meng
fde1801eaa x86: tsc: Remove the fail handling in try_msr_calibrate_tsc()
If either ratio or freq is zero, the return value is zero. There
is no need to create a fail branch and return zero there.

This keeps in sync with Linux kernel commit:
  14bb4e3: x86/tsc_msr: Remove debugging messages

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Bin Meng
0b992e4932 x86: tsc: Identify Intel-specific code
try_msr_calibrate_tsc() is currently Intel-specific, and should not
execute on any other vendor's parts.

This keeps in sync with Linux kernel commit:
  ba82683: x86/tsc_msr: Identify Intel-specific code

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Bin Meng
d92e9c8d31 x86: tsc: Read all ratio bits from MSR_PLATFORM_INFO
Currently we read the tsc radio like this:

	ratio = (MSR_PLATFORM_INFO >> 8) & 0x1f;

Thus we get bit 8-12 of MSR_PLATFORM_INFO, however according to the
Intel manual, the ratio bits are bit 8-15.

Fix this problem by masking 0xff instead.

This keeps in sync with Linux kernel commit:
  886123f: x86/tsc: Read all ratio bits from MSR_PLATFORM_INFO

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Bin Meng
e719b6b0f8 x86: Enforce toolchain to generate 64-bit codes for 64-bit U-Boot
64-bit U-Boot image is a combination of 32-bit U-Boot (SPL) plus
64-bit U-Boot (proper). For the U-Boot proper, it has be compiled
to 64-bit object codes. Attempting to use a toolchain to compile
64-bit U-Boot for qemu-x86_64, like kernel.org 4.9 i386-linux-gcc,
fails with the following errors:

  arch/x86/cpu/intel_common/microcode.c:79:2: error: PIC register
  clobbered by 'ebx' in 'asm'

The issue is because toolchain is preconfigured to generate code
for the 32-bit architecture (i386), and currently '-m64' is missing
in the makefile fragment. Using kernel.org 4.9 x86_64-linux-gcc
works out of the box, since it is preconfigured to generate 64-bit
codes.

When compiling U-Boot SPL, '-m32' is passed to the toolchain, no
mater 32-bit (i386-linux-) or 64-bit (x86_64-linux) the toolchain
is preconfigured to generate.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Bin Meng
9a95f51ffe x86: Use default stack boundary alignment
At present U-Boot x86 build is using -mpreferred-stack-boundary=2
which is 4 bytes stack boundary alignment. With 64-bit U-Boot, the
minimal required stack boundary alignment is 16 bytes.

If -mpreferred-stack-boundary is not specified, the default is 4
(16 bytes). Switch to use the default one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01 20:17:02 +08:00
Jean-Jacques Hiblot
5c970013a6 regulator: palmas: disable bypass when the LDO is enabled
Some LDOs have a bypass capability. Make sure that the bypass is disabled
when is the LDO is enabled (otherwise the voltage can't be changed).

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-01 11:58:01 +09:00
Kishon Vijay Abraham I
9554a14df2 regulator: palmas: Add support for LDO1 regulator to provide 1.8V
Modify palmas_mmc1_poweron_ldo() API to set the voltage based on the
voltage parameter passed as argument instead of always setting it to
3.0V. This allows MMC1 to set the LDO1 regulator voltage to 3.3V or 1.8V.
1.8V is required to add support for UHS mode.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-01 11:58:01 +09:00
Simon Glass
3936514b82 dm: sunxi: Move Linksprite_pcDuino3 to use DM for MMC, SATA
Move this board over to driver model for MMC and SATA. This means that it
uses CONFIG_BLK as well. In SPL these options remain turned off since it
increases the code size. One option would be to use CONFIG_SPL_OF_PLATDATA
to avoid device-tree overhead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-01 11:58:01 +09:00
Simon Glass
cf7b2e10c9 dm: sata: sunxi: Add support for driver model
Adjust SATA setup to support driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-08-01 11:58:01 +09:00
Simon Glass
74daf94a23 dm: sunxi: sata: Don't build sata support into SPL
This is not used in SPL so we do not need to compile it. Make this change
before adding driver-model support to the driver, to avoid build errors.
With driver model we define a U_BOOT_DRIVER() which would otherwise be
present in SPL and not be garbage-collected when building.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-08-01 11:58:01 +09:00
Simon Glass
8620f38409 dm: sunxi: Linksprite_pcDuino3: Correct polarity of MMC card detect
This is shown as active high in the schematics[1], so fix it.

[1] https://patchwork.ozlabs.org/patch/777890/

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-08-01 11:58:01 +09:00
Simon Glass
dd27918c22 dm: mmc: sunxi: Add support for driver model
Add a driver-model version of this driver which mostly uses the existing
code. The old code can be removed once all boards are switched over.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-01 11:58:01 +09:00
Simon Glass
ec73d96090 dm: mmc: sunxi: Drop mmc_clk_io_on()
This function has #ifdefs in it which we want to avoid for driver model.
Instead we should use different compatible strings and the .data field.
It also uses the MMC device number which is not available in driver
model except through aliases.

Move the function's into its caller so that the driver-model version can
do things its own way.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-08-01 11:58:01 +09:00
Simon Glass
034e226bc7 dm: mmc: sunxi: Pass private data around explicitly
At present the driver-private data is obtained in various functions by
various means. With driver model this is provided automatically. Without
driver model it comes from a C array declared at the top of the file.

Adjust internal functions so that they are passed the private data as
a parameter, allowing the caller to obtain it using either means.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-08-01 11:58:01 +09:00
Simon Glass
3f5af12a5d dm: mmc: sunxi: Rename mmchost to priv
Use the driver-model naming convention for this structure. It is data
private to the driver so the local variable should be called 'priv'.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-08-01 11:58:01 +09:00
Simon Glass
e3c794e2fa dm: mmc: sunxi: Rename struct sunxi_mmc_host to sunxi_mmc_priv
Use the driver-model naming convention for this structure. It is data
private to the driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-08-01 11:58:01 +09:00
Simon Glass
bfc1c6b483 dm: ahci: Correct uclass private data
This is expected to be attached to the uclass and the code operates that
way, but the uclass has not been updated. Fix it to avoid using memory at
address 0.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 47fc61a (dm: ahci: Drop use of probe_ent)
2017-08-01 11:58:01 +09:00
Simon Glass
068a2fc1d5 dm: scsi: Drop duplicate SCSI and DM_SCSI options
When the SATA code was moved into drivers/ata these Kconfig options were
added to that directory. They already exist in drivers/scsi. Remove them
from drivers/ata to fix the duplication.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 7f2b5f4 (sata: Move drivers into new drivers/ata directory)
2017-08-01 11:58:01 +09:00
Simon Glass
336a44877a fdt: Correct fdt_get_base_address()
This function appears to obtain the value of the 'ranges' property rather
than 'reg'. As such it does not behave as documented or expected.

In addition it picks up the second field of the property which is the size
(with prop += naddr) rather than the first which is the address.

Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-01 11:58:00 +09:00
Simon Glass
c4d660d4d0 dm: mmc: Allow disabling driver model in SPL
At present if U-Boot proper uses driver model for MMC, then SPL has to
also. While this is desirable, it places a significant barrier to moving
to driver model in some cases. For example, with a space-constrained SPL
it may be necessary to enable CONFIG_SPL_OF_PLATDATA which involves
adjusting some drivers.

Add new SPL versions of the options for DM_MMC, DM_MMC_OPS and BLK. By
default these follow their non-SPL versions, but this can be changed by
boards which need it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-01 11:58:00 +09:00
Simon Glass
745a94f352 ahci: Support non-PCI controllers
At present the AHCI SCSI driver only supports PCI with driver model.
Rename the existing function to indicate this and add support for adding
a non-PCI controller .

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-01 11:58:00 +09:00
Tom Rini
6364a5d4bd Prepare v2017.09-rc1
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-31 20:37:25 -04:00
Tom Rini
eddc7dabe0 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-31 18:59:01 -04:00
Tom Rini
8f1a80e99e configs: Migrate CMD_NAND*
Migrate all remaining instances of CMD_NAND, CMD_NAND_TRIMFFS
CMD_NAND_LOCK_UNLOCK and CMD_NAND_TORTURE from the headers into the
defconfig files.

Tested-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-31 12:21:40 -04:00
Simon Glass
7b3c4c3a53 dm: console: Check for serial devices properly
With driver model the serial device is often not called "serial". Mark
driver-model stdio devices so that they can be detected and we can look up
the uclass. This is a more reliable way of finding out whether the console
is connected to a serial device or not.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-31 12:21:40 -04:00
Simon Glass
42f9f915c2 console: Unify the check for a serial console
Put the check for whether a console is a serial device in a function so
that we can share the code in the two places that use it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-31 12:21:40 -04:00
Andrew F. Davis
ef3fc42ded arm: mach-omap2: Align image address before cache operations
The image address passed to secure_boot_verify_image() may not be
cacheline aligned, round the address down to the nearest cacheline.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-07-31 12:21:39 -04:00
Tom Rini
c826d17286 ti: Default to ENV_IS_IN_FAT if MMC_OMAP_HS
When we have MMC available we assume that we want to put the env as a
file on FAT.

Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-31 12:21:25 -04:00
Tom Rini
3c7be0c91a am335x_hs_evm: Disable CONFIG_SPL_ENV_SUPPORT
The main uses of CONFIG_SPL_ENV_SUPPORT are for network support and for
disabling "Falcon Mode" support at run-time.  As this build enables
neither, remove this feature.

Cc: Andrew F. Davis <afd@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-31 11:22:56 -04:00
Tom Rini
43ba3c59cb env: Migrate CONFIG_ENV_IS_IN_FAT options to Kconfig
We rename the various FAT_ENV_xxx options to CONFIG_ENV_FAT_xxx so that
they can be modified via Kconfig.  Migrate all existing users to the new
values.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-31 11:22:56 -04:00
Adam Ford
3158eebd21 Remove unused CONFIG_TWL4030_PWM
CONFIG_TWL4030_PWM is not being used by any source, so let's remove the #define
and the whitelist entry

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-31 11:22:55 -04:00
Patrice Chotard
84e9dcc120 serial: stm32x7: Convert CONFIG_STM32X7_SERIAL to Kconfig
Add CONFIG_STM32X7_SERIAL as a Kconfig option.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-07-31 11:22:54 -04:00
Philipp Tomsich
0fa0abecfc dm: Kconfig: fix typo in help for SPL_PINCTRL
Changes 'controlloers' to 'controllers' in the help-text for
SPL_PINCTRL.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-31 11:22:53 -04:00
Alexander Graf
c1ae1a1608 efi_loader: Fix warning in efi_gop
Commit ca9193d2b1 ("efi_loader: gop: fixes for CONFIG_DM_VIDEO without
CONFIG_LCD") dropped the explicit (void*) cast for fb_base in efi gop support
for CONFIG_LCD without DM. This patch adds it back, eliminating the now occuring
warning again

Fixes: ca9193d2b1 ("efi_loader: gop: fixes for CONFIG_DM_VIDEO without CONFIG_LCD")
Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-31 07:28:13 -04:00
Tom Rini
2218b32d88 Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot
Patch queue for efi - 2017-07-29

A lot of EFI greatness this time around. Thanks a lot to the
two amazing new contributors

  Heinrich Schuchardt and
  Rob Clark

we now gain

  - stable objects across multiple bootefi invocations
  - fixes for shim
  - fixes for ipxe
  - protocol installation
  - device path conversion to/from text
  - working "lsefi" support in grub
  - working notifiers
  - various bug fixes
2017-07-31 07:27:45 -04:00
Bin Meng
55f228b07e x86: minnowmax: Remove CONFIG_SMSC_LPC47M
There is no SMSC LPC47M Super I/O chipset on the MinnowMax board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-30 10:30:25 +08:00
Andy Shevchenko
382fabb297 x86: acpi: Don't touch hardware on HW reduced platforms
If ACPI HW reduced bit in FADT is set we should ignore any ACPI hardware
communications.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-30 10:30:25 +08:00
Andy Shevchenko
ace7762b28 x86: acpi: Export acpi_fill_mcfg() with __weak attribute
Some platforms might require different approach when filling memory
mappings configuration table.

Allow them to override the common method.

At the same time export acpi_create_mcfg_mmconfig().

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-30 10:30:25 +08:00
Andy Shevchenko
b156da91fb x86: acpi: Deduplicate acpi_fill_madt() implementation
In Baytrail and Quark support code acpi_fill_madt() is identical.

Deduplicate its implementation by moving to lib/acpi_tables.c.

At the same time mark acpi_fill_madt() with __weak attribute to keep a
possibility to override it in platform code

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-30 10:30:25 +08:00
Andy Shevchenko
2dcbef6f6c x86: acpi: Name fields in FADT in accordance with specification
ACPI specification defines FADT fields marked as reserved in U-Boot.

Name these fields in accordance with ACPI specification.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-30 10:30:25 +08:00
Andy Shevchenko
684c4cd011 x86: acpi: Fill OEM revision
Fill OEM revision field in the tables by U-Boot build date.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-30 10:30:25 +08:00
Andy Shevchenko
e7aa9c2947 Makefile: Export build date as integer
In some cases we would need build date as integer value.
Export U_BOOT_BUILD_DATE as %Y%m%d integer value.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-30 10:30:25 +08:00
Andy Shevchenko
06054b1a62 Makefile: Don't shadow actual error when compile ASL
If ASL compiler failed by any reason do not produce output C file.
Otherwise sequential run of make will shadow the actual error in ASL,
i.e.

  CC      board/intel/edison/dsdt.o
board/intel/edison/dsdt.c:1:1: error: unterminated comment
 /*

and user has to remove dsdt.c and run make in order to see the error again.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-30 10:30:25 +08:00
Stefan Roese
66712c298d x86: conga-qeval20-qa3-e3845.dts: Enable xHCI support in dts
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-30 10:30:25 +08:00
Stefan Roese
1f4e25780a x86: dfi-bt700: Add xHCI USB support
Change from EHCI to xHCI on the DFI BayTrail SoM.

The xHCI USB hub is connected to an GPIO on the DFI BayTrail SoM. For
correct operation, it needs to get reset upon power-up. Otherwise it
may happen that the hub is not detected after a software reboot. This
patch also configures this GPIO in the dts for correct operation.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-30 10:30:25 +08:00
Stefan Roese
db1d20a904 x86: conga-qeval20-qa3-e3845: Select CONFIG_BOARD_LATE_INIT
This config option is needed on the congatec x86 BayTrail board, as
otherwise the USB hub will not get initialized correctly. This
patch selects this Kconfig option again.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-30 10:30:25 +08:00
Stefan Roese
68b3f8d8c4 x86: theadorable-x86-dfi-bt700: Add Spansion SPI support and move VIDEO blob
To support the Spansion SPI NOR flashes, this patch enables the support in
defconfig. This increases the U-Boot binary too much so that it does
not fit into its area in the ROM. So also move the VIDEO BIOS blob
a bit to make some space here.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-30 10:30:25 +08:00
Andy Shevchenko
495f3774be x86: Add Intel Edison board files
Add Intel Edison board which is using U-Boot.

The patch is based on work done by the following people (in alphabetical
order):
	Aiden Park <aiden.park@intel.com>
	Dukjoon Jeon <dukjoon.jeon@intel.com>
	eric.park <eric.park@intel.com>
	Fabien Chereau <fabien.chereau@intel.com>
	Felipe Balbi <felipe.balbi@linux.intel.com>
	Scott D Phillips <scott.d.phillips@intel.com>
	Sebastien Colleur <sebastienx.colleur@intel.com>
	Steve Sakoman <steve.sakoman@intel.com>
	Vincent Tinelli <vincent.tinelli@intel.com>

In case we're building for Intel Edison, we must have 4096 bytes of
zeroes in the beginning on u-boot.bin. This is done in
board/intel/edison/config.mk.

First run sets hardware_id environment variable which is read from
System Controller Unit (SCU).

Serial number (serial# environment variable) is generated based on eMMC
CID.

MAC address on USB network interface is unique to the board but kept the
same all over the time.

Set mac address from U-Boot using following scheme:
	OUI = 02:00:86
	next 3 bytes of MAC address set from eMMC serial number

This allows to have a unique mac address across reboot and flashing.

Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[bmeng: Add MAINTAINERS file for Intel Edison board]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-30 10:30:25 +08:00
Felipe Balbi
e71de54a49 x86: Add Intel Tangier support
Add Intel Tangier SoC support.

Intel Tangier SoC is a core part of Intel Merrifield platform. For
example, Intel Edison board is based on such platform.

The patch is based on work done by the following people (in alphabetical
order):
	Aiden Park <aiden.park@intel.com>
	Dukjoon Jeon <dukjoon.jeon@intel.com>
	eric.park <eric.park@intel.com>
	Fabien Chereau <fabien.chereau@intel.com>
	Scott D Phillips <scott.d.phillips@intel.com>
	Sebastien Colleur <sebastienx.colleur@intel.com>
	Steve Sakoman <steve.sakoman@intel.com>
	Vincent Tinelli <vincent.tinelli@intel.com>

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2017-07-30 10:30:25 +08:00
Andy Shevchenko
b7026b0c98 x86: Add dma-mapping.h to architectural code
Some cross-platform drivers rely on this header present.
Make it so for x86.

It's just a copy'n'paste of arch/arm/include/asm/dma-mapping.h.

Suggested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2017-07-30 10:30:25 +08:00
Felipe Balbi
8f8a12d1e7 watchdog: Introduce watchdog driver for Intel Tangier
Add watchdog driver for Intel Tangier based platforms.

Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-30 10:30:25 +08:00
Andy Shevchenko
611dbb7f95 arch/x86: Select USB before selecting host driver
Kbuild complains if USB is not selected before any of host driver.

warning: (X86) selects USB_EHCI_HCD which has unmet direct dependencies (USB)
warning: (X86) selects USB_EHCI_HCD which has unmet direct dependencies (USB)

Select it for X86.

Fixes: 64d6ac5bc4 ("Kconfig: USB: Migrate CONFIG_USB_EHCI_HCD users to Kconfig")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
[bmeng: Update all x86 boards' defconfig files to remove CONFIG_USB]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-30 10:30:25 +08:00
Tom Rini
19d1f1a2f3 Merge git://git.denx.de/u-boot-socfpga 2017-07-29 11:44:08 -04:00
Tom Rini
211aaf309c Merge git://git.denx.de/u-boot-usb 2017-07-29 11:43:51 -04:00
Rob Clark
af65db85b8 efi_loader: indent entry/exit prints to show nesting level
This should make it easier to see when a callback back to UEFI world
calls back in to the u-boot world, and generally match up EFI_ENTRY()
and EFI_EXIT() calls.

Signed-off-by: Rob Clark <robdclark@gmail.com>
[agraf: remove static from const var]
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-29 00:18:46 +02:00
Rob Clark
c160d2f5ec efi_loader: add checking for incorrect use of EFI_ENTRY/EXIT
Missing an EFI_ENTRY() or doubling up EFI_EXIT() leads to non-obvious
crashes.  Let's add some error checking.

Signed-off-by: Rob Clark <robdclark@gmail.com>
[agraf: fix bogus assert() and fix app_gd breakage]
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-29 00:18:24 +02:00
Patrice Chotard
b108d8a0de clk: fix compilation errors for poplar platform
Move clk_release_all() prototype and definition inside
OF_CONTROL flag to avoid following compilation error for
poplar platform:

aarch64:  +   poplar
+drivers/usb/host/built-in.o: In function `ehci_usb_remove':
+drivers/usb/host/ehci-generic.c:159: undefined reference to `clk_release_all'
+drivers/usb/host/built-in.o: In function `ehci_usb_probe':
+drivers/usb/host/ehci-generic.c:133: undefined reference to `clk_release_all'
+make[1]: *** [u-boot] Error 139
+make: *** [sub-make] Error 2

Introduced by 4e542c4 clk: add clk_release_all()

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-07-28 23:34:46 +02:00
Patrice Chotard
d38a8ea19c usb: host: xhci-dxc3: fix compilation warnings
Fix following warnings encountered with platforms
dra7xx_evm and dra7xx_hs_evm :

       arm:  +   dra7xx_evm
+  hccr = (struct xhci_hccr *)devfdt_get_addr(dev);
+         ^
+  hcor = (struct xhci_hcor *)((phys_addr_t)hccr +
+                              ^
w+drivers/usb/host/xhci-dwc3.c: In function 'xhci_dwc3_probe':
w+drivers/usb/host/xhci-dwc3.c:124:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
w+drivers/usb/host/xhci-dwc3.c:125:30: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
w+drivers/usb/host/xhci-dwc3.c:125:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
       arm:  +   dra7xx_hs_evm
+  hccr = (struct xhci_hccr *)devfdt_get_addr(dev);
+         ^
+  hcor = (struct xhci_hcor *)((phys_addr_t)hccr +
+                              ^
w+drivers/usb/host/xhci-dwc3.c: In function 'xhci_dwc3_probe':
w+drivers/usb/host/xhci-dwc3.c:124:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
w+drivers/usb/host/xhci-dwc3.c:125:30: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
w+drivers/usb/host/xhci-dwc3.c:125:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]

Introduced by 7e65e84 usb: host: xhci-dwc3: Convert driver to DM

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-07-28 23:34:45 +02:00
Jean-Jacques Hiblot
3b63db37ad phy: add a NO-OP phy driver
This driver is used to stub PHY operations in a driver (USB, SATA).
This is useful when the 'client' driver (USB, SATA, ...) uses the PHY
framework and there is no actual PHY harwdare to drive.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2017-07-28 23:34:44 +02:00
Patrice Chotard
2080d023d9 usb: host: ohci-generic: initialize PHY only when found
Call generic_phy_init() only when a PHY was found.
This will avoid a crash if no "phys" property is found in DT.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reported-by: Patrick Delaunay <patrick.delaunay@st.com>
2017-07-28 23:34:43 +02:00
Patrice Chotard
4b3928a08f usb: host: ehci-generic: initialize PHY only when found
Call generic_phy_init() only when a PHY was found.
This will avoid a crash if no "phys" property is found in DT.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reported-by: Patrick Delaunay <patrick.delaunay@st.com>
2017-07-28 23:34:43 +02:00
Patrice Chotard
623b7aca1f dm: usb: host: xhci-dwc3: add missing #ifdef CONFIG_DM_USB
Add CONFIG_DM_USB flag to avoid following compilation errors
detected by buildman :
+drivers/usb/host/built-in.o: In function `xhci_dwc3_remove':
+drivers/usb/host/xhci-dwc3.c:168: undefined reference to `xhci_deregister'
+drivers/usb/host/built-in.o: In function `xhci_dwc3_probe':
+drivers/usb/host/xhci-dwc3.c:145: undefined reference to `usb_get_dr_mode'
+drivers/usb/host/xhci-dwc3.c:152: undefined reference to `xhci_register'

introduced by patch d5c3f014da3 "usb: host: xhci-dwc3: Convert driver to DM"

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reported-by: Ran Wang <ran.wang_1@nxp.com>
2017-07-28 23:34:42 +02:00
Patrice Chotard
d9fb7bece0 dm: phy: add missing #ifdef CONFIG_PHY
To avoid compilation breakage on platform that doesn't
support DM PHY but uses xhci-dwc3 driver, add the missing
CONFIG_PHY flag.

Introduced by patch :
84e53877 "usb: host: xhci-dwc3: Add generic PHY support"

Cc: Ran Wang <ran.wang_1@nxp.com>
Cc: Bin Meng <bmeng.cn@gmail.com>

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reported-by: Ran Wang <ran.wang_1@nxp.com>
2017-07-28 23:34:41 +02:00
Patrick Delaunay
6fa8dddd06 dfu: add common function to initiate transaction
- factorize code between read and write transaction
- always use dfu_transaction_cleanup() to initialize
  the internal variable: easy maintenance
- replace direct access by dfu_get_buf() and dfu_get_buf_size()

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2017-07-28 23:34:40 +02:00
Patrick Delaunay
57da060755 dfu: factorize transaction cleanup
rename cleanup function, as now called by read

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2017-07-28 23:34:40 +02:00
Patrick Delaunay
15970d871c dfu: remove limitation on partition size
Change long (32 bits on arm) to u64 (same type than offset)
for size and read offset r_left

So partition and device used for DFU can be greater than 4GB

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2017-07-28 23:34:39 +02:00
Patrick Delaunay
4de512018b dfu: allow dfu read on partition greater than 2GB
solve issue on get_medium_size() function
the detection of error is a simple test < 0
but for ARM platform, long is 32bits and 2GB = 0x80000000
is seen as error.

I solve the issue by changing the prototype fo the function
to separate size and result.
This patch prepare the next patch with size change to u64.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2017-07-28 23:34:38 +02:00
Siva Durga Prasad Paladugu
bab0146ea9 usb: gadget: f_thor: Free the allocated out request buffer
Fix the memory leak by freeing the allocated out request buffer

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-07-28 23:34:38 +02:00
Bin Meng
78e3098752 usb: xhci: Enable TT to support LS/FS devices behind a HS hub
So far LS/FS devices directly attached to xHC root port can be
successfully enumerated by xHCI driver, but if they are connected
behind a hub, the enumeration process fails to address the device.

It turns out xHCI driver still misses a part that in the device's
input slot context, all Transaction Translator (TT) related fields
are not programmed. The xHCI spec defines how to enable TT.

Now LS/FS devices like USB keyboard/mouse can be enumerated behind
a high speed hub.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:37 +02:00
Bin Meng
196ef8323c usb: xhci: Correct TT_SLOT and TT_PORT macros
These two macros really need a parameter to make them useful.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:36 +02:00
Bin Meng
d228ca362b usb: xhci: Implement update_hub_device() operation
There is no way to know whether the attached device is a hub or
not in advance before the device's descriptor is fetched. But
once we know it's a high speed hub, per the xHCI spec, we need
to tell xHC it's a hub device by initializing hub-related fields
in the input slot context.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:36 +02:00
Bin Meng
81060bb1c0 usb: hub: Call usb_update_hub_device() after hub descriptor is fetched
After fetching hub descriptor, we need to call USB uclass operation
update_hub_device() to notify HCD to do some preparation work.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:35 +02:00
Bin Meng
9ca1b4bab1 dm: usb: Add a new USB controller operation 'update_hub_device'
For USB host controllers like xHC, its internal representation of
hub needs to be updated after the hub descriptor is fetched. This
adds a new op that does this.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:35 +02:00
Bin Meng
5624dfd5aa usb: hub: Parse and save TT details from device descriptor
A high speed hub has a special responsibility to handle full speed/
low speed devices connected on downstream ports. In this case, the
hub must isolate the high speed signaling environment from the full
speed/low speed signaling environment with the help of Transaction
Translator (TT). TT details are provided by hub descriptors and we
parse and save it to hub uclass_priv for later use.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:34 +02:00
Bin Meng
493b8dd070 usb: xhci: Program 'route string' in the input slot context
xHCI spec says: the values of the 'route string' field shall be
initialized by the first 'Address Device' command issued to a
device slot, and shall not be modified by any other command.

So far U-Boot does not program this field, and it does not prevent
SS device directly attached to root port, or HS device behind an HS
hub, from working, due to the fact that 'route string' is used by
the xHC to target SS packets. But in order to enumerate devices
behind an SS hub, this field must be programmed.

With this commit and along with previous commits, now SS & HS devices
attached to a USB 3.0 hub can be enumerated by U-Boot.

As usual, this new feature is only available when DM is on.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:33 +02:00
Bin Meng
daec469144 usb: xhci: Change xhci_setup_addressable_virt_dev() signature
For future extension, change xhci_setup_addressable_virt_dev()
signature to accept a pointer to 'struct usb_device', instead
of its members slot_id & speed, as the struct already contains
these two plus some other useful information of the device.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:33 +02:00
Bin Meng
bbc6f06c00 usb: hub: Support 'set hub depth' request for USB 3.0 hubs
USB 3.0 hub uses a hub depth value multiplied by four as an offset
into the 'route string' to locate the bits it uses to determine the
downstream port number. We shall set the hub depth value of a USB
3.0 hub after it is configured.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:32 +02:00
Bin Meng
74ffc7cbb1 usb: hub: Translate USB 3.0 hub port status into old version
USB 3.0 hub port status field has different bit positions from 2.0
hubs. Since U-Boot only understands the old version, translate the
new one into the old one.

Since we are going to add USB 3.0 hub support, this feature is only
available with driver model USB.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:31 +02:00
Bin Meng
46c1d49330 usb: hub: Add a new API to test if a hub device is root hub
Sometimes we need know if a given hub device is root hub or not.
Add a new API to test this. This removes the xHCI driver's own
version is_root_hub() and change to use the new API.

While we are here, remove the unused/commented out get_usb_device()
in the xHCI driver too.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-28 23:34:30 +02:00
Bin Meng
a199a72448 usb: hub: Remove hub_port_reset()
At present hub_port_reset() is defined in DM USB, but it is never
called hence remove it (removing another ifdefs).

While we are here, change legacy_hub_port_reset() name to
usb_hub_port_reset() to better match other function names in the
same hub module.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:30 +02:00
Bin Meng
dfa96e0676 usb: hub: Use 'struct usb_hub_device' as hub device's uclass_priv
Use USB hub device's dev->uclass_priv to point to 'usb_hub_device'
so that with driver model usb_hub_reset() and usb_hub_allocate()
are no longer needed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:29 +02:00
Bin Meng
5e941943d8 usb: xhci-pci: Clean up the driver a little bit
This cleans up the driver a little bit.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:29 +02:00
Bin Meng
978f6a3b14 usb: xhci-pci: Drop non-DM version of xhci-pci driver
As there is no board that currently uses xhci-pci driver without DM
USB, drop its support and leave only DM support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:28 +02:00
Bin Meng
c9621012a6 x86: minnowmax: Enable USB xHCI support
BayTrail SoC supports both EHCI and xHCI controllers. However only
one host controller (either EHCI or xHCI) can be used. To enable
HSIC and SS ports, xHCI must be used. This turns on xHCI support on
Intel MinnowMax board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:27 +02:00
Bin Meng
6e4d039aaa x86: minnowmax: Add a environment variable for USB power-on delay
Occasionally it was observed that on Intel MinnowMax board, with a
USB 2.0 device connected to the bottom port, when doing 'usb start'
on the xHCI controller:

  scanning bus 0 for devices... cannot reset port 3!?

But neither of the two USB ports is routed to xHCI root port 3.
Adding some debug information shows that xHCI port 3 PORTSC register
mysteriously reports both CCS = 1 and CSC = 1.

This is not seen every time. After increasing the timeout to wait
for power to become stable, the issue is gone. So this indicates
current default USB power-on delay (20ms) might be at a critical
region where power is stable/unstable. U-Boot provides a mechanism
to have a environment variable to override the default one. Add
one for MinnowMax.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:27 +02:00
Bin Meng
d7cde28113 usb: xhci: Convert CONFIG_USB_XHCI_PCI to Kconfig
Add CONFIG_USB_XHCI_PCI as a Kconfig option.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:26 +02:00
Bin Meng
78abf14fc2 usb: cmd: Print actual packet size for super speed devices
USB 3.0 defines bMaxPacketSize0 field in the device descriptor as
the exponent of 2, so let's print the calculated actual size.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:25 +02:00
Bin Meng
cbb89ed026 configs: Remove CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS in all boards
Now that EHCD does not use CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS,
remove it in all boards' config files.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:24 +02:00
Bin Meng
99c2255688 usb: ehci: Get rid of CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS
EHC reports supported maximum number of ports in the HCSPARAMS
register, so it's unnecessary to use a hardcoded config option
CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:23 +02:00
Bin Meng
2931342874 configs: Remove CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS in all boards
Now that xHCD does not use CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS,
remove it in all boards' config files.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:23 +02:00
Bin Meng
7274671e04 usb: xhci: Get rid of CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS
xHC reports supported maximum number of ports in the HCSPARAMS1
register, so it's unnecessary to use a hardcoded config option
CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:22 +02:00
Bin Meng
1bdcd9019d usb: xhci: Change MAX_HC_PORTS to 255
HCSPARAMS1:MaxPorts field specifies the maximum port number value,
and its valid values are in the range of 1 to 255.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:21 +02:00
Bin Meng
98ba3d6c23 usb: hub: Add 3.0 hub port status mask of 2.0 hub
USB 3.0 hub port status has different bit position regarding to
port power, port speed, etc. But others are the same as 2.0 hubs.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:21 +02:00
Bin Meng
337fc7e665 usb: hub: Change USB hub descriptor to match USB 3.0 hubs
USB 3.0 hubs have a slightly different hub descriptor than USB 2.0
hubs, with a fixed (rather than variable length) size. Change the
host controller drivers that access those last two fields
(DeviceRemovable and PortPowerCtrlMask) to use the union.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:20 +02:00
Bin Meng
53771a490e usb: hub: Revise wLength for 'get port status' request
For accuracy, we should use 'sizeof(struct usb_port_status)' as the
wLength for 'get port status' request, although it happens to be
equal to 'sizeof(struct usb_hub_status)'.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:19 +02:00
Bin Meng
f342119602 usb: hub: Send correct wValue to get hub descriptor of a USB 3.0 hub
Testing a USB 3.0 hub by connecting it to the xHCI port on Intel
MinnowMax, when issuing 'get hub descriptor' to the hub, xHCI
reports a transfer event TRB with a completion code 6 which means
'Stall Error'.

In fact super speed USB hub descriptor type is 0x2a, not 0x29.
Sending correct SETUP packet to the hub makes it not stall anymore.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:18 +02:00
Bin Meng
f7a9e5dd03 usb: hub: Update handling connect status/change in usb_scan_port()
It was observed that on Intel MinnowMax board, when xHCI is enabled
in the BayTrail SoC, with a USB 3.0 device connected to the bottom
USB 3.0 port (mapped to xHCI root port #7), its PORTSC register is
always 0x201203 (CCS = 1, CSC = 0). The root cause of such behavior
is unknown yet. Connect status change bit is set on the same port
with a USB 2.0 device (mapped to xHCI port #1, which is a different
port on the root hub).

With current logic in usb_scan_port(), the enumeration process will
abort if it does not detect a connect status change on a hub port.
However since a device connection status is correctly reported, the
enumeration process can still continue.

With this change, USB device connected to the bottom blue port on
MinnowMax board can be enumerated under either SS or HS mode.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Dinh Nguyen <dinguyen@kernel.org>
2017-07-28 23:34:18 +02:00
Bin Meng
aab0db08c0 usb: xhci: Add input slot context in xhci_set_configuration()
A valid input slot context for a 'configure endpoint' command requires
the 'Context Entries' field to be initialized to the index of the last
valid endpoint context that is defined by the target configuration. We
set up the 'Context Entries' field, but we forget to include the input
slot context in the input control context 'Add Context flags' bitmap.
So xHC will simply ignore input slot context and continue using its own
which contains old information of the device.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:17 +02:00
Bin Meng
209b98de01 usb: xhci: Initialize scratchpad buffer array and scratchpad buffers
The scratchpad buffer array is used to define the locations of
statically allocated memory pages that are available for the
private use of the xHC. The xHCI spec explicitly mentions that
system software shall allocate the scratchpad buffers before
placing the xHC in to Run mode (Run/Stop (R/S) = ‘1’), however
U-Boot is missing this part.

This causes xHC on Intel platform does not respond the very first
'enable slot' command that is given to xHC and the 'enable slot'
command completion event TRB is never generated and xHC seems to
hang forever.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:16 +02:00
Bin Meng
43eb0d4488 usb: xhci: Correct command TRB 4th dword initialization
In xhci_queue_command(), when the command is not 'reset endpoint',
'stop endpoint' or 'set TR dequeue pointer', endpoint ID should not
be encoded in the TRB.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:15 +02:00
Bin Meng
f2e0315e9d usb: xhci: Remove incorrect comments for struct xhci_container_ctx
There is no member called 'dma' in struct xhci_container_ctx. Remove
the comments that mentions it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:14 +02:00
Patrice Chotard
28df1cfddd usb: host: ohci-generic: add generic PHY support
Extend ohci-generic driver with generic PHY framework

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:14 +02:00
Patrice Chotard
8a51b4b3da usb: host: ohci-generic: add RESET support
use array to save deasserted resets reference in order to
assert them in case of error during probe() or during driver
removal.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:13 +02:00
Patrice Chotard
155d9f65d3 usb: host: ohci-generic: add CLOCK support
use array to save enabled clocks reference in order to
disabled them in case of error during probe() or during
driver removal.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:11 +02:00
Patrice Chotard
0d0ba1a73d usb: host: ehci-generic: add generic PHY support
Extend ehci-generic driver with generic PHY framework

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:10 +02:00
Patrice Chotard
a1cee8e808 usb: host: ehci-generic: add error path and .remove callback
Use an array to save enabled clocks reference and deasserted resets
in order to respectively disabled and asserted them in case of error
during probe() or during driver removal.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:09 +02:00
Patrice Chotard
10bb775e92 usb: host: ehci-generic: replace printf() by error()
this allows to get file, line and function location
of the current error message.

Signed-off-by: patrice chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:09 +02:00
Patrice Chotard
642346ae26 dm: core: add ofnode_count_phandle_with_args()
This function is usefull to get phandle number contained
in a property list.
For example,  this allows to allocate the right amount
of memory to keep clock's reference contained into the
"clocks" property.

To implement it, either of_count_phandle_with_args() or
fdtdec_parse_phandle_with_args() are used respectively
for live tree and flat tree.
By passing index = -1, these 2 functions returns the
number of phandle contained into the property list.

Add also the dev_count_phandle_with_args() based on
ofnode_count_phandle_with_args()

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:08 +02:00
Patrice Chotard
82a8a669b4 clk: add clk_release_all()
Add clk_release_all() method which Disable/Free an
array of clocks that has been previously requested by
clk_request/get_by_*()

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:08 +02:00
Patrice Chotard
3b9d1bdd4e reset: add reset_release_all()
Add reset_release_all() method which Assert/Free an
array of resets signal that has been previously successfully
requested by reset_get_by_*()

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:07 +02:00
Patrice Chotard
9bd5cdf6b6 reset: add reset_request()
This is needed in error path to assert previously deasserted
reset by using a saved reset_ctl reference.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:06 +02:00
Patrice Chotard
f56db163ad usb: host: xhci-dwc3: Add generic PHY support
Add support of generic PHY framework support

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:05 +02:00
Patrice Chotard
b94888b4c0 drivers: phy: add generic_phy_valid() method
This allow to check if a PHY has been correctly
initialised and avoid to get access to phy struct.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-07-28 23:34:05 +02:00
Patrice Chotard
b9688df3cb drivers: phy: Set phy->dev to NULL when generic_phy_get_by_index() fails
phy->dev need to be set to NULL in case of generic_phy_get_by_index()
fails. Then phy->dev can be used to check if the phy is valid

Reported-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:04 +02:00
Patrice Chotard
576e3cc700 usb: host: xhci-dwc3: Add dual role mode support from DT
DWC3 dual role mode is selected using DT "dr_mode"
property. If not found, DWC3 controller is configured
in HOST mode by default

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 23:34:03 +02:00
Patrice Chotard
b7c1c7d2ba usb: host: xhci-dwc3: Convert driver to DM
Add Driver Model support with use of generic DT
compatible string "snps,dwc3"

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-28 23:34:02 +02:00
Masahiro Yamada
121a4d13e6 usb: add static to local symbols
Sparse reports "... was not declared. Should it be static?"

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-07-28 23:34:01 +02:00
Simon Glass
32ca40bf8b dm: tegra: Move nyan-big, jetson-tk1/tx1, beaver to livetree
Change these board to use a live device tree after relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:48 -06:00
Simon Glass
f6a4093ba0 fdtdec: Drop old compatible values
These are not needed now since the drivers now use driver model. Drop
them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:48 -06:00
Simon Glass
e3f44f5c89 dm: power: Convert as3722 to driver model
Convert this PMIC driver to driver model and fix up other users. The
regulator and GPIO functions are now handled by separate drivers.

Update nyan-big to work correct. Three boards will need to be updated by
the maintainers: apalis-tk1, cei-tk1-som. Also the TODO in the code re
as3722_sd_set_voltage() needs to be completed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
c2012cb47c power: Add a GPIO driver for the as3722 PMIC
This pmic includes GPIOs which should have their own driver. Add
a driver to support these.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
deea211aec power: Add a regulator driver for the as3722 PMIC
This pmic includes regulators which should have their own driver. Add
a driver to support these.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
68f0081139 dm: tegra: pci: Convert to livetree
Update the tegra pci driver to support a live device tree. Fix the check
for nvidia,num-lanes so that an error will actually be detected.

Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
49cb9308c4 dm: tegra: mmc: Convert to livetree
Update the tegra mmc driver to support a live device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
4b0f21cf50 dm: tegra: pwm: Convert to livetree
Update the tegra pwm driver to support a live device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
d8554d0853 dm: tegra: i2c: Convert to livetree
Update the tegra i2c driver to support a live device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
28a3e5a864 dm: tegra: spi: Convert to livetree
Update the tegra114 spi driver to support a live device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
5ae28c0a60 dm: tegra: usb: Convert to livetree
Update the Tegra EHCI driver to support a live device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
56f5c40ad9 dm: tegra: gpio: Convert to support livetree
Update the GPIO driver to support a live device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
e93812e81c tegra: dts: Move stdout-path to /chosen
This property should be in the /chosen node, not /aliases.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
079ff3b902 dm: video: tegra124: Convert to livetree
Update these drives to support a live device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
000f15fa15 dm: tegra: Convert clock_decode_periph_id() to support livetree
Adjust this to take a device as a parameter instead of a node.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
be7890927a dm: tegra: Convert USB setup to livetree
Adjust this code to support a live device tree. This should be implemented
as a PHY driver but that is left as an exercise for the maintainer.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
66de3eee79 tegra: tegra124: Add a PMC syscon driver
The PMC can be modelled as a syscon peripheral. Add a driver for this
so that it can be accessed by drivers when needed. Enable it for tegra124
boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
9b6b3c1b50 tegra: spl: Enable debug UART
Enable the debug UART in SPL to allow early serial output even if the
standard UART does not work (e.g. due to driver model problem).

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
0f6507a7e4 dm: core: Fix up ofnode_get_addr_index() for 64-bit values
At present this function only supports 32-bit (single-cell) values. Update
it to support two-cell values also.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
dcf988525f dm: core: Add ofnode_read_resource()
We sometimes need to read a resource from an arbitrary node. In any case
for consistency we should not put the live-tree switching code in
a dev_read_...() function. Update this to suit.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Masahiro Yamada
c61d0009fe console: simplify puts()
Current puts() and putc() have similar #ifdef / if() conditionals.
Make puts() iterate over putc() to avoid code duplication.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 12:02:47 -06:00
Masahiro Yamada
47b98ad0f6 sandbox: remove os_putc() and os_puts()
They are unused since commit d8c6fb8ced ("sandbox: Drop special
case console code for sandbox").

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-07-28 12:02:47 -06:00
Masahiro Yamada
fd73621cba dm: ofnode: change return type of dev_read_prop() to opaque pointer
DT property values can be strings as well as integers.  This is why
of_get_property/fdt_getprop returns an opaque pointer.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-07-28 12:02:47 -06:00
Philipp Tomsich
00b26f7cdb dm: Fix typo in include-guard for dm-structs.h
The include-guard for dm-structs.h was misspelled as __DT_STTUCTS.
Change it.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 12:02:47 -06:00
Bin Meng
db13a768a0 cmd: scsi: Fix null pointer dereference in 'scsi reset'
During 'scsi reset', scsi_bus_reset() is called with udevice pointed
to NULL, which causes exception. As a temporary fix, disable the call
for DM SCSI for now.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 12:02:47 -06:00
Bin Meng
9c1390d4b9 dm: ahci: Avoid scsi_scan_dev() in ahci_probe_scsi()
Running 'scsi scan' command causes scsi_scan_dev() to be called,
from which device_probe() is called and consequently AHCI driver
probe routine will be called as SCSI driver's parent, and finally
ahci_probe_scsi() calls scsi_scan_dev() again.

Remove the call to scsi_scan_dev() in ahci_probe_scsi().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 12:02:47 -06:00
Vagrant Cascadian
3b22599e1a arm: imx: Enable booting from SATA on wandboard.
Enable booting from SATA on the wandboard.

Sata support was already enabled, but distro_bootcmd is not configured
to boot from it.

Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-28 13:44:54 +02:00
Lothar Waßmann
cb5761f774 net: fec_mxc: adjust prototype of fec_get_miibus() for DM_ETH
commit 306dd7dabd ("net: fec_mxc: fix PHY initialization bug with CONFIG_DM_ETH")
has broken the build of the fec_mxc driver with CONFIG_DM_ETH
enabled because it changed the parameters passed to *fec_get_miibus()
without changing the functions prototype.

This patch fixes up the prototype of fec_get_miibus() for the DM_ETH case.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
2017-07-28 13:41:49 +02:00
Rob Clark
a095aadffa efi_loader: Add an EFI_CALL() macro
Rather than open-coding EFI_EXIT() + callback + EFI_ENTRY(), introduce
an EFI_CALL() macro.  This makes callbacks into UEFI world (of which
there will be more in the future) more concise and easier to locate in
the code.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-28 09:15:45 +02:00
Rob Clark
3f1aa97577 efi_loader: only evaluate EFI_EXIT()'s ret once
There are a couple spots doing things like:

   return EFI_EXIT(some_fxn(...));

which I handn't noticed before.  With addition of printing return value
in the EFI_EXIT() macro, now the fxn call was getting evaluated twice.
Which we didn't really want.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-28 09:14:01 +02:00
Rob Clark
6cfd5f133a efi_loader: add some missing breaks
Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-28 09:13:17 +02:00
Kever Yang
2672233525 rockchip: puma-rk3399: remove duplicate code (merge artifact)
A few lines (defines and declarations) had been duplicated when the
puma-rk3399 board was initially merged.  This removes the duplicates
and changes the style to use local constants instead of pasted
literals.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[fixed up commit-message & converted to use 'const u32':]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:04 +02:00
Andy Yan
86b1122a84 rockchip: add u-boot specific dts for rk3036 sdk
Add this dts to enable debug uart releated devices
before relocation.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:04 +02:00
Andy Yan
77c17f4354 rockchip: use puts instead of printf when back to bootrom
printf will increase the code size more than 1kb, but platform
like rk3036 has no enough space for it.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:04 +02:00
Andy Yan
d26bfa73ed rockchip: enable SPL_LIBGENERIC for rk3036 based boards
function board_init_f_init_reserve will call memset, which
is implemented in lib, and enabled by CONFIG_SPL_LIBGENERIC_SUPPORT
in spl stage.
To reduce the code size, also enable SPL_TINY_MEMSET.
As rk3036 will return to bootrom immediately after dram
initialization, there is no need to run DM, so disable
SPL_DM_SERIAL.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:04 +02:00
Andy Yan
8b154ed61c rockchip: disable SPL_ARCH_MEMCPY/MEMSET for rk3036
RK3036 has no enough sapce use ARCH_MEMCPY/MEMSET in spl stage

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:04 +02:00
Andy Yan
7f38025824 rockchip: set malloc pool size to 0 before relocation in spl state on rk3036 based board
RK3036 only has 4kb sram, the spl code will use
3.4 ~ 3.5 kb, the last 0.5kb are used for SP and
GD, so there is no space for malloc. Also, the spl
will directly return to bootrom after dram initialized,
they never need the space for malloc.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:04 +02:00
Andy Yan
1fc50d727f sandbox: use CONFIG_VAL(SYS_MALLOC_F_LEN) to distinguish malloc pool size before relocation
SPL and normal u-boot stage use different malloc pool size
configuration before relocation, so use CONFIG_VAL(SYS_MALLOC_F_LEN)
to fit different boot stage.

Signed-off-by: Andy Yan <andyshrk@gmail.com>

Changes in v3:
- use CONFIG_VAL(), which suggested by Simon

Changes in v2: None

 arch/sandbox/cpu/start.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:04 +02:00
Andy Yan
9eea50162c microblaze: spl: configure SYS_MALLOC_F_LEN independently for SPL and full U-Boot
Some platforms have very limited SRAM to run SPL code, so there may
not be the same amount space for a malloc pool before relocation in
the SPL stage as the normal U-Boot stage.

Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN,
so the size of pre-relocation malloc pool can be configured memory
space independently.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up commit-message:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:03 +02:00
Andy Yan
2b71d098ee powerpc: spl: configure SYS_MALLOC_F_LEN independently for SPL and full U-Boot
Some platforms have very limited SRAM to run SPL code, so there may
not be the same amount space for a malloc pool before relocation in
the SPL stage as the normal U-Boot stage.

Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN,
so the size of pre-relocation malloc pool can be configured memory
space independently.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up commit-message:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:03 +02:00
Andy Yan
f5868a5da1 mips: spl: configure SYS_MALLOC_F_LEN independently for SPL and full U-Boot
Some platforms have very limited SRAM to run SPL code, so there may
not be the same amount space for a malloc pool before relocation in
the SPL stage as the normal U-Boot stage.

Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN,
so the size of pre-relocation malloc pool can be configured memory
space independently.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up commit-message:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:03 +02:00
Andy Yan
f1896c45cb spl: make SPL and normal u-boot stage use independent SYS_MALLOC_F_LEN
Some platforms have very limited SRAM to run SPL code, so there may
not be the same amount space for a malloc pool before relocation in
the SPL stage as the normal U-Boot stage.

Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN,
so the size of pre-relocation malloc pool can be configured memory
space independently.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up commit-message:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:03 +02:00
Leo Wen
a1903c18db rockchip: firefly: Add "usb start" to auto-start USB device
Add "preboot=usb start" to ROCKCHIP_DEVICE_SETTINGS,you don't
need to input "usb start" in command line of u-boot console,it
can auto-start the USB device,after that usb keyboard can work.

Signed-off-by: Leo Wen <leo.wen@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:03 +02:00
Leo Wen
af83064769 rockchip: firefly: Set the environment variable 'usbkbd' to the stdin
Add the 'usbkbd' environment variable to the 'stdin', the contents of
the keyboard input can be auto-displayed on the serial terminal,so
you don't need to manually set the environment variable 'stdin'.

Signed-off-by: Leo Wen <leo.wen@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:03 +02:00
Leo Wen
73f255b7dc rockchip: firefly: Add some macros to enable the usb keyboard
Add four macros of CONFIG_USB_KEYBOARD,CONFIG_DM_KEYBOARD,etc in the
firefly-rk3288_defconfig,can support usb keyboard device when these four
macros are enabled.

Signed-off-by: Leo Wen <leo.wen@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:03 +02:00
Philipp Tomsich
c0508e427f rockchip: rk3399: enable SPL_SERIAL_SUPPORT and SPL_DRIVERS_MISC_SUPPORT via Kconfig
SPL_SERIAL_SUPPORT and SPL_DRIVERS_MISC_SUPPORT were previously
enabled through rk3399_common.h.  This change implies these options
through Kconfig.

These need to always be active for the RK3399, as follows:
 - SPL_SERIAL_SUPPORT is needed to pass the SPL build
 - SPL_DRIVERS_MISC_SUPPORT is needed to pass the SPL build

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:02 +02:00
Romain Perier
478e6f2e94 rockchip: rk3288: Add support for drive-strength in PINCTRL
Currently, drive-strenght to 12ma are described and supposed to be used
on RK3288. However, the pinctrl driver for this SoC only handles muxing
and pull up/pull down via PU/PD control registers. So complex IPs like
GMAC are working in normal ethernet 100mbps, but not at 1gbps typically.

This commit adds support for handling drive-strength of 12ma, when it's
defined in the DT.

Signed-off-by: Romain Perier <romain.perier@collabora.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:02 +02:00
Kever Yang
42ec247e69 rockchip: use UUID for root partitions
We use to use /dev/mmcbl0p7 as root partition, and pass it
to kernel by cmdline, but the mmc number in kernel in not
fixed, we need to change the bootargs to adapt it from time
to time.
We can use the UUID to fix it, the ID is from:
https://www.freedesktop.org/wiki/Specifications/DiscoverablePartitionsSpec/
ARM 32bit: 69dad710-2ce4-4e3c-b16c-21a1d49abed3
ARM 64bit: b921b045-1df0-41c3-af44-4c6f280d3fae

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:02 +02:00
Philipp Tomsich
4436c5db05 rockchip: dts: rk3399-puma: put EFI partition entries at 2MB
When creating a EFI/GUID partition map for the RK3399-Q7 through
U-Boot, the partition entries should be places at a 1MB offset from
the start of the device to give us space for the environment (at 16KB
on SD/MMC devices), the SPL stage (at 32KB on SD/MMC devices) and the
image payload (at 256KB on SD/MMC devices).

This change sets this up through the u-boot,efi-partition-entries-offset
/config property in the RK3399-Q7 DTSI.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:02 +02:00
Philipp Tomsich
56f580d3eb rockchip: dts: rk3399-puma: put environment (in MMC/SD configurations) before SPL
As our SPL stage can grow quite large (80KB+ are not unusual) on the
RK3399-Q7, the default setting for the environment location (in
include/configs/rockchip-common.h) can overlap our SPL.

This change finally makes use of the 'u-boot,mmc-env-offset' DTS
property to override the environment location and put it at 16KB into
the device, which is right before the SPL (located at 32KB).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:02 +02:00
Philipp Tomsich
01106571ad rockchip: clk: rk3399: remove unused fields from priv-structures
This removes the unused 'rate' field from both rk3399_pmuclk_priv and
rk3399_clk_priv. I didn't bother to check where this came from (i.e.
what the historical context of these was), but only verified that
these are indeed unused across all code-paths.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-27 14:59:02 +02:00
Philipp Tomsich
80c83e8190 rockchip: clk: rk3368: remove unused fields from rk3368_clk_priv
The rk3368_clk_priv has two unused fields: rate, has_bwadj. This
removes them as there's no need for either (i.e. has_bwadj is always
true for the RK3368, according to its TRM).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-27 14:59:02 +02:00
Philipp Tomsich
cdc6080a28 rockchip: clk: rk3368: use correct (i.e. 'rk3368_clk_priv') structure for auto-alloc
The clk driver for the RK3368 picked the wrong data structure's size
for its auto-alloc size: the size was calculated on the structure
representing the CRU hardware block instead of the priv structure.
As the CRU's register file is much larger than the driver's priv,
this did not cause any pain (except wasting memory).

Fix this by using the correct data structure's size.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-27 14:59:02 +02:00
Philipp Tomsich
700f3108d3 rockchip: spl: make boot0 hook TPL safe
When building for a TPL/SPL setup (e.g. on the RK3368), we need the
TPL stage to have the extra space for for the 'Rockchip SPL name'
(i.e. 'RK33' word).  Yet, the SPL will start execution at its first
word (i.e. the first word in the SPL binary needs to be a valid
instruction).  To make things a bit more involved, CONFIG_SPL_BUILD
is defined both for the SPL and the TPL stage.

To avoid having to explicitly test for the first stage (TPL, if and
only if TPL and SPL are built, SPL otherwise), this commit modifies
the sequence to repeat the 'b reset' (instead of reserving 4 bytes
of undefined space) at the start of the boot0 hook: if overwritten
(and execution starts at the second word), the first instruction is
still a 'b reset'... if not overwritten, we start on a 'b reset' as
well.

This solution wouldn't even require the check whether we are in the
SPL/TPL build (i.e. CONFIG_SPL_BUILD), but we leave this check in for
documentation purposes.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-27 14:59:02 +02:00
Kever Yang
06f4e36baf rockchip: pwm: add mask for config setting
Use mask to clear old setting before direct set the new config,
or else there it will mess up the config when it's not the same
with default value.

Fixes: 3851059 rockchip: Setup default PWM flags
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:01 +02:00
Kever Yang
3030c951f1 power: pwm_regulator: remove redundant code
The regulator_enable() should be called from upper layer like
regulators_enable_boot_on(), remove it from pwm regulator driver.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up typo in commit message:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:01 +02:00
Kever Yang
f339bca248 power: pwm_regulator: fix the pwm_set_config parameter order
The rkpwm reg order has fixed by below patch:
e3ef41d rockchip: pwm: fix the register layout for the PWM controller

We need to correct the parameter order for pwm_set_config() to make
the pwm regulator works correctly.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:01 +02:00
Kever Yang
7ba3182e2d rockchip: dts: correct vdd_log setting for firefly-rk3399
Add regulator-init-microvolt for driver to init the regulator,
and the min output value is not 800000mV for the PWM2 io domain has
changed to VCC3V0 instead of VCC1V8 in rockchip evb, we need to
correct it with the value measured when PWM2 output HIGH.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:01 +02:00
Kever Yang
56f2dd0aed rockchip: dts: firefly using ddr3 1600
According to my test, some of firefly-rk3399 hang after dram init
when using ddr3-1333 config, while using ddr3-1600 config works
for all the board I have test.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:01 +02:00
Wadim Egorov
c03635c3d1 rockchip: phycore: Add ID page of M24C32-D EEPROM
The Identification Page (32 byte) is an additional page which can be written
and (later) permanently locked in Read-only mode.

phyCORE-RK3288 SoMs are using this page to describe the module variant.
This page also contains a MAC.

Our boards can be equipped with a different amount of EEPROMs. To make
this more transparent let's add an alias for the eeprom which stores the
module variant.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:01 +02:00
Romain Perier
3641d346ea rockchip: rk3288: Revert MAC_TXCLK in pinctrl for GMAC
This reverts TXCLK toggling that was accidently dropped while reworking
commit 2454b719fb ("rockchip: rk3288: Add pinctrl support for the gmac
ethernet interface"). So the TX clock is enabled and we can use
GMAC_ROCKCHIP in 1Gbps when basic PINCTRL support is enabled
(!PINTRL_FULL).

Fixes: 2454b719fb ("rockchip: rk3288: Add pinctrl support for the...")
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:01 +02:00
Romain Perier
a98fc4325e rockchip: rk3288: Remove phy reset GPIO pull up
We should not handle this pin explicitly from pinctrl. GMAC driver takes
care of it by using a "reset-gpio" in the DT.

This commit removes pull up for GPIO4B0.

Fixes: 2454b719fb ("rockchip: rk3288: Add pinctrl support for the...")
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:01 +02:00
Philipp Tomsich
928979cb2b rockchip: efuse: dm: change to use dev_read_addr
This changes the rockchip-efuse driver to use dev_read_addr instead of
devfdt_get_addr.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:00 +02:00
Philipp Tomsich
cb91173a7f rockchip: timer: make register sizes explicit
We are about to reuse the rockchip timer (header file) for 64bit ARMv8
chips, so it seems a good time to make the register sizes explicit by
changing from 'unsigned int' to 'u32'.

Reorders the header-includes in rk_timer.c to ensure that 'u32' is
definded before it is used by 'asm/arch/timer.h'.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:00 +02:00
Meng Dongyang
0124062853 rockchip: dts: rk3229: add dwc2 node for fastboot
Add dwc2 node for fastboot to init dwc2 controller.

Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:00 +02:00
Rob Clark
a1b24823b6 efi_loader: fix bug in efi_get_memory_map
When booting shim -> fallback -> shim -> grub -> linux the memory map is
a bit larger than the size linux passes in on the first call.  But in
the EFI_BUFFER_TOO_SMALL case we were not passing back the updated size
to linux so it would loop forever.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-26 22:09:49 +02:00
Tom Rini
f19955a014 Merge git://git.denx.de/u-boot-uniphier 2017-07-26 11:29:25 -04:00
Tom Rini
0ddc9c1722 Merge git://git.denx.de/u-boot-mips 2017-07-26 11:29:20 -04:00
Bin Meng
dc5210a20d MAINTAINERS: Update maintainer for x86
This adds myself as one of the x86 maintainers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-26 11:29:16 -04:00
Tom Rini
25fa0b930f FIT: List kernel_noload in the list of types
In the source_file_format.txt file we talk about how to construct a
valid FIT image.  While it already says to look at the source for the
full list, add kernel_noload to the explicit list of types.  This is
arguably the most important type to use as most often we are including a
kernel that will run from wherever it is loaded into memory and execute.

This for example, allows you to create a single FIT image for Linux that
can be used on both OMAP and i.MX devices as the kernel will not need to
be moved in memory.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-26 11:29:15 -04:00
Patrice Chotard
7016651eac ram: stm32: add stm32h7 support
STM32F7 and H7 shared the same SDRAM control block.
On STM32H7 few control bits has been added.
The current driver need some minor adaptation as FMC block
enable/disable for H7.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-07-26 11:29:15 -04:00
Patrice Chotard
4eefb0070d ARM: DTS: stm32: remove useless mr-nbanks property
FMC driver is now able to discover the bank number by
parsing bank subnodes.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-26 11:29:15 -04:00
Patrice Chotard
f303aaf21b ram: stm32: add second SDRAM bank management
FMC is able to manage 2 SDRAM banks, but the current driver
implementation is only able to manage the first SDRAM bank.

Even if only bank2 is used, some bank1 registers must be
configured.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-26 11:29:15 -04:00
Patrice Chotard
f39b90dc8c ram: stm32: replace fdtdec_get by ofnode calls
Replace all fdtdec_get..() calls by ofnode_read...() or dev_read..().
This will allow drivers to support a live device tree.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-26 11:29:14 -04:00
Patrice Chotard
1421e0a375 ram: stm32: get base address from DT
Retrieve RAM base address from DT instead of using STM32_SDRAM_FMC

For STM32F7, FMC block base address is 0xA0000000, but SDRAM
registers are located at offset 0x140 inside FMC block.
Update the stm32_fmc_regs fields with all FMC registers
to map SDRAM registers at the right address.

These additionals registers will be used later.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-07-26 11:29:14 -04:00
Patrice Chotard
9242ece12b ram: stm32: migrate fmc defines in driver file
Migrate all FMC defines from arch/arm/include/asm/arch-stm32f7/fmc.h
to drivers/ram/stm32_sdram.c

This will avoid to add an additionnal arch-stm32xx/fmc.h file when
a new stm32 family soc will be introduced.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-26 11:29:07 -04:00
Patrice Chotard
81d0128d2b clk: stm32f7: remove clock_get()
All drivers which was using clock_get() are now using
clk_get_rate() from clock framework, now it's safe to
remove clock_get().

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26 11:28:08 -04:00
Patrice Chotard
541cd6e54e spi: stm32_qspi: add clk_get_rate() support
Replace proprietary clock_get() by clk_get_rate()
The stm32_qspi is now "generic" and can be used
by other STM32 SoCs.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26 11:28:08 -04:00
Patrice Chotard
27265cee76 serial: stm32x7: add clk_get_rate() support
Replace proprietary clock_get() by clk_get_rate()
The stm32x7 serial driver is now "generic" and can be used
by other STM32 SoCs.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26 11:28:08 -04:00
Patrice Chotard
122b2d4763 serial: stm32x7: migrate serial struct to driver
This allow to remove include/dm/platform_data/serial_stm32x7.h
which was included in the past by stm32x7 driver and by
stm32f746-disco.c board file.
Since patch 42bf5e7c27 "serial: stm32f7: add device tree support"
this file is no more needed in board file.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26 11:26:54 -04:00
Patrice Chotard
b9e86511d1 clk: stm32f7: cleanup clocks unused definitions
clean the code by removing unused enums, structs and
defines related to clocks

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26 11:26:54 -04:00
Patrice Chotard
288f17e648 clk: stm32f7: add clock .get_rate() callback
Add clock framework .get_rate callback.
This step will allow to convert all drivers which was using
proprietary clock_get() to use clock framework .get_rate().

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26 11:26:53 -04:00
Patrice Chotard
199a2178fe clk: stm32f7: get RCC base address from DT
Retrieve RCC base address from DT, this will prepare
the ground for future STM32 SoCs support.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26 11:26:53 -04:00
Patrice Chotard
704e954cee clk: stm32f7: add static for configure_clocks()
Also remove its declaration from stm32.h which
is no more needed.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26 11:26:53 -04:00
Patrice Chotard
fa87abb6b6 ARM: DTS: stm32: align DT clock declaration with kernel
Use the same clocks macro than the one used by kernel DT.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26 11:26:52 -04:00
Srinivas, Madan
94f536fc4f arm: mach-keystone: Fixes issue with return values in inline assembly
The inline assembly functions in mon.c assume that the caller will
check for the return value in r0 according to regular ARM calling
conventions.

However, this assumption breaks down if the compiler inlines the
functions. The caller is then under no obligation to use r0 for the
result.

To fix this disconnect, we must explicitly move the return value
from the smc/bl call to the variable that the function returns.

Signed-off-by: Madan Srinivas <madans@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-26 11:26:52 -04:00
Madan Srinivas
1a7c159a8d configs: ti: armv7: Fixes bug in fit_loadaddr for ramfs boot
The load address of ramdisk, rdaddr is 0x88080000 and fit_loadaddr
is defined as 0x88000000. This leaves only 512Kbytes for the
fit image. When the FIT images are larger than this, it will
overwite the ramdisk and cause the boot to fail.

For eg, The K2 HS fit images are a few MB and end up overwriting
the ramdsk. This patch moves the fit_loadaddr to 0x87000000,
leaving a 16MB window for the fit image. This memory can be
reclaimed once the kernel starts running.

Signed-off-by: Madan Srinivas <madans@ti.com>
2017-07-26 11:26:51 -04:00
Madan Srinivas
1d73ce6f68 arm: mach-keystone: Updates mon_install for K2G HS
On early K2 devices (eg. K2HK) the secure ROM code does not support
loading secure code to firewall protected memory, before decrypting,
authenticating and executing it.

To load the boot monitor on these devices, it is necessary to first
authenticate and run a copy loop from non-secure memory that copies
the boot monitor behind firewall protected memory, before decrypting
and executing it.

On K2G, the secure ROM does not allow secure code executing from
unprotected memory. Further, ROM first copies the signed and encrypted
image into firewall protected memory, then decrypts, authenticates
and executes it.

As a result of this, we cannot use the copy loop for K2G. The
mon_install has to be modified to pass the address the signed and
encrypted secure boot monitor image to the authentication API.

For backward compatibility with other K2 devices and K2G GP,
the mon_install API still supports a single argument. In this case
the second argument is set to 0 by u-boot and is ignored by ROM

Signed-off-by: Thanh Tran <thanh-tran@ti.com>
Signed-off-by: Madan Srinivas <madans@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-26 11:26:51 -04:00
Andrew F. Davis
3f5651a724 configs: k2x_evm: Reorder default boot command
We first split the CONFIG_BOOTCOMMAND into its components to improve
readability. We then make the following order changes:

 - Run findfdt first so the fdt name can be used in envboot like OMAP
 - Install the boot monitor before running the PMMC so we can make any
     needed secure changes before PMMC, do this on both HS and non-HS
 - Move set_name_pmmc to just before get_pmmc_${boot}

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-26 11:26:50 -04:00
Madan Srinivas
08d06310f4 configs: k2x_evm: Adds environment variables for secure devices
Updates the default u-boot environment variables to support secure
boot. On secure devices, a secure boot monitor (sec-bm) needs to
be installed by u-boot.

Signed-off-by: Madan Srinivas <madans@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-26 11:26:50 -04:00
Andrew F. Davis
881261c82e configs: k2x_evm: Adds FIT loading environment variables
Updates the default u-boot environment variables to support FIT image
loading.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-26 11:26:50 -04:00
Lokesh Vutla
f70a427268 board: ti: x15: Add support for beagle_X15 revC
BeagleBoard X15 revC board is similar to X15 revB1 except
with a SR2.0 where revB1 uses a SR1.1. Add board detection
support for revC.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-26 11:26:49 -04:00
Lokesh Vutla
7087922477 board: ti: am57xx: Fix detection of board version
board_is*("rev", board_ti_get_rev()) uses strncmp() for
revison detection and assumes it is success if return value
is <= 0. This will fail in case of multiple versions, as
revb will be true for board_is_*revb() and board_is_*reva().
Fix it by looking for exact match of the string.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-26 11:26:49 -04:00
Beniamino Galvani
9cb1c49afb odroid-c2: enable GPIO
GPIOs are now supported on Meson GXBB, enable driver and command in
the config.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-26 11:26:49 -04:00
Beniamino Galvani
2009a8d03f pinctrl: meson: add GPIO support
This commit adds GPIO support to the Amlogic Meson pin controller
driver, based on code from Linux kernel.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
2017-07-26 11:26:48 -04:00
Beniamino Galvani
4a63a75c83 arm: dts: meson: import dts files from Linux 4.12
Import Amlogic Meson DTS files from Linux kernel version 4.12

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-26 11:26:48 -04:00
Masahiro Yamada
a3f54bc74f ARM: uniphier: enable CONFIG_CMD_FS_GENERIC
Enable file system commands such as load, ls.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-07-26 22:27:15 +09:00
Masahiro Yamada
b8faf5f12b ARM: uniphier: remove part number info from the boot log
As is often the case with SoC development, slightly different
products (i.e. different part number) are developed based on the
same silicon-die.  Such fine grained information is unmaintainable.

Also, "SoC:" is a better fit that "CPU:".

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-07-26 22:27:15 +09:00
Masahiro Yamada
673ac334fc doc: uniphier: rework README.uniphier
Rework the readme to reflect the latest boot mechanism on ARMv8 SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-07-26 22:27:15 +09:00
Masahiro Yamada
ee8d037ce7 ARM: uniphier: remove SPL support for ARMv8 SoCs
It has been a while since ARM Trusted Firmware supported UniPhier SoC
family.  U-Boot SPL was intended as a temporary loader that runs in
secure world.  It is a maintenance headache to support two different
boot mechanisms.  Secure firmware is realm of ARM Trusted Firmware
and now U-Boot only serves as a non-secure boot loader for UniPhier
ARMv8 SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-07-26 22:27:15 +09:00
Alexander Graf
f4f9993f7e efi_loader: Fix configuration table override
Before commit 7cbc12415d ("efi_loader: initalize EFI object list
only once") we recreated the world on every bootefi invocation.

That included the object tree as well as the configuration tables.

Now however we don't recreate them, which means we must not explicitly
override the configuration tables, as otherwise we may lose our SMBIOS
table from the configuration table list on second bootefi invocation.

This patch makes bootefi call our normal configuration table modification
APIs to add/remove the FDT instead of recreating all tables from scratch.
That way the SMBIOS table gets preserved across multiple invocations.

Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-26 15:24:47 +02:00
Alexander Graf
d98cdf6a92 efi_loader: Improve install_configuration_table
The INSTALL_CONFIGURATION_TABLE callback also provides the ability to
remove table entries. This patch adds that functionality.

Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-26 15:23:54 +02:00
Tien Fong Chee
9af91b7c40 arm: socfpga: Enable all FPGA config support for Arria 10
Enable all FPGA config support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-07-26 10:31:44 +02:00
Tien Fong Chee
2baa997240 arm: socfpga: Add FPGA driver support for Arria 10
Add FPGA driver support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-07-26 10:31:44 +02:00
Tien Fong Chee
812dfdd4f7 configs: Add FPGA driver config for Arria 10
Add FPGA driver config for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-07-26 10:31:44 +02:00
Tien Fong Chee
386c65e556 drivers: Enable FPGA driver build on SPL
Enable FPGA driver build for Arria 10 SPL because FPGA driver is
needed by Arria 10 SPL to configure and getting DDR up before
loading U-boot into DDR and booting from there.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-07-26 10:31:44 +02:00
Tien Fong Chee
fa23ba1aa5 kconfig: Convert FPGA_SOCFPGA configuration to Kconfig
This converts the following to Kconfig:
   CONFIG_FPGA_SOCFPGA

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-07-26 10:31:44 +02:00
Tien Fong Chee
c2caaee73e kconfig: Convert FPGA and FPGA_ALTERA configuration to Kconfig
This converts the following to Kconfig:
   CONFIG_FPGA
   CONFIG_FPGA_ALTERA

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-07-26 10:31:44 +02:00
Tien Fong Chee
6867e19a43 arm: socfpga: Restructure FPGA driver in the preparation to support A10
Move FPGA driver which is Gen5 specific code into Gen5 driver file
and keeping common FPGA driver intact. All the changes are still keeping
in driver/fpga/ and no functional change. Subsequent patch would move
FPGA manager driver from arch/arm into driver/fpga/.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-07-26 10:31:44 +02:00
Tien Fong Chee
6a34af5b41 arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset
Remove parameter from socfpga_bridges_reset(), and keeping this function
for single purpose which is just triggering reset on bridges.
socfpga_reset_deassert_bridges_handoff() can be called for releasing reset
on any bridges based on the bridge setting defined in fdt.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-07-26 10:31:43 +02:00
Rob Clark
3304990ba4 efi_loader: remove more double EFI_EXIT() in efi_disk.c
Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-26 08:56:15 +02:00
Rob Clark
b5104821c1 efi_loader: remove double EFI_EXIT() with efi_unsupported
Probably this went unnoticed before, but it causes problems with
addition of 804b1d73 ("efi_loader: log EFI return values too")

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-26 08:56:03 +02:00
Simon Glass
609bf92411 Convert CONFIG_ENV_IS_IN_ONENAND to Kconfig
This converts the following to Kconfig:
   CONFIG_ENV_IS_IN_ONENAND

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-25 21:34:39 -04:00
Simon Glass
b31e065f89 Convert CONFIG_ENV_IS_IN_FAT to Kconfig
This converts the following to Kconfig:
   CONFIG_ENV_IS_IN_FAT

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-25 21:34:15 -04:00
Simon Glass
337cd3f211 Convert CONFIG_ENV_IS_IN_REMOTE to Kconfig
This converts the following to Kconfig:
   CONFIG_ENV_IS_IN_REMOTE

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-25 21:33:22 -04:00
Simon Glass
91c868fe7c Convert CONFIG_ENV_IS_IN_SPI_FLASH to Kconfig
This converts the following to Kconfig:
   CONFIG_ENV_IS_IN_SPI_FLASH

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-25 21:31:03 -04:00
Simon Glass
ef6253d7b3 Convert CONFIG_ENV_IS_IN_DATAFLASH to Kconfig
This converts the following to Kconfig:
   CONFIG_ENV_IS_IN_DATAFLASH

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-25 21:24:09 -04:00
Simon Glass
f0bc2b542b Convert CONFIG_ENV_IS_IN_EEPROM to Kconfig
This converts the following to Kconfig:
   CONFIG_ENV_IS_IN_EEPROM

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-25 21:22:56 -04:00
Simon Glass
88b233a347 Convert CONFIG_ENV_IS_IN_NVRAM to Kconfig
This converts the following to Kconfig:
   CONFIG_ENV_IS_IN_NVRAM

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-25 21:21:24 -04:00
Simon Glass
85fc970d74 Convert CONFIG_ENV_IS_IN_FLASH to Kconfig
This converts the following to Kconfig:
   CONFIG_ENV_IS_IN_FLASH

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-25 21:20:02 -04:00
Simon Glass
e73496d08e env: Move help from README to Kconfig
The CONFIG_ENV_IS_IN_... options which have already been converted to
Kconfig only have a small amount of help. Move the rest of it over from
the README.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-25 21:08:07 -04:00
Simon Glass
2be296538e Convert CONFIG_ENV_IS_IN_MMC/NAND/UBI and NOWHERE to Kconfig
This converts the following to Kconfig:
   CONFIG_ENV_IS_IN_MMC
   CONFIG_ENV_IS_IN_NAND
   CONFIG_ENV_IS_IN_UBI
   CONFIG_ENV_IS_NOWHERE

In fact this already exists for sunxi as a 'choice' config. However not
all the choices are available in Kconfig yet so we cannot use that. It
would lead to more than one option being set.

In addition, one purpose of this series is to allow the environment to be
stored in more than one place. So the existing choice is converted to a
normal config allowing each option to be set independently.

There are not many opportunities for Kconfig updates to reduce the size of
this patch. This was tested with

   ./tools/moveconfig.py -i CONFIG_ENV_IS_IN_MMC

And then manual updates.  This is because for CHAIN_OF_TRUST boards they
can only have ENV_IS_NOWHERE set, so we enforce that via Kconfig logic
now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-25 21:08:01 -04:00
Paul Burton
e94136bd87 mips-relocs: Fix warning from gcc 6.3
It seems that gcc 6.3 at least is smart enough to warn about the _val
variable being unassigned in the default case in the set_hdr_field()
macro, but not smart enough to figure out that the default case is never
taken. This results in warnings such as the following:

  pfx##hdr32[idx].field = _val;   \
                          ^
 ../tools/mips-relocs.c:51:11: note: _val was declared here
   uint64_t _val;      \
            ^
 ../tools/mips-relocs.c:88:2: note: in expansion of macro set_hdr_field
   set_hdr_field(p, idx, field, val)
   ^~~~~~~~~~~~~
 ../tools/mips-relocs.c:408:3: note: in expansion of macro set_phdr_field
    set_phdr_field(i, p_filesz, load_sz);
    ^~~~~~~~~~~~~~
 ../tools/mips-relocs.c: In function main:
 ../tools/mips-relocs.c:77:25: warning: _val may be used uninitialized
    in this function [-Wmaybe-uninitialized]

Avoid this by assigning _val = 0 in the default case, and asserting that
we didn't actually hit it for good measure.

For reference gcc 7.1.1 seems to be smart enough to not hit the above
warning without this patch.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fixes: 011dd93ca97a ("MIPS: Stop building position independent code")
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: u-boot@lists.denx.de
2017-07-25 20:44:38 +02:00
Zubair Lutfullah Kakakhel
48bfc31b64 MIPS: bootm: Fix broken boot_env_legacy codepath
This patch fixes 2 bugs introduced by the following commit

2bb5b63 MIPS: bootm: rework and fix broken bootm code

The CONFIG_IS_ENABLED macro prepends 'CONFIG_' Hence, remove CONFIG_
from CONFIG_MIPS_BOOT_ENV_LEGACY usage.

Also, 2bb5b63 reworks bootm so that linux_env_legacy runs before
linux_cmdline_legacy. However, linux_env_legacy depends on
linux_cmdline_legacy running first as linux_cmdline_init initialilzes
linux_argp which linux_env_legacy later depends on during its
initialization.

Reorder the code so that linux_cmdline_legacy runs before
linux_env_legacy.

Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
2017-07-25 20:44:00 +02:00
Paul Burton
703ec9ddf9 MIPS: Stop building position independent code
U-Boot has up until now built with -fpic for the MIPS architecture,
producing position independent code which uses indirection through a
global offset table, making relocation fairly straightforward as it
simply involves patching up GOT entries.

Using -fpic does however have some downsides. The biggest of these is
that generated code is bloated in various ways. For example, function
calls are indirected through the GOT & the t9 register:

  8f998064   lw     t9,-32668(gp)
  0320f809   jalr   t9

Without -fpic the call is simply:

  0f803f01   jal    be00fc04 <puts>

This is more compact & faster (due to the lack of the load & the
dependency the jump has on its result). It is also easier to read &
debug because the disassembly shows what function is being called,
rather than just an offset from gp which would then have to be looked up
in the ELF to discover the target function.

Another disadvantage of -fpic is that each function begins with a
sequence to calculate the value of the gp register, for example:

  3c1c0004   lui    gp,0x4
  279c3384   addiu  gp,gp,13188
  0399e021   addu   gp,gp,t9

Without using -fpic this sequence no longer appears at the start of each
function, reducing code size considerably.

This patch switches U-Boot from building with -fpic to building with
-fno-pic, in order to gain the benefits described above. The cost of
this is an extra step during the build process to extract relocation
data from the ELF & write it into a new .rel section in a compact
format, plus the added complexity of dealing with multiple types of
relocation rather than the single type that applied to the GOT. The
benefit is smaller, cleaner, more debuggable code. The relocate_code()
function is reimplemented in C to handle the new relocation scheme,
which also makes it easier to read & debug.

Taking maltael_defconfig as an example the size of u-boot.bin built
using the Codescape MIPS 2016.05-06 toolchain (gcc 4.9.2, binutils
2.24.90) shrinks from 254KiB to 224KiB.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tested-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2017-07-25 20:44:00 +02:00
Paul Burton
09bebb8397 Makefile: Allow arch post-link hook
This commit allows an architecture to provide a Makefile.postlink whose
u-boot target gets invoked after the u-boot ELF is linked. This will be
of use for MIPS in a following commit.

This mirrors Linux commit fbe6e37dab97 ("kbuild: add arch specific
post-link Makefile").

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: u-boot@lists.denx.de
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tested-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2017-07-25 20:44:00 +02:00
Tom Rini
5785e51940 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-25 13:52:46 -04:00
Rob Clark
a17e62cc53 efi_loader: expose protocols via GUID
shim.efi (or rather gnu-efi's LibLocateProtocol() which shim.efi uses)
resolves protocols via efi_locate_handle() so the console protocols
need to be added to the efi object list.

Signed-off-by: Rob Clark <robdclark@gmail.com>
[agraf: whitespace fixes]
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-25 10:58:07 +02:00
Rob Clark
641833db4a efi_loader: add helper macro to construct protocol objects
There are a bunch of protocols which should be exposed by GUID but are
not.  Add a helper macro to create an efi_object, to avoid much typing.

Note that using the pointer for efiobj->handle is semi-arbitrary.  We
just need a unique value to match the efiobj supporting the protocol
with the handle that LocateHandle() returns..

See LibLocateProtocol() in gnu-efi.  It does LocateHandle() to find all
the handles, and then loops over them calling HandleProtocol() with the
GUID of the protocol it is trying to find.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-25 10:55:51 +02:00
Rob Clark
804b1d737a efi_loader: log EFI return values too
Turns out this is rather useful to tracking down where things fail.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-25 10:29:46 +02:00
xypron.glpk@gmx.de
c0ebfc8664 efi_loader: implement ProtocolsPerHandle
Boot service ProtocolsPerHandle is implemented in
efi_protocols_per_handle.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-25 10:03:50 +02:00
Tom Rini
d56b4b1974 configs: Migrate RBTREE, LZO, CMD_MTDPARTS, CMD_UBI and CMD_UBIFS
The above CONFIG options are in Kconfig, and now have correct depends and
inter-dependencies.  Migrate these to configs/ from include/configs/.  In the
case of CMD_UBIFS also change it to be a default y if CMD_UBI.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-24 20:35:55 -04:00
xypron.glpk@gmx.de
b521d29eb1 efi_loader: parameter types for CreateEvent, SetTimer
The first argument 'type' of CreateEvent is an 32bit unsigned
integer bitmap and not an enum.

The second argument 'type' of SetTimer take values of an
enum which is called EFI_TIMER_DELAY in the UEFI standard.
To avoid confusion rename efi_event_type to efi_timer_delay.

Reported-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-24 14:54:29 +02:00
Heinrich Schuchardt
7cbc12415d efi_loader: initalize EFI object list only once
If several EFI applications are executed in sequence we want
to keep the content of the EFI object list.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-24 14:53:32 +02:00
xypron.glpk@gmx.de
ff925938c8 efi_console: use EFIAPI for callback functions
The call to efi_create_event requires notification functions
flagged as EFIAPI.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-24 14:48:09 +02:00
Rob Clark
661c8327a6 efi_loader: workaround for grub lsefi bug
Patch has also been sent to fix grub to not ignore the error returned
and treat protocol_buffer_count as valid.  But that that might take a
while to trickle into distro's, so this workaround might be useful.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-24 14:47:36 +02:00
xypron.glpk@gmx.de
09c5ab909c efi_loader: implement ConvertDeviceNodeToText
Move the logic for converting a node to text from
efi_convert_device_path_to_text to convert_device_node_to_text.

Provide a wrapper function convert_device_node_to_text_ext.

As we use only shallow device paths so we can call
directly call efi_device_node_to_text from efi_device_path_to_text.

Add output for MAC addresses.

Add output for not yet supported types/subtypes.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-24 14:47:04 +02:00
xypron.glpk@gmx.de
c6e3c3e68a efi_memory: return MapKey
efi_get_memory_map should set a defined value for map_key.

We later can introduce the test against this value in
efi_exit_boot_services as required by the UEFI standard.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-24 14:46:13 +02:00
xypron.glpk@gmx.de
0ecba5db85 efi_memory: do parameter checks first
The parameter checks should be done first.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-24 14:46:01 +02:00
Rob Clark
ca9193d2b1 efi_loader: gop: fixes for CONFIG_DM_VIDEO without CONFIG_LCD
Make EFI GOP support work with DM_VIDEO but without legacy LCD.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-24 14:43:40 +02:00
Rob Clark
3e094c592b efi_loader: move guidcmp to header
Want to re-use this for file protocol, which I'm working on.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-24 14:38:21 +02:00
Rob Clark
3e433e9608 efi_loader: EFI file paths should be DOS style
shim.efi, for example, actually tries to parse this, but is expecting
backslashes.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-24 14:33:32 +02:00
Karl Beldan
24fc9531a1 cmd: Kconfig: Fix CMD_UBIFS dependencies
Remove the ARCH_SUNXI and RBTREE dependencies.
CMD_UBIFS already gets RBTREE from CMD_UBI (from MTD_UBI), and should
the first become independant from the latter, there would likely be a
dependency on MTD_UBI anyway.

Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Jagan Teki <jagan@openedev.com>
Signed-off-by: Karl Beldan <karl.beldan-ext@sagemcom.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-24 07:33:34 -04:00
Karl Beldan
22cf953a40 cmd: Kconfig: Make CMD_UBI select CMD_MTDPARTS
Many configs still define CMD_MTDPARTS in their non-Kconfig but
CMD_MTDPARTS has now moved to Kconfig.

Signed-off-by: Karl Beldan <karl.beldan-ext@sagemcom.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-24 07:33:34 -04:00
Karl Beldan
f8dc5a0f9b ubi: Kconfig: Make MTD_UBI select MTD_PARTITIONS
This missing dependency has probably remained under the radar because
MTD_PARTITIONS is still whitelisted.

Signed-off-by: Karl Beldan <karl.beldan-ext@sagemcom.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-24 07:33:34 -04:00
Karl Beldan
b2237a4f5d cmd: Kconfig: Fix a dependency of CMD_MTDPARTS
Remove the ARCH_SUNXI dependency.

Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Jagan Teki <jagan@openedev.com>
Signed-off-by: Karl Beldan <karl.beldan-ext@sagemcom.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-24 07:33:33 -04:00
Karl Beldan
fc94f209a8 ubi: Kconfig: Fix MTD_UBI selection dependency
Remove the ARCH_SUNXI dependency on selection of RBTREE.

Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Jagan Teki <jagan@openedev.com>
Signed-off-by: Karl Beldan <karl.beldan-ext@sagemcom.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-24 07:33:33 -04:00
Tom Rini
92c05d9d6c xilinx-ppc.h: Drop
With PowerPC 4xx support removed, we have removed xilinx-ppc support as
well, remove this file now.

Fixes 98f705c9ce ("powerpc: remove 4xx support")
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-23 17:04:50 -04:00
Stefan Roese
6822cf3ec7 serial: ns16550: Add RX interrupt buffer support
Pasting longer lines into the U-Boot console prompt sometimes leads to
characters missing. One problem here is the small 16-byte FIFO of the
legacy NS16550 UART, e.g. on x86 platforms.

This patch now introduces a Kconfig option to enable RX interrupt
buffer support for NS16550 style UARTs. With this option enabled, I was
able paste really long lines into the U-Boot console, without any
characters missing.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
[trini: Guard ns16550_serial_remove with
CONFIG_IS_ENABLED(SERIAL_PRESENT) to match struct assignment]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-23 17:04:46 -04:00
Adam Ford
c3bec5478f arm: omap3: Detect boot mode very early
Fixes 4bd754d8ab ("arm: omap: Detect boot mode very early") where
the intent was to store the boot params information in a known
location and pass it to SPL very early. Unfortunately it didn't
account for OMAP3 boards.

This patch adds adds this functionality back into OMAP3 boards.

Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
2017-07-23 09:24:47 -04:00
Christophe Leroy
72281c5c46 powerpc: Remove 8260 remainders
commit 2eb48ff7a2 ("powerpc, 8260: remove support for mpc8260")
removed support for 8260 CPU.

This patch remove some remainders.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2017-07-23 09:24:47 -04:00
Christophe Leroy
08dd988be5 powerpc, 8xx: fix missing function declarations.
Add missing .h and add missing declarations in .h
Declare local functions as static.  Make interrupt_init_cpu function
signatures consistent with how decrementer_count is declared.

Based on warnings reported by 'make C=2'

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
[trini: drop cpu_init_f as 8xx/83xx are different from the rest, rework
interrupt_init_cpu/decrementer_count]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-23 09:23:29 -04:00
Christophe Leroy
ba2c5a5c9d powerpc: move get_pvr() and get_svr() into C
Avoid unnecessary assembly functions when they can easily be written
in C.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2017-07-22 22:22:51 -04:00
Christophe Leroy
506cb8be7e powerpc, 8xx: move cache helper into C
Avoid unnecessary assembly functions when they can easily be written
in C.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2017-07-22 22:22:51 -04:00
Christophe Leroy
7fd697fd54 powerpc, 8xx: move get_immr() into C
Avoid unnecessary assembly functions when they can easily be written
in C.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2017-07-22 22:22:50 -04:00
Christophe Leroy
1e7cefef58 powerpc, 8xx: Move cache function into C files
Avoid unnecessary assembly functions when they can easily be written
in C.

Also remove dc_read() as it is nowhere referenced

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2017-07-22 22:22:50 -04:00
Christophe Leroy
36d3260756 powerpc, 8xx: Simplifying check_CPU()
All complex case have been removed and we now only support
MPC866 and MPC885 families.

So check_CPU() can be made a lot simpler.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2017-07-22 22:22:50 -04:00
Christophe Leroy
f3603b4382 powerpc: Remove unneccessary #ifdefs in reginfo
reginfo command is calling mpc8xx_reginfo(), mpc85xx_reginfo()
or mpc86xx_reginfo() based on CONFIG_ symbol.
As those 3 functions can't me defined at the same time, let's
rename them print_reginfo() to avoid the #ifdefs
The name is kept generic as it is not at all dependent on
powerpc arch and any other arch could want to also print
such information.

In addition, as the Makefile compiles cmd/reginfo.c only when
CONFIG_CMD_REGINFO is set, there is no need to enclose the U_BOOT_CMD
definition inside a #ifdef CONFIG_CMD_REGINFO

Lets all remove the #ifdefs around the U_BOOT_CMD as this
file is only compiled when CONFIG_CMD_REGINFO is defined

Finally, this is a PowerPC-only command, disable it on a number of
non-PowerPC platforms.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-22 22:22:49 -04:00
Christophe Leroy
f1cd73674f powerpc: move set_msr() and get_msr() into .h
set_msr() and get_msr() are defined and used twice.
This patch moves them into ppc.h

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2017-07-22 22:22:49 -04:00
Christophe Leroy
f0eda3cb89 power, timer: reset TBL before TBU
In order to avoid TBU increment due to TBL reaching its max
and wrapping, reset TBL before resetting TBU

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2017-07-22 22:22:48 -04:00
Christophe Leroy
93e85d02b2 powerpc, timer: Does 8xx specific actions in 8xx cpu_init
The actions inside #ifdef CONFIG_8xx in arch/powerpc/lib/time.c
can be performed before, in a 8xx dedicated function.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2017-07-22 22:22:48 -04:00
Christophe Leroy
0819450fdd powerpc: get rid of addr_probe()
This function has never been used, at least since the beginning
of the git repository

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2017-07-22 22:22:48 -04:00
Christophe Leroy
7a0a550c7f powerpc, 8xx: Simplify brgclk calculation and remove get_brgclk()
divider is calculated based on SCCR_DFBRG, with:
SCCR_DFBRG 00 => divider 1  = 1 << 0
SCCR_DFBRG 01 => divider 4  = 1 << 2
SCCR_DFBRG 10 => divider 16 = 1 << 4
SCCR_DFBRG 11 => divider 64 = 1 << 6

This can be easily converted to a single shift operation:
divider = 1 << (SCCR_DFBRG * 2)

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2017-07-22 22:22:47 -04:00
Holger Brunck
b2f2c7be34 km/ivm: allow to set locally administred MAC addresses
It is possible to flag MAC addresses as locally administred. In this
case they don't need to be unique. This is only allowed for interfaces
which have no connection to the outside. For the TEGR1 board we use
this feature.

Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
2017-07-22 22:22:47 -04:00
Holger Brunck
b63d4f34d0 km/ivm: always set ethaddr after reading IVM
If we rebrand the IVM and ethaddr was set previously we need to change
ethaddr. Otherwise we end up with a wrong MAC adress for the ethernet
interface.

Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
2017-07-22 22:22:46 -04:00
Simon Glass
6821a7457c RFC: moveconfig: Use toolchains from buildman
It is annoying to have to set up and maintain two sets of toolchains, one
for buildman and one for moveconfig.

Adjust moveconfig to make use to buildman's toolchains. This should make
things easier.

One missing feature is the ability to specify the toolchain on the command
line with a special environment variable, e.g. CROSS_COMPILE_ARM. I'm not
sure if that is useful, but if it is it could be implemented in buildman.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-22 22:22:46 -04:00
Simon Glass
dee36c74ea moveconfig: Tidy up imply flag parsing
Add an option to specify 'all' to enable all flags. Also print an error
if an unrecognised flag is used. At present it just prints usage
information which is not very helpful.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-22 22:22:46 -04:00
Andrew F. Davis
7fe463f54f board: ti: am43xx: Add FDT fixup for HS devices
Disable RNG and add TEE to FDT used on HS devices.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2017-07-22 22:22:45 -04:00
Andrew F. Davis
3630094cf9 board: ti: am43xx: Add TEE loading and firewall setup
Add support for loading a TEE and setting up firewalled regions to
AM43xx HS boards.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2017-07-22 22:22:45 -04:00
Andrew F. Davis
ddf013458d arm: mach-omap2: am33xx: Add FDT fixup suport for AM33xx/AM43xx boards
Similar to what is done with OMAP5 class boards we need to
perform fixups common to this SoC class, add support for this here
and add HS fixups.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2017-07-22 22:22:44 -04:00
Andrew F. Davis
137ae0c4b1 arm: mach-omap2: fdt-common: Add OP-TEE node when firmware node is defined
If a firmware node is already present in the FDT we will fail to create
one and so fail to add our OP-TEE node, make this fixup first check for
a firmware node and then only try to add one if it is not found.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2017-07-22 22:22:44 -04:00
Andrew F. Davis
03750231a8 arm: mach-omap2: Factor out common FDT fixup suport
Some of the fixups currently done for OMAP5 class boards are common to
other OMAP family devices, move these to fdt-common.c.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2017-07-22 22:22:43 -04:00
Andrew F. Davis
3348e0c0a6 arm: mach-omap2: Move omap5/sec-fxns.c into sec-common.c
TEE loading and firewall setup are common to all omap2 devices, move
these function out of omap5 and into mach-omap2. This allows us
to use these functions from other omap class devices.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2017-07-22 22:22:42 -04:00
Philipp Tomsich
0d982c5853 Makefile: add dependencies to regenerate u-boot.cfg when lost
When running a 'make clean' or carelessly removing u-boot.cfg, all
future make invocations (until autoconf is regenerated) will print
an error for a missing u-boot.cfg due to missing rules and dependencies.

This commit adds (i) an explicit rule dependency from all (which will
invokes the configuration checker) to cfg, and (b) adds a rule to
invoke scripts/Makefile.autoconf to regenerate u-boot.cfg.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-22 15:36:19 -04:00
Emmanuel Vadot
47a52cd1e4 dtc: mkimage: Add the possibility to specify DTC
FreeBSD recently switch to it's BSDL dtc. While it support most of the
features of the GPL one it still lacks the incbin directive.
Add the possibility to specify which dtc we want to use for compiling dts
and generating fit image.

Signed-off-by: Emmanuel Vadot <manu@bidouilliste.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-07-22 15:36:19 -04:00
xypron.glpk@gmx.de
e42f096f78 meson-gx: reserved memory regions
The Odroid C2 has two GiB of memory with two reserved regions.
reg = <0x0 0x0 0x0 0x1000000>;
reg = <0x0 0x10000000 0x0 0x200000>;

Patch
bfcef28ae4 (arm: add initial support for Amlogic Meson and
ODROID-C2) provided function dram_init_banksize to reserve the
first 16 MiB of RAM for firmware in function dram_init_banksize
in arch/arm/mach-meson/board.c and defined
CONFIG_NR_DRAM_BANKS = 1.

With this patch dram_init_banksize is changed to additionally
reserve the 2MiB region for the ARM Trusted Firmware (BL31).
CONFIG_NR_DRAM_BANKS is set to 2.

Cc: Andreas Färber <afaerber@suse.de>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-07-22 15:36:18 -04:00
Fiach Antaw
9d364af23e env: Switch env_nand, env_mmc and env_ubi to env_import_redund
The env_nand, env_mmc and env_ubi implementations all implement
redundancy using an identical serial-number scheme. This commit
migrates them to use the implementation in env_common, which is
functionally identical.

Signed-off-by: Fiach Antaw <fiach.antaw@uqconnect.edu.au>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-22 15:36:17 -04:00
Fiach Antaw
76768f5f08 env: Add generic redundant environment implementation
All current environments that implement redundancy use almost
identical implementations. This patch implements the env_nand
implementation as a function in env_common, and updates the
env_export function to export an env_nand-style 'flags' field by
default.

Signed-off-by: Fiach Antaw <fiach.antaw@uqconnect.edu.au>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-22 15:36:17 -04:00
Tom Rini
845e10d165 tests: test_dfu.py: Add example udev rule for host_usb_dev_node
If one does not already have a rule to create a custom device node when
a given device enumerates it can be useful to have udev create a
bus path based node to the entry in /dev/bus/usb that was just
enumerated.  Given that DFU itself does not require a /dev entry it is a
good idea to provide a rule that will generate one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-22 15:36:16 -04:00
Michael Heimpold
7e99e14d4b tools/fw_env: use fsync to ensure that data is physically stored
Closing a file descriptor does not guarantee that the data has been
successfully saved to disk, as the kernel might defer the write.

Signed-off-by: Michael Heimpold <mhei@heimpold.de>
2017-07-22 15:36:16 -04:00
xypron.glpk@gmx.de
8787b02e32 efi_loader: correctly implement 100ns conversion
In efi_set_timer we receive the trigger time in intervals of 100 ns.
We should convert it to intervals of 1000 ns by 64bit division.

The patch supplies function efi_div10 that uses multiplication to
implement the missing 64 bit division.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:36:14 +02:00
xypron.glpk@gmx.de
91be9a77b7 efi_console: set up events
Set up a timer event and the WaitForKey event.
In the notify function of the timer event check for console input
and signal the WaitForKey event accordingly.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:36:04 +02:00
xypron.glpk@gmx.de
bfc724625f efi_loader: refactor efi_set_timer
efi_set_timer is refactored to make the function callable internally.
Wrapper function efi_set_timer_ext is provided for EFI applications.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:31:40 +02:00
xypron.glpk@gmx.de
49deb455e6 efi_loader: refactor efi_create_event
efi_create_event is refactored to make it possible to call it
internally. For EFI applications wrapper function
efi_create_event_ext is created.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:31:35 +02:00
xypron.glpk@gmx.de
503f269554 efi_loader: correct size for tpl level
The UEFI standard defines the type for the tpl level as EFI_TPL
alias UINTN.

UINTN is an integer is defined as an unsigned integer of native
width. So we can use size_t for the definition.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:31:04 +02:00
xypron.glpk@gmx.de
c68415922b efi_loader: implement multiple event support
Up to now the boot time supported only a single event.
This patch now allows four events.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:26:09 +02:00
xypron.glpk@gmx.de
2fd945fe72 efi_loader: use struct efi_event * instead of void *
In our implementation the internal structure of events is known.
So use the known type instead of void.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:26:01 +02:00
xypron.glpk@gmx.de
71275a3e98 efi_memory: avoid NULL dereference in efi_free_pool
If efi_free_pool is called with argument NULL an illegal memory
access occurs.

So let's check the parameter on entry.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:41 +02:00
xypron.glpk@gmx.de
70bfcdc6bb efi_loader: disk: iterate only over valid block devices
The efi_loader currently stops iterating over the available
block devices stopping at the first device that fails.
This may imply that no block device is found.

With the patch efi_loader only iterates over valid devices.

It is based on patch
06d592bf52f6 (dm: core: Add uclass_first/next_device_check())
which is currently in u-boot-dm.git.

For testing I used an odroid-c2 with a dts including
&sd_emmc_a {
	status = "okay";
};
This device does not exist on the board and cannot be initialized.

Without the patch:

=> bootefi hello
## Starting EFI application at 01000000 ...
WARNING: Invalid device tree, expect boot to fail
mmc_init: -95, time 1806
Found 0 disks
Hello, world!
## Application terminated, r = 0

With the patch:

=> bootefi hello
## Starting EFI application at 01000000 ...
WARNING: Invalid device tree, expect boot to fail
mmc_init: -95, time 1806
Scanning disk mmc@70000.blk...
Scanning disk mmc@72000.blk...
Card did not respond to voltage select!
mmc_init: -95, time 9
Scanning disk mmc@74000.blk...
Found 3 disks
Hello, world!
## Application terminated, r = 0

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:41 +02:00
xypron.glpk@gmx.de
1da1bac477 efi_loader: provide meaningful status code
Currenty any EFI status other than EFI_SUCCESS is reported as
Application terminated, r = -22

With the patch the status code returned by the EFI application
is printed.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:41 +02:00
xypron.glpk@gmx.de
3c8ffb6875 efi_loader: define all known status codes
efi.h held only a few EFI status codes.

The patch adds the missing definitions for later usage.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:40 +02:00
xypron.glpk@gmx.de
b06d8ac39e bootefi: allow return without EFI_BOOT_SERVICES.Exit
The Unified Extensible Firmware Interface Specification, version 2.7,
defines in chapter 2.1.2 - UEFI Application that an EFI application may
either directly return or call EFI_BOOT_SERVICES.Exit().

Unfortunately U-Boot makes the incorrect assumption that
EFI_BOOT_SERVICES.Exit() is always called.

So the following application leads to a memory exception on the aarch64
architecture when returning:

EFI_STATUS efi_main(
  EFI_HANDLE handle,
  EFI_SYSTEM_TABlE systable) {
	return EFI_SUCCESS;
}

With this patch the entry point is stored in the image handle.

The new wrapper function do_enter is used to call the EFI entry point.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:40 +02:00
xypron.glpk@gmx.de
cc5b70812f efi_loader: implement EFI_DEVICE_PATH_TO_TEXT_PROTOCOL
ConvertPathToText is implemented for
* type 4    - media device path
* subtype 4 - file path

This is the kind of device path we hand out for block devices.

All other cases may be implemented later.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
[agraf: fix whitespace]
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:40 +02:00
xypron.glpk@gmx.de
88adae5ef0 efi_loader: reimplement efi_locate_protocol
The UEFI specification requires that LocateProtol finds the first
handle supporting the protocol and to return a pointer to its
interface.

So we have to assign the protocols to an efi_object and not use
any separate storage.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:40 +02:00
xypron.glpk@gmx.de
011f432745 efi_loader: provide a sufficient number of protocols
Four protocols per object is too few to run iPXE.

Let's raise the number of protocols per object to eight.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:39 +02:00
xypron.glpk@gmx.de
c2e703f903 efi_loader: implement LocateHandleBuffer
UEFI boot service LocateHandleBuffer is implemented by calling
efi_allocate_handle and efi_locate_handle.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:39 +02:00
xypron.glpk@gmx.de
26329584f3 efi_loader: refactor efi_locate_handle
To implement LocateHandleBuffer we need to call efi_locate_handle
internally without running through EFI_EXIT.

So put EFI_ENTRY and EFI_EXIT into a new wrapper function
efi_locate_handle_ext.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:39 +02:00
xypron.glpk@gmx.de
58b8358606 efi_loader: implement InstallMultipleProtocolInterfaces
Implement InstallMultipleProtocolInterfaces in function
efi_install_multiple_protocol_interfaces by repeatedly
calling efi_install_protocol_interface.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:39 +02:00
xypron.glpk@gmx.de
3d8e145608 efi_loader: refactor efi_uninstall_protocol_interface
For the implementation of UninstallMultipleProtocolInterfaces we
need to call efi_uninstall_protocol_interface. In internal calls
we should not pass through EFI_EXIT.

The patch introduces a wrapper function
efi_uninstall_protocol_interface_ext.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:39 +02:00
xypron.glpk@gmx.de
8bee5a3c13 efi_loader: refactor efi_install_protocol_interface
For the implementation of InstallMultipleProtocolInterfaces we
need to call efi_install_protocol_interface. In internal calls
we should not pass through EFI_EXIT.

The patch introduces a wrapper function
efi_install_protocol_interface_ext.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:38 +02:00
xypron.glpk@gmx.de
4b6ed0d7a1 efi_loader: implement UninstallProtocolInterface
Without the patch efi_uninstall_protocol_interface always returns an
error.

With the patch protocols without interface can be uninstalled.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:38 +02:00
xypron.glpk@gmx.de
e0549f8a17 efi_loader: implement InstallProtocolInterface
efi_install_protocol_interface up to now only returned an error code.

The patch implements the UEFI specification for InstallProtocolInterface
with the exception that it will not create new handles.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:38 +02:00
xypron.glpk@gmx.de
69baec6781 efi_loader: efi_open_protocol: parameter checks
Add all parameter checks for function efi_open_protocol that do not
depend on a locking table.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:38 +02:00
xypron.glpk@gmx.de
b5349f742a efi_loader: refactor efi_open_protocol
efi_open_protocol was implemented to call a protocol specific open
function to retrieve the protocol interface.

The UEFI specification does not know of such a function.

It is not possible to implement InstallProtocolInterface with the
current design.

With the patch the protocol interface itself is stored in the list
of installed protocols of an efi_object instead of an open function.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
[agraf: fix efi gop support]
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-07-19 14:14:23 +02:00
Masahiro Yamada
aae6f016a7 mmc: cadence: use fdt32_t for DT property value to fix sparse warning
DTB is encoded in big endian.  When we retrieve property values,
we need to use fdt32_to_cpu (aka be32_to_cpu) for endian conversion.
This is a bit error-prone, but sparse is useful to detect endian
mismatch.

We need to use (fdt32_t *) instead of (u32 *) for a pointer of a
property value.  Otherwise sparse warns "cast to restricted __be32".

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-07-19 19:13:59 +09:00
Masahiro Yamada
207d8b3533 mmc: add static to spl_mmc_get_device_index()
This function is only used in common/spl/spl_mmc.c[

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-07-19 19:13:59 +09:00
Keerthy
a79e8dfed6 power: regulator: lp87565: get_enable should return integer
get_enable should be able to return error values. Hence change
the return type to integer.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-19 19:13:59 +09:00
Keerthy
43d0247e3e power: regulator: lp873x: get_enable should return integer
get_enable should be able to return error values. Hence change
the return type to integer.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-19 19:13:59 +09:00
Keerthy
4e98a140c8 power: regulator: s5m8767: get_enable should return integer
get_enable should be able to return error values. Hence change
the return type to integer.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-19 19:13:59 +09:00
Keerthy
3bbe7c136b power: sandbox: fixed: get_enable should return integer
get_enable should be able to return error values. Hence change
the return type to integer.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-19 19:13:59 +09:00
Keerthy
585c7032bf power: regulator: rk8xx: get_enable should return integer
get_enable should be able to return error values. Hence change
the return type to integer.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-19 19:13:59 +09:00
Keerthy
2a4747d3cd power: regulator: tps65090: get_enable should return integer
get_enable should be able to return error values. Hence change
the return type to integer.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-19 19:13:59 +09:00
Keerthy
117daa8220 power: regulator: pfuze100: get_enable should return integer
get_enable should be able to return error values. Hence change
the return type to integer.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-19 19:13:59 +09:00
Keerthy
5c3195c61b power: regulator: palmas: get_enable should return integer
get_enable should be able to return error values. Hence change
the return type to integer.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-19 19:13:59 +09:00
Keerthy
b616835ddf power: regulator: max77686: get_enable should return integer
get_enable should be able to return error values. Hence change
the return type to integer.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-19 19:13:59 +09:00
Keerthy
85f87de313 power: regulator: act8846: get_enable should return integer
get_enable should be able to return error values. Hence change
the return type to integer.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-19 19:13:59 +09:00
Keerthy
0f2194d825 power: regulator: fixed: get_enable should return integer
get_enable should be able to return error values. Hence change
the return type to integer.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-19 19:13:59 +09:00
Keerthy
06bdf6003b regulator: Change get_enable return type to integer from bool
Change get_enable return type to int so errors can be returned.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-19 19:13:59 +09:00
Kever Yang
343749c425 mmc: rpmb: update size format for write_counter
According to MMC spec, the write_counter is 4-byte length,
use 'int' instead of 'long' type for the 'long' is not 4-byte
in 64 bit CPU.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-07-19 19:13:59 +09:00
Kever Yang
4dc80c8732 mmc: use new hwpart API when CONFIG_BLK enabled
When CONFIG_BLK is enabled, the hwpart id is different with legacy
interface, update it to kame driver work with CONFIG_BLK.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-07-19 19:13:59 +09:00
Marek Vasut
2710d54f54 ARM: Mark AE boards orphan
I no longer have any of these boards, mark boards orphan.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
2017-07-18 15:21:30 -04:00
Tom Rini
39632b4a01 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2017-07-18 08:42:48 -04:00
Fabio Estevam
651782a08b mx6cuboxi: Move CONFIG_CMD_SATA to Kconfig
Move CONFIG_CMD_SATA option to Kconfig to fix the following build
error:

In file included from include/configs/mx6cuboxi.h:137:0,
                 from include/config.h:7,
                 from include/common.h:21,
                 from common/env_common.c:11:
include/config_distro_bootcmd.h:161:2: error: expected '}' before 'BOOT_TARGET_DEVICES_references_SATA_without_CONFIG_SATA'
  BOOT_TARGET_DEVICES_references_SATA_without_CONFIG_SATA

Reported-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-14 15:16:01 +02:00
Fabio Estevam
3f0a1042bb mx6sabreauto: Make Ethernet functional again
Since commit ce412b79e7 ("drivers: net: phy: atheros: add separate
config for AR8031") Ethernet does not work on mx6sabreauto.

This commit correctly assigns ar8031_config() as the configuration
function for AR8031 in the same way as done in the Linux kernel.

However, on mx6sabreauto design we need some additional configurations,
such as enabling the 125 MHz AR8031 output and setting the TX clock
delay that need to be done in the board file.

This is the equivalent fix from commit 4b6035da48 ("mx6sabresd: Make
Ethernet functional again").

Reported-by: Miquel RAYNAL <miquel.raynal@free-electrons.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-13 15:05:49 +02:00
Tom Rini
e14b1169c0 Merge git://www.denx.de/git/u-boot-marvell 2017-07-12 08:16:41 -04:00
Patrick Bruenn
bc104a7066 imx: cx9020: try pxe boot, if no vmlinuz on mmc
If no vmlinuz is found on mmc, try to boot from pxe.

Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
2017-07-12 10:29:57 +02:00
Patrick Bruenn
f8e63850c2 imx: cx9020: use fdt_addr_r and ramdisk_addr_r
Replace fdtaddr and rdaddr variable names with u-boot standard names
fdt_addr_r and ramdisk_addr_r.
This will make the use of pxe boot more easy.

Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
2017-07-12 10:29:40 +02:00
Diego Dorta
07f6ddb67a mx6sabreauto: Add Falcon mode support
Add support for Falcon mode and explain in the README the steps to
boot the kernel directly without loading the full U-Boot.

Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
Acked-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-12 10:28:19 +02:00
Fabio Estevam
283c2a6553 warp: Use PARTUUID to specify the rootfs location
warp can run different kernel versions, such as NXP 4.1 or
mainline.

Currently the rootfs location is passed via mmcblk number and the
problem with this approach is that the mmcblk number for the eMMC
changes depending on the kernel version.

In order to avoid such issue, use UUID method to specify the rootfs
location.

Succesfully tested booting a NXP 4.1 and also a mainline 4.12 kernel.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2017-07-12 10:25:52 +02:00
Fabio Berton
0f29a61c53 embestmx6boards: Use PARTUUID to specify the rootfs location
Currently the rootfs location is passed via mmcblk number and the
problem with this approach is that the mmcblk number for the eMMC
changes depending on the kernel version.

In order to avoid such issue, use UUID method to specify the rootfs
location.

Also add CONFIG_BOOTCOMMAND to run finduuid function and distro_bootcmd.

This change was made based on U-Boot commit:

  - ca4f338e2e

Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-12 10:25:04 +02:00
Fabio Berton
35ba390d62 mx6cuboxi: Use PARTUUID to specify the rootfs location
Currently the rootfs location is passed via mmcblk number and the
problem with this approach is that the mmcblk number for the eMMC
changes depending on the kernel version.

In order to avoid such issue, use UUID method to specify the rootfs
location.

This change was made based on U-Boot commit:

  - ca4f338e2e

Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-12 10:24:48 +02:00
Fabio Berton
84b4690f26 wandboard: Use PARTUUID to specify the rootfs location
Currently the rootfs location is passed via mmcblk number and the
problem with this approach is that the mmcblk number for the eMMC
changes depending on the kernel version.

In order to avoid such issue, use UUID method to specify the rootfs
location.

This change was made based on U-Boot commit:

  - ca4f338e2e

Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-12 10:24:34 +02:00
Fabio Estevam
00f43e51c5 mx6sabre: Use PARTUUID to specify the rootfs location
mx6sabre boards can run different kernel versions, such as NXP 4.1 or
mainline.

Currently the rootfs location is passed via mmcblk number and the
problem with this approach is that the mmcblk number for the eMMC
changes depending on the kernel version.

In order to avoid such issue, use UUID method to specify the rootfs
location.

Succesfully tested booting a NXP 4.1 and also a mainline kernel on a
mx6qsabresd and mx6dlsabreauto.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-12 10:23:37 +02:00
Fabio Estevam
ca62e5d043 mx6sabreauto: Do not enable WEIM by default
WEIM cannot be used when I2C3 is enabled due to pin conflict, so keep
WEIM disabled by default.

I2C3 controls GPIO I2C expander (USB host and OTG have VBUS controlled by
the GPIO I2C expander), magnetometer, accelerometer.

Not disabling WEIM in U-Boot causes I2C3 to behave badly when booting
a NXP 4.1 kernel, which leads to probe failure on several devices,
including the lack of USB:

imx_usb 2184000.usb: Can't register ci_hdrc platform device, err=-517

By keeping WEIM disabled in U-Boot these kernel issues are gone.

Reported-by: Takashi Matsuzawa <tmatsuzawa@xevo.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-12 10:21:10 +02:00
Stefano Babic
552a848e4f imx: reorganize IMX code as other SOCs
Change is consistent with other SOCs and it is in preparation
for adding SOMs. SOC's related files are moved from cpu/ to
mach-imx/<SOC>.

This change is also coherent with the structure in kernel.

Signed-off-by: Stefano Babic <sbabic@denx.de>

CC: Fabio Estevam <fabio.estevam@nxp.com>
CC: Akshay Bhat <akshaybhat@timesys.com>
CC: Ken Lin <Ken.Lin@advantech.com.tw>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: Heiko Schocher <hs@denx.de>
CC: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com>
CC: Christian Gmeiner <christian.gmeiner@gmail.com>
CC: Stefan Roese <sr@denx.de>
CC: Patrick Bruenn <p.bruenn@beckhoff.com>
CC: Troy Kisky <troy.kisky@boundarydevices.com>
CC: Nikita Kiryanov <nikita@compulab.co.il>
CC: Otavio Salvador <otavio@ossystems.com.br>
CC: "Eric Bénard" <eric@eukrea.com>
CC: Jagan Teki <jagan@amarulasolutions.com>
CC: Ye Li <ye.li@nxp.com>
CC: Peng Fan <peng.fan@nxp.com>
CC: Adrian Alonso <adrian.alonso@nxp.com>
CC: Alison Wang <b18965@freescale.com>
CC: Tim Harvey <tharvey@gateworks.com>
CC: Martin Donnelly <martin.donnelly@ge.com>
CC: Marcin Niestroj <m.niestroj@grinn-global.com>
CC: Lukasz Majewski <lukma@denx.de>
CC: Adam Ford <aford173@gmail.com>
CC: "Albert ARIBAUD (3ADEV)" <albert.aribaud@3adev.fr>
CC: Boris Brezillon <boris.brezillon@free-electrons.com>
CC: Soeren Moch <smoch@web.de>
CC: Richard Hu <richard.hu@technexion.com>
CC: Wig Cheng <wig.cheng@technexion.com>
CC: Vanessa Maegima <vanessa.maegima@nxp.com>
CC: Max Krummenacher <max.krummenacher@toradex.com>
CC: Stefan Agner <stefan.agner@toradex.com>
CC: Markus Niebel <Markus.Niebel@tq-group.com>
CC: Breno Lima <breno.lima@nxp.com>
CC: Francesco Montefoschi <francesco.montefoschi@udoo.org>
CC: Jaehoon Chung <jh80.chung@samsung.com>
CC: Scott Wood <oss@buserror.net>
CC: Joe Hershberger <joe.hershberger@ni.com>
CC: Anatolij Gustschin <agust@denx.de>
CC: Simon Glass <sjg@chromium.org>
CC: "Andrew F. Davis" <afd@ti.com>
CC: "Łukasz Majewski" <l.majewski@samsung.com>
CC: Patrice Chotard <patrice.chotard@st.com>
CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Hans de Goede <hdegoede@redhat.com>
CC: Masahiro Yamada <yamada.masahiro@socionext.com>
CC: Stephen Warren <swarren@nvidia.com>
CC: Andre Przywara <andre.przywara@arm.com>
CC: "Álvaro Fernández Rojas" <noltari@gmail.com>
CC: York Sun <york.sun@nxp.com>
CC: Xiaoliang Yang <xiaoliang.yang@nxp.com>
CC: Chen-Yu Tsai <wens@csie.org>
CC: George McCollister <george.mccollister@gmail.com>
CC: Sven Ebenfeld <sven.ebenfeld@gmail.com>
CC: Filip Brozovic <fbrozovic@gmail.com>
CC: Petr Kulhavy <brain@jikos.cz>
CC: Eric Nelson <eric@nelint.com>
CC: Bai Ping <ping.bai@nxp.com>
CC: Anson Huang <Anson.Huang@nxp.com>
CC: Sanchayan Maity <maitysanchayan@gmail.com>
CC: Lokesh Vutla <lokeshvutla@ti.com>
CC: Patrick Delaunay <patrick.delaunay@st.com>
CC: Gary Bisson <gary.bisson@boundarydevices.com>
CC: Alexander Graf <agraf@suse.de>
CC: u-boot@lists.denx.de
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-07-12 10:17:44 +02:00
Peng Fan
f34ccce50a mmc: fsl_esdhc: drop CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT is not the correct method
to set I/O to 1.8. To boards that does not support vqmmc-supply,
use vs18_enable in fsl_esdhc_cfg. If regulator is supported,
use fixed 1.8V regulator for vqmmc-supply.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2017-07-12 09:44:22 +02:00
Peng Fan
4483b7eb88 dm: mmc: fsl_esdhc: handle vqmmc supply
Handle vqmmc supply. Some boards have a fixed I/O voltage
at 1.8V for emmc, so the usdhc also needs to be configured
as 1.8V by setting VSELECT bit. The vs18_enable is the one
that used to checking whether setting VSELECT or not in
the driver. So if vqmmc supply is 1.8V, set vs18_enable,
the driver will set VSELECT.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-07-12 09:44:22 +02:00
Peng Fan
32a9179f3a mmc: fsl_esdhc: introduce vs18_enable for 1.8V fix I/O
When using eMMC with 1.8V I/O, the VSELECT bit need to be set in
the USDHC controller when init.

This patch adds a parameter "vs18_enable" in fsl_esdhc_cfg
structure and priv data, so each controller can have different
settings.

We could not use CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT, it has problem
that it will apply to all USDHC controllers and it only set the 1.8V
at init phase. So if user does not select to the eMMC device,
the voltage on the I/O pins are not correct.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2017-07-12 09:44:22 +02:00
Peng Fan
15a91651bf mmc: fsl_esdhc: correct type of wp_enable
The type should be int, not u8. cfg->wp_enable will finally be
assigned to priv->wp_enable whose type is int.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2017-07-12 09:44:22 +02:00
Jagan Teki
ed2d02d4ce imx6_spl: Add u-boot-dtb.img for SPL payload
Add u-boot-dtb.img for SPL_FS_LOAD_PAYLOAD_NAME when
OF_CONTROL used.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-07-12 09:44:22 +02:00
Vanessa Maegima
d7c11502df mx6sabreauto: Update to SPL only mode
As mx6sabreauto supports SPL now, all variants can boot using the same
defconfig.

This patch:
- Removes non-SPL targets.
- Renames target to mx6sabreauto_defconfig.
- Renames folder and board files to mx6sabreauto.
- Updates MAINTAINERS, Makefile and Kconfig accordingly.
- Removes .cfg files.
- Adds a README with instructions to build and flash SPL and u-boot.img.

Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-07-12 09:44:22 +02:00
Vanessa Maegima
823dff9d02 mx6qsabreauto: Add SPL support
Add support for mx6q, mx6dl and mx6qp sabreauto boards in SPL.

Retrieved the mx6q DCD table from:
board/freescale/mx6qsabreauto/imximage.cfg

Retrieved the mx6dl DCD table from:
board/freescale/mx6qsabreauto/mx6dl.cfg

Retrieved the mx6qp DCD table from:
board/freescale/mx6qsabreauto/mx6qp.cfg

Flashed SPL and u-boot.img to an SD card and could successfully boot it
on mx6q, mx6qp and mx6dl sabreauto boards.

Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-07-12 09:44:22 +02:00
Peter Robinson
ff18156325 mx6cuboxi: Add support for sata
The Cubox-i and Hummingboard series of devices have an option of
SATA on board, and depending on how the fuses are blown even the
option to boot SPL from SATA. So enable support for it so it can
be used to boot the OS from if people desire.

Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Acked-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-12 09:44:22 +02:00
Gautam Bhat
d8fab10cb4 mx7dsabresd: Set VLD04 output to 2.8V in PMIC initialization.
This change sets the VLDO4 settings output to 2.8V in PMIC
initialization so that the MIPI DSI/CSI input voltage is 2.8V
as per the schematics. The original code provides an output of
3.3V which violates the voltage mentioned in the schematics.

Signed-off-by: Gautam Bhat <mindentropy@gmail.com>
Acked-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-12 09:44:22 +02:00
Fabio Estevam
a1d1fdc920 mx6: soc: Move mxs_dma_init() into the mxs nand driver
Currently the following build error is seen when a board using MMC SPL
is built and the MXS nand driver is also selected:

arch/arm/cpu/armv7/built-in.o: In function `arch_cpu_init':
arch/arm/cpu/armv7/mx6/soc.c:432: undefined reference to 'mxs_dma_init'

On mx6 the only user of mxs_dma_init() is the mxs nand driver, so
move it there.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-12 09:44:22 +02:00
Lothar Waßmann
306dd7dabd net: fec_mxc: fix PHY initialization bug with CONFIG_DM_ETH
When CONFIG_DM_ETH is set, the FEC ethernet controller is reset after
the PHY has been set up and initialzed. This breaks the communication
with the PHY and results in an inoperable ethernet interface.

Do the initialization with CONFIG_DM_ETH in the same order as with
legacy ETH support to fix this.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-07-12 09:44:22 +02:00
Jagan Teki
34d45d123a icorem6_rqs: Rename icorem6_rqs config file
imx6qdl_icore_mmc_defconfig => imx6qdl_icore_rqs_defconfig
Since icorem6_rqs support MMC/eMMC boot, so doesn't need
to name it explicitly.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-07-12 09:44:22 +02:00
Florian Fainelli
022b7fb515 dt-bindings: Document the Broadcom STB wake-up timer node
Document the binding for the Broadcom STB SoCs wake-up timer node
allowing the system to generate alarms and exit low power states.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2017-07-12 09:44:22 +02:00
Jagan Teki
61366b71a8 serial: mxc: Add debug uart support
Add support for the debug UART to assist with early debugging.
Enable it for i.CoreM6 as an example.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-12 09:44:22 +02:00
Jagan Teki
52c14cabda serial: mxc: Code cleanup
- Remove space between #define to macro
- Add tab between macro and value

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-12 09:42:33 +02:00
Jagan Teki
45d97511a9 serial: mxc: Move common baud gen into _mxc_serial_setbrg
Move the common baud generation code into _mxc_serial_setbrg
so-that dm and non-dm can call this func.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-12 09:42:33 +02:00
Jagan Teki
97548d5947 serial: mxc: Move common init into _mxc_serial_init
Move the common initialization code into _mxc_serial_init
so-that dm and non-dm can call this func.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-12 09:42:33 +02:00
Jagan Teki
57d3e98f57 serial: mxc: Move cr1 and cr2 write to mxc_serial_setbrg
Control reg write should be part of setbrg for better
buadrate generation, so move cr1 and cr2 write to
mxc_serial_setbrg

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-12 09:42:33 +02:00
Jagan Teki
62af03ee97 serial: mxc: Use RFDIV in dm-code
Use RFDIV in dm-code instead of numeric value, so-that
it can be common for dm and non-dm.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-12 09:42:33 +02:00
Jagan Teki
ffa8bcd7f1 serial: mxc: Add common mxc_uart reg space
This patch will add common reg space for non-dm and
dm code and non-dm reg space can be accessed using
mxc_base.

This will
- get rid of __REG volatile assignments
- Make common reg_space by removing unneeded macros

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-12 09:42:33 +02:00
Stefan Agner
3fd9579085 imx: mx6ull: fix USB bmode for i.MX 6UL and 6ULL
i.MX 6UL and 6ULL have different boot device capabilities and
use therefor use a different boot device selection table than
other i.MX 6 devices. Particularly, the value which has been
used so far (b0001) is assigned to QSPI boot for these two
devices.

There is no common reserved value for all i.MX 6devices. Use
b0010 for i.MX 6UL and 6ULL via compile time ifdef.

Reported-by: Joël Esponde <joel.esponde@honeywell.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Joël Esponde <joel.esponde@honeywell.com>
2017-07-12 09:42:33 +02:00
Christian Gmeiner
8be70bb4aa ot1200: enable CONFIG_IMX_THERMAL for detailed thermal information
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-07-12 09:42:33 +02:00
Fabio Estevam
258f76fd21 mx6sabresd: Fix guard file symbol
Remove the "Q" from the file guard symbol, so that it matches
the file name.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-12 09:42:33 +02:00
Fabio Estevam
b8b9790e23 wandboard: Remove unnecessary delay
There is no need to add a 100us delay after the DDR initialization.

Other imx6 boards do not have such delay either, so simply remove it.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-12 09:42:33 +02:00
Fabio Estevam
dfa33fbe48 cm_fx6: Remove SPL entry from CONFIG_SYS_EXTRA_OPTIONS
SPL is already selected via CONFIG_SPL=y, so there is no need
to pass it inside CONFIG_SYS_EXTRA_OPTIONS.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-12 09:42:33 +02:00
Fabio Estevam
d84a8c5b28 cgtqmx6eval: Remove SPL entry from CONFIG_SYS_EXTRA_OPTIONS
SPL is already selected via CONFIG_SPL=y, so there is no need
to pass it inside CONFIG_SYS_EXTRA_OPTIONS.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-12 09:42:33 +02:00
Fabio Estevam
7f27eec72e mx6slevk_spl: Remove SPL entry from CONFIG_SYS_EXTRA_OPTIONS
SPL is already selected via CONFIG_SPL=y, so there is no need
to pass it inside CONFIG_SYS_EXTRA_OPTIONS.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-12 09:42:33 +02:00
Fabio Estevam
41857231d5 mx6sabresd: Remove SPL entry from CONFIG_SYS_EXTRA_OPTIONS
SPL is already selected via CONFIG_SPL=y, so there is no need
to pass it inside CONFIG_SYS_EXTRA_OPTIONS.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-12 09:42:33 +02:00
Baruch Siach
172b2e0b56 arm: mvebu: clearfog: fix chip name comment
The clearfog uses Armada 388.

Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-07-12 06:57:55 +02:00
Baruch Siach
db7cd4ed33 tools/kwbimage: fix v1 header verification
The verify_header callback in kwbimage.c only verifies v0 headers checksum.
Running 'mkimage -l' on a v1 image gives the following misleading output:

GP Header: Size ae000000 LoadAddr 34160600

Implement support for v1 headers. For that, factor out the header checksum code
to a separate main_hdr_checksum_ok() routine. This routine relies on the fact
that the checksum field offset is the same in both v0 and v1 headers. With this
patch applied 'mkimage -l' correctly identifies the image:

Image Type:   MVEBU Boot from sdio Image
Image version:1
Data Size:    398904 Bytes = 389.55 KiB = 0.38 MiB
Load Address: 007fffc0
Entry Point:  00800000

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-07-12 06:57:55 +02:00
Baruch Siach
37d108b64f tools/kwbimage.h: make offset marks style consistent
The offset marking in kwbimage.h is inconsistent. main_hdr_v0 uses decimals,
main_hdr_v1 uses hex without '0x' prefix, secure_hdr_v1 uses hex with '0x'
prefix. Make all offset marks hex with '0x' prefix.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-07-12 06:57:55 +02:00
Baruch Siach
ed72741d9f tools/kwbimage: update the list of SoCs using v1 header
Armada 38x also uses image header v1.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-07-12 06:57:55 +02:00
Igal Liberman
b6518b1ea3 arm64: mvebu: use single defconfig for Armada8K development boards
Currently, Marvell Armada8k development board use 3 different
defconfigs:
        mvebu_db-88f7040-nand_defconfig
        mvebu_db-88f7040_defconfig
        mvebu_db-88f8040_defconfig
Having 3 different defconfigs makes maintenance difficult.

This patch removes the defconfigs mentioned above and introduce
a new defconfig which represents the Armada8k family.

NOTE:
In order not to break automatic tools compilation,
a default device-tree is set in the defconfig (armada-8040-db).
However, when compiling u-boot, the user MUST explicitly export
the DEVICE_TREE for the requested board because using A80x0
device-tree on A70x0 might break the device.

For more information, refer to "doc/README.marvell" (intoduced
in this patch).

Change-Id: I98515b6306498358f3722ecf7ac4c87f236ebbd8
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-07-12 06:57:55 +02:00
Marek Behún
b6ee860b87 marvell: armada385: Add the Turris Omnia board
The Turris Omnia is a open-source router created by CZ.NIC.

The code is based on the Marvell/db-88f6820-gp by Stefan Roese
with modifications from Tomas Hlavacek in the CZ.NIC turris-omnia-uboot
repository, which can be found at
https://gitlab.labs.nic.cz/turris/turris-omnia-uboot

By default, the Turris Omnia uses btrfs as the main and only filesystem,
and also loads kernel and device tree from this filesystem. Since U-Boot
does not yet support btrfs, you should not flash your Turris Omnia board
with this unless you know what you are doing.

Signed-off-by: Tomas Hlavacek <tomas.hlavacek@nic.cz>
Signed-off-by: Marek Behun <marek.behun@nic.cz>

 create mode 100644 board/CZ.NIC/turris_omnia/Makefile
 create mode 100644 board/CZ.NIC/turris_omnia/kwbimage.cfg
 create mode 100644 board/CZ.NIC/turris_omnia/turris_omnia.c
 create mode 100644 configs/turris_omnia_defconfig
 create mode 100644 include/configs/turris_omnia.h
Signed-off-by: Stefan Roese <sr@denx.de>
2017-07-12 06:57:38 +02:00
Marek Behún
aa5eb9a3ac drivers/misc: Add basic support for ATSHA204A Crypto module
This module can be found on the Turris Omnia board connected
via the I2C interface.

Among some cryptographic functions, the chip has a 512 bit
One Time Programmable memory, 88 byte configuration memory
and 512 byte general purpose memory.

The Turris Omnia stores serial number and device MAC address in
the OTP memory.

This commit adds basic support for reading the EEPROM and also
exposes the chips Random Number Generator.

The driver is based on code by
  Josh Datko, Cryptotronix, jbd@cryptotronix.com
and also
  Tomas Hlavacek, CZ.NIC, tomas.hlavacek@nic.cz

Signed-off-by: Tomas Hlavacek <tomas.hlavacek@nic.cz>
Signed-off-by: Marek Behun <marek.behun@nic.cz>

 create mode 100644 drivers/misc/atsha204a-i2c.c
 create mode 100644 include/atsha204a-i2c.h
Signed-off-by: Stefan Roese <sr@denx.de>
2017-07-12 06:57:38 +02:00
Marek Behún
8e6eda7cda drivers/i2c/muxes/pca954x: Add pca9547 I2C mux support
This I2C mux is found, for example, on the Turris Omnia board.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-07-12 06:56:48 +02:00
Marek Behún
c2502e7b82 arch/arm/dts: Add Turris Omnia device tree
This device tree is taken from mainline Linux kernel commit
7b7db5ab. Added is also a -u-boot.dtsi file with these additions:

  - aliases for I2C and SPI devices are added, because i2cmux and
    SPI flash doesn't work otherwise
  - spi_flash node has been added so that the new DM API works
  - the ATSHA204A node is added in the i2c@5 node
  - "u-boot,dm-pre-reloc"s are added in needed nodes for SPL
    build to work correctly

Signed-off-by: Marek Behun <marek.behun@nic.cz>

 create mode 100644 arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi
 create mode 100644 arch/arm/dts/armada-385-turris-omnia.dts
Signed-off-by: Stefan Roese <sr@denx.de>
2017-07-12 06:56:48 +02:00
Marek Behún
2ab7704a6d orion_wdt: Support for the Orion Watchdog
The Orion watchdog can be found on some Marvell Armada chips.

This driver is based on the code by Tomas Hlavacek in the CZ.NIC
turris-omnia-uboot repository, which can be found at
https://gitlab.labs.nic.cz/turris/turris-omnia-uboot, and that
one is based on code by Sylver Bruneau. His code is already in
mainline Linux kernel.

The code uses the new driver model API.

Signed-off-by: Tomas Hlavacek <tomas.hlavacek@nic.cz>
Signed-off-by: Marek Behun <marek.behun@nic.cz>

 create mode 100644 drivers/watchdog/orion_wdt.c
Signed-off-by: Stefan Roese <sr@denx.de>
2017-07-12 06:56:48 +02:00
Marek Behún
90bcc3d38d driver/ddr: Add support for setting timing in hws_topology_map
The DDR3 training code for Marvell A38X currently computes 1t timing
when given board topology map of the Turris Omnia, but Omnia needs 2t.

This patch adds support for enforcing the 2t timing in struct
hws_topology_map, through a new enum hws_timing, which can assume
following values:
  HWS_TIM_DEFAULT - default behaviour, compute whether to enable 2t
                    from the number of CSs
  HWS_TIM_1T      - enforce 1t
  HWS_TIM_2T      - enforce 2t

This patch also sets all the board topology maps (db-88f6820-amc,
db-88f6820-gp, controlcenterdc and clearfog) to have timing set to
HWS_TIM_DEFAULT.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-07-12 06:56:48 +02:00
Alexandru Gagniuc
409a81ddd4 am33xx: board: Refactor USB initialization into separate function
The declaration of otg*_plat and otg*_board_data is guarded by
CONFIG_USB_MUSB_*, but their use in arch_misc_init is not. The
ifdef flow goes something like:

if (CONFIG_USB_MUSB_* && other_conditions)
	declare usb_data
if (other_conditions)
	use usb_data

Thus when CONFIG_USB_MUSB_* is not declared, we try to use the
data structures, but these structures aren't defined.

To fix this, move the USB initialization code into the same #ifdef
which guards the declaration of the data structures. Since the DM_USB
vs legacy cases are completely different, use two versions of
arch_misc_init(), for readability.

Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-11 22:49:39 -04:00
Alexandru Gagniuc
17a21e206a configs: am335x_evm: Enable FASTBOOT based on kconfig
When CONFIG_CMD_FASTBOOT or CONFIG_USB_FUNCTION_FASTBOOT are defined
in am335x_evm.h, a dependency on g_dnl.c is created. This in turn
creates a dependency on having USB gadget enabled.
As a result we can't create configs with USB gadget disabled.

Since these CONFIG_ variables are now part of kconfig, move them to
the board defconfigs, and out of am335x_evm.h. This both preserves
current defaults, and allows creating configs with USB gadget off.

Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-11 22:49:38 -04:00
Tom Rini
ab86dc7948 ARM: ti816x: Fix enabling GPIO0, enable GPIO1 as well
The TI816x has 2 GPIO banks.  For bank 0 we had been clearing the enable
bit when setting BIT(8).  Correct this by setting it to BIT(1) | BIT(8)
after we set and wait for BIT(1) (aka PRCM_MOD_EN).  Enable GPIO1 as
well so that when CMD_GPIO is enabled it won't crash probing the second
bank.  Enable CMD_GPIO on ti816x_evm.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-11 22:41:56 -04:00
Tom Rini
39b4f6bce3 ti816x: Enable ethernet support
The ti816x SoC revision of the ethernet IP block is handled by the
"davinci_emac" driver, rather than the "cpsw" driver as done by later
members of the family.  Enable the relevant plumbing.

Signed-off-by: Sriramakrishnan <srk@ti.com>
Signed-off-by: Vitaly Wool <vitaly.wool@konsulko.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-11 22:41:56 -04:00
Grygorii Strashko
7a9dfe75cf mtd: nand: make nand_info array static
Make make nand_info array static, since all direct users of nand_info array
have been converted to use get_nand_dev_by_index() API.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:54 -04:00
Grygorii Strashko
8a049dd642 armv8: fsl-layerscape: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly.

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: York Sun <york.sun@nxp.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:53 -04:00
Grygorii Strashko
bf264cd0f6 board: toradex: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly.

Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:52 -04:00
Grygorii Strashko
573cc46c65 board: BuR: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by:  Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11 22:41:52 -04:00
Grygorii Strashko
2ecba112d7 board: ronetix: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:51 -04:00
Grygorii Strashko
31f8d39e2a board: atmel: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:51 -04:00
Grygorii Strashko
7021c7e6f2 cmd: mvebu: bubt: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:49 -04:00
Grygorii Strashko
88b81bf792 mtd: nand: drv: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:49 -04:00
Grygorii Strashko
750b34c9ae net: fm: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2017-07-11 22:41:48 -04:00
Grygorii Strashko
1ceac70080 net: phy: cortina: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2017-07-11 22:41:48 -04:00
Grygorii Strashko
6308e71be4 cmd: nand: remove direct access to struct mtd_info->priv
Replace direct access to struct mtd_info->priv with proper
accessor mtd_to_nand().

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:47 -04:00
Grygorii Strashko
eb6a5c3c02 fs: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:47 -04:00
Grygorii Strashko
edba8cc4f3 common: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:46 -04:00
Grygorii Strashko
bfdba68eac cmd: jffs2: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:46 -04:00
Grygorii Strashko
f370b51510 cmd: bootm: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:45 -04:00
Grygorii Strashko
1652018991 dfu: dfu_nand: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:45 -04:00
Grygorii Strashko
a94a261939 common: env_nand: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:44 -04:00
Mugunthan V N
ad92dff28c cmd: nand: abstract global variable usage for dm conversion
nand_info is used all over the file so abstract it with
get_nand_dev_by_index() which will help for DM conversion.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:44 -04:00
Tom Rini
8d3a25685e Merge git://git.denx.de/u-boot-dm 2017-07-11 20:28:46 -04:00
Tom Rini
d43ef73bf2 Merge branch 'master' of git://git.denx.de/u-boot-rockchip 2017-07-11 14:21:50 -04:00
Masahiro Yamada
8c9eaadaaa dm: ofnode: use fdt32_t for DT property value to fix sparse warning
DTB is encoded in big endian.  When we retrieve property values,
we need to use fdt32_to_cpu (aka be32_to_cpu) for endian conversion.
This is a bit error-prone, but sparse is useful to detect endian
mismatch.

We need to use (fdt32_t *) instead of (u32 *) for a pointer of a
property value.  Otherwise sparse warns "cast to restricted __be32".

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Masahiro Yamada
fce136aafe dm: include <dm/util.h> from driver/core/dump.c
Include <dm/util.h> to fix sparse warnings:
symbol 'dm_dump_all' was not declared. Should it be static?
symbol 'dm_dump_uclass' was not declared. Should it be static?

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Masahiro Yamada
b2ec7ea731 dm: ofnode: simplify ofnode_read_bool()
Reuse ofnode_get_property() to simplify the implementation.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Masahiro Yamada
61e51babdb dm: ofnode: rename ofnode_read_prop() to ofnode_get_property()
This function returns the pointer to the value of a node property.
The current name ofnode_read_prop() is confusing.  Follow the naming
of_get_property() from Linux.

The return type (const u32 *) is wrong.  DT property values can be
strings as well as integers.  This is why of_get_property/fdt_getprop
returns an opaque pointer.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Masahiro Yamada
cb7dbe1fb0 dm: ofnode: simplify ofnode_read_prop()
The code inside the if-block is the same as of_get_property().

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Masahiro Yamada
252510ac69 dm: ofnode: use ofnode_read_bool() to check property existence
This will clarify the code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Masahiro Yamada
766c28a548 dm: include <dm/util.h> from drivers/core/util.c
Fix sparse warnings "... was not declared. Should it be static?"

Also, fix redefinition of dm_warn/dm_dbg.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:20 -06:00
Tom Rini
99bb38e2cc fdt: Check for NULL return from fdt_getprop in 'fdt set'
While the previous pass through fixed one place where we knew that
fdt_getprop would be given a positive len, in the case of 'fdt set' we
do not, so check that we did no get NULL from fdt_getprop().

Cc: Simon Glass <sjg@chromium.org>
Reported-by: Coverity (CID: 163249)
Fixes 72c98ed1ab ("fdt: Add a check to do_fdt() for coverity")
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Simon Glass
f53dcc0e35 tegra: fdt: Ensure that the console UART is enabled
Many tegra boards have the console UART node disabled. With livetree this
prevents serial from working since it does not 'force' the console to be
bound. Updates the affected boards to fix this error.

The boards were checked with:

for b in $(grep  tegra boards.cfg  |grep -v integrator | \
		awk '{print $7}' | sort); do
	echo $b;
	fdtgrep -c nvidia,tegra20-uart b/$b/u-boot.dtb |grep okay;
done

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
50d8c4a465 tegra: Show a debug message if the LCD PMIC fails to start
This error condition should have a debug() message. Add it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
f93472a022 dm: serial: Add livetree support
Add support for a live device tree to the core serial uclass.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
d09608534c dm: serial: Separate out the core serial-device finding code
This function is quite long. Move the core code into a separate function
in preparation for adding livetree support.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
db9f8f6ad5 dm: serial: ns16550: Convert to livetree
Update this driver to support a live device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
03bc3f18b7 tegra: Fix up include file ordering
Update these two files so include files in the right order.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
1a9f3da917 video: simple-panel: Add a little more debugging
Add some debugging to show when the backlight is enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
7cf208d73b dm: video: Update pwm_backlight to support livetree
Update this driver to support a live device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
fb0b709eff dm: video: Sync display on backspace
We should sync the display (e.g. flush cache) when backspace is pressed
to ensure that the character is erased correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
2f0dd5cafe tegra: nyan-big: Enable bootstage
Enable full bootstage support so we can time SPL and U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
c1eb3d5966 dm: Fix error handling when unflattening the DT
The error handling code does not current detect an error right away.
Adjust it to return immediately.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
0be3a3b473 tegra: nyan-big: Enable the debug UART
Enable this to allow debugging when the serial UART driver is
misconfigured.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
23acc48d84 tegra: video: Time the LCD init
Calculate the time taken to set up the LCD.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
878d68c0c3 dm: core: Add functions to obtain node's address/size cells
The of_n_addr_cells() and of_n_size_cells() functions are useful for
getting the size of addresses in a node, but in a few places U-Boot needs
to obtain the actual property value for a node without walking up the
stack. Add functions for this and just the existing code to use it.

Add a comment to the existing ofnode functions which do not do the right
thing with a flat tree.

This fixes a problem reading PCI addresses.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
f7d6fcf7ae dm: core: Add dev_read_enabled() to check if a device is enabled
This function allows a device's status to be read. This indicates whether
the device should be enabled or disabled.

Note: In normal operation disabled devices will not be present in the
driver-model tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
a44810123f dm: core: Add dev_read_resource() to read device resources
Add a function which reads resources from a device, such as the device
hardware address. This uses the "reg" property in the device.

Unlike other functions there is little sense in inlining this when
livetree is not being used because it has some logic in it and this would
just bloat the code size.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
8c293d6ac9 dm: core: Add ofnode_read_string_count()
This provides a way to find the number of strings in a string list. Add it
and also fix up the comment for ofnode_read_string_index().

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
2017-07-11 10:08:20 -06:00
Simon Glass
7feccfdc45 binman: Put our local modules ahead of system modules
If a system module is named the same as one of those used by binman we
currently pick the system module. Adjust the ordering so that our modules
are chosen instead.

The module conflict reported was 'tools' from jira-python. I cannot access
that package to test it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
2017-07-11 10:08:20 -06:00
Simon Glass
c07919281c dtoc: Add tests
Add some tests of dtoc's functionality to make it easier to expand and
enhance the tool.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Simon Glass
2028cc59f7 sandbox: Stop printing platdata at the start of SPL
Currently we have code which prints out platform data at the start of SPL.
Now that we have tests for dtoc this is probably not necessary. Drop it.
Update test_ofplatdata to check for empty output since it is useful to
check that sandbox_spl works as expected.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Simon Glass
30107b08d7 dtoc: Add a comment about string replace in conv_name_to_c()
This function uses several separate string replaces where a regular
expression might seem more reasonable. Add a comment justifying the way it
is currently done.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Simon Glass
fa0ea5b09e dtoc: Move the main logic into the dtb_platdata file
Collect the main logic of dtoc into a function and put it into
dtb_platdata. This will allow tests to use this function instead of
duplicating the code themselves.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Simon Glass
56e0bbe057 dtoc: Move static functions out of the class
Rather than using static functions within the class, move them out of the
class. This will make it slightly easier for tests to call them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Simon Glass
e36024b05f dtoc: Pass include_disabled explicitly
This option is the only one actually used by the dtb_platdata class. Pass
it explicitly to avoid needing to pass the whole option object to the
constructor.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Simon Glass
86290ce40e dtoc: Don't handle properties with / in them
This conversion appears to not be needed as it does not occur in practice.
Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Simon Glass
2be282ca01 dtoc: Fix pylint warnings
Unfortunately I neglected to run pylint on this tool with its initial
submission. Fix the warnings.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Simon Glass
7581c01a15 dtoc: Split out the main class into its own file
To simplify running tests we should move this class into its own file.
This allows the tests to import it without having to import dtoc.py, which
runs the tests.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Simon Glass
14f5acfc5b dtoc: Add a comment at the top
Add a description of the dtoc tool at the top of the file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Simon Glass
418355cbaa dtoc: Use self._options instead of the global options
This class should use the options object passed to it rather than finding
the global one. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Simon Glass
cb008830aa moveconfig: Allow automatic location and adding of 'imply'
By using a Kconfig parser we can find the location of each option in the
Kconfig tree. Using the information from the database we can then
automatically add an 'imply' option into the right place if requested by
the user.

Add a -a option to support adding 'imply' options. Display the location of
any existing 'imply' option so that progress can be examined. Add a -A
option to hide any existing 'imply' options so that already-completed
additions need not be considered further.

Also add documentation for this feature.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Simon Glass
9b2a2e87d2 moveconfig: Allow control of which implying configs are shown
Sometimes it is useful to display CONFIG_TARGET or CONFIG_CMD configs. Add
an option to control this.

Also we generally ignore implying configs which affect fewer than 5
boards. But sometimes it is useful to show those those, so add an option
that reduces the minimum to two.

ERRATUM configs are never useful for implying things, so ignore those.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Simon Glass
2ddd85dc34 moveconfig: Allow piping in 'git show --stat' output
It is useful to be able to process only a subset of boards to save time.
Often that subset is defined by the defconfig files in a git commit. This
change allows things like:

   # Build the database
   ./tools.moveconfig.py -b

   # Find some implying configs
   ./tools/moveconfig.py -i CONFIG_X

   # Add some 'imply' statements to Kconfig files
   ./tools/moveconfig.py -i CONFIG_X -a CONFIG_A,CONFIG_B

   # Reprocess the defconfig files to see if we can drop some changes
   git show --stat | ./tools/moveconfig.py -s -d -

   # Update the commit, with fewer defconfig changes
   gii commit -au

Where the commit contains defconfig files, this will reprocess them to
take account of the imply statements that you added.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:20 -06:00
Simon Glass
d8c6fb8ced sandbox: Drop special case console code for sandbox
At present sandbox has a special case where it directly calls os_putc()
when it does not have a console yet.

Now that we have the pre-console buffer enabled we can drop this. Any
early characters will be buffered and output later.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-11 10:08:20 -06:00
Simon Glass
d63b5b4fbb sandbox: Enable more console options
Enable the pre-console buffer, displaying the model and post-relocation
console announce on sandbox. Also add a model name to the device tree.
This allows testing of these features.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-11 10:08:20 -06:00
Simon Glass
4e6bafa568 console: Use map_sysmem() for the pre-relocation console
At present this feature casts the address to a pointer. Use the
map_sysmem() function so that it will work correctly on sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-11 10:08:19 -06:00
Simon Glass
e5a9d27fdb test: Add a test for snprintf() and the banner/version
Add a simple test to make sure that these functions obey the buffer size
passed into them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-11 10:08:19 -06:00
Simon Glass
b0895384be Allow displaying the U-Boot banner on a video display
At present the U-Boot banner is only displayed on the serial console. If
this is not visible to the user, the banner does not show. Some devices
have a video display which can usefully display this information.

Add a banner which is printed after relocation only on non-serial devices
if CONFIG_DISPLAY_BOARDINFO_LATE is defined.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-11 10:08:19 -06:00
Simon Glass
6c519f2dc4 display_options: Refactor to allow obtaining the banner
Move the display options code into a separate function so that the U-Boot
banner can be obtained from other code. Adjust the 'version' command to
use it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-11 10:08:19 -06:00
Simon Glass
32e9ec1f88 x86: Move link to use driver model for SCSI
As a demonstration of how to use SCSI with driver model, move link over
to use this. This patch needs more work, but illustrates the concept.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
7337fcd8c0 dm: scsi: Drop scsi_init() when driver model is used
This function should not be used with driver model. Update the code to
reflect this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
681357ffd9 dm: ahci: Add a driver for SCSI on AHCI
Some AHCI drivers use SCSI under the hood. Rather than making the AHCI
driver be in the SCSI uclass it makes sense to have the AHCI device create
a SCSI device as a child. That way we can handle any AHCI-specific
operations rather than trying to pretend tha the device is just SCSI.

To handle this we need to provide a way for AHCI drivers to bind a SCSI
device as its child, and probe it. Add functions for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
5c56176318 dm: scsi: Split out the bus scanning code
Split out the code that scans a single SCSI bus into a separate function.
This will allow it to be used from driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
f6580ef39b dm: scsi: Adjust return value of scsi_exec()
Change this function to return an error number instead of true/false.
This allows us to return a proper error number.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
f6ab5a92ac dm: scsi: Add operations for SCSI devices
The SCSI uclass currently has no operations. It just uses the global SCSI
functions. Fix this by adding operations to the only two drivers that use
the uclass, and replacing the global functions with those defined locally
in the SCSI code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
4e74901458 dm: ahci: Create a local version of two SCSI functions
With driver model we need to define implementations of exec() and
bus_reset() separately for each SCSI driver. As a first step, create a
local version of each function in the AHCI driver and call each from its
global version.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
8eab1a58dd dm: scsi: Document and rename the scsi_scan() parameter
The 'mode' parameter is actually a flag to determine whether to display
a list of devices found during the scan. Rename it to reflect this, add a
function comment and adjust callers to use a boolean.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
4682c8a19b dm: scsi: Add a device pointer to scan_exec(), scsi_bus_reset()
With driver model these functions need a device pointer. Add one even
when CONFIG_DM_SCSI is not defined. This avoids having ugly conditional
function prototypes, When CONFIG_DM_SCSI is not defined we can just ignore
the pointer.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
322f73f473 dm: scsi: Add operations
Add operations for SCSI. These are not yet implemented, but we have the
struct.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
4279efc4c9 dm: ahci: Drop use of probe_ent
With driver model we cannot have static data or assume that there is only
one device of each time. Adjust the code so that 'probe_ent' is not needed
with driver model. Add a new ahci_init_dm() function which can init AHCI
for driver model without re-allocating the uclass data. Move over the only
existing driver to use this new function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
7cf1afce7f dm: ahci: Unwind the confusing init code
Two AHCI drivers use SCSI with CONFIG_DM_SCSI. The SCSI uclass calls
scsi_low_level_init() which is implemented by ahci.c. If
CONFIG_SCSI_AHCI_PLAT is defined it does one thing and if it is not
it does something else.

We don't need to call through scsi_low_level_init() to get the init
completed. Instead, adjust the two drivers to call into AHCI directly.
Drop the post-probe init in the SCSI uclass. This means that driver model
doesn't need to use scsi_low_level_init(). It is a legacy function and
driver model should use a driver's probe() method instead.

While we are here, add a comment to the top of the file explaining what
ahci.c does.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
62b4ec8e30 dm: ahci: Move common code for starting ports into a function
This code is duplicated. Create a ahci_start_ports() function to handle
this and call it from both places.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
099c239d68 dm: scsi: Indent the confusing #ifdefs
These are very confusing without some sort of indentation. At some point
we will be able to remove them, but for now, indent them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
225b1da7bf dm: ahci: Refactor to avoid static variables
With driver model we need each device to have its own state. As a step
towards this, restrict use of the global 'probe_ent' to just a few places
in the file. This will allow us to add driver-model functions which can
pass the correct data around.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
4b62b2ff53 dm: sata: Move ataid into struct ahci_uc_priv
This array relates to the AHCI controller so should be exist out on its
own in the file. Move it into the structure. Adjust functions that need
access to this to take the structure as a parameter.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
2c9f9efb3d dm: ahci: Rename struct ahci_probe_ent
This is not a very useful name since once it is probed it still hangs
around. With driver model we will use uclass data for this, so rename the
struct.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
1dc64f6c00 dm: scsi: Use the uclass platform data
At present the two driver-model SCSI drivers use device platform data to
store information that relates to the uclass. It is better to use uclass
platform data in this situation. Update the code to do this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
b9560ad649 dm: scsi: Drop the ccb typedef
We should not be using typedefs in U-Boot and 'ccb' is a pretty short
name. It is also used with variables. Drop the typedef and use 'struct'
instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
aae5ec3403 dm: scsi: Rename struct SCSI_cmd_block to struct scsi_cmd
This name should be lower case. Also the _block suffix is superfluous.
Rename it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
043682422c dm: scsi: Rearrange header file for driver model
Put the driver-model declarations first since we are migrating to that.
Also drop scsi_init() when driver model is used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
0fcd48fe00 scsi: Move drivers into new drivers/scsi directory
At present we have the SCSI drivers in the drivers/block and common/
directories. It is better to split them out into their own place. Use
drivers/scsi which is what Linux does.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
f2105c6182 sata: Move drivers into new drivers/ata directory
At present we have the SATA and PATA drivers mixed up in the drivers/block
directory. It is better to split them out into their own place. Use
drivers/ata which is what Linux does.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
10e40d54b3 Kconfig: Add CONFIG_SATA to enable SATA
At present CONFIG_CMD_SATA enables the 'sata' command which also brings
in SATA support. Some boards may wish to enable SATA without the command.
Add a separate CONFIG to permit this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
3bf926c0dd Convert CONFIG_CMD_SATA to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_SATA

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
a6fb185c70 scsi: Drop scsi_print_error()
This function is only defined by one driver and is empty. Move it into
the SCSI implementation itself. We could remove it, but it should be
useful for debugging.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
b8beb6b463 scsi: Drop sym53c8xx driver
This driver is for a PowerPC board that will likely be removed soon.
Rather than converting it to driver model, drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
fedb428c5b Convert CONFIG_SCSI to Kconfig
This converts the following to Kconfig:
   CONFIG_SCSI

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
2cce586651 dtoc: Support multiple compatible strings in a node
Sometimes a node will have multiple compatible strings. Drivers may use
one or the other so the best approach seems to be to #define them to be
equivalent.

Update dtoc to support this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-07-11 10:08:19 -06:00
Alison Chaiken
564cf25d5b cmd gpt: test in sandbox
Make minor changes to README.gpt and sandbox_defconfig to support
testing of the gpt command's functionality in the sandbox.

Signed-off-by: Alison Chaiken <alison@peloton-tech.com>
2017-07-11 10:08:19 -06:00
Alison Chaiken
6b20c347a0 sandbox: README: fix partition command invocation
The instructions for creating a disk image that are presently in
README.sandbox fail because sfdisk doesn't know about GPT.

Signed-off-by: Alison Chaiken <alison@peloton-tech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:19 -06:00
Simon Glass
99b66605f0 moveconfig: Support looking for implied CONFIG options
Some CONFIG options can be implied by others and this can help to reduce
the size of the defconfig files. For example, CONFIG_X86 implies
CONFIG_CMD_IRQ, so we can put 'imply CMD_IRQ' under 'config X86' and
all x86 boards will have that option, avoiding adding CONFIG_CMD_IRQ to
each of the x86 defconfig files.

Add a -i option which searches for such options.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2017-07-11 10:08:19 -06:00
Simon Glass
d73fcb12e2 moveconfig: Support building a simple config database
Add a -b option which scans all the defconfigs and builds a database of
all the CONFIG options used by each. This is useful for querying later.

At present this only works with the separate -b option, which does not
move any configs. It would be possible to adjust the script to build the
database automatically when moving configs, but this might not be useful
as the database does not change that often.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:19 -06:00
Simon Glass
f3b8e6470c moveconfig: Add a constant for auto.conf
This filename is used a few times. Move it to a constant before adding
further uses.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:19 -06:00
Simon Glass
ddf91c6423 moveconfig: Tidy up the documentation and add hints
The newest clean-up features are not mentioned in the docs. Fix this and
add a few hints for particular workflows that are hopefully helpful.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:19 -06:00
Simon Glass
ee4e61bda4 moveconfig: Allow reading the defconfig list from stdin
Support passes in a defconfig filename of '-' to read the list from stdin
instead of from a file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:19 -06:00
Simon Glass
25f978cb1c moveconfig: Support providing a path to the defconfig files
It is convenient to provide the full patch to the defconfig files in some
situations, e.g. when the file was generated by a shell command (e.g.
'ls configs/zynq*').

Add support for this, and move the globbing code into a function with its
own documentation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:19 -06:00
Kever Yang
69aaec0bca rockchip: dts: rk3328: add aliases for mmc controller
Add aliases for mmc controller to get a fixed order with
emmc at index 0 and sdmmc at index 1.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:19 -06:00
Simon Glass
95ce385a4a dm: core: Add uclass_first/next_device_check()
Sometimes it is useful to iterate through all devices in a uclass and
skip over those which do not work correctly (e.g fail to probe). Add two
new functions to provide this feature.

The caller must check the return value each time to make sure that the
device is valid. But the device pointer is always returned.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:19 -06:00
Simon Glass
9856157259 dm: core: Test uclass_first/next_device() on probe failure
Add some tests which check the behaviour of uclass_first_device() and
uclass_next_device() when probing of a device fails.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:19 -06:00
Simon Glass
30a570a983 dm: core: Clarify uclass_first/next_device() comments
These are not as clear as they could be. Tidy them up a bit. Also fix a
tiny code-style nit.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-07-11 10:08:19 -06:00
Sjoerd Simons
2454b719fb rockchip: rk3288: Add pinctrl support for the gmac ethernet interface
Add support for the gmac ethernet interface to pinctrl. This hardcodes
the setup to match that of the firefly and Radxa Rock2 boards, using the
RGMII phy mode for gmac interface and GPIO4B0 as the phy reset GPIO.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 15:23:38 +02:00
Kever Yang
cc93c090d0 rockchip: evb-rk3328: enable boot on regulator
Enable all the boot-on regulator in default.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 15:23:38 +02:00
Kever Yang
df813322e5 rockchip: dts: rk3328-evb: add sdmmc-pwren regulator
Use fixed regulator for sdmmc-pwren for sdmmc power.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 15:23:38 +02:00
Kever Yang
fe450895ff rockchip: pinctrl: rk3328: use gpio instead of sdmmc-pwren
SDMMC-PWREN is a pin to control voltage for SDMMC IO, it may
be high active or low active, the dwmmc driver always assume
the sdmmc-pwren as high active.

Kernel treat this pin as fixed regulator instead of a pin from
controller, and then it can set in dts file upon board schematic,
that's a good solution, we can also do this in u-boot.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 15:23:38 +02:00
Wadim Egorov
a84b589e5d doc: rockchip: Add phyCORE-RK3288 RDK to board list
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 15:23:38 +02:00
Wadim Egorov
bafcf2db41 rockchip: Add basic support for phyCORE-RK3288 SoM based carrier board
The phyCORE-RK3288 is a SoM (System on Module) containing a RK3288 SoC.
The module can be connected to different carrier boards.
It can be also equipped with different RAM, SPI flash and eMMC variants.
The Rapid Development Kit option is using the following setup:

  - 1 GB DDR3 RAM (2 Banks)
  - 1x 4 KB EEPROM
  - DP83867 Gigabit Ethernet PHY
  - 16 MB SPI Flash
  - 4 GB eMMC Flash

Add basic support for the PCM-947 carrier board, a RK3288 based development
board made by PHYTEC. This board works in a combination with
the phyCORE-RK3288 System on Module.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 15:23:38 +02:00
Wadim Egorov
ad98f882e8 power: regulator: rk8xx: Allow input current/charger shutdown configuration
The RK818 PMIC contains a charger. Add very basic charger functionality
to be able to regulate the USB input current and charger shutdown limits.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 15:23:38 +02:00
Wadim Egorov
8926c2f584 power: regulator: rk8xx: Build get_ldo_reg only for SPL
Enabling CONFIG_SPL_POWER_SUPPORT will cause a compiler warning:
  ‘get_ldo_reg’ defined but not used [-Wunused-function]

Let's wrap get_ldo_reg(), rk808_ldo and rk818_ldo with ENABLE_DRIVER
which is only set for non SPL builds.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 15:23:37 +02:00
Meng Dongyang
f6f47c2ee1 rockchip: dts: rk3399: control vbus of typec by fixed regulator
Add fixed regulator for the port of typec0 and typec1 to control vbus
instead of gpio.

Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:49 +02:00
Meng Dongyang
863456ade3 rockchip: dts: rk3328: support and enable dwc2
Enable dwc2 controller and add fixed regulator for dwc2 controller to
control vbus.

Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:49 +02:00
Meng Dongyang
c93bef9323 rockchip: rk3328: board: add support of dwc2 gadget
Probe dwc2 udc in the function of board_usb_start to enable
usb gadget function.

Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:49 +02:00
Meng Dongyang
dd22bace7a usb: dwc2: use dev_read_bool() instead of fdt_getprop()
Use dev_read_bool() instead of fdt_getprop() to get the property
from DTS. And add a comment for "hnp-srp-disable" property to
fully describe its effect.

Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:49 +02:00
Meng Dongyang
6424de9303 rockchip: dts: rk3328: add fixed regulator node for xhci
The driver changes gpio to fixed regulator to control vbus, so add
fixed regulator node in DTS for xhci driver.

Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:49 +02:00
Philipp Tomsich
4ac72f5c5b usb: Kconfig: migrate USB_DWC2 to Kconfig
This change migrates the USB_DWC2 configuration item to Kconfig
and runs moveconfig to adjust header files and defconfig.

Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Split off into a separate patch:
Ran moveconfig to migrate other boards:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:49 +02:00
Meng Dongyang
296bd19e4e rockchip: dts: rk3328: add fixed regulator node for xhci
The driver changes gpio to fixed regulator to control vbus, so add
fixed regulator node in DTS for xhci driver.

Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:48 +02:00
Meng Dongyang
26a8b80fac usb: host: xhci-rockchip: use fixed regulator to control vbus
Use fixed regulator to control the voltage of vbus. Enable vbus
supply when usb start and disable vbus supply when usb stop.

Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:48 +02:00
Meng Dongyang
e85f00abda usb: Kconfig: config USB_XHCI_ROCKCHIP depends on DM_REGULATOR and DM_USB
The xhci-rockchip driver depends on DM_REGULATOR and DM_USB.
So add dependent features for xhci-rockchip driver in Kconfig.

Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:48 +02:00
Kever Yang
64a524b08a rockchip: rk3036: sync os_reg2 define with other soc
Rockchip using the same bit definition for dram info and write
to os_reg, the col and bw info is not correct and let's fix it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:48 +02:00
Kever Yang
d59b9dd397 rockchip: rk3036 remove CONFIG_RAM from defconfig
rk3036 sdram driver does not use DM, remove CONFIG_RAM first.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:48 +02:00
eric.gao@rock-chips.com
0c6d52bc4b rockchip: video: mipi: Modify format type for debug message
Modify format type for debug message.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
2017-07-11 12:13:48 +02:00
eric.gao@rock-chips.com
0c9eceb7af rockchip: video: mipi: Modify variable type for arm32 compatibility
Some address relevant varibable is defined originally as u64. To
compatible with arm32, this patch change them to uintptr_t type.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11 12:13:47 +02:00
eric.gao@rock-chips.com
e3ef41df48 rockchip: pwm: fix the register layout for the PWM controller
According to rk3288 spec, the pwm register order is:
    PWM_PWM0_CNT,
    PWM_PWM0_PERIOD_HPR,
    PWM_PWM0_DUTY_LPR,
    PWM_PWM0_CTRL
but the source code's order is:
  struct rk3288_pwm {
    u32 cnt;
    u32 duty_lpr;
    u32 period_hpr;
    u32 ctrl;
  };

So, correct it here. It is the same as RK3399.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Edited the commit message:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:47 +02:00
Kever Yang
419b08012a Revert "mmc: dw_mmc: rockchip: select proper card clock"
The origin patch get rockchip dwmmc by name 'ciu', which lead
to the SPL not able to remove 'clock-names' node in dts.
I'm not saying this is not correct, but I would prefer to handle
this in dts or clock driver to save memory for SPL.
For example the rk3288 SPL size has out of memory if not enable
BACK_TO_BROM option, there are many other SoCs has less internal
memory than rk3288.

This reverts commit 480a9b834c.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:47 +02:00
Kever Yang
d9379b1a89 rockchip: firefly-rk3399: enable dwmmc driver for the board
Enable mmc_dw_rockchip driver, disable CONFIG_SPL_OF_PLATDATA
first for some dependence patches still not merged.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11 12:13:47 +02:00
Kever Yang
522cd58077 rockchip: firefly-rk3399: dts: enable sdmmc device
Enable sdmmc device and add the spl boot device sequence.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:47 +02:00
Kever Yang
8093529809 rockchip: dwmmc: use max-frequency when OF_PLATDATA enabled
Since the 'clock-freq-min-max' is deprecated, we use max-frequency for
all rockchip SoC dwmmc controller.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:47 +02:00
Kever Yang
ebac2cf084 rockchip: rk3328: dtsi use max-frequency for mmc node
Since the 'clock-freq-min-max' is deprecated, we use max-frequency.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:47 +02:00
Kever Yang
16e358ac32 rockchip: rk3288: dtsi use max-frequency for mmc node
Since the 'clock-freq-min-max' is deprecated, we use max-frequency.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:47 +02:00
Kever Yang
3f7a725598 rockchip: rk3036: dtsi use max-frequency for mmc node
Since the 'clock-freq-min-max' is deprecated, we use max-frequency.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:46 +02:00
Kever Yang
b24a8ec15c rockchip: add evb_rk3229 board
evb_rk3229 is a RK3229 based board, with:
- 8GB eMMC;
- 1GB DDR SDRAM;
- 2 USB2.0 HOST port;
- 1 MAC port;
- 1 HDMI port;
- IR;
- WiFi;

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:46 +02:00
Kever Yang
a21e132894 rockchip: rk322x: add sysreset driver
Rockchip rk322x sysreset is much like rk3036 and other Rockchip SoCs,
only difference is that the target register address is different.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:46 +02:00
Kever Yang
168eef7ada rockchip: rk322x: add basic soc support
Enable soc support for SPL and U-boot skeleton.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:46 +02:00
Kever Yang
b647442ce8 rockchip: rk322x: add dts file
The dts files are from kernel and with modify to adapt U-Boot.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:46 +02:00
Kever Yang
5cc9d31a79 rockchip: rk322x: add pinctrl driver
Add init pinctrl driver support for:
- i2c;
- spi;
- uart;
- pwm;
- emmc/sdmmc;

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:46 +02:00
Kever Yang
045029cbd1 rockchip: rk322x: add clock driver
Add clock driver init support for:
- cpu, bus clock init;
- emmc, sdmmc clock;
- ddr clock;

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Fixed format specified (%x -> %p) in clk_rk322x.c:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:45 +02:00
Kever Yang
236776d63f rockchip: mkimage: add support for rk322x soc
Add support for rk322x package header in mkimage tool.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:45 +02:00
Kever Yang
3ee7e68739 rockchip: rv1108: disable CONFIG_RAM before we have driver
The rv1108 do not have DRAM driver now, so disable it first,
or else it will get conflict with the sdram common code.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:45 +02:00
Kever Yang
975e4abad2 rockchip: correct the bank0 ram size
The bank0 ram size should be the DRAM size minus reserved size,
the DRAM size may be 1GB, 2GB, 4GB, we can not hard code it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Added DECLARE_GLOBAL_DATA_PTR for RK3328, RK3368 and RK3399:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:45 +02:00
Kever Yang
c541a7a12a rockchip: dts: rk3368: add dmc node
Add dmc node to enable sdram driver.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:45 +02:00
Kever Yang
8f313328e5 rockchip: dts: rk3328: add dmc node
Add a dmc node for sdram driver.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:45 +02:00
Kever Yang
cc89369fb0 rockchip: rk3368: add sdram driver for U-Boot
Add sdram driver in U-Boot for get the correct sdram size from
sys_reg, so that U-Boot can co-work with Rockchip loader or SPL
to get different dram capability and then tell the kernel.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:45 +02:00
Kever Yang
39648e6167 rockchip: rk3328: add sdram driver in U-Boot
Add sdram driver in U-Boot for get the correct sdram size from
sys_reg, so that U-Boot can co-work with Rockchip loader or SPL
to get different dram capability and then tell the kernel.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:44 +02:00
Kever Yang
7805cdf494 rockchip: use common sdram function
Replace the sdram_init() in board init and rockchip_sdram_size() in
sdram driver for all the Rockchip SoCs which enable CONFIG_RAM.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Make dram_init() in rk3036-board.c conditional on CONFIG_RAM:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:44 +02:00
Kever Yang
6d1970fa8a rockchip: add sdram_common for common functions
There are some functions like sdram_size_mb can be re-used for
different rockchip SoCs, just put them into common file.
Add board_get_usable_ram_top() for ram_top init base on
SDRAM_MAX_SIZE.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Added SDRAM_MAX_SIZE definition for RK3036:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

fixup: 3036 fix for sdram_common
2017-07-11 12:13:44 +02:00
Kever Yang
be8da534e2 rockchip: rk3328: correct mem_region
According to rk3328 TRM:
0~0xff000000 is ddr space;
0xff000000~0xffffffff is device space.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:44 +02:00
Philipp Tomsich
8f1034e627 rockchip: dm: convert fdt_get to dev_read
With the new dev_read functions available, we can convert the rockchip
architecture-specific drivers and common drivers used by these devices
over to the dev_read family of calls.

This covers the DRAM controller initialisation for the RK3188, RK3288
and RK3399... all of these read some of the tuning/setup/timing
parameters from the device-tree.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11 12:13:44 +02:00
Philipp Tomsich
3d40479f00 rockchip: ns16550: dm: convert fdt_get to dev_read
With the new dev_read functions available, we can convert the rockchip
architecture-specific drivers and common drivers used by these devices
over to the dev_read family of calls.

This covers the serial driver (ns16550 and compatible) used for the
Rockchip devices.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11 12:13:44 +02:00
Philipp Tomsich
7ad326a905 rockchip: net: dm: convert fdt_get to dev_read
With the new dev_read functions available, we can convert the rockchip
architecture-specific drivers and common drivers used by these devices
over to the dev_read family of calls.

This covers the Gigabit Ethernet MAC (i.e. common designware driver and
rockchip-specific wrapper).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11 12:13:43 +02:00
Philipp Tomsich
fd1bf8df25 rockchip: mmc: dm: convert fdt_get to dev_read
With the new dev_read functions available, we can convert the rockchip
architecture-specific drivers and common drivers used by these devices
over to the dev_read family of calls.

This covers the dw_mmc and sdhci wrapper drivers for Rockchip.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11 12:13:43 +02:00
Philipp Tomsich
f2708c97c2 rockchip: xhci: dm: convert fdt_get to dev_read
With the new dev_read functions available, we can convert the rockchip
architecture-specific drivers and common drivers used by these devices
over to the dev_read family of calls.

This change covers the USB3 (xhci) driver for the Rockchip devices.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11 12:13:43 +02:00
Philipp Tomsich
6c65577ce6 rockchip: spi: dm: convert fdt_get to dev_read
With the new dev_read functions available, we can convert the rockchip
architecture-specific drivers and common drivers used by these devices
over to the dev_read family of calls.

This change covers the rk_spi.c (SPI driver) used in Rockchip devices.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11 12:13:43 +02:00
Philipp Tomsich
9f4f914d7f rockchip: pinctrl: dm: convert fdt_get to dev_read
With the new dev_read functions available, we can convert the rockchip
architecture-specific drivers and common drivers used by these devices
over to the dev_read family of calls.

This change covers the pinctrl drivers for the Rockchip devices.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11 12:13:43 +02:00
Jean-Jacques Hiblot
6b26aaef08 pipe3: Fix broken dependency
ARCH_OMAP2 has been renamed ARCH_OMAP2PLUS in commit a93fbf4a78
("ARM: omap2+: rename config to ARCH_OMAP2PLUS and consolidate Kconfig")

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:26:05 -04:00
Patrice Chotard
c5c1756c68 mtd: stm32: use parameter instead of default value
To set wait state, a hard coded value is used instead of using
latency parameter. stm32_flash_latency_cfg() is currently used
in arch/arm/mach-stm32/stm32f4/clock.c and in
drivers/clk/clk_stm32f7.c with, in both case, "5" as parameter.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-07-10 14:26:05 -04:00
Andrew F. Davis
9e58d4dbe3 arm: mach-keystone: Modify secure image size before copy
The size of the secure image does not include the size of the
header, subtract this out before we move the image or we grab
extra data after the image.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-07-10 14:26:05 -04:00
Lokesh Vutla
7bdc6947d2 ARM: dts: OMAP5+: Enable gpio in SPL
gpio2 is used to detect lcd based on which pin mux is done in SPL.
gpio7 is used to enable vtt regulator. Enable these two gpio nodes
in SPL.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:26:04 -04:00
Lokesh Vutla
3c9c4a2c50 arm: omap4+: Enable spl_early_init()
Enable spl_early_init() so that spl can use
DT very early during boot.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:26:04 -04:00
Lokesh Vutla
4bd754d8ab arm: omap: Detect boot mode very early
ROM stores the boot params information in a known location
and passes it to SPL. This information needs to be copied
very early during boot or else there is a chance of getting
corrupted by SPL. So move this boot device detection very early
during boot.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:26:04 -04:00
Jorge Ramirez-Ortiz
d754254f20 ARM64: poplar: hi3798cv200: u-boot support for Poplar 96Boards
This port adds support for:
        1) Serial
        2) eMMC
        3) USB

It has been tested with ARM TRUSTED FIRMWARE running u-boot as the
BL33 executable [see board's README]

eMMC has been tested for reading and booting the loader and linux
kernels as well as saving the u-boot environment.

USB has been tested with ASIX networking adapter and SanDisk 7.4GB
drive.

PSCI has been tested via the reset call (PSCI executes from DDR)

The firwmare upgrade process has been tested via TFTP and USB FAT
filesystem containing the fastboot.bin image in one of the partitions.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
2017-07-10 14:26:03 -04:00
Jorge Ramirez-Ortiz
fc50a6cbc0 driver: mmc: update debug info
This driver is used in another board; remove board information from
the driver debug log.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-10 14:26:03 -04:00
Jorge Ramirez-Ortiz
ccaa83f802 ARM64: dts: hi3798cv200-poplar: add device tree bindings
Pulled from Linux 4.12-rc3

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-10 14:26:02 -04:00
Christophe Kerello
bb44b96803 pinctrl: stm32: add set_state ops
set_state_ops is kept under PINCTRL_FULL flag in order
to decrease memory footprint in some configuration.
PINCTRL_FULL can be enabled for debug purpose.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-07-10 14:26:02 -04:00
Christophe Kerello
ad0376e093 pinctrl: stm32: handle a configuration list
This patch handles a configuration list behind pinctrl-0
like pinctrl-0 = <&qspi_clk_a &qspi_bk1_a &qspi_bk2_a>;

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-10 14:26:02 -04:00
Cooper Jr., Franklin
82f40f3e8b defconfig: k2g_evm_defconfig: Add K2G ICE to OF_LIST
Include K2G ICE to OF_LIST so it can be used for runtime board
detection.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:26:01 -04:00
Cooper Jr., Franklin
bc420967be ARM: k2g: Add K2G ICE DTB to the list of possible DTBs
K2G ICE evm will have its own dtb. Therefore, add it to the list of dtbs
located in the appended U-boot dtb FIT image. Therefore, when swapping out
dtbs K2G ICE boards can grab the correct one.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:26:01 -04:00
Cooper Jr., Franklin
6aba890eb6 ARM: dts: k2g: Add DT support for K2G Industrial Communication Engine evm
Add basic DT support for K2G ICE evm. Only minimal peripherals are
supported to allow console output and MMC boot.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:26:01 -04:00
Cooper Jr., Franklin
42468c8b77 ARM: dts: k2g: Disable netcp by default
Disable netcp by default like all other peripherals in the dtsi file.
Enable the peripheral explicitly in the board specific dts file.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:26:00 -04:00
Cooper Jr., Franklin
0d3f97db71 ARM: dts: keystone-k2g-evm: Add unit address to memory node
Upstream Linux has the unit address being added to the various 66AK2Gx
boards dts. Therefore, update the dts to mimic this change.

Also remove memory node from the base K2G dtsi file.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:26:00 -04:00
Cooper Jr., Franklin
df5ec72d7a ARM: dts: keystone-k2g: Remove skeleton.dtsi
Adding the unit address to the memory node was causing the below error:
Warning (reg_format): "reg" property in /memory has invalid length
(8 bytes) (#address-cells == 2, #size-cells == 2)

Further debugging showed that this was due to the memory node added by
default to skeleton.dtsi which was being included in keystone-k2g.dtsi.
Adding a missing node was all that was needed to remove this deprecated
dtsi file from the SoC dtsi. With skeleton.dtsi removed the dtc compiler
no longer complained about including the unit address for the memory node.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:26:00 -04:00
Cooper Jr., Franklin
92761fcc2f ARM: k2g: Update board_name u-boot env variable at runtime
Enable CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG to allow "board_name" to
be set depending on the board it is being ran on.

Update findfdt to use this new dynamic board_name value to determine
which dtb should be used.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:59 -04:00
Cooper Jr., Franklin
4f490402c4 ARM: k2g: Use board detection to wrap K2G GP specific calls
Certain peripherals used by K2G GP aren't used on K2G ICE evm. Or
configuration is slightly different. Therefore, use board detection to
deal with these variations.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:59 -04:00
Cooper Jr., Franklin
e66a5da3f9 board: ks2: Use board detection to wrap code not specific to K2G ICE evm
Some code doesn't apply to K2G ICE evm. Therefore, use board detection to
wrap these calls.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:59 -04:00
Cooper Jr., Franklin
652606eccf ARM: k2g: Add DDR3 configuration for K2G ICE evm
Add configuration settings used by the K2G ICE evm. Also use board
detection to determine which DDR3 configuration to use.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:58 -04:00
Cooper Jr., Franklin
b9b342eaec ARM: k2g: Add pinmux support for K2G ICE evm
Add basic pinmux data for new K2G ICE evm. Also add pinmuxing for a
generic K2G evm which includes I2C 0 and 1 used for board detection
purposes.

Since multiple K2G boards are supported that means initially generic
pinmuxing should be used when board detection hasn't ran. Once board
detection runs the proper pinmuxing can be reran to match the board
being ran on.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:58 -04:00
Cooper Jr., Franklin
e6e2435f39 ks2_evm: Add EEPROM based board detection helper functions
Add a function that can be used to determine if the board being ran on is
a K2G Industrial Communication Engine EVM or K2G General Purpose EVM based
on values programmed on the EEPROM.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:58 -04:00
Cooper Jr., Franklin
e5e546aad1 ARM: k2g: Program DDRPHY_DATX8 registers via mask and value variables
Different K2G evms may need to program the various
KS2_DDRPHY_DATX8_X_OFFSET registers in different ways. Therefore, use
the mask and val registers for each KS2_DDRPHY_DATAX_X_OFFSET to
properly program the register.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:57 -04:00
Cooper Jr., Franklin
a76a6f3e04 ARM: k2g: Program DDR PHY MR2 register with the default value
K2G GP doesn't require the MR2 register to be programed since the
default is good enough. However, newer K2G boards do need to change
this register value. Therefore, instead of not writing this register if
ran on a K2G board just program the value to be written to match the
default/reset value.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:57 -04:00
Cooper Jr., Franklin
f8b4a2d7e2 ARM: keystone2: Add additional fields used for DDR3 configuration
Future boards will need to configure DDR3 registers in a slightly
different manner. Support this by defining additional variables and
defines that will be utilized later.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:56 -04:00
Cooper Jr., Franklin
3107696784 defconfig: keystone2: Enable U-boot runtime DTB detection
Enable various config options to allow U-boot at runtime to select the
proper dtb to use from the list of dtb's within the FIT image.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:56 -04:00
Cooper Jr., Franklin
e820f523d8 ks2_evm: Add EEPROM based board detection
Some K2G evms have their EEPROM programming while most do not. Therefore,
add EEPROM board detection to be used as the default method and fall back
to the alternative board detection when needed.

Also reorder board configuration. Perform bare minimal configuration
initially since board detection hasn't ran. Finish board configuration
once the board has been identified.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:56 -04:00
Cooper Jr., Franklin
7234f215cc ARM: keystone2: Define board_fit_config_name_match for Keystone 2 boards
Now with support for U-boot runtime dtb selection each board needs to
define board_fit_config_name_match so U-boot can determine what the
correct dtb is within the FIT blob.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:55 -04:00
Cooper Jr., Franklin
5f48da9a98 ARM: k2g: Define embedded_dtb_select for runtime DTB selection in U-boot
For K2G, runtime DTB selection utilizes the embedded_dtb_select function.
Therefore, define the function which will perform a EEPROM read and then
retries selecting the correct dtb now that it can detect which board its
on. For other Keystone devices use an empty function since they will still
use the embedded FIT functionality but their FIT will only contain a single
dtb.

Most production K2G boards do not have their EEPROM programmed. Therefore,
perform a test to verify a K2G GP is currently being used and if it is then
set the values normally set by a EEPROM read.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:55 -04:00
Cooper Jr., Franklin
85bfe48b0a ARM: keystone2: Allow to build with all image formats
u-boot.bin is a copy of:
u-boot-fit-dtb.bin if CONFIG_FIT_EMBED is enabled,
u-boot-dtb.bin if CONFIG_OF_SEPARATE is enabled,
u-boot-nodtb.bin if DT is not enabled.
So, use u-boot.bin to to generate keystone images instead of
u-boot-dtb.bin

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:55 -04:00
Cooper Jr., Franklin
6f59fb07f4 Makefile: Build additional binaries for dtb FIT blobs appended to U-boot
Add additional make targets and options for building embedded FIT U-boot
images.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:54 -04:00
Cooper Jr., Franklin
af9e6ad4ab board_f: Add new function to allow runtime DTB selection
Runtime U-boot dtb selection is generally a two step process. First step
is to simply use an initial generic dtb. The second step is to select
the dtb and perhaps execute additional code ones U-boot knows what board
it is running on. Embedded_dtb_select handles the second step by allowing
board specific code to run and perform what ever necessary configuration
that is needed.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:54 -04:00
Cooper Jr., Franklin
80364a42c1 arm: dts: Add new "generic" 66AK2Gx device tree file.
With U-boot runtime board detect for DTB selection a "default" dtb needs
to be created. This will be used temporarily until the "proper" dtb is
selected.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:54 -04:00
Cooper Jr., Franklin
e0f3a3dc4f ARM: dts: k2g: Introduce U-boot specific dtsi file
Introduce K2G evm specific dtsi file for U-boot specific configurations.
This will help seperate U-boot only configurations thus making it easier to
keep device tree files synced between U-boot and Linux.

For now only add nodes to allow i2c drivers to be probed early during
the boot process.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:53 -04:00
Cooper Jr., Franklin
d97974099b dts: Allow OF_LIST to depend on FIT_EMBED
OF_LIST will be useable by SPL and U-boot. Therefore, update its
dependency to allow it to be enable by either SPL or U-boot specific
config option.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Andrew F. Davis <afd@ti.com>
2017-07-10 14:25:53 -04:00
Cooper Jr., Franklin
69e8d4ba7f ti: common: board_detect: Add function to determine if EEPROM was read
When the EEPROM is first read its contents are stored in memory as a
cache to avoid further I2C operations. To determine if the EEPROM was
previously read the easiest way is to check the memory to see if the
EEPROM's magic header value is set. Create a new function that can
determine if the EEPROM was previously read or not without having to
perform a I2C transaction.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:53 -04:00
Cooper Jr., Franklin
2059ecf30f fdt: Enable selecting correct DTB from appended FIT Image
This patch gives U-boot the runtime support to have the board specific
code decide which FDT to use. This is especially useful for devices
that need this type of runtime determination and also doesn't use SPL.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:52 -04:00
Cooper Jr., Franklin
92926bc80c boot_fit: Create helper functions that can be used to select DTB out of FIT
Some platforms may append a FIT image to the U-boot image. This function
aids in parsing the FIT image and selecting the correct DTB at runtime.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:50 -04:00
Cooper Jr., Franklin
3863f840fa spl: fit: Break out some functions into a common file
Some of the functions within spl_fit will be used for non spl purposes.
Instead of duplicating functions simply break the functions to be reused
into its own file.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Only add the new define to image.h, otherwise we see breakage
due to massive include leakage into host tools in some cases]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:24:39 -04:00
Nishanth Menon
e936f997a9 ti: common: board_detect: Allow settings board detection variables manually
In some situations the EEPROM used for board detection may not be
programmed or simply programmed incorrectly. Therefore, it may be
necessary to "simulate" reading the contents of the EEPROM to set
appropriate variables used in the board detection code.

This may also be helpful in certain boot modes where doing i2c reads
may be costly and the config supports running only a specific board.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Franklin S Cooper Jr. <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 13:45:35 -04:00
Cooper Jr., Franklin
a75df9aef0 ARM: dts: keystone-k2e-evm: Add U-boot specific dtsi file
With Davinci I2C switching to device model, K2E requires U-boot specific
device tree entries. This is only required for I2C 1 which is needed
extremely early during the boot process.

Fixes: 1743d040b1 ("ARM: keystone: Enable DM_I2C by default")
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
2017-07-10 13:45:34 -04:00
3422 changed files with 60153 additions and 32421 deletions

1
.gitignore vendored
View File

@@ -30,6 +30,7 @@
#
# Top-level generic files
#
fit-dtb.blob
/MLO*
/SPL*
/System.map

View File

@@ -263,6 +263,15 @@ matrix:
- TEST_PY_BD="sandbox"
BUILDMAN="^sandbox$"
TOOLCHAIN="x86_64"
- env:
- TEST_PY_BD="sandbox_spl"
TEST_PY_TEST_SPEC="test_ofplatdata"
BUILDMAN="^sandbox$"
TOOLCHAIN="x86_64"
- env:
- TEST_PY_BD="sandbox_flattree"
BUILDMAN="^sandbox_flattree$"
TOOLCHAIN="x86_64"
- env:
- TEST_PY_BD="vexpress_ca15_tc2"
TEST_PY_ID="--id qemu"

View File

@@ -0,0 +1,16 @@
NOP PHY driver
This driver is used to stub PHY operations in a driver (USB, SATA).
This is useful when the 'client' driver (USB, SATA, ...) uses the PHY framework
and there is no actual PHY harwdare to drive.
Required properties:
- compatible : must contain "nop-phy"
- #phy-cells : must contain <0>
Example:
nop_phy {
compatible = "nop-phy";
#phy-cells = <0>;
};

View File

@@ -0,0 +1,22 @@
Broadcom STB wake-up Timer
The Broadcom STB wake-up timer provides a 27Mhz resolution timer, with the
ability to wake up the system from low-power suspend/standby modes.
Required properties:
- compatible : should contain "brcm,brcmstb-waketimer"
- reg : the register start and length for the WKTMR block
- interrupts : The TIMER interrupt
- interrupt-parent: The phandle to the Always-On (AON) Power Management (PM) L2
interrupt controller node
- clocks : The phandle to the UPG fixed clock (27Mhz domain)
Example:
waketimer@f0411580 {
compatible = "brcm,brcmstb-waketimer";
reg = <0xf0411580 0x14>;
interrupts = <0x3>;
interrupt-parent = <&aon_pm_l2_intc>;
clocks = <&upg_fixed>;
};

33
Kconfig
View File

@@ -95,6 +95,26 @@ config SYS_MALLOC_F_LEN
particular needs this to operate, so that it can allocate the
initial serial device and any others that are needed.
config SPL_SYS_MALLOC_F_LEN
hex "Size of malloc() pool in SPL before relocation"
depends on SYS_MALLOC_F
default SYS_MALLOC_F_LEN
help
Before relocation, memory is very limited on many platforms. Still,
we can provide a small malloc() pool if needed. Driver model in
particular needs this to operate, so that it can allocate the
initial serial device and any others that are needed.
config TPL_SYS_MALLOC_F_LEN
hex "Size of malloc() pool in TPL before relocation"
depends on SYS_MALLOC_F
default SYS_MALLOC_F_LEN
help
Before relocation, memory is very limited on many platforms. Still,
we can provide a small malloc() pool if needed. Driver model in
particular needs this to operate, so that it can allocate the
initial serial device and any others that are needed.
menuconfig EXPERT
bool "Configure standard U-Boot features (expert users)"
default y
@@ -142,6 +162,13 @@ endmenu # General setup
menu "Boot images"
config ANDROID_BOOT_IMAGE
bool "Enable support for Android Boot Images"
default y if FASTBOOT
help
This enables support for booting images which use the Android
image format header.
config FIT
bool "Support Flattened Image Tree"
select MD5
@@ -325,12 +352,14 @@ config SYS_EXTRA_OPTIONS
config SYS_TEXT_BASE
depends on ARC || X86 || ARCH_UNIPHIER || ARCH_ZYNQMP || \
(M68K && !TARGET_ASTRO_MCF5373L) || MICROBLAZE || MIPS || \
ARCH_ZYNQ || ARCH_KEYSTONE
ARCH_ZYNQ || ARCH_KEYSTONE || ARCH_OMAP2PLUS
depends on !EFI_APP
hex "Text Base"
help
TODO: Move CONFIG_SYS_TEXT_BASE for all the architecture
default 0x80800000 if ARCH_OMAP2PLUS
config SYS_CLK_FREQ
depends on ARC || ARCH_SUNXI
@@ -358,6 +387,8 @@ source "disk/Kconfig"
source "dts/Kconfig"
source "env/Kconfig"
source "net/Kconfig"
source "drivers/Kconfig"

View File

@@ -96,11 +96,11 @@ F: arch/arm/cpu/arm1136/mx*/
F: arch/arm/cpu/arm926ejs/mx*/
F: arch/arm/cpu/armv7/mx*/
F: arch/arm/cpu/armv7/vf610/
F: arch/arm/imx-common/
F: arch/arm/mach-imx/
F: arch/arm/include/asm/arch-imx/
F: arch/arm/include/asm/arch-mx*/
F: arch/arm/include/asm/arch-vf610/
F: arch/arm/include/asm/imx-common/
F: arch/arm/include/asm/mach-imx/
F: board/freescale/*mx*/
ARM HISILICON
@@ -324,12 +324,6 @@ S: Maintained
T: git git://git.denx.de/u-boot-mpc8xx.git
F: arch/powerpc/cpu/mpc8xx/
POWERPC MPC82XX
M: Wolfgang Denk <wd@denx.de>
S: Maintained
T: git git://git.denx.de/u-boot-mpc82xx.git
F: arch/powerpc/cpu/mpc82*/
POWERPC MPC83XX
M: Mario Six <mario.six@gdsys.cc>
S: Maintained
@@ -455,9 +449,12 @@ M: Anatolij Gustschin <agust@denx.de>
S: Maintained
T: git git://git.denx.de/u-boot-video.git
F: drivers/video/
F: common/lcd*.c
F: include/lcd*.h
X86
M: Simon Glass <sjg@chromium.org>
M: Bin Meng <bmeng.cn@gmail.com>
S: Maintained
T: git git://git.denx.de/u-boot-x86.git
F: arch/x86/

View File

@@ -3,7 +3,7 @@
#
VERSION = 2017
PATCHLEVEL = 07
PATCHLEVEL = 09
SUBLEVEL =
EXTRAVERSION =
NAME =
@@ -349,7 +349,7 @@ OBJDUMP = $(CROSS_COMPILE)objdump
AWK = awk
PERL = perl
PYTHON ?= python
DTC = dtc
DTC ?= dtc
CHECK = sparse
CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
@@ -516,6 +516,9 @@ include/config/%.conf: $(KCONFIG_CONFIG) include/config/auto.conf.cmd
@# Otherwise, 'make silentoldconfig' would be invoked twice.
$(Q)touch include/config/auto.conf
u-boot.cfg spl/u-boot.cfg tpl/u-boot.cfg: include/config.h FORCE
$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.autoconf $(@)
-include include/autoconf.mk
-include include/autoconf.mk.dep
@@ -687,6 +690,7 @@ libs-y += drivers/usb/phy/
libs-y += drivers/usb/ulpi/
libs-y += cmd/
libs-y += common/
libs-y += env/
libs-$(CONFIG_API) += api/
libs-$(CONFIG_HAS_POST) += post/
libs-y += test/
@@ -851,7 +855,7 @@ quiet_cmd_cfgcheck = CFGCHK $2
cmd_cfgcheck = $(srctree)/scripts/check-config.sh $2 \
$(srctree)/scripts/config_whitelist.txt $(srctree)
all: $(ALL-y)
all: $(ALL-y) cfg
ifeq ($(CONFIG_DM_I2C_COMPAT)$(CONFIG_SANDBOX),y)
@echo "===================== WARNING ======================"
@echo "This board uses CONFIG_DM_I2C_COMPAT. Please remove"
@@ -873,7 +877,21 @@ dts/dt.dtb: checkdtc u-boot
quiet_cmd_copy = COPY $@
cmd_copy = cp $< $@
ifeq ($(CONFIG_OF_SEPARATE),y)
ifeq ($(CONFIG_FIT_EMBED),y)
fit-dtb.blob: dts/dt.dtb FORCE
$(call if_changed,mkimage)
MKIMAGEFLAGS_fit-dtb.blob = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
-a 0 -e 0 -E \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) -d /dev/null
u-boot-fit-dtb.bin: u-boot-nodtb.bin fit-dtb.blob
$(call if_changed,cat)
u-boot.bin: u-boot-fit-dtb.bin FORCE
$(call if_changed,copy)
else ifeq ($(CONFIG_OF_SEPARATE),y)
u-boot-dtb.bin: u-boot-nodtb.bin dts/dt.dtb FORCE
$(call if_changed,cat)
@@ -885,7 +903,7 @@ u-boot.bin: u-boot-nodtb.bin FORCE
endif
%.imx: %.bin
$(Q)$(MAKE) $(build)=arch/arm/imx-common $@
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
%.vyb: %.imx
$(Q)$(MAKE) $(build)=arch/arm/cpu/armv7/vf610 $@
@@ -1050,10 +1068,10 @@ tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE
$(call if_changed,pad_cat)
SPL: spl/u-boot-spl.bin FORCE
$(Q)$(MAKE) $(build)=arch/arm/imx-common $@
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL u-boot.bin FORCE
$(Q)$(MAKE) $(build)=arch/arm/imx-common $@
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
MKIMAGEFLAGS_u-boot.ubl = -n $(UBL_CONFIG) -T ublimage -e $(CONFIG_SYS_TEXT_BASE)
@@ -1215,13 +1233,16 @@ u-boot.elf: u-boot.bin
$(Q)$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< u-boot-elf.o
$(call if_changed,u-boot-elf)
ARCH_POSTLINK := $(wildcard $(srctree)/arch/$(ARCH)/Makefile.postlink)
# Rule to link u-boot
# May be overridden by arch/$(ARCH)/config.mk
quiet_cmd_u-boot__ ?= LD $@
cmd_u-boot__ ?= $(LD) $(LDFLAGS) $(LDFLAGS_u-boot) -o $@ \
-T u-boot.lds $(u-boot-init) \
--start-group $(u-boot-main) --end-group \
$(PLATFORM_LIBS) -Map u-boot.map
$(PLATFORM_LIBS) -Map u-boot.map; \
$(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true)
quiet_cmd_smap = GEN common/system_map.o
cmd_smap = \
@@ -1231,7 +1252,7 @@ cmd_smap = \
-c $(srctree)/common/system_map.c -o common/system_map.o
u-boot: $(u-boot-init) $(u-boot-main) u-boot.lds FORCE
$(call if_changed,u-boot__)
+$(call if_changed,u-boot__)
ifeq ($(CONFIG_KALLSYMS),y)
$(call cmd,smap)
$(call cmd,u-boot__) common/system_map.o
@@ -1338,6 +1359,7 @@ define filechk_timestamp.h
LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TIME "%T"'; \
LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TZ "%z"'; \
LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \
LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \
else \
return 42; \
fi; \
@@ -1346,6 +1368,7 @@ define filechk_timestamp.h
LC_ALL=C date +'#define U_BOOT_TIME "%T"'; \
LC_ALL=C date +'#define U_BOOT_TZ "%z"'; \
LC_ALL=C date +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \
LC_ALL=C date +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \
fi)
endef
@@ -1356,7 +1379,7 @@ $(timestamp_h): $(srctree)/Makefile FORCE
$(call filechk,timestamp.h)
checkbinman: tools
@if ! ( echo 'import libfdt' | ( PYTHONPATH=tools python )); then \
@if ! ( echo 'import libfdt' | ( PYTHONPATH=tools $(PYTHON) )); then \
echo >&2; \
echo >&2 '*** binman needs the Python libfdt library.'; \
echo >&2 '*** Either install it on your system, or try:'; \
@@ -1378,7 +1401,8 @@ u-boot.lds: $(LDSCRIPT) prepare FORCE
spl/u-boot-spl.bin: spl/u-boot-spl
@:
spl/u-boot-spl: tools prepare \
$(if $(CONFIG_OF_SEPARATE)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb)
$(if $(CONFIG_OF_SEPARATE)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb) \
$(if $(CONFIG_OF_SEPARATE)$(CONFIG_TPL_OF_PLATDATA),dts/dt.dtb)
$(Q)$(MAKE) obj=spl -f $(srctree)/scripts/Makefile.spl all
spl/sunxi-spl.bin: spl/u-boot-spl
@@ -1441,14 +1465,14 @@ checkarmreloc: u-boot
false; \
fi
env: scripts_basic
$(Q)$(MAKE) $(build)=tools/$@
envtools: scripts_basic
$(Q)$(MAKE) $(build)=tools/env
tools-only: scripts_basic $(version_h) $(timestamp_h)
$(Q)$(MAKE) $(build)=tools
tools-all: export HOST_TOOLS_ALL=y
tools-all: env tools ;
tools-all: envtools tools ;
cross_tools: export CROSS_BUILD_TOOLS=y
cross_tools: tools ;
@@ -1473,7 +1497,7 @@ CLEAN_DIRS += $(MODVERDIR) \
$(filter-out include, $(shell ls -1 $d 2>/dev/null))))
CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \
boot* u-boot* MLO* SPL System.map
boot* u-boot* MLO* SPL System.map fit-dtb.blob
# Directories & files removed with 'make mrproper'
MRPROPER_DIRS += include/config include/generated spl tpl \
@@ -1562,6 +1586,7 @@ help:
@echo ' ubootrelease - Output the release version string (use with make -s)'
@echo ' ubootversion - Output the version stored in Makefile (use with make -s)'
@echo " cfg - Don't build, just create the .cfg files"
@echo " envtools - Build only the target-side environment tools"
@echo ''
@echo 'Static analysers'
@echo ' checkstack - Generate a list of stack hogs'

591
README
View File

@@ -404,12 +404,6 @@ The following options need to be configured:
supported, core will start to execute uboot when wakes up.
- Generic CPU options:
CONFIG_SYS_GENERIC_GLOBAL_DATA
Defines global data is initialized in generic board board_init_f().
If this macro is defined, global data is created and cleared in
generic board board_init_f(). Without this macro, architecture/board
should initialize global data before calling board_init_f().
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
Defines the endianess of the CPU. Implementation of those
@@ -699,11 +693,6 @@ The following options need to be configured:
when no character is read on the console interface
within "Boot Delay" after reset.
CONFIG_BOOTARGS
This can be used to pass arguments to the bootm
command. The value of CONFIG_BOOTARGS goes into the
environment value "bootargs".
CONFIG_RAMBOOT and CONFIG_NFSBOOT
The value of these goes into the environment as
"ramboot" and "nfsboot" respectively, and can be used
@@ -756,114 +745,6 @@ The following options need to be configured:
Select one of the baudrates listed in
CONFIG_SYS_BAUDRATE_TABLE, see below.
- Monitor Functions:
Monitor commands can be included or excluded
from the build by using the #include files
<config_cmd_all.h> and #undef'ing unwanted
commands, or adding #define's for wanted commands.
The default command configuration includes all commands
except those marked below with a "*".
CONFIG_CMD_AES AES 128 CBC encrypt/decrypt
CONFIG_CMD_ASKENV * ask for env variable
CONFIG_CMD_BDI bdinfo
CONFIG_CMD_BOOTD bootd
CONFIG_CMD_BOOTI * ARM64 Linux kernel Image support
CONFIG_CMD_CACHE * icache, dcache
CONFIG_CMD_CONSOLE coninfo
CONFIG_CMD_DHCP * DHCP support
CONFIG_CMD_DIAG * Diagnostics
CONFIG_CMD_ECHO echo arguments
CONFIG_CMD_EDITENV edit env variable
CONFIG_CMD_ELF * bootelf, bootvx
CONFIG_CMD_ENV_EXISTS * check existence of env variable
CONFIG_CMD_EXPORTENV * export the environment
CONFIG_CMD_EXT2 * ext2 command support
CONFIG_CMD_EXT4 * ext4 command support
CONFIG_CMD_FS_GENERIC * filesystem commands (e.g. load, ls)
that work for multiple fs types
CONFIG_CMD_FS_UUID * Look up a filesystem UUID
CONFIG_CMD_SAVEENV saveenv
CONFIG_CMD_FLASH flinfo, erase, protect
CONFIG_CMD_FPGA FPGA device initialization support
CONFIG_CMD_GO * the 'go' command (exec code)
CONFIG_CMD_GREPENV * search environment
CONFIG_CMD_I2C * I2C serial bus support
CONFIG_CMD_IMI iminfo
CONFIG_CMD_IMLS List all images found in NOR flash
CONFIG_CMD_IMLS_NAND * List all images found in NAND flash
CONFIG_CMD_IMPORTENV * import an environment
CONFIG_CMD_INI * import data from an ini file into the env
CONFIG_CMD_ITEST Integer/string test of 2 values
CONFIG_CMD_LDRINFO * ldrinfo (display Blackfin loader)
CONFIG_CMD_LINK_LOCAL * link-local IP address auto-configuration
(169.254.*.*)
CONFIG_CMD_LOADB loadb
CONFIG_CMD_LOADS loads
CONFIG_CMD_MD5SUM * print md5 message digest
(requires CONFIG_CMD_MEMORY and CONFIG_MD5)
CONFIG_CMD_MEMINFO * Display detailed memory information
CONFIG_CMD_MEMORY md, mm, nm, mw, cp, cmp, crc, base,
loop, loopw
CONFIG_CMD_MEMTEST * mtest
CONFIG_CMD_MISC Misc functions like sleep etc
CONFIG_CMD_MMC * MMC memory mapped support
CONFIG_CMD_MII * MII utility commands
CONFIG_CMD_MTDPARTS * MTD partition support
CONFIG_CMD_NAND * NAND support
CONFIG_CMD_NET bootp, tftpboot, rarpboot
CONFIG_CMD_NFS NFS support
CONFIG_CMD_PCA953X * PCA953x I2C gpio commands
CONFIG_CMD_PCA953X_INFO * PCA953x I2C gpio info command
CONFIG_CMD_PCI * pciinfo
CONFIG_CMD_PCMCIA * PCMCIA support
CONFIG_CMD_PING * send ICMP ECHO_REQUEST to network
host
CONFIG_CMD_PORTIO * Port I/O
CONFIG_CMD_READ * Read raw data from partition
CONFIG_CMD_REGINFO * Register dump
CONFIG_CMD_RUN run command in env variable
CONFIG_CMD_SANDBOX * sb command to access sandbox features
CONFIG_CMD_SAVES * save S record dump
CONFIG_SCSI * SCSI Support
CONFIG_CMD_SDRAM * print SDRAM configuration information
(requires CONFIG_CMD_I2C)
CONFIG_CMD_SF * Read/write/erase SPI NOR flash
CONFIG_CMD_SOFTSWITCH * Soft switch setting command for BF60x
CONFIG_CMD_SOURCE "source" command Support
CONFIG_CMD_SPI * SPI serial bus support
CONFIG_CMD_TFTPSRV * TFTP transfer in server mode
CONFIG_CMD_TFTPPUT * TFTP put command (upload)
CONFIG_CMD_TIME * run command and report execution time (ARM specific)
CONFIG_CMD_TIMER * access to the system tick timer
CONFIG_CMD_USB * USB support
CONFIG_CMD_CDP * Cisco Discover Protocol support
CONFIG_CMD_MFSL * Microblaze FSL support
CONFIG_CMD_XIMG Load part of Multi Image
CONFIG_CMD_UUID * Generate random UUID or GUID string
EXAMPLE: If you want all functions except of network
support you can write:
#include "config_cmd_all.h"
#undef CONFIG_CMD_NET
Other Commands:
fdt (flattened device tree) command: CONFIG_OF_LIBFDT
Note: Don't enable the "icache" and "dcache" commands
(configuration option CONFIG_CMD_CACHE) unless you know
what you (and your U-Boot users) are doing. Data
cache cannot be enabled on systems like the
8xx (where accesses to the IMMR region must be
uncached), and it cannot be disabled on all other
systems where we (mis-) use the data cache to hold an
initial stack and some data.
XXX - this list needs to get updated!
- Removal of commands
If no commands are needed to boot, you can disable
CONFIG_CMDLINE to remove them. In this case, the command line
@@ -895,7 +776,7 @@ The following options need to be configured:
binary in its image. This device tree file should be in the
board directory and called <soc>-<board>.dts. The binary file
is then picked up in board_init_f() and made available through
the global data structure as gd->blob.
the global data structure as gd->fdt_blob.
CONFIG_OF_SEPARATE
If this variable is defined, U-Boot will build a device tree
@@ -1043,16 +924,11 @@ The following options need to be configured:
Default is 32bit.
- SCSI Support:
At the moment only there is only support for the
SYM53C8XX SCSI controller; define
CONFIG_SCSI_SYM53C8XX to enable it.
CONFIG_SYS_SCSI_MAX_LUN [8], CONFIG_SYS_SCSI_MAX_SCSI_ID [7] and
CONFIG_SYS_SCSI_MAX_DEVICE [CONFIG_SYS_SCSI_MAX_SCSI_ID *
CONFIG_SYS_SCSI_MAX_LUN] can be adjusted to define the
maximum numbers of LUNs, SCSI ID's and target
devices.
CONFIG_SYS_SCSI_SYM53C8XX_CCF to fix clock timing (80Mhz)
The environment variable 'scsidevs' is set to the number of
SCSI devices found during the last scan.
@@ -1070,10 +946,6 @@ The following options need to be configured:
Allow generic access to the SPI bus on the Intel 8257x, for
example with the "sspi" command.
CONFIG_CMD_E1000
Management command for E1000 devices. When used on devices
with SPI support you can reprogram the EEPROM from U-Boot.
CONFIG_EEPRO100
Support for Intel 82557/82559/82559ER chips.
Optional CONFIG_EEPRO100_SROM_WRITE enables EEPROM
@@ -1208,11 +1080,6 @@ The following options need to be configured:
to. Contemporary x86 systems usually map it at
0xfed40000.
CONFIG_CMD_TPM
Add tpm monitor functions.
Requires CONFIG_TPM. If CONFIG_TPM_AUTH_SESSIONS is set, also
provides monitor access to authorized functions.
CONFIG_TPM
Define this to enable the TPM support library which provides
functional interfaces to some TPM commands.
@@ -1340,12 +1207,6 @@ The following options need to be configured:
CONFIG_USB_FUNCTION_DFU
This enables the USB portion of the DFU USB class
CONFIG_CMD_DFU
This enables the command "dfu" which is used to have
U-Boot create a DFU class device via USB. This command
requires that the "dfu_alt_info" environment variable be
set and define the alt settings to expose to the host.
CONFIG_DFU_MMC
This enables support for exposing (e)MMC devices via DFU.
@@ -1381,57 +1242,6 @@ The following options need to be configured:
entering dfuMANIFEST state. Host waits this timeout, before
sending again an USB request to the device.
- USB Device Android Fastboot support:
CONFIG_USB_FUNCTION_FASTBOOT
This enables the USB part of the fastboot gadget
CONFIG_CMD_FASTBOOT
This enables the command "fastboot" which enables the Android
fastboot mode for the platform's USB device. Fastboot is a USB
protocol for downloading images, flashing and device control
used on Android devices.
See doc/README.android-fastboot for more information.
CONFIG_ANDROID_BOOT_IMAGE
This enables support for booting images which use the Android
image format header.
CONFIG_FASTBOOT_BUF_ADDR
The fastboot protocol requires a large memory buffer for
downloads. Define this to the starting RAM address to use for
downloaded images.
CONFIG_FASTBOOT_BUF_SIZE
The fastboot protocol requires a large memory buffer for
downloads. This buffer should be as large as possible for a
platform. Define this to the size available RAM for fastboot.
CONFIG_FASTBOOT_FLASH
The fastboot protocol includes a "flash" command for writing
the downloaded image to a non-volatile storage device. Define
this to enable the "fastboot flash" command.
CONFIG_FASTBOOT_FLASH_MMC_DEV
The fastboot "flash" command requires additional information
regarding the non-volatile storage device. Define this to
the eMMC device that fastboot should use to store the image.
CONFIG_FASTBOOT_GPT_NAME
The fastboot "flash" command supports writing the downloaded
image to the Protective MBR and the Primary GUID Partition
Table. (Additionally, this downloaded image is post-processed
to generate and write the Backup GUID Partition Table.)
This occurs when the specified "partition name" on the
"fastboot flash" command line matches this value.
The default is "gpt" if undefined.
CONFIG_FASTBOOT_MBR_NAME
The fastboot "flash" command supports writing the downloaded
image to DOS MBR.
This occurs when the "partition name" specified on the
"fastboot flash" command line matches this value.
If not defined the default value "mbr" is used.
- Journaling Flash filesystem support:
CONFIG_JFFS2_NAND
Define these for a default partition on a NAND device
@@ -1626,11 +1436,6 @@ The following options need to be configured:
the malloc area (as defined by CONFIG_SYS_MALLOC_LEN) should
be at least 4MB.
CONFIG_LZO
If this option is set, support for LZO compressed images
is included.
- MII/PHY support:
CONFIG_PHY_ADDR
@@ -1640,11 +1445,6 @@ The following options need to be configured:
The clock frequency of the MII bus
CONFIG_PHY_GIGE
If this option is set, support for speed/duplex
detection of gigabit PHY is included.
CONFIG_PHY_RESET_DELAY
Some PHY like Intel LXT971A need extra delay after
@@ -2507,12 +2307,7 @@ The following options need to be configured:
commands cp, md...
- Serial Flash support
CONFIG_CMD_SF
Defining this option enables SPI flash commands
'sf probe/read/write/erase/update'.
Usage requires an initial 'probe' to define the serial
Usage requires an initial 'sf probe' to define the serial
flash parameters, followed by read/write/erase/update
commands.
@@ -2525,12 +2320,6 @@ The following options need to be configured:
CONFIG_SF_DEFAULT_MODE (see include/spi.h)
CONFIG_SF_DEFAULT_SPEED in Hz
CONFIG_CMD_SF_TEST
Define this option to include a destructive SPI flash
test ('sf test').
- SystemACE Support:
CONFIG_SYSTEMACE
Adding this option adds support for Xilinx SystemACE
@@ -2802,13 +2591,6 @@ FIT uImage format:
kernel. Needed for UBI support.
- UBI support
CONFIG_CMD_UBI
Adds commands for interacting with MTD partitions formatted
with the UBI flash translation layer
Requires also defining CONFIG_RBTREE
CONFIG_UBI_SILENCE_MSG
Make the verbose messages from UBI stop printing. This leaves
@@ -2877,13 +2659,6 @@ FIT uImage format:
default: 0
- UBIFS support
CONFIG_CMD_UBIFS
Adds commands for interacting with UBI volumes formatted as
UBIFS. UBIFS is read-only in u-boot.
Requires UBI support as well as CONFIG_LZO
CONFIG_UBIFS_SILENCE_MSG
Make the verbose messages from UBIFS stop printing. This leaves
@@ -3060,10 +2835,6 @@ FIT uImage format:
Define this if you need to first read the OOB and then the
data. This is used, for example, on davinci platforms.
CONFIG_SPL_OMAP3_ID_NAND
Support for an OMAP3-specific set of functions to return the
ID and MFR of the first attached NAND chip, if present.
CONFIG_SPL_RAM_DEVICE
Support for running image already present in ram, in SPL binary
@@ -3438,90 +3209,6 @@ following configurations:
Builds up envcrc with the target environment so that external utils
may easily extract it and embed it in final U-Boot images.
- CONFIG_ENV_IS_IN_FLASH:
Define this if the environment is in flash memory.
a) The environment occupies one whole flash sector, which is
"embedded" in the text segment with the U-Boot code. This
happens usually with "bottom boot sector" or "top boot
sector" type flash chips, which have several smaller
sectors at the start or the end. For instance, such a
layout can have sector sizes of 8, 2x4, 16, Nx32 kB. In
such a case you would place the environment in one of the
4 kB sectors - with U-Boot code before and after it. With
"top boot sector" type flash chips, you would put the
environment in one of the last sectors, leaving a gap
between U-Boot and the environment.
- CONFIG_ENV_OFFSET:
Offset of environment data (variable area) to the
beginning of flash memory; for instance, with bottom boot
type flash chips the second sector can be used: the offset
for this sector is given here.
CONFIG_ENV_OFFSET is used relative to CONFIG_SYS_FLASH_BASE.
- CONFIG_ENV_ADDR:
This is just another way to specify the start address of
the flash sector containing the environment (instead of
CONFIG_ENV_OFFSET).
- CONFIG_ENV_SECT_SIZE:
Size of the sector containing the environment.
b) Sometimes flash chips have few, equal sized, BIG sectors.
In such a case you don't want to spend a whole sector for
the environment.
- CONFIG_ENV_SIZE:
If you use this in combination with CONFIG_ENV_IS_IN_FLASH
and CONFIG_ENV_SECT_SIZE, you can specify to use only a part
of this flash sector for the environment. This saves
memory for the RAM copy of the environment.
It may also save flash memory if you decide to use this
when your environment is "embedded" within U-Boot code,
since then the remainder of the flash sector could be used
for U-Boot code. It should be pointed out that this is
STRONGLY DISCOURAGED from a robustness point of view:
updating the environment in flash makes it always
necessary to erase the WHOLE sector. If something goes
wrong before the contents has been restored from a copy in
RAM, your target system will be dead.
- CONFIG_ENV_ADDR_REDUND
CONFIG_ENV_SIZE_REDUND
These settings describe a second storage area used to hold
a redundant copy of the environment data, so that there is
a valid backup copy in case there is a power failure during
a "saveenv" operation.
BE CAREFUL! Any changes to the flash layout, and some changes to the
source code will make it necessary to adapt <board>/u-boot.lds*
accordingly!
- CONFIG_ENV_IS_IN_NVRAM:
Define this if you have some non-volatile memory device
(NVRAM, battery buffered SRAM) which you want to use for the
environment.
- CONFIG_ENV_ADDR:
- CONFIG_ENV_SIZE:
These two #defines are used to determine the memory area you
want to use for environment. It is assumed that this memory
can just be read and written to, without any special
provision.
BE CAREFUL! The first access to the environment happens quite early
in U-Boot initialization (when we try to get the setting of for the
console baudrate). You *MUST* have mapped your NVRAM area then, or
@@ -3532,288 +3219,20 @@ environment in RAM: we could work on NVRAM directly, but we want to
keep settings there always unmodified except somebody uses "saveenv"
to save the current settings.
- CONFIG_ENV_IS_IN_EEPROM:
Use this if you have an EEPROM or similar serial access
device and a driver for it.
- CONFIG_ENV_OFFSET:
- CONFIG_ENV_SIZE:
These two #defines specify the offset and size of the
environment area within the total memory of your EEPROM.
- CONFIG_SYS_I2C_EEPROM_ADDR:
If defined, specified the chip address of the EEPROM device.
The default address is zero.
- CONFIG_SYS_I2C_EEPROM_BUS:
If defined, specified the i2c bus of the EEPROM device.
- CONFIG_SYS_EEPROM_PAGE_WRITE_BITS:
If defined, the number of bits used to address bytes in a
single page in the EEPROM device. A 64 byte page, for example
would require six bits.
- CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS:
If defined, the number of milliseconds to delay between
page writes. The default is zero milliseconds.
- CONFIG_SYS_I2C_EEPROM_ADDR_LEN:
The length in bytes of the EEPROM memory array address. Note
that this is NOT the chip address length!
- CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW:
EEPROM chips that implement "address overflow" are ones
like Catalyst 24WC04/08/16 which has 9/10/11 bits of
address and the extra bits end up in the "chip address" bit
slots. This makes a 24WC08 (1Kbyte) chip look like four 256
byte chips.
Note that we consider the length of the address field to
still be one byte because the extra address bits are hidden
in the chip address.
- CONFIG_SYS_EEPROM_SIZE:
The size in bytes of the EEPROM device.
- CONFIG_ENV_EEPROM_IS_ON_I2C
define this, if you have I2C and SPI activated, and your
EEPROM, which holds the environment, is on the I2C bus.
- CONFIG_I2C_ENV_EEPROM_BUS
if you have an Environment on an EEPROM reached over
I2C muxes, you can define here, how to reach this
EEPROM. For example:
#define CONFIG_I2C_ENV_EEPROM_BUS 1
EEPROM which holds the environment, is reached over
a pca9547 i2c mux with address 0x70, channel 3.
- CONFIG_ENV_IS_IN_DATAFLASH:
Define this if you have a DataFlash memory device which you
want to use for the environment.
- CONFIG_ENV_OFFSET:
- CONFIG_ENV_ADDR:
- CONFIG_ENV_SIZE:
These three #defines specify the offset and size of the
environment area within the total memory of your DataFlash placed
at the specified address.
- CONFIG_ENV_IS_IN_SPI_FLASH:
Define this if you have a SPI Flash memory device which you
want to use for the environment.
- CONFIG_ENV_OFFSET:
- CONFIG_ENV_SIZE:
These two #defines specify the offset and size of the
environment area within the SPI Flash. CONFIG_ENV_OFFSET must be
aligned to an erase sector boundary.
- CONFIG_ENV_SECT_SIZE:
Define the SPI flash's sector size.
- CONFIG_ENV_OFFSET_REDUND (optional):
This setting describes a second storage area of CONFIG_ENV_SIZE
size used to hold a redundant copy of the environment data, so
that there is a valid backup copy in case there is a power failure
during a "saveenv" operation. CONFIG_ENV_OFFSET_REDUND must be
aligned to an erase sector boundary.
- CONFIG_ENV_SPI_BUS (optional):
- CONFIG_ENV_SPI_CS (optional):
Define the SPI bus and chip select. If not defined they will be 0.
- CONFIG_ENV_SPI_MAX_HZ (optional):
Define the SPI max work clock. If not defined then use 1MHz.
- CONFIG_ENV_SPI_MODE (optional):
Define the SPI work mode. If not defined then use SPI_MODE_3.
- CONFIG_ENV_IS_IN_REMOTE:
Define this if you have a remote memory space which you
want to use for the local device's environment.
- CONFIG_ENV_ADDR:
- CONFIG_ENV_SIZE:
These two #defines specify the address and size of the
environment area within the remote memory space. The
local device can get the environment from remote memory
space by SRIO or PCIE links.
BE CAREFUL! For some special cases, the local device can not use
"saveenv" command. For example, the local device will get the
environment stored in a remote NOR flash by SRIO or PCIE link,
but it can not erase, write this NOR flash by SRIO or PCIE interface.
- CONFIG_ENV_IS_IN_NAND:
Define this if you have a NAND device which you want to use
for the environment.
- CONFIG_ENV_OFFSET:
- CONFIG_ENV_SIZE:
These two #defines specify the offset and size of the environment
area within the first NAND device. CONFIG_ENV_OFFSET must be
aligned to an erase block boundary.
- CONFIG_ENV_OFFSET_REDUND (optional):
This setting describes a second storage area of CONFIG_ENV_SIZE
size used to hold a redundant copy of the environment data, so
that there is a valid backup copy in case there is a power failure
during a "saveenv" operation. CONFIG_ENV_OFFSET_REDUND must be
aligned to an erase block boundary.
- CONFIG_ENV_RANGE (optional):
Specifies the length of the region in which the environment
can be written. This should be a multiple of the NAND device's
block size. Specifying a range with more erase blocks than
are needed to hold CONFIG_ENV_SIZE allows bad blocks within
the range to be avoided.
- CONFIG_ENV_OFFSET_OOB (optional):
Enables support for dynamically retrieving the offset of the
environment from block zero's out-of-band data. The
"nand env.oob" command can be used to record this offset.
Currently, CONFIG_ENV_OFFSET_REDUND is not supported when
using CONFIG_ENV_OFFSET_OOB.
- CONFIG_NAND_ENV_DST
Defines address in RAM to which the nand_spl code should copy the
environment. If redundant environment is used, it will be copied to
CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE.
- CONFIG_ENV_IS_IN_UBI:
Define this if you have an UBI volume that you want to use for the
environment. This has the benefit of wear-leveling the environment
accesses, which is important on NAND.
- CONFIG_ENV_UBI_PART:
Define this to a string that is the mtd partition containing the UBI.
- CONFIG_ENV_UBI_VOLUME:
Define this to the name of the volume that you want to store the
environment in.
- CONFIG_ENV_UBI_VOLUME_REDUND:
Define this to the name of another volume to store a second copy of
the environment in. This will enable redundant environments in UBI.
It is assumed that both volumes are in the same MTD partition.
- CONFIG_UBI_SILENCE_MSG
- CONFIG_UBIFS_SILENCE_MSG
You will probably want to define these to avoid a really noisy system
when storing the env in UBI.
- CONFIG_ENV_IS_IN_FAT:
Define this if you want to use the FAT file system for the environment.
- FAT_ENV_INTERFACE:
Define this to a string that is the name of the block device.
- FAT_ENV_DEVICE_AND_PART:
Define this to a string to specify the partition of the device. It can
be as following:
"D:P", "D:0", "D", "D:" or "D:auto" (D, P are integers. And P >= 1)
- "D:P": device D partition P. Error occurs if device D has no
partition table.
- "D:0": device D.
- "D" or "D:": device D partition 1 if device D has partition
table, or the whole device D if has no partition
table.
- "D:auto": first partition in device D with bootable flag set.
If none, first valid partition in device D. If no
partition table then means device D.
- FAT_ENV_FILE:
It's a string of the FAT file name. This file use to store the
environment.
- CONFIG_FAT_WRITE:
This must be enabled. Otherwise it cannot save the environment file.
- CONFIG_ENV_IS_IN_MMC:
Define this if you have an MMC device which you want to use for the
environment.
- CONFIG_SYS_MMC_ENV_DEV:
Specifies which MMC device the environment is stored in.
- CONFIG_SYS_MMC_ENV_PART (optional):
Specifies which MMC partition the environment is stored in. If not
set, defaults to partition 0, the user area. Common values might be
1 (first MMC boot partition), 2 (second MMC boot partition).
- CONFIG_ENV_OFFSET:
- CONFIG_ENV_SIZE:
These two #defines specify the offset and size of the environment
area within the specified MMC device.
If offset is positive (the usual case), it is treated as relative to
the start of the MMC partition. If offset is negative, it is treated
as relative to the end of the MMC partition. This can be useful if
your board may be fitted with different MMC devices, which have
different sizes for the MMC partitions, and you always want the
environment placed at the very end of the partition, to leave the
maximum possible space before it, to store other data.
These two values are in units of bytes, but must be aligned to an
MMC sector boundary.
- CONFIG_ENV_OFFSET_REDUND (optional):
Specifies a second storage area, of CONFIG_ENV_SIZE size, used to
hold a redundant copy of the environment data. This provides a
valid backup copy in case the other copy is corrupted, e.g. due
to a power failure during a "saveenv" operation.
This value may also be positive or negative; this is handled in the
same way as CONFIG_ENV_OFFSET.
This value is also in units of bytes, but must also be aligned to
an MMC sector boundary.
- CONFIG_ENV_SIZE_REDUND (optional):
This value need not be set, even when CONFIG_ENV_OFFSET_REDUND is
set. If this value is set, it must be set to the same value as
CONFIG_ENV_SIZE.
Please note that the environment is read-only until the monitor
has been relocated to RAM and a RAM copy of the environment has been
created; also, when using EEPROM you will have to use getenv_f()
created; also, when using EEPROM you will have to use env_get_f()
until then to read environment variables.
The environment is protected by a CRC32 checksum. Before the monitor
@@ -4077,7 +3496,7 @@ Low Level (hardware related) configuration options:
- CONFIG_LOOPW
Add the "loopw" memory command. This only takes effect if
the memory commands are activated globally (CONFIG_CMD_MEM).
the memory commands are activated globally (CONFIG_CMD_MEMORY).
- CONFIG_MX_CYCLIC
Add the "mdc" and "mwc" memory commands. These are cyclic
@@ -4091,7 +3510,7 @@ Low Level (hardware related) configuration options:
This command will write 12345678 to address 100 all 10 ms.
This only takes effect if the memory commands are activated
globally (CONFIG_CMD_MEM).
globally (CONFIG_CMD_MEMORY).
- CONFIG_SKIP_LOWLEVEL_INIT
[ARM, NDS32, MIPS only] If this variable is defined, then certain

View File

@@ -458,7 +458,7 @@ static int API_env_get(va_list ap)
if ((value = (char **)va_arg(ap, uintptr_t)) == NULL)
return API_EINVAL;
*value = getenv(name);
*value = env_get(name);
return 0;
}
@@ -481,7 +481,7 @@ static int API_env_set(va_list ap)
if ((value = (char *)va_arg(ap, uintptr_t)) == NULL)
return API_EINVAL;
setenv(name, value);
env_set(name, value);
return 0;
}
@@ -625,7 +625,7 @@ int syscall(int call, int *retval, ...)
void api_init(void)
{
struct api_signature *sig = NULL;
struct api_signature *sig;
/* TODO put this into linker set one day... */
calls_table[API_RSVD] = NULL;
@@ -663,7 +663,7 @@ void api_init(void)
return;
}
setenv_hex("api_address", (unsigned long)sig);
env_set_hex("api_address", (unsigned long)sig);
debugf("API sig @ 0x%lX\n", (unsigned long)sig);
memcpy(sig->magic, API_SIG_MAGIC, 8);
sig->version = API_SIG_VERSION;

View File

@@ -63,7 +63,7 @@ void dev_stor_init(void)
specs[ENUM_MMC].type = DEV_TYP_STOR | DT_STOR_MMC;
specs[ENUM_MMC].name = "mmc";
#endif
#if defined(CONFIG_CMD_SATA)
#if defined(CONFIG_SATA)
specs[ENUM_SATA].max_dev = CONFIG_SYS_SATA_MAX_DEVICE;
specs[ENUM_SATA].enum_started = 0;
specs[ENUM_SATA].enum_ended = 0;

View File

@@ -66,6 +66,7 @@ config SANDBOX
select DM_SPI
select DM_GPIO
select DM_MMC
select LZO
imply CMD_GETTIME
imply CMD_HASH
imply CMD_IO
@@ -75,6 +76,9 @@ config SANDBOX
imply FAT_WRITE
imply HASH_VERIFY
imply LZMA
imply SCSI
imply CMD_SATA
imply CMD_SF_TEST
config SH
bool "SuperH architecture"
@@ -84,18 +88,36 @@ config X86
bool "x86 architecture"
select CREATE_ARCH_SYMLINK
select HAVE_PRIVATE_LIBGCC
select USE_PRIVATE_LIBGCC
select SUPPORT_OF_CONTROL
select OF_CONTROL
select DM
select DM_KEYBOARD
select DM_SERIAL
select DM_GPIO
select DM_SPI
select DM_SPI_FLASH
select USB_EHCI_HCD
select DM_PCI
select PCI
select TIMER
select X86_TSC_TIMER
imply BLK
imply DM_ETH
imply DM_GPIO
imply DM_KEYBOARD
imply DM_MMC
imply DM_RTC
imply DM_SERIAL
imply DM_SCSI
imply DM_SPI
imply DM_SPI_FLASH
imply DM_USB
imply DM_VIDEO
imply CMD_FPGA_LOADMK
imply CMD_GETTIME
imply CMD_IO
imply CMD_IRQ
imply CMD_PCI
imply CMD_SF_TEST
imply CMD_ZBOOT
imply USB_HOST_ETHER
imply USB_ETHER_ASIX
imply USB_ETHER_SMSC95XX
config XTENSA
bool "Xtensa architecture"

View File

@@ -85,7 +85,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
r2 = (unsigned int)images->ft_addr;
} else {
r0 = 1;
r2 = (unsigned int)getenv("bootargs");
r2 = (unsigned int)env_get("bootargs");
}
smp_set_core_boot_addr((unsigned long)kernel_entry, -1);

View File

@@ -97,6 +97,9 @@ config ARM_ERRATA_833069
config ARM_ERRATA_833471
bool
config ARM_ERRATA_845369
bool
config ARM_ERRATA_852421
bool
@@ -308,6 +311,7 @@ config TARGET_GPLUGD
config ARCH_DAVINCI
bool "TI DaVinci"
select CPU_ARM926EJS
imply CMD_SAVES
help
Support for TI's DaVinci platform.
@@ -409,21 +413,25 @@ config TARGET_SPEAR300
bool "Support spear300"
select CPU_ARM926EJS
select BOARD_EARLY_INIT_F
imply CMD_SAVES
config TARGET_SPEAR310
bool "Support spear310"
select CPU_ARM926EJS
select BOARD_EARLY_INIT_F
imply CMD_SAVES
config TARGET_SPEAR320
bool "Support spear320"
select CPU_ARM926EJS
select BOARD_EARLY_INIT_F
imply CMD_SAVES
config TARGET_SPEAR600
bool "Support spear600"
select CPU_ARM926EJS
select BOARD_EARLY_INIT_F
imply CMD_SAVES
config TARGET_STV0991
bool "Support stv0991"
@@ -522,6 +530,9 @@ config TARGET_BCMCYGNUS
imply CMD_HASH
imply FAT_WRITE
imply HASH_VERIFY
imply NETDEVICES
imply BCM_SF2_ETH
imply BCM_SF2_ETH_GMAC
config TARGET_BCMNSP
bool "Support bcmnsp"
@@ -569,7 +580,9 @@ config ARCH_KEYSTONE
select SUPPORT_SPL
select SYS_THUMB_BUILD
select CMD_POWEROFF
imply CMD_MTDPARTS
imply FIT
imply CMD_SAVES
config ARCH_OMAP2PLUS
bool "TI OMAP2+"
@@ -607,6 +620,11 @@ config ARCH_MX6
select SYS_FSL_SEC_LE
select SYS_THUMB_BUILD if SPL
if ARCH_MX6
config SPL_LDSCRIPT
default "arch/arm/mach-omap2/u-boot-spl.lds"
endif
config ARCH_MX5
bool "Freescale MX5"
select CPU_V7
@@ -649,6 +667,7 @@ config ARCH_SOCFPGA
select ARCH_MISC_INIT
select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
select SYS_THUMB_BUILD
imply CMD_MTDPARTS
imply CRC32_VERIFY
imply FAT_WRITE
@@ -674,6 +693,8 @@ config ARCH_SUNXI
select USB_STORAGE if DISTRO_DEFAULTS
select USB_KEYBOARD if DISTRO_DEFAULTS
select USE_TINY_PRINTF
imply CMD_FASTBOOT
imply FASTBOOT
imply FAT_WRITE
imply PRE_CONSOLE_BUFFER
imply SPL_GPIO_SUPPORT
@@ -683,6 +704,7 @@ config ARCH_SUNXI
imply SPL_MMC_SUPPORT if MMC
imply SPL_POWER_SUPPORT
imply SPL_SERIAL_SUPPORT
imply USB_FUNCTION_FASTBOOT
config TARGET_TS4600
bool "Support TS4600"
@@ -693,6 +715,8 @@ config ARCH_VF610
bool "Freescale Vybrid"
select CPU_V7
select SYS_FSL_ERRATUM_ESDHC111
imply CMD_MTDPARTS
imply NAND
config ARCH_ZYNQ
bool "Xilinx Zynq Platform"
@@ -707,7 +731,6 @@ config ARCH_ZYNQ
select DM_GPIO
select SPL_DM if SPL
select DM_MMC
select DM_MMC_OPS
select DM_SPI
select DM_SERIAL
select DM_SPI_FLASH
@@ -719,6 +742,7 @@ config ARCH_ZYNQ
select CLK_ZYNQ
imply CMD_CLK
imply FAT_WRITE
imply CMD_SPL
config ARCH_ZYNQMP
bool "Support Xilinx ZynqMP Platform"
@@ -792,6 +816,7 @@ config TARGET_LS2080AQDS
select BOARD_LATE_INIT
select SUPPORT_SPL
select ARCH_MISC_INIT
imply SCSI
help
Support for Freescale LS2080AQDS platform
The LS2080A Development System (QDS) is a high-performance
@@ -806,6 +831,7 @@ config TARGET_LS2080ARDB
select BOARD_LATE_INIT
select SUPPORT_SPL
select ARCH_MISC_INIT
imply SCSI
help
Support for Freescale LS2080ARDB platform.
The LS2080A Reference design board (RDB) is a high-performance
@@ -837,6 +863,19 @@ config TARGET_HIKEY
Support for HiKey 96boards platform. It features a HI6220
SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
config TARGET_POPLAR
bool "Support Poplar 96boards Enterprise Edition Platform"
select ARM64
select DM
select OF_CONTROL
select DM_SERIAL
select DM_USB
help
Support for Poplar 96boards EE platform. It features a HI3798cv200
SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
making it capable of running any commercial set-top solution based on
Linux or Android.
config TARGET_LS1012AQDS
bool "Support ls1012aqds"
select ARCH_LS1012A
@@ -853,6 +892,7 @@ config TARGET_LS1012ARDB
select ARCH_LS1012A
select ARM64
select BOARD_LATE_INIT
imply SCSI
help
Support for Freescale LS1012ARDB platform.
The LS1012A Reference design board (RDB) is a high-performance
@@ -881,6 +921,7 @@ config TARGET_LS1021AQDS
select LS1_DEEP_SLEEP
select SYS_FSL_DDR
select BOARD_EARLY_INIT_F
imply SCSI
config TARGET_LS1021ATWR
bool "Support ls1021atwr"
@@ -893,6 +934,7 @@ config TARGET_LS1021ATWR
select ARCH_SUPPORT_PSCI
select LS1_DEEP_SLEEP
select BOARD_EARLY_INIT_F
imply SCSI
config TARGET_LS1021AIOT
bool "Support ls1021aiot"
@@ -903,6 +945,7 @@ config TARGET_LS1021AIOT
select SUPPORT_SPL
select ARCH_LS1021A
select ARCH_SUPPORT_PSCI
imply SCSI
help
Support for Freescale LS1021AIOT platform.
The LS1021A Freescale board (IOT) is a high-performance
@@ -917,6 +960,7 @@ config TARGET_LS1043AQDS
select BOARD_LATE_INIT
select SUPPORT_SPL
select BOARD_EARLY_INIT_F
imply SCSI
help
Support for Freescale LS1043AQDS platform.
@@ -928,6 +972,7 @@ config TARGET_LS1043ARDB
select BOARD_LATE_INIT
select SUPPORT_SPL
select BOARD_EARLY_INIT_F
imply SCSI
help
Support for Freescale LS1043ARDB platform.
@@ -940,6 +985,7 @@ config TARGET_LS1046AQDS
select SUPPORT_SPL
select DM_SPI_FLASH if DM_SPI
select BOARD_EARLY_INIT_F
imply SCSI
help
Support for Freescale LS1046AQDS platform.
The LS1046A Development System (QDS) is a high-performance
@@ -956,6 +1002,7 @@ config TARGET_LS1046ARDB
select DM_SPI_FLASH if DM_SPI
select POWER_MC34VR500
select BOARD_EARLY_INIT_F
imply SCSI
help
Support for Freescale LS1046ARDB platform.
The LS1046A Reference Design Board (RDB) is a high-performance
@@ -977,7 +1024,6 @@ config TARGET_COLIBRI_PXA270
config ARCH_UNIPHIER
bool "Socionext UniPhier SoCs"
select BOARD_LATE_INIT
select CLK_UNIPHIER
select DM
select DM_GPIO
select DM_I2C
@@ -1031,14 +1077,17 @@ config ARCH_ROCKCHIP
select DM_GPIO
select DM_I2C
select DM_MMC
select DM_MMC_OPS
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
select DM_USB if USB
select DM_PWM
select DM_REGULATOR
imply CMD_FASTBOOT
imply FASTBOOT
imply FAT_WRITE
imply USB_FUNCTION_FASTBOOT
imply SPL_SYSRESET
config TARGET_THUNDERX_88XX
bool "Support ThunderX 88xx"
@@ -1075,13 +1124,13 @@ source "arch/arm/mach-mvebu/Kconfig"
source "arch/arm/cpu/armv7/ls102xa/Kconfig"
source "arch/arm/cpu/armv7/mx7ulp/Kconfig"
source "arch/arm/mach-imx/mx7ulp/Kconfig"
source "arch/arm/cpu/armv7/mx7/Kconfig"
source "arch/arm/mach-imx/mx7/Kconfig"
source "arch/arm/cpu/armv7/mx6/Kconfig"
source "arch/arm/mach-imx/mx6/Kconfig"
source "arch/arm/cpu/armv7/mx5/Kconfig"
source "arch/arm/mach-imx/mx5/Kconfig"
source "arch/arm/mach-omap2/Kconfig"
@@ -1121,7 +1170,7 @@ source "arch/arm/cpu/armv8/zynqmp/Kconfig"
source "arch/arm/cpu/armv8/Kconfig"
source "arch/arm/imx-common/Kconfig"
source "arch/arm/mach-imx/Kconfig"
source "board/aries/m28evk/Kconfig"
source "board/bosch/shc/Kconfig"
@@ -1165,6 +1214,7 @@ source "board/grinn/chiliboard/Kconfig"
source "board/gumstix/pepper/Kconfig"
source "board/h2200/Kconfig"
source "board/hisilicon/hikey/Kconfig"
source "board/hisilicon/poplar/Kconfig"
source "board/imx31_phycore/Kconfig"
source "board/isee/igep003x/Kconfig"
source "board/olimex/mx23_olinuxino/Kconfig"
@@ -1193,3 +1243,10 @@ source "board/zipitz2/Kconfig"
source "arch/arm/Kconfig.debug"
endmenu
config SPL_LDSCRIPT
default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if TARGET_APX4DEVKIT || TARGET_BG0900 || TARGET_M28EVK || TARGET_MX23_OLINUXINO || TARGET_MX23EVK || TARGET_MX28EVK || TARGET_SANSA_FUZE_PLUS || TARGET_SC_SPS_1 || TARGET_TS4600 || TARGET_XFI3
default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64

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@@ -96,11 +96,11 @@ libs-y += arch/arm/lib/
ifeq ($(CONFIG_SPL_BUILD),y)
ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35))
libs-y += arch/arm/imx-common/
libs-y += arch/arm/mach-imx/
endif
else
ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs vf610))
libs-y += arch/arm/imx-common/
libs-y += arch/arm/mach-imx/
endif
endif

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@@ -12,7 +12,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/imx-common/sys_proto.h>
#include <asm/mach-imx/sys_proto.h>
#ifdef CONFIG_MMC_MXC
#include <asm/arch/mxcmmc.h>
#endif

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@@ -14,7 +14,7 @@
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/imx-common/dma.h>
#include <asm/mach-imx/dma.h>
#include <asm/arch/gpio.h>
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>

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@@ -16,6 +16,8 @@ obj-$(CONFIG_DDR_MT47H64M16) += spr600_mt47h64m16_3_333_cl5_psync.o
obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o
obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_37e_166_cl4_sync.o
obj-$(CONFIG_DDR_MT47H128M8) += spr600_mt47h128m8_3_266_cl5_async.o
else
obj-y += spr_misc.o spr_lowlevel_init.o
endif
extra-$(CONFIG_SPL_BUILD) := start.o

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@@ -84,7 +84,7 @@ int print_cpuinfo(void)
}
#endif
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_ECC_BCH)
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_ECC_BCH) && defined(CONFIG_NAND_FSMC)
static int do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
{

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@@ -222,7 +222,7 @@ static void snor_init(void)
u32 spl_boot_device(void)
{
u32 mode;
u32 mode = 0;
/* Currently only SNOR is supported as the only */
if (snor_boot_selected()) {

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@@ -53,15 +53,15 @@ int misc_init_r(void)
#if defined(CONFIG_CMD_NET)
uchar mac_id[6];
if (!eth_getenv_enetaddr("ethaddr", mac_id) && !i2c_read_mac(mac_id))
eth_setenv_enetaddr("ethaddr", mac_id);
if (!eth_env_get_enetaddr("ethaddr", mac_id) && !i2c_read_mac(mac_id))
eth_env_set_enetaddr("ethaddr", mac_id);
#endif
setenv("verify", "n");
env_set("verify", "n");
#if defined(CONFIG_SPEAR_USBTTY)
setenv("stdin", "usbtty");
setenv("stdout", "usbtty");
setenv("stderr", "usbtty");
env_set("stdin", "usbtty");
env_set("stdout", "usbtty");
env_set("stderr", "usbtty");
#ifndef CONFIG_SYS_NO_DCACHE
dcache_enable();

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@@ -33,10 +33,6 @@ obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/
obj-$(if $(filter mx5,$(SOC)),y) += mx5/
obj-$(CONFIG_MX6) += mx6/
obj-$(CONFIG_MX7) += mx7/
obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
obj-$(CONFIG_RMOBILE) += rmobile/
obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/

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@@ -479,9 +479,9 @@ unsigned long clk_get_rate(struct clk *c)
{
unsigned long rate;
debug("%s: %s\n", __func__, c->name);
if (!c || !c->ops || !c->ops->get_rate)
return 0;
debug("%s: %s\n", __func__, c->name);
rate = c->ops->get_rate(c);
debug("%s: rate = %ld\n", __func__, rate);
@@ -493,9 +493,9 @@ int clk_set_rate(struct clk *c, unsigned long rate)
{
int ret;
debug("%s: %s rate=%ld\n", __func__, c->name, rate);
if (!c || !c->ops || !c->ops->set_rate)
return -EINVAL;
debug("%s: %s rate=%ld\n", __func__, c->name, rate);
if (c->use_cnt)
return -EINVAL;

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@@ -479,9 +479,9 @@ unsigned long clk_get_rate(struct clk *c)
{
unsigned long rate;
debug("%s: %s\n", __func__, c->name);
if (!c || !c->ops || !c->ops->get_rate)
return 0;
debug("%s: %s\n", __func__, c->name);
rate = c->ops->get_rate(c);
debug("%s: rate = %ld\n", __func__, rate);
@@ -493,9 +493,9 @@ int clk_set_rate(struct clk *c, unsigned long rate)
{
int ret;
debug("%s: %s rate=%ld\n", __func__, c->name, rate);
if (!c || !c->ops || !c->ops->set_rate)
return -EINVAL;
debug("%s: %s rate=%ld\n", __func__, c->name, rate);
if (c->use_cnt)
return -EINVAL;

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@@ -14,6 +14,8 @@ config ARCH_LS1021A
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_LE
imply SCSI
imply CMD_PCI
menu "LS102xA architecture"
depends on ARCH_LS1021A

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@@ -36,7 +36,7 @@ int ls1021a_sata_init(void)
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
ahci_init((void __iomem *)AHCI_BASE_ADDR);
scsi_scan(0);
scsi_scan(false);
return 0;
}

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@@ -187,6 +187,12 @@ ENTRY(cpu_init_cp15)
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_845369
mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
orr r0, r0, #1 << 22 @ set bit #22
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
#endif
mov r5, lr @ Store my Caller
mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR)
mov r3, r1, lsr #20 @ get variant field

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@@ -9,7 +9,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/imx-common/sys_proto.h>
#include <asm/mach-imx/sys_proto.h>
#include <netdev.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
@@ -329,7 +329,7 @@ int arch_misc_init(void)
strcpy(soc, "vf");
strcat(soc, soc_type);
setenv("soc", soc);
env_set("soc", soc);
return 0;
}

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@@ -68,6 +68,7 @@ void mpu_config(struct mpu_region_config *reg_config)
break;
case DEVICE_NON_SHARED:
attr = (2 << TEX_SHIFT) | BUFFERABLE;
break;
default:
attr = 0; /* strongly ordered */
break;

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@@ -8,7 +8,9 @@
extra-y := start.o
obj-y += cpu.o
ifndef CONFIG_$(SPL_TPL_)TIMER
obj-y += generic_timer.o
endif
obj-y += cache_v8.o
obj-y += exceptions.o
obj-y += cache.o

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@@ -22,6 +22,7 @@
* x1: 0 clean & invalidate, 1 invalidate only
* x2~x9: clobbered
*/
.pushsection .text.__asm_dcache_level, "ax"
ENTRY(__asm_dcache_level)
lsl x12, x0, #1
msr csselr_el1, x12 /* select cache level */
@@ -58,6 +59,7 @@ loop_way:
ret
ENDPROC(__asm_dcache_level)
.popsection
/*
* void __asm_flush_dcache_all(int invalidate_only)
@@ -66,6 +68,7 @@ ENDPROC(__asm_dcache_level)
*
* flush or invalidate all data cache by SET/WAY.
*/
.pushsection .text.__asm_dcache_all, "ax"
ENTRY(__asm_dcache_all)
mov x1, x0
dsb sy
@@ -102,16 +105,21 @@ skip:
finished:
ret
ENDPROC(__asm_dcache_all)
.popsection
.pushsection .text.__asm_flush_dcache_all, "ax"
ENTRY(__asm_flush_dcache_all)
mov x0, #0
b __asm_dcache_all
ENDPROC(__asm_flush_dcache_all)
.popsection
.pushsection .text.__asm_invalidate_dcache_all, "ax"
ENTRY(__asm_invalidate_dcache_all)
mov x0, #0x1
b __asm_dcache_all
ENDPROC(__asm_invalidate_dcache_all)
.popsection
/*
* void __asm_flush_dcache_range(start, end)
@@ -121,6 +129,7 @@ ENDPROC(__asm_invalidate_dcache_all)
* x0: start address
* x1: end address
*/
.pushsection .text.__asm_flush_dcache_range, "ax"
ENTRY(__asm_flush_dcache_range)
mrs x3, ctr_el0
lsr x3, x3, #16
@@ -138,6 +147,7 @@ ENTRY(__asm_flush_dcache_range)
dsb sy
ret
ENDPROC(__asm_flush_dcache_range)
.popsection
/*
* void __asm_invalidate_dcache_range(start, end)
*
@@ -146,6 +156,7 @@ ENDPROC(__asm_flush_dcache_range)
* x0: start address
* x1: end address
*/
.pushsection .text.__asm_invalidate_dcache_range, "ax"
ENTRY(__asm_invalidate_dcache_range)
mrs x3, ctr_el0
ubfm x3, x3, #16, #19
@@ -162,41 +173,51 @@ ENTRY(__asm_invalidate_dcache_range)
dsb sy
ret
ENDPROC(__asm_invalidate_dcache_range)
.popsection
/*
* void __asm_invalidate_icache_all(void)
*
* invalidate all tlb entries.
*/
.pushsection .text.__asm_invalidate_icache_all, "ax"
ENTRY(__asm_invalidate_icache_all)
ic ialluis
isb sy
ret
ENDPROC(__asm_invalidate_icache_all)
.popsection
.pushsection .text.__asm_invalidate_l3_dcache, "ax"
ENTRY(__asm_invalidate_l3_dcache)
mov x0, #0 /* return status as success */
ret
ENDPROC(__asm_invalidate_l3_dcache)
.weak __asm_invalidate_l3_dcache
.popsection
.pushsection .text.__asm_flush_l3_dcache, "ax"
ENTRY(__asm_flush_l3_dcache)
mov x0, #0 /* return status as success */
ret
ENDPROC(__asm_flush_l3_dcache)
.weak __asm_flush_l3_dcache
.popsection
.pushsection .text.__asm_invalidate_l3_icache, "ax"
ENTRY(__asm_invalidate_l3_icache)
mov x0, #0 /* return status as success */
ret
ENDPROC(__asm_invalidate_l3_icache)
.weak __asm_invalidate_l3_icache
.popsection
/*
* void __asm_switch_ttbr(ulong new_ttbr)
*
* Safely switches to a new page table.
*/
.pushsection .text.__asm_switch_ttbr, "ax"
ENTRY(__asm_switch_ttbr)
/* x2 = SCTLR (alive throghout the function) */
switch_el x4, 3f, 2f, 1f
@@ -244,3 +265,4 @@ ENTRY(__asm_switch_ttbr)
ret x3
ENDPROC(__asm_switch_ttbr)
.popsection

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@@ -26,6 +26,8 @@ config ARCH_LS1043A
select SYS_FSL_HAS_DDR4
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
imply SCSI
imply CMD_PCI
config ARCH_LS1046A
bool
@@ -46,6 +48,7 @@ config ARCH_LS1046A
select SYS_FSL_SRDS_2
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
imply SCSI
config ARCH_LS2080A
bool
@@ -305,7 +308,7 @@ config SYS_FSL_DSPI_CLK_DIV
default 2
help
This is the divider that is used to derive DSPI clock from Platform
PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider.
clock, in another word DSPI_clk = Platform_clk / this_divider.
config SYS_FSL_DUART_CLK_DIV
int "DUART clock divider"
@@ -390,3 +393,6 @@ config SYS_MC_RSV_MEM_ALIGN
help
Reserved memory needs to be aligned for MC to use. Default value
is 512MB.
config SPL_LDSCRIPT
default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A

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@@ -345,11 +345,38 @@ static void fdt_fixup_msi(void *blob)
}
#endif
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
/* Remove JR node used by SEC firmware */
void fdt_fixup_remove_jr(void *blob)
{
int jr_node, addr_cells, len;
int crypto_node = fdt_path_offset(blob, "crypto");
u64 jr_offset, used_jr;
fdt32_t *reg;
used_jr = sec_firmware_used_jobring_offset();
fdt_support_default_count_cells(blob, crypto_node, &addr_cells, NULL);
jr_node = fdt_node_offset_by_compatible(blob, crypto_node,
"fsl,sec-v4.0-job-ring");
while (jr_node != -FDT_ERR_NOTFOUND) {
reg = (fdt32_t *)fdt_getprop(blob, jr_node, "reg", &len);
jr_offset = fdt_read_number(reg, addr_cells);
if (jr_offset == used_jr) {
fdt_del_node(blob, jr_node);
break;
}
jr_node = fdt_node_offset_by_compatible(blob, jr_node,
"fsl,sec-v4.0-job-ring");
}
}
#endif
void ft_cpu_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_FSL_LSCH2
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
unsigned int svr = in_be32(&gur->svr);
unsigned int svr = gur_in32(&gur->svr);
/* delete crypto node if not on an E-processor */
if (!IS_E_PROCESSOR(svr))
@@ -358,11 +385,15 @@ void ft_cpu_setup(void *blob, bd_t *bd)
else {
ccsr_sec_t __iomem *sec;
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
if (fdt_fixup_kaslr(blob))
fdt_fixup_remove_jr(blob);
#endif
sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
}
#endif
#endif
#ifdef CONFIG_MP
ft_fixup_cpu(blob);

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@@ -497,9 +497,7 @@ slave_cpu:
rev x0, x0 /* BE to LE conversion */
cpu_is_le:
ldr x5, [x11, #24]
ldr x6, =IH_ARCH_DEFAULT
cmp x6, x5
b.eq 1f
cbz x5, 1f
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
adr x4, secondary_switch_to_el1
@@ -541,9 +539,7 @@ ENTRY(secondary_switch_to_el1)
ldr x4, [x11]
ldr x5, [x11, #24]
ldr x6, =IH_ARCH_DEFAULT
cmp x6, x5
b.eq 2f
cbz x5, 2f
ldr x5, =ES_TO_AARCH32
bl switch_to_el1

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@@ -29,9 +29,14 @@ void update_os_arch_secondary_cores(uint8_t os_arch)
u64 *table = get_spin_tbl_addr();
int i;
for (i = 1; i < CONFIG_MAX_CPUS; i++)
table[i * WORDS_PER_SPIN_TABLE_ENTRY +
SPIN_TABLE_ELEM_OS_ARCH_IDX] = os_arch;
for (i = 1; i < CONFIG_MAX_CPUS; i++) {
if (os_arch == IH_ARCH_DEFAULT)
table[i * WORDS_PER_SPIN_TABLE_ENTRY +
SPIN_TABLE_ELEM_ARCH_COMP_IDX] = OS_ARCH_SAME;
else
table[i * WORDS_PER_SPIN_TABLE_ENTRY +
SPIN_TABLE_ELEM_ARCH_COMP_IDX] = OS_ARCH_DIFF;
}
}
#ifdef CONFIG_FSL_LSCH3

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@@ -173,8 +173,9 @@ int ppa_init(void)
debug("%s: PPA image load from NAND\n", __func__);
nand_init();
ret = nand_read(nand_info[0], (loff_t)CONFIG_SYS_LS_PPA_FW_ADDR,
&fdt_header_len, (u_char *)&fit);
ret = nand_read(get_nand_dev_by_index(0),
(loff_t)CONFIG_SYS_LS_PPA_FW_ADDR,
&fdt_header_len, (u_char *)&fit);
if (ret == -EUCLEAN) {
printf("NAND read of PPA FIT header at offset 0x%x failed\n",
CONFIG_SYS_LS_PPA_FW_ADDR);
@@ -196,8 +197,9 @@ int ppa_init(void)
fw_length = CONFIG_LS_PPA_ESBC_HDR_SIZE;
ret = nand_read(nand_info[0], (loff_t)CONFIG_SYS_LS_PPA_ESBC_ADDR,
&fw_length, (u_char *)ppa_hdr_ddr);
ret = nand_read(get_nand_dev_by_index(0),
(loff_t)CONFIG_SYS_LS_PPA_ESBC_ADDR,
&fw_length, (u_char *)ppa_hdr_ddr);
if (ret == -EUCLEAN) {
free(ppa_hdr_ddr);
printf("NAND read of PPA firmware at offset 0x%x failed\n",
@@ -221,8 +223,9 @@ int ppa_init(void)
return -ENOMEM;
}
ret = nand_read(nand_info[0], (loff_t)CONFIG_SYS_LS_PPA_FW_ADDR,
&fw_length, (u_char *)ppa_fit_addr);
ret = nand_read(get_nand_dev_by_index(0),
(loff_t)CONFIG_SYS_LS_PPA_FW_ADDR,
&fw_length, (u_char *)ppa_fit_addr);
if (ret == -EUCLEAN) {
free(ppa_fit_addr);
printf("NAND read of PPA firmware at offset 0x%x failed\n",

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@@ -95,7 +95,7 @@ static void erratum_a008514(void)
static unsigned long get_internval_val_mhz(void)
{
char *interval = getenv(PLATFORM_CYCLE_ENV_VAR);
char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
/*
* interval is the number of platform cycles(MHz) between
* wake up events generated by EPU.
@@ -225,7 +225,7 @@ int sata_init(void)
out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
ahci_init((void __iomem *)CONFIG_SYS_SATA1);
scsi_scan(0);
scsi_scan(false);
return 0;
}
@@ -244,7 +244,7 @@ int sata_init(void)
out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
ahci_init((void __iomem *)CONFIG_SYS_SATA);
scsi_scan(0);
scsi_scan(false);
return 0;
}

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@@ -231,6 +231,59 @@ unsigned int sec_firmware_support_psci_version(void)
}
#endif
/*
* Check with sec_firmware if it supports random number generation
* via HW RNG
*
* The return value will be true if it is supported
*/
bool sec_firmware_support_hwrng(void)
{
uint8_t rand[8];
if (sec_firmware_addr & SEC_FIRMWARE_RUNNING) {
if (!sec_firmware_get_random(rand, 8))
return true;
}
return false;
}
/*
* sec_firmware_get_random - Get a random number from SEC Firmware
* @rand: random number buffer to be filled
* @bytes: Number of bytes of random number to be supported
* @eret: -1 in case of error, 0 for success
*/
int sec_firmware_get_random(uint8_t *rand, int bytes)
{
unsigned long long num;
struct pt_regs regs;
int param1;
if (!bytes || bytes > 8) {
printf("Max Random bytes genration supported is 8\n");
return -1;
}
#define SIP_RNG_64 0xC200FF11
regs.regs[0] = SIP_RNG_64;
if (bytes <= 4)
param1 = 0;
else
param1 = 1;
regs.regs[1] = param1;
smc_call(&regs);
if (regs.regs[0])
return -1;
num = regs.regs[1];
memcpy(rand, &num, bytes);
return 0;
}
/*
* sec_firmware_init - Initialize the SEC Firmware
* @sec_firmware_img: the SEC Firmware image address
@@ -278,3 +331,49 @@ int sec_firmware_init(const void *sec_firmware_img,
return 0;
}
/*
* fdt_fix_kaslr - Add kalsr-seed node in Device tree
* @fdt: Device tree
* @eret: 0 in case of error, 1 for success
*/
int fdt_fixup_kaslr(void *fdt)
{
int nodeoffset;
int err, ret = 0;
u8 rand[8];
#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT)
/* Check if random seed generation is supported */
if (sec_firmware_support_hwrng() == false)
return 0;
ret = sec_firmware_get_random(rand, 8);
if (ret < 0) {
printf("WARNING: No random number to set kaslr-seed\n");
return 0;
}
err = fdt_check_header(fdt);
if (err < 0) {
printf("fdt_chosen: %s\n", fdt_strerror(err));
return 0;
}
/* find or create "/chosen" node. */
nodeoffset = fdt_find_or_add_subnode(fdt, 0, "chosen");
if (nodeoffset < 0)
return 0;
err = fdt_setprop(fdt, nodeoffset, "kaslr-seed", rand,
sizeof(rand));
if (err < 0) {
printf("WARNING: can't set kaslr-seed %s.\n",
fdt_strerror(err));
return 0;
}
ret = 1;
#endif
return ret;
}

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@@ -14,7 +14,8 @@
* void __asm_invalidate_tlb_all(void)
*
* invalidate all tlb entries.
*/
*/
.pushsection .text.__asm_invalidate_tlb_all, "ax"
ENTRY(__asm_invalidate_tlb_all)
switch_el x9, 3f, 2f, 1f
3: tlbi alle3
@@ -31,3 +32,4 @@ ENTRY(__asm_invalidate_tlb_all)
0:
ret
ENDPROC(__asm_invalidate_tlb_all)
.popsection

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@@ -10,6 +10,7 @@
#include <linux/linkage.h>
#include <asm/macro.h>
.pushsection .text.armv8_switch_to_el2, "ax"
ENTRY(armv8_switch_to_el2)
switch_el x6, 1f, 0f, 0f
0:
@@ -30,7 +31,9 @@ ENTRY(armv8_switch_to_el2)
br x4
1: armv8_switch_to_el2_m x4, x5, x6
ENDPROC(armv8_switch_to_el2)
.popsection
.pushsection .text.armv8_switch_to_el1, "ax"
ENTRY(armv8_switch_to_el1)
switch_el x6, 0f, 1f, 0f
0:
@@ -40,7 +43,10 @@ ENTRY(armv8_switch_to_el1)
br x4
1: armv8_switch_to_el1_m x4, x5, x6
ENDPROC(armv8_switch_to_el1)
.popsection
.pushsection .text.armv8_el2_to_aarch32, "ax"
WEAK(armv8_el2_to_aarch32)
ret
ENDPROC(armv8_el2_to_aarch32)
.popsection

View File

@@ -56,6 +56,17 @@ config ZYNQMP_USB
config SYS_MALLOC_F_LEN
default 0x600
config DEFINE_TCM_OCM_MMAP
bool "Define TCM and OCM memory in MMU Table"
help
This option if enabled defines the TCM and OCM memory and its
memory attributes in MMU table entry.
config ZYNQMP_PSU_INIT_ENABLED
bool "Include psu_init"
help
Include psu_init to full u-boot. SPL include psu_init by default.
config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
bool "Overwrite SPL bootmode"
depends on SPL

View File

@@ -38,6 +38,14 @@ static struct mm_region zynqmp_mem_map[] = {
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
.virt = 0xffe00000UL,
.phys = 0xffe00000UL,
.size = 0x00200000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
#endif
.virt = 0x400000000UL,
.phys = 0x400000000UL,
.size = 0x200000000UL,
@@ -102,9 +110,8 @@ unsigned int zynqmp_get_silicon_version(void)
#define ZYNQMP_MMIO_READ 0xC2000014
#define ZYNQMP_MMIO_WRITE 0xC2000013
#ifndef CONFIG_SPL_BUILD
int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3,
u32 *ret_payload)
int __maybe_unused invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2,
u32 arg3, u32 *ret_payload)
{
/*
* Added SIP service call Function Identifier
@@ -164,28 +171,7 @@ void zynqmp_pmufw_version(void)
}
#endif
int zynqmp_mmio_write(const u32 address,
const u32 mask,
const u32 value)
{
return invoke_smc(ZYNQMP_MMIO_WRITE, address, mask, value, 0, NULL);
}
int zynqmp_mmio_read(const u32 address, u32 *value)
{
u32 ret_payload[PAYLOAD_ARG_CNT];
u32 ret;
if (!value)
return -EINVAL;
ret = invoke_smc(ZYNQMP_MMIO_READ, address, 0, 0, 0, ret_payload);
*value = ret_payload[1];
return ret;
}
#else
int zynqmp_mmio_write(const u32 address,
static int zynqmp_mmio_rawwrite(const u32 address,
const u32 mask,
const u32 value)
{
@@ -200,9 +186,40 @@ int zynqmp_mmio_write(const u32 address,
return 0;
}
int zynqmp_mmio_read(const u32 address, u32 *value)
static int zynqmp_mmio_rawread(const u32 address, u32 *value)
{
*value = readl((ulong)address);
return 0;
}
#endif
int zynqmp_mmio_write(const u32 address,
const u32 mask,
const u32 value)
{
if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3)
return zynqmp_mmio_rawwrite(address, mask, value);
else if (!IS_ENABLED(CONFIG_SPL_BUILD))
return invoke_smc(ZYNQMP_MMIO_WRITE, address, mask,
value, 0, NULL);
return -EINVAL;
}
int zynqmp_mmio_read(const u32 address, u32 *value)
{
u32 ret_payload[PAYLOAD_ARG_CNT];
u32 ret;
if (!value)
return -EINVAL;
if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
ret = zynqmp_mmio_rawread(address, value);
} else if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
ret = invoke_smc(ZYNQMP_MMIO_READ, address, 0, 0,
0, ret_payload);
*value = ret_payload[1];
}
return ret;
}

View File

@@ -206,6 +206,21 @@ static void write_tcm_boot_trampoline(u32 boot_addr)
}
}
void initialize_tcm(bool mode)
{
if (!mode) {
set_r5_tcm_mode(LOCK);
set_r5_halt_mode(HALT, LOCK);
enable_clock_r5();
release_r5_reset(LOCK);
} else {
set_r5_tcm_mode(SPLIT);
set_r5_halt_mode(HALT, SPLIT);
enable_clock_r5();
release_r5_reset(SPLIT);
}
}
int cpu_release(int nr, int argc, char * const argv[])
{
if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {

View File

@@ -17,7 +17,7 @@
void board_init_f(ulong dummy)
{
psu_init();
board_early_init_f();
board_early_init_r();
#ifdef CONFIG_DEBUG_UART

View File

@@ -34,6 +34,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-fennec.dtb \
rk3288-firefly.dtb \
rk3288-miqi.dtb \
rk3288-phycore-rdk.dtb \
rk3288-popmetal.dtb \
rk3288-rock2-square.dtb \
rk3288-tinker.dtb \
@@ -41,6 +42,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-mickey.dtb \
rk3288-veyron-minnie.dtb \
rk3328-evb.dtb \
rk3368-lion.dtb \
rk3368-sheep.dtb \
rk3368-geekbox.dtb \
rk3368-px5-evb.dtb \
@@ -117,8 +119,6 @@ dtb-$(CONFIG_ARCH_UNIPHIER_PXS2) += \
uniphier-pxs2-vodka.dtb
dtb-$(CONFIG_ARCH_UNIPHIER_PXS3) += \
uniphier-pxs3-ref.dtb
dtb-$(CONFIG_ARCH_UNIPHIER_SLD3) += \
uniphier-sld3-ref.dtb
dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \
uniphier-sld8-ref.dtb
@@ -131,13 +131,14 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
zynq-topic-miami.dtb \
zynq-topic-miamilite.dtb \
zynq-topic-miamiplus.dtb \
zynq-zturn-myir.dtb \
zynq-zc770-xm010.dtb \
zynq-zc770-xm011.dtb \
zynq-zc770-xm012.dtb \
zynq-zc770-xm013.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-ep108.dtb \
zynqmp-zcu102.dtb \
zynqmp-zcu102-revA.dtb \
zynqmp-zcu102-revB.dtb \
zynqmp-zc1751-xm015-dc1.dtb \
zynqmp-zc1751-xm016-dc2.dtb \
@@ -333,6 +334,8 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \
sun50i-h5-orangepi-zero-plus2.dtb
dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-bananapi-m64.dtb \
sun50i-a64-nanopi-a64.dtb \
sun50i-a64-olinuxino.dtb \
sun50i-a64-orangepi-win.dtb \
sun50i-a64-pine64-plus.dtb \
sun50i-a64-pine64.dtb
@@ -354,6 +357,7 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
imx6sll-evk.dtb \
imx6dl-icore.dtb \
imx6dl-icore-rqs.dtb \
imx6q-cm-fx6.dtb \
imx6q-icore.dtb \
imx6q-icore-rqs.dtb \
imx6q-logicpd.dtb \
@@ -369,10 +373,22 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
dtb-$(CONFIG_RCAR_GEN3) += \
r8a7795-h3ulcb.dtb \
r8a7795-salvator-x.dtb \
r8a7796-m3ulcb.dtb \
r8a7796-salvator-x.dtb
dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
keystone-k2l-evm.dtb \
keystone-k2e-evm.dtb \
keystone-k2g-evm.dtb
keystone-k2g-evm.dtb \
keystone-k2g-generic.dtb \
keystone-k2g-ice.dtb
dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb
dtb-$(CONFIG_TARGET_PM9263) += at91sam9263ek.dtb
dtb-$(CONFIG_TARGET_AT91SAM9263EK) += at91sam9263ek.dtb

View File

@@ -315,7 +315,6 @@
&edma 25>;
dma-names = "tx", "rx";
interrupts = <64>;
interrupt-parent = <&intc>;
reg = <0x48060000 0x1000>;
status = "disabled";
};
@@ -328,7 +327,6 @@
&edma 3>;
dma-names = "tx", "rx";
interrupts = <28>;
interrupt-parent = <&intc>;
reg = <0x481d8000 0x1000>;
status = "disabled";
};
@@ -338,7 +336,6 @@
ti,hwmods = "mmc3";
ti,needs-special-reset;
interrupts = <29>;
interrupt-parent = <&intc>;
reg = <0x47810000 0x1000>;
status = "disabled";
};
@@ -724,7 +721,6 @@
0x4a101200 0x100>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
/*
* c0_rx_thresh_pend
* c0_rx_pend
@@ -787,7 +783,6 @@
lcdc: lcdc@4830e000 {
compatible = "ti,am33xx-tilcdc";
reg = <0x4830e000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <36>;
ti,hwmods = "lcdc";
status = "disabled";
@@ -796,7 +791,6 @@
tscadc: tscadc@44e0d000 {
compatible = "ti,am3359-tscadc";
reg = <0x44e0d000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <16>;
ti,hwmods = "adc_tsc";
status = "disabled";

View File

@@ -154,7 +154,7 @@
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p128", "jedec,spi-nor";
compatible = "st,m25p128", "jedec,spi-nor", "spi-flash";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
m25p,fast-read;

View File

@@ -0,0 +1,55 @@
/*
* Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/ {
aliases {
i2c0 = &i2c0;
i2c1 = &i2cmux;
spi0 = &spi0;
};
};
&i2c0 {
u-boot,dm-pre-reloc;
i2cmux: i2cmux@70 {
u-boot,dm-pre-reloc;
i2c@0 {
u-boot,dm-pre-reloc;
};
i2c@1 {
u-boot,dm-pre-reloc;
};
i2c@5 {
u-boot,dm-pre-reloc;
/* ATSHA204A at address 0x64 */
atsha204a@64 {
u-boot,dm-pre-reloc;
compatible = "atmel,atsha204a";
reg = <0x64>;
};
};
};
};
&spi0 {
u-boot,dm-pre-reloc;
spi-flash@0 {
compatible = "spi-flash";
reg = <0>;
spi-max-frequency = <40000000>;
u-boot,dm-pre-reloc;
};
};
&uart0 {
u-boot,dm-pre-reloc;
};

View File

@@ -0,0 +1,392 @@
/*
* Device Tree file for the Turris Omnia
*
* Copyright (C) 2016 Uwe Kleine-König <uwe@kleine-koenig.org>
* Copyright (C) 2016 Tomas Hlavacek <tmshlvkc@gmail.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "armada-385.dtsi"
/ {
model = "Turris Omnia";
compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380";
chosen {
stdout-path = &uart0;
};
memory {
device_type = "memory";
reg = <0x00000000 0x40000000>; /* 1024 MB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
internal-regs {
/* USB part of the PCIe2/USB 2.0 port */
usb@58000 {
status = "okay";
};
sata@a8000 {
status = "okay";
};
sdhci@d8000 {
pinctrl-names = "default";
pinctrl-0 = <&sdhci_pins>;
status = "okay";
bus-width = <8>;
no-1-8-v;
non-removable;
};
usb3@f0000 {
status = "okay";
};
usb3@f8000 {
status = "okay";
};
};
pcie-controller {
status = "okay";
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
pcie@3,0 {
/* Port 2, Lane 0 */
status = "okay";
};
};
};
};
/* Connected to 88E6176 switch, port 6 */
&eth0 {
pinctrl-names = "default";
pinctrl-0 = <&ge0_rgmii_pins>;
status = "okay";
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
/* Connected to 88E6176 switch, port 5 */
&eth1 {
pinctrl-names = "default";
pinctrl-0 = <&ge1_rgmii_pins>;
status = "okay";
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
/* WAN port */
&eth2 {
status = "okay";
phy-mode = "sgmii";
phy = <&phy1>;
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
i2cmux@70 {
compatible = "nxp,pca9547";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
status = "okay";
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
/* STM32F0 command interface at address 0x2a */
/* leds device (in STM32F0) at address 0x2b */
eeprom@54 {
compatible = "at,24c64";
reg = <0x54>;
/* The EEPROM contains data for bootloader.
* Contents:
* struct omnia_eeprom {
* u32 magic; (=0x0341a034 in LE)
* u32 ramsize; (in GiB)
* char regdomain[4];
* u32 crc32;
* };
*/
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
/* routed to PCIe0/mSATA connector (CN7A) */
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
/* routed to PCIe1/USB2 connector (CN61A) */
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
/* routed to PCIe2 connector (CN62A) */
};
i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
/* routed to SFP+ */
};
i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
/* ATSHA204A at address 0x64 */
};
i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
/* exposed on pin header */
};
i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
pcawan: gpio@71 {
/*
* GPIO expander for SFP+ signals and
* and phy irq
*/
compatible = "nxp,pca9538";
reg = <0x71>;
pinctrl-names = "default";
pinctrl-0 = <&pcawan_pins>;
interrupt-parent = <&gpio1>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
gpio-controller;
#gpio-cells = <2>;
};
};
};
};
&mdio {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
status = "okay";
phy1: phy@1 {
status = "okay";
compatible = "ethernet-phy-id0141.0DD1", "ethernet-phy-ieee802.3-c22";
reg = <1>;
/* irq is connected to &pcawan pin 7 */
};
/* Switch MV88E6176 at address 0x10 */
switch@10 {
compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
dsa,member = <0 0>;
reg = <0x10>;
ports {
#address-cells = <1>;
#size-cells = <0>;
ports@0 {
reg = <0>;
label = "lan0";
};
ports@1 {
reg = <1>;
label = "lan1";
};
ports@2 {
reg = <2>;
label = "lan2";
};
ports@3 {
reg = <3>;
label = "lan3";
};
ports@4 {
reg = <4>;
label = "lan4";
};
ports@5 {
reg = <5>;
label = "cpu";
ethernet = <&eth1>;
phy-mode = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
/* port 6 is connected to eth0 */
};
};
};
&pinctrl {
pcawan_pins: pcawan-pins {
marvell,pins = "mpp46";
marvell,function = "gpio";
};
spi0cs0_pins: spi0cs0-pins {
marvell,pins = "mpp25";
marvell,function = "spi0";
};
spi0cs1_pins: spi0cs1-pins {
marvell,pins = "mpp26";
marvell,function = "spi0";
};
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
status = "okay";
spi-nor@0 {
compatible = "spansion,s25fl164k", "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <40000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x0 0x00100000>;
label = "U-Boot";
};
partition@100000 {
reg = <0x00100000 0x00700000>;
label = "Rescue system";
};
};
};
/* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */
};
&uart0 {
/* Pin header CN10 */
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&uart1 {
/* Pin header CN11 */
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};

View File

@@ -34,6 +34,7 @@
tcb1 = &tcb1;
i2c0 = &i2c0;
ssc0 = &ssc0;
spi0 = &spi0;
};
cpus {
#address-cells = <0>;

View File

@@ -118,7 +118,7 @@
cs-gpios = <0>, <&pioC 11 0>, <0>, <0>;
mtd_dataflash@0 {
compatible = "atmel,at45", "atmel,dataflash";
spi-max-frequency = <50000000>;
spi-max-frequency = <15000000>;
reg = <1>;
};
};

View File

@@ -30,6 +30,7 @@
ssc0 = &ssc0;
ssc1 = &ssc1;
ssc2 = &ssc2;
spi0 = &spi0;
};
cpus {
@@ -70,6 +71,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges;
u-boot,dm-pre-reloc;
usb0: ohci@00500000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
@@ -112,6 +114,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges;
u-boot,dm-pre-reloc;
tcb0: timer@fffa0000 {
compatible = "atmel,at91rm9200-tcb";
@@ -286,20 +289,61 @@
status = "disabled";
};
pioA: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
u-boot,dm-pre-reloc;
};
pioB: gpio@fffff600 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
u-boot,dm-pre-reloc;
};
pioC: gpio@fffff800 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioC_clk>;
u-boot,dm-pre-reloc;
};
pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
ranges = <0xfffff400 0xfffff400 0x600>;
reg = <0xfffff400 0x200 /* pioA */
0xfffff600 0x200 /* pioB */
0xfffff800 0x200 /* pioC */
>;
atmel,mux-mask =
/* A B */
<0xffffffff 0xfffffff7>, /* pioA */
<0xffffffff 0xfffffff4>, /* pioB */
<0xffffffff 0xffffff07>; /* pioC */
u-boot,dm-pre-reloc;
/* shared pinctrl settings */
dbgu {
u-boot,dm-pre-reloc;
pinctrl_dbgu: dbgu-0 {
atmel,pins =
<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE>,
@@ -532,39 +576,6 @@
<AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
};
pioA: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
};
pioB: gpio@fffff600 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
};
pioC: gpio@fffff800 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioC_clk>;
};
};
pmc: pmc@fffffc00 {
@@ -575,6 +586,7 @@
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
u-boot,dm-pre-reloc;
main_osc: main_osc {
compatible = "atmel,at91rm9200-clk-main-osc";
@@ -589,7 +601,7 @@
clocks = <&main_osc>;
};
plla: pllack {
plla: pllack@0 {
compatible = "atmel,at91rm9200-clk-pll";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_LOCKA>;
@@ -601,7 +613,7 @@
<190000000 240000000 2 1>;
};
pllb: pllbck {
pllb: pllbck@1 {
compatible = "atmel,at91rm9200-clk-pll";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_LOCKB>;
@@ -619,6 +631,7 @@
clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
atmel,clk-output-range = <0 94000000>;
atmel,clk-divisors = <1 2 4 0>;
u-boot,dm-pre-reloc;
};
usb: usbck {
@@ -635,25 +648,25 @@
interrupt-parent = <&pmc>;
clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
prog0: prog0 {
prog0: progi@0 {
#clock-cells = <0>;
reg = <0>;
interrupts = <AT91_PMC_PCKRDY(0)>;
};
prog1: prog1 {
prog1: prog@1 {
#clock-cells = <0>;
reg = <1>;
interrupts = <AT91_PMC_PCKRDY(1)>;
};
prog2: prog2 {
prog2: prog@2 {
#clock-cells = <0>;
reg = <2>;
interrupts = <AT91_PMC_PCKRDY(2)>;
};
prog3: prog3 {
prog3: prog@3 {
#clock-cells = <0>;
reg = <3>;
interrupts = <AT91_PMC_PCKRDY(3)>;
@@ -665,49 +678,49 @@
#address-cells = <1>;
#size-cells = <0>;
uhpck: uhpck {
uhpck: uhpck@6 {
#clock-cells = <0>;
reg = <6>;
clocks = <&usb>;
};
udpck: udpck {
udpck: udpck@7 {
#clock-cells = <0>;
reg = <7>;
clocks = <&usb>;
};
pck0: pck0 {
pck0: pck@8 {
#clock-cells = <0>;
reg = <8>;
clocks = <&prog0>;
};
pck1: pck1 {
pck1: pck@9 {
#clock-cells = <0>;
reg = <9>;
clocks = <&prog1>;
};
pck2: pck2 {
pck2: pck@10 {
#clock-cells = <0>;
reg = <10>;
clocks = <&prog2>;
};
pck3: pck3 {
pck3: pck@11 {
#clock-cells = <0>;
reg = <11>;
clocks = <&prog3>;
};
hclk0: hclk0 {
hclk0: hclk@16 {
#clock-cells = <0>;
reg = <16>;
clocks = <&mck>;
};
hclk1: hclk1 {
hclk1: hclk@17 {
#clock-cells = <0>;
reg = <17>;
clocks = <&mck>;
@@ -719,98 +732,102 @@
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mck>;
u-boot,dm-pre-reloc;
pioA_clk: pioA_clk {
pioA_clk: pioA_clk@2 {
#clock-cells = <0>;
reg = <2>;
u-boot,dm-pre-reloc;
};
pioB_clk: pioB_clk {
pioB_clk: pioB_clk@3 {
#clock-cells = <0>;
reg = <3>;
u-boot,dm-pre-reloc;
};
pioC_clk: pioC_clk {
pioC_clk: pioC_clk@4 {
#clock-cells = <0>;
reg = <4>;
u-boot,dm-pre-reloc;
};
usart0_clk: usart0_clk {
usart0_clk: usart0_clk@6 {
#clock-cells = <0>;
reg = <6>;
};
usart1_clk: usart1_clk {
usart1_clk: usart1_clk@7 {
#clock-cells = <0>;
reg = <7>;
};
usart2_clk: usart2_clk {
usart2_clk: usart2_clk@8 {
#clock-cells = <0>;
reg = <8>;
};
mci0_clk: mci0_clk {
mci0_clk: mci0_clk@9 {
#clock-cells = <0>;
reg = <9>;
};
udc_clk: udc_clk {
udc_clk: udc_clk@10 {
#clock-cells = <0>;
reg = <10>;
};
twi0_clk: twi0_clk {
twi0_clk: twi0_clk@11 {
reg = <11>;
#clock-cells = <0>;
};
spi0_clk: spi0_clk {
spi0_clk: spi0_clk@12 {
#clock-cells = <0>;
reg = <12>;
};
spi1_clk: spi1_clk {
spi1_clk: spi1_clk@13 {
#clock-cells = <0>;
reg = <13>;
};
ssc0_clk: ssc0_clk {
ssc0_clk: ssc0_clk@14 {
#clock-cells = <0>;
reg = <14>;
};
ssc1_clk: ssc1_clk {
ssc1_clk: ssc1_clk@15 {
#clock-cells = <0>;
reg = <15>;
};
ssc2_clk: ssc2_clk {
ssc2_clk: ssc2_clk@16 {
#clock-cells = <0>;
reg = <16>;
};
tc0_clk: tc0_clk {
tc0_clk: tc0_clk@17 {
#clock-cells = <0>;
reg = <17>;
};
tc1_clk: tc1_clk {
tc1_clk: tc1_clk@18 {
#clock-cells = <0>;
reg = <18>;
};
tc2_clk: tc2_clk {
tc2_clk: tc2_clk@19 {
#clock-cells = <0>;
reg = <19>;
};
ohci_clk: ohci_clk {
ohci_clk: ohci_clk@20 {
#clock-cells = <0>;
reg = <20>;
};
lcd_clk: lcd_clk {
lcd_clk: lcd_clk@21 {
#clock-cells = <0>;
reg = <21>;
};

View File

@@ -0,0 +1,211 @@
/*
* at91sam9261ek.dts - Device Tree file for Atmel at91sam9261 reference board
*
* Copyright (C) 2013 Jean-Jacques Hiblot <jjhiblot@traphandler.com>
*
* Licensed under GPLv2 only.
*/
/dts-v1/;
#include "at91sam9261.dtsi"
/ {
model = "Atmel at91sam9261ek";
compatible = "atmel,at91sam9261ek", "atmel,at91sam9261", "atmel,at91sam9";
chosen {
bootargs = "rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs rw";
stdout-path = "serial0:115200n8";
};
memory {
reg = <0x20000000 0x4000000>;
};
clocks {
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <18432000>;
};
};
ahb {
usb0: ohci@00500000 {
status = "okay";
};
fb0: fb@0x00600000 {
display = <&display0>;
atmel,power-control-gpio = <&pioA 12 GPIO_ACTIVE_LOW>;
status = "okay";
display0: display {
bits-per-pixel = <16>;
atmel,lcdcon-backlight;
atmel,dmacon = <0x1>;
atmel,lcdcon2 = <0x80008002>;
atmel,guard-time = <1>;
atmel,lcd-wiring-mode = "BRG";
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <4965000>;
hactive = <240>;
vactive = <320>;
hback-porch = <1>;
hfront-porch = <33>;
vback-porch = <1>;
vfront-porch = <0>;
hsync-len = <5>;
vsync-len = <1>;
hsync-active = <1>;
vsync-active = <1>;
};
};
};
};
nand0: nand@40000000 {
nand-bus-width = <8>;
nand-ecc-mode = "soft";
nand-on-flash-bbt;
status = "okay";
at91bootstrap@0 {
label = "at91bootstrap";
reg = <0x0 0x40000>;
};
bootloader@40000 {
label = "bootloader";
reg = <0x40000 0x80000>;
};
bootloaderenv@c0000 {
label = "bootloader env";
reg = <0xc0000 0xc0000>;
};
dtb@180000 {
label = "device tree";
reg = <0x180000 0x80000>;
};
kernel@200000 {
label = "kernel";
reg = <0x200000 0x600000>;
};
rootfs@800000 {
label = "rootfs";
reg = <0x800000 0x0f800000>;
};
};
apb {
usb1: gadget@fffa4000 {
atmel,vbus-gpio = <&pioB 29 GPIO_ACTIVE_HIGH>;
status = "okay";
};
spi0: spi@fffc8000 {
cs-gpios = <&pioA 3 0>, <0>, <&pioA 28 0>, <0>;
status = "okay";
mtd_dataflash@0 {
compatible = "atmel,at45", "atmel,dataflash";
reg = <0>;
spi-max-frequency = <15000000>;
};
tsc2046@0 {
reg = <2>;
compatible = "ti,ads7843";
interrupts-extended = <&pioC 2 IRQ_TYPE_EDGE_BOTH>;
spi-max-frequency = <3000000>;
pendown-gpio = <&pioC 2 GPIO_ACTIVE_HIGH>;
ti,x-min = /bits/ 16 <150>;
ti,x-max = /bits/ 16 <3830>;
ti,y-min = /bits/ 16 <190>;
ti,y-max = /bits/ 16 <3830>;
ti,vref-delay-usecs = /bits/ 16 <450>;
ti,x-plate-ohms = /bits/ 16 <450>;
ti,y-plate-ohms = /bits/ 16 <250>;
ti,pressure-max = /bits/ 16 <15000>;
ti,debounce-rep = /bits/ 16 <0>;
ti,debounce-tol = /bits/ 16 <65535>;
ti,debounce-max = /bits/ 16 <1>;
wakeup-source;
};
};
dbgu: serial@fffff200 {
status = "okay";
};
watchdog@fffffd40 {
status = "okay";
};
};
};
leds {
compatible = "gpio-leds";
ds8 {
label = "ds8";
gpios = <&pioA 13 GPIO_ACTIVE_LOW>;
linux,default-trigger = "none";
};
ds7 {
label = "ds7";
gpios = <&pioA 14 GPIO_ACTIVE_LOW>;
linux,default-trigger = "nand-disk";
};
ds1 {
label = "ds1";
gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
};
gpio_keys {
compatible = "gpio-keys";
button_0 {
label = "button_0";
gpios = <&pioA 27 GPIO_ACTIVE_LOW>;
linux,code = <256>;
wakeup-source;
};
button_1 {
label = "button_1";
gpios = <&pioA 26 GPIO_ACTIVE_LOW>;
linux,code = <257>;
wakeup-source;
};
button_2 {
label = "button_2";
gpios = <&pioA 25 GPIO_ACTIVE_LOW>;
linux,code = <258>;
wakeup-source;
};
button_3 {
label = "button_3";
gpios = <&pioA 24 GPIO_ACTIVE_LOW>;
linux,code = <259>;
wakeup-source;
};
};
};

View File

@@ -32,6 +32,7 @@
ssc0 = &ssc0;
ssc1 = &ssc1;
pwm0 = &pwm0;
spi0 = &spi0;
};
cpus {

View File

@@ -87,7 +87,7 @@
cs-gpios = <&pioA 5 0>, <0>, <0>, <0>;
mtd_dataflash@0 {
compatible = "atmel,at45", "atmel,dataflash";
spi-max-frequency = <50000000>;
spi-max-frequency = <15000000>;
reg = <0>;
};
};

View File

@@ -99,7 +99,7 @@
cs-gpios = <0>, <&pioC 11 0>, <0>, <0>;
mtd_dataflash@0 {
compatible = "atmel,at45", "atmel,dataflash";
spi-max-frequency = <50000000>;
spi-max-frequency = <15000000>;
reg = <1>;
};
};

View File

@@ -34,6 +34,7 @@
ssc0 = &ssc0;
ssc1 = &ssc1;
pwm0 = &pwm0;
spi0 = &spi0;
};
cpus {

View File

@@ -0,0 +1,60 @@
/*
* at91sam9xe.dtsi - Device Tree Include file for AT91SAM9XE family SoC
*
* Copyright (C) 2015 Atmel,
* 2015 Alexandre Belloni <alexandre.Belloni@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "at91sam9260.dtsi"
/ {
model = "Atmel AT91SAM9XE family SoC";
compatible = "atmel,at91sam9xe", "atmel,at91sam9260";
sram0: sram@002ff000 {
status = "disabled";
};
sram1: sram@00300000 {
compatible = "mmio-sram";
reg = <0x00300000 0x4000>;
};
};

View File

@@ -0,0 +1,94 @@
/*
* ethernut5.dts - Device Tree file for Ethernut 5 board
*
* Copyright (C) 2012 egnite GmbH <info@egnite.de>
*
* Licensed under GPLv2.
*/
/dts-v1/;
#include "at91sam9xe.dtsi"
/ {
model = "Ethernut 5";
compatible = "egnite,ethernut5", "atmel,at91sam9260", "atmel,at91sam9";
chosen {
bootargs = "console=ttyS0,115200 root=/dev/mtdblock0 rw rootfstype=jffs2";
};
memory {
reg = <0x20000000 0x08000000>;
};
clocks {
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <18432000>;
};
};
ahb {
apb {
dbgu: serial@fffff200 {
status = "okay";
};
usart0: serial@fffb0000 {
status = "okay";
};
usart1: serial@fffb4000 {
status = "okay";
};
macb0: ethernet@fffc4000 {
phy-mode = "rmii";
status = "okay";
};
usb1: gadget@fffa4000 {
atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
nand0: nand@40000000 {
nand-bus-width = <8>;
nand-ecc-mode = "soft";
nand-on-flash-bbt;
status = "okay";
gpios = <0
&pioC 14 GPIO_ACTIVE_HIGH
0
>;
root@0 {
label = "root";
reg = <0x0 0x08000000>;
};
data@20000 {
label = "data";
reg = <0x08000000 0x38000000>;
};
};
usb0: ohci@00500000 {
num-ports = <2>;
status = "okay";
};
};
i2c-gpio-0 {
status = "okay";
pcf8563@50 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
};

View File

@@ -0,0 +1,162 @@
/*
* DTS File for HiSilicon Poplar Development Board
*
* Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
*
* Released under the GPLv2 only.
* SPDX-License-Identifier: GPL-2.0
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "hi3798cv200.dtsi"
/ {
model = "HiSilicon Poplar Development Board";
compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200";
aliases {
serial0 = &uart0;
serial2 = &uart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
leds {
compatible = "gpio-leds";
user-led0 {
label = "USER-LED0";
gpios = <&gpio6 3 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
user-led1 {
label = "USER-LED1";
gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
linux,default-trigger = "mmc0";
default-state = "off";
};
user-led2 {
label = "USER-LED2";
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
linux,default-trigger = "none";
default-state = "off";
};
user-led3 {
label = "USER-LED3";
gpios = <&gpio10 6 GPIO_ACTIVE_LOW>;
linux,default-trigger = "cpu0";
default-state = "off";
};
};
};
&gmac1 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
phy-handle = <&eth_phy1>;
phy-mode = "rgmii";
hisilicon,phy-reset-delays-us = <10000 10000 30000>;
eth_phy1: phy@3 {
reg = <3>;
};
};
&gpio1 {
status = "okay";
gpio-line-names = "LS-GPIO-E", "",
"", "",
"", "LS-GPIO-F",
"", "LS-GPIO-J";
};
&gpio2 {
status = "okay";
gpio-line-names = "LS-GPIO-H", "LS-GPIO-I",
"LS-GPIO-L", "LS-GPIO-G",
"LS-GPIO-K", "",
"", "";
};
&gpio3 {
status = "okay";
gpio-line-names = "", "",
"", "",
"LS-GPIO-C", "",
"", "LS-GPIO-B";
};
&gpio4 {
status = "okay";
gpio-line-names = "", "",
"", "",
"", "LS-GPIO-D",
"", "";
};
&gpio5 {
status = "okay";
gpio-line-names = "", "USER-LED-1",
"USER-LED-2", "",
"", "LS-GPIO-A",
"", "";
};
&gpio6 {
status = "okay";
gpio-line-names = "", "",
"", "USER-LED-0",
"", "",
"", "";
};
&gpio10 {
status = "okay";
gpio-line-names = "", "",
"", "",
"", "",
"USER-LED-3", "";
};
&i2c0 {
status = "okay";
label = "LS-I2C0";
};
&i2c2 {
status = "okay";
label = "LS-I2C1";
};
&ir {
status = "okay";
};
&spi0 {
status = "okay";
label = "LS-SPI0";
};
&uart0 {
status = "okay";
};
&uart2 {
status = "okay";
label = "LS-UART0";
};
/* No optional LS-UART1 on Low Speed Expansion Connector. */

View File

@@ -0,0 +1,29 @@
/*
* U-Boot addition to:
* 1) use platform data for the console
* 2) provide support for the generic-ehci USB driver currently not available
* in the linux kernel (8/May/2017).
*
* (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
&soc {
usb2: ehci@9890000 {
compatible = "generic-ehci";
reg = <0x9890000 0x100>;
status = "okay";
};
};
&uart0 {
status = "disabled";
};
/{
chosen {
stdout-path = "";
};
};

View File

@@ -0,0 +1,411 @@
/*
* DTS File for HiSilicon Hi3798cv200 SoC.
*
* Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
*
* Released under the GPLv2 only.
* SPDX-License-Identifier: GPL-2.0
*/
#include <dt-bindings/clock/histb-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/ti-syscon.h>
/ {
compatible = "hisilicon,hi3798cv200";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x0>;
enable-method = "psci";
};
cpu@1 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x1>;
enable-method = "psci";
};
cpu@2 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x2>;
enable-method = "psci";
};
cpu@3 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x3>;
enable-method = "psci";
};
};
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */
<0x0 0xf1002000 0x0 0x100>; /* GICC */
#address-cells = <0>;
#interrupt-cells = <3>;
interrupt-controller;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>;
};
soc: soc@f0000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xf0000000 0x10000000>;
crg: clock-reset-controller@8a22000 {
compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";
reg = <0x8a22000 0x1000>;
#clock-cells = <1>;
#reset-cells = <2>;
gmacphyrst: reset-controller {
compatible = "ti,syscon-reset";
#reset-cells = <1>;
ti,reset-bits =
<0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR |
DEASSERT_SET|STATUS_NONE)>,
<0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR |
DEASSERT_SET|STATUS_NONE)>;
};
};
sysctrl: system-controller@8000000 {
compatible = "hisilicon,hi3798cv200-sysctrl", "syscon";
reg = <0x8000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <2>;
};
uart0: serial@8b00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x8b00000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysctrl HISTB_UART0_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
uart2: serial@8b02000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x8b02000 0x1000>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_UART2_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
i2c0: i2c@8b10000 {
compatible = "hisilicon,hix5hd2-i2c";
reg = <0x8b10000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
clocks = <&crg HISTB_I2C0_CLK>;
status = "disabled";
};
i2c1: i2c@8b11000 {
compatible = "hisilicon,hix5hd2-i2c";
reg = <0x8b11000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
clocks = <&crg HISTB_I2C1_CLK>;
status = "disabled";
};
i2c2: i2c@8b12000 {
compatible = "hisilicon,hix5hd2-i2c";
reg = <0x8b12000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
clocks = <&crg HISTB_I2C2_CLK>;
status = "disabled";
};
i2c3: i2c@8b13000 {
compatible = "hisilicon,hix5hd2-i2c";
reg = <0x8b13000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
clocks = <&crg HISTB_I2C3_CLK>;
status = "disabled";
};
i2c4: i2c@8b14000 {
compatible = "hisilicon,hix5hd2-i2c";
reg = <0x8b14000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
clocks = <&crg HISTB_I2C4_CLK>;
status = "disabled";
};
spi0: spi@8b1a000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x8b1a000 0x1000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
num-cs = <1>;
cs-gpios = <&gpio7 1 0>;
clocks = <&crg HISTB_SPI0_CLK>;
clock-names = "apb_pclk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
emmc: mmc@9830000 {
compatible = "snps,dw-mshc";
reg = <0x9830000 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_MMC_CIU_CLK>,
<&crg HISTB_MMC_BIU_CLK>;
clock-names = "ciu", "biu";
};
gpio0: gpio@8b20000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b20000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio1: gpio@8b21000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b21000 0x1000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio2: gpio@8b22000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b22000 0x1000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio3: gpio@8b23000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b23000 0x1000>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio4: gpio@8b24000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b24000 0x1000>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio5: gpio@8004000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8004000 0x1000>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio6: gpio@8b26000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b26000 0x1000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio7: gpio@8b27000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b27000 0x1000>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio8: gpio@8b28000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b28000 0x1000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio9: gpio@8b29000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b29000 0x1000>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio10: gpio@8b2a000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b2a000 0x1000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio11: gpio@8b2b000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b2b000 0x1000>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio12: gpio@8b2c000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b2c000 0x1000>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gmac0: ethernet@9840000 {
compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
reg = <0x9840000 0x1000>,
<0x984300c 0x4>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_ETH0_MAC_CLK>,
<&crg HISTB_ETH0_MACIF_CLK>;
clock-names = "mac_core", "mac_ifc";
resets = <&crg 0xcc 8>,
<&crg 0xcc 10>,
<&gmacphyrst 0>;
reset-names = "mac_core", "mac_ifc", "phy";
status = "disabled";
};
gmac1: ethernet@9841000 {
compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
reg = <0x9841000 0x1000>,
<0x9843010 0x4>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_ETH1_MAC_CLK>,
<&crg HISTB_ETH1_MACIF_CLK>;
clock-names = "mac_core", "mac_ifc";
resets = <&crg 0xcc 9>,
<&crg 0xcc 11>,
<&gmacphyrst 1>;
reset-names = "mac_core", "mac_ifc", "phy";
status = "disabled";
};
ir: ir@8001000 {
compatible = "hisilicon,hix5hd2-ir";
reg = <0x8001000 0x1000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysctrl HISTB_IR_CLK>;
status = "disabled";
};
};
};

View File

@@ -0,0 +1,115 @@
/*
* Copyright 2013 CompuLab Ltd.
*
* Author: Valentin Raevsky <valentin@compulab.co.il>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx6q.dtsi"
/ {
model = "CompuLab CM-FX6";
compatible = "compulab,cm-fx6", "fsl,imx6q";
memory {
reg = <0x10000000 0x80000000>;
};
leds {
compatible = "gpio-leds";
heartbeat-led {
label = "Heartbeat";
gpios = <&gpio2 31 0>;
linux,default-trigger = "heartbeat";
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
status = "okay";
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
status = "okay";
};
&iomuxc {
imx6q-cm-fx6 {
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
>;
};
};
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&sata {
status = "okay";
};
&usdhc3 {
status = "okay";
};

View File

@@ -0,0 +1,15 @@
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
/{
soc {
u-boot,dm-pre-reloc;
};
};
&i2c1 {
u-boot,dm-pre-reloc;
};

View File

@@ -0,0 +1,19 @@
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
/{
soc {
u-boot,dm-pre-reloc;
};
};
&i2c0 {
u-boot,dm-pre-reloc;
};
&i2c1 {
u-boot,dm-pre-reloc;
};

View File

@@ -18,6 +18,11 @@
chosen {
stdout-path = &uart0;
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
};
&mdio {
@@ -32,6 +37,10 @@
phy-handle = <&ethphy0>;
};
&netcp {
status = "okay";
};
&spi1 {
status = "okay";

View File

@@ -0,0 +1,19 @@
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
/{
soc {
u-boot,dm-pre-reloc;
};
};
&i2c0 {
u-boot,dm-pre-reloc;
};
&i2c1 {
u-boot,dm-pre-reloc;
};

View File

@@ -0,0 +1,28 @@
/*
* Device Tree Source for Generic 66AK2G0X EVM
*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "keystone-k2g.dtsi"
/ {
compatible = "ti,k2g-generic", "ti,k2g", "ti,keystone";
model = "Texas Instruments 66AK2G02 Generic";
chosen {
stdout-path = &uart0;
};
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
};

View File

@@ -0,0 +1,19 @@
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
/{
soc {
u-boot,dm-pre-reloc;
};
};
&i2c0 {
u-boot,dm-pre-reloc;
};
&i2c1 {
u-boot,dm-pre-reloc;
};

View File

@@ -0,0 +1,36 @@
/*
* Device Tree Source for K2G Industrial Communication Engine EVM
*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "keystone-k2g.dtsi"
/ {
compatible = "ti,k2g-ice", "ti,k2g", "ti,keystone";
model = "Texas Instruments K2G Industrial Communication EVM";
chosen {
stdout-path = &uart0;
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>;
};
};
&mmc1 {
status = "okay";
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
};

View File

@@ -99,6 +99,7 @@ netcp: netcp@4000000 {
reg = <0x2620110 0x8>;
reg-names = "efuse";
compatible = "ti,netcp-1.0";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
/* power-domains = <&k2g_pds K2G_DEV_NSS0>; */

View File

@@ -9,7 +9,6 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"
/ {
model = "Texas Instruments K2G SoC";
@@ -17,6 +16,8 @@
#size-cells = <1>;
interrupt-parent = <&gic>;
chosen { };
aliases {
serial0 = &uart0;
spi0 = &spi0;
@@ -29,11 +30,6 @@
i2c2 = &i2c2;
};
memory {
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;

View File

@@ -71,6 +71,14 @@
reg = <0x0 0x10000000 0x0 0x200000>;
no-map;
};
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0xbc00000>;
alignment = <0x0 0x400000>;
linux,cma-default;
};
};
cpus {
@@ -233,7 +241,7 @@
};
i2c_A: i2c@8500 {
compatible = "amlogic,meson-gxbb-i2c";
compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
reg = <0x0 0x08500 0x0 0x20>;
interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
@@ -255,6 +263,14 @@
status = "disabled";
};
saradc: adc@8680 {
compatible = "amlogic,meson-saradc";
reg = <0x0 0x8680 0x0 0x34>;
#io-channel-cells = <1>;
interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
pwm_ef: pwm@86c0 {
compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
reg = <0x0 0x086c0 0x0 0x10>;
@@ -271,7 +287,7 @@
};
i2c_B: i2c@87c0 {
compatible = "amlogic,meson-gxbb-i2c";
compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
reg = <0x0 0x087c0 0x0 0x20>;
interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
@@ -280,7 +296,7 @@
};
i2c_C: i2c@87e0 {
compatible = "amlogic,meson-gxbb-i2c";
compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
reg = <0x0 0x087e0 0x0 0x20>;
interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
@@ -288,6 +304,14 @@
status = "disabled";
};
spifc: spi@8c80 {
compatible = "amlogic,meson-gx-spifc", "amlogic,meson-gxbb-spifc";
reg = <0x0 0x08c80 0x0 0x80>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
watchdog@98d0 {
compatible = "amlogic,meson-gx-wdt", "amlogic,meson-gxbb-wdt";
reg = <0x0 0x098d0 0x0 0x10>;
@@ -309,7 +333,7 @@
};
sram: sram@c8000000 {
compatible = "amlogic,meson-gxbb-sram", "mmio-sram";
compatible = "amlogic,meson-gx-sram", "amlogic,meson-gxbb-sram", "mmio-sram";
reg = <0x0 0xc8000000 0x0 0x14000>;
#address-cells = <1>;
@@ -317,12 +341,12 @@
ranges = <0 0x0 0xc8000000 0x14000>;
cpu_scp_lpri: scp-shmem@0 {
compatible = "amlogic,meson-gxbb-scp-shmem";
compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
reg = <0x13000 0x400>;
};
cpu_scp_hpri: scp-shmem@200 {
compatible = "amlogic,meson-gxbb-scp-shmem";
compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
reg = <0x13400 0x400>;
};
};
@@ -334,6 +358,13 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
clkc_AO: clock-controller@040 {
compatible = "amlogic,gx-aoclkc", "amlogic,gxbb-aoclkc";
reg = <0x0 0x00040 0x0 0x4>;
#clock-cells = <1>;
#reset-cells = <1>;
};
uart_AO: serial@4c0 {
compatible = "amlogic,meson-uart";
reg = <0x0 0x004c0 0x0 0x14>;
@@ -350,8 +381,24 @@
status = "disabled";
};
i2c_AO: i2c@500 {
compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
reg = <0x0 0x500 0x0 0x20>;
interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pwm_AO_ab: pwm@550 {
compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
reg = <0x0 0x00550 0x0 0x10>;
#pwm-cells = <3>;
status = "disabled";
};
ir: ir@580 {
compatible = "amlogic,meson-gxbb-ir";
compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir";
reg = <0x0 0x00580 0x0 0x40>;
interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
@@ -365,13 +412,12 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
rng {
hwrng: rng {
compatible = "amlogic,meson-rng";
reg = <0x0 0x0 0x0 0x4>;
};
};
hiubus: hiubus@c883c000 {
compatible = "simple-bus";
reg = <0x0 0xc883c000 0x0 0x2000>;
@@ -395,7 +441,6 @@
0x0 0xc8834540 0x0 0x4>;
interrupts = <0 8 1>;
interrupt-names = "macirq";
phy-mode = "rgmii";
status = "disabled";
};
@@ -442,6 +487,38 @@
cvbs_vdac_port: port@0 {
reg = <0>;
};
/* HDMI-TX output port */
hdmi_tx_port: port@1 {
reg = <1>;
hdmi_tx_out: endpoint {
remote-endpoint = <&hdmi_tx_in>;
};
};
};
hdmi_tx: hdmi-tx@c883a000 {
compatible = "amlogic,meson-gx-dw-hdmi";
reg = <0x0 0xc883a000 0x0 0x1c>;
interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
/* VPU VENC Input */
hdmi_tx_venc_port: port@0 {
reg = <0>;
hdmi_tx_in: endpoint {
remote-endpoint = <&hdmi_tx_out>;
};
};
/* TMDS Output */
hdmi_tx_tmds_port: port@1 {
reg = <1>;
};
};
};
};

View File

@@ -50,7 +50,7 @@
/ {
compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
model = "Hardkernel ODROID-C2";
aliases {
serial0 = &uart_AO;
};
@@ -96,7 +96,7 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio_ao GPIOAO_12 GPIO_ACTIVE_HIGH>;
gpio = <&gpio GPIOY_12 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
@@ -152,6 +152,13 @@
pinctrl-0 = <&eth_rgmii_pins>;
pinctrl-names = "default";
phy-handle = <&eth_phy0>;
phy-mode = "rgmii";
snps,reset-gpio = <&gpio GPIOZ_14 0>;
snps,reset-delays-us = <0 10000 1000000>;
snps,reset-active-low;
amlogic,tx-delay-ns = <2>;
mdio {
compatible = "snps,dwmac-mdio";
@@ -165,6 +172,57 @@
};
};
&pinctrl_aobus {
gpio-line-names = "UART TX", "UART RX", "VCCK En", "TF 3V3/1V8 En",
"USB HUB nRESET", "USB OTG Power En",
"J7 Header Pin2", "IR In", "J7 Header Pin4",
"J7 Header Pin6", "J7 Header Pin5", "J7 Header Pin7",
"HDMI CEC", "SYS LED";
};
&pinctrl_periphs {
gpio-line-names = /* Bank GPIOZ */
"Eth MDIO", "Eth MDC", "Eth RGMII RX Clk",
"Eth RX DV", "Eth RX D0", "Eth RX D1", "Eth RX D2",
"Eth RX D3", "Eth RGMII TX Clk", "Eth TX En",
"Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3",
"Eth PHY nRESET", "Eth PHY Intc",
/* Bank GPIOH */
"HDMI HPD", "HDMI DDC SDA", "HDMI DDC SCL", "",
/* Bank BOOT */
"eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", "eMMC D4",
"eMMC D5", "eMMC D6", "eMMC D7", "eMMC Clk",
"eMMC Reset", "eMMC CMD",
"", "", "", "", "", "", "",
/* Bank CARD */
"SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
"SDCard D3", "SDCard D2", "SDCard Det",
/* Bank GPIODV */
"", "", "", "", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "", "",
"I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK",
"PWM D", "PWM B",
/* Bank GPIOY */
"Revision Bit0", "Revision Bit1", "",
"J2 Header Pin35", "", "", "", "J2 Header Pin36",
"J2 Header Pin31", "", "", "", "TF VDD En",
"J2 Header Pin32", "J2 Header Pin26", "", "",
/* Bank GPIOX */
"J2 Header Pin29", "J2 Header Pin24",
"J2 Header Pin23", "J2 Header Pin22",
"J2 Header Pin21", "J2 Header Pin18",
"J2 Header Pin33", "J2 Header Pin19",
"J2 Header Pin16", "J2 Header Pin15",
"J2 Header Pin12", "J2 Header Pin13",
"J2 Header Pin8", "J2 Header Pin10",
"", "", "", "", "",
"J2 Header Pin11", "", "J2 Header Pin7",
/* Bank GPIOCLK */
"", "", "", "",
/* GPIO_TEST_N */
"";
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
@@ -177,6 +235,21 @@
pinctrl-names = "default";
};
&gpio_ao {
/*
* WARNING: The USB Hub on the Odroid-C2 needs a reset signal
* to be turned high in order to be detected by the USB Controller
* This signal should be handled by a USB specific power sequence
* in order to reset the Hub when USB bus is powered down.
*/
usb-hub {
gpio-hog;
gpios = <GPIOAO_4 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "usb-hub-reset";
};
};
&usb0_phy {
status = "okay";
phy-supply = <&usb_otg_pwr>;
@@ -194,6 +267,11 @@
status = "okay";
};
&saradc {
status = "okay";
vref-supply = <&vcc1v8>;
};
/* SD */
&sd_emmc_b {
status = "okay";

View File

@@ -97,17 +97,6 @@
};
};
&cbus {
spifc: spi@8c80 {
compatible = "amlogic,meson-gxbb-spifc";
reg = <0x0 0x08c80 0x0 0x80>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_SPI>;
status = "disabled";
};
};
&ethmac {
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
@@ -129,6 +118,7 @@
reg-names = "mux", "pull", "gpio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_aobus 0 0 14>;
};
uart_ao_a_pins: uart_ao_a {
@@ -203,30 +193,62 @@
function = "pwm_ao_b";
};
};
};
clkc_AO: clock-controller@040 {
compatible = "amlogic,gxbb-aoclkc";
reg = <0x0 0x00040 0x0 0x4>;
#clock-cells = <1>;
#reset-cells = <1>;
};
i2s_am_clk_pins: i2s_am_clk {
mux {
groups = "i2s_am_clk";
function = "i2s_out_ao";
};
};
pwm_ab_AO: pwm@550 {
compatible = "amlogic,meson-gxbb-pwm";
reg = <0x0 0x0550 0x0 0x10>;
#pwm-cells = <3>;
status = "disabled";
};
i2s_out_ao_clk_pins: i2s_out_ao_clk {
mux {
groups = "i2s_out_ao_clk";
function = "i2s_out_ao";
};
};
i2c_AO: i2c@500 {
compatible = "amlogic,meson-gxbb-i2c";
reg = <0x0 0x500 0x0 0x20>;
interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_AO_I2C>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
i2s_out_lr_clk_pins: i2s_out_lr_clk {
mux {
groups = "i2s_out_lr_clk";
function = "i2s_out_ao";
};
};
i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
mux {
groups = "i2s_out_ch01_ao";
function = "i2s_out_ao";
};
};
i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
mux {
groups = "i2s_out_ch23_ao";
function = "i2s_out_ao";
};
};
i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
mux {
groups = "i2s_out_ch45_ao";
function = "i2s_out_ao";
};
};
spdif_out_ao_6_pins: spdif_out_ao_6 {
mux {
groups = "spdif_out_ao_6";
function = "spdif_out_ao";
};
};
spdif_out_ao_13_pins: spdif_out_ao_13 {
mux {
groups = "spdif_out_ao_13";
function = "spdif_out_ao";
};
};
};
};
@@ -245,6 +267,7 @@
reg-names = "mux", "pull", "pull-enable", "gpio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_periphs 0 14 120>;
};
emmc_pins: emmc {
@@ -467,6 +490,34 @@
function = "hdmi_i2c";
};
};
i2sout_ch23_y_pins: i2sout_ch23_y {
mux {
groups = "i2sout_ch23_y";
function = "i2s_out";
};
};
i2sout_ch45_y_pins: i2sout_ch45_y {
mux {
groups = "i2sout_ch45_y";
function = "i2s_out";
};
};
i2sout_ch67_y_pins: i2sout_ch67_y {
mux {
groups = "i2sout_ch67_y";
function = "i2s_out";
};
};
spdif_out_y_pins: spdif_out_y {
mux {
groups = "spdif_out_y";
function = "spdif_out";
};
};
};
};
@@ -478,10 +529,51 @@
};
};
&apb {
mali: gpu@c0000 {
compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
reg = <0x0 0xc0000 0x0 0x40000>;
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gp", "gpmmu", "pp", "pmu",
"pp0", "ppmmu0", "pp1", "ppmmu1",
"pp2", "ppmmu2";
clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
clock-names = "bus", "core";
/*
* Mali clocking is provided by two identical clock paths
* MALI_0 and MALI_1 muxed to a single clock by a glitch
* free mux to safely change frequency while running.
*/
assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
<&clkc CLKID_MALI_0>,
<&clkc CLKID_MALI>; /* Glitch free mux */
assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
<0>, /* Do Nothing */
<&clkc CLKID_MALI_0>;
assigned-clock-rates = <0>, /* Do Nothing */
<666666666>,
<0>; /* Do Nothing */
};
};
&i2c_A {
clocks = <&clkc CLKID_I2C>;
};
&i2c_AO {
clocks = <&clkc CLKID_AO_I2C>;
};
&i2c_B {
clocks = <&clkc CLKID_I2C>;
};
@@ -490,6 +582,16 @@
clocks = <&clkc CLKID_I2C>;
};
&saradc {
compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
clocks = <&xtal>,
<&clkc CLKID_SAR_ADC>,
<&clkc CLKID_SANA>,
<&clkc CLKID_SAR_ADC_CLK>,
<&clkc CLKID_SAR_ADC_SEL>;
clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
};
&sd_emmc_a {
clocks = <&clkc CLKID_SD_EMMC_A>,
<&xtal>,
@@ -511,6 +613,27 @@
clock-names = "core", "clkin0", "clkin1";
};
&spifc {
clocks = <&clkc CLKID_SPI>;
};
&vpu {
compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
};
&hwrng {
clocks = <&clkc CLKID_RNG0>;
clock-names = "core";
};
&hdmi_tx {
compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
resets = <&reset RESET_HDMITX_CAPB3>,
<&reset RESET_HDMI_SYSTEM_RESET>,
<&reset RESET_HDMI_TX>;
reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
clocks = <&clkc CLKID_HDMI_PCLK>,
<&clkc CLKID_CLK81>,
<&clkc CLKID_GCLK_VENCI_INT0>;
clock-names = "isfr", "iahb", "venci";
};

View File

@@ -52,3 +52,11 @@
u-boot,dm-spl;
};
};
&gpio2 {
u-boot,dm-spl;
};
&gpio7 {
u-boot,dm-spl;
};

View File

@@ -0,0 +1,376 @@
/*
* Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board
*
* Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2016 Cogent Embedded, Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/dts-v1/;
#include "r8a7795.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Renesas H3ULCB board based on r8a7795";
compatible = "renesas,h3ulcb", "renesas,r8a7795";
aliases {
serial0 = &scif2;
ethernet0 = &avb;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
memory@500000000 {
device_type = "memory";
reg = <0x5 0x00000000 0x0 0x40000000>;
};
memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x0 0x40000000>;
};
memory@700000000 {
device_type = "memory";
reg = <0x7 0x00000000 0x0 0x40000000>;
};
leds {
compatible = "gpio-leds";
led5 {
gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
};
led6 {
gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
};
};
keyboard {
compatible = "gpio-keys";
key-1 {
linux,code = <KEY_1>;
label = "SW3";
wakeup-source;
debounce-interval = <20>;
gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
};
};
x12_clk: x12 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
};
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator1 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vcc_sdhi0: regulator-vcc-sdhi0 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
audio_clkout: audio-clkout {
/*
* This is same as <&rcar_sound 0>
* but needed to avoid cs2000/rcar_sound probe dead-lock
*/
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <11289600>;
};
rsnd_ak4613: sound {
compatible = "simple-audio-card";
simple-audio-card,format = "left_j";
simple-audio-card,bitclock-master = <&sndcpu>;
simple-audio-card,frame-master = <&sndcpu>;
sndcpu: simple-audio-card,cpu {
sound-dai = <&rcar_sound>;
};
sndcodec: simple-audio-card,codec {
sound-dai = <&ak4613>;
};
};
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
scif2_pins: scif2 {
groups = "scif2_data_a";
function = "scif2";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_a";
function = "scif_clk";
};
i2c2_pins: i2c2 {
groups = "i2c2_a";
function = "i2c2";
};
avb_pins: avb {
groups = "avb_mdc";
function = "avb";
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
sdhi0_pins_uhs: sd0_uhs {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <1800>;
};
sdhi2_pins: sd2 {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
power-source = <3300>;
};
sdhi2_pins_uhs: sd2_uhs {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
power-source = <1800>;
};
sound_pins: sound {
groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
function = "ssi";
};
sound_clk_pins: sound-clk {
groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
"audio_clkout_a", "audio_clkout3_a";
function = "audio_clk";
};
usb1_pins: usb1 {
groups = "usb1";
function = "usb1";
};
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
};
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <100000>;
ak4613: codec@10 {
compatible = "asahi-kasei,ak4613";
#sound-dai-cells = <0>;
reg = <0x10>;
clocks = <&rcar_sound 3>;
asahi-kasei,in1-single-end;
asahi-kasei,in2-single-end;
asahi-kasei,out1-single-end;
asahi-kasei,out2-single-end;
asahi-kasei,out3-single-end;
asahi-kasei,out4-single-end;
asahi-kasei,out5-single-end;
asahi-kasei,out6-single-end;
};
cs2000: clk-multiplier@4f {
#clock-cells = <0>;
compatible = "cirrus,cs2000-cp";
reg = <0x4f>;
clocks = <&audio_clkout>, <&x12_clk>;
clock-names = "clk_in", "ref_clk";
assigned-clocks = <&cs2000>;
assigned-clock-rates = <24576000>; /* 1/1 divide */
};
};
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
#sound-dai-cells = <0>;
/* audio_clkout0/1/2/3 */
#clock-cells = <1>;
clock-frequency = <11289600>;
status = "okay";
/* update <audio_clk_b> to <cs2000> */
clocks = <&cpg CPG_MOD 1005>,
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&cs2000>,
<&audio_clk_c>,
<&cpg CPG_CORE R8A7795_CLK_S0D4>;
rcar_sound,dai {
dai0 {
playback = <&ssi0 &src0 &dvc0>;
capture = <&ssi1 &src1 &dvc1>;
};
};
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
sd-uhs-sdr50;
status = "okay";
};
&sdhi2 {
/* used for on-board 8bit eMMC */
pinctrl-0 = <&sdhi2_pins>;
pinctrl-1 = <&sdhi2_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
non-removable;
status = "okay";
};
&ssi1 {
shared-pin;
};
&wdt0 {
timeout-sec = <60>;
status = "okay";
};
&audio_clk_a {
clock-frequency = <22579200>;
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
status = "okay";
phy0: ethernet-phy@0 {
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
};
};
&usb2_phy1 {
pinctrl-0 = <&usb1_pins>;
pinctrl-names = "default";
status = "okay";
};
&ehci1 {
status = "okay";
};
&ohci1 {
status = "okay";
};

View File

@@ -0,0 +1,584 @@
/*
* Device Tree Source for the Salvator-X board
*
* Copyright (C) 2015 Renesas Electronics Corp.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/*
* SSI-AK4613
*
* This command is required when Playback/Capture
*
* amixer set "DVC Out" 100%
* amixer set "DVC In" 100%
*
* You can use Mute
*
* amixer set "DVC Out Mute" on
* amixer set "DVC In Mute" on
*
* You can use Volume Ramp
*
* amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
* amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
* amixer set "DVC Out Ramp" on
* aplay xxx.wav &
* amixer set "DVC Out" 80% // Volume Down
* amixer set "DVC Out" 100% // Volume Up
*/
/dts-v1/;
#include "r8a7795.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Renesas Salvator-X board based on r8a7795";
compatible = "renesas,salvator-x", "renesas,r8a7795";
aliases {
serial0 = &scif2;
serial1 = &scif1;
ethernet0 = &avb;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
x12_clk: x12 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
};
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator1 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vcc_sdhi0: regulator-vcc-sdhi0 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
vcc_sdhi3: regulator-vcc-sdhi3 {
compatible = "regulator-fixed";
regulator-name = "SDHI3 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi3: regulator-vccq-sdhi3 {
compatible = "regulator-gpio";
regulator-name = "SDHI3 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
vbus0_usb2: regulator-vbus0-usb2 {
compatible = "regulator-fixed";
regulator-name = "USB20_VBUS0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
audio_clkout: audio_clkout {
/*
* This is same as <&rcar_sound 0>
* but needed to avoid cs2000/rcar_sound probe dead-lock
*/
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <11289600>;
};
rsnd_ak4613: sound {
compatible = "simple-audio-card";
simple-audio-card,format = "left_j";
simple-audio-card,bitclock-master = <&sndcpu>;
simple-audio-card,frame-master = <&sndcpu>;
sndcpu: simple-audio-card,cpu {
sound-dai = <&rcar_sound>;
};
sndcodec: simple-audio-card,codec {
sound-dai = <&ak4613>;
};
};
vga-encoder {
compatible = "adi,adv7123";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7123_in: endpoint {
remote-endpoint = <&du_out_rgb>;
};
};
port@1 {
reg = <1>;
adv7123_out: endpoint {
remote-endpoint = <&vga_in>;
};
};
};
};
vga {
compatible = "vga-connector";
port {
vga_in: endpoint {
remote-endpoint = <&adv7123_out>;
};
};
};
};
&du {
pinctrl-0 = <&du_pins>;
pinctrl-names = "default";
status = "okay";
ports {
port@0 {
endpoint {
remote-endpoint = <&adv7123_in>;
};
};
port@3 {
lvds_connector: endpoint {
};
};
};
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
scif1_pins: scif1 {
groups = "scif1_data_a", "scif1_ctrl";
function = "scif1";
};
scif2_pins: scif2 {
groups = "scif2_data_a";
function = "scif2";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_a";
function = "scif_clk";
};
i2c2_pins: i2c2 {
groups = "i2c2_a";
function = "i2c2";
};
avb_pins: avb {
mux {
groups = "avb_link", "avb_phy_int", "avb_mdc",
"avb_mii";
function = "avb";
};
pins_mdc {
groups = "avb_mdc";
drive-strength = <24>;
};
pins_mii_tx {
pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
"PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
drive-strength = <12>;
};
};
du_pins: du {
groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0";
function = "du";
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
sdhi0_pins_uhs: sd0_uhs {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <1800>;
};
sdhi2_pins: sd2 {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
power-source = <3300>;
};
sdhi2_pins_uhs: sd2_uhs {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
power-source = <1800>;
};
sdhi3_pins: sd3 {
groups = "sdhi3_data4", "sdhi3_ctrl";
function = "sdhi3";
power-source = <3300>;
};
sdhi3_pins_uhs: sd3_uhs {
groups = "sdhi3_data4", "sdhi3_ctrl";
function = "sdhi3";
power-source = <1800>;
};
sound_pins: sound {
groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
function = "ssi";
};
sound_clk_pins: sound_clk {
groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
"audio_clkout_a", "audio_clkout3_a";
function = "audio_clk";
};
usb0_pins: usb0 {
groups = "usb0";
function = "usb0";
};
usb1_pins: usb1 {
mux {
groups = "usb1";
function = "usb1";
};
ovc {
pins = "GP_6_27";
bias-pull-up;
};
pwen {
pins = "GP_6_26";
bias-pull-down;
};
};
usb2_pins: usb2 {
groups = "usb2";
function = "usb2";
};
};
&scif1 {
pinctrl-0 = <&scif1_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
};
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <100000>;
ak4613: codec@10 {
compatible = "asahi-kasei,ak4613";
#sound-dai-cells = <0>;
reg = <0x10>;
clocks = <&rcar_sound 3>;
asahi-kasei,in1-single-end;
asahi-kasei,in2-single-end;
asahi-kasei,out1-single-end;
asahi-kasei,out2-single-end;
asahi-kasei,out3-single-end;
asahi-kasei,out4-single-end;
asahi-kasei,out5-single-end;
asahi-kasei,out6-single-end;
};
cs2000: clk_multiplier@4f {
#clock-cells = <0>;
compatible = "cirrus,cs2000-cp";
reg = <0x4f>;
clocks = <&audio_clkout>, <&x12_clk>;
clock-names = "clk_in", "ref_clk";
assigned-clocks = <&cs2000>;
assigned-clock-rates = <24576000>; /* 1/1 divide */
};
};
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
#sound-dai-cells = <0>;
/* audio_clkout0/1/2/3 */
#clock-cells = <1>;
clock-frequency = <11289600>;
status = "okay";
/* update <audio_clk_b> to <cs2000> */
clocks = <&cpg CPG_MOD 1005>,
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&cs2000>,
<&audio_clk_c>,
<&cpg CPG_CORE R8A7795_CLK_S0D4>;
rcar_sound,dai {
dai0 {
playback = <&ssi0 &src0 &dvc0>;
capture = <&ssi1 &src1 &dvc1>;
};
};
};
&sata {
status = "okay";
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
sd-uhs-sdr50;
status = "okay";
};
&sdhi2 {
/* used for on-board 8bit eMMC */
pinctrl-0 = <&sdhi2_pins>;
pinctrl-1 = <&sdhi2_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
non-removable;
status = "okay";
};
&sdhi3 {
pinctrl-0 = <&sdhi3_pins>;
pinctrl-1 = <&sdhi3_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi3>;
vqmmc-supply = <&vccq_sdhi3>;
cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
sd-uhs-sdr50;
status = "okay";
};
&ssi1 {
shared-pin;
};
&wdt0 {
timeout-sec = <60>;
status = "okay";
};
&audio_clk_a {
clock-frequency = <22579200>;
};
&i2c_dvfs {
status = "okay";
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
status = "okay";
phy0: ethernet-phy@0 {
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
};
};
&xhci0 {
status = "okay";
};
&usb2_phy0 {
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";
vbus-supply = <&vbus0_usb2>;
status = "okay";
};
&usb2_phy1 {
pinctrl-0 = <&usb1_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb2_phy2 {
pinctrl-0 = <&usb2_pins>;
pinctrl-names = "default";
status = "okay";
};
&ehci0 {
status = "okay";
};
&ehci1 {
status = "okay";
};
&ehci2 {
status = "okay";
};
&ohci0 {
status = "okay";
};
&ohci1 {
status = "okay";
};
&ohci2 {
status = "okay";
};
&hsusb {
status = "okay";
};
&pcie_bus_clk {
clock-frequency = <100000000>;
};
&pciec0 {
status = "okay";
};
&pciec1 {
status = "okay";
};

1870
arch/arm/dts/r8a7795.dtsi Normal file

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/*
* Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board
*
* Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2016 Cogent Embedded, Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/dts-v1/;
#include "r8a7796.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Renesas M3ULCB board based on r8a7796";
compatible = "renesas,m3ulcb", "renesas,r8a7796";
aliases {
serial0 = &scif2;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
leds {
compatible = "gpio-leds";
led5 {
gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
};
led6 {
gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
};
};
keyboard {
compatible = "gpio-keys";
key-1 {
linux,code = <KEY_1>;
label = "SW3";
wakeup-source;
debounce-interval = <20>;
gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
};
};
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator1 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vcc_sdhi0: regulator-vcc-sdhi0 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
scif2_pins: scif2 {
groups = "scif2_data_a";
function = "scif2";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_a";
function = "scif_clk";
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
sdhi0_pins_uhs: sd0_uhs {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <1800>;
};
sdhi2_pins: sd2 {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
power-source = <3300>;
};
sdhi2_pins_uhs: sd2_uhs {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
power-source = <1800>;
};
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
sd-uhs-sdr50;
status = "okay";
};
&sdhi2 {
/* used for on-board 8bit eMMC */
pinctrl-0 = <&sdhi2_pins>;
pinctrl-1 = <&sdhi2_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
non-removable;
status = "okay";
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
};
&wdt0 {
timeout-sec = <60>;
status = "okay";
};

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/*
* Device Tree Source for the Salvator-X board
*
* Copyright (C) 2016 Renesas Electronics Corp.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/dts-v1/;
#include "r8a7796.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Renesas Salvator-X board based on r8a7796";
compatible = "renesas,salvator-x", "renesas,r8a7796";
aliases {
serial0 = &scif2;
serial1 = &scif1;
ethernet0 = &avb;
};
chosen {
bootargs = "ignore_loglevel";
stdout-path = "serial0:115200n8";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x0 0x80000000>;
};
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator1 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vcc_sdhi0: regulator-vcc-sdhi0 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
vcc_sdhi3: regulator-vcc-sdhi3 {
compatible = "regulator-fixed";
regulator-name = "SDHI3 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi3: regulator-vccq-sdhi3 {
compatible = "regulator-gpio";
regulator-name = "SDHI3 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
avb_pins: avb {
groups = "avb_mdc";
function = "avb";
};
scif1_pins: scif1 {
groups = "scif1_data_a", "scif1_ctrl";
function = "scif1";
};
scif2_pins: scif2 {
groups = "scif2_data_a";
function = "scif2";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_a";
function = "scif_clk";
};
i2c2_pins: i2c2 {
groups = "i2c2_a";
function = "i2c2";
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
sdhi0_pins_uhs: sd0_uhs {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <1800>;
};
sdhi2_pins: sd2 {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
power-source = <3300>;
};
sdhi2_pins_uhs: sd2_uhs {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
power-source = <1800>;
};
sdhi3_pins: sd3 {
groups = "sdhi3_data4", "sdhi3_ctrl";
function = "sdhi3";
power-source = <3300>;
};
sdhi3_pins_uhs: sd3_uhs {
groups = "sdhi3_data4", "sdhi3_ctrl";
function = "sdhi3";
power-source = <1800>;
};
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
status = "okay";
phy0: ethernet-phy@0 {
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
};
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
sd-uhs-sdr50;
status = "okay";
};
&sdhi2 {
/* used for on-board 8bit eMMC */
pinctrl-0 = <&sdhi2_pins>;
pinctrl-1 = <&sdhi2_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
non-removable;
status = "okay";
};
&sdhi3 {
pinctrl-0 = <&sdhi3_pins>;
pinctrl-1 = <&sdhi3_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi3>;
vqmmc-supply = <&vccq_sdhi3>;
cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
sd-uhs-sdr50;
status = "okay";
};
&scif1 {
pinctrl-0 = <&scif1_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
};
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
status = "okay";
};
&wdt0 {
timeout-sec = <60>;
status = "okay";
};
&i2c_dvfs {
status = "okay";
};

1041
arch/arm/dts/r8a7796.dtsi Normal file

File diff suppressed because it is too large Load Diff

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@@ -0,0 +1,11 @@
&uart2 {
u-boot,dm-pre-reloc;
};
&grf {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};

View File

@@ -244,7 +244,7 @@
emmc: dwmmc@1021c000 {
compatible = "rockchip,rk3288-dw-mshc";
clock-frequency = <37500000>;
clock-freq-min-max = <400000 37500000>;
max-frequency = <37500000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";

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@@ -0,0 +1,92 @@
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
#include "rk322x.dtsi"
/ {
model = "Rockchip RK3229 Evaluation board";
compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
chosen {
stdout-path = &uart2;
};
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x40000000>;
};
ext_gmac: ext_gmac {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "ext_gmac";
#clock-cells = <0>;
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
enable-active-high;
regulator-name = "vcc_phy";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
};
&dmc {
rockchip,sdram-channel = /bits/ 8 <1 10 3 2 1 0 15 15>;
rockchip,pctl-timing = <0x96 0xC8 0x1F3 0xF 0x8000004D 0x4 0x4E 0x6 0x3
0x0 0x6 0x5 0xC 0x10 0x6 0x4 0x4
0x5 0x4 0x200 0x3 0xA 0x40 0x0 0x1
0x5 0x5 0x3 0xC 0x1E 0x100 0x0 0x4
0x0 0x924>;
rockchip,phy-timing = <0x220 0x1 0x0 0x0 0x0 0x4 0x60>;
rockchip,sdram-params = <0x428B188 0x0 0x21 0x472 0x15
0 300 3 0 120>;
};
&gmac {
assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>;
assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>;
clock_in_out = "input";
phy-supply = <&vcc_phy>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
tx_delay = <0x30>;
rx_delay = <0x10>;
status = "okay";
};
&emmc {
u-boot,dm-pre-reloc;
status = "okay";
};
&sdmmc {
status = "okay";
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
card-detect-delay = <200>;
disable-wp;
num-slots = <1>;
supports-sd;
};
&uart2 {
status = "okay";
};
&usb20_otg {
status = "okay";
};

782
arch/arm/dts/rk322x.dtsi Normal file
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@@ -0,0 +1,782 @@
/*
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3228-cru.h>
#include <dt-bindings/thermal/thermal.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
mmc0 = &emmc;
mmc1 = &sdmmc;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@f00 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf00>;
resets = <&cru SRST_CORE0>;
operating-points = <
/* KHz uV */
816000 1000000
>;
#cooling-cells = <2>; /* min followed by max */
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
};
cpu1: cpu@f01 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf01>;
resets = <&cru SRST_CORE1>;
};
cpu2: cpu@f02 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf02>;
resets = <&cru SRST_CORE2>;
};
cpu3: cpu@f03 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf03>;
resets = <&cru SRST_CORE3>;
};
};
amba {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
pdma: pdma@110f0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x110f0000 0x4000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
clocks = <&cru ACLK_DMAC>;
clock-names = "apb_pclk";
};
};
arm-pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
timer {
compatible = "arm,armv7-timer";
arm,cpu-registers-not-fw-configured;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clock-frequency = <24000000>;
};
xin24m: oscillator {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xin24m";
#clock-cells = <0>;
};
bus_intmem@10080000 {
compatible = "mmio-sram";
reg = <0x10080000 0x9000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x10080000 0x9000>;
smp-sram@0 {
compatible = "rockchip,rk322x-smp-sram";
reg = <0x00 0x10>;
};
ddr_sram: ddr-sram@1000 {
compatible = "rockchip,rk322x-ddr-sram";
reg = <0x1000 0x8000>;
};
};
i2s1: i2s1@100b0000 {
compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
reg = <0x100b0000 0x4000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
dmas = <&pdma 14>, <&pdma 15>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&i2s1_bus>;
status = "disabled";
};
i2s0: i2s0@100c0000 {
compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
reg = <0x100c0000 0x4000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
dmas = <&pdma 11>, <&pdma 12>;
dma-names = "tx", "rx";
status = "disabled";
};
i2s2: i2s2@100e0000 {
compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
reg = <0x100e0000 0x4000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
dmas = <&pdma 0>, <&pdma 1>;
dma-names = "tx", "rx";
status = "disabled";
};
grf: syscon@11000000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3228-grf", "syscon";
reg = <0x11000000 0x1000>;
};
uart0: serial@11010000 {
compatible = "snps,dw-apb-uart";
reg = <0x11010000 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart1: serial@11020000 {
compatible = "snps,dw-apb-uart";
reg = <0x11020000 0x100>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart2: serial@11030000 {
compatible = "snps,dw-apb-uart";
reg = <0x11030000 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart2_xfer>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
i2c0: i2c@11050000 {
compatible = "rockchip,rk3228-i2c";
reg = <0x11050000 0x1000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_xfer>;
status = "disabled";
};
i2c1: i2c@11060000 {
compatible = "rockchip,rk3228-i2c";
reg = <0x11060000 0x1000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C1>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_xfer>;
status = "disabled";
};
i2c2: i2c@11070000 {
compatible = "rockchip,rk3228-i2c";
reg = <0x11070000 0x1000>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C2>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_xfer>;
status = "disabled";
};
i2c3: i2c@11080000 {
compatible = "rockchip,rk3228-i2c";
reg = <0x11080000 0x1000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C3>;
pinctrl-names = "default";
pinctrl-0 = <&i2c3_xfer>;
status = "disabled";
};
pwm0: pwm@110b0000 {
compatible = "rockchip,rk3288-pwm";
reg = <0x110b0000 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
status = "disabled";
};
pwm1: pwm@110b0010 {
compatible = "rockchip,rk3288-pwm";
reg = <0x110b0010 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm1_pin>;
status = "disabled";
};
pwm2: pwm@110b0020 {
compatible = "rockchip,rk3288-pwm";
reg = <0x110b0020 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm2_pin>;
status = "disabled";
};
pwm3: pwm@110b0030 {
compatible = "rockchip,rk3288-pwm";
reg = <0x110b0030 0x10>;
#pwm-cells = <2>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm3_pin>;
status = "disabled";
};
timer: timer@110c0000 {
compatible = "rockchip,rk3288-timer";
reg = <0x110c0000 0x20>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&xin24m>, <&cru PCLK_TIMER>;
clock-names = "timer", "pclk";
};
cru: clock-controller@110e0000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3228-cru";
reg = <0x110e0000 0x1000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks = <&cru PLL_GPLL>;
assigned-clock-rates = <594000000>;
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <100>; /* milliseconds */
polling-delay = <5000>; /* milliseconds */
thermal-sensors = <&tsadc 0>;
trips {
cpu_alert0: cpu_alert0 {
temperature = <70000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
cpu_alert1: cpu_alert1 {
temperature = <75000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
cpu_crit: cpu_crit {
temperature = <90000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert0>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT 6>;
};
map1 {
trip = <&cpu_alert1>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
tsadc: tsadc@11150000 {
compatible = "rockchip,rk3228-tsadc";
reg = <0x11150000 0x100>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
clock-names = "tsadc", "apb_pclk";
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
pinctrl-names = "init", "default", "sleep";
pinctrl-0 = <&otp_gpio>;
pinctrl-1 = <&otp_out>;
pinctrl-2 = <&otp_gpio>;
#thermal-sensor-cells = <0>;
rockchip,hw-tshut-temp = <95000>;
status = "disabled";
};
sdmmc: dwmmc@30000000 {
compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30000000 0x4000>;
max-frequency = <150000000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
fifo-depth = <0x100>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
status = "disabled";
};
sdio: dwmmc@30010000 {
compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30010000 0x4000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
fifo-depth = <0x100>;
pinctrl-names = "default";
pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
status = "disabled";
};
emmc: dwmmc@30020000 {
compatible = "rockchip,rk3288-dw-mshc";
reg = <0x30020000 0x4000>;
max-frequency = <150000000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
bus-width = <8>;
default-sample-phase = <158>;
num-slots = <1>;
fifo-depth = <0x100>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
resets = <&cru SRST_EMMC>;
reset-names = "reset";
status = "disabled";
};
usb20_otg: usb@30040000 {
compatible = "rockchip,rk3229-usb", "rockchip,rk3288-usb",
"snps,dwc2";
reg = <0x30040000 0x40000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
hnp-srp-disable;
dr_mode = "otg";
status = "disabled";
};
gmac: ethernet@30200000 {
compatible = "rockchip,rk3228-gmac";
reg = <0x30200000 0x10000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
<&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
<&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
<&cru PCLK_GMAC>;
clock-names = "stmmaceth", "mac_clk_rx",
"mac_clk_tx", "clk_mac_ref",
"clk_mac_refout", "aclk_mac",
"pclk_mac";
resets = <&cru SRST_GMAC>;
reset-names = "stmmaceth";
rockchip,grf = <&grf>;
status = "disabled";
};
gic: interrupt-controller@32010000 {
compatible = "arm,gic-400";
interrupt-controller;
#interrupt-cells = <3>;
#address-cells = <0>;
reg = <0x32011000 0x1000>,
<0x32012000 0x2000>,
<0x32014000 0x2000>,
<0x32016000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
pinctrl: pinctrl {
compatible = "rockchip,rk3228-pinctrl";
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio0: gpio0@11110000 {
compatible = "rockchip,gpio-bank";
reg = <0x11110000 0x100>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO0>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio1@11120000 {
compatible = "rockchip,gpio-bank";
reg = <0x11120000 0x100>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio2@11130000 {
compatible = "rockchip,gpio-bank";
reg = <0x11130000 0x100>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio3@11140000 {
compatible = "rockchip,gpio-bank";
reg = <0x11140000 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pcfg_pull_up: pcfg-pull-up {
bias-pull-up;
};
pcfg_pull_down: pcfg-pull-down {
bias-pull-down;
};
pcfg_pull_none: pcfg-pull-none {
bias-disable;
};
pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
drive-strength = <12>;
};
sdmmc {
sdmmc_clk: sdmmc-clk {
rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
};
sdmmc_cmd: sdmmc-cmd {
rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
};
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<1 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<1 20 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<1 21 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
};
};
sdio {
sdio_clk: sdio-clk {
rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
};
sdio_cmd: sdio-cmd {
rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
};
sdio_bus4: sdio-bus4 {
rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<3 3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<3 4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<3 5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
};
};
emmc {
emmc_clk: emmc-clk {
rockchip,pins = <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>;
};
emmc_cmd: emmc-cmd {
rockchip,pins = <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none>;
};
emmc_bus8: emmc-bus8 {
rockchip,pins = <1 RK_PD0 RK_FUNC_2 &pcfg_pull_none>,
<1 RK_PD1 RK_FUNC_2 &pcfg_pull_none>,
<1 RK_PD2 RK_FUNC_2 &pcfg_pull_none>,
<1 RK_PD3 RK_FUNC_2 &pcfg_pull_none>,
<1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>,
<1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
<1 RK_PD6 RK_FUNC_2 &pcfg_pull_none>,
<1 RK_PD7 RK_FUNC_2 &pcfg_pull_none>;
};
};
gmac {
rgmii_pins: rgmii-pins {
rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<2 RK_PC6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<2 RK_PC7 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<2 RK_PB1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>,
<2 RK_PC4 RK_FUNC_2 &pcfg_pull_none>,
<2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>;
};
rmii_pins: rmii-pins {
rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>;
};
phy_pins: phy-pins {
rockchip,pins = <2 RK_PB6 RK_FUNC_2 &pcfg_pull_none>,
<2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>;
};
};
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 RK_PA0 RK_FUNC_1 &pcfg_pull_none>,
<0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>;
};
};
i2c1 {
i2c1_xfer: i2c1-xfer {
rockchip,pins = <0 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
<0 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
};
};
i2c2 {
i2c2_xfer: i2c2-xfer {
rockchip,pins = <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
};
};
i2c3 {
i2c3_xfer: i2c3-xfer {
rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
<0 RK_PA7 RK_FUNC_1 &pcfg_pull_none>;
};
};
i2s1 {
i2s1_bus: i2s1-bus {
rockchip,pins = <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
<0 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
<0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
<0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
<0 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
<0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
<1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
<1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,
<1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
};
};
pwm0 {
pwm0_pin: pwm0-pin {
rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
};
};
pwm1 {
pwm1_pin: pwm1-pin {
rockchip,pins = <0 RK_PD6 RK_FUNC_2 &pcfg_pull_none>;
};
};
pwm2 {
pwm2_pin: pwm2-pin {
rockchip,pins = <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none>;
};
};
pwm3 {
pwm3_pin: pwm3-pin {
rockchip,pins = <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none>;
};
};
tsadc {
otp_gpio: otp-gpio {
rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
otp_out: otp-out {
rockchip,pins = <0 RK_PD0 RK_FUNC_2 &pcfg_pull_none>;
};
};
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PD3 RK_FUNC_1 &pcfg_pull_none>;
};
uart0_cts: uart0-cts {
rockchip,pins = <2 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
};
uart0_rts: uart0-rts {
rockchip,pins = <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>;
};
};
uart1 {
uart1_xfer: uart1-xfer {
rockchip,pins = <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
<1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>;
};
uart1_cts: uart1-cts {
rockchip,pins = <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>;
};
uart1_rts: uart1-rts {
rockchip,pins = <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;
};
};
uart2 {
uart2_xfer: uart2-xfer {
rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
<1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>;
};
uart2_cts: uart2-cts {
rockchip,pins = <0 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
};
uart2_rts: uart2-rts {
rockchip,pins = <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
};
};
};
dmc: dmc@11200000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3228-dmc", "syscon";
rockchip,cru = <&cru>;
rockchip,grf = <&grf>;
rockchip,msch = <&service_msch>;
reg = <0x11200000 0x3fc
0x12000000 0x400>;
rockchip,sram = <&ddr_sram>;
};
service_msch: syscon@31090000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3228-msch", "syscon";
reg = <0x31090000 0x2000>;
};
};

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/*
* Device tree file for Phytec PCM-947 carrier board
* Copyright (C) 2017 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "rk3288-phycore-som.dtsi"
/ {
model = "Phytec RK3288 PCM-947";
compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288";
chosen {
stdout-path = &uart2;
};
config {
u-boot,dm-pre-reloc;
u-boot,boot0 = &emmc;
};
user_buttons: user-buttons {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&user_button_pins>;
button@0 {
label = "home";
linux,code = <KEY_HOME>;
gpios = <&gpio8 0 GPIO_ACTIVE_HIGH>;
wakeup-source;
};
button@1 {
label = "menu";
linux,code = <KEY_MENU>;
gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>;
wakeup-source;
};
};
vcc_host0_5v: usb-host0-regulator {
compatible = "regulator-fixed";
gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host0_vbus_drv>;
regulator-name = "vcc_host0_5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
vin-supply = <&vdd_in_otg_out>;
};
vcc_host1_5v: usb-host1-regulator {
compatible = "regulator-fixed";
gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host1_vbus_drv>;
regulator-name = "vcc_host1_5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
vin-supply = <&vdd_in_otg_out>;
};
vcc_otg_5v: usb-otg-regulator {
compatible = "regulator-fixed";
gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&otg_vbus_drv>;
regulator-name = "vcc_otg_5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
vin-supply = <&vdd_in_otg_out>;
};
};
&dmc {
rockchip,num-channels = <2>;
rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
0x5 0x0>;
rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
0xa60 0x40 0x10 0x0>;
rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xe 0xe>;
rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 5 1>;
};
&gmac {
status = "okay";
};
&hdmi {
status = "okay";
};
&i2c1 {
status = "okay";
touchscreen@44 {
compatible = "st,stmpe811";
reg = <0x44>;
};
adc@64 {
compatible = "maxim,max1037";
reg = <0x64>;
};
i2c_rtc: rtc@68 {
compatible = "rv4162";
reg = <0x68>;
pinctrl-names = "default";
pinctrl-0 = <&i2c_rtc_int>;
interrupt-parent = <&gpio5>;
interrupts = <10 0>;
};
};
&i2c3 {
status = "okay";
i2c_eeprom_cb: eeprom@51 {
compatible = "atmel,24c32";
reg = <0x51>;
pagesize = <32>;
};
};
&i2c4 {
status = "okay";
};
&i2c5 {
status = "okay";
};
&pinctrl {
u-boot,dm-pre-reloc;
pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma {
bias-pull-up;
drive-strength = <12>;
};
buttons {
user_button_pins: user-button-pins {
/* button 1 */
rockchip,pins = <8 3 RK_FUNC_GPIO &pcfg_pull_up>,
/* button 2 */
<8 0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
rv4162 {
i2c_rtc_int: i2c-rtc-int {
rockchip,pins = <5 10 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
sdmmc {
/*
* Default drive strength isn't enough to achieve even
* high-speed mode on pcm-947 board so bump up to 12 mA.
*/
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
<6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
<6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
<6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>;
};
sdmmc_clk: sdmmc-clk {
rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>;
};
sdmmc_cmd: sdmmc-cmd {
rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>;
};
sdmmc_pwr: sdmmc-pwr {
rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
touchscreen {
ts_irq_pin: ts-irq-pin {
rockchip,pins = <5 15 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb_host {
host0_vbus_drv: host0-vbus-drv {
rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
};
host1_vbus_drv: host1-vbus-drv {
rockchip,pins = <2 0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb_otg {
otg_vbus_drv: otg-vbus-drv {
rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&sdmmc {
u-boot,dm-pre-reloc;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
card-detect-delay = <200>;
disable-wp;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
vmmc-supply = <&vdd_io_sd>;
vqmmc-supply = <&vdd_io_sd>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
status = "okay";
};
&uart2 {
u-boot,dm-pre-reloc;
status = "okay";
};
&usbphy {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host1 {
status = "okay";
};
&usb_otg {
status = "okay";
};

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@@ -0,0 +1,514 @@
/*
* Device tree file for Phytec phyCORE-RK3288 SoM
* Copyright (C) 2017 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/net/ti-dp83867.h>
#include "rk3288.dtsi"
/ {
model = "Phytec RK3288 phyCORE";
compatible = "phytec,rk3288-phycore-som", "rockchip,rk3288";
/*
* Set the minimum memory size here and
* let the bootloader set the real size.
*/
memory {
device_type = "memory";
reg = <0 0x8000000>;
};
aliases {
rtc0 = &i2c_rtc;
rtc1 = &rk818;
eeprom0 = &i2c_eeprom_id;
};
ext_gmac: external-gmac-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
clock-output-names = "ext_gmac";
};
io_domains: io_domains {
compatible = "rockchip,rk3288-io-voltage-domain";
status = "okay";
sdcard-supply = <&vdd_io_sd>;
flash0-supply = <&vdd_emmc_io>;
flash1-supply = <&vdd_misc_1v8>;
gpio1830-supply = <&vdd_3v3_io>;
gpio30-supply = <&vdd_3v3_io>;
bb-supply = <&vdd_3v3_io>;
dvp-supply = <&vdd_3v3_io>;
lcdc-supply = <&vdd_3v3_io>;
wifi-supply = <&vdd_3v3_io>;
audio-supply = <&vdd_3v3_io>;
};
leds: user-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&user_led>;
user {
label = "green_led";
gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
default-state = "keep";
};
};
vdd_emmc_io: vdd-emmc-io {
compatible = "regulator-fixed";
regulator-name = "vdd_emmc_io";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vdd_3v3_io>;
};
vdd_in_otg_out: vdd-in-otg-out {
compatible = "regulator-fixed";
regulator-name = "vdd_in_otg_out";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vdd_misc_1v8: vdd-misc-1v8 {
compatible = "regulator-fixed";
regulator-name = "vdd_misc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
&cpu0 {
cpu0-supply = <&vdd_cpu>;
operating-points = <
/* KHz uV */
1800000 1400000
1608000 1350000
1512000 1300000
1416000 1200000
1200000 1100000
1008000 1050000
816000 1000000
696000 950000
600000 900000
408000 900000
312000 900000
216000 900000
126000 900000
>;
};
&emmc {
status = "okay";
u-boot,dm-pre-reloc;
bus-width = <8>;
cap-mmc-highspeed;
disable-wp;
non-removable;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
vmmc-supply = <&vdd_3v3_io>;
vqmmc-supply = <&vdd_emmc_io>;
};
&gmac {
assigned-clocks = <&cru SCLK_MAC>;
assigned-clock-parents = <&ext_gmac>;
clock_in_out = "input";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins &phy_rst &phy_int>;
phy-handle = <&phy0>;
phy-supply = <&vdd_eth_2v5>;
phy-mode = "rgmii-id";
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
tx_delay = <0x0>;
rx_delay = <0x0>;
mdio0 {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
interrupt-parent = <&gpio4>;
interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
enet-phy-lane-no-swap;
};
};
};
&hdmi {
ddc-i2c-bus = <&i2c5>;
};
&i2c0 {
status = "okay";
u-boot,dm-pre-reloc;
clock-frequency = <400000>;
rk818: pmic@1c {
status = "okay";
compatible = "rockchip,rk818";
reg = <0x1c>;
interrupt-parent = <&gpio0>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
u-boot,dm-pre-reloc;
vcc1-supply = <&vdd_sys>;
vcc2-supply = <&vdd_sys>;
vcc3-supply = <&vdd_sys>;
vcc4-supply = <&vdd_sys>;
boost-supply = <&vdd_in_otg_out>;
vcc6-supply = <&vdd_sys>;
vcc7-supply = <&vdd_misc_1v8>;
vcc8-supply = <&vdd_misc_1v8>;
vcc9-supply = <&vdd_3v3_io>;
vddio-supply = <&vdd_3v3_io>;
regulators {
u-boot,dm-pre-reloc;
vdd_log: DCDC_REG1 {
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1250000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vdd_3v3_io: DCDC_REG4 {
regulator-name = "vdd_3v3_io";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vdd_sys: DCDC_BOOST {
regulator-name = "vdd_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <5000000>;
};
};
/* vcc9 */
vdd_sd: SWITCH_REG {
regulator-name = "vdd_sd";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
/* vcc6 */
vdd_eth_2v5: LDO_REG2 {
regulator-name = "vdd_eth_2v5";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <2500000>;
};
};
/* vcc7 */
vdd_1v0: LDO_REG3 {
regulator-name = "vdd_1v0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
/* vcc8 */
vdd_1v8_lcd_ldo: LDO_REG4 {
regulator-name = "vdd_1v8_lcd_ldo";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
/* vcc8 */
vdd_1v0_lcd: LDO_REG6 {
regulator-name = "vdd_1v0_lcd";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
/* vcc7 */
vdd_1v8_ldo: LDO_REG7 {
regulator-name = "vdd_1v8_ldo";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
/* vcc9 */
vdd_io_sd: LDO_REG9 {
regulator-name = "vdd_io_sd";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
};
};
/* M24C32-D */
i2c_eeprom: eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
};
/* M24C32-D Identification page */
i2c_eeprom_id: eeprom@58 {
compatible = "atmel,24c32";
reg = <0x58>;
pagesize = <32>;
};
vdd_cpu: regulator@60 {
compatible = "fcs,fan53555";
reg = <0x60>;
fcs,suspend-voltage-selector = <1>;
regulator-always-on;
regulator-boot-on;
regulator-enable-ramp-delay = <300>;
regulator-name = "vdd_cpu";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1430000>;
regulator-ramp-delay = <8000>;
vin-supply = <&vdd_sys>;
};
};
&pinctrl {
pcfg_output_high: pcfg-output-high {
output-high;
};
emmc {
/*
* We run eMMC at max speed; bump up drive strength.
* We also have external pulls, so disable the internal ones.
*/
emmc_clk: emmc-clk {
rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_12ma>;
};
emmc_cmd: emmc-cmd {
rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_12ma>;
};
emmc_bus8: emmc-bus8 {
rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_12ma>,
<3 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
<3 2 RK_FUNC_2 &pcfg_pull_none_12ma>,
<3 3 RK_FUNC_2 &pcfg_pull_none_12ma>,
<3 4 RK_FUNC_2 &pcfg_pull_none_12ma>,
<3 5 RK_FUNC_2 &pcfg_pull_none_12ma>,
<3 6 RK_FUNC_2 &pcfg_pull_none_12ma>,
<3 7 RK_FUNC_2 &pcfg_pull_none_12ma>;
};
};
gmac {
phy_int: phy-int {
rockchip,pins = <4 2 RK_FUNC_GPIO &pcfg_pull_up>;
};
phy_rst: phy-rst {
rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>;
};
};
leds {
user_led: user-led {
rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_output_high>;
};
};
pmic {
pmic_int: pmic-int {
rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
};
/* Pin for switching state between sleep and non-sleep state */
pmic_sleep: pmic-sleep {
rockchip,pins = <RK_GPIO0 0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&pwm1 {
status = "okay";
};
&saradc {
status = "okay";
vref-supply = <&vdd_1v8_ldo>;
};
&spi2 {
status = "okay";
serial_flash: flash@0 {
compatible = "micron,n25q128a13", "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <50000000>;
m25p,fast-read;
#address-cells = <1>;
#size-cells = <1>;
status = "okay";
};
};
&tsadc {
status = "okay";
rockchip,hw-tshut-mode = <0>;
rockchip,hw-tshut-polarity = <0>;
};
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};
&vopl {
status = "okay";
};
&vopl_mmu {
status = "okay";
};
&wdt {
status = "okay";
};

View File

@@ -167,7 +167,7 @@
sdmmc: dwmmc@ff0c0000 {
compatible = "rockchip,rk3288-dw-mshc";
clock-freq-min-max = <400000 150000000>;
max-frequency = <150000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
@@ -179,7 +179,7 @@
sdio0: dwmmc@ff0d0000 {
compatible = "rockchip,rk3288-dw-mshc";
clock-freq-min-max = <400000 150000000>;
max-frequency = <150000000>;
clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
<&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
@@ -191,7 +191,7 @@
sdio1: dwmmc@ff0e0000 {
compatible = "rockchip,rk3288-dw-mshc";
clock-freq-min-max = <400000 150000000>;
max-frequency = <150000000>;
clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
<&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
@@ -203,7 +203,7 @@
emmc: dwmmc@ff0f0000 {
compatible = "rockchip,rk3288-dw-mshc";
clock-freq-min-max = <400000 150000000>;
max-frequency = <150000000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";

View File

@@ -14,6 +14,32 @@
chosen {
stdout-path = &uart2;
};
vcc3v3_sdmmc: sdmmc-pwren {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
regulator-always-on;
regulator-boot-on;
};
vcc5v0_otg: vcc5v0-otg-drv {
compatible = "regulator-fixed";
enable-active-high;
regulator-name = "vcc5v0_otg";
gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc5v0_host_xhci: vcc5v0-host-xhci-drv {
compatible = "regulator-fixed";
enable-active-high;
regulator-name = "vcc5v0_host_xhci";
gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
&uart2 {
@@ -52,7 +78,12 @@
status = "okay";
};
&usb_host0_xhci {
rockchip,vbus-gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
&usb20_otg {
vbus-supply = <&vcc5v0_otg>;
status = "okay";
};
&usb_host0_xhci {
vbus-supply = <&vcc5v0_host_xhci>;
status = "okay";
};

View File

@@ -25,6 +25,9 @@
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
mmc0 = &emmc;
mmc1 = &sdmmc;
mmc2 = &sdmmc_ext;
};
cpus {
@@ -184,6 +187,7 @@
};
grf: syscon@ff100000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
reg = <0x0 0xff100000 0x0 0x1000>;
#address-cells = <1>;
@@ -350,6 +354,12 @@
status = "disabled";
};
dmc: dmc@ff400000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3328-dmc", "syscon";
reg = <0x0 0xff400000 0x0 0x1000>;
};
cru: clock-controller@ff440000 {
compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
reg = <0x0 0xff440000 0x0 0x1000>;
@@ -415,7 +425,7 @@
sdmmc: rksdmmc@ff500000 {
compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff500000 0x0 0x4000>;
clock-freq-min-max = <400000 150000000>;
max-frequency = <150000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
clock-names = "biu", "ciu";
fifo-depth = <0x100>;
@@ -426,7 +436,7 @@
sdio: dwmmc@ff510000 {
compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff510000 0x0 0x4000>;
clock-freq-min-max = <400000 150000000>;
max-frequency = <150000000>;
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
@@ -438,7 +448,7 @@
emmc: rksdmmc@ff520000 {
compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff520000 0x0 0x4000>;
clock-freq-min-max = <400000 150000000>;
max-frequency = <150000000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
clock-names = "biu", "ciu";
fifo-depth = <0x100>;
@@ -460,10 +470,20 @@
status = "disabled";
};
usb20_otg: usb@ff580000 {
compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
"snps,dwc2";
reg = <0x0 0xff580000 0x0 0x40000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
hnp-srp-disable;
dr_mode = "otg";
status = "disabled";
};
sdmmc_ext: rksdmmc@ff5f0000 {
compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff5f0000 0x0 0x4000>;
clock-freq-min-max = <400000 150000000>;
max-frequency = <150000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
clock-names = "biu", "ciu";
fifo-depth = <0x100>;

View File

@@ -0,0 +1,34 @@
/*
* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
&pinctrl {
u-boot,dm-pre-reloc;
};
&service_msch {
u-boot,dm-pre-reloc;
};
&dmc {
u-boot,dm-pre-reloc;
status = "okay";
};
&pmugrf {
u-boot,dm-pre-reloc;
};
&cru {
u-boot,dm-pre-reloc;
};
&grf {
u-boot,dm-pre-reloc;
};
&uart2 {
u-boot,dm-pre-reloc;
};

View File

@@ -0,0 +1,93 @@
/*
* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
/ {
config {
u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */
u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */
};
chosen {
stdout-path = "serial0:115200n8";
u-boot,spl-boot-order = &emmc, &sdmmc;
};
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&service_msch {
u-boot,dm-pre-reloc;
};
&dmc {
u-boot,dm-pre-reloc;
/*
* Validation of throughput using SPEC2000 shows the following
* relative performance for the different memory schedules:
* - CBDR: 30.1
* - CBRD: 29.8
* - CRBD: 29.9
* Note that the best performance for any given application workload
* may vary from the default configured here (e.g. 164.gzip is fastest
* with CBRD, whereas 252.eon and 186.crafty are fastest with CRBD).
*
* See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for
* details on the 'rockchip,memory-schedule' property and how it
* affects the physical-address to device-address mapping.
*/
rockchip,memory-schedule = <DMC_MSCH_CBDR>;
rockchip,ddr-frequency = <800000000>;
rockchip,ddr-speed-bin = <DDR3_1600K>;
status = "okay";
};
&pmugrf {
u-boot,dm-pre-reloc;
};
&sgrf {
u-boot,dm-pre-reloc;
};
&cru {
u-boot,dm-pre-reloc;
};
&grf {
u-boot,dm-pre-reloc;
};
&uart0 {
u-boot,dm-pre-reloc;
};
&emmc {
u-boot,dm-pre-reloc;
};
&sdmmc {
u-boot,dm-pre-reloc;
};
&spi1 {
u-boot,dm-pre-reloc;
spiflash: w25q32dw@0 {
u-boot,dm-pre-reloc;
};
};
&timer0 {
u-boot,dm-pre-reloc;
clock-frequency = <24000000>;
};

View File

@@ -0,0 +1,195 @@
/*
* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
#include "rk3368.dtsi"
#include "rk3368-lion-u-boot.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Theobroma Systems RK3368-uQ7 SoM";
compatible = "tsd,rk3368-uq7", "tsd,lion", "rockchip,rk3368";
aliases {
mmc0 = &emmc;
mmc1 = &sdmmc;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
ext_gmac: gmac-clk {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "ext_gmac";
#clock-cells = <0>;
};
vcc_sys: vcc-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
};
&uart0 {
status = "okay";
};
&emmc {
status = "okay";
bus-width = <8>;
cap-mmc-highspeed;
clock-frequency = <150000000>;
disable-wp;
keep-power-in-suspend;
non-removable;
num-slots = <1>;
vmmc-supply = <&vcc33_io>;
vqmmc-supply = <&vcc18_io>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>;
};
&sdmmc {
status = "okay";
};
&gmac {
status = "okay";
phy-supply = <&vcc33_io>;
phy-mode = "rgmii";
clock_in_out = "input";
snps,reset-gpio = <&gpio3 11 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <2 10000 50000>;
assigned-clocks = <&cru SCLK_MAC>;
assigned-clock-parents = <&ext_gmac>;
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
tx_delay = <0x10>;
rx_delay = <0x10>;
};
&i2c0 {
status = "okay";
rk808: pmic@1b {
compatible = "rockchip,rk808";
reg = <0x1b>;
interrupt-parent = <&gpio0>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
rockchip,system-power-controller;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc6-supply = <&vcc_sys>;
vcc7-supply = <&vcc_sys>;
vcc8-supply = <&vcc_sys>;
vcc9-supply = <&vcc_sys>;
vcc10-supply = <&vcc_sys>;
vcc11-supply = <&vcc_sys>;
vcc12-supply = <&vcc_sys>;
clock-output-names = "xin32k", "rk808-clkout2";
#clock-cells = <1>;
regulators {
vdd_cpu: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vdd_cpu";
};
vdd_log: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vdd_log";
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_ddr";
};
vcc33_io: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc33_io";
};
vcc33_video: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc33_video";
};
vdd10_pll: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vdd10_pll";
};
vcc18_io: LDO_REG4 {
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc18_io";
};
vdd10_video: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vdd10_video";
};
vcc18_video: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc18_video";
};
};
};
};
&uart0 {
status = "okay";
};
&spi1 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
spiflash: w25q32dw@0 {
compatible = "spi-flash";
reg = <0>;
spi-max-frequency = <49500000>;
spi-cpol;
spi-cpha;
};
};

View File

@@ -0,0 +1,34 @@
/*
* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
&pinctrl {
u-boot,dm-pre-reloc;
};
&service_msch {
u-boot,dm-pre-reloc;
};
&dmc {
u-boot,dm-pre-reloc;
status = "okay";
};
&pmugrf {
u-boot,dm-pre-reloc;
};
&cru {
u-boot,dm-pre-reloc;
};
&grf {
u-boot,dm-pre-reloc;
};
&uart4 {
u-boot,dm-pre-reloc;
};

View File

@@ -0,0 +1,34 @@
/*
* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
&pinctrl {
u-boot,dm-pre-reloc;
};
&service_msch {
u-boot,dm-pre-reloc;
};
&dmc {
u-boot,dm-pre-reloc;
status = "okay";
};
&pmugrf {
u-boot,dm-pre-reloc;
};
&cru {
u-boot,dm-pre-reloc;
};
&grf {
u-boot,dm-pre-reloc;
};
&uart2 {
u-boot,dm-pre-reloc;
};

View File

@@ -46,6 +46,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/memory/rk3368-dmc.h>
/ {
compatible = "rockchip,rk3368";
@@ -227,6 +228,21 @@
#clock-cells = <0>;
};
dmc: dmc@ff610000 {
compatible = "rockchip,rk3368-dmc", "syscon";
rockchip,cru = <&cru>;
rockchip,grf = <&grf>;
rockchip,msch = <&service_msch>;
reg = <0 0xff610000 0 0x400
0 0xff620000 0 0x400>;
};
service_msch: syscon@ffac0000 {
compatible = "rockchip,rk3368-msch", "syscon";
reg = <0x0 0xffac0000 0x0 0x2000>;
status = "okay";
};
sdmmc: dwmmc@ff0c0000 {
compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff0c0000 0x0 0x4000>;
@@ -645,6 +661,11 @@
reg = <0x0 0xff738000 0x0 0x1000>;
};
sgrf: syscon@ff740000 {
compatible = "rockchip,rk3368-sgrf", "syscon";
reg = <0x0 0xff740000 0x0 0x1000>;
};
cru: clock-controller@ff760000 {
compatible = "rockchip,rk3368-cru";
reg = <0x0 0xff760000 0x0 0x1000>;
@@ -666,7 +687,7 @@
status = "disabled";
};
timer@ff810000 {
timer0: timer@ff810000 {
compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
reg = <0x0 0xff810000 0x0 0x20>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;

View File

@@ -60,6 +60,18 @@
gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
};
vcc5v0_typec0: vcc5v0-typec0-en {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_typec0";
gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
};
vcc5v0_typec1: vcc5v0-typec1-en {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_typec1";
gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
};
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
@@ -163,7 +175,7 @@
};
&dwc3_typec0 {
rockchip,vbus-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
vbus-supply = <&vcc5v0_typec0>;
status = "okay";
};
@@ -176,7 +188,7 @@
};
&dwc3_typec1 {
rockchip,vbus-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
vbus-supply = <&vcc5v0_typec1>;
status = "okay";
};
@@ -264,19 +276,3 @@
rx_delay = <0x10>;
status = "okay";
};
&gmac {
phy-supply = <&vcc_phy>;
phy-mode = "rgmii";
clock_in_out = "input";
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>;
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
tx_delay = <0x10>;
rx_delay = <0x10>;
status = "okay";
};

View File

@@ -8,7 +8,7 @@
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3399.dtsi"
#include "rk3399-sdram-ddr3-1333.dtsi"
#include "rk3399-sdram-ddr3-1600.dtsi"
/ {
model = "Firefly-RK3399 Board";
@@ -16,6 +16,7 @@
chosen {
stdout-path = &uart2;
u-boot,spl-boot-order = &sdhci, &sdmmc;
};
backlight: backlight {
@@ -156,8 +157,9 @@
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-min-microvolt = <430000>;
regulator-max-microvolt = <1400000>;
regulator-init-microvolt = <950000>;
};
vccadc_ref: vccadc-ref {
@@ -209,8 +211,8 @@
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
tx_delay = <0x28>;
rx_delay = <0x11>;
tx_delay = <0x33>;
rx_delay = <0x45>;
status = "okay";
};
@@ -590,6 +592,12 @@
status = "okay";
};
&sdmmc {
u-boot,dm-pre-reloc;
bus-width = <4>;
status = "okay";
};
&sdhci {
bus-width = <8>;
keep-power-in-suspend;

View File

@@ -12,7 +12,9 @@
compatible = "tsd,rk3399-q7", "tsd,puma", "rockchip,rk3399";
config {
u-boot,spl-payload-offset = <0x40000>; /* 256kbyte */
u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */
u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */
u-boot,efi-partition-entries-offset = <0x200000>; /* 2MB */
u-boot,boot-led = "module_led";
};

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