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151 Commits

Author SHA1 Message Date
Tom Rini
c98ac3487e Prepare v2017.09
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-11 14:10:40 -04:00
Jorge Ramirez-Ortiz
bbfbdb5722 MAINTAINERS: board: qcom: db410c: Maintainer changed
Replacing original author Mateusz Kulikowski
<mateusz.kulikowski@gmail.com> as db410c maintainer

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
2017-09-11 13:34:31 -04:00
Bin Meng
584f316f11 cmd: ide: Make the first device the default one
At present the IDE device number is initialized to -1, which means
we cannot type "ide read" command before setting the device number
via "ide device #".

For convenience, let's set the first device as the default one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-10 12:27:43 -04:00
Bin Meng
1f4adab873 block: ide: Don't bother to create BLK device if no CDROM inserted
When there is no CDROM inserted, the block size is zero hence there
is no need to create a BLK device for it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-10 12:27:40 -04:00
Bin Meng
68e6f221ed block: ide: Fix block read/write with driver model
This converts the IDE driver to driver model so that block read and
write are fully functional.

Fixes: b7c6baef ("x86: Convert MMC to driver model")
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-09-10 12:27:37 -04:00
Bin Meng
eb81b1a4d3 blk: Use macros for block device vendor/product/rev string size
So far these are using magic numbers. Replace them with macros.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-10 12:27:32 -04:00
Tom Rini
4ccceefb7f edison: Disable CONFIG_USB_HOST_ETHER
This board does dwc3 gadget, not host, so we cannot have host support or
we will fail to link.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-08 16:43:24 -04:00
Tom Rini
5eb35220b2 env: Migrate CONFIG_ENV_AES to Kconfig and deprecate
The underlying implementation for ENV_AES has security complications and
is not recommended for use.  Please see CVE-2017-3225 and CVE-2017-3226
for more details.  Mark this as deprecated now and delete this in the
medium term if no one comes forward to re-work the support.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-08 13:12:16 -04:00
Chris Packham
0683fb7242 usb: doc: update README.usb for new config options
A number of the config options for USB networking have been migrated to
Kconfig. Update README.usb to reflect this.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
2017-09-08 10:23:01 -04:00
Chris Packham
f58ad98a62 usb: net: migrate USB Ethernet adapters to Kconfig
This migrates ASIX, ASIX88179, MCS7830, RTL8152 and SMSC95XX to Kconfig.
Update defconfigs.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-08 10:23:00 -04:00
Chris Packham
ae3584498b usb: net: migrate CONFIG_USB_HOST_ETHER to Kconfig
CONFIG_USB_HOST_ETHER is the framework that the drivers are dependent on
USB_HOST_ETHER. Use this as a menu and move the existing LAN75XX and
LAN78XX options under new menu. Finally update the defconfigs that need
CONFIG_USB_HOST_ETHER.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-08 10:21:46 -04:00
Chris Packham
8ffb23cbf5 Kconfig: drop CONFIG_USB_ETHER_RNDIS
This is not a valid option. Drop it.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-08 10:17:17 -04:00
Chris Packham
9272c7b160 Kconfig: drop CONFIG_USB_ETHER_DM9601
This is not a valid option. Drop it.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-08 10:15:47 -04:00
Nobuhiro Iwamatsu
eb3eb6020f README: Fix typo in description of CONFIG_OF_EMBED
The correct name is 'gd->fdt_blob', not 'gd->blob'.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-08 10:15:47 -04:00
Tom Rini
df35f4530b configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-08 10:14:49 -04:00
Kever Yang
0532ceef30 rockchip: enable SPL_SYSRESET config for all Rockchip SoCs
With Makefiles testing for $(SPL_TPL_)SYSRESET, we need SPL_SYSRESET
for do_reset() in SPL for Rockchip SoCs.

References: 87c16d4 "drivers: spl: consistently use the $(SPL_TPL_) macro"
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-08 11:45:19 +02:00
Kever Yang
e1f6881367 rockchip: rk3328: fix syscon id table
syscon id table need a dummy member as NULL ending, or else system
will panic while try to match a compatible in this table as a list.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-08 11:44:51 +02:00
Marek Vasut
25f840d7ef ARM: rmobile: Disable CONFIG_ARCH_FIXUP_FDT_MEMORY
Disable CONFIG_ARCH_FIXUP_FDT_MEMORY to prevent U-Boot from modifying
the memory {} nodes in the DT passed to the Linux kernel. The R8A779x
DT contains multiple memory {} nodes, while U-Boot only modifies the
first one and stuffs all the memory entries into it, which is wrong.
Disabling CONFIG_ARCH_FIXUP_FDT_MEMORY is the least intrusive way to
fix the issue this close to the release, while the real fix is to
extend the fdt_fixup_memory_banks() to handle multiple memory nodes
in DT.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-07 20:04:41 -04:00
Marek Vasut
183f5fd3ca ARM: rmobile: Fix SD divider settings on Gen3
On RCar M3 and on RCar H3 newer than and not including ES1.0, the SD clock
must be divided by 4 rather than 2 because a hardware workaround present
only in the H3 ES1.0 has been removed from these chips. U-Boot currently
only supports M3 and H3 ES 2.0 and newer, so configure the SD pre-divider
to 4 to prevent SD instability.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-07 20:04:40 -04:00
Tom Rini
ec6bc928bb Merge git://git.denx.de/u-boot-net 2017-09-07 14:48:23 -04:00
Heinrich Schuchardt
e4691564cc net: fix typos
%s/Desriptor/Descriptor/g

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-09-07 13:23:52 -05:00
Madalin Bucur
10710b4ec5 armv8: ls1043/ls1046aqds: add support for RGMII_TXID
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: York Sun <york.sun@nxp.com>
2017-09-07 13:23:52 -05:00
Tom Rini
0b1e580672 net: nfs: Drop CONFIG_NFS_READ_SIZE
In the general case, CONFIG_NFS_READ_SIZE is unchanged from the default
of 1024.  There are in fact no in-tree users that increase this size.
Adjust the comment to reflect what could be done in the future in
conjunction with CONFIG_IP_DEFRAG.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-09-07 13:23:52 -05:00
Madalin Bucur
05b29aa0cb net: phy: realtek: fix enabling of the TX-delay for RTL8211F
The old logic always enabled the TX-delay when the phy-mode was set to
PHY_INTERFACE_MODE_RGMII. With this patch we enable the TX delay for
PHY_INTERFACE_MODE_RGMII_ID and PHY_INTERFACE_MODE_RGMII_TXID and
disable it for PHY_INTERFACE_MODE_RGMII.

Based on a similar change made in the Linux Realtek PHY driver
by Martin Blumenstingl <martin.blumenstingl@googlemail.com>.

Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: York Sun <york.sun@nxp.com>
2017-09-07 13:23:52 -05:00
Kever Yang
b5b82abcf5 spl: typo fix for SPL_ATF_SUPPORT description
Delete one redundant 'which' for SPL_ATF_SUPPORT description.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2017-09-07 10:44:38 -04:00
Heinrich Schuchardt
d72fd7b340 linker_lists: remove incorrect comment
Remove a comment line refering to a non-existent file.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-09-07 10:44:37 -04:00
Heinrich Schuchardt
de2de3192f vsprintf: vsprintf does not have parameter size
The inline documentation of vsprintf mentions a parameter size
which does not exist in the function declaration.

int vsprintf(char *buf, const char *fmt, va_list args);

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-09-07 10:44:37 -04:00
Paul Barker
2d0cf3b2ae Revert "dm: arm: rpi: Drop CONFIG_OF_EMBED"
This reverts commit 25877d4e4c.

This is a workaround for Raspberry Pi boot failures seen when passing on
the device tree provided by the Raspberry Pi firmware at boot. Without
CONFIG_OF_EMBED, we just get stuck at "Starting kernel ..." when we try
to boot Linux with this device tree.

Signed-off-by: Paul Barker <pbarker@toganlabs.com>
Cc: Simon Glass <sjg@chromium.org>
Tested-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-07 10:44:36 -04:00
Bin Meng
eab44c93eb tools: .gitignore: Add libfdt related files
Some files are generated during libfdt build. Ignore them.

This was wrongly put in the .gitignore in the root directory before.
Now let's remove entries there and put them in the right place.

Fixes: 34e2c285 ("gitignore: add intermediates from libfdt build")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-07 10:44:35 -04:00
Bin Meng
d11d3b2fa6 tools: .gitignore: Sort in alphabetical order
These are currently out of alphabetical order.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-07 10:44:34 -04:00
Alison Chaiken
2105f34843 doc: remove duplicate text in README.gpt
Signed-off-by: Alison Chaiken <alison@she-devel.com>
2017-09-07 10:44:34 -04:00
Bin Meng
337e3b897d part: mac: Suppress the error message after reading ddb
Change to use 'debug' to output the error message if it fails to
read the driver descriptor block.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-07 10:44:33 -04:00
Simon Glass
84a42069f2 env: Add 'envtools' target to 'make help'
The target is not currently mentioned anywhere. Add it to the help so
people can find it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-09-05 20:34:09 -04:00
Simon Glass
5733295714 env: Fix operation of 'make environ'
This was broken by the recent environment refactoring. Specifically:

$  make environ
scripts/Makefile.build:59: tools/environ/Makefile: No such file or directory
make[1]: *** No rule to make target 'tools/environ/Makefile'.  Stop.
make: *** [Makefile:1469: environ] Error 2

Fix this by updating the Makefile and adjusting the #include filesnames in
two C files.

Fixes: ec74f5f (Makefile: Rename 'env' target to 'environ')
Reported-by: Måns Rullgård <mans@mansr.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-09-05 20:34:08 -04:00
Sam Protsenko
de4e4edaff usb: gadget: g_dnl: Sync internal SN variable with env
Since commit 842778a091 ("usb: gadget: g_dnl: only set iSerialNumber
if we have a serial#") "fastboot devices" stopped to show correct device
serial number for TI boards, showing this line instead:

    ????????????	fastboot

This is because serial# env variable could be set after g_dnl gadget was
initialized (e.g. by using env_set() in the board file).

To fix this, let's update internal serial number variable (g_dnl_serial)
when "serial#" env var is changed.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Cc: Felipe Balbi <felipe.balbi@linux.intel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Acked-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
2017-09-05 20:17:08 -04:00
Tom Rini
2d3229bea2 env: Fix out of tree building of tools-all
With the move of environment code from common/ to env/ a number of
changes needed to be made to various make targets.  We missed updating
some of the files required for out of tree builds of the tools.  Correct
the 'environ' target to know that we need to work under tools/env/ still
(not tools/environ/) and then update the wrappers in env_attr.c and
env_flags.c to point to the new correct file.

Reported-by: Peter Robinson <pbrobinson@gmail.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-05 15:59:47 -04:00
Tom Rini
8dcb6f1f81 Merge git://git.denx.de/u-boot-video 2017-09-05 08:54:55 -04:00
Tom Rini
08d0c53d6b Merge git://git.denx.de/u-boot-rockchip 2017-09-05 07:11:46 -04:00
Anatolij Gustschin
c967fb78e4 MAINTAINERS: add lcd files to video section
LCD drivers are video related, so add them to video section.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-09-05 11:17:31 +02:00
Wadim Egorov
5deaa53028 rockchip: i2c: fix >32 byte reads
The hw can read up to 32 bytes at a time. If we need
more than one chunk, we have to enter the plain RX mode.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-05 11:13:36 +02:00
Kever Yang
313bbcf0ea rockchip: firefly-rk3399: enable ATF and dwmmc
enable the ATF option and SDCard in defconfig.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-05 11:04:35 +02:00
Philipp Tomsich
5798d503fc rockchip: timer: fix U_BOOT_DRIVER name
When I originally added this driver, I did some careless (and in
retrospect: mindless) copy & paste for the U_BOOT_DRIVER structure
skeletion... unfortunately, the 'arc_timer' string was committed
and slipped through all reviews.

This fixes the U_BOOT_DRIVER name to read 'rockchip_rk3368_timer'
(as originally intended).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reported-by: Artturi Alm <artturi.alm@gmail.com>
2017-09-05 11:04:35 +02:00
Wadim Egorov
40d4f79b81 rockchip: rk3288: Add reset reason detection
Sometimes it's helpful to know the reset reason caused in the SoC.
Add reset reason detection for the RK3288 SoC.
This will set an environment variable which represents the reset reason.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-05 11:04:35 +02:00
Wadim Egorov
32191a3912 rockchip: phycore: Read configuration EEPROM & set ethaddr in late init
Read SoM information from EEPROM and set ethaddr in late init.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-05 11:04:34 +02:00
Tom Rini
a0e80c97c9 Merge branch 'rmobile' of git://git.denx.de/u-boot-sh 2017-09-04 22:17:59 -04:00
Marek Vasut
0d0915bef7 ARM: rmobile: Add missing IPSR18 bits to R8A7795 PFC
The IPSR18 register bits were missing from the R8A7795 ES2.0+ PFC
tables, which triggered a BUG() in sh_pfc driver. This is because
of an out-of-bounds access to the pinmux_gpios[] array in the PFC
tables, which was too short due to the missing IPSR18 bits.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-05 07:51:39 +09:00
Marek Vasut
8212f56347 ARM: rmobile: Drop board_mmc_init
The board_mmc_init() is no longer invoked when DM is used, so move
all the pinmux config into board_init() instead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-05 07:51:39 +09:00
Marek Vasut
3158b6f606 ARM: rmobile: Replace CONFIG_RAVB with CONFIG_RENESAS_RAVB in boards
The configuration option name is the later, so replace usage of
CONFIG_RAVB in board files with CONFIG_RENESAS_RAVB , otherwise
the RAVB pinmux is not set and ethernet does not work.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-05 07:51:39 +09:00
Niko Mauno
a7126edcb3 splash_source: Verify FIT magic
Before reading entire FIT image, add sanity check by testing image
header against FDT_MAGIC. This should help avoid problems in situations
where FIT is not yet available from storage device, for example when
performing initial programming of device.

Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: Tomas Melin <tomas.melin@vaisala.com>
2017-09-04 23:53:47 +02:00
Anatolij Gustschin
f8ba7f2774 video: ipuv3_fb: skip IPU shutdown if IPU was not enabled before
Boards can skip display interface init using board_video_skip().
If display interface was not initialized (e.g. no ipuv3 framebuffer
registered or IPU clock disabled), booting Linux stops due to the
crash in IPU shutdown function, when accessing IPU registers.
Check IPU clock and skip shutdown if clock is not enabled.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-09-04 23:33:45 +02:00
Tom Rini
ced0fd938d Merge git://git.denx.de/u-boot-dm 2017-09-04 14:56:45 -04:00
Tom Rini
0e88cdd17d Prepare v2017.09-rc4
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-04 09:02:48 -04:00
Clemens Gruber
4c2cf973aa crypto/fsl: fix obj-yy in Makefile
When enabling CONFIG_CMD_BLOB and/or CONFIG_CMD_DEKBLOB, the build fails
with a linker error:
  ...
  LD      u-boot
arch/arm/mach-imx/built-in.o: In function `blob_encap_dek':
/home/clemens/dev/u-boot/arch/arm/mach-imx/cmd_dek.c:46: undefined
reference to `blob_dek'

This is due to an error in the Makefile, resulting in obj-yy/obj-yn/..
and fsl_blob.o is therefore not linked.

Fix it by splitting it up into two obj-y lines.

Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-09-04 09:02:07 -04:00
Lukasz Majewski
4b51a89170 git: mailrc: Update e-mail address
Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-09-04 09:02:06 -04:00
Simon Glass
d944bf6b5e dm: core: Add livetree documentation
Add some documentation for the live device tree support in U-Boot. This
was missing from the initial series.

Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
2017-09-04 02:10:06 -06:00
Philipp Tomsich
34e2c285da gitignore: add intermediates from libfdt build
Since ee95d10 (fdt: Build the new python libfdt module), a number of
additional files are auto-generated/installed into the tools directory.
List these in .gitignore to suppress having them listed as untracked.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
References: ee95d10 (fdt: Build the new python libfdt module)
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-04 02:10:06 -06:00
Hannes Schmelzer
cee8c35d1b fdt: fix 'prop (...) not found!' error in 'fdt set' command
This commit brings things back to the well known working state of the
command.
-
With commit 9620d87259
(cmd/fdt: support single value replacement within an array)

there was an error introduced modifying (inserting) a property to a
device-tree node.
fdt_getprop(...) returnes a len with -1 for a non-existing property, but
a memcpy with len -1 isn't a good idea and things went wrong (crash).
-
Some times later Tom did repair this
with commit 99bb38e2cc
(fdt: Check for NULL return from fdt_getprop in 'fdt set')

This repairs the crash but the behaviour of the command isn't like
before, it makes it impossible to insert a property.
-

Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Acked-by: Simon Glass <sjg@chromium.org>
2017-09-04 02:10:06 -06:00
Simon Glass
302466d07f dm: Add migration plan for CONFIG_BLK
The CONFIG_BLK conversion involves quite invasive changes in the U-Boot
code, with #ifdefs and different code paths. We should try to move over to
this soon so we can drop the old code.

Set a deadline of 9 months for this work, rounded up to the next release.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-04 02:10:06 -06:00
Bin Meng
6935aec0e3 Makefile: Suppress output of python libfdt build command
This should not be printed by default. Prefix it with $(Q).

Fixes ee95d10b: ("fdt: Build the new python libfdt module")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-03 15:30:37 -04:00
Bin Meng
a5ab5c771b Makefile: Quiesce libfdt build
Since commit 3809e302 "Makefile: honor PYTHON configuration properly",
the build commands of libfdt are printed while previously were not.

This adds the missing '--quiet' back.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-03 15:30:36 -04:00
Derald D. Woods
c257c96d9b omap3: evm: Fixes for CONFIG_NAND, SPL_OS_BOOT, USB, and environment
- Pass MTDPARTS kernel arguments to kernel
- Use Kconfig CONFIG_NAND instead of CONFIG_SYS_EXTRA_OPTIONS="NAND"
- Call 'usb_stop' on kernel start
- Update Falcon mode setup to match other OMAP3 boards
- Use "uEnv.txt" as boot script instead of "boot.scr"
2017-09-03 15:30:36 -04:00
Bin Meng
2c3b68081a block: Drop the ftide020 driver
This is not used in U-Boot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-03 15:30:35 -04:00
Bin Meng
caa8bfbc45 block: ide: Drop CONFIG_IDE_LED
This is actually not used. Drop it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-03 15:30:35 -04:00
Bin Meng
f1823d3aaa block: ide: Drop CONFIG_IDE_INIT_POSTRESET
This is not referenced anywhere. Drop it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-03 15:30:34 -04:00
Bin Meng
9e18eae276 nvme: Remove dead codes in nvme_setup_io_queues()
Execution cannot reach this statement: "nr_io_queues = result;"

Reported-by: Coverity (CID: 166731)
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 15:30:34 -04:00
Bin Meng
52a5690efb nvme: Fix potential sign extension issue in nvme_blk_rw()
"lbas" with type "u16" (16 bits, unsigned) is promoted in
"lbas << ns->lba_shift" to type "int" (32 bits, signed), then
sign-extended to type "unsigned long long" (64 bits, unsigned).
If "lbas << ns->lba_shift" is greater than 0x7FFFFFFF, the upper
bits of the result will all be 1.

Fix it by casting "lbas" to "u32".

Reported-by: Coverity (CID: 166730)
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 15:30:33 -04:00
Bin Meng
37d46870b3 nvme: Fix wrong ndev->queues memset
memset() was given a sizeof(NVME_Q_NUM * sizeof(struct nvme_queue *)
to clear, which is wrong.

Reported-by: Coverity (CID: 166729)
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 15:30:32 -04:00
Heinrich Schuchardt
5eae466ea1 disk: part: fix typo
%s/Desriptor/Descriptor/g

Fix lines over 80 characters with said typo.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-09-03 15:30:32 -04:00
Lukasz Majewski
40fe89c6e8 fix: fw_env: Prevent writing error message on special files, which don't support fsync
According to fsync specification [1] some special files (e.g., a pipe, FIFO,
or socket) don't support synchronization and return either EROFS or EINVAL.

On the linux side the sys_fsync -> do_fsync() checks if the requested file
has f_op->fsync defined. If not it returns EINVAL [2].

This commit prevents writing error messages for files (devices), which
do not support fsync().

[1] - http://man7.org/linux/man-pages/man2/fsync.2.html
[2] - http://elixir.free-electrons.com/linux/v4.13-rc6/source/fs/sync.c#L183

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Michael Heimpold <mhei@heimpold.de>
2017-09-03 15:30:31 -04:00
Jonathan Gray
8f1603bd78 bch: don't use __BSD_VISIBLE to test for fls
Commit 4ecc988301 assumes fls is in libc
if __BSD_VISIBLE is defined.  This appears to only be true on FreeBSD
and DragonFlyBSD.  OpenBSD defines __BSD_VISIBLE and does not have fls
in strings.h/libc.

Switch the test for __BSD_VISIBLE to one for __DragonFly__ and
__FreeBSD__ to unbreak the build on OpenBSD.

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
2017-09-03 15:30:31 -04:00
Thomas Petazzoni
e090579d0a include/configs: remove numerous CONFIG_SYS_BARGSIZE definitions
This commit removes definitions of CONFIG_SYS_BARGSIZE defined to be
equal to CONFIG_SYS_CBSIZE in numerous configuration files.

We remove such definitions in two situations:

 - CONFIG_SYS_CBSIZE is otherwise not defined in the board
   configuration file, which means the default value of
   CONFIG_SYS_CBSIZE == 256 applies. In this case, the default value
   of CONFIG_SYS_BARGSIZE == 512 (common/image.c) is suitable, as it is
   larger.

 - CONFIG_SYS_CBSIZE is defined in the board configuration file, but
   to a value equal or less than 512. In this case, the default value
   of CONFIG_SYS_BARGSIZE == 512 (common.image.c) is suitable, as it
   is equal or larger.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 15:30:30 -04:00
Thomas Petazzoni
8a7507a8a3 include/configs: remove default values of CONFIG_SYS_BARGSIZE
CONFIG_SYS_BARGSIZE is already defined to 512 in common/image.c when
not defined. Therefore, there is no point in having board
configuration files define it to 512.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 15:30:30 -04:00
Thomas Petazzoni
1f20fc53b3 include/configs: drop default definitions of CONFIG_SYS_MAXARGS
Now that include/config_fallbacks.h define a sane fallback for
CONFIG_SYS_MAXARGS, we can drop the definition of this constant in all
configurations that were using the default value.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 15:30:29 -04:00
Thomas Petazzoni
bb939d7a6d include/config_fallbacks.h: add default for CONFIG_SYS_MAXARGS
CONFIG_SYS_MAXARGS contains the maximum number of arguments accepted
by U-Boot commands. Since the vast majority of the platforms define it
to 16, it makes sense to have a default definition to 16, which will
allow to remove this definition from a significant number of
platforms.

It will allow to remove the default definition from 216 platform .h
files, leaving only 56 platforms with non-default values (15, 24, 32,
48, 64, 96, 128 or 256).

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 15:30:29 -04:00
Thomas Petazzoni
432e398068 include/configs: drop default definitions of CONFIG_SYS_PBSIZE
Now that the fallback value of CONFIG_SYS_PBSIZE in
include/config_fallbacks.h has been adjusted, remove its definition
from a large number of board configuration files.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 15:30:28 -04:00
Thomas Petazzoni
80c914f1bb include/config_fallbacks.h: change fallback for CONFIG_SYS_PBSIZE
Most of the platforms are using CONFIG_SYS_CBSIZE +
sizeof(CONFIG_SYS_PROMPT) + 16 as their value for CONFIG_SYS_PBSIZE,
so let's adopt this for the fallback value of CONFIG_SYS_PBSIZE.

This will allow us to drop an explicit definition of CONFIG_SYS_PBSIZE
from a large number of platforms.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 15:30:27 -04:00
Thomas Petazzoni
3784c789e7 include/configs: remove CONFIG_SYS_CBSIZE when the default value is used
Now that include/config_fallbacks.h define a sane fallback for
CONFIG_SYS_CBSIZE, we can drop the definition of this constant in all
configurations that were using the default value.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Drop <config.h> from stih410-b2260.h]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-03 15:30:06 -04:00
Thomas Petazzoni
72f09606d8 include/config_fallbacks.h: add default for CONFIG_SYS_CBSIZE
CONFIG_SYS_CBSIZE contains the buffer size for input for the
console. The vast majority of platforms define them to some reasonable
value (256, 512 or 1024 bytes), and it is quite annoying to repeat
this definition for all platforms while it isn't really HW-related.

Therefore, let's provide a sane fallback value in config_fallbacks.h,
so that platforms can rely on it instead of having to explicitly
define it.

We use 1024 when KGDB is enabled, and 256 otherwise, which is what the
majority of the platforms are doing.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 11:04:52 -04:00
Maxime Ripard
79c5912e8d part: efi: Disable overlap check
The current code checks that no partitions overlap with the GPT partition
table using the offset of the first LBA usable for that partition.

This works fine, unless you have a partition entry that is further away
than it usually is and you want to create partitions in the gap between the
GPT header and the GPT partition entries, for example to reflash a
bootloader that needs to be set there.

Rework the test to something a bit smarter that checks whether a partition
would overlap with either the GPT header or the partition entries, no
matter where it is on the disk.

Partitions that do not have a start LBA specified will still start at the
first LBA usable set in the GPT header, to avoid weird behaviours.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 11:04:51 -04:00
Maxime Ripard
47d7ee47ba part: efi: make gpt_fill_pte take the device descriptor
The gpt_fill_pte will need to access the device block size. Let's pass the
device descriptor as an argument.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 11:04:51 -04:00
Maxime Ripard
5276e8b62d part: efi: rework the partition start and size in gpt_fill_pte
The start variable is only used inside a loop, and is never affected inside
it, so it's a purely local variable.

In the same way the partition size is accessed several times, so we can
store it in a variable.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 11:04:48 -04:00
Maxime Ripard
89d33a2c0d part: efi: Fix offset
Both the config option and the DT options specify the offset to set the GPT
at in bytes, yet the code treats those values as block numbers.

Fix that.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-03 11:04:47 -04:00
Tom Rini
41a85fe3b9 Merge git://git.denx.de/u-boot-x86 2017-09-02 20:50:59 -04:00
Adam Ford
e3f24d4f2c Kconfig: Add EEPROM options to Kconfig when I2C_EEPROM is set
Add the following options to drivers/misc/Kconfig:
	SYS_I2C_EEPROM_ADDR
	SYS_I2C_EEPROM_BUS
	SYS_EEPROM_SIZE
	SYS_EEPROM_PAGE_WRITE_BITS
	SYS_EEPROM_PAGE_WRITE_DELAY_MS
	SYS_I2C_EEPROM_ADDR_LEN
	SYS_I2C_EEPROM_ADDR_OVERFLOW

This does not migrate any boards, but provides a foundations for
those who want/need these options

Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Migrate uniphier]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-02 15:50:30 -04:00
Stefan Roese
f04034cba4 x86: theadorable-x86-common: Remove "ip=dhcp" from default environment
Without ethernet cable plugged, "ip=dhcp" leads to a complete hangup in
Linux booting and the system does not boot into userland at all. Since
its not required to have an active network connection on these board,
lets remove this statement from the default environment.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-02 23:49:34 +08:00
Bin Meng
3fe6e6e2aa x86: baytrail: acpi: Add full reset bit to the reset register value in FADT
It was noticed a few times, that the reboot from Linux (reboot command)
is different from the reboot (reset command) under U-Boot. The U-Boot
version does seem to reset the board more deeply (PCI cards etc) than
the Linux reboot.

This is actually caused by missing full reset bit in the reset register
value in the ACPI FADT table.

Reported-by: Stefan Roese <sr@denx.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
2017-09-02 23:35:55 +08:00
Bin Meng
d2ca80c3d7 x86: ich-spi: Clear atomic preop only when SPI settings are not locked
The atomic preop register can only be written when SPI settings are
not locked, otherwise it's read-only.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-09-02 23:35:55 +08:00
Bin Meng
52dd56ba84 x86: ich-spi: Remove useless assignment in ich_spi_xfer()
In ich_spi_xfer() when the driver presets control fields, control
variable gets assigned twice. Apparently only the last assignment
takes effect. Remove the other one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-09-02 23:35:55 +08:00
Adam Ford
db35573a71 omap3_logic: Move CONFIG_SYS_NAND_U_BOOT_OFFS to Kconfig
Manually enable SYS_NAND_U_BOOT_LOCATIONS.
Set CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 and remove it from header

Signed-off-by: Adam Ford <aford173@gmail.com>
2017-09-02 10:45:24 -04:00
Adam Ford
6ef2f90108 Convert CONFIG_BCH to Kconfig
This converts the following to Kconfig:
   CONFIG_BCH

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-01 20:45:26 -04:00
Adam Ford
edd1653f04 Convert CONFIG_SPL_OMAP3_ID_NAND to Kconfig
This converts the following to Kconfig:
   CONFIG_SPL_OMAP3_ID_NAND

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-01 20:45:26 -04:00
Adam Ford
fc760cc6e8 Convert CONFIG_SYS_I2C_BUS_MAX to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_I2C_BUS_MAX

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
[trini: Fix AM43XX drop AM44XX]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-01 20:44:30 -04:00
Adam Ford
ac1d8ac871 Configs: Migrate I2C_BUS_MAX to CONFIG_SYS_I2C_BUS_MAX
For consistency with other platforms and in preparation of Kconfig
migration, let's change Several TI platforms that use I2C_BUS_MAX
to CONFIG_SYS_I2C_BUS_MAX

Signed-off-by: Adam Ford <aford173@gmail.com>
2017-09-01 17:56:20 -04:00
Tom Rini
48f6232e58 Kconfig: Migrate all of cmd/fastboot/Kconfig to defconfigs
- Move ANDROID_IMAGE_SUPPORT to top level Kconfig under images as it's
  not strictly part of fastboot.
- Add some defaults for the fastboot buffer location and size
- Migrate all options listed in cmd/fastboot/Kconfig
- Cleanup the README

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-01 16:18:21 -04:00
Tom Rini
ecad7051b0 configs: Migrate all of the existing USB symbols, except fastboot
This syncs all of the currently Kconfig'd symbols out of the headers and
into the defconfig files.  This has two exceptions, first am335x_evm
needs to be converted to DM in SPL and then it can stop undef'ing
CONFIG_DM_USB.  Leaving this as-is results in a build failure, and
without work, run time failure.  The other case is am43xx_evm.h and in
turn am43xx_evm_usbhost_boot.  The problem here is that we need DWC3 USB
host mode in SPL, but still desire to have gadget mode in U-Boot proper.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-01 16:18:20 -04:00
Tom Rini
9493d05a41 Revert "Merge git://git.denx.de/u-boot-video"
This reverts commit 1d20170467, reversing
changes made to 6aee2ab68c.

The mxc_ipuv3_fb.c changes introduce build failures on some targets.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-01 16:17:17 -04:00
Tom Rini
0b6e5b2c48 Merge git://git.denx.de/u-boot-sunxi 2017-09-01 13:30:19 -04:00
Tom Rini
1d20170467 Merge git://git.denx.de/u-boot-video 2017-09-01 12:57:03 -04:00
Dave Prue
6ff005cf19 sunxi: Fix CONFIG_SUNXI_GMAC references
SUNXI_GMAC was still used to configure the code where as the
same has been renamed and moved to Kconfig in below commit
"sunxi: Move SUNXI_GMAC to Kconfig"
(sha1: 4d43d065db)

Signed-off-by: Dave Prue <dave@prue.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Tested-by: Mark Kettenis <kettenis@openbsd.org>
[Tweek commit message, config_whitelist.txt, build-whitelist.sh]
Signed-off-by: Jagan Teki <jagan@openedev.com>
2017-09-01 20:48:27 +05:30
Tom Rini
6aee2ab68c Merge git://git.denx.de/u-boot-imx
Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	configs/imx6qdl_icore_mmc_defconfig
	configs/imx6qdl_icore_rqs_defconfig
2017-09-01 10:40:59 -04:00
Tom Rini
4109d70293 Merge git://git.denx.de/u-boot-marvell 2017-09-01 10:33:21 -04:00
Tom Rini
e4adc8ed3c Merge git://git.denx.de/u-boot-uniphier
- add {ofnode,dev}_read_resource_byname
- provide DT probe hook to Denali NAND driver
- update clk/reset driver
- update DT
- misc cleanups
2017-09-01 10:32:35 -04:00
Tom Rini
9ec61dbc80 Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2017-09-01 10:31:07 -04:00
Chen-Yu Tsai
8a647fc3ca mmc: sunxi: Only update timing mode bit when enabling new timing mode
When enabling the new mmc timing mode, we inadvertently clear all the
remaining bits in the new timing mode register. The bits cleared
include a default phase delay on the output clock. The BSP kernel
states that the default values are supposed to be used. Clearing them
results in decreased performance or transfer errors on some boards.

Fixes: de9b1771c3 ("mmc: sunxi: Support new mode")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-09-01 19:49:47 +05:30
Jagan Teki
63af4b0ad0 i.MX6Q: icorem6: Add falcon mode
Add Falcon mode support in Engicam i.CoreM6 board.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-08-30 12:18:41 +02:00
Jagan Teki
46668df5d0 i.MX6Q: spl: Fix falcon to use dram_init_banksize
Memory dt node update introduced by spl_fixup_fdt() in below
commit was making DDR configuration in-appropriate
to boot falcon mode. Hence added dram_init_banksize for
explicit assignment of  proper base and size of DDR.

"boot: fdt: Perform arch_fixup_fdt() on the given device tree for falcon boot"
(sha1: 6e7585bb64)

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-08-30 12:18:26 +02:00
Stefan Agner
624da53ca8 imx: remove SATA boot mode for i.MX 6UL and 6ULL
The NXP i.MX 6UL and 6ULL do not support SATA and have no SATA
boot mode, hence remove it from the boot device detecion. This
fixes a build error introduced with 3bd1642d4d ("imx: fix USB
boot mode detection for i.MX 6UL and 6ULL")

Fixes: 3bd1642d4d ("imx: fix USB boot mode detection for i.MX 6UL and 6ULL")
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-30 12:17:53 +02:00
Chris Packham
dbc3e64fd1 ARM: mvebu: add "spi-flash" compatible string
U-boots spi-nor support is currently considered a work in progress. For
now to avoid issues it is necessary to add a "spi-flash" compatible
string. Eventually the "jedec,spi-nor" will be sufficient when the core
U-boot code is updated to support it.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-30 10:03:35 +02:00
Masahiro Yamada
0cc0c544bc ARM: uniphier: enable Denali NAND driver for 64bit SoCs
Now the entry to the NAND driver init can be is controlled by DT;
it should not hurt to compile the driver all the time.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Masahiro Yamada
d8a10e7fac ARM: uniphier: set system bus pinmux for PXs3
The system bus is not enabled by default for NAND, eMMC boot
etc. of PXs3.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Masahiro Yamada
b173c19663 ARM: uniphier: move CONFIG_NAND to defconfig
This imply was added when the option was moved by the moveconfig tool,
but the intention is not clear.  Move it to defconfig.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Masahiro Yamada
31c86aa7fd ARM: dts: uniphier: update PXs3 SoC/board DT
Support PXs3 SoC and its reference development board.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Masahiro Yamada
6c9e46efae ARM: dts: uniphier: sync with Linux
Import updates queued up for Linux 4.14-rc1.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Masahiro Yamada
111689e744 reset: uniphier: add PXs3 support
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Masahiro Yamada
1fc84d6be2 reset: uniphier: fix compatible for SD reset node for LD11/LD20
LD20 has SD ctrl instead of MIO ctrl.  LD11 has both of them.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Masahiro Yamada
d7505752bb clk: uniphier: add System clock support
Support system clocks for LD4, Pro4, sLD8, Pro5, PXs2/LD6b, LD11, LD20.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Dai Okamura
4013bbb1f3 ARM: uniphier: fix DSPLL init code for LD20 SoC
Signed-off-by: Dai Okamura <okamura.dai@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Masahiro Yamada
e0daca7de5 ARM: uniphier: remove ad-hoc pin settings for NAND
This is now set up by the pinctrl driver when the NAND driver is
probed.  Remove the legacy code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:06:57 +09:00
Masahiro Yamada
e2f87de0f8 ARM: uniphier: enable CONFIG_NAND_DENALI_DT
Migrate to the DT-based NAND init entry.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:03:11 +09:00
Masahiro Yamada
8de11a5eef ARM: uniphier: remove unneeded NAND config options
CONFIG_NAND_DENALI select's CONFIG_SYS_NAND_SELF_INIT, so the
NAND initialization process is driven by the driver itself.
CONFIG_SYS_NAND_MAX_CHIPS and CONFIG_SYS_NAND_BASE are unused.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:03:11 +09:00
Masahiro Yamada
4914a68de7 ARM: uniphier: add PLL settings for PXs3
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:03:11 +09:00
Masahiro Yamada
a55957b9ad ARM: uniphier: move PLLCTRL register macros to each SoC .c file
The new SoC PXs3 changed the address of PLL, but still uses the
same PLL name.  We can not define SC_*PLLCTRL in the common header.
Move them to per-SoC .c file.  Also, fix some PLL comments.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:03:11 +09:00
Masahiro Yamada
546197b986 ARM: uniphier: replace <common.h> with <linux/delay.h> in pll settings
The #include <common.h> was added for mdelay().  Later, the declaration
of mdelay was moved to <linux/delay.h> by commit 5bc516ed66 ("delay:
collect {m, n, u}delay declarations to include/linux/delay.h").

There is no need to include <common.h> now.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:03:11 +09:00
Masahiro Yamada
1d9654dc43 mtd: nand: denali_dt: add a DT driver
A patch for NAND uclass support was proposed about half a year ago:
https://patchwork.ozlabs.org/patch/722282/

It was not merged and I do not see on-going work for this.

Without DM-based probing, we need to set up pinctrl etc. in an ad-hoc
way and give lots of crappy CONFIG options for base addresses and
properties, which are supposed to be specified by DT.  This is painful.

This commit just provides a probe hook to retrieve "reg" from DT and
allocate private data in a DM manner.  This DT driver is not essentially
a NAND driver, in fact it is (ab)using UCLASS_MISC.  Once UCLASS_NAND is
supported, it would be possible to migrate to it.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:03:11 +09:00
Masahiro Yamada
7b8b47bd29 ofnode: add {ofnode, dev}_read_resource_byname()
Linux supports platform_get_resource_byname() to look up a resource
by name.

We want a similar helper.  It is useful when a device node has named
register regions.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-29 23:56:17 +09:00
Anatolij Gustschin
0d1ae97c02 video: ipuv3_fb: skip IPU shutdown if IPU was not enabled before
Boards can skip display interface init using board_video_skip().
If display interface was not initialized (e.g. no ipuv3 framebuffer
registered or IPU clock disabled), booting Linux stops due to the
crash in IPU shutdown function, when accessing IPU registers.
Check IPU clock and skip shutdown if clock is not enabled.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-08-29 15:23:55 +02:00
Jagan Teki
a2b137b38d icorem6: Fix to find MMC devices
U-Boot proper is using DM_MMC so, enable CONFIG_BLK otherwise
find_mmc_device failed to detect MMC device.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-08-29 09:50:40 +02:00
Anatolij Gustschin
ffc36f57bc imx6: don't include unneeded boot_mode array in SPL
The soc_boot_modes array is only used by bmode command
and not needed in SPL. Don't include it into SPL.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-08-29 09:49:51 +02:00
Anatolij Gustschin
f9d42d821c spl: do not repeat timer init on i.MX6
The GPT timer was already initialised in board_init_f() as
it is needed in dram init. Do not repeat timer init in
board_init_r().

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2017-08-29 09:48:37 +02:00
Anatolij Gustschin
ae64226dbe imx: timer: don't clear the GPT control register multiple times
There is no need to clear the control register 100 times in a
loop, a single zero write clears the register. I didn't find any
justification why clearing this register in a loop is needed
(no info in i.MX6 errata or GPT timer linux driver, linux driver
uses single write to clear this control register).

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2017-08-29 09:47:28 +02:00
Stefano Babic
cb40adff8f pfla02: Fix RAM detection and support 1 bank SOM
In case of 2 banks, the address space of the first CS must be defined
and not let to the higher value.

Add support for SOM with a single bank of RAM. It was tested with i.MX6Q
modules in the following configurations:

- 2 Banks, 4 GB
- 2 Banks, 1 GB
- 1 Bank,  1 GB

Signed-off-by: Stefano Babic <sbabic@denx.de>
2017-08-29 09:46:32 +02:00
Niko Mauno
22aa21dba4 splash_source: Verify FIT magic
Before reading entire FIT image, add sanity check by testing image
header against FDT_MAGIC. This should help avoid problems in situations
where FIT is not yet available from storage device, for example when
performing initial programming of device.

Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: Tomas Melin <tomas.melin@vaisala.com>
2017-08-29 00:20:16 +02:00
Maxime Ripard
ead3697d7e mmc: sunxi: fix legacy MMC initialisation
The driver-model rework changed, among other things, the way the private
data were moved around. It now uses the private field in the struct mmc.

However, the mmc_create argument was changed in the process to always pass
the array we used to have to store our private structures.

The basically means that all the MMC driver instances will now have the
private data of the first instance, which obviously doesn't work very well.

Pass the proper pointer to mmc_create.

Fixes: 034e226bc7 ("dm: mmc: sunxi: Pass private data around explicitly")
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-28 22:38:05 +05:30
Jagan Teki
c9319b3f20 sunxi: bpi-m3: Enable eMMC
Add CONFIG_MMC_SUNXI_SLOT_EXTRA=2 to use eMMC on
BPI_M3 board.

Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-08-28 22:36:52 +05:30
Maxime Ripard
343ff16106 sunxi: Enable MMC new mode for A83T
The eMMC controller for the A83T uses the new operating mode. Enable it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-28 22:36:48 +05:30
Maxime Ripard
de9b1771c3 mmc: sunxi: Support new mode
Almost all of the newer Allwinner SoCs have a new operating mode for the
eMMC clocks that needs to be enabled in both the clock and the MMC
controller.

Details about that mode are sparse, and the name itself (new mode vs old
mode) doesn't give much details, but it seems that the it changes the
sampling of the MMC clock. One side effect is also that it divides the
parent clock rate by 2.

Add support for it through a Kconfig option.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-28 22:36:44 +05:30
Breno Lima
3aa4b703b4 imx: imx6: Move gpr_init() function to soc.c
Since the gpr_init() function is common for boards using MX6S, MX6DL, MX6D,
MX6Q and MX6QP processors move it to the soc.c file.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-08-28 09:48:53 +02:00
Stefan Agner
962c78b1df imx: use BOOT_DEVICE_BOARD instead of UART
i.MX 6 serial downloader is not necessarily booting via UART but can
also boot from USB. In fact only some i.MX chips have serial
downloader support via UART (e.g. 6UL/ULL and Vybrid) but all of
them have serial downloader support via USB. Use the more appropriate
BOOT_DEVICE_BOARD define which is used for ROM provided recovery
mechanisms in general.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2017-08-25 13:31:47 +02:00
Stefan Agner
3bd1642d4d imx: fix USB boot mode detection for i.MX 6UL and 6ULL
Add the reserved boot mode used in the bmode command for i.MX 6UL
and 6ULL as introduced in commit 3fd9579085 ("imx: mx6ull: fix USB
bmode for i.MX 6UL and 6ULL").

Also replace BMODE_UART with BMODE_RESERVED, which is more appropriate.
Commit 96aac843b6 ("imx: Use IMX6_BMODE_* macros instead of numericals")
added macros for boot modes, in the process the reserved boot mode got
named BMODE_UART. We use the reserved boot mode in the bmode command to
let the boot ROM enter serial downloader recovery mode. But this is only
a side effect, the actual boot mode is reserved...

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2017-08-25 13:31:31 +02:00
Peng Fan
7a7bfec39e pinctrl: imx7ulp: Add new info instance for iomuxc1
To i.MX7ULP, we need to create two info instances for
iomux0 and iomux1 respectively, otherwise iomuxc0/1 will
share one info instance and use one base, because imx_pinctrl_probe
will use info to store base address and etc. But iomuxc0/1
actually have different base address.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
2017-08-23 10:48:15 +02:00
Peng Fan
63fbc59b4f pinctrl: imx: Fix mask when SHARE_MUX_CONF_REG is set
when using SHARE_MUX_CONF_REG, wrong mask is used for
writing config value, which causes mux value is cleared.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
2017-08-23 10:47:00 +02:00
Stefano Babic
7c09cbf68b imx: fix licensing in i.MX files
Some files for i.MX do not yet have the SPDX ID to reference the correct
license.

Signed-off-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Wolfgang Denk <wd@denx.de>
2017-08-23 10:45:45 +02:00
Peng Fan
fa85b0217d imx: mx7: psci: add copyright and license
Add copyright and license header.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2017-08-23 10:45:25 +02:00
Stefan Agner
f0e0698cee apalis/colibri_imx6: enable SDP by default
Enable Serial Download Protocol (SDP) in SPL and U-Boot. This is
useful to make use of imx_usb to download the complete U-Boot
(u-boot.img) after SPL has been downloaded. The U-Boot command
sdp allows to enumerate as SDP capable device again, e.g. to
download a Linux kernel and/or U-Boot script.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
2017-08-23 10:41:58 +02:00
Stefan Agner
2b2f678280 apalis/colibri_imx6: use independent USB PID for SPL
Use a completely independent USB Product ID for SPL. This allows
to differentiate a SDP running in SPL and SDP running in a U-Boot
which could not read the config block successfully.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
2017-08-23 10:41:58 +02:00
Stefan Agner
f9c39d95f1 doc: add Serial Download Protocol documentation
Document the U-Boot Serial Download Protocol implementation and
some typical use cases.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
2017-08-23 10:41:58 +02:00
Stefan Agner
a3774c1c3c spl: add serial download protocol (SDP) support
Add USB serial download protocol support to SPL. If the SoC started
in recovery mode the SPL will immediately switch to SDP and wait for
further downloads/commands from the host side.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
2017-08-23 10:41:58 +02:00
Stefan Agner
2f005695df cmd: add sdp command
Add a new command to start USB Serial Download Protocol (SDP)
state machine.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-08-23 10:41:58 +02:00
Stefan Agner
ccd7a4d2f4 usb: gadget: sdp: extend images compatible for jumps
Support U-Boot images in SPL so that u-boot.img files can be
directly downloaded and executed. Furthermore support U-Boot
scripts download and execution in full U-Boot so that custom
recovery actions can be downloaded from the host in a third
step.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-08-23 10:41:58 +02:00
Stefan Agner
5661f08a71 usb: gadget: add SDP driver
Add SDP (Serial Downloader Protocol) implementation for U-Boot. The
protocol is used in NXP SoC's boot ROM and allows to download program
images. Beside that, it can also be used to read/write registers and
download complete Device Configuration Data (DCD) sets. This basic
implementation supports downloading images with the imx header format
reading and writing registers.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
2017-08-23 10:41:58 +02:00
Stefan Agner
4e76c0774a imx: move imximage header to common location
Move the imximage.h header file to a common location so we can make
use of it from U-Boot too.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
2017-08-23 10:41:58 +02:00
872 changed files with 3535 additions and 3358 deletions

View File

@@ -162,6 +162,13 @@ endmenu # General setup
menu "Boot images"
config ANDROID_BOOT_IMAGE
bool "Enable support for Android Boot Images"
default y if FASTBOOT
help
This enables support for booting images which use the Android
image format header.
config FIT
bool "Support Flattened Image Tree"
select MD5

View File

@@ -449,6 +449,8 @@ M: Anatolij Gustschin <agust@denx.de>
S: Maintained
T: git git://git.denx.de/u-boot-video.git
F: drivers/video/
F: common/lcd*.c
F: include/lcd*.h
X86
M: Simon Glass <sjg@chromium.org>

View File

@@ -5,7 +5,7 @@
VERSION = 2017
PATCHLEVEL = 09
SUBLEVEL =
EXTRAVERSION = -rc3
EXTRAVERSION =
NAME =
# *DOCUMENTATION*
@@ -1465,14 +1465,14 @@ checkarmreloc: u-boot
false; \
fi
environ: scripts_basic
$(Q)$(MAKE) $(build)=tools/$@
envtools: scripts_basic
$(Q)$(MAKE) $(build)=tools/env
tools-only: scripts_basic $(version_h) $(timestamp_h)
$(Q)$(MAKE) $(build)=tools
tools-all: export HOST_TOOLS_ALL=y
tools-all: environ tools ;
tools-all: envtools tools ;
cross_tools: export CROSS_BUILD_TOOLS=y
cross_tools: tools ;
@@ -1586,6 +1586,7 @@ help:
@echo ' ubootrelease - Output the release version string (use with make -s)'
@echo ' ubootversion - Output the version stored in Makefile (use with make -s)'
@echo " cfg - Don't build, just create the .cfg files"
@echo " envtools - Build only the target-side environment tools"
@echo ''
@echo 'Static analysers'
@echo ' checkstack - Generate a list of stack hogs'

50
README
View File

@@ -776,7 +776,7 @@ The following options need to be configured:
binary in its image. This device tree file should be in the
board directory and called <soc>-<board>.dts. The binary file
is then picked up in board_init_f() and made available through
the global data structure as gd->blob.
the global data structure as gd->fdt_blob.
CONFIG_OF_SEPARATE
If this variable is defined, U-Boot will build a device tree
@@ -1242,50 +1242,6 @@ The following options need to be configured:
entering dfuMANIFEST state. Host waits this timeout, before
sending again an USB request to the device.
- USB Device Android Fastboot support:
CONFIG_USB_FUNCTION_FASTBOOT
This enables the USB part of the fastboot gadget
CONFIG_ANDROID_BOOT_IMAGE
This enables support for booting images which use the Android
image format header.
CONFIG_FASTBOOT_BUF_ADDR
The fastboot protocol requires a large memory buffer for
downloads. Define this to the starting RAM address to use for
downloaded images.
CONFIG_FASTBOOT_BUF_SIZE
The fastboot protocol requires a large memory buffer for
downloads. This buffer should be as large as possible for a
platform. Define this to the size available RAM for fastboot.
CONFIG_FASTBOOT_FLASH
The fastboot protocol includes a "flash" command for writing
the downloaded image to a non-volatile storage device. Define
this to enable the "fastboot flash" command.
CONFIG_FASTBOOT_FLASH_MMC_DEV
The fastboot "flash" command requires additional information
regarding the non-volatile storage device. Define this to
the eMMC device that fastboot should use to store the image.
CONFIG_FASTBOOT_GPT_NAME
The fastboot "flash" command supports writing the downloaded
image to the Protective MBR and the Primary GUID Partition
Table. (Additionally, this downloaded image is post-processed
to generate and write the Backup GUID Partition Table.)
This occurs when the specified "partition name" on the
"fastboot flash" command line matches this value.
The default is "gpt" if undefined.
CONFIG_FASTBOOT_MBR_NAME
The fastboot "flash" command supports writing the downloaded
image to DOS MBR.
This occurs when the "partition name" specified on the
"fastboot flash" command line matches this value.
If not defined the default value "mbr" is used.
- Journaling Flash filesystem support:
CONFIG_JFFS2_NAND
Define these for a default partition on a NAND device
@@ -2879,10 +2835,6 @@ FIT uImage format:
Define this if you need to first read the OOB and then the
data. This is used, for example, on davinci platforms.
CONFIG_SPL_OMAP3_ID_NAND
Support for an OMAP3-specific set of functions to return the
ID and MFR of the first attached NAND chip, if present.
CONFIG_SPL_RAM_DEVICE
Support for running image already present in ram, in SPL binary

View File

@@ -115,6 +115,9 @@ config X86
imply CMD_PCI
imply CMD_SF_TEST
imply CMD_ZBOOT
imply USB_HOST_ETHER
imply USB_ETHER_ASIX
imply USB_ETHER_SMSC95XX
config XTENSA
bool "Xtensa architecture"

View File

@@ -693,6 +693,8 @@ config ARCH_SUNXI
select USB_STORAGE if DISTRO_DEFAULTS
select USB_KEYBOARD if DISTRO_DEFAULTS
select USE_TINY_PRINTF
imply CMD_FASTBOOT
imply FASTBOOT
imply FAT_WRITE
imply PRE_CONSOLE_BUFFER
imply SPL_GPIO_SUPPORT
@@ -702,6 +704,7 @@ config ARCH_SUNXI
imply SPL_MMC_SUPPORT if MMC
imply SPL_POWER_SUPPORT
imply SPL_SERIAL_SUPPORT
imply USB_FUNCTION_FASTBOOT
config TARGET_TS4600
bool "Support TS4600"
@@ -1080,7 +1083,11 @@ config ARCH_ROCKCHIP
select DM_USB if USB
select DM_PWM
select DM_REGULATOR
imply CMD_FASTBOOT
imply FASTBOOT
imply FAT_WRITE
imply USB_FUNCTION_FASTBOOT
imply SPL_SYSRESET
config TARGET_THUNDERX_88XX
bool "Support ThunderX 88xx"

View File

@@ -154,7 +154,7 @@
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p128", "jedec,spi-nor";
compatible = "st,m25p128", "jedec,spi-nor", "spi-flash";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
m25p,fast-read;

View File

@@ -9,7 +9,7 @@
*/
/dts-v1/;
/include/ "uniphier-ld11.dtsi"
#include "uniphier-ld11.dtsi"
/ {
model = "UniPhier LD11 Global Board (REF_LD11_GP)";
@@ -68,3 +68,7 @@
&usb2 {
status = "okay";
};
&nand {
status = "okay";
};

View File

@@ -8,9 +8,9 @@
*/
/dts-v1/;
/include/ "uniphier-ld11.dtsi"
/include/ "uniphier-ref-daughter.dtsi"
/include/ "uniphier-support-card.dtsi"
#include "uniphier-ld11.dtsi"
#include "uniphier-ref-daughter.dtsi"
#include "uniphier-support-card.dtsi"
/ {
model = "UniPhier LD11 Reference Board";

View File

@@ -348,9 +348,11 @@
};
};
aidet@5fc20000 {
compatible = "simple-mfd", "syscon";
aidet: aidet@5fc20000 {
compatible = "socionext,uniphier-ld11-aidet";
reg = <0x5fc20000 0x200>;
interrupt-controller;
#interrupt-cells = <2>;
};
gic: interrupt-controller@5fe00000 {
@@ -376,6 +378,10 @@
compatible = "socionext,uniphier-ld11-reset";
#reset-cells = <1>;
};
watchdog {
compatible = "socionext,uniphier-wdt";
};
};
nand: nand@68000000 {
@@ -387,9 +393,8 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clocks = <&sys_clk 2>;
nand-ecc-strength = <8>;
};
};
};
/include/ "uniphier-pinctrl.dtsi"
#include "uniphier-pinctrl.dtsi"

View File

@@ -9,7 +9,7 @@
*/
/dts-v1/;
/include/ "uniphier-ld20.dtsi"
#include "uniphier-ld20.dtsi"
/ {
model = "UniPhier LD20 Global Board (REF_LD20_GP)";
@@ -50,3 +50,7 @@
&i2c0 {
status = "okay";
};
&nand {
status = "okay";
};

View File

@@ -8,9 +8,9 @@
*/
/dts-v1/;
/include/ "uniphier-ld20.dtsi"
/include/ "uniphier-ref-daughter.dtsi"
/include/ "uniphier-support-card.dtsi"
#include "uniphier-ld20.dtsi"
#include "uniphier-ref-daughter.dtsi"
#include "uniphier-support-card.dtsi"
/ {
model = "UniPhier LD20 Reference Board";

View File

@@ -313,7 +313,7 @@
sdctrl@59810000 {
compatible = "socionext,uniphier-ld20-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
reg = <0x59810000 0x400>;
sd_clk: clock {
compatible = "socionext,uniphier-ld20-sd-clock";
@@ -383,9 +383,11 @@
};
};
aidet@5fc20000 {
compatible = "simple-mfd", "syscon";
aidet: aidet@5fc20000 {
compatible = "socionext,uniphier-ld20-aidet";
reg = <0x5fc20000 0x200>;
interrupt-controller;
#interrupt-cells = <2>;
};
gic: interrupt-controller@5fe00000 {
@@ -411,6 +413,10 @@
compatible = "socionext,uniphier-ld20-reset";
#reset-cells = <1>;
};
watchdog {
compatible = "socionext,uniphier-wdt";
};
};
usb: usb@65b00000 {
@@ -440,9 +446,8 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clocks = <&sys_clk 2>;
nand-ecc-strength = <8>;
};
};
};
/include/ "uniphier-pinctrl.dtsi"
#include "uniphier-pinctrl.dtsi"

View File

@@ -8,9 +8,9 @@
*/
/dts-v1/;
/include/ "uniphier-ld4.dtsi"
/include/ "uniphier-ref-daughter.dtsi"
/include/ "uniphier-support-card.dtsi"
#include "uniphier-ld4.dtsi"
#include "uniphier-ref-daughter.dtsi"
#include "uniphier-support-card.dtsi"
/ {
model = "UniPhier LD4 Reference Board";

View File

@@ -424,9 +424,11 @@
interrupt-controller;
};
aidet@61830000 {
compatible = "simple-mfd", "syscon";
aidet: aidet@61830000 {
compatible = "socionext,uniphier-ld4-aidet";
reg = <0x61830000 0x200>;
interrupt-controller;
#interrupt-cells = <2>;
};
sysctrl@61840000 {
@@ -452,11 +454,10 @@
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
interrupts = <0 65 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
pinctrl-0 = <&pinctrl_nand2cs>;
clocks = <&sys_clk 2>;
nand-ecc-strength = <8>;
};
};
};
/include/ "uniphier-pinctrl.dtsi"
#include "uniphier-pinctrl.dtsi"

View File

@@ -8,9 +8,9 @@
*/
/dts-v1/;
/include/ "uniphier-ld6b.dtsi"
/include/ "uniphier-ref-daughter.dtsi"
/include/ "uniphier-support-card.dtsi"
#include "uniphier-ld6b.dtsi"
#include "uniphier-ref-daughter.dtsi"
#include "uniphier-support-card.dtsi"
/ {
model = "UniPhier LD6b Reference Board";

View File

@@ -12,7 +12,7 @@
* The D-chip (digital chip) is the same as the PXs2 die.
* Reuse the PXs2 device tree with some properties overridden.
*/
/include/ "uniphier-pxs2.dtsi"
#include "uniphier-pxs2.dtsi"
/ {
compatible = "socionext,uniphier-ld6b";

View File

@@ -8,6 +8,11 @@
*/
&pinctrl {
pinctrl_aout: aout_grp {
groups = "aout";
function = "aout";
};
pinctrl_emmc: emmc_grp {
groups = "emmc", "emmc_dat8";
function = "emmc";

View File

@@ -8,7 +8,7 @@
*/
/dts-v1/;
/include/ "uniphier-pro4.dtsi"
#include "uniphier-pro4.dtsi"
/ {
model = "UniPhier Pro4 Ace Board";

View File

@@ -8,9 +8,9 @@
*/
/dts-v1/;
/include/ "uniphier-pro4.dtsi"
/include/ "uniphier-ref-daughter.dtsi"
/include/ "uniphier-support-card.dtsi"
#include "uniphier-pro4.dtsi"
#include "uniphier-ref-daughter.dtsi"
#include "uniphier-support-card.dtsi"
/ {
model = "UniPhier Pro4 Reference Board";

View File

@@ -8,7 +8,7 @@
*/
/dts-v1/;
/include/ "uniphier-pro4.dtsi"
#include "uniphier-pro4.dtsi"
/ {
model = "UniPhier Pro4 Sanji Board";

View File

@@ -531,9 +531,11 @@
};
};
aidet@5fc20000 {
compatible = "simple-mfd", "syscon";
aidet: aidet@5fc20000 {
compatible = "socionext,uniphier-pro4-aidet";
reg = <0x5fc20000 0x200>;
interrupt-controller;
#interrupt-cells = <2>;
};
timer@60000200 {
@@ -619,9 +621,8 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clocks = <&sys_clk 2>;
nand-ecc-strength = <8>;
};
};
};
/include/ "uniphier-pinctrl.dtsi"
#include "uniphier-pinctrl.dtsi"

View File

@@ -8,7 +8,7 @@
*/
/dts-v1/;
/include/ "uniphier-pro5.dtsi"
#include "uniphier-pro5.dtsi"
/ {
model = "UniPhier Pro5 4KBOX Board";
@@ -26,7 +26,7 @@
i2c6 = &i2c6;
};
memory {
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x40000000>;
};

View File

@@ -500,7 +500,7 @@
sdctrl@59810000 {
compatible = "socionext,uniphier-pro5-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
reg = <0x59810000 0x400>;
u-boot,dm-pre-reloc;
sd_clk: clock {
@@ -542,9 +542,11 @@
};
};
aidet@5fc20000 {
compatible = "simple-mfd", "syscon";
aidet: aidet@5fc20000 {
compatible = "socionext,uniphier-pro5-aidet";
reg = <0x5fc20000 0x200>;
interrupt-controller;
#interrupt-cells = <2>;
};
timer@60000200 {
@@ -628,9 +630,8 @@
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
interrupts = <0 65 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
pinctrl-0 = <&pinctrl_nand2cs>;
clocks = <&sys_clk 2>;
nand-ecc-strength = <8>;
};
emmc: sdhc@68400000 {
@@ -670,4 +671,4 @@
};
};
/include/ "uniphier-pinctrl.dtsi"
#include "uniphier-pinctrl.dtsi"

View File

@@ -8,7 +8,7 @@
*/
/dts-v1/;
/include/ "uniphier-pxs2.dtsi"
#include "uniphier-pxs2.dtsi"
/ {
model = "UniPhier PXs2 Gentil Board";

View File

@@ -8,7 +8,7 @@
*/
/dts-v1/;
/include/ "uniphier-pxs2.dtsi"
#include "uniphier-pxs2.dtsi"
/ {
model = "UniPhier PXs2 Vodka Board";

View File

@@ -477,7 +477,7 @@
sdctrl@59810000 {
compatible = "socionext,uniphier-pxs2-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
reg = <0x59810000 0x400>;
u-boot,dm-pre-reloc;
sd_clk: clock {
@@ -554,9 +554,11 @@
};
};
aidet@5fc20000 {
compatible = "simple-mfd", "syscon";
aidet: aidet@5fc20000 {
compatible = "socionext,uniphier-pxs2-aidet";
reg = <0x5fc20000 0x200>;
interrupt-controller;
#interrupt-cells = <2>;
};
timer@60000200 {
@@ -640,11 +642,10 @@
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
interrupts = <0 65 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
pinctrl-0 = <&pinctrl_nand2cs>;
clocks = <&sys_clk 2>;
nand-ecc-strength = <8>;
};
};
};
/include/ "uniphier-pinctrl.dtsi"
#include "uniphier-pinctrl.dtsi"

View File

@@ -4,13 +4,12 @@
* Copyright (C) 2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+ X11
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
/include/ "uniphier-pxs3.dtsi"
/include/ "uniphier-ref-daughter.dtsi"
/include/ "uniphier-support-card.dtsi"
#include "uniphier-pxs3.dtsi"
#include "uniphier-support-card.dtsi"
/ {
model = "UniPhier PXs3 Reference Board";
@@ -39,7 +38,7 @@
};
&ethsc {
interrupts = <0 48 4>;
interrupts = <0 52 4>;
};
&serial0 {
@@ -49,3 +48,23 @@
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
};
&i2c2 {
status = "okay";
};
&i2c3 {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};

View File

@@ -4,46 +4,10 @@
* Copyright (C) 2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/memreserve/ 0x80000000 0x00080000;
/memreserve/ 0x80000000 0x02000000;
/ {
compatible = "socionext,uniphier-pxs3";
@@ -76,28 +40,74 @@
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x000>;
clocks = <&sys_clk 33>;
enable-method = "psci";
operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x001>;
clocks = <&sys_clk 33>;
enable-method = "psci";
operating-points-v2 = <&cluster0_opp>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x002>;
clocks = <&sys_clk 33>;
enable-method = "psci";
operating-points-v2 = <&cluster0_opp>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x003>;
clocks = <&sys_clk 33>;
enable-method = "psci";
operating-points-v2 = <&cluster0_opp>;
};
};
cluster0_opp: opp_table {
compatible = "operating-points-v2";
opp-shared;
opp-250000000 {
opp-hz = /bits/ 64 <250000000>;
clock-latency-ns = <300>;
};
opp-325000000 {
opp-hz = /bits/ 64 <325000000>;
clock-latency-ns = <300>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
clock-latency-ns = <300>;
};
opp-650000000 {
opp-hz = /bits/ 64 <650000000>;
clock-latency-ns = <300>;
};
opp-666667000 {
opp-hz = /bits/ 64 <666667000>;
clock-latency-ns = <300>;
};
opp-866667000 {
opp-hz = /bits/ 64 <866667000>;
clock-latency-ns = <300>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
clock-latency-ns = <300>;
};
opp-1300000000 {
opp-hz = /bits/ 64 <1300000000>;
clock-latency-ns = <300>;
};
};
@@ -172,6 +182,22 @@
clock-frequency = <58820000>;
};
gpio: gpio@55000000 {
compatible = "socionext,uniphier-pxs3-gpio";
reg = <0x55000000 0x200>;
interrupt-parent = <&aidet>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 0>,
<&pinctrl 96 0 0>,
<&pinctrl 160 0 0>;
gpio-ranges-group-names = "gpio_range0",
"gpio_range1",
"gpio_range2";
};
i2c0: i2c@58780000 {
compatible = "socionext,uniphier-fi2c";
status = "disabled";
@@ -205,6 +231,8 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 43 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&peri_clk 6>;
clock-frequency = <100000>;
};
@@ -251,7 +279,7 @@
sdctrl@59810000 {
compatible = "socionext,uniphier-pxs3-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
reg = <0x59810000 0x400>;
sd_clk: clock {
compatible = "socionext,uniphier-pxs3-sd-clock";
@@ -282,7 +310,6 @@
emmc: sdhc@5a000000 {
compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
status = "disabled";
reg = <0x5a000000 0x400>;
interrupts = <0 78 4>;
pinctrl-names = "default";
@@ -291,6 +318,11 @@
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
cdns,phy-input-delay-legacy = <4>;
cdns,phy-input-delay-mmc-highspeed = <2>;
cdns,phy-input-delay-mmc-ddr = <3>;
cdns,phy-dll-delay-sdclk = <21>;
cdns,phy-dll-delay-sdclk-hsmmc = <21>;
};
sd: sdhc@5a400000 {
@@ -317,9 +349,11 @@
};
};
aidet@5fc20000 {
compatible = "simple-mfd", "syscon";
aidet: aidet@5fc20000 {
compatible = "socionext,uniphier-pxs3-aidet";
reg = <0x5fc20000 0x200>;
interrupt-controller;
#interrupt-cells = <2>;
};
gic: interrupt-controller@5fe00000 {
@@ -345,10 +379,50 @@
compatible = "socionext,uniphier-pxs3-reset";
#reset-cells = <1>;
};
watchdog {
compatible = "socionext,uniphier-wdt";
};
};
usb0: usb@65b00000 {
compatible = "socionext,uniphier-pxs3-dwc3";
status = "disabled";
reg = <0x65b00000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
dwc3@65a00000 {
compatible = "snps,dwc3";
reg = <0x65a00000 0x10000>;
interrupts = <0 134 4>;
dr_mode = "host";
tx-fifo-resize;
};
};
usb1: usb@65d00000 {
compatible = "socionext,uniphier-pxs3-dwc3";
status = "disabled";
reg = <0x65d00000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
dwc3@65c00000 {
compatible = "snps,dwc3";
reg = <0x65c00000 0x10000>;
interrupts = <0 137 4>;
dr_mode = "host";
tx-fifo-resize;
};
};
nand: nand@68000000 {
compatible = "socionext,denali-nand-v5b";
compatible = "socionext,uniphier-denali-nand-v5b";
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
@@ -356,9 +430,8 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clocks = <&sys_clk 2>;
nand-ecc-strength = <8>;
};
};
};
/include/ "uniphier-pinctrl.dtsi"
#include "uniphier-pinctrl.dtsi"

View File

@@ -8,9 +8,9 @@
*/
/dts-v1/;
/include/ "uniphier-sld8.dtsi"
/include/ "uniphier-ref-daughter.dtsi"
/include/ "uniphier-support-card.dtsi"
#include "uniphier-sld8.dtsi"
#include "uniphier-ref-daughter.dtsi"
#include "uniphier-support-card.dtsi"
/ {
model = "UniPhier sLD8 Reference Board";

View File

@@ -424,9 +424,11 @@
interrupt-controller;
};
aidet@61830000 {
compatible = "simple-mfd", "syscon";
aidet: aidet@61830000 {
compatible = "socionext,uniphier-sld8-aidet";
reg = <0x61830000 0x200>;
interrupt-controller;
#interrupt-cells = <2>;
};
sysctrl@61840000 {
@@ -452,11 +454,10 @@
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
interrupts = <0 65 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
pinctrl-0 = <&pinctrl_nand2cs>;
clocks = <&sys_clk 2>;
nand-ecc-strength = <8>;
};
};
};
/include/ "uniphier-pinctrl.dtsi"
#include "uniphier-pinctrl.dtsi"

View File

@@ -10,7 +10,6 @@
#define I2C_BASE1 0x44E0B000
#define I2C_BASE2 0x4802A000
#define I2C_BASE3 0x4819C000
#define I2C_BUS_MAX 3
#define I2C_DEFAULT_BASE I2C_BASE1

View File

@@ -3,23 +3,7 @@
* Texas Instruments, <www.ti.com>
* Syed Mohammed Khasim <khasim@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation's version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef MMC_HOST_DEF_H

View File

@@ -3,12 +3,7 @@
* Copyright (C) 2010 Freescale Semiconductor, Inc.
* Copyright (C) 2009-2012 Genesi USA, Inc.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
* SPDX-License-Identifier: GPL-2.0+
*/
/*

View File

@@ -2,12 +2,7 @@
* Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
* Copyright (C) 2010 Freescale Semiconductor, Inc.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MACH_IOMUX_MX23_H__

View File

@@ -2,12 +2,7 @@
* Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
* Copyright (C) 2010 Freescale Semiconductor, Inc.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MACH_IOMUX_MX28_H__

View File

@@ -7,7 +7,6 @@
#ifndef _OMAP3_I2C_H_
#define _OMAP3_I2C_H_
#define I2C_BUS_MAX 3
#define I2C_DEFAULT_BASE I2C_BASE1
struct i2c {

View File

@@ -7,7 +7,6 @@
#ifndef _OMAP4_I2C_H_
#define _OMAP4_I2C_H_
#define I2C_BUS_MAX 4
#define I2C_DEFAULT_BASE I2C_BASE1
struct i2c {

View File

@@ -7,7 +7,6 @@
#ifndef _OMAP5_I2C_H_
#define _OMAP5_I2C_H_
#define I2C_BUS_MAX 5
#define I2C_DEFAULT_BASE I2C_BASE1
struct i2c {

View File

@@ -220,4 +220,16 @@ enum {
CLKF_MASK = 0x1fff << CLKF_SHIFT,
};
/* CRU_GLB_RST_ST */
enum {
GLB_POR_RST,
FST_GLB_RST_ST = BIT(0),
SND_GLB_RST_ST = BIT(1),
FST_GLB_TSADC_RST_ST = BIT(2),
SND_GLB_TSADC_RST_ST = BIT(3),
FST_GLB_WDT_RST_ST = BIT(4),
SND_GLB_WDT_RST_ST = BIT(5),
GLB_RST_ST_MASK = GENMASK(5, 0),
};
#endif

View File

@@ -220,6 +220,7 @@ struct sunxi_ccm_reg {
#define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20)
#define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
#define CCM_MMC_CTRL_PLL6 (0x1 << 24)
#define CCM_MMC_CTRL_MODE_SEL_NEW (0x1 << 30)
#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
#define CCM_USB_CTRL_PHY0_RST (0x1 << 0)

View File

@@ -35,16 +35,19 @@ struct sunxi_mmc {
u32 cbcr; /* 0x48 CIU byte count */
u32 bbcr; /* 0x4c BIU byte count */
u32 dbgc; /* 0x50 debug enable */
u32 res0[11];
u32 res0; /* 0x54 reserved */
u32 a12a; /* 0x58 Auto command 12 argument */
u32 ntsr; /* 0x5c New timing set register */
u32 res1[8];
u32 dmac; /* 0x80 internal DMA control */
u32 dlba; /* 0x84 internal DMA descr list base address */
u32 idst; /* 0x88 internal DMA status */
u32 idie; /* 0x8c internal DMA interrupt enable */
u32 chda; /* 0x90 */
u32 cbda; /* 0x94 */
u32 res1[26];
u32 res2[26];
#ifdef CONFIG_SUNXI_GEN_SUN6I
u32 res2[64];
u32 res3[64];
#endif
u32 fifo; /* 0x100 / 0x200 FIFO access address */
};
@@ -116,6 +119,8 @@ struct sunxi_mmc {
#define SUNXI_MMC_STATUS_CARD_DATA_BUSY (0x1 << 9)
#define SUNXI_MMC_STATUS_DATA_FSM_BUSY (0x1 << 10)
#define SUNXI_MMC_NTSR_MODE_SEL_NEW (0x1 << 31)
#define SUNXI_MMC_IDMAC_RESET (0x1 << 0)
#define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1)
#define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7)

View File

@@ -24,7 +24,7 @@ void sdelay(unsigned long);
void return_to_fel(uint32_t lr, uint32_t sp);
/* Board / SoC level designware gmac init */
#if !defined CONFIG_SPL_BUILD && defined CONFIG_SUNXI_GMAC
#if !defined CONFIG_SPL_BUILD && defined CONFIG_SUN7I_GMAC
void eth_init_board(void);
#else
static inline void eth_init_board(void) {}

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@@ -69,8 +69,13 @@ enum imx6_bmode_emi {
enum imx6_bmode {
IMX6_BMODE_EMI,
IMX6_BMODE_UART,
#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
IMX6_BMODE_QSPI,
IMX6_BMODE_RESERVED,
#else
IMX6_BMODE_RESERVED,
IMX6_BMODE_SATA,
#endif
IMX6_BMODE_SERIAL_ROM,
IMX6_BMODE_SD,
IMX6_BMODE_ESD,
@@ -85,6 +90,8 @@ static inline u8 imx6_is_bmode_from_gpr9(void)
}
u32 imx6_src_get_boot_mode(void);
void gpr_init(void);
#endif /* CONFIG_MX6 */
u32 get_nr_cpus(void);

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@@ -21,6 +21,9 @@ config ARCH_EXYNOS5
imply CRC32_VERIFY
imply CMD_HASH
imply HASH_VERIFY
imply USB_ETHER_RTL8152
imply USB_ETHER_ASIX
imply USB_ETHER_SMSC95XX
help
Samsung Exynos5 SoC family are based on ARM Cortex-A15 CPU (and
Cortex-A7 CPU in big.LITTLE configuration). There are multiple SoCs

View File

@@ -307,6 +307,10 @@ config TARGET_MX6ULL_14X14_EVK
config TARGET_NITROGEN6X
bool "nitrogen6x"
imply USB_HOST_ETHER
imply USB_ETHER_ASIX
imply USB_ETHER_SMSC95XX
imply USB_ETHER_MCS7830
config TARGET_OPOS6ULDEV
bool "Armadeus OPOS6ULDev board"

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@@ -551,6 +551,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
}
#endif
#ifndef CONFIG_SPL_BUILD
/*
* cfg_val will be used for
* Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
@@ -577,6 +578,7 @@ const struct boot_mode soc_boot_modes[] = {
{"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
{NULL, 0},
};
#endif
void reset_misc(void)
{
@@ -681,6 +683,23 @@ void imx_setup_hdmi(void)
}
#endif
void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
if (is_mx6dqp()) {
/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
writel(0x77177717, &iomux->gpr[6]);
writel(0x77177717, &iomux->gpr[7]);
} else {
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
}
#ifdef CONFIG_IMX_BOOTAUX
int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
{

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@@ -1,3 +1,10 @@
/*
* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/io.h>
#include <asm/psci.h>
#include <asm/secure.h>

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@@ -1,3 +1,10 @@
/*
* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <linux/linkage.h>

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@@ -15,6 +15,8 @@
#include <spl.h>
#include <asm/mach-imx/hab.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_MX6)
/* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 register */
u32 spl_boot_device(void)
@@ -27,7 +29,7 @@ u32 spl_boot_device(void)
* BOOT_MODE - see IMX6DQRM Table 8-1
*/
if (((bmode >> 24) & 0x03) == 0x01) /* Serial Downloader */
return BOOT_DEVICE_UART;
return BOOT_DEVICE_BOARD;
/* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */
switch ((reg & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
@@ -42,11 +44,13 @@ u32 spl_boot_device(void)
break;
}
/* Reserved: Used to force Serial Downloader */
case IMX6_BMODE_UART:
return BOOT_DEVICE_UART;
case IMX6_BMODE_RESERVED:
return BOOT_DEVICE_BOARD;
/* SATA: See 8.5.4, Table 8-20 */
#if !defined(CONFIG_MX6UL) && !defined(CONFIG_MX6ULL)
case IMX6_BMODE_SATA:
return BOOT_DEVICE_SATA;
#endif
/* Serial ROM: See 8.5.5.1, Table 8-22 */
case IMX6_BMODE_SERIAL_ROM:
/* BOOT_CFG4[2:0] */
@@ -126,3 +130,13 @@ __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
}
#endif
#if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT)
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = imx_ddr_size();
return 0;
}
#endif

View File

@@ -74,8 +74,7 @@ int timer_init(void)
__raw_writel(GPTCR_SWR, &cur_gpt->control);
/* We have no udelay by now */
for (i = 0; i < 100; i++)
__raw_writel(0, &cur_gpt->control);
__raw_writel(0, &cur_gpt->control);
i = __raw_readl(&cur_gpt->control);
i &= ~GPTCR_CLKSOURCE_MASK;

View File

@@ -20,6 +20,7 @@ config OMAP34XX
imply SPL_LIBGENERIC_SUPPORT
imply SPL_MMC_SUPPORT
imply SPL_NAND_SUPPORT
imply SPL_OMAP3_ID_NAND
imply SPL_POWER_SUPPORT
imply SPL_SERIAL_SUPPORT
imply SYS_I2C_OMAP24XX

View File

@@ -149,6 +149,12 @@ config TARGET_SNIPER
endchoice
config SPL_OMAP3_ID_NAND
bool "Support OMAP3-specific ID and MFR function"
help
Support for an OMAP3-specific set of functions to return the
ID and MFR of the first attached NAND chip, if present.
config SYS_SOC
default "omap3"

View File

@@ -2185,6 +2185,27 @@ enum {
FSO_TOEx_MARK,
TPU0TO1_MARK,
/* IPSR18 */
USB3_PWEN_IMARK,
AUDIO_CLKOUT2_B_MARK,
SSI_SCK9_B_MARK,
TS_SDEN0_E_MARK,
STP_ISEN_0_E_MARK,
RIF2_D0_B_MARK,
TPU0TO2_MARK,
FMCLK_C_MARK,
FMCLK_D_MARK,
USB3_OVC_IMARK,
AUDIO_CLKOUT3_B_MARK,
SSI_WS9_B_MARK,
TS_SPSYNC0_E_MARK,
STP_ISSYNC_0_E_MARK,
RIF2_D1_B_MARK,
TPU0TO3_MARK,
FMIN_C_MARK,
FMIN_D_MARK,
PINMUX_MARK_END,
};
@@ -3288,6 +3309,27 @@ static struct pinmux_gpio pinmux_gpios[] = {
GPIO_FN(RIF3_D1_B),
GPIO_FN(FSO_TOEx),
GPIO_FN(TPU0TO1),
/* IPSR18 */
GPIO_IFN(USB3_PWEN),
GPIO_FN(AUDIO_CLKOUT2_B),
GPIO_FN(SSI_SCK9_B),
GPIO_FN(TS_SDEN0_E),
GPIO_FN(STP_ISEN_0_E),
GPIO_FN(RIF2_D0_B),
GPIO_FN(TPU0TO2),
GPIO_FN(FMCLK_C),
GPIO_FN(FMCLK_D),
GPIO_IFN(USB3_OVC),
GPIO_FN(AUDIO_CLKOUT3_B),
GPIO_FN(SSI_WS9_B),
GPIO_FN(TS_SPSYNC0_E),
GPIO_FN(STP_ISSYNC_0_E),
GPIO_FN(RIF2_D1_B),
GPIO_FN(TPU0TO3),
GPIO_FN(FMIN_C),
GPIO_FN(FMIN_D),
};
static struct pinmux_cfg_reg pinmux_config_regs[] = {

View File

@@ -11,6 +11,7 @@
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk3288.h>
#include <asm/arch/periph.h>
#include <asm/arch/pmu_rk3288.h>
#include <asm/arch/qos_rk3288.h>
@@ -70,10 +71,48 @@ int rk3288_qos_init(void)
return 0;
}
static void rk3288_detect_reset_reason(void)
{
struct rk3288_cru *cru = rockchip_get_cru();
const char *reason;
if (IS_ERR(cru))
return;
switch (cru->cru_glb_rst_st) {
case GLB_POR_RST:
reason = "POR";
break;
case FST_GLB_RST_ST:
case SND_GLB_RST_ST:
reason = "RST";
break;
case FST_GLB_TSADC_RST_ST:
case SND_GLB_TSADC_RST_ST:
reason = "THERMAL";
break;
case FST_GLB_WDT_RST_ST:
case SND_GLB_WDT_RST_ST:
reason = "WDOG";
break;
default:
reason = "unknown reset";
}
env_set("reset_reason", reason);
/*
* Clear cru_glb_rst_st, so we can determine the last reset cause
* for following resets.
*/
rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK);
}
int board_late_init(void)
{
setup_boot_mode();
rk3288_qos_init();
rk3288_detect_reset_reason();
return rk_board_late_init();
}

View File

@@ -11,6 +11,7 @@
static const struct udevice_id rk3328_syscon_ids[] = {
{ .compatible = "rockchip,rk3328-grf", .data = ROCKCHIP_SYSCON_GRF },
{ }
};
U_BOOT_DRIVER(syscon_rk3328) = {

View File

@@ -125,6 +125,7 @@ config MACH_SUN8I_A83T
bool "sun8i (Allwinner A83T)"
select CPU_V7
select SUNXI_GEN_SUN6I
select MMC_SUNXI_HAS_NEW_MODE
select SUPPORT_SPL
config MACH_SUN8I_H3

View File

@@ -9,7 +9,6 @@ config ARCH_UNIPHIER_32BIT
select CPU_V7_HAS_NONSEC
select ARMV7_NONSEC
select ARCH_SUPPORT_PSCI
imply NAND
choice
prompt "UniPhier SoC select"

View File

@@ -78,7 +78,6 @@ static void uniphier_ld20_misc_init(void)
struct uniphier_initdata {
unsigned int soc_id;
bool nand_2cs;
void (*sbc_init)(void);
void (*pll_init)(void);
void (*clk_init)(void);
@@ -89,7 +88,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
#if defined(CONFIG_ARCH_UNIPHIER_LD4)
{
.soc_id = UNIPHIER_LD4_ID,
.nand_2cs = true,
.sbc_init = uniphier_ld4_sbc_init,
.pll_init = uniphier_ld4_pll_init,
.clk_init = uniphier_ld4_clk_init,
@@ -98,7 +96,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
{
.soc_id = UNIPHIER_PRO4_ID,
.nand_2cs = false,
.sbc_init = uniphier_sbc_init_savepin,
.pll_init = uniphier_pro4_pll_init,
.clk_init = uniphier_pro4_clk_init,
@@ -107,7 +104,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
{
.soc_id = UNIPHIER_SLD8_ID,
.nand_2cs = true,
.sbc_init = uniphier_ld4_sbc_init,
.pll_init = uniphier_ld4_pll_init,
.clk_init = uniphier_ld4_clk_init,
@@ -116,7 +112,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
{
.soc_id = UNIPHIER_PRO5_ID,
.nand_2cs = true,
.sbc_init = uniphier_sbc_init_savepin,
.clk_init = uniphier_pro5_clk_init,
},
@@ -124,7 +119,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
{
.soc_id = UNIPHIER_PXS2_ID,
.nand_2cs = true,
.sbc_init = uniphier_pxs2_sbc_init,
.clk_init = uniphier_pxs2_clk_init,
},
@@ -132,7 +126,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
{
.soc_id = UNIPHIER_LD6B_ID,
.nand_2cs = true,
.sbc_init = uniphier_pxs2_sbc_init,
.clk_init = uniphier_pxs2_clk_init,
},
@@ -140,7 +133,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
#if defined(CONFIG_ARCH_UNIPHIER_LD11)
{
.soc_id = UNIPHIER_LD11_ID,
.nand_2cs = false,
.sbc_init = uniphier_ld11_sbc_init,
.pll_init = uniphier_ld11_pll_init,
.clk_init = uniphier_ld11_clk_init,
@@ -150,7 +142,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
{
.soc_id = UNIPHIER_LD20_ID,
.nand_2cs = false,
.sbc_init = uniphier_ld11_sbc_init,
.pll_init = uniphier_ld20_pll_init,
.clk_init = uniphier_ld20_clk_init,
@@ -160,7 +151,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
#if defined(CONFIG_ARCH_UNIPHIER_PXS3)
{
.soc_id = UNIPHIER_PXS3_ID,
.nand_2cs = false,
.sbc_init = uniphier_pxs2_sbc_init,
.pll_init = uniphier_pxs3_pll_init,
.clk_init = uniphier_pxs3_clk_init,
@@ -172,7 +162,6 @@ UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_initdata, uniphier_initdata)
int board_init(void)
{
const struct uniphier_initdata *initdata;
int ret;
led_puts("U0");
@@ -188,33 +177,24 @@ int board_init(void)
led_puts("U0");
if (IS_ENABLED(CONFIG_NAND_DENALI)) {
ret = uniphier_pin_init(initdata->nand_2cs ?
"nand2cs_grp" : "nand_grp");
if (ret)
pr_err("failed to init NAND pins\n");
}
led_puts("U1");
if (initdata->pll_init)
initdata->pll_init();
led_puts("U2");
led_puts("U1");
if (initdata->clk_init)
initdata->clk_init();
led_puts("U3");
led_puts("U2");
if (initdata->misc_init)
initdata->misc_init();
led_puts("U4");
led_puts("U3");
uniphier_setup_xirq();
led_puts("U5");
led_puts("U4");
support_card_late_init();

View File

@@ -88,7 +88,7 @@ int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi)
if (!base)
return -ENOMEM;
tmp = readl(base + 8); /* SSCPLLCTRL */
tmp = readl(base + 8); /* SSCPLLCTRL3 */
tmp &= ~SC_PLLCTRL3_REGI_MASK;
tmp |= regi << SC_PLLCTRL3_REGI_SHIFT;
writel(tmp, base + 8);
@@ -133,9 +133,9 @@ int uniphier_ld20_dspll_init(unsigned long reg_base)
if (!base)
return -ENOMEM;
tmp = readl(base + 8); /* DSPLLCTRL2 */
tmp = readl(base + 4); /* DSPLLCTRL2 */
tmp |= SC_DSPLLCTRL2_K_LD;
writel(tmp, base + 8);
writel(tmp, base + 4);
iounmap(base);

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@@ -4,13 +4,24 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/delay.h>
#include <linux/io.h>
#include "../init.h"
#include "../sc64-regs.h"
#include "pll.h"
/* PLL type: SSC */
#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */
#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */
#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* DSP */
#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x1440) /* Video codec, VPE etc. */
#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1460) /* DDR memory */
/* PLL type: VPLL27 */
#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
void uniphier_ld11_pll_init(void)
{
uniphier_ld20_sscpll_init(SC_CPLLCTRL, 1960, 1, 2); /* 2000MHz -> 1960MHz */

View File

@@ -5,12 +5,31 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/delay.h>
#include "../init.h"
#include "../sc64-regs.h"
#include "pll.h"
/* PLL type: SSC */
#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */
#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */
#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* DSP */
#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* Video codec */
#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1440) /* VPE etc. */
#define SC_GPPLLCTRL (SC_BASE_ADDR | 0x1450) /* GPU/Mali */
#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1460) /* DDR memory 0 */
#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* DDR memory 1 */
#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x1480) /* DDR memory 2 */
/* PLL type: VPLL27 */
#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
/* PLL type: DSPLL */
#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540)
#define SC_A2PLLCTRL (SC_BASE_ADDR | 0x15C0)
void uniphier_ld20_pll_init(void)
{
uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);

View File

@@ -1,9 +1,64 @@
/*
* Copyright (C) 2017 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/delay.h>
#include "../init.h"
#include "../sc64-regs.h"
#include "pll.h"
/* PLL type: SSC */
#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */
#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */
#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* DSP */
#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1430) /* VPE */
#define SC_VGPLLCTRL (SC_BASE_ADDR | 0x1440)
#define SC_DECPLLCTRL (SC_BASE_ADDR | 0x1450)
#define SC_ENCPLLCTRL (SC_BASE_ADDR | 0x1460)
#define SC_PXFPLLCTRL (SC_BASE_ADDR | 0x1470)
#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1480) /* DDR memory 0 */
#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1490) /* DDR memory 1 */
#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x14a0) /* DDR memory 2 */
#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x14c0)
/* PLL type: VPLL27 */
#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
/* PLL type: DSPLL */
#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540)
void uniphier_pxs3_pll_init(void)
{
uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
/* do nothing for SPLL */
uniphier_ld20_sscpll_init(SC_SPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
uniphier_ld20_sscpll_init(SC_VPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
uniphier_ld20_sscpll_init(SC_VGPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
uniphier_ld20_sscpll_init(SC_DECPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
uniphier_ld20_sscpll_init(SC_ENCPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
uniphier_ld20_sscpll_init(SC_PXFPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
mdelay(1);
uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL);
uniphier_ld20_sscpll_ssc_en(SC_SPLL2CTRL);
uniphier_ld20_sscpll_ssc_en(SC_VPPLLCTRL);
uniphier_ld20_sscpll_ssc_en(SC_VGPLLCTRL);
uniphier_ld20_sscpll_ssc_en(SC_DECPLLCTRL);
uniphier_ld20_sscpll_ssc_en(SC_ENCPLLCTRL);
uniphier_ld20_sscpll_ssc_en(SC_PXFPLLCTRL);
uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL);
uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL);
uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL);
uniphier_ld20_sscpll_ssc_en(SC_VSPLLCTRL);
uniphier_ld20_vpll27_init(SC_VPLL27FCTRL);
uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);
uniphier_ld20_dspll_init(SC_VPLL8KCTRL);
}

View File

@@ -16,4 +16,6 @@ void uniphier_pxs2_sbc_init(void)
/* necessary for ROM boot ?? */
/* system bus output enable */
writel(0x17, PC0CTRL);
uniphier_pin_init("system_bus_grp"); /* PXs3 */
}

View File

@@ -12,27 +12,6 @@
#define SC_BASE_ADDR 0x61840000
/* PLL type: SSC */
#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* LD11/20: CPU/ARM */
#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* LD11/20: misc */
#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* LD20: IPP */
#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* LD11/20: Video codec */
#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x1440) /* LD11 */
#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1440) /* LD20: VPE etc. */
#define SC_GPPLLCTRL (SC_BASE_ADDR | 0x1450) /* LD20: GPU/Mali */
#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1460) /* LD11: DDR memory */
#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1460) /* LD20: DDR memory 0 */
#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* LD20: DDR memory 1 */
#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x1480) /* LD20: DDR memory 2 */
/* PLL type: VPLL27 */
#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
/* PLL type: DSPLL */
#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540)
#define SC_A2PLLCTRL (SC_BASE_ADDR | 0x15C0)
#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
#define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c)

View File

@@ -73,7 +73,7 @@ void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
fadt->reset_reg.addrl = IO_PORT_RESET;
fadt->reset_reg.addrh = 0;
fadt->reset_value = SYS_RST | RST_CPU;
fadt->reset_value = SYS_RST | RST_CPU | FULL_RST;
fadt->x_firmware_ctl_l = (u32)facs;
fadt->x_firmware_ctl_h = 0;

View File

@@ -169,17 +169,6 @@ static void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6);
}
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
int board_early_init_f(void)
{
ccgr_init();

View File

@@ -75,15 +75,4 @@ static inline void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6);
}
static inline void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
#endif /* _PLATINUM_H_ */

View File

@@ -955,17 +955,6 @@ static void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6);
}
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
/* Define a minimal structure so that the part number can be read via SPL */
struct mfgdata {
unsigned char tsize;

View File

@@ -570,17 +570,6 @@ static void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6);
}
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
/*
* This section requires the differentiation between iMX6 Sabre boards, but
* for now, it will configure only for the mx6q variant.

View File

@@ -39,6 +39,17 @@ static iomux_v3_cfg_t const uart_pads[] = {
#endif
};
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
/* break into full u-boot on 'c' */
if (serial_tstc() && serial_getc() == 'c')
return 1;
return 0;
}
#endif
#ifdef CONFIG_MX6QDL
/*
* Driving strength:
@@ -332,17 +343,6 @@ static void ccgr_init(void)
#endif
}
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
static void spl_dram_init(void)
{
#ifdef CONFIG_MX6QDL

View File

@@ -476,6 +476,7 @@ int board_eth_init(bd_t *bis)
}
break;
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_TXID:
if (i == FM1_DTSEC3)
mdio_mux[i] = EMI1_RGMII1;
else if (i == FM1_DTSEC4)

View File

@@ -397,6 +397,7 @@ int board_eth_init(bd_t *bis)
}
break;
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_TXID:
if (i == FM1_DTSEC3)
mdio_mux[i] = EMI1_RGMII1;
else if (i == FM1_DTSEC4)

View File

@@ -798,23 +798,6 @@ static void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6);
}
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
if (is_mx6dqp()) {
/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
writel(0x77177717, &iomux->gpr[6]);
writel(0x77177717, &iomux->gpr[7]);
} else {
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
}
static int mx6q_dcd_table[] = {
0x020e0798, 0x000C0000,
0x020e0758, 0x00000000,

View File

@@ -747,23 +747,6 @@ static void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6);
}
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
if (is_mx6dqp()) {
/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
writel(0x77177717, &iomux->gpr[6]);
writel(0x77177717, &iomux->gpr[7]);
} else {
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
}
static int mx6q_dcd_table[] = {
0x020e0798, 0x000C0000,
0x020e0758, 0x00000000,

View File

@@ -583,17 +583,6 @@ static void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6);
}
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
/*
* called from C runtime startup code (arch/arm/lib/crt0.S:_main)
* - we have a stack and a place to store GD, both in SRAM

View File

@@ -550,17 +550,6 @@ static void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6);
}
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
/*
* called from C runtime startup code (arch/arm/lib/crt0.S:_main)
* - we have a stack and a place to store GD, both in SRAM

View File

@@ -260,17 +260,6 @@ static void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6);
}
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
static void spl_dram_init(void)
{
if (is_cpu_type(MXC_CPU_MX6SOLO)) {

View File

@@ -487,18 +487,6 @@ static void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6);
}
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
static void spl_dram_init(void)
{
struct mx6_ddr_sysinfo sysinfo = {

View File

@@ -9,4 +9,10 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "pfla02"
config SPL_DRAM_1_BANK
bool "DRAM on just one bank"
help
activate, if the module has just one bank
of RAM
endif

View File

@@ -485,9 +485,9 @@ static const struct mx6_mmdc_calibration mx6_mmcd_calib = {
/* Index in RAM Chip array */
enum {
RAM_1GB,
RAM_2GB,
RAM_4GB
RAM_MT64K,
RAM_MT128K,
RAM_MT256K
};
static struct mx6_ddr3_cfg mt41k_xx[] = {
@@ -550,42 +550,11 @@ static void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6);
}
static void gpr_init(void)
static void spl_dram_init(struct mx6_ddr_sysinfo *sysinfo,
struct mx6_ddr3_cfg *mem_ddr)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
static void spl_dram_init(struct mx6_ddr3_cfg *mem_ddr)
{
struct mx6_ddr_sysinfo sysinfo = {
/* width of data bus:0=16,1=32,2=64 */
.dsize = 2,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32, /* 32Gb per CS */
/* single chip select */
.ncs = 2,
.cs1_mirror = 0,
.rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
.rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
.walat = 1, /* Write additional latency */
.ralat = 5, /* Read additional latency */
.mif3_mode = 3, /* Command prediction working mode */
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.ddr_type = DDR_TYPE_DDR3,
.refsel = 1, /* Refresh cycles at 32KHz */
.refr = 7, /* 8 refresh commands per refresh cycle */
};
mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, mem_ddr);
mx6_dram_cfg(sysinfo, &mx6_mmcd_calib, mem_ddr);
}
int board_mmc_init(bd_t *bis)
@@ -627,10 +596,12 @@ void board_boot_order(u32 *spl_boot_list)
* Function checks for mirrors in the first CS
*/
#define RAM_TEST_PATTERN 0xaa5555aa
static unsigned int pfla02_detect_ramsize(void)
#define MIN_BANK_SIZE (512 * 1024 * 1024)
static unsigned int pfla02_detect_chiptype(void)
{
u32 *p, *p1;
unsigned int offset = 512 * 1024 * 1024;
unsigned int offset = MIN_BANK_SIZE;
int i;
for (i = 0; i < 2; i++) {
@@ -649,12 +620,38 @@ static unsigned int pfla02_detect_ramsize(void)
if (*p == *p1)
return i;
}
return RAM_4GB;
return RAM_MT256K;
}
void board_init_f(ulong dummy)
{
unsigned int ramchip;
struct mx6_ddr_sysinfo sysinfo = {
/* width of data bus:0=16,1=32,2=64 */
.dsize = 2,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32, /* 512 MB */
/* single chip select */
#if IS_ENABLED(CONFIG_SPL_DRAM_1_BANK)
.ncs = 1,
#else
.ncs = 2,
#endif
.cs1_mirror = 1,
.rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
.rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
.walat = 1, /* Write additional latency */
.ralat = 5, /* Read additional latency */
.mif3_mode = 3, /* Command prediction working mode */
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.ddr_type = DDR_TYPE_DDR3,
.refsel = 1, /* Refresh cycles at 32KHz */
.refr = 7, /* 8 refresh commands per refresh cycle */
};
#ifdef CONFIG_CMD_NAND
/* Enable NAND */
setup_gpmi_nand();
@@ -682,10 +679,23 @@ void board_init_f(ulong dummy)
setup_gpios();
/* DDR initialization */
spl_dram_init(&mt41k_xx[RAM_4GB]);
ramchip = pfla02_detect_ramsize();
if (ramchip != RAM_4GB)
spl_dram_init(&mt41k_xx[ramchip]);
spl_dram_init(&sysinfo, &mt41k_xx[RAM_MT256K]);
ramchip = pfla02_detect_chiptype();
debug("Detected chip %d\n", ramchip);
#if !IS_ENABLED(CONFIG_SPL_DRAM_1_BANK)
switch (ramchip) {
case RAM_MT64K:
sysinfo.cs_density = 6;
break;
case RAM_MT128K:
sysinfo.cs_density = 10;
break;
case RAM_MT256K:
sysinfo.cs_density = 18;
break;
}
#endif
spl_dram_init(&sysinfo, &mt41k_xx[ramchip]);
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);

View File

@@ -5,4 +5,66 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/io.h>
#include <common.h>
#include <dm.h>
#include <i2c.h>
#include <i2c_eeprom.h>
#include <netdev.h>
#include "som.h"
static int valid_rk3288_som(struct rk3288_som *som)
{
unsigned char *p = (unsigned char *)som;
unsigned char *e = p + sizeof(struct rk3288_som) - 1;
int hw = 0;
while (p < e) {
hw += hweight8(*p);
p++;
}
return hw == som->bs;
}
int rk_board_late_init(void)
{
int ret;
struct udevice *dev;
struct rk3288_som opt;
int off;
/* Get the identificatioin page of M24C32-D EEPROM */
off = fdt_path_offset(gd->fdt_blob, "eeprom0");
if (off < 0) {
printf("%s: No eeprom0 path offset\n", __func__);
return off;
}
ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
if (ret) {
printf("%s: Could not find EEPROM\n", __func__);
return ret;
}
ret = i2c_set_chip_offset_len(dev, 2);
if (ret)
return ret;
ret = i2c_eeprom_read(dev, 0, (uint8_t *)&opt,
sizeof(struct rk3288_som));
if (ret) {
printf("%s: Could not read EEPROM\n", __func__);
return ret;
}
if (opt.api_version != 0 || !valid_rk3288_som(&opt)) {
printf("Invalid data or wrong EEPROM layout version.\n");
/* Proceed anyway, since there is no fallback option */
}
if (is_valid_ethaddr(opt.mac))
eth_env_set_enetaddr("ethaddr", opt.mac);
return 0;
}

View File

@@ -0,0 +1,21 @@
/*
* Copyright (C) 2017 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* rk3288_som struct represents the eeprom layout for PHYTEC RK3288 based SoMs
*/
struct rk3288_som {
unsigned char api_version; /* EEPROM layout API version */
unsigned char mod_version; /* PCM/PFL/PCA */
unsigned char option[12]; /* coding for variants */
unsigned char som_rev; /* SOM revision */
unsigned char mac[6];
unsigned char ksp; /* 1: KSP, 2: KSM */
unsigned char kspno; /* Number for KSP/KSM module */
unsigned char reserved[8]; /* not used */
unsigned char bs; /* Bits set in previous bytes */
} __attribute__ ((__packed__));

View File

@@ -1,5 +1,5 @@
DRAGONBOARD410C BOARD
M: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
M: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
S: Maintained
F: board/qualcomm/dragonboard410c/
F: include/configs/dragonboard410c.h

View File

@@ -74,10 +74,10 @@ int board_early_init_f(void)
/* SDHI0, 3 */
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314 | SD3_MSTP311);
writel(0, SD0CKCR);
writel(0, SD1CKCR);
writel(0, SD2CKCR);
writel(0, SD3CKCR);
writel(1, SD0CKCR);
writel(1, SD1CKCR);
writel(1, SD2CKCR);
writel(1, SD3CKCR);
#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */
@@ -116,7 +116,7 @@ int board_init(void)
/* USB1 pull-up */
setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
#ifdef CONFIG_RAVB
#ifdef CONFIG_RENESAS_RAVB
/* EtherAVB Enable */
/* GPSR2 */
gpio_request(GPIO_GFN_AVB_AVTP_CAPTURE_A, NULL);
@@ -158,12 +158,7 @@ int board_init(void)
udelay(1);
#endif
return 0;
}
#ifdef CONFIG_SH_SDHI
int board_mmc_init(bd_t *bis)
{
#ifdef CONFIG_MMC
/* SDHI0 */
gpio_request(GPIO_GFN_SD0_DAT0, NULL);
gpio_request(GPIO_GFN_SD0_DAT1, NULL);
@@ -227,10 +222,10 @@ int board_mmc_init(bd_t *bis)
gpio_request(GPIO_GP_3_14, NULL);
gpio_direction_output(GPIO_GP_3_15, 1); /* power on */
gpio_direction_output(GPIO_GP_3_14, 1); /* 1: 3.3V, 0: 1.8V */
#endif
return 0;
}
#endif
int dram_init(void)
{

View File

@@ -72,10 +72,10 @@ int board_early_init_f(void)
/* SDHI0 */
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314);
writel(0, SD0CKCR);
writel(0, SD1CKCR);
writel(0, SD2CKCR);
writel(0, SD3CKCR);
writel(1, SD0CKCR);
writel(1, SD1CKCR);
writel(1, SD2CKCR);
writel(1, SD3CKCR);
#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */
@@ -105,7 +105,7 @@ int board_init(void)
/* USB1 pull-up */
setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
#ifdef CONFIG_RAVB
#ifdef CONFIG_RENESAS_RAVB
/* EtherAVB Enable */
/* GPSR2 */
gpio_request(GPIO_GFN_AVB_AVTP_CAPTURE_A, NULL);
@@ -137,12 +137,7 @@ int board_init(void)
udelay(1);
#endif
return 0;
}
#ifdef CONFIG_SH_SDHI
int board_mmc_init(bd_t *bis)
{
#ifdef CONFIG_MMC
/* SDHI0 */
gpio_request(GPIO_GFN_SD0_DAT0, NULL);
gpio_request(GPIO_GFN_SD0_DAT1, NULL);
@@ -179,10 +174,10 @@ int board_mmc_init(bd_t *bis)
gpio_request(GPIO_GP_5_9, NULL);
gpio_direction_output(GPIO_GP_5_3, 0); /* 1: 3.3V, 0: 1.8V */
gpio_direction_output(GPIO_GP_5_9, 0); /* 1: 3.3V, 0: 1.8V */
#endif
return 0;
}
#endif
int dram_init(void)
{

View File

@@ -581,17 +581,6 @@ static void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6);
}
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
static void spl_dram_init(int width)
{
struct mx6_ddr_sysinfo sysinfo = {

View File

@@ -9,7 +9,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += board.o
obj-$(CONFIG_SUNXI_GMAC) += gmac.o
obj-$(CONFIG_SUN7I_GMAC) += gmac.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_SUNXI_AHCI) += ahci.o
endif

View File

@@ -122,6 +122,17 @@ int board_init(void)
return 0;
}
#if defined(CONFIG_SPL_OS_BOOT)
int spl_start_uboot(void)
{
/* break into full u-boot on 'c' */
if (serial_tstc() && serial_getc() == 'c')
return 1;
return 0;
}
#endif /* CONFIG_SPL_OS_BOOT */
#if defined(CONFIG_SPL_BUILD)
/*
* Routine: get_board_mem_timings
@@ -323,7 +334,14 @@ void board_mmc_power_init(void)
}
#endif /* CONFIG_MMC */
#if defined(CONFIG_USB_EHCI_HCD)
#if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD)
/* Call usb_stop() before starting the kernel */
void show_boot_progress(int val)
{
if (val == BOOTSTAGE_ID_RUN_OS)
usb_stop();
}
static struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,

View File

@@ -29,6 +29,7 @@
#include <dm/platform_data/serial_mxc.h>
#include <dm/platdata.h>
#include <fsl_esdhc.h>
#include <g_dnl.h>
#include <i2c.h>
#include <imx_thermal.h>
#include <linux/errno.h>
@@ -1159,17 +1160,6 @@ static void ccgr_init(void)
writel(0x000000FB, &ccm->ccosr);
}
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
static void ddr_init(int *table, int size)
{
int i;
@@ -1234,6 +1224,18 @@ void reset_cpu(ulong addr)
{
}
#ifdef CONFIG_SPL_USB_GADGET_SUPPORT
int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
{
unsigned short usb_pid;
usb_pid = TORADEX_USB_PRODUCT_NUM_OFFSET + 0xfff;
put_unaligned(usb_pid, &dev->idProduct);
return 0;
}
#endif
#endif
static struct mxc_serial_platdata mxc_serial_plat = {

View File

@@ -28,6 +28,7 @@
#include <dm/platform_data/serial_mxc.h>
#include <dm/platdata.h>
#include <fsl_esdhc.h>
#include <g_dnl.h>
#include <i2c.h>
#include <imx_thermal.h>
#include <linux/errno.h>
@@ -1036,17 +1037,6 @@ static void ccgr_init(void)
writel(0x000000FB, &ccm->ccosr);
}
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
static void ddr_init(int *table, int size)
{
int i;
@@ -1118,6 +1108,18 @@ void reset_cpu(ulong addr)
{
}
#ifdef CONFIG_SPL_USB_GADGET_SUPPORT
int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
{
unsigned short usb_pid;
usb_pid = TORADEX_USB_PRODUCT_NUM_OFFSET + 0xfff;
put_unaligned(usb_pid, &dev->idProduct);
return 0;
}
#endif
#endif
static struct mxc_serial_platdata mxc_serial_plat = {

View File

@@ -211,17 +211,6 @@ static void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6);
}
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000FF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
static void spl_dram_init(void)
{
if (is_cpu_type(MXC_CPU_MX6DL)) {

View File

@@ -266,17 +266,6 @@ static void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6);
}
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
static void spl_dram_init(void)
{
if (is_cpu_type(MXC_CPU_MX6SOLO)) {

View File

@@ -895,6 +895,13 @@ config CMD_USB
help
USB support.
config CMD_USB_SDP
bool "sdp"
select USB_FUNCTION_SDP
help
Enables the command "sdp" which is used to have U-Boot emulating the
Serial Download Protocol (SDP) via USB.
config CMD_USB_MASS_STORAGE
bool "UMS usb mass storage"
help

View File

@@ -132,6 +132,7 @@ obj-$(CONFIG_CMD_FASTBOOT) += fastboot.o
obj-$(CONFIG_CMD_FS_UUID) += fs_uuid.o
obj-$(CONFIG_CMD_USB_MASS_STORAGE) += usb_mass_storage.o
obj-$(CONFIG_CMD_USB_SDP) += usb_gadget_sdp.o
obj-$(CONFIG_CMD_THOR_DOWNLOAD) += thordown.o
obj-$(CONFIG_CMD_XIMG) += ximg.o
obj-$(CONFIG_CMD_YAFFS2) += yaffs2.o

View File

@@ -2,6 +2,7 @@ comment "FASTBOOT"
menuconfig FASTBOOT
bool "Fastboot support"
depends on USB_GADGET
if FASTBOOT
@@ -20,16 +21,20 @@ config CMD_FASTBOOT
See doc/README.android-fastboot for more information.
config ANDROID_BOOT_IMAGE
bool "Enable support for Android Boot Images"
help
This enables support for booting images which use the Android
image format header.
if USB_FUNCTION_FASTBOOT
config FASTBOOT_BUF_ADDR
hex "Define FASTBOOT buffer address"
default 0x82000000 if MX6SX || MX6SL || MX6UL || MX6SLL
default 0x81000000 if ARCH_OMAP2PLUS
default 0x42000000 if ARCH_SUNXI && !MACH_SUN9I
default 0x22000000 if ARCH_SUNXI && MACH_SUN9I
default 0x60800800 if ROCKCHIP_RK3036 || ROCKCHIP_RK3188 || \
ROCKCHIP_RK322X
default 0x800800 if ROCKCHIP_RK3288 || ROCKCHIP_RK3329 || \
ROCKCHIP_RK3399
default 0x280000 if ROCKCHIP_RK3368
default 0x100000 if ARCH_ZYNQMP
help
The fastboot protocol requires a large memory buffer for
downloads. Define this to the starting RAM address to use for
@@ -37,6 +42,10 @@ config FASTBOOT_BUF_ADDR
config FASTBOOT_BUF_SIZE
hex "Define FASTBOOT buffer size"
default 0x8000000 if ARCH_ROCKCHIP
default 0x6000000 if ARCH_ZYNQMP
default 0x2000000 if ARCH_SUNXI
default 0x7000000
help
The fastboot protocol requires a large memory buffer for
downloads. This buffer should be as large as possible for a
@@ -59,7 +68,7 @@ config FASTBOOT_FLASH
config FASTBOOT_FLASH_MMC_DEV
int "Define FASTBOOT MMC FLASH default device"
depends on FASTBOOT_FLASH
depends on FASTBOOT_FLASH && MMC
help
The fastboot "flash" command requires additional information
regarding the non-volatile storage device. Define this to

View File

@@ -284,16 +284,14 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
len = 0;
} else {
ptmp = fdt_getprop(working_fdt, nodeoffset, prop, &len);
if (!ptmp) {
printf("prop (%s) not found!\n", prop);
return 1;
}
if (len > SCRATCHPAD) {
printf("prop (%d) doesn't fit in scratchpad!\n",
len);
return 1;
}
memcpy(data, ptmp, len);
if (ptmp != NULL)
memcpy(data, ptmp, len);
ret = fdt_parse_prop(&argv[4], argc - 4, data, &len);
if (ret != 0)
return ret;

View File

@@ -30,7 +30,7 @@
#endif
/* Current I/O Device */
static int curr_device = -1;
static int curr_device;
int do_ide(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{

50
cmd/usb_gadget_sdp.c Normal file
View File

@@ -0,0 +1,50 @@
/*
* cmd_sdp.c -- sdp command
*
* Copyright (C) 2016 Toradex
* Author: Stefan Agner <stefan.agner@toradex.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <g_dnl.h>
#include <sdp.h>
#include <usb.h>
static int do_sdp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int ret = CMD_RET_FAILURE;
if (argc < 2)
return CMD_RET_USAGE;
char *usb_controller = argv[1];
int controller_index = simple_strtoul(usb_controller, NULL, 0);
board_usb_init(controller_index, USB_INIT_DEVICE);
g_dnl_clear_detach();
g_dnl_register("usb_dnl_sdp");
ret = sdp_init(controller_index);
if (ret) {
error("SDP init failed: %d", ret);
goto exit;
}
/* This command typically does not return but jumps to an image */
sdp_handle(controller_index);
error("SDP ended");
exit:
g_dnl_unregister();
board_usb_cleanup(controller_index, USB_INIT_DEVICE);
return ret;
}
U_BOOT_CMD(sdp, 2, 1, do_sdp,
"Serial Downloader Protocol",
"<USB_controller>\n"
" - serial downloader protocol via <USB_controller>\n"
);

View File

@@ -668,6 +668,12 @@ config SPL_DFU_RAM
endchoice
config SPL_USB_SDP_SUPPORT
bool "Support SDP (Serial Download Protocol)"
help
Enable Serial Download Protocol (SDP) device support in SPL. This
allows to download images into memory and execute (jump to) them
using the same protocol as implemented by the i.MX family's boot ROM.
endif
config SPL_WATCHDOG_SUPPORT
@@ -690,7 +696,7 @@ config SPL_ATF_SUPPORT
bool "Support ARM Trusted Firmware"
depends on ARM64
help
ATF(ARM Trusted Firmware) is a component for ARM arch64 which which
ATF(ARM Trusted Firmware) is a component for ARM arch64 which
is loaded by SPL(which is considered as BL2 in ATF terminology).
More detail at: https://github.com/ARM-software/arm-trusted-firmware

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