Prepare v2017.09-rc4

Signed-off-by: Tom Rini <trini@konsulko.com>
crypto/fsl: fix obj-yy in Makefile
2026-06-13 15:03:58 +03:00 · 2017-09-04 09:02:48 -04:00 · 2017-09-04 09:02:07 -04:00 · 2017-09-04 09:02:06 -04:00 · 2017-09-03 15:30:37 -04:00 · 2017-09-03 15:30:36 -04:00
693 changed files with 2491 additions and 3006 deletions
--- a/7
+++ b/7
@@ -162,6 +162,13 @@ endmenu		# General setup

 menu "Boot images"

+config ANDROID_BOOT_IMAGE
+	bool "Enable support for Android Boot Images"
+	default y if FASTBOOT
+	help
+	  This enables support for booting images which use the Android
+	  image format header.
+
 config FIT
 	bool "Support Flattened Image Tree"
 	select MD5
--- a/2
+++ b/2
@@ -5,7 +5,7 @@
 VERSION = 2017
 PATCHLEVEL = 09
 SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION = -rc4
 NAME =

 # *DOCUMENTATION*
--- a/48
+++ b/48
@@ -1242,50 +1242,6 @@ The following options need to be configured:
 		entering dfuMANIFEST state. Host waits this timeout, before
 		sending again an USB request to the device.

- USB Device Android Fastboot support:
-		CONFIG_USB_FUNCTION_FASTBOOT
-		This enables the USB part of the fastboot gadget
-
-		CONFIG_ANDROID_BOOT_IMAGE
-		This enables support for booting images which use the Android
-		image format header.
-
-		CONFIG_FASTBOOT_BUF_ADDR
-		The fastboot protocol requires a large memory buffer for
-		downloads. Define this to the starting RAM address to use for
-		downloaded images.
-
-		CONFIG_FASTBOOT_BUF_SIZE
-		The fastboot protocol requires a large memory buffer for
-		downloads. This buffer should be as large as possible for a
-		platform. Define this to the size available RAM for fastboot.
-
-		CONFIG_FASTBOOT_FLASH
-		The fastboot protocol includes a "flash" command for writing
-		the downloaded image to a non-volatile storage device. Define
-		this to enable the "fastboot flash" command.
-
-		CONFIG_FASTBOOT_FLASH_MMC_DEV
-		The fastboot "flash" command requires additional information
-		regarding the non-volatile storage device. Define this to
-		the eMMC device that fastboot should use to store the image.
-
-		CONFIG_FASTBOOT_GPT_NAME
-		The fastboot "flash" command supports writing the downloaded
-		image to the Protective MBR and the Primary GUID Partition
-		Table. (Additionally, this downloaded image is post-processed
-		to generate and write the Backup GUID Partition Table.)
-		This occurs when the specified "partition name" on the
-		"fastboot flash" command line matches this value.
-		The default is "gpt" if undefined.
-
-		CONFIG_FASTBOOT_MBR_NAME
-		The fastboot "flash" command supports writing the downloaded
-		image to DOS MBR.
-		This occurs when the "partition name" specified on the
-		"fastboot flash" command line matches this value.
-		If not defined the default value "mbr" is used.
-
 - Journaling Flash filesystem support:
 		CONFIG_JFFS2_NAND
 		Define these for a default partition on a NAND device
@@ -2879,10 +2835,6 @@ FIT uImage format:
 		Define this if you need to first read the OOB and then the
 		data. This is used, for example, on davinci platforms.

-		CONFIG_SPL_OMAP3_ID_NAND
-		Support for an OMAP3-specific set of functions to return the
-		ID and MFR of the first attached NAND chip, if present.
-
 		CONFIG_SPL_RAM_DEVICE
 		Support for running image already present in ram, in SPL binary

--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -693,6 +693,8 @@ config ARCH_SUNXI
 	select USB_STORAGE if DISTRO_DEFAULTS
 	select USB_KEYBOARD if DISTRO_DEFAULTS
 	select USE_TINY_PRINTF
+	imply CMD_FASTBOOT
+	imply FASTBOOT
 	imply FAT_WRITE
 	imply PRE_CONSOLE_BUFFER
 	imply SPL_GPIO_SUPPORT
@@ -702,6 +704,7 @@ config ARCH_SUNXI
 	imply SPL_MMC_SUPPORT if MMC
 	imply SPL_POWER_SUPPORT
 	imply SPL_SERIAL_SUPPORT
+	imply USB_FUNCTION_FASTBOOT

 config TARGET_TS4600
 	bool "Support TS4600"
@@ -1080,7 +1083,10 @@ config ARCH_ROCKCHIP
 	select DM_USB if USB
 	select DM_PWM
 	select DM_REGULATOR
+	imply CMD_FASTBOOT
+	imply FASTBOOT
 	imply FAT_WRITE
+	imply USB_FUNCTION_FASTBOOT

 config TARGET_THUNDERX_88XX
 	bool "Support ThunderX 88xx"
--- a/arch/arm/dts/armada-385-amc.dts
+++ b/arch/arm/dts/armada-385-amc.dts
@@ -154,7 +154,7 @@
 		u-boot,dm-pre-reloc;
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "st,m25p128", "jedec,spi-nor";
+		compatible = "st,m25p128", "jedec,spi-nor", "spi-flash";
 		reg = <0>; /* Chip select 0 */
 		spi-max-frequency = <50000000>;
 		m25p,fast-read;
--- a/arch/arm/dts/uniphier-ld11-global.dts
+++ b/arch/arm/dts/uniphier-ld11-global.dts
@@ -9,7 +9,7 @@
 */

 /dts-v1/;
-/include/ "uniphier-ld11.dtsi"
+#include "uniphier-ld11.dtsi"

 / {
 	model = "UniPhier LD11 Global Board (REF_LD11_GP)";
@@ -68,3 +68,7 @@
 &usb2 {
 	status = "okay";
 };
+
+&nand {
+	status = "okay";
+};
--- a/arch/arm/dts/uniphier-ld11-ref.dts
+++ b/arch/arm/dts/uniphier-ld11-ref.dts
@@ -8,9 +8,9 @@
 */

 /dts-v1/;
-/include/ "uniphier-ld11.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
+#include "uniphier-ld11.dtsi"
+#include "uniphier-ref-daughter.dtsi"
+#include "uniphier-support-card.dtsi"

 / {
 	model = "UniPhier LD11 Reference Board";
--- a/arch/arm/dts/uniphier-ld11.dtsi
+++ b/arch/arm/dts/uniphier-ld11.dtsi
@@ -348,9 +348,11 @@
 			};
 		};

-		aidet@5fc20000 {
-			compatible = "simple-mfd", "syscon";
+		aidet: aidet@5fc20000 {
+			compatible = "socionext,uniphier-ld11-aidet";
 			reg = <0x5fc20000 0x200>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
 		};

 		gic: interrupt-controller@5fe00000 {
@@ -376,6 +378,10 @@
 				compatible = "socionext,uniphier-ld11-reset";
 				#reset-cells = <1>;
 			};
+
+			watchdog {
+				compatible = "socionext,uniphier-wdt";
+			};
 		};

 		nand: nand@68000000 {
@@ -387,9 +393,8 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_nand>;
 			clocks = <&sys_clk 2>;
-			nand-ecc-strength = <8>;
 		};
 	};
 };

-/include/ "uniphier-pinctrl.dtsi"
+#include "uniphier-pinctrl.dtsi"
--- a/arch/arm/dts/uniphier-ld20-global.dts
+++ b/arch/arm/dts/uniphier-ld20-global.dts
@@ -9,7 +9,7 @@
 */

 /dts-v1/;
-/include/ "uniphier-ld20.dtsi"
+#include "uniphier-ld20.dtsi"

 / {
 	model = "UniPhier LD20 Global Board (REF_LD20_GP)";
@@ -50,3 +50,7 @@
 &i2c0 {
 	status = "okay";
 };
+
+&nand {
+	status = "okay";
+};
--- a/arch/arm/dts/uniphier-ld20-ref.dts
+++ b/arch/arm/dts/uniphier-ld20-ref.dts
@@ -8,9 +8,9 @@
 */

 /dts-v1/;
-/include/ "uniphier-ld20.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
+#include "uniphier-ld20.dtsi"
+#include "uniphier-ref-daughter.dtsi"
+#include "uniphier-support-card.dtsi"

 / {
 	model = "UniPhier LD20 Reference Board";
--- a/arch/arm/dts/uniphier-ld20.dtsi
+++ b/arch/arm/dts/uniphier-ld20.dtsi
@@ -313,7 +313,7 @@
 		sdctrl@59810000 {
 			compatible = "socionext,uniphier-ld20-sdctrl",
 				     "simple-mfd", "syscon";
-			reg = <0x59810000 0x800>;
+			reg = <0x59810000 0x400>;

 			sd_clk: clock {
 				compatible = "socionext,uniphier-ld20-sd-clock";
@@ -383,9 +383,11 @@
 			};
 		};

-		aidet@5fc20000 {
-			compatible = "simple-mfd", "syscon";
+		aidet: aidet@5fc20000 {
+			compatible = "socionext,uniphier-ld20-aidet";
 			reg = <0x5fc20000 0x200>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
 		};

 		gic: interrupt-controller@5fe00000 {
@@ -411,6 +413,10 @@
 				compatible = "socionext,uniphier-ld20-reset";
 				#reset-cells = <1>;
 			};
+
+			watchdog {
+				compatible = "socionext,uniphier-wdt";
+			};
 		};

 		usb: usb@65b00000 {
@@ -440,9 +446,8 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_nand>;
 			clocks = <&sys_clk 2>;
-			nand-ecc-strength = <8>;
 		};
 	};
 };

-/include/ "uniphier-pinctrl.dtsi"
+#include "uniphier-pinctrl.dtsi"
--- a/arch/arm/dts/uniphier-ld4-ref.dts
+++ b/arch/arm/dts/uniphier-ld4-ref.dts
@@ -8,9 +8,9 @@
 */

 /dts-v1/;
-/include/ "uniphier-ld4.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
+#include "uniphier-ld4.dtsi"
+#include "uniphier-ref-daughter.dtsi"
+#include "uniphier-support-card.dtsi"

 / {
 	model = "UniPhier LD4 Reference Board";
--- a/arch/arm/dts/uniphier-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ld4.dtsi
@@ -424,9 +424,11 @@
 			interrupt-controller;
 		};

-		aidet@61830000 {
-			compatible = "simple-mfd", "syscon";
+		aidet: aidet@61830000 {
+			compatible = "socionext,uniphier-ld4-aidet";
 			reg = <0x61830000 0x200>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
 		};

 		sysctrl@61840000 {
@@ -452,11 +454,10 @@
 			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 			interrupts = <0 65 4>;
 			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_nand>;
+			pinctrl-0 = <&pinctrl_nand2cs>;
 			clocks = <&sys_clk 2>;
-			nand-ecc-strength = <8>;
 		};
 	};
 };

-/include/ "uniphier-pinctrl.dtsi"
+#include "uniphier-pinctrl.dtsi"
--- a/arch/arm/dts/uniphier-ld6b-ref.dts
+++ b/arch/arm/dts/uniphier-ld6b-ref.dts
@@ -8,9 +8,9 @@
 */

 /dts-v1/;
-/include/ "uniphier-ld6b.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
+#include "uniphier-ld6b.dtsi"
+#include "uniphier-ref-daughter.dtsi"
+#include "uniphier-support-card.dtsi"

 / {
 	model = "UniPhier LD6b Reference Board";
--- a/arch/arm/dts/uniphier-ld6b.dtsi
+++ b/arch/arm/dts/uniphier-ld6b.dtsi
@@ -12,7 +12,7 @@
 * The D-chip (digital chip) is the same as the PXs2 die.
 * Reuse the PXs2 device tree with some properties overridden.
 */
-/include/ "uniphier-pxs2.dtsi"
+#include "uniphier-pxs2.dtsi"

 / {
 	compatible = "socionext,uniphier-ld6b";
--- a/arch/arm/dts/uniphier-pinctrl.dtsi
+++ b/arch/arm/dts/uniphier-pinctrl.dtsi
@@ -8,6 +8,11 @@
 */

 &pinctrl {
+	pinctrl_aout: aout_grp {
+		groups = "aout";
+		function = "aout";
+	};
+
 	pinctrl_emmc: emmc_grp {
 		groups = "emmc", "emmc_dat8";
 		function = "emmc";
--- a/arch/arm/dts/uniphier-pro4-ace.dts
+++ b/arch/arm/dts/uniphier-pro4-ace.dts
@@ -8,7 +8,7 @@
 */

 /dts-v1/;
-/include/ "uniphier-pro4.dtsi"
+#include "uniphier-pro4.dtsi"

 / {
 	model = "UniPhier Pro4 Ace Board";
--- a/arch/arm/dts/uniphier-pro4-ref.dts
+++ b/arch/arm/dts/uniphier-pro4-ref.dts
@@ -8,9 +8,9 @@
 */

 /dts-v1/;
-/include/ "uniphier-pro4.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
+#include "uniphier-pro4.dtsi"
+#include "uniphier-ref-daughter.dtsi"
+#include "uniphier-support-card.dtsi"

 / {
 	model = "UniPhier Pro4 Reference Board";
--- a/arch/arm/dts/uniphier-pro4-sanji.dts
+++ b/arch/arm/dts/uniphier-pro4-sanji.dts
@@ -8,7 +8,7 @@
 */

 /dts-v1/;
-/include/ "uniphier-pro4.dtsi"
+#include "uniphier-pro4.dtsi"

 / {
 	model = "UniPhier Pro4 Sanji Board";
--- a/arch/arm/dts/uniphier-pro4.dtsi
+++ b/arch/arm/dts/uniphier-pro4.dtsi
@@ -531,9 +531,11 @@
 			};
 		};

-		aidet@5fc20000 {
-			compatible = "simple-mfd", "syscon";
+		aidet: aidet@5fc20000 {
+			compatible = "socionext,uniphier-pro4-aidet";
 			reg = <0x5fc20000 0x200>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
 		};

 		timer@60000200 {
@@ -619,9 +621,8 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_nand>;
 			clocks = <&sys_clk 2>;
-			nand-ecc-strength = <8>;
 		};
 	};
 };

-/include/ "uniphier-pinctrl.dtsi"
+#include "uniphier-pinctrl.dtsi"
--- a/arch/arm/dts/uniphier-pro5-4kbox.dts
+++ b/arch/arm/dts/uniphier-pro5-4kbox.dts
@@ -8,7 +8,7 @@
 */

 /dts-v1/;
-/include/ "uniphier-pro5.dtsi"
+#include "uniphier-pro5.dtsi"

 / {
 	model = "UniPhier Pro5 4KBOX Board";
@@ -26,7 +26,7 @@
 		i2c6 = &i2c6;
 	};

-	memory {
+	memory@80000000 {
 		device_type = "memory";
 		reg = <0x80000000 0x40000000>;
 	};
--- a/arch/arm/dts/uniphier-pro5.dtsi
+++ b/arch/arm/dts/uniphier-pro5.dtsi
@@ -500,7 +500,7 @@
 		sdctrl@59810000 {
 			compatible = "socionext,uniphier-pro5-sdctrl",
 				     "simple-mfd", "syscon";
-			reg = <0x59810000 0x800>;
+			reg = <0x59810000 0x400>;
 			u-boot,dm-pre-reloc;

 			sd_clk: clock {
@@ -542,9 +542,11 @@
 			};
 		};

-		aidet@5fc20000 {
-			compatible = "simple-mfd", "syscon";
+		aidet: aidet@5fc20000 {
+			compatible = "socionext,uniphier-pro5-aidet";
 			reg = <0x5fc20000 0x200>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
 		};

 		timer@60000200 {
@@ -628,9 +630,8 @@
 			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 			interrupts = <0 65 4>;
 			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_nand>;
+			pinctrl-0 = <&pinctrl_nand2cs>;
 			clocks = <&sys_clk 2>;
-			nand-ecc-strength = <8>;
 		};

 		emmc: sdhc@68400000 {
@@ -670,4 +671,4 @@
 	};
 };

-/include/ "uniphier-pinctrl.dtsi"
+#include "uniphier-pinctrl.dtsi"
--- a/arch/arm/dts/uniphier-pxs2-gentil.dts
+++ b/arch/arm/dts/uniphier-pxs2-gentil.dts
@@ -8,7 +8,7 @@
 */

 /dts-v1/;
-/include/ "uniphier-pxs2.dtsi"
+#include "uniphier-pxs2.dtsi"

 / {
 	model = "UniPhier PXs2 Gentil Board";
--- a/arch/arm/dts/uniphier-pxs2-vodka.dts
+++ b/arch/arm/dts/uniphier-pxs2-vodka.dts
@@ -8,7 +8,7 @@
 */

 /dts-v1/;
-/include/ "uniphier-pxs2.dtsi"
+#include "uniphier-pxs2.dtsi"

 / {
 	model = "UniPhier PXs2 Vodka Board";
--- a/arch/arm/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/dts/uniphier-pxs2.dtsi
@@ -477,7 +477,7 @@
 		sdctrl@59810000 {
 			compatible = "socionext,uniphier-pxs2-sdctrl",
 				     "simple-mfd", "syscon";
-			reg = <0x59810000 0x800>;
+			reg = <0x59810000 0x400>;
 			u-boot,dm-pre-reloc;

 			sd_clk: clock {
@@ -554,9 +554,11 @@
 			};
 		};

-		aidet@5fc20000 {
-			compatible = "simple-mfd", "syscon";
+		aidet: aidet@5fc20000 {
+			compatible = "socionext,uniphier-pxs2-aidet";
 			reg = <0x5fc20000 0x200>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
 		};

 		timer@60000200 {
@@ -640,11 +642,10 @@
 			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 			interrupts = <0 65 4>;
 			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_nand>;
+			pinctrl-0 = <&pinctrl_nand2cs>;
 			clocks = <&sys_clk 2>;
-			nand-ecc-strength = <8>;
 		};
 	};
 };

-/include/ "uniphier-pinctrl.dtsi"
+#include "uniphier-pinctrl.dtsi"
--- a/arch/arm/dts/uniphier-pxs3-ref.dts
+++ b/arch/arm/dts/uniphier-pxs3-ref.dts
@@ -4,13 +4,12 @@
 * Copyright (C) 2017 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 *
- * SPDX-License-Identifier:	GPL-2.0+	X11
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 */

 /dts-v1/;
-/include/ "uniphier-pxs3.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
+#include "uniphier-pxs3.dtsi"
+#include "uniphier-support-card.dtsi"

 / {
 	model = "UniPhier PXs3 Reference Board";
@@ -39,7 +38,7 @@
 };

 &ethsc {
-	interrupts = <0 48 4>;
+	interrupts = <0 52 4>;
 };

 &serial0 {
@@ -49,3 +48,23 @@
 &i2c0 {
 	status = "okay";
 };
+
+&i2c1 {
+	status = "okay";
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&i2c3 {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};
--- a/arch/arm/dts/uniphier-pxs3.dtsi
+++ b/arch/arm/dts/uniphier-pxs3.dtsi
@@ -4,46 +4,10 @@
 * Copyright (C) 2017 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 */

-/memreserve/ 0x80000000 0x00080000;
+/memreserve/ 0x80000000 0x02000000;

 / {
 	compatible = "socionext,uniphier-pxs3";
@@ -76,28 +40,74 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0 0x000>;
+			clocks = <&sys_clk 33>;
 			enable-method = "psci";
+			operating-points-v2 = <&cluster0_opp>;
 		};

 		cpu1: cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0 0x001>;
+			clocks = <&sys_clk 33>;
 			enable-method = "psci";
+			operating-points-v2 = <&cluster0_opp>;
 		};

 		cpu2: cpu@2 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0 0x002>;
+			clocks = <&sys_clk 33>;
 			enable-method = "psci";
+			operating-points-v2 = <&cluster0_opp>;
 		};

 		cpu3: cpu@3 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0 0x003>;
+			clocks = <&sys_clk 33>;
 			enable-method = "psci";
+			operating-points-v2 = <&cluster0_opp>;
+		};
+	};
+
+	cluster0_opp: opp_table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-250000000 {
+			opp-hz = /bits/ 64 <250000000>;
+			clock-latency-ns = <300>;
+		};
+		opp-325000000 {
+			opp-hz = /bits/ 64 <325000000>;
+			clock-latency-ns = <300>;
+		};
+		opp-500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			clock-latency-ns = <300>;
+		};
+		opp-650000000 {
+			opp-hz = /bits/ 64 <650000000>;
+			clock-latency-ns = <300>;
+		};
+		opp-666667000 {
+			opp-hz = /bits/ 64 <666667000>;
+			clock-latency-ns = <300>;
+		};
+		opp-866667000 {
+			opp-hz = /bits/ 64 <866667000>;
+			clock-latency-ns = <300>;
+		};
+		opp-1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			clock-latency-ns = <300>;
+		};
+		opp-1300000000 {
+			opp-hz = /bits/ 64 <1300000000>;
+			clock-latency-ns = <300>;
 		};
 	};

@@ -172,6 +182,22 @@
 			clock-frequency = <58820000>;
 		};

+		gpio: gpio@55000000 {
+			compatible = "socionext,uniphier-pxs3-gpio";
+			reg = <0x55000000 0x200>;
+			interrupt-parent = <&aidet>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pinctrl 0 0 0>,
+				      <&pinctrl 96 0 0>,
+				      <&pinctrl 160 0 0>;
+			gpio-ranges-group-names = "gpio_range0",
+						  "gpio_range1",
+						  "gpio_range2";
+		};
+
 		i2c0: i2c@58780000 {
 			compatible = "socionext,uniphier-fi2c";
 			status = "disabled";
@@ -205,6 +231,8 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupts = <0 43 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c2>;
 			clocks = <&peri_clk 6>;
 			clock-frequency = <100000>;
 		};
@@ -251,7 +279,7 @@
 		sdctrl@59810000 {
 			compatible = "socionext,uniphier-pxs3-sdctrl",
 				     "simple-mfd", "syscon";
-			reg = <0x59810000 0x800>;
+			reg = <0x59810000 0x400>;

 			sd_clk: clock {
 				compatible = "socionext,uniphier-pxs3-sd-clock";
@@ -282,7 +310,6 @@

 		emmc: sdhc@5a000000 {
 			compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
-			status = "disabled";
 			reg = <0x5a000000 0x400>;
 			interrupts = <0 78 4>;
 			pinctrl-names = "default";
@@ -291,6 +318,11 @@
 			bus-width = <8>;
 			mmc-ddr-1_8v;
 			mmc-hs200-1_8v;
+			cdns,phy-input-delay-legacy = <4>;
+			cdns,phy-input-delay-mmc-highspeed = <2>;
+			cdns,phy-input-delay-mmc-ddr = <3>;
+			cdns,phy-dll-delay-sdclk = <21>;
+			cdns,phy-dll-delay-sdclk-hsmmc = <21>;
 		};

 		sd: sdhc@5a400000 {
@@ -317,9 +349,11 @@
 			};
 		};

-		aidet@5fc20000 {
-			compatible = "simple-mfd", "syscon";
+		aidet: aidet@5fc20000 {
+			compatible = "socionext,uniphier-pxs3-aidet";
 			reg = <0x5fc20000 0x200>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
 		};

 		gic: interrupt-controller@5fe00000 {
@@ -345,10 +379,50 @@
 				compatible = "socionext,uniphier-pxs3-reset";
 				#reset-cells = <1>;
 			};
+
+			watchdog {
+				compatible = "socionext,uniphier-wdt";
+			};
+		};
+
+		usb0: usb@65b00000 {
+			compatible = "socionext,uniphier-pxs3-dwc3";
+			status = "disabled";
+			reg = <0x65b00000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
+			dwc3@65a00000 {
+				compatible = "snps,dwc3";
+				reg = <0x65a00000 0x10000>;
+				interrupts = <0 134 4>;
+				dr_mode = "host";
+				tx-fifo-resize;
+			};
+		};
+
+		usb1: usb@65d00000 {
+			compatible = "socionext,uniphier-pxs3-dwc3";
+			status = "disabled";
+			reg = <0x65d00000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
+			dwc3@65c00000 {
+				compatible = "snps,dwc3";
+				reg = <0x65c00000 0x10000>;
+				interrupts = <0 137 4>;
+				dr_mode = "host";
+				tx-fifo-resize;
+			};
 		};

 		nand: nand@68000000 {
-			compatible = "socionext,denali-nand-v5b";
+			compatible = "socionext,uniphier-denali-nand-v5b";
 			status = "disabled";
 			reg-names = "nand_data", "denali_reg";
 			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
@@ -356,9 +430,8 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_nand>;
 			clocks = <&sys_clk 2>;
-			nand-ecc-strength = <8>;
 		};
 	};
 };

-/include/ "uniphier-pinctrl.dtsi"
+#include "uniphier-pinctrl.dtsi"
--- a/arch/arm/dts/uniphier-sld8-ref.dts
+++ b/arch/arm/dts/uniphier-sld8-ref.dts
@@ -8,9 +8,9 @@
 */

 /dts-v1/;
-/include/ "uniphier-sld8.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
+#include "uniphier-sld8.dtsi"
+#include "uniphier-ref-daughter.dtsi"
+#include "uniphier-support-card.dtsi"

 / {
 	model = "UniPhier sLD8 Reference Board";
--- a/arch/arm/dts/uniphier-sld8.dtsi
+++ b/arch/arm/dts/uniphier-sld8.dtsi
@@ -424,9 +424,11 @@
 			interrupt-controller;
 		};

-		aidet@61830000 {
-			compatible = "simple-mfd", "syscon";
+		aidet: aidet@61830000 {
+			compatible = "socionext,uniphier-sld8-aidet";
 			reg = <0x61830000 0x200>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
 		};

 		sysctrl@61840000 {
@@ -452,11 +454,10 @@
 			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 			interrupts = <0 65 4>;
 			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_nand>;
+			pinctrl-0 = <&pinctrl_nand2cs>;
 			clocks = <&sys_clk 2>;
-			nand-ecc-strength = <8>;
 		};
 	};
 };

-/include/ "uniphier-pinctrl.dtsi"
+#include "uniphier-pinctrl.dtsi"
--- a/arch/arm/include/asm/arch-am33xx/i2c.h
+++ b/arch/arm/include/asm/arch-am33xx/i2c.h
@@ -10,7 +10,6 @@
 #define  I2C_BASE1		0x44E0B000
 #define  I2C_BASE2		0x4802A000
 #define  I2C_BASE3		0x4819C000
-#define	 I2C_BUS_MAX		3

 #define I2C_DEFAULT_BASE		I2C_BASE1

--- a/arch/arm/include/asm/arch-mx35/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-mx35/mmc_host_def.h
@@ -3,23 +3,7 @@
 * Texas Instruments, <www.ti.com>
 * Syed Mohammed Khasim <khasim@ti.com>
 *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation's version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0
 */

 #ifndef MMC_HOST_DEF_H
--- a/arch/arm/include/asm/arch-mx5/iomux-mx51.h
+++ b/arch/arm/include/asm/arch-mx5/iomux-mx51.h
@@ -3,12 +3,7 @@
 * Copyright (C) 2010 Freescale Semiconductor, Inc.
 * Copyright (C) 2009-2012 Genesi USA, Inc.
 *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ * SPDX-License-Identifier:	GPL-2.0+
 */

 /*
--- a/arch/arm/include/asm/arch-mxs/iomux-mx23.h
+++ b/arch/arm/include/asm/arch-mxs/iomux-mx23.h
@@ -2,12 +2,7 @@
 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
 * Copyright (C) 2010 Freescale Semiconductor, Inc.
 *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ * SPDX-License-Identifier:	GPL-2.0+
 */

 #ifndef __MACH_IOMUX_MX23_H__
--- a/arch/arm/include/asm/arch-mxs/iomux-mx28.h
+++ b/arch/arm/include/asm/arch-mxs/iomux-mx28.h
@@ -2,12 +2,7 @@
 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
 * Copyright (C) 2010 Freescale Semiconductor, Inc.
 *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ * SPDX-License-Identifier:	GPL-2.0+
 */

 #ifndef __MACH_IOMUX_MX28_H__
--- a/arch/arm/include/asm/arch-omap3/i2c.h
+++ b/arch/arm/include/asm/arch-omap3/i2c.h
@@ -7,7 +7,6 @@
 #ifndef _OMAP3_I2C_H_
 #define _OMAP3_I2C_H_

-#define I2C_BUS_MAX	3
 #define I2C_DEFAULT_BASE	I2C_BASE1

 struct i2c {
--- a/arch/arm/include/asm/arch-omap4/i2c.h
+++ b/arch/arm/include/asm/arch-omap4/i2c.h
@@ -7,7 +7,6 @@
 #ifndef _OMAP4_I2C_H_
 #define _OMAP4_I2C_H_

-#define I2C_BUS_MAX	4
 #define I2C_DEFAULT_BASE	I2C_BASE1

 struct i2c {
--- a/arch/arm/include/asm/arch-omap5/i2c.h
+++ b/arch/arm/include/asm/arch-omap5/i2c.h
@@ -7,7 +7,6 @@
 #ifndef _OMAP5_I2C_H_
 #define _OMAP5_I2C_H_

-#define I2C_BUS_MAX	5
 #define I2C_DEFAULT_BASE	I2C_BASE1

 struct i2c {
--- a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h
@@ -220,6 +220,7 @@ struct sunxi_ccm_reg {
 #define CCM_MMC_CTRL_SCLK_DLY(x)	((x) << 20)
 #define CCM_MMC_CTRL_OSCM24		(0x0 << 24)
 #define CCM_MMC_CTRL_PLL6		(0x1 << 24)
+#define CCM_MMC_CTRL_MODE_SEL_NEW	(0x1 << 30)
 #define CCM_MMC_CTRL_ENABLE		(0x1 << 31)

 #define CCM_USB_CTRL_PHY0_RST (0x1 << 0)
--- a/arch/arm/include/asm/arch-sunxi/mmc.h
+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
@@ -35,16 +35,19 @@ struct sunxi_mmc {
 	u32 cbcr;		/* 0x48 CIU byte count */
 	u32 bbcr;		/* 0x4c BIU byte count */
 	u32 dbgc;		/* 0x50 debug enable */
-	u32 res0[11];
+	u32 res0;		/* 0x54 reserved */
+	u32 a12a;		/* 0x58 Auto command 12 argument */
+	u32 ntsr;		/* 0x5c	New timing set register */
+	u32 res1[8];
 	u32 dmac;		/* 0x80 internal DMA control */
 	u32 dlba;		/* 0x84 internal DMA descr list base address */
 	u32 idst;		/* 0x88 internal DMA status */
 	u32 idie;		/* 0x8c internal DMA interrupt enable */
 	u32 chda;		/* 0x90 */
 	u32 cbda;		/* 0x94 */
-	u32 res1[26];
+	u32 res2[26];
 #ifdef CONFIG_SUNXI_GEN_SUN6I
-	u32 res2[64];
+	u32 res3[64];
 #endif
 	u32 fifo;		/* 0x100 / 0x200 FIFO access address */
 };
@@ -116,6 +119,8 @@ struct sunxi_mmc {
 #define SUNXI_MMC_STATUS_CARD_DATA_BUSY		(0x1 << 9)
 #define SUNXI_MMC_STATUS_DATA_FSM_BUSY		(0x1 << 10)

+#define SUNXI_MMC_NTSR_MODE_SEL_NEW		(0x1 << 31)
+
 #define SUNXI_MMC_IDMAC_RESET		(0x1 << 0)
 #define SUNXI_MMC_IDMAC_FIXBURST	(0x1 << 1)
 #define SUNXI_MMC_IDMAC_ENABLE		(0x1 << 7)
--- a/arch/arm/include/asm/arch-sunxi/sys_proto.h
+++ b/arch/arm/include/asm/arch-sunxi/sys_proto.h
@@ -24,7 +24,7 @@ void sdelay(unsigned long);
 void return_to_fel(uint32_t lr, uint32_t sp);

 /* Board / SoC level designware gmac init */
-#if !defined CONFIG_SPL_BUILD && defined CONFIG_SUNXI_GMAC
+#if !defined CONFIG_SPL_BUILD && defined CONFIG_SUN7I_GMAC
 void eth_init_board(void);
 #else
 static inline void eth_init_board(void) {}
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -69,8 +69,13 @@ enum imx6_bmode_emi {

 enum imx6_bmode {
 	IMX6_BMODE_EMI,
-	IMX6_BMODE_UART,
+#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
+	IMX6_BMODE_QSPI,
+	IMX6_BMODE_RESERVED,
+#else
+	IMX6_BMODE_RESERVED,
 	IMX6_BMODE_SATA,
+#endif
 	IMX6_BMODE_SERIAL_ROM,
 	IMX6_BMODE_SD,
 	IMX6_BMODE_ESD,
@@ -85,6 +90,8 @@ static inline u8 imx6_is_bmode_from_gpr9(void)
 }

 u32 imx6_src_get_boot_mode(void);
+void gpr_init(void);
+
 #endif /* CONFIG_MX6 */

 u32 get_nr_cpus(void);
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -551,6 +551,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 }
 #endif

+#ifndef CONFIG_SPL_BUILD
 /*
 * cfg_val will be used for
 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
@@ -577,6 +578,7 @@ const struct boot_mode soc_boot_modes[] = {
 	{"esdhc4",	MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 	{NULL,		0},
 };
+#endif

 void reset_misc(void)
 {
@@ -681,6 +683,23 @@ void imx_setup_hdmi(void)
 }
 #endif

+void gpr_init(void)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* enable AXI cache for VDOA/VPU/IPU */
+	writel(0xF00000CF, &iomux->gpr[4]);
+	if (is_mx6dqp()) {
+		/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
+		writel(0x77177717, &iomux->gpr[6]);
+		writel(0x77177717, &iomux->gpr[7]);
+	} else {
+		/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+		writel(0x007F007F, &iomux->gpr[6]);
+		writel(0x007F007F, &iomux->gpr[7]);
+	}
+}
+
 #ifdef CONFIG_IMX_BOOTAUX
 int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
 {
--- a/arch/arm/mach-imx/mx7/psci-mx7.c
+++ b/arch/arm/mach-imx/mx7/psci-mx7.c
@@ -1,3 +1,10 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
 #include <asm/io.h>
 #include <asm/psci.h>
 #include <asm/secure.h>
--- a/arch/arm/mach-imx/mx7/psci.S
+++ b/arch/arm/mach-imx/mx7/psci.S
@@ -1,3 +1,10 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
 #include <config.h>
 #include <linux/linkage.h>

--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -15,6 +15,8 @@
 #include <spl.h>
 #include <asm/mach-imx/hab.h>

+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_MX6)
 /* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 register */
 u32 spl_boot_device(void)
@@ -27,7 +29,7 @@ u32 spl_boot_device(void)
 	 * BOOT_MODE - see IMX6DQRM Table 8-1
 	 */
 	if (((bmode >> 24) & 0x03) == 0x01) /* Serial Downloader */
-		return BOOT_DEVICE_UART;
+		return BOOT_DEVICE_BOARD;

 	/* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */
 	switch ((reg & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
@@ -42,11 +44,13 @@ u32 spl_boot_device(void)
 		break;
 		}
 	/* Reserved: Used to force Serial Downloader */
-	case IMX6_BMODE_UART:
-		return BOOT_DEVICE_UART;
+	case IMX6_BMODE_RESERVED:
+		return BOOT_DEVICE_BOARD;
 	/* SATA: See 8.5.4, Table 8-20 */
+#if !defined(CONFIG_MX6UL) && !defined(CONFIG_MX6ULL)
 	case IMX6_BMODE_SATA:
 		return BOOT_DEVICE_SATA;
+#endif
 	/* Serial ROM: See 8.5.5.1, Table 8-22 */
 	case IMX6_BMODE_SERIAL_ROM:
 		/* BOOT_CFG4[2:0] */
@@ -126,3 +130,13 @@ __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 }

 #endif
+
+#if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT)
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = imx_ddr_size();
+
+	return 0;
+}
+#endif
--- a/arch/arm/mach-imx/timer.c
+++ b/arch/arm/mach-imx/timer.c
@@ -74,8 +74,7 @@ int timer_init(void)
 	__raw_writel(GPTCR_SWR, &cur_gpt->control);

 	/* We have no udelay by now */
-	for (i = 0; i < 100; i++)
-		__raw_writel(0, &cur_gpt->control);
+	__raw_writel(0, &cur_gpt->control);

 	i = __raw_readl(&cur_gpt->control);
 	i &= ~GPTCR_CLKSOURCE_MASK;
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -20,6 +20,7 @@ config OMAP34XX
 	imply SPL_LIBGENERIC_SUPPORT
 	imply SPL_MMC_SUPPORT
 	imply SPL_NAND_SUPPORT
+	imply SPL_OMAP3_ID_NAND
 	imply SPL_POWER_SUPPORT
 	imply SPL_SERIAL_SUPPORT
 	imply SYS_I2C_OMAP24XX
--- a/arch/arm/mach-omap2/omap3/Kconfig
+++ b/arch/arm/mach-omap2/omap3/Kconfig
@@ -149,6 +149,12 @@ config TARGET_SNIPER

 endchoice

+config SPL_OMAP3_ID_NAND
+	bool "Support OMAP3-specific ID and MFR function"
+	help
+	  Support for an OMAP3-specific set of functions to return the
+	  ID and MFR of the first attached NAND chip, if present.
+
 config SYS_SOC
 	default "omap3"

--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -125,6 +125,7 @@ config MACH_SUN8I_A83T
 	bool "sun8i (Allwinner A83T)"
 	select CPU_V7
 	select SUNXI_GEN_SUN6I
+	select MMC_SUNXI_HAS_NEW_MODE
 	select SUPPORT_SPL

 config MACH_SUN8I_H3
--- a/arch/arm/mach-uniphier/Kconfig
+++ b/arch/arm/mach-uniphier/Kconfig
@@ -9,7 +9,6 @@ config ARCH_UNIPHIER_32BIT
 	select CPU_V7_HAS_NONSEC
 	select ARMV7_NONSEC
 	select ARCH_SUPPORT_PSCI
-	imply NAND

 choice
        prompt "UniPhier SoC select"
--- a/arch/arm/mach-uniphier/board_init.c
+++ b/arch/arm/mach-uniphier/board_init.c
@@ -78,7 +78,6 @@ static void uniphier_ld20_misc_init(void)

 struct uniphier_initdata {
 	unsigned int soc_id;
-	bool nand_2cs;
 	void (*sbc_init)(void);
 	void (*pll_init)(void);
 	void (*clk_init)(void);
@@ -89,7 +88,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
 	{
 		.soc_id = UNIPHIER_LD4_ID,
-		.nand_2cs = true,
 		.sbc_init = uniphier_ld4_sbc_init,
 		.pll_init = uniphier_ld4_pll_init,
 		.clk_init = uniphier_ld4_clk_init,
@@ -98,7 +96,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
 #if defined(CONFIG_ARCH_UNIPHIER_PRO4)
 	{
 		.soc_id = UNIPHIER_PRO4_ID,
-		.nand_2cs = false,
 		.sbc_init = uniphier_sbc_init_savepin,
 		.pll_init = uniphier_pro4_pll_init,
 		.clk_init = uniphier_pro4_clk_init,
@@ -107,7 +104,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
 #if defined(CONFIG_ARCH_UNIPHIER_SLD8)
 	{
 		.soc_id = UNIPHIER_SLD8_ID,
-		.nand_2cs = true,
 		.sbc_init = uniphier_ld4_sbc_init,
 		.pll_init = uniphier_ld4_pll_init,
 		.clk_init = uniphier_ld4_clk_init,
@@ -116,7 +112,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
 #if defined(CONFIG_ARCH_UNIPHIER_PRO5)
 	{
 		.soc_id = UNIPHIER_PRO5_ID,
-		.nand_2cs = true,
 		.sbc_init = uniphier_sbc_init_savepin,
 		.clk_init = uniphier_pro5_clk_init,
 	},
@@ -124,7 +119,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
 #if defined(CONFIG_ARCH_UNIPHIER_PXS2)
 	{
 		.soc_id = UNIPHIER_PXS2_ID,
-		.nand_2cs = true,
 		.sbc_init = uniphier_pxs2_sbc_init,
 		.clk_init = uniphier_pxs2_clk_init,
 	},
@@ -132,7 +126,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
 #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
 	{
 		.soc_id = UNIPHIER_LD6B_ID,
-		.nand_2cs = true,
 		.sbc_init = uniphier_pxs2_sbc_init,
 		.clk_init = uniphier_pxs2_clk_init,
 	},
@@ -140,7 +133,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
 #if defined(CONFIG_ARCH_UNIPHIER_LD11)
 	{
 		.soc_id = UNIPHIER_LD11_ID,
-		.nand_2cs = false,
 		.sbc_init = uniphier_ld11_sbc_init,
 		.pll_init = uniphier_ld11_pll_init,
 		.clk_init = uniphier_ld11_clk_init,
@@ -150,7 +142,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
 #if defined(CONFIG_ARCH_UNIPHIER_LD20)
 	{
 		.soc_id = UNIPHIER_LD20_ID,
-		.nand_2cs = false,
 		.sbc_init = uniphier_ld11_sbc_init,
 		.pll_init = uniphier_ld20_pll_init,
 		.clk_init = uniphier_ld20_clk_init,
@@ -160,7 +151,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
 #if defined(CONFIG_ARCH_UNIPHIER_PXS3)
 	{
 		.soc_id = UNIPHIER_PXS3_ID,
-		.nand_2cs = false,
 		.sbc_init = uniphier_pxs2_sbc_init,
 		.pll_init = uniphier_pxs3_pll_init,
 		.clk_init = uniphier_pxs3_clk_init,
@@ -172,7 +162,6 @@ UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_initdata, uniphier_initdata)
 int board_init(void)
 {
 	const struct uniphier_initdata *initdata;
-	int ret;

 	led_puts("U0");

@@ -188,33 +177,24 @@ int board_init(void)

 	led_puts("U0");

-	if (IS_ENABLED(CONFIG_NAND_DENALI)) {
-		ret = uniphier_pin_init(initdata->nand_2cs ?
-					"nand2cs_grp" : "nand_grp");
-		if (ret)
-			pr_err("failed to init NAND pins\n");
-	}
-
-	led_puts("U1");
-
 	if (initdata->pll_init)
 		initdata->pll_init();

-	led_puts("U2");
+	led_puts("U1");

 	if (initdata->clk_init)
 		initdata->clk_init();

-	led_puts("U3");
+	led_puts("U2");

 	if (initdata->misc_init)
 		initdata->misc_init();

-	led_puts("U4");
+	led_puts("U3");

 	uniphier_setup_xirq();

-	led_puts("U5");
+	led_puts("U4");

 	support_card_late_init();

--- a/arch/arm/mach-uniphier/clk/pll-base-ld20.c
+++ b/arch/arm/mach-uniphier/clk/pll-base-ld20.c
@@ -88,7 +88,7 @@ int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi)
 	if (!base)
 		return -ENOMEM;

-	tmp = readl(base + 8);	/* SSCPLLCTRL */
+	tmp = readl(base + 8);	/* SSCPLLCTRL3 */
 	tmp &= ~SC_PLLCTRL3_REGI_MASK;
 	tmp |= regi << SC_PLLCTRL3_REGI_SHIFT;
 	writel(tmp, base + 8);
@@ -133,9 +133,9 @@ int uniphier_ld20_dspll_init(unsigned long reg_base)
 	if (!base)
 		return -ENOMEM;

-	tmp = readl(base + 8);		/* DSPLLCTRL2 */
+	tmp = readl(base + 4);		/* DSPLLCTRL2 */
 	tmp |= SC_DSPLLCTRL2_K_LD;
-	writel(tmp, base + 8);
+	writel(tmp, base + 4);

 	iounmap(base);

--- a/arch/arm/mach-uniphier/clk/pll-ld11.c
+++ b/arch/arm/mach-uniphier/clk/pll-ld11.c
@@ -4,13 +4,24 @@
 * SPDX-License-Identifier:	GPL-2.0+
 */

-#include <common.h>
+#include <linux/delay.h>
 #include <linux/io.h>

 #include "../init.h"
 #include "../sc64-regs.h"
 #include "pll.h"

+/* PLL type: SSC */
+#define SC_CPLLCTRL	(SC_BASE_ADDR | 0x1400)	/* CPU/ARM */
+#define SC_SPLLCTRL	(SC_BASE_ADDR | 0x1410)	/* misc */
+#define SC_MPLLCTRL	(SC_BASE_ADDR | 0x1430)	/* DSP */
+#define SC_VSPLLCTRL	(SC_BASE_ADDR | 0x1440)	/* Video codec, VPE etc. */
+#define SC_DPLLCTRL	(SC_BASE_ADDR | 0x1460)	/* DDR memory */
+
+/* PLL type: VPLL27 */
+#define SC_VPLL27FCTRL	(SC_BASE_ADDR | 0x1500)
+#define SC_VPLL27ACTRL	(SC_BASE_ADDR | 0x1520)
+
 void uniphier_ld11_pll_init(void)
 {
 	uniphier_ld20_sscpll_init(SC_CPLLCTRL, 1960, 1, 2);	/* 2000MHz -> 1960MHz */
--- a/arch/arm/mach-uniphier/clk/pll-ld20.c
+++ b/arch/arm/mach-uniphier/clk/pll-ld20.c
@@ -5,12 +5,31 @@
 * SPDX-License-Identifier:	GPL-2.0+
 */

-#include <common.h>
+#include <linux/delay.h>

 #include "../init.h"
 #include "../sc64-regs.h"
 #include "pll.h"

+/* PLL type: SSC */
+#define SC_CPLLCTRL	(SC_BASE_ADDR | 0x1400)	/* CPU/ARM */
+#define SC_SPLLCTRL	(SC_BASE_ADDR | 0x1410)	/* misc */
+#define SC_SPLL2CTRL	(SC_BASE_ADDR | 0x1420)	/* DSP */
+#define SC_MPLLCTRL	(SC_BASE_ADDR | 0x1430)	/* Video codec */
+#define SC_VPPLLCTRL	(SC_BASE_ADDR | 0x1440)	/* VPE etc. */
+#define SC_GPPLLCTRL	(SC_BASE_ADDR | 0x1450)	/* GPU/Mali */
+#define SC_DPLL0CTRL	(SC_BASE_ADDR | 0x1460)	/* DDR memory 0 */
+#define SC_DPLL1CTRL	(SC_BASE_ADDR | 0x1470)	/* DDR memory 1 */
+#define SC_DPLL2CTRL	(SC_BASE_ADDR | 0x1480)	/* DDR memory 2 */
+
+/* PLL type: VPLL27 */
+#define SC_VPLL27FCTRL	(SC_BASE_ADDR | 0x1500)
+#define SC_VPLL27ACTRL	(SC_BASE_ADDR | 0x1520)
+
+/* PLL type: DSPLL */
+#define SC_VPLL8KCTRL	(SC_BASE_ADDR | 0x1540)
+#define SC_A2PLLCTRL	(SC_BASE_ADDR | 0x15C0)
+
 void uniphier_ld20_pll_init(void)
 {
 	uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
--- a/arch/arm/mach-uniphier/clk/pll-pxs3.c
+++ b/arch/arm/mach-uniphier/clk/pll-pxs3.c
@@ -1,9 +1,64 @@
 /*
+ * Copyright (C) 2017 Socionext Inc.
+ *
 * SPDX-License-Identifier:	GPL-2.0+
 */

+#include <linux/delay.h>
+
 #include "../init.h"
+#include "../sc64-regs.h"
+#include "pll.h"
+
+/* PLL type: SSC */
+#define SC_CPLLCTRL	(SC_BASE_ADDR | 0x1400)	/* CPU/ARM */
+#define SC_SPLLCTRL	(SC_BASE_ADDR | 0x1410)	/* misc */
+#define SC_SPLL2CTRL	(SC_BASE_ADDR | 0x1420)	/* DSP */
+#define SC_VPPLLCTRL	(SC_BASE_ADDR | 0x1430)	/* VPE */
+#define SC_VGPLLCTRL	(SC_BASE_ADDR | 0x1440)
+#define SC_DECPLLCTRL	(SC_BASE_ADDR | 0x1450)
+#define SC_ENCPLLCTRL	(SC_BASE_ADDR | 0x1460)
+#define SC_PXFPLLCTRL	(SC_BASE_ADDR | 0x1470)
+#define SC_DPLL0CTRL	(SC_BASE_ADDR | 0x1480)	/* DDR memory 0 */
+#define SC_DPLL1CTRL	(SC_BASE_ADDR | 0x1490)	/* DDR memory 1 */
+#define SC_DPLL2CTRL	(SC_BASE_ADDR | 0x14a0)	/* DDR memory 2 */
+#define SC_VSPLLCTRL	(SC_BASE_ADDR | 0x14c0)
+
+/* PLL type: VPLL27 */
+#define SC_VPLL27FCTRL	(SC_BASE_ADDR | 0x1500)
+#define SC_VPLL27ACTRL	(SC_BASE_ADDR | 0x1520)
+
+/* PLL type: DSPLL */
+#define SC_VPLL8KCTRL	(SC_BASE_ADDR | 0x1540)

 void uniphier_pxs3_pll_init(void)
 {
+	uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
+	/* do nothing for SPLL */
+	uniphier_ld20_sscpll_init(SC_SPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
+	uniphier_ld20_sscpll_init(SC_VPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+	uniphier_ld20_sscpll_init(SC_VGPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+	uniphier_ld20_sscpll_init(SC_DECPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+	uniphier_ld20_sscpll_init(SC_ENCPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
+	uniphier_ld20_sscpll_init(SC_PXFPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+	uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+
+	mdelay(1);
+
+	uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_SPLL2CTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_VPPLLCTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_VGPLLCTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_DECPLLCTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_ENCPLLCTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_PXFPLLCTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_VSPLLCTRL);
+
+	uniphier_ld20_vpll27_init(SC_VPLL27FCTRL);
+	uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);
+
+	uniphier_ld20_dspll_init(SC_VPLL8KCTRL);
 }
--- a/arch/arm/mach-uniphier/sbc/sbc-pxs2.c
+++ b/arch/arm/mach-uniphier/sbc/sbc-pxs2.c
@@ -16,4 +16,6 @@ void uniphier_pxs2_sbc_init(void)
 	/* necessary for ROM boot ?? */
 	/* system bus output enable */
 	writel(0x17, PC0CTRL);
+
+	uniphier_pin_init("system_bus_grp");	/* PXs3 */
 }
--- a/arch/arm/mach-uniphier/sc64-regs.h
+++ b/arch/arm/mach-uniphier/sc64-regs.h
@@ -12,27 +12,6 @@

 #define SC_BASE_ADDR		0x61840000

-/* PLL type: SSC */
-#define SC_CPLLCTRL	(SC_BASE_ADDR | 0x1400)	/* LD11/20: CPU/ARM */
-#define SC_SPLLCTRL	(SC_BASE_ADDR | 0x1410)	/* LD11/20: misc */
-#define SC_SPLL2CTRL	(SC_BASE_ADDR | 0x1420)	/* LD20: IPP */
-#define SC_MPLLCTRL	(SC_BASE_ADDR | 0x1430)	/* LD11/20: Video codec */
-#define SC_VSPLLCTRL	(SC_BASE_ADDR | 0x1440)	/* LD11 */
-#define SC_VPPLLCTRL	(SC_BASE_ADDR | 0x1440)	/* LD20: VPE etc. */
-#define SC_GPPLLCTRL	(SC_BASE_ADDR | 0x1450)	/* LD20: GPU/Mali */
-#define SC_DPLLCTRL	(SC_BASE_ADDR | 0x1460)	/* LD11: DDR memory */
-#define SC_DPLL0CTRL	(SC_BASE_ADDR | 0x1460)	/* LD20: DDR memory 0 */
-#define SC_DPLL1CTRL	(SC_BASE_ADDR | 0x1470)	/* LD20: DDR memory 1 */
-#define SC_DPLL2CTRL	(SC_BASE_ADDR | 0x1480)	/* LD20: DDR memory 2 */
-
-/* PLL type: VPLL27 */
-#define SC_VPLL27FCTRL	(SC_BASE_ADDR | 0x1500)
-#define SC_VPLL27ACTRL	(SC_BASE_ADDR | 0x1520)
-
-/* PLL type: DSPLL */
-#define SC_VPLL8KCTRL	(SC_BASE_ADDR | 0x1540)
-#define SC_A2PLLCTRL	(SC_BASE_ADDR | 0x15C0)
-
 #define SC_RSTCTRL		(SC_BASE_ADDR | 0x2000)
 #define SC_RSTCTRL3		(SC_BASE_ADDR | 0x2008)
 #define SC_RSTCTRL4		(SC_BASE_ADDR | 0x200c)
--- a/arch/x86/cpu/baytrail/acpi.c
+++ b/arch/x86/cpu/baytrail/acpi.c
@@ -73,7 +73,7 @@ void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
 	fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
 	fadt->reset_reg.addrl = IO_PORT_RESET;
 	fadt->reset_reg.addrh = 0;
-	fadt->reset_value = SYS_RST | RST_CPU;
+	fadt->reset_value = SYS_RST | RST_CPU | FULL_RST;

 	fadt->x_firmware_ctl_l = (u32)facs;
 	fadt->x_firmware_ctl_h = 0;
--- a/board/bachmann/ot1200/ot1200.c
+++ b/board/bachmann/ot1200/ot1200.c
@@ -169,17 +169,6 @@ static void ccgr_init(void)
 	writel(0x000003FF, &ccm->CCGR6);
 }

-static void gpr_init(void)
-{
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
-	/* enable AXI cache for VDOA/VPU/IPU */
-	writel(0xF00000CF, &iomux->gpr[4]);
-	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-	writel(0x007F007F, &iomux->gpr[6]);
-	writel(0x007F007F, &iomux->gpr[7]);
-}
-
 int board_early_init_f(void)
 {
 	ccgr_init();
--- a/board/barco/platinum/platinum.h
+++ b/board/barco/platinum/platinum.h
@@ -75,15 +75,4 @@ static inline void ccgr_init(void)
 	writel(0x000003FF, &ccm->CCGR6);
 }

-static inline void gpr_init(void)
-{
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
-	/* enable AXI cache for VDOA/VPU/IPU */
-	writel(0xF00000CF, &iomux->gpr[4]);
-	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-	writel(0x007F007F, &iomux->gpr[6]);
-	writel(0x007F007F, &iomux->gpr[7]);
-}
-
 #endif /* _PLATINUM_H_ */
--- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c
+++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
@@ -955,17 +955,6 @@ static void ccgr_init(void)
 	writel(0x000003FF, &ccm->CCGR6);
 }

-static void gpr_init(void)
-{
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
-	/* enable AXI cache for VDOA/VPU/IPU */
-	writel(0xF00000CF, &iomux->gpr[4]);
-	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-	writel(0x007F007F, &iomux->gpr[6]);
-	writel(0x007F007F, &iomux->gpr[7]);
-}
-
 /* Define a minimal structure so that the part number can be read via SPL */
 struct mfgdata {
 	unsigned char tsize;
--- a/board/el/el6x/el6x.c
+++ b/board/el/el6x/el6x.c
@@ -570,17 +570,6 @@ static void ccgr_init(void)
 	writel(0x000003FF, &ccm->CCGR6);
 }

-static void gpr_init(void)
-{
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
-	/* enable AXI cache for VDOA/VPU/IPU */
-	writel(0xF00000CF, &iomux->gpr[4]);
-	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-	writel(0x007F007F, &iomux->gpr[6]);
-	writel(0x007F007F, &iomux->gpr[7]);
-}
-
 /*
 * This section requires the differentiation between iMX6 Sabre boards, but
 * for now, it will configure only for the mx6q variant.
--- a/board/engicam/common/spl.c
+++ b/board/engicam/common/spl.c
@@ -39,6 +39,17 @@ static iomux_v3_cfg_t const uart_pads[] = {
 #endif
 };

+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+	return 0;
+}
+#endif
+
 #ifdef CONFIG_MX6QDL
 /*
 * Driving strength:
@@ -332,17 +343,6 @@ static void ccgr_init(void)
 #endif
 }

-static void gpr_init(void)
-{
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
-	/* enable AXI cache for VDOA/VPU/IPU */
-	writel(0xF00000CF, &iomux->gpr[4]);
-	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-	writel(0x007F007F, &iomux->gpr[6]);
-	writel(0x007F007F, &iomux->gpr[7]);
-}
-
 static void spl_dram_init(void)
 {
 #ifdef CONFIG_MX6QDL
--- a/board/freescale/mx6sabreauto/mx6sabreauto.c
+++ b/board/freescale/mx6sabreauto/mx6sabreauto.c
@@ -798,23 +798,6 @@ static void ccgr_init(void)
 	writel(0x000003FF, &ccm->CCGR6);
 }

-static void gpr_init(void)
-{
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
-	/* enable AXI cache for VDOA/VPU/IPU */
-	writel(0xF00000CF, &iomux->gpr[4]);
-	if (is_mx6dqp()) {
-		/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
-		writel(0x77177717, &iomux->gpr[6]);
-		writel(0x77177717, &iomux->gpr[7]);
-	} else {
-		/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-		writel(0x007F007F, &iomux->gpr[6]);
-		writel(0x007F007F, &iomux->gpr[7]);
-	}
-}
-
 static int mx6q_dcd_table[] = {
 	0x020e0798, 0x000C0000,
 	0x020e0758, 0x00000000,
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -747,23 +747,6 @@ static void ccgr_init(void)
 	writel(0x000003FF, &ccm->CCGR6);
 }

-static void gpr_init(void)
-{
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
-	/* enable AXI cache for VDOA/VPU/IPU */
-	writel(0xF00000CF, &iomux->gpr[4]);
-	if (is_mx6dqp()) {
-		/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
-		writel(0x77177717, &iomux->gpr[6]);
-		writel(0x77177717, &iomux->gpr[7]);
-	} else {
-		/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-		writel(0x007F007F, &iomux->gpr[6]);
-		writel(0x007F007F, &iomux->gpr[7]);
-	}
-}
-
 static int mx6q_dcd_table[] = {
 	0x020e0798, 0x000C0000,
 	0x020e0758, 0x00000000,
--- a/board/gateworks/gw_ventana/gw_ventana_spl.c
+++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
@@ -583,17 +583,6 @@ static void ccgr_init(void)
 	writel(0x000003FF, &ccm->CCGR6);
 }

-static void gpr_init(void)
-{
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
-	/* enable AXI cache for VDOA/VPU/IPU */
-	writel(0xF00000CF, &iomux->gpr[4]);
-	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-	writel(0x007F007F, &iomux->gpr[6]);
-	writel(0x007F007F, &iomux->gpr[7]);
-}
-
 /*
 * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
 * - we have a stack and a place to store GD, both in SRAM
--- a/board/kosagi/novena/novena_spl.c
+++ b/board/kosagi/novena/novena_spl.c
@@ -550,17 +550,6 @@ static void ccgr_init(void)
 	writel(0x000003FF, &ccm->CCGR6);
 }

-static void gpr_init(void)
-{
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
-	/* enable AXI cache for VDOA/VPU/IPU */
-	writel(0xF00000CF, &iomux->gpr[4]);
-	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-	writel(0x007F007F, &iomux->gpr[6]);
-	writel(0x007F007F, &iomux->gpr[7]);
-}
-
 /*
 * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
 * - we have a stack and a place to store GD, both in SRAM
--- a/board/liebherr/mccmon6/spl.c
+++ b/board/liebherr/mccmon6/spl.c
@@ -260,17 +260,6 @@ static void ccgr_init(void)
 	writel(0x000003FF, &ccm->CCGR6);
 }

-static void gpr_init(void)
-{
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
-	/* enable AXI cache for VDOA/VPU/IPU */
-	writel(0xF00000CF, &iomux->gpr[4]);
-	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-	writel(0x007F007F, &iomux->gpr[6]);
-	writel(0x007F007F, &iomux->gpr[7]);
-}
-
 static void spl_dram_init(void)
 {
 	if (is_cpu_type(MXC_CPU_MX6SOLO)) {
--- a/board/phytec/pcm058/pcm058.c
+++ b/board/phytec/pcm058/pcm058.c
@@ -487,18 +487,6 @@ static void ccgr_init(void)
 	writel(0x000003FF, &ccm->CCGR6);
 }

-static void gpr_init(void)
-{
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
-	/* enable AXI cache for VDOA/VPU/IPU */
-	writel(0xF00000CF, &iomux->gpr[4]);
-	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-	writel(0x007F007F, &iomux->gpr[6]);
-	writel(0x007F007F, &iomux->gpr[7]);
-}
-
-
 static void spl_dram_init(void)
 {
 	struct mx6_ddr_sysinfo sysinfo = {
--- a/board/phytec/pfla02/Kconfig
+++ b/board/phytec/pfla02/Kconfig
@@ -9,4 +9,10 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "pfla02"

+config SPL_DRAM_1_BANK
+	bool "DRAM on just one bank"
+	help
+	  activate, if the module has just one bank
+	  of RAM
+
 endif
--- a/board/phytec/pfla02/pfla02.c
+++ b/board/phytec/pfla02/pfla02.c
@@ -485,9 +485,9 @@ static const struct mx6_mmdc_calibration mx6_mmcd_calib = {

 /* Index in RAM Chip array */
 enum {
-	RAM_1GB,
-	RAM_2GB,
-	RAM_4GB
+	RAM_MT64K,
+	RAM_MT128K,
+	RAM_MT256K
 };

 static struct mx6_ddr3_cfg mt41k_xx[] = {
@@ -550,42 +550,11 @@ static void ccgr_init(void)
 	writel(0x000003FF, &ccm->CCGR6);
 }

-static void gpr_init(void)
+static void spl_dram_init(struct mx6_ddr_sysinfo *sysinfo,
+				struct mx6_ddr3_cfg *mem_ddr)
 {
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
-	/* enable AXI cache for VDOA/VPU/IPU */
-	writel(0xF00000CF, &iomux->gpr[4]);
-	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-	writel(0x007F007F, &iomux->gpr[6]);
-	writel(0x007F007F, &iomux->gpr[7]);
-}
-
-static void spl_dram_init(struct mx6_ddr3_cfg *mem_ddr)
-{
-	struct mx6_ddr_sysinfo sysinfo = {
-		/* width of data bus:0=16,1=32,2=64 */
-		.dsize = 2,
-		/* config for full 4GB range so that get_mem_size() works */
-		.cs_density = 32, /* 32Gb per CS */
-		/* single chip select */
-		.ncs = 2,
-		.cs1_mirror = 0,
-		.rtt_wr = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Wr = RZQ/4 */
-		.rtt_nom = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Nom = RZQ/4 */
-		.walat = 1,	/* Write additional latency */
-		.ralat = 5,	/* Read additional latency */
-		.mif3_mode = 3,	/* Command prediction working mode */
-		.bi_on = 1,	/* Bank interleaving enabled */
-		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
-		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
-		.ddr_type = DDR_TYPE_DDR3,
-		.refsel = 1,	/* Refresh cycles at 32KHz */
-		.refr = 7,	/* 8 refresh commands per refresh cycle */
-	};
-
 	mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
-	mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, mem_ddr);
+	mx6_dram_cfg(sysinfo, &mx6_mmcd_calib, mem_ddr);
 }

 int board_mmc_init(bd_t *bis)
@@ -627,10 +596,12 @@ void board_boot_order(u32 *spl_boot_list)
 * Function checks for mirrors in the first CS
 */
 #define RAM_TEST_PATTERN	0xaa5555aa
-static unsigned int pfla02_detect_ramsize(void)
+#define MIN_BANK_SIZE		(512 * 1024 * 1024)
+
+static unsigned int pfla02_detect_chiptype(void)
 {
 	u32 *p, *p1;
-	unsigned int offset = 512 * 1024 * 1024;
+	unsigned int offset = MIN_BANK_SIZE;
 	int i;

 	for (i = 0; i < 2; i++) {
@@ -649,12 +620,38 @@ static unsigned int pfla02_detect_ramsize(void)
 		if (*p == *p1)
 			return i;
 	}
-	return RAM_4GB;
+	return RAM_MT256K;
 }

 void board_init_f(ulong dummy)
 {
 	unsigned int ramchip;
+
+	struct mx6_ddr_sysinfo sysinfo = {
+		/* width of data bus:0=16,1=32,2=64 */
+		.dsize = 2,
+		/* config for full 4GB range so that get_mem_size() works */
+		.cs_density = 32, /* 512 MB */
+		/* single chip select */
+#if IS_ENABLED(CONFIG_SPL_DRAM_1_BANK)
+		.ncs = 1,
+#else
+		.ncs = 2,
+#endif
+		.cs1_mirror = 1,
+		.rtt_wr = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Wr = RZQ/4 */
+		.rtt_nom = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Nom = RZQ/4 */
+		.walat = 1,	/* Write additional latency */
+		.ralat = 5,	/* Read additional latency */
+		.mif3_mode = 3,	/* Command prediction working mode */
+		.bi_on = 1,	/* Bank interleaving enabled */
+		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
+		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+		.ddr_type = DDR_TYPE_DDR3,
+		.refsel = 1,	/* Refresh cycles at 32KHz */
+		.refr = 7,	/* 8 refresh commands per refresh cycle */
+	};
+
 #ifdef CONFIG_CMD_NAND
 	/* Enable NAND */
 	setup_gpmi_nand();
@@ -682,10 +679,23 @@ void board_init_f(ulong dummy)
 	setup_gpios();

 	/* DDR initialization */
-	spl_dram_init(&mt41k_xx[RAM_4GB]);
-	ramchip = pfla02_detect_ramsize();
-	if (ramchip != RAM_4GB)
-		spl_dram_init(&mt41k_xx[ramchip]);
+	spl_dram_init(&sysinfo, &mt41k_xx[RAM_MT256K]);
+	ramchip = pfla02_detect_chiptype();
+	debug("Detected chip %d\n", ramchip);
+#if !IS_ENABLED(CONFIG_SPL_DRAM_1_BANK)
+	switch (ramchip) {
+		case RAM_MT64K:
+			sysinfo.cs_density = 6;
+			break;
+		case RAM_MT128K:
+			sysinfo.cs_density = 10;
+			break;
+		case RAM_MT256K:
+			sysinfo.cs_density = 18;
+			break;
+	}
+#endif
+	spl_dram_init(&sysinfo, &mt41k_xx[ramchip]);

 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -581,17 +581,6 @@ static void ccgr_init(void)
 	writel(0x000003FF, &ccm->CCGR6);
 }

-static void gpr_init(void)
-{
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
-	/* enable AXI cache for VDOA/VPU/IPU */
-	writel(0xF00000CF, &iomux->gpr[4]);
-	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-	writel(0x007F007F, &iomux->gpr[6]);
-	writel(0x007F007F, &iomux->gpr[7]);
-}
-
 static void spl_dram_init(int width)
 {
 	struct mx6_ddr_sysinfo sysinfo = {
--- a/board/sunxi/Makefile
+++ b/board/sunxi/Makefile
@@ -9,7 +9,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 obj-y	+= board.o
-obj-$(CONFIG_SUNXI_GMAC)	+= gmac.o
+obj-$(CONFIG_SUN7I_GMAC)	+= gmac.o
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_SUNXI_AHCI)	+= ahci.o
 endif
--- a/board/ti/evm/evm.c
+++ b/board/ti/evm/evm.c
@@ -122,6 +122,17 @@ int board_init(void)
 	return 0;
 }

+#if defined(CONFIG_SPL_OS_BOOT)
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+	return 0;
+}
+#endif /* CONFIG_SPL_OS_BOOT */
+
 #if defined(CONFIG_SPL_BUILD)
 /*
 * Routine: get_board_mem_timings
@@ -323,7 +334,14 @@ void board_mmc_power_init(void)
 }
 #endif /* CONFIG_MMC */

-#if defined(CONFIG_USB_EHCI_HCD)
+#if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD)
+/* Call usb_stop() before starting the kernel */
+void show_boot_progress(int val)
+{
+	if (val == BOOTSTAGE_ID_RUN_OS)
+		usb_stop();
+}
+
 static struct omap_usbhs_board_data usbhs_bdata = {
 	.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
 	.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -29,6 +29,7 @@
 #include <dm/platform_data/serial_mxc.h>
 #include <dm/platdata.h>
 #include <fsl_esdhc.h>
+#include <g_dnl.h>
 #include <i2c.h>
 #include <imx_thermal.h>
 #include <linux/errno.h>
@@ -1159,17 +1160,6 @@ static void ccgr_init(void)
 	writel(0x000000FB, &ccm->ccosr);
 }

-static void gpr_init(void)
-{
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
-	/* enable AXI cache for VDOA/VPU/IPU */
-	writel(0xF00000CF, &iomux->gpr[4]);
-	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-	writel(0x007F007F, &iomux->gpr[6]);
-	writel(0x007F007F, &iomux->gpr[7]);
-}
-
 static void ddr_init(int *table, int size)
 {
 	int i;
@@ -1234,6 +1224,18 @@ void reset_cpu(ulong addr)
 {
 }

+#ifdef CONFIG_SPL_USB_GADGET_SUPPORT
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+{
+	unsigned short usb_pid;
+
+	usb_pid = TORADEX_USB_PRODUCT_NUM_OFFSET + 0xfff;
+	put_unaligned(usb_pid, &dev->idProduct);
+
+	return 0;
+}
+#endif
+
 #endif

 static struct mxc_serial_platdata mxc_serial_plat = {
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -28,6 +28,7 @@
 #include <dm/platform_data/serial_mxc.h>
 #include <dm/platdata.h>
 #include <fsl_esdhc.h>
+#include <g_dnl.h>
 #include <i2c.h>
 #include <imx_thermal.h>
 #include <linux/errno.h>
@@ -1036,17 +1037,6 @@ static void ccgr_init(void)
 	writel(0x000000FB, &ccm->ccosr);
 }

-static void gpr_init(void)
-{
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
-	/* enable AXI cache for VDOA/VPU/IPU */
-	writel(0xF00000CF, &iomux->gpr[4]);
-	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-	writel(0x007F007F, &iomux->gpr[6]);
-	writel(0x007F007F, &iomux->gpr[7]);
-}
-
 static void ddr_init(int *table, int size)
 {
 	int i;
@@ -1118,6 +1108,18 @@ void reset_cpu(ulong addr)
 {
 }

+#ifdef CONFIG_SPL_USB_GADGET_SUPPORT
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+{
+	unsigned short usb_pid;
+
+	usb_pid = TORADEX_USB_PRODUCT_NUM_OFFSET + 0xfff;
+	put_unaligned(usb_pid, &dev->idProduct);
+
+	return 0;
+}
+#endif
+
 #endif

 static struct mxc_serial_platdata mxc_serial_plat = {
--- a/board/udoo/udoo_spl.c
+++ b/board/udoo/udoo_spl.c
@@ -211,17 +211,6 @@ static void ccgr_init(void)
 	writel(0x000003FF, &ccm->CCGR6);
 }

-static void gpr_init(void)
-{
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
-	/* enable AXI cache for VDOA/VPU/IPU */
-	writel(0xF00000FF, &iomux->gpr[4]);
-	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-	writel(0x007F007F, &iomux->gpr[6]);
-	writel(0x007F007F, &iomux->gpr[7]);
-}
-
 static void spl_dram_init(void)
 {
 	if (is_cpu_type(MXC_CPU_MX6DL)) {
--- a/board/wandboard/spl.c
+++ b/board/wandboard/spl.c
@@ -266,17 +266,6 @@ static void ccgr_init(void)
 	writel(0x000003FF, &ccm->CCGR6);
 }

-static void gpr_init(void)
-{
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
-	/* enable AXI cache for VDOA/VPU/IPU */
-	writel(0xF00000CF, &iomux->gpr[4]);
-	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-	writel(0x007F007F, &iomux->gpr[6]);
-	writel(0x007F007F, &iomux->gpr[7]);
-}
-
 static void spl_dram_init(void)
 {
 	if (is_cpu_type(MXC_CPU_MX6SOLO)) {
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -895,6 +895,13 @@ config CMD_USB
 	help
 	  USB support.

+config CMD_USB_SDP
+	bool "sdp"
+	select USB_FUNCTION_SDP
+	help
+	  Enables the command "sdp" which is used to have U-Boot emulating the
+	  Serial Download Protocol (SDP) via USB.
+
 config CMD_USB_MASS_STORAGE
 	bool "UMS usb mass storage"
 	help
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -132,6 +132,7 @@ obj-$(CONFIG_CMD_FASTBOOT) += fastboot.o
 obj-$(CONFIG_CMD_FS_UUID) += fs_uuid.o

 obj-$(CONFIG_CMD_USB_MASS_STORAGE) += usb_mass_storage.o
+obj-$(CONFIG_CMD_USB_SDP) += usb_gadget_sdp.o
 obj-$(CONFIG_CMD_THOR_DOWNLOAD) += thordown.o
 obj-$(CONFIG_CMD_XIMG) += ximg.o
 obj-$(CONFIG_CMD_YAFFS2) += yaffs2.o
--- a/cmd/fastboot/Kconfig
+++ b/cmd/fastboot/Kconfig
@@ -2,6 +2,7 @@ comment "FASTBOOT"

 menuconfig FASTBOOT
 	bool "Fastboot support"
+	depends on USB_GADGET

 if FASTBOOT

@@ -20,16 +21,20 @@ config CMD_FASTBOOT

 	  See doc/README.android-fastboot for more information.

-config ANDROID_BOOT_IMAGE
-	bool "Enable support for Android Boot Images"
-	help
-	  This enables support for booting images which use the Android
-	  image format header.
-
 if USB_FUNCTION_FASTBOOT

 config FASTBOOT_BUF_ADDR
 	hex "Define FASTBOOT buffer address"
+	default 0x82000000 if MX6SX || MX6SL || MX6UL || MX6SLL
+	default 0x81000000 if ARCH_OMAP2PLUS
+	default 0x42000000 if ARCH_SUNXI && !MACH_SUN9I
+	default 0x22000000 if ARCH_SUNXI && MACH_SUN9I
+	default 0x60800800 if ROCKCHIP_RK3036 || ROCKCHIP_RK3188 || \
+				ROCKCHIP_RK322X
+	default 0x800800 if ROCKCHIP_RK3288 || ROCKCHIP_RK3329 || \
+				ROCKCHIP_RK3399
+	default 0x280000 if ROCKCHIP_RK3368
+	default 0x100000 if ARCH_ZYNQMP
 	help
 	  The fastboot protocol requires a large memory buffer for
 	  downloads. Define this to the starting RAM address to use for
@@ -37,6 +42,10 @@ config FASTBOOT_BUF_ADDR

 config FASTBOOT_BUF_SIZE
 	hex "Define FASTBOOT buffer size"
+	default 0x8000000 if ARCH_ROCKCHIP
+	default 0x6000000 if ARCH_ZYNQMP
+	default 0x2000000 if ARCH_SUNXI
+	default 0x7000000
 	help
 	  The fastboot protocol requires a large memory buffer for
 	  downloads. This buffer should be as large as possible for a
@@ -59,7 +68,7 @@ config FASTBOOT_FLASH

 config FASTBOOT_FLASH_MMC_DEV
 	int "Define FASTBOOT MMC FLASH default device"
-	depends on FASTBOOT_FLASH
+	depends on FASTBOOT_FLASH && MMC
 	help
 	  The fastboot "flash" command requires additional information
 	  regarding the non-volatile storage device. Define this to
--- a/cmd/usb_gadget_sdp.c
+++ b/cmd/usb_gadget_sdp.c
@@ -0,0 +1,50 @@
+/*
+ * cmd_sdp.c -- sdp command
+ *
+ * Copyright (C) 2016 Toradex
+ * Author: Stefan Agner <stefan.agner@toradex.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <g_dnl.h>
+#include <sdp.h>
+#include <usb.h>
+
+static int do_sdp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int ret = CMD_RET_FAILURE;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	char *usb_controller = argv[1];
+	int controller_index = simple_strtoul(usb_controller, NULL, 0);
+	board_usb_init(controller_index, USB_INIT_DEVICE);
+
+	g_dnl_clear_detach();
+	g_dnl_register("usb_dnl_sdp");
+
+	ret = sdp_init(controller_index);
+	if (ret) {
+		error("SDP init failed: %d", ret);
+		goto exit;
+	}
+
+	/* This command typically does not return but jumps to an image */
+	sdp_handle(controller_index);
+	error("SDP ended");
+
+exit:
+	g_dnl_unregister();
+	board_usb_cleanup(controller_index, USB_INIT_DEVICE);
+
+	return ret;
+}
+
+U_BOOT_CMD(sdp, 2, 1, do_sdp,
+	"Serial Downloader Protocol",
+	"<USB_controller>\n"
+	"  - serial downloader protocol via <USB_controller>\n"
+);
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -668,6 +668,12 @@ config SPL_DFU_RAM

 endchoice

+config SPL_USB_SDP_SUPPORT
+	bool "Support SDP (Serial Download Protocol)"
+	help
+	  Enable Serial Download Protocol (SDP) device support in SPL. This
+	  allows to download images into memory and execute (jump to) them
+	  using the same protocol as implemented by the i.MX family's boot ROM.
 endif

 config SPL_WATCHDOG_SUPPORT
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -30,4 +30,5 @@ obj-$(CONFIG_$(SPL_TPL_)SATA_SUPPORT) += spl_sata.o
 obj-$(CONFIG_$(SPL_TPL_)DFU_SUPPORT) += spl_dfu.o
 obj-$(CONFIG_$(SPL_TPL_)SPI_LOAD) += spl_spi.o
 obj-$(CONFIG_$(SPL_TPL_)RAM_SUPPORT) += spl_ram.o
+obj-$(CONFIG_$(SPL_TPL_)USB_SDP_SUPPORT) += spl_sdp.o
 endif
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -379,7 +379,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
 		if (spl_init())
 			hang();
 	}
-#ifndef CONFIG_PPC
+#if !defined(CONFIG_PPC) && !defined(CONFIG_ARCH_MX6)
 	/*
 	 * timer_init() does not exist on PPC systems. The timer is initialized
 	 * and enabled (decrementer) in interrupt_init() here.
--- a/common/spl/spl_sdp.c
+++ b/common/spl/spl_sdp.c
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2016 Toradex
+ * Author: Stefan Agner <stefan.agner@toradex.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <usb.h>
+#include <g_dnl.h>
+#include <sdp.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int spl_sdp_load_image(struct spl_image_info *spl_image,
+			      struct spl_boot_device *bootdev)
+{
+	int ret;
+	const int controller_index = 0;
+
+	g_dnl_clear_detach();
+	g_dnl_register("usb_dnl_sdp");
+
+	ret = sdp_init(controller_index);
+	if (ret) {
+		error("SDP init failed: %d", ret);
+		return -ENODEV;
+	}
+
+	/* This command typically does not return but jumps to an image */
+	sdp_handle(controller_index);
+	error("SDP ended");
+
+	return -EINVAL;
+}
+SPL_LOAD_IMAGE_METHOD("USB SDP", 0, BOOT_DEVICE_BOARD, spl_sdp_load_image);
--- a/configs/A10-OLinuXino-Lime_defconfig
+++ b/configs/A10-OLinuXino-Lime_defconfig
@@ -23,3 +23,4 @@ CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
--- a/configs/A10s-OLinuXino-M_defconfig
+++ b/configs/A10s-OLinuXino-M_defconfig
@@ -19,3 +19,4 @@ CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SUN4I_EMAC=y
 CONFIG_AXP152_POWER=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
--- a/configs/A13-OLinuXinoM_defconfig
+++ b/configs/A13-OLinuXinoM_defconfig
@@ -21,3 +21,4 @@ CONFIG_SPL=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUNXI_NO_PMIC=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
--- a/configs/A13-OLinuXino_defconfig
+++ b/configs/A13-OLinuXino_defconfig
@@ -16,6 +16,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_DFU=y
 # CONFIG_CMD_FLASH is not set
@@ -28,6 +30,7 @@ CONFIG_DFU_RAM=y
 CONFIG_AXP_ALDO3_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Allwinner Technology"
--- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
+++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
@@ -13,6 +13,8 @@ CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_DFU=y
 # CONFIG_CMD_FLASH is not set
@@ -30,6 +32,7 @@ CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Allwinner Technology"
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -12,6 +12,8 @@ CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_DFU=y
 # CONFIG_CMD_FLASH is not set
@@ -29,6 +31,7 @@ CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Allwinner Technology"
--- a/configs/A20-OLinuXino-Lime_defconfig
+++ b/configs/A20-OLinuXino-Lime_defconfig
@@ -22,3 +22,4 @@ CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -25,3 +25,4 @@ CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -27,3 +27,4 @@ CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
--- a/configs/A33-OLinuXino_defconfig
+++ b/configs/A33-OLinuXino_defconfig
@@ -24,3 +24,4 @@ CONFIG_SPL=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_AXP_DCDC1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
--- a/configs/Ainol_AW1_defconfig
+++ b/configs/Ainol_AW1_defconfig
@@ -22,3 +22,4 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_ISO_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_USB_MUSB_HOST=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
--- a/configs/Ampe_A76_defconfig
+++ b/configs/Ampe_A76_defconfig
@@ -23,3 +23,4 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_ISO_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_USB_MUSB_HOST=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
--- a/configs/Auxtek-T003_defconfig
+++ b/configs/Auxtek-T003_defconfig
@@ -17,3 +17,4 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_AXP152_POWER=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
--- a/configs/Auxtek-T004_defconfig
+++ b/configs/Auxtek-T004_defconfig
@@ -15,3 +15,4 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_AXP152_POWER=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
--- a/Show More
+++ b/Show More