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250 Commits

Author SHA1 Message Date
Tom Rini
c92ccdd4dc Prepare v2017.09-rc3
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-28 22:42:44 -04:00
Tom Rini
95431aa54c Merge branch 'master' of git://git.denx.de/u-boot-usb 2017-08-28 22:42:12 -04:00
Masahiro Yamada
6ea247d137 usb: dwc3: fix Kconfig dependency to accept host driver in drivers/usb/dwc3
We see the choice of USB_DWC3_HOST / _GADGET in drivers/usb/dwc3/Kconfig,
but we can not choose USB_DWC3_HOST unless USB_GADGET is defined.
This is strange.

Loosen the "depends on" and also move "select USB_GADGET_DUALSPEED" to
the correct place.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-28 22:32:34 +02:00
Hannes Schmelzer
a223e2bc10 bootvx_fdt: fix missing 'fdt_fixup_ethernet(...)' on vxWorks boot
Before commit 26d6119 (fdt: Move fdt_fixup_ethernet to a common place)
the fdt_fixup_ethernet(...) was called during do_bootvx_fdt(...).

Afterwards the only (common) place for this fixup is during
image_setup_libfdt(...) and this is only called, at least on ARM
platform, from image_setup_linux(...).

All this ends up in the fact, that the fdt_fixup_ethernet(...) is only
called on booting a linux image and not on booting a vxWorks image.

We fix this with adding the fdt_fixup_ethernet(...) call again to
do_bootvx_fdt(...)

Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:19:13 -04:00
Wilson Lee
5daf6e56d3 common: console: Fix duplicated CONFIG in silent env callback
The silent environment callback function does not update the silent
flag during silent env set or unset. That is because of duplicated
CONFIG keyword at preprocessor condition in silent environment
callback function and cause silent env callback unable to work.

This patch is to remove the duplicated CONFIG keywork in silent
environment callback function.

Signed-off-by: Wilson Lee <wilson.lee@ni.com>
Cc: Keng Soon Cheah <keng.soon.cheah@ni.com>
Cc: Chen Yee Chew <chen.yee.chew@ni.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2017-08-28 07:19:12 -04:00
Bin Meng
dd027dde75 sandbox: Enable NVMe driver for build testing
This enables NVMe driver on sandbox for build testing.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:17 -04:00
Bin Meng
0d1414bd97 sandbox: Add a dummy invalidate_dcache_range() function
This adds invalidate_dcache_range() so that some drivers can build
without error on sandbox.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:16 -04:00
Bin Meng
fceadc1459 nvme: Adjust the 'nvme' command to use blk_common_cmd()
Instead of having separate code in the 'nvme' command, adjust it to use
the common function.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:15 -04:00
Bin Meng
18aa5a4134 nvme: Get rid of the global variable nvme_info
At present the NVMe uclass driver uses a global variable nvme_info
to store global information like namespace id, and NVMe controller
driver's priv struct has a blk_dev_start that is used to calculate
the namespace id based on the global information from nvme_info.

This is not a good design in the DM world and can be replaced with
the following changes:

- Encode the namespace id in the NVMe block device name during
  the NVMe uclass post probe
- Extract the namespace id from the device name during the NVMe
  block device probe
- Let BLK uclass calculate the devnum for us by passing -1 to
  blk_create_devicef() as the devnum

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:14 -04:00
Bin Meng
d5b7ee9c6e nvme: Use blk_create_devicef() API
The codes in nvme_uclass_post_probe() can be replaced to call the
blk_create_devicef() API directly.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:14 -04:00
Bin Meng
704e040a51 nvme: Apply cache operations on the DMA buffers
So far cache operations are only applied on the submission queue and
completion queue, but they are missing in other places like identify
and block read/write routines.

In order to correctly operate on the caches, the DMA buffer passed
to identify routine must be allocated properly on the stack with the
existing macro ALLOC_CACHE_ALIGN_BUFFER().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:13 -04:00
Bin Meng
625a483cea nvme: Consolidate block read and write routines
The NVMe block read and write routines are almost the same except
the command opcode. Let's consolidate them to avoid duplication.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:13 -04:00
Bin Meng
722e668db2 nvme: Use macros to access NVMe queues
NVMe driver only uses two queues. The first one is allocated to do
admin stuff, while the second one is for IO stuff. So far the driver
uses magic number (0/1) to access them. Change to use macros.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:12 -04:00
Bin Meng
04d2a38401 nvme: Respect timeout when en/disabling the controller
So far the driver unconditionally delays 10ms when en/disabling the
controller and still return 0 if 10ms times out. In fact, spec defines
a timeout value in the CAP register that is the worst case time that
host software shall wait for the controller to become ready.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:12 -04:00
Bin Meng
b65c692143 nvme: Cache controller's capabilities
Capabilities register is RO and accessed at various places in the
driver. Let's cache it in the controller driver's priv struct.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:11 -04:00
Bin Meng
3e18562961 nvme: Fix endianness assignment to prp2 in nvme_identify()
So far this is not causing any issue due to NVMe and x86 are using
the same endianness, but for correctness, it should be fixed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:11 -04:00
Bin Meng
099c2015b0 nvme: Fix ndev->queues allocation
ndev->queues is a pointer to pointer, but the allocation wrongly
requests sizeof(struct nvme_queue). Fix it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:11 -04:00
Bin Meng
e5dc2d2665 nvme: Fix getting PCI vendor id of the NVMe block device
The codes currently try to read PCI vendor id of the NVMe block
device by dm_pci_read_config16() with its parameter set as its
root complex controller (ndev->pdev) instead of itself. This is
seriously wrong. We can read the vendor id by passing the correct
udevice parameter to the dm_pci_read_config16() API, however there
is a shortcut by reading the cached vendor id from the PCI device's
struct pci_child_platdata.

While we are here fixing this bug, apparently the quirk stuff handle
codes in nvme_get_info_from_identify() never takes effect since its
logic has never been true at all. Remove these codes completely.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:10 -04:00
Bin Meng
abe25db611 nvme: Remove useless defines
These are leftover when the driver was ported from Linux and are not
used by the U-Boot driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:10 -04:00
Tom Rini
5dc4dfd2a9 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-28 07:16:32 -04:00
Tom Rini
34f98a3d2e sh: Fix linking of ms7722se
While it is true that we no longer have 'ppcenv' and similar sections,
including env/embedded.o at all results in the text/etc sections being
available for the rest of the link.  This in turn is required for the
setup used on ms7722se.  This also, likely, needs further fine-tuning.

Fixes: f40ad66fa0 ("arch/sh: don't bring common/env_embedded.o into the link")
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-27 11:50:16 -04:00
Tom Rini
c3b572c4e2 cmd/spl.c: Include <libfdt.h> for fdt_totalsize
In order to be able to reliably use fdt_totalsize, we must have
<libfdt.h> included.

Fixes: 767cb74a00 ("cmd: spl: provide address and size of prepared FDT ...")
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-26 21:17:05 -04:00
Tom Rini
8b3cec7da1 mtdparts: Fix uninitialized scalar usage
When reworking this code to fix other issues found by Coverity, I forgot
to ensure tmp_ep was always cleared before use.

Reported-by: Coverity (CID: 166612)
Fixes: bc028345ac ("mtdparts: Fix final outstanding issue reported by Coverity")
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-26 16:59:24 -04:00
Tom Rini
bd95e655b2 Merge git://git.denx.de/u-boot-sh 2017-08-26 15:10:49 -04:00
Tom Rini
f72b96ec8f Merge branch 'rmobile' of git://git.denx.de/u-boot-sh 2017-08-26 15:10:46 -04:00
Tom Rini
0031af9ce7 Merge git://git.denx.de/u-boot-x86 2017-08-26 15:10:40 -04:00
Tom Rini
cc0427d269 Merge git://git.denx.de/u-boot-i2c 2017-08-26 15:10:38 -04:00
Tom Rini
c2150e4dc1 Merge git://www.denx.de/git/u-boot-cfi-flash 2017-08-26 15:10:35 -04:00
Stefan Agner
5c27535dc9 disk: part: align buffer so it can be used with DMA enabled drivers
When using ISO partitions with a DMA enabled block device driver
reading the ISO partition leads to unaligned DMA operations:
  CACHE: Misaligned operation at range [bffb7da8, bffb85a8]

Align the buffer to make sure we pass a buffer which works for
DMA operations.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-26 14:56:15 -04:00
Stephen Boyd
527d86558e scripts: objdiff: Ignore debug info when comparing
If the kernel is configured to be built with debug symbols, or
has bug tables, comparing files may not work if line numbers
change. This makes comparing object files with these options
harder to do. Let's strip out the debug info and drop the
__bug_table here so that we don't see false positives. There may
be other things to drop later, and it may be architecture
specific, but this works for me with my ARM64 build.

[ Import Linux commit: 65ba6fa439e7c3cbf97de9dce9e7a3390ae2638c ]

Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Reviewed-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-26 14:56:14 -04:00
Masahiro Yamada
e43f74ac0b doc: verified-boot: fix typos
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-26 14:56:14 -04:00
Tom Rini
10b078d836 fs: ext4: Fix journal overrun issue reported by Coverity
While &p_jdb[fs->blksz] is a valid expression (it points *one* char
sized element past the end of the array, e.g. &p_jdb[fs->blksz + 1] is
invalid (according to the C standard (C99/C11)).

Changing this to tag = (struct ext3_journal_block_tag *)(p_jdb + ofs);

Cc: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Suggested-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Reported-by: Coverity (CID: 165117, 165110)
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
2017-08-26 14:56:13 -04:00
Tom Rini
bc028345ac mtdparts: Fix final outstanding issue reported by Coverity
As part of fixing the previously reported issues, it was missed that in
the case of mtdparts_init() we need to make sure that tmp_ep is long
enough to contain PARTITION_MAXLEN and a NULL termination.  Then, to be
sure the buffer is NULL terminated, zero the entire buffer rather than
just ensuring the first character is NULL.

Cc: Lothar Waßmann <LW@KARO-electronics.de>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Reported-by: Coverity (CID: 166329)
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-26 14:56:13 -04:00
Vikas Manocha
1e87f9ced4 spl: stm32: make falcon mode activation configurable
With this change, it will be possible to de-select falcon mode & spl
will only boot U-Boot.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Suggested-by: Bo Shen <voice.shen@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-26 14:56:13 -04:00
Anatolij Gustschin
767cb74a00 cmd: spl: provide address and size of prepared FDT in environment
Writing prepared FDT to persistent storage should be possible in
scripts. Create environment variables containing address and size
of the updated FDT. Scripts can use these variables after running
'spl export fdt ...' command to write the new blob to persistent
storage.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-08-26 14:56:12 -04:00
Pau Pajuelo
195dc23185 igep00x0: merge igep0020 and igep0030 defconfigs to igep00x0_defconfig
Update igep00x0 code with the following features:
- Add board and revision detection for the boards:
  - IGEP0020-RF
  - IGEP0020-RC
  - IGEP0030-RG
  - IGEP0030-RE
- Merge IGEP0020 and IGEP0030 mux tables
- Add suport to use GPIO_126, GPIO_127 and GPIO_129
- board_name and board_rev environment variables display board and
  revision informations
- Move dtb name selection from code to boot script

Signed-off-by: Pau Pajuelo <ppajuel@gmail.com>
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tested-by: Pau Pajuelo <ppajuel@gmail.com>
2017-08-26 14:56:12 -04:00
Ladislav Michl
4c699a4747 igep00x0: move SPL routines into separate file
Avoid cluttering board file with CONFIG_SPL_BUILD ifdefs
by moving SPL related functions into separate file.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tested-by: Pau Pajuelo <ppajuel@gmail.com>
Acked-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
2017-08-26 14:56:12 -04:00
Semen Protsenko
ea8c7fcacc arm: dra7xx: Define Android boot arguments
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
2017-08-26 14:56:11 -04:00
Semen Protsenko
49c7d0ac14 arm: am57xx: Define Android boot arguments
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
2017-08-26 14:56:11 -04:00
Semen Protsenko
a17c8b1844 arm: omap: Define command for booting Android from eMMC
If SD card is present -- try to boot from it first. If no -- try to boot
Android from eMMC.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
2017-08-26 14:56:11 -04:00
Ruchika Gupta
a797f274d7 ARMv8/sec_firmware : Update chosen/kaslr-seed with random number
kASLR support in kernel requires a random number to be passed via
chosen/kaslr-seed propert. sec_firmware generates this random seed
which can then be passed in the device tree node.

sec_firmware reserves JR3 for it's own usage. Node for JR3 is
removed from device-tree.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
2017-08-26 14:56:11 -04:00
Thomas Petazzoni
225bfd3906 arch/arm/cpu/arm926ejs/spear/cpu.c: guard do_switch_ecc() with CONFIG_NAND_FSMC
do_switch_ecc() calls fsmc_nand_switch_ecc(), which is a direct
function call into drivers/mtd/nand/fsmc_nand.c. However, this
function is not guarded by CONFIG_NAND_FSMC, which results to a build
failure if CONFIG_NAND_FSMC is disabled.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2017-08-26 14:56:10 -04:00
Thomas Petazzoni
c25c4fd010 board/spear/common: move code to arch/arm/cpu/arm926ejs/spear/
The code in board/spear/common/ is not board-specific but
SoC-specific. Therefore, boards from other vendors than "spear" may
want to re-use this code, which is currently difficult with the code
being placed in board/spear/common/.

Since this code really is SoC-specific, this commit moves it to
arch/arm/cpu/arm926ejs/spear/, with the rest of the SPEAr related
code.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2017-08-26 14:56:10 -04:00
Wenyou.Yang@microchip.com
fc6adebbc1 board: atmel: Use the new PIT timer driver
Use the Atmel PIT timer driver which supports the driver model
and device tree.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-08-26 14:56:09 -04:00
Wenyou.Yang@microchip.com
47edaea494 driver: timer: Add the Atmel PIT timer driver
Add the new Atmel PIT timer driver, which supports the driver model
and device tree.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-08-26 14:56:08 -04:00
Tom Rini
deff9b1d2a powerpc: Rework interrupt_init_cpu()
The function interrupt_init_cpu() is given an int return type but does
not return anything but 0.  Rework this to be a void function.

Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Mario Six <mario.six@gdsys.cc>
2017-08-26 14:56:08 -04:00
Reno Farnesi
76216211f8 fs: fat: fix fatwrite overflow calculation
The overflow calculation was incorrect. Adding the start block of the
partition is not needed because the sectors are already relative to the
beginning of the partition. If you attempted to write a file smaller
than cur_part_info.start blocks on a full partition the old calculation
fails to catch the overflow. This would cause an infinite loop in the
determine_fatent function.

Old, incorrect calculation:

ending sector of new file = start sector + file size (in sectors)
last sector = partition start + total sectors on the partition

Adding the partition start block number is not needed because sectors
are already relative to the start of the partition.

New calculation:

ending sector of new file = start sector + file size (in sectors)
last sector = total sectors on the partition

Signed-off-by: Reno Farnesi <nfarnesi4@gmail.com>
2017-08-26 14:56:07 -04:00
Suniel Mahesh
528f2b66dc arm: dts: am33xx: sync DTS with Linux 4.13-rc4
This re-syncs AM33xx DTS file with current file from
Linux v4.13-rc4 to ensure a consistent configuration. Upstream
Linux removed the redundant Interrupt-parent property from mmc,
mac, lcdc and tscadc sub nodes.

Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-26 14:56:07 -04:00
Jagan Teki
93fd5b0ac1 ram: kconfig: s/SPL/TPL/ in TPL_RAM help text
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-08-26 14:56:06 -04:00
Simon Glass
e5ec12bbe1 rpi: Enable USB keyboard support
This is currently disabled, so USB keyboards are not detected in U-Boot.
Enable this option to fix that.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Paul Barker <pbarker@toganlabs.com>
2017-08-26 14:55:49 -04:00
Thomas Petazzoni
f40ad66fa0 arch/sh: don't bring common/env_embedded.o into the link
The linker script for SuperH brings the .ppcenv and .ppcenvr section
of common/env_embedded.o into the .text section. However, the .ppcenv
section is only ever filled in by env_embedded.o when
CONFIG_SYS_USE_PPCENV is defined, but no platforms in mainline U-Boot
use this.

In addition, common/env_embedded.o is not always built (when you use
CONFIG_ENV_IS_NOWHERE for example), which causes the following build
failure:

Fixes:

  LD      u-boot
/home/thomas/sh4aeb-linux-musl/bin/sh4aeb-linux-ld.bfd: cannot find common/env_embedded.o

We fix this by no longer adding the .ppcenv and .ppcenvr sections from
common/env_embedded.o into the .text section.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:40:36 +09:00
Thomas Petazzoni
90340c87e5 arch/sh: allow building in big-endian mode
The SuperH architecture allows to be run in either little or big
endian mode. Some SuperH SoCs get the little vs. big endian decision
through mode pins sampled at reset, so if big endian has been choosen
by HW designers, it cannot be easily changed.

Therefore, it makes sense to allow building U-Boot for SuperH in big
endian mode. To allow this, the only change needed is to adjust the
OUTPUT_FORMAT() in the linker script.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2017-08-26 07:38:39 +09:00
Marek Vasut
f7f79b4493 ARM: rmobile: Enable MMC and USB DM on ULCB
Enable the MMC and USB DM on the board since it's the modern method
and now supported by the drivers.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
3345ca21a1 ARM: rmobile: Enable MMC and USB DM on Salvator-X
Enable the MMC and USB DM on the board since it's the modern method
and now supported by the drivers.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
6f38085492 ARM: rmobile: Remove SH SDHI probing from ULCB board
Drop the SH SDHI bit from the board since SD now probes from DT instead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
ddb39a075b ARM: rmobile: Remove SH SDHI probing from Salvator-X board
Drop the SH SDHI bit from the board since SD now probes from DT instead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
3f63551471 ARM: rmobile: Remove Serial SH probing from ULCB board
Drop the Serial SH bit from the board since UART now probes from DT instead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
1c30aea5b1 ARM: rmobile: Remove Serial SH probing from Salvator-X board
Drop the Serial SH bit from the board since UART now probes from DT instead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
75ba2bf99f ARM: rmobile: Remove RAVB probing from ULCB board
Drop the RAVB bit from the board since RAVB now probes from DT instead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
a88026c51d ARM: rmobile: Remove RAVB probing from Salvator-X board
Drop the RAVB bit from the board since RAVB now probes from DT instead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
d47f356cde ARM: rmobile: Enable HUSH parser
The HUSH parser was disabled somewhere along the way, reenable it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alexandru Gagniuc <alex.g@adaptrum.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
c4464e163e ARM: rmobile: Enable KSZ90X1 PHY on Salvator-X
Commit da3b9e7fd6 (Move PHY_MICREL and PHY_MICREL_KSZ90X1 to Kconfig)
broke ethernet support on R8A779x Salvator-X boards by disabling the
KSZ90x1 PHY in Kconfig. Reenable it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alexandru Gagniuc <alex.g@adaptrum.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
46933dfbe1 ARM: rmobile: Add u-boot, dm-pre-reloc to clock nodes on Gen3
We need the clock available very early, add the u-boot,dm-pre-reloc
DT property on those nodes, so they come up very in the process.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
fd8692b8ff clk: rmobile: Split R8A7795 and R8A7796 core clock tables
The R8A7795 and R8A7796 tables use different constants to identify
clock in DT, so split the tables and use the correct constants on
R8A7795. This fixes UART clock misconfiguration on R8A7795.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Bin Meng
438505fe69 x86: tangier: kconfig: Guard tangier-specific options
These options should not be exposed to other platforms.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2017-08-24 11:00:47 +08:00
Bin Meng
207d532bef x86: bayleybay: Adjust VGA rom address
Adjust VGA rom address to 0xfffb0000 so that u-boot.rom image can be
built again.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-24 11:00:47 +08:00
Bin Meng
81c727d86c x86: baytrail: Fix turbo enable
CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED must be turned on for Baytrail.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-24 11:00:47 +08:00
Bin Meng
2ddb1a177a x86: Convert CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED to Kconfig
This converts CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED to a Kconfig option.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-24 11:00:47 +08:00
Stefan Roese
5091a8b04d x86: dfi-bt700: Select SERIAL_RX_BUFFER via Kconfig
To support more input characters (longer stings pasted into the U-Boot
prompt) without dropping, lets selects the recently added UART RX
buffer for these boards.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-24 11:00:47 +08:00
Stefan Roese
b48dcd3751 x86: conga-qeval20-qa3-e3845: Select SERIAL_RX_BUFFER via Kconfig
To support more input characters (longer stings pasted into the U-Boot
prompt) without dropping, lets selects the recently added UART RX
buffer for these boards.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-24 11:00:47 +08:00
Stefan Roese
3ca7a06afb serial: serial-uclass: Add generic serial RX buffer support
Pasting longer lines into the U-Boot console prompt sometimes leads to
characters missing. One problem here is the small 16-byte FIFO of the
legacy NS16550 UART, e.g. on x86 platforms.

This patch now introduces a Kconfig option to enable RX buffer support
for all DM based serial drivers. With this option enabled, I was
able paste really long lines into the U-Boot console, without any
characters missing.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-24 11:00:47 +08:00
Stefan Roese
7fded0ce0f Revert "serial: ns16550: Add RX interrupt buffer support"
This reverts commit 6822cf3ec7.

As Bin Meng has tested and pointed out, we don't need the RX interrupt
for the RX buffer support at all. Just reading all available characters
into a buffer is sufficient to solve the problem with the dropped
characters upon long lines pasted into the U-Boot prompt. Since this
RX buffer support can be implemented in a generic way, without any
device specifica (e.g. for the ns16550), I'll post a new patch with
a new serial RX buffer support for DM, which all DM based serial
drivers can use.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-24 11:00:47 +08:00
Bin Meng
76e726502e vbe: Drop vbe_get_video_info()
With DM video, this is not used any more. Drop it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-24 11:00:47 +08:00
Bin Meng
c11b17c6bf x86: kconfig: Imply CMD_PCI
Let's imply the 'pci' command to access the de facto interconnect
bus in an x86 system.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24 11:00:47 +08:00
Bin Meng
1e6ebee667 x86: fsp: Configure SPI opcode registers before SPI is locked down
Some Intel FSP (like Braswell) does SPI lock-down during the call
to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done,
it's bootloader's responsibility to configure the SPI controller's
opcode registers properly otherwise SPI controller driver doesn't
know how to communicate with the SPI flash device.

This introduces a Kconfig option CONFIG_FSP_LOCKDOWN_SPI for such
FSPs. When it is on, U-Boot will configure the SPI opcode registers
before the lock-down.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24 11:00:47 +08:00
Bin Meng
b42711f90c x86: ich-spi: Move opcode registers configuration to another routine
At present the ICH SPI opcode registers configuration is done in the
ich_spi_remove() routine, a little bit weird but that's how current.
Linux MTD driver works. This changes to move the opcode registers
configuration to a separate routine ich_spi_config_opcode() which
might be called by U-Boot itself as well.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24 11:00:47 +08:00
Bin Meng
3e79141684 x86: ich-spi: Don't read cached lock status
At present the ICH SPI controller driver reads the controller lock
status from its register in the probe routine and saves the lock
status to a member of priv. Later the driver uses the cached status
from priv to judge whether the controller setting is locked and do
different setup.

But such logic is only valid when there is only the SPI controller
driver that touches the SPI hardware. In fact the lock status change
can be trigged outside the driver, eg: during the fsp_notify() call
when Intel FSP is used.

This changes the driver to read the lock status every time when an
SPI transfer is initiated instead of reading the cached one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24 11:00:47 +08:00
Bin Meng
7d82978927 x86: ich-spi: Remove unnecessary assignment in ich_init_controller()
There is no need to do another assignment to ich7_spi.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24 11:00:47 +08:00
Bin Meng
94bc9177ca x86: ich-spi: Remove spi_write_protect_region()
This routine is not called anywhere.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24 11:00:47 +08:00
Peng Fan
a430556ecb i2c: muxes: add i2c gpio multiplexer driver
Add an i2c mux driver providing access to i2c bus segments using a
hardware MUX sitting on a master bus and controlled through gpio pins.

E.G. something like:

         ----------              ----------  Bus segment 1   - - - - -
        |          | SCL/SDA    |          |-------------- |           |
        |          |------------|          |
        |          |            |          | Bus segment 2 |           |
        |  Linux   | GPIO 1..N  |   MUX    |---------------   Devices
        |          |------------|          |               |           |
        |          |            |          | Bus segment M
        |          |            |          |---------------|           |
         ----------              ----------                  - - - - -

SCL/SDA of the master I2C bus is multiplexed to bus segment 1..M
according to the settings of the GPIO pins 1..N.

Note commit log from kernel
commit 92ed1a76("i2c: Add generic I2C multiplexer using GPIO API")

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Peng Fan <peng.fan@nxp.com> (i.MX6QP-Sabreauto)
Cc: Heiko Schocher <hs@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Simon Glass <sjg@chromium.org>
2017-08-23 07:04:56 +02:00
Patrice Chotard
4fadcaf097 i2c: add i2c driver for stm32
Add i2c driver which can be used on both STM32F7 and STM32H7.
This I2C block supports the following features:
 _ Slave and master modes
 _ Multimaster capability
 _ Standard-mode (up to 100 kHz)
 _ Fast-mode (up to 400 kHz)
 _ Fast-mode Plus (up to 1 MHz)
 _ 7-bit and 10-bit addressing mode
 _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
 _ All 7-bit addresses acknowledge mode
 _ General call
 _ Programmable setup and hold times
 _ Easy to use event management
 _ Optional clock stretching
 _ Software reset

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-23 07:04:40 +02:00
Tom Rini
90ae53ce1a fastboot: Ensure we treat CONFIG_FASTBOOT_BUF_ADDR as long
Otherwise:
drivers/usb/gadget/f_fastboot.c:564:32: warning: format "%lx" expects
argument of type "long unsigned int", but argument 3 has type "unsigned
int" [-Wformat=]

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-22 08:20:02 -04:00
Marek Vasut
236c49a1c8 mtd: cfi: staticize functions
Staticize a few functions and variables which are no longer exposed.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-22 09:56:09 +02:00
Tom Rini
ad8afeaee0 Merge git://www.denx.de/git/u-boot-marvell 2017-08-21 07:17:15 -04:00
Tom Rini
09b6a6dd01 Merge git://git.denx.de/u-boot-usb 2017-08-21 07:16:56 -04:00
Tom Rini
8197d92843 Merge git://git.denx.de/u-boot-uniphier
- Fix unmet direct dependencies warning
 - Remove old sLD3 SoC support
 - Update reset data
 - Add dr_mode DT property to avoid warning
2017-08-21 07:16:16 -04:00
Chris Packham
6ab09b05f3 ARM: mvebu: set correct mem_size for db-88f6820-amc
The db-88f6820-amc has four chips with 2Gb density giving a total of 1GB
DRAM. Update the board_topology_map to reflect the correct
configuration.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-21 11:40:49 +02:00
Lukasz Majewski
5bf4475f1d doc: license: Add license header to the README.dfutftp file
Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-08-21 11:31:11 +02:00
Tom Rini
6bafa5a4bd fb_mmc.c: Correct blk_dread() return value checks
The function blk_dread will return -ENOSYS on failure or on success the
number of blocks read, which must be the number asked to read (otherwise
it failed somewhere).  Correct this check.

Cc: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-21 11:31:11 +02:00
Tom Rini
2341c80cd2 common/fb_mmc.c: Fix warnings about casts
When building the flash zImage code on aarch64 we see warnings about
pointer size casts.  Use uintptr_t instead to correct these.

Cc: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-By: Sam Protsenko <semen.protsenko@linaro.org>
2017-08-21 11:31:10 +02:00
John Keeping
7715dea48b fastboot: avoid printing invalid data
There is no guarantee that commands are null-terminated in the USB
request buffer, so limit the length of data that is printed.

Signed-off-by: John Keeping <john@metanate.com>
Tested-by: Steve Rae <steve.rae@raedomain.com>
2017-08-21 11:31:10 +02:00
Peter Chubb
d331084298 Fix fastboot boot address
Fastboot loads an image at CONFIG_FASTBOOT_BUF_ADDR, but currently
tells do_bootm() to look for an image at $loadaddr.  This breaks if
CONFIG_FASTBOOT_BUF_ADDR is different from the current user-set
loadaddr.

Instead, tell do_bootm() to pick up the image where it was laoded.

Signed-off-by: Peter Chubb <peter.chubb@data61.csiro.au>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Steve Rae <steve.rae@raedomain.com>
2017-08-21 11:31:10 +02:00
Bin Meng
a11a5b8ad9 usb: ehci: Convert CONFIG_USB_EHCI_PCI to Kconfig
This converts CONFIG_USB_EHCI_PCI to a Kconfig option, and updates
all boards that use it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-21 11:30:44 +02:00
Simon Glass
2d7cb5b426 env: Replace all open-coded gd->env_valid values with ENV_ flags
Some of these were missed in the conversion.
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-20 19:27:44 -04:00
Simon Glass
c55d8b9400 env: Allow env_load() to detect errors
Now that we have errors available in the environment driver's load()
method, check the return valid.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-20 19:27:43 -04:00
Tom Rini
eeba55cb4a env: Correct case of no sub-init function
With the change to the environment code to remove the common init stage
of pointing to the default environment and setting it as valid, combined
with the change to switch gd->env_valid from 0/1/2 to an enum we now
must set env_valid to one of the enum values rather than an int.  And in
this case, not only was setting it to an int wrong, it was now the wrong
value.  Finally, in the case of ENV_IS_NOWHERE we must still say that
our envionrment is invalid after init for things to continue to
function.

Fixes: 7938822a6b ("env: Drop common init() functions")
Tested-by: Marek Vasut <marek.vasut@gmail.com>
Reported-by: Marek Vasut <marek.vasut@gmail.com>
Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
Changes in v3:
- Actually include changes for env/nowhere.c
2017-08-20 19:27:28 -04:00
Masahiro Yamada
3444d1d40e ARM: dts: uniphier: add dr_mode property to dwc3 node
Since commit 576e3cc700 ("usb: host: xhci-dwc3: Add dual role mode
support from DT"), warning is displayed if dr_mode is not specified.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-20 23:07:02 +09:00
Masahiro Yamada
6584b1ea10 reset: uniphier: refactor reset data and add NAND/eMMC reset lines
- Merge sys_reset data of LD4, Pro4, sLD8 and Pro5

  - Merge sys_reset data of LD11 and LD20

  - Use primitive UNIPHIER_RESETX() macro because bit assignments for
    system reset will be changed for every SoC in the future

  - Add NAND and eMMC resets

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-20 23:06:20 +09:00
Masahiro Yamada
c5161eee38 Revert "ARM: uniphier: fix ROM boot mode for PH1-sLD3"
This reverts commit 82d075e79f.

Commit 82d075e79f ("ARM: uniphier: fix ROM boot mode for PH1-sLD3")
was a workaround for sLD3.  Now the sLD3 SoC support has been removed.

Revert it to allow to simplify the init code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-20 23:05:39 +09:00
Masahiro Yamada
0aa8b2c3e0 Revert "ARM: uniphier: move lowlevel debug init code after page table switch"
This reverts commit bcc51c1512.

Commit bcc51c1512 ("ARM: uniphier: move lowlevel debug init code
after page table switch") was intended to support lowlevel debug for
sLD3.  Now the sLD3 SoC support has been removed.

Revert it to allow to enable lowlevel debug earlier.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-20 23:05:39 +09:00
Masahiro Yamada
00aa453ebf ARM: uniphier: remove sLD3 SoC support
This SoC is too old.  It is difficult to maintain any longer.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-20 23:05:39 +09:00
Masahiro Yamada
213fcabdfd clk: uniphier: fix unmet direct dependencies warning
Since commit f0776a5517 ("spl: dm: Kconfig: SPL_CLK depends on
SPL_DM"), the following warning is displayed:

  $ make uniphier_v8_defconfig
  warning: (ARCH_ZYNQ && ARCH_ZYNQMP && STM32F7 && CLK_UNIPHIER) selects
  SPL_CLK which has unmet direct dependencies (CLK && SPL_DM)

While I am here, I am removing the prompt to make it user-unconfigurable
option so that "select CLK_UNIPHIER" can be omitted.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-20 23:05:39 +09:00
Anatolij Gustschin
f1a7ba1da5 Fix 'notes' typos
s/notes/nodes

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-08-20 09:54:34 -04:00
Andy Shevchenko
e94c1268f2 env: Sort selection of default choices
It would be easier to catch out which platform is using which default.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2017-08-20 09:54:33 -04:00
Heiko Schocher
79c85f7115 arm, at91: fix taurus board
since commit: b529993e02 "spl: add hierarchical defaults for SPL_LDSCRIPT"

taurus board stopped working. Use the ldscript from
arch/arm/cpu/u-boot-spl.lds (as before this patch) fixed it.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-20 09:54:33 -04:00
Thomas Petazzoni
c1ee8936bf common/board_f.c: remove CONFIG_SYS_GENERIC_GLOBAL_DATA
CONFIG_SYS_GENERIC_GLOBAL_DATA is no longer used by any board or
platform, so support for it can be dropped.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-20 09:54:32 -04:00
Peter Griffin
fb53e7eb60 ARM: hisilicon: hikey: Fix eMMC with latest ATF & U-Boot
ATF can leave the MMC IP in a state where U-Boot mmc driver
can't enumerate the eMMC.

This patch provides a mmc0_reset_clk() function like we
already so do sd card controller which resets the IP
when entering U-Boot.

With this patch applied eMMC partitions are successfully
enumerated again.

=> mmc dev 0
switch to partitions #0, OK
mmc0(part 0) is current device
=> mmc part

Partition Map for MMC device 0  --   Partition Type: EFI

Part	Start LBA	End LBA		Name
	Attributes
	Type GUID
	Partition GUID
  1	0x00000800	0x00000fff	"vrl"
	attrs:	0x0000000000000000
	type:	ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
	guid:	496847ab-56a1-4cd5-a1ad-47f4acf055c9
  2	0x00001000	0x000017ff	"vrl_backup"
	attrs:	0x0000000000000000
	type:	ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
	guid:	61a36fc1-8efb-4899-84d8-b61642efa723
  3	0x00001800	0x00001fff	"mcuimage"
<snip>

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
2017-08-20 09:54:31 -04:00
Tom Rini
42a9f147d8 fs/fat: Correct blk_dread() return value check
The function blk_dread will return -ENOSYS on failure or on success the
number of blocks read, which must be the number asked to read (otherwise
it failed somewhere).  Correct this check.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-20 09:54:31 -04:00
Tom Rini
9585dd3fff spl: spl_mmc.c Correct blk_dread() return value check
The function blk_dread will return -ENOSYS on failure or on success the
number of blocks read, which must be the number asked to read (otherwise
it failed somewhere).  Correct this check.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-20 09:54:30 -04:00
Tom Rini
d03618d5cb cmd/read.c: Fix checking blk_dread return value
The function blk_dread will return -ENOSYS on failure or on success the
number of blocks read, which must be the number asked to read (otherwise
it failed somewhere).  Correct this check.

Reported-by: Coverity (CID: 166335)
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-20 09:54:30 -04:00
Tom Rini
54f1792c8d mtdparts: Fix various issues reported by Coverity
Now that sandbox is building cmd/mtdparts.c Coverity has looked at the
code and found a number of issues.  In index_partitions() it is possible
that part will be NULL, so re-work the checks and debug statements to
take this into account.  We have a number of string buffers that we
print to in the exact size of, and use string functions on, so we need
to ensure they are large enough to be NULL terminated.  In
device_parse() it is not possible for num_partitions to be 0 (we would
have hit a different error first) so remove logically dead code.
Finally, in parse_mtdparts() if we have an error we need to free the
memory allocated to dev.

Cc: Lothar Waßmann <LW@KARO-electronics.de>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Reported-by: Coverity (CID: 166334, 166333, 166332, 166329, 166328)
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-20 09:54:29 -04:00
Tom Rini
78eda89e9a hash: Compile only hardware or software versions of SHA algorithms
Commit 089df18bfe ("lib: move hash CONFIG options to Kconfig") moved
CONFIG_SHA1, CONFIG_SHA256, CONFIG_SHA_HW_ACCEL, and
CONFIG_SHA_PROG_HW_ACCEL config options to Kconfig. So in the case of
SPL, CONFIG_SPL_HASH_SUPPORT enables CONFIG_SHA1 and CONFIG_SHA256 which
enables SHA SW library by default.  But in the case of platforms with
SHA HW library support, SHA SW library becomes redundant and increases
size of SPL by approx 18K.  Rework the code so that we have named
members and only have either software or hardware versions of the
algorithm, depending on the relevant config options.  Update the comment
around hash_algo to reflect this as well.

Reported-by: Sumit Garg <sumit.garg@nxp.com>
Cc: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Sumit Garg <sumit.garg@nxp.com>
2017-08-20 09:53:13 -04:00
Clément Bœsch
3809e30273 Makefile: honor PYTHON configuration properly
On some systems `python` is `python3` (for instance, Archlinux). The
`PYTHON` variable can be used to point to `python2` to have a successful
build.

The use of `PYTHON` is currently limited in the Makefile and needs to be
extended in other places:

First, pylibfdt is required to be a Python 2 binding (binman imports
pylibfdt and is only compatible Python 2), so its setup.py needs to be
called accordingly. An alternative would be to change the libfdt
setup.py shebang to python2, but the binding is actually portable. Also,
it would break on system where there is no such thing as `python2`.

Secondly, the libfdt import checks need to be done against Python 2 as
well since the Python 2 compiled modules (in this case _libdft.so) can
not be imported from Python 3.

Note on the libfdt imports: "@if ! PYTHONPATH=tools $(PYTHON) -c 'import
libfdt'; then..." is probably simpler than the currently sub-optimal
pipe.
Reviewed-by: Jonathan Gray <jsg@jsg.id.au>
2017-08-20 09:53:13 -04:00
Tom Rini
2629a21e20 Merge git://git.denx.de/u-boot-video 2017-08-19 22:11:05 -04:00
xypron.glpk@gmx.de
021414a332 lcd: avoid possible NULL dereference
Do not dereference bmp before the check if it is NULL.

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-19 20:42:20 +02:00
Tom Rini
5619295995 Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot
EFI Fixes for 2017.09:
  - Fix GOP w/o display
  - Fix LocateHandle
  - Fix exit return value truncation
  - Fix missing EFIAPI in efi_locate_handle (for x86)
2017-08-18 18:24:58 -04:00
Tom Rini
1fdafb2e3d Merge branch 'master' of git://git.denx.de/u-boot-mmc 2017-08-18 18:24:36 -04:00
Tom Rini
a6dd10c70b Merge branch 'master' of git://git.denx.de/u-boot-coldfire 2017-08-18 18:24:08 -04:00
Tom Rini
804f1d9938 Merge branch 'master' of git://git.denx.de/u-boot-rockchip 2017-08-18 18:23:58 -04:00
Kever Yang
957b4ee3f3 rockchip: rk322x: pinctrl: fix IO MASK error on sdcard pin
Fix the IOMUX setting for SDcard CMD pin at the same time.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-18 18:00:46 +02:00
Kever Yang
a634236b8d rockchip: rk322x: pinctrl: using compatible name same with dts
The dts from kernel is using rk3228-pinctrl as compatible name,
need to sync with it to make the driver work.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-18 18:00:29 +02:00
Kever Yang
a80b3b0378 rockchip: rk322x: update MACRO for mmc clksel reg
The description for eMMC/SDIO/SDMMC src is not correct,
update the CRU_CLKSEL11_CON value definition according to TRM.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-18 17:52:47 +02:00
Kever Yang
44c5ba557b rockchip: rk322x: update dram bank size
The DRAM start address is not 0, so need to update the last bank size
as:
DRAM start addr + DRAM_SIZE - last bank start addr

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-18 16:55:25 +02:00
Philipp Tomsich
a299a4879e rockchip: rk3399: spl: remove unused header inclusion
fdtdec.h is included, but not used in rk3399-board-spl.c: remove the
'#include'-statement.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-18 16:55:15 +02:00
Kever Yang
caa6b3b530 rockchip: dts: rk3399-evb: remove redundant gmac node
There are two same gmac node, remove one.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-18 16:54:39 +02:00
xypron.glpk@gmx.de
c81883dfce efi_loader: do not cast return value in EFI_EXIT
UEFI API functions have different return types.
Some return a value of type EFI_STATUS other don't.

We therefore should not cast the return value of EFI_EXIT
to another type than the expression passed to EFI_EXIT.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-08-18 10:53:23 +02:00
Bin Meng
a191ccaf12 mmc: Support generic PCI SD host controller
This changes pci_mmc driver to use PCI_CLASS_SYSTEM_SDHCI instead of
individual vendor id & device id pair to support generic PCI SD host
controller.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-18 15:37:38 +09:00
Angelo Dureghello
a373024e7f m68k: add board stmark2, mcf5441x based
Sysam stmark2 board is a generic and fully (hw and sw) open board, with
a mcf54415 Coldfire CPU, 128MB of DDR2, 16MB of SPI flash and SD card
as non volatile memories, and a wifi module included on-board.
The board is actually used mainly for Coldfire custodian testing activity
related to the mcf5441x Coldfire family.

For further information please see: http://sysam.it/cff_stmark2.html

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
---

Changes in v2:
 - remove CMD_REGINFO
 - add board information in commit message
2017-08-18 01:26:52 +02:00
Angelo Dureghello
02a6eddaba m68k: mcf5445x: allow CS0 to be undefined
On some boards, CONFIG_SYS_CS0_BASE can be undefined, since
CS0 is not connected to any signal.

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
2017-08-18 01:26:39 +02:00
Angelo Dureghello
c533cfcd93 m68k: fix cache.c for Coldfire V4E
- fix cache.c CONFIG_CF_V4e to CONFIG_CF_V4E
- fix cache.c to properly enable/disable cache for V4E

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
2017-08-18 01:26:17 +02:00
Angelo Dureghello
c74dda8b44 m68k: mcf5445x: move early ddr init as board-specific
For certain boot types and sbf, for V4 cpu's, an early ddr/sdram init
is required. This patch moves this ddr/sdram early initalization
away from start.S (to be board related).

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
2017-08-18 01:26:08 +02:00
Philipp Tomsich
b5c4d81b35 spl: fix Makefile for NOR, XIP and YMODEM
During the the conversion to $(SPL_TPL_), the SPL_ fragment was
left over for the NOR, XIP and YMODEM boot methods in SPL, making
these unselectable.

This commit fixes this by dropping the spurious 'SPL_' fragment
from each line.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reported-by: Bo Shen <voice.shen@gmail.com>
Fixes: f94e643 (spl: consistently use $(SPL_TPL_) to select features for SPL and TPL builds)
2017-08-17 10:15:24 +02:00
Kever Yang
1ade3a9013 rockchip: dts: rk3399-firefly: update gmac parameter
Update the tx_delay and rx_delay to match the timing for
rk3399-firefly board to improve the stability of gmac data
transfer.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-17 10:11:18 +02:00
Angelo Dureghello
bdb6099666 cmd: mmc: add mmc partconf read capability
This patch allows to show the EXT_CSD[179] partition_config
register info, just by specifying the dev param:

  U-Boot> mmc partconf 0
  EXT_CSD[179], PARTITION_CONFIG:
  BOOT_ACK: 0x0
  BOOT_PARTITION_ENABLE: 0x0
  PARTITION_ACCESS: 0x0

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-08-17 17:00:11 +09:00
Simon Glass
e7881d85a9 dm: mmc: Drop CONFIG_DM_MMC_OPS
All boards which use DM_MMC have now been converted to use DM_MMC_OPS.
Drop the option and good riddance.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:59:55 +09:00
Simon Glass
b9a40c0c0a dm: mmc: Correct Kconfig condition for SPL_DM_MMC_OPS
This should depend on SPL_DM_MMC, not SPL_DM. For it and update the only
affected board's defconfig.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:18 +09:00
Simon Glass
2088747743 dm: imx: Move i.MX devices to use CONFIG_DM_MMC_OPS
Now that the driver supports it, move these boards over to use driver
model fully for MMC.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
5248930ebf dm: imx: cm_fx6: Enable more driver model support
Enable driver model for MMC (including BLK), SATA and USB. Note that USB
does not yet work correctly since the nodes are disabled. Hopefully this
can be resolved by the maintainer.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
4f6478d646 dm: imx: cm_fx6: Add MMC support for CONFIG_BLK
When CONFIG_BLK is enabled our weak board_mmc_init() will not be called.
Since there is no clock driver for MX6 yet, we must manually enable the
clocks.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
5ec1f560f3 dm: imx: cm_fx6: Add device tree for cm_fx6
Add this file so we can use device-tree control for cm_fx6. It comes from
linux 4.12.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
8d331e38e0 dm: imx: cm_fx6: Support driver model for SATA
Add support for using driver model for SATA with the cm_fx6 board. The old
code remains for now to permit testing.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
653282b567 dm: mmc: fsl_esdhc: Update to support MMC operations
This driver does not currently support CONFIG_DM_MMC_OPS. Update it to
fully convert it to driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
4aac33f510 dm: mmc: fsl_esdhc: Update to support livetree
Update this driver to support a live device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
d6eb25e987 dm: mmc: fsl_esdhc: Drop mmc_init() call from fsl_esdhc_init()
We want to use fsl_esdhc_init() with driver model. Move the mmc_init() out
of this function so that we can use it for our common init.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
e88e1d9c04 dm: mmc: fsl_esdhc: Set up platform data
With driver model we want to store the mmc and configuration structure in
platform data. Set up structure up and use it for non-DM as well.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
201e828b22 dm: mmc: fsl_esdhc: Detect init failure
Since esdhc_init_common() can fail it should return an error code. Update
this and also adjust the timeout mechanism to use get_timer(), which is a
more common approach.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
446e077a21 dm: mmc: fsl_esdhc: Detect reset failure
Since esdhc_reset() can fail it should return an error code. Update this
and also adjust the timeout mechanism to use get_timer(), which is a more
common approach.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
9586aa6ea3 dm: mmc: fsl_esdhc: Set up common versions of operations
Driver model wants to use the core functions in this file but accesses the
driver-private data in a different way. Move the code into new 'common'
functions and set up stubs to call these. Also sort the operations into
alphabetical order for consistency.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
09b465fd0f dm: mmc: fsl_esdhc: Pass private data to internal functions
With driver model we will not use mmc->priv to access driver-private data.
To accomodate this, update internal functions so that we can pass the
private data directly. This will allow the caller to obtain it as it
prefers.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
c893f1e6e5 dm: sata: dwc_ahsata: Add support for driver model
Update this driver to support driver model. This involves implementing the
AHCI operations and reusing existing common code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
b8341f1c39 dm: sata: Update the AHCI uclass to support operations
At present the AHCI uclass is just a shell and we still use the global
functions to access SATA. Fix this by adding operations to the uclass.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
7e0712b26e dm: sata: imx: Allow driver model to be used for sata
Update the sata call to work with driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
f19f1ecb60 dm: sata: Support driver model with the 'sata' command
Update this command to support driver model. This has a different way of
starting and stopping SATA.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
752126a05a dm: sata: dw_sata: Set up common versions of operations
Driver model wants to use the core functions in this file but accesses the
uclass-private data in a different way. Move the code into new 'common'
functions and set up stubs to call these.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
036a803e1b dm: sata: dw_sata: More ahci_init_one() futher down
This function will not be used with driver model and it relates to the
other exported functions. Move it down next to them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
5908d85eb7 dm: sata: dw_sata: Drop is_ready
This variable is set but never used. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
90abb28fcf dm: sata: dw_sata: Rename the dwc_ahsata private header
Rename dwc_ahsata.h to indicate that it is a private header file. We plan
to create another header with some public functions.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
0f07df4301 dm: sata: dw_sata: Sort #include directives
Sort the header file inclusions into the correct order.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
3e59c30fcf dm: sata: dw_sata: Drop unnecessary brackets
There is a strange &(var) coding style in this driver. Adjust it to use
&var instead, which is more usual.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
47c0f3692d dm: sata: dw_sata: Pass uc_priv to internal functions
With driver model sata_dev_desc[] does not exist. We still want to use the
common code of this driver so update it to pass struct ahci_uc_priv * to
each of these functions, instead of an integer which must be looked up in
sata_dev_desc[].

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
4b640dbcac dm: sata: dw_sata: Drop unnecessary casts
Most of the casts in this driver are not necessary. With driver model we
do not cast from void *. Update the driver to follow this rule.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
09bb951bf3 dm: sata: dw_sata: Rename 'probe_ent' to uc_priv
With driver model this becomes uclass-private data. Rename the parameter
varable to reflect this.

With the driver model conversion we will not have any exported functions.
Move all exported functions to be together at the end of the file so that
we can deal with them in one #ifdef block.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:16 +09:00
Simon Glass
c5273acf5c dm: sata: dw_sata: Move exported functions to the end
With the driver model conversion we will not have any exported functions.
Move all exported functions to be together at the end of the file so that
we can deal with them in one #ifdef block.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:16 +09:00
Simon Glass
1dae3b06b7 dm: sata: dw_sata: Drop dwc_ahsata_rw_ncq_cmd()
This function is not called from anywhere. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:16 +09:00
Simon Glass
d7f094354c dm: sata: dwc_ahsata: Make functions static
Some functions are not called from outside this file. Make these static
to make that obvious.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:16 +09:00
Simon Glass
e88afccc44 dm: core: Add a comment about the device_remove() flags
We should explain which flags are used for this function. Update the
comment to indicate this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:16 +09:00
Simon Glass
7074b2a364 dm: blk: Update return value in blk_create_devicef()
This returns 'ret' but the value is always zero. Update it to simply
return 0, for clarity.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:16 +09:00
Simon Glass
c16ad675d5 dm: usb: Adjust the 'usb' command to use blk_common_cmd()
Instead of having separate code in the 'usb' command, adjust it to use
the common function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-17 16:44:16 +09:00
Simon Glass
09ed0d616d dm: ide: Adjust the 'ide' command to use blk_common_cmd()
Instead of having separate code in the 'ide' command, adjust it to use
the common function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-17 16:44:16 +09:00
Simon Glass
1eaadd3423 dm: scsi: Adjust the 'scsi' command to use blk_common_cmd()
Instead of having separate code in the 'scsi' command, adjust it to use
the common function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-17 16:44:16 +09:00
Simon Glass
e29e71e93a dm: sata: Adjust the 'sata' command to use blk_common_cmd()
Instead of having separate code in the 'sata' command, adjust it to use
the common function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-17 16:44:16 +09:00
Simon Glass
4395f66739 dm: blk: Add a generic function for block device commands
Most block devices provide a command (e.g. 'sata', 'scsi', 'ide') and
these commands generally do the same thing. This makes it harder to
maintain this code and keep it consistent.

We now have a block device interface which is either implemented by driver
model (when CONFIG_BLK is enabled) or with a legacy interface. Therefore
it is possible to handle most of what these commands do with generic code.

Add a new generic function to process block-device commands using the
interface type and the current device number for that type.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:16 +09:00
Simon Glass
6faa4ed74d dm: blk: Add a function to find an interface-type name
Add a function to find the name of an interface type (e.g. "sata", "scsi")
from the interface type enum.

This is useful for generic code (not specific to SATA or SCSI, for
example) that wants to display the type of interface it is dealing with.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:16 +09:00
Simon Glass
745fb9c25e dm: core: Avoid calling dm_scan_fdt_dev() with of-platdata
We cannot call dm_scan_fdt_dev() with of-platdata since there is no device
tree. Fix this with an #if check.

Fixes: 3be9a37 (dm: syscon: scan sub-nodes of the syscon node)
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:16 +09:00
Wenyou.Yang@microchip.com
722b150e6f mmc: gen_atmel_mci: Fix wrong arguments used of bind()
The bind() method is called before the device is probed and so the
device has no private data, should use the platform data, and set up
a new struct to hold the mmc and cfg members.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:12 +09:00
Marek Vasut
8cd46cba53 mmc: sd_sdhi: Enable clock using clock framework
Since we now have clock driver for the RCar Gen3 , add support for
enabling the clock into the SH SDHI driver to prevent hacks in the
board files.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-17 14:38:18 +09:00
Marek Vasut
a3f0a7d5b5 mmc: sh_sdhi: Fix the ACMD handling
The command handling in this driver is awful, esp. because the driver
depends on command numbers to determine whether this is APPCMD or not.
Also, handling of command RSP response types is totally wrong.

This patch at least plucks out some of the custom command encoding and
fixes the APPCMD handling. The RSP handling still needs work, yet that
might not be needed as it turns out the uniphier-sd.c driver is in much
better shape and supports the same IP, so we might be able to just drop
this driver in favor of the uniphier one.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-17 14:38:02 +09:00
Marek Vasut
d1c18ca110 mmc: sh_sdhi: Add DM and DT probing support
Add MMC DM and DT probing support into the SH SDHI driver.
This patch abstracts out the common bits of the send command
and set ios functions, so they can be used both by DM and non
DM setups and adds the DM probe support.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-17 14:37:45 +09:00
Marek Vasut
ac5efc358b mmc: uniphier-sd: Fix long response processing
The long response entry 0..3 LSByte comes from the next response
register MSByte, not from the next response register LSByte. Fix
this to make the driver report correct values in response 136 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-17 14:36:05 +09:00
Tom Rini
336aee50cf Merge git://git.denx.de/u-boot-tegra 2017-08-16 18:12:58 -04:00
Tom Rini
ceff355a5f Merge git://git.denx.de/u-boot-sunxi
Update A20-OLinuXino-Lime2-eMMC_defconfig to include CONFIG_SCSI

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-16 18:12:40 -04:00
Tom Rini
470135be27 Merge git://www.denx.de/git/u-boot-imx
Update pfla02 for setenv changes and PHYLIB/etc migration to Kconfig.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-16 18:12:00 -04:00
Tom Rini
390194d43f Merge git://git.denx.de/u-boot-spi 2017-08-16 18:07:15 -04:00
Bin Meng
294f2050c4 sf: Preserve QE bit when clearing BP# bits for Macronix flash
On some flash (like Macronix), QE (quad enable) bit is in the same
status register as BP# bits, and we need preserve its original value
during a reboot cycle as this is required by some platforms (like
Intel ICH SPI controller working under descriptor mode).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
[Refined code for readability]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-08-16 18:21:50 +05:30
Simon Glass
c595199194 env: Adjust the load() method to return an error
The load() methods have inconsistent behaviour on error. Some of them load
an empty default environment. Some load an environment containing an error
message. Others do nothing.

As a step in the right direction, have the method return an error code.
Then the caller could handle this itself in a consistent way.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:31:24 -04:00
Simon Glass
21f639446d env: Adjust the get_char() method to return an int
In principle this can fail, e.g. if the index is out of range. Adjust the
driver signature to allow returning an error code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-16 08:31:24 -04:00
Simon Glass
723806cc5b env: Rename some other getenv()-related functions
We are now using an env_ prefix for environment functions. Rename these
other functions as well, for consistency:

   getenv_vlan()
   getenv_bootm_size()
   getenv_bootm_low()
   getenv_bootm_mapsize()
   env_get_default()

Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:31:11 -04:00
Simon Glass
35affd7a2f env: Rename eth_getenv_enetaddr() to eth_env_get_enetaddr()
Rename this function for consistency with env_get().

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:30:44 -04:00
Simon Glass
bfebc8c965 env: Rename getenv_hex(), getenv_yesno(), getenv_ulong()
We are now using an env_ prefix for environment functions. Rename these
for consistency. Also add function comments in common.h.

Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:30:32 -04:00
Simon Glass
00caae6d47 env: Rename getenv/_f() to env_get()
We are now using an env_ prefix for environment functions. Rename these
two functions for consistency. Also add function comments in common.h.

Quite a few places use getenv() in a condition context, provoking a
warning from checkpatch. These are fixed up in this patch also.

Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:30:24 -04:00
Simon Glass
fd1e959e91 env: Rename eth_setenv_enetaddr() to eth_env_set_enetaddr()
Rename this function for consistency with env_set().

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:23:56 -04:00
Simon Glass
018f530323 env: Rename common functions related to setenv()
We are now using an env_ prefix for environment functions. Rename these
commonly used functions, for consistency. Also add function comments in
common.h.

Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:23:32 -04:00
Simon Glass
382bee57f1 env: Rename setenv() to env_set()
We are now using an env_ prefix for environment functions. Rename setenv()
for consistency. Also add function comments in common.h.

Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:22:18 -04:00
Peng Fan
e872f27a02 imx: mx7: fix build warning when CONFIG_IMX_RDC not enabled
Fix build warning when CONFIG_IMX_RDC not defined in defconfig.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
2017-08-16 12:43:09 +02:00
Peng Fan
9402cafb23 imx: mx6sl: simplify code using setbits_le32
Simplify code by removing set_preclk_from_osc with directly setbits_le32.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
2017-08-16 12:43:09 +02:00
Peng Fan
7236297aee imx: mx6sx: select OSC as uart's clk parent
As M4 is sourcing UART clk from OSC, to make UART work
when M4 is enabled, need to select OSC as clk parent,
24M OSC is enough for debug UART in uboot.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
2017-08-16 12:43:04 +02:00
Peng Fan
79a57b5ae1 imx: mx6: soc: fix mx6sll settings
There is not LDO_SOC/PU/ARM/MMDC1 on i.MX6SLL, also no need to gate/ungate
all PFDs to make PFD working.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
2017-08-16 11:56:22 +02:00
Peng Fan
3d3598d0f6 imx: mx6: select ARM_ERRATA_845369
Select ARM_ERRATA_845369 for i.MX6DQ/DL/QP.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-08-16 11:51:00 +02:00
Peng Fan
11d94319c3 arm: Implement workaround for Cortex-A9 errata 845369
Under very rare timing circumstances, transitioning into streaming
mode might create a data corruption. Present on Two or more processors
or 1 core with ACP, all revisions. This erratum can be worked round
by setting bit[22] of the undocumented Diagnostic Control Register to 1.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-08-16 11:50:51 +02:00
Peng Fan
91435cd40d ARM: i.MX6: exclude the ARM errata from i.MX6 UP system
The ARM errata 751472, 794072, 761320 only applied
to the following configuration:

This erratum affects configurations with either:
- One processor if the ACP is present
- Two or more processors

i.MX6 family does not have the ACP and thus only the MPCore system
will be impacted, which are the i.MX6DQ, i.MX6DL, and i.MX6QP.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
2017-08-16 11:50:40 +02:00
Sébastien Szymanski
0c7c6fb764 imx: imx6ull: correct get_cpu_speed_grade_hz
i.MX6ULL has different speed grades than i.MX6UL.

Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
2017-08-16 11:45:10 +02:00
Sébastien Szymanski
44e670532d imx: imx6ul: correct get_cpu_speed_grade_hz on 696MHz SoCs
Return the correct value when the speed grade is 696MHz.

Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
2017-08-16 11:44:57 +02:00
Breno Lima
6efb613373 mx6sabreauto: Fix IOMUXC_GPR6 and IOMUXC_GPR7 values
The IPU AXI QoS for the i.MX6QP and i.MX6DP processors have to be set as
commented in the code:
/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */

Set IOMUXC_GPR6 and IOMUXC_GPR7 to 0x77177717 instead of 0x007F007F.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
2017-08-16 11:44:18 +02:00
Breno Lima
a500a33115 mx6sabresd: Fix IOMUXC_GPR6 and IOMUXC_GPR7 values
The IPU AXI QoS for the i.MX6QP and i.MX6DP processors have to be set as
commented in the code:
/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */

Set IOMUXC_GPR6 and IOMUXC_GPR7 to 0x77177717 instead of 0x007F007F.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
2017-08-16 11:43:15 +02:00
Anatolij Gustschin
ff3a5fc46d imx6: clock: correct comment for PLL_VIDEO
This appear to be a copy-paste error, clean it up.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-08-16 11:38:27 +02:00
Anatolij Gustschin
557b9b7250 imx6: use SION macro in SDn_CMD mux mode bitfield arguments
Select SION by appropriate macro instead of constant.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-08-16 11:36:05 +02:00
Simon Glass
01510091de env: Drop saveenv() in favour of env_save()
Use the env_save() function directly now that there is only one
implementation of saveenv().

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Denk <wd@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 20:50:30 -04:00
Simon Glass
310fb14b26 env: Drop env_relocate_spec() in favour of env_load()
This is a strange name for a function that loads the environment. There is
now only one implementation of this function, so use the new env_load()
function directly instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 20:50:29 -04:00
Simon Glass
a69d0f60e5 env: Drop env_get_char_spec()
We only have a single implementation of this function now and it is called
env_get_char(). Drop the old function and the weak version.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-15 20:50:29 -04:00
Simon Glass
6eeae42469 env: Drop env_init_new()
Now that env_init() is only defined once we can drop the env_init_new()
name and just use env_init().

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 20:50:29 -04:00
Simon Glass
98b5755fb0 env: Drop unused env_ptr variables
This variable is declared as a global in most environment location
drivers. But it is not used outside the drivers and most of the
declarations are unnecessary.

Also some drivers call free() on env_ptr which seems wrong since it is
not in the heap.

Drop the variable where possible, and all calls to free().

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 20:50:28 -04:00
Simon Glass
ac358beb85 env: Drop the env_name_spec global
Add a name to the driver and use that instead of the global variable
declared by each driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 20:50:28 -04:00
Simon Glass
7938822a6b env: Drop common init() functions
Most of the init() implementations just use the default environment.
Adjust env_init_new() to do this automatically, and drop the redundant
code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 20:50:27 -04:00
Simon Glass
e5bce247b0 env: Switch over to use environment location drivers
Move over to use a the master implementation of the location drivers, with
each method calling out to the appropriate driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 20:50:27 -04:00
Simon Glass
c9d728dd33 env: Add a new implementation of environment access
We plan to move to a environment access via drivers for each location
where the environment can be stored. Add an implementation for this. So
far it is not used, but will be pressed into service in a future patch.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-15 20:50:26 -04:00
Simon Glass
c1c3fe2307 env: Convert CONFIG_ENV_IS_IN... to a choice
At present we support multiple environment drivers but there is not way to
select between them at run time. Also settings related to the position and
size of the environment area are global (i.e. apply to all locations).

Until these limitations are removed we cannot really support more than one
environment location. Adjust the location to be a choice so that only one
can be selected. By default the environment is 'nowhere', meaning that the
environment exists only in memory and cannot be saved.

Also expand the help for the 'nowhere' option and move it to the top since
it is the default.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Move all of the imply logic to default X if Y so it works again]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-15 20:50:01 -04:00
Marcel Ziswiler
33848eb53e apalis_t30/tk1, colibri_t20/t30: fix i2c bus frequencies
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2017-08-15 14:51:18 -07:00
Marcel Ziswiler
8b733af831 apalis-tk1: remove duplicate hdmi_ddc device tree node
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2017-08-15 14:51:18 -07:00
Marcel Ziswiler
ceef960812 dm: tegra: move apalis t30/tk1, colibri t20/t30 to livetree
Change these board to use a live device tree after relocation.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2017-08-15 14:51:18 -07:00
Marcel Ziswiler
9a50b6fc81 apalis_t30: fix usb otg power enable
Fix USB OTG power enable aka USBO1_EN which on Apalis T30 is connected
to the T30 ball GEN2_I2C_SCL.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2017-08-15 14:51:18 -07:00
Simon Glass
4415f1d1f1 env: Create a location driver for each location
Set up a location driver for each supported environment location. At
present this just points to the global functions and is not used. A
later patch will switch this over to use private functions in each driver.

There are several special cases here in various drivers to handle
peculiarities of certain boards:

1. Some boards define CONFIG_ENV_IS_IN_FAT and CONFIG_SPL_ENV_SUPPORT but
do not actually load the environment in SPL. The env load code was
optimised out before but with the driver, it is not. Therefore a special
case is added to env/fat.c. The correct fix (depending on board testing
might be to disable CONFIG_SPL_ENV_SUPPORT.

2. A similar situations happens with CONFIG_ENV_IS_IN_FLASH. Some boards
do not actually load the environment in SPL, so to reduce code size we
need to drop that code. A similar fix may be possible with these boards,
or it may be possible to adjust the environment CONFIG settings.

Added to the above is that the CONFIG_SPL_ENV_SUPPORT option does not
apply when the environment is in flash.

Obviously the above has been discovered through painful and time-consuming
trial and error. Hopefully board maintainers can take a look and figure
out what is actually needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-15 08:18:53 -04:00
Simon Glass
42a8180d19 env: Rename nand env_location to nand_env_location
We want to use this name for all environment drivers. Update the nand
driver to use a more specific name.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 08:18:51 -04:00
Simon Glass
203e94f6c9 env: Add an enum for environment state
At present we have three states for the environment, numbered 0, 1 and 2.
Add an enum to record this to avoid open-coded values.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 08:18:51 -04:00
Simon Glass
75de597d2d env: common: Drop env_get_char_memory()
This function is the same as env_get_char_spec() apart from dropping the
brackets. Drop the brackets from env_get_char_spec() and use that instead
of env_get_char_memory().

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 08:18:47 -04:00
Simon Glass
81a4dea228 env: common: Drop env_get_char_init()
This function does nothing but call env_get_char_spec(). Drop it and
adjust its only caller.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 08:18:47 -04:00
Simon Glass
5fc5254084 env: common: Factor out the common env_valid check
The check for gd->env_valid is used in both the 'if' and 'else' part of
env_get_char(). Move it into that function instead for simplicity. Drop
that code from the two leaf functions.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 08:18:46 -04:00
Simon Glass
0219fb61c1 env: common: Drop env_get_addr()
This function is not used anywhere other than env_get_char(). Move the
code into that function.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-15 08:18:46 -04:00
Simon Glass
bcdfb8d5a5 env: common: Make env_get_addr/get_char_memory() static
These functions are not used outside this file. Make them static and order
them to avoid forward declarations.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 08:18:46 -04:00
Simon Glass
91d3aa05d0 env: Use tabs in ENV_IS_IN_FAT
Tidy up the formatting of this option.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-15 08:18:46 -04:00
Simon Glass
0649cd0d49 Move environment files from common/ to env/
About a quarter of the files in common/ relate to the environment. It
seems better to put these into their own subdirectory and remove the
prefix.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 08:18:45 -04:00
Simon Glass
ec74f5f9c3 Makefile: Rename 'env' target to 'environ'
This target stops us using 'env' as a subdirectory. It is not mentioned in
the help so seems to be an internal target. Rename it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 08:18:42 -04:00
Jagan Teki
585bf8ae6f sun50i: a64: Add A64-OLinuXino initial support
OLimex A64-OLinuXino is an open-source hardware board
using the Allwinner A64 SOC.

OLimex A64-OLinuXino has
- A64 Quad-core Cortex-A53 64bit
- 1GB or 2GB RAM DDR3L @ 672Mhz
- microSD slot and 4/8/16GB eMMC
- Debug TTL UART
- HDMI
- LCD
- IR receiver
- 5V DC power supply

Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-08-15 11:30:59 +05:30
Jagan Teki
f322657204 sun50i: a64: Add initial NanoPi A64 support
NanoPi A64 is a new board of high performance with low cost
designed by FriendlyElec., using the Allwinner A64 SOC.

Nanopi A64 features
- Allwinner A64, 64-bit Quad-core Cortex-A53@648MHz to 1.152GHz, DVFS
- 1GB DDR3 RAM
- MicroSD
- Gigabit Ethernet (RTL8211E)
- Wi-Fi 802.11b/g/n
- IR receiver
- Audio In/Out
- Video In/Out
- Serial Debug Port
- microUSB 5V 2A DC power-supply

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-08-15 11:30:19 +05:30
xypron.glpk@gmx.de
a44bffcc95 efi_loader: use EFI_PAGE_SIZE instead of 4096
We should use constant EFI_PAGE_SIZE instead of 4096 where the
coding relies on 4096 being EFI_PAGE_SIZE.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-08-12 14:06:23 +02:00
xypron.glpk@gmx.de
aee4f06dff efi_loader: use EFI_PAGE_MASK instead of EFI_PAGE_SIZE - 1
We should be consistent in the way we calculate page sizes.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-08-12 14:05:45 +02:00
Jagan Teki
7e4bef711e sun50i: a64: Sync Linux [oe]hci0 nodes
Synced ohci0 and ehci0 nodes from Linux for sun50i-a64.dtsi

Here is the Linux last merge tag details:
Merge: 0e91f43d e5770b7
Author: Stephen Rothwell <sfr@canb.auug.org.au>
Date:   Fri Jun 9 14:59:55 2017 +1000

    Merge remote-tracking branch 'staging/staging-next'

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-08-11 21:51:43 +05:30
Rob Clark
3d9880784e efi_loader: GOP fix for no display
uclass_first_device() returns 0 if there is no device, but error if
there is a device that failed to probe.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-08-11 13:49:23 +02:00
Icenowy Zheng
a8df97d0da sunxi: add MACPWR in Orange Pi PC2 defconfig
The Ethernet function is enabled in the Orange Pi PC2 device tree and
defconfig, however, CONFIG_MACPWR is not properly set, which left the
PHY being disabled when booting, which makes the Ethernet function not
usable.

Add the proper value of this option in the PC2 defconfig.

Fixes: e7bd15ea15 ("sunxi: Add OrangePi PC 2 initial support")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-11 15:53:27 +05:30
Icenowy Zheng
e37a1b17e7 sunxi: switch PRCM to non-secure on H3/H5 SoCs
The PRCM of H3/H5 SoCs have a secure/non-secure switch, which controls
the access to some clock/power related registers in PRCM.

Current Linux kernel will access the CPUS (AR100) clock in the PRCM
block, so the PRCM should be switched to non-secure.

Add code to switch the PRCM to non-secure.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-11 15:49:39 +05:30
Icenowy Zheng
39858b12cc sunxi: add PRCM secure switch register definition
Some new Allwinner SoCs' PRCM has a secure switch register, which
controls the access to some clock and power registers in PRCM block.

Add the definition of this register and its bits in the PRCM header
file.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Tested-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-11 15:49:39 +05:30
Clément Bœsch
8792a64d87 sunxi: reduce Orange Pi Zero DRAM clock speed
Using `fel-boot-lima-memtester-on-orange-pi-pc 672` on an Orange Pi
without heatsink results in the following error after a few minutes:
  WRITE FAILURE: 0x00200000 != 0xffdfffff at offset 0x0137f47c (bitflip).

Also, the constructor repository (github/orangepi-xunlong) seems to
contain that 624 Mhz clock speed in its u-boot fork. It may be that 672
Mhz is the advertized overclocked speed.

According to http://linux-sunxi.org/Orange_Pi_PC#DRAM_clock_speed_limit
it may be worth decreasing that value with other Orange Pi boards.

See also e7d6aa0b74.

Signed-off-by: Clément Bœsch <u@pkh.me>
[Add s-o-b line]
Signed-off-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-11 15:43:44 +05:30
Olliver Schinagl
335d30050b sun7i: Add support for Olimex A20-OLinuXino-LIME2-eMMC
This patch adds support for the Olimex OLinuXino Lime2 with eMMC flash
storage.
https://www.olimex.com/Products/OLinuXino/A20/A20-OLinuXino-LIME2-eMMC/

It is a assembly variant of the regular Lime2 but featuring eMMC for
storage.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-11 15:16:39 +05:30
Emmanuel Vadot
fb7fe04da2 ARM: dts: sunxi: Change node name for pwrseq pin on Olinuxino-lime2-emmc
The node name for the power seq pin is mmc2@0 like the mmc2_pins_a one.
This makes the original node (mmc2_pins_a) scrapped out of the dtb and
result in a unusable eMMC if U-Boot didn't configured the pins to the
correct functions.

Signed-off-by: Emmanuel Vadot <manu@bidouilliste.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-11 15:16:39 +05:30
Rob Clark
796a78cbe5 efi_loader: LocateHandle should return EFI_NOT_FOUND if none found
Spotted this debugging OpenBSD's bootloader in qemu.  (Wouldn't really
fix anything, the problem was not having any disks, but we should
probably return the correct error code.)

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-08-11 11:08:33 +02:00
xypron.glpk@gmx.de
ebf199b92f efi_loader: attribute EFIAPI of efi_locate handle()
efi_locate_handle is called internally so it should not be
marked as EFIAPI.

The external function is efi_locate_handle_ext.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-08-11 10:57:10 +02:00
Wenyou.Yang@microchip.com
8fc2faefdd mtd: spi: sf_dataflash: Add print message while erase error
Add the print message to tell us why the erase operation doesn't work.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-08 12:34:27 +05:30
Bin Meng
ac6777b1e3 sf: Add Macronix MX25U6435F device parameters
This adds support for Macronix flash MX25U6435F (device ID 0xc22537).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-08 12:26:05 +05:30
Stefano Babic
83605d37b0 mx6: Add support for Phytec pfla02 (NAND)
Add support for Phytec pfla02, equipped with NAND.

CPU:   Freescale i.MX6Q rev1.5 996 MHz (running at 792 MHz)
CPU:   Automotive temperature grade (-40C to 125C) at 31C
Reset cause: POR
I2C:   ready
DRAM:  1 GiB
NAND:  2048 MiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
SF: Detected n25q128 with page size 256 Bytes, erase size 64 KiB, total
16 MiB
In:    serial
Out:   serial
Err:   serial
Net:   FEC [PRIME]
Hit any key to stop autoboot:  0

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Stefan Christ <s.christ@phytec.de>
CC: Stefan Müller-Klieser <S.Mueller-Klieser@phytec.de>
CC: Christian Hemp <C.Hemp@phytec.de>
2017-08-02 11:45:27 +02:00
Vagrant Cascadian
3b22599e1a arm: imx: Enable booting from SATA on wandboard.
Enable booting from SATA on the wandboard.

Sata support was already enabled, but distro_bootcmd is not configured
to boot from it.

Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-28 13:44:54 +02:00
Lothar Waßmann
cb5761f774 net: fec_mxc: adjust prototype of fec_get_miibus() for DM_ETH
commit 306dd7dabd ("net: fec_mxc: fix PHY initialization bug with CONFIG_DM_ETH")
has broken the build of the fec_mxc driver with CONFIG_DM_ETH
enabled because it changed the parameters passed to *fec_get_miibus()
without changing the functions prototype.

This patch fixes up the prototype of fec_get_miibus() for the DM_ETH case.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
2017-07-28 13:41:49 +02:00
1560 changed files with 9532 additions and 6767 deletions

View File

@@ -380,6 +380,8 @@ source "disk/Kconfig"
source "dts/Kconfig"
source "env/Kconfig"
source "net/Kconfig"
source "drivers/Kconfig"

View File

@@ -5,7 +5,7 @@
VERSION = 2017
PATCHLEVEL = 09
SUBLEVEL =
EXTRAVERSION = -rc2
EXTRAVERSION = -rc3
NAME =
# *DOCUMENTATION*
@@ -690,6 +690,7 @@ libs-y += drivers/usb/phy/
libs-y += drivers/usb/ulpi/
libs-y += cmd/
libs-y += common/
libs-y += env/
libs-$(CONFIG_API) += api/
libs-$(CONFIG_HAS_POST) += post/
libs-y += test/
@@ -1378,7 +1379,7 @@ $(timestamp_h): $(srctree)/Makefile FORCE
$(call filechk,timestamp.h)
checkbinman: tools
@if ! ( echo 'import libfdt' | ( PYTHONPATH=tools python )); then \
@if ! ( echo 'import libfdt' | ( PYTHONPATH=tools $(PYTHON) )); then \
echo >&2; \
echo >&2 '*** binman needs the Python libfdt library.'; \
echo >&2 '*** Either install it on your system, or try:'; \
@@ -1464,14 +1465,14 @@ checkarmreloc: u-boot
false; \
fi
env: scripts_basic
environ: scripts_basic
$(Q)$(MAKE) $(build)=tools/$@
tools-only: scripts_basic $(version_h) $(timestamp_h)
$(Q)$(MAKE) $(build)=tools
tools-all: export HOST_TOOLS_ALL=y
tools-all: env tools ;
tools-all: environ tools ;
cross_tools: export CROSS_BUILD_TOOLS=y
cross_tools: tools ;

8
README
View File

@@ -404,12 +404,6 @@ The following options need to be configured:
supported, core will start to execute uboot when wakes up.
- Generic CPU options:
CONFIG_SYS_GENERIC_GLOBAL_DATA
Defines global data is initialized in generic board board_init_f().
If this macro is defined, global data is created and cleared in
generic board board_init_f(). Without this macro, architecture/board
should initialize global data before calling board_init_f().
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
Defines the endianess of the CPU. Implementation of those
@@ -3286,7 +3280,7 @@ but it can not erase, write this NOR flash by SRIO or PCIE interface.
Please note that the environment is read-only until the monitor
has been relocated to RAM and a RAM copy of the environment has been
created; also, when using EEPROM you will have to use getenv_f()
created; also, when using EEPROM you will have to use env_get_f()
until then to read environment variables.
The environment is protected by a CRC32 checksum. Before the monitor

View File

@@ -458,7 +458,7 @@ static int API_env_get(va_list ap)
if ((value = (char **)va_arg(ap, uintptr_t)) == NULL)
return API_EINVAL;
*value = getenv(name);
*value = env_get(name);
return 0;
}
@@ -481,7 +481,7 @@ static int API_env_set(va_list ap)
if ((value = (char *)va_arg(ap, uintptr_t)) == NULL)
return API_EINVAL;
setenv(name, value);
env_set(name, value);
return 0;
}
@@ -663,7 +663,7 @@ void api_init(void)
return;
}
setenv_hex("api_address", (unsigned long)sig);
env_set_hex("api_address", (unsigned long)sig);
debugf("API sig @ 0x%lX\n", (unsigned long)sig);
memcpy(sig->magic, API_SIG_MAGIC, 8);
sig->version = API_SIG_VERSION;

View File

@@ -112,6 +112,7 @@ config X86
imply CMD_GETTIME
imply CMD_IO
imply CMD_IRQ
imply CMD_PCI
imply CMD_SF_TEST
imply CMD_ZBOOT

View File

@@ -85,7 +85,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
r2 = (unsigned int)images->ft_addr;
} else {
r0 = 1;
r2 = (unsigned int)getenv("bootargs");
r2 = (unsigned int)env_get("bootargs");
}
smp_set_core_boot_addr((unsigned long)kernel_entry, -1);

View File

@@ -97,6 +97,9 @@ config ARM_ERRATA_833069
config ARM_ERRATA_833471
bool
config ARM_ERRATA_845369
bool
config ARM_ERRATA_852421
bool
@@ -493,7 +496,6 @@ config ARCH_BCM283X
select DM_GPIO
select OF_CONTROL
imply FAT_WRITE
imply ENV_IS_IN_FAT
config TARGET_VEXPRESS_CA15_TC2
bool "Support vexpress_ca15_tc2"
@@ -726,7 +728,6 @@ config ARCH_ZYNQ
select DM_GPIO
select SPL_DM if SPL
select DM_MMC
select DM_MMC_OPS
select DM_SPI
select DM_SERIAL
select DM_SPI_FLASH
@@ -1020,7 +1021,6 @@ config TARGET_COLIBRI_PXA270
config ARCH_UNIPHIER
bool "Socionext UniPhier SoCs"
select BOARD_LATE_INIT
select CLK_UNIPHIER
select DM
select DM_GPIO
select DM_I2C
@@ -1039,7 +1039,6 @@ config ARCH_UNIPHIER
select SPL_PINCTRL if SPL
select SUPPORT_SPL
imply FAT_WRITE
imply ENV_IS_IN_MMC
help
Support for UniPhier SoC family developed by Socionext Inc.
(formerly, System LSI Business Division of Panasonic Corporation)
@@ -1075,7 +1074,6 @@ config ARCH_ROCKCHIP
select DM_GPIO
select DM_I2C
select DM_MMC
select DM_MMC_OPS
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH

View File

@@ -16,6 +16,8 @@ obj-$(CONFIG_DDR_MT47H64M16) += spr600_mt47h64m16_3_333_cl5_psync.o
obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o
obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_37e_166_cl4_sync.o
obj-$(CONFIG_DDR_MT47H128M8) += spr600_mt47h128m8_3_266_cl5_async.o
else
obj-y += spr_misc.o spr_lowlevel_init.o
endif
extra-$(CONFIG_SPL_BUILD) := start.o

View File

@@ -84,7 +84,7 @@ int print_cpuinfo(void)
}
#endif
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_ECC_BCH)
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_ECC_BCH) && defined(CONFIG_NAND_FSMC)
static int do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
{

View File

@@ -53,15 +53,15 @@ int misc_init_r(void)
#if defined(CONFIG_CMD_NET)
uchar mac_id[6];
if (!eth_getenv_enetaddr("ethaddr", mac_id) && !i2c_read_mac(mac_id))
eth_setenv_enetaddr("ethaddr", mac_id);
if (!eth_env_get_enetaddr("ethaddr", mac_id) && !i2c_read_mac(mac_id))
eth_env_set_enetaddr("ethaddr", mac_id);
#endif
setenv("verify", "n");
env_set("verify", "n");
#if defined(CONFIG_SPEAR_USBTTY)
setenv("stdin", "usbtty");
setenv("stdout", "usbtty");
setenv("stderr", "usbtty");
env_set("stdin", "usbtty");
env_set("stdout", "usbtty");
env_set("stderr", "usbtty");
#ifndef CONFIG_SYS_NO_DCACHE
dcache_enable();

View File

@@ -187,6 +187,12 @@ ENTRY(cpu_init_cp15)
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_845369
mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
orr r0, r0, #1 << 22 @ set bit #22
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
#endif
mov r5, lr @ Store my Caller
mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR)
mov r3, r1, lsr #20 @ get variant field

View File

@@ -329,7 +329,7 @@ int arch_misc_init(void)
strcpy(soc, "vf");
strcat(soc, soc_type);
setenv("soc", soc);
env_set("soc", soc);
return 0;
}

View File

@@ -345,11 +345,38 @@ static void fdt_fixup_msi(void *blob)
}
#endif
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
/* Remove JR node used by SEC firmware */
void fdt_fixup_remove_jr(void *blob)
{
int jr_node, addr_cells, len;
int crypto_node = fdt_path_offset(blob, "crypto");
u64 jr_offset, used_jr;
fdt32_t *reg;
used_jr = sec_firmware_used_jobring_offset();
fdt_support_default_count_cells(blob, crypto_node, &addr_cells, NULL);
jr_node = fdt_node_offset_by_compatible(blob, crypto_node,
"fsl,sec-v4.0-job-ring");
while (jr_node != -FDT_ERR_NOTFOUND) {
reg = (fdt32_t *)fdt_getprop(blob, jr_node, "reg", &len);
jr_offset = fdt_read_number(reg, addr_cells);
if (jr_offset == used_jr) {
fdt_del_node(blob, jr_node);
break;
}
jr_node = fdt_node_offset_by_compatible(blob, jr_node,
"fsl,sec-v4.0-job-ring");
}
}
#endif
void ft_cpu_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_FSL_LSCH2
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
unsigned int svr = in_be32(&gur->svr);
unsigned int svr = gur_in32(&gur->svr);
/* delete crypto node if not on an E-processor */
if (!IS_E_PROCESSOR(svr))
@@ -358,11 +385,15 @@ void ft_cpu_setup(void *blob, bd_t *bd)
else {
ccsr_sec_t __iomem *sec;
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
if (fdt_fixup_kaslr(blob))
fdt_fixup_remove_jr(blob);
#endif
sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
}
#endif
#endif
#ifdef CONFIG_MP
ft_fixup_cpu(blob);

View File

@@ -95,7 +95,7 @@ static void erratum_a008514(void)
static unsigned long get_internval_val_mhz(void)
{
char *interval = getenv(PLATFORM_CYCLE_ENV_VAR);
char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
/*
* interval is the number of platform cycles(MHz) between
* wake up events generated by EPU.

View File

@@ -231,6 +231,59 @@ unsigned int sec_firmware_support_psci_version(void)
}
#endif
/*
* Check with sec_firmware if it supports random number generation
* via HW RNG
*
* The return value will be true if it is supported
*/
bool sec_firmware_support_hwrng(void)
{
uint8_t rand[8];
if (sec_firmware_addr & SEC_FIRMWARE_RUNNING) {
if (!sec_firmware_get_random(rand, 8))
return true;
}
return false;
}
/*
* sec_firmware_get_random - Get a random number from SEC Firmware
* @rand: random number buffer to be filled
* @bytes: Number of bytes of random number to be supported
* @eret: -1 in case of error, 0 for success
*/
int sec_firmware_get_random(uint8_t *rand, int bytes)
{
unsigned long long num;
struct pt_regs regs;
int param1;
if (!bytes || bytes > 8) {
printf("Max Random bytes genration supported is 8\n");
return -1;
}
#define SIP_RNG_64 0xC200FF11
regs.regs[0] = SIP_RNG_64;
if (bytes <= 4)
param1 = 0;
else
param1 = 1;
regs.regs[1] = param1;
smc_call(&regs);
if (regs.regs[0])
return -1;
num = regs.regs[1];
memcpy(rand, &num, bytes);
return 0;
}
/*
* sec_firmware_init - Initialize the SEC Firmware
* @sec_firmware_img: the SEC Firmware image address
@@ -278,3 +331,49 @@ int sec_firmware_init(const void *sec_firmware_img,
return 0;
}
/*
* fdt_fix_kaslr - Add kalsr-seed node in Device tree
* @fdt: Device tree
* @eret: 0 in case of error, 1 for success
*/
int fdt_fixup_kaslr(void *fdt)
{
int nodeoffset;
int err, ret = 0;
u8 rand[8];
#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT)
/* Check if random seed generation is supported */
if (sec_firmware_support_hwrng() == false)
return 0;
ret = sec_firmware_get_random(rand, 8);
if (ret < 0) {
printf("WARNING: No random number to set kaslr-seed\n");
return 0;
}
err = fdt_check_header(fdt);
if (err < 0) {
printf("fdt_chosen: %s\n", fdt_strerror(err));
return 0;
}
/* find or create "/chosen" node. */
nodeoffset = fdt_find_or_add_subnode(fdt, 0, "chosen");
if (nodeoffset < 0)
return 0;
err = fdt_setprop(fdt, nodeoffset, "kaslr-seed", rand,
sizeof(rand));
if (err < 0) {
printf("WARNING: can't set kaslr-seed %s.\n",
fdt_strerror(err));
return 0;
}
ret = 1;
#endif
return ret;
}

View File

@@ -119,8 +119,6 @@ dtb-$(CONFIG_ARCH_UNIPHIER_PXS2) += \
uniphier-pxs2-vodka.dtb
dtb-$(CONFIG_ARCH_UNIPHIER_PXS3) += \
uniphier-pxs3-ref.dtb
dtb-$(CONFIG_ARCH_UNIPHIER_SLD3) += \
uniphier-sld3-ref.dtb
dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \
uniphier-sld8-ref.dtb
@@ -336,6 +334,8 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \
sun50i-h5-orangepi-zero-plus2.dtb
dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-bananapi-m64.dtb \
sun50i-a64-nanopi-a64.dtb \
sun50i-a64-olinuxino.dtb \
sun50i-a64-orangepi-win.dtb \
sun50i-a64-pine64-plus.dtb \
sun50i-a64-pine64.dtb
@@ -357,6 +357,7 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
imx6sll-evk.dtb \
imx6dl-icore.dtb \
imx6dl-icore-rqs.dtb \
imx6q-cm-fx6.dtb \
imx6q-icore.dtb \
imx6q-icore-rqs.dtb \
imx6q-logicpd.dtb \

View File

@@ -315,7 +315,6 @@
&edma 25>;
dma-names = "tx", "rx";
interrupts = <64>;
interrupt-parent = <&intc>;
reg = <0x48060000 0x1000>;
status = "disabled";
};
@@ -328,7 +327,6 @@
&edma 3>;
dma-names = "tx", "rx";
interrupts = <28>;
interrupt-parent = <&intc>;
reg = <0x481d8000 0x1000>;
status = "disabled";
};
@@ -338,7 +336,6 @@
ti,hwmods = "mmc3";
ti,needs-special-reset;
interrupts = <29>;
interrupt-parent = <&intc>;
reg = <0x47810000 0x1000>;
status = "disabled";
};
@@ -724,7 +721,6 @@
0x4a101200 0x100>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
/*
* c0_rx_thresh_pend
* c0_rx_pend
@@ -787,7 +783,6 @@
lcdc: lcdc@4830e000 {
compatible = "ti,am33xx-tilcdc";
reg = <0x4830e000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <36>;
ti,hwmods = "lcdc";
status = "disabled";
@@ -796,7 +791,6 @@
tscadc: tscadc@44e0d000 {
compatible = "ti,am3359-tscadc";
reg = <0x44e0d000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <16>;
ti,hwmods = "adc_tsc";
status = "disabled";

View File

@@ -0,0 +1,115 @@
/*
* Copyright 2013 CompuLab Ltd.
*
* Author: Valentin Raevsky <valentin@compulab.co.il>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx6q.dtsi"
/ {
model = "CompuLab CM-FX6";
compatible = "compulab,cm-fx6", "fsl,imx6q";
memory {
reg = <0x10000000 0x80000000>;
};
leds {
compatible = "gpio-leds";
heartbeat-led {
label = "Heartbeat";
gpios = <&gpio2 31 0>;
linux,default-trigger = "heartbeat";
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
status = "okay";
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
status = "okay";
};
&iomuxc {
imx6q-cm-fx6 {
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
>;
};
};
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&sata {
status = "okay";
};
&usdhc3 {
status = "okay";
};

View File

@@ -129,6 +129,7 @@
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
u-boot,dm-pre-reloc;
};
extalr_clk: extalr {
@@ -136,6 +137,7 @@
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
u-boot,dm-pre-reloc;
};
/*
@@ -189,6 +191,7 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
u-boot,dm-pre-reloc;
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
@@ -380,6 +383,7 @@
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
u-boot,dm-pre-reloc;
};
rst: reset-controller@e6160000 {

View File

@@ -111,6 +111,7 @@
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
u-boot,dm-pre-reloc;
};
extalr_clk: extalr {
@@ -118,6 +119,7 @@
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
u-boot,dm-pre-reloc;
};
/* External CAN clock - to be overridden by boards that provide it */
@@ -140,6 +142,7 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
u-boot,dm-pre-reloc;
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
@@ -333,6 +336,7 @@
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
u-boot,dm-pre-reloc;
};
rst: reset-controller@e6160000 {

View File

@@ -276,19 +276,3 @@
rx_delay = <0x10>;
status = "okay";
};
&gmac {
phy-supply = <&vcc_phy>;
phy-mode = "rgmii";
clock_in_out = "input";
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>;
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
tx_delay = <0x10>;
rx_delay = <0x10>;
status = "okay";
};

View File

@@ -211,8 +211,8 @@
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
tx_delay = <0x28>;
rx_delay = <0x11>;
tx_delay = <0x33>;
rx_delay = <0x45>;
status = "okay";
};

View File

@@ -632,6 +632,34 @@
status = "disabled";
};
rstc@f8048000 {
compatible = "atmel,sama5d3-rstc";
reg = <0xf8048000 0x10>;
clocks = <&clk32k>;
};
shdwc@f8048010 {
compatible = "atmel,sama5d2-shdwc";
reg = <0xf8048010 0x10>;
clocks = <&clk32k>;
#address-cells = <1>;
#size-cells = <0>;
atmel,wakeup-rtc-timer;
};
pit: timer@f8048030 {
compatible = "atmel,at91sam9260-pit";
reg = <0xf8048030 0x10>;
clocks = <&h32ck>;
};
watchdog@f8048040 {
compatible = "atmel,sama5d4-wdt";
reg = <0xf8048040 0x10>;
clocks = <&clk32k>;
status = "disabled";
};
sckc@f8048050 {
compatible = "atmel,at91sam9x5-sckc";
reg = <0xf8048050 0x4>;

View File

@@ -0,0 +1,115 @@
/*
* Copyright (C) 2017 Jagan Teki <jteki@openedev.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun50i-a64.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "FriendlyARM NanoPi A64";
compatible = "friendlyarm,nanopi-a64", "allwinner,sun50i-a64";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
reg_vcc3v3: vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&ehci0 {
status = "okay";
};
&ehci1 {
status = "okay";
};
/* i2c1 connected with gpio headers like pine64, bananapi */
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "disabled";
};
&i2c1_pins {
bias-pull-up;
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_vcc3v3>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
cd-inverted;
disable-wp;
bus-width = <4>;
status = "okay";
};
&ohci0 {
status = "okay";
};
&ohci1 {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
&usbphy {
status = "okay";
};

View File

@@ -0,0 +1,84 @@
/*
* Copyright (C) 2017 Jagan Teki <jteki@openedev.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun50i-a64.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Olimex A64-Olinuxino";
compatible = "olimex,a64-olinuxino", "allwinner,sun50i-a64";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
reg_vcc3v3: vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_vcc3v3>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
cd-inverted;
disable-wp;
bus-width = <4>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};

View File

@@ -204,6 +204,28 @@
#phy-cells = <1>;
};
ehci0: usb@01c1a000 {
compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
reg = <0x01c1a000 0x100>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI0>,
<&ccu CLK_BUS_EHCI0>,
<&ccu CLK_USB_OHCI0>;
resets = <&ccu RST_BUS_OHCI0>,
<&ccu RST_BUS_EHCI0>;
status = "disabled";
};
ohci0: usb@01c1a400 {
compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
reg = <0x01c1a400 0x100>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI0>,
<&ccu CLK_USB_OHCI0>;
resets = <&ccu RST_BUS_OHCI0>;
status = "disabled";
};
ehci1: usb@01c1b000 {
compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
reg = <0x01c1b000 0x100>;

View File

@@ -56,7 +56,7 @@
};
&pio {
mmc2_pins_nrst: mmc2@0 {
mmc2_pins_nrst: mmc2-rst-pin {
allwinner,pins = "PC16";
allwinner,function = "gpio_out";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;

View File

@@ -1610,17 +1610,13 @@
status = "okay";
};
hdmi_ddc: i2c@7000c400 {
clock-frequency = <100000>;
};
/*
* GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier
* board)
*/
i2c@7000c000 {
status = "okay";
clock-frequency = <100000>;
clock-frequency = <400000>;
pcie-switch@58 {
compatible = "plx,pex8605";
@@ -1639,7 +1635,7 @@
*/
hdmi_ddc: i2c@7000c400 {
status = "okay";
clock-frequency = <100000>;
clock-frequency = <10000>;
};
/*
@@ -1648,7 +1644,7 @@
*/
i2c@7000c500 {
status = "okay";
clock-frequency = <100000>;
clock-frequency = <400000>;
};
/* I2C4 (DDC): unused */

View File

@@ -64,7 +64,7 @@
*/
i2c@7000c000 {
status = "okay";
clock-frequency = <100000>;
clock-frequency = <400000>;
};
/* GEN2_I2C: unused */
@@ -72,7 +72,7 @@
/* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */
i2c@7000c400 {
status = "okay";
clock-frequency = <100000>;
clock-frequency = <10000>;
};
/*

View File

@@ -65,7 +65,7 @@
*/
i2c@7000c000 {
status = "okay";
clock-frequency = <100000>;
clock-frequency = <400000>;
};
/* GEN2_I2C: unused */
@@ -76,13 +76,13 @@
*/
i2c@7000c500 {
status = "okay";
clock-frequency = <100000>;
clock-frequency = <400000>;
};
/* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */
i2c@7000c700 {
status = "okay";
clock-frequency = <100000>;
clock-frequency = <10000>;
};
/*

View File

@@ -33,7 +33,7 @@
*/
i2c@7000c000 {
status = "okay";
clock-frequency = <100000>;
clock-frequency = <400000>;
};
/* GEN2_I2C: unused */
@@ -43,7 +43,7 @@
/* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */
i2c@7000c700 {
status = "okay";
clock-frequency = <100000>;
clock-frequency = <10000>;
};
/*

View File

@@ -426,6 +426,7 @@
compatible = "snps,dwc3";
reg = <0x65a00000 0x10000>;
interrupts = <0 134 4>;
dr_mode = "host";
tx-fifo-resize;
};
};

View File

@@ -587,6 +587,7 @@
compatible = "snps,dwc3";
reg = <0x65a00000 0x10000>;
interrupts = <0 134 4>;
dr_mode = "host";
tx-fifo-resize;
};
};
@@ -604,6 +605,7 @@
compatible = "snps,dwc3";
reg = <0x65c00000 0x10000>;
interrupts = <0 137 4>;
dr_mode = "host";
tx-fifo-resize;
};
};

View File

@@ -598,6 +598,7 @@
compatible = "snps,dwc3";
reg = <0x65a00000 0x10000>;
interrupts = <0 134 4>;
dr_mode = "host";
tx-fifo-resize;
};
};
@@ -615,6 +616,7 @@
compatible = "snps,dwc3";
reg = <0x65c00000 0x10000>;
interrupts = <0 137 4>;
dr_mode = "host";
tx-fifo-resize;
};
};

View File

@@ -610,6 +610,7 @@
compatible = "snps,dwc3";
reg = <0x65a00000 0x10000>;
interrupts = <0 134 4>;
dr_mode = "host";
tx-fifo-resize;
};
};
@@ -627,6 +628,7 @@
compatible = "snps,dwc3";
reg = <0x65c00000 0x10000>;
interrupts = <0 137 4>;
dr_mode = "host";
tx-fifo-resize;
};
};

View File

@@ -1,100 +0,0 @@
/*
* Device Tree Source for UniPhier sLD3 Reference Board
*
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
/include/ "uniphier-sld3.dtsi"
/include/ "uniphier-ref-daughter.dtsi"
/include/ "uniphier-support-card.dtsi"
/ {
model = "UniPhier sLD3 Reference Board";
compatible = "socionext,uniphier-sld3-ref", "socionext,uniphier-sld3";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
serial0 = &serial0;
serial1 = &serial1;
serial2 = &serial2;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
};
memory@8000000 {
device_type = "memory";
reg = <0x80000000 0x20000000
0xc0000000 0x20000000>;
};
};
&ethsc {
interrupts = <0 49 4>;
};
&serial0 {
status = "okay";
};
&serial1 {
status = "okay";
};
&serial2 {
status = "okay";
};
&i2c0 {
status = "okay";
};
&emmc {
status = "okay";
};
&sd {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};
&usb2 {
status = "okay";
};
&usb3 {
status = "okay";
};
/* for U-Boot only */
&serial0 {
u-boot,dm-pre-reloc;
};
&emmc {
u-boot,dm-pre-reloc;
};
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
};
&pinctrl_emmc {
u-boot,dm-pre-reloc;
};

View File

@@ -1,458 +0,0 @@
/*
* Device Tree Source for UniPhier sLD3 SoC
*
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/ {
compatible = "socionext,uniphier-sld3";
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
enable-method = "psci";
next-level-cache = <&l2>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
enable-method = "psci";
next-level-cache = <&l2>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
clocks {
refclk: ref {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24576000>;
};
arm_timer_clk: arm_timer_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupt-parent = <&intc>;
u-boot,dm-pre-reloc;
timer@20000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x20000200 0x20>;
interrupts = <1 11 0x304>;
clocks = <&arm_timer_clk>;
};
timer@20000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x20000600 0x20>;
interrupts = <1 13 0x304>;
clocks = <&arm_timer_clk>;
};
intc: interrupt-controller@20001000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x20001000 0x1000>,
<0x20000100 0x100>;
};
l2: l2-cache@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
interrupts = <0 174 4>, <0 175 4>;
cache-unified;
cache-size = <(512 * 1024)>;
cache-sets = <256>;
cache-line-size = <128>;
cache-level = <2>;
};
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
interrupts = <0 33 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&sys_clk 0>;
clock-frequency = <36864000>;
};
serial1: serial@54006900 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
interrupts = <0 35 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&sys_clk 0>;
clock-frequency = <36864000>;
};
serial2: serial@54006a00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
interrupts = <0 37 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&sys_clk 0>;
clock-frequency = <36864000>;
};
port0x: gpio@55000008 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000008 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port1x: gpio@55000010 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000010 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port2x: gpio@55000018 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000018 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port3x: gpio@55000020 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000020 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port4: gpio@55000028 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000028 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port5x: gpio@55000030 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000030 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port6x: gpio@55000038 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000038 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port7x: gpio@55000040 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000040 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port8x: gpio@55000048 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000048 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port9x: gpio@55000050 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000050 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port10x: gpio@55000058 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000058 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port11x: gpio@55000060 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000060 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port12x: gpio@55000068 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000068 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port13x: gpio@55000070 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000070 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port14x: gpio@55000078 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000078 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port16x: gpio@55000088 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000088 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
i2c0: i2c@58400000 {
compatible = "socionext,uniphier-i2c";
status = "disabled";
reg = <0x58400000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 41 1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&sys_clk 1>;
clock-frequency = <100000>;
};
i2c1: i2c@58480000 {
compatible = "socionext,uniphier-i2c";
status = "disabled";
reg = <0x58480000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 42 1>;
clocks = <&sys_clk 1>;
clock-frequency = <100000>;
};
i2c2: i2c@58500000 {
compatible = "socionext,uniphier-i2c";
status = "disabled";
reg = <0x58500000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 43 1>;
clocks = <&sys_clk 1>;
clock-frequency = <100000>;
};
i2c3: i2c@58580000 {
compatible = "socionext,uniphier-i2c";
status = "disabled";
reg = <0x58580000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 44 1>;
clocks = <&sys_clk 1>;
clock-frequency = <100000>;
};
/* chip-internal connection for DMD */
i2c4: i2c@58600000 {
compatible = "socionext,uniphier-i2c";
reg = <0x58600000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 45 1>;
clocks = <&sys_clk 1>;
clock-frequency = <400000>;
};
system_bus: system-bus@58c00000 {
compatible = "socionext,uniphier-system-bus";
status = "disabled";
reg = <0x58c00000 0x400>;
#address-cells = <2>;
#size-cells = <1>;
};
smpctrl@59801000 {
compatible = "socionext,uniphier-smpctrl";
reg = <0x59801000 0x400>;
};
mioctrl@59810000 {
compatible = "socionext,uniphier-sld3-mioctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
u-boot,dm-pre-reloc;
mio_clk: clock {
compatible = "socionext,uniphier-sld3-mio-clock";
#clock-cells = <1>;
u-boot,dm-pre-reloc;
};
mio_rst: reset {
compatible = "socionext,uniphier-sld3-mio-reset";
#reset-cells = <1>;
};
};
emmc: sdhc@5a400000 {
compatible = "socionext,uniphier-sdhc";
status = "disabled";
reg = <0x5a400000 0x200>;
interrupts = <0 78 4>;
pinctrl-names = "default", "1.8v";
pinctrl-0 = <&pinctrl_emmc>;
pinctrl-1 = <&pinctrl_emmc_1v8>;
clocks = <&mio_clk 1>;
reset-names = "host", "bridge";
resets = <&mio_rst 1>, <&mio_rst 4>;
bus-width = <8>;
non-removable;
cap-mmc-highspeed;
cap-mmc-hw-reset;
};
sd: sdhc@5a500000 {
compatible = "socionext,uniphier-sdhc";
status = "disabled";
reg = <0x5a500000 0x200>;
interrupts = <0 76 4>;
pinctrl-names = "default", "1.8v";
pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_1v8>;
clocks = <&mio_clk 0>;
reset-names = "host", "bridge";
resets = <&mio_rst 0>, <&mio_rst 3>;
bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
};
usb0: usb@5a800100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
interrupts = <0 80 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
<&mio_rst 12>;
};
usb1: usb@5a810100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
interrupts = <0 81 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
<&mio_rst 13>;
};
usb2: usb@5a820100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a820100 0x100>;
interrupts = <0 82 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
<&mio_rst 14>;
};
usb3: usb@5a830100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a830100 0x100>;
interrupts = <0 83 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb3>;
clocks = <&mio_clk 7>, <&mio_clk 11>, <&mio_clk 15>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 11>,
<&mio_rst 15>;
};
soc-glue@5f800000 {
compatible = "socionext,uniphier-sld3-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
u-boot,dm-pre-reloc;
pinctrl: pinctrl {
compatible = "socionext,uniphier-sld3-pinctrl";
u-boot,dm-pre-reloc;
};
};
aidet@f1830000 {
compatible = "simple-mfd", "syscon";
reg = <0xf1830000 0x200>;
};
sysctrl@f1840000 {
compatible = "socionext,uniphier-sld3-sysctrl",
"simple-mfd", "syscon";
reg = <0xf1840000 0x10000>;
sys_clk: clock {
compatible = "socionext,uniphier-sld3-clock";
#clock-cells = <1>;
};
sys_rst: reset {
compatible = "socionext,uniphier-sld3-reset";
#reset-cells = <1>;
};
};
nand: nand@f8000000 {
compatible = "socionext,uniphier-denali-nand-v5a";
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
interrupts = <0 65 4>;
clocks = <&sys_clk 2>;
nand-ecc-strength = <8>;
};
};
};
/include/ "uniphier-pinctrl.dtsi"

View File

@@ -863,7 +863,7 @@ MX6_PAD_DECL(SD3_DAT4__SD3_DATA4, 0x069C, 0x02B4, 0, 0x0000, 0, 0)
MX6_PAD_DECL(SD3_DAT4__UART2_TX_DATA, 0x069C, 0x02B4, 1, 0x0000, 0, 0)
MX6_PAD_DECL(SD3_DAT4__UART2_RX_DATA, 0x069C, 0x02B4, 1, 0x0928, 5, 0)
MX6_PAD_DECL(SD3_DAT4__GPIO7_IO01, 0x069C, 0x02B4, 5, 0x0000, 0, 0)
MX6_PAD_DECL(SD3_CMD__SD3_CMD, 0x06A0, 0x02B8, 16, 0x0000, 0, 0)
MX6_PAD_DECL(SD3_CMD__SD3_CMD, 0x06A0, 0x02B8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
MX6_PAD_DECL(SD3_CMD__UART2_CTS_B, 0x06A0, 0x02B8, 1, 0x0000, 0, 0)
MX6_PAD_DECL(SD3_CMD__UART2_RTS_B, 0x06A0, 0x02B8, 1, 0x0924, 2, 0)
MX6_PAD_DECL(SD3_CMD__FLEXCAN1_TX, 0x06A0, 0x02B8, 2, 0x0000, 0, 0)
@@ -924,7 +924,7 @@ MX6_PAD_DECL(NANDF_CS3__ESAI_TX1, 0x06D8, 0x02F0, 2, 0x0878, 1, 0)
MX6_PAD_DECL(NANDF_CS3__EIM_ADDR26, 0x06D8, 0x02F0, 3, 0x0000, 0, 0)
MX6_PAD_DECL(NANDF_CS3__GPIO6_IO16, 0x06D8, 0x02F0, 5, 0x0000, 0, 0)
MX6_PAD_DECL(NANDF_CS3__IPU2_SISG1, 0x06D8, 0x02F0, 6, 0x0000, 0, 0)
MX6_PAD_DECL(SD4_CMD__SD4_CMD, 0x06DC, 0x02F4, 16, 0x0000, 0, 0)
MX6_PAD_DECL(SD4_CMD__SD4_CMD, 0x06DC, 0x02F4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
MX6_PAD_DECL(SD4_CMD__NAND_RE_B, 0x06DC, 0x02F4, 1, 0x0000, 0, 0)
MX6_PAD_DECL(SD4_CMD__UART3_TX_DATA, 0x06DC, 0x02F4, 2, 0x0000, 0, 0)
MX6_PAD_DECL(SD4_CMD__UART3_RX_DATA, 0x06DC, 0x02F4, 2, 0x0930, 2, 0)
@@ -1001,7 +1001,7 @@ MX6_PAD_DECL(SD1_DAT3__PWM1_OUT, 0x072C, 0x0344, 3, 0x0000, 0, 0)
MX6_PAD_DECL(SD1_DAT3__WDOG2_B, 0x072C, 0x0344, 4, 0x0000, 0, 0)
MX6_PAD_DECL(SD1_DAT3__GPIO1_IO21, 0x072C, 0x0344, 5, 0x0000, 0, 0)
MX6_PAD_DECL(SD1_DAT3__WDOG2_RESET_B_DEB, 0x072C, 0x0344, 6, 0x0000, 0, 0)
MX6_PAD_DECL(SD1_CMD__SD1_CMD, 0x0730, 0x0348, 16, 0x0000, 0, 0)
MX6_PAD_DECL(SD1_CMD__SD1_CMD, 0x0730, 0x0348, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
MX6_PAD_DECL(SD1_CMD__ECSPI5_MOSI, 0x0730, 0x0348, 1, 0x0830, 0, 0)
MX6_PAD_DECL(SD1_CMD__PWM4_OUT, 0x0730, 0x0348, 2, 0x0000, 0, 0)
MX6_PAD_DECL(SD1_CMD__GPT_COMPARE1, 0x0730, 0x0348, 3, 0x0000, 0, 0)
@@ -1022,7 +1022,7 @@ MX6_PAD_DECL(SD2_CLK__ECSPI5_SCLK, 0x073C, 0x0354, 1, 0x0828, 1, 0)
MX6_PAD_DECL(SD2_CLK__KEY_COL5, 0x073C, 0x0354, 2, 0x08E8, 3, 0)
MX6_PAD_DECL(SD2_CLK__AUD4_RXFS, 0x073C, 0x0354, 3, 0x07C0, 1, 0)
MX6_PAD_DECL(SD2_CLK__GPIO1_IO10, 0x073C, 0x0354, 5, 0x0000, 0, 0)
MX6_PAD_DECL(SD2_CMD__SD2_CMD, 0x0740, 0x0358, 16, 0x0000, 0, 0)
MX6_PAD_DECL(SD2_CMD__SD2_CMD, 0x0740, 0x0358, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
MX6_PAD_DECL(SD2_CMD__ECSPI5_MOSI, 0x0740, 0x0358, 1, 0x0830, 1, 0)
MX6_PAD_DECL(SD2_CMD__KEY_ROW5, 0x0740, 0x0358, 2, 0x08F4, 2, 0)
MX6_PAD_DECL(SD2_CMD__AUD4_RXC, 0x0740, 0x0358, 3, 0x07BC, 1, 0)

View File

@@ -162,20 +162,17 @@ enum {
/* CRU_CLKSEL11_CON */
EMMC_PLL_SHIFT = 12,
EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT,
EMMC_SEL_APLL = 0,
EMMC_SEL_DPLL,
EMMC_SEL_CPLL = 0,
EMMC_SEL_GPLL,
EMMC_SEL_24M,
SDIO_PLL_SHIFT = 10,
SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT,
SDIO_SEL_APLL = 0,
SDIO_SEL_DPLL,
SDIO_SEL_CPLL = 0,
SDIO_SEL_GPLL,
SDIO_SEL_24M,
MMC0_PLL_SHIFT = 8,
MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT,
MMC0_SEL_APLL = 0,
MMC0_SEL_DPLL,
MMC0_SEL_CPLL = 0,
MMC0_SEL_GPLL,
MMC0_SEL_24M,
MMC0_DIV_SHIFT = 0,

View File

@@ -196,6 +196,10 @@
#define PRCM_CPU3_PWR_CLAMP(n) (((n) & 0xff) << 0)
#define PRCM_CPU3_PWR_CLAMP_MASK PRCM_CPU3_PWR_CLAMP(0xff)
#define PRCM_SEC_SWITCH_APB0_CLK_NONSEC (0x1 << 0)
#define PRCM_SEC_SWITCH_PLL_CFG_NONSEC (0x1 << 1)
#define PRCM_SEC_SWITCH_PWR_GATE_NONSEC (0x1 << 2)
#ifndef __ASSEMBLY__
#include <linux/compiler.h>
@@ -233,6 +237,8 @@ struct __packed sunxi_prcm_reg {
u32 dram_pwr; /* 0x180 */
u8 res12[0xc]; /* 0x184 */
u32 dram_tst; /* 0x190 */
u8 res13[0x3c]; /* 0x194 */
u32 prcm_sec_switch; /* 0x1d0 */
};
void prcm_apb0_enable(u32 flags);

View File

@@ -8,10 +8,14 @@
#define __SEC_FIRMWARE_H_
#define PSCI_INVALID_VER 0xffffffff
#define SEC_JR3_OFFSET 0x40000
int sec_firmware_init(const void *, u32 *, u32 *);
int _sec_firmware_entry(const void *, u32 *, u32 *);
bool sec_firmware_is_valid(const void *);
bool sec_firmware_support_hwrng(void);
int sec_firmware_get_random(uint8_t *rand, int bytes);
int fdt_fixup_kaslr(void *fdt);
#ifdef CONFIG_SEC_FIRMWARE_ARMV8_PSCI
unsigned int sec_firmware_support_psci_version(void);
unsigned int _sec_firmware_support_psci_version(void);
@@ -22,4 +26,9 @@ static inline unsigned int sec_firmware_support_psci_version(void)
}
#endif
static inline unsigned int sec_firmware_used_jobring_offset(void)
{
return SEC_JR3_OFFSET;
}
#endif /* __SEC_FIRMWARE_H_ */

View File

@@ -216,7 +216,7 @@ static void do_nonsec_virt_switch(void)
/* Subcommand: PREP */
static void boot_prep_linux(bootm_headers_t *images)
{
char *commandline = getenv("bootargs");
char *commandline = env_get("bootargs");
if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
#ifdef CONFIG_OF_LIBFDT
@@ -273,7 +273,7 @@ __weak bool armv7_boot_nonsec_default(void)
#ifdef CONFIG_ARMV7_NONSEC
bool armv7_boot_nonsec(void)
{
char *s = getenv("bootm_boot_mode");
char *s = env_get("bootm_boot_mode");
bool nonsec = armv7_boot_nonsec_default();
if (s && !strcmp(s, "sec"))
@@ -361,7 +361,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
ulong addr = (ulong)kernel_entry | 1;
kernel_entry = (void *)addr;
#endif
s = getenv("machid");
s = env_get("machid");
if (s) {
if (strict_strtoul(s, 16, &machid) < 0) {
debug("strict_strtoul failed!\n");

View File

@@ -200,7 +200,7 @@ static int do_smhload(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
/* Optionally save returned end to the environment */
if (argc == 4) {
sprintf(end_str, "0x%08lx", end_addr);
setenv(argv[3], end_str);
env_set(argv[3], end_str);
}
} else {
return CMD_RET_USAGE;

View File

@@ -22,7 +22,9 @@ obj-y += cache.o
obj-y += clock.o
obj-y += cpu.o
obj-y += reset.o
ifeq ($(CONFIG_ATMEL_PIT_TIMER),)
obj-y += timer.o
endif
ifndef CONFIG_SKIP_LOWLEVEL_INIT
obj-y += lowlevel_init.o

View File

@@ -14,4 +14,6 @@ obj-$(CONFIG_SAMA5D4) += sama5d4_devices.o
obj-y += clock.o
obj-y += cpu.o
obj-y += reset.o
ifeq ($(CONFIG_ATMEL_PIT_TIMER),)
obj-y += timer.o
endif

View File

@@ -90,7 +90,7 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr)
uint8_t env_enetaddr[6];
int ret;
ret = eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr);
ret = eth_env_get_enetaddr_by_index("eth", 0, env_enetaddr);
if (!ret) {
/*
* There is no MAC address in the environment, so we
@@ -99,7 +99,7 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr)
debug("### Setting environment from EEPROM MAC address = "
"\"%pM\"\n",
env_enetaddr);
ret = !eth_setenv_enetaddr("ethaddr", rom_enetaddr);
ret = !eth_env_set_enetaddr("ethaddr", rom_enetaddr);
}
if (!ret)
printf("Failed to set mac address from EEPROM: %d\n", ret);

View File

@@ -8,7 +8,6 @@ config ARCH_EXYNOS4
bool "Exynos4 SoC family"
select CPU_V7
select BOARD_EARLY_INIT_F
imply ENV_IS_IN_MMC
help
Samsung Exynos4 SoC family are based on ARM Cortex-A9 CPU. There
are multiple SoCs in this family including Exynos4210, Exynos4412,

View File

@@ -279,7 +279,7 @@ void arch_preboot_os(void)
imx_pcie_remove();
#endif
#if defined(CONFIG_SATA)
sata_stop();
sata_remove(0);
#if defined(CONFIG_MX6)
disable_sata_clock();
#endif

View File

@@ -1,24 +1,32 @@
if ARCH_MX6
config MX6_SMP
select ARM_ERRATA_751472
select ARM_ERRATA_761320
select ARM_ERRATA_794072
select ARM_ERRATA_845369
bool
config MX6
select ARM_ERRATA_743622 if !MX6UL
bool
default y
select ARM_ERRATA_743622 if !MX6UL
select ARM_ERRATA_751472 if !MX6UL
select ARM_ERRATA_761320 if !MX6UL
select ARM_ERRATA_794072 if !MX6UL
imply CMD_FUSE
config MX6D
select MX6_SMP
bool
config MX6DL
select MX6_SMP
bool
config MX6Q
select MX6_SMP
bool
config MX6QDL
select MX6_SMP
bool
config MX6S
@@ -30,7 +38,6 @@ config MX6SL
config MX6SX
select ROM_UNIFIED_SECTIONS
bool
imply ENV_IS_IN_MMC
config MX6SLL
select ROM_UNIFIED_SECTIONS
@@ -332,6 +339,11 @@ config TARGET_PCM058
select BOARD_LATE_INIT
select SUPPORT_SPL
config TARGET_PFLA02
bool "Phytec PFLA02 (PhyFlex) i.MX6 Quad"
select BOARD_LATE_INIT
select SUPPORT_SPL
config TARGET_SECOMX6
bool "secomx6 boards"
@@ -429,6 +441,7 @@ source "board/freescale/mx6ul_14x14_evk/Kconfig"
source "board/freescale/mx6ullevk/Kconfig"
source "board/grinn/liteboard/Kconfig"
source "board/phytec/pcm058/Kconfig"
source "board/phytec/pfla02/Kconfig"
source "board/gateworks/gw_ventana/Kconfig"
source "board/kosagi/novena/Kconfig"
source "board/samtec/vining_2000/Kconfig"

View File

@@ -19,7 +19,7 @@ enum pll_clocks {
PLL_USBOTG, /* OTG USB PLL */
PLL_ENET, /* ENET PLL */
PLL_AUDIO, /* AUDIO PLL */
PLL_VIDEO, /* AUDIO PLL */
PLL_VIDEO, /* VIDEO PLL */
};
struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

View File

@@ -132,7 +132,7 @@ int board_late_init(void)
/* In bootstrap don't use the env vars */
if (((reg & 0x3000000) >> 24) == 0x1) {
set_default_env(NULL);
setenv("preboot", "");
env_set("preboot", "");
}
return opos6ul_board_late_init();

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@@ -114,6 +114,12 @@ u32 get_cpu_rev(void)
#define OCOTP_CFG3_SPEED_528MHZ 1
#define OCOTP_CFG3_SPEED_696MHZ 2
/*
* For i.MX6ULL
*/
#define OCOTP_CFG3_SPEED_792MHZ 2
#define OCOTP_CFG3_SPEED_900MHZ 3
u32 get_cpu_speed_grade_hz(void)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
@@ -126,11 +132,22 @@ u32 get_cpu_speed_grade_hz(void)
val >>= OCOTP_CFG3_SPEED_SHIFT;
val &= 0x3;
if (is_mx6ul() || is_mx6ull()) {
if (is_mx6ul()) {
if (val == OCOTP_CFG3_SPEED_528MHZ)
return 528000000;
else if (val == OCOTP_CFG3_SPEED_696MHZ)
return 69600000;
return 696000000;
else
return 0;
}
if (is_mx6ull()) {
if (val == OCOTP_CFG3_SPEED_528MHZ)
return 528000000;
else if (val == OCOTP_CFG3_SPEED_792MHZ)
return 792000000;
else if (val == OCOTP_CFG3_SPEED_900MHZ)
return 900000000;
else
return 0;
}
@@ -234,6 +251,10 @@ static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
u32 val, step, old, reg = readl(&anatop->reg_core);
u8 shift;
/* No LDO_SOC/PU/ARM */
if (is_mx6sll())
return 0;
if (mv < 725)
val = 0x00; /* Power gated off */
else if (mv > 1450)
@@ -293,7 +314,7 @@ static void clear_mmdc_ch_mask(void)
reg = readl(&mxc_ccm->ccdr);
/* Clear MMDC channel mask */
if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl())
if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() || is_mx6sll())
reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
else
reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
@@ -344,20 +365,10 @@ static void init_bandgap(void)
}
}
#ifdef CONFIG_MX6SL
static void set_preclk_from_osc(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
u32 reg;
reg = readl(&mxc_ccm->cscmr1);
reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
writel(reg, &mxc_ccm->cscmr1);
}
#endif
int arch_cpu_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
init_aips();
/* Need to clear MMDC_CHx_MASK to make warm reset work. */
@@ -421,12 +432,14 @@ int arch_cpu_init(void)
}
/* Set perclk to source from OSC 24MHz */
#if defined(CONFIG_MX6SL)
set_preclk_from_osc();
#endif
if (is_mx6sl())
setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK);
imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
if (is_mx6sx())
setbits_le32(&ccm->cscdr1, MXC_CCM_CSCDR1_UART_CLK_SEL);
init_src();
return 0;
@@ -495,6 +508,10 @@ uint mmc_get_env_part(struct mmc *mmc)
int board_postclk_init(void)
{
/* NO LDO SOC on i.MX6SLL */
if (is_mx6sll())
return 0;
set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
return 0;
@@ -576,7 +593,7 @@ void s_init(void)
u32 mask528;
u32 reg, periph1, periph2;
if (is_mx6sx() || is_mx6ul() || is_mx6ull())
if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sll())
return;
/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs

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@@ -13,7 +13,6 @@ config MX7D
select ROM_UNIFIED_SECTIONS
imply CMD_FUSE
bool
imply ENV_IS_IN_MMC
choice
prompt "MX7 board select"

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@@ -31,7 +31,7 @@ U_BOOT_DEVICE(imx7_thermal) = {
};
#endif
#ifdef CONFIG_IMX_RDC
#if CONFIG_IS_ENABLED(IMX_RDC)
/*
* In current design, if any peripheral was assigned to both A7 and M4,
* it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
@@ -245,8 +245,9 @@ int arch_cpu_init(void)
mxs_dma_init();
#endif
if (IS_ENABLED(CONFIG_IMX_RDC))
isolate_resource();
#if CONFIG_IS_ENABLED(IMX_RDC)
isolate_resource();
#endif
return 0;
}
@@ -256,9 +257,9 @@ int arch_misc_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
if (is_mx7d())
setenv("soc", "imx7d");
env_set("soc", "imx7d");
else
setenv("soc", "imx7s");
env_set("soc", "imx7s");
#endif
return 0;

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@@ -10,7 +10,7 @@ int board_video_skip(void)
{
int i;
int ret;
char const *panel = getenv("panel");
char const *panel = env_get("panel");
if (!panel) {
for (i = 0; i < display_count; i++) {

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@@ -11,13 +11,11 @@ config ARCH_INTEGRATOR_AP
config ARCH_INTEGRATOR_CP
bool "Support Integrator/CP platform"
select ARCH_CINTEGRATOR
imply ENV_IS_IN_FLASH
endchoice
config ARCH_CINTEGRATOR
bool
imply ENV_IS_IN_FLASH
choice
prompt "Integrator core module select"

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@@ -331,7 +331,7 @@ void ddr3_check_ecc_int(u32 base)
int ecc_test = 0;
u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET);
env = getenv("ecc_test");
env = env_get("ecc_test");
if (env)
ecc_test = simple_strtol(env, NULL, 0);

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@@ -46,7 +46,7 @@ int misc_init_r(void)
char *env;
long ks2_debug = 0;
env = getenv("ks2_debug");
env = env_get("ks2_debug");
if (env)
ks2_debug = simple_strtol(env, NULL, 0);

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@@ -129,7 +129,7 @@ int kw_config_adr_windows(void)
static void kw_sysrst_action(void)
{
int ret;
char *s = getenv("sysrstcmd");
char *s = env_get("sysrstcmd");
if (!s) {
debug("Error.. %s failed, check sysrstcmd\n",
@@ -153,7 +153,7 @@ static void kw_sysrst_check(void)
/*
* no action if sysrstdelay environment variable is not defined
*/
s = getenv("sysrstdelay");
s = env_get("sysrstdelay");
if (s == NULL)
return;

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@@ -32,7 +32,6 @@ config ARMADA_38X
config ARMADA_XP
bool
select ARMADA_32BIT
imply ENV_IS_IN_SPI_FLASH
# ARMv8 SoCs...
config ARMADA_3700

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@@ -10,6 +10,7 @@
#include <common.h>
#include <ahci.h>
#include <environment.h>
#include <spl.h>
#include <asm/omap_common.h>
#include <asm/arch/omap.h>
@@ -240,8 +241,8 @@ void arch_preboot_os(void)
int fb_set_reboot_flag(void)
{
printf("Setting reboot to fastboot flag ...\n");
setenv("dofastboot", "1");
saveenv();
env_set("dofastboot", "1");
env_save();
return 0;
}
#endif

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@@ -40,7 +40,7 @@ static void omap_set_fastboot_cpu(void)
printf("Warning: fastboot.cpu: unknown CPU rev: %u\n", cpu_rev);
}
setenv("fastboot.cpu", cpu);
env_set("fastboot.cpu", cpu);
}
static void omap_set_fastboot_secure(void)
@@ -63,18 +63,18 @@ static void omap_set_fastboot_secure(void)
printf("Warning: fastboot.secure: unknown CPU sec: %u\n", dev);
}
setenv("fastboot.secure", secure);
env_set("fastboot.secure", secure);
}
static void omap_set_fastboot_board_rev(void)
{
const char *board_rev;
board_rev = getenv("board_rev");
board_rev = env_get("board_rev");
if (board_rev == NULL)
printf("Warning: fastboot.board_rev: unknown board revision\n");
setenv("fastboot.board_rev", board_rev);
env_set("fastboot.board_rev", board_rev);
}
#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
@@ -118,7 +118,7 @@ static void omap_set_fastboot_userdata_size(void)
sprintf(buf, "%u", sz_kb);
}
setenv("fastboot.userdata_size", buf);
env_set("fastboot.userdata_size", buf);
}
#else
static inline void omap_set_fastboot_userdata_size(void)
@@ -169,11 +169,11 @@ void omap_die_id_serial(void)
omap_die_id((unsigned int *)&die_id);
if (!getenv("serial#")) {
if (!env_get("serial#")) {
snprintf(serial_string, sizeof(serial_string),
"%08x%08x", die_id[0], die_id[3]);
setenv("serial#", serial_string);
env_set("serial#", serial_string);
}
}
@@ -182,7 +182,7 @@ void omap_die_id_get_board_serial(struct tag_serialnr *serialnr)
char *serial_string;
unsigned long long serial;
serial_string = getenv("serial#");
serial_string = env_get("serial#");
if (serial_string) {
serial = simple_strtoull(serial_string, NULL, 16);
@@ -202,7 +202,7 @@ void omap_die_id_usbethaddr(void)
omap_die_id((unsigned int *)&die_id);
if (!getenv("usbethaddr")) {
if (!env_get("usbethaddr")) {
/*
* Create a fake MAC address from the processor ID code.
* First byte is 0x02 to signify locally administered.
@@ -214,7 +214,7 @@ void omap_die_id_usbethaddr(void)
mac[4] = die_id[0] & 0xff;
mac[5] = (die_id[0] >> 8) & 0xff;
eth_setenv_enetaddr("usbethaddr", mac);
eth_env_set_enetaddr("usbethaddr", mac);
}
}

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@@ -49,11 +49,6 @@
/* SDHI CMD VALUE */
#define CMD_MASK 0x0000ffff
#define SDHI_APP 0x0040
#define SDHI_MMC_SEND_OP_COND 0x0701
#define SDHI_SD_APP_SEND_SCR 0x0073
#define SDHI_SD_SWITCH 0x1C06
#define SDHI_MMC_SEND_EXT_CSD 0x1C08
/* SDHI_PORTSEL */
#define USE_1PORT (1 << 8) /* 1 port */

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@@ -34,11 +34,11 @@ static void setup_boot_mode(void)
switch (boot_mode) {
case BOOT_FASTBOOT:
printf("enter fastboot!\n");
setenv("preboot", "setenv preboot; fastboot usb0");
env_set("preboot", "setenv preboot; fastboot usb0");
break;
case BOOT_UMS:
printf("enter UMS!\n");
setenv("preboot", "setenv preboot; ums mmc 0");
env_set("preboot", "setenv preboot; ums mmc 0");
break;
}
}

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@@ -30,11 +30,11 @@ static void setup_boot_mode(void)
switch (boot_mode) {
case BOOT_FASTBOOT:
printf("enter fastboot!\n");
setenv("preboot", "setenv preboot; fastboot usb0");
env_set("preboot", "setenv preboot; fastboot usb0");
break;
case BOOT_UMS:
printf("enter UMS!\n");
setenv("preboot", "setenv preboot; ums mmc 0");
env_set("preboot", "setenv preboot; ums mmc 0");
break;
}
}
@@ -72,11 +72,13 @@ int board_init(void)
int dram_init_banksize(void)
{
/* Reserve 0x200000 for OPTEE */
gd->bd->bi_dram[0].start = 0x60000000;
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = 0x8400000;
gd->bd->bi_dram[1].start = 0x6a400000;
gd->bd->bi_dram[1].size = gd->ram_size - gd->bd->bi_dram[1].start;
/* Reserve 0x200000 for OPTEE */
gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
+ gd->bd->bi_dram[0].size + 0x200000;
gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
+ gd->ram_size - gd->bd->bi_dram[1].start;
return 0;
}

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@@ -37,11 +37,11 @@ static void setup_boot_mode(void)
switch (boot_mode) {
case BOOT_FASTBOOT:
printf("enter fastboot!\n");
setenv("preboot", "setenv preboot; fastboot usb0");
env_set("preboot", "setenv preboot; fastboot usb0");
break;
case BOOT_UMS:
printf("enter UMS!\n");
setenv("preboot", "setenv preboot; if mmc dev 0;"
env_set("preboot", "setenv preboot; if mmc dev 0;"
"then ums mmc 0; else ums mmc 1;fi");
break;
}

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@@ -7,7 +7,6 @@
#include <common.h>
#include <debug_uart.h>
#include <dm.h>
#include <fdtdec.h>
#include <ram.h>
#include <spl.h>
#include <asm/gpio.h>

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@@ -219,9 +219,9 @@ int arch_misc_init(void)
{
const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
const int fpga_id = socfpga_fpga_id(0);
setenv("bootmode", bsel_str[bsel].mode);
env_set("bootmode", bsel_str[bsel].mode);
if (fpga_id >= 0)
setenv("fpgatype", socfpga_fpga_model[fpga_id].var);
env_set("fpgatype", socfpga_fpga_model[fpga_id].var);
return socfpga_eth_reset();
}
#endif

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@@ -18,7 +18,7 @@ config STM32F7
select SPL_OF_CONTROL
select SPL_OF_LIBFDT
select SPL_OF_TRANSLATE
select SPL_OS_BOOT
imply SPL_OS_BOOT
select SPL_PINCTRL
select SPL_RAM
select SPL_SERIAL_SUPPORT

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@@ -62,7 +62,6 @@ config MACH_SUNXI_H3_H5
select SUNXI_DRAM_DW_32BIT
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
imply ENV_IS_IN_MMC
choice
prompt "Sunxi SoC Variant"
@@ -74,7 +73,6 @@ config MACH_SUN4I
select ARM_CORTEX_CPU_IS_UP
select SUNXI_GEN_SUN4I
select SUPPORT_SPL
imply ENV_IS_IN_MMC
config MACH_SUN5I
bool "sun5i (Allwinner A13)"
@@ -92,7 +90,6 @@ config MACH_SUN6I
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
imply ENV_IS_IN_MMC
config MACH_SUN7I
bool "sun7i (Allwinner A20)"
@@ -103,7 +100,6 @@ config MACH_SUN7I
select SUNXI_GEN_SUN4I
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
imply ENV_IS_IN_MMC
config MACH_SUN8I_A23
bool "sun8i (Allwinner A23)"
@@ -114,7 +110,6 @@ config MACH_SUN8I_A23
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
imply ENV_IS_IN_MMC
config MACH_SUN8I_A33
bool "sun8i (Allwinner A33)"
@@ -140,7 +135,6 @@ config MACH_SUN8I_H3
select ARCH_SUPPORT_PSCI
select MACH_SUNXI_H3_H5
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
imply ENV_IS_IN_MMC
config MACH_SUN8I_R40
bool "sun8i (Allwinner R40)"

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@@ -66,11 +66,17 @@ void clock_init_sec(void)
#ifdef CONFIG_MACH_SUNXI_H3_H5
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
struct sunxi_prcm_reg * const prcm =
(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
setbits_le32(&ccm->ccu_sec_switch,
CCM_SEC_SWITCH_MBUS_NONSEC |
CCM_SEC_SWITCH_BUS_NONSEC |
CCM_SEC_SWITCH_PLL_NONSEC);
setbits_le32(&prcm->prcm_sec_switch,
PRCM_SEC_SWITCH_APB0_CLK_NONSEC |
PRCM_SEC_SWITCH_PLL_CFG_NONSEC |
PRCM_SEC_SWITCH_PWR_GATE_NONSEC);
#endif
}

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@@ -60,7 +60,6 @@ config TEGRA_ARMV8_COMMON
bool "Tegra 64-bit common options"
select ARM64
select TEGRA_COMMON
imply ENV_IS_IN_MMC
choice
prompt "Tegra SoC select"
@@ -78,7 +77,6 @@ config TEGRA30
select ARM_ERRATA_743622
select ARM_ERRATA_751472
select TEGRA_ARMV7_COMMON
imply ENV_IS_IN_MMC
config TEGRA114
bool "Tegra114 family"
@@ -87,7 +85,6 @@ config TEGRA114
config TEGRA124
bool "Tegra124 family"
select TEGRA_ARMV7_COMMON
imply ENV_IS_IN_MMC
imply REGMAP
imply SYSCON

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@@ -214,9 +214,9 @@ int board_late_init(void)
#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
if (tegra_cpu_is_non_secure()) {
printf("CPU is in NS mode\n");
setenv("cpu_ns_mode", "1");
env_set("cpu_ns_mode", "1");
} else {
setenv("cpu_ns_mode", "");
env_set("cpu_ns_mode", "");
}
#endif
start_cpu_fan();

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@@ -15,7 +15,7 @@ static int set_fdt_addr(void)
{
int ret;
ret = setenv_hex("fdt_addr", nvtboot_boot_x0);
ret = env_set_hex("fdt_addr", nvtboot_boot_x0);
if (ret) {
printf("Failed to set fdt_addr to point at DTB: %d\n", ret);
return ret;
@@ -35,7 +35,7 @@ static int set_ethaddr_from_nvtboot(void)
const u32 *prop;
/* Already a valid address in the environment? If so, keep it */
if (getenv("ethaddr"))
if (env_get("ethaddr"))
return 0;
node = fdt_path_offset(nvtboot_blob, "/chosen");
@@ -49,7 +49,7 @@ static int set_ethaddr_from_nvtboot(void)
return -ENOENT;
}
ret = setenv("ethaddr", (void *)prop);
ret = env_set("ethaddr", (void *)prop);
if (ret) {
printf("Failed to set ethaddr from nvtboot DTB: %d\n", ret);
return ret;

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@@ -15,10 +15,6 @@ choice
prompt "UniPhier SoC select"
default ARCH_UNIPHIER_PRO4
config ARCH_UNIPHIER_SLD3
bool "UniPhier sLD3 SoC"
select ARCH_UNIPHIER_32BIT
config ARCH_UNIPHIER_LD4_SLD8
bool "UniPhier LD4/sLD8 SoCs"
select ARCH_UNIPHIER_32BIT

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@@ -197,9 +197,6 @@ void uniphier_cache_set_active_ways(int cpu, u32 active_ways)
void __iomem *base = (void __iomem *)UNIPHIER_SSCC + 0xc00;
switch (readl(UNIPHIER_SSCID)) { /* revision */
case 0x11: /* sLD3 */
base = (void __iomem *)UNIPHIER_SSCC + 0x870;
break;
case 0x12: /* LD4 */
case 0x16: /* sld8 */
base = (void __iomem *)UNIPHIER_SSCC + 0x840;

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@@ -26,27 +26,6 @@ ENTRY(debug_ll_init)
and r1, r1, #SG_REVISION_TYPE_MASK
mov r1, r1, lsr #SG_REVISION_TYPE_SHIFT
#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
#define UNIPHIER_SLD3_UART_CLK 36864000
cmp r1, #0x25
bne sld3_end
sg_set_pinsel 64, 1, 4, 4, r0, r1 @ TXD0 -> TXD0
ldr r0, =BCSCR5
ldr r1, =0x24440000
str r1, [r0]
ldr r0, =SC_CLKCTRL
ldr r1, [r0]
orr r1, r1, #SC_CLKCTRL_CEN_PERI
str r1, [r0]
ldr r3, =DIV_ROUND(UNIPHIER_SLD3_UART_CLK, 16 * BAUDRATE)
b init_uart
sld3_end:
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD4)
#define UNIPHIER_LD4_UART_CLK 36864000
cmp r1, #0x26

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@@ -25,13 +25,16 @@ ENTRY(lowlevel_init)
orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache
mcr p15, 0, r0, c1, c0, 0
#ifdef CONFIG_DEBUG_LL
bl debug_ll_init
#endif
bl setup_init_ram @ RAM area for stack and page table
/*
* Now we are using the page table embedded in the Boot ROM.
* It is not handy since it is not a straight mapped table for sLD3.
* Also, the access to the external bus is prohibited. What we need
* to do next is to create a page table and switch over to it.
* What we need to do next is to create a page table and switch
* over to it.
*/
bl create_page_table
bl __v7_flush_dcache_all
@@ -43,10 +46,6 @@ ENTRY(lowlevel_init)
bl enable_mmu
#ifdef CONFIG_DEBUG_LL
bl debug_ll_init
#endif
mov lr, r8 @ restore link
mov pc, lr @ back to my caller
ENDPROC(lowlevel_init)
@@ -99,11 +98,6 @@ ENDPROC(enable_mmu)
ENTRY(setup_init_ram)
ldr r1, = SSCO_BASE
mrc p15, 0, r0, c2, c0, 0 @ TTBR0
ldr r0, [r0, #0x400] @ entry for virtual address 0x100*****
bfc r0, #0, #20
cmp r0, #0x50000000 @ is sLD3 page table?
biceq r1, r1, #0xc0000000 @ sLD3 ROM maps 0x5******* to 0x1*******
/* Touch to zero for the boot way */
0: ldr r0, = 0x00408006 @ touch to zero with address range

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@@ -29,7 +29,6 @@ u32 uniphier_smp_booted[CONFIG_ARMV7_PSCI_NR_CPUS];
static int uniphier_get_nr_cpus(void)
{
switch (uniphier_get_soc_id()) {
case UNIPHIER_SLD3_ID:
case UNIPHIER_PRO4_ID:
case UNIPHIER_PRO5_ID:
return 2;

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@@ -2,6 +2,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += bcu-sld3.o
obj-$(CONFIG_ARCH_UNIPHIER_LD4) += bcu-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += bcu-ld4.o

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@@ -1,39 +0,0 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/io.h>
#include "../init.h"
#include "bcu-regs.h"
#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
void uniphier_sld3_bcu_init(const struct uniphier_board_data *bd)
{
int shift;
writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
/*
* 0xe0000000-0xefffffff: Ex-bus
* 0xf0000000-0xfbffffff: ASM bus
* 0xfc000000-0xffffffff: OCM bus
*/
writel(0x24440000, BCSCR5);
/* Specify DDR channel */
shift = bd->dram_ch[0].size / 0x04000000 * 4;
writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
shift -= 32;
writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
shift -= 32;
writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
}

View File

@@ -86,15 +86,6 @@ struct uniphier_initdata {
};
static const struct uniphier_initdata uniphier_initdata[] = {
#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
{
.soc_id = UNIPHIER_SLD3_ID,
.nand_2cs = true,
.sbc_init = uniphier_sbc_init_admulti,
.pll_init = uniphier_sld3_pll_init,
.clk_init = uniphier_ld4_clk_init,
},
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD4)
{
.soc_id = UNIPHIER_LD4_ID,

View File

@@ -37,7 +37,7 @@ static int uniphier_set_fdt_file(void)
char dtb_name[256];
int buf_len = sizeof(dtb_name);
if (getenv("fdt_file"))
if (env_get("fdt_file"))
return 0; /* do nothing if it is already set */
compat = fdt_stringlist_get(gd->fdt_blob, 0, "compatible", 0, NULL);
@@ -55,7 +55,7 @@ static int uniphier_set_fdt_file(void)
strncat(dtb_name, ".dtb", buf_len);
return setenv("fdt_file", dtb_name);
return env_set("fdt_file", dtb_name);
}
int board_late_init(void)
@@ -65,20 +65,20 @@ int board_late_init(void)
switch (uniphier_boot_device_raw()) {
case BOOT_DEVICE_MMC1:
printf("eMMC Boot");
setenv("bootmode", "emmcboot");
env_set("bootmode", "emmcboot");
break;
case BOOT_DEVICE_NAND:
printf("NAND Boot");
setenv("bootmode", "nandboot");
env_set("bootmode", "nandboot");
nand_denali_wp_disable();
break;
case BOOT_DEVICE_NOR:
printf("NOR Boot");
setenv("bootmode", "norboot");
env_set("bootmode", "norboot");
break;
case BOOT_DEVICE_USB:
printf("USB Boot");
setenv("bootmode", "usbboot");
env_set("bootmode", "usbboot");
break;
default:
printf("Unknown");

View File

@@ -13,25 +13,6 @@
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
static const struct uniphier_board_data uniphier_sld3_data = {
.dram_freq = 1600,
.dram_ch[0] = {
.size = 0x20000000,
.width = 32,
},
.dram_ch[1] = {
.size = 0x20000000,
.width = 16,
},
.dram_ch[2] = {
.size = 0x10000000,
.width = 16,
},
.flags = UNIPHIER_BD_DRAM_SPARSE,
};
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD4)
static const struct uniphier_board_data uniphier_ld4_data = {
.dram_freq = 1600,
@@ -146,9 +127,6 @@ struct uniphier_board_id {
};
static const struct uniphier_board_id uniphier_boards[] = {
#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
{ "socionext,uniphier-sld3", &uniphier_sld3_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD4)
{ "socionext,uniphier-ld4", &uniphier_ld4_data, },
#endif

View File

@@ -4,7 +4,6 @@
obj-y += boot-device.o
obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += boot-device-sld3.o
obj-$(CONFIG_ARCH_UNIPHIER_LD4) += boot-device-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += boot-device-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += boot-device-ld4.o

View File

@@ -1,84 +0,0 @@
/*
* Copyright (C) 2014 Panasonic Corporation
* Copyright (C) 2015-2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include "boot-device.h"
const struct uniphier_boot_device uniphier_sld3_boot_device_table[] = {
{BOOT_DEVICE_NOR, "NOR (XECS0)"},
{BOOT_DEVICE_NONE, "External Master"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_MMC1, "eMMC (3.3V, Boot Oparation)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_MMC1, "eMMC (1.8V, Boot Oparation)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_MMC1, "eMMC (3.3V, Normal)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_MMC1, "eMMC (1.8V, Normal)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
};
const unsigned uniphier_sld3_boot_device_count =
ARRAY_SIZE(uniphier_sld3_boot_device_table);

View File

@@ -26,15 +26,6 @@ struct uniphier_boot_device_info {
};
static const struct uniphier_boot_device_info uniphier_boot_device_info[] = {
#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
{
.soc_id = UNIPHIER_SLD3_ID,
.boot_device_sel_shift = 0,
.boot_device_table = uniphier_sld3_boot_device_table,
.boot_device_count = &uniphier_sld3_boot_device_count,
.have_internal_stm = 0,
},
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD4)
{
.soc_id = UNIPHIER_LD4_ID,

View File

@@ -13,14 +13,12 @@ struct uniphier_boot_device {
const char *desc;
};
extern const struct uniphier_boot_device uniphier_sld3_boot_device_table[];
extern const struct uniphier_boot_device uniphier_ld4_boot_device_table[];
extern const struct uniphier_boot_device uniphier_pro5_boot_device_table[];
extern const struct uniphier_boot_device uniphier_pxs2_boot_device_table[];
extern const struct uniphier_boot_device uniphier_ld11_boot_device_table[];
extern const struct uniphier_boot_device uniphier_pxs3_boot_device_table[];
extern const unsigned int uniphier_sld3_boot_device_count;
extern const unsigned int uniphier_ld4_boot_device_count;
extern const unsigned int uniphier_pro5_boot_device_count;
extern const unsigned int uniphier_pxs2_boot_device_count;

View File

@@ -4,17 +4,15 @@
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += clk-early-sld3.o clk-dram-sld3.o dpll-sld3.o
obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-early-sld3.o clk-dram-sld3.o dpll-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-early-sld3.o clk-dram-sld3.o dpll-pro4.o
obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-early-sld3.o clk-dram-sld3.o dpll-sld8.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-early-sld3.o clk-dram-pro5.o dpll-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-early-sld3.o clk-dram-pxs2.o dpll-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-early-sld3.o clk-dram-pxs2.o dpll-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-early-ld4.o clk-dram-ld4.o dpll-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-early-ld4.o clk-dram-ld4.o dpll-pro4.o
obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-early-ld4.o clk-dram-ld4.o dpll-sld8.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-early-ld4.o clk-dram-pro5.o dpll-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
else
obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += clk-ld4.o pll-sld3.o dpll-tail.o
obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-ld4.o pll-ld4.o dpll-tail.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-pro4.o pll-pro4.o dpll-tail.o
obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-ld4.o pll-ld4.o dpll-tail.o

View File

@@ -12,7 +12,7 @@
#include "../init.h"
#include "../sc-regs.h"
void uniphier_sld3_dram_clk_init(void)
void uniphier_ld4_dram_clk_init(void)
{
u32 tmp;

View File

@@ -12,7 +12,7 @@
#include "../init.h"
#include "../sc-regs.h"
void uniphier_sld3_early_clk_init(void)
void uniphier_ld4_early_clk_init(void)
{
u32 tmp;

View File

@@ -1,13 +0,0 @@
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "../init.h"
int uniphier_sld3_dpll_init(const struct uniphier_board_data *bd)
{
/* add pll init code here */
return 0;
}

View File

@@ -1,14 +0,0 @@
/*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "../init.h"
#include "pll.h"
void uniphier_sld3_pll_init(void)
{
uniphier_ld4_dpll_ssc_en();
}

View File

@@ -23,10 +23,6 @@ int print_cpuinfo(void)
puts("SoC: ");
switch (id) {
case UNIPHIER_SLD3_ID:
puts("sLD3");
required_model = 2;
break;
case UNIPHIER_LD4_ID:
puts("LD4");
required_rev = 2;

View File

@@ -3,7 +3,6 @@
#
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += debug-uart-sld3.o
obj-$(CONFIG_ARCH_UNIPHIER_LD4) += debug-uart-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += debug-uart-pro4.o
obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += debug-uart-sld8.o

View File

@@ -1,31 +0,0 @@
/*
* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include "../bcu/bcu-regs.h"
#include "../sc-regs.h"
#include "../sg-regs.h"
#include "debug-uart.h"
#define UNIPHIER_SLD3_UART_CLK 36864000
unsigned int uniphier_sld3_debug_uart_init(void)
{
u32 tmp;
sg_set_pinsel(64, 1, 4, 4); /* TXD0 -> TXD0 */
writel(0x24440000, BCSCR5);
tmp = readl(SC_CLKCTRL);
tmp |= SC_CLKCTRL_CEN_PERI;
writel(tmp, SC_CLKCTRL);
return DIV_ROUND_CLOSEST(UNIPHIER_SLD3_UART_CLK, 16 * CONFIG_BAUDRATE);
}

View File

@@ -33,11 +33,6 @@ void _debug_uart_init(void)
unsigned int divisor;
switch (uniphier_get_soc_id()) {
#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
case UNIPHIER_SLD3_ID:
divisor = uniphier_sld3_debug_uart_init();
break;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD4)
case UNIPHIER_LD4_ID:
divisor = uniphier_ld4_debug_uart_init();

View File

@@ -7,7 +7,6 @@
#ifndef _MACH_DEBUG_UART_H
#define _MACH_DEBUG_UART_H
unsigned int uniphier_sld3_debug_uart_init(void);
unsigned int uniphier_ld4_debug_uart_init(void);
unsigned int uniphier_pro4_debug_uart_init(void);
unsigned int uniphier_sld8_debug_uart_init(void);

View File

@@ -4,7 +4,6 @@
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += umc-sld3.o
obj-$(CONFIG_ARCH_UNIPHIER_LD4) += umc-ld4.o \
ddrphy-training.o ddrphy-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += umc-pro4.o \

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