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1439 Commits

Author SHA1 Message Date
Tom Rini
c253573f3e Prepare v2017.11
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-11-13 20:08:06 -05:00
Soeren Moch
be135cc5eb Revert "console: simplify puts()"
This reverts commit c61d0009fe.

A tbs2910 board user reported a very slow console frambuffer as
regression in current u-boot. I could bisect this down to the
above mentioned commit.

This revert brings back the fast framebuffer console (one
cache flush per string in puts(), not after each char).

Reported-by: Uwe Scheffler <scheffler.u@web.de>
Signed-off-by: Soeren Moch <smoch@web.de>
Tested-by: Uwe Scheffler <scheffler.u@web.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-12 16:18:16 -05:00
Angelo Dureghello
ae147ab4a8 board: sysam: stmark2: add missing environment location
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
2017-11-12 16:18:16 -05:00
Marek Vasut
2bfd43e550 ARM: rmobile: Fix eMMC signal voltage on Salvator-X/XS
The eMMC is 1V8 device only and the signaling is always 1V8,
fix the DT for Salvator-X/XS to describe the hardware correctly.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-12 16:17:31 -05:00
Tom Rini
66bd5a3ebb Merge git://git.denx.de/u-boot-sunxi 2017-11-10 10:04:21 -05:00
Werner Böllmann
8e2c2d413c sunxi: SATA link timeout fix
After updating u-boot from v2016.01 to 2017.09, issue with
"SATA link 0 timeout." on my Cubietruck board.

mdelay milled after moving satapwr code to board.
"sunxi: Turn satapwr on from board_init"
(sha1: 9fbb0c3aa4)

After adding the "mdelay(500);"
line that was lost in the path the error is gone.

Signed-off-by: Werner Böllmann <Werner.Boellmann@fh-dortmund.de>
[Rebased and updated change and commit message]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-11-10 19:21:24 +05:30
Chen-Yu Tsai
13ae2a40e7 net: sun8i_emac: Fix build for non-H3/H5 SoCs
Only the H3/H5 SoCs have an internal PHY and its related clock and
reset controls.

Use an #ifdef to guard the internal PHY control code block so it
can be built for other SoCs, such as the A83T or A64.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-11-10 19:10:33 +05:30
Tom Rini
60567a320f Merge git://git.denx.de/u-boot-rockchip 2017-11-10 08:19:01 -05:00
Jagan Teki
36b6e0cc3c rockchip: configs: vyasa: Update falcon offsets
Update the falcon offsets for args to 16MB and kernel to 17MB
Since the below commit updated U-Boot proper location along
with rockchip boot image offsets
"spl: set SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR to 0x4000 for rockchip"
(sha1: 8f4d62b403)

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-10 14:08:22 +01:00
Jagan Teki
d80599e894 rockchip: doc: Fix U-Boot proper location for falcon
This patch fixed U-Boot proper location has been
missed to update in bewlo commit
"rockchip: doc: update U-Boot location info"
(sha1: 73e6dbe855)

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-10 14:08:21 +01:00
Goldschmidt Simon
341e44ed66 rockchip: doc: update U-Boot location info
The U-Boot location has been moved to block 16384.
This is 8MB, not 4MB.

Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-10 14:08:20 +01:00
Tom Rini
1c4043e532 Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2017-11-09 08:11:40 -05:00
Tom Rini
3c674b7e87 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2017-11-09 08:11:30 -05:00
Lukasz Majewski
9c8979cdb7 imx7: Add include guards for include/asm/arch-mx7/sys_proto.h file
Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-11-09 11:32:49 +01:00
Lukasz Majewski
e895e996ab imx5: Add include guards for include/asm/arch-mx5/sys_proto.h file
Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-11-09 11:32:49 +01:00
Lukasz Majewski
90d0e38c1e imx6: Add include guards for include/asm/arch-mx6/sys_proto.h file
Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-11-09 11:32:49 +01:00
Lukasz Majewski
a3eec24ad3 imx:display5: Add support for LWN's DISPLAY5 board
This commit provides support for LWN's IMX6Q based DISPLAY5 board.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-11-09 11:32:49 +01:00
Lukasz Majewski
ec1b26973c imx6: iomux: Add generic function to set RGMII IO voltage on IMX6 SoCs
This commit provides generic function to set the RGMII/HSIC IO voltage
level on iMX6 devices.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-11-09 11:32:49 +01:00
Lukasz Majewski
8ea754da60 board: imx6: marsboard: Remove doubled #include <asm/arch/sys_proto.h>
The sys_proto.h file has been included earlier in this file.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-11-09 11:32:49 +01:00
Artturi Alm
6270a3f035 sunxi: restore PHYLIB for CONFIG_SUN4I_EMAC users
due misnaming of CONFIG_SUN4I_EMAC in include/configs/sunxi-common.h,
likely missed in:
	commit 3146f0c017 ("Move PHYLIB to Kconfig")

Signed-off-by: Artturi Alm <artturi.alm@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-11-09 14:39:30 +05:30
Artturi Alm
e286fada9d sunxi: fix CONFIG_SUNXI_EMAC references
fixes CONFIG_SUNXI_EMAC references from drivers/net/Makefile and
include/configs/sunxi-common.h likely forgotten in:
	commit abc3e4df59 ("sunxi: Convert SUNXI_EMAC to Kconfig")

Signed-off-by: Artturi Alm <artturi.alm@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-11-09 14:39:09 +05:30
Benoît Thébaudeau
bcfb365375 mmc: fsl_esdhc: Fix PIO timeout
The following error has been observed on i.MX25 with a high-speed SDSC
card:
    Data Write Failed in PIO Mode.

It was caused by the timeout set on PRSSTAT.BWEN, which was triggered
because this bit takes 15 ms to be set after writing the first block to
DATPORT with this card. Without this timeout, all the blocks are
properly written.

This timeout was implemented by decrementing a variable, so it was
depending on the CPU frequency. Fix this issue by setting this timeout
to a long enough absolute duration (500 ms).

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-11-07 10:26:27 +01:00
Jagan Teki
cc65e354fe i.MX6: engicam: Fix MAINTAINERS/README
- Update newly added include/configs file in MAINTAINERS
- Update newly added defconfig file in README

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-11-07 10:13:39 +01:00
Fabio Estevam
b2e6ad451b mx51: Select the ESDHC_A001 erratum
When a high speed card is connected to mx51evk the following error is seen:

U-Boot 2017.11-rc2 (Oct 18 2017 - 13:49:26 -0200)

CPU:   Freescale i.MX51 rev3.0 at 800 MHz
Reset cause: POR
Board: MX51EVK
DRAM:  512 MiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
*** Warning - read failed, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   FEC
Hit any key to stop autoboot:  0
=> saveenv
Saving Environment to MMC...
Writing to MMC(0)... failed

The root cause for the failure is the eSDHC-A001 erratum:

"eSDHC-A001 : Data timeout counter (SYSCTL[DTOCV]) is not reliable for
values of 0x4,0x8, and 0xC" that is listed
on some PowerArchitecture chips:
https://www.nxp.com/files-static/32bit/doc/errata/MPC8379ECE.pdf

Even though eSDHC-A001 is not documented on the i.MX51 errata document,
I have confirmed with the NXP design team that this erratum does affect
i.MX51, so fix the problem by selecting SYS_FSL_ERRATUM_ESDHC_A001
at SoC level.

The i.MX51 ts4800 board already selects this option, but it is better
to move this selection to the i.MX51 SoC level instead.

Successfully tested with a high speed SD card on a mx51evk board.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
2017-11-07 10:13:11 +01:00
Fabio Estevam
5d09c27138 mx25: Select the ESDHC_A001 erratum
When a high speed card is connected to mx25 the following error is seen:

U-Boot 2017.11-rc2-00104-gb79372a (Oct 31 2017 - 11:02:22 -0200)

CPU:   Freescale i.MX25 rev1.2 at 399 MHz
Reset cause: POR
Board: MX25PDK
I2C:   ready
DRAM:  64 MiB
No arch specific invalidate_icache_all available!
MMC:   FSL_SDHC: 0
*** Warning - read failed, using default environment
In:    serial
Out:   serial
Err:   serial
Net:   FEC
Hit any key to stop autoboot:  0
=> saveenv
Saving Environment to MMC...
Writing to MMC(0)... failed

, which prevents any usage of the SD card.

The root cause for the failure is the eSDHC-A001 erratum:

"eSDHC-A001 : Data timeout counter (SYSCTL[DTOCV]) is not reliable for
values of 0x4,0x8, and 0xC" that is listed
on some PowerArchitecture chips:
https://www.nxp.com/files-static/32bit/doc/errata/MPC8379ECE.pdf

Even though eSDHC-A001 is not documented on the i.MX25 errata document,
I have confirmed with the NXP design team that this erratum does affect
i.MX25, so fix the problem by selecting SYS_FSL_ERRATUM_ESDHC_A001
at SoC level.

Successfully tested with a high speed SD card on a mx25pdk board.

Suggested-by: Benoît Thébaudeau <benoit@wsystem.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Tested-by: Otavio Salvador <otavio@ossystems.com.br> # mx25pdk
2017-11-07 10:13:00 +01:00
Fabio Estevam
07df697e14 mx25: Move MX25 selection to Kconfig
The motivation for moving MX25 selection to Kconfig is to be
able to better handle MX25 specific errata, so that an errata option
can be selected at SoC level instead of board level.

This selection method also aligns with the way other i.MX SoCs are
selected in U-Boot.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
2017-11-07 10:12:50 +01:00
Kever Yang
021a8ae00a rockchip: remove SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR from defconfig
Use default value 0x4000 for SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR instead
of define a new one.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-07 09:16:58 +01:00
Kever Yang
73e6dbe855 rockchip: doc: update U-Boot location info
Update rockchip U-Boot location to 0x4000/16384.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-07 09:16:57 +01:00
Kever Yang
8f4d62b403 spl: set SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR to 0x4000 for rockchip
Rockchip use a 'loader2' partition for U-Boot, so u-boot.bin or
u-boot.itb load by SPL need to locate at0x4000. Detail here:
http://opensource.rock-chips.com/wiki_Boot_option

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-07 09:16:57 +01:00
Klaus Goger
b5557ffc0f rockchip: board: puma_rk3399: make env location selectable via Kconfig
The environment storage location is selectable via Kconfig. We support
eMMC, SD and SPI-NOR as location for U-Boot. This adds support to store
the environment in the SPI-NOR additional to the default eMMC location.

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-07 09:16:57 +01:00
Klaus Goger
4f70039b36 rockchip: dts: rk3399: change sd-card io voltage to 3.0V
The VCC_SD and VCC_SDIO rail should only be powered up to 3.0V on RK3399
platforms.

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-07 09:16:57 +01:00
Klaus Goger
366812fa26 rockchip: dts: Use defines for pin names in rk3399-puma.dtsi and rk3368-lion.dts
pinctrl/rockchip.h provides defines that map pin numbers to pin names.
Use them to make the dts more human readable.

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-07 09:16:57 +01:00
Philipp Tomsich
b1e1ce2cd4 rockchip: dts: rk3399-puma: update USB configuration
This change updates the USB configuration for the RK3399-Q7 in the DTS:
 * fixes the OTG board configuration by enabling it ('okay')
 * improves the speed of 'usb start' by disabling the unused EHCI/OHCI
   controllers

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2017-11-07 09:16:57 +01:00
Philipp Tomsich
f2a9513168 rockchip: dts: rk3399-puma: update usbhub_enable regulator
To correctly model the usbhub_enable regulator for U-Boot, we need
to change the settings to:
 * the GPIO polarity is GPIO_ACTIVE_LOW
 * should be set to inactive (enable-active-low) when boot-on settings
   are applied
 * it can be changed at runtime (i.e. remove the always-on)

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2017-11-07 09:16:57 +01:00
Philipp Tomsich
df1e6212f9 rockchip: dts: rk3399-puma: fix the modelling of BIOS_DISABLE
The fixed regulator for overriding BIOS_DISABLE had been modelling
backwards (i.e. the GPIO polarity and the enable-active-low/high
property had both been inverted), causing the 'regulator' command
to always print/expect 'disabled'/'enabled' backwards.

This fixes the mix-up and models it correctly:
 * the GPIO is low-active
 * the regulator should be enabled (enable-active-high) during
   boot-on initialisation

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2017-11-07 09:16:56 +01:00
Kever Yang
be942f2e0d rockchip: config: use common CONFIG_ENV_SIZE for all SoCs
All Rockchip SoCs use 32KB as CONFIG_ENV_SIZE.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-07 09:16:56 +01:00
Kever Yang
c742043f74 rockchip: config: sync the ENV offset from rockchip legacy U-Boot
Using the ENV offset from rockchip legacy U-Boot for all SoCs,
the offset is 4MB-32KB

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-07 09:16:56 +01:00
Kever Yang
5d2f1d8271 rockchip: rock: remove CONFIG_ENV_OFFSET
We use the same default ENV setting in rockchip_common.h for all SoC.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-07 09:16:56 +01:00
Tom Rini
7a69604bce Prepare v2017.11-rc4
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-11-06 18:25:37 -05:00
Chris Brandt
fc85605018 cosmetic: rmobile: renesas spelled wrong
Renesas was spelled wrong.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
2017-11-06 09:59:03 -05:00
Jan Kundrát
b95a5190ba Do not attempt to use the systemwide libfdt
U-Boot bundles a patched copy of libfdt, so it's wrong to attempt to
include it <like/this>. This breaks the build for me when I have dtc
fully installed in my host -- as happened earlier tonight with
Buildroot, for example.

There are several other occurrences throughout the code where '<libfdt'
matches. I'm not modifying these because I have no clue why the
<systemwide> include style is being used -- IMHO wrongly.

Signed-off-by: Jan Kundrát <jan.kundrat@cesnet.cz>
2017-11-06 09:59:02 -05:00
Angelo Dureghello
6ba2da90de m68k: doc: update outdated documentation
Update m68k documentation to reflect the current ColdFire
architecture support status.

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
2017-11-06 09:59:02 -05:00
Shawn Guo
8f7102cf6b disk: part_dos: fix part_get_info_extended() function
The check in part_get_info_extended() for a successful partition
searching misses a condition for extended partition. In case of
(ext_part_sector == 0), we should anyway mark the partition as found,
even if it's an extended partition, i.e. (is_extended(pt->sys_ind) == 0).
Otherwise, the extended partition (type 0x0f) will never be identified,
and the following recursive call to part_get_info_extended() will get a
wrong 'part_num' and 'which_part' parameter.  In the end, all those
partitions in extended table will not be identified.

Let's add the missing OR condition of (ext_part_sector == 0) for
is_extended() check to fix the problem.

The issue is discovered by running fastboot flash to an extended
partition on eMMC.

  $ fastboot flash mmcsda5 cache.img
  target reported max download size of 536870912 bytes
  sending 'mmcsda5' (18796 KB)...
  OKAY [  2.144s]
  writing 'mmcsda5'...
  FAILED (remote: cannot find partition)
  finished. total time: 2.261s

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2017-11-06 09:59:01 -05:00
Lukasz Majewski
bb021013ba gpt: Use cache aligned buffers for gpt_h and gpt_e
Before this patch one could receive following errors when executing
"gpt write" command on machine with cache enabled:

display5 factory > gpt write mmc ${mmcdev} ${partitions}
Writing GPT:
CACHE: Misaligned operation at range [4ef8f7f0, 4ef8f9f0]
CACHE: Misaligned operation at range [4ef8f9f8, 4ef939f8]
CACHE: Misaligned operation at range [4ef8f9f8, 4ef939f8]
CACHE: Misaligned operation at range [4ef8f7f0, 4ef8f9f0]
success!

To alleviate this problem - the calloc()s have been replaced with
malloc_cache_aligned() and memset().

After those changes the buffers are properly aligned (with both start
address and size) to SoC cache line.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-11-06 09:59:01 -05:00
Masahiro Yamada
76b9cbab25 tools: image: fix message when fail to add verification data for config
This function is called when signing configuration nodes.  Adjust
the error message.

I do not know why we do not need to show the error message in case of
ENOSPC.  Remove the if-conditional that seems unnecessary.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-06 09:59:01 -05:00
Masahiro Yamada
6793d017a7 tools: image: allow to sign image nodes without -K option
If -K option is missing when you sign image nodes, it fails with
an unclear error message:

  tools/mkimage Can't add hashes to FIT blob: -1

It is hard to figure out the cause of the failure.

In contrast, when you sign configuration nodes, -K is optional because
fit_config_process_sig() returns successfully if keydest is unset.
Probably this is a preferred behavior when you want to update FIT with
the same key; you do not have to update the public key in this case.

So, this commit changes fit_image_process_sig() to continue signing
without keydest.  If ->add_verify_data() fails, show a clearer error
message, which has been borrowed from fit_config_process_sig().

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-06 09:59:00 -05:00
Masahiro Yamada
1d88a99d1b tools: image: fix "algo" property of public key for verified boot
The "algo_name" points to a property in a blob being edited.  The
pointer becomes stale when fit_image_write_sig() inserts signatures.
Then crypto->add_verify_data() writes wrong data to the public key
destination.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-06 09:59:00 -05:00
Stephen Warren
ac122efdb6 test/py: regenerate persistent GPT image if code changes
test_gpt generates a persistent disk image which can be re-used across
multiple test runs. Currently, if the Python code that generates the disk
image change, the image is not regenerated, which could cause test
failures e.g. if a test was updated to expect some new partition name or
size, yet the persistent disk image contained the old name or size. This
change introduces functionality to regenerate the disk image if the
instructions to generate the image have changed.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2017-11-06 09:59:00 -05:00
Stefan Agner
84d46e7e89 tools: env: allow to print U-Boot version
The fw_env utility family has a default environment compiled in
which ties it quite strongly to the U-Boot source/config it has
been built with. Allow to display the U-Boot version it has been
built with using the -v/--version argument.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2017-11-06 09:58:59 -05:00
Masahiro Yamada
8ec87df376 image-sig: use designated initializers for algorithm
Designated initializers are more readable because we do not
have to check the order in the struct definitions.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-06 09:58:59 -05:00
Tom Rini
79df00fdb4 MAINTAINERS: Add missing boards and config entries
As part of my usual round of build testing, output about missing
MAINTAINERS information was not logged, and thus often overlooked.
Correct that mistake by ensuring that I log the output of
genboardscfg.py every time.  As part of that, address a number of
missing MAINTAINERS entires.  In the case of a missing file, I have put
the original submitter down.  In the rest of the cases I have added the
config (and sometimes relevant header file) to the existing set of file
globs.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-11-06 09:58:51 -05:00
Patrice Chotard
05cd11948e tpm: st33zp24: fix STMicroelectronics copyright
Uniformize STMicroelectronics copyrights header

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-06 09:51:01 -05:00
Patrice Chotard
e36591c350 spear: fix STMicroelectronics copyright
Uniformize STMicroelectronics copyrights headers for SPEAR
related code.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-06 09:51:01 -05:00
Patrice Chotard
1537d38619 stv0991: fix STMicroelectronics copyright
Uniformize STMicroelectronics copyrights headers for STV0991
related code.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-06 09:51:01 -05:00
Patrice Chotard
3bc599c956 stm32: fix STMicroelectronics copyright
Uniformize STMicroelectronics copyrights headers for STM32
related code.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-06 09:51:01 -05:00
Patrice Chotard
fb48bc448c sti: fix STMicroelectronics copyright
Uniformize all STMicroelectronics copyrights headers for STi
related code.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-06 09:51:01 -05:00
Tom Rini
57270eca55 Merge git://git.denx.de/u-boot-samsung 2017-11-06 09:24:55 -05:00
Icenowy Zheng
460b15adc9 video: sunxi: de2: fix SimpleFB node creation when HDMI not initialized
When HDMI is not initialized (e.g. no monitor is plugged), the current
SimpleFB code will still create a broken SimpleFB node.

Detect whether HDMI is initialized when creating SimpleFB node.

Fixes: be5b96f0e4 ("sunxi: setup simplefb for Allwinner DE2")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-11-06 13:43:28 +05:30
Dongjin Kim
568197fa03 ARM: dts: exynos: fix property values of LDO15/17 for ODROID-XU3/4
Looking at the schematic, LDO15 and LDO17 are tied as a power source of a
builtin network chipset. The voltage on LDO15 is corrected to 3.3V and the
name of LDO17 is corrected to "vdd_ldo17".

Signed-off-by: Dongjin Kim <tobetter@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2017-11-06 16:59:32 +09:00
Tom Rini
43ede0bca7 Kconfig: Migrate MTDIDS_DEFAULT / MTDPARTS_DEFAULT
We move all instances of CONFIG_MTDIDS_DEFAULT and
CONFIG_MTDPARTS_DEFAULT from the header files to the defconfig files.
There's a few cases here where we need to expand upon what was in the
header file.

Tested-by: Adam Ford <aford173@gmail.com>  #omap3_logic
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-11-05 11:21:35 -05:00
Tom Rini
804dcf771a Merge tag 'xilinx-fixes-for-v2017.11' of git://www.denx.de/git/u-boot-microblaze
Xilinx fix for v2017.11

- Fix ceva sata initialization
2017-11-03 10:02:29 -04:00
Michal Simek
cba64a2a73 scsi: ceva: Start port in probe
The patch:
"dm: ahci: Unwind the confusing init code"
(sha1: 7cf1afce7f)
introduce bug for ceva sata because port didn't start.
On the other hand the dwc_ahci.c was fixed correctly.
Do the same change for ceva too.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
2017-11-03 09:31:27 +01:00
Tom Rini
a0cdb534e1 Merge git://git.denx.de/u-boot-rockchip 2017-11-01 09:32:14 -04:00
Philipp Tomsich
ed6be4fcdf rockchip: lion-rk3368: defconfig: select PHY_MICREL_KSZ90X1
The RK3368-uQ7 uses a KSZ9031 PHY on-module.  Enable PHY_MICREL_KSZ90X1
in the associated defconfig.

References: da3b9e7f ("Move PHY_MICREL and PHY_MICREL_KSZ90X1 to Kconfig")
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-01 11:21:32 +01:00
Philipp Tomsich
18a158979c rockchip: puma-rk3399: defconfig: select PHY_MICREL_KSZ90X1
The RK3368-uQ7 uses a KSZ9031 PHY on-module.  Enable PHY_MICREL_KSZ90X1
in the associated defconfig (this somehow got lost with da3b9e7f).

References: da3b9e7f ("Move PHY_MICREL and PHY_MICREL_KSZ90X1 to Kconfig")
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-01 11:21:32 +01:00
Kever Yang
4c1a60c597 rockchip: evb-rk3328: remove CONFIG_ENV_OFFSET
Remove CONFIG_ENV_OFFSET for there already have one in rockchip_common.h

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-01 11:21:32 +01:00
Kever Yang
36de37f5ca rockchip: rk3328: fix rockchip_get_cru api
The API for get priv pointer is wrong, fix it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-01 11:21:32 +01:00
Kever Yang
9f636a249c rockchip: rk3399: init CPU clock when rkclk_init()
Init the CPU and its buses to speed up the boot time.
Move rkclk_init() to a place after rk3399_configure_cpu has defined
at the same time, or else there will be a warning.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-01 11:21:32 +01:00
Klaus Goger
6e278a8c1c rockchip: configs: only add available BOOT_TARGET_DEVICES
BOOT_TARGET_DEVICES should only be added if the corresponding u-boot
command is enabled.

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-01 11:21:32 +01:00
Klaus Goger
e3e842f17c rockchip: configs: use rockchip-common.h for rk3368
rockchip-common.h already defines values that are missing from
rk3368_common.h

For example BOOT_TARGET_DEVICES was defined empty and therefore
distroboot had no boot targets.

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-01 11:21:32 +01:00
Tom Rini
3c1af17c5e Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2017-10-31 08:14:53 -04:00
Fabio Estevam
40b0dae151 mx6slevk: Call gpio_request()
We should call gpio_request() prior to reading the GPIO value.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-10-31 11:35:01 +01:00
Fabio Estevam
0d6a41edb5 udoo: Remove cpu type check prior to setup_sata()
Inside setup_sata() there is a cpu type check, so there is no need to
do this check in the board file.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-10-31 11:13:56 +01:00
Fabio Estevam
d7f7eb749f wandboard: Remove cpu type check prior to setup_sata()
Inside setup_sata() there is a cpu type check, so there is no need to
do this check in the board file.

This also brings the benefit to allowing setup_sata() to be called for the
mx6qp wandboard variant.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-10-31 11:13:33 +01:00
Marek Vasut
506abdb4ee ARM: imx6: Enable UMS and DFU on DHCOM i.MX6 PDK
Enable UMS and DFU, so that the eMMC can be accessed via the
USB gadget port on the board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2017-10-31 11:11:10 +01:00
Peng Fan
27dc324a10 imx: mx6slevk: cleanup board usb code
Since DM_USB enabled, no need the usb code in board file.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-10-31 11:10:41 +01:00
Fabio Estevam
723dfe8f02 mx6slevk: Fix MMC breakage for the SPL target
Commit 001cdbbb32 ("imx: mx6slevk: enable more DM drivers") breaks
MMC support in U-Boot proper on the mx6slevk_spl_defconfig target:

U-Boot SPL 2017.09-00396-g6ca43a5 (Oct 01 2017 - 16:20:18)
Trying to boot from MMC1

U-Boot 2017.09-00396-g6ca43a5 (Oct 01 2017 - 16:20:18 -0300)

CPU:   Freescale i.MX6SL rev1.0 792 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 33C
Reset cause: POR
Board: MX6SLEVK
I2C:   ready
DRAM:  1 GiB
MMC:   FSL_SDHC: 0
MMC Device 1 not found
*** Warning - No MMC card found, using default environment

As mx6slevk_spl_defconfig does not use CONFIG_DM_MMC and its
board file does not register the mmc controller for U-Boot proper,
let's fix this by adding CONFIG_DM_MMC=y and device tree support.

While at it, add more DM drivers, so that it becomes closer to
mx6slevk_defconfig.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-10-31 11:10:18 +01:00
Fabio Estevam
e1f0715f64 wandboard: Add support for the MX6QP variant
Add support for the latest MX6QP wandboard variant.

Based on Richard Hu's work from Technexion's U-Boot tree.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-10-31 11:01:38 +01:00
Stefan Agner
c0f432c377 configs: vf610: increase maximum size and enforce correct limit
On Vybrid SoCs U-Boot gets loaded into GFX SRAM which is 512KiB.
Currently 32KiB is reserved for the IMX header. However, this is
not reflected in the size limit. In v2017.11-rc2 the actual size
limit (512KiB-32KiB) has been reached for Colibri VF61, which
lead to a successful build of U-Boot but not a working binary.

The IMX header is much smaller than 32KiB, typically around 1KiB.
Decrease the reserved size to 4KiB and specify the correct U-Boot
size limit. Apply this new base address and limit for all Vybrid
based boards.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2017-10-31 11:00:54 +01:00
Tom Rini
da125b72fd Prepare v2017.11-rc3
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-30 21:28:51 -04:00
Fabio Estevam
41b93679fd net: fec_mxc: Change "error frame" message to debug level
As reported by Jonathan Gray:

"After the recent changes to add SimpleNetworkProtocol to efi_loader
when booting off mmc via an efi payload that doesn't use
SimpleNetworkProtocol U-Boot's fec_mxc driver will now display
various "error frame" messages.
....
MMC Device 1 not found
MMC Device 2 not found
MMC Device 3 not found
Scanning disks on sata...
Found 6 disks
reading efi/boot/bootarm.efi
67372 bytes read in 32 ms (2 MiB/s)
## Starting EFI application at 12000000 ...
>> OpenBSD/armv7 BOOTARM 1.0
error frame: 0x8f57ec40 0x00003d74
error frame: 0x8f57ec40 0x00007079
error frame: 0x8f57ec40 0x00006964
error frame: 0x8f57ec40 0x00006f6f
error frame: 0x8f57ec40 0x0000726f
error frame: 0x8f57ec40 0x00002074
error frame: 0x8f57ec40 0x00006f6f"

Heinrich Schuchardt explains:

"A receive FIFO overrun can be expected if network packages are not
processed.
With the network patches we check if a package is available quite often."

Move the "error frame" messages to debug level so that a clean output
log can be seen.

Reported-by: Jonathan Gray <jsg@jsg.id.au>
Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-10-30 18:57:42 +01:00
Fabio Estevam
c46305a829 imx: Fix regression with CONFIG_DM_MMC=y
When CONFIG_DM_MMC=y, CONFIG_BLK should be selected, otherwise the
SD/eMMC card cannot be used.

Also, select CONFIG_DM_USB=y when CONFIG_USB=y to avoid build failure.

Tested on mx6slevk, mx7dsabresd and mx6ullevk.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Adam Ford <aford173@gmail.com>
Tested-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Tested-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-10-30 18:54:38 +01:00
Tom Rini
73dd818cc4 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-30 12:58:33 -04:00
Heinrich Schuchardt
b79372ae94 scripts/get_maintainer.pl: enable find_maintainer_files
Many MAINTAINERS files are in subdirectories.
We should enable searching these.

Reported-by: Walt Feasel <waltfeasel@gmail.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-10-29 10:13:10 -04:00
Heinrich Schuchardt
9ef2684c03 checkpatch: Support wide strings
Allow prefixing typical strings with L for wide strings

Patch originally by Joe Perches
https://lkml.org/lkml/2017/10/17/1117

Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-10-29 10:13:10 -04:00
Tom Rini
2d5e6b4aac Merge git://git.denx.de/u-boot-video 2017-10-29 10:11:08 -04:00
Dongjin Kim
9b73bcc6c3 exynos: video: fix typo in DisplayPort driver
Signed-off-by: Dongjin Kim <tobetter@gmail.com>
CC: Simon Glass <sjg@chromium.org>
CC: Minkyu Kang <mk7.kang@samsung.com>
2017-10-29 14:33:55 +01:00
Niko Mauno
963be68937 video/da8xx-fb: Cache-align memory allocations
Resort to malloc_cache_aligned() rather than malloc() which also removes
'CACHE: Misaligned operation at range' warnings.

Signed-off-by: Niko Mauno <niko.mauno@vaisala.com>
2017-10-29 14:33:24 +01:00
Alexander Graf
405835645a efi_loader: Disable env_save() call on boot
With the introduction of EFI variable support, we also wanted to persist
these EFI variables. However, the way it was implemented we ended up
persisting all U-Boot environment variables on every EFI boot.

That could potentially lead to unexpected side effects because variables
that were not supposed to be written to persisted env get written. It also
means we may end up writing the environment more often than we should.

For this release, let's just disable EFI variable persistence and instead
implement it properly for the next one.

Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Fixes: ad644e7c18 ("efi_loader: efi variable support")
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-10-29 07:59:08 -04:00
Tom Rini
bb3d9ed3a9 Merge git://git.denx.de/u-boot-fsl-qoriq 2017-10-27 21:59:10 -04:00
Sumit Garg
9b3f40ad09 armv8: sec_firmware: Add support for loadables in FIT
Enable support for loadables in SEC firmware FIT image. Currently
support is added for single loadable image.

Brief description of implementation:
  Add two more address pointers (loadable_h, loadable_l) as arguments to
  sec_firmware_init() api.
  Create new api: sec_firmware_checks_copy_loadable() to check if loadables
  node is present in SEC firmware FIT image. If present, verify loadable
  image and copies it to secure DDR memory.
  Populate address pointers with secure DDR memory addresses where loadable
  is copied.

Example use-case could be trusted OS (tee.bin) as loadables node in SEC
firmware FIT image.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:47:14 -07:00
Sumit Garg
9781d9ff5f armv8: layerscape: Allocate 66 MB DDR for secure memory
Change DDR allocated for secure memory from 2 MB to 66 MB. This
additional 64 MB secure memory is required for trusted OS running
in Trusted Execution Environment using ARMv8 TrustZone.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:47:14 -07:00
Ran Wang
18ed801e10 armv8: ls1088aqds: Enable USB command on QDS for qspi-boot
Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:47:14 -07:00
Ran Wang
d4c746c7b1 armv8: ls1088ardb: Enable USB command RDB qspi-boot
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:47:06 -07:00
Ran Wang
90be2fe37e arm: layerscape: Remove CONFIG_USB_MAX_CONTROLLER_COUNT
Because COMFIG_DM_USB has been enabled and will not use it anymore.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:44:31 -07:00
Ran Wang
420b0eba3c usb: host: Move CONFIG_XHCI_FSL to Kconfig
use Kconfig to select xhci accordingly.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:44:06 -07:00
Ran Wang
4417e83495 arm64: layerscape: Move CONFIG_HAS_FSL_XHCI_USB to Kconfig
Use Kconfig to select QE-HDLC and USB pin-mux.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:43:57 -07:00
Ashish Kumar
2af1b08a1a armv8: ls1088aqds: Change phy mode to PHY_INTERFACE_MODE_RGMII_ID
Since TX delay is now enabled only in PHY_INTERFACE_MODE_RGMII_ID
PHY_INTERFACE_MODE_RGMII_TXID.

These change where introduced in phy driver in commit 05b29aa0cb
("net: phy: realtek: fix enabling of the TX-delay for RTL8211F").

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:41:12 -07:00
Yuantian Tang
b584510f07 armv8: configs: ls1012a: correct the generic timer frequency
On ls1012a soc, core clock source frequency is fixed at 100Mhz.
Generic timer frequency is core clock source divided by 4, which
is 25Mhz.

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:39:49 -07:00
Ashish Kumar
f89072ab92 armv8: ls1088: Move CONFIG_ENV_IS_IN_SPI_FLASH to defconfig
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:39:34 -07:00
Prabhakar Kushwaha
a572fb6bdd driver: fsl-mc: use calloc instead malloc
Memory allocated via malloc is not guaranteed to be zeroized.
So explicitly use calloc instead of malloc.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:38:29 -07:00
Masahiro Yamada
33fe271278 AT91: remove CONFIG_PMECC_INDEX_TABLE_OFFSET
This macro is defined, but not referenced by anyone.

I did not touch config_whitelist.txt - the CONFIG will be dropped
by the next re-sync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-27 08:52:22 -04:00
Masahiro Yamada
268d05f552 exynos: remove CONFIG_LCD_MENU_BOARD
This macro is defined, but not referenced by anyone.

I did not touch config_whitelist.txt - the CONFIG will be dropped
by the next re-sync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
2017-10-27 08:52:22 -04:00
Masahiro Yamada
795428fc67 net: remove CONFIG_NET_MULTI
This macro is defined, but not referenced by anyone.

I did not touch config_whitelist.txt - the CONFIG will be dropped
by the next re-sync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:52:22 -04:00
Masahiro Yamada
a28b90b787 mpc85xx: xpedite550x: remove CONFIG_FDT_FIXUP_PCI_IRQ
This macro is defined, but not referenced by anyone.

I did not touch config_whitelist.txt - the CONFIG will be dropped
by the next re-sync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-27 08:52:22 -04:00
Masahiro Yamada
1c0eece3d8 AM33XX: etamin: remove CONFIG_DFU_MTD
This macro is defined, but not referenced by anyone.

I did not touch config_whitelist.txt - the CONFIG will be dropped
by the next re-sync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-27 08:52:22 -04:00
Masahiro Yamada
eac89575af MX28: remove CONFIG_DEFAULT_SPI_CS
This macro is defined, but not referenced by anyone.

I did not touch config_whitelist.txt - the CONFIG will be dropped
by the next re-sync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-27 08:52:22 -04:00
Masahiro Yamada
00687674a9 exynos: remove CONFIG_CORE_COUNT
This macro is defined, but not referenced by anyone.

I did not touch config_whitelist.txt - the CONFIG will be dropped
by the next re-sync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
2017-10-27 08:52:22 -04:00
Masahiro Yamada
08019ccf9c omap4: sdp4430: match the #endif comment to #ifdef
This comment creates a wrong entry in config_whitelist.txt.

I did not touch config_whitelist.txt - the CONFIG will be dropped
by the next re-sync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-27 08:52:22 -04:00
Masahiro Yamada
a0dd989ffb SOCFPGA: remove CONFIG_AUTONEG_TIMEOUT
This macro is defined, but not referenced by anyone.

I did not touch config_whitelist.txt - the CONFIG will be dropped
by the next re-sync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-27 08:52:22 -04:00
Masahiro Yamada
ac47750460 ARC: remove CONFIG_ARC_UART_BASE
This macro is defined, but not referenced by anyone.

I did not touch config_whitelist.txt - the CONFIG will be dropped
by the next re-sync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-27 08:52:22 -04:00
Masahiro Yamada
e5fa2b368c sh7734: remove CONFIG_553MHZ_MODE
This macro only appears in commented-out lines.  It is not referenced
by anyone.

I did not touch config_whitelist.txt - the CONFIG will be dropped
by the next re-sync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-27 08:52:22 -04:00
Masahiro Yamada
020e701d8d mpc85xx: freescale: remove CONFIG_ADDR_STREAMING
This macro is defined, but not referenced by anyone.

I did not touch config_whitelist.txt - the CONFIG will be dropped
by the next re-sync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:52:22 -04:00
Masahiro Yamada
8e07bb2b2b omap4: sdp4430: remove CONFIG_4430SDP
This macro is defined, but not referenced by anyone.

I did not touch config_whitelist.txt - the CONFIG will be dropped
by the next re-sync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-27 08:52:22 -04:00
Masahiro Yamada
b7e4dadfd9 IMX: novena: remove CONFIG_I2C_MXC
This macro is defined, but not referenced by anyone.

I did not touch config_whitelist.txt - the CONFIG will be dropped
by the next re-sync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Heiko Schocher<hs@denx.de>
2017-10-27 08:52:22 -04:00
Masahiro Yamada
af6715bfb4 i2c: fti2c010: remove unused/unmaintained driver
CONFIG_SYS_I2C_FTI2C010 is not enabled by anyone.

Commit 2852709676 ("dm: i2c: Add a note to I2C drivers which need
conversion") prompted to convert this driver to DM before June 2017,
but not converted yet.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Heiko Schocher <hs@denx.de>
2017-10-27 08:52:22 -04:00
Masahiro Yamada
1d14cbdcd8 i2c: adi_i2c: remove left-over Blackfin I2C driver
This driver was used by Blackfin boards, but Blackfin support is
gone.  There is no user of this driver.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Heiko Schocher <hs@denx.de>
2017-10-27 08:52:22 -04:00
Tom Rini
ae6ac0a06e Merge git://git.denx.de/u-boot-x86 2017-10-27 08:50:16 -04:00
Vasily Khoruzhick
1d7eef3f3f sunxi: video: add LCD support to DE2 driver
Extend DE2 driver with LCD support. Tested on Pinebook which is based
on A64 and has ANX6345 eDP bridge with eDP panel connected to it.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
[agust: rebased v5 on u-boot-video/master]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-10-27 09:44:48 +02:00
Vasily Khoruzhick
79f285ddeb sunxi: video: split out PLL configuration code
It will be reused in new DM LCD driver.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2017-10-27 09:39:19 +02:00
Bin Meng
411898dc87 x86: acpi: Put sleepstates.asl to the common place
The supported sleep states are generic on Intel processors. Move the
ASL definition to the common place.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-27 15:13:47 +08:00
Bin Meng
dc80d3b230 x86: fsp: graphics: Add some notes about the graphics info hob
On some platforms (eg: Braswell), the FSP will not produce the
graphics info HOB unless you plug some cables to the display
interface (eg: HDMI) on the board. Add such notes in the FSP
video driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-27 15:13:47 +08:00
Bin Meng
4c9f4c5ee4 x86: braswell: cherryhill: Update dts for SPI lock down
Intel Braswell FSP requires SPI controller settings to be locked down,
let's do this in the chrryhill.dts and remove previous Kconfig option.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-27 15:13:47 +08:00
Bin Meng
ab20107468 spi: ich: Lock down controller settings if required
Some Intel FSP (like Braswell) does SPI lock-down during the call
to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done,
it's bootloader's responsibility to configure the SPI controller's
opcode registers properly otherwise SPI controller driver doesn't
know how to communicate with the SPI flash device.

Rather than passively doing the opcode configuration, let's add a
simple DTS property "intel,spi-lock-down" and let the driver call
the opcode configuration function if required by such FSP.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-27 15:13:47 +08:00
Bin Meng
fb2c53091f Revert "x86: fsp: Configure SPI opcode registers before SPI is locked down"
This reverts commit 1e6ebee667.

It's not appropriate to call the Intel SPI driver specific stuff in
the FSP codes. We may add a simple DTS property "intel,spi-lock-down"
and let the Intel SPI driver call these stuff instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-27 15:13:47 +08:00
Bin Meng
aa9c5956c9 x86: Fix ACPI resume dependency to MRC cache
In an S3 resume path, MRC cache is mandatory. Enforce the dependency
in the Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-27 15:13:47 +08:00
Bin Meng
3a856473fd env: x86: braswell: Set ENV_IS_IN_SPI_FLASH as default
Imply does not work for a Kconfig choice. Update ENV_IS_IN_SPI_FLASH
to be the default one for Intel Braswell.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-27 15:13:47 +08:00
Bin Meng
4a5a7fcac2 x86: braswell: Fix unexpected crash during Linux kernel boot
It was observed that when booting Linux kernel on Intel Cherry Hill
board, unexpected crash happens quite randomly. Sometimes kernel
just oops, while sometimes kernel throws MCE errors and hangs:

  mce: [Hardware Error]: Machine check events logged
  mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank 4: c400000000010151
  mce: [Hardware Error]: TSC 0 ADDR 130f3f2c0
  mce: [Hardware Error]: PROCESSOR 0:406c3 TIME 1508160686 SOCKET 0 APIC 0 microcode 363

This looks like a hardware error per mcelog. After debugging, it
seems turning off turbo mode on the processor does not expose this
behavior, although U-Boot runs OK with turbo mode on. Suspect it is
related to an errata of Braswell processor.

To fix this, remove the Braswell cpu driver which does the turbo
mode configuration, and switch to use the generic cpu-x86 driver.
Also there is a configuration option in the FSP that turns on the
turbo mode and that has been turned off too.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-27 15:13:47 +08:00
Bin Meng
7995dd3782 x86: galileo: Fix boot failure
With latest codes on mainstream master, Intel Galileo board does not
boot unfortunately. Git biset leads to b383d6c0 "bootstage: Convert
to use malloc()".

Disable bootstage support to make it boot again. The root cause needs
to be investigated however.

Fixes: b383d6c0 ("bootstage: Convert to use malloc()")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-27 15:13:47 +08:00
Tom Rini
ddeaaefde3 Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2017-10-26 11:50:33 -04:00
Vasily Khoruzhick
491041c749 video: add anx6345 DM driver
This is a eDP bridge similar to ANX9804, it allows to connect eDP panels
to the chips that can output only parallel signal

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
[agust: fixed most checkpatch errors/warnings]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-10-26 15:43:11 +02:00
Vasily Khoruzhick
24bf59d024 video: anx9804: split out registers definitions into a separate header
This header will be used in anx6345 driver

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
[agust: moved header to drivers/video]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-10-26 14:31:42 +02:00
Vasily Khoruzhick
fdb5525572 dm: video: bridge: add operation to read EDID
Add an operation to read EDID, since bridge may have ability to read
EDID from the panel that is connected to it, for example LCD<->eDP bridge.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2017-10-26 14:17:01 +02:00
Icenowy Zheng
be5b96f0e4 sunxi: setup simplefb for Allwinner DE2
As the support of EFI boot on Allwinner H3 is broken, we still need to
use simplefb to pass the framebuffer to Linux.

Add code to setup simplefb for Allwinner DE2 driver.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-26 11:57:14 +02:00
Icenowy Zheng
f6bdddc92b video: add an option for video simplefb via DT
Add an option to indicate that the video driver should setup a SimpleFB
node that passes the video framebuffer initialized by U-Boot to the
operating system kernel.

Currently only the Allwinner DE driver uses this option, and the
definition of this option in the sunxi-common.h config header is
converted to an imply of this option from CONFIG_VIDEO_SUNXI.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-26 11:53:39 +02:00
Icenowy Zheng
e5f92467d7 video: sunxi: extract simplefb match code to a new file
As the DE2 simplefb setup code can also benefit from the simplefb match
code, extract it to a new source file.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-26 11:51:45 +02:00
Icenowy Zheng
401a3ca0fb sunxi: change the DE1 video option to CONFIG_VIDEO_SUNXI
The sunxi DE1 video option used to be CONFIG_VIDEO, which has the same
name as the "Enable legacy video support" option in
drivers/video/Kconfig.

Change the option name to CONFIG_VIDEO_SUNXI, which is really used by
Makefile under drivers/video/sunxi/, and defined in sunxi-common.h
when CONFIG_VIDEO is selected before this change. Now CONFIG_VIDEO_SUNXI
selects CONFIG_VIDEO and the usages of CONFIG_VIDEO in sunxi Kconfig and
config headers are all converted to use CONFIG_VIDEO_SUNXI.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2017-10-26 11:48:49 +02:00
Maxime Ripard
819f1e081c sunxi: binman: Add U-Boot binary size check
The U-Boot binary may trip over its actual allocated size in the storage.
In such a case, the environment will not be readable anymore (because
corrupted when the new image was flashed), and any attempt at using saveenv
to reconstruct the environment will result in a corrupted U-Boot binary.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-25 10:05:06 +02:00
Maxime Ripard
ce2e44d836 sunxi: Enable THUMB build for the U-Boot binary
We start to get to the limit of our main U-Boot binary size (with some
boards even crossing it). Enable its build using thumb2 to get some extra
room.

Suggested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-25 10:05:06 +02:00
Maxime Ripard
7514069aa3 sunxi: Add support for the Banana Pi M2-Magic
The Banana Pi M2-Magic is a small board with an Allwinner A33, an eMMC, a
wifi chip and some pin headers. Enable support for it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-25 10:05:06 +02:00
Benjamin Young
7dec673ea9 cmd: fastboot: Enable FASTBOOT_FLASH_NAND for SUNXI_NAND devices
Encountered an issue where fastboot can't write to NAND on a CHIP_pro,
the symbol was neither present in the board's config header, nor the
Kconfig, this patch puts it in the Kconfig and defaults on when
SUNXI_NAND is selected.

Signed-off-by: Ben Young <computermouth@crunchbangplusplus.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-25 10:05:06 +02:00
Quentin Schulz
c96f598be7 sunxi: clk: fix N formula for CPUX clocks
As explained in arch/arm/mach-sunxi/clock_sun8i_a83t.c, clk for CPU
clusters is computed as clk = 24*n. However, the current formula is clk
= 24*(n-1).

This results in a clock set to a frequency that isn't specified as
possible for CPUs.

Let's use the correct formula.

Fixes: f542948b1e ("sunxi: clk: add basic clocks for A83T")

Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-10-25 10:05:05 +02:00
Andre Przywara
a722359de4 SPL: SPI: select SPL_SPI_FLASH_SUPPORT on SPL_SPI_SUNXI
The Allwinner SPI flash SPL boot support is guarded by the SPL_SPI_SUNXI
symbol. But despite its generic name, the actual only use case for this
is to provide SPI flash support to the SPL, which requires
CONFIG_SPL_SPI_FLASH_SUPPORT to be defined.
Select this symbol from the SPL_SPI_SUNXI Kconfig definition. This
avoids doing this explicitly in the defconfig, and fixes SPI booting on
the Pine64 SoPine (and -LTS version) and the OrangePi Win board (both with
SPI flash).

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-25 10:05:05 +02:00
Heinrich Schuchardt
4c7a211046 Kconfig: add CONFIG_BROKEN
Provide a Kconfig option that we can use as dependency for
features that are broken. This allows to easily disable them
without removing the code.

As no short text is supplied the option will not appear in
menuconfig.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-23 17:28:18 -04:00
Masahiro Yamada
6af5520fe1 doc: verified-boot: fix crypto algorithm examples
As you see in crypto_algos in common/image-sig.c, the algorithm
should be either "rsa2048" or "rsa4096".  "rs2048" is a typo.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-23 17:28:18 -04:00
Masahiro Yamada
16067e6b87 tools: image: fix node name of signature node in FIT
Both "conf_name" and "sig_name" point to the name of config node.
The latter should be the name of the signature node.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-23 17:28:17 -04:00
Masahiro Yamada
3aca4a44f8 test/py: fix typos in README.md
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2017-10-23 17:28:17 -04:00
Patrick Delaunay
3a2605fa87 cmd: gpt: solve issue for swap and rename command
don't use prettyprint_part_size() in create_gpt_partitions_list()
that avoid to align offset and size to 1 MiB and increase precision for
start and size.
This patch avoid the risk to change partition size and lost data during
rename or swap.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-10-23 17:28:11 -04:00
Patrick Delaunay
0cf02ff612 test/py: gpt: test start LBA for sub-command rename and swap
Add test of first and last LBA in gpt for rename and swap.
Only the name is expected to change, so test 3 columns
for part command
1: first LBA (start)
2: last LBA (end)
3: partition name

After rename, the last LBA change and it is a error in current U-Boot code
+ "first" = 0x7ff : invalid value (<start)
+ "second" = 0x17ff => size increasing !

Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2017-10-23 17:28:08 -04:00
Patrick Delaunay
b61a3b5c8d test/py: gpt: add test for sub-command write
+ test write for one partition on all the device (size=0)
+ test write with disk uuid and 2 partitions

Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2017-10-23 17:27:58 -04:00
Patrick Delaunay
ae0e0228e6 disk: efi: correct the overlap check on GPT header and PTE
the partition starting at 0x4400 is refused with overlap error:
  $> gpt write mmc 0 "name=test,start=0x4400,size=0"
  Writing GPT: Partition overlap
  error!

even if the 0x4400 is the first available offset for LBA35 with default
value:
- MBR=LBA1
- GPT header=LBA2
- PTE= 32 LBAs (128 entry), 3 to 34

And the command to have one partition for all the disk failed also :
  $> gpt write mmc 0 "name=test,size=0"

After the patch :

  $> gpt write mmc 0 "name=test,size=0"
  Writing GPT: success!
  $> part list mmc 0

  Partition Map for MMC device 0  --   Partition Type: EFI

  Part	Start LBA	End LBA		Name
	Attributes
	Type GUID
	Partition GUID
  1	0x00000022	0x01ce9fde	"test"
	attrs:	0x0000000000000000
	type:	ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
	type:	data
	guid:	b4b84b8a-04e3-4000-0036-aff5c9c495b1

And 0x22 = 34 LBA => offset = 0x4400 is accepted as expected

Reviewed-by: Łukasz Majewski <lukma@denx.de>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2017-10-23 17:27:48 -04:00
Patrick Delaunay
30ef7cbb81 test/py: gpt: add test for sub-command read and verify
add sandbox test for some gpt sub-command
- gpt read / part list : read the gpt partition created by sgdisk on host
  test start, size, LBA and name output
- gpt verify : verify the gpt partition create by sgdisk on host

PS: persistent data test_gpt_disk_image.bin are udpated

Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2017-10-23 17:27:42 -04:00
Patrick Delaunay
da4c4bbd61 test/py: gpt: copy persistent file
copy the persistent gpt binary file as it can be modified during the test
that avoid issue if the test fail: the test always restart with clean file

Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2017-10-23 17:27:05 -04:00
Bin Meng
6087be2ba6 rtc: mc146818: Correct alarm message for day alarm
RTC_CONFIG_D register contains the day within the month to generate
an alarm, not the month. This corrects the printf to indicate it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-23 17:25:40 -04:00
Michal Oleszczyk
d17207ea83 chiliboard config: use CONFIG_DEFAULT_FDT_FILE as env variable
Remove hardcoded ftd file name from environment variables.
Use CONFIG_DEFAULT_FDT_FILE macro instead.

Signed-off-by: Michal Oleszczyk <m.oleszczyk@grinn-global.com>
2017-10-23 17:25:40 -04:00
Masahiro Yamada
3d569a807e simple-bus: remove DECLARE_GLOBAL_DATA_PTR
No global pointer is used in this file.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-23 17:25:40 -04:00
York Sun
1e0d51a6c4 powerpc: mpc85xx: Implement CPU erratum A-007907 for secondary cores
Commit 06ad970b53 ("powerpc: mpc85xx: Implemente workaround for CPU
erratum A-007907") clears L1CSR2 for the boot core, but other cores
don't run through the workaround. Add similar code for secondary
cores to clear DCSTASHID field in L1CSR2 register.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-10-23 14:02:48 -07:00
Masahiro Yamada
8b7f4b9cc1 mtd: remove MTDDEBUG() and CONFIG_MTD_DEBUG
All users of this macro have been converted.  Remove MTDDEBUG and
related CONFIG options.

ubifs_dbg_msg_key() is kept.  It is silent unless DEBUG is defined.

I am not touching scripts/config_whitelist.txt.  The deprecated options
will be dropped by the next resync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-23 14:07:26 -04:00
Masahiro Yamada
166cae20dd mtd: replace MTDDEBUG() with pr_debug()
In old days, the MTD subsystem in Linux had debug facility like
DEBUG(MTD_DEBUG_LEVEL1, ...).

They were all replaced with pr_debug() until Linux 3.2.  See Linux
commit 289c05222172 ("mtd: replace DEBUG() with pr_debug()").

U-Boot still uses similar macros.  Covert all of them for easier sync.

Done with the help of Coccinelle.

The semantic patch I used is as follows:

// <smpl>
@@
expression e1, e2;
@@
-MTDDEBUG(e1, e2)
+pr_debug(e2)
@@
expression e1, e2;
@@
-MTDDEBUG(e1, e2,
+pr_debug(e2,
 ...)
// </smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-23 14:07:26 -04:00
Tom Rini
ce0dea889a Merge git://git.denx.de/u-boot-uniphier 2017-10-22 19:21:04 -04:00
Masahiro Yamada
624c0954c7 ARM: uniphier: use pr_*() more where appropriate
Commit dd74b945af ("ARM: uniphier: use pr_() instead of printf()
where appropriate"), but I missed to update this file for some reason.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-23 01:09:22 +09:00
Masahiro Yamada
9e19031ca3 doc: uniphier: add simple guide to Verified Boot
Add a simple documentation about how to use the Verified Boot on
UniPhier boards.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-23 01:09:22 +09:00
Masahiro Yamada
15d0f3538a ARM: uniphier: remove verify=n from environments
If the environment "verify" is set to n, the image verification
is entirely skipped.  Remove it as a preparation for verified boot.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-23 01:02:05 +09:00
Masahiro Yamada
571e050b45 ARM: uniphier: increase CONFIG_SYS_BOOTM_LEN to 32MB
The default value of CONFIG_SYS_BOOTM_LEN, 0x800000, causes error
when uncompressing Image.gz out of FIT image.

   Uncompressing Kernel Image ... Error: inflate() returned -5
Image too large: increase CONFIG_SYS_BOOTM_LEN

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-23 01:02:05 +09:00
Masahiro Yamada
272874879b ARM: dts: uniphier: sync DT with Linux 4.14-rc5
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-23 01:02:05 +09:00
Masahiro Yamada
9ac0e7b37a ARM: uniphier: split u-boot,dm-pre-reloc out to uniphier-v7-u-boot.dtsi
UniPhier 32-bit SoCs use CONFIG_SPL_OF_CONTROL.  So, many nodes must
be marked as dm-pre-reloc to prevent fdtgrep from stripping them off.

Sprinkling U-Boot-specific properties all over the place is painful
because DT files are synced with Linux from time to time.

Split u-boot,dm-pre-reloc out to uniphier-v7-u-boot.dtsi, which is
appended to UniPhier V7 DTS before the build.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-10-23 01:02:05 +09:00
Masahiro Yamada
d0df9588e8 ARM: uniphier: remove CONFIG_UNIPHIER_ETH
The option is never enabled by anyone.  Remove the code surrounded
by its ifdef.  This should be handled by the clock/reset drivers.

CONFIG_UNIPHIER_ETH in scripts/config_whitelist.txt will be dropped
by the next resync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-23 01:02:05 +09:00
Masahiro Yamada
0b55abd34a ARM: uniphier: enable DWC3 xHCI driver really
I thought commit d37d31849c ("ARM: uniphier: enable DWC3 xHCI
driver") enabled CONFIG_USB_DWC3_UNIPHIER, but CONFIG_USB_XHCI_DWC3
was missing in uniphier_v7_defconfig.  Re-add.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-23 01:02:05 +09:00
Tom Rini
23d51bef94 uniphier_ld4_sld8: Re-add SMC911X_BASE address
This was dropped by accident in the Kconfig conversion.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-21 10:26:34 -04:00
Adam Ford
8daec2d9d3 net: Add SMC911X driver to Kconfig, convert
We add the various SMC91XX symbols to drivers/net/Kconfig and then this
converts the following to Kconfig:
   CONFIG_SMC911X
   CONFIG_SMC911X_BASE
   CONFIG_SMC911X_16_BIT
   CONFIG_SMC911X_32_BIT

Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Apply to the rest of the tree, re-squash old and new patch]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-20 21:40:26 -04:00
Adam Ford
0a9ef45158 Convert CONFIG_NAND_OMAP_GPMC et al and CONFIG_NAND_MXC to Kconfig
This converts the following to Kconfig:
   CONFIG_NAND_MXC
   CONFIG_NAND_OMAP_GPMC
   CONFIG_NAND_OMAP_GPMC_PREFETCH
   CONFIG_NAND_OMAP_ELM
   CONFIG_SPL_NAND_AM33XX_BCH
   CONFIG_SPL_NAND_SIMPLE
   CONFIG_SYS_NAND_BUSWIDTH_16BIT

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
[trini: Finish migration of CONFIG_SPL_NAND_SIMPLE, fix some build issues,
        add CONFIG_NAND_MXC so we can do CONFIG_SYS_NAND_BUSWIDTH_16BIT]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-20 16:44:07 -04:00
Tom Rini
0def58f7fd Merge git://git.denx.de/u-boot-x86 2017-10-19 11:19:38 -04:00
Stefan Roese
9af43acba6 x86: conga-qeval20-qa3-e3845-internal-uart_defconfig: Add ACPI resume support
I've missed to add the ACPI resume support to this x86 build target.
This patch adds the ACPI resume support enabling S3 suspend /
resume.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-19 11:37:51 +08:00
Heinrich Schuchardt
871aa41d4c x86: provide CONFIG_BUILD_ROM
Up to now we depended on an exported variable to build u-boot.rom.
We should be able to specify it in the configuration file, too.

With this patch this becomes possible using the new Kconfig option
CONFIG_BUILD_ROM.

This option depends on CONFIG_X86 and is selected in
qemu-x86_defconfig and qemu-x86_64_defconfig.

Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-19 11:37:51 +08:00
Bin Meng
83262f99cd x86: baytrail: fsp: Move Azalia update codes to board
Azalia configuration may be different across boards, hence it's not
appropriate to do that in the SoC level. Instead, let's make the
SoC update_fsp_azalia_configs() routine as a weak version, and do
the actual work in the board codes.

So far it seems only som-db5800-som-6867 board enables the Azalia.
Move the original codes into som-db5800-som-6867.c.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-10-19 11:37:51 +08:00
Bin Meng
f6859558ca x86: baytrail: fsp: Use a function to update the Azalia config pointer
At present we directly pass the Azalia config pointer to the FSP UPD.
This updates to use a function to do the stuff, like Braswell does.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-10-19 11:37:51 +08:00
Bin Meng
abddcd52ab x86: fsp: Consolidate Azalia header file
So far there are two copies of Azalia struct defines with one in
baytrail and the other one in braswell. This consolidates these
two into one, put it in the common place, and remove the prefix
pch_ to these structs to make their names more generic.

This also corrects reset_wait_timer from us to ms.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-10-19 11:37:51 +08:00
Bin Meng
3322a8e1a3 x86: Turn off running VGA ROM during S3 resume
This is only needed when graphics console is used. For kernel with
native graphics driver, this can be turned off to speed up.

Change this option's default to n in the Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-10-19 11:37:51 +08:00
Bin Meng
febdfaabc7 x86: baytrail: Fix unstable ACPI S3 resume
It was observed that when booting a Ubuntu 16.04 kernel, doing ACPI
S3 suspend/resume sometimes causes the Ubuntu kernel hang forever.
The issue is however not reproduced with a kernel built from i386/
x86_64 defconfig configuration.

The unstability is actually caused by unexpected interrupts being
generated during the S3 resume. For some unknown reason, FSP (gold4)
for BayTrail configures the GPIO DFX5 PAD to enable level interrupt
(bit 24 and 25). As this pin keeps generating interrupts during an
S3 resume, and there is no IRQ requester in the kernel to handle it,
the kernel seems to hang and does not continue resuming.

Clear the mysterious interrupt bits for this pin.

Reported-by: Stefan Roese <sr@denx.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-10-19 11:37:51 +08:00
Bin Meng
917d3565b5 x86: minnowmax: Adjust VGA rom address
Adjust VGA rom address to 0xfffb0000 so that u-boot.rom image
can be built again.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-10-19 11:37:51 +08:00
Tom Rini
6b0fea3342 Merge git://git.denx.de/u-boot-i2c 2017-10-18 09:32:35 -04:00
Tom Rini
002e91087c Merge git://git.denx.de/u-boot-spi 2017-10-18 09:32:21 -04:00
Patrice Chotard
d10bd6cfd8 i2c: stm32f7_i2c: fix usage of useless local variable
Remove useless local variable "s" and use directly
function's parameter "output"

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-10-17 11:28:41 +02:00
Christophe Kerello
81c4843763 i2c: stm32f7_i2c: fix data abort
As "v" is a local variable in stm32_i2c_choose_solution()
"v" has to be copied into "s" to avoid data abort in
stm32_i2c_compute_timing().

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-10-17 11:28:27 +02:00
Masahiro Yamada
c4e5990ad2 i2c: remove DECLARE_GLOBAL_DATA_PTR from i2c-uclass
No global pointer is used in this file.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2017-10-17 11:27:42 +02:00
Tom Rini
eb0044db39 Prepare v2017.11-rc2
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-16 21:40:56 -04:00
Tom Rini
308e066566 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-16 21:35:43 -04:00
Heinrich Schuchardt
6c7c3dcc59 test/py/tests/test_sleep.py: test time approximately
On qemu errors like
assert 2.999650001525879 >= 3
occur.

According to the comment in the code the test is meant to be
approximate. So we should accept some milliseconds less.

Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2017-10-16 13:45:37 -04:00
Heinrich Schuchardt
59ab72d7bc scripts/get_maintainer.pl: update to current version
Update the script to version 0.26 (as of Linux v4.14-rc1)
Keep our "penguin_chief".
Keep our top_of_kernel_tree.

The negative forms of the command line parameters are described
when using --help.

New options are

 --git-blame-signatures => when used with --git-blame,
                           also include all commit signers
 --r => include reviewer(s) if any
 --letters => print all matching 'letter' types
              from all matching sections

File .get_maintainer.ignore can be used to specify
email addressees that shall be ignored.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-10-16 13:45:36 -04:00
Praneeth Bajjuri
9b46ce8cfc arm: dra76: fastboot: extend cpu type for getvar command
'commit fa24eca1f2 ("omap: Add routine for setting fastboot variables")'
adds initial support and usage of "fastboot getvar" command
for DRA75x and DRA72x devices.

and
'commit 0f9e6aee9d ("arm: dra76: Add support for ES1.0 detection")'
adds initial dra76 device definition

This patch is to extend usage of "fastboot getvar" for DRA76 device.

Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-10-16 09:43:34 -04:00
Vishal Mahaveer
b6df93598c omap-common: fastboot: extend cpu type for DRA71x rev 2.1
DRA71x processors are reduced pin and software compatible
derivative of DRA72 processors. Extend support for this
revision in "getvar cpu" command.

Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
[praneeth@ti.com: rebase to u-boot master]
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-10-16 09:43:34 -04:00
Vishal Mahaveer
3f3607ded4 arm: dra7xx: Add vendor partition to Android GPT table for eMMC
Add vendor partition to Android GPT table for eMMC.

A Vendor image contains SoC-specific code and configuration.

Prior to Android 8.0, the vendor partition was optional ;
files belonging to these images were placed in boot.img or system.img
with symlinks (such as /vendor >/system/vendor ) when absent.

Android 8.0 makes the vendor partition mandatory

The goal is to modularize Android partitions with standard interface between
the Android Platform (on system.img ) and vendor-provided code(on vendor.img).

This standard interface enables the Android Platform to be updated
without affecting the SoC partitions. This makes it possible to upgrade a
device system.img from Android 8.0 to Android P while other images (such as
vendor.img) remain at Android 8.0. This modularity enables timely
Android platform upgrades (such as monthly security updates )
without requiring SoC/ODM partners to update SoC- and device-specific code.

Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-10-16 09:43:34 -04:00
Praneeth Bajjuri
d5a42f6634 arm: am57xx: Add vendor partition to Android GPT table for eMMC
Add vendor partition to Android GPT table for eMMC.

A Vendor image contains SoC-specific code and configuration.

Prior to Android 8.0, the vendor partition was optional ;
files belonging to these images were placed in boot.img or system.img
with symlinks (such as /vendor >/system/vendor ) when absent.

Android 8.0 makes the vendor partition mandatory

The goal is to modularize Android partitions with standard interface between
the Android Platform (on system.img ) and vendor-provided code(on vendor.img).

This standard interface enables the Android Platform to be updated
without affecting the SoC partitions. This makes it possible to upgrade a
device system.img from Android 8.0 to Android P while other images (such as
vendor.img) remain at Android 8.0. This modularity enables timely
Android platform upgrades (such as monthly security updates )
without requiring SoC/ODM partners to update SoC- and device-specific code.

Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-10-16 09:43:34 -04:00
Heinrich Schuchardt
c409336dac usbtty: fix typos
Fix typos in USB tty driver.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-10-16 09:42:51 -04:00
Bin Meng
3b306c37cd tools: env: Add embedded.c to .gitignore
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-16 09:42:51 -04:00
Tom Rini
59ee8f83b6 cmd/pxe.c: Rework bootargs construction to clarify string checks
As the code currently stands, we first check that the length of the
given command line, along with ip_str/mac_str along with an additional 1
for the NULL termination will fit within the buffer we have, and if not,
we return an error.  The way this code was originally written however
left Coverity "unhappy" due to using strcat rather than strncat.
Switching this to strncat however causes clang to be unhappy that we
aren't enforcing the "1" portion within strncat.  Rather than further
re-work the code to include a "- 1" in this case as well, make the
strcat code only be done within the else side of the length test.  This
keeps both clang and Coverity happy.

Fixes: 48ee0a87bc ("cmd/pxe.c: Rework initrd and bootargs handling slightly")
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-16 09:42:51 -04:00
Masahiro Yamada
ecc9709fc1 kbuild: fix dependency of DT build
I saw a DT build issue report some time before [1].  I was able to
reproduce the bug, and figure out the root cause.

Since commit 6d427c6b1f ("binman: Automatically include a U-Boot
.dtsi file"), invalid .*.cmd files are generated.

Since that commit, DTS files are put into sed and piped to CPP.
Because CPP reads the stream from stdin, -Wp,-MD,$(depfile).pre.tmp
option generates a depfile with the target name "-".  This is not
the format expected by fixdep.

Use one more temporary file instead of using pipe.  With this, deps_
in the .*.cmd will be fixed.  Having a temp file name in source_ is
odd, but it is unsed in the build system.  Not a big deal.

[1] https://lists.denx.de/pipermail/u-boot/2017-June/294451.html

Fiexes: 6d427c6b1f ("binman: Automatically include a U-Boot .dtsi file")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-16 09:42:51 -04:00
Tuomas Tynkkynen
137aefba03 common: Remove genimg_get_image()
Removal of the legacy DataFlash code turned genimg_get_image() into a
no-op. Drop all calls to it and the function itself.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
2017-10-16 09:42:51 -04:00
Tuomas Tynkkynen
c68c03f52b Drop CONFIG_HAS_DATAFLASH
Last user of this option went away in commit:

fdc7718999 ("board: usb_a9263: Update to support DT and DM")

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
2017-10-16 09:42:51 -04:00
Tuomas Tynkkynen
95688de311 spi: Drop CONFIG_ATMEL_DATAFLASH_SPI
Last user of this option went away in commit:

fdc7718999 ("board: usb_a9263: Update to support DT and DM")

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Acked-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-10-16 09:42:51 -04:00
Tuomas Tynkkynen
7b7341d7f3 env: Drop CONFIG_ENV_IS_IN_DATAFLASH
Last user of this option went away in commit:

fdc7718999 ("board: usb_a9263: Update to support DT and DM")

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
2017-10-16 09:42:51 -04:00
Vagrant Cascadian
c005f7edbb fs/jffs2/mini_inflate.c: use "static inline" instead of "inline"
This makes gcc no longer expect an out-of-line version of the
functions being present elsewhere.

This fixes a failure to build on several marvell targets with gcc-7 on
Debian:

  https://bugs.debian.org/877963

Signed-off-by: Adrian Bunk <bunk@debian.org>
Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
2017-10-16 09:42:51 -04:00
Engling, Uwe
41ba7f525f jffs2: ECC corrected nand data is ignored
Hello,

I ran into a problem with the JFFS2 filesystem driver implemented in U-Boot.

I've got a NAND device that has correctable ECC errors (corrected somewhere in mtd/nand/nand_base.c).
The NAND driver tells the filesystem layer (jffs2_1pass.c) above that there occurred correctable ECC errors and returns with a "value > 0".
The JFFS2 driver recognizes the corrected ECC errors as real error and skips this block because the only accepts a "return value == 0" as correct.

This problem exists for over 8 years (I checked version 2010.09) so I'm a little bit worried that I interpreted something wrong or didn't get the whole context.

Can someone confirm this bug (and the bugfix) in the u-boot jffs2 driver?

There was a mail in 2012 that mentioned the same problem, but there was no patch:
http://u-boot.10912.n7.nabble.com/JFFS2-seems-to-drop-nand-data-with-ECC-corrections-td142008.html
Sometime after this discussion the return value of nand_read() changed from -EUCLEAN as correctable ECC error to a positive value with the count of ECC corrected errors.

With kind reguards,
Uwe Engling
2017-10-16 09:42:51 -04:00
Tuomas Tynkkynen
d5587fa308 ARM: Add documentation for the qemu-arm board
Add brief documentation for the recently merged qemu-arm board.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
2017-10-16 09:42:51 -04:00
Christophe Kerello
6c36e97be6 mmc: stm32_sdmmc2: increase polling status register delay
MMC commands like MMC_CMD_ALL_SEND_CID or MMC_CMD_SEND_CSD can reach
500 us. This patch increases the polling status register delay to avoid
a timeout on a command.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-10-16 09:42:51 -04:00
Patrice Chotard
6c1bf6c442 dm: clk: fix PWR_CR3 register's bit 2 name
Fix bit 2 name of PWR_CR3 register to match with the
last STM32H7 reference manual available here :

http://www.st.com/content/st_com/en/support/resources/
resource-selector.html?querycriteria=productId=SS1951$$
resourceCategory=technical_literature$$resourceType=reference_manual

Update also comment about voltage scaling 1 values

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-10-16 09:42:51 -04:00
Patrice Chotard
1b4ce69dc2 dm: clk: remove CLK() macro for clk_stm32h7
CLK() macro is a residue of a previously reworked patch,
remove it.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-10-16 09:42:51 -04:00
Tuomas Tynkkynen
0c19efa7e1 ARM: tegra: Remove unused define CONFIG_ARMCORTEXA9
This macro isn't used by anything, and in fact hasn't ever been used
according to the Git logs.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
2017-10-16 09:42:51 -04:00
Marek Behún
38fc683d33 fs: Set .opendir to fs_opendir_unsupported for btrfs
Otherwise fs_opendir will fault.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
2017-10-16 09:42:51 -04:00
Marek Behún
733d963e3b fs: btrfs: Remove a foreign language note
I accidentaly left a foreign language note in the code from development.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
2017-10-16 09:42:51 -04:00
Marek Behún
ecab881c7f fs: btrfs: Fix usage of uninitialized variables
The variable res should be initialized to 0 in these functions,
because if the searched key is not found, the variable is used
uninitialized.

Reported-by: Coverity (CID: 167335)
Reported-by: Coverity (CID: 167336)
Reported-by: Coverity (CID: 167337)
Signed-off-by: Marek Behun <marek.behun@nic.cz>
2017-10-16 09:42:51 -04:00
Marek Behún
502af618ec linux/time.h: Remove dead code
Since
  rem = ((long) *tim_p) % SECSPERDAY;
the second while cycle
  while (rem >= SECSPERDAY)
is dead.

Reported-by: Coverity (CID: 167334)
Signed-off-by: Marek Behun <marek.behun@nic.cz>
2017-10-16 09:42:51 -04:00
Alexander Graf
b16339e254 iso: Reduce verbosity on test and info calls
The test and info callbacks into the partition callback struct are
used by the "part list" command on the command line. That command
is used by the distro script.

With verb=1 set, "part list" thus throws a lot of warnings about
partitions it can't find when an upper layer searches for partitions.

So let's reduce verbosity to bring it to the same level of noise
as the other partition targets.

Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-16 09:42:51 -04:00
Masahiro Yamada
7d8e9e8e24 fixdep: fix dependency on options surrounded by CONFIG_VAL()
CONFIG options surrounded by

  CONFIG_IS_ENABLED(...)
  CONFIG_IS_BUILTIN(...)
  CONFIG_IS_MODULE(...)
  CONFIG_VAL(...)

need special care for proper dependency tracking.

I do not remember why, but I missed to add CONFIG_VAL(...) handling.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-16 09:42:51 -04:00
Jon Smith
06d326d3a6 tools: bmp_logo: correctly interpret BMP files with larger headers
All BMP files were being treated as though they had a 40 byte header.
There are several BMP header formats consisting of additional data.
This was causing some of the header to be read as color information,
skewing the color palette.

Signed-off-by: Jon Smith <jtsmith@pdiarm.com>
2017-10-16 09:42:51 -04:00
Diego Dorta
026d7958ba common: Add a prototype for s_init()
When compiling with W=1 the following warning is observed:

arch/arm/mach-imx/mx6/soc.c:590:6: warning: no previous prototype for ‘s_init’ [-Wmissing-prototypes] void s_init(void)

Remove this warning by adding the function prototype into include/common.h file.

Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
2017-10-16 09:42:51 -04:00
Mirza, Taimoor
a6e9810495 tools/mkimage: Fix DTC run command to handle file names with space
fit_handle_file function does not quote input and output files while preparing
command to run DTC to convert .its to .itb. This results in a failure if input
or output files contain spaces in their names. Quote input and output files in
DTC command to avoid this failure.

Signed-off-by: Mirza, Taimoor <Taimoor_Mirza@mentor.com>
2017-10-16 09:42:51 -04:00
Alexander Graf
409f05f259 fdt: update bcm283x device tree sources to Linux 4.14 state
Upstream Linux has received a few device tree updates to the RPi
which we should propagate into the builtin U-Boot one as well to
gain hardware support.

This patch bumps the dts files to their 4.14 Linux counterparts
with the exception of sdhost on 32bit RPi versions. There we stay
with iproc as the sdhost driver is missing in U-Boot.

Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-16 09:42:51 -04:00
Tom Rini
b351ccf11a part_efi: In is_gpt_valid() check argument validity before allocation
While this goes somewhat against normal coding style we should ensure
that dev_desc is not NULL before we dereference it in allocation of
legacy_mbr.

Reported-by: Coverity (CID: 167292)
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-16 09:42:51 -04:00
ext-vasily.gurevich@vaisala.com
c12d8b7d70 SPL: FIT: Kconfig: Change SPL_FIT_IMAGE_POST_PROCESS entry
Remove depends on TI_SECURE_DEVICE for other platforms.

Signed-off-by: Vasily Gurevich <ext-vasily.gurevich@vaisala.com>
2017-10-16 09:42:51 -04:00
Masahiro Yamada
7d9927c895 clk: uniphier: add NAND controller clock
This allows the NAND driver to enable clock and get its clock rate.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-15 22:32:25 +09:00
Masahiro Yamada
a89b9bc095 mtd: nand: denali_dt: add clock support
Enable clock in the probe hook.  The clock rate will be necessary
when setup_data_interface hook is supported.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-15 22:32:25 +09:00
Masahiro Yamada
c7372d61fd ARM: uniphier: adjust ifdefs for new UniPhier DWC3 CONFIG
Now USB 3.0 feature is enabled/disabled by CONFIG_USB_DWC3_UNIPHIER.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-15 22:32:25 +09:00
Masahiro Yamada
d37d31849c ARM: uniphier: enable DWC3 xHCI driver
Enable CONFIGs for the DWC3 core and the UniPhier specific glue layer.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-15 22:32:25 +09:00
Masahiro Yamada
5e5edca27c ARM: uniphier: change the default of SoC select to UNIPHIER_V7_MULTI
ARCH_UNIPHIER_V8_MULTI depends on !SPL, so the default may be hidden.
Use a clearer default.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-15 22:32:25 +09:00
Masahiro Yamada
def4eadba9 reset: uniphier: fix the first argument passed to dev_err()
priv->dev does not exist.  Pass the correct pointer to udevice.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-15 22:32:25 +09:00
Masahiro Yamada
ab05406e73 clk: uniphier: add PXs3 clock data
Add basic clock data for Socionext's new SoC PXs3.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-15 22:32:25 +09:00
Masahiro Yamada
d6c7ee7d28 clk: uniphier: rework for better clock tree structure
U-Boot does not support fancy clock tree structures like the Linux
common clock framework.  Implement a simple clock tree model at the
driver level.  With this, the clock data will be simplified.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-15 22:32:25 +09:00
Masahiro Yamada
2b7b2df91e i2c: uniphier-f: replace debug() with dev_dbg()
Use dev_dbg() functions.  It will be helpful to prefix log messages
with the corresponding device name when the core framework is ready.

While I am here, I renamed "dev", which was actually private data,
into "priv" because dev->dev looks confusing.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-15 22:32:25 +09:00
Masahiro Yamada
804cf1c46f i2c: uniphier: replace debug() with dev_dbg()
Use dev_dbg() functions.  It will be helpful to prefix log messages
with the corresponding device name when the core framework is ready.

While I am here, I renamed "dev", which was actually private data,
into "priv" because dev->dev looks confusing.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-15 22:32:24 +09:00
Masahiro Yamada
4bb3dac772 usb: dwc3-uniphier: replace <common.h> with <linux/bitops.h>
Including <common.h> pulls in a lot of bloat.  What this driver needs
is BIT(), so replace it with <linux/bitops.h>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Marek Vasut <marex@denx.de>
2017-10-15 22:32:24 +09:00
Masahiro Yamada
dd74b945af ARM: uniphier: use pr_() instead of printf() where appropriate
Replace printf() with pr_() to specify proper loglevel.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-15 22:32:24 +09:00
Masahiro Yamada
f73cfb4d0d pinctrl: uniphier: simplify input enable and delete pin arrays
The pin data are implemented for old SoCs to specify the bit shift of
the IECTRL register.  They are not wortwhile given the required memory
footprint.  Delete all the pin data and enable all bits of the IECTRL
register.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-15 22:32:24 +09:00
Masahiro Yamada
c906032c04 pinctrl: uniphier: set PUPD_SIMPLE cap flag for PXs3
Like other recenct UniPhier SoCs, the pupdctrl number of PXs3
matches to the pin number.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-15 22:32:24 +09:00
Masahiro Yamada
0f72b74b32 ARM: dts: uniphier: update GPIO nodes
Switch to the single node design.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-15 22:32:24 +09:00
Masahiro Yamada
c5fb1c2524 gpio: uniphier: rework single device node model
First, I implemented this driver as per-bank model, but it was
a design mistake.

  - There are 31 banks in the maximum case.  It is painful to add
    so many nodes to DT.

  - The IRQ control registers are shared between banks.  Per-bank
    design is a problem for Linux.  The counterpart for Linux turned
    around to the single node model.

Rework based on the driver for Linux.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-15 22:32:24 +09:00
Masahiro Yamada
83ee44ab9e ARM: uniphier: switch to CONFIG_ENV_IS_NOWHERE
The non-volatile storage varies board by board.  The default should
be NOWHERE.  Please choose a proper device via Kconfig.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-15 22:32:24 +09:00
Masahiro Yamada
fe3fddfad7 mtd: nand: do not check R/B# for CMD_SET_FEATURES in nand_command(_lp)
Set Features (0xEF) command toggles the R/B# pin after 4 sub feature
parameters are written.

Currently, nand_command(_lp) calls chip->dev_ready immediately after
the address cycle because NAND_CMD_SET_FEATURES falls into default:
label.  No wait is needed at this point.

If you see nand_onfi_set_features(), R/B# is already cared by the
chip->waitfunc call.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>

[ Linux commit: c5d664aa5a4c4b257a54eb35045031630d105f49 ]
2017-10-15 22:32:10 +09:00
Masahiro Yamada
6f29c7a8f1 mtd: nand: do not check R/B# for CMD_READID in nand_command(_lp)
Read ID (0x90) command does not toggle the R/B# pin.  Without this
patch, NAND_CMD_READID falls into the default: label, then R/B# is
checked by chip->dev_ready().

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>

[ Linux commit: 3158fa0e739615769cc047d2428f30f4c3b6640e ]
2017-10-15 22:31:35 +09:00
Chris Packham
ce3ba458a8 moveconfig: fix error message in do_autoconf()
Move the % arch outside the double quote so that the missing toolchain
message is displayed correctly.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-15 18:13:13 +09:00
Tom Rini
f855a7bc12 Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot
Patch queue for efi - 2017-10-13

This is the second batch of amazing improvements for efi_loader in 2017.11:

  - New self tests to verify our own code
  - A few bug fixes
  - colored text support
  - event and SNP improvements, should get us close to iPXE working
2017-10-13 09:53:58 -04:00
Heinrich Schuchardt
abe994633b efi_selftest: correctly check return values
When cancelling the timer we should check the return
value provided by the set_timer service.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-13 10:24:22 +02:00
Tom Rini
26f9184e09 Merge git://git.denx.de/u-boot-fsl-qoriq 2017-10-12 13:36:58 -04:00
Tom Rini
e11d2fff73 Merge git://www.denx.de/git/u-boot-imx 2017-10-12 13:36:37 -04:00
Marek Vasut
0a333602df ARM: imx6: Add DHCOM i.MX6 PDK board support
Add support for the DHCOM i.MX6 PDK board. This board has:
- FEC ethernet
- EHCI USB host
- 3x SDMMC

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2017-10-12 18:01:06 +02:00
Uri Mashiach
1a95913979 imx: mx7: spl: remove redundant SATA definitionas
The i.MX7 SOC doesn't include the SATA interface.

Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-10-12 18:00:46 +02:00
Diego Dorta
e2000731ae mx6: sys_proto: Add prototypes for imx6_pcie_toggle() functions
When compiling with W=1 errors are observed:

drivers/pci/pcie_imx.c:517:12: warning: no previous prototype for ‘imx6_pcie_toggle_power’ [-Wmissing-prototypes] __weak int imx6_pcie_toggle_power(void)

drivers/pci/pcie_imx.c:528:12: warning: no previous prototype for ‘imx6_pcie_toggle_reset’ [-Wmissing-prototypes] __weak int imx6_pcie_toggle_reset(void)

Remove these warnings by adding the functions prototypes on arch-mx6/sys_proto.

Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
2017-10-12 18:00:18 +02:00
Diego Dorta
342b4b09b1 mx6: clock: Add a prototype for do_mx6_showclocks()
When compiling with W=1 the following warning is observed:

arch/arm/mach-imx/mx6/clock.c:1268:5: warning: no previous prototype for ‘do_mx6_showclocks’ [-Wmissing-prototypes] int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])

Remove this warning by adding the function prototype into arch-mx6/clock.h file.

Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
2017-10-12 18:00:01 +02:00
Anatolij Gustschin
fe12386c2a i.mx6ul: xpress: update UART init for current board revision
UART pinmux has been changed on the last board revision. Change
board pinmux accordingly. Console is on UART7 now, add pinmux,
base address and update console string in environment.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-10-12 17:58:42 +02:00
Fabio Estevam
a0046393da mx6slevk: Use PARTUUID to specify the rootfs location
mx6slevk can run different kernel versions, such as NXP 4.1 or mainline.

Currently the rootfs location is passed via mmcblk number and the
problem with this approach is that the mmcblk number for the SD
card changes depending on the kernel version.

In order to avoid such issue, use the UUID method to specify the
rootfs location.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-10-12 17:58:15 +02:00
Sven-Ola Tuecke
b2915ba25e drivers: pci: imx: fix imx_pcie_remove function
We have at least a minor count of boards, that failed to re-initialize
PCI express in the Linux kernel. Typical failure rate is 20% on affected
boards. This is mitigated by commit 6ecbe13756 ("drivers: pci: imx:
add imx_pcie_remove function").

However, at least on some i.MX6 custom boards, when calling
assert_core_reset() as part of the first-time PCIe init, read access
to PCIE_PL_PFLR simply hangs. Surround this readl() with
imx_pcie_fix_dabt_handler() does not help. For this reason, the forced
LTSSM detection is only used on the second assert_core_reset() that is
called shorly before starting the Linux kernel.

Signed-off-by: Sven-Ola Tuecke <sven-ola.tuecke@numberfour.eu>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: David Müller <d.mueller@elsoft.ch>
2017-10-12 17:56:28 +02:00
Fabio Estevam
066d97c733 wandboard: Add support for the latest revd1 revision
Latest wandboard hardware revision is revd1, which brings the following
new features:

- PFUZE100 PMIC
- AR8035 Ethernet PHY
- Upgrade Wifi/BT chip to BCM4339/BCM43430.

The detection mechanism is to probe the PMIC and when it is
found, then the revision of the board is revd1.

As the detection is done via PMIC, we need to print the board version
at a later stage via CONFIG_DISPLAY_BOARDINFO_LATE and also need
to disable CONFIG_DISPLAY_BOARDINFO, which is done much earlier.

Make the necessary adjustments for the AR8035 PHY to work on revd1.

Based on Richard Hu's work from Technexion's U-Boot tree.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-10-12 17:31:16 +02:00
Stefan Agner
accb428402 doc: update imx_usb_loader URL
The changes required to use U-Boot's Serial Download Protocol
implementation are now available in upstream imx_usb_loader
repository. Update the URL accordingly.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-10-12 17:31:16 +02:00
Ilya Ledvich
6963204c4c arm: imx7d: add support for Compulab cl-som-imx7
Add initial support for Compulab cl-som-imx7 SoM.
The initial support includes:
 - MMC
 - eMMC
 - SPI flash
 - I2C
 - FEC
 - USB
 - Serial console

Signed-off-by: Ilya Ledvich <ilya@compulab.co.il>
2017-10-12 17:31:16 +02:00
Uri Mashiach
c5c6f37a04 imx: mx7: SPL support for i.MX7
Add configuration file and spl_boot_device function for the i.MX7 SPL.

Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
2017-10-12 17:31:16 +02:00
Uri Mashiach
258bad41ac imx: mx7: DDR controller configuration for the i.MX7 architecture
The configuration files imximage.cfg are used for the DDR controller
configuration.
Add DDR configuration function to replace the DDR controller
configuration in the imximage.cfg file. The function can be used for
DDR size detection.

Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
2017-10-12 17:31:16 +02:00
Uri Mashiach
8bf2d77806 imx: mx7: fix the CCM_ macros
The CCM_ macros use the CCM_BASE_ADDRESS macro, which doesn't exist.
Replace the CCM_BASE_ADDRESS macros with CCM_BASE_ADDR.

Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2017-10-12 17:31:16 +02:00
Jagan Teki
683a06b1dc icorem6_rqs: env: Return mmc devno
Instead of changing mmc devno from dts nodes better
to return the detected devno so-that env trigger the same.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-10-12 17:31:16 +02:00
Jagan Teki
913bdd65d3 icore: configs: Fix merge conflict issue
Fix for finding mmc devices on i.MX6Q icore boards
added in below comment
"icorem6: Fix to find MMC devices"
(sha1: a2b137b38d)

which is reverted in during u-boot-imx merge
" Merge git://git.denx.de/u-boot-imx"
(sha1: 6aee2ab68c)

This patch, is recreated to fix merge conflict.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-10-12 17:31:16 +02:00
Fabio Estevam
fadcf4811a topic_miami: Remove CONFIG_CMD_BOOTZ undef
CONFIG_CMD_BOOTZ option has been converted to defconfig, so there
is no need to undefine it in board config file anymore.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-10-12 17:31:16 +02:00
Diego Dorta
adaf7c9f13 mx6sabresd: Include <usb/ehci-ci.h> header file
When compiling with W=1 the following warning is observed:

board/freescale/mx6sabresd/mx6sabresd.c:586:5: warning: no previous prototype for ‘board_ehci_hcd_init’ [-Wmissing-prototypes] int board_ehci_hcd_init(int port)

Remove this warning by including <usb/ehci-ci.h>.

Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
2017-10-12 17:31:16 +02:00
Diego Dorta
2dcff642ef usb: ehci-ci: Add a prototype for board_ehci_power()
When compiling with W=1 the following warning is observed:

board/freescale/mx6sabresd/mx6sabresd.c:601:5: warning: no previous prototype for ‘board_ehci_power’ [-Wmissing-prototypes] int board_ehci_power(int port, int on)

Remove this warning by adding the function prototype into usb/ehci-ci.h file.

Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
2017-10-12 17:31:16 +02:00
Diego Dorta
adf9bd3b23 mx6sabresd: Include <asm/mach-imx/spi.h> header file
When compiling with W=1 the following warning is observed:

board/freescale/mx6sabresd/mx6sabresd.c:680:5: warning: no previous prototype for ‘board_spi_cs_gpio’ [-Wmissing-prototypes] int board_spi_cs_gpio(unsigned bus, unsigned cs)

Remove this warning by including <asm/mach-imx/spi.h>.

Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
2017-10-12 17:31:16 +02:00
Diego Dorta
c49fa34e5b mx6: soc: Include <asm/bootm.h> header file
When compiling with W=1 the following warning is observed:

arch/arm/mach-imx/mx6/soc.c:213:12: warning: no previous prototype for ‘get_board_rev’ [-Wmissing-prototypes] u32 __weak get_board_rev(void)

Fix the build warning by including <asm/bootm.h>.

Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
2017-10-12 17:31:16 +02:00
Fabio Estevam
d26e2c8453 mx7ulp_evk: Move CONFIG_CMD_BOOTZ to Kconfig
CONFIG_CMD_BOOTZ symbol does not work in board config file
anymore, so fix this by moving it to Kconfig.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2017-10-12 17:31:16 +02:00
Diego Dorta
9f272573b7 imx: sys_proto: Add a prototype for board_mmc_get_env_dev()
When compiling with W=1 the following warning is observed:

board/freescale/mx6sabresd/mx6sabresd.c:266:5: warning:
no previous prototype for ‘board_mmc_get_env_dev’
[-Wmissing-prototypes] int board_mmc_get_env_dev(int devno)

Remove this warning by adding the function prototype into sys_proto.h file.

Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-10-12 17:31:16 +02:00
Diego Dorta
7594c51ae6 imx: Include <input.h> header file
When building with W=1 errors like the one below is seen:

board/freescale/mx6sabresd/mx6sabresd.c:546:5: warning:
no previous prototype for ‘overwrite_console’
[-Wmissing-prototypes] int overwrite_console(void)

Fix the build warnings by including <input.h>.

Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-10-12 17:31:16 +02:00
Fabio Estevam
54ba383873 mx6: toradex: Remove custom CONFIG_SPL_PAD_TO definition
CONFIG_SPL_PAD_TO is already defined inside "imx6_spl.h", so there
is no need to redefine it in the board config files.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
2017-10-12 17:31:16 +02:00
Otavio Salvador
baf348fb36 mx25pdk: Remove duplicated define
The CONFIG_SYS_MMC_ENV_DEV is duplicated, drop it.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2017-10-12 17:31:16 +02:00
Otavio Salvador
f3652c1888 mx25pdk: Use generic filesystem commands
This rework the board to use the generic filesystem commands instead
of forcing the use of FAT for the boot files.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2017-10-12 17:31:16 +02:00
Fabio Estevam
626365b4f7 README.imx6: Prefer loading SPL via the new SDP mechanism
Now that it is possible to load SPL and u-boot.img via imx_usb_loader
tool, mention this method instead of the old one that relied on ymodem.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-10-12 17:31:16 +02:00
Fabio Estevam
560a8af2f4 mx53loco: Let CONFIG_DISPLAY_CPUINFO be selected
With CONFIG_DISPLAY_CPUINFO=y we get a "Reset cause" line, which
brings important information of the reboot cause.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-10-12 17:31:16 +02:00
Anatolij Gustschin
38df370182 imx6: disable clock command and print_cpuinfo code in SPL
We do not use print_cpuinfo and clock command code in SPL,
disable it when building SPL image.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-10-12 17:30:32 +02:00
Fabio Estevam
464c988a1d colibri_imx6: Avoid calling setup_display() from SPL code
There is no need call setup_display() from SPL code, so move it to
board_init(), which executes only in U-Boot proper.

Reported-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-10-12 17:30:32 +02:00
Fabio Estevam
f89bfe7c17 apalis_imx6: Avoid calling setup_display() from SPL code
There is no need call setup_display() from SPL code, so move it to
board_init(), which executes only in U-Boot proper.

Reported-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-10-12 17:30:32 +02:00
Fabio Estevam
ae40e82eef mx6cuboxi: Avoid calling setup_display() from SPL code
There is no need call setup_display() from SPL code, so move it to
board_init(), which executes only in U-Boot proper.

Reported-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-10-12 17:30:32 +02:00
Fabio Estevam
1b853e4793 wandboard: Avoid calling setup_display() from SPL code
There is no need call setup_display() from SPL code, so move it to
board_init(), which executes only in U-Boot proper.

Reported-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-10-12 17:30:32 +02:00
Fabio Estevam
5e5b20c89f cgtqmx6eval: Avoid calling setup_display() from SPL code
There is no need call setup_display() from SPL code, so move it to
board_init(), which executes only in U-Boot proper.

Reported-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-10-12 17:30:32 +02:00
Fabio Estevam
b5d959910b mx6sabresd: Avoid calling setup_display() from SPL code
There is no need call setup_display() from SPL code, so move it to
board_init(), which executes only in U-Boot proper.

Reported-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-10-12 17:30:32 +02:00
Rob Clark
2d5dc2a52d efi_loader: console support for color attributes
Shell.efi uses this, and supporting color attributes makes things look
nicer.  Map the EFI fg/bg color attributes to ANSI escape sequences.
Not all colors have a perfect match, but spec just says "Devices
supporting a different number of text colors are required to emulate the
above colors to the best of the device’s capabilities".

Signed-off-by: Rob Clark <robdclark@gmail.com>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Alexander Graf <agraf@suse.de>
[agraf: s/unsigned/unsigned int/]
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-12 17:24:25 +02:00
Rob Clark
bf19273e81 efi_loader: Add mem-mapped for fallback
When we don't have a real device/image path, such as 'bootefi hello',
construct a mem-mapped device-path.

This fixes 'bootefi hello' after devicepath refactoring.

Fixes: 95c5553ea2 ("efi_loader: refactor boot device and loaded_image handling")
Signed-off-by: Rob Clark <robdclark@gmail.com>
Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-12 17:22:58 +02:00
Tom Rini
1b22c5ba49 Merge git://git.denx.de/u-boot-i2c 2017-10-11 08:38:20 -04:00
Chris Packham
5bc90a8953 i2c: muxes: pca954x: look up width from chip_desc
Commit 8e6eda7cda ("drivers/i2c/muxes/pca954x: Add pca9547 I2C mux
support") introduced a chip_desc for the pca954x devices but failed to
update pca954x_ofdata_to_platdata() to be aware of it. Make
pca954x_ofdata_to_platdata() lookup the chip_desc to validate the device
width.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Marek Behun <marek.behun@nic.cz>
2017-10-11 06:17:22 +02:00
Tom Rini
2ee87b0c1a Merge branch 'rmobile' of git://git.denx.de/u-boot-sh 2017-10-10 20:14:38 -04:00
Tuomas Tynkkynen
45c9d96ae4 configs: Re-sync CONFIG_CMD_IMLS with moveconfig
The option is specified in Kconfig, but still a few config header files
are overriding the choice by #undef'ing it. Re-sync the option with
moveconfig to rid of the #undefs.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
2017-10-10 17:52:07 -04:00
Tuomas Tynkkynen
ad12dc1844 cmd: Toggle the default value of CONFIG_CMD_IMLS
Having this as a 'default y' is rather annoying because it doesn't
actually compile unless other options are defined in the board header:

../cmd/bootm.c: In function 'do_imls_nor':
../cmd/bootm.c:330:7: error: 'CONFIG_SYS_MAX_FLASH_BANKS' undeclared (first use in this function); did you mean 'CONFIG_SYS_MAX_FLASH_SECT'?
   i < CONFIG_SYS_MAX_FLASH_BANKS; ++i, ++info) {

Make it 'default n' so people who develop new boards that start from a
blank defconfig have one less compilation failure to debug.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
2017-10-10 17:51:04 -04:00
Jonathan Gray
bcbc4a8046 efi_loader: don't increment part twice per loop
Correct a mistake in the part number handling of commit
16a73b249d and only increment part once
per loop.

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-10 18:14:05 +02:00
Heinrich Schuchardt
984f251fee efi_loader: MAX_UTF8_PER_UTF16 = 3
The constant MAX_UTF8_PER_UTF16 is used to calculate
required memory when converting from UTF-16 to UTF-8.
If this constant is too big we waste memory.

A code point encoded by one UTF-16 symbol is converted to a
maximum of three UTF-8 symbols, e.g.

0xffff could be encoded as 0xef 0xbf 0xbf.
The first byte carries four bits, the second and third byte
carry six bits each.

A code point encoded by two UTF-16 symbols is converted to four
UTF-8 symbols.

So in this case we need a maximum of two UTF-8 symbols per
UTF-16 symbol.

As the overall maximum is three UTF-8 symobls per UTF-16 symbol
we need MAX_UTF8_PER_UTF16 = 3.

Fixes: 78178bb0c9 lib: add some utf16 handling helpers
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-10 10:01:27 +02:00
Jonathan Gray
16a73b249d efi_loader: search all possible disk partitions
When searching for partitions don't stop if a partition is not present
for a given partition number as there may be valid partitions after.

Search for up to MAX_SEARCH_PARTITIONS matching the other callers of
part_get_info().

This allows OpenBSD to boot via the efi_loader on rpi_3 again after
changes made after U-Boot 2017.09.  With MBR partitioning OpenBSD will
by default use the fourth partition for the 0xA6 (OpenBSD) partition.

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-10 09:56:04 +02:00
Tom Rini
ebdd65258b Merge git://git.denx.de/u-boot-dm 2017-10-09 20:19:39 -04:00
Marek Vasut
17cf99a5bb ARM: rmobile: dts: Add SDR104/HS200 to Salvator-X
Add DT nodes to enable SDR104/HS200 modes on Salvator-X boards.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-10-10 08:22:54 +09:00
Marek Vasut
3219c77e58 ARM: rmobile: Fixup ULCB CPLD support after PFC rework
The ULCB CPLD support was not updated during the PFC table rework,
fix up the GPIO numbers until the CPLD support is rewritten to a
proper DM capable and DT probing driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-10-10 08:22:47 +09:00
Tom Rini
74d90d17ee Merge git://git.denx.de/u-boot-video 2017-10-09 13:31:33 -04:00
York Sun
23af484b01 armv8: ls1043ardb_sdcard: prepare falcon boot
Due to a conflict with recent Primary Protected Application (PPA),
PPA cannot be loaded for SPL stage, falcon boot is not enabled by
default. With compatible PPA image, to enable falcon boot, activate
these Kconfig options in defconfig
CONFIG_SPL_FIT=y
CONFIG_SPL_FSL_LS_PPA=y
CONFIG_SPL_GZIP=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_OF_LIBFDT=y

Because environment variables are not avaiable during SPL stage for
SD boot, set "boot_os=y" as default.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-09 08:48:45 -07:00
York Sun
b7234531db armv8: ls1043ardb: Enable spl_board_init() function
CONFIG_SPL_BOARD_INIT is used for SPL boot. Enable it in defconfig
for LS1043ARDB SPL targets.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-10-09 08:48:45 -07:00
York Sun
fb97b8621e armv8: layerscape: Enable falcon boot
Add jump_to_image_linux() for arm64. Add "noreturn" flag to
armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon
boot.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
Tested-by: Łukasz Majewski <lukma@denx.de>
2017-10-09 08:48:45 -07:00
York Sun
f554411bea armv8: ls1043ardb: Use static DDR setting for SPL boot
This board has soldered DDR chips. To reduce the SPL image size,
use static DDR setting instead of dynamic DDR driver.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-10-09 08:48:45 -07:00
York Sun
7eb40f0f9d armv8: fsl-layerscape: Avoid running dram_init_banksize again
gd->ram_size is reduced in this function to reserve secure memory.
Avoid running this function again to further reduce memory size.
This fixes issue for SPL boot with PPA image loaded in which case
secure memory is incorrectly allocated due to repeated calling.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-09 08:48:44 -07:00
York Sun
b65ac633f5 cmd: spl: fix compiling error when CONFIG_CMD_SPL_WRITE_SIZE not defined
CONFIG_CMD_SPL_WRITE_SIZE is used for writing parameters to non-volatile
storage. So far it is only used for NAND. Fix compiling error when this
macro is not used for SD.

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Anatolij Gustschin <agust@denx.de>
2017-10-09 08:48:44 -07:00
York Sun
d1fc0a31b5 spl: fix assignment of board info to global data
Commit 15eb1d43bf ("spl: reorder the assignment of board info to
global data") intended to move assignment of board info earlier,
into board_init_r(). However, function preload_console_init() is
called either from spl_board_init() or from board_init_f(). For the
latter case, the board info assignment is much earlier than proposed
board_init_r(). Create a new function to fill gd->bd and call this
function when needed.

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Lokesh Vutla <lokeshvutla@ti.com>
CC: Ravi Babu <ravibabu@ti.com>
CC: Lukasz Majewski <lukma@denx.de>
CC: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-09 08:48:44 -07:00
Bogdan Purcareata
c48deb9073 armv8: ls1088a: Update MC boot sequence
The MC boot sequence is contained in mc_env_boot. Update LS1088A
boards to use this function, and hook it to reset_phy so that it's
called late enough, after the ports have been initialized, for
proper DPC / DPL fixup.

Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-09 08:48:44 -07:00
Sumit Garg
710d0cd79e armv8: fsl-layerscape: Allocate Secure memory from first ddr region
This change is required due to trusted OS (OP-TEE) not being position
independent code, it requires compile time fixed base address.

To take care of this it is assumed that all layerscape armv8 platforms
has minimum 2G ddr in first region. So we can have fixed address
space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from
top of first 2G ddr region and compile trusted OS with this fixed
base address.

But one exception here is ls1012 where we have only 1G (rdb) or 512M
(frdm) ddr memory. For those we can have different fixed compile time
base addresses for trusted OS.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-09 08:48:44 -07:00
Fabio Estevam
4912551bb0 armv7: ls1021aiot: Move CONFIG_CMD_BOOTZ to Kconfig
CONFIG_CMD_BOOTZ symbol does not work in board config file
anymore, so fix this by moving it to Kconfig.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-09 08:48:44 -07:00
Ran Wang
7458c5e65f armv8: Apply workaround for USB erratum A-009007 to LS1088A
Rx Compliance tests may fail intermittently at high jitter
frequencies using default register values.

Program register USB_PHY_RX_OVRD_IN_HI in certain sequence
to make the Rx compliance test pass.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-09 08:36:37 -07:00
Gong Qianyu
752513d8d9 armv8: ls1046aqds: Fix NAND offset for Fman ucode and env
Fix a bug of 'commit 8104deb2d6 ("armv8: layerscape: Adjust memory
mapping for Flash/SD card on LS1046A")' as NAND block size is 256KB
on LS1046AQDS.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-09 08:35:58 -07:00
Heinrich Schuchardt
fdd04563ce efi_selftest: error handling in SNP test
Avoid NULL pointer dereference after setup failed due to a
missing network.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-09 07:00:38 +02:00
Heinrich Schuchardt
10a08c4ed7 efi_loader: comments for functions add missing @return
For some functions the @return description is missing.

Fix typo.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-09 07:00:38 +02:00
Rob Clark
77511b3b4b efi_loader: Fix disk dp's for pre-DM/legacy devices
This fixes an issue with OpenBSD's bootloader, and I think should also
fix a similar issue with grub2 on legacy devices.  In the legacy case
we were creating disk objects for the partitions, but not also the
parent device.

Reported-by: Jonathan Gray <jsg@jsg.id.au>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-09 07:00:38 +02:00
Heinrich Schuchardt
1a2c8d2f60 efi_loader: avoid NULL dereference in efi_dp_match
When calling bootefi hello twice a kernel dump occurs.

Neither bootefi hello nor bootefi selftest have an image
device patch. So do not try to dereference the NULL
value.

Fixes: 95c5553ea2 efi_loader: refactor boot device and loaded_image handling
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-09 07:00:37 +02:00
Heinrich Schuchardt
7f8ec5b63e efi_selftest: avoid dereferencing NULL in tpl test
The task priority levels test uses two events one passes the
notification counter as context. The other passes NULL.
Both use the same notification function. So we need to check
for NULL here.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-09 07:00:37 +02:00
Heinrich Schuchardt
c155dfeb1e efi_selftest: efi_st_memcmp return difference of bytes
If the memory regions are different efi_st_memcmp currently
returns the difference of the addresses. Insted the
difference of the first differing byte pair should be
returned.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-09 07:00:36 +02:00
Heinrich Schuchardt
5ca23ed5bc efi_loader: supply EFI network test
This patch provides an EFI application to check the correct function
of the Simple Network Protocol implementation.

It sends a DHCP request and analyzes the DHCP offer.

Different error conditions including a 10s timeout are checked.

A successful execution will look like this:

=> bootefi nettest
Scanning disk ide.blk#0...
Found 1 disks
WARNING: Invalid device tree, expect boot to fail
Network test
DHCP Discover
DHCP reply received from 192.168.76.2 (52:55:c0:a8:4c:02)
as broadcast message.
OK. The test was completed successfully.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-09 07:00:36 +02:00
Heinrich Schuchardt
1b6332597f efi_selftest: allow printing MAC addresses
Add %pm as format string to print a MAC address.
This is helpful when analyzing network problems.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-09 07:00:35 +02:00
Heinrich Schuchardt
9820c2f30c efi_selftest: correct definition of efi_st_error
Enclose definition in parantheses to allow using efi_st_error
like a void function.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-09 07:00:35 +02:00
Heinrich Schuchardt
336d9dfc0a efi_loader: fill return values in SimpleNetworkProtocol
In the receive function all return values should be filled.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-09 07:00:35 +02:00
Heinrich Schuchardt
8db174d651 efi_loader: size fields in SimpleNetworkProtocol
The size fields in the Simple Network Protocol are all
UINTN in the UEFI spec. So use size_t.

Provide a function description of the receive function.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-09 07:00:34 +02:00
Heinrich Schuchardt
891b3d9051 efi_loader: fix efi_net_get_status
The returned interrupt status was wrong.

As out transmit buffer is empty we need to always set
EFI_SIMPLE_NETWORK_TRANSMIT_INTERRUPT.

When we have received a packet we need to set
EFI_SIMPLE_NETWORK_RECEIVE_INTERRUPT.

Furthermore we should call efi_timer_check() to handle events.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-09 07:00:34 +02:00
Heinrich Schuchardt
e5c21603fc efi_loader: implement WaitForPacket event
The WaitForPacket event informs that a network package has been
received by the SimpleNetworkProtocol.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
[agraf: Move is_signaled = true line into efi_net_push()]
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-09 07:00:33 +02:00
Heinrich Schuchardt
a0549ef607 efi_loader: use events for efi_net_receive
A timer event is defined. The timer handler cares for receiving new
packets.

efi_timer_check is called both in efi_net_transmit and efi_net_receive
to enable events during network communication.

Calling efi_timer_check in efi_net_get_status is implemented in a
separate patch.

[agraf] This patch is needed to make efi_net_get_status() actually
        report incoming packets.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
[agraf: fix spelling in comment]
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-09 07:00:33 +02:00
Heinrich Schuchardt
61da678c39 efi_net: return EFI_UNSUPPORTED where appropriate
U-Boot does not implement all functions of the simple network
protocol. The unimplemented functions return either of
EFI_SUCCESS and EFI_INVALID_PARAMETER.

The UEFI spec foresees to return EFI_UNSUPPORTED in these cases.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-09 07:00:32 +02:00
Heinrich Schuchardt
5d4a5ea964 efi_loader: efi_net: hwaddr_size = 6
The length of a MAC address is 6.
We have to set this length in the EFI_SIMPLE_NETWORK_MODE
structure of the EFI_SIMPLE_NETWORK_PROTOCOL.

Without this patch iPXE fails to initialize the network with
error message
SNP MAC(001e0633bcbf,0x0) has invalid hardware address length 0

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-09 07:00:32 +02:00
Heinrich Schuchardt
bdecf974f1 efi_loader: fill simple network protocol revision
Provide the simple network protocol revision.
This revision number could be used to identify backwards compatible
enhancements of the protocol.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-09 07:00:32 +02:00
Heinrich Schuchardt
2e0864a47e efi_loader: correct bits of receive_filters bit mask
Remove extraneous commas.
Add comment.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-09 07:00:31 +02:00
Heinrich Schuchardt
84a12ce64e efi_loader: incorrect definition of EFI_SIMPLE_NETWORK_PROTOCOL
WaitForPacket is an event and not a function pointer.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-09 07:00:31 +02:00
Heinrich Schuchardt
ca379e1bf1 efi_loader: wrong type in wait_for_event
The UEFI spec defines parameter index of WaitForEvent as UINTN*.
So we should use size_t here.

I deliberately do not use UINTN because I hold a following patch
that will eliminate UINTN because uppercase types to not match
the U-Boot coding style.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-09 07:00:30 +02:00
Heinrich Schuchardt
5a9682d0dd efi_loader: pass GUIDs as const efi_guid_t *
We need to call some boottime services internally.
Our GUIDs are stored as const efi_guid_t *.

The boottime services never change GUIDs.
So we can define the parameters as const efi_guid_t *.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-09 07:00:30 +02:00
Heinrich Schuchardt
fc05a95906 efi_loader: parameters of CopyMem and SetMem
The UEFI spec defines the length parameters of CopyMem and SetMem
as UINTN. We should size_t here.

The source buffer of CopyMem should be marked as const.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-09 07:00:29 +02:00
Heinrich Schuchardt
f7c78176d6 efi_loader: call EFI_EXIT in efi_copy_mem, efi_set_mem
EFI_ENTRY and EFI_EXIT calls must match.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-09 07:00:29 +02:00
Heinrich Schuchardt
7d963323a2 efi_loader: replace efi_div10 by do_div
We should use the existing 64bit division instead of
reinventing the wheel.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-09 07:00:29 +02:00
Heinrich Schuchardt
332468f7fc efi_loader: provide function comments for boot services
Provide comments describing the boot service functions.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-09 07:00:28 +02:00
Heinrich Schuchardt
e67e7249c8 efi_selftest: make tests easier to read
Rename counter to more illustrative names.
Update notification function description.
Simplify notification function.
Add comment for arbitrary non-zero value.
Document @return.
Use constants for return values of setup, execute, teardown.

Reported-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-09 07:00:23 +02:00
Heinrich Schuchardt
e190e8972f efi_loader: use type bool for event states
Queued and signaled describe boolean states of events.
So let's use type bool and rename the structure members to is_queued
and is_signaled.

Update the comments for is_queued and is_signaled.

Reported-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-09 06:59:38 +02:00
Heinrich Schuchardt
037ee6f91b efi_selftest: use efi_st_error for all error messages
All error messages in the selftests should use efi_st_error.
efi_st_error will print the file name and line number of the error.

Splitting message texts due to lines being over 80
characters is avoided. This resolves the issue reported
by Simon Glass in
https://lists.denx.de/pipermail/u-boot/2017-September/307387.html

Reported-by: Simon Glass <sjg@chromium.org>
Fixes: 623b3a5797 efi_selftest: provide an EFI selftest application
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-09 06:59:24 +02:00
Heinrich Schuchardt
04d0da5157 sandbox: avoid memory leak in os_dirent_ls
Realloc does not free the old memory area if it fails.

Identified by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-08 20:41:09 -06:00
Klaus Goger
68a345294a dm: ofnode: query correct property in livetree ofnode_get_addr_size
The livetree codepath of ofnode_get_addr_size always used the "reg"
property for of_get_property. Use the property parameter of the function
call instead and check the return value if the property exists.
Otherwise return FDT_ADDR_T_NONE.

This was discoverd while using SPI NOR with livetree.
spi_flash_decode_fdt checks for memory-map and will not fail with
livetree even if the property does not exist.

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-08 20:41:09 -06:00
Faiz Abbas
5924da1dfe dm: core: Round up size when allocating so that it is cache line aligned
The size variable may not be always be a mulitple of
ARCH_DMA_MINALIGN and using it to flush cache leads to cache
misaligned warnings.

Therefore, round up the size to a multiple of ARCH_DMA_MINLAIGN
when allocating private data.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-08 20:41:09 -06:00
Simon Glass
ae06a1b996 dm: gpio: pca953x: Drop pointless data structure checks
These checks cannot fail since driver model will not call a driver's
method if it cannot fully create the driver data structures.

It is confusing to have these checks and others might copy them. Drop this
code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-10-08 20:41:09 -06:00
Simon Glass
7c84319af9 dm: gpio: Correct use of -ENODEV in drivers
In U-Boot -ENODEV means that there is no device. When there is a problem
with the device, drivers should return an error like -ENXIO or -EREMOTEIO.
When the device tree properties cannot be read correct , they should
return -EINVAL.

Update various GPIO drivers to follow this rule, to help with consistency
for future driver writers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Adam Ford <aford173@gmail.com>
2017-10-08 20:41:09 -06:00
Simon Glass
4d68604189 dm: gpio: Add a comment about not copying some drivers
These three drivers all use U_BOOT_DEVICE rather than device tree to
create devices, so have to do manual allocation of platform data. This is
not true for new platforms.

Add a more explicit comment so that people do not copy this approach with
new boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Adam Ford <aford173@gmail.com>
2017-10-08 20:41:08 -06:00
Simon Glass
1ba214767d dm: gpio: vybrid_gpio: Correct driver's use of bind() method
It does not look like this driver needs to use a bind() method. It does
not manually create devices with device_bind() nor does it create devices
using U_BOOT_DEVICE(). It seems to only use device tree.

Therefore the manual allocation of platform data is not needed and is
confusing. Also platform data should be set up by the ofdata_to_platdata()
method, not bind().

Update the driver in case others use it as a model in future.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Adam Ford <aford173@gmail.com>
2017-10-08 20:08:19 -06:00
Rob Clark
085391b223 test: print_ut: Add test for %ls strings
Add a simple test for long strings.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-08 20:08:19 -06:00
Patrice Chotard
52ff28745b configs: stm32h743-eval: enable filesystem related flags
Enable CMD_GPT/EXT2/EXT4/EXT4_WRITE/FAT_FS_GENERIC flags

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-10-08 16:19:56 -04:00
Patrice Chotard
9f7d8f6788 configs: stm32h743-disco: enable filesystem related flags
Enable CMD_GPT/EXT2/EXT4/EXT4_WRITE/FAT_FS_GENERIC flags

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-10-08 16:19:56 -04:00
Patrice Chotard
a3def70a0e configs: stm32h743-disco: enable SDMMC support
Enable CMD_MMC, DM_MMC and STM32_SDMMC2 flags

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-10-08 16:19:56 -04:00
Patrice Chotard
fac0013228 configs: stm32h743-eval: enable SDMMC support
Enable CMD_MMC, DM_MMC and STM32_SDMMC2 flags

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-10-08 16:19:56 -04:00
Patrice Chotard
53c656a85e dm: mmc: remove DM_MMC_OPS for STM32_SDMMC
Since e7881d85 "dm: mmc: Drop CONFIG_DM_MMC_OPS" DM_MMC_OPS
is no more used, remove it from STM32_SDMMC2 dependencies

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-10-08 16:19:56 -04:00
Patrice Chotard
d8f69e563b ARM: DTS: stm32: add SDMMC support fo stm32h743-eval
Add pinctrl and sdmmc nodes to add MMC support for
STM32H743 evaluation board.

Evaluation board needs a second pinctrl node
"pinctrl_sdmmc1_level_shifter" to drive a level shifter
on MMC bus.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-10-08 16:19:56 -04:00
Patrice Chotard
eccac3e120 ARM: DTS: stm32: add SDMMC support for stm32h743 disco
Add pinctrl and sdmmc nodes to add MMC support for
STM32H743 discovery board.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-10-08 16:19:56 -04:00
Patrice Chotard
ca4abdcdfa configs: stm32: update SRAM address for STM32H7 disco and eval
As suggested by Vikas Manocha, update embedded SRAM address
to use AXI SRAM available on D1 domain instead of using
AHB SRAM (D2 domain).
On some STM32H743 SoCs, D2 domain SRAM is accessible even if
SRAMxEN bit in AHB2ENR bits are not set whereas on others SoCs
version it's not accessible.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-10-08 16:19:56 -04:00
Bo Shen
72dee54b4e ARM: stm32f7: fix prescaler calculation of timer
As the timer 2 is on APB1 bus, the maximum of clock frequency of APB1 timer
clock is half of SYSCLK. Then to calculate the timer prescaler for timer 2
which need to be divided by 2.

Signed-off-by: Bo Shen <voice.shen@gmail.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-10-08 16:19:56 -04:00
Tuomas Tynkkynen
af609e3764 fs/fat: Check malloc return values and fix memory leaks
Check malloc() return values and properly unwind on errors so
memory allocated for fat_itr structures get freed properly.

Also fixes a leak of fsdata.fatbuf in fat_size().

Fixes: 2460098cff ("fs/fat: Reduce stack usage")
Reported-by: Coverity (CID: 167225, 167233, 167234)
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-10-08 16:19:56 -04:00
Tuomas Tynkkynen
09fa964bba fs/fat: Fix 'CACHE: Misaligned operation at range' warnings
The 'block' field of fat_itr needs to be properly aligned for DMA and
while it does have '__aligned(ARCH_DMA_MINALIGN)', the fat_itr structure
itself needs to be properly aligned as well.

While at it use malloc_cache_aligned() for the other aligned allocations
in the file as well.

Fixes: 2460098cff ("fs/fat: Reduce stack usage")
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-10-08 16:19:56 -04:00
Tom Rini
99e46dfc6a cmd: Make CMD_LZMA / CMD_UNZIP default y if CMD_BOOTI
In the Linux Kernel on ARM64, the Image.COMPRESSION file is not
self-extracting in the way that x86 and ARM images are.  So when
CMD_BOOTI is enabled we should also default to enabling CMD_UNZIP and
CONFIG_LZMA in order for the user to be able to decompress many of the
common compressions that will be done to an Image file.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-08 16:19:56 -04:00
Sam Protsenko
610eec7f05 scripts: Move Kconfig contents to cmd/Kconfig
On case-insensitive file systems we have collision between
scripts/kconfig/ directory and scripts/Kconfig file. This patch moves
scripts/Kcofnig contents to cmd/Kconfig to fix that.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-08 16:19:56 -04:00
Patrice Chotard
9a212d7f55 serial: stm32x7: remove useless CONFIG_CLK and OF_CONTROL flag
This driver is currently used by STM32F7 and STM32H7 SoCs.
As CONFIG_CLK and OF_CONTROL flags are set by default for these
2 SoCs, this flag becomes useless in this driver, so remove it.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-10-08 16:19:56 -04:00
Patrice Chotard
6c30f15bf1 serial: stm32x7: add STM32F4 support
stm32f4 doesn't support FIFO and OVERRUN feature.
The enable bit is not at the same location in CR1
register than for STM32F7 and STM32H7.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-10-08 16:19:56 -04:00
Patrice Chotard
2a7ecc5360 serial: stm32x7: add fifo support for STM32H7
Add fifo mode support for rx and tx.
As only STM32H7 supports this feature, add has_fifo flag
to uart configuration to use fifo only when possible.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-10-08 16:19:56 -04:00
Patrice Chotard
60a996bacb serial: stm32x7: prepare the ground to STM32F4 support
STM32F4 serial IP is similar to F7 and H7, but registers
are not located at the same offset and some feature are
only supported by F7 and H7 version.

Registers offset must be added for each version and also
some flags indicated the supported feature.

Update registers name to match with datasheet (sr to isr,
rx_dr to rdr and tx_dr to tdr) and remove unused regs
(cr2, gtpr, rtor, and rqr).

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-10-08 16:19:56 -04:00
Patrice Chotard
75d5853ffc serial: stm32x7: remove stm32f7-usart and stm32h7-usart compatible
This patch remove the extra compatibility string "st,stm32h7-usart"
and "st,stm32f7-usart" to avoid confusion, save some time & space.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-10-08 16:19:56 -04:00
Patrice Chotard
2a52a9527a serial: stm32x7: cleanup code
Use BIT() macro and GENMASK() macro

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-10-08 16:19:56 -04:00
zijun_hu
34f9a92583 ARMv8: make master CPU checking logic more clear
macro branch_if_master checks master CPU via (Aff3 & (Aff2:Aff1:Aff0))
it is simple but a little obscure.

fix by checking Affx fields within MPIDR_EL1 directly.

Signed-off-by: zijun_hu <zijun_hu@htc.com>
2017-10-08 16:19:56 -04:00
Lee Jones
b813908354 board: STiH410-B2260: set ramdisk_addr_r to 0x48000000
Add missing ramdisk_addr_r param and set it to 0x48000000

Signed-off-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-08 16:19:56 -04:00
Nicolas Le Bayon
7aac4e916e board: STiH410-B2260: fix sdram size
32MB are reserved for TrustZone purpose

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
2017-10-08 16:19:56 -04:00
Patrice Chotard
3ef751ed8c board: STiH410-B2260: update environment variable
Update environment variable by updating:
 _ BOOT_TARGET_DEVICE
 _ CONFIGS_BOOTARGS
 _ kernel_addr_r, fdtfile, fdt_addr_r, scriptaddr, fdt_high, intird_high

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-08 16:19:56 -04:00
zijun_hu
7baf952fdb ARMv8: fix error in freeing stack frame
relocate_code() allocates 32 bytes stack frame but only 16 bytes are
freed before return. it will cause errors to possible previous frames
and doesn't make relocate_code() look like a function.

fix by freeing 32 bytes stack space

Signed-off-by: zijun_hu <zijun_hu@htc.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-08 16:19:56 -04:00
zijun_hu
01a8359989 ARMv8: get new GD address from gd->new_gd directly
the new GD address is calculated via board data BD currently
it require the new GD area locates below BD tightly, so a strict
constraint is imposed on memory layout which maybe make special
platform unpleasant.

fix it by getting new GD address from gd->new_gd directly.

Signed-off-by: zijun_hu <zijun_hu@htc.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-08 16:19:56 -04:00
Tom Rini
0d3aaa35b8 Travis-CI: Fix microblaze and xilinx jobs
Given how we handle the ARM toolchain we can't easily combine these two
jobs, so don't.  Give xilinx/ARM a separate build.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-07 15:54:18 -04:00
Tom Rini
bf52fcdef4 cmd/gpt.c, cmd/nvedit.c, tools/fit_image.c: Rework recent fixes for Coverity
The recent changes to these files did not completely fix the previous
issues, or introduced different (minor) issues.  In cmd/gpt.c we need to
dereference str_disk_guid to be sure that malloc worked.  In
cmd/nvedit.c we need to be careful that we can also fit in that leading
space when adding to the string.  And in tools/fit_image.c we need to
re-work the error handling slightly in fit_import_data() so that we only
call munmap() once.  We have two error paths here, one where we have an
fd to close and one where we do not.  Adjust labels to match this.

Reported-by: Coverity (CID: 167366, 167367, 167370)
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-07 11:27:59 -04:00
Tom Rini
83e92f79d3 Merge git://git.denx.de/u-boot-x86 2017-10-07 09:12:04 -04:00
Andy Shevchenko
256df1e1c6 x86: edison: Bring minimal ACPI support to the board
This board is based on Intel Tangier SoC (Intel Merrifield platform)
and may utilize ACPI powerfulness.

Bring minimum support by appending initial DSDT table for it.

Note, the addresses for generated tables are carefully chosen to avoid
any conflicts with existing shadowed BIOS data. The user have somewhat
like ~31 kB available for compiled ACPI tables that ought to be enough.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2017-10-07 15:07:59 +08:00
Andy Shevchenko
39665beed6 x86: tangier: Enable ACPI support for Intel Tangier
Intel Tangier SoC is a part of Intel Merrifield platform which doesn't
utilize ACPI by default. Here is an attempt to unleash ACPI flexibility
power on Intel Merrifield based platforms.

The change brings minimum support of the devices that found on
Intel Merrifield based end user device.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-07 15:07:59 +08:00
Stefan Roese
b6519b777d x86: theadorable-x86-xxx_defconfig: Enable setexpr command
The setexpr command is useful for scripting, lets enable it for all
x86 based theadorable platforms.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-07 12:06:27 +08:00
Stefan Roese
70e6c8c65a x86: theadorable-x86-common: Move "-generic" into kernel-ver variable
This enables the easier usage of "-custom" kernel versions as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-07 12:06:27 +08:00
Stefan Roese
43c9841042 x86: theadorable-x86-common: Add further pci hotplug cmdline parameters
This is needed for the PCIe hotplug to work correctly on some boards.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-07 12:06:27 +08:00
Tom Rini
afbdfd829f Travis-CI: Split out more vendors from the catch-all ARM job
- Move SoCFPGA and K2 boards to their own job
- Expand the microblaze job to cover ARM boards from Xilinx as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-06 16:37:06 -04:00
Tom Rini
575e1607d3 Travis-CI: Move Boundary and Engicam devices to their own jobs
The i.MX6 job can still be close to the time limit, move a few more
devices out.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-06 16:27:42 -04:00
Tom Rini
bc3eed965f Travis-CI: Move Toradex into its own job
A few of the big jobs are getting close to the time limit again, split a
few more things out.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-06 11:28:23 -04:00
Tom Rini
fa9ca8a5d2 fs/ext4/ext4fs.c: Free dirnode in error path of ext4fs_ls
As reported by Coverity, we did not free dirnode in the case of failure.
Do so now.

Reported-by: Coverity (CID: 131221)
Cc: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-06 11:28:22 -04:00
Tom Rini
3c2dff5490 tools/fit_image.c: Update some return code paths
Coverity has found some problems with the return paths in parts of this
code.  We have a case where we were going to the wrong part of the
unwind (open() failed so we cannot close the fd), a case where we were
only free()ing our buf on the error path and finally a case where we did
not munmap in the failure path.

Reported-by: Coverity (CID: 138492, 138495, 143064)
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-06 11:28:22 -04:00
Tom Rini
146dda3911 cmd/time.c: Initialize 'repeatable' variable
We cannot leave this uninitialized, set it to 0.

Reported-by: Coverity (CID: 144426)
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-06 11:28:21 -04:00
Tom Rini
48ee0a87bc cmd/pxe.c: Rework initrd and bootargs handling slightly
For the initrd portion of handling our bootm arguments we do not have a
sufficiently long enough buffer for some improbable 64bit cases.  Expand
this buffer to allow for a 64bit address and almost 256MB initrd to be
used.  Make use of strncpy/strncat when constructing the values here
since we know what the worst case valid values are, length wise.

Similarly for bootargs themselves, we need to make use of strlen/sizeof
and strncpy/strncat to ensure that we don't overflow bootargs itself.

Cc: Simon Glass <sjg@chromium.org>
Cc: Alexander Graf <agraf@suse.de>
Reported-by: Coverity (CID: 131256)
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-06 11:28:21 -04:00
Tom Rini
c667723ffb cmd/nvedit.c: Update input handling to cover overflow cases
When we have multiple messages provided, we need to be sure that we do
not exceed the length of our 'message' buffer.  In the for loop, make
sure that pos is not larger than message.  Only copy in at most however
much of the message buffer remains.  Finally, if we have not reached the
end of the message buffer, put in a space and NULL, and if we have,
ensure the buffer is now NULL termined.

Reported-by: Coverity (CID: 165116)
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-06 11:28:21 -04:00
Tom Rini
e2e6daed5a test/dm: Fix string handling issues in the eth test
Coverity scan has identified potential buffer overruns in these tests.
Correct this by zeroing our buffer and using strncpy not strcpy.

Reported-by: Coverity (CID: 155462, 155463)
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2017-10-06 11:28:20 -04:00
Tom Rini
d91062c41e test/overlay: Fix various malloc/free leaks
With the overlay tests now being built in sandbox Coverity has found a
number of issues in the tests.  In short, if malloc ever failed we would
leak the previous mallocs, so we need to do the usual goto pattern to
free each in turn.  Finally, we always looked at the free()d location to
see how many tests had failed for the return code.

Reported-by: Coverity (CID: 167224, 167227, 167230, 167236)
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-06 11:28:20 -04:00
Alison Chaiken
18030d04d2 GPT: fix memory leaks identified by Coverity
Create a common exit for most of the error handling code in
do_rename_gpt_parts.   Delete the list elements in disk_partitions
before calling INIT_LIST_HEAD from get_gpt_info() a second time.

The SIZEOF_MISMATCH error is not addressed, since that problem was
already fixed by "GPT: incomplete initialization in
allocate_disk_part".

Signed-off-by: Alison Chaiken <alison@peloton-tech.com>
Reported-by: Coverity (CID: 167222, 167235, 167237)
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-10-06 11:28:19 -04:00
Tuomas Tynkkynen
7c890f149d fs-test: Add test for a filename using '..' to go back to the root
The previous commit fixed a problem in FAT code where going back to the
root directory using '..' wouldn't work correctly on FAT12 or FAT16.
Add a test to exercise this case (which was once fixed in commit
18a10d46f2 "fat: handle paths that include ../" but reintroduced due to
the directory iterator refactoring).

This test only very barely catches the problem - without the fix the
size command still gives valid output but the additional spurious
"Invalid FAT entry" error message makes it not get caught in the
'egrep -A3 ' output. I tried to make a proper test that grows the root
directory to two clusters lots of with dummy files but that causes the
write tests to crash the sandbox totally...

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-10-06 11:28:19 -04:00
Tuomas Tynkkynen
8df8731474 fs/fat: Fix pathnames using '..' that lead to the root directory
If we end up back in the root directory via a '..' directory entry, set
itr->is_root accordingly. Failing to do that gives spews like
"Invalid FAT entry" and being unable to access directory entries located
past the first cluster of the root directory.

Fixes: 8eafae209c ("fat/fs: convert to directory iterators")
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
2017-10-06 11:28:19 -04:00
Tuomas Tynkkynen
edce588a45 fs-test: Add FAT16 support
Currently we can only test FAT32 which is the default FAT version that
mkfs.vfat creates by default. Instead make it explicitly create either a
FAT16 or a FAT32 volume. This allows us to exercise more code, for
instance the root directory handling is done differently in FAT32 than
the older FATs.

Adding FAT12 support is a much bigger job since the test creates a 2.5GB
file and the FAT12 maximum partition size is way smaller than that.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-10-06 11:28:18 -04:00
Tuomas Tynkkynen
385b731855 fs/ext4: Fix group descriptor checksum calculation
The current code doesn't compute the group descriptor checksum correctly
for the filesystems that e2fsprogs 1.43.4 creates (they have
'Group descriptor size: 64' as reported by tune2fs). Extend the checksum
calculation to be done as ext4_group_desc_csum() does in Linux.

This fixes these errors in dmesg from running fs-test.sh and makes it
succeed again:

[1671902.620699] EXT4-fs (loop1): ext4_check_descriptors: Checksum for group 0 failed (35782!=10965)
[1671902.620706] EXT4-fs (loop1): group descriptors corrupted!

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
2017-10-06 11:28:18 -04:00
Felix Brack
bd2259e3c4 doc: Fix statements on case sensitivity for regulator prefix
The regulator bindings state that regulator prefixes are allowd to be
in upper or lower case. However pmic_bind_children from pmic_uclass uses
strncmp to compare DT node name against prefix. This comparison is case
sensitive hence the regulator driver prefix case matters.

Signed-off-by: Felix Brack <fb@ltec.ch>
2017-10-06 11:28:17 -04:00
Sam Protsenko
268577669a omap: Fix warning when looking for userdata part
When eMMC was formattaed for Linux partition table, "userdata" partition
is missing. In this case, part_get_info_by_name() iterates over all
registered drivers (which are PART_TYPE_EFI, PART_TYPE_DOS and
PART_TYPE_ISO). And when it comes to PART_TYPE_ISO (which has empty
partition table), we can see next warning in U-Boot output:

    ** First descriptor is NOT a primary desc on 1:1 **

This patch switches to part_get_info_by_name_type() API in order to
check only EFI partitions for "userdata" partitions. This eliminates
mentioned warning.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-06 11:28:17 -04:00
Sam Protsenko
3078909556 disk: Provide API to get partition by name for specific type
There is already existing function part_get_info_by_name().
But sometimes user is particularly interested in looking for only
specific partition type. This patch implements such an API that
provides partition searching by name for specified partition type.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-06 11:28:17 -04:00
Sam Protsenko
19d141a0f9 omap: Omit fastboot.userdata_size related errors
When using regular $partitions variable (for Linux boot), we can see
some unwanted messages:

> ERROR: cannot find partition: 'userdata'

> at arch/arm/mach-omap2/utils.c:96/omap_mmc_get_part_size()
> Warning: fastboot.userdata_size: unable to calc

Let's remove those, as missing 'userdata' partition is correct behavior
for Linux partition, and we don't want to see some Android-related
messages in this case.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
2017-10-06 11:28:16 -04:00
Tuomas Tynkkynen
7b09dffc3b travis.yml: Add job for running test.py in qemu_arm
Note that this commit requires
https://github.com/swarren/uboot-test-hooks/pull/14 to go in first.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
2017-10-06 11:28:16 -04:00
Tuomas Tynkkynen
32f1182926 ARM: Add a new arch + board for QEMU's 'virt' machine
This board builds an U-Boot binary that is bootable with QEMU's 'virt'
machine on ARM. The minimal QEMU command line is:

    qemu-system-arm -machine virt,highmem=off -bios u-boot.bin

(Note that the 'highmem=off' parameter to the 'virt' machine is required for
PCI to work in U-Boot.) This command line enables the following:
    - u-boot.bin loaded and executing in the emulated flash at address 0x0
    - A generated device tree blob placed at the start of RAM
    - A freely configurable amount of RAM, described by the DTB
    - A PL011 serial port, discoverable via the DTB
    - An ARMv7 architected timer
    - PSCI for rebooting the system
    - A generic ECAM-based PCI host controller, discoverable via the DTB

Additionally, QEMU allows plugging a bunch of useful peripherals to the PCI bus.
The following ones are supported by both U-Boot and Linux:

- To add a Serial ATA disk via an Intel ICH9 AHCI controller, pass e.g.:
    -drive if=none,file=disk.img,id=mydisk -device ich9-ahci,id=ahci -device ide-drive,drive=mydisk,bus=ahci.0
- To add an Intel E1000 network adapter, pass e.g.:
    -net nic,model=e1000 -net user
- To add an EHCI-compliant USB host controller, pass e.g.:
    -device usb-ehci,id=ehci
- To add a NVMe disk, pass e.g.:
    -drive if=none,file=disk.img,id=mydisk -device nvme,drive=mydisk,serial=foo

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
2017-10-06 11:28:16 -04:00
Tuomas Tynkkynen
3675cb044e PCI: Add driver for a 'pci-host-ecam-generic' host controller
QEMU emulates such a device with '-machine virt,highmem=off' on ARM.
The 'highmem=off' part is required for things to work as the PCI code
in U-Boot doesn't seem to support 64-bit BARs.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-06 11:28:12 -04:00
Tuomas Tynkkynen
e434a90ec4 pci: layerscape: Use pci_generic_mmap_{read, write}_config
Use the new helpers to avoid boilerplate in the driver.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-06 11:27:41 -04:00
Tuomas Tynkkynen
75e3feac1b pci: xilinx: Use pci_generic_mmap_{read, write}_config()
Use the new helper function to avoid boilerplate in the driver.

Note that this changes __raw_writel et al. to writel. AFAICT this is
no problem because:

- The Linux driver for the same hardware uses the non-__raw variants as
  well (via pci_generic_config_write()).
- This driver seems to be used only on MIPS so far, where the __raw and
  non-__raw accessors are the same.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-06 11:27:41 -04:00
Tuomas Tynkkynen
badb99220a pci: Add helper for implementing memory-mapped config space accesses
This sort of pattern for implementing memory-mapped PCI config space
accesses appears in U-Boot twice already, and a third user is coming up.
So add helper functions to avoid code duplication, similar to how Linux
has pci_generic_config_write and pci_generic_config_read.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-06 11:27:40 -04:00
Jean-Jacques Hiblot
a4d72869f8 omap: detect board before spl_early_init()
In order to be able to select the right DTB, we need to have identified the
board before spl_early_init() is called.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-06 11:27:40 -04:00
Jean-Jacques Hiblot
2f57c95100 spl: dm: Make it possible for the SPL to pick its own DTB from a FIT
u-boot can be embedded within a FIT image with multiple DTBs. It then
selects at run-time  which one is best suited for the platform.
Use the same principle here for the SPL: put the DTBs in a FIT image,
compress it (LZO, GZIP, or no compression) and append it at the end of the
SPL.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
[trini: Move default y of SPL_MULTI_DTB_FIT_DYN_ALLOC to it being the
default choice if SYS_MALLOC_F, drop spl.h include from lib/fdtdec.c
it's unused.]
Signed-off-by Tom Rini <trini@konsulko.com>
2017-10-06 11:26:41 -04:00
Jean-Jacques Hiblot
035d64025c fdtdec: sort include files
Sort include files in accordance to U-Boot coding style.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2017-10-05 21:31:04 -04:00
Jean-Jacques Hiblot
f52bdf4b67 lib: allow building lzo for the SPL
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-05 21:31:04 -04:00
Jean-Jacques Hiblot
376ddf9d4a gzip: add a function to parse the header
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-05 21:31:04 -04:00
Jean-Jacques Hiblot
d753f942ec lzo: add a function to check the validity of the header
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-05 21:31:04 -04:00
Jean-Jacques Hiblot
02035d0086 fit: If no matching config is found in fit_find_config_node(), use the default one
If board_fit_config_name_match() doesn't match any configuration node,
then use the default one (if provided).

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-05 21:31:04 -04:00
Jean-Jacques Hiblot
d56b86eec3 fit: fixed bug in locate_dtb_in_fit()
If the dtb is the first data of the FIT, the its offset is 0x0. Change the
test to '<' instead of '<='

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-05 21:31:04 -04:00
Jean-Jacques Hiblot
906a9dbbcb fit: use 'const' for the input of fdt_offset() and locate_dtb_in_fit()
Those 2 functions don't modify their input, we can mark it const.
This prevents compilation warnings when they are provided const input.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-05 21:31:04 -04:00
Jean-Jacques Hiblot
11955590a2 dts: renamed FIT_EMBED to MULTI_DTB_FIT and moved it to the dts Kconfig
CONFIG_FIT_EMBED might be confused with CONFIG_OF_EMBED, rename it
MULTI_DTB_FIT as it is able to get a DTB from a FIT image containing
multiple DTBs. Also move the option to the Kconfig dedicated to the DTS
options and create a README for this feature.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-05 21:31:04 -04:00
Masahiro Yamada
84570a0c11 linux/kernel.h: import DIV_ROUND_{DOWN, UP}_ULL from Linux
These macros are useful to avoid link error on 32-bit systems.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-05 21:31:04 -04:00
Fabio Estevam
3ea0520512 disk: part_dos: Use the original allocation scheme for the SPL case
Since commit ff98cb9051 ("part: extract MBR signature from partitions")
SPL boot on i.MX6 starts to fail:

U-Boot SPL 2017.09-00221-g0d6ab32 (Oct 02 2017 - 15:13:19)
Trying to boot from MMC1
(keep in loop)

Use the original allocation scheme for the SPL case, so that MX6 boards
can boot again.

This is a temporary solution to avoid the boot regression.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Rob Clark <robdclark@gmail.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
2017-10-05 10:45:33 -04:00
Heinrich Schuchardt
4a59ada5e6 efi_selftest: enable CONFIG_CMD_BOOTEFI_SELFTEST
The EFI selftest has been broken by a patch on efi-next.
We should enable CONFIG_CMD_BOOTEFI_SELFTEST on
qemu-x86_defconfig and qemu-x86_64_defconfig by default
to catch this type of problem in the Travis CI tests.

These systems typically have abundant memory so that
enabling this option should not pose a problem.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-05 14:47:02 +02:00
Heinrich Schuchardt
3cc6e3fe95 efi_loader: allow creating new handles
In efi_install_protocol_interface support creating
a new handle.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-05 14:46:57 +02:00
Heinrich Schuchardt
842a8e434e efi_loader: support 16 protocols per efi_object
8 protocols per efi_object is insufficient for iPXE.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-05 14:46:48 +02:00
Tom Rini
4f42a0d721 Merge git://git.denx.de/u-boot-sunxi 2017-10-05 08:26:36 -04:00
Tom Rini
6a3e65dea3 common: Drop LOGLEVEL to 4
While this came in with a default value of 6 I am lowering this to 4.
The MTD/UBI code has a large number of error messages that we include
now.  In addition, "normally" warning messages are not included so this
feels like a more natural level to have.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-05 08:25:18 -04:00
Masahiro Yamada
ceb9190969 dm: replace dm_dbg() with pr_debug()
As we discussed before in ML, dm_dbg() causes undefined reference
error if #define DEBUG is added to users, but not drivers/core/util.c

We do not need this macro because we can use pr_debug() instead, and
it is pretty easy to enable it for the DM core by using ccflags-y.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-04 12:00:21 -04:00
Masahiro Yamada
6990e91f09 linux/bitfield.h: import <linux/bitfield.h> from Linux 4.13
Copied from Linux 4.13.

Commit log of 3e9b3112ec74 of Linux explains well why this header
is useful.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-04 12:00:21 -04:00
Masahiro Yamada
c898cba41e dm: define dev_*() log functions in DM header
Many drivers had started to use dev_err, dev_info, etc. for log
functions.  Currently, we are relying on <linux/compat.h>, but I
guess the best home is <dm/device.h>, taking into account that
Linux defines them in <linux/device.h>.

For now, I am leaving the ones in <linux/compat.h> because lots of
Linux-originated code uses dev_*(), but the first argument is not
struct udevice, so we need to ignore the bogus argument.  More
efforts are needed to iron out the issues.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-04 12:00:20 -04:00
Masahiro Yamada
0a70fb4c1c bug.h: move runtime BUG/WARN macros into <linux/bug.h>
Collect runtime BUG/WARN into a self-contained header <linux/bug.h>
to make these macros easier to use.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-04 12:00:20 -04:00
Masahiro Yamada
059a48096c bug.h: sync BUILD_BUG stuff with Linux 4.13
As commit 84b8bf6d5d ("bug.h: move BUILD_BUG_* defines to
include/linux/bug.h") noted, include/linux/bug.h was locally
modified for U-Boot because the name conflict of error() caused
build errors at that time.

Now error() is gone, so we can fully sync BUILD_BUG* with Linux.
These macros are just compile-time utilities.  Nothing depends on
platform code, so it should make sense to simply copy Linux's ones.

Please note Linux split BUILD_BUG stuff out into <linux/build_bug.h>
by commit bc6245e5efd7.  Let's follow it.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-04 12:00:19 -04:00
Masahiro Yamada
f7d6b896d6 vsprintf.h: include <linux/types.h>
This header uses ulong, size_t, loff_t.
Include <linux/types.h> to make this header self-contained.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-04 12:00:19 -04:00
Masahiro Yamada
5a719f9218 common.h: remove error()
This macro prevents us from using compiletime_error/assert defined
in <linux/compiler.h>.

Now we can remove it, then we will be able to import more BUILD_BUG
macros from Linux.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-04 12:00:18 -04:00
Masahiro Yamada
9b643e312d treewide: replace with error() with pr_err()
U-Boot widely uses error() as a bit noisier variant of printf().

This macro causes name conflict with the following line in
include/linux/compiler-gcc.h:

  # define __compiletime_error(message) __attribute__((error(message)))

This prevents us from using __compiletime_error(), and makes it
difficult to fully sync BUILD_BUG macros with Linux.  (Notice
Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().)

Let's convert error() into now treewide-available pr_err().

Done with the help of Coccinelle, excluing tools/ directory.

The semantic patch I used is as follows:

// <smpl>
@@@@
-error
+pr_err
 (...)
// </smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Re-run Coccinelle]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-04 11:59:44 -04:00
Masahiro Yamada
b44b30260f printk: collect printk stuff into <linux/printk.h> with loglevel support
When we import code from Linux, with regular re-sync planned, we want
to use printk() and pr_*().  U-Boot does not support them in a clean
way.  So, people end up with local macros, or compat headers here and
there, then we occasionally see build errors of definition conflicts.

We have include/linux/compat.h, but putting all sorts of unrelated
things into a single header is just a temporal workaround.  Hence this
patch, to find the best home for all printk variants.  If you want to
use printk() and friends, please include <linux/printk.h>.  This header
is self-contained, and pulls in only a few headers.

When I was testing this clean-up, I noticed the image size exceeded
its platform limit on some boards.  This is because all pr_*() that
were previously defined as no-op in include/linux/mtd/mtd.h (unless
CONFIG_MTD_DEBUG is set), are now enabled.

To make such boards happy, this commit also implements CONFIG_LOGLEVEL.
The concept is similar to the kernel parameter "loglevel".  (Actually,
the Kconfig help message was taken from kernel-paremeter.txt of Linux)
Messages with a loglevel smaller than console loglevel will be printed.

The difference is the loglevel is build-time determined.  To save the
image size, lower priority pr_*() are compiled out.  I set the default
of CONFIG_LOGLEVEL to 6, i.e. pr_notice and higher priority messages
are compiled in.

I adjusted CONFIG_LOGLEVEL to avoid build error for some boards.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Add in SPL_LOGLEVEL that is the same as LOGLEVEL]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-04 10:31:17 -04:00
Masahiro Yamada
7fea7b1a37 stdio.h: move printf() stuff from <common.h> to <stdio.h>
<common.h> pulls in a lot of headers.  Including it from every .c
file is a bad idea.  We need to remove contents until it contains
nothing.

Move printf() and friends to <stdio.h>.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-04 07:55:21 -04:00
Marek Vasut
fd107e32ee doc: rmobile: Update README
Update the README with build instructions for R8A7795/R8A7796 boards.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-10-04 08:50:43 +09:00
Marek Vasut
55f6847138 ARM: rmobile: Enable pinconf
Enable pinconf since it's now implemented and used in the DTs.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-10-04 08:50:43 +09:00
Marek Vasut
d52132c320 pinctrl: rmobile: Add pinconf to Renesas RCar pincontrol driver
Add pinconf support to the PFC driver, so that it can handle DT
props bias-disable, bias-pull-up, bias-pull-down, drive-strength
and power-source.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-10-04 08:50:43 +09:00
Marek Vasut
c322d4b72b usb: Drop the EHCI RCar Gen3
Since we use EHCI generic driver on RCar Gen3 , this driver is useless.
Remove it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-10-04 08:50:43 +09:00
Icenowy Zheng
e6ee85a689 sunxi: only init USB Ethernet gadget when it's enabled
If the USB Ethernet gadget is not yet enabled, the call of
usb_ether_init in board/sunxi/board.c will lead to undefined reference
error when building.

Fix this problem.

Fixes: 50ddbf1199a0 ("sunxi: Register usb_ether")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:06 +02:00
Maxime Ripard
9f35688349 sunxi: usb_phy: invert the USB phy_ctl condition
All the new SoCs from Allwinner since the A33 have had the phy_ctl offset
at 0x410 instead of 0x404 that was used on the previous SoCs.

Instead of adding more and more special cases as the number of SoCs grow,
let's invert the test to have 0x410 by default, and the (hopefully) fixed
number of old SoCs being the exception.

Suggested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Suggested-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-10-03 19:12:06 +02:00
Jagan Teki
ea5b1e1efb sun7i: a20: Add Bananapi M1 Plus support
Banana Pi M1 Plus is an open-source single-board computer
that adds more connectivity to the classic board using
Allwinner A20 SOC.

Bananapi M1-Plus features:
- A20 Dual-core 1.0GHz
- 1 GB DDR3 SDRAM
- MicroSD
- 10/100/1000 Ethernet RJ45
- WiFi b/g/n
- 5V DC Micro USB power-supply

For dts file,
Sync with Linux commit f92ca09("Merge branch 'akpm/master'").

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-10-03 19:12:06 +02:00
Icenowy Zheng
d4aac530c6 sunxi: defaultly enable SPL for Lichee Pi Zero
As we have already DRAM initialization code for V3s SoC, we can
defaultly enable SPL now on Lichee Pi Zero.

Add CONFIG_SPL in Lichee Pi Zero defconfig.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-10-03 19:12:06 +02:00
Chen-Yu Tsai
818b293305 sunxi: Enable eMMC on Cubietruck Plus
Set CONFIG_MMC_SUNXI_SLOT_EXTRA=2 to enable the eMMC controller to
access eMMC on the board.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:06 +02:00
Chen-Yu Tsai
1328a81621 sunxi: rename Bananapi M3 dts file name
The upstream (Linux) device tree file for the Bananapi M3 follows the
convention of using the well known brand name, instead of the vendor
name, for naming. The file was recently added to upstream in commit
359b5a1e1c2d ("ARM: sun8i: a83t: Add device tree for Sinovoip Bananapi
BPI-M3")

Rename the device tree file in U-boot to match.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:06 +02:00
Maxime Ripard
3c989f3a19 sunxi: Fix USB_GADGET implication
USB_GADGET will fail to compile if USB_MUSB_GADGET is not defined. Make
sure we have that condition right.

Fixes: e0ea88042d51 ("sunxi: Imply USB_ETHER")
Suggested-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:06 +02:00
Maxime Ripard
de86fc3859 sunxi: Remove the MMC index hack
The current code, if there's both an eMMC and an MMC slot available on the
board, will swap the MMC indices based on whether we booted from the eMMC
or the MMC. This way, the MMC we're supposed to boot on will always have
the index 0.

However, this causes various issues, for example when using other
components that base their behaviour on the MMC index, such as fastboot.

Let's remove that hack, and take the opposite approach. The MMC will always
have the same index, but the bootcmd will pick the same device than the one
we booted from. This is done through the introduction of the mmc_bootdev
environment variable that will be filled by the board code based on the
boot device informations we can get from the SoC.

In order to not introduce regressions, we also need to adjust the fastboot
MMC device and the environment device in order to set it to the eMMC, over
the MMC, like it used to be the case.

Tested-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:06 +02:00
Maxime Ripard
f4c3523c98 sunxi: Use sunxi_get_boot_device
Our current board code duplicates a bit the sunxi_get_boot_device logic.
Now that we can use that function in the full-flavoured U-Boot, remove that
duplication and call the function instead.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:06 +02:00
Maxime Ripard
8829076a5b arm: sunxi: Move spl_boot_device in a separate function
U-Boot itself might need to identify the boot device, for example to be
able to tell where to load the kernel from when several options are
possible.

Move the logic of spl_boot_device to a function that is compiled both for
the SPL and the main binary.

Tested-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:06 +02:00
Stefan Mavrodiev
6ee9d7be06 sunxi: Add support for A20-OLinuXino-MICRO-eMMC
From rev.J A20-OLinuXino-MICRO has eMMC option. For now this is
only 4GB, but in the future size may increase.

The dts file is the same from mainline kernel.

Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:05 +02:00
Maxime Ripard
a12fb0e368 sunxi: Enable CMD_GPT by default
GPT is pretty common these days and can be useful for things like fastboot.
Add a platform imply, so that users can still opt out if they wish so.

Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:05 +02:00
Maxime Ripard
47738acced cmd: Move CONFIG_RANDOM_UUID to Kconfig
CONFIG_RANDOM_UUID is used by the GPT command to generate random UUID when
none are provided.

Move that option to Kconfig.

Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:05 +02:00
Maxime Ripard
5ed8239383 sunxi: sina33: Sync the device tree with the kernel
The kernel DT of the SinA33 has evolved quite a bit. Make sure we sync it
and its upstream DTSI to be able to use the OTG. The DTs were taken from
the 4.13 kernel release.

Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:05 +02:00
Maxime Ripard
6e2166c186 sunxi: Imply USB_ETHER
Now that we can enable the usb_ether gadget, do it. This will be especially
useful for boards that don't have any ethernet controller, such as the ones
based on the A13 or A33.

Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:05 +02:00
Maxime Ripard
90dd2f19d6 sunxi: Register usb_ether
Call the function to register the usb_ether gadget in the board.

Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:05 +02:00
Maxime Ripard
3a61b080ac musb: sunxi: switch to the device model
The device model was implemented so far using a hook that needed to be
called from the board support, without DT support and only for the host.

Switch to probing both in peripheral and host mode through the DT.

Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:05 +02:00
Maxime Ripard
cfa34996b0 cmd: fastboot: Rework fastboot dependency
Fastboot need a bunch of options to be operating properly, such as the
g_dnl gadget, the fastboot command, and some options that make sense. Since
fastboot is now part of Kconfig, make sure we have them right.

That will also reduce the boilerplate in the defconfigs.

Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:05 +02:00
Maxime Ripard
654b02b18c sunxi: imply USB_GADGET
A good number of our boards have USB_GADGET enabled. Imply it so that all
the boards can benefit from it, and remove some boilerplate from our
defconfigs.

Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:05 +02:00
Maxime Ripard
e02687bda9 sunxi: provide default USB gadget setup
All the Allwinner boards use the same manufacturer, VID and PID for the
gadgets. Make them the defaults to remove some boilerplate from our
defconfigs.

Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:05 +02:00
Maxime Ripard
10ac57fda3 usb: gadget: usb_ether: Move settings to common
The usb_ether gadget duplicates the USB settings for the manufacturer,
product ID and vendor ID.

Make sure we use the common option so that we can expect a single VID/PID
couple for a single device.

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:05 +02:00
Maxime Ripard
a95aee6af7 usb: gadget: Make g_dnl USB settings common
The g_dnl USB settings for the vendor ID, product ID and manufacturer are
actually common settings that can and should be shared by all the gadgets.

Make them common by renaming them, and convert all the users.

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:05 +02:00
Maxime Ripard
d2f0f4af4b usb: gadget: usb_ether: Move the interfaces to Kconfig
We need to select an interface for the usb_ether gadget, and they haven't
been converted to Kconfig yet. Add a choice to make sure we have an option
selected, and convert all the users.

Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:05 +02:00
Maxime Ripard
3f33d3c8f4 usb: gadget: Convert USB_ETHER to Kconfig
The USB Ethernet gadget option has not yet been moved to Kconfig, let's
deal with that.

Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:05 +02:00
Maxime Ripard
c163668a4a usb: gadget: Move USBNET_HOST_ADDR to Kconfig
While the USB Ethernet device address is already defined in Kconfig, the
host address isn't. Convert it.

Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:04 +02:00
Maxime Ripard
74e7997c70 usb: gadget: Document USBNET_DEVADDR
Add an help about the USBNET_DEVADDR Kconfig option to make it clearer what
it's about.

Acked-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:04 +02:00
Maxime Ripard
5506ff149d usb: gadget: Move USBNET_DEVADDR option out of g_dnl
The USBNET_DEVADDR has nothing to do with the USB download gadget, but
rather with the USB Ethernet gadget. Move it out of the if statement.

Acked-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:04 +02:00
Maxime Ripard
a4dd8722fa sandbox: Expand list of IO accessors
The setbits/clrbits/clrsetbits macros are used widely across the tree,
let's provide implementation for them in the sandbox.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:04 +02:00
Tom Rini
39dd65a059 sandbox: Enable btrfs support
For better test coverage, enable btrfs.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-03 08:44:55 -04:00
Tom Rini
6b7fd350e8 fs/btrfs: Fix warning in btrfs_check_super()
We specifically say that the last arg is u32, so use %lu.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-03 08:44:13 -04:00
Paul Burton
f7ae1ca3e8 sandbox: Use asm-generic/io.h
Convert the sandbox architecture to make use of the new asm-generic/io.h
to provide address mapping functions. As sandbox actually performs
non-identity mapping between physical & virtual addresses we can't
simply make use of the generic mapping functions, but are able to
implement phys_to_virt() & make use of it from map_physmem().

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2017-10-02 21:52:24 -04:00
Paul Burton
ae07d609e9 powerpc: Use asm-generic/io.h
Convert the powerpc architecture to make use of the new asm-generic/io.h
to provide address mapping functions. As powerpc can actually perform
non-identity mapping between physical & virtual addresses we can't
simply make use of the generic phys_to_virt() & virt_to_phys()
functions. However since map_physmem() already effectively implemented
the same thing as virt_to_phys() we can simply implement virt_to_phys()
instead of map_physmem() & use the generic map_physmem(). We also drop
the no-op unmap_physmem().

This has only been build-tested, feedback from architecture maintainers
is welcome.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Wolfgang Denk <wd@denx.de>
2017-10-02 21:52:23 -04:00
Paul Burton
e16986c481 nios2: Use asm-generic/io.h
Convert the nios2 architecture to make use of the new asm-generic/io.h to
provide address mapping functions. As nios2 actually performs
non-identity mapping between physical & virtual addresses we can't
simply make use of the generic functions, with the exception of being
able to drop our no-op unmap_physmem() and definitions of unused map
flags.

Feedback from architecture maintainers is welcome.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Thomas Chou <thomas@wytron.com.tw>
2017-10-02 21:52:23 -04:00
Paul Burton
d1cbeafd5e mips: Use asm-generic/io.h
Convert the mips architecture to make use of the new asm-generic/io.h to
provide address mapping functions. As mips actually performs
non-identity mapping between physical & virtual addresses we can't
simply make use of the generic functions, with the exception of being
able to drop our no-op unmap_physmem() and definitions of unused map
flags.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2017-10-02 21:52:23 -04:00
Paul Burton
e8645527b1 xtensa: Use asm-generic/io.h
Convert the xtensa architecture to make use of the new asm-generic/io.h
to provide address mapping functions. As the generic implementations are
suitable for xtensa this is primarily a matter of moving code.

This has only been build-tested, feedback from architecture maintainers
is welcome.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Max Filippov <jcmvbkbc@gmail.com>
2017-10-02 21:52:22 -04:00
Paul Burton
6f01316f36 x86: Use asm-generic/io.h
Convert the x86 architecture to make use of the new asm-generic/io.h to
provide address mapping functions. As the generic implementations are
suitable for x86 this is primarily a matter of moving code.

This has only been build-tested, feedback from architecture maintainers
is welcome.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-02 21:52:22 -04:00
Paul Burton
505fe9cdd0 sh: Use asm-generic/io.h
Convert the sh architecture to make use of the new asm-generic/io.h to
provide address mapping functions. As the generic implementations are
suitable for sh this is primarily a matter of moving code.

Feedback from architecture maintainers is welcome.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-10-02 21:52:21 -04:00
Paul Burton
b3666a693a nds32: Use asm-generic/io.h
Convert the nds32 architecture to make use of the new asm-generic/io.h
to provide address mapping functions. As the generic implementations are
suitable for nds32 this is primarily a matter of removing code.

Feedback from architecture maintainers is welcome.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Macpaul Lin <macpaul@andestech.com>
2017-10-02 21:52:21 -04:00
Paul Burton
dbee715237 microblaze: Use asm-generic/io.h
Convert the microblaze architecture to make use of the new
asm-generic/io.h to provide address mapping functions. As the generic
implementations are suitable for microblaze this is primarily a matter
of removing code.

Feedback from architecture maintainers is welcome.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Michal Simek <monstr@monstr.eu>
2017-10-02 21:52:21 -04:00
Paul Burton
0884077b70 m68k: Use asm-generic/io.h
Convert the m68k architecture to make use of the new asm-generic/io.h to
provide address mapping functions. As the generic implementations are
suitable for m68k this is primarily a matter of emoving code.

Feedback from architecture maintainers is welcome.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Huan Wang <alison.wang@freescale.com>
Cc: Angelo Dureghello <angelo@sysam.it>
Acked-by: Angelo Dureghello <angelo@sysam.it>
Tested-by: Angelo Dureghello <angelo@sysam.it>
2017-10-02 21:52:20 -04:00
Paul Burton
8f8e6304df arm: Use asm-generic/io.h
Convert the arm architecture to make use of the new asm-generic/io.h to
provide address mapping functions. As the generic implementations are
suitable for arm this is primarily a matter of removing code.

This has only been build-tested, feedback from architecture maintainers
is welcome.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-02 21:52:20 -04:00
Paul Burton
593477c6b3 arc: Use asm-generic/io.h
Convert the arc architecture to make use of the new asm-generic/io.h to
provide address mapping functions. As the generic implementations are
suitable for arc this is primarily a matter of removing code.

Feedback from architecture maintainers is welcome.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Alexey Brodkin <alexey.brodkin@synopsys.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
2017-10-02 21:52:20 -04:00
Paul Burton
d4150ca6de Provide a generic io.h & address mapping functions
Most architectures currently supported by U-Boot use trivial
implementations of map_to_physmem & virt_to_phys which simply cast a
physical address to a pointer for use a virtual address & vice-versa.
This results in a lot of duplicate implementations of these mapping
functions.

The set of functions provided by different architectures also differs,
with some having implementations of phys_to_virt & others not. A later
patch will make use of phys_to_virt in architecture-neutral code, and so
requires that it be provided for all architectures.

This patch introduces an asm-generic/io.h which provides generic
implementations of address mapping functions, allowing the duplication
of them between architectures to be removed. Once architectures are
converted to make use of this generic header it will also ensure that
all of phys_to_virt, virt_to_phys, map_physmem & unmap_physmem are
provided. The 2 families of functions differ in that map_physmem may
create dynamic mappings whilst phys_to_virt may not & therefore is more
limited in scope but doesn't require information such as a length &
flags.

This patch doesn't convert any architectures to make use of this generic
header - later patches in the series will do so.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Alexey Brodkin <alexey.brodkin@synopsys.com>
Cc: Angelo Dureghello <angelo@sysam.it>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Macpaul Lin <macpaul@andestech.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Thomas Chou <thomas@wytron.com.tw>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Angelo Dureghello <angelo@sysam.it>
Tested-by: Angelo Dureghello <angelo@sysam.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2017-10-02 21:52:19 -04:00
Marek Behún
32c778637b mvebu: turris_omnia: Add CONFIG_CMD_BTRFS to defconfig
Signed-off-by: Marek Behun <marek.behun@nic.cz>
2017-10-02 21:52:19 -04:00
Marek Behún
9d84550955 cmd: Add the 'btrsubvol' command to list BTRFS subvolumes
Signed-off-by: Marek Behun <marek.behun@nic.cz>

 create mode 100644 cmd/btrfs.c
2017-10-02 21:52:18 -04:00
Marek Behún
0c936ee319 fs: btrfs: Add U-Boot fs handlers.
Signed-off-by: Marek Behun <marek.behun@nic.cz>

 create mode 100644 fs/btrfs/Kconfig
 create mode 100644 fs/btrfs/Makefile
 create mode 100644 fs/btrfs/btrfs.c
 create mode 100644 include/btrfs.h
2017-10-02 21:52:18 -04:00
Marek Behún
21a14facb1 fs: btrfs: Add single-device read-only BTRFS implementation
This adds the proper implementation for the BTRFS filesystem.
The implementation currently supports only read-only mode and
the filesystem can be only on a single device.

Checksums of data chunks is unimplemented.

Compression is implemented (ZLIB + LZO).

Signed-off-by: Marek Behun <marek.behun@nic.cz>

 create mode 100644 fs/btrfs/btrfs.h
 create mode 100644 fs/btrfs/chunk-map.c
 create mode 100644 fs/btrfs/compression.c
 create mode 100644 fs/btrfs/ctree.c
 create mode 100644 fs/btrfs/dev.c
 create mode 100644 fs/btrfs/dir-item.c
 create mode 100644 fs/btrfs/extent-io.c
 create mode 100644 fs/btrfs/hash.c
 create mode 100644 fs/btrfs/inode.c
 create mode 100644 fs/btrfs/root.c
 create mode 100644 fs/btrfs/subvolume.c
 create mode 100644 fs/btrfs/super.c
2017-10-02 21:52:17 -04:00
Marek Behún
597b4aff7b fs: btrfs: Add disk-to-cpu and cpu-to-disk conversion functions
BTRFS on disk structures are stored in Little Endian. Add functions
to convert this structures to cpu and to disk format.

On Little Endian hosts, these functions do nothing.

On Big Endian the CALL_MACRO_FROM_EACH from variadic-macro.h is used
to define all the members for each structure on which cpu_to_le* or
le*_to_cpu is to be called.

Signed-off-by: Marek Behun <marek.behun@nic.cz>

 create mode 100644 fs/btrfs/conv-funcs.h
2017-10-02 21:52:17 -04:00
Marek Behún
d4a704af5d fs: btrfs: Add btrfs_tree.h and ctree.h from Linux (and modified)
Add btrfs_tree.h and ctree.h from Linux which contains constants
and structures for the BTRFS filesystem.

Signed-off-by: Marek Behun <marek.behun@nic.cz>

 create mode 100644 fs/btrfs/btrfs_tree.h
 create mode 100644 fs/btrfs/ctree.h
2017-10-02 21:52:17 -04:00
Marek Behún
59981e6a3d include: Add a variadic macro to call a callback for all arguments
Add a header variadic-macro.h which defines the CALL_MACRO_FOR_EACH marco.

This macro can be used as follows:
  #define TEST(x)
  CALL_MACRO_FOR_EACH(TEST, a, b, c, d)

This will expand to
  TEST(a) TEST(b) TEST(c) TEST(d)

The nice thing is that CALL_MACRO_FOR_EACH is a variadic macro, thus the
number of arguments can vary (although it has an upper limit - in this
implementation 32 arguments).

Signed-off-by: Marek Behun <marek.behun@nic.cz>

 create mode 100644 include/u-boot/variadic-macro.h
2017-10-02 21:52:16 -04:00
Marek Behún
5994e8b643 fs: Create a common fs_devread for ext4/reiserfs/zfs
The ext4, reiserfs and zfs filesystems all have their own implementation
of the same function, *_devread. Generalize this function into fs_devread
and put the code into fs/fs_internal.c.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
[trini: Move fs/fs_internal.o hunk to the end of fs/Makefile as all
cases need it]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-02 21:51:50 -04:00
Marek Behún
85d8bf5713 lib: Add CRC32-C
This is needed for BTRFS.

Signed-off-by: Marek Behun <marek.behun@nic.cz>

 create mode 100644 lib/crc32c.c
2017-10-02 20:31:25 -04:00
Tom Rini
43dd6dacb2 Prepare v2017.11-rc1
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-02 20:11:24 -04:00
Bin Meng
de163ecedb scripts: dtc: Add .gitignore
Ignore these generated files during the build of dtc.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-02 18:03:37 -04:00
Tom Rini
4d1c166fee Merge git://git.denx.de/u-boot-usb 2017-10-01 18:06:53 -04:00
Tom Rini
16d4ff76c5 Merge git://git.denx.de/u-boot-rockchip 2017-10-01 13:05:53 -04:00
Masahiro Yamada
dc04b35ef2 usb: dwc3: add UniPhier specific glue layer
Add UniPhier platform specific glue layer to support USB3 Host mode
on Synopsys DWC3 IP.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2017-10-01 16:32:55 +02:00
Bin Meng
72ac8f3fc2 usb: storage: Fix overwritten in usb_stor_set_max_xfer_blk()
The stored 'blk' value is overwritten to 'size / 512' before it can
be used in usb_stor_set_max_xfer_blk(). This is not what we want.
In fact, when 'size' exceeds the upper limit (USHRT_MAX * 512), we
should simply assign 'size' to the upper limit.

Reported-by: Coverity (CID: 167250)
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-01 16:32:55 +02:00
Bin Meng
fae35857e1 usb: xhci: Set 'Average TRB Length' to 8 for control endpoints
Update the codes to conform with xHCI spec chapter 6.2.3.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-01 16:32:55 +02:00
Bin Meng
ab2b727dc0 usb: xhci: Set 'Error Count' to 0 for isoch endpoints
Per xHCI spec, 'Error Count' should be set to 0 for isoch endpoints.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-01 16:32:54 +02:00
Bin Meng
fa483b2c75 usb: xhci: Program max burst size for endpoint
The 'Max Burst Size' indicates to the xHC the maximum number of
consecutive USB transactions that should be executed per scheduling
opportunity. This is a “zero-based” value, where 0 to 15 represents
burst sizes of 1 to 16, but at present this is always set to zero.
Let's program the required value according to real needs.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-01 16:32:54 +02:00
Bin Meng
f51966bf7a usb: xhci: Honor endpoint's interval
USB endpoint reports the period between consecutive requests to send
or receive data as bInverval in its endpoint descriptor. So far this
is ignored by xHCI driver and the 'Interval' field in xHC's endpoint
context is always programmed to zero which means 1ms for low speed
or full speed , or 125us for high speed or super speed. We should
honor the interval by getting it from endpoint descriptor.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-01 16:32:54 +02:00
Bin Meng
061895fbe5 usb: hub: Clear BH reset status change for a 3.0 hub
USB 3.0 hubs report bit[5] in the port status change response as BH
reset. The hub shall set the C_BH_PORT_RESET field for this port.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-01 16:32:54 +02:00
Bin Meng
b90203526f usb: hub: Clear port reset before usb_hub_port_connect_change()
During usb_hub_port_connect_change(), a port reset set feature
request is issued to the port, and later a port reset clear feature
is done to the same port before the function returns. However at
the end of usb_scan_port(), we attempt to clear port reset again
on a cached port status change variable, which should not be done.

Adjust the call to clear port reset to right before the call to
usb_hub_port_connect_change().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-01 16:32:54 +02:00
Bin Meng
b5aa857b95 usb: xhci: Fix max packet size for full speed device endpoint 0
In xhci_check_maxpacket(), the control endpoint 0 max packet size
is wrongly taken from the interface's endpoint descriptor. However
the default endpoint 0 does not come with an endpoint descriptor
hence is not included in the interface structure. Change to use
epmaxpacketin[0] instead.

The other bug in this routine is that when setting max packet size
to the xHC endpoint 0 context, it does not clear its previous value
at all before programming a new one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-01 16:32:54 +02:00
Bin Meng
932bb668bb usb: Read device descriptor after device is addressed for xHCI
For xHCI it is not possible to read a device descriptor before it
has been assigned an address. That's why usb_setup_descriptor()
was called with 'do_read' being false. But we really need try to
read the device descriptor before starting any real communication
with the default control endpoint.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-01 16:32:53 +02:00
Bin Meng
c008faa773 usb: Only get 64 bytes device descriptor for full speed devices
Full speed device endpoint 0 can have 8/16/32/64 bMaxPacketSize0.
Other speed devices report fixed value per USB spec. So it only
makes sense if we send a get device descriptor with 64 bytes to
full speed devices.

While we are here, update the comment block to be within 80 cols.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-01 16:32:53 +02:00
Bin Meng
1897d60130 usb: xhci: Add interrupt transfer support
xHCI uses normal TRBs for both bulk and interrupt. This adds the
missing interrupt transfer support to xHCI so that devices like
USB keyboard that uses interrupt transfer can work.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-01 16:32:53 +02:00
Bin Meng
2f0eb2ac4b usb: Handle audio extension endpoint descriptor in usb_parse_config()
Normal endpoint descriptor size is 7, but for audio extension it is
9. Handle that correctly when parsing endpoint descriptor.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-01 16:32:53 +02:00
Bin Meng
8a0e6d8307 usb: xhci: Don't assume LS/FS devices are always behind a HS hub
At present xHCI driver assumes LS/FS devices are attached directly
to a HS hub. If they are connected to a LS/FS hub, the driver will
fail to perform the USB enumeration process on such devices.

This is fixed by looking from the device itself all the way up to
the HS hub where the TT that serves the device is located.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-01 16:32:52 +02:00
Bin Meng
f4d4f7d41c test: dm: usb: Update test cases for USB
Now that we have changed to remove all devices under the root hub in
usb_stop(), and corrected the USB emulator select logic, it makes no
sense to do various tests based on 'usb tree' output since the order
of devices is no longer fixed. Remove these USB test cases related
to 'usb tree'.

For the USB remove test, ideally we should remove an emulator device
node from the device tree, but this is so far not working. Change to
test the 'usb stop' only.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-01 16:32:51 +02:00
Bin Meng
ad56e4b684 dm: usb: emul: Drop usb_emul_reset()
With the root hub unbinding in usb_stop(), there is no need to do
a Sandbox-specific reset operation. usb_emul_reset() is no longer
used anywhere, drop it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-01 16:32:51 +02:00
Bin Meng
ad0a9378bf dm: usb: Remove no longer needed blk_unbind_all()
With the root hub unbinding in usb_stop(), there is no need to do
a blk uclass specific unbind operation.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-01 16:32:51 +02:00
Bin Meng
d4efefe32e dm: usb: Fix broken usb_stop()
At present we only do device_remove() during usb stop. The DM API
device_remove() only marks the device state as inactivated, but
still keeps its USB topology (eg: parent, children, etc) in the DM
device structure. There is no issue if we only start USB subsystem
once and never stop it. But a big issue occurs when we do 'usb stop'
and 'usb start' multiple times.

Strange things may be observed with current implementation, like:
- the enumeration may report only 1 mass storage device is detected,
  but the total number of USB devices is correct.
- USB keyboard does not work anymore after a bunch of 'usb reset'
  even if 'usb tree' shows it is correctly identified.
- read/write flash drive via 'fatload usb' may complain "Bad device"

In fact, every time when USB host controller starts the enumeration
process, it takes random time for each USB port to show up online,
hence each USB device may appear in a different order from previous
enumeration, and gets assigned to a totally different USB address.
As a result, we end up using a stale USB topology in the DM device
structure which still reflects the previous enumeration result, and
it may create an exact same DM device name like generic_bus_0_dev_7
that is already in the DM device structure. And since the DM device
structure is there, there is no device_bind() call to bind driver to
the device during current enumeration process, eventually creating
an inconsistent software representation of the hardware topology, a
non-working USB subsystem.

The fix is to clear the unused USB topology in the usb_stop(), by
calling device_unbind() on each controller's root hub device, and
the unbinding will unbind all of its children automatically.

For Sandbox, we need scan the device tree each time when we start
the USB stack, in order to re-create the emulated USB devices and
bind drivers for them before we actually do the driver probe.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-01 16:32:51 +02:00
Bin Meng
d7771f0c5c usb: emul: hub: Report the actual device speed of the emulation device
At present the usb hub emulator always reports its downstream port
speed as full speed. Actually it is high speed for sandbox-flash,
and low speed for sandbox-keyb. We can determine the device speed
by checking its device descriptor bcdUSB field, and do the proper
hub port status report based on that.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-01 16:32:51 +02:00
Bin Meng
848436a48d usb: emul: Expose find_descriptor() as a public API
This can be useful outside of the sandbox usb emulation uclass
driver. Expose it as a public API with a proper prefix (usb_emul_).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-01 16:32:51 +02:00
Bin Meng
84aa8536f0 usb: sandbox: Fix emulator device select logic in usb_emul_find_devnum()
Current emulator select logic in usb_emul_find_devnum() is to test
the USB address. The USB address of the device being enumerated is
initialized to zero at the beginning of the enumeration process in
usb_setup_device(). At this point, the saved USB address in the
platform data has not been assigned to any valid USB address either.
This means: the logic will select an emulator device according to
its sequence of declaring order in the device tree. Take test.dts
for example, flash-stick@0 will be selected before flash-stick@1.
But unfortunately such logic is wrong.

In fact USB devices show up in a random order during the enumeration
which means usb_emul_find_devnum() may be called on port 3 for keyb@3
before on port 0 for flash-stick@0.

To fix this, we introduce a new emulator uclass specific platdata
to store the USB device's port number on its parent hub, and update
the logic to test the port number instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-01 16:32:50 +02:00
Bin Meng
813f74ea47 usb: sandbox: Initialize root hub's device speed to high speed
At present 'usb tree' shows that the root hub on the Sandbox USB
controller is at full speed. But its device descriptor says it's
USB 2.0, so let's report it as a high speed device.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-01 16:32:50 +02:00
Bin Meng
8d36c68741 usb: Fix comments of usb_emul_find_for_dev()
There is no such a parameter called 'bus'.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-01 16:32:50 +02:00
Bin Meng
98b639fc50 usb: emul: Remove maxpacketsize in usb_emul_setup_device()
This parameter is never used.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-01 16:32:50 +02:00
Tom Rini
958046fc78 Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot
Patch queue for efi - 2017-10-01

Lots of new things this time. High level highlights are:

  - Shim support (to boot Fedora)
  - Initial set of unit tests
  - Preparations to support UEFI Shell
2017-10-01 08:48:38 -04:00
Kever Yang
e19fa89c9d rockchip: enable TPL_SYSRESET for all rockchip SoCs
With Makefiles testing for $(SPL_TPL_)SYSRESET, we need TPL_SYSRESET
for do_reset() in TPL for Rockchip SoCs.

References: 87c16d4 "drivers: spl: consistently use the $(SPL_TPL_)
macro"

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:35 +02:00
Jagan Teki
2ee3021ae1 rk3288: spl: Add dram_init_banksize
Falcon mode, is updating DDR dt node configuration through
spl_fixup_fdt() so add appropriate DDR base and size through
dram_init_banksize.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:35 +02:00
Philipp Tomsich
7c158634ca rockchip: defconfig: puma-rk3399: update for DM_REGULATOR support in SPL
The RK3399-Q7 requires DM regulator support in SPL, so we can use the
regulator framework to reenable the eMMC and SPI, if these had been
turned of by the BIOS_DISABLE signal.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01 00:33:35 +02:00
Philipp Tomsich
9086eab8fe power: spl: add SPL_DM_REGULATOR_FIXED in Kconfig
The Makefile already tests for SPL_DM_REGULATOR_FIXED, but Kconfig
does not provide it.  This adds SPL_DM_REGULATOR_FIXED to Kconfig.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01 00:33:35 +02:00
Philipp Tomsich
482cf22333 rockchip: rk3399-puma: add boot-on regulator to override BIOS_DISABLE
The (Qseven) BIOS_DISABLE signal on the RK3399-Q7 (Puma) keeps the
eMMC and SPI in reset initially and we need to write a GPIO to turn
them on before continuing the boot-up.

This adds the DTS entries for the additional regulator and makes
pinctrl and gpio3 available during SPL.  It also adds a hook to the
spl_board_init() to ensure that the regulator gets probed and enabled.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01 00:33:35 +02:00
Philipp Tomsich
0b5e7aab0e rockchip: puma-rk3399: update board_init()
The original initialisation code for board_init() was largely lifted
from the code on the EVB.  However, the RK3399-Q7 can do with a much
more concise init sequence.

This cleans up the board_init() by updating it to the essentials for
the RK3399-Q7 and getting rid of the accumulated cruft.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01 00:33:35 +02:00
Philipp Tomsich
775bd78a11 rockchip: dts: rk3399-puma: add 'same-as-spl' to the front of the boot-order
In the general case, we want to continue booting the full U-Boot
(contained in a discoverable FIT image) from the same device the SPL
stage was loaded from.  This prepends the 'same-as-spl' specifier to
our configurable boot-order to make this the default behaviour.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01 00:33:35 +02:00
Philipp Tomsich
c55addd360 rockchip: spl: rk3399: implement chip-specific board_spl_was_booted_from()
To support the new "same-as-spl" specifier in the boot-order on the
RK3399, this implements the chip-specific mapping from the information
obtainable from the BROM to a OF path name.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01 00:33:34 +02:00
Philipp Tomsich
80e9f88e67 rockchip: spl: support a 'same-as-spl'-specifier in the spl-boot-order
It is often desirable to configure the spl-boot-order (i.e. the order
that SPL probes devices to find the FIT image containing a full U-Boot)
such that it contains 'the same device the SPL stage was booted from'
early on.  To support this, we introduce the 'same-as-spl' specifier
for the spl-boot-order property.

This commit adds:
 - documentation for the new board_spl_was_booted_from() function that
   individual SoCs/boards should provide, if they can determine where
   the SPL was booted from
 - implements the new board_spl_was_booted_from() stub function
 - adds support for handling the 'same-as-spl' specifier and calling
   into the per-SoC/per-board support code.

This also updates the documentation for the 'u-boot,spl-boot-order'
property.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01 00:33:34 +02:00
Philipp Tomsich
dbad01cab5 rockchip: spl: add documentation for spl_node_to_boot_device()
In the expectation that the spl-boot-order code will eventually
gain use outside of mach-rockchip: let's add documentation on the
spl_node_to_boot_device() function, which is likely to become a
publicly exported function.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01 00:33:34 +02:00
Philipp Tomsich
3b4f87735d rockchip: bootrom: add definitions to retrieve BROM boot-source
The Rockchip BROM allows reading where it booted from from SRAM.
This adds the necessary definitions (as received from Kever) for
the location of this information in the RK3399's SRAM and naming
for the constants used.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01 00:33:34 +02:00
Philipp Tomsich
fb7406469c rockchip: rk3399: make spl_board_init board-specific
The later-stage spl_board_init (as opposed to board_init_f) should set
up board-specific details: these differ between the EVB-RK3399 and the
RK3399-Q7 (Puma).

This moves spl_board_init back into the individual boards and removes
the unneeded functionality from Puma.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:34 +02:00
Heinrich Schuchardt
861ff27757 evb-rk3399: avoid redefinition of CONFIG_ENV_OFFSET
CONFIG_ENV_OFFSET is already defined in
include/configs/rockchip-common.h

For CONFIG_ROCKCHIP_BACK_TO_BROM=y we redefine CONFIG_ENV_OFFSET
to an unsuitable value. We were lucky to get a compiler warning.

Remove the incorrect redefinition.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:34 +02:00
Kever Yang
4a18729726 rockchip: rk322x: update the sysreg number for boot mode
The boot mode for rk322x is stored in sysreg 0, update it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:34 +02:00
Elaine Zhang
f9674f5eec rockchip: dts: rk3328-evb: add i2c1 and rk805 nodes
add i2c1 and rk805 nodes to support rk805 init setting.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:33 +02:00
Elaine Zhang
dd834e26b2 configs: rk3328: add support for pmic rk8xx and regulator and i2c driver
Add defconfig for rk8xx and regulator and i2c controller.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:33 +02:00
Elaine Zhang
be93fc2476 rockchip: i2c: rk3328: support i2c for rk3328 SoC
Add compatible to support rk3328 i2c

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Heiko Schocher<hs@denx.de>
2017-10-01 00:33:33 +02:00
Philipp Tomsich
fd0a1ba52e rockchip: pinctrl: rk3368: add pinctrl for SDMMC0
Apparently, our earlier assumption that the BROM will always set up
the iomux for SDcard communication does not always hold true: when
booting U-Boot from the on-module (on the RK3368-uQ7) eMMC, the SDcard
pins are not set up and need to be configured by the pinctrl driver to
allow SD card access.

This change implements support for setting up the SDMMC pins in
pinctrl for the RK3368.

Reported-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01 00:33:33 +02:00
Philipp Tomsich
6696fe5a2f rockchip: board: lion-rk3368: avoid ATF overwriting active SPL stage
The RK3368-uQ7 ATF has been moved back to 0x100000 (1MB from the start
of DRAM) to avoid it overwriting the active SPL stage during FIT image
loading.  This change adapts the .its to match up (again) with our ATF
repository for the RK3368-uQ7.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01 00:33:33 +02:00
Jagan Teki
5d94ebedcd rk3288: vyasa: Add falcon mode support
Add Falcon mode support in vyasa rk3288 board.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:33 +02:00
Jagan Teki
532cb7f5ad rk3288: vyasa: Add TPL support
Since the size of SPL can't be exceeded 0x8000 bytes in RK3288,
it is not possible add new SPL features like Falcon mode or etc.

So add TPL stage so-that adding new features to SPL is possible.
- TPL: DRAM init, clocks
- SPL: MMC, falcon, etc

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:33 +02:00
Jagan Teki
a982d5156d armv7: rk3288: Move configure_l2ctlr to common
configure_l2ctlr will be shared between SPL and TPL so
move them into asm/arch/sys_proto.h

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:33 +02:00
Jagan Teki
d9a7dcf5b8 armv7: Move L2CTLR read/write to common
L2CTLR read/write functions are common to armv7 so, move
them in to include/asm/armv7.h and use them where ever it need.

Cc: Tom Warren <twarren@nvidia.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Backed out the change to arch/arm/mach-tegra/cache.c:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:33 +02:00
Kever Yang
f3f6591ca3 rockchip: rk322x: fix pd_bus hclk/pclk
The pd_bus hclk/pclk source is pd_bus aclk, not the PLL.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:32 +02:00
Kever Yang
5d62aba4e3 rockchip: mkimage: add support for rk3128 soc
Add support for rk3128 package header in mkimage tool.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:32 +02:00
Kever Yang
04e97e48d0 rockchip: rk3036: fix grf macro define
Some of macros definition are not correct, fix them according to TRM.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:32 +02:00
Kever Yang
21c7acc7cb rockchip: clk: fix typo in rk322x clock driver
Fix typo RK322X/RK3036 in rk322x clock driver.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:32 +02:00
Philipp Tomsich
cbe18f10e6 rockchip: rk3399: spl: convert to using BOOT_DEVICE_BOOTROM
Instead of directly calling into the back-to-bootrom code, the RK3399
common SPL implementation now uses BOOT_DEVICE_BOOTROM to trigger a
transfer back into the bootrom.

With this factored out, the spl_board_init function can not be
customised for each RK3399 board.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01 00:33:32 +02:00
Philipp Tomsich
8d35f3694f rockchip: lion-rk3368: defconfig: remove duplicate CONFIG_ENV_IS_IN_MMC
Remove a duplicate CONFIG_ENV_IS_IN_MMC assignment for the lion-rk3368
defconfig.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:32 +02:00
Kever Yang
a27290a6f8 rockchip: rk3188: ram: add support for 16bit row address
RK3188 using the same ddr_conf for both 15 bit and 16 bit row address.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Fixed compile-error by declaring 'row':]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:32 +02:00
Kever Yang
ffd1cd67da rockchip: dts: rk3229: remove dram channel info
The dram channel info will be auto detect by the driver,
we do not need it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2017-10-01 00:33:32 +02:00
Kever Yang
0176399b79 rockchip: rk322x: add sdram driver
Add driver for rk322x to support sdram initialize in SPL.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:32 +02:00
Kever Yang
f0768491db rockchip: rk3328: move sdram driver to driver/ram
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:31 +02:00
Kever Yang
c9eb7bca4b rockchip: rk3288: move sdram driver to driver/ram
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:31 +02:00
Kever Yang
5b67d7010b rockchip: rk3188: move sdram driver to driver/ram
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:31 +02:00
Kever Yang
b5934cf67c rockchip: rk3399: move sdram driver to driver/ram
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:31 +02:00
Philipp Tomsich
8e8bcccc18 rockchip: imply ADC and SARADC_ROCKCHIP for Rockchip SOCs
Enable the Rockchip SARADC driver for all Rockchip SoCs.

Note that the SARADC peripheral is available on all SoCs except the
RK3036 and RK3228.  However, as this is a DM-driver, enabling by
default will not cause any function problems (and can always be
changed from defconfig, if size is a concern).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: David Wu <david.wu@rock-chips.com>
2017-10-01 00:33:31 +02:00
David Wu
3b4cab15ac rockchip: dts: Enable SARADC for rk3399-evb
Enable the SARADC for download key pressed detect.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:31 +02:00
David Wu
6333a3bad9 rockchip: dts: Enable SARADC for rk3368-sheep
Enable the SARADC for download key pressed detect.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:31 +02:00
David Wu
0ac1ae65ea rockchip: dts: Enable SARADC for rk3368-px5-evb
Enable the SARADC for download key pressed detect.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:30 +02:00
David Wu
f957dec682 rockchip: dts: Enable SARADC for rk3328-evb
Enable the SARADC for download key pressed detect.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:30 +02:00
David Wu
0eaf58bfaa rockchip: dts: Enable SARADC for rk3288-popmetal
Enable the SARADC for download key pressed detect.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:30 +02:00
David Wu
679276bde6 rockchip: dts: Enable SARADC for rv1108-evb
Enable the SARADC for download key pressed detect.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:30 +02:00
David Wu
fdc1eccbd1 rockchip: dts: rv1108: Add SARADC node at dtsi level
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:30 +02:00
David Wu
364fc7315a rockchip: clk: Add rk3399 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:30 +02:00
David Wu
615514c16d rockchip: clk: Add rk3368 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:30 +02:00
David Wu
b375d84135 rockchip: clk: Add rk3328 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:30 +02:00
David Wu
ef4cf5ae39 rockchip: clk: Add SARADC clock support for rk3288
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:29 +02:00
David Wu
2e4ce50d1a rockchip: clk: Add rv1108 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:29 +02:00
David Wu
ae3ed042ed dm: adc: Add driver for Rockchip SARADC
The ADC can support some channels signal-ended some bits Successive Approximation
Register (SAR) A/D Converter, like 6-channel and 10-bit. It converts the analog
input signal into some bits binary digital codes.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:29 +02:00
Sam Protsenko
6ca43a58db env: ti: boot: Show boot status information
Add tracing printings to Linux/Android boot commands, so that we can see
what's going on. Helps to trace possible bugs on early stages and
improves the output for user (which is especially useful, because we
have a bunch of boot commands executing one by one).

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-29 14:07:58 -04:00
Sam Protsenko
2717c08485 env: ti: boot: Extract command for eMMC Linux boot
Extract commands for booting Linux from eMMC to separate command. It
seems more logical that way, and allows us to run the whole command set
from U-Boot shell with only one command.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-29 14:07:58 -04:00
Sam Protsenko
a0b0ff0ae6 arm: dra7xx: Fix Linux boot from eMMC
Right now on OMAP5-based boards we have only one partition defined for
Linux boot, which is rootfs. That doesn't work with bootpart=1:2 (that
is defined in include/environment/ti/boot.h). To fix Linux boot we may
either:

 1. Change bootpart to be 1:1
 2. Or add preceding partition, so that rootfs is actually 1:2

Second choice seems more reasonable, as DFU is already using similar
partition table and can rely on bootpart to be 1:2.

This patch adds "bootloader" partition. So now eMMC layout for Linux
boot looks like this:

offset               content                 size          partition
(KiB)                                        (KiB)
Reviewed-by: Tom Rini <trini@konsulko.com>

=======================================================================

0       +--------------------------------+
        | MBR/GPT header                 |   128           -
128     +--------------------------------+
        | MLO                            |   256           -
384     +--------------------------------+
        | u-boot.img                     |   1792          bootloader
2176    +--------------------------------+
        | //////////// hole //////////// |   256           -
2432    +--------------------------------+
        | U-Boot environment             |   128           -
2560    +--------------------------------+
        | U-Boot environment (redundant) |   128           -
2688    +--------------------------------+
        | rootfs                         |   remaining     rootfs
end     +--------------------------------+

=======================================================================

Guard hole appears because U-Boot environment offset was calculated for
Android partition table, which has two additional partitions in place of
that hole ("environment" and "misc" partitions).

This patch also changes rootfs offset from 2 MiB further to 2688 KiB,
so that there won't be any collisions with U-Boot environment when we
flash rootfs.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
2017-09-29 14:07:58 -04:00
Sam Protsenko
f6d245b8c5 arm: am57xx: Fix Linux boot from eMMC
Right now on OMAP5-based boards we have only one partition defined for
Linux boot, which is rootfs. That doesn't work with bootpart=1:2 (that
is defined in include/environment/ti/boot.h). To fix Linux boot we may
either:

 1. Change bootpart to be 1:1
 2. Or add preceding partition, so that rootfs is actually 1:2

Second choice seems more reasonable, as DFU is already using similar
partition table and can rely on bootpart to be 1:2.

This patch adds "bootloader" partition. So now eMMC layout for Linux
boot looks like this:

offset               content                 size          partition
(KiB)                                        (KiB)
Reviewed-by: Tom Rini <trini@konsulko.com>

=======================================================================

0       +--------------------------------+
        | MBR/GPT header                 |   128           -
128     +--------------------------------+
        | MLO                            |   256           -
384     +--------------------------------+
        | u-boot.img                     |   1792          bootloader
2176    +--------------------------------+
        | //////////// hole //////////// |   256           -
2432    +--------------------------------+
        | U-Boot environment             |   128           -
2560    +--------------------------------+
        | U-Boot environment (redundant) |   128           -
2688    +--------------------------------+
        | rootfs                         |   remaining     rootfs
end     +--------------------------------+

=======================================================================

Guard hole appears because U-Boot environment offset was calculated for
Android partition table, which has two additional partitions in place of
that hole ("environment" and "misc" partitions).

This patch also changes rootfs offset from 2 MiB further to 2688 KiB,
so that there won't be any collisions with U-Boot environment when we
flash rootfs.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
2017-09-29 14:07:57 -04:00
Karthik Tummala
8adb6ec885 arm: dts: omap3: sync DTS with Linux 4.14-rc1
This re-syncs omap3 DTS file with current file from
Linux v4.14-rc1 to ensure a consistent configuration. Upstream
Linux removed the redundant Interrupt-parent property from usbhsohci,
usbhsehci, ssi_port1 and ssi_port2 sub nodes.

Signed-off-by: Karthik Tummala <karthik@techveda.org>
2017-09-29 14:07:57 -04:00
Patrice Chotard
0cc40dfc66 dm: clk: add missing .priv_auto_alloc_size() for stm32f7
Add missing .priv_auto_alloc_size() callback.
Previously private struct stm32_clk was not allocate
which leads to unpredictable behaviour

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-29 14:07:57 -04:00
Lokesh Vutla
df518f804f ARM: dts: OMAP5+: Enable all gpios in SPL
With DM enabled, gpio numbering is assigned based on the
probed order of gpios, irrespective of the gpio base. So enable
all necessary gpios in SPL.

Fixes: edf25d94d55c (“ARM: dts: OMAP5+: Enable gpio in SPL”)
Reported-by: Gou, Hongmei <h-gou@ti.com>
Tested-by: Aparna Balasubramanian <aparnab@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-29 14:07:56 -04:00
Lokesh Vutla
ba7f58b12f configs: keystone2: env: Fix burn_uboot_spi command
Now the u-boot spi image is greater than 0x80000, increase the same
in env during spi erase.

Reported-by: Yan Liu <yan-liu@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-29 14:07:56 -04:00
Andrew F. Davis
f8e714ebfa configs: k2g_evm: Make findfdt command populate fdtfile variable
On all other platforms the command 'findfdt' populates the variable
'fdtfile', but on K2G we only populate 'name_fdt'. The generic boot
and automation scripts fail when 'findfdt' is not populated, fix
this for K2G.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2017-09-29 14:07:56 -04:00
Andrew F. Davis
373358f27a configs: am43xx_evm: Avoid relocation onto firewall at the end of DRAM
On secure devices the initial secure software may install a firewall at
the end of DRAM, define protected RAM to avoid space.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2017-09-29 14:07:55 -04:00
Madan Srinivas
0830d72bb9 arm: am33xx: security: adds auth support for encrypted images
This patch adds support for authentication of both plain
text and encrypted binaries. A new SECDEV package is needed
to enable encryption of binaries by default for AM3x.

The ROM authentication API detects encrypted images at
runtime and automatically decrypts the image if the
signature verification passes.

Addition of encryption on AM3x results in a change in the
image format. On AM4x, AM5x and, on AM3x devices signing
clear test images, the signature is appended to the end of the
binary.

On AM3x, when the SECDEV package is used to create signed
and encrypted images, the signature is added as a header
to the start of the binary. So the binary size calculation
has been updated to reflect this change.

The signing tools and encrypted image format for AM3x
cannot be changed to behave like AM4x and AM5x to
maintain backward compatibility with older Sitara
M-Shield releases.

Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
2017-09-29 14:07:55 -04:00
Andrew F. Davis
c2dca3374a defconfigs: Add a config for AM335x High Security EVM with UART Boot support
Add a new defconfig file for the AM335x High Security EVM. This config
is specific for the case of UART booting

Signed-off-by: Andrew F. Davis <afd@ti.com>
2017-09-29 14:07:55 -04:00
Adam Ford
b85781c2a8 ARM: omap3: am3517-evm: Add device tree and DM support
With the device tree ported from Linux 4.13, this enables
Driver Model and Device Tree support for the am3517-evm

Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Derald D. Woods <woods.technical@gmail.com>
2017-09-29 14:07:54 -04:00
Adam Ford
a56fd949a5 arm: dts: am3517_evm: Sync DTS files with Linux 4.13-RC5
To keep the DTS and DTSI files clean and in sync with Linux, new
u-boot.dtsi files are added.

There are some spacing issues in the patch, but they appear to be
present in the Linux source files.  I'll try to get to fixing them there,
and do a future re-sync at a later date.

Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Derald D. Woods <woods.technical@gmail.com>
2017-09-29 14:07:54 -04:00
Ulf Magnusson
4e1102f6de kconfiglib: update with 'imply' support
Corresponds to 375506d (File writing nit) from upstream
(https://github.com/ulfalizer/Kconfiglib).

Adds proper 'imply' support and fixes a few minor issues, one of which
previously triggered the following weird warning:

  configs/taurus_defconfig: /tmp/tmpisI45S:6: warning: assignment to SPL_LDSCRIPT changes mode of containing choice from "arch/$(ARCH)/cpu/u-boot-spl.lds" to "y"

The change in 8639f69 (genconfig.py: Print defconfig next to warnings)
was reapplied.

tools/moveconfig.py previously depended on a hack that merged 'select's
with 'imply's. It was modified to look at the union of
Symbol.get_selected_symbols() and Symbol.get_implied_symbols(), which
should give the same behavior.

tools/genboardscfg.py was verified to produce identical board.cfg's
before and after the change.

Signed-off-by: Ulf Magnusson <ulfalizer@gmail.com>
2017-09-29 14:07:54 -04:00
Heinrich Schuchardt
2719ae3346 scripts/checkpatch: add missing spelling.txt
Checkpatch can use two dictionaries for finding typos:
* scripts/spelling.txt
* /usr/share/codespell/dictionary.txt
  which comes with package codespell and is selected by parameter
  --codespell

If the file scripts/spelling.txt is missing, a warning is shown.

Add the spelling.txt file from the Linux kernel 4.13 source.

We can later add our own typo corrections.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Dan Murphy <dmurphy@ti.com>
2017-09-29 14:07:53 -04:00
Stephen Warren
117eeb7f84 test/py: fix anchors in HTML status report
The current code wraps a pre tag inside an a tag. For some reason, this
causes at least Firefox to attempt to drag the pre section content when
using a mouse drag to select text. Re-order the tags so that the text can
be selected using the mouse, at least if you start the drag outside the
text (after the end of the line, for example).

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2017-09-29 14:07:53 -04:00
Stephen Warren
2d26bf6c26 test/py: add skip marker for reliance on tools
Some tests use external tools (executables) during their operation. Add
a test.py mark to indicate this. This allows those tests to be skipped if
the required tool is not present.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2017-09-29 14:07:53 -04:00
Stephen Warren
d5170448ae test/py: provide more information about test skip reason
When skipping tests, explicitly mention the board type or config option
that caused the skip. This will help people understand/fix any issues.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2017-09-29 14:07:52 -04:00
Stephen Warren
af3fae0b1b test/py: Document required tools/packages
Some tests rely on external tools. Mention these in the test/py README.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2017-09-29 14:07:52 -04:00
Tom Rini
ff6c3125e7 TI: ARCH_OMAP2PLUS: Enable SPL_STACK_R and provide default value
On ARCH_OMAP2PLUS platforms we know what the DDR layout is going to be,
and that it is safe to use SPL_STACK_R and provide a default value for
it.  select this and re-sync the defconfigs.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-29 14:07:51 -04:00
Adam Ford
c774207f48 ARM: da850-evm: Enable DM_I2C
With DM now enabled with the device tree pulled from Linux, we can
enable DM_I2C in U-Boot.

Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Add DM_I2C_COMPAT to da850_am18xxevm to fix warning]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-29 14:07:18 -04:00
Rob Clark
40186ee213 video: test: Add ANSI escape sequence tests
This adds tests for clear, set-cursor and color escape sequences.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-09-29 17:59:58 +02:00
Rob Clark
a7495ac872 video: test: Helper for writing strings
I'll need some more of this, let's not just copy-pasta the
vidconsole_put_char() loop.

Named to match vidconsole_put_char() in case that is ever useful
outside of the tests.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-09-29 17:58:45 +02:00
Rob Clark
703d885c22 dm: video: Add color ANSI escape sequence support
Note that this doesn't differentiate (due to lack of information in
video_priv) between different possible component orders for 32bpp.
But the main user at this point is efi_loader, and GOP expects xBGR
so any video drivers that this is incorrect for already have problems.
(Also, conveniently, this matches what simple-framebuffer bindings
expect for kernels that use the simple-framebuffer DT binding to
take over the bootloader display.)

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-09-29 17:55:16 +02:00
Rob Clark
a085aa1f27 dm: video: Add basic ANSI escape sequence support
Really just the subset that is needed by efi_console.  Perhaps more will
be added later, for example color support would be useful to implement
efi_cout_set_attribute().

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-29 17:53:21 +02:00
Rob Clark
889808da9b dm: video: Fix cache flushes
Content can come to screen via putc() and we cannot always rely on
updates ending with a puts().  This is the case with efi_console output
to vidconsole.  Fixes corruption with Shell.efi.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-09-29 17:51:29 +02:00
Wenyou Yang
40f3429415 board: at91sam9x5ek: Convert to CONFIG_DM_VIDEO
Convert the board to support the video driver model, add the device
tree node, and remove the unnecessary code.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-29 17:51:56 +02:00
Wenyou Yang
e974b08119 board: sama5d4_xplained: Convert to CONFIG_DM_VIDEO
Convert the board to support the video driver model, add the device
tree node, and remove the unnecessary code.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-29 17:51:22 +02:00
Wenyou Yang
4b0467db53 board: sama5d4ek: Convert to CONFIG_DM_VIDEO
Convert the board to support the video driver model, add the device
tree node, and remove the unnecessary code.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-29 17:50:44 +02:00
Wenyou Yang
fe32c6d159 board: sama5d3xek: Convert to CONFIG_DM_VIDEO
Convert the board to support the video driver model, add the device
tree node, and remove the unnecessary code.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-29 17:50:04 +02:00
Wenyou Yang
d2cd09bb44 board: sama5d2_xplained: Convert to CONFIG_DM_VIDEO
Convert the board to support the video driver model, add the device
tree node, and remove the unnecessary code.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-29 17:48:56 +02:00
Adam Ford
f4fad71612 arm: da850-evm: Enable MTD Parts in SPI Flash
There is a discrepency between U-Boot and Linux on the partition map.
This enabes the MTD parts to pass MTD partition information from U-Boot to
Linux.  Linux already has a pending patch to enable MTD PARTS in
davinci_all_defconfig

Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
2017-09-29 10:52:22 -04:00
Adam Ford
a4670f8ebb arm: da850-evm: Enable DM and device tree support for da850-evm
With the device tree ported and DM compatible drivers, enable:
OF_CONTROL, DM_SPI, DM_SPI_FLASH and DM_SERIAL

Note: DM_SERIAL is not enabled for da850evm_direct_nor_defconfig
yet.

Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
2017-09-29 10:52:21 -04:00
Adam Ford
ab0ac27242 spi: davinci_spi: Add da830-spi support for DM
The DM support is already in the driver, so add
da830-spi to the compatible list.

Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
2017-09-29 10:52:20 -04:00
Adam Ford
4c70755986 arm: dts: da850: Migrate da850-evm DTS files from Linux 4.13-RC5
A few small additional items are needed to support DM_SPI and
DM_SERIAL, so those were added to da850-evm-u-boot.dtsi

Signed-off-by: Adam Ford <aford173@gmail.com>
2017-09-29 10:52:20 -04:00
Tom Rini
ec4e99a4a2 Merge git://git.denx.de/u-boot-mmc 2017-09-28 23:31:11 -04:00
Masahiro Yamada
3d3108d459 mmc: sdhci-cadence: set timing mode register depending on frequency
The MMC framework in U-Boot does not support a systematic API for
timing switch like mmc_set_timing() in Linux.

U-Boot just provides a hook to change the clock frequency via
mmc_set_clock().  It is up to drivers if additional register
settings are needed.

This driver needs to set a correct timing mode into a register when
it migrates to a different speed mode.  Only increasing clock frequency
could result in setup/hold timing violation.

The timing mode should be decided by checking MMC_TIMING_* like
drivers/mmc/host/sdhci-cadence.c in Linux, but "timing" is not
supported by U-Boot for now.  Just use mmc->clock to decide the
timing mode.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-09-29 11:34:22 +09:00
Seung-Woo Kim
b016b58542 spl: spl_mmc: add __maybe_unused to mmc_load_image_raw_sector()
If there are no CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR and CONFIG_SPL_OS_BOOT,
there is unused-function build warning. Add __maybe_unused macro
to remove the warning.

Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
2017-09-29 11:23:45 +09:00
Marek Vasut
9f13021f81 mmc: uniphier-sd: Add vqmmc regulator support
Add initial support for setting the vqmmc regulator. Since we do not
support 1V8 modes, set the regulator to 3V3 and enable it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-09-29 11:17:29 +09:00
Marek Vasut
d6c40031d5 mmc: uniphier-sd: Update the file to match V3 patchset
Old version of the uniphier-sd 64bit IO support patchset V1 was
applied by the maintainer, update the uniphier-sd.c with the
changes from the V3 of the patchset.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-09-29 11:14:14 +09:00
Tom Rini
9969306971 Merge git://git.denx.de/u-boot-nds32 2017-09-28 09:03:05 -04:00
Patrice Chotard
b312c590bc mmc: Add MMC support for stm32h7 Socs
This patch adds SD/MMC support for STM32H7 SoCs.

Here is an extraction of SDMMC main features, embedded in
STM32H7 SoCs.
The SD/MMC block include the following:
 _ Full compliance with MultiMediaCard System Specification
   Version 4.51. Card support for three different databus modes:
   1-bit (default), 4-bit and 8-bit.
 _ Full compatibility with previous versions of MultiMediaCards
   (backward compatibility).
 _ Full compliance with SD memory card specifications version 4.1.
   (SDR104 SDMMC_CK speed limited to maximum allowed IO speed,
    SPI mode and UHS-II mode not supported).
 _ Full compliance with SDIO card specification version 4.0.
   Card support for two different databus modes: 1-bit (default)
   and 4-bit. (SDR104 SDMMC_CK speed limited to maximum allowed IO
   speed, SPI mode and UHS-II mode not supported).
 _ Data transfer up to 208 Mbyte/s for the 8 bit mode.
   (depending maximum allowed IO speed).
 _ Data and command output enable signals to control external
   bidirectional drivers.

The current version of the SDMMC supports only one SD/SDIO/MMC card
at any one time and a stack of MMC Version 4.51 or previous.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-28 20:23:19 +09:00
rick
9c7ffc94dc nds32: Fix io.h warning message about readb
It is caused from asm/io.h declare different input type.

Signed-off-by: rick <rick@andestech.com>
2017-09-28 13:16:54 +08:00
Marek Vasut
9c4c79f432 ARM: rmobile: Zap ad-hoc PFC and GPIO setup in board files
At long last, nuke all this ad-hoc setup in board files in favor of
letting PFC pinmux and GPIO drivers do the same job, but based on DT
description of the hardware rather than this board-file ugliness.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-28 06:54:06 +09:00
Marek Vasut
793afcde6c ARM: rmobile: Switch to DM PFC pinmux and GPIO driver
Enable the PFC pinmux and GPIO drivers and disable the SH GPIO combo
driver. This allows the drivers to obtain pinmux and GPIO configuration
from DT rather than hard-coding it in board files.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-28 06:54:06 +09:00
Marek Vasut
f5f6959444 gpio: rmobile: Add Renesas RCar GPIO driver
Add GPIO driver for the Renesas RCar SoCs . The driver currently supports
only the RCar Gen3 R8A7795 and R8A7796 SoCs, but is easily extensible for
the other RCar SoCs as well.

This driver is meant to replace the pinmux part of SH_GPIO_PFC driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-28 06:54:06 +09:00
Marek Vasut
910df4d07e pinctrl: rmobile: Add Renesas RCar pincontrol driver
Add PFC pincontrol driver for the Renesas RCar Gen3 R8A7795 and R8A7796
SoCs. This driver uses the PFC pin tables from Linux, thus letting us
share the occassional fixes to those tables. This driver also has a DT
support, so the pinmux is configured from DT instead of the ad-hoc setup
in board file.

This driver is meant to replace the pinmux part of SH_GPIO_PFC driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-28 06:54:06 +09:00
Marek Vasut
0e9b18c376 ARM: rmobile: Enable DM regulator support
Regulators are needed for the MMC framework to let it toggle the SD power.
Enable DM regulator support and support for fixed and GPIO regulator.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-28 06:51:37 +09:00
Marek Vasut
9ac9c341f9 ARM: rmobile: Switch to UniPhier SD driver on Gen3
The UniPhier SD driver handles the same Matsushita IP as is used
in the Renesas RCar SoCs, yet the driver is significantly better
than the SH SDHI one. Switch over to the Uniphier driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-28 06:38:30 +09:00
Tom Rini
6e9b109aa9 Merge git://git.denx.de/u-boot-usb 2017-09-27 09:39:48 -04:00
Seung-Woo Kim
a939af0c74 usb: dwc2: Align size of invalidating dcache before starting DMA
During using dwc2 usb gadget, if usb message size is too small,
following cache misaligned warning is shown:

   CACHE: Misaligned operation at range [bfdbcb00, bfdbcb04]

Align size of invalidating dcache before starting DMA to remove the
warning.

Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
2017-09-27 12:12:23 +02:00
Bin Meng
2e5026a2f0 usb: kbd: Set a default polling mechanism for USB keyboard
The choice of "USB keyboard polling" cannot be optional as without
one mechanism being set, it just doesn't work. Set the default one
to CONFIG_SYS_USB_EVENT_POLL.

Fixes: ecad7051 ("configs: Migrate all of the existing USB symbols, except fastboot")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-27 12:12:23 +02:00
Philipp Tomsich
6e652e3a7d usb: host: ehci-generic: convert to livetree
Update the generic EHCI driver to support a live tree.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-27 12:12:23 +02:00
Philipp Tomsich
a9d3037a8e usb: dwc2: convert to livetree
Update the DWC2 USB driver to support a live tree.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-27 12:12:22 +02:00
Philipp Tomsich
32c8eee37f rockchip: xhci: Convert to livetree
Update the Rockchip xhci wrapper driver to support a live device tree.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-27 12:12:22 +02:00
Bin Meng
ea7fad9101 dm: usb: storage: Fix broken read/write when both EHCD and xHCD are enabled
When EHCD and xHCD are enabled at the same time, USB storage device
driver will fail to read/write from/to the storage device attached
to the xHCI interface, due to its transfer blocks exceeds the xHCD
driver limitation.

With driver model, we have an API to get the controller's maximum
transfer size and we can use that to determine the storage driver's
capability of read/write.

Note: the non-DM version driver is still broken with xHCD and the
intent here is not to fix the non-DM one, since the xHCD itself is
already broken in places like 3.0 hub support, etc.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-27 12:12:22 +02:00
Bin Meng
6158d0b424 usb: storage: Refactor to use max_xfer_blk from struct us_data
This adds a new memeber max_xfer_blk in struct us_data to record
the maximum number of transfer blocks for the storage device.

It is set per HCD setting, and so far is to 65535 for EHCD and 20
for everything else.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-27 12:12:22 +02:00
Bin Meng
a23aa66baa dm: usb: ehci: Implement get_max_xfer_size() operation
EHCD can handle any transfer length as long as there is enough free
heap space left, hence set the theoretical max number SIZE_MAX.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-27 12:12:22 +02:00
Bin Meng
022ceacaf8 dm: usb: xhci: Implement get_max_xfer_size() operation
xHCD allocates one segment which includes 64 TRBs for each endpoint
and the last TRB in this segment is configured as a link TRB to form
a TRB ring. Each TRB can transfer up to 64K bytes, however data
buffers referenced by transfer TRBs shall not span 64KB boundaries.
Hence the maximum number of TRBs we can use in one transfer is 62.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-27 12:12:22 +02:00
Bin Meng
3e59f59015 dm: usb: Add a new USB controller operation 'get_max_xfer_size'
The HCD may have limitation on the maximum bytes to be transferred
in a USB transfer. USB class driver needs to be aware of this.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-27 12:12:21 +02:00
Marek Vasut
7489d22a3c usb: xhci: Set number of event segments and entries to 1
The Linux kernel driver sets the number of event segments and entries
to 1 , while the initial import of the xhci code set that values to 3
for reasons unknown. While most controllers are fine with more event
segments with more entries, there are standard-conformant controllers
(ie. Renesas RCar xHCI) which only support 1 event segment.

Set the number of event segments and event entries back to 1 to allow
such controllers to work with U-Boot xHCI stack. Note that the Renesas
controller correctly indicates ERST Max = 1 in HCSPARAMS2[7:4] .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
2017-09-27 12:12:21 +02:00
Lukasz Majewski
ca1ac16da0 sf: bar: Clean BA24 Bank Address Register bit after read/write/erase operation
The content of Bank Address Register (BAR) is volatile. It is cleared
after power cycle or reset command (RESET F0h).

Some memories (like e.g. s25fl256s) use it to access memory larger than
0x1000000 (16 MiB).

The problem shows up when one:

1. Reads/writes/erases memory > 16 MiB
2. Calls "reset" u-boot command (which is not causing BAR to be cleared)

In the above scenario, the SoC ROM sends 0x000000 address to read SPL.
Unfortunately, the BA24 bit is still set and hence it receives content
from 0x1000000 (16 MiB) memory address.
As a result the SoC aborts and we hang. Only power cycle can take the
SoC out of this state.

How to reproduce/test:

sf probe; sf erase 0x1200000 0x800000; reset
sf probe; sf erase 0x1200000 0x800000; sf write 0x11000000 0x1200000 0x800000; reset
sf probe; sf read 0x11000000 0x1200000 0x800000; reset

Signed-off-by: Lukasz Majewski <lukma@denx.de>
[Fixed comment text on clean_bar function]
Signed-off-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-09-27 13:31:59 +05:30
Andre Przywara
ba09440131 SPL: SPI: sunxi: add SPL FIT image support
The sunxi-specific SPI load routine only knows how to load a legacy
U-Boot image.
Teach it how to handle FIT images as well, simply by providing the
existing SPL FIT loader with the right loader routine to access the SPI
NOR flash.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reported-by: Peter Kosa <kope@madnet.sk>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-09-27 12:45:32 +05:30
Tom Rini
9241265f29 Merge git://www.denx.de/git/u-boot-cfi-flash 2017-09-26 19:38:04 -04:00
Heinrich Schuchardt
f66bc0e0be GPT: incomplete initialization in allocate_disk_part
memset(newpart, '\0', sizeof(newpart));
only initializes the firest 4 or 8 bytes of *newpart and not the whole
structure disk_part.

We should use sizeof(struct disk_part).

Instead of malloc and memset we can use calloc.

Identified by cppcheck.

Fixes: 09a49930e4 GPT: read partition table from device into a data structure
Reported-by: Coverity (CID: 167228)
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-26 12:54:42 -04:00
Tom Rini
0cc8c3064d Merge git://www.denx.de/git/u-boot-marvell 2017-09-26 08:26:57 -04:00
Marek Vasut
72443c7f7d mtd: cfi: Add support for status register polling
The status register is optional in the AMD command sets, but it's
presence can be checked by reading out CFI table entry 0xc bit 0.
If the register is present, prefer using it's bit 7 to determine
if the flash is busy over reading the flash ; this is needed ie.
on Hyperflash memories.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-09-26 10:57:53 +02:00
Marek Vasut
1ec0a37e1c mtd: cfi: Zap cfi_flash_base in DM case
Embed the flash base into struct flash_info instead of having ad-hoc
static array in the code. This does not only remove static variable,
but also allows CFI-like controllers, ie. HyperFlash ones, to use most
of the CFI flash code by populating the flash_info with matching base
address.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-09-26 10:57:53 +02:00
Baruch Siach
0d106f1e73 arm: mvebu: clearfog: document boot from UART
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-09-26 06:53:26 +02:00
Baruch Siach
f3a88e2ca1 arm: mvebu: fix boot from UART on ClearFog Base
The ClearFog Base boot from UART when setting the DIP switches to 01001.
Unfortunately, the SPL code sometimes fails to detect the UART boot
method at run-time. Add an alternative SAR UART boot value to fix this.

Note that this alternative value is not documented (Armada 38x Hardware
Specifications, Table 48). But experimentations showed it on the
ClearFog Base.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-09-26 06:53:18 +02:00
Chris Packham
c3ab274444 ARM: mvebu: handle unused DRAM banks with ECC enabled
dram_ecc_scrubbing() had code to skip unused DRAM banks but it would not
work because mvebu_sdram_bs() returns 0 and the code was subtracting 1
before checking the size. Remove the -1 from the bank size and the +1
from the total which will skip unused banks and still calculate the
correct size. Put the -1 where it is needed for scrubbing via the xor
engine.

Reported-by: Joshua Scott <joshua.scott@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-09-26 06:52:57 +02:00
Chris Packham
0a91e1cce4 ARM: mvebu: add SAR frequency values for 1.8/2.0GHz
The Armada-38x has 1.8GHz and 2.0GHz variants. Add entries for these
variants to the sar_freq_tab.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-09-26 06:51:54 +02:00
Joshua Scott
631407c5c0 ARM: mvebu: add additional information to board_add_ram_info()
Display more information about the current RAM configuration. With these
changes the output on a 88F6820 board is

  SoC:   MV88F6820-A0 at 1600 MHz
  DRAM:  2 GiB (800 MHz, 32-bit, ECC not enabled)

Signed-off-by: Joshua Scott <joshua.scott@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-09-26 06:51:50 +02:00
Chris Packham
0f8031a333 ARM: mvebu: Add SoC IDs for Marvell's integrated CPUs
These SoCs are network packet processors (switch chips) with integrated
ARMv7 cores. They share a great deal of commonality with the Armada-XP
CPUs.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-09-26 06:51:43 +02:00
Stefan Roese
a30d3e7777 arm: mvebu: Remove theadorable_defconfig
Currently, we support 2 "theadorable" MVEBU build targets. One with a
stripped down configuration (theadorable) and one with a full blown
configuration (theadorable_debug), including PCI, ethernet etc. When
we introduced these configs, the plan was to remove the debug version
at some point. But now it seems better to keep the full-blown version
and remove the "non-debug" version instead.

At a later stage, I will rename the remaining "theadorable_debug"
target into a more fitting one.

Signed-off-by: Stefan Roese <sr@denx.de>
2017-09-26 06:51:37 +02:00
Chris Packham
7654f62f4e ARM: mvebu: Convert CONFIG_MVNETA to Kconfig
This converts the following to Kconfig:
   CONFIG_MVNETA

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-09-26 06:51:30 +02:00
Tom Rini
3efd018954 Merge git://git.denx.de/u-boot-spi 2017-09-25 17:28:31 -04:00
Tom Rini
78cb000b84 Merge git://git.denx.de/u-boot-mmc 2017-09-25 17:28:16 -04:00
Suresh Gupta
1050998728 spi: fsl_qspi: Copy 16 byte aligned data in TX FIFO
In some of the QSPI controller version, there must be atleast
128bit data available in TX FIFO for any pop operation otherwise
error bit will be set. The code will not make any behavior change
for previous controller as the transfer data size in ipcr register
is still the same.

Patch is tested on LS1046A which do not require 16 bytes aligned and
LS1088A which require 16 bytes aligned data in TX FIFO

Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Anupam Kumar <anupam.kumar_1@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-09-25 15:45:15 +05:30
Vsevolod Gribov
db10809c17 Fix s25fl256s position in spi_flash_ids list
Spansion S25FS256S and S25FL256S flashes have equal JEDEC ID and ext ID.
As far as S25FL256S occures in spi_flash_ids before S25FS256S, U-Boot
incorrectly detects FS flash as FL. Thus its better to compare with
S25FS256S first.

Signed-off-by: Vsevolod Gribov <vgribov@larch-networks.com>
[Added S-o-b]
Signed-off-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-09-25 13:00:34 +05:30
Marek Vasut
545a438222 sf: Fix S25FL116K entry
The flash chip is 2 MiB , organized as 32 x 64 kiB sectors .
Rectify the entry to match the datasheet, reality and Linux SNOR IDs.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-09-25 12:54:10 +05:30
Yogesh Gaur
811b6be166 mtd/spi: Add MT35XU512ABA1G12 NOR flash support
Add MT35XU512ABA1G12 parameters to NOR flash parameters array.

The MT35XU512ABA1G12 only supports 1 bit mode and 8 bits. It can't support
dual and quad. Supports subsector erase with 4KB granularity, have support
of FSR(flag status register) and flash size is 64MB.

Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-09-25 12:51:20 +05:30
Suresh Gupta
1c631da459 spi: fsl_qspi: Add controller busy check before new spi operation
It is recommended to check either controller is free to take
new spi action. The IP_ACC and AHB_ACC bits indicates that
the controller is busy in IP or AHB mode respectively.
And the BUSY bit indicates that controller is currently
busy handling a transaction to an external flash device

Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-09-25 12:49:56 +05:30
Peng Fan
994266bdff spi: mxc_spi: support driver model
Add driver model support for mxc spi driver.
Most functions are restructured to be reused by DM and non-DM.
Tested on mx6slevk/mx6qsabresd board.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-09-25 12:47:59 +05:30
Tom Rini
1f6049e250 tools/mkimage: Make the path to the dtc binary that mkimage calls configurable
In some cases, such as FreeBSD, the path to an alternative dtc needs to
be used.  Rather than override the one given in the Makefile on the
command line, make this part of the build configuration.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-24 07:33:03 -04:00
Tom Rini
36dd5f1b8a dtc: Switch to building and using our own dtc unless provided
This makes us act like the Linux Kernel does and allow for dtc to be
provided externally but otherwise we use the version of dtc that is
included in the sources.  This in turn means that we can drop the
checkdtc logic.  We select DTC in the cases where we will need the dtc
tool provided.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-24 07:32:24 -04:00
Marek Vasut
286056d28c ARM: rmobile: Enable GPIO command
This command is convenient for manipulating the GPIOs, so enable it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-24 14:13:05 +09:00
Marek Vasut
a09a5c88bf ARM: rmobile: Remove SCIF clock configuration from board files
The configuration is now fully performed by the SCIF and clk drivers,
so remove it from the board file.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-24 14:12:07 +09:00
Marek Vasut
08c8888253 ARM: rmobile: Remove AVB clock configuration from board files
The configuration is now fully performed by the AVB and clk drivers,
so remove it from the board file.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-24 14:12:07 +09:00
Marek Vasut
667d13fbfa ARM: rmobile: Remove SD clock configuration from board files
The configuration is now fully performed by the SD and clk drivers,
so remove it from the board file.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-24 14:12:07 +09:00
Marek Vasut
891ac390b8 ARM: dts: rmobile: Add PHY reset GPIO
The PHY reset GPIOs were missing from the DT, add them.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-24 14:12:07 +09:00
Marek Vasut
791c174d58 serial: sh: Enable clock if available
If the clock framework provides the driver with valid clock,
enable them, otherwise the SCIF might not work if the clock
are not enabled prior to the driver probe.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-24 14:12:07 +09:00
Marek Vasut
bddb44e94a net: ravb: Add PHY reset GPIO support
Add support for obtaining PHY reset GPIO from DT and toggling it
before configuring the PHY to put the PHY into defined state.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-24 14:12:07 +09:00
Marek Vasut
849ab0a66f clk: rmobile: Add RPC hyperflash clock
Add missing RPC hyperflash entry into the clock driver tables.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-24 14:12:07 +09:00
Marek Vasut
4b20eef382 clk: rmobile: Add support for setting SDxCKCR
The SDxCKCR must be configured correctly, otherwise the SDIF can be
unstable. This is done in board files thus far, but those are going
away, so move the setting of SDxCKCR into the correct place.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-24 14:12:07 +09:00
Marek Vasut
8103bc57f9 ARM: rmobile: Place initial stack right below U-Boot
Place the stack right below U-Boot so it's not in the way in case
U-Boot grows too much.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-24 14:12:07 +09:00
Marek Vasut
7208d903eb ARM: rmobile: Move CONFIG_CMD_ from rcar-gen3-common to configs
Just move those config options from macros to configs.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-24 14:12:07 +09:00
Tom Rini
2d4c225993 scripts/dtc: Update to upstream version v1.4.4-50-gfe50bd1ecc1d
This adds the following commits from upstream:

fe50bd1ecc1d fdtget: Split out cell list display into a new function
62d812308d11 README: Add a note about test_tree1.dts
5bed86aee9e8 pylibfdt: Add support for fdt_subnode_offset()
46f31b65b3b3 pylibfdt: Add support for fdt_node_offset_by_phandle()
a3ae43723687 pylibfdt: Add support for fdt_parent_offset()
a198af80344c pylibfdt: Add support for fdt_get_phandle()
b9eba92ea50f tests: Return a failure code when any tests fail
155faf6cc209 pylibfdt: Use local pylibfdt module
50e5cd07f325 pylibfdt: Add a test for use of uint32_t
ab78860f09f5 pylibfdt: Add stdint include to fix uint32_t
36f511fb1113 tests: Add stacked overlay tests on fdtoverlay
1bb00655d3e5 fdt: Allow stacked overlays phandle references
a33c2247ac8d Introduce fdt_setprop_placeholder() method
0016f8c2aa32 dtc: change default phandles to ePAPR style instead of both
e3b9a9588a35 tests: fdtoverlay unit test
42409146f2db fdtoverlay: A tool that applies overlays
aae22722fc8d manual: Document missing options
13ce6e1c2fc4 dtc: fix sprintf() format string error, again
d990b8013889 Makefile: Fix build on MSYS2 and Cygwin
51f56dedf8ea Clean up shared library compile/link options
21a2bc896e3d Suppress expected error message in fdtdump test
2a42b14d0d03 dtc: check.c fix compile error
a10cb3c818d3 Fix get_node_by_path string equality check
548aea2c436a fdtdump: Discourage use of fdtdump
c2258841a785 fdtdump: Fix over-zealous version check
9067ee4be0e6 Fix a few whitespace and style nits
e56f2b07be38 pylibfdt: Use setup.py to build the swig file
896f1c133265 pylibfdt: Use Makefile constructs to implement NO_PYTHON
90db6d9989ca pylibfdt: Allow setup.py to operate stand-alone
e20d9658cd8f Add Coverity Scan support
b04a2cf08862 pylibfdt: Fix code style in setup.py
1c5170d3a466 pylibfdt: Rename libfdt.swig to libfdt.i
580a9f6c2880 Add a libfdt function to write a property placeholder
ab15256d8d02 pylibfdt: Use the call function to simplify the Makefile
9f2e3a3a1f19 pylibfdt: Use the correct libfdt version in the module
e91c652af215 pylibfdt: Enable installation of Python module
8a892fd85d94 pylibfdt: Allow building to be disabled
741cdff85d3e .travis.yml: Add builds with and without Python library prerequisites
14c4171f4f9a pylibfdt: Use package_dir to set the package directory
89a5062ab231 pylibfdt: Use environment to pass C flags and files
4e0e0d049757 pylibfdt: Allow pkg-config to be supplied in the environment
6afd7d9688f5 Correct typo: s/pylibgfdt/pylibfdt/
756ffc4f52f6 Build pylibfdt as part of the normal build process
8cb3896358e9 Adjust libfdt.h to work with swig
b40aa8359aff Mention pylibfdt in the documentation
12cfb740cc76 Add tests for pylibfdt
50f250701631 Add an initial Python library for libfdt
cdbb2b6c7a3a checks: Warn on node name unit-addresses with '0x' or leading 0s
4c15d5da17cc checks: Add bus checks for simple-bus buses
33c3985226d3 checks: Add bus checks for PCI buses

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-23 17:33:10 -04:00
Tom Rini
d6fc90ced4 scripts/dtc: Update to upstream version v1.4.4
This adds the following commits from upstream:

558cd81bdd43 dtc: Bump version to v1.4.4
c17a811c62eb fdtput: Remove star from value_len documentation
194d5caaefcb fdtget: Use @return to document the return value
d922ecdd017b tests: Make realloc_fdt() really allocate *fdt
921cc17fec29 libfdt: overlay: Check the value of the right variable
9ffdf60bf463 dtc: Simplify asm_emit_string() implementation
881012e44386 libfdt: Change names of sparse helper macros
bad5b28049e5 Fix assorted sparse warnings
672ac09ea04d Clean up gcc attributes
49300f2ade6a dtc: Don't abuse struct fdt_reserve_entry

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-23 17:33:06 -04:00
Tom Rini
c0e032e009 scripts/dtc: Update to upstream version v1.4.3
Using the update-dtc-source.sh script from Linux v4.14-rc1 import the
portions of dtc that we require.  We bring in update-dtc-source.sh and
scripts/dtc/Makefile from Linux v4.14-rc1.  Rework DTC_FLAGS handling to
not require a test.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-23 17:33:03 -04:00
Tom Rini
0929863aff Merge git://git.denx.de/u-boot-socfpga 2017-09-23 17:32:53 -04:00
Tom Rini
6ef71c61f6 Merge git://git.denx.de/u-boot-fsl-qoriq 2017-09-23 09:43:09 -04:00
Frank Kunz
a7d5b6c668 arm: socfpga: Configuration for EFI boot on DE0-nano-SoC
For EFI boot GPT partition table support is needed as well
as the part command and also the SPL needs to fallback to
other boot methods after parse the SPL header.

Signed-off-by: Frank Kunz <mailinglists@kunz-im-inter.net>
2017-09-23 15:13:20 +02:00
Masahiro Yamada
5e8c39d4f4 ARM: socfpga: fix duplicate const specifier warning
GCC 7.1 warns:
duplicate ‘const’ declaration specifier [-Wduplicate-decl-specifier]

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-09-23 15:13:20 +02:00
Masahiro Yamada
2aca29557d ARM: socfpga: remove unneeded NAND config options
CONFIG_NAND_DENALI select's CONFIG_SYS_NAND_SELF_INIT, so the
NAND initialization process is driven by the driver itself.
CONFIG_SYS_NAND_MAX_CHIPS and CONFIG_SYS_NAND_BASE are unused.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-09-23 15:13:20 +02:00
Yangbo Lu
09c6778d9f armv8: ls1046ardb: disable PPA loading during SPL stage for SD boot
PPA loading during SPL stage is not required for nornal
SD boot scenario.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22 12:49:51 -07:00
Yangbo Lu
e2c43a4242 armv8: ls1043ardb: disable PPA loading during SPL stage for SD boot
PPA loading during SPL stage is not required for nornal
SD boot scenario.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22 12:49:36 -07:00
Yangbo Lu
3c7d647e11 armv8: ls1043a: disable IFC in SPL only when QSPI is used
Current u-boot disables IFC support for SD boot on all ls1043a
boards. Actually IFC only conflicts with QSPI on ls1043a hardware.
Only when QSPI is used, IFC should be disabled. Otherwise,
the u-boot with ls1043aqds_sdcard_ifc_defconfig would not work.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22 12:49:30 -07:00
Priyanka Jain
b5dfd47581 board/ls2080ardb: Update board env based on SoC
As per current implementation, default value of board env is
based on board filename i.e ls2080ardb.

With distro support changes, this env is used to decide upon
kernel dtb which is different for other SoCs (ls2088a, ls2081a)
combination supported with this board.

Add support to modify board env at runtime based on SoC type

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22 12:49:14 -07:00
Priyanka Jain
8472d8765b board/ls2080ardb: Add mcmemsize variable in default env
For most of ls2080ardb use-cases, mc private DRAM block is required
to be of 1.75GB.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
[YS: this reservation needs to be reduced if memory is not enough]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22 12:46:46 -07:00
Sriram Dash
0d7f1ae0fe armv8: fsl: i2c: Put I2C related code under CONFIG_SYS_I2C
I2C code is put under CONFIG_SYS_I2C.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22 12:45:27 -07:00
Sriram Dash
e45ff0ce63 armv8: fsl: ifc: Put IFC related code under CONFIG_FSL_IFC
IFC code is put under CONFIG_FSL_IFC

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22 12:45:17 -07:00
Bharat Bhushan
4b97a82442 pci: layerscape: Fixup iommu-map for LS208xA
Commit 0aaa1a9 added support for LS208xA devices but fixing
iommu-map property is missing. This patch adds support for
fixing iommu-map.

Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
[YS: revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22 12:42:29 -07:00
Santan Kumar
77dc01bdc1 board/ls2081ardb: Update QSPI flash type from n25q512a to s25fs512s
As per updated board design, different QSPI flash
is connected on boards, hence change QSPI flash type
from Micron n25q512a device to spansion s25fs512s
device in dts and config.

Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22 12:41:54 -07:00
Santan Kumar
32999fa5d6 board/ls2080ardb: Remove CONFIG_DISPLAY_BOARDINFO_LATE
CONFIG_DISPLAY_BOARDINFO_LATE config is used to delay
the prints of boardinfo late in cycle during uboot boot.
This feature is not required in case of QSPI_BOOT.

Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22 12:41:46 -07:00
Ashish Kumar
bdbcb52256 armv8: fsl-layerscape: Put SATA code under SATA configs
It is not necessary for every SoC to have 2 SATA controller.
So put SATA1, SATA2 code under respective defines.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22 12:41:24 -07:00
York Sun
88486d0423 armv7: ls1021a: Fix marco CONFIG_LS102XA
Commit a8ecb39e accidentally reverted config macro CONFIG_ARCH_LS1021A
to CONFIG_LS102XA.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-09-22 12:40:48 -07:00
Jean-Jacques Hiblot
8ff7763d62 regulator: pbias: Add PBIAS regulator for proper voltage switching on MMC1
In the TI SOCs a PBIAS cell exists to provide a bias voltage to the MMC1
IO cells. Without this bias voltage these I/O cells can not function
properly. The PBIAS cell is controlled by software.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 23:23:54 +09:00
Jean-Jacques Hiblot
b5a144a501 dm: core: Add functions to get strings and the string count from a stringlist
dev_read_string_count() is used to get the number of strings in a
stringlist.
dev_read_string_index() is used to get a string in the stringlist based on
its position in the list.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2017-09-22 23:23:54 +09:00
Marek Vasut
b24633df31 mmc: uniphier-sd: Add support for R8A7795 and R7A7796
Add OF match entries and quirks for Renesas RCar Gen3 controllers
into the driver. The IP this driver handles is in fact Matsushita
one and in used both in Socionext and Renesas chips.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
2017-09-22 23:23:45 +09:00
Marek Vasut
4b26d5e3ae mmc: uniphier-sd: Add support for quirks
Check if the OF match has any associated data and if so, use those
data as the controller quirks, otherwise fallback to the old method
of reading the controller version register to figure out the quirks.
This allows us to supply controller quirks on controllers which ie.
do not have version register.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
2017-09-22 23:23:35 +09:00
Marek Vasut
484d9db4f9 mmc: uniphier-sd: Add support for 64bit FIFO
The Renesas RCar Gen3 contains the same controller, originally
Matsushita. This patch adds support for handling of the 64bit
FIFO on this controller.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
2017-09-22 23:23:31 +09:00
Marek Vasut
1c99f68e93 mmc: uniphier-sd: Add support for 64bit controller
The Renesas RCar Gen3 contains the same controller, originally
Matsushita, yet the register addresses are shifted by 1 to the
left. The whole controller is also 64bit, including the data
FIFOs and RSP registers. This patch adds support for handling
the register IO by shifting the register offset by 1 in the IO
accessor functions.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
2017-09-22 23:23:27 +09:00
Marek Vasut
3d7b1d1bc4 mmc: uniphier-sd: Factor out register IO
This patch prepares the driver to support controller(s) with registers
at locations shifted by constant. Pull out the readl()/writel() from
the driver into separate functions, where the adjustment of the register
offset can be easily contained.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
2017-09-22 23:23:23 +09:00
Tom Rini
91ebf30093 Travis-CI: Checkout only v1.4.3 of dtc
Our minimum DTC version is 1.4.3, so check that out.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-22 07:40:06 -04:00
Jörg Krause
64b8d7a677 net/tftp: fix build if CMD_BOOTEFI is not set
Fixes:
net/tftp.c:811: undefined reference to `efi_set_bootdev'

Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-22 07:40:05 -04:00
Tom Rini
2fa73e784d Makefile: Update minimum dtc version to 1.4.3
With support for overlays and calling the -@ flag to dtc we need to have
at least 1.4.3 available now.

Cc: Simon Glass <sjg@chromium.org>
Reported-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-22 07:40:05 -04:00
York Sun
933f67aa56 spl: Fix compiling warning on gunzip argument
common/spl/spl_fit.c:201:12: warning: passing argument 4 of ‘gunzip’
from incompatible pointer type [-Wincompatible-pointer-types]
       src, &length))

Signed-off-by: York Sun <york.sun@nxp.com>
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
CC: Jean-Jacques Hiblot <jjhiblot@ti.com>
2017-09-22 07:40:04 -04:00
Felix Brack
7cc238f2ee arm: am33xx: Make pin multiplexing functions optional
This patch provides default implementations of the two functions
set_uart_mux_conf and set_mux_conf_regs. Hence boards not using
them do not need to provide their distinct empty definitions.

Signed-off-by: Felix Brack <fb@ltec.ch>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-22 07:40:04 -04:00
Patrice Chotard
246771b184 board: Add stm32h7 SoC, discovery and evaluation boards support
This patch adds support for stm32h7 soc family, stm32h743
discovery and evaluation boards.

For more information about STM32H7 series, please visit:
http://www.st.com/en/microcontrollers/stm32h7-series.html

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:40:03 -04:00
Patrice Chotard
a1e384b4d9 ARM: DTS: stm32: adapt stm32h7 dts files for U-boot
This patch adapts stm32h743 disco and eval dts files to match
with U-boot requirements or add features wich are not yet
upstreamed on kernel side :

_ Add RCC clock driver node and update all clocks phandle
  accordingly.

  By default, on kernel side, all clocks was temporarly
  configured as a phandle to timer_clk waiting for a RCC
  clock driver to be available.
  On U-boot side, we now have a dedicated RCC clock driver, we
  can configured all clocks as phandle to this driver.

  All this binding update will be available soon in a kernel tag,
  as all the bindings have been acked by Rob Herring [1].

  [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html

_ Align STM32H7 serial compatible string with the one which will be
  available in next kernel tag. The bindings has been acked by
  Rob Herring [2].
  This compatible string will be usefull to add stm32h7 specific
  feature for this serial driver.

  [2] https://lkml.org/lkml/2017/7/17/739

_ Add gpio compatible and aliases for stm32h743

_ Add FMC sdram node with associated new bindings value to
  manage second bank (ie bank 1).

_ Add missing HSI and CSI oscillators nodes needed
  by STM32H7 RCC clock driver.

  Clock sources could be:
	_ HSE (High Speed External)
	_ HSI (High Speed Internal)
	_ CSI (Low Power Internal)

  These clocks can be used as clocksource in some configuration.
  By default, HSE is selected as clock source.

_ Set HSE to 25Mhz for stm32h743i-disco and eval board

  By default, the external oscillator frequency is defined at
  25 Mhz in SoC stm32h743.dtsi file.
  It has been set at 125 Mhz in kernel DT temporarly waiting for
  RCC clock driver becomes available.

  As in U-boot we got a RCC clock driver, the real value of HSE
  clock can be used.

_ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl,
  pwrcfg and gpio nodes.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:40:03 -04:00
Patrice Chotard
5fbb2b25ae ARM: DTS: stm32: add stm32h743i-eval files
This file is imported from linux kernel v4.13

Add device tree support for STM32H743 evaluation board.
This board offers :
  _ STM32H743XIH6 microcontroller with 2 Mbytes of
    Flash memory and 1 Mbyte of RAM in TFBGA240+25 package
  _ 5.7” 640x480 TFT color LCD with touch screen
  _ Ethernet compliant with IEEE-802.3-2002
  _ USB OTG HS and FS
  _ I2 C compatible serial interface
  _ RTC with rechargeable backup battery
  _ SAI Audio DAC
  _ ST-MEMS digital microphones
  _ 8-Gbyte (or more) SDIO3.0 interface microSD™ card
  _ 8Mx32bit SDRAM, 1Mx16bit SRAM and 8Mx16bit NOR Flash
  _ 1-Gbit Twin Quad-SPI NOR Flash
  _ Potentiometer
  _ 4 colored user LEDs
  _ Reset, wakeup, tamper or key buttons
  _ Joystick with 4-direction control and selector
  _ Board connectors :
     Power jack
     3 USB with Micro-AB
     RS-232 communications
     Ethernet RJ45
     FD-CAN compliant connection
     Stereo headset jack including analog microphone input
     2 audio jacks for external speakers
     microSD™ card
     JTAG/SWD and ETM trace
   _ Expansion connectors:
     Extension connectors and memory connectors for daughterboard
     or wire-wrap board
   _ Flexible power-supply options: ST-LINK USB VBUS or external
     sources
   _ On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration
     capability: mass storage, virtual COM port and debug port

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:40:03 -04:00
Patrice Chotard
d983a0f008 ARM: DTS: stm32: add stm32h743i-disco files
All these files are imported from linux kernel v4.13

Add device tree support for STM32H743 SoC and discovery
board. This board offers :
  _ STM32H743XIH6 microcontroller with 2 Mbytes of
    Flash memory and 1 Mbyte of RAM in TFBGA240+25 package
  _ 5.7” 640x480 TFT color LCD with touch screen
  _ Ethernet compliant with IEEE-802.3-2002
  _ USB OTG HS
  _ I2 C compatible serial interface
  _ ST-MEMS digital microphones
  _ 8-Gbyte (or more) SDIO3.0 interface microSD™ card
  _ 8Mx32bit SDRAM
  _ 1-Gbit Twin Quad-SPI NOR Flash
  _ Reset, wakeup, or key buttons
  _ Joystick with 4-direction control and selector
  _ Board connectors :
	1 USB with Micro-AB
	Ethernet RJ45
	Stereo headset jack including analog microphone input
	microSD™ card
	RCA connector
	JTAG/SWD and ETM trace
   _ Expansion connectors:
	Arduino Uno compatible Connectors
	2 x PIO connectors (PMOD and PMOD+)
   _ On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration
     capability: mass storage, virtual COM port and debug port

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:40:02 -04:00
Christophe Kerello
4e280b91a1 dm: misc: add stm32 rcc driver
This patch adds the support of reset and clock control
block (rcc) found on STM32 SoCs.
This driver is similar to a MFD linux driver.

This driver supports currently STM32H7 only.
STM32F4 and STM32F7 will be migrated to this rcc MFD driver
in the future to uniformize all STM32 SoCs already upstreamed.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:40:02 -04:00
Patrice Chotard
23a0641685 dm: reset: add stm32 reset driver
This driver is adapted from linux drivers/reset/reset-stm32.c
It's compatible with STM32 F4/F7/H7 SoCs.

This driver doesn't implement .of_match as it's binded
by MFD RCC driver.

To add support for each SoC family, a SoC's specific
include/dt-binfings/mfd/stm32xx-rcc.h file must be added.

This patch only includes stm32h7-rcc.h dedicated for STM32H7 SoCs.
Other SoCs support will be added in the future.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:40:01 -04:00
Patrice Chotard
4c3aebd56a dm: clk: add clk driver support for stm32h7 SoCs
This driver implements basic clock setup, only clock gating
is implemented.

This driver doesn't implement .of_match as it's binded
by MFD RCC driver.

Files include/dt-bindings/clock/stm32h7-clks.h and
doc/device-tree-bindings/clock/st,stm32h7-rcc.txt
will be available soon in a kernel tag, as all the
bindings have been acked by Rob Herring [1].

[1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:40:01 -04:00
Patrice Chotard
776b2ddbfa serial: stm32x7: add STM32H7 support
STM32F7 and STM32H7 shares the same UART block, add
STM32H7 compatible string.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:40:01 -04:00
Patrice Chotard
092e72cbb3 pinctrl: stm32: add stm32h743-pinctrl compatible
STM32H7 SoCs uses the same pinctrl block as found into
STM32F7 SoCs

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-09-22 07:40:00 -04:00
Kever Yang
a8c5112a26 spl: stash bootstage info before jump to next stage
Since we may jump to next stage like ATF/OP-TEE instead of U-Boot,
we need to stash the bootstage info before it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:40:00 -04:00
Patrice Chotard
4e6eeeac12 board: STiH410-B2260: add fastboot support
Add usb_gadget_handle_interrupts(), board_usb_init(),
board_usb_cleanup() and g_dnl_board_usb_cable_connected()
callbacks needed for FASTBOOT support

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:40:00 -04:00
Patrice Chotard
bfd7ef110a ARM: dts: STiH410: update ehci and ohci compatible
Update ehci and ohci node's compatible string in order to
use ehci-generic and ohci-generic drivers.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:39:59 -04:00
Patrice Chotard
01d142850e ARM: dts: STiH410: set DWC3 dual role mode to peripheral
On STi 96boards, configure by default the micro USB connector
(managed by DWC3 hardware block) in peripheral mode.
This will allow to use fastboot feature.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:39:59 -04:00
Patrice Chotard
40d1a31e63 usb: dwc3: Add dwc3 glue driver support for STi
This patch adds the ST glue logic to manage the DWC3 HC
on STiH407 SoC family. It configures the internal glue
logic and syscfg registers.

Part of this code been extracted from kernel.org driver
(drivers/usb/dwc3/dwc3-st.c)

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:39:59 -04:00
Patrice Chotard
8b35f4346f STiH410-B2260: enable USB, fastboot, reset, PHY related flags
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:39:58 -04:00
Patrice Chotard
e9d1257203 STiH410-B2260: enable USB Host Networking
Enable USB Host Networking support by enabling Ethernet/USB
adaptors support and by enabling some BOOTP flags

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:39:58 -04:00
Patrice Chotard
b7ca56dcda usb: phy: Add STi USB2 PHY
This is the generic phy driver for the picoPHY ports
used by USB2/1.1 controllers. It is found on STiH407 SoC
family from STMicroelectronics.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:39:57 -04:00
Patrice Chotard
dca3166f55 mmc: sti_sdhci: Use reset framework
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:39:57 -04:00
Patrice Chotard
9ea2fc88dd ARM: dts: stih410-family: Add missing reset_names for mmc1 node
reset-names property is needed to use the reset
API for STi sdhci driver.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:39:57 -04:00
Patrice Chotard
819c626bb0 mmc: sti_sdhci: Rework sti_mmc_core_config()
Use struct udevice* as input parameter. Previous
parameters are retrieved through plat and priv data.

This to prepare to use the reset framework.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:39:56 -04:00
Tuomas Tynkkynen
44913a185f pci: Remove unnecessary 'default n' from Kconfig
'default n' is the default anyway so it doesn't need to be specified
explicitly, and the rest of the file doesn't specify it either anywhere.
Drop it.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-22 07:39:56 -04:00
Tuomas Tynkkynen
93b1431f1a pci: layerscape: Remove unused field 'hose' from struct ls_pcie
This field is no longer used since the DM conversion. Drop it.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-22 07:39:55 -04:00
Tuomas Tynkkynen
be0105bc1e pci: tegra: Remove unused field 'hose' from struct tegra_pcie
This field is no longer used since the DM conversion. Drop it.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-22 07:39:55 -04:00
Tuomas Tynkkynen
bee278de81 pci: xilinx: Remove unused field 'hose' from struct xilinx_pcie
This field has never been used as the driver has been DM-based since the
beginning. Drop it.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-22 07:39:55 -04:00
Tuomas Tynkkynen
adfc3e4804 pci: xilinx: Fix doc comments on config space accessors
These take the 'struct udevice *' as an argument, not the
'struct xilinx_pcie *` which is a local variable. Fix the comments to
match the code.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-22 07:39:54 -04:00
Tom Rini
2460098cff fs/fat: Reduce stack usage
We have limited stack in SPL builds.  Drop itrblock and move to
malloc/free of itr to move this off of the stack.  As part of this fix a
double-free issue in fat_size().

Signed-off-by: Tom Rini <trini@konsulko.com>
---
Rework to use malloc/free as moving this to a global overflows some SH
targets.
2017-09-22 07:37:43 -04:00
Tom Rini
2dc5b553b9 Merge branch 'next' of git://git.denx.de/u-boot-video 2017-09-21 07:51:20 -04:00
Rob Clark
7dd5d44753 efi_loader: fix efi_exit
efi_exit() already restores gd, so we shouldn't EFI_EXIT() on the
otherside of the longjmp().

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-21 09:04:25 +02:00
rick
7155cd2e6e nds32: spi: Support spi dm driver.
Support spi driver and can detect MX25U1635E flash on AE3XX board.

Verification:

sf probe 0:0 50000000 0
spi_flash_std_probe(sf_Probr.c)
	spi_flash_probe_slave(sf_Probr.c)
	SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
	NDS32 # sf test 0x100000 0x1000
	SPI flash test:
	0 erase: 34 ticks, 117 KiB/s 0.936 Mbps
	1 check: 15 ticks, 266 KiB/s 2.128 Mbps
	2 write: 21 ticks, 190 KiB/s 1.520 Mbps
	3 read: 11 ticks, 363 KiB/s 2.904 Mbps
	Test passed
	0 erase: 34 ticks, 117 KiB/s 0.936 Mbps
	1 check: 15 ticks, 266 KiB/s 2.128 Mbps
	2 write: 21 ticks, 190 KiB/s 1.520 Mbps
	3 read: 11 ticks, 363 KiB/s 2.904 Mbps

Signed-off-by: rick <rick@andestech.com>
2017-09-21 10:30:22 +08:00
rick
7b1a50b7b6 nds32: board: Support SPI driver.
Add spi dts node and enable spi dm flash config.

Signed-off-by: rick <rick@andestech.com>
2017-09-21 10:30:22 +08:00
rick
6d3cb0fdcd nds32: mtd: add spi flash id MX25U16335E.
To support MACRONIX MX25U1635E 16M-BIT flash.

Signed-off-by: rick <rick@andestech.com>
2017-09-21 10:30:22 +08:00
rick
1341494c7d nds32: ftmac100: Fix write mac addr fail problem.
After soft reset complete, write mac address immediately will fail.
Add delay to work around this problem.

Signed-off-by: rick <rick@andestech.com>
2017-09-21 10:30:22 +08:00
rick
e336b73d8a nds32: ftmac100 support cache enable.
Enable cache and ftmac100 performance can be improved.

Signed-off-by: rick <rick@andestech.com>
2017-09-21 10:30:22 +08:00
rick
ce4e2370f7 nds32: ftmac100: support cache enable.
Add cache inval and flush when rx and tx.

Signed-off-by: rick <rick@andestech.com>
2017-09-21 10:30:22 +08:00
rick
19fc21fb4a nds32: bootm: Fix warning of struct tag_serialnr declared
move #include <asm/setup.h> from bootm.c to bootm.h

Signed-off-by: rick <rick@andestech.com>
2017-09-21 10:30:22 +08:00
rick
d573b36402 nds32: board: Fix andestech adp-ae3xx.c make fail problem.
Add #include <asm/mach-types.h> to fix it.

Signed-off-by: rick <rick@andestech.com>
2017-09-21 10:30:21 +08:00
Heinrich Schuchardt
7aca68ca06 efi_loader: reenable selftest
ad503ffe9c6 efi_loader: refactor boot device and loaded_image handling
leads to an error when building with CONFIG_CMD_BOOTEFI_SELFTEST=y
This patch fixes the problem.

Fixes: ad503ffe9c6 efi_loader: refactor boot device and loaded_image handling
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-20 23:34:41 +02:00
Tom Rini
e884656c2c Merge git://www.denx.de/git/u-boot-imx 2017-09-20 12:32:34 -04:00
Fabio Estevam
031426a7af mx6sabresd: Add Serial Download Protocol support
Add Serial Download Protocol support (SDP), which allows loading
SPL and u-boot.img via imx_usb_loader tool as explained in
doc/README.sdp.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-09-20 15:34:59 +02:00
Fabio Estevam
511db3bf5a toradex: imx6: Move g_dnl_bind_fixup() into common SPL code
Instead of having every board file to add its own g_dnl_bind_fixup()
implementation, move it to the common imx6 SPL code.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
2017-09-20 15:34:59 +02:00
Ian Ray
be2808c3b0 board: ge: bx50v3: set eth0 MAC address
Define i2c mux configuration.  Add new vpd_reader which is used to read
vital product data.  Read VPD from EEPROM and set eth0 MAC address.

Signed-off-by: Ian Ray <ian.ray@ge.com>
Signed-off-by: Jose Alarcon <jose.alarcon@ge.com>
2017-09-20 15:34:59 +02:00
Dennis Gilmore
b1e8512e9d detect and setup solidrun hummingboard2
The hummingboard2 is slightly different to the cubox i and to the
hummingboard. The GPIO pin info to probe came from solidruns
for of u-boot on github.
https://github.com/SolidRun/u-boot-imx6/blob/imx6/board/solidrun/mx6_cubox-i/mx6_cubox-i.c#L569-L589
I have tested on a hummingboard-edge witha  imx6 solo and 512mb of
ram.

Signed-off-by: Dennis Gilmore <dgilmore@redhat.com>
2017-09-20 15:34:59 +02:00
Rob Clark
3a45bc7faa efi_loader: Some console improvements for vidconsole
1) use fputs() to reduce cache flushes from once-per-char to
   once-per-string
2) handle \r, \t, and \b in addition to just \n for tracking
   cursor position
3) cursor row/col are zero based, not one based

Signed-off-by: Rob Clark <robdclark@gmail.com>
[agraf: s/unsigned/unsigned int/]
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-20 11:29:35 +02:00
Rob Clark
a18c5a8382 efi_loader: Correctly figure out size for vidconsole
If stdout is vidconsole, we cannot rely on ANSI escape sequences to
query the size, as vidconsole cannot reply on stdin.  Instead special-
case this if stdout is vidconsole.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-20 11:28:39 +02:00
Rob Clark
71cc25c35c efi_loader: split out escape sequence based size query
We need to do something different for vidconsole, since it cannot
respond to the query on stdin.  Prep work for next patch.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-20 11:14:12 +02:00
Rob Clark
778e6af8a6 efi_loader: print GUIDs
Utilize printf GUID support to print GUIDs.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-20 11:10:42 +02:00
Rob Clark
4657a3f1ac efi_loader: set loaded image code/data type properly
These should be set according to the image type.  Shell.efi and SCT.efi
use these fields to determine what sort of image they are loading.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-20 11:10:24 +02:00
Rob Clark
61b7e22479 efi_loader: file_path should be variable length
Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-20 11:08:58 +02:00
Rob Clark
9975fe96b6 efi_loader: add bootmgr
Similar to a "real" UEFI implementation, the bootmgr looks at the
BootOrder and BootXXXX variables to try to find an EFI payload to load
and boot.  This is added as a sub-command of bootefi.

The idea is that the distro bootcmd would first try loading a payload
via the bootmgr, and then if that fails (ie. first boot or corrupted
EFI variables) it would fallback to loading bootaa64.efi.  (Which
would then load fallback.efi which would look for \EFI\*\boot.csv and
populate BootOrder and BootXXXX based on what it found.)

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-20 11:08:01 +02:00
Rob Clark
ad644e7c18 efi_loader: efi variable support
Add EFI variable support, mapping to u-boot environment variables.
Variables are pretty important for setting up boot order, among other
things.  If the board supports saveenv, then it will be called in
ExitBootServices() to persist variables set by the efi payload.  (For
example, fallback.efi configuring BootOrder and BootXXXX load-option
variables.)

Variables are *not* currently exposed at runtime, post ExitBootServices.
On boards without a dedicated device for storage, which the loaded OS
is not trying to also use, this is rather tricky.  One idea, at least
for boards that can persist RAM across reboot, is to keep a "journal"
of modified variables in RAM, and then turn halt into a reboot into
u-boot, plus store variables, plus halt.  Whatever the solution, it
likely involves some per-board support.

Mapping between EFI variables and u-boot variables:

  efi_$guid_$varname = {attributes}(type)value

For example:

  efi_8be4df61-93ca-11d2-aa0d-00e098032b8c_OsIndicationsSupported=
     "{ro,boot,run}(blob)0000000000000000"
  efi_8be4df61-93ca-11d2-aa0d-00e098032b8c_BootOrder=
     "(blob)00010000"

The attributes are a comma separated list of these possible
attributes:

  + ro   - read-only
  + boot - boot-services access
  + run  - runtime access

NOTE: with current implementation, no variables are available after
ExitBootServices, and all are persisted (if possible).

If not specified, the attributes default to "{boot}".

The required type is one of:

  + utf8 - raw utf8 string
  + blob - arbitrary length hex string

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-20 11:00:57 +02:00
Rob Clark
946160f334 efi_loader: make pool allocations cacheline aligned
This avoids printf() spam about file reads (such as loading an image)
into unaligned buffers (and the associated memcpy()).  And generally
seems like a good idea.

Signed-off-by: Rob Clark <robdclark@gmail.com>
[agraf: use __aligned]
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-20 10:48:09 +02:00
Rob Clark
838ee4b479 efi_loader: support load_image() from a file-path
Previously we only supported the case when the EFI application loaded
the image into memory for us.  But fallback.efi does not do this.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-20 10:45:28 +02:00
Rob Clark
2a92080d8c efi_loader: add file/filesys support
fallback.efi (and probably other things) use UEFI's simple-file-system
protocol and file support to search for OS's to boot.

Signed-off-by: Rob Clark <robdclark@gmail.com>
[agraf: whitespace fixes, unsigned fixes]
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-20 10:43:54 +02:00
Rob Clark
95c5553ea2 efi_loader: refactor boot device and loaded_image handling
Get rid of the hacky fake boot-device and duplicate device-path
constructing (which needs to match what efi_disk and efi_net do).
Instead convert over to use efi_device_path helpers to construct
device-paths, and use that to look up the actual boot device.

Also, extract out a helper to plug things in properly to the
loaded_image.  In a following patch we'll want to re-use this in
efi_load_image() to handle the case of loading an image from a
file_path.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-20 10:36:56 +02:00
Rob Clark
e15fc33548 efi_loader: use proper device-paths for net
Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-20 10:35:29 +02:00
Rob Clark
884bcf6f65 efi_loader: use proper device-paths for partitions
Also, create disk objects for the disk itself, in addition to the
partitions.  (UEFI terminology is a bit confusing, a "disk" object is
really a partition.)  This helps grub properly identify the boot device
since it is trying to match up partition "disk" object with it's parent
device.

Now instead of seeing devices like:

  /File(sdhci@07864000.blk)/EndEntire
  /File(usb_mass_storage.lun0)/EndEntire

You see:

  /ACPI(133741d0,0)/UnknownMessaging(1d)/EndEntire
  /ACPI(133741d0,0)/UnknownMessaging(1d)/HD(0,800,64000,dd904a8c00000000,1,1)/EndEntire
  /ACPI(133741d0,0)/UnknownMessaging(1d)/HD(1,64800,200000,dd904a8c00000000,1,1)/EndEntire
  /ACPI(133741d0,0)/UnknownMessaging(1d)/HD(2,264800,19a000,dd904a8c00000000,1,1)/EndEntire
  /ACPI(133741d0,0)/USB(0,0)/USB(0,0)/USB(0,0)/EndEntire
  /ACPI(133741d0,0)/USB(0,0)/USB(0,0)/USB(0,0)/HD(0,800,60000,38ca680200000000,1,1)/EndEntire
  /ACPI(133741d0,0)/USB(0,0)/USB(0,0)/USB(0,0)/HD(1,61000,155000,38ca680200000000,1,1)/EndEntire
  /ACPI(133741d0,0)/USB(0,0)/USB(0,0)/USB(0,0)/HD(2,20fa800,1bbf8800,38ca680200000000,1,1)/EndEntire
  /ACPI(133741d0,0)/USB(0,0)/USB(0,0)/USB(0,0)/HD(3,1b6800,1f44000,38ca680200000000,1,1)/EndEntire

This is on a board with single USB disk and single sd-card.  The
UnknownMessaging(1d) node in the device-path is the MMC device,
but grub_efi_print_device_path() hasn't been updated yet for some
of the newer device-path sub-types.

This patch is inspired by a patch originally from Peter Jones, but
re-worked to use efi_device_path, so it doesn't much resemble the
original.

Signed-off-by: Rob Clark <robdclark@gmail.com>
[agraf: s/unsigned/unsigned int/]
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-20 10:34:42 +02:00
Rob Clark
adae4313cd efi_loader: flesh out device-path to text
It needs to handle more device-path node types, and also multiple levels
of path hierarchy.  To simplify this, initially construct utf8 string to
a temporary buffer, and then allocate the real utf16 buffer that is
returned.  This should be mostly for debugging or at least not critical-
path so an extra copy won't hurt, and is saner than the alternative.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-20 10:32:54 +02:00
Rob Clark
9309a1b76c efi_loader: drop redundant efi_device_path_protocol
This is really the same thing as the efi_device_path struct.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-20 10:32:00 +02:00
Rob Clark
b66c60dde9 efi_loader: add device-path utils
Helpers to construct device-paths from devices, partitions, files, and
for parsing and manipulating device-paths.

For non-legacy devices, this will use u-boot's device-model to construct
device-paths which include bus hierarchy to construct device-paths.  For
legacy devices we still fake it, but slightly more convincingly.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-20 10:31:55 +02:00
Peter Jones
c80214ce1f efi: add some more device path structures
Signed-off-by: Peter Jones <pjones@redhat.com>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-20 10:22:00 +02:00
Rob Clark
a8606ef075 efi: add some missing __packed
All of the device-path related structures should be packed.  UEFI
defines the device-path as a byte-aligned data structure.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-20 10:21:38 +02:00
Peter Jones
ff98cb9051 part: extract MBR signature from partitions
EFI client programs need the signature information from the partition
table to determine the disk a partition is on, so we need to fill that
in here.

Signed-off-by: Peter Jones <pjones@redhat.com>
[separated from efi_loader part, and fixed build-errors for non-
 CONFIG_EFI_PARTITION case]
Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-20 10:20:19 +02:00
Rob Clark
0d6ab32e37 part: move efi_guid_t
Prep work for next patch.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-20 10:20:00 +02:00
Heinrich Schuchardt
0923876d29 efi_selftest: check notification of ExitBootServices
Check that the notification function of an
EVT_SIGNAL_EXIT_BOOT_SERVICES event is called
exactly once.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-18 23:53:57 +02:00
Heinrich Schuchardt
152a263c86 efi_loader: notify when ExitBootServices is invoked
All events of type EVT_SIGNAL_EXIT_BOOT_SERVICES have to be
notified when ExitBootServices is invoked.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-18 23:53:57 +02:00
Heinrich Schuchardt
1835f6ea71 efi_selftest: test task priority levels
Run a 10 ms periodic timer and check that it is called 10 times
while waiting for 100 ms single shot timer.

Raise the TPL level to the level of the 10 ms timer and observe
that the notification function is not called again.

Lower the TPL level and check that the queued notification
function is called.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-18 23:53:57 +02:00
Heinrich Schuchardt
32f4b2f8c4 efi_loader: implement task priority level (TPL)
Define variable holding tpl.
Implement RaiseTPL and RestoreTPL.
Implement TPL check in efi_signal_event.
Implement TPL check in efi_wait_for_event.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-18 23:53:57 +02:00
Heinrich Schuchardt
bd126692da efi_selftest: provide unit test for event services
This unit test uses timer events to check the implementation
of the following boottime services:
CreateEvent, CloseEvent, WaitForEvent, CheckEvent, SetTimer

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-18 23:53:57 +02:00
Heinrich Schuchardt
2eca84523f efi_loader: efi_set_timer: reset signaled state
We should be able to call efi_set_timer repeatedly.
So let us reset the signaled state here.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-18 23:53:57 +02:00
Heinrich Schuchardt
ca62a4f53e efi_loader: implement queueing of the notification function
For the correct implementation of the task priority level (TPL)
calling the notification function must be queued.

Add a status field 'queued' to events.

In function efi_signal_event set status queued if a notification
function exists and reset it after we have called the function.
A later patch will add a check of the TPL here.

In efi_create_event and efi_close_event unset the queued status.

In function efi_wait_for_event and efi_check_event
queue the notification function.

In efi_timer_check call the efi_notify_event
if the status queued is set.
For all timer events set status signaled.

In efi_console_timer_notify set the signaled state of the
WaitForKey event.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-18 23:53:57 +02:00
Heinrich Schuchardt
38b1b79021 test/py: add a test calling the EFI selftest
A Python test script is provided that runs the EFI selftest
if CONFIG_CMD_EFI_SELFTEST=y.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-18 23:53:57 +02:00
Heinrich Schuchardt
623b3a5797 efi_selftest: provide an EFI selftest application
A testing framework for the EFI API is provided.
It can be executed with the 'bootefi selftest' command.

It is coded in a way that at a later stage we may turn it
into a standalone EFI application. The current build system
does not allow this yet.

All tests use a driver model and are run in three phases:
setup, execute, teardown.

A test may be setup and executed at boottime,
it may be setup at boottime and executed at runtime,
or it may be setup and executed at runtime.

After executing all tests the system is reset.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-18 23:53:57 +02:00
Heinrich Schuchardt
ea630ce9ea efi_loader: allow return value in EFI_CALL
Macro EFI_CALL was introduced to call an UEFI function.
Unfortunately it does not support return values.
Most UEFI functions have a return value.

So let's rename EFI_CALL to EFI_CALL_VOID and introduce a
new EFI_CALL macro that supports return values.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-18 23:53:56 +02:00
Heinrich Schuchardt
29f1a3670e efi_loader: fix typo in include/efi.h
Fix typo in teh EFI_BOOT_SERVICES_CODE description.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-18 23:53:56 +02:00
Heinrich Schuchardt
591cf2e161 efi_loader: avoid obscure constants in efi_runtime.c
We should use the predefined constants EFI_PAGE_SHIFT
and EFI_PAGE_MASK where applicable.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-18 23:53:56 +02:00
Andre Przywara
eefa0a647d EFI: find EFI system partition by legacy MBR partition type
The UEFI spec allows an EFI system partition (ESP, with the bootloader or
kernel EFI apps on it) to reside on a disk using a "legacy" MBR
partitioning scheme.
But in contrast to actual legacy disks the ESP is not marked as
"bootable" using bit 7 in byte 0 of the legacy partition entry, but is
instead using partition *type* 0xef (in contrast to 0x0b or 0x0c for a
normal FAT partition). The EFI spec isn't 100% clear on this, but it even
seems to discourage the use of the bootable flag for ESPs.
Also it seems that some EFI implementations (EDK2?) even seem to ignore
partitions marked as bootable (probably since they believe they contain
legacy boot code).
The Debian installer [1] (*not* mini.iso), for instance, contains such an
MBR, where none of the two partitions are marked bootable, but the ESP
has clearly type 0xef.
Now U-Boot cannot find the ESP on such a disk (USB flash drive) and
fails to load the EFI grub and thus the installer.

Since it all boils down to the distro bootcmds eventually calling
"part list -bootable" to find potential boot partitions, it seems logical
to just add this "partition type is 0xef" condition to the is_bootable()
implementation.

This allows the bog standard arm64 Debian-testing installer to boot from
an USB pen drive on Allwinner A64 boards (Pine64, BananaPi-M64).
(Ubuntu and other distribution installers don't have a legacy MBR, so
U-Boot falls back to El Torito there).

[1] https://cdimage.debian.org/cdimage/daily-builds/daily/arch-latest/arm64/iso-cd/
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-18 23:53:56 +02:00
Heinrich Schuchardt
c96967e6d7 efi_loader: usage of always in Makefile
Variable always should only be appended but not overwritten by
lib/efi_loader/Makefile.

Remove variable efiprogs which is not otherwise used.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-18 23:53:56 +02:00
Heinrich Schuchardt
b0763108ea scripts/Makefile.lib: generalize building built in EFI app
Replace all occurences of helloworld by generalized forms.
This allows us to build additional EFI applications that are
included into the U-Boot binary without loading
scripts/Makefile.lib with specific filenames.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-18 23:53:56 +02:00
Heinrich Schuchardt
5e44489bc1 efi_loader: rename __efi_hello_world_*
In scripts/Makefile.lib we build section including helloworld.efi.
This allows to load the EFI binary with command 'bootefi hello'.

scripts/Makefile.lib contains explicit references to strings
containing helloworld and hello_world. This makes it impossible
to generalize the coding to accomodate additional built in
EFI binaries.

Let us rename the variables __efi_hello_world_* to
__efi_helloworld_*.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-18 23:53:56 +02:00
Heinrich Schuchardt
d6507e6fd9 scripts/Makefile.lib: remove overridden target $(obj)/helloworld.so:
The target
$(obj)/helloworld.so:
exists twice in Makefile.lib.

If you add an echo command to each of the two recipes you get
warnings like:

scripts/Makefile.lib:383: warning:
overriding recipe for target 'drivers/power/battery/helloworld.so'
scripts/Makefile.lib:379: warning:
ignoring old recipe for target 'drivers/power/battery/helloworld.so'

This patch removes the obsolete target.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-18 23:53:56 +02:00
Alexander Graf
a148920e12 efi_loader: Fix efi_exit gd clobbering
Commit f494950b (efi_loader: call __efi_exit_check in efi_exit) added a call
to __efi_exit_check inside efi_exit to account for the fact that we're exiting
the efi_exit function via a longjmp call.

However, __efi_exit_check also swizzles gd to the application gd while the
longjmp will put us back into EFI context, so we need the efi (u-boot) gd.

This patch fixes that up by explicitly setting gd back to efi_gd before
doing the longjmp. It also adds a few comments on why it does that.

Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-18 23:53:56 +02:00
Heinrich Schuchardt
ae0bd3a983 efi_loader: write protocol GUID in OpenProtocol
To understand what is happening in OpenProtocol or LocateProtocol
it is necessary to know the protocol interface GUID.
Let's write a debug message.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-18 23:53:56 +02:00
Heinrich Schuchardt
da94073b42 efi_loader: call __efi_exit_check in efi_exit
The calls to __efi_entry_check and __efi_exit_check have to match.
If DEBUG is defined, panic() will be called otherwise.

If debugging is activated some Travis CI builds fail due to an
assertion in EFI_CALL without the patch.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-18 23:53:56 +02:00
Heinrich Schuchardt
a80a232e96 efi_disk: efi_disk_rw_blocks is not an API function
There is no need to use attribute EFIAPI for
efi_disk_rw_blocks. It is not an API function.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-18 23:53:56 +02:00
Heinrich Schuchardt
51c533fdce efi_loader: bootefi hello should use loadaddr
Command 'bootefi hello' currently uses CONFIG_SYS_LOAD_ADDR
as loading address.

qemu machines have by default 128 MiB RAM.
CONFIG_SYS_LOAD_ADDR for x86 is 0x20000000 (512 MiB).
This causes 'bootefi hello' to fail.

We should use the environment variable loadaddr if available.
It defaults to 0x1000000 (16 MiB) on qemu_x86.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-09-18 23:53:56 +02:00
Tom Rini
975f97b431 Merge git://git.denx.de/u-boot-rockchip 2017-09-18 15:44:57 -04:00
Klaus Goger
60d7c50945 rockchip: puma_rk3399: increase serialno_str size
Increase serialno_str to 17 bytes so it can hold the 16 bytes long serial
nummer and the terminating null byte added by snprintf.

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2017-09-18 20:40:38 +02:00
Kever Yang
6e5bd8d6f3 rockchip: ram: rk3399: update reg map for of-platdata
After Simon's patch, the dtoc can work with 64bit address,
so we need to fix reg number for it.
Depend on Simon's patch set:
https://patchwork.ozlabs.org/cover/807266/

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:38 +02:00
Kever Yang
5184daddaa rockchip: sdhci: update reg map for of-platdata
After Simon's patch, the dtoc can work with 64bit address,
so we need to fix reg number for it.
Depend on Simon's patch set:
https://patchwork.ozlabs.org/cover/807266/

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:38 +02:00
Philipp Tomsich
75ff057851 rockchip: dts: rk3368: reduce the number of nodes seen in TPL
The RK3368 TPL stage always returns to the BootROM, so it has no need
for the eMMC, SD and SPI nodes.  This marks those nodes (that should
be included in SPL, but not TPL) as 'u-boot,dm-spl'.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-18 20:40:38 +02:00
Philipp Tomsich
1d70f0ac88 rockchip: rk3368: adjust DMC driver for 32/64bit-aware OF_PLATDATA
With the new 32/64bit-aware dtoc, the type of reg is fdt64_t and the
OF_PLATDATA structure layout changes.  This adjusts the DMC driver for
the RK3368 to track these changes.

For the time being (i.e. until regmap_init_mem_platdata works for the
64bit case), we won't use regmap_init_mem_platdata here and simply
access of_plat.reg[] directly.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-18 20:40:38 +02:00
Philipp Tomsich
8158a848fa rockchip: timer: update for 32/64bit-aware OF_PLATDATA
With dtoc emitting fdt64_t for addresses (and region sizes), the array
indices for accessing the reg[] array needs to be adjusted.  This
adjusts the Rockchip DM timer driver to correctly handle OF_PLATDATA
given this new structure layout.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-18 20:40:37 +02:00
Philipp Tomsich
7b87e3bfaf rockchip: defconfig: puma-rk3399: enable OF_LIVE (live tree)
With the critical drivers ready for switching to a live tree, we can
now enable it in the defconfig for the RK3399-Q7.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-18 20:40:37 +02:00
Philipp Tomsich
f6230a0057 rockchip: efuse: change to use dev_read_addr_ptr
With the dev_read_addr_ptr function available, we can change the
efuse driver to use it (and eliminate the explicit type-cast).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-18 20:40:37 +02:00
Philipp Tomsich
75c7859803 rockchip: clk: rk3399: Convert to livetree
Update the clock driver for the RK3399  to support a live device tree.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-18 20:40:37 +02:00
Philipp Tomsich
46c89c8efa rockchip: dts: rk3399-puma: replace 'rockchip, vbus-gpio' with fixed regulator
On the RK3399-Q7, we need to turn on the on-module USB hub before using the
USB host interfaces (only the OTG interface is directly connected to the edge
connector).  This drops the deprecated 'rockchip,vbus-gpio' property and uses
a fixed regulator to turn on the USB hub.

References: 26a8b80 "usb: host: xhci-rockchip: use fixed regulator to control vbus"
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-18 20:40:37 +02:00
Philipp Tomsich
2f01a2b214 rockchip: clk: rk3399: add clk_enable function and support USB HOST0/1
The generic ehci-driver (ehci-generic.c) will try to enable the clocks
listed in the DTSI. If this fails (e.g. due to clk_enable not being
implemented in a driver and -ENOSYS being returned by the clk-uclass),
the driver will bail our and print an error message.

This implements a minimal clk_enable for the RK3399 and supports the
clocks mandatory for the EHCI controllers; as these are enabled by
default we simply return success.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-18 20:40:37 +02:00
Andy Yan
8ac884974a rockchip: rk3368: add the missing target and pinctrl config for sheep board
Add the missing target and pinctrl config for rk3368 sheep board

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:36 +02:00
Andy Yan
ffaefb885e rockchip: rk3368: add ENV_MEM_LAYOUT to extra env settings
Add the ENV_MEM_LAYOUT_SETTINGS to CONFIG_EXTRA_ENV_SETTINGS

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:36 +02:00
Jagan Teki
d55af074e5 rk3288: Add Vyasa initial board support
This patch adds support for Vyasa RK3288 initial board
from Amarula Solutions.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:36 +02:00
Philipp Tomsich
ba1657338b rockchip: rk3399: spl: remove hard-coded addresses for GRF and SGRF
On the RK3399, we will have either OF_PLATDATA or full OF_CONTROL
enabled: this allows the use of syscon to retrieve the addresses of
GRF and SGRF (except for the early debug UART setup, which runs so
early that the device-model is not initialised).

This removes the hard-coded addresses and goes through syscon to
retrieve the base-addresses of GRF and SGRF. After that, we use
the structure definitions to locate the respective registers.

In addition to this, the inclusion of header files is also cleaned up:
- all headers are included at the beginning (there was a spurious
  inclusion of the grf header from within a function)
- all #include statements for unused headers are removed
- the remaining #include statements are sorted (while keeping common.h
  included in front)

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-18 20:40:36 +02:00
Philipp Tomsich
c254b29fef rockchip: lion-rk3368: defconfig: resync w/ OF_LIVE and BOOTSTAGE enabled
This adds OF_LIVE and BOOTSTAGE support for the RK3368-uQ7 and
regenerates the defconfig (picking up a few changes/reorderings) from
upstream Kconfig changes.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:36 +02:00
Philipp Tomsich
f041176c46 rockchip: dts: rk3368-lion: add /chosen/tick-timer
To support bootstage recording, we want to mark our DM timer as the
tick-timer; this triggers the support for 'trying harder' to read the
timer in the Rockchip DM timer driver, even if the device model isn't
ready yet.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:36 +02:00
Philipp Tomsich
c23ce9ab85 rockchip: gpio: remove outdated/misleading comment
Remove a comment claiming that this driver only supports the RK3288,
as we also use it on the RK3368, RK3399 and (most likely) on other
variants.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Version-changes: 2
- use the dev_read_addr_ptr function in rk_gpio.c
2017-09-18 20:40:35 +02:00
Philipp Tomsich
a1d3480bc6 rockchip: gpio: convert to livetree
Update the Rockchip GPIO-bank driver to support a live tree.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Version-changes: 2
- use the dev_read_addr_ptr function in rk_gpio.c
2017-09-18 20:40:35 +02:00
Philipp Tomsich
cc91bdf8d4 rockchip: i2c: Convert to livetree
Update the Rockchip I2C driver to support livetree.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Heiko Schocher <hs@denx.de>
2017-09-18 20:40:35 +02:00
Philipp Tomsich
a904a16bc1 rockchip: rk8xx: remove unused header includes
Remove header file includes that have been left over after the
conversion to livetree-support.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:35 +02:00
Philipp Tomsich
327b2b35c5 rockchip: sdhci: Convert to livetree
Update the Rockchip SDHCI wrapper to support a live device tree.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Version-changes: 2
- use the dev_read_addr_ptr function in	rockchip_sdhci.c
2017-09-18 20:40:35 +02:00
Philipp Tomsich
d27c273908 rockchip: spi: Convert to livetree
Update the Rockchip SPI driver to support a live device tree.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:35 +02:00
Philipp Tomsich
d2edb968c4 rockchip: pinctrl: rk3368: Convert to livetree
Update the pinctrl driver for the RK3368 to support a live device tree.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:34 +02:00
Philipp Tomsich
9a342f48a6 rockchip: clk: rk3368: Convert to livetree
Update the clock driver for the RK3368 to support a live device tree.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Version-changes: 2
- use the dev_read_addr_ptr function in	clk_rk3368.c
2017-09-18 20:40:34 +02:00
Philipp Tomsich
6675c952f2 rockchip: timer: Convert to livetree
Update the Rockchip timer driver to support a live device tree.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:34 +02:00
Philipp Tomsich
cc7ce94e02 rockchip: timer: implement timer_get_boot_us
To make the Rockchip DM timer driver useful for the timing of
bootstages, we need a few enhancements:
 - This implements timer_get_boot_us.
 - This avoids reinitialising the timer, if it has already been
   set up (e.g. by our TPL and SPL stages). Now, we have a single
   timebase ticking from TPL through the full U-Boot.
 - This adds support for reading the timer even before the
   device-model is ready: we find the timer via /chosen/tick-timer,
   then read its address and clock-frequency, and finally read the
   timeval directly).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:34 +02:00
Philipp Tomsich
be5f04e850 rockchip: mmc: convert to livetree
Update the Rockchip-specific wrapper for the Designware driver to
support a live device tree.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Version-changes: 2
- use the dev_read_addr_ptr function in rockchip_dw_mmc.c
2017-09-18 20:40:34 +02:00
Philipp Tomsich
b343837e90 net: phy: micrel: Convert to livetree
Update the Micrel KSZ90x1 driver for a live tree.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-18 20:40:34 +02:00
Philipp Tomsich
15050f1cb0 net: designware: Convert to livetree
Update the Designware Ethernet MAC driver to support a live device
tree.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-18 20:40:34 +02:00
Philipp Tomsich
c131c8bca8 dm: core: add dev_read_addr_ptr()
The dev_read_addr_ptr() mimics the behaviour of the devfdt_get_addr_ptr(),
retrieving the first address of the node's reg-property and returning
it as a pointer (or NULL on failure).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-18 20:40:33 +02:00
Philipp Tomsich
af82315164 dm: timer: handle being called before dm_root is ready
When used with bootstage recording, dm_timer_init may be called
surprisingly early: i.e. before dm_root is ready. To deal with
this case, we explicitly check for this condition and return
-EAGAIN to the caller (refer to drivers/timer/rockchip_timer.c
for a case where this is needed/used).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:33 +02:00
Philipp Tomsich
b61e8b0c9e dm: timer: Convert to livetree
This updates dm_timer_init to support a live tree and deals with
some fallout (i.e. the need to restructure the code such, that we
don't need multiple discontinuous #if CONFIG_IS_ENABLED blocks).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:33 +02:00
Philipp Tomsich
148a139d65 bootstage: adjust Makefile to allow including bootstage in SPL, but not in TPL
For timing our bootstages on the RK3368, which has a minimal TPL
(and where we consequently don't want to time the bootstages) and a
full-featured SPL (where we can bootstage recording), we need to
adjust the Makefile.

Use the $(SPL_TPL_) macro in the Makefile for bootstage.o

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:33 +02:00
Klaus Goger
c914034090 rockchip: board: puma_rk3399: update README flash instructions
Puma supports other boot sources then SD-Card. Update README to include
the required steps.

 * how to package a SPI-NOR SPL
 * how to flash eMMC with rkdeveloptool

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:33 +02:00
Klaus Goger
cc8fb2f793 rockchip: board: lion_rk3368: update README flash instructions
Add a section to the README on how to flash the on-board eMMC
with the rkdeveloptool.

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:33 +02:00
David Wu
4c94aacd62 rockchip: rk322x: Disable integrated macphy for saving power consuming
Unfortunately, the integrated macphy default is enabled, which will
increase power consuming, if we do not use this PHY. So let's disable
it at first, which will save power consuming. If we really use it, then
enable it in driver level.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:33 +02:00
Kever Yang
c964a0dcae rockchip: rk322x: enable fastboot to set boot mode tag
To support fastboot "fastboot reboot-bootloader" cmd.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:32 +02:00
Kever Yang
578ab33eab rockchip: enable rk322x sysreset driver
The sysreset driver for rk322x is ready but not enabled,
add it to Makefile to make sure it's enabled.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:32 +02:00
William Wu
809ec9454f ARM: dts: rockchip: add USB nodes for evb-rv1108
This patch adds USB OTG/EHCI/OHCI nodes for evb-rv1108 USB ports.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:32 +02:00
William Wu
cbeedafdc8 configs: rockchip: add USB configs for evb-rv1108 board
This patch adds USB configs to support the USB OTG port(consist
of DWC2 controller) and the USB Host port(consist of EHCI and OHCI
controllers) on evb-rv1108 board, and also support fastboot over
USB and USB mass storage.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:32 +02:00
Anatolij Gustschin
30df9f770b imx6: drop duplicated bss memset and board_init_r() call
bss section is cleared in crt0.S. board_init_r() is also
entered from crt0 code.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-09-18 17:15:28 +02:00
Vanessa Maegima
0bfd4f81ae pico-imx7d: Add "how to boot with NXP 4.1 Kernel"
The NXP 4.1 kernel needs to boot with secure boot.

Add information on how to enable secure boot mode.

Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com>
2017-09-18 17:15:28 +02:00
Eric Nelson
8590786acf imx: imx7d: remove CamelCase from ENET_xMHz macros
Update these macros to use all upper-case to avoid checkpatch
warnings:

	ENET_25MHz,
	ENET_50MHz,
	ENET_125MHz,

Signed-off-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-09-18 17:15:28 +02:00
Stefan Agner
e203dcf23e imx_common: detect USB serial downloader reliably
The current mechanism using SCR/GPR registers work well when
the serial downloader boot mode has been selected explicitly
(either via boot mode pins or using bmode command). However,
in case the system entered boot ROM due to unbootable primary
boot devices (e.g. empty eMMC), the SPL fails to detect that
it has been downloaded through serial loader and tries to
continue booting from eMMC:
  Trying to boot from MMC1
  mmc_load_image_raw_sector: mmc block read error
  SPL: failed to boot from all boot devices
  ### ERROR ### Please RESET the board ###

The only known way to reliably detect USB serial downloader
is by checking the USB PHY receiver block power state...

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
2017-09-18 17:15:22 +02:00
Tom Rini
45d19acb2f Merge git://git.denx.de/u-boot-uniphier 2017-09-18 10:58:10 -04:00
Stefan Agner
7d289d6239 imx: add macro to detect whether USB PHY is active
This macro allows to detect whether the USB PHY is active. This
is helpful to detect if the boot ROM has previously started the
USB serial downloader.

The idea is taken from the mfgtool support in the NXP U-Boot:
http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/commit/?h=imx_v2016.03_4.1.15_2.0.0_ga&id=a352ed3c5184b95c4c9f7468f5fbb5f43de5e412

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
2017-09-18 16:51:36 +02:00
Masahiro Yamada
a184fb8e96 ARM: uniphier: add GPU(Mali) reset deassert and clk enable
The driver for Linux is out of control of Socionext, so set up
reset / clock in here.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-09-18 20:26:18 +09:00
Masahiro Yamada
2bf7c86ebb ARM: uniphier: remove bit field macros from sc64-regs.h
Starting from PXs3, the bit fields of  RSTCTRL, CLKCTRL registers
will change every SoC.  There is no more point to define bitfields
in the common header file.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-09-18 20:26:12 +09:00
Masahiro Yamada
81b9bb5fcb ARM: uniphier: merge two defconfig files into uniphier_v7_defconfig
The main difference between Pro4 and PXs2/LD6b is the Denali NAND
IP version.  This is now distinguished by DT.  Merge the two defconfig
files into uniphier_v7_defconfig.

Update the README.uniphier too.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-09-18 20:26:06 +09:00
Masahiro Yamada
6c71b6f454 mtd: nand: denali: allow to override corrupted revision register
The Denali IP does not update the revision register properly.
Allow to override it with SoC data associated with compatible.

Linux had already finished big surgery of this driver, but I need
to prepare the NAND core before the full sync of the driver.
For now, I am fixing the most fatal problem on UniPhier platform.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-09-18 20:26:00 +09:00
Tom Rini
c07f38208a Merge git://git.denx.de/u-boot-x86 2017-09-17 11:46:51 -04:00
Heinrich Schuchardt
8a1c44271c x86: ivybridge: remove unused variables
legacy_hole_base_k and legacy_hole_size_k are defined but
not used.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-16 14:57:44 +08:00
Simon Glass
2b2e9f6b9e x86: Enable early timer for chromebook_link
Enable this option for link so that the timer is available earlier.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-16 14:57:44 +08:00
Simon Glass
d69bb0ecbf bootstage: Provide a separate record count setting for SPL
With SPL we often have limited memory and do not need very many bootstage
records. Add a separate Kconfig option for SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-16 14:57:44 +08:00
Simon Glass
066b25b6c4 bootstage: Drop unused options
The CONFIG_BOOTSTAGE_USER_COUNT option is no-longer needed since we can now
support any number of user IDs. Also BOOTSTAGE_ID_COUNT is not needed now.

Drop these unused options.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-16 14:57:44 +08:00
Simon Glass
2ff50f5fa4 dm: x86: Allow TSC timer to be used before DM is ready
With bootstage we need access to the timer before driver model is set up.
To handle this, put the required state in global_data and provide a new
function to set up the device, separate from the driver's probe() method.

This will be used by the 'early' timer also.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-16 14:57:44 +08:00
Simon Glass
5ee94b4f40 board_f: Drop the timer after relocation
Once U-Boot relocates itself the existing driver-model timer (if any) is
no-longer valid until the device is reinitialised. Any use of the device
may cause a crash. To handle this, set the timer to NULL after relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-16 14:57:44 +08:00
Bin Meng
eb45787b39 x86: Support Intel Cherry Hill board
This adds support to Intel Cherry Hill board, a board based on
Intel Braswell SoC. The following devices are validated:

- serial port as the serial console
- on-board Realtek 8169 ethernet controller
- SATA AHCI controller
- EMMC/SDHC controller
- USB 3.0 xHCI controller
- PCIe x1 slot with a graphics card
- ICH SPI controller with an 8MB Macronix SPI flash
- Integrated graphics device as the video console

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16 14:57:44 +08:00
Bin Meng
507f1024b8 x86: braswell: Disable PUNIT power configuration for B0 stepping
FSP's built-in UPD configuration enables PUNIT power configuration,
but on B0 stepping, this causes CPU hangs in fsp_init(). Disable it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16 14:57:44 +08:00
Bin Meng
fffad9264a x86: braswell: Add FSP configuration
Add FSP related configuration for Braswell.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16 14:57:44 +08:00
Bin Meng
e61a2687b3 x86: braswell: Add microcode for B0/C0/D0 stepping SoC
This adds microcode device tree fragment for Braswell B0 (406C2),
C0 (406C3) and D0 (406C4) stepping SoC.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16 14:57:44 +08:00
Bin Meng
de9ac9a1b9 x86: Add Intel Braswell SoC support
This adds initial Intel Braswell SoC support. It uses Intel FSP
to initialize the chipset.

Similar to its predecessor BayTrail, there are some work to do to
enable the legacy UART integrated in the Braswell SoC.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16 14:57:44 +08:00
Bin Meng
b3fd2126dc x86: fsp: Update fsp command to show spec 1.1 header
FSP spec 1.1 adds 3 new APIs and their offsets are in the header.
Update the 'fsp hdr' command to show these new entries.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16 14:57:44 +08:00
Bin Meng
5df91f1c82 x86: dm: video: Add a framebuffer driver that utilizes VBT
When a VBT is given to an FSP that supports graphics initialization,
the FSP will produce a graphics info HOB that contains all necessary
information for the linear frame buffer of the integrated graphics
device. This adds a DM video driver for it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16 14:57:44 +08:00
Bin Meng
6c22379eaf x86: dts: Include Intel Video BIOS Table in the ROM image
Now that binman is able to recognize the Video BIOS Table entry,
add such one in the u-boot.dtsi.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16 14:57:44 +08:00
Bin Meng
59ea8c250b tools: binman: Add a new entry type for Intel VBT
This adds a new entry type for Intel Video BIOS Table.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16 14:57:44 +08:00
Bin Meng
ae3ca1251d x86: Add Video BIOS Table (VBT) related Kconfig options
This adds Kconfig options for Video BIOS Table which is normally
required if you are using an Intel FSP firmware that is complaint
with spec 1.1 or later to initialize the integrated graphics device.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16 14:57:44 +08:00
Bin Meng
4ff333b7dd x86: fsp: Add FSP_GRAPHICS_INFO_HOB
This adds a new HOB type for graphics information introduced in FSP
spec 1.1. When graphics capability is included in FSP and enabled,
FSP produces an FSP_GRAPHICS_INFO_HOB as described in the EFI PI
specification which provides information about the graphics mode and
framebuffer.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16 14:57:44 +08:00
Bin Meng
bb737ced7f x86: fsp: Update struct common_buf for FSP spec 1.1
FSP spec 1.1 adds one more member to the struct common_buf to
determine the memory size that can be reserved by FSP below "top
of low usable memory" for bootloader usage. This new member uses
the reserved space so that it is still compatible with previous
FSP spec 1.0.

A new HOB (FSP_HOB_RESOURCE_OWNER_BOOTLOADER_TOLUM_GUID) is also
published when common_buf.tolum_size is valid and non zero.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16 14:57:44 +08:00
Bin Meng
3df39ef107 x86: tsc: Add Airmont reference clock values
Per the Intel 64 and IA-32 Architecture Software Developer's Manual,
add the reference clock for Intel Atom Processors based on the Airmont
Microarchitecture (Braswell).

This keeps in sync with Linux kernel commit:
  6fcb41c: x86/tsc_msr: Add Airmont reference clock values

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16 14:57:44 +08:00
Tom Rini
08cebeeaad Merge git://git.denx.de/u-boot-fdt 2017-09-15 22:34:34 -04:00
Stephen Warren
110ba62519 test/py: gpt: make use of infra-structure
Make various changes to the GPT test:

1) Reference the disk image using an absolute path in all cases. This
allows test/py to operate correctly if it's run from a directory other
than the root of the U-Boot source tree.

2) Store the disk image in the teswt/py persistent data directory. This
removes the need to re-generate it every time the tests are run.

3) Execute sgdisk using u_boot_utils.run_and_log() so that its output is
captured in the test log. This allows debugging any problems running it.

4) Make the disk image a test fixture. This removes the requirement to
always run all GPT tests, and run them in order. The current code doesn't
create the disk image if e.g. just test_gpt_uuid() is executed via the
test.py -k command-line option.

5) Use @pytest.mark.buildconfigspec for all feature dependencies, rather
than manually implementing some of them.

6) Make all tests depend on sandbox, since they use the sandbox-specific
host command.

Fixes: a2f422555f ("add pytests for 'gpt guid' command in sandbox")
Fixes: c5772188ed ("add pytests for 'gpt rename' and 'gpt swap'")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Tom Rini <trini@konsulko.com>
2017-09-15 22:33:41 -04:00
Adam Ford
079c92b0a7 ARM: davinci: Remove CONFIG_SOC_DA830
Nothing CONFIG_SOC_DA830 anymore, so let's remove it and
the one remaining source file for it. It appears to have been
abandoned a while ago.

Signed-off-by: Adam Ford <aford173@gmail.com>
2017-09-15 12:35:48 -04:00
Jean-Jacques Hiblot
8ce5fac9a0 arm: dts: Add missing u-boot specific dtsi for dra7-evm
commit b63b995 (arm: dts: Add u-boot specific compatibles) separated out
u-boot specific compatibles from dts files.
The u-boot specifics were moved in *-u-boot.dtsi files for all dra7
platforms except dra7-evm.
Without it the SD card is broken on DRA7-evm because the regulator cannot
be enabled.
Fix it by adding the missing dra7-evm-u-boot.dtsi with the needed
properties.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-15 12:35:48 -04:00
Harinarayan Bhatta
a1e4bc65e1 arm: mach-omap2: Relax checks on OP-TEE location to allow pageable image
When the OP-TEE image is built for secure paging the load address may be
in SRAM, remove checks that prevent this.

Signed-off-by: Harinarayan Bhatta <harinarayan@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-15 09:03:16 -04:00
Rob Clark
725ffdb5cb fs/fat: fix fatbuf leak
A new fatbuf was allocated by get_fs_info() (called by fat_itr_root()),
but not freed, resulting in eventually running out of memory.  Spotted
by running 'ls -r' in a large FAT filesystem from Shell.efi.

fatbuf is mainly used to cache FAT entry lookups (get_fatent())..
possibly once fat_write.c it can move into the iterator to simplify
this.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
2017-09-15 09:03:15 -04:00
Rob Clark
265edc03d5 fs/fat: Clean up open-coded sector <-> cluster conversions
Use the clust_to_sect() helper that was introduced earlier, and add an
inverse sect_to_clust(), plus update the various spots that open-coded
this conversion previously.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-15 09:03:15 -04:00
Rob Clark
21a24c3bf3 fs/fat: fix case for FAT shortnames
Noticed when comparing our output to linux.  There are some lcase bits
which control whether filename and/or extension should be downcase'd.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-15 09:03:14 -04:00
Rob Clark
89191d6267 fat/fs: move ls to generic implementation
Add a generic implementation of 'ls' using opendir/readdir/closedir, and
replace fat's custom implementation.  Other filesystems should move to
the generic implementation after they add opendir/readdir/closedir
support.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-15 09:03:13 -04:00
Rob Clark
41fa83d1a6 fat/fs: remove a bunch of dead code
Spotted by chance, when trying to remove file_fat_ls(), I noticed there
were some dead users of the API.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Acked-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-15 09:03:12 -04:00
Rob Clark
1f40366b31 fs/fat: implement opendir/readdir/closedir
Implement the readdir interface using the directory iterators.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-15 09:03:12 -04:00
Rob Clark
4bbcc965f9 fs: add fs_readdir()
Needed to support efi file protocol.  The fallback.efi loader wants
to be able to read the contents of the /EFI directory to find an OS
to boot.

Modelled after POSIX opendir()/readdir()/closedir().  Unlike the other
fs APIs, this is stateful (ie. state is held in the FS_DIR "directory
stream"), to avoid re-traversing of the directory structure at each
step.  The directory stream must be released with closedir() when it
is no longer needed.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-15 09:03:11 -04:00
Rob Clark
8eafae209c fat/fs: convert to directory iterators
And drop a whole lot of ugly code!

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-15 09:03:11 -04:00
Rob Clark
c6e3baa565 fs/fat: introduce new director iterators
Untangle directory traversal into a simple iterator, to replace the
existing multi-purpose do_fat_read_at() + get_dentfromdir().

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
2017-09-15 09:03:10 -04:00
Rob Clark
45449980f8 fs/fat: split out helper to init fsdata
Want to re-use this in fat dirent iterator in next patch.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-15 09:03:09 -04:00
Tom Rini
1c7b5d0309 Merge git://git.denx.de/u-boot-ubi 2017-09-15 08:45:21 -04:00
Tom Rini
c977226840 Merge git://git.denx.de/u-boot-i2c 2017-09-15 08:45:10 -04:00
Heinrich Schuchardt
cd3e8a72a6 test/py: u_boot_console_base.py: fix typo
run_command does not have a parameter wait_for_each.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-09-15 08:05:12 -04:00
Heinrich Schuchardt
5c761ce586 checkpatch.pl: Add warning for new __packed additions
While there are valid reasons to use __packed, often the answer is that
you should be doing something else here instead.

This reintroduces the changes of
f503cc49a5 (Add warning for new __packed additions)

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-09-15 08:05:11 -04:00
Bin Meng
e2888a7fa7 cmd: blk: Use LBAFU in the common block command
There is already a macro LBAFU to aid formatted print with lbaint_t
variables. Let's use it in the common block command codes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-15 08:05:10 -04:00
Bin Meng
723b43daec blk: Remove various places that do flush cache after read
All these places seem to inherit the codes from the MMC driver where
a FIXME was put in the comment. However the correct operation after
read should be cache invalidate, not flush.

The underlying drivers should be responsible for the cache operation.
Remove these codes completely.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: York Sun <york.sun@nxp.com>
2017-09-15 08:05:10 -04:00
Pantelis Antoniou
ea28e488f7 test: overlay: Add unit test for stacked overlay
Verify that stacked overlays work.

Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-09-15 05:27:49 -06:00
Pantelis Antoniou
706708d3b2 ut: fix fdt_getprop_u32() change
fdt_getprop_u32 is not exported and it's different than what the
unit test uses. Rename u32 prop access methods to something that's
unit test specific.

Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-09-15 05:27:49 -06:00
Pantelis Antoniou
1e9c4393fd config: sandbox: Add unit tests
Add unit tests for sandbox default config.

Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-09-15 05:27:49 -06:00
Pantelis Antoniou
da0b3a946f dtbo: make dtbos special
Special rule for dtbo generation

Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-09-15 05:27:49 -06:00
Franklin S Cooper Jr
56fc7032e1 doc: overlays: Tweak documentation regarding overlays
Pull some information regarding overlays from commit messages and
put them directly within the documentation. Also add some information
regarding required dtc version to properly use overlays.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-09-15 05:27:49 -06:00
Pantelis Antoniou
d80162cfc5 doc: Document how to apply fdt overlays
We have the capability to apply overlays on the command line but
we didn't have a document explaining how.

Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Reviewed-by: Łukasz Majewski
Acked-by: Simon Glass <sjg@chromium.org>
2017-09-15 05:27:49 -06:00
Pantelis Antoniou
6b54e50b5a fit: fdt overlays doc
Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Reviewed-by: Łukasz Majewski
Acked-by: Simon Glass <sjg@chromium.org>
2017-09-15 05:27:49 -06:00
Pantelis Antoniou
169043d826 fit: Introduce methods for applying overlays on fit-load
Introduce an overlay based method for constructing a base DT blob
to pass to the kernel.

It is based on a specific method now to get the FDT from a FIT image
named boot_get_fdt_fit().

Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-09-15 05:27:49 -06:00
Pantelis Antoniou
7c3dc776b9 fit: Do not throw away extra configuration on fit_image_load()
fit_image_load() threw away the extra configuration parts when
loading. We need them around for applying extra overlays for
building the boot fdt.

Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-09-15 05:27:48 -06:00
Pantelis Antoniou
ad026adbcf fit: Allow multiple images per property
As part of the fdt overlay support which need it, allow
a list of configurations per property.

Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-09-15 05:27:48 -06:00
Pantelis Antoniou
f00c36a01e fdt: Allow stacked overlays phandle references
This patch enables an overlay to refer to a previous overlay's
labels by performing a merge of symbol information at application
time.

In a nutshell it allows an overlay to refer to a symbol that a previous
overlay has defined. It requires both the base and all the overlays
to be compiled with the -@ command line switch so that symbol
information is included.

base.dts
--------

	/dts-v1/;
	/ {
		foo: foonode {
			foo-property;
		};
	};

	$ dtc -@ -I dts -O dtb -o base.dtb base.dts

bar.dts
-------

	/dts-v1/;
	/plugin/;
	/ {
		fragment@1 {
			target = <&foo>;
			__overlay__ {
				overlay-1-property;
				bar: barnode {
					bar-property;
				};
			};
		};
	};

	$ dtc -@ -I dts -O dtb -o bar.dtb bar.dts

baz.dts
-------

	/dts-v1/;
	/plugin/;
	/ {
		fragment@1 {
			target = <&bar>;
			__overlay__ {
				overlay-2-property;
				baz: baznode {
					baz-property;
				};
			};
		};
	};

	$ dtc -@ -I dts -O dtb -o baz.dtb baz.dts

Applying the overlays:

	$ fdtoverlay -i base.dtb -o target.dtb bar.dtb baz.dtb

Dumping:

	$ fdtdump target.dtb
	/ {
            foonode {
                overlay-1-property;
                foo-property;
                linux,phandle = <0x00000001>;
                phandle = <0x00000001>;
                barnode {
                    overlay-2-property;
                    phandle = <0x00000002>;
                    linux,phandle = <0x00000002>;
                    bar-property;
                    baznode {
                        phandle = <0x00000003>;
                        linux,phandle = <0x00000003>;
                        baz-property;
                    };
                };
            };
            __symbols__ {
                baz = "/foonode/barnode/baznode";
                bar = "/foonode/barnode";
                foo = "/foonode";
            };
	};

Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Acked-by: Simon Glass <sjg@chromium.org>
2017-09-15 05:27:48 -06:00
Pantelis Antoniou
81ecc5d92b fdt: Switch to using the verbose overlay application method
The verbose overlay application method prints out more helpful
messages, so switch to it.

Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-09-15 05:27:48 -06:00
Pantelis Antoniou
fc7c31891c fdt: Introduce helper method fdt_overlay_apply_verbose()
Introduce fdt_overlay_apply_verbose, a method that applies an
overlay but in the case of an error produces a helpful message.

In addition if a base tree is found to be missing the __symbols__
node the message will point out that the probable reason is that
the base tree was miscompiled without the -@ option.

Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-09-15 05:27:48 -06:00
Tien Fong Chee
18c991ca2b libfdt: Initialize the stack variable
Report Coverity log:
The code uses a variable that has not
been initialized, leading to unpredictable
or unintended results.

Reported-by: Coverity (CID: 60519)
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2017-09-15 05:27:48 -06:00
Simon Glass
d503114c66 dtoc: Add a header to the generated files
Add a header that indicates that the files generated by dtoc should not be
modified.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-09-15 05:27:48 -06:00
Simon Glass
b145b45b0c dtoc: Rename the auto-generated dt-structs.h file
The filename of the auto-generated file is the same as the file that
includes it. Even though the form is in the generated/ subdirectory, this
could be confused.

Rename the generated file to something that makes it clear it is
auto-generated.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-09-15 05:27:48 -06:00
Simon Glass
634eba4be0 dtoc: Support properties containing multiple phandle values
At present dtoc has a very simplistic view of phandles. It assumes that
a property has only a single phandle with a single argument (i.e. two
cells per property).

This is not true in many cases. Enhance the implementation to scan all
phandles in a property and to use the correct number of arguments (which
can be 0, 1, 2 or more) when generating the C code. For the struct
definitions, use a struct which can hold the maximum number of arguments
used by the property.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-09-15 05:27:48 -06:00
Simon Glass
bc79617fdf dtoc: Put phandle args in an array
We want to support more than one phandle argument. It makes sense to use
an array for this rather than discrete struct members. Adjust the code to
support this. Rename the member to 'arg' instead of 'id'.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-09-15 05:27:48 -06:00
Simon Glass
35d503700f dtoc: Put each phandle on a separate line
When writing values from properties which contain phandles, dtoc currently
writes 8 phandles per line. Change this to write one phandle per line.
This helps reduce line length, since phandles are generally longer and may
have arguments.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-09-15 05:27:47 -06:00
Simon Glass
0d15463c05 dtoc: Rename the phandle struct
Rather than naming the phandle struct according to the number of cells it
uses (e.g. struct phandle_2_cell) name it according to the number of
arguments it has (e.g. struct phandle_1_arg). This is a more intuitive
naming.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-09-15 05:27:47 -06:00
Simon Glass
8fed2eb20c dtoc: Rename is_phandle() and adjust it to return more detail
Update this function to return more detail about a property that contains
phandles. This will allow (in a future commit) more accurate handling of
these properties.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-09-15 05:27:47 -06:00
Simon Glass
2925c26bb2 dtoc: Make is_phandle() a member function
This function will need to have access to class members once we enhance it
to support multiple phandle values. In preparation for that, move it into
the class.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-09-15 05:27:47 -06:00
Simon Glass
72ab7c5e38 dtoc: Use the Fdt's class's phandle map
Now that the Fdt class can map phandles to the associated nodes, use that
instead of a separate implementation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-09-15 05:27:47 -06:00
Simon Glass
09264e0433 dtoc: Update the Fdt class to record phandles
Add a map from phandles to nodes. This can be used by clients of the the
class instead of maintaining this themselves.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-09-15 05:27:47 -06:00
Simon Glass
5ec741fd84 dtoc: Handle 'reg' properties with unusual sizes
At present dtoc assumes that all 'reg' properties have both an address and
a size. For I2C devices we do not have this. Adjust dtoc to cope.

Reported-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-09-15 05:27:47 -06:00
Simon Glass
c20ee0ed07 dtoc: Add support for 32 or 64-bit addresses
When using 32-bit addresses dtoc works correctly. For 64-bit addresses it
does not since it ignores the #address-cells and #size-cells properties.

Update the tool to use fdt64_t as the element type for reg properties when
either the address or size is larger than one cell. Use the correct value
so that C code can obtain the information from the device tree easily.

Alos create a new type, fdt_val_t, which is defined to either fdt32_t or
fdt64_t depending on the word size of the machine. This type corresponds
to fdt_addr_t and fdt_size_t. Unfortunately we cannot just use those types
since they are defined to phys_addr_t and phys_size_t which use
'unsigned long' in the 32-bit case, rather than 'unsigned int'.

Add tests for the four combinations of address and size values (32/32,
64/64, 32/64, 64/32). Also update existing uses for rk3399 and rk3368
which now need to use the new fdt_val_t type.

Signed-off-by: Simon Glass <sjg@chromium.org>

Suggested-by: Heiko Stuebner <heiko@sntech.de>
Reported-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-09-15 05:27:38 -06:00
Simon Glass
21d54ac353 dtoc: Avoid very long lines in output
Large arrays can result in lines with hundreds or thousands of characters
which is not very editor-friendly. To avoid this, addjust the tool to
group values 8 per line.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-09-15 05:24:39 -06:00
Simon Glass
fbdfd228fb dtoc: Add a 64-bit type and a way to convert cells into 64 bits
When dealing with multi-cell values we need a type that can hold this
value. Add this and a function to process it from a list of cell values.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-09-15 05:24:39 -06:00
Simon Glass
979ab02473 dtoc: Adjust Node to record its parent
We need to be able to search back up the tree for #address-cells and
 #size-cells. Record the parent of each node to make this easier.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-09-15 05:24:39 -06:00
Simon Glass
93c94b889b fdt: Sync libfdt up to upstream
Add upstream changes to U-Boot:

- new pylibfdt functions
- fdt_setprop_placeholder()

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-09-15 05:24:39 -06:00
Tom Rini
ae1c0a38c8 Travis-CI: Switch back to using the top of tree dtc
In a0f3e3df4a we switched to using the Ubuntu-provided dtc as travis
was having a problem with the number of warnings that were generated by
the newer dtc.  This is no longer a concern as we now have the same
logic as Linux to enable/disable additional more stringent warnings.  Go
back to building dtc from source.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on travis-ci:
Tested-by: Simon Glass <sjg@chromium.org>
2017-09-15 05:24:33 -06:00
Heinrich Schuchardt
6305db9604 checkpatch: update from Linux v4.13-rc6
Checkpatch produces the following warning:

Unescaped left brace in regex is deprecated here
(and will be fatal in Perl 5.30), passed through in regex;
marked by <-- HERE in m/^(\+.*(?:do|\))){ <-- HERE /
at scripts/checkpatch.pl line 3348.

The curent checkpatch of the Linux kernel corrects this
bug and many others.

It provides improved colored output.

So replace checkpatch by the current Linux version.

Add an empty file scripts/const_structs.checkpatch.
We can later fill it according to our needs.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-09-14 21:33:00 -04:00
Rob Clark
2e79461483 lib: strto: fix incorrect handling of specified base
The strto functions should honor the specified base (if non-zero) rather
than permitting a hex or octal string when the user wanted (for example)
base 10.

This has been fixed somewhere along the way in the upstream linux kernel
src tree, at some point after these was copied in to u-boot.  And also
in a way that duplicates less code.  So port _parse_integer_fixup_radix()
to u-boot.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14 21:32:59 -04:00
Alison Chaiken
c5772188ed add pytests for 'gpt rename' and 'gpt swap'
Add unit tests for the 'gpt rename' and 'gpt swap' commands that
rely on the block device created by test/py/make_test_disk.py.
Add CONFIG_CMD_GPT_RENAME to the sandbox_defconfig.  Remove the
testdisk.raw test device at the end of the tests.

Signed-off-by: Alison Chaiken <alison@peloton-tech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14 21:32:59 -04:00
Alison Chaiken
a2f422555f add pytests for 'gpt guid' command in sandbox
Run unit tests for the 'gpt guid' command, making use of the block
device created by test/py/make_test_disk.py.  Remove this device at
the end of the tests.

Signed-off-by: Alison Chaiken <alison@peloton-tech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14 21:32:57 -04:00
Alison Chaiken
bf6d76b84a GPT: create block device for sandbox testing
Provide a Python function that creates a small block device for the
purpose of testing the cmd/gpt.c or cmd/part.c functions in the u-boot
sandbox.

Signed-off-by: Alison Chaiken <alison@peloton-tech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14 21:32:57 -04:00
Suman Anna
2f9455c849 ARM: DRA7: Cleanup old pinctrl macros
Commit 6ae4c3efbd ("ARM: DRA7: Add pinctrl register definitions")
has added new macros for pinmux configuration in line with the kernel
definitions. Cleanup the old pinctrl macros from the common header
file so that they are not used by any new boards.

Signed-off-by: Suman Anna <s-anna@ti.com>
2017-09-14 21:32:56 -04:00
Suman Anna
101d2171e1 arm: am57xx: cl-som-am57x: Use new pinctrl macros
Commit 6ae4c3efbd ("ARM: DRA7: Add pinctrl register definitions")
has added new macros for pinmux configuration in line with the
kernel definitions. Fixup the current pinctrl data for the CompuLab
CL-SOM-AM57x board to use these new macros to facilitate the removal
of the old macros.

NOTE:
The PEN and PDIS macro values used previously were actually defined
inversely, a value of 1 in bit position 16 actually means that the
internal pullup/pulldown is disabled and not enabled as inferred by
PEN. So, previous pinmux config data such as (PDIS | PTU) is confusing
as it actually was meant for enabling internal pullup. The data is
fixed up only to be equivalent to the previous data.

Signed-off-by: Suman Anna <s-anna@ti.com>
2017-09-14 21:32:55 -04:00
Wenyou Yang
5541543f68 configs: at91: Remove CONFIG_SYS_EXTRA_OPTIONS assignment
To remove the assignment of CONFIG_SYS_EXTRA_OPTIONS option,
which is deprecated, use the CONFIG_XXXX_BOOT options to
indicate the boot media, and the SoC is selected by the board.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-09-14 16:02:48 -04:00
Wenyou Yang
a35c34025e ARM: at91: spl: Add macro CONFIG_XXXX_BOOT support
Use the CONFIG_XXXX_BOOT to indicate the boot media, instead of
the CONFIG_SYS_USE_XXXX option, which is declared by
CONFIG_SYS_EXTRA_OPTIONS option.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-09-14 16:02:47 -04:00
Wenyou Yang
e61ed48ff5 ARM: at91: Remove hardware.h included in configs
As said in READRE.kconfig, include/configs/*.h will be removed
after all options are switched to Kconfig. As the first step,
remove the follow line from include/configs/*.h.

 #include <asm/hardware.h>

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-09-14 16:02:47 -04:00
Wenyou Yang
2269337614 ARM: at91: Add the SoC options to Kconfig
To prepare to remove the SoCs options such as SAMA5D2, SAMA5D3
and SAMA5D4 from the CONFIG_SYS_EXTRA_OPTIONS option which is
deprecated, add the SoC options to Kconfig.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-09-14 16:02:47 -04:00
Wenyou Yang
6553581a81 ARM: at91: Move CONFIG_AT91FAMILY option to Kconfig
Move the CONFIG_AT91FAMILY option from include/mach/<soc>.h header
file to Kconfig.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-09-14 16:02:46 -04:00
Wenyou Yang
ce4054bf82 board: atmel: Add SAMA5D27 SOM1 EK board
The SAMA5D27-SiP (System in Package) integrates the SAMA5D2
with 1Gbit DDR2-SDRAM in a single package.

The SAMA5D27 SOM1 embeds a 64Mbit QSPI flash, KSZ8081 Phy and
Mac-address EEPROM.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14 16:02:46 -04:00
Wenyou Yang
245cbc583d ARM: at91: Get the Chip ID of SAMA5D2 SiP
The SAMA5D2 SiP(System in Package) has different Chip IDs in the
CHIPID and CHIP_EXID registers.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14 16:02:45 -04:00
Wenyou Yang
b5c13daca4 ARM: at91: mach: Add missing defines of MPDDRC
Add missing defines of Multiport DDR-SDRAM Controller (MPDDRC).

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14 16:02:45 -04:00
Wenyou Yang
dfd6d3a9d4 ARM: at91: spl: Add boot device for boot from QSPI
Add the boot device for booting from the QSPI flash.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14 16:02:45 -04:00
Wenyou Yang
23a19e0358 board: sama5d2_xplained: Make SPL work on spiflash
Because before switching to a lower clock source, we must switch
the clock source first instead of last. So before configuring the
PMC_MCKR register, invoke at91_mck_init_down() first.

As said in datasheet, the the size of SPL must not exceed the maximum
size allowed(64Kbytes).

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14 16:02:44 -04:00
Wenyou Yang
2b21cf55cc ARM: at91: spl: Add mck function to lower rate while switching
Refer to the commit 70f8c8316ad(PMC: add new mck function to lower
rate while switching) from AT91Bootstrap.

While switching to a lower clock source, we must switch the clock
source first instead of last. Otherwise, we could end up with
too high frequency on internal bus and peripherals.
This happens on SAMA5D2 as exitting from the ROM code.

Add a function pmc_mck_init_down() to allow this sequence.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14 16:02:44 -04:00
Wenyou Yang
3ceb5118c6 ARM: at91: spl: Adjust switching to oscillator for SAMA5D2
As said in 29.5.7 section of SAMA5D2 datasheet, before switching to
the crystal oscillator, a check must be carried out to ensure that
the oscillator is present and that its freqency is valid.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14 16:02:44 -04:00
Wenyou Yang
82e0646af7 atmel: common: Add function to display via DM_VIDEO's API
Add a function to display the company's logo and board information
via the API from DM_VIDEO. This function can be shared by other
atmel boards, so locate it in board/atmel/common folder.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14 16:02:43 -04:00
Wenyou Yang
d330e04d9d lib: at91: Add logo files used via API of DM_VIDEO
In order to display the company's logo via the API of DM_VIDEO,
and add the logo files of both Atmel and Microchip.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14 16:02:43 -04:00
Wenyou Yang
56246d1e87 ARM: dts: at91: sama5: Add the sfr node
For sama5d2, add the sfr node with syscon support.

In order to access the SFR_UTMICKTRIM register for the utmi clock
driver, add the phandle property for the utmi node to point to the
sfr node.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-09-14 16:02:43 -04:00
Wenyou Yang
e7c831543a clk: at91: utmi: Set the reference clock frequency
By default, it is assumed that the UTMI clock is generated from
a 12 MHz reference clock (MAINCK). If it's not the case, the FREQ
field of the SFR_UTMICKTRIM has to be updated to generate the UTMI
clock in the proper way.

The UTMI clock has a fixed rate of 480 MHz. In fact, there is no
multiplier we can configure. The multiplier is managed internally,
depending on the reference clock frequency, to achieve the target
of 480 MHz.

The patch is cloned from the patch of mailing-list:
	[PATCH v2] clk: at91: utmi: set the mainck rate

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
[trini: Depend on SPL_DM]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-14 16:02:29 -04:00
Wenyou Yang
0712b672d2 clk: Kconfig: Add dependences of SPL_CLK
The SPL_CLK config should depend on SPL && SPL_DM.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14 13:58:22 -04:00
Tom Rini
b861c61698 Merge git://git.denx.de/u-boot-dm 2017-09-13 21:35:45 -04:00
Simon Glass
ad8931400b patman: Fix error when the email blacklist is missing
This section of the settings file may be missing. Handle that gracefully
rather than emitting an error.

Also update patman to write this section when a new settings file is
created.

Fixes: e11aa602 (patman: add support for omitting bouncing addresses)

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Chris Packham <judge.pckham@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-13 19:32:13 -06:00
Adam Ford
e333083bf3 ARM: davinci: Update da8xxevm Maintainers
The e-mail addresses for DA8XXEVM BOARD and DA850_AM18XXEVM BOARD
are invalid.

Remove DA8XXEVM.

Update DA850_AM18XXEVM to have me be the maintainer since I work
for Logic PD and have access to OMAP-L138 and AM1808 EVM kits.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-13 09:24:28 -04:00
Adam Ford
34330a362f Convert CONFIG_EMIF4 et al to Kconfig
This converts the following to Kconfig:
   CONFIG_EMIF4
   CONFIG_SDRC

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-09-13 09:24:27 -04:00
Adam Ford
f0333b4c2e Convert CONFIG_MAC_ADDR_IN_SPIFLASH et al to Kconfig
This converts the following to Kconfig:
   CONFIG_MAC_ADDR_IN_SPIFLASH
   CONFIG_MAC_ADDR_IN_EEPROM

Signed-off-by: Adam Ford <aford173@gmail.com>
2017-09-13 09:24:27 -04:00
Adam Ford
919ccb9fe5 davinci: da850evm: Make EEPROM MAC code configurable
There was a check for CONFIG_MAC_ADDR_IN_EEPROM and
a check for CONFIG_MAC_ADDR_IN_SPIFLASH, however
some of the EEPROM related code wasn't encapsulated
inside the #if defined statement so the EEPROM code
could get executed even when it wasn't explicitly
enabled or wanted.

Signed-off-by: Adam Ford <aford173@gmail.com>
2017-09-13 09:24:26 -04:00
Adam Ford
7672d9d582 include/configs: remove references to SMNAND_ENV_OFFSET
In mancy cases both CONFIG_ENV_OFFSET and CONFIG_ENV_ADDR point
to an otherwise-unused SMNAND_ENV_OFFSET.
This patch will set both CONFIG_ENV_OFFSET and CONFIG_ENV_ADDR to
whatever value was defined by SMNAND_ENV_OFFSET.

Signed-off-by: Adam Ford <aford173@gmail.com>
2017-09-13 09:24:26 -04:00
Adam Ford
bf1ddfc026 arm: dts: omap3: Re-sync DTS files with Linux 4.13-RC5
The DTS files had some spacing issues and they needed fixing. This
pull re-sync's the OMAP3xx related DTS files with Linux 4.13-RC5.

To keep the DTS and DTSI files clean and in sync with Linux, new
u-boot.dtsi files are added.

Signed-off-by: Adam Ford <aford173@gmail.com>

V3: The resync broke card detect on MMC1 on Logic PD's Torpedo,
    so we add the cd-invert to the Torpedo's -u-boot.dtsi file.

V2: Add the u-boot.dtsi files for OMAP3, OMAP36xx, and Torpedo
    Remove the need for the second patch in the series
2017-09-13 09:24:26 -04:00
Adam Ford
74cd48e132 omap3: omap3_logic: Finish enabling fastboot on MUSB
Either the USB and Fastboot were never finished, or somehow it got
lost.  This puts enough hooks back into omap3logic to enable
fastboot and hopefully prepare it for Kconfig conversion.

Signed-off-by: Adam Ford <aford173@gmail.com>
2017-09-13 09:24:25 -04:00
Wenyou Yang
3e9f8f2f51 ARM: dts: ethernut5: Fix the build warning
Fix the building warning as below:
---8<----
Warning (reg_format): "reg" property in /i2c-gpio-0/pcf8563@50 has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
Warning (avoid_default_addr_size): Relying on default #address-cells value for /i2c-gpio-0/pcf8563@50
Warning (avoid_default_addr_size): Relying on default #size-cells value for /i2c-gpio-0/pcf8563@50
--->8----

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-13 09:24:25 -04:00
Keng Soon Cheah
cac73f20ac serial: nulldev: Add nulldev serial driver
Some device the serial console's initialization cannot run early during
the boot process. Hence, nulldev serial device is helpful on that
situation.

For example, if the serial module was implemented in FPGA. Serial
initialization is prohibited to run until the FPGA was programmed.

This commit is to adding nulldev serial driver. This will allows the
default console to be specified as a nulldev.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Keng Soon Cheah <keng.soon.cheah@ni.com>
Cc: Chen Yee Chew <chen.yee.chew@ni.com>
2017-09-13 09:24:24 -04:00
Anatolij Gustschin
2d2531be86 spl: add newline in debug output
With debug enabled, SPL output following these debug prints is on the
same line and it is hard to read. Fix it.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-13 08:27:01 -04:00
Moritz Fischer
36bdeb75a4 i2c: muxes: pca954x: Add support for GPIO reset line
This commit adds support for GPIO reset lines matching the
common linux "reset-gpios" devicetree binding.

Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-13 05:35:48 +02:00
Vishal Mahaveer
ba39608147 ARM: DRA72x: Add support for detection of DRA71x SR 2.1
DRA71x processors are reduced pin and software compatible
derivative of DRA72 processors. Add support for detection
of SR2.1 version of DRA71x family of processors.

Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-12 18:02:29 -04:00
Adam Ford
f926837504 davinci: da850-evm: switch to using TI_COMMON_CMD_OPTIONS
Like the OMAP-L138 LCDK before it, let's move the da850-evm and
the variations to TI_COMMON_CMD_OPTIONS to cut back one some of the
defconfig entries.

Signed-off-by: Adam Ford <aford173@gmail.com>
2017-09-12 18:02:25 -04:00
Masahiro Yamada
6c06f8dc4a linux/io.h: import generic ioread* / iowrite* accessors from Linux
Some drivers in Linux (ex. drivers/mtd/nand/denali.c) use
ioread*/iowrite* accessors.  Import them to make drivers more
synced.  I copied code from include/asm-generic/io.h of Linux.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-09-12 18:02:23 -04:00
Masahiro Yamada
b27af39935 dma: import linux/dma-direction.h to consolidate enum dma_data_direction
Import include/linux/dma-direction.h from Linux 4.13-rc7 and delete
duplicated definitions of enum dma_data_direction.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2017-09-12 18:02:23 -04:00
Adam Ford
29487ef4d5 omap3: am3517_evm: Enable TI_COMMON_CMD_OPTION
Enable TI_COMMON_CMD_OPTIONS and remove similar options
from the defconfig. Updated with savedefconfig.

Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Derald D. Woods <woods.technical@gmail.com>
2017-09-12 18:02:21 -04:00
Adam Ford
261ec8f6a6 ARM: OMAP3: am3517_evm: Move header to ti_omap3_common.h
Much of the AM3517 functions are copies of the standard definitions
used in ti_omap3_common.h.  Moving to include a common file
reduces the amount of duplicative code and clutter.  A few
AM3517 specific functions (like EMIF4) are explictly defined
and a few items are undefined or redefined, but overall the number
of lines of code shink.

Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Derald D. Woods <woods.technical@gmail.com>
2017-09-12 18:01:31 -04:00
Andy Yan
347e30e172 armv8: mmu: add space around operator
Add space around operator "+", make it
match the coding style.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-12 18:00:09 -04:00
Andy Yan
4f84cb980f armv8: mmu: remove unused macro definition
Macro VA_BITS and PTE_BLOCK_BITS are not used
in the code, so remove them.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-12 18:00:08 -04:00
Tomas Melin
bac9170fb2 cosmetic: bootcount: correct comment for used scratch register
Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
2017-09-12 17:58:54 -04:00
Wenyou Yang
de6567522e misc: i2c_eeprom: Add compatible for AT24MAC402
Add the new compatible "atmel,24mac402" to accommodate AT24MAC402.
The AT24MAC402 is a 2K Serial EEPROM and the 2-Kbit memory array
is internally organized as 16 pages of 16 bytes of EEPROM each.
The 48-bit EUI address in the AT24MAC402 are located in the extended
memory block.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-09-12 17:58:54 -04:00
Wenyou Yang
7264066707 misc: i2c_eeprom: Add compatible for 24AA02E48
Add the new compatible "microchip,24aa02e48" to accommodate 24AA02E48,
the 24AA02E48 is a 2K I2C Serial EEPROM with pre-programmed globally
unique, 48-bit node address, and 8-byte page size.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-09-12 17:58:53 -04:00
Andrew F. Davis
82f1205601 configs: k2g_evm: Remove PMMC loading environment commands
The PMMC firmware should be bundled with the FIT image for HS devices,
remove the steps that load and install this firmware outside of FIT.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2017-09-12 17:58:03 -04:00
Andrew F. Davis
58fac52d2f ARM: k2g: Add FIT image handler for PMMC firmware
The PMMC firmware should be bundled into a FIT image on HS
devices to allow authentication/decryption, add a handler to
process this PMMC firmware.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2017-09-12 17:58:02 -04:00
Andrew F. Davis
6442c9643e image: Add TI PMMC image type
Add a new image type representing TI Power Management
Micro-Controller (PMMC) Firmware image type.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2017-09-12 17:58:02 -04:00
Rob Clark
7e3e205607 examples: add fallback memcpy
Solves build issue:

  Building current source for 134 boards (12 threads, 1 job per thread)
         arm:  +   lsxhl
  +examples/api/vsprintf.o: In function `string16':
  +lib/vsprintf.c:278: undefined reference to `memcpy'
  +examples/api/uuid.o: In function `uuid_bin_to_str':
  +lib/uuid.c:197: undefined reference to `memcpy'
  +lib/uuid.c:199: undefined reference to `memcpy'
  +make[3]: *** [examples/api/demo] Error 1
  +make[2]: *** [examples/api] Error 2
  +make[1]: *** [examples] Error 2
  +make: *** [sub-make] Error 2
    133    0    1 /134    sheevaplug

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-09-12 17:58:01 -04:00
Rob Clark
22ada0c8e6 vsprintf.c: add GUID printing
This works (roughly) the same way as linux's, but we currently always
print lower-case (ie. we just keep %pUB and %pUL for compat with linux),
mostly just because that is what uuid_bin_to_str() supports.

  %pUb:   01020304-0506-0708-090a-0b0c0d0e0f10
  %pUl:   04030201-0605-0807-090a-0b0c0d0e0f10

It will be used by a later efi_loader paths for efi variables and for
device-path-to-text protocol, and also quite useful for debug prints
of protocol GUIDs.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-12 17:58:00 -04:00
Rob Clark
274325c509 vsprintf.c: add UTF-16 string (%ls) support
This is convenient for efi_loader which deals a lot with UTF-16.  Only
enabled with CC_SHORT_WCHAR, leaving room to add a UTF-32 version when
CC_SHORT_WCHAR is not enabled.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-12 17:57:59 -04:00
Rob Clark
78178bb0c9 lib: add some utf16 handling helpers
We'll eventually want these in a few places in efi_loader, and also
vsprintf.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-09-12 17:57:59 -04:00
Rob Clark
4a85663ec7 kbuild: Enable -fshort-wchar
EFI_LOADER really wants UTF-16 strings (ie. %ls and L"string" are 16bit
chars instead of 32bit chars).  But rather than enabling -fshort-wchar
conditionally if EFI_LOADER is enabled, it was deemed preferrable to
globally switch.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-09-12 17:57:57 -04:00
Marek Vasut
e8f86f2bac ARM: rmobile: dts: Add XHCI USB node to r8a7796
The R8A7796 XHCI USB nodes are missing from r8a7796 dtsi, add them.
These nodes don't come from mainline Linux, yet the DT binding is
similar enough to R8A7795 which already has those in mainline and
once the nodes hit mainline, this DT should be resynched.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-12 23:02:30 +02:00
Marek Vasut
a79c31156e ARM: rmobile: Enable EHCI generic on ULCB
Enable the EHCI generic driver, which is superior to ad-hoc SoC specific one.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-12 19:07:24 +02:00
Marek Vasut
c54b0b754b ARM: rmobile: Enable EHCI generic on Salvator-X
Enable the EHCI generic driver, which is superior to ad-hoc SoC specific one.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-12 19:07:23 +02:00
Marek Vasut
ef60323326 ARM: rmobile: Move HSUSB configuration to board on ULCB
In order to use ehci-generic driver, move the configuration of HSUSB
block into the board file. This configuration should not have been in
the Gen3 EHCI USB driver in the first place, so move it to the board
file until there is a proper infrastructure and driver for the HSUSB
block.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-12 19:07:22 +02:00
Marek Vasut
afb19d65d9 ARM: rmobile: Move HSUSB configuration to board on Salvator-X
In order to use ehci-generic driver, move the configuration of HSUSB
block into the board file. This configuration should not have been in
the Gen3 EHCI USB driver in the first place, so move it to the board
file until there is a proper infrastructure and driver for the HSUSB
block.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-12 19:07:21 +02:00
Marek Vasut
1d871465c4 ARM: rmobile: dts: Add EHCI USB nodes to r8a7796
The R8A7796 EHCI USB nodes are missing from r8a7796 dtsi, add them.
These nodes don't come from mainline Linux, yet the DT binding is
similar enough to R8A7795 which already has those in mainline and
once the nodes hit mainline, this DT should be resynched.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-12 19:07:20 +02:00
Marek Vasut
37a7908137 ARM: dts: rmobile: Update DTS to match Linux 4.13
Import the RCar Gen3 DTS and headers from upstream Linux kernel v4.13,
commit 569dbb88e80deb68974ef6fdd6a13edb9d686261 . This includes both M3
and H3 ULCB and Salvator-X boards.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-12 23:01:51 +02:00
Tom Rini
8a33cb8b6b Merge git://git.denx.de/u-boot-fsl-qoriq 2017-09-12 12:02:50 -04:00
Tom Rini
fa6365b7c7 Travis-CI: Update PATH
We now can no longer re-use the provided path and need to give the
full PATH we want used now.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-12 11:00:53 -04:00
Tom Rini
de2ad2c40d Merge git://git.denx.de/u-boot-dm 2017-09-12 09:32:51 -04:00
Rob Clark
8ef0535250 video: add config option to skip framebuffer clear
The use-case is that the thing that loaded u-boot already put a splash
image on screen.  And we want to preserve that until grub boot menu
takes over.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-09-12 13:40:47 +02:00
Rob Clark
971d7e6424 video: simplefb
Not really qcom specific, but for now qcom/lk is the one firmware that
is (afaiu) setting up the appropriate dt node for pre-configured
display.  Uses the generic simple-framebuffer DT bindings so this should
be useful on other platforms.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-09-12 13:40:47 +02:00
Philippe CORNU
72719d2f8a video: add STM32 LTDC display controller
The STM32 LTDC display controller provides a parallel digital RGB and
signals for horizontal, vertical synchronization, Pixel Clock and Data
Enable as output to interface directly to a variety of LCD and TFT panels.

The LTDC main features are:
- 24-bit RGB Parallel Pixel Output, Programmable timings & polarity for
  HSync, VSync and Data Enable.
- 2 layers with Blending, Color Keying, Window position & size,
  Dithering, Background color, Color Look-Up Table (CLUT).
- Supported layer color formats: ARGB8888, RGB888, RGB565, ARGB1555,
  ARGB4444, L8 CLUT, AL44 & AL88

This LTDC driver:
- supports: RGB parallel output with timings & polarity, 1 layer
  in RGB565.
- supports but with hard-coded configurations: blending, window
  position & size (crop), background color.
- does not support yet: rgb888, argb8888, 8-bit clut, dithering.

This LTDC driver is compatible with all stm32 platforms with the
LTDC IP and has been tested on stm32 f746-disco board.

Signed-off-by: Philippe CORNU <philippe.cornu@st.com>
2017-09-12 13:40:47 +02:00
Patrick Delaunay
5b6a6a91c8 dm: backlight: Add a driver for GPIO backlight
Add a driver for GPIO backlights.
It understands the standard device tree binding.
It can be used with simple-panel when PWM is not necessary.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2017-09-12 13:40:47 +02:00
Patrick Delaunay
08a43cfbc2 dm: backlight: Add CONFIG_BACKLIGHT_PWM
Add a config to select individually the driver for PWM backlights.
Manage "depends on" to be backyard compatible.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2017-09-12 13:40:47 +02:00
Holger Dengler
985fa93e61 cmd: set filesize variable in ubi read
After a successful read of a UBI volume, the variable filesize is set
to the number of read bytes. To boot linux with a raw initramfs/initrd,
you must specify the exact size of the initramfs/initrd image in boot
command. If the initramfs/inird is read from UBI volume, $filesize is
required to access the number of read bytes.

Example:
  ubi read ${loadaddr} kernelvol
  ubi read ${fdtaddr} dtbvol
  ubi read ${initrd_addr} initrdvol
  bootz ${loadaddr} ${initrd_addr}:${filesize} ${fdt_addr}

Signed-off-by: Holger Dengler <dengler@linutronix.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
2017-09-12 10:08:05 +02:00
Patrice Chotard
ee87a097b0 dm: test: replace dm_scan_dt() by of dm_extended_scan_fdt() in dm_do_test
This allows to scan the DT including all "clocks" node's sub-nodes
in which fixed-clock are defined.
All fixed-clock should be defined inside a clocks node which collect all
external oscillators. Until now, all clocks sub-nodes can't be binded except
if the "simple-bus" compatible string is added which is a hack.

Update test.dts by moving clk_fixed node inside clocks.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-11 21:43:58 -06:00
Patrice Chotard
e81c98649b dm: core: add clocks node scan
Currently, all fixed-clock declared in "clocks" node in device tree
can be binded by clk_fixed_rate.c driver only if each of them have
the "simple-bus" compatible string.
This constraint has been invoked here [1].

This patch offers a solution to avoid adding "simple-bus" compatible
string to nodes that are not busses.

[1] https://patchwork.ozlabs.org/patch/558837/

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-11 21:43:58 -06:00
Chris Packham
e11aa602ab patman: add support for omitting bouncing addresses
Add support for reading a list of bouncing addresses from a in-tree file
(doc/bounces) and from the ~/.patman config file. These addresses are
stripped from the Cc list.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com <mailto:philipp.tomsich@theobroma-systems.com>>
2017-09-11 21:43:58 -06:00
Simon Glass
c79d18c4b4 moveconfig: Use fd.write() instead of print >>
Adjust this code so that it can work with Python 2 and 3.

Fixes: d73fcb1 (moveconfig: Support building a simple config database)
Reported-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-09-11 21:43:58 -06:00
Simon Glass
3991f42ed2 dm: core: Add ofnode_for_each_subnode()
Add a convenience macro to iterate over subnodes of a node. Make use of
this where appropriate in the code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-09-11 21:43:58 -06:00
Simon Glass
8639f69a61 genconfig.py: Print defconfig next to warnings
At present we sometimes see warnings of the form:

/tmp/tmpMA89kB:36: warning: overriding the value of CMD_SPL.
	Old value: "y", new value: "y".

This is not very useful as it does not show whch defconfig file it relates
to. Update the tool to show this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-09-11 21:43:58 -06:00
Simon Glass
ee3e520dad dm: core: Show driver name with 'dm tree'
It is often useful to see which driver was actually selected for each
device. Add a new 'Driver' column to provide this information. Sample
output:

 Class       Probed   Driver     Name
----------------------------------------
 root        [ + ]    root_drive root_driver
 keyboard    [ + ]    i8042_kbd  |-- keyboard
 serial      [ + ]    ns16550_se |-- serial
 rtc         [   ]    rtc_mc1468 |-- rtc
 timer       [ + ]    tsc_timer  |-- tsc-timer
 syscon      [ + ]    ich6_pinct |-- pch_pinctrl
 pci         [ + ]    pci_x86    |-- pci
 northbridge [ + ]    bd82x6x_no |   |-- northbridge@0,0
 video       [ + ]    bd82x6x_vi |   |-- gma@2,0
 vidconsole0 [ + ]    vidconsole |   |   `-- gma@2,0.vidconsole0
...

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-11 21:43:58 -06:00
Simon Glass
a0f9acb08b dm: core: Drop use of strlcpy()
We can use printf() to limit the string width. Adjust the code to do this
instead of using strlcpy() which is a bit clumbsy.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-11 21:43:58 -06:00
Bin Meng
226b50bbd8 sandbox: Convert SANDBOX_BITS_PER_LONG to Kconfig
Convert SANDBOX_BITS_PER_LONG to Kconfig and assign it a correct
number depending on which host we are going to build and run.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-11 21:43:58 -06:00
Bin Meng
98cff66027 sandbox: Introduce Kconfig option for 32/64 bit host
It seems most of the time we are building and running sandbox on 64-bit host.
But we do support 32-bit host as well. Introduce Kconfig option for this.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-11 21:43:58 -06:00
Jean-Jacques Hiblot
5fe7702ecc blk: dm: make blk_create_device() take a number of block instead of a size
There is an overflow problem when taking the size instead of the number
of blocks in blk_create_device(). This results in a wrong device size: the
device apparent size is its real size  modulo 4GB.
Using the number of blocks instead of the device size fixes the problem and
is more coherent with the internals of the block layer.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-11 21:43:58 -06:00
Wenyou Yang
d81a1de96e misc: Kconfig: Add SPL_I2C_EEPROM option
This option is an SPL-variant of the I2C_EEPROM option to enable
the driver for generic I2C-attached EEPROMs for SPL.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-11 22:44:30 -04:00
Wenyou Yang
fafa440342 board: sama5d4_xplained: Set mac address from eeprom
Add the code to set the ethernet mac address from eeprom by using
the common code from the common folder.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-11 16:23:08 -04:00
Wenyou Yang
34e2819d31 board: sama5d2_xplained: Replace code to set mac address
Replace the code to set the ethernet mac address with the code from
the common folder.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-11 16:23:07 -04:00
Wenyou Yang
d9b23e26f0 board: atmel: Create board/$(VENDOR)/common folder
Create board/$(VENDOR)/common folder to accommodate the common code
shared by other atmel boards, now put the code to set ethernet mac
address from eeprom, which uses the i2c eeprom driver.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-11 16:23:06 -04:00
Lokesh Vutla
08318317af env: ti: boot: Select dtb name for X15 revC
Select dtb name for am57xx BeagleBoard-X15 revC

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-11 16:23:05 -04:00
Lokesh Vutla
8b2551a4db board: ti: am57xx: Add dt support for BeagleBoard-X15 revC
Add support for selecting proper dtb for
am57xx BeagleBoard X15 revC u-boot from FIT

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-11 16:23:04 -04:00
Steve Kipisz
209742fa88 board: ti: am571x: Add 666MHz support for AM571x IDK
AM571x supports DDR running at 666MHz. Right now it is
clocked at 532MHz which is lower than what is supported.
In order to have maximum performance on AM571-IDK,
switch DDR to 666MHz.

Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-11 16:22:31 -04:00
Lokesh Vutla
fede942980 board: ti: dra76: Add dt support
Add support for selecting proper dtb for
dra76x u-boot from FIT.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-11 16:22:30 -04:00
Lokesh Vutla
b63b995b16 arm: dts: Add u-boot specific compatibles
Separate out u-boot specific compatibles from dts files.
This will help in syncing dts files in future.
Also these will get deleted eventually once respective drivers
are capable of handling Linux dts files.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-11 16:19:49 -04:00
Lokesh Vutla
4ddaa6ce28 arm: dts: dra7: sync DT with latest Linux
Sync all dra7* specific dts files with the upstream
kernel including changes queued for 4.14

https://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git/log/?h=omap-for-v4.14/dt-v3

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-11 16:19:48 -04:00
Lokesh Vutla
911d76c417 env: ti: boot: Select dtb name for dra76
Select dtb name for dra76-evm.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-11 16:19:44 -04:00
Lokesh Vutla
cd43b51600 board: ti: dra76-evm: Add support for powering on mmc ldo
ldo4 is used to poweron mmc on dra76-evm. Enable it.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-11 16:19:43 -04:00
Lokesh Vutla
9120ef079c board: ti: dra76-evm: Add the pinmux data
Adding pinmux and IODELAY data for dra76-evm.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-11 16:19:42 -04:00
Lokesh Vutla
c9a7c17a96 board: ti: dra76-evm: Add DDR data
dra76-evm has the ddr parts connectedi running at 666MHz:
EMIF1: MT41K512M16HA-125 AIT:A  x 2
EMIF2: MT41K512M8RH-125-AAT:E x 4
Add support for configuring the above DDR parts.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-11 16:19:41 -04:00
Keerthy
c247605510 board: ti: dra76-evm: Add the pmic data
dra76-evm uses lp8736 and tps65917 pmic for powering on
various peripherals. Add data for these pmics and register
for dra76-evm.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-11 16:19:40 -04:00
Lokesh Vutla
c8c04eca30 board: ti: dra76-evm: Add epprom support
The dra76-evm is a board based on TI's DRA76 processor
Add eeprom support

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-11 16:19:39 -04:00
Praneeth Bajjuri
0f9e6aee9d arm: dra76: Add support for ES1.0 detection
dra76 family is a high-performance, infotainment application
device, based on OMAP architecture on a 28-nm technology.
This contains most of the subsystems, peripherals that are
available on dra74, dra72 family. This SoC mainly features
Subsystems:
- 2 x Cortex-A15 with max speed of 1.8GHz
- 2 X DSP
- 2 X Cortex-M4 IPU
- ISS
- CAL
- DSS
- VPE
- VIP
Connectivity peripherals:
- 1 USB3.0 and 3 USB2.0 subsystems
- 1 x SATA
- 2 x PCI Express Gen2
- 3-port Gigabit ethernet switch
- 2 x CAN
- MCAN

Adding CPU detection support for the dra76 ES1.0 soc
and update prcm, control module, dplls data.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-11 16:19:38 -04:00
Lokesh Vutla
0537e097c9 arm: dra7: Kconfig: Select LP87565 related configs
LP87565 is present on dra76-evm. Select it for
TARGET_DRA7XX_EVM.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-11 16:19:37 -04:00
Lokesh Vutla
db4fce8fcd palmas: Add support for powering different ldos
It is not necessary that ldo1 is used to power on mmc.
So, add support for passing ldo registers for powering on mmc.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-11 16:19:37 -04:00
Lokesh Vutla
91d3e90668 arm: omap5+: Add board specific ldo powering
It is not necessary all omap5+ based uses the same PMIC
to poweron mmc. So add support for enabling mmc based on board.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-11 16:19:35 -04:00
Tom Rini
bce2629887 Merge branch 'master' of git://git.denx.de/u-boot-video 2017-09-11 15:54:39 -04:00
Tom Rini
c98ac3487e Prepare v2017.09
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-11 14:10:40 -04:00
Jorge Ramirez-Ortiz
bbfbdb5722 MAINTAINERS: board: qcom: db410c: Maintainer changed
Replacing original author Mateusz Kulikowski
<mateusz.kulikowski@gmail.com> as db410c maintainer

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
2017-09-11 13:34:31 -04:00
York Sun
42f43aa258 armv8: fsl-layerscape: Add back L3 flushing for all exception levels
CCN-504 HPF registers were believed to be accessible only from EL3.
However, recent tests proved otherwise. Remove checking for exception
level to re-enable L3 cache flushing for all levels.

Signed-off-by: York Sun <york.sun@nxp.com>
Tested-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-09-11 08:02:13 -07:00
Hou Zhiqiang
4950eb4a48 armv8: ls1088a: Enable PCIe in defconfigs
Enabled PCIe support and PCI command feature.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:07 -07:00
Hou Zhiqiang
4c5c87da7b armv8: ls1088a: add PCIe dts node
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:07 -07:00
Hou Zhiqiang
c4787f4b23 armv8: ls1088a: fix the MMU table for pcie config space
The pcie config space of ls1088a is different from ls2080a.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:07 -07:00
York Sun
e9303a4146 armv8: fsl-layerscape: Fix MC reserved memory calculation
In case high region memory doesn't have enough space for Management
Complex (MC), the return value should indicate a failure so the
caller can handle it accordingly.

Signed-off-by: York Sun <york.sun@nxp.com>
Reported-by: Ebony Zhu <ebony.zhu@nxp.com>
2017-09-11 08:01:07 -07:00
Ran Wang
0e8a4264ec armv7: Add workaround for USB erratum A-009007
Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values

Program register USB_PHY_RX_OVRD_IN_HI in certain sequence
to make the Rx compliance test pass.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.bhagat@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:07 -07:00
Ran Wang
e10d114279 armv7: Add workaround for USB erratum A-008997
Low Frequency Periodic Singaling (LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter settings

Change config of transmitter signal swings by setting register
PCSTXSWINGFULL to 0x47 to pass compliance tests.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:06 -07:00
Ran Wang
c1853f6f73 armv7: Add workaround for USB erratum A-009798
The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receive
Compliance test failure for a 100mV threshold.

Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE
to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:06 -07:00
Ran Wang
83fa71189a armv7: Add workaround for USB erratum A-009008
USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature

Optimal eye at TXREFTUNE value to 0x9 is observed, change
set the same value.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:06 -07:00
Ran Wang
15d59b5316 armv8: Add workaround for USB erratum A-009007
Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values.

Program register USB_PHY_RX_OVRD_IN_HI in certain sequence
to make the Rx compliance test pass.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.bhagat@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:06 -07:00
Ran Wang
9d1cd910f7 armv8: Add workaround for USB erratum A-008997
Low Frequency Periodic Signaling(LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter
settings

Change config of transmitter signal swings by setting register
PCSTXSWINGFULL to 0x47 to pass compliance tests.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:06 -07:00
Ran Wang
2a8a353958 armv8: Add workaround for USB erratum A-009798
The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receiver
Compliance test failure for a 100mV threshold.

Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE
to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:06 -07:00
Ran Wang
2ab1553f08 armv8: Add workaround for USB erratum A-009008
USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature

Optimal eye at TXREFTUNE value to 0x9 is observed, change
set the same value.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:06 -07:00
Ran Wang
9a609a8800 armv8: Add scfg_clrsetbits_32(), scfg_clrbits_32()
Some erratum patch might need it to program registers.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:05 -07:00
Prabhakar Kushwaha
9f244b3587 armv8: ls1088aqds: Add support of EC1 and EC2
EC1 and EC2 are RGMII interface on ls1088aqds platform.
This patch add support of RGMII with PHY and MDIO

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:05 -07:00
Ashish Kumar
17d066fc5d armv8: fsl-layerscape: Support to add RGMII for ls1088aqds
This patch adds support for RGMII protocol

NXP's LDPAA2 support RGMII protocol. LS1088A is the
first Soc supporting both RGMII and SGMII.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:05 -07:00
Ashish Kumar
7769776a60 armv8: ls1088aqds: Add support of LS1088AQDS
This patch add support of LS1088AQDS platform.

The LS1088A QorIQTM Development System (QDS) is a high-performance
computing, evaluation, and development platform that supports the
LS1088A QorIQ Architecture processor.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:05 -07:00
Ashish Kumar
e84a324ba7 armv8: ls1088ardb: Add support for LS1088ARDB platform
LS1088A is an ARMv8 implementation. The LS1088ARDB is an evaluatoin
platform that supports the LS1088A family SoCs. This patch add basic
support of the platform.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Disabled NAND in board header file]
Reviewed-by: York Sun <york.sun@nxp.com>

WIP: disable NAND for LS1088ARDB
2017-09-11 08:00:13 -07:00
Ashish Kumar
6d9b82d085 armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:00:13 -07:00
Suresh Gupta
22c51855bf armv8: fsl-layerscape: Fix final MMU table for QSPI and IFC
For QSPI and IFC addresses execution shouldn't be allowed
when u-boot running from DDR. Revise the MMU final table
to enforce execute-never bits.

Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:00:13 -07:00
Ran Wang
5436c6a347 armv8: fsl: Use correct conditional compile for ls1012a
According current code base, CONFIG_LS1012A should be
CONFIG_ARCH_LS1012A, or function fsl_fdt_disable(blob) will be
wrongly called to disable all dwc3 USB nodes on LS1012A, which
cause Linux USB function stop working at all.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:00:13 -07:00
Priyanka Jain
033c538e56 drivers:net:fsl-mc: Update MC address calculation
Update MC address calculation as per MC design requirement of address
as least significant 512MB address of MC private allocated memory,
i.e. address should point to end address masked with 512MB offset in
private DRAM block.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com>
[YS: reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 07:55:36 -07:00
Ashish Kumar
c055cee195 armv8: fsl-lsch3: Make CCN-504 related code conditional
LS2080 family has CCN-504 cache coherent interconnet. Other SoCs
in LSCH3 family may have differnt interconnect.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[YS: revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 07:55:36 -07:00
York Sun
c8bc3c0c9f spl: fit: Add booting OS first
If CONFIG_SPL_OS_BOOT is enabled, boot OS if kernel image is found
in FIT structure.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-11 07:55:36 -07:00
York Sun
5fd13d9736 spl: fit: Support both external and embedded data
SPL supports U-Boot image in FIT format which has data outside of
FIT structure. This adds support for embedded data for normal FIT
images.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-11 07:55:36 -07:00
York Sun
7264f2928b spl: fit: Eanble GZIP support for image decompression
Add Kconfig option SPL_GZIP and SPL_ZLIB to enable gunzip support for
SPL boot, eg. falcon boot compressed kernel image.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-11 07:55:36 -07:00
York Sun
d1f2ee7021 cmd: spl: Fix compiling warning
Fix warning "cast from pointer to integer of different size".

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-11 07:55:36 -07:00
York Sun
05e35d26db tools: pblimage: Fix address calculation
The image size should be added to the initial pbl command, not bit
"ORed".

Signed-off-by: York Sun <york.sun@nxp.com>
2017-09-11 07:55:36 -07:00
Udit Agarwal
73fbcdf163 armv8: LS2080ARDB: Add secure boot defconfig for QSPI boot.
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
[YS: dropped redundant commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 07:55:36 -07:00
Udit Agarwal
15e7c681e1 LS2080ARDB: QSPI boot: Secure Boot image validation
Adds header address for PPA to be validated during ESBC phase for
ARCH_LS2088 and QSPI_BOOT. Moves sec_init prior to ppa_init(). It
must be initialized before the PPA.

Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
[YS: revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 07:55:36 -07:00
Sumit Garg
06fb06f66c SECURE_BOOT: Unify memory map for Layerscape based platforms
Unify memory map for Layerscape based platforms. This patch includes
changes in bootscript, bootscript header and PPA header addresses
change as per unified memory map.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 07:55:36 -07:00
Zhao Qiang
a7a81756b8 QE: Set QE_IRAM_READY after uploading firmware
QE_IRAM_READY should be set only after successfully uploading the
firmware.

Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 07:55:36 -07:00
Ashish Kumar
63b2316c5c fsl-layerscape: Consolidate registers space defination for CCI-400 bus
CoreLink Cache Coherent Interconnect (CCI) provides full cache
coherency between two clusters of multi-core CPUs and I/O coherency
for devices and I/O masters.

This patch add new config option SYS_FSL_HAS_CCI400 and moves
existing register space definaton of CCI-400 bus to fsl_immap to be
shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET
in Kconfig.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[YS: revised commit message, squashed patches for armv8 and armv7]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 07:55:36 -07:00
Fabio Estevam
c7430d7d5e ipu_common: Let the MX6 IPU clock be calculated in run-time
MX6Q/QP IPU operates at 264MHz and MX6DL IPU at 198MHz.

When running a SPL target, which supports multiple MX6 variants we cannot
properly setup the IPU clock frequency via CONFIG_IPUV3_CLK option as
such decision is done in build-time currently.

Remove the CONFIG_IPUV3_CLK option and let the IPU clock frequency be
configured in run-time on mx6.

Reported-by: Eric Nelson <eric@nelint.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
[agust: fixed #endif in cgtqmx6eval.h]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-09-11 12:46:51 +02:00
Bin Meng
584f316f11 cmd: ide: Make the first device the default one
At present the IDE device number is initialized to -1, which means
we cannot type "ide read" command before setting the device number
via "ide device #".

For convenience, let's set the first device as the default one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-10 12:27:43 -04:00
Bin Meng
1f4adab873 block: ide: Don't bother to create BLK device if no CDROM inserted
When there is no CDROM inserted, the block size is zero hence there
is no need to create a BLK device for it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-10 12:27:40 -04:00
Bin Meng
68e6f221ed block: ide: Fix block read/write with driver model
This converts the IDE driver to driver model so that block read and
write are fully functional.

Fixes: b7c6baef ("x86: Convert MMC to driver model")
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-09-10 12:27:37 -04:00
Bin Meng
eb81b1a4d3 blk: Use macros for block device vendor/product/rev string size
So far these are using magic numbers. Replace them with macros.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-10 12:27:32 -04:00
Tom Rini
4ccceefb7f edison: Disable CONFIG_USB_HOST_ETHER
This board does dwc3 gadget, not host, so we cannot have host support or
we will fail to link.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-08 16:43:24 -04:00
Tom Rini
5eb35220b2 env: Migrate CONFIG_ENV_AES to Kconfig and deprecate
The underlying implementation for ENV_AES has security complications and
is not recommended for use.  Please see CVE-2017-3225 and CVE-2017-3226
for more details.  Mark this as deprecated now and delete this in the
medium term if no one comes forward to re-work the support.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-08 13:12:16 -04:00
Chris Packham
0683fb7242 usb: doc: update README.usb for new config options
A number of the config options for USB networking have been migrated to
Kconfig. Update README.usb to reflect this.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
2017-09-08 10:23:01 -04:00
Chris Packham
f58ad98a62 usb: net: migrate USB Ethernet adapters to Kconfig
This migrates ASIX, ASIX88179, MCS7830, RTL8152 and SMSC95XX to Kconfig.
Update defconfigs.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-08 10:23:00 -04:00
Chris Packham
ae3584498b usb: net: migrate CONFIG_USB_HOST_ETHER to Kconfig
CONFIG_USB_HOST_ETHER is the framework that the drivers are dependent on
USB_HOST_ETHER. Use this as a menu and move the existing LAN75XX and
LAN78XX options under new menu. Finally update the defconfigs that need
CONFIG_USB_HOST_ETHER.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-08 10:21:46 -04:00
Chris Packham
8ffb23cbf5 Kconfig: drop CONFIG_USB_ETHER_RNDIS
This is not a valid option. Drop it.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-08 10:17:17 -04:00
Chris Packham
9272c7b160 Kconfig: drop CONFIG_USB_ETHER_DM9601
This is not a valid option. Drop it.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-08 10:15:47 -04:00
Nobuhiro Iwamatsu
eb3eb6020f README: Fix typo in description of CONFIG_OF_EMBED
The correct name is 'gd->fdt_blob', not 'gd->blob'.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-08 10:15:47 -04:00
Tom Rini
df35f4530b configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-08 10:14:49 -04:00
Kever Yang
0532ceef30 rockchip: enable SPL_SYSRESET config for all Rockchip SoCs
With Makefiles testing for $(SPL_TPL_)SYSRESET, we need SPL_SYSRESET
for do_reset() in SPL for Rockchip SoCs.

References: 87c16d4 "drivers: spl: consistently use the $(SPL_TPL_) macro"
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-08 11:45:19 +02:00
Kever Yang
e1f6881367 rockchip: rk3328: fix syscon id table
syscon id table need a dummy member as NULL ending, or else system
will panic while try to match a compatible in this table as a list.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-08 11:44:51 +02:00
Marek Vasut
25f840d7ef ARM: rmobile: Disable CONFIG_ARCH_FIXUP_FDT_MEMORY
Disable CONFIG_ARCH_FIXUP_FDT_MEMORY to prevent U-Boot from modifying
the memory {} nodes in the DT passed to the Linux kernel. The R8A779x
DT contains multiple memory {} nodes, while U-Boot only modifies the
first one and stuffs all the memory entries into it, which is wrong.
Disabling CONFIG_ARCH_FIXUP_FDT_MEMORY is the least intrusive way to
fix the issue this close to the release, while the real fix is to
extend the fdt_fixup_memory_banks() to handle multiple memory nodes
in DT.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-07 20:04:41 -04:00
Marek Vasut
183f5fd3ca ARM: rmobile: Fix SD divider settings on Gen3
On RCar M3 and on RCar H3 newer than and not including ES1.0, the SD clock
must be divided by 4 rather than 2 because a hardware workaround present
only in the H3 ES1.0 has been removed from these chips. U-Boot currently
only supports M3 and H3 ES 2.0 and newer, so configure the SD pre-divider
to 4 to prevent SD instability.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-07 20:04:40 -04:00
Tom Rini
ec6bc928bb Merge git://git.denx.de/u-boot-net 2017-09-07 14:48:23 -04:00
Heinrich Schuchardt
e4691564cc net: fix typos
%s/Desriptor/Descriptor/g

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-09-07 13:23:52 -05:00
Madalin Bucur
10710b4ec5 armv8: ls1043/ls1046aqds: add support for RGMII_TXID
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: York Sun <york.sun@nxp.com>
2017-09-07 13:23:52 -05:00
Tom Rini
0b1e580672 net: nfs: Drop CONFIG_NFS_READ_SIZE
In the general case, CONFIG_NFS_READ_SIZE is unchanged from the default
of 1024.  There are in fact no in-tree users that increase this size.
Adjust the comment to reflect what could be done in the future in
conjunction with CONFIG_IP_DEFRAG.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-09-07 13:23:52 -05:00
Madalin Bucur
05b29aa0cb net: phy: realtek: fix enabling of the TX-delay for RTL8211F
The old logic always enabled the TX-delay when the phy-mode was set to
PHY_INTERFACE_MODE_RGMII. With this patch we enable the TX delay for
PHY_INTERFACE_MODE_RGMII_ID and PHY_INTERFACE_MODE_RGMII_TXID and
disable it for PHY_INTERFACE_MODE_RGMII.

Based on a similar change made in the Linux Realtek PHY driver
by Martin Blumenstingl <martin.blumenstingl@googlemail.com>.

Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: York Sun <york.sun@nxp.com>
2017-09-07 13:23:52 -05:00
Kever Yang
b5b82abcf5 spl: typo fix for SPL_ATF_SUPPORT description
Delete one redundant 'which' for SPL_ATF_SUPPORT description.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2017-09-07 10:44:38 -04:00
Heinrich Schuchardt
d72fd7b340 linker_lists: remove incorrect comment
Remove a comment line refering to a non-existent file.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-09-07 10:44:37 -04:00
Heinrich Schuchardt
de2de3192f vsprintf: vsprintf does not have parameter size
The inline documentation of vsprintf mentions a parameter size
which does not exist in the function declaration.

int vsprintf(char *buf, const char *fmt, va_list args);

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-09-07 10:44:37 -04:00
Paul Barker
2d0cf3b2ae Revert "dm: arm: rpi: Drop CONFIG_OF_EMBED"
This reverts commit 25877d4e4c.

This is a workaround for Raspberry Pi boot failures seen when passing on
the device tree provided by the Raspberry Pi firmware at boot. Without
CONFIG_OF_EMBED, we just get stuck at "Starting kernel ..." when we try
to boot Linux with this device tree.

Signed-off-by: Paul Barker <pbarker@toganlabs.com>
Cc: Simon Glass <sjg@chromium.org>
Tested-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-07 10:44:36 -04:00
Bin Meng
eab44c93eb tools: .gitignore: Add libfdt related files
Some files are generated during libfdt build. Ignore them.

This was wrongly put in the .gitignore in the root directory before.
Now let's remove entries there and put them in the right place.

Fixes: 34e2c285 ("gitignore: add intermediates from libfdt build")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-07 10:44:35 -04:00
Bin Meng
d11d3b2fa6 tools: .gitignore: Sort in alphabetical order
These are currently out of alphabetical order.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-07 10:44:34 -04:00
Alison Chaiken
2105f34843 doc: remove duplicate text in README.gpt
Signed-off-by: Alison Chaiken <alison@she-devel.com>
2017-09-07 10:44:34 -04:00
Bin Meng
337e3b897d part: mac: Suppress the error message after reading ddb
Change to use 'debug' to output the error message if it fails to
read the driver descriptor block.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-07 10:44:33 -04:00
Simon Glass
84a42069f2 env: Add 'envtools' target to 'make help'
The target is not currently mentioned anywhere. Add it to the help so
people can find it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-09-05 20:34:09 -04:00
Simon Glass
5733295714 env: Fix operation of 'make environ'
This was broken by the recent environment refactoring. Specifically:

$  make environ
scripts/Makefile.build:59: tools/environ/Makefile: No such file or directory
make[1]: *** No rule to make target 'tools/environ/Makefile'.  Stop.
make: *** [Makefile:1469: environ] Error 2

Fix this by updating the Makefile and adjusting the #include filesnames in
two C files.

Fixes: ec74f5f (Makefile: Rename 'env' target to 'environ')
Reported-by: Måns Rullgård <mans@mansr.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-09-05 20:34:08 -04:00
Sam Protsenko
de4e4edaff usb: gadget: g_dnl: Sync internal SN variable with env
Since commit 842778a091 ("usb: gadget: g_dnl: only set iSerialNumber
if we have a serial#") "fastboot devices" stopped to show correct device
serial number for TI boards, showing this line instead:

    ????????????	fastboot

This is because serial# env variable could be set after g_dnl gadget was
initialized (e.g. by using env_set() in the board file).

To fix this, let's update internal serial number variable (g_dnl_serial)
when "serial#" env var is changed.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Cc: Felipe Balbi <felipe.balbi@linux.intel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Acked-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
2017-09-05 20:17:08 -04:00
Tom Rini
2d3229bea2 env: Fix out of tree building of tools-all
With the move of environment code from common/ to env/ a number of
changes needed to be made to various make targets.  We missed updating
some of the files required for out of tree builds of the tools.  Correct
the 'environ' target to know that we need to work under tools/env/ still
(not tools/environ/) and then update the wrappers in env_attr.c and
env_flags.c to point to the new correct file.

Reported-by: Peter Robinson <pbrobinson@gmail.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-05 15:59:47 -04:00
Tom Rini
8dcb6f1f81 Merge git://git.denx.de/u-boot-video 2017-09-05 08:54:55 -04:00
Tom Rini
08d0c53d6b Merge git://git.denx.de/u-boot-rockchip 2017-09-05 07:11:46 -04:00
Anatolij Gustschin
c967fb78e4 MAINTAINERS: add lcd files to video section
LCD drivers are video related, so add them to video section.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-09-05 11:17:31 +02:00
Wadim Egorov
5deaa53028 rockchip: i2c: fix >32 byte reads
The hw can read up to 32 bytes at a time. If we need
more than one chunk, we have to enter the plain RX mode.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-05 11:13:36 +02:00
Kever Yang
313bbcf0ea rockchip: firefly-rk3399: enable ATF and dwmmc
enable the ATF option and SDCard in defconfig.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-05 11:04:35 +02:00
Philipp Tomsich
5798d503fc rockchip: timer: fix U_BOOT_DRIVER name
When I originally added this driver, I did some careless (and in
retrospect: mindless) copy & paste for the U_BOOT_DRIVER structure
skeletion... unfortunately, the 'arc_timer' string was committed
and slipped through all reviews.

This fixes the U_BOOT_DRIVER name to read 'rockchip_rk3368_timer'
(as originally intended).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reported-by: Artturi Alm <artturi.alm@gmail.com>
2017-09-05 11:04:35 +02:00
Wadim Egorov
40d4f79b81 rockchip: rk3288: Add reset reason detection
Sometimes it's helpful to know the reset reason caused in the SoC.
Add reset reason detection for the RK3288 SoC.
This will set an environment variable which represents the reset reason.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-05 11:04:35 +02:00
Wadim Egorov
32191a3912 rockchip: phycore: Read configuration EEPROM & set ethaddr in late init
Read SoM information from EEPROM and set ethaddr in late init.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-05 11:04:34 +02:00
Tom Rini
a0e80c97c9 Merge branch 'rmobile' of git://git.denx.de/u-boot-sh 2017-09-04 22:17:59 -04:00
Marek Vasut
0d0915bef7 ARM: rmobile: Add missing IPSR18 bits to R8A7795 PFC
The IPSR18 register bits were missing from the R8A7795 ES2.0+ PFC
tables, which triggered a BUG() in sh_pfc driver. This is because
of an out-of-bounds access to the pinmux_gpios[] array in the PFC
tables, which was too short due to the missing IPSR18 bits.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-05 07:51:39 +09:00
Marek Vasut
8212f56347 ARM: rmobile: Drop board_mmc_init
The board_mmc_init() is no longer invoked when DM is used, so move
all the pinmux config into board_init() instead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-05 07:51:39 +09:00
Marek Vasut
3158b6f606 ARM: rmobile: Replace CONFIG_RAVB with CONFIG_RENESAS_RAVB in boards
The configuration option name is the later, so replace usage of
CONFIG_RAVB in board files with CONFIG_RENESAS_RAVB , otherwise
the RAVB pinmux is not set and ethernet does not work.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-05 07:51:39 +09:00
Niko Mauno
a7126edcb3 splash_source: Verify FIT magic
Before reading entire FIT image, add sanity check by testing image
header against FDT_MAGIC. This should help avoid problems in situations
where FIT is not yet available from storage device, for example when
performing initial programming of device.

Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: Tomas Melin <tomas.melin@vaisala.com>
2017-09-04 23:53:47 +02:00
Anatolij Gustschin
f8ba7f2774 video: ipuv3_fb: skip IPU shutdown if IPU was not enabled before
Boards can skip display interface init using board_video_skip().
If display interface was not initialized (e.g. no ipuv3 framebuffer
registered or IPU clock disabled), booting Linux stops due to the
crash in IPU shutdown function, when accessing IPU registers.
Check IPU clock and skip shutdown if clock is not enabled.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-09-04 23:33:45 +02:00
Tom Rini
ced0fd938d Merge git://git.denx.de/u-boot-dm 2017-09-04 14:56:45 -04:00
Tom Rini
0e88cdd17d Prepare v2017.09-rc4
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-04 09:02:48 -04:00
Clemens Gruber
4c2cf973aa crypto/fsl: fix obj-yy in Makefile
When enabling CONFIG_CMD_BLOB and/or CONFIG_CMD_DEKBLOB, the build fails
with a linker error:
  ...
  LD      u-boot
arch/arm/mach-imx/built-in.o: In function `blob_encap_dek':
/home/clemens/dev/u-boot/arch/arm/mach-imx/cmd_dek.c:46: undefined
reference to `blob_dek'

This is due to an error in the Makefile, resulting in obj-yy/obj-yn/..
and fsl_blob.o is therefore not linked.

Fix it by splitting it up into two obj-y lines.

Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-09-04 09:02:07 -04:00
Lukasz Majewski
4b51a89170 git: mailrc: Update e-mail address
Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-09-04 09:02:06 -04:00
Simon Glass
d944bf6b5e dm: core: Add livetree documentation
Add some documentation for the live device tree support in U-Boot. This
was missing from the initial series.

Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
2017-09-04 02:10:06 -06:00
Philipp Tomsich
34e2c285da gitignore: add intermediates from libfdt build
Since ee95d10 (fdt: Build the new python libfdt module), a number of
additional files are auto-generated/installed into the tools directory.
List these in .gitignore to suppress having them listed as untracked.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
References: ee95d10 (fdt: Build the new python libfdt module)
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-04 02:10:06 -06:00
Hannes Schmelzer
cee8c35d1b fdt: fix 'prop (...) not found!' error in 'fdt set' command
This commit brings things back to the well known working state of the
command.
-
With commit 9620d87259
(cmd/fdt: support single value replacement within an array)

there was an error introduced modifying (inserting) a property to a
device-tree node.
fdt_getprop(...) returnes a len with -1 for a non-existing property, but
a memcpy with len -1 isn't a good idea and things went wrong (crash).
-
Some times later Tom did repair this
with commit 99bb38e2cc
(fdt: Check for NULL return from fdt_getprop in 'fdt set')

This repairs the crash but the behaviour of the command isn't like
before, it makes it impossible to insert a property.
-

Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Acked-by: Simon Glass <sjg@chromium.org>
2017-09-04 02:10:06 -06:00
Simon Glass
302466d07f dm: Add migration plan for CONFIG_BLK
The CONFIG_BLK conversion involves quite invasive changes in the U-Boot
code, with #ifdefs and different code paths. We should try to move over to
this soon so we can drop the old code.

Set a deadline of 9 months for this work, rounded up to the next release.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-04 02:10:06 -06:00
Bin Meng
6935aec0e3 Makefile: Suppress output of python libfdt build command
This should not be printed by default. Prefix it with $(Q).

Fixes ee95d10b: ("fdt: Build the new python libfdt module")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-03 15:30:37 -04:00
Bin Meng
a5ab5c771b Makefile: Quiesce libfdt build
Since commit 3809e302 "Makefile: honor PYTHON configuration properly",
the build commands of libfdt are printed while previously were not.

This adds the missing '--quiet' back.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-03 15:30:36 -04:00
Derald D. Woods
c257c96d9b omap3: evm: Fixes for CONFIG_NAND, SPL_OS_BOOT, USB, and environment
- Pass MTDPARTS kernel arguments to kernel
- Use Kconfig CONFIG_NAND instead of CONFIG_SYS_EXTRA_OPTIONS="NAND"
- Call 'usb_stop' on kernel start
- Update Falcon mode setup to match other OMAP3 boards
- Use "uEnv.txt" as boot script instead of "boot.scr"
2017-09-03 15:30:36 -04:00
Bin Meng
2c3b68081a block: Drop the ftide020 driver
This is not used in U-Boot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-03 15:30:35 -04:00
Bin Meng
caa8bfbc45 block: ide: Drop CONFIG_IDE_LED
This is actually not used. Drop it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-03 15:30:35 -04:00
Bin Meng
f1823d3aaa block: ide: Drop CONFIG_IDE_INIT_POSTRESET
This is not referenced anywhere. Drop it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-03 15:30:34 -04:00
Bin Meng
9e18eae276 nvme: Remove dead codes in nvme_setup_io_queues()
Execution cannot reach this statement: "nr_io_queues = result;"

Reported-by: Coverity (CID: 166731)
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 15:30:34 -04:00
Bin Meng
52a5690efb nvme: Fix potential sign extension issue in nvme_blk_rw()
"lbas" with type "u16" (16 bits, unsigned) is promoted in
"lbas << ns->lba_shift" to type "int" (32 bits, signed), then
sign-extended to type "unsigned long long" (64 bits, unsigned).
If "lbas << ns->lba_shift" is greater than 0x7FFFFFFF, the upper
bits of the result will all be 1.

Fix it by casting "lbas" to "u32".

Reported-by: Coverity (CID: 166730)
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 15:30:33 -04:00
Bin Meng
37d46870b3 nvme: Fix wrong ndev->queues memset
memset() was given a sizeof(NVME_Q_NUM * sizeof(struct nvme_queue *)
to clear, which is wrong.

Reported-by: Coverity (CID: 166729)
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 15:30:32 -04:00
Heinrich Schuchardt
5eae466ea1 disk: part: fix typo
%s/Desriptor/Descriptor/g

Fix lines over 80 characters with said typo.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-09-03 15:30:32 -04:00
Lukasz Majewski
40fe89c6e8 fix: fw_env: Prevent writing error message on special files, which don't support fsync
According to fsync specification [1] some special files (e.g., a pipe, FIFO,
or socket) don't support synchronization and return either EROFS or EINVAL.

On the linux side the sys_fsync -> do_fsync() checks if the requested file
has f_op->fsync defined. If not it returns EINVAL [2].

This commit prevents writing error messages for files (devices), which
do not support fsync().

[1] - http://man7.org/linux/man-pages/man2/fsync.2.html
[2] - http://elixir.free-electrons.com/linux/v4.13-rc6/source/fs/sync.c#L183

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Michael Heimpold <mhei@heimpold.de>
2017-09-03 15:30:31 -04:00
Jonathan Gray
8f1603bd78 bch: don't use __BSD_VISIBLE to test for fls
Commit 4ecc988301 assumes fls is in libc
if __BSD_VISIBLE is defined.  This appears to only be true on FreeBSD
and DragonFlyBSD.  OpenBSD defines __BSD_VISIBLE and does not have fls
in strings.h/libc.

Switch the test for __BSD_VISIBLE to one for __DragonFly__ and
__FreeBSD__ to unbreak the build on OpenBSD.

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
2017-09-03 15:30:31 -04:00
Thomas Petazzoni
e090579d0a include/configs: remove numerous CONFIG_SYS_BARGSIZE definitions
This commit removes definitions of CONFIG_SYS_BARGSIZE defined to be
equal to CONFIG_SYS_CBSIZE in numerous configuration files.

We remove such definitions in two situations:

 - CONFIG_SYS_CBSIZE is otherwise not defined in the board
   configuration file, which means the default value of
   CONFIG_SYS_CBSIZE == 256 applies. In this case, the default value
   of CONFIG_SYS_BARGSIZE == 512 (common/image.c) is suitable, as it is
   larger.

 - CONFIG_SYS_CBSIZE is defined in the board configuration file, but
   to a value equal or less than 512. In this case, the default value
   of CONFIG_SYS_BARGSIZE == 512 (common.image.c) is suitable, as it
   is equal or larger.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 15:30:30 -04:00
Thomas Petazzoni
8a7507a8a3 include/configs: remove default values of CONFIG_SYS_BARGSIZE
CONFIG_SYS_BARGSIZE is already defined to 512 in common/image.c when
not defined. Therefore, there is no point in having board
configuration files define it to 512.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 15:30:30 -04:00
Thomas Petazzoni
1f20fc53b3 include/configs: drop default definitions of CONFIG_SYS_MAXARGS
Now that include/config_fallbacks.h define a sane fallback for
CONFIG_SYS_MAXARGS, we can drop the definition of this constant in all
configurations that were using the default value.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 15:30:29 -04:00
Thomas Petazzoni
bb939d7a6d include/config_fallbacks.h: add default for CONFIG_SYS_MAXARGS
CONFIG_SYS_MAXARGS contains the maximum number of arguments accepted
by U-Boot commands. Since the vast majority of the platforms define it
to 16, it makes sense to have a default definition to 16, which will
allow to remove this definition from a significant number of
platforms.

It will allow to remove the default definition from 216 platform .h
files, leaving only 56 platforms with non-default values (15, 24, 32,
48, 64, 96, 128 or 256).

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 15:30:29 -04:00
Thomas Petazzoni
432e398068 include/configs: drop default definitions of CONFIG_SYS_PBSIZE
Now that the fallback value of CONFIG_SYS_PBSIZE in
include/config_fallbacks.h has been adjusted, remove its definition
from a large number of board configuration files.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 15:30:28 -04:00
Thomas Petazzoni
80c914f1bb include/config_fallbacks.h: change fallback for CONFIG_SYS_PBSIZE
Most of the platforms are using CONFIG_SYS_CBSIZE +
sizeof(CONFIG_SYS_PROMPT) + 16 as their value for CONFIG_SYS_PBSIZE,
so let's adopt this for the fallback value of CONFIG_SYS_PBSIZE.

This will allow us to drop an explicit definition of CONFIG_SYS_PBSIZE
from a large number of platforms.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 15:30:27 -04:00
Thomas Petazzoni
3784c789e7 include/configs: remove CONFIG_SYS_CBSIZE when the default value is used
Now that include/config_fallbacks.h define a sane fallback for
CONFIG_SYS_CBSIZE, we can drop the definition of this constant in all
configurations that were using the default value.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Drop <config.h> from stih410-b2260.h]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-03 15:30:06 -04:00
Thomas Petazzoni
72f09606d8 include/config_fallbacks.h: add default for CONFIG_SYS_CBSIZE
CONFIG_SYS_CBSIZE contains the buffer size for input for the
console. The vast majority of platforms define them to some reasonable
value (256, 512 or 1024 bytes), and it is quite annoying to repeat
this definition for all platforms while it isn't really HW-related.

Therefore, let's provide a sane fallback value in config_fallbacks.h,
so that platforms can rely on it instead of having to explicitly
define it.

We use 1024 when KGDB is enabled, and 256 otherwise, which is what the
majority of the platforms are doing.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 11:04:52 -04:00
Maxime Ripard
79c5912e8d part: efi: Disable overlap check
The current code checks that no partitions overlap with the GPT partition
table using the offset of the first LBA usable for that partition.

This works fine, unless you have a partition entry that is further away
than it usually is and you want to create partitions in the gap between the
GPT header and the GPT partition entries, for example to reflash a
bootloader that needs to be set there.

Rework the test to something a bit smarter that checks whether a partition
would overlap with either the GPT header or the partition entries, no
matter where it is on the disk.

Partitions that do not have a start LBA specified will still start at the
first LBA usable set in the GPT header, to avoid weird behaviours.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 11:04:51 -04:00
Maxime Ripard
47d7ee47ba part: efi: make gpt_fill_pte take the device descriptor
The gpt_fill_pte will need to access the device block size. Let's pass the
device descriptor as an argument.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 11:04:51 -04:00
Maxime Ripard
5276e8b62d part: efi: rework the partition start and size in gpt_fill_pte
The start variable is only used inside a loop, and is never affected inside
it, so it's a purely local variable.

In the same way the partition size is accessed several times, so we can
store it in a variable.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-03 11:04:48 -04:00
Maxime Ripard
89d33a2c0d part: efi: Fix offset
Both the config option and the DT options specify the offset to set the GPT
at in bytes, yet the code treats those values as block numbers.

Fix that.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-03 11:04:47 -04:00
Tom Rini
41a85fe3b9 Merge git://git.denx.de/u-boot-x86 2017-09-02 20:50:59 -04:00
Adam Ford
e3f24d4f2c Kconfig: Add EEPROM options to Kconfig when I2C_EEPROM is set
Add the following options to drivers/misc/Kconfig:
	SYS_I2C_EEPROM_ADDR
	SYS_I2C_EEPROM_BUS
	SYS_EEPROM_SIZE
	SYS_EEPROM_PAGE_WRITE_BITS
	SYS_EEPROM_PAGE_WRITE_DELAY_MS
	SYS_I2C_EEPROM_ADDR_LEN
	SYS_I2C_EEPROM_ADDR_OVERFLOW

This does not migrate any boards, but provides a foundations for
those who want/need these options

Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Migrate uniphier]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-02 15:50:30 -04:00
Stefan Roese
f04034cba4 x86: theadorable-x86-common: Remove "ip=dhcp" from default environment
Without ethernet cable plugged, "ip=dhcp" leads to a complete hangup in
Linux booting and the system does not boot into userland at all. Since
its not required to have an active network connection on these board,
lets remove this statement from the default environment.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-02 23:49:34 +08:00
Bin Meng
3fe6e6e2aa x86: baytrail: acpi: Add full reset bit to the reset register value in FADT
It was noticed a few times, that the reboot from Linux (reboot command)
is different from the reboot (reset command) under U-Boot. The U-Boot
version does seem to reset the board more deeply (PCI cards etc) than
the Linux reboot.

This is actually caused by missing full reset bit in the reset register
value in the ACPI FADT table.

Reported-by: Stefan Roese <sr@denx.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
2017-09-02 23:35:55 +08:00
Bin Meng
d2ca80c3d7 x86: ich-spi: Clear atomic preop only when SPI settings are not locked
The atomic preop register can only be written when SPI settings are
not locked, otherwise it's read-only.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-09-02 23:35:55 +08:00
Bin Meng
52dd56ba84 x86: ich-spi: Remove useless assignment in ich_spi_xfer()
In ich_spi_xfer() when the driver presets control fields, control
variable gets assigned twice. Apparently only the last assignment
takes effect. Remove the other one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-09-02 23:35:55 +08:00
Adam Ford
db35573a71 omap3_logic: Move CONFIG_SYS_NAND_U_BOOT_OFFS to Kconfig
Manually enable SYS_NAND_U_BOOT_LOCATIONS.
Set CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 and remove it from header

Signed-off-by: Adam Ford <aford173@gmail.com>
2017-09-02 10:45:24 -04:00
Adam Ford
6ef2f90108 Convert CONFIG_BCH to Kconfig
This converts the following to Kconfig:
   CONFIG_BCH

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-01 20:45:26 -04:00
Adam Ford
edd1653f04 Convert CONFIG_SPL_OMAP3_ID_NAND to Kconfig
This converts the following to Kconfig:
   CONFIG_SPL_OMAP3_ID_NAND

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-01 20:45:26 -04:00
Adam Ford
fc760cc6e8 Convert CONFIG_SYS_I2C_BUS_MAX to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_I2C_BUS_MAX

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
[trini: Fix AM43XX drop AM44XX]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-01 20:44:30 -04:00
Adam Ford
ac1d8ac871 Configs: Migrate I2C_BUS_MAX to CONFIG_SYS_I2C_BUS_MAX
For consistency with other platforms and in preparation of Kconfig
migration, let's change Several TI platforms that use I2C_BUS_MAX
to CONFIG_SYS_I2C_BUS_MAX

Signed-off-by: Adam Ford <aford173@gmail.com>
2017-09-01 17:56:20 -04:00
Tom Rini
48f6232e58 Kconfig: Migrate all of cmd/fastboot/Kconfig to defconfigs
- Move ANDROID_IMAGE_SUPPORT to top level Kconfig under images as it's
  not strictly part of fastboot.
- Add some defaults for the fastboot buffer location and size
- Migrate all options listed in cmd/fastboot/Kconfig
- Cleanup the README

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-01 16:18:21 -04:00
Tom Rini
ecad7051b0 configs: Migrate all of the existing USB symbols, except fastboot
This syncs all of the currently Kconfig'd symbols out of the headers and
into the defconfig files.  This has two exceptions, first am335x_evm
needs to be converted to DM in SPL and then it can stop undef'ing
CONFIG_DM_USB.  Leaving this as-is results in a build failure, and
without work, run time failure.  The other case is am43xx_evm.h and in
turn am43xx_evm_usbhost_boot.  The problem here is that we need DWC3 USB
host mode in SPL, but still desire to have gadget mode in U-Boot proper.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-01 16:18:20 -04:00
Tom Rini
9493d05a41 Revert "Merge git://git.denx.de/u-boot-video"
This reverts commit 1d20170467, reversing
changes made to 6aee2ab68c.

The mxc_ipuv3_fb.c changes introduce build failures on some targets.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-01 16:17:17 -04:00
Tom Rini
0b6e5b2c48 Merge git://git.denx.de/u-boot-sunxi 2017-09-01 13:30:19 -04:00
Tom Rini
1d20170467 Merge git://git.denx.de/u-boot-video 2017-09-01 12:57:03 -04:00
Dave Prue
6ff005cf19 sunxi: Fix CONFIG_SUNXI_GMAC references
SUNXI_GMAC was still used to configure the code where as the
same has been renamed and moved to Kconfig in below commit
"sunxi: Move SUNXI_GMAC to Kconfig"
(sha1: 4d43d065db)

Signed-off-by: Dave Prue <dave@prue.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Tested-by: Mark Kettenis <kettenis@openbsd.org>
[Tweek commit message, config_whitelist.txt, build-whitelist.sh]
Signed-off-by: Jagan Teki <jagan@openedev.com>
2017-09-01 20:48:27 +05:30
Tom Rini
6aee2ab68c Merge git://git.denx.de/u-boot-imx
Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	configs/imx6qdl_icore_mmc_defconfig
	configs/imx6qdl_icore_rqs_defconfig
2017-09-01 10:40:59 -04:00
Tom Rini
4109d70293 Merge git://git.denx.de/u-boot-marvell 2017-09-01 10:33:21 -04:00
Tom Rini
e4adc8ed3c Merge git://git.denx.de/u-boot-uniphier
- add {ofnode,dev}_read_resource_byname
- provide DT probe hook to Denali NAND driver
- update clk/reset driver
- update DT
- misc cleanups
2017-09-01 10:32:35 -04:00
Tom Rini
9ec61dbc80 Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2017-09-01 10:31:07 -04:00
Chen-Yu Tsai
8a647fc3ca mmc: sunxi: Only update timing mode bit when enabling new timing mode
When enabling the new mmc timing mode, we inadvertently clear all the
remaining bits in the new timing mode register. The bits cleared
include a default phase delay on the output clock. The BSP kernel
states that the default values are supposed to be used. Clearing them
results in decreased performance or transfer errors on some boards.

Fixes: de9b1771c3 ("mmc: sunxi: Support new mode")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-09-01 19:49:47 +05:30
Jagan Teki
63af4b0ad0 i.MX6Q: icorem6: Add falcon mode
Add Falcon mode support in Engicam i.CoreM6 board.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-08-30 12:18:41 +02:00
Jagan Teki
46668df5d0 i.MX6Q: spl: Fix falcon to use dram_init_banksize
Memory dt node update introduced by spl_fixup_fdt() in below
commit was making DDR configuration in-appropriate
to boot falcon mode. Hence added dram_init_banksize for
explicit assignment of  proper base and size of DDR.

"boot: fdt: Perform arch_fixup_fdt() on the given device tree for falcon boot"
(sha1: 6e7585bb64)

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-08-30 12:18:26 +02:00
Stefan Agner
624da53ca8 imx: remove SATA boot mode for i.MX 6UL and 6ULL
The NXP i.MX 6UL and 6ULL do not support SATA and have no SATA
boot mode, hence remove it from the boot device detecion. This
fixes a build error introduced with 3bd1642d4d ("imx: fix USB
boot mode detection for i.MX 6UL and 6ULL")

Fixes: 3bd1642d4d ("imx: fix USB boot mode detection for i.MX 6UL and 6ULL")
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-30 12:17:53 +02:00
Chris Packham
dbc3e64fd1 ARM: mvebu: add "spi-flash" compatible string
U-boots spi-nor support is currently considered a work in progress. For
now to avoid issues it is necessary to add a "spi-flash" compatible
string. Eventually the "jedec,spi-nor" will be sufficient when the core
U-boot code is updated to support it.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-30 10:03:35 +02:00
Masahiro Yamada
0cc0c544bc ARM: uniphier: enable Denali NAND driver for 64bit SoCs
Now the entry to the NAND driver init can be is controlled by DT;
it should not hurt to compile the driver all the time.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Masahiro Yamada
d8a10e7fac ARM: uniphier: set system bus pinmux for PXs3
The system bus is not enabled by default for NAND, eMMC boot
etc. of PXs3.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Masahiro Yamada
b173c19663 ARM: uniphier: move CONFIG_NAND to defconfig
This imply was added when the option was moved by the moveconfig tool,
but the intention is not clear.  Move it to defconfig.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Masahiro Yamada
31c86aa7fd ARM: dts: uniphier: update PXs3 SoC/board DT
Support PXs3 SoC and its reference development board.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Masahiro Yamada
6c9e46efae ARM: dts: uniphier: sync with Linux
Import updates queued up for Linux 4.14-rc1.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Masahiro Yamada
111689e744 reset: uniphier: add PXs3 support
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Masahiro Yamada
1fc84d6be2 reset: uniphier: fix compatible for SD reset node for LD11/LD20
LD20 has SD ctrl instead of MIO ctrl.  LD11 has both of them.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Masahiro Yamada
d7505752bb clk: uniphier: add System clock support
Support system clocks for LD4, Pro4, sLD8, Pro5, PXs2/LD6b, LD11, LD20.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Dai Okamura
4013bbb1f3 ARM: uniphier: fix DSPLL init code for LD20 SoC
Signed-off-by: Dai Okamura <okamura.dai@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Masahiro Yamada
e0daca7de5 ARM: uniphier: remove ad-hoc pin settings for NAND
This is now set up by the pinctrl driver when the NAND driver is
probed.  Remove the legacy code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:06:57 +09:00
Masahiro Yamada
e2f87de0f8 ARM: uniphier: enable CONFIG_NAND_DENALI_DT
Migrate to the DT-based NAND init entry.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:03:11 +09:00
Masahiro Yamada
8de11a5eef ARM: uniphier: remove unneeded NAND config options
CONFIG_NAND_DENALI select's CONFIG_SYS_NAND_SELF_INIT, so the
NAND initialization process is driven by the driver itself.
CONFIG_SYS_NAND_MAX_CHIPS and CONFIG_SYS_NAND_BASE are unused.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:03:11 +09:00
Masahiro Yamada
4914a68de7 ARM: uniphier: add PLL settings for PXs3
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:03:11 +09:00
Masahiro Yamada
a55957b9ad ARM: uniphier: move PLLCTRL register macros to each SoC .c file
The new SoC PXs3 changed the address of PLL, but still uses the
same PLL name.  We can not define SC_*PLLCTRL in the common header.
Move them to per-SoC .c file.  Also, fix some PLL comments.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:03:11 +09:00
Masahiro Yamada
546197b986 ARM: uniphier: replace <common.h> with <linux/delay.h> in pll settings
The #include <common.h> was added for mdelay().  Later, the declaration
of mdelay was moved to <linux/delay.h> by commit 5bc516ed66 ("delay:
collect {m, n, u}delay declarations to include/linux/delay.h").

There is no need to include <common.h> now.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:03:11 +09:00
Masahiro Yamada
1d9654dc43 mtd: nand: denali_dt: add a DT driver
A patch for NAND uclass support was proposed about half a year ago:
https://patchwork.ozlabs.org/patch/722282/

It was not merged and I do not see on-going work for this.

Without DM-based probing, we need to set up pinctrl etc. in an ad-hoc
way and give lots of crappy CONFIG options for base addresses and
properties, which are supposed to be specified by DT.  This is painful.

This commit just provides a probe hook to retrieve "reg" from DT and
allocate private data in a DM manner.  This DT driver is not essentially
a NAND driver, in fact it is (ab)using UCLASS_MISC.  Once UCLASS_NAND is
supported, it would be possible to migrate to it.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:03:11 +09:00
Masahiro Yamada
7b8b47bd29 ofnode: add {ofnode, dev}_read_resource_byname()
Linux supports platform_get_resource_byname() to look up a resource
by name.

We want a similar helper.  It is useful when a device node has named
register regions.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-29 23:56:17 +09:00
Anatolij Gustschin
0d1ae97c02 video: ipuv3_fb: skip IPU shutdown if IPU was not enabled before
Boards can skip display interface init using board_video_skip().
If display interface was not initialized (e.g. no ipuv3 framebuffer
registered or IPU clock disabled), booting Linux stops due to the
crash in IPU shutdown function, when accessing IPU registers.
Check IPU clock and skip shutdown if clock is not enabled.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-08-29 15:23:55 +02:00
Jagan Teki
a2b137b38d icorem6: Fix to find MMC devices
U-Boot proper is using DM_MMC so, enable CONFIG_BLK otherwise
find_mmc_device failed to detect MMC device.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-08-29 09:50:40 +02:00
Anatolij Gustschin
ffc36f57bc imx6: don't include unneeded boot_mode array in SPL
The soc_boot_modes array is only used by bmode command
and not needed in SPL. Don't include it into SPL.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-08-29 09:49:51 +02:00
Anatolij Gustschin
f9d42d821c spl: do not repeat timer init on i.MX6
The GPT timer was already initialised in board_init_f() as
it is needed in dram init. Do not repeat timer init in
board_init_r().

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2017-08-29 09:48:37 +02:00
Anatolij Gustschin
ae64226dbe imx: timer: don't clear the GPT control register multiple times
There is no need to clear the control register 100 times in a
loop, a single zero write clears the register. I didn't find any
justification why clearing this register in a loop is needed
(no info in i.MX6 errata or GPT timer linux driver, linux driver
uses single write to clear this control register).

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2017-08-29 09:47:28 +02:00
Stefano Babic
cb40adff8f pfla02: Fix RAM detection and support 1 bank SOM
In case of 2 banks, the address space of the first CS must be defined
and not let to the higher value.

Add support for SOM with a single bank of RAM. It was tested with i.MX6Q
modules in the following configurations:

- 2 Banks, 4 GB
- 2 Banks, 1 GB
- 1 Bank,  1 GB

Signed-off-by: Stefano Babic <sbabic@denx.de>
2017-08-29 09:46:32 +02:00
Tom Rini
c92ccdd4dc Prepare v2017.09-rc3
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-28 22:42:44 -04:00
Tom Rini
95431aa54c Merge branch 'master' of git://git.denx.de/u-boot-usb 2017-08-28 22:42:12 -04:00
Niko Mauno
22aa21dba4 splash_source: Verify FIT magic
Before reading entire FIT image, add sanity check by testing image
header against FDT_MAGIC. This should help avoid problems in situations
where FIT is not yet available from storage device, for example when
performing initial programming of device.

Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: Tomas Melin <tomas.melin@vaisala.com>
2017-08-29 00:20:16 +02:00
Masahiro Yamada
6ea247d137 usb: dwc3: fix Kconfig dependency to accept host driver in drivers/usb/dwc3
We see the choice of USB_DWC3_HOST / _GADGET in drivers/usb/dwc3/Kconfig,
but we can not choose USB_DWC3_HOST unless USB_GADGET is defined.
This is strange.

Loosen the "depends on" and also move "select USB_GADGET_DUALSPEED" to
the correct place.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-28 22:32:34 +02:00
Maxime Ripard
ead3697d7e mmc: sunxi: fix legacy MMC initialisation
The driver-model rework changed, among other things, the way the private
data were moved around. It now uses the private field in the struct mmc.

However, the mmc_create argument was changed in the process to always pass
the array we used to have to store our private structures.

The basically means that all the MMC driver instances will now have the
private data of the first instance, which obviously doesn't work very well.

Pass the proper pointer to mmc_create.

Fixes: 034e226bc7 ("dm: mmc: sunxi: Pass private data around explicitly")
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-28 22:38:05 +05:30
Jagan Teki
c9319b3f20 sunxi: bpi-m3: Enable eMMC
Add CONFIG_MMC_SUNXI_SLOT_EXTRA=2 to use eMMC on
BPI_M3 board.

Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-08-28 22:36:52 +05:30
Maxime Ripard
343ff16106 sunxi: Enable MMC new mode for A83T
The eMMC controller for the A83T uses the new operating mode. Enable it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-28 22:36:48 +05:30
Maxime Ripard
de9b1771c3 mmc: sunxi: Support new mode
Almost all of the newer Allwinner SoCs have a new operating mode for the
eMMC clocks that needs to be enabled in both the clock and the MMC
controller.

Details about that mode are sparse, and the name itself (new mode vs old
mode) doesn't give much details, but it seems that the it changes the
sampling of the MMC clock. One side effect is also that it divides the
parent clock rate by 2.

Add support for it through a Kconfig option.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-28 22:36:44 +05:30
Hannes Schmelzer
a223e2bc10 bootvx_fdt: fix missing 'fdt_fixup_ethernet(...)' on vxWorks boot
Before commit 26d6119 (fdt: Move fdt_fixup_ethernet to a common place)
the fdt_fixup_ethernet(...) was called during do_bootvx_fdt(...).

Afterwards the only (common) place for this fixup is during
image_setup_libfdt(...) and this is only called, at least on ARM
platform, from image_setup_linux(...).

All this ends up in the fact, that the fdt_fixup_ethernet(...) is only
called on booting a linux image and not on booting a vxWorks image.

We fix this with adding the fdt_fixup_ethernet(...) call again to
do_bootvx_fdt(...)

Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:19:13 -04:00
Wilson Lee
5daf6e56d3 common: console: Fix duplicated CONFIG in silent env callback
The silent environment callback function does not update the silent
flag during silent env set or unset. That is because of duplicated
CONFIG keyword at preprocessor condition in silent environment
callback function and cause silent env callback unable to work.

This patch is to remove the duplicated CONFIG keywork in silent
environment callback function.

Signed-off-by: Wilson Lee <wilson.lee@ni.com>
Cc: Keng Soon Cheah <keng.soon.cheah@ni.com>
Cc: Chen Yee Chew <chen.yee.chew@ni.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2017-08-28 07:19:12 -04:00
Bin Meng
dd027dde75 sandbox: Enable NVMe driver for build testing
This enables NVMe driver on sandbox for build testing.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:17 -04:00
Bin Meng
0d1414bd97 sandbox: Add a dummy invalidate_dcache_range() function
This adds invalidate_dcache_range() so that some drivers can build
without error on sandbox.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:16 -04:00
Bin Meng
fceadc1459 nvme: Adjust the 'nvme' command to use blk_common_cmd()
Instead of having separate code in the 'nvme' command, adjust it to use
the common function.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:15 -04:00
Bin Meng
18aa5a4134 nvme: Get rid of the global variable nvme_info
At present the NVMe uclass driver uses a global variable nvme_info
to store global information like namespace id, and NVMe controller
driver's priv struct has a blk_dev_start that is used to calculate
the namespace id based on the global information from nvme_info.

This is not a good design in the DM world and can be replaced with
the following changes:

- Encode the namespace id in the NVMe block device name during
  the NVMe uclass post probe
- Extract the namespace id from the device name during the NVMe
  block device probe
- Let BLK uclass calculate the devnum for us by passing -1 to
  blk_create_devicef() as the devnum

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:14 -04:00
Bin Meng
d5b7ee9c6e nvme: Use blk_create_devicef() API
The codes in nvme_uclass_post_probe() can be replaced to call the
blk_create_devicef() API directly.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:14 -04:00
Bin Meng
704e040a51 nvme: Apply cache operations on the DMA buffers
So far cache operations are only applied on the submission queue and
completion queue, but they are missing in other places like identify
and block read/write routines.

In order to correctly operate on the caches, the DMA buffer passed
to identify routine must be allocated properly on the stack with the
existing macro ALLOC_CACHE_ALIGN_BUFFER().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:13 -04:00
Bin Meng
625a483cea nvme: Consolidate block read and write routines
The NVMe block read and write routines are almost the same except
the command opcode. Let's consolidate them to avoid duplication.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:13 -04:00
Bin Meng
722e668db2 nvme: Use macros to access NVMe queues
NVMe driver only uses two queues. The first one is allocated to do
admin stuff, while the second one is for IO stuff. So far the driver
uses magic number (0/1) to access them. Change to use macros.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:12 -04:00
Bin Meng
04d2a38401 nvme: Respect timeout when en/disabling the controller
So far the driver unconditionally delays 10ms when en/disabling the
controller and still return 0 if 10ms times out. In fact, spec defines
a timeout value in the CAP register that is the worst case time that
host software shall wait for the controller to become ready.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:12 -04:00
Bin Meng
b65c692143 nvme: Cache controller's capabilities
Capabilities register is RO and accessed at various places in the
driver. Let's cache it in the controller driver's priv struct.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:11 -04:00
Bin Meng
3e18562961 nvme: Fix endianness assignment to prp2 in nvme_identify()
So far this is not causing any issue due to NVMe and x86 are using
the same endianness, but for correctness, it should be fixed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:11 -04:00
Bin Meng
099c2015b0 nvme: Fix ndev->queues allocation
ndev->queues is a pointer to pointer, but the allocation wrongly
requests sizeof(struct nvme_queue). Fix it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:11 -04:00
Bin Meng
e5dc2d2665 nvme: Fix getting PCI vendor id of the NVMe block device
The codes currently try to read PCI vendor id of the NVMe block
device by dm_pci_read_config16() with its parameter set as its
root complex controller (ndev->pdev) instead of itself. This is
seriously wrong. We can read the vendor id by passing the correct
udevice parameter to the dm_pci_read_config16() API, however there
is a shortcut by reading the cached vendor id from the PCI device's
struct pci_child_platdata.

While we are here fixing this bug, apparently the quirk stuff handle
codes in nvme_get_info_from_identify() never takes effect since its
logic has never been true at all. Remove these codes completely.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:10 -04:00
Bin Meng
abe25db611 nvme: Remove useless defines
These are leftover when the driver was ported from Linux and are not
used by the U-Boot driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-28 07:17:10 -04:00
Tom Rini
5dc4dfd2a9 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-28 07:16:32 -04:00
Breno Lima
3aa4b703b4 imx: imx6: Move gpr_init() function to soc.c
Since the gpr_init() function is common for boards using MX6S, MX6DL, MX6D,
MX6Q and MX6QP processors move it to the soc.c file.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-08-28 09:48:53 +02:00
Tom Rini
34f98a3d2e sh: Fix linking of ms7722se
While it is true that we no longer have 'ppcenv' and similar sections,
including env/embedded.o at all results in the text/etc sections being
available for the rest of the link.  This in turn is required for the
setup used on ms7722se.  This also, likely, needs further fine-tuning.

Fixes: f40ad66fa0 ("arch/sh: don't bring common/env_embedded.o into the link")
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-27 11:50:16 -04:00
Tom Rini
c3b572c4e2 cmd/spl.c: Include <libfdt.h> for fdt_totalsize
In order to be able to reliably use fdt_totalsize, we must have
<libfdt.h> included.

Fixes: 767cb74a00 ("cmd: spl: provide address and size of prepared FDT ...")
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-26 21:17:05 -04:00
Tom Rini
8b3cec7da1 mtdparts: Fix uninitialized scalar usage
When reworking this code to fix other issues found by Coverity, I forgot
to ensure tmp_ep was always cleared before use.

Reported-by: Coverity (CID: 166612)
Fixes: bc028345ac ("mtdparts: Fix final outstanding issue reported by Coverity")
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-26 16:59:24 -04:00
Tom Rini
bd95e655b2 Merge git://git.denx.de/u-boot-sh 2017-08-26 15:10:49 -04:00
Tom Rini
f72b96ec8f Merge branch 'rmobile' of git://git.denx.de/u-boot-sh 2017-08-26 15:10:46 -04:00
Tom Rini
0031af9ce7 Merge git://git.denx.de/u-boot-x86 2017-08-26 15:10:40 -04:00
Tom Rini
cc0427d269 Merge git://git.denx.de/u-boot-i2c 2017-08-26 15:10:38 -04:00
Tom Rini
c2150e4dc1 Merge git://www.denx.de/git/u-boot-cfi-flash 2017-08-26 15:10:35 -04:00
Stefan Agner
5c27535dc9 disk: part: align buffer so it can be used with DMA enabled drivers
When using ISO partitions with a DMA enabled block device driver
reading the ISO partition leads to unaligned DMA operations:
  CACHE: Misaligned operation at range [bffb7da8, bffb85a8]

Align the buffer to make sure we pass a buffer which works for
DMA operations.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-26 14:56:15 -04:00
Stephen Boyd
527d86558e scripts: objdiff: Ignore debug info when comparing
If the kernel is configured to be built with debug symbols, or
has bug tables, comparing files may not work if line numbers
change. This makes comparing object files with these options
harder to do. Let's strip out the debug info and drop the
__bug_table here so that we don't see false positives. There may
be other things to drop later, and it may be architecture
specific, but this works for me with my ARM64 build.

[ Import Linux commit: 65ba6fa439e7c3cbf97de9dce9e7a3390ae2638c ]

Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Reviewed-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-26 14:56:14 -04:00
Masahiro Yamada
e43f74ac0b doc: verified-boot: fix typos
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-26 14:56:14 -04:00
Tom Rini
10b078d836 fs: ext4: Fix journal overrun issue reported by Coverity
While &p_jdb[fs->blksz] is a valid expression (it points *one* char
sized element past the end of the array, e.g. &p_jdb[fs->blksz + 1] is
invalid (according to the C standard (C99/C11)).

Changing this to tag = (struct ext3_journal_block_tag *)(p_jdb + ofs);

Cc: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Suggested-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Reported-by: Coverity (CID: 165117, 165110)
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
2017-08-26 14:56:13 -04:00
Tom Rini
bc028345ac mtdparts: Fix final outstanding issue reported by Coverity
As part of fixing the previously reported issues, it was missed that in
the case of mtdparts_init() we need to make sure that tmp_ep is long
enough to contain PARTITION_MAXLEN and a NULL termination.  Then, to be
sure the buffer is NULL terminated, zero the entire buffer rather than
just ensuring the first character is NULL.

Cc: Lothar Waßmann <LW@KARO-electronics.de>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Reported-by: Coverity (CID: 166329)
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-26 14:56:13 -04:00
Vikas Manocha
1e87f9ced4 spl: stm32: make falcon mode activation configurable
With this change, it will be possible to de-select falcon mode & spl
will only boot U-Boot.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Suggested-by: Bo Shen <voice.shen@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-26 14:56:13 -04:00
Anatolij Gustschin
767cb74a00 cmd: spl: provide address and size of prepared FDT in environment
Writing prepared FDT to persistent storage should be possible in
scripts. Create environment variables containing address and size
of the updated FDT. Scripts can use these variables after running
'spl export fdt ...' command to write the new blob to persistent
storage.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-08-26 14:56:12 -04:00
Pau Pajuelo
195dc23185 igep00x0: merge igep0020 and igep0030 defconfigs to igep00x0_defconfig
Update igep00x0 code with the following features:
- Add board and revision detection for the boards:
  - IGEP0020-RF
  - IGEP0020-RC
  - IGEP0030-RG
  - IGEP0030-RE
- Merge IGEP0020 and IGEP0030 mux tables
- Add suport to use GPIO_126, GPIO_127 and GPIO_129
- board_name and board_rev environment variables display board and
  revision informations
- Move dtb name selection from code to boot script

Signed-off-by: Pau Pajuelo <ppajuel@gmail.com>
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tested-by: Pau Pajuelo <ppajuel@gmail.com>
2017-08-26 14:56:12 -04:00
Ladislav Michl
4c699a4747 igep00x0: move SPL routines into separate file
Avoid cluttering board file with CONFIG_SPL_BUILD ifdefs
by moving SPL related functions into separate file.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tested-by: Pau Pajuelo <ppajuel@gmail.com>
Acked-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
2017-08-26 14:56:12 -04:00
Semen Protsenko
ea8c7fcacc arm: dra7xx: Define Android boot arguments
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
2017-08-26 14:56:11 -04:00
Semen Protsenko
49c7d0ac14 arm: am57xx: Define Android boot arguments
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
2017-08-26 14:56:11 -04:00
Semen Protsenko
a17c8b1844 arm: omap: Define command for booting Android from eMMC
If SD card is present -- try to boot from it first. If no -- try to boot
Android from eMMC.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
2017-08-26 14:56:11 -04:00
Ruchika Gupta
a797f274d7 ARMv8/sec_firmware : Update chosen/kaslr-seed with random number
kASLR support in kernel requires a random number to be passed via
chosen/kaslr-seed propert. sec_firmware generates this random seed
which can then be passed in the device tree node.

sec_firmware reserves JR3 for it's own usage. Node for JR3 is
removed from device-tree.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
2017-08-26 14:56:11 -04:00
Thomas Petazzoni
225bfd3906 arch/arm/cpu/arm926ejs/spear/cpu.c: guard do_switch_ecc() with CONFIG_NAND_FSMC
do_switch_ecc() calls fsmc_nand_switch_ecc(), which is a direct
function call into drivers/mtd/nand/fsmc_nand.c. However, this
function is not guarded by CONFIG_NAND_FSMC, which results to a build
failure if CONFIG_NAND_FSMC is disabled.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2017-08-26 14:56:10 -04:00
Thomas Petazzoni
c25c4fd010 board/spear/common: move code to arch/arm/cpu/arm926ejs/spear/
The code in board/spear/common/ is not board-specific but
SoC-specific. Therefore, boards from other vendors than "spear" may
want to re-use this code, which is currently difficult with the code
being placed in board/spear/common/.

Since this code really is SoC-specific, this commit moves it to
arch/arm/cpu/arm926ejs/spear/, with the rest of the SPEAr related
code.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2017-08-26 14:56:10 -04:00
Wenyou.Yang@microchip.com
fc6adebbc1 board: atmel: Use the new PIT timer driver
Use the Atmel PIT timer driver which supports the driver model
and device tree.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-08-26 14:56:09 -04:00
Wenyou.Yang@microchip.com
47edaea494 driver: timer: Add the Atmel PIT timer driver
Add the new Atmel PIT timer driver, which supports the driver model
and device tree.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-08-26 14:56:08 -04:00
Tom Rini
deff9b1d2a powerpc: Rework interrupt_init_cpu()
The function interrupt_init_cpu() is given an int return type but does
not return anything but 0.  Rework this to be a void function.

Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Mario Six <mario.six@gdsys.cc>
2017-08-26 14:56:08 -04:00
Reno Farnesi
76216211f8 fs: fat: fix fatwrite overflow calculation
The overflow calculation was incorrect. Adding the start block of the
partition is not needed because the sectors are already relative to the
beginning of the partition. If you attempted to write a file smaller
than cur_part_info.start blocks on a full partition the old calculation
fails to catch the overflow. This would cause an infinite loop in the
determine_fatent function.

Old, incorrect calculation:

ending sector of new file = start sector + file size (in sectors)
last sector = partition start + total sectors on the partition

Adding the partition start block number is not needed because sectors
are already relative to the start of the partition.

New calculation:

ending sector of new file = start sector + file size (in sectors)
last sector = total sectors on the partition

Signed-off-by: Reno Farnesi <nfarnesi4@gmail.com>
2017-08-26 14:56:07 -04:00
Suniel Mahesh
528f2b66dc arm: dts: am33xx: sync DTS with Linux 4.13-rc4
This re-syncs AM33xx DTS file with current file from
Linux v4.13-rc4 to ensure a consistent configuration. Upstream
Linux removed the redundant Interrupt-parent property from mmc,
mac, lcdc and tscadc sub nodes.

Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-26 14:56:07 -04:00
Jagan Teki
93fd5b0ac1 ram: kconfig: s/SPL/TPL/ in TPL_RAM help text
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-08-26 14:56:06 -04:00
Simon Glass
e5ec12bbe1 rpi: Enable USB keyboard support
This is currently disabled, so USB keyboards are not detected in U-Boot.
Enable this option to fix that.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Paul Barker <pbarker@toganlabs.com>
2017-08-26 14:55:49 -04:00
Thomas Petazzoni
f40ad66fa0 arch/sh: don't bring common/env_embedded.o into the link
The linker script for SuperH brings the .ppcenv and .ppcenvr section
of common/env_embedded.o into the .text section. However, the .ppcenv
section is only ever filled in by env_embedded.o when
CONFIG_SYS_USE_PPCENV is defined, but no platforms in mainline U-Boot
use this.

In addition, common/env_embedded.o is not always built (when you use
CONFIG_ENV_IS_NOWHERE for example), which causes the following build
failure:

Fixes:

  LD      u-boot
/home/thomas/sh4aeb-linux-musl/bin/sh4aeb-linux-ld.bfd: cannot find common/env_embedded.o

We fix this by no longer adding the .ppcenv and .ppcenvr sections from
common/env_embedded.o into the .text section.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:40:36 +09:00
Thomas Petazzoni
90340c87e5 arch/sh: allow building in big-endian mode
The SuperH architecture allows to be run in either little or big
endian mode. Some SuperH SoCs get the little vs. big endian decision
through mode pins sampled at reset, so if big endian has been choosen
by HW designers, it cannot be easily changed.

Therefore, it makes sense to allow building U-Boot for SuperH in big
endian mode. To allow this, the only change needed is to adjust the
OUTPUT_FORMAT() in the linker script.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2017-08-26 07:38:39 +09:00
Marek Vasut
f7f79b4493 ARM: rmobile: Enable MMC and USB DM on ULCB
Enable the MMC and USB DM on the board since it's the modern method
and now supported by the drivers.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
3345ca21a1 ARM: rmobile: Enable MMC and USB DM on Salvator-X
Enable the MMC and USB DM on the board since it's the modern method
and now supported by the drivers.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
6f38085492 ARM: rmobile: Remove SH SDHI probing from ULCB board
Drop the SH SDHI bit from the board since SD now probes from DT instead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
ddb39a075b ARM: rmobile: Remove SH SDHI probing from Salvator-X board
Drop the SH SDHI bit from the board since SD now probes from DT instead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
3f63551471 ARM: rmobile: Remove Serial SH probing from ULCB board
Drop the Serial SH bit from the board since UART now probes from DT instead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
1c30aea5b1 ARM: rmobile: Remove Serial SH probing from Salvator-X board
Drop the Serial SH bit from the board since UART now probes from DT instead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
75ba2bf99f ARM: rmobile: Remove RAVB probing from ULCB board
Drop the RAVB bit from the board since RAVB now probes from DT instead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
a88026c51d ARM: rmobile: Remove RAVB probing from Salvator-X board
Drop the RAVB bit from the board since RAVB now probes from DT instead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
d47f356cde ARM: rmobile: Enable HUSH parser
The HUSH parser was disabled somewhere along the way, reenable it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alexandru Gagniuc <alex.g@adaptrum.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
c4464e163e ARM: rmobile: Enable KSZ90X1 PHY on Salvator-X
Commit da3b9e7fd6 (Move PHY_MICREL and PHY_MICREL_KSZ90X1 to Kconfig)
broke ethernet support on R8A779x Salvator-X boards by disabling the
KSZ90x1 PHY in Kconfig. Reenable it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alexandru Gagniuc <alex.g@adaptrum.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
46933dfbe1 ARM: rmobile: Add u-boot, dm-pre-reloc to clock nodes on Gen3
We need the clock available very early, add the u-boot,dm-pre-reloc
DT property on those nodes, so they come up very in the process.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Marek Vasut
fd8692b8ff clk: rmobile: Split R8A7795 and R8A7796 core clock tables
The R8A7795 and R8A7796 tables use different constants to identify
clock in DT, so split the tables and use the correct constants on
R8A7795. This fixes UART clock misconfiguration on R8A7795.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Stefan Agner
962c78b1df imx: use BOOT_DEVICE_BOARD instead of UART
i.MX 6 serial downloader is not necessarily booting via UART but can
also boot from USB. In fact only some i.MX chips have serial
downloader support via UART (e.g. 6UL/ULL and Vybrid) but all of
them have serial downloader support via USB. Use the more appropriate
BOOT_DEVICE_BOARD define which is used for ROM provided recovery
mechanisms in general.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2017-08-25 13:31:47 +02:00
Stefan Agner
3bd1642d4d imx: fix USB boot mode detection for i.MX 6UL and 6ULL
Add the reserved boot mode used in the bmode command for i.MX 6UL
and 6ULL as introduced in commit 3fd9579085 ("imx: mx6ull: fix USB
bmode for i.MX 6UL and 6ULL").

Also replace BMODE_UART with BMODE_RESERVED, which is more appropriate.
Commit 96aac843b6 ("imx: Use IMX6_BMODE_* macros instead of numericals")
added macros for boot modes, in the process the reserved boot mode got
named BMODE_UART. We use the reserved boot mode in the bmode command to
let the boot ROM enter serial downloader recovery mode. But this is only
a side effect, the actual boot mode is reserved...

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2017-08-25 13:31:31 +02:00
Bin Meng
438505fe69 x86: tangier: kconfig: Guard tangier-specific options
These options should not be exposed to other platforms.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2017-08-24 11:00:47 +08:00
Bin Meng
207d532bef x86: bayleybay: Adjust VGA rom address
Adjust VGA rom address to 0xfffb0000 so that u-boot.rom image can be
built again.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-24 11:00:47 +08:00
Bin Meng
81c727d86c x86: baytrail: Fix turbo enable
CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED must be turned on for Baytrail.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-24 11:00:47 +08:00
Bin Meng
2ddb1a177a x86: Convert CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED to Kconfig
This converts CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED to a Kconfig option.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-24 11:00:47 +08:00
Stefan Roese
5091a8b04d x86: dfi-bt700: Select SERIAL_RX_BUFFER via Kconfig
To support more input characters (longer stings pasted into the U-Boot
prompt) without dropping, lets selects the recently added UART RX
buffer for these boards.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-24 11:00:47 +08:00
Stefan Roese
b48dcd3751 x86: conga-qeval20-qa3-e3845: Select SERIAL_RX_BUFFER via Kconfig
To support more input characters (longer stings pasted into the U-Boot
prompt) without dropping, lets selects the recently added UART RX
buffer for these boards.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-24 11:00:47 +08:00
Stefan Roese
3ca7a06afb serial: serial-uclass: Add generic serial RX buffer support
Pasting longer lines into the U-Boot console prompt sometimes leads to
characters missing. One problem here is the small 16-byte FIFO of the
legacy NS16550 UART, e.g. on x86 platforms.

This patch now introduces a Kconfig option to enable RX buffer support
for all DM based serial drivers. With this option enabled, I was
able paste really long lines into the U-Boot console, without any
characters missing.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-24 11:00:47 +08:00
Stefan Roese
7fded0ce0f Revert "serial: ns16550: Add RX interrupt buffer support"
This reverts commit 6822cf3ec7.

As Bin Meng has tested and pointed out, we don't need the RX interrupt
for the RX buffer support at all. Just reading all available characters
into a buffer is sufficient to solve the problem with the dropped
characters upon long lines pasted into the U-Boot prompt. Since this
RX buffer support can be implemented in a generic way, without any
device specifica (e.g. for the ns16550), I'll post a new patch with
a new serial RX buffer support for DM, which all DM based serial
drivers can use.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-24 11:00:47 +08:00
Bin Meng
76e726502e vbe: Drop vbe_get_video_info()
With DM video, this is not used any more. Drop it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-24 11:00:47 +08:00
Bin Meng
c11b17c6bf x86: kconfig: Imply CMD_PCI
Let's imply the 'pci' command to access the de facto interconnect
bus in an x86 system.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24 11:00:47 +08:00
Bin Meng
1e6ebee667 x86: fsp: Configure SPI opcode registers before SPI is locked down
Some Intel FSP (like Braswell) does SPI lock-down during the call
to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done,
it's bootloader's responsibility to configure the SPI controller's
opcode registers properly otherwise SPI controller driver doesn't
know how to communicate with the SPI flash device.

This introduces a Kconfig option CONFIG_FSP_LOCKDOWN_SPI for such
FSPs. When it is on, U-Boot will configure the SPI opcode registers
before the lock-down.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24 11:00:47 +08:00
Bin Meng
b42711f90c x86: ich-spi: Move opcode registers configuration to another routine
At present the ICH SPI opcode registers configuration is done in the
ich_spi_remove() routine, a little bit weird but that's how current.
Linux MTD driver works. This changes to move the opcode registers
configuration to a separate routine ich_spi_config_opcode() which
might be called by U-Boot itself as well.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24 11:00:47 +08:00
Bin Meng
3e79141684 x86: ich-spi: Don't read cached lock status
At present the ICH SPI controller driver reads the controller lock
status from its register in the probe routine and saves the lock
status to a member of priv. Later the driver uses the cached status
from priv to judge whether the controller setting is locked and do
different setup.

But such logic is only valid when there is only the SPI controller
driver that touches the SPI hardware. In fact the lock status change
can be trigged outside the driver, eg: during the fsp_notify() call
when Intel FSP is used.

This changes the driver to read the lock status every time when an
SPI transfer is initiated instead of reading the cached one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24 11:00:47 +08:00
Bin Meng
7d82978927 x86: ich-spi: Remove unnecessary assignment in ich_init_controller()
There is no need to do another assignment to ich7_spi.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24 11:00:47 +08:00
Bin Meng
94bc9177ca x86: ich-spi: Remove spi_write_protect_region()
This routine is not called anywhere.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24 11:00:47 +08:00
Peng Fan
7a7bfec39e pinctrl: imx7ulp: Add new info instance for iomuxc1
To i.MX7ULP, we need to create two info instances for
iomux0 and iomux1 respectively, otherwise iomuxc0/1 will
share one info instance and use one base, because imx_pinctrl_probe
will use info to store base address and etc. But iomuxc0/1
actually have different base address.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
2017-08-23 10:48:15 +02:00
Peng Fan
63fbc59b4f pinctrl: imx: Fix mask when SHARE_MUX_CONF_REG is set
when using SHARE_MUX_CONF_REG, wrong mask is used for
writing config value, which causes mux value is cleared.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
2017-08-23 10:47:00 +02:00
Stefano Babic
7c09cbf68b imx: fix licensing in i.MX files
Some files for i.MX do not yet have the SPDX ID to reference the correct
license.

Signed-off-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Wolfgang Denk <wd@denx.de>
2017-08-23 10:45:45 +02:00
Peng Fan
fa85b0217d imx: mx7: psci: add copyright and license
Add copyright and license header.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2017-08-23 10:45:25 +02:00
Stefan Agner
f0e0698cee apalis/colibri_imx6: enable SDP by default
Enable Serial Download Protocol (SDP) in SPL and U-Boot. This is
useful to make use of imx_usb to download the complete U-Boot
(u-boot.img) after SPL has been downloaded. The U-Boot command
sdp allows to enumerate as SDP capable device again, e.g. to
download a Linux kernel and/or U-Boot script.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
2017-08-23 10:41:58 +02:00
Stefan Agner
2b2f678280 apalis/colibri_imx6: use independent USB PID for SPL
Use a completely independent USB Product ID for SPL. This allows
to differentiate a SDP running in SPL and SDP running in a U-Boot
which could not read the config block successfully.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
2017-08-23 10:41:58 +02:00
Stefan Agner
f9c39d95f1 doc: add Serial Download Protocol documentation
Document the U-Boot Serial Download Protocol implementation and
some typical use cases.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
2017-08-23 10:41:58 +02:00
Stefan Agner
a3774c1c3c spl: add serial download protocol (SDP) support
Add USB serial download protocol support to SPL. If the SoC started
in recovery mode the SPL will immediately switch to SDP and wait for
further downloads/commands from the host side.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
2017-08-23 10:41:58 +02:00
Stefan Agner
2f005695df cmd: add sdp command
Add a new command to start USB Serial Download Protocol (SDP)
state machine.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-08-23 10:41:58 +02:00
Stefan Agner
ccd7a4d2f4 usb: gadget: sdp: extend images compatible for jumps
Support U-Boot images in SPL so that u-boot.img files can be
directly downloaded and executed. Furthermore support U-Boot
scripts download and execution in full U-Boot so that custom
recovery actions can be downloaded from the host in a third
step.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-08-23 10:41:58 +02:00
Stefan Agner
5661f08a71 usb: gadget: add SDP driver
Add SDP (Serial Downloader Protocol) implementation for U-Boot. The
protocol is used in NXP SoC's boot ROM and allows to download program
images. Beside that, it can also be used to read/write registers and
download complete Device Configuration Data (DCD) sets. This basic
implementation supports downloading images with the imx header format
reading and writing registers.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
2017-08-23 10:41:58 +02:00
Stefan Agner
4e76c0774a imx: move imximage header to common location
Move the imximage.h header file to a common location so we can make
use of it from U-Boot too.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
2017-08-23 10:41:58 +02:00
Peng Fan
a430556ecb i2c: muxes: add i2c gpio multiplexer driver
Add an i2c mux driver providing access to i2c bus segments using a
hardware MUX sitting on a master bus and controlled through gpio pins.

E.G. something like:

         ----------              ----------  Bus segment 1   - - - - -
        |          | SCL/SDA    |          |-------------- |           |
        |          |------------|          |
        |          |            |          | Bus segment 2 |           |
        |  Linux   | GPIO 1..N  |   MUX    |---------------   Devices
        |          |------------|          |               |           |
        |          |            |          | Bus segment M
        |          |            |          |---------------|           |
         ----------              ----------                  - - - - -

SCL/SDA of the master I2C bus is multiplexed to bus segment 1..M
according to the settings of the GPIO pins 1..N.

Note commit log from kernel
commit 92ed1a76("i2c: Add generic I2C multiplexer using GPIO API")

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Peng Fan <peng.fan@nxp.com> (i.MX6QP-Sabreauto)
Cc: Heiko Schocher <hs@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Simon Glass <sjg@chromium.org>
2017-08-23 07:04:56 +02:00
Patrice Chotard
4fadcaf097 i2c: add i2c driver for stm32
Add i2c driver which can be used on both STM32F7 and STM32H7.
This I2C block supports the following features:
 _ Slave and master modes
 _ Multimaster capability
 _ Standard-mode (up to 100 kHz)
 _ Fast-mode (up to 400 kHz)
 _ Fast-mode Plus (up to 1 MHz)
 _ 7-bit and 10-bit addressing mode
 _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
 _ All 7-bit addresses acknowledge mode
 _ General call
 _ Programmable setup and hold times
 _ Easy to use event management
 _ Optional clock stretching
 _ Software reset

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-23 07:04:40 +02:00
Tom Rini
90ae53ce1a fastboot: Ensure we treat CONFIG_FASTBOOT_BUF_ADDR as long
Otherwise:
drivers/usb/gadget/f_fastboot.c:564:32: warning: format "%lx" expects
argument of type "long unsigned int", but argument 3 has type "unsigned
int" [-Wformat=]

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-22 08:20:02 -04:00
Marek Vasut
236c49a1c8 mtd: cfi: staticize functions
Staticize a few functions and variables which are no longer exposed.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-22 09:56:09 +02:00
Tom Rini
ad8afeaee0 Merge git://www.denx.de/git/u-boot-marvell 2017-08-21 07:17:15 -04:00
Tom Rini
09b6a6dd01 Merge git://git.denx.de/u-boot-usb 2017-08-21 07:16:56 -04:00
Tom Rini
8197d92843 Merge git://git.denx.de/u-boot-uniphier
- Fix unmet direct dependencies warning
 - Remove old sLD3 SoC support
 - Update reset data
 - Add dr_mode DT property to avoid warning
2017-08-21 07:16:16 -04:00
Chris Packham
6ab09b05f3 ARM: mvebu: set correct mem_size for db-88f6820-amc
The db-88f6820-amc has four chips with 2Gb density giving a total of 1GB
DRAM. Update the board_topology_map to reflect the correct
configuration.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-21 11:40:49 +02:00
Lukasz Majewski
5bf4475f1d doc: license: Add license header to the README.dfutftp file
Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-08-21 11:31:11 +02:00
Tom Rini
6bafa5a4bd fb_mmc.c: Correct blk_dread() return value checks
The function blk_dread will return -ENOSYS on failure or on success the
number of blocks read, which must be the number asked to read (otherwise
it failed somewhere).  Correct this check.

Cc: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-21 11:31:11 +02:00
Tom Rini
2341c80cd2 common/fb_mmc.c: Fix warnings about casts
When building the flash zImage code on aarch64 we see warnings about
pointer size casts.  Use uintptr_t instead to correct these.

Cc: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-By: Sam Protsenko <semen.protsenko@linaro.org>
2017-08-21 11:31:10 +02:00
John Keeping
7715dea48b fastboot: avoid printing invalid data
There is no guarantee that commands are null-terminated in the USB
request buffer, so limit the length of data that is printed.

Signed-off-by: John Keeping <john@metanate.com>
Tested-by: Steve Rae <steve.rae@raedomain.com>
2017-08-21 11:31:10 +02:00
Peter Chubb
d331084298 Fix fastboot boot address
Fastboot loads an image at CONFIG_FASTBOOT_BUF_ADDR, but currently
tells do_bootm() to look for an image at $loadaddr.  This breaks if
CONFIG_FASTBOOT_BUF_ADDR is different from the current user-set
loadaddr.

Instead, tell do_bootm() to pick up the image where it was laoded.

Signed-off-by: Peter Chubb <peter.chubb@data61.csiro.au>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Steve Rae <steve.rae@raedomain.com>
2017-08-21 11:31:10 +02:00
Bin Meng
a11a5b8ad9 usb: ehci: Convert CONFIG_USB_EHCI_PCI to Kconfig
This converts CONFIG_USB_EHCI_PCI to a Kconfig option, and updates
all boards that use it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-21 11:30:44 +02:00
Simon Glass
2d7cb5b426 env: Replace all open-coded gd->env_valid values with ENV_ flags
Some of these were missed in the conversion.
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-20 19:27:44 -04:00
Simon Glass
c55d8b9400 env: Allow env_load() to detect errors
Now that we have errors available in the environment driver's load()
method, check the return valid.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-20 19:27:43 -04:00
Tom Rini
eeba55cb4a env: Correct case of no sub-init function
With the change to the environment code to remove the common init stage
of pointing to the default environment and setting it as valid, combined
with the change to switch gd->env_valid from 0/1/2 to an enum we now
must set env_valid to one of the enum values rather than an int.  And in
this case, not only was setting it to an int wrong, it was now the wrong
value.  Finally, in the case of ENV_IS_NOWHERE we must still say that
our envionrment is invalid after init for things to continue to
function.

Fixes: 7938822a6b ("env: Drop common init() functions")
Tested-by: Marek Vasut <marek.vasut@gmail.com>
Reported-by: Marek Vasut <marek.vasut@gmail.com>
Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
Changes in v3:
- Actually include changes for env/nowhere.c
2017-08-20 19:27:28 -04:00
Masahiro Yamada
3444d1d40e ARM: dts: uniphier: add dr_mode property to dwc3 node
Since commit 576e3cc700 ("usb: host: xhci-dwc3: Add dual role mode
support from DT"), warning is displayed if dr_mode is not specified.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-20 23:07:02 +09:00
Masahiro Yamada
6584b1ea10 reset: uniphier: refactor reset data and add NAND/eMMC reset lines
- Merge sys_reset data of LD4, Pro4, sLD8 and Pro5

  - Merge sys_reset data of LD11 and LD20

  - Use primitive UNIPHIER_RESETX() macro because bit assignments for
    system reset will be changed for every SoC in the future

  - Add NAND and eMMC resets

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-20 23:06:20 +09:00
Masahiro Yamada
c5161eee38 Revert "ARM: uniphier: fix ROM boot mode for PH1-sLD3"
This reverts commit 82d075e79f.

Commit 82d075e79f ("ARM: uniphier: fix ROM boot mode for PH1-sLD3")
was a workaround for sLD3.  Now the sLD3 SoC support has been removed.

Revert it to allow to simplify the init code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-20 23:05:39 +09:00
Masahiro Yamada
0aa8b2c3e0 Revert "ARM: uniphier: move lowlevel debug init code after page table switch"
This reverts commit bcc51c1512.

Commit bcc51c1512 ("ARM: uniphier: move lowlevel debug init code
after page table switch") was intended to support lowlevel debug for
sLD3.  Now the sLD3 SoC support has been removed.

Revert it to allow to enable lowlevel debug earlier.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-20 23:05:39 +09:00
Masahiro Yamada
00aa453ebf ARM: uniphier: remove sLD3 SoC support
This SoC is too old.  It is difficult to maintain any longer.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-20 23:05:39 +09:00
Masahiro Yamada
213fcabdfd clk: uniphier: fix unmet direct dependencies warning
Since commit f0776a5517 ("spl: dm: Kconfig: SPL_CLK depends on
SPL_DM"), the following warning is displayed:

  $ make uniphier_v8_defconfig
  warning: (ARCH_ZYNQ && ARCH_ZYNQMP && STM32F7 && CLK_UNIPHIER) selects
  SPL_CLK which has unmet direct dependencies (CLK && SPL_DM)

While I am here, I am removing the prompt to make it user-unconfigurable
option so that "select CLK_UNIPHIER" can be omitted.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-20 23:05:39 +09:00
Anatolij Gustschin
f1a7ba1da5 Fix 'notes' typos
s/notes/nodes

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-08-20 09:54:34 -04:00
Andy Shevchenko
e94c1268f2 env: Sort selection of default choices
It would be easier to catch out which platform is using which default.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2017-08-20 09:54:33 -04:00
Heiko Schocher
79c85f7115 arm, at91: fix taurus board
since commit: b529993e02 "spl: add hierarchical defaults for SPL_LDSCRIPT"

taurus board stopped working. Use the ldscript from
arch/arm/cpu/u-boot-spl.lds (as before this patch) fixed it.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-20 09:54:33 -04:00
Thomas Petazzoni
c1ee8936bf common/board_f.c: remove CONFIG_SYS_GENERIC_GLOBAL_DATA
CONFIG_SYS_GENERIC_GLOBAL_DATA is no longer used by any board or
platform, so support for it can be dropped.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-20 09:54:32 -04:00
Peter Griffin
fb53e7eb60 ARM: hisilicon: hikey: Fix eMMC with latest ATF & U-Boot
ATF can leave the MMC IP in a state where U-Boot mmc driver
can't enumerate the eMMC.

This patch provides a mmc0_reset_clk() function like we
already so do sd card controller which resets the IP
when entering U-Boot.

With this patch applied eMMC partitions are successfully
enumerated again.

=> mmc dev 0
switch to partitions #0, OK
mmc0(part 0) is current device
=> mmc part

Partition Map for MMC device 0  --   Partition Type: EFI

Part	Start LBA	End LBA		Name
	Attributes
	Type GUID
	Partition GUID
  1	0x00000800	0x00000fff	"vrl"
	attrs:	0x0000000000000000
	type:	ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
	guid:	496847ab-56a1-4cd5-a1ad-47f4acf055c9
  2	0x00001000	0x000017ff	"vrl_backup"
	attrs:	0x0000000000000000
	type:	ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
	guid:	61a36fc1-8efb-4899-84d8-b61642efa723
  3	0x00001800	0x00001fff	"mcuimage"
<snip>

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
2017-08-20 09:54:31 -04:00
Tom Rini
42a9f147d8 fs/fat: Correct blk_dread() return value check
The function blk_dread will return -ENOSYS on failure or on success the
number of blocks read, which must be the number asked to read (otherwise
it failed somewhere).  Correct this check.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-20 09:54:31 -04:00
Tom Rini
9585dd3fff spl: spl_mmc.c Correct blk_dread() return value check
The function blk_dread will return -ENOSYS on failure or on success the
number of blocks read, which must be the number asked to read (otherwise
it failed somewhere).  Correct this check.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-20 09:54:30 -04:00
Tom Rini
d03618d5cb cmd/read.c: Fix checking blk_dread return value
The function blk_dread will return -ENOSYS on failure or on success the
number of blocks read, which must be the number asked to read (otherwise
it failed somewhere).  Correct this check.

Reported-by: Coverity (CID: 166335)
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-20 09:54:30 -04:00
Tom Rini
54f1792c8d mtdparts: Fix various issues reported by Coverity
Now that sandbox is building cmd/mtdparts.c Coverity has looked at the
code and found a number of issues.  In index_partitions() it is possible
that part will be NULL, so re-work the checks and debug statements to
take this into account.  We have a number of string buffers that we
print to in the exact size of, and use string functions on, so we need
to ensure they are large enough to be NULL terminated.  In
device_parse() it is not possible for num_partitions to be 0 (we would
have hit a different error first) so remove logically dead code.
Finally, in parse_mtdparts() if we have an error we need to free the
memory allocated to dev.

Cc: Lothar Waßmann <LW@KARO-electronics.de>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Reported-by: Coverity (CID: 166334, 166333, 166332, 166329, 166328)
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-20 09:54:29 -04:00
Tom Rini
78eda89e9a hash: Compile only hardware or software versions of SHA algorithms
Commit 089df18bfe ("lib: move hash CONFIG options to Kconfig") moved
CONFIG_SHA1, CONFIG_SHA256, CONFIG_SHA_HW_ACCEL, and
CONFIG_SHA_PROG_HW_ACCEL config options to Kconfig. So in the case of
SPL, CONFIG_SPL_HASH_SUPPORT enables CONFIG_SHA1 and CONFIG_SHA256 which
enables SHA SW library by default.  But in the case of platforms with
SHA HW library support, SHA SW library becomes redundant and increases
size of SPL by approx 18K.  Rework the code so that we have named
members and only have either software or hardware versions of the
algorithm, depending on the relevant config options.  Update the comment
around hash_algo to reflect this as well.

Reported-by: Sumit Garg <sumit.garg@nxp.com>
Cc: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Sumit Garg <sumit.garg@nxp.com>
2017-08-20 09:53:13 -04:00
Clément Bœsch
3809e30273 Makefile: honor PYTHON configuration properly
On some systems `python` is `python3` (for instance, Archlinux). The
`PYTHON` variable can be used to point to `python2` to have a successful
build.

The use of `PYTHON` is currently limited in the Makefile and needs to be
extended in other places:

First, pylibfdt is required to be a Python 2 binding (binman imports
pylibfdt and is only compatible Python 2), so its setup.py needs to be
called accordingly. An alternative would be to change the libfdt
setup.py shebang to python2, but the binding is actually portable. Also,
it would break on system where there is no such thing as `python2`.

Secondly, the libfdt import checks need to be done against Python 2 as
well since the Python 2 compiled modules (in this case _libdft.so) can
not be imported from Python 3.

Note on the libfdt imports: "@if ! PYTHONPATH=tools $(PYTHON) -c 'import
libfdt'; then..." is probably simpler than the currently sub-optimal
pipe.
Reviewed-by: Jonathan Gray <jsg@jsg.id.au>
2017-08-20 09:53:13 -04:00
Tom Rini
2629a21e20 Merge git://git.denx.de/u-boot-video 2017-08-19 22:11:05 -04:00
xypron.glpk@gmx.de
021414a332 lcd: avoid possible NULL dereference
Do not dereference bmp before the check if it is NULL.

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-19 20:42:20 +02:00
Tom Rini
5619295995 Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot
EFI Fixes for 2017.09:
  - Fix GOP w/o display
  - Fix LocateHandle
  - Fix exit return value truncation
  - Fix missing EFIAPI in efi_locate_handle (for x86)
2017-08-18 18:24:58 -04:00
Tom Rini
1fdafb2e3d Merge branch 'master' of git://git.denx.de/u-boot-mmc 2017-08-18 18:24:36 -04:00
Tom Rini
a6dd10c70b Merge branch 'master' of git://git.denx.de/u-boot-coldfire 2017-08-18 18:24:08 -04:00
Tom Rini
804f1d9938 Merge branch 'master' of git://git.denx.de/u-boot-rockchip 2017-08-18 18:23:58 -04:00
Kever Yang
957b4ee3f3 rockchip: rk322x: pinctrl: fix IO MASK error on sdcard pin
Fix the IOMUX setting for SDcard CMD pin at the same time.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-18 18:00:46 +02:00
Kever Yang
a634236b8d rockchip: rk322x: pinctrl: using compatible name same with dts
The dts from kernel is using rk3228-pinctrl as compatible name,
need to sync with it to make the driver work.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-18 18:00:29 +02:00
Kever Yang
a80b3b0378 rockchip: rk322x: update MACRO for mmc clksel reg
The description for eMMC/SDIO/SDMMC src is not correct,
update the CRU_CLKSEL11_CON value definition according to TRM.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-18 17:52:47 +02:00
Kever Yang
44c5ba557b rockchip: rk322x: update dram bank size
The DRAM start address is not 0, so need to update the last bank size
as:
DRAM start addr + DRAM_SIZE - last bank start addr

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-18 16:55:25 +02:00
Philipp Tomsich
a299a4879e rockchip: rk3399: spl: remove unused header inclusion
fdtdec.h is included, but not used in rk3399-board-spl.c: remove the
'#include'-statement.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-18 16:55:15 +02:00
Kever Yang
caa6b3b530 rockchip: dts: rk3399-evb: remove redundant gmac node
There are two same gmac node, remove one.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-18 16:54:39 +02:00
xypron.glpk@gmx.de
c81883dfce efi_loader: do not cast return value in EFI_EXIT
UEFI API functions have different return types.
Some return a value of type EFI_STATUS other don't.

We therefore should not cast the return value of EFI_EXIT
to another type than the expression passed to EFI_EXIT.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-08-18 10:53:23 +02:00
Bin Meng
a191ccaf12 mmc: Support generic PCI SD host controller
This changes pci_mmc driver to use PCI_CLASS_SYSTEM_SDHCI instead of
individual vendor id & device id pair to support generic PCI SD host
controller.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-18 15:37:38 +09:00
Angelo Dureghello
a373024e7f m68k: add board stmark2, mcf5441x based
Sysam stmark2 board is a generic and fully (hw and sw) open board, with
a mcf54415 Coldfire CPU, 128MB of DDR2, 16MB of SPI flash and SD card
as non volatile memories, and a wifi module included on-board.
The board is actually used mainly for Coldfire custodian testing activity
related to the mcf5441x Coldfire family.

For further information please see: http://sysam.it/cff_stmark2.html

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
---

Changes in v2:
 - remove CMD_REGINFO
 - add board information in commit message
2017-08-18 01:26:52 +02:00
Angelo Dureghello
02a6eddaba m68k: mcf5445x: allow CS0 to be undefined
On some boards, CONFIG_SYS_CS0_BASE can be undefined, since
CS0 is not connected to any signal.

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
2017-08-18 01:26:39 +02:00
Angelo Dureghello
c533cfcd93 m68k: fix cache.c for Coldfire V4E
- fix cache.c CONFIG_CF_V4e to CONFIG_CF_V4E
- fix cache.c to properly enable/disable cache for V4E

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
2017-08-18 01:26:17 +02:00
Angelo Dureghello
c74dda8b44 m68k: mcf5445x: move early ddr init as board-specific
For certain boot types and sbf, for V4 cpu's, an early ddr/sdram init
is required. This patch moves this ddr/sdram early initalization
away from start.S (to be board related).

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
2017-08-18 01:26:08 +02:00
Philipp Tomsich
b5c4d81b35 spl: fix Makefile for NOR, XIP and YMODEM
During the the conversion to $(SPL_TPL_), the SPL_ fragment was
left over for the NOR, XIP and YMODEM boot methods in SPL, making
these unselectable.

This commit fixes this by dropping the spurious 'SPL_' fragment
from each line.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reported-by: Bo Shen <voice.shen@gmail.com>
Fixes: f94e643 (spl: consistently use $(SPL_TPL_) to select features for SPL and TPL builds)
2017-08-17 10:15:24 +02:00
Kever Yang
1ade3a9013 rockchip: dts: rk3399-firefly: update gmac parameter
Update the tx_delay and rx_delay to match the timing for
rk3399-firefly board to improve the stability of gmac data
transfer.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-17 10:11:18 +02:00
Angelo Dureghello
bdb6099666 cmd: mmc: add mmc partconf read capability
This patch allows to show the EXT_CSD[179] partition_config
register info, just by specifying the dev param:

  U-Boot> mmc partconf 0
  EXT_CSD[179], PARTITION_CONFIG:
  BOOT_ACK: 0x0
  BOOT_PARTITION_ENABLE: 0x0
  PARTITION_ACCESS: 0x0

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-08-17 17:00:11 +09:00
Simon Glass
e7881d85a9 dm: mmc: Drop CONFIG_DM_MMC_OPS
All boards which use DM_MMC have now been converted to use DM_MMC_OPS.
Drop the option and good riddance.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:59:55 +09:00
Simon Glass
b9a40c0c0a dm: mmc: Correct Kconfig condition for SPL_DM_MMC_OPS
This should depend on SPL_DM_MMC, not SPL_DM. For it and update the only
affected board's defconfig.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:18 +09:00
Simon Glass
2088747743 dm: imx: Move i.MX devices to use CONFIG_DM_MMC_OPS
Now that the driver supports it, move these boards over to use driver
model fully for MMC.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
5248930ebf dm: imx: cm_fx6: Enable more driver model support
Enable driver model for MMC (including BLK), SATA and USB. Note that USB
does not yet work correctly since the nodes are disabled. Hopefully this
can be resolved by the maintainer.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
4f6478d646 dm: imx: cm_fx6: Add MMC support for CONFIG_BLK
When CONFIG_BLK is enabled our weak board_mmc_init() will not be called.
Since there is no clock driver for MX6 yet, we must manually enable the
clocks.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
5ec1f560f3 dm: imx: cm_fx6: Add device tree for cm_fx6
Add this file so we can use device-tree control for cm_fx6. It comes from
linux 4.12.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
8d331e38e0 dm: imx: cm_fx6: Support driver model for SATA
Add support for using driver model for SATA with the cm_fx6 board. The old
code remains for now to permit testing.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
653282b567 dm: mmc: fsl_esdhc: Update to support MMC operations
This driver does not currently support CONFIG_DM_MMC_OPS. Update it to
fully convert it to driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
4aac33f510 dm: mmc: fsl_esdhc: Update to support livetree
Update this driver to support a live device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
d6eb25e987 dm: mmc: fsl_esdhc: Drop mmc_init() call from fsl_esdhc_init()
We want to use fsl_esdhc_init() with driver model. Move the mmc_init() out
of this function so that we can use it for our common init.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
e88e1d9c04 dm: mmc: fsl_esdhc: Set up platform data
With driver model we want to store the mmc and configuration structure in
platform data. Set up structure up and use it for non-DM as well.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
201e828b22 dm: mmc: fsl_esdhc: Detect init failure
Since esdhc_init_common() can fail it should return an error code. Update
this and also adjust the timeout mechanism to use get_timer(), which is a
more common approach.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
446e077a21 dm: mmc: fsl_esdhc: Detect reset failure
Since esdhc_reset() can fail it should return an error code. Update this
and also adjust the timeout mechanism to use get_timer(), which is a more
common approach.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
9586aa6ea3 dm: mmc: fsl_esdhc: Set up common versions of operations
Driver model wants to use the core functions in this file but accesses the
driver-private data in a different way. Move the code into new 'common'
functions and set up stubs to call these. Also sort the operations into
alphabetical order for consistency.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
09b465fd0f dm: mmc: fsl_esdhc: Pass private data to internal functions
With driver model we will not use mmc->priv to access driver-private data.
To accomodate this, update internal functions so that we can pass the
private data directly. This will allow the caller to obtain it as it
prefers.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
c893f1e6e5 dm: sata: dwc_ahsata: Add support for driver model
Update this driver to support driver model. This involves implementing the
AHCI operations and reusing existing common code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
b8341f1c39 dm: sata: Update the AHCI uclass to support operations
At present the AHCI uclass is just a shell and we still use the global
functions to access SATA. Fix this by adding operations to the uclass.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
7e0712b26e dm: sata: imx: Allow driver model to be used for sata
Update the sata call to work with driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
f19f1ecb60 dm: sata: Support driver model with the 'sata' command
Update this command to support driver model. This has a different way of
starting and stopping SATA.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
752126a05a dm: sata: dw_sata: Set up common versions of operations
Driver model wants to use the core functions in this file but accesses the
uclass-private data in a different way. Move the code into new 'common'
functions and set up stubs to call these.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
036a803e1b dm: sata: dw_sata: More ahci_init_one() futher down
This function will not be used with driver model and it relates to the
other exported functions. Move it down next to them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
5908d85eb7 dm: sata: dw_sata: Drop is_ready
This variable is set but never used. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
90abb28fcf dm: sata: dw_sata: Rename the dwc_ahsata private header
Rename dwc_ahsata.h to indicate that it is a private header file. We plan
to create another header with some public functions.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
0f07df4301 dm: sata: dw_sata: Sort #include directives
Sort the header file inclusions into the correct order.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
3e59c30fcf dm: sata: dw_sata: Drop unnecessary brackets
There is a strange &(var) coding style in this driver. Adjust it to use
&var instead, which is more usual.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
47c0f3692d dm: sata: dw_sata: Pass uc_priv to internal functions
With driver model sata_dev_desc[] does not exist. We still want to use the
common code of this driver so update it to pass struct ahci_uc_priv * to
each of these functions, instead of an integer which must be looked up in
sata_dev_desc[].

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
4b640dbcac dm: sata: dw_sata: Drop unnecessary casts
Most of the casts in this driver are not necessary. With driver model we
do not cast from void *. Update the driver to follow this rule.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
09bb951bf3 dm: sata: dw_sata: Rename 'probe_ent' to uc_priv
With driver model this becomes uclass-private data. Rename the parameter
varable to reflect this.

With the driver model conversion we will not have any exported functions.
Move all exported functions to be together at the end of the file so that
we can deal with them in one #ifdef block.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:16 +09:00
Simon Glass
c5273acf5c dm: sata: dw_sata: Move exported functions to the end
With the driver model conversion we will not have any exported functions.
Move all exported functions to be together at the end of the file so that
we can deal with them in one #ifdef block.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:16 +09:00
Simon Glass
1dae3b06b7 dm: sata: dw_sata: Drop dwc_ahsata_rw_ncq_cmd()
This function is not called from anywhere. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:16 +09:00
Simon Glass
d7f094354c dm: sata: dwc_ahsata: Make functions static
Some functions are not called from outside this file. Make these static
to make that obvious.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:16 +09:00
Simon Glass
e88afccc44 dm: core: Add a comment about the device_remove() flags
We should explain which flags are used for this function. Update the
comment to indicate this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:16 +09:00
Simon Glass
7074b2a364 dm: blk: Update return value in blk_create_devicef()
This returns 'ret' but the value is always zero. Update it to simply
return 0, for clarity.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:16 +09:00
Simon Glass
c16ad675d5 dm: usb: Adjust the 'usb' command to use blk_common_cmd()
Instead of having separate code in the 'usb' command, adjust it to use
the common function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-17 16:44:16 +09:00
Simon Glass
09ed0d616d dm: ide: Adjust the 'ide' command to use blk_common_cmd()
Instead of having separate code in the 'ide' command, adjust it to use
the common function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-17 16:44:16 +09:00
Simon Glass
1eaadd3423 dm: scsi: Adjust the 'scsi' command to use blk_common_cmd()
Instead of having separate code in the 'scsi' command, adjust it to use
the common function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-17 16:44:16 +09:00
Simon Glass
e29e71e93a dm: sata: Adjust the 'sata' command to use blk_common_cmd()
Instead of having separate code in the 'sata' command, adjust it to use
the common function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-17 16:44:16 +09:00
Simon Glass
4395f66739 dm: blk: Add a generic function for block device commands
Most block devices provide a command (e.g. 'sata', 'scsi', 'ide') and
these commands generally do the same thing. This makes it harder to
maintain this code and keep it consistent.

We now have a block device interface which is either implemented by driver
model (when CONFIG_BLK is enabled) or with a legacy interface. Therefore
it is possible to handle most of what these commands do with generic code.

Add a new generic function to process block-device commands using the
interface type and the current device number for that type.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:16 +09:00
Simon Glass
6faa4ed74d dm: blk: Add a function to find an interface-type name
Add a function to find the name of an interface type (e.g. "sata", "scsi")
from the interface type enum.

This is useful for generic code (not specific to SATA or SCSI, for
example) that wants to display the type of interface it is dealing with.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:16 +09:00
Simon Glass
745fb9c25e dm: core: Avoid calling dm_scan_fdt_dev() with of-platdata
We cannot call dm_scan_fdt_dev() with of-platdata since there is no device
tree. Fix this with an #if check.

Fixes: 3be9a37 (dm: syscon: scan sub-nodes of the syscon node)
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:16 +09:00
Wenyou.Yang@microchip.com
722b150e6f mmc: gen_atmel_mci: Fix wrong arguments used of bind()
The bind() method is called before the device is probed and so the
device has no private data, should use the platform data, and set up
a new struct to hold the mmc and cfg members.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:12 +09:00
Marek Vasut
8cd46cba53 mmc: sd_sdhi: Enable clock using clock framework
Since we now have clock driver for the RCar Gen3 , add support for
enabling the clock into the SH SDHI driver to prevent hacks in the
board files.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-17 14:38:18 +09:00
Marek Vasut
a3f0a7d5b5 mmc: sh_sdhi: Fix the ACMD handling
The command handling in this driver is awful, esp. because the driver
depends on command numbers to determine whether this is APPCMD or not.
Also, handling of command RSP response types is totally wrong.

This patch at least plucks out some of the custom command encoding and
fixes the APPCMD handling. The RSP handling still needs work, yet that
might not be needed as it turns out the uniphier-sd.c driver is in much
better shape and supports the same IP, so we might be able to just drop
this driver in favor of the uniphier one.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-17 14:38:02 +09:00
Marek Vasut
d1c18ca110 mmc: sh_sdhi: Add DM and DT probing support
Add MMC DM and DT probing support into the SH SDHI driver.
This patch abstracts out the common bits of the send command
and set ios functions, so they can be used both by DM and non
DM setups and adds the DM probe support.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-17 14:37:45 +09:00
Marek Vasut
ac5efc358b mmc: uniphier-sd: Fix long response processing
The long response entry 0..3 LSByte comes from the next response
register MSByte, not from the next response register LSByte. Fix
this to make the driver report correct values in response 136 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-17 14:36:05 +09:00
Tom Rini
336aee50cf Merge git://git.denx.de/u-boot-tegra 2017-08-16 18:12:58 -04:00
Tom Rini
ceff355a5f Merge git://git.denx.de/u-boot-sunxi
Update A20-OLinuXino-Lime2-eMMC_defconfig to include CONFIG_SCSI

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-16 18:12:40 -04:00
Tom Rini
470135be27 Merge git://www.denx.de/git/u-boot-imx
Update pfla02 for setenv changes and PHYLIB/etc migration to Kconfig.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-16 18:12:00 -04:00
Tom Rini
390194d43f Merge git://git.denx.de/u-boot-spi 2017-08-16 18:07:15 -04:00
Bin Meng
294f2050c4 sf: Preserve QE bit when clearing BP# bits for Macronix flash
On some flash (like Macronix), QE (quad enable) bit is in the same
status register as BP# bits, and we need preserve its original value
during a reboot cycle as this is required by some platforms (like
Intel ICH SPI controller working under descriptor mode).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
[Refined code for readability]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-08-16 18:21:50 +05:30
Simon Glass
c595199194 env: Adjust the load() method to return an error
The load() methods have inconsistent behaviour on error. Some of them load
an empty default environment. Some load an environment containing an error
message. Others do nothing.

As a step in the right direction, have the method return an error code.
Then the caller could handle this itself in a consistent way.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:31:24 -04:00
Simon Glass
21f639446d env: Adjust the get_char() method to return an int
In principle this can fail, e.g. if the index is out of range. Adjust the
driver signature to allow returning an error code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-16 08:31:24 -04:00
Simon Glass
723806cc5b env: Rename some other getenv()-related functions
We are now using an env_ prefix for environment functions. Rename these
other functions as well, for consistency:

   getenv_vlan()
   getenv_bootm_size()
   getenv_bootm_low()
   getenv_bootm_mapsize()
   env_get_default()

Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:31:11 -04:00
Simon Glass
35affd7a2f env: Rename eth_getenv_enetaddr() to eth_env_get_enetaddr()
Rename this function for consistency with env_get().

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:30:44 -04:00
Simon Glass
bfebc8c965 env: Rename getenv_hex(), getenv_yesno(), getenv_ulong()
We are now using an env_ prefix for environment functions. Rename these
for consistency. Also add function comments in common.h.

Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:30:32 -04:00
Simon Glass
00caae6d47 env: Rename getenv/_f() to env_get()
We are now using an env_ prefix for environment functions. Rename these
two functions for consistency. Also add function comments in common.h.

Quite a few places use getenv() in a condition context, provoking a
warning from checkpatch. These are fixed up in this patch also.

Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:30:24 -04:00
Simon Glass
fd1e959e91 env: Rename eth_setenv_enetaddr() to eth_env_set_enetaddr()
Rename this function for consistency with env_set().

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:23:56 -04:00
Simon Glass
018f530323 env: Rename common functions related to setenv()
We are now using an env_ prefix for environment functions. Rename these
commonly used functions, for consistency. Also add function comments in
common.h.

Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:23:32 -04:00
Simon Glass
382bee57f1 env: Rename setenv() to env_set()
We are now using an env_ prefix for environment functions. Rename setenv()
for consistency. Also add function comments in common.h.

Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:22:18 -04:00
Peng Fan
e872f27a02 imx: mx7: fix build warning when CONFIG_IMX_RDC not enabled
Fix build warning when CONFIG_IMX_RDC not defined in defconfig.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
2017-08-16 12:43:09 +02:00
Peng Fan
9402cafb23 imx: mx6sl: simplify code using setbits_le32
Simplify code by removing set_preclk_from_osc with directly setbits_le32.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
2017-08-16 12:43:09 +02:00
Peng Fan
7236297aee imx: mx6sx: select OSC as uart's clk parent
As M4 is sourcing UART clk from OSC, to make UART work
when M4 is enabled, need to select OSC as clk parent,
24M OSC is enough for debug UART in uboot.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
2017-08-16 12:43:04 +02:00
Peng Fan
79a57b5ae1 imx: mx6: soc: fix mx6sll settings
There is not LDO_SOC/PU/ARM/MMDC1 on i.MX6SLL, also no need to gate/ungate
all PFDs to make PFD working.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
2017-08-16 11:56:22 +02:00
Peng Fan
3d3598d0f6 imx: mx6: select ARM_ERRATA_845369
Select ARM_ERRATA_845369 for i.MX6DQ/DL/QP.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-08-16 11:51:00 +02:00
Peng Fan
11d94319c3 arm: Implement workaround for Cortex-A9 errata 845369
Under very rare timing circumstances, transitioning into streaming
mode might create a data corruption. Present on Two or more processors
or 1 core with ACP, all revisions. This erratum can be worked round
by setting bit[22] of the undocumented Diagnostic Control Register to 1.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-08-16 11:50:51 +02:00
Peng Fan
91435cd40d ARM: i.MX6: exclude the ARM errata from i.MX6 UP system
The ARM errata 751472, 794072, 761320 only applied
to the following configuration:

This erratum affects configurations with either:
- One processor if the ACP is present
- Two or more processors

i.MX6 family does not have the ACP and thus only the MPCore system
will be impacted, which are the i.MX6DQ, i.MX6DL, and i.MX6QP.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
2017-08-16 11:50:40 +02:00
Sébastien Szymanski
0c7c6fb764 imx: imx6ull: correct get_cpu_speed_grade_hz
i.MX6ULL has different speed grades than i.MX6UL.

Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
2017-08-16 11:45:10 +02:00
Sébastien Szymanski
44e670532d imx: imx6ul: correct get_cpu_speed_grade_hz on 696MHz SoCs
Return the correct value when the speed grade is 696MHz.

Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
2017-08-16 11:44:57 +02:00
Breno Lima
6efb613373 mx6sabreauto: Fix IOMUXC_GPR6 and IOMUXC_GPR7 values
The IPU AXI QoS for the i.MX6QP and i.MX6DP processors have to be set as
commented in the code:
/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */

Set IOMUXC_GPR6 and IOMUXC_GPR7 to 0x77177717 instead of 0x007F007F.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
2017-08-16 11:44:18 +02:00
Breno Lima
a500a33115 mx6sabresd: Fix IOMUXC_GPR6 and IOMUXC_GPR7 values
The IPU AXI QoS for the i.MX6QP and i.MX6DP processors have to be set as
commented in the code:
/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */

Set IOMUXC_GPR6 and IOMUXC_GPR7 to 0x77177717 instead of 0x007F007F.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
2017-08-16 11:43:15 +02:00
Anatolij Gustschin
ff3a5fc46d imx6: clock: correct comment for PLL_VIDEO
This appear to be a copy-paste error, clean it up.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-08-16 11:38:27 +02:00
Anatolij Gustschin
557b9b7250 imx6: use SION macro in SDn_CMD mux mode bitfield arguments
Select SION by appropriate macro instead of constant.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-08-16 11:36:05 +02:00
Simon Glass
01510091de env: Drop saveenv() in favour of env_save()
Use the env_save() function directly now that there is only one
implementation of saveenv().

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Denk <wd@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 20:50:30 -04:00
Simon Glass
310fb14b26 env: Drop env_relocate_spec() in favour of env_load()
This is a strange name for a function that loads the environment. There is
now only one implementation of this function, so use the new env_load()
function directly instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 20:50:29 -04:00
Simon Glass
a69d0f60e5 env: Drop env_get_char_spec()
We only have a single implementation of this function now and it is called
env_get_char(). Drop the old function and the weak version.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-15 20:50:29 -04:00
Simon Glass
6eeae42469 env: Drop env_init_new()
Now that env_init() is only defined once we can drop the env_init_new()
name and just use env_init().

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 20:50:29 -04:00
Simon Glass
98b5755fb0 env: Drop unused env_ptr variables
This variable is declared as a global in most environment location
drivers. But it is not used outside the drivers and most of the
declarations are unnecessary.

Also some drivers call free() on env_ptr which seems wrong since it is
not in the heap.

Drop the variable where possible, and all calls to free().

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 20:50:28 -04:00
Simon Glass
ac358beb85 env: Drop the env_name_spec global
Add a name to the driver and use that instead of the global variable
declared by each driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 20:50:28 -04:00
Simon Glass
7938822a6b env: Drop common init() functions
Most of the init() implementations just use the default environment.
Adjust env_init_new() to do this automatically, and drop the redundant
code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 20:50:27 -04:00
Simon Glass
e5bce247b0 env: Switch over to use environment location drivers
Move over to use a the master implementation of the location drivers, with
each method calling out to the appropriate driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 20:50:27 -04:00
Simon Glass
c9d728dd33 env: Add a new implementation of environment access
We plan to move to a environment access via drivers for each location
where the environment can be stored. Add an implementation for this. So
far it is not used, but will be pressed into service in a future patch.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-15 20:50:26 -04:00
Simon Glass
c1c3fe2307 env: Convert CONFIG_ENV_IS_IN... to a choice
At present we support multiple environment drivers but there is not way to
select between them at run time. Also settings related to the position and
size of the environment area are global (i.e. apply to all locations).

Until these limitations are removed we cannot really support more than one
environment location. Adjust the location to be a choice so that only one
can be selected. By default the environment is 'nowhere', meaning that the
environment exists only in memory and cannot be saved.

Also expand the help for the 'nowhere' option and move it to the top since
it is the default.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Move all of the imply logic to default X if Y so it works again]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-15 20:50:01 -04:00
Marcel Ziswiler
33848eb53e apalis_t30/tk1, colibri_t20/t30: fix i2c bus frequencies
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2017-08-15 14:51:18 -07:00
Marcel Ziswiler
8b733af831 apalis-tk1: remove duplicate hdmi_ddc device tree node
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2017-08-15 14:51:18 -07:00
Marcel Ziswiler
ceef960812 dm: tegra: move apalis t30/tk1, colibri t20/t30 to livetree
Change these board to use a live device tree after relocation.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2017-08-15 14:51:18 -07:00
Marcel Ziswiler
9a50b6fc81 apalis_t30: fix usb otg power enable
Fix USB OTG power enable aka USBO1_EN which on Apalis T30 is connected
to the T30 ball GEN2_I2C_SCL.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2017-08-15 14:51:18 -07:00
Simon Glass
4415f1d1f1 env: Create a location driver for each location
Set up a location driver for each supported environment location. At
present this just points to the global functions and is not used. A
later patch will switch this over to use private functions in each driver.

There are several special cases here in various drivers to handle
peculiarities of certain boards:

1. Some boards define CONFIG_ENV_IS_IN_FAT and CONFIG_SPL_ENV_SUPPORT but
do not actually load the environment in SPL. The env load code was
optimised out before but with the driver, it is not. Therefore a special
case is added to env/fat.c. The correct fix (depending on board testing
might be to disable CONFIG_SPL_ENV_SUPPORT.

2. A similar situations happens with CONFIG_ENV_IS_IN_FLASH. Some boards
do not actually load the environment in SPL, so to reduce code size we
need to drop that code. A similar fix may be possible with these boards,
or it may be possible to adjust the environment CONFIG settings.

Added to the above is that the CONFIG_SPL_ENV_SUPPORT option does not
apply when the environment is in flash.

Obviously the above has been discovered through painful and time-consuming
trial and error. Hopefully board maintainers can take a look and figure
out what is actually needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-15 08:18:53 -04:00
Simon Glass
42a8180d19 env: Rename nand env_location to nand_env_location
We want to use this name for all environment drivers. Update the nand
driver to use a more specific name.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 08:18:51 -04:00
Simon Glass
203e94f6c9 env: Add an enum for environment state
At present we have three states for the environment, numbered 0, 1 and 2.
Add an enum to record this to avoid open-coded values.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 08:18:51 -04:00
Simon Glass
75de597d2d env: common: Drop env_get_char_memory()
This function is the same as env_get_char_spec() apart from dropping the
brackets. Drop the brackets from env_get_char_spec() and use that instead
of env_get_char_memory().

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 08:18:47 -04:00
Simon Glass
81a4dea228 env: common: Drop env_get_char_init()
This function does nothing but call env_get_char_spec(). Drop it and
adjust its only caller.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 08:18:47 -04:00
Simon Glass
5fc5254084 env: common: Factor out the common env_valid check
The check for gd->env_valid is used in both the 'if' and 'else' part of
env_get_char(). Move it into that function instead for simplicity. Drop
that code from the two leaf functions.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 08:18:46 -04:00
Simon Glass
0219fb61c1 env: common: Drop env_get_addr()
This function is not used anywhere other than env_get_char(). Move the
code into that function.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-15 08:18:46 -04:00
Simon Glass
bcdfb8d5a5 env: common: Make env_get_addr/get_char_memory() static
These functions are not used outside this file. Make them static and order
them to avoid forward declarations.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 08:18:46 -04:00
Simon Glass
91d3aa05d0 env: Use tabs in ENV_IS_IN_FAT
Tidy up the formatting of this option.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-15 08:18:46 -04:00
Simon Glass
0649cd0d49 Move environment files from common/ to env/
About a quarter of the files in common/ relate to the environment. It
seems better to put these into their own subdirectory and remove the
prefix.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 08:18:45 -04:00
Simon Glass
ec74f5f9c3 Makefile: Rename 'env' target to 'environ'
This target stops us using 'env' as a subdirectory. It is not mentioned in
the help so seems to be an internal target. Rename it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 08:18:42 -04:00
Jagan Teki
585bf8ae6f sun50i: a64: Add A64-OLinuXino initial support
OLimex A64-OLinuXino is an open-source hardware board
using the Allwinner A64 SOC.

OLimex A64-OLinuXino has
- A64 Quad-core Cortex-A53 64bit
- 1GB or 2GB RAM DDR3L @ 672Mhz
- microSD slot and 4/8/16GB eMMC
- Debug TTL UART
- HDMI
- LCD
- IR receiver
- 5V DC power supply

Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-08-15 11:30:59 +05:30
Jagan Teki
f322657204 sun50i: a64: Add initial NanoPi A64 support
NanoPi A64 is a new board of high performance with low cost
designed by FriendlyElec., using the Allwinner A64 SOC.

Nanopi A64 features
- Allwinner A64, 64-bit Quad-core Cortex-A53@648MHz to 1.152GHz, DVFS
- 1GB DDR3 RAM
- MicroSD
- Gigabit Ethernet (RTL8211E)
- Wi-Fi 802.11b/g/n
- IR receiver
- Audio In/Out
- Video In/Out
- Serial Debug Port
- microUSB 5V 2A DC power-supply

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-08-15 11:30:19 +05:30
xypron.glpk@gmx.de
a44bffcc95 efi_loader: use EFI_PAGE_SIZE instead of 4096
We should use constant EFI_PAGE_SIZE instead of 4096 where the
coding relies on 4096 being EFI_PAGE_SIZE.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-08-12 14:06:23 +02:00
xypron.glpk@gmx.de
aee4f06dff efi_loader: use EFI_PAGE_MASK instead of EFI_PAGE_SIZE - 1
We should be consistent in the way we calculate page sizes.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-08-12 14:05:45 +02:00
Jagan Teki
7e4bef711e sun50i: a64: Sync Linux [oe]hci0 nodes
Synced ohci0 and ehci0 nodes from Linux for sun50i-a64.dtsi

Here is the Linux last merge tag details:
Merge: 0e91f43d e5770b7
Author: Stephen Rothwell <sfr@canb.auug.org.au>
Date:   Fri Jun 9 14:59:55 2017 +1000

    Merge remote-tracking branch 'staging/staging-next'

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-08-11 21:51:43 +05:30
Rob Clark
3d9880784e efi_loader: GOP fix for no display
uclass_first_device() returns 0 if there is no device, but error if
there is a device that failed to probe.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-08-11 13:49:23 +02:00
Icenowy Zheng
a8df97d0da sunxi: add MACPWR in Orange Pi PC2 defconfig
The Ethernet function is enabled in the Orange Pi PC2 device tree and
defconfig, however, CONFIG_MACPWR is not properly set, which left the
PHY being disabled when booting, which makes the Ethernet function not
usable.

Add the proper value of this option in the PC2 defconfig.

Fixes: e7bd15ea15 ("sunxi: Add OrangePi PC 2 initial support")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-11 15:53:27 +05:30
Icenowy Zheng
e37a1b17e7 sunxi: switch PRCM to non-secure on H3/H5 SoCs
The PRCM of H3/H5 SoCs have a secure/non-secure switch, which controls
the access to some clock/power related registers in PRCM.

Current Linux kernel will access the CPUS (AR100) clock in the PRCM
block, so the PRCM should be switched to non-secure.

Add code to switch the PRCM to non-secure.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-11 15:49:39 +05:30
Icenowy Zheng
39858b12cc sunxi: add PRCM secure switch register definition
Some new Allwinner SoCs' PRCM has a secure switch register, which
controls the access to some clock and power registers in PRCM block.

Add the definition of this register and its bits in the PRCM header
file.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Tested-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-11 15:49:39 +05:30
Clément Bœsch
8792a64d87 sunxi: reduce Orange Pi Zero DRAM clock speed
Using `fel-boot-lima-memtester-on-orange-pi-pc 672` on an Orange Pi
without heatsink results in the following error after a few minutes:
  WRITE FAILURE: 0x00200000 != 0xffdfffff at offset 0x0137f47c (bitflip).

Also, the constructor repository (github/orangepi-xunlong) seems to
contain that 624 Mhz clock speed in its u-boot fork. It may be that 672
Mhz is the advertized overclocked speed.

According to http://linux-sunxi.org/Orange_Pi_PC#DRAM_clock_speed_limit
it may be worth decreasing that value with other Orange Pi boards.

See also e7d6aa0b74.

Signed-off-by: Clément Bœsch <u@pkh.me>
[Add s-o-b line]
Signed-off-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-11 15:43:44 +05:30
Olliver Schinagl
335d30050b sun7i: Add support for Olimex A20-OLinuXino-LIME2-eMMC
This patch adds support for the Olimex OLinuXino Lime2 with eMMC flash
storage.
https://www.olimex.com/Products/OLinuXino/A20/A20-OLinuXino-LIME2-eMMC/

It is a assembly variant of the regular Lime2 but featuring eMMC for
storage.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-11 15:16:39 +05:30
Emmanuel Vadot
fb7fe04da2 ARM: dts: sunxi: Change node name for pwrseq pin on Olinuxino-lime2-emmc
The node name for the power seq pin is mmc2@0 like the mmc2_pins_a one.
This makes the original node (mmc2_pins_a) scrapped out of the dtb and
result in a unusable eMMC if U-Boot didn't configured the pins to the
correct functions.

Signed-off-by: Emmanuel Vadot <manu@bidouilliste.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-11 15:16:39 +05:30
Rob Clark
796a78cbe5 efi_loader: LocateHandle should return EFI_NOT_FOUND if none found
Spotted this debugging OpenBSD's bootloader in qemu.  (Wouldn't really
fix anything, the problem was not having any disks, but we should
probably return the correct error code.)

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-08-11 11:08:33 +02:00
xypron.glpk@gmx.de
ebf199b92f efi_loader: attribute EFIAPI of efi_locate handle()
efi_locate_handle is called internally so it should not be
marked as EFIAPI.

The external function is efi_locate_handle_ext.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2017-08-11 10:57:10 +02:00
Wenyou.Yang@microchip.com
8fc2faefdd mtd: spi: sf_dataflash: Add print message while erase error
Add the print message to tell us why the erase operation doesn't work.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-08 12:34:27 +05:30
Bin Meng
ac6777b1e3 sf: Add Macronix MX25U6435F device parameters
This adds support for Macronix flash MX25U6435F (device ID 0xc22537).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-08 12:26:05 +05:30
Stefano Babic
83605d37b0 mx6: Add support for Phytec pfla02 (NAND)
Add support for Phytec pfla02, equipped with NAND.

CPU:   Freescale i.MX6Q rev1.5 996 MHz (running at 792 MHz)
CPU:   Automotive temperature grade (-40C to 125C) at 31C
Reset cause: POR
I2C:   ready
DRAM:  1 GiB
NAND:  2048 MiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
SF: Detected n25q128 with page size 256 Bytes, erase size 64 KiB, total
16 MiB
In:    serial
Out:   serial
Err:   serial
Net:   FEC [PRIME]
Hit any key to stop autoboot:  0

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Stefan Christ <s.christ@phytec.de>
CC: Stefan Müller-Klieser <S.Mueller-Klieser@phytec.de>
CC: Christian Hemp <C.Hemp@phytec.de>
2017-08-02 11:45:27 +02:00
Vagrant Cascadian
3b22599e1a arm: imx: Enable booting from SATA on wandboard.
Enable booting from SATA on the wandboard.

Sata support was already enabled, but distro_bootcmd is not configured
to boot from it.

Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-28 13:44:54 +02:00
Lothar Waßmann
cb5761f774 net: fec_mxc: adjust prototype of fec_get_miibus() for DM_ETH
commit 306dd7dabd ("net: fec_mxc: fix PHY initialization bug with CONFIG_DM_ETH")
has broken the build of the fec_mxc driver with CONFIG_DM_ETH
enabled because it changed the parameters passed to *fec_get_miibus()
without changing the functions prototype.

This patch fixes up the prototype of fec_get_miibus() for the DM_ETH case.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
2017-07-28 13:41:49 +02:00
3483 changed files with 118999 additions and 30966 deletions

View File

@@ -29,9 +29,6 @@ addons:
- device-tree-compiler
install:
# install latest device tree compiler
#- git clone --depth=1 git://git.kernel.org/pub/scm/utils/dtc/dtc.git /tmp/dtc
#- make -j4 -C /tmp/dtc
# Clone uboot-test-hooks
- git clone --depth=1 git://github.com/swarren/uboot-test-hooks.git /tmp/uboot-test-hooks
- ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
@@ -52,7 +49,7 @@ install:
env:
global:
- PATH=/tmp/dtc:/tmp/qemu-install/bin:/tmp/uboot-test-hooks/bin:$PATH
- PATH=/tmp/qemu-install/bin:/tmp/uboot-test-hooks/bin:/usr/bin:/bin
- PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci
- BUILD_DIR=build
- HOSTCC="cc"
@@ -140,6 +137,12 @@ matrix:
- BUILDMAN="atmel"
- env:
- BUILDMAN="aries"
- env:
- JOB="Boundary Devices"
BUILDMAN="boundary"
- env:
- JOB="engicam"
BUILDMAN="engicam"
- env:
- JOB="Freescale ARM32"
BUILDMAN="freescale -x powerpc,m68k,aarch64"
@@ -148,12 +151,16 @@ matrix:
BUILDMAN="freescale&aarch64"
- env:
- JOB="i.MX6 (non-Freescale)"
BUILDMAN="mx6 -x freescale"
BUILDMAN="mx6 -x freescale,toradex,boundary,engicam"
- env:
- JOB="i.MX (non-Freescale, non-i.MX6)"
BUILDMAN="mx -x freescale,mx6"
BUILDMAN="mx -x freescale,mx6,toradex"
- env:
- BUILDMAN="k2"
- env:
- BUILDMAN="samsung"
- env:
- BUILDMAN="socfpga"
- env:
- BUILDMAN="sun4i"
- env:
@@ -170,16 +177,19 @@ matrix:
- BUILDMAN="sun50i"
- env:
- JOB="Catch-all ARM"
BUILDMAN="arm -x arm11,arm7,arm9,aarch64,atmel,aries,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap3,omap4,omap5,pxa,rockchip"
BUILDMAN="arm -x arm11,arm7,arm9,aarch64,atmel,aries,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap3,omap4,omap5,pxa,rockchip,toradex,socfpga,k2,xilinx"
- env:
- BUILDMAN="sandbox x86"
TOOLCHAIN="x86_64"
- env:
- BUILDMAN="toradex"
- env:
- BUILDMAN="kirkwood"
- env:
- BUILDMAN="mvebu"
- env:
- BUILDMAN="pxa"
- JOB="PXA"
- BUILDMAN="pxa -x toradex"
- env:
- BUILDMAN="m68k"
TOOLCHAIN="m68k"
@@ -210,7 +220,8 @@ matrix:
- env:
- BUILDMAN="siemens"
- env:
- BUILDMAN="tegra"
- JOB="tegra"
BUILDMAN="tegra -x toradex"
- env:
- JOB="am33xx"
BUILDMAN="am33xx -x siemens"
@@ -223,12 +234,16 @@ matrix:
- env:
- BUILDMAN="uniphier"
- env:
- BUILDMAN="aarch64 -x tegra,freescale,mvebu,uniphier,sunxi,samsung,rockchip"
- JOB="aarch64"
BUILDMAN="aarch64 -x tegra,freescale,mvebu,uniphier,sunxi,samsung,rockchip"
- env:
- BUILDMAN="rockchip"
- env:
- BUILDMAN="sh4"
TOOLCHAIN="sh4"
- env:
- JOB="Xilinx (ARM)"
BUILDMAN="xilinx -x microblaze"
- env:
- BUILDMAN="xtensa"
TOOLCHAIN="xtensa"
@@ -288,6 +303,11 @@ matrix:
TEST_PY_ID="--id qemu"
QEMU_TARGET="arm-softmmu"
BUILDMAN="^integratorcp_cm926ejs$"
- env:
- TEST_PY_BD="qemu_arm"
TEST_PY_TEST_SPEC="not sleep"
QEMU_TARGET="arm-softmmu"
BUILDMAN="^qemu_arm$"
- env:
- TEST_PY_BD="qemu_mips"
TEST_PY_TEST_SPEC="not sleep"

28
Kconfig
View File

@@ -14,6 +14,12 @@ source "arch/Kconfig"
menu "General setup"
config BROKEN
bool
help
This option cannot be enabled. It is used as dependency
for broken and incomplete features.
config LOCALVERSION
string "Local version - append to U-Boot release"
help
@@ -158,10 +164,26 @@ config PHYS_64BIT
This can be used not only for 64bit SoCs, but also for
large physical address extention on 32bit SoCs.
config BUILD_ROM
bool "Build U-Boot as BIOS replacement"
depends on X86
help
This option allows to build a ROM version of U-Boot.
The build process generally requires several binary blobs
which are not shipped in the U-Boot source tree.
Please, see doc/README.x86 for details.
endmenu # General setup
menu "Boot images"
config ANDROID_BOOT_IMAGE
bool "Enable support for Android Boot Images"
default y if FASTBOOT
help
This enables support for booting images which use the Android
image format header.
config FIT
bool "Support Flattened Image Tree"
select MD5
@@ -266,7 +288,7 @@ config SPL_LOAD_FIT
config SPL_FIT_IMAGE_POST_PROCESS
bool "Enable post-processing of FIT artifacts after loading by the SPL"
depends on SPL_LOAD_FIT && TI_SECURE_DEVICE
depends on SPL_LOAD_FIT
help
Allows doing any sort of manipulation to blobs after they got extracted
from the U-Boot FIT image like stripping off headers or modifying the
@@ -380,6 +402,8 @@ source "disk/Kconfig"
source "dts/Kconfig"
source "env/Kconfig"
source "net/Kconfig"
source "drivers/Kconfig"
@@ -389,5 +413,3 @@ source "fs/Kconfig"
source "lib/Kconfig"
source "test/Kconfig"
source "scripts/Kconfig"

View File

@@ -259,8 +259,9 @@ EFI PAYLOAD
M: Alexander Graf <agraf@suse.de>
S: Maintained
T: git git://github.com/agraf/u-boot.git
F: include/efi_loader.h
F: lib/efi_loader/
F: include/efi*
F: lib/efi*
F: test/py/tests/test_efi*
F: cmd/bootefi.c
FLATTENED DEVICE TREE
@@ -419,6 +420,7 @@ F: arch/arm/mach-omap2/omap5/sec-fxns.c
F: arch/arm/mach-omap2/sec-common.c
F: arch/arm/mach-omap2/config_secure.mk
F: configs/am335x_hs_evm_defconfig
F: configs/am335x_hs_evm_uart_defconfig
F: configs/am43xx_hs_evm_defconfig
F: configs/am57xx_hs_evm_defconfig
F: configs/dra7xx_hs_evm_defconfig
@@ -449,6 +451,8 @@ M: Anatolij Gustschin <agust@denx.de>
S: Maintained
T: git git://git.denx.de/u-boot-video.git
F: drivers/video/
F: common/lcd*.c
F: include/lcd*.h
X86
M: Simon Glass <sjg@chromium.org>

View File

@@ -3,9 +3,9 @@
#
VERSION = 2017
PATCHLEVEL = 09
PATCHLEVEL = 11
SUBLEVEL =
EXTRAVERSION = -rc2
EXTRAVERSION =
NAME =
# *DOCUMENTATION*
@@ -349,7 +349,7 @@ OBJDUMP = $(CROSS_COMPILE)objdump
AWK = awk
PERL = perl
PYTHON ?= python
DTC ?= dtc
DTC ?= $(objtree)/scripts/dtc/dtc
CHECK = sparse
CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
@@ -360,6 +360,7 @@ KBUILD_CPPFLAGS := -D__KERNEL__ -D__UBOOT__
KBUILD_CFLAGS := -Wall -Wstrict-prototypes \
-Wno-format-security \
-fno-builtin -ffreestanding
KBUILD_CFLAGS += -fshort-wchar
KBUILD_AFLAGS := -D__ASSEMBLY__
# Read UBOOTRELEASE from include/config/uboot.release (if it exists)
@@ -690,6 +691,7 @@ libs-y += drivers/usb/phy/
libs-y += drivers/usb/ulpi/
libs-y += cmd/
libs-y += common/
libs-y += env/
libs-$(CONFIG_API) += api/
libs-$(CONFIG_HAS_POST) += post/
libs-y += test/
@@ -794,7 +796,7 @@ ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf
ALL-$(CONFIG_EFI_APP) += u-boot-app.efi
ALL-$(CONFIG_EFI_STUB) += u-boot-payload.efi
ifneq ($(BUILD_ROM),)
ifneq ($(BUILD_ROM)$(CONFIG_BUILD_ROM),)
ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
endif
@@ -870,13 +872,13 @@ endif
PHONY += dtbs
dtbs: dts/dt.dtb
@:
dts/dt.dtb: checkdtc u-boot
dts/dt.dtb: u-boot
$(Q)$(MAKE) $(build)=dts dtbs
quiet_cmd_copy = COPY $@
cmd_copy = cp $< $@
ifeq ($(CONFIG_FIT_EMBED),y)
ifeq ($(CONFIG_MULTI_DTB_FIT),y)
fit-dtb.blob: dts/dt.dtb FORCE
$(call if_changed,mkimage)
@@ -1378,7 +1380,7 @@ $(timestamp_h): $(srctree)/Makefile FORCE
$(call filechk,timestamp.h)
checkbinman: tools
@if ! ( echo 'import libfdt' | ( PYTHONPATH=tools python )); then \
@if ! ( echo 'import libfdt' | ( PYTHONPATH=tools $(PYTHON) )); then \
echo >&2; \
echo >&2 '*** binman needs the Python libfdt library.'; \
echo >&2 '*** Either install it on your system, or try:'; \
@@ -1445,12 +1447,6 @@ SYSTEM_MAP = \
System.map: u-boot
@$(call SYSTEM_MAP,$<) > $@
checkdtc:
@if test $(call dtc-version) -lt 0104; then \
echo '*** Your dtc is too old, please upgrade to dtc 1.4 or newer'; \
false; \
fi
#########################################################################
# ARM relocations should all be R_ARM_RELATIVE (32-bit) or
@@ -1464,14 +1460,14 @@ checkarmreloc: u-boot
false; \
fi
env: scripts_basic
$(Q)$(MAKE) $(build)=tools/$@
envtools: scripts_basic
$(Q)$(MAKE) $(build)=tools/env
tools-only: scripts_basic $(version_h) $(timestamp_h)
$(Q)$(MAKE) $(build)=tools
tools-all: export HOST_TOOLS_ALL=y
tools-all: env tools ;
tools-all: envtools tools ;
cross_tools: export CROSS_BUILD_TOOLS=y
cross_tools: tools ;
@@ -1585,6 +1581,7 @@ help:
@echo ' ubootrelease - Output the release version string (use with make -s)'
@echo ' ubootversion - Output the version stored in Makefile (use with make -s)'
@echo " cfg - Don't build, just create the .cfg files"
@echo " envtools - Build only the target-side environment tools"
@echo ''
@echo 'Static analysers'
@echo ' checkstack - Generate a list of stack hogs'

93
README
View File

@@ -312,6 +312,19 @@ Many of the options are named exactly as the corresponding Linux
kernel configuration options. The intention is to make it easier to
build a config tool - later.
- ARM Platform Bus Type(CCI):
CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
provides full cache coherency between two clusters of multi-core
CPUs and I/O coherency for devices and I/O masters
CONFIG_SYS_FSL_HAS_CCI400
Defined For SoC that has cache coherent interconnect
CCN-400
CONFIG_SYS_FSL_HAS_CCN504
Defined for SoC that has cache coherent interconnect CCN-504
The following options need to be configured:
@@ -404,12 +417,6 @@ The following options need to be configured:
supported, core will start to execute uboot when wakes up.
- Generic CPU options:
CONFIG_SYS_GENERIC_GLOBAL_DATA
Defines global data is initialized in generic board board_init_f().
If this macro is defined, global data is created and cleared in
generic board board_init_f(). Without this macro, architecture/board
should initialize global data before calling board_init_f().
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
Defines the endianess of the CPU. Implementation of those
@@ -782,7 +789,7 @@ The following options need to be configured:
binary in its image. This device tree file should be in the
board directory and called <soc>-<board>.dts. The binary file
is then picked up in board_init_f() and made available through
the global data structure as gd->blob.
the global data structure as gd->fdt_blob.
CONFIG_OF_SEPARATE
If this variable is defined, U-Boot will build a device tree
@@ -1021,21 +1028,6 @@ The following options need to be configured:
control registers. This behavior won't affect the
correctnessof 10/100 link speed update.
CONFIG_SMC911X
Support for SMSC's LAN911x and LAN921x chips
CONFIG_SMC911X_BASE
Define this to hold the physical address
of the device (I/O space)
CONFIG_SMC911X_32_BIT
Define this if data bus is 32 bits
CONFIG_SMC911X_16_BIT
Define this if data bus is 16 bits. If your processor
automatically converts one 32 bit word to two 16 bit
words you may also try CONFIG_SMC911X_32_BIT.
CONFIG_SH_ETHER
Support for Renesas on-chip Ethernet controller
@@ -1248,50 +1240,6 @@ The following options need to be configured:
entering dfuMANIFEST state. Host waits this timeout, before
sending again an USB request to the device.
- USB Device Android Fastboot support:
CONFIG_USB_FUNCTION_FASTBOOT
This enables the USB part of the fastboot gadget
CONFIG_ANDROID_BOOT_IMAGE
This enables support for booting images which use the Android
image format header.
CONFIG_FASTBOOT_BUF_ADDR
The fastboot protocol requires a large memory buffer for
downloads. Define this to the starting RAM address to use for
downloaded images.
CONFIG_FASTBOOT_BUF_SIZE
The fastboot protocol requires a large memory buffer for
downloads. This buffer should be as large as possible for a
platform. Define this to the size available RAM for fastboot.
CONFIG_FASTBOOT_FLASH
The fastboot protocol includes a "flash" command for writing
the downloaded image to a non-volatile storage device. Define
this to enable the "fastboot flash" command.
CONFIG_FASTBOOT_FLASH_MMC_DEV
The fastboot "flash" command requires additional information
regarding the non-volatile storage device. Define this to
the eMMC device that fastboot should use to store the image.
CONFIG_FASTBOOT_GPT_NAME
The fastboot "flash" command supports writing the downloaded
image to the Protective MBR and the Primary GUID Partition
Table. (Additionally, this downloaded image is post-processed
to generate and write the Backup GUID Partition Table.)
This occurs when the specified "partition name" on the
"fastboot flash" command line matches this value.
The default is "gpt" if undefined.
CONFIG_FASTBOOT_MBR_NAME
The fastboot "flash" command supports writing the downloaded
image to DOS MBR.
This occurs when the "partition name" specified on the
"fastboot flash" command line matches this value.
If not defined the default value "mbr" is used.
- Journaling Flash filesystem support:
CONFIG_JFFS2_NAND
Define these for a default partition on a NAND device
@@ -2349,13 +2297,6 @@ The following options need to be configured:
this is instead controlled by the value of
/config/load-environment.
- DataFlash Support:
CONFIG_HAS_DATAFLASH
Defining this option enables DataFlash features and
allows to read/write in Dataflash via the standard
commands cp, md...
- Serial Flash support
Usage requires an initial 'sf probe' to define the serial
flash parameters, followed by read/write/erase/update
@@ -2885,10 +2826,6 @@ FIT uImage format:
Define this if you need to first read the OOB and then the
data. This is used, for example, on davinci platforms.
CONFIG_SPL_OMAP3_ID_NAND
Support for an OMAP3-specific set of functions to return the
ID and MFR of the first attached NAND chip, if present.
CONFIG_SPL_RAM_DEVICE
Support for running image already present in ram, in SPL binary
@@ -3286,7 +3223,7 @@ but it can not erase, write this NOR flash by SRIO or PCIE interface.
Please note that the environment is read-only until the monitor
has been relocated to RAM and a RAM copy of the environment has been
created; also, when using EEPROM you will have to use getenv_f()
created; also, when using EEPROM you will have to use env_get_f()
until then to read environment variables.
The environment is protected by a CRC32 checksum. Before the monitor

View File

@@ -458,7 +458,7 @@ static int API_env_get(va_list ap)
if ((value = (char **)va_arg(ap, uintptr_t)) == NULL)
return API_EINVAL;
*value = getenv(name);
*value = env_get(name);
return 0;
}
@@ -481,7 +481,7 @@ static int API_env_set(va_list ap)
if ((value = (char *)va_arg(ap, uintptr_t)) == NULL)
return API_EINVAL;
setenv(name, value);
env_set(name, value);
return 0;
}
@@ -663,7 +663,7 @@ void api_init(void)
return;
}
setenv_hex("api_address", (unsigned long)sig);
env_set_hex("api_address", (unsigned long)sig);
debugf("API sig @ 0x%lX\n", (unsigned long)sig);
memcpy(sig->magic, API_SIG_MAGIC, 8);
sig->version = API_SIG_VERSION;

View File

@@ -112,8 +112,12 @@ config X86
imply CMD_GETTIME
imply CMD_IO
imply CMD_IRQ
imply CMD_PCI
imply CMD_SF_TEST
imply CMD_ZBOOT
imply USB_HOST_ETHER
imply USB_ETHER_ASIX
imply USB_ETHER_SMSC95XX
config XTENSA
bool "Xtensa architecture"

View File

@@ -50,30 +50,6 @@
#define __iowmb() do { } while (0)
#endif
/*
* Given a physical address and a length, return a virtual address
* that can be used to access the memory range with the caching
* properties specified by "flags".
*/
#define MAP_NOCACHE (0)
#define MAP_WRCOMBINE (0)
#define MAP_WRBACK (0)
#define MAP_WRTHROUGH (0)
static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
return (void *)((unsigned long)paddr);
}
/*
* Take down a mapping set up by map_physmem().
*/
static inline void unmap_physmem(void *vaddr, unsigned long flags)
{
}
static inline void sync(void)
{
/* Not yet implemented */
@@ -302,9 +278,6 @@ static inline int __raw_writesl(unsigned int addr, void *data, int longlen)
#define setbits_8(addr, set) setbits(8, addr, set)
#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
static inline phys_addr_t virt_to_phys(void *vaddr)
{
return (phys_addr_t)((unsigned long)vaddr);
}
#include <asm-generic/io.h>
#endif /* __ASM_ARC_IO_H */

View File

@@ -85,7 +85,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
r2 = (unsigned int)images->ft_addr;
} else {
r0 = 1;
r2 = (unsigned int)getenv("bootargs");
r2 = (unsigned int)env_get("bootargs");
}
smp_set_core_boot_addr((unsigned long)kernel_entry, -1);

View File

@@ -97,6 +97,9 @@ config ARM_ERRATA_833069
config ARM_ERRATA_833471
bool
config ARM_ERRATA_845369
bool
config ARM_ERRATA_852421
bool
@@ -338,17 +341,6 @@ config TARGET_WORK_92105
select CPU_ARM926EJS
select SUPPORT_SPL
config TARGET_MX25PDK
bool "Support mx25pdk"
select BOARD_LATE_INIT
select CPU_ARM926EJS
select BOARD_EARLY_INIT_F
config TARGET_ZMX25
bool "Support zmx25"
select BOARD_LATE_INIT
select CPU_ARM926EJS
config TARGET_APF27
bool "Support apf27"
select CPU_ARM926EJS
@@ -493,7 +485,6 @@ config ARCH_BCM283X
select DM_GPIO
select OF_CONTROL
imply FAT_WRITE
imply ENV_IS_IN_FAT
config TARGET_VEXPRESS_CA15_TC2
bool "Support vexpress_ca15_tc2"
@@ -586,6 +577,7 @@ config ARCH_OMAP2PLUS
bool "TI OMAP2+"
select CPU_V7
select SPL_BOARD_INIT if SPL
select SPL_STACK_R if SPL
select SUPPORT_SPL
imply FIT
@@ -596,6 +588,10 @@ config ARCH_MESON
targeted at media players and tablet computers. We currently
support the S905 (GXBaby) 64-bit SoC.
config ARCH_MX25
bool "NXP MX25"
select CPU_ARM926EJS
config ARCH_MX7ULP
bool "NXP MX7ULP"
select CPU_V7
@@ -628,6 +624,14 @@ config ARCH_MX5
select CPU_V7
select BOARD_EARLY_INIT_F
config ARCH_QEMU
bool "QEMU Virtual Platform"
select CPU_V7
select ARCH_SUPPORT_PSCI
select DM
select DM_SERIAL
select OF_CONTROL
config ARCH_RMOBILE
bool "Renesas ARM SoCs"
select DM
@@ -687,10 +691,12 @@ config ARCH_SUNXI
select SPL_SYS_MALLOC_SIMPLE if SPL
select SYS_NS16550
select SPL_SYS_THUMB_BUILD if !ARM64
select SYS_THUMB_BUILD if !ARM64
select USB if DISTRO_DEFAULTS
select USB_STORAGE if DISTRO_DEFAULTS
select USB_KEYBOARD if DISTRO_DEFAULTS
select USE_TINY_PRINTF
imply CMD_GPT
imply FAT_WRITE
imply PRE_CONSOLE_BUFFER
imply SPL_GPIO_SUPPORT
@@ -700,6 +706,7 @@ config ARCH_SUNXI
imply SPL_MMC_SUPPORT if MMC
imply SPL_POWER_SUPPORT
imply SPL_SERIAL_SUPPORT
imply USB_GADGET
config TARGET_TS4600
bool "Support TS4600"
@@ -726,7 +733,6 @@ config ARCH_ZYNQ
select DM_GPIO
select SPL_DM if SPL
select DM_MMC
select DM_MMC_OPS
select DM_SPI
select DM_SERIAL
select DM_SPI_FLASH
@@ -804,6 +810,19 @@ config TARGET_LS2080A_SIMU
development platform that supports the QorIQ LS2080A
Layerscape Architecture processor.
config TARGET_LS1088AQDS
bool "Support ls1088aqds"
select ARCH_LS1088A
select ARM64
select ARMV8_MULTIENTRY
select ARCH_MISC_INIT
select BOARD_LATE_INIT
help
Support for NXP LS1088AQDS platform
The LS1088A Development System (QDS) is a high-performance
development platform that supports the QorIQ LS1088A
Layerscape Architecture processor.
config TARGET_LS2080AQDS
bool "Support ls2080aqds"
select ARCH_LS2080A
@@ -905,6 +924,19 @@ config TARGET_LS1012AFRDM
development platform that supports the QorIQ LS1012A
Layerscape Architecture processor.
config TARGET_LS1088ARDB
bool "Support ls1088ardb"
select ARCH_LS1088A
select ARM64
select ARMV8_MULTIENTRY
select ARCH_MISC_INIT
select BOARD_LATE_INIT
help
Support for NXP LS1088ARDB platform.
The LS1088A Reference design board (RDB) is a high-performance
development platform that supports the QorIQ LS1088A
Layerscape Architecture processor.
config TARGET_LS1021AQDS
bool "Support ls1021aqds"
select BOARD_LATE_INIT
@@ -1020,7 +1052,6 @@ config TARGET_COLIBRI_PXA270
config ARCH_UNIPHIER
bool "Socionext UniPhier SoCs"
select BOARD_LATE_INIT
select CLK_UNIPHIER
select DM
select DM_GPIO
select DM_I2C
@@ -1039,7 +1070,6 @@ config ARCH_UNIPHIER
select SPL_PINCTRL if SPL
select SUPPORT_SPL
imply FAT_WRITE
imply ENV_IS_IN_MMC
help
Support for UniPhier SoC family developed by Socionext Inc.
(formerly, System LSI Business Division of Panasonic Corporation)
@@ -1075,14 +1105,20 @@ config ARCH_ROCKCHIP
select DM_GPIO
select DM_I2C
select DM_MMC
select DM_MMC_OPS
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
select DM_USB if USB
select DM_PWM
select DM_REGULATOR
imply CMD_FASTBOOT
imply FASTBOOT
imply FAT_WRITE
imply USB_FUNCTION_FASTBOOT
imply SPL_SYSRESET
imply TPL_SYSRESET
imply ADC
imply SARADC_ROCKCHIP
config TARGET_THUNDERX_88XX
bool "Support ThunderX 88xx"
@@ -1119,6 +1155,8 @@ source "arch/arm/mach-mvebu/Kconfig"
source "arch/arm/cpu/armv7/ls102xa/Kconfig"
source "arch/arm/mach-imx/mx2/Kconfig"
source "arch/arm/mach-imx/mx7ulp/Kconfig"
source "arch/arm/mach-imx/mx7/Kconfig"
@@ -1137,6 +1175,8 @@ source "arch/arm/mach-rmobile/Kconfig"
source "arch/arm/mach-meson/Kconfig"
source "arch/arm/mach-qemu/Kconfig"
source "arch/arm/mach-rockchip/Kconfig"
source "arch/arm/mach-s5pc1xx/Kconfig"
@@ -1187,6 +1227,7 @@ source "board/creative/xfi3/Kconfig"
source "board/freescale/ls2080a/Kconfig"
source "board/freescale/ls2080aqds/Kconfig"
source "board/freescale/ls2080ardb/Kconfig"
source "board/freescale/ls1088a/Kconfig"
source "board/freescale/ls1021aqds/Kconfig"
source "board/freescale/ls1043aqds/Kconfig"
source "board/freescale/ls1021atwr/Kconfig"
@@ -1198,7 +1239,6 @@ source "board/freescale/ls1012aqds/Kconfig"
source "board/freescale/ls1012ardb/Kconfig"
source "board/freescale/ls1012afrdm/Kconfig"
source "board/freescale/mx23evk/Kconfig"
source "board/freescale/mx25pdk/Kconfig"
source "board/freescale/mx28evk/Kconfig"
source "board/freescale/mx31ads/Kconfig"
source "board/freescale/mx31pdk/Kconfig"
@@ -1224,7 +1264,6 @@ source "board/spear/spear320/Kconfig"
source "board/spear/spear600/Kconfig"
source "board/spear/x600/Kconfig"
source "board/st/stv0991/Kconfig"
source "board/syteco/zmx25/Kconfig"
source "board/tcl/sl50/Kconfig"
source "board/birdland/bav335x/Kconfig"
source "board/timll/devkit3250/Kconfig"

View File

@@ -16,6 +16,8 @@ obj-$(CONFIG_DDR_MT47H64M16) += spr600_mt47h64m16_3_333_cl5_psync.o
obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o
obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_37e_166_cl4_sync.o
obj-$(CONFIG_DDR_MT47H128M8) += spr600_mt47h128m8_3_266_cl5_async.o
else
obj-y += spr_misc.o spr_lowlevel_init.o
endif
extra-$(CONFIG_SPL_BUILD) := start.o

View File

@@ -84,7 +84,7 @@ int print_cpuinfo(void)
}
#endif
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_ECC_BCH)
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_ECC_BCH) && defined(CONFIG_NAND_FSMC)
static int do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
{

View File

@@ -53,15 +53,15 @@ int misc_init_r(void)
#if defined(CONFIG_CMD_NET)
uchar mac_id[6];
if (!eth_getenv_enetaddr("ethaddr", mac_id) && !i2c_read_mac(mac_id))
eth_setenv_enetaddr("ethaddr", mac_id);
if (!eth_env_get_enetaddr("ethaddr", mac_id) && !i2c_read_mac(mac_id))
eth_env_set_enetaddr("ethaddr", mac_id);
#endif
setenv("verify", "n");
env_set("verify", "n");
#if defined(CONFIG_SPEAR_USBTTY)
setenv("stdin", "usbtty");
setenv("stdout", "usbtty");
setenv("stderr", "usbtty");
env_set("stdin", "usbtty");
env_set("stdout", "usbtty");
env_set("stderr", "usbtty");
#ifndef CONFIG_SYS_NO_DCACHE
dcache_enable();

View File

@@ -2,9 +2,14 @@ config ARCH_LS1021A
bool
select SYS_FSL_ERRATUM_A008378
select SYS_FSL_ERRATUM_A008407
select SYS_FSL_ERRATUM_A008997
select SYS_FSL_ERRATUM_A009007
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009663
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_HAS_CCI400
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -49,9 +54,40 @@ config SECURE_BOOT
Enable Freescale Secure Boot feature. Normally selected
by defconfig. If unsure, do not change.
config SYS_CCI400_OFFSET
hex "Offset for CCI400 base"
depends on SYS_FSL_HAS_CCI400
default 0x180000
help
Offset for CCI400 base.
CCI400 base addr = CCSRBAR + CCI400_OFFSET
config SYS_FSL_ERRATUM_A008997
bool
help
Workaround for USB PHY erratum A008997
config SYS_FSL_ERRATUM_A009007
bool
help
Workaround for USB PHY erratum A009007
config SYS_FSL_ERRATUM_A009008
bool
help
Workaround for USB PHY erratum A009008
config SYS_FSL_ERRATUM_A009798
bool
help
Workaround for USB PHY erratum A009798
config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315"
config SYS_FSL_HAS_CCI400
bool
config SYS_FSL_SRDS_1
bool

View File

@@ -60,6 +60,50 @@ unsigned int get_soc_major_rev(void)
return major;
}
static void erratum_a009008(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
clrsetbits_be32(scfg + SCFG_USB3PRM1CR / 4,
0xF << 6,
SCFG_USB_TXVREFTUNE << 6);
#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
}
static void erratum_a009798(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
clrbits_be32(scfg + SCFG_USB3PRM1CR / 4,
SCFG_USB_SQRXTUNE_MASK << 23);
#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
}
static void erratum_a008997(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
clrsetbits_be32(scfg + SCFG_USB3PRM2CR / 4,
SCFG_USB_PCSTXSWINGFULL_MASK,
SCFG_USB_PCSTXSWINGFULL_VAL);
#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
}
static void erratum_a009007(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A009007
void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE;
out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1);
out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2);
out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3);
out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4);
#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
}
void s_init(void)
{
}
@@ -80,7 +124,8 @@ void erratum_a010315(void)
int arch_soc_init(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
unsigned int major;
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
@@ -146,6 +191,12 @@ int arch_soc_init(void)
*/
out_be32(&scfg->eddrtqcfg, 0x63b20042);
/* Erratum */
erratum_a009008();
erratum_a009798();
erratum_a008997();
erratum_a009007();
return 0;
}

View File

@@ -187,6 +187,12 @@ ENTRY(cpu_init_cp15)
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_845369
mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
orr r0, r0, #1 << 22 @ set bit #22
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
#endif
mov r5, lr @ Store my Caller
mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR)
mov r3, r1, lsr #20 @ get variant field

View File

@@ -1,6 +1,6 @@
#
# (C) Copyright 2014
# Vikas Manocha, ST Microelectronics, vikas.manocha@stcom
# Copyright (C) 2014, STMicroelectronics - All Rights Reserved
# Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
#
# SPDX-License-Identifier: GPL-2.0+
#

View File

@@ -1,6 +1,6 @@
/*
* (C) Copyright 2014
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@@ -1,6 +1,6 @@
/*
* (C) Copyright 2014
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@@ -1,6 +1,6 @@
/*
* (C) Copyright 2014
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@@ -1,6 +1,6 @@
/*
* (C) Copyright 2014
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@@ -329,7 +329,7 @@ int arch_misc_init(void)
strcpy(soc, "vf");
strcat(soc, soc_type);
setenv("soc", soc);
env_set("soc", soc);
return 0;
}

View File

@@ -1,6 +1,6 @@
/*
* (C) Copyright 2017
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@@ -1,6 +1,6 @@
/*
* (C) Copyright 2017
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@@ -88,6 +88,7 @@ config PSCI_RESET
depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && !TARGET_LS2080A_EMU && \
!TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \
!TARGET_LS2080ARDB && !TARGET_LS1012AQDS && \
!TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \
!TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
!TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \

View File

@@ -16,8 +16,12 @@ config ARCH_LS1043A
select SYS_FSL_DDR_BE
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008850
select SYS_FSL_ERRATUM_A008997
select SYS_FSL_ERRATUM_A009007
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009660
select SYS_FSL_ERRATUM_A009663
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A009929
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
@@ -39,6 +43,10 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A008336
select SYS_FSL_ERRATUM_A008511
select SYS_FSL_ERRATUM_A008850
select SYS_FSL_ERRATUM_A008997
select SYS_FSL_ERRATUM_A009007
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A009801
select SYS_FSL_ERRATUM_A009803
select SYS_FSL_ERRATUM_A009942
@@ -50,6 +58,33 @@ config ARCH_LS1046A
select BOARD_EARLY_INIT_F
imply SCSI
config ARCH_LS1088A
bool
select ARMV8_SET_SMPEN
select FSL_LSCH3
select SYS_FSL_DDR
select SYS_FSL_DDR_LE
select SYS_FSL_DDR_VER_50
select SYS_FSL_EC1
select SYS_FSL_EC2
select SYS_FSL_ERRATUM_A009803
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A008511
select SYS_FSL_ERRATUM_A008850
select SYS_FSL_ERRATUM_A009007
select SYS_FSL_HAS_CCI400
select SYS_FSL_HAS_DDR4
select SYS_FSL_HAS_RGMII
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_LE
select SYS_FSL_SRDS_1
select SYS_FSL_SRDS_2
select FSL_TZASC_1
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
config ARCH_LS2080A
bool
select ARMV8_SET_SMPEN
@@ -61,6 +96,7 @@ config ARCH_LS2080A
select SYS_FSL_DDR
select SYS_FSL_DDR_LE
select SYS_FSL_DDR_VER_50
select SYS_FSL_HAS_CCN504
select SYS_FSL_HAS_DP_DDR
select SYS_FSL_HAS_SEC
select SYS_FSL_HAS_DDR4
@@ -73,8 +109,12 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A008511
select SYS_FSL_ERRATUM_A008514
select SYS_FSL_ERRATUM_A008585
select SYS_FSL_ERRATUM_A008997
select SYS_FSL_ERRATUM_A009007
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009635
select SYS_FSL_ERRATUM_A009663
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A009801
select SYS_FSL_ERRATUM_A009803
select SYS_FSL_ERRATUM_A009942
@@ -85,6 +125,7 @@ config ARCH_LS2080A
config FSL_LSCH2
bool
select SYS_FSL_HAS_CCI400
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_BE
@@ -98,7 +139,7 @@ config FSL_LSCH3
config FSL_MC_ENET
bool "Management Complex network"
depends on ARCH_LS2080A
depends on ARCH_LS2080A || ARCH_LS1088A
default y
select RESV_RAM
help
@@ -114,6 +155,7 @@ config FSL_PCIE_COMPAT
default "fsl,ls1043a-pcie" if ARCH_LS1043A
default "fsl,ls1046a-pcie" if ARCH_LS1046A
default "fsl,ls2080a-pcie" if ARCH_LS2080A
default "fsl,ls1088a-pcie" if ARCH_LS1088A
help
This compatible is used to find pci controller node in Kernel DT
to complete fixup.
@@ -182,6 +224,7 @@ config SYS_LS_PPA_FW_ADDR
default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A
default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
default 0x400000 if SYS_LS_PPA_FW_IN_MMC
default 0x400000 if SYS_LS_PPA_FW_IN_NAND
@@ -195,12 +238,13 @@ config SYS_LS_PPA_FW_ADDR
config SYS_LS_PPA_ESBC_ADDR
hex "hdr address of PPA firmware loading from"
depends on FSL_LS_PPA && CHAIN_OF_TRUST
default 0x600c0000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
default 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
default 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
default 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3
default 0x700000 if SYS_LS_PPA_FW_IN_MMC
default 0x700000 if SYS_LS_PPA_FW_IN_NAND
default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
default 0x680000 if SYS_LS_PPA_FW_IN_MMC
default 0x680000 if SYS_LS_PPA_FW_IN_NAND
help
If the PPA header firmware locate at XIP flash, such as NOR or
QSPI flash, this address is a directly memory-mapped.
@@ -217,6 +261,20 @@ config LS_PPA_ESBC_HDR_SIZE
endmenu
config SYS_FSL_ERRATUM_A008997
bool "Workaround for USB PHY erratum A008997"
config SYS_FSL_ERRATUM_A009007
bool
help
Workaround for USB PHY erratum A009007
config SYS_FSL_ERRATUM_A009008
bool "Workaround for USB PHY erratum A009008"
config SYS_FSL_ERRATUM_A009798
bool "Workaround for USB PHY erratum A009798"
config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315"
@@ -228,6 +286,7 @@ config MAX_CPUS
default 4 if ARCH_LS1043A
default 4 if ARCH_LS1046A
default 16 if ARCH_LS2080A
default 8 if ARCH_LS1088A
default 1
help
Set this number to the maximum number of possible CPUs in the SoC.
@@ -248,12 +307,27 @@ config QSPI_AHB_INIT
But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
bus for those flashes to support the full QSPI flash size.
config SYS_CCI400_OFFSET
hex "Offset for CCI400 base"
depends on SYS_FSL_HAS_CCI400
default 0x3090000 if ARCH_LS1088A
default 0x180000 if FSL_LSCH2
help
Offset for CCI400 base
CCI400 base addr = CCSRBAR + CCI400_OFFSET
config SYS_FSL_IFC_BANK_COUNT
int "Maximum banks of Integrated flash controller"
depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
default 4 if ARCH_LS1043A
default 4 if ARCH_LS1046A
default 8 if ARCH_LS2080A
default 8 if ARCH_LS2080A || ARCH_LS1088A
config SYS_FSL_HAS_CCI400
bool
config SYS_FSL_HAS_CCN504
bool
config SYS_FSL_HAS_DP_DDR
bool
@@ -296,6 +370,7 @@ config SYS_FSL_PCLK_DIV
int "Platform clock divider"
default 1 if ARCH_LS1043A
default 1 if ARCH_LS1046A
default 1 if ARCH_LS1088A
default 2
help
This is the divider that is used to derive Platform clock from
@@ -362,6 +437,18 @@ config RESV_RAM
be at the high end of physical memory. The reserve RAM may be
excluded from memory bank(s) passed to OS, or marked as reserved.
config SYS_FSL_EC1
bool
help
Ethernet controller 1, this is connected to MAC3.
Provides DPAA2 capabilities
config SYS_FSL_EC2
bool
help
Ethernet controller 2, this is connected to MAC4.
Provides DPAA2 capabilities
config SYS_FSL_ERRATUM_A008336
bool
@@ -386,13 +473,27 @@ config SYS_FSL_ERRATUM_A009660
config SYS_FSL_ERRATUM_A009929
bool
config SYS_FSL_HAS_RGMII
bool
depends on SYS_FSL_EC1 || SYS_FSL_EC2
config SYS_MC_RSV_MEM_ALIGN
hex "Management Complex reserved memory alignment"
depends on RESV_RAM
default 0x20000000
default 0x20000000 if ARCH_LS2080A
default 0x70000000 if ARCH_LS1088A
help
Reserved memory needs to be aligned for MC to use. Default value
is 512MB.
config SPL_LDSCRIPT
default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
config HAS_FSL_XHCI_USB
bool
default y if ARCH_LS1043A || ARCH_LS1046A
help
For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
pins, select it when the pins are assigned to USB.

View File

@@ -38,3 +38,7 @@ endif
ifneq ($(CONFIG_ARCH_LS1046A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
endif
ifneq ($(CONFIG_ARCH_LS1088A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o
endif

View File

@@ -16,6 +16,7 @@
#include <asm/arch/soc.h>
#include <asm/arch/cpu.h>
#include <asm/arch/speed.h>
#include <fsl_immap.h>
#include <asm/arch/mp.h>
#include <efi_loader.h>
#include <fm_eth.h>
@@ -516,6 +517,10 @@ int arch_early_init_r(void)
printf("Did not wake secondary cores\n");
}
#ifdef CONFIG_SYS_FSL_HAS_RGMII
fsl_rgmii_init();
#endif
#ifdef CONFIG_SYS_HAS_SERDES
fsl_serdes_init();
#endif
@@ -614,13 +619,22 @@ void efi_reset_system_init(void)
#endif
/*
* Calculate reserved memory with given memory bank
* Return aligned memory size on success
* Return (ram_size + needed size) for failure
*/
phys_size_t board_reserve_ram_top(phys_size_t ram_size)
{
phys_size_t ram_top = ram_size;
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
ram_top = mc_get_dram_block_size();
if (ram_top > ram_size)
return ram_size + ram_top;
ram_top = ram_size - ram_top;
/* The start address of MC reserved memory needs to be aligned. */
ram_top -= mc_get_dram_block_size();
ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
#endif
@@ -633,13 +647,14 @@ phys_size_t get_effective_memsize(void)
/*
* For ARMv8 SoCs, DDR memory is split into two or three regions. The
* first region is 2GB space at 0x8000_0000. If the memory extends to
* the second region (or the third region if applicable), the secure
* memory and Management Complex (MC) memory should be put into the
* highest region, i.e. the end of DDR memory. CONFIG_MAX_MEM_MAPPED
* is set to the size of first region so U-Boot doesn't relocate itself
* into higher address. Should DDR be configured to skip the first
* region, this function needs to be adjusted.
* first region is 2GB space at 0x8000_0000. Secure memory needs to
* allocated from first region. If the memory extends to the second
* region (or the third region if applicable), Management Complex (MC)
* memory should be put into the highest region, i.e. the end of DDR
* memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so
* U-Boot doesn't relocate itself into higher address. Should DDR be
* configured to skip the first region, this function needs to be
* adjusted.
*/
if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
ea_size = CONFIG_MAX_MEM_MAPPED;
@@ -650,22 +665,16 @@ phys_size_t get_effective_memsize(void)
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
/* Check if we have enough space for secure memory */
if (rem > CONFIG_SYS_MEM_RESERVE_SECURE) {
rem -= CONFIG_SYS_MEM_RESERVE_SECURE;
} else {
if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE) {
ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
rem = 0; /* Presume MC requires more memory */
} else {
printf("Error: No enough space for secure memory.\n");
}
}
if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
else
printf("Error: No enough space for secure memory.\n");
#endif
/* Check if we have enough memory for MC */
if (rem < board_reserve_ram_top(rem)) {
/* Not enough memory in high region to reserve */
if (ea_size > board_reserve_ram_top(rem))
ea_size -= board_reserve_ram_top(rem);
if (ea_size > board_reserve_ram_top(ea_size))
ea_size -= board_reserve_ram_top(ea_size);
else
printf("Error: No enough space for reserved memory.\n");
}
@@ -684,8 +693,19 @@ int dram_init_banksize(void)
* memory. The DDR extends from low region to high region(s) presuming
* no hole is created with DDR configuration. gd->arch.secure_ram tracks
* the location of secure memory. gd->arch.resv_ram tracks the location
* of reserved memory for Management Complex (MC).
* of reserved memory for Management Complex (MC). Because gd->ram_size
* is reduced by this function if secure memory is reserved, checking
* gd->arch.secure_ram should be done to avoid running it repeatedly.
*/
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
debug("No need to run again, skip %s\n", __func__);
return 0;
}
#endif
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
@@ -704,32 +724,14 @@ int dram_init_banksize(void)
gd->bd->bi_dram[0].size = gd->ram_size;
}
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
if (gd->bd->bi_dram[2].size >= CONFIG_SYS_MEM_RESERVE_SECURE) {
gd->bd->bi_dram[2].size -= CONFIG_SYS_MEM_RESERVE_SECURE;
gd->arch.secure_ram = gd->bd->bi_dram[2].start +
gd->bd->bi_dram[2].size;
if (gd->bd->bi_dram[0].size >
CONFIG_SYS_MEM_RESERVE_SECURE) {
gd->bd->bi_dram[0].size -=
CONFIG_SYS_MEM_RESERVE_SECURE;
gd->arch.secure_ram = gd->bd->bi_dram[0].start +
gd->bd->bi_dram[0].size;
gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
} else
#endif
{
if (gd->bd->bi_dram[1].size >= CONFIG_SYS_MEM_RESERVE_SECURE) {
gd->bd->bi_dram[1].size -=
CONFIG_SYS_MEM_RESERVE_SECURE;
gd->arch.secure_ram = gd->bd->bi_dram[1].start +
gd->bd->bi_dram[1].size;
gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
} else if (gd->bd->bi_dram[0].size >
CONFIG_SYS_MEM_RESERVE_SECURE) {
gd->bd->bi_dram[0].size -=
CONFIG_SYS_MEM_RESERVE_SECURE;
gd->arch.secure_ram = gd->bd->bi_dram[0].start +
gd->bd->bi_dram[0].size;
gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
}
}
#endif /* CONFIG_SYS_MEM_RESERVE_SECURE */
@@ -783,6 +785,11 @@ int dram_init_banksize(void)
}
#endif
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
debug("%s is called. gd->ram_size is reduced to %lu\n",
__func__, (ulong)gd->ram_size);
#endif
return 0;
}

View File

@@ -0,0 +1,140 @@
Falcon boot option
------------------
Falcon boot is a short cut boot method for SD/eMMC targets. It skips loading the
RAM version U-Boot. Instead, it loads FIT image and boot directly to Linux.
CONFIG_SPL_OS_BOOT enables falcon boot. CONFIG_SPL_LOAD_FIT enables the FIT
image support (also need CONFIG_SPL_OF_LIBFDT, CONFIG_SPL_FIT and optionally
CONFIG_SPL_GZIP).
To enable falcon boot, a hook function spl_start_uboot() returns 0 to indicate
booting U-Boot is not the first choice. The kernel FIT image needs to be put
at CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR. SPL mmc driver reads the header to
determine if this is a FIT image. If true, FIT image components are parsed and
copied or decompressed (if applicable) to their destinations. If FIT image is
not found, normal U-Boot flow will follow.
An important part of falcon boot is to prepare the device tree. A normal U-Boot
does FDT fixups when booting Linux. For falcon boot, Linux boots directly from
SPL, skipping the normal U-Boot. The device tree has to be prepared in advance.
A command "spl export" should be called under the normal RAM version U-Boot.
It is equivalent to go through "bootm" step-by-step until device tree fixup is
done. The device tree in memory is the one needed for falcon boot. Falcon boot
flow suggests to save this image to SD/eMMC at the location pointed by macro
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR, with maximum size specified by macro
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS. However, when FIT image is used for
Linux, the device tree stored in FIT image overwrites the memory loaded by spl
driver from these sectors. We could change this loading order to favor the
stored sectors. But when secure boot is enabled, these sectors are used for
signature header and needs to be loaded before the FIT image. So it is important
to understand the device tree in FIT image should be the one actually used, or
leave it absent to favor the stored sectors. It is easier to deploy the FIT
image with embedded static device tree to multiple boards.
Macro CONFIG_SYS_SPL_ARGS_ADDR serves two purposes. One is the pointer to load
the stored sectors to. Normally this is the static device tree. The second
purpose is the memory location of signature header for secure boot. After the
FIT image is loaded into memory, it is validated against the signature header
before individual components are extracted (and optionally decompressed) into
their final memory locations, respectively. After the validation, the header
is no longer used. The static device tree is copied into this location. So
this macro is passed as the location of device tree when booting Linux.
Steps to prepare static device tree
-----------------------------------
To prepare the static device tree for Layerscape boards, it is important to
understand the fixups in U-Boot. Memory size and location, as well as reserved
memory blocks are added/updated. Ethernet MAC addressed are updated. FMan
microcode (if used) is embedded in the device tree. Kernel command line and
initrd information are embedded. Others including CPU status, boot method,
Ethernet port status, etc. are also updated.
Following normal booting process, all variables are set, all images are loaded
before "bootm" command would be issued to boot, run command
spl export fdt <address>
where the address is the location of FIT image. U-Boot goes through the booting
process as if "bootm start", "bootm loados", "bootm ramdisk"... commands but
stops before "bootm go". There we have the fixed-up device tree in memory.
We can check the device tree header by these commands
fdt addr <fdt address>
fdt header
Where the fdt address is the device tree in memory. It is printed by U-Boot.
It is useful to know the exact size. One way to extract this static device
tree is to save it to eMMC/SD using command in U-Boot, and extract under Linux
with these commands, repectively
mmc write <address> <sector> <sectors>
dd if=/dev/mmcblk0 of=<filename> bs=512 skip=<sector> count=<sectors>
Note, U-Boot takes values as hexadecimals while Linux takes them as decimals by
default. If using NAND or other storage, the commands are slightly different.
When we have the static device tree image, we can re-make the FIT image with
it. It is important to specify the load addresses in FIT image for every
components. Otherwise U-Boot cannot load them correctly.
Generate FIT image with static device tree
------------------------------------------
Example:
/dts-v1/;
/ {
description = "Image file for the LS1043A Linux Kernel";
#address-cells = <1>;
images {
kernel@1 {
description = "ARM64 Linux kernel";
data = /incbin/("./arch/arm64/boot/Image.gz");
type = "kernel";
arch = "arm64";
os = "linux";
compression = "gzip";
load = <0x80080000>;
entry = <0x80080000>;
};
fdt@1 {
description = "Flattened Device Tree blob";
data = /incbin/("./fsl-ls1043ardb-static.dtb");
type = "flat_dt";
arch = "arm64";
compression = "none";
load = <0x90000000>;
};
ramdisk@1 {
description = "LS1043 Ramdisk";
data = /incbin/("./rootfs.cpio.gz");
type = "ramdisk";
arch = "arm64";
os = "linux";
compression = "gzip";
load = <0xa0000000>;
};
};
configurations {
default = "config@1";
config@1 {
description = "Boot Linux kernel";
kernel = "kernel@1";
fdt = "fdt@1";
ramdisk = "ramdisk@1";
loadables = "fdt", "ramdisk";
};
};
};
The "loadables" is not optional. It tells SPL which images to load into memory.
Other things to consider
-----------------------
Falcon boot skips a lot of initialization in U-Boot. If Linux expects the
hardware to be initialized by U-Boot, the related code should be ported to SPL
build. For example, if Linux expect Ethernet PHY to be initialized in U-Boot
(which is not a common case), the PHY initialization has to be included in
falcon boot. This increases the SPL image size and should be handled carefully.
If Linux has PHY driver enabled, it still depends on the correct MDIO bus setup
in U-Boot. Normal U-Boot sets the MDC ratio to generate a proper clock signal.

View File

@@ -1,11 +1,12 @@
SoC overview
1. LS1043A
2. LS2080A
3. LS1012A
4. LS1046A
5. LS2088A
6. LS2081A
2. LS1088A
3. LS2080A
4. LS1012A
5. LS1046A
6. LS2088A
7. LS2081A
LS1043A
---------
@@ -45,6 +46,38 @@ The LS1043A SoC includes the following function and features:
- Integrated flash controller supporting NAND and NOR flash
- QorIQ platform's trust architecture 2.1
LS1088A
--------
The QorIQ LS1088A processor is built on the Layerscape
architecture combining eight ARM A53 processor cores
with advanced, high-performance datapath acceleration
and networks, peripheral interfaces required for
networking, wireless infrastructure, and general-purpose
embedded applications.
LS1088A is compliant with the Layerscape Chassis Generation 3.
Features summary:
- 8 32-bit / 64-bit ARM v8 Cortex-A53 CPUs
- Cores are in 2 cluster of 4-cores each
- 1MB L2 - Cache per cluster
- Cache coherent interconnect (CCI-400)
- 1 64-bit DDR4 SDRAM memory controller with ECC
- Data path acceleration architecture 2.0 (DPAA2)
- 4-Lane 10GHz SerDes comprising of WRIOP
- 4-Lane 10GHz SerDes comprising of PCI, SATA, uQE(TDM/HLDC/UART)
- Ethernet interfaces: SGMIIs, RGMIIs, QSGMIIs, XFIs
- QSPI, SPI, IFC2.0 supporting NAND, NOR flash
- 3 PCIe3.0 , 1 SATA3.0, 2 USB3.0, 1 SDXC, 2 DUARTs etc
- 2 DUARTs
- 4 I2C, GPIO
- Thermal monitor unit(TMU)
- 4 Flextimers and 1 generic timer
- Support for hardware virtualization and partitioning enforcement
- QorIQ platform's trust architecture 3.0
- Service processor (SP) provides pre-boot initialization and secure-boot
capabilities
LS2080A
--------
The LS2080A integrated multicore processor combines eight ARM Cortex-A57

View File

@@ -345,11 +345,38 @@ static void fdt_fixup_msi(void *blob)
}
#endif
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
/* Remove JR node used by SEC firmware */
void fdt_fixup_remove_jr(void *blob)
{
int jr_node, addr_cells, len;
int crypto_node = fdt_path_offset(blob, "crypto");
u64 jr_offset, used_jr;
fdt32_t *reg;
used_jr = sec_firmware_used_jobring_offset();
fdt_support_default_count_cells(blob, crypto_node, &addr_cells, NULL);
jr_node = fdt_node_offset_by_compatible(blob, crypto_node,
"fsl,sec-v4.0-job-ring");
while (jr_node != -FDT_ERR_NOTFOUND) {
reg = (fdt32_t *)fdt_getprop(blob, jr_node, "reg", &len);
jr_offset = fdt_read_number(reg, addr_cells);
if (jr_offset == used_jr) {
fdt_del_node(blob, jr_node);
break;
}
jr_node = fdt_node_offset_by_compatible(blob, jr_node,
"fsl,sec-v4.0-job-ring");
}
}
#endif
void ft_cpu_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_FSL_LSCH2
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
unsigned int svr = in_be32(&gur->svr);
unsigned int svr = gur_in32(&gur->svr);
/* delete crypto node if not on an E-processor */
if (!IS_E_PROCESSOR(svr))
@@ -358,11 +385,15 @@ void ft_cpu_setup(void *blob, bd_t *bd)
else {
ccsr_sec_t __iomem *sec;
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
if (fdt_fixup_kaslr(blob))
fdt_fixup_remove_jr(blob);
#endif
sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
}
#endif
#endif
#ifdef CONFIG_MP
ft_fixup_cpu(blob);
@@ -387,7 +418,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_firmware(blob);
#endif
#ifndef CONFIG_LS1012A
#ifndef CONFIG_ARCH_LS1012A
fsl_fdt_disable_usb(blob);
#endif
#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN

View File

@@ -28,6 +28,20 @@ __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
return;
}
/*
*The return value of this func is the serdes protocol used.
*Typically this function is called number of times depending
*upon the number of serdes blocks in the Silicon.
*Zero is used to denote that no serdes was enabled,
*this is the case when golden RCW was used where DPAA2 bring was
*intentionally removed to achieve boot to prompt
*/
__weak int serdes_get_number(int serdes, int cfg)
{
return cfg;
}
int is_serdes_configured(enum srds_prtcl device)
{
int ret = 0;
@@ -73,6 +87,9 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
printf("invalid SerDes%d\n", sd);
break;
}
cfg = serdes_get_number(sd, cfg);
/* Is serdes enabled at all? */
if (cfg == 0)
return -ENODEV;
@@ -99,6 +116,8 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
cfg >>= sd_prctl_shift;
cfg = serdes_get_number(sd, cfg);
printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
if (!is_serdes_prtcl_valid(sd, cfg))

View File

@@ -76,7 +76,7 @@ ENTRY(lowlevel_init)
switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
1:
#ifdef CONFIG_FSL_LSCH3
#if defined (CONFIG_SYS_FSL_HAS_CCN504)
/* Set Wuo bit for RN-I 20 */
#ifdef CONFIG_ARCH_LS2080A
@@ -171,7 +171,7 @@ ENTRY(lowlevel_init)
ldr x0, =CCI_S2_QOS_CONTROL_BASE(20)
ldr x1, =0x00FF000C
bl ccn504_set_qos
#endif
#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
#ifdef SMMU_BASE
/* Set the SMMU page size in the sACR register */
@@ -338,7 +338,9 @@ get_svr:
ldr x1, =FSL_LSCH3_SVR
ldr w0, [x1]
ret
#endif
#ifdef CONFIG_SYS_FSL_HAS_CCN504
hnf_pstate_poll:
/* x0 has the desired status, return 0 for success, 1 for timeout
* clobber x1, x2, x3, x4, x6, x7
@@ -394,9 +396,6 @@ ENTRY(__asm_flush_l3_dcache)
mov x29, lr
mov x8, #0
switch_el x0, 1f, 100f, 100f /* skip if not in EL3 */
1:
dsb sy
mov x0, #0x1 /* HNFPSTAT_SFONLY */
bl hnf_set_pstate
@@ -414,13 +413,12 @@ ENTRY(__asm_flush_l3_dcache)
bl hnf_pstate_poll
cbz x0, 1f
add x8, x8, #0x2
100:
1:
mov x0, x8
mov lr, x29
ret
ENDPROC(__asm_flush_l3_dcache)
#endif
#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
#ifdef CONFIG_MP
/* Keep literals not used by the secondary boot code outside it */

View File

@@ -0,0 +1,126 @@
/*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/fsl_serdes.h>
struct serdes_config {
u8 ip_protocol;
u8 lanes[SRDS_MAX_LANES];
u8 rcw_lanes[SRDS_MAX_LANES];
};
static struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
{0x12, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 3, 3 } },
{0x15, {SGMII3, SGMII7, XFI1, XFI2 }, {3, 3, 1, 1 } },
{0x16, {SGMII3, SGMII7, SGMII1, XFI2 }, {3, 3, 3, 1 } },
{0x17, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 3, 2 } },
{0x18, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 2, 2 } },
{0x19, {SGMII3, QSGMII_B, XFI1, XFI2}, {3, 4, 1, 1 } },
{0x1A, {SGMII3, QSGMII_B, SGMII1, XFI2 }, {3, 4, 3, 1 } },
{0x1B, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 3, 2 } },
{0x1C, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 2, 2 } },
{0x1D, {QSGMII_A, QSGMII_B, XFI1, XFI2 }, {4, 4, 1, 1 } },
{0x1E, {QSGMII_A, QSGMII_B, SGMII1, XFI2 }, {4, 4, 3, 1 } },
{0x1F, {QSGMII_A, QSGMII_B, SGMII1, SGMII2 }, {4, 4, 3, 2 } },
{0x20, {QSGMII_A, QSGMII_B, SGMII1, SGMII2 }, {4, 4, 2, 2 } },
{0x35, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 3, 3 } },
{0x36, {QSGMII_A, QSGMII_B, SGMII1, SGMII2 }, {4, 4, 3, 3 } },
{0x3A, {SGMII3, PCIE1, SGMII1, SGMII2 }, {3, 5, 3, 3 } },
{}
};
static struct serdes_config serdes2_cfg_tbl[] = {
/* SerDes 2 */
{0x0C, {PCIE1, PCIE1, PCIE1, PCIE1 }, {8, 8, 8, 8 } },
{0x0D, {PCIE1, PCIE2, PCIE3, SATA1 }, {5, 5, 5, 9 } },
{0x0E, {PCIE1, PCIE1, PCIE2, SATA1 }, {7, 7, 6, 9 } },
{0x13, {PCIE1, PCIE1, PCIE3, PCIE3 }, {7, 7, 7, 7 } },
{0x14, {PCIE1, PCIE2, PCIE3, PCIE3 }, {5, 5, 7, 7 } },
{0x3C, {NONE, PCIE2, NONE, PCIE3 }, {0, 5, 0, 6 } },
{}
};
static struct serdes_config *serdes_cfg_tbl[] = {
serdes1_cfg_tbl,
serdes2_cfg_tbl,
};
int serdes_get_number(int serdes, int cfg)
{
struct serdes_config *ptr;
int i, j, index, lnk;
int is_found, max_lane = SRDS_MAX_LANES;
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;
ptr = serdes_cfg_tbl[serdes];
while (ptr->ip_protocol) {
is_found = 1;
for (i = 0, j = max_lane - 1; i < max_lane; i++, j--) {
lnk = cfg & (0xf << 4 * i);
lnk = lnk >> (4 * i);
index = (serdes == FSL_SRDS_1) ? j : i;
if (ptr->rcw_lanes[index] == lnk && is_found)
is_found = 1;
else
is_found = 0;
}
if (is_found)
return ptr->ip_protocol;
ptr++;
}
return 0;
}
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
{
struct serdes_config *ptr;
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;
ptr = serdes_cfg_tbl[serdes];
while (ptr->ip_protocol) {
if (ptr->ip_protocol == cfg)
return ptr->lanes[lane];
ptr++;
}
return 0;
}
int is_serdes_prtcl_valid(int serdes, u32 prtcl)
{
int i;
struct serdes_config *ptr;
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;
ptr = serdes_cfg_tbl[serdes];
while (ptr->ip_protocol) {
if (ptr->ip_protocol == prtcl)
break;
ptr++;
}
if (!ptr->ip_protocol)
return 0;
for (i = 0; i < SRDS_MAX_LANES; i++) {
if (ptr->lanes[i] != NONE)
return 1;
}
return 0;
}

View File

@@ -35,6 +35,7 @@ int ppa_init(void)
unsigned int el = current_el();
void *ppa_fit_addr;
u32 *boot_loc_ptr_l, *boot_loc_ptr_h;
u32 *loadable_l, *loadable_h;
int ret;
#ifdef CONFIG_CHAIN_OF_TRUST
@@ -107,9 +108,6 @@ int ppa_init(void)
return -EIO;
}
/* flush cache after read */
flush_cache((ulong)fitp, cnt * 512);
ret = fdt_check_header(fitp);
if (ret) {
free(fitp);
@@ -134,9 +132,6 @@ int ppa_init(void)
}
debug("Read PPA header to 0x%p\n", ppa_hdr_ddr);
/* flush cache after read */
flush_cache((ulong)ppa_hdr_ddr, cnt * 512);
ppa_esbc_hdr = (uintptr_t)ppa_hdr_ddr;
#endif
@@ -164,9 +159,6 @@ int ppa_init(void)
return -EIO;
}
/* flush cache after read */
flush_cache((ulong)ppa_fit_addr, cnt * 512);
#elif defined(CONFIG_SYS_LS_PPA_FW_IN_NAND)
struct fdt_header fit;
@@ -208,9 +200,6 @@ int ppa_init(void)
}
debug("Read PPA header to 0x%p\n", ppa_hdr_ddr);
/* flush cache after read */
flush_cache((ulong)ppa_hdr_ddr, fw_length);
ppa_esbc_hdr = (uintptr_t)ppa_hdr_ddr;
#endif
@@ -232,9 +221,6 @@ int ppa_init(void)
CONFIG_SYS_LS_PPA_FW_ADDR);
return -EIO;
}
/* flush cache after read */
flush_cache((ulong)ppa_fit_addr, fw_length);
#else
#error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined"
#endif
@@ -255,9 +241,9 @@ int ppa_init(void)
PPA_KEY_HASH,
&ppa_img_addr);
if (ret != 0)
printf("PPA validation failed\n");
printf("SEC firmware(s) validation failed\n");
else
printf("PPA validation Successful\n");
printf("SEC firmware(s) validation Successful\n");
}
#if defined(CONFIG_SYS_LS_PPA_FW_IN_MMC) || \
defined(CONFIG_SYS_LS_PPA_FW_IN_NAND)
@@ -269,15 +255,24 @@ int ppa_init(void)
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
boot_loc_ptr_l = &gur->bootlocptrl;
boot_loc_ptr_h = &gur->bootlocptrh;
/* Assign addresses to loadable ptrs */
loadable_l = &gur->scratchrw[4];
loadable_h = &gur->scratchrw[5];
#elif defined(CONFIG_FSL_LSCH2)
struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
boot_loc_ptr_l = &scfg->scratchrw[1];
boot_loc_ptr_h = &scfg->scratchrw[0];
/* Assign addresses to loadable ptrs */
loadable_l = &scfg->scratchrw[2];
loadable_h = &scfg->scratchrw[3];
#endif
debug("fsl-ppa: boot_loc_ptr_l = 0x%p, boot_loc_ptr_h =0x%p\n",
boot_loc_ptr_l, boot_loc_ptr_h);
ret = sec_firmware_init(ppa_fit_addr, boot_loc_ptr_l, boot_loc_ptr_h);
ret = sec_firmware_init(ppa_fit_addr, boot_loc_ptr_l, boot_loc_ptr_h,
loadable_l, loadable_h);
#if defined(CONFIG_SYS_LS_PPA_FW_IN_MMC) || \
defined(CONFIG_SYS_LS_PPA_FW_IN_NAND)

View File

@@ -5,6 +5,7 @@
*/
#include <common.h>
#include <fsl_immap.h>
#include <fsl_ifc.h>
#include <ahci.h>
#include <scsi.h>
@@ -23,6 +24,7 @@
#ifdef CONFIG_CHAIN_OF_TRUST
#include <fsl_validate.h>
#endif
#include <fsl_immap.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -52,6 +54,109 @@ bool soc_has_aiop(void)
return false;
}
static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
{
scfg_clrsetbits32(scfg + offset / 4,
0xF << 6,
SCFG_USB_TXVREFTUNE << 6);
}
static void erratum_a009008(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
#elif defined(CONFIG_ARCH_LS2080A)
set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
#endif
#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
}
static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
{
scfg_clrbits32(scfg + offset / 4,
SCFG_USB_SQRXTUNE_MASK << 23);
}
static void erratum_a009798(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
#elif defined(CONFIG_ARCH_LS2080A)
set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
#endif
#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
}
#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
{
scfg_clrsetbits32(scfg + offset / 4,
0x7F << 9,
SCFG_USB_PCSTXSWINGFULL << 9);
}
#endif
static void erratum_a008997(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
#endif
#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
}
#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
#endif
static void erratum_a009007(void)
{
#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;
PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
usb_phy = (void __iomem *)SCFG_USB_PHY2;
PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
usb_phy = (void __iomem *)SCFG_USB_PHY3;
PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
void __iomem *dcsr = (void __iomem *)DCSR_BASE;
PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
}
#if defined(CONFIG_FSL_LSCH3)
/*
* This erratum requires setting a value to eddrtqcr1 to
@@ -95,7 +200,7 @@ static void erratum_a008514(void)
static unsigned long get_internval_val_mhz(void)
{
char *interval = getenv(PLATFORM_CYCLE_ENV_VAR);
char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
/*
* interval is the number of platform cycles(MHz) between
* wake up events generated by EPU.
@@ -155,8 +260,8 @@ static void erratum_rcw_src(void)
#ifdef CONFIG_SYS_FSL_ERRATUM_A009203
static void erratum_a009203(void)
{
u8 __iomem *ptr;
#ifdef CONFIG_SYS_I2C
u8 __iomem *ptr;
#ifdef I2C1_BASE_ADDR
ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
@@ -192,12 +297,18 @@ void bypass_smmu(void)
void fsl_lsch3_early_init_f(void)
{
erratum_rcw_src();
#ifdef CONFIG_FSL_IFC
init_early_memctl_regs(); /* tighten IFC timing */
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A009203
erratum_a009203();
#endif
erratum_a008514();
erratum_a008336();
erratum_a009008();
erratum_a009798();
erratum_a008997();
erratum_a009007();
#ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -214,11 +325,14 @@ int sata_init(void)
{
struct ccsr_ahci __iomem *ccsr_ahci;
#ifdef CONFIG_SYS_SATA2
ccsr_ahci = (void *)CONFIG_SYS_SATA2;
out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
#endif
#ifdef CONFIG_SYS_SATA1
ccsr_ahci = (void *)CONFIG_SYS_SATA1;
out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
@@ -226,6 +340,7 @@ int sata_init(void)
ahci_init((void __iomem *)CONFIG_SYS_SATA1);
scsi_scan(false);
#endif
return 0;
}
@@ -285,7 +400,8 @@ static void erratum_a008850_early(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
/* part 1 of 2 */
struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
/* Skip if running at lower exception level */
@@ -304,7 +420,8 @@ void erratum_a008850_post(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
/* part 2 of 2 */
struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
u32 tmp;
@@ -439,7 +556,8 @@ int setup_chip_volt(void)
void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
@@ -473,6 +591,10 @@ void fsl_lsch2_early_init_f(void)
erratum_a009929();
erratum_a009660();
erratum_a010539();
erratum_a009008();
erratum_a009798();
erratum_a008997();
erratum_a009007();
}
#endif

View File

@@ -80,6 +80,7 @@ void board_init_f(ulong dummy)
get_clocks();
preloader_console_init();
spl_set_bd();
#ifdef CONFIG_SPL_I2C_SUPPORT
i2c_init_all();
@@ -116,4 +117,29 @@ void board_init_f(ulong dummy)
gd->arch.tlb_allocated = gd->arch.tlb_addr;
#endif /* CONFIG_SPL_FSL_LS_PPA */
}
#ifdef CONFIG_SPL_OS_BOOT
/*
* Return
* 0 if booting into OS is selected
* 1 if booting into U-Boot is selected
*/
int spl_start_uboot(void)
{
env_init();
if (env_get_yesno("boot_os") != 0)
return 0;
return 1;
}
#endif /* CONFIG_SPL_OS_BOOT */
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
/* Just empty function now - can't decide what to choose */
debug("%s: %s\n", __func__, name);
return 0;
}
#endif
#endif /* CONFIG_SPL_BUILD */

View File

@@ -105,6 +105,74 @@ static int sec_firmware_parse_image(const void *sec_firmware_img,
return 0;
}
/*
* SEC Firmware FIT image parser to check if any loadable is
* present. If present, verify integrity of the loadable and
* copy loadable to address provided in (loadable_h, loadable_l).
*
* Returns 0 on success and a negative errno on error task fail.
*/
static int sec_firmware_check_copy_loadable(const void *sec_firmware_img,
u32 *loadable_l, u32 *loadable_h)
{
phys_addr_t sec_firmware_loadable_addr = 0;
int conf_node_off, ld_node_off;
char *conf_node_name = NULL;
const void *data;
size_t size;
ulong load;
conf_node_name = SEC_FIRMEWARE_FIT_CNF_NAME;
conf_node_off = fit_conf_get_node(sec_firmware_img, conf_node_name);
if (conf_node_off < 0) {
printf("SEC Firmware: %s: no such config\n", conf_node_name);
return -ENOENT;
}
ld_node_off = fit_conf_get_prop_node(sec_firmware_img, conf_node_off,
FIT_LOADABLE_PROP);
if (ld_node_off >= 0) {
printf("SEC Firmware: '%s' present in config\n",
FIT_LOADABLE_PROP);
/* Verify secure firmware image */
if (!(fit_image_verify(sec_firmware_img, ld_node_off))) {
printf("SEC Loadable: Bad loadable image (bad CRC)\n");
return -EINVAL;
}
if (fit_image_get_data(sec_firmware_img, ld_node_off,
&data, &size)) {
printf("SEC Loadable: Can't get subimage data/size");
return -ENOENT;
}
/* Get load address, treated as load offset to secure memory */
if (fit_image_get_load(sec_firmware_img, ld_node_off, &load)) {
printf("SEC Loadable: Can't get subimage load");
return -ENOENT;
}
/* Compute load address for loadable in secure memory */
sec_firmware_loadable_addr = (sec_firmware_addr -
gd->arch.tlb_size) + load;
/* Copy loadable to secure memory and flush dcache */
debug("%s copied to address 0x%p\n",
FIT_LOADABLE_PROP, (void *)sec_firmware_loadable_addr);
memcpy((void *)sec_firmware_loadable_addr, data, size);
flush_dcache_range(sec_firmware_loadable_addr,
sec_firmware_loadable_addr + size);
}
/* Populate address ptrs for loadable image with loadbale addr */
out_le32(loadable_l, (sec_firmware_loadable_addr & WORD_MASK));
out_le32(loadable_h, (sec_firmware_loadable_addr >> WORD_SHIFT));
return 0;
}
static int sec_firmware_copy_image(const char *title,
u64 image_addr, u32 image_size, u64 sec_firmware)
{
@@ -117,9 +185,11 @@ static int sec_firmware_copy_image(const char *title,
/*
* This function will parse the SEC Firmware image, and then load it
* to secure memory.
* to secure memory. Also load any loadable if present along with SEC
* Firmware image.
*/
static int sec_firmware_load_image(const void *sec_firmware_img)
static int sec_firmware_load_image(const void *sec_firmware_img,
u32 *loadable_l, u32 *loadable_h)
{
const void *raw_image_addr;
size_t raw_image_size = 0;
@@ -172,6 +242,15 @@ static int sec_firmware_load_image(const void *sec_firmware_img)
if (ret)
goto out;
/*
* Check if any loadable are present along with firmware image, if
* present load them.
*/
ret = sec_firmware_check_copy_loadable(sec_firmware_img, loadable_l,
loadable_h);
if (ret)
goto out;
sec_firmware_addr |= SEC_FIRMWARE_LOADED;
debug("SEC Firmware: Entry point: 0x%llx\n",
sec_firmware_addr & SEC_FIRMWARE_ADDR_MASK);
@@ -231,22 +310,80 @@ unsigned int sec_firmware_support_psci_version(void)
}
#endif
/*
* Check with sec_firmware if it supports random number generation
* via HW RNG
*
* The return value will be true if it is supported
*/
bool sec_firmware_support_hwrng(void)
{
uint8_t rand[8];
if (sec_firmware_addr & SEC_FIRMWARE_RUNNING) {
if (!sec_firmware_get_random(rand, 8))
return true;
}
return false;
}
/*
* sec_firmware_get_random - Get a random number from SEC Firmware
* @rand: random number buffer to be filled
* @bytes: Number of bytes of random number to be supported
* @eret: -1 in case of error, 0 for success
*/
int sec_firmware_get_random(uint8_t *rand, int bytes)
{
unsigned long long num;
struct pt_regs regs;
int param1;
if (!bytes || bytes > 8) {
printf("Max Random bytes genration supported is 8\n");
return -1;
}
#define SIP_RNG_64 0xC200FF11
regs.regs[0] = SIP_RNG_64;
if (bytes <= 4)
param1 = 0;
else
param1 = 1;
regs.regs[1] = param1;
smc_call(&regs);
if (regs.regs[0])
return -1;
num = regs.regs[1];
memcpy(rand, &num, bytes);
return 0;
}
/*
* sec_firmware_init - Initialize the SEC Firmware
* @sec_firmware_img: the SEC Firmware image address
* @eret_hold_l: the address to hold exception return address low
* @eret_hold_h: the address to hold exception return address high
* @loadable_l: the address to hold loadable address low
* @loadable_h: the address to hold loadable address high
*/
int sec_firmware_init(const void *sec_firmware_img,
u32 *eret_hold_l,
u32 *eret_hold_h)
u32 *eret_hold_h,
u32 *loadable_l,
u32 *loadable_h)
{
int ret;
if (!sec_firmware_is_valid(sec_firmware_img))
return -EINVAL;
ret = sec_firmware_load_image(sec_firmware_img);
ret = sec_firmware_load_image(sec_firmware_img, loadable_l,
loadable_h);
if (ret) {
printf("SEC Firmware: Failed to load image\n");
return ret;
@@ -278,3 +415,49 @@ int sec_firmware_init(const void *sec_firmware_img,
return 0;
}
/*
* fdt_fix_kaslr - Add kalsr-seed node in Device tree
* @fdt: Device tree
* @eret: 0 in case of error, 1 for success
*/
int fdt_fixup_kaslr(void *fdt)
{
int nodeoffset;
int err, ret = 0;
u8 rand[8];
#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT)
/* Check if random seed generation is supported */
if (sec_firmware_support_hwrng() == false)
return 0;
ret = sec_firmware_get_random(rand, 8);
if (ret < 0) {
printf("WARNING: No random number to set kaslr-seed\n");
return 0;
}
err = fdt_check_header(fdt);
if (err < 0) {
printf("fdt_chosen: %s\n", fdt_strerror(err));
return 0;
}
/* find or create "/chosen" node. */
nodeoffset = fdt_find_or_add_subnode(fdt, 0, "chosen");
if (nodeoffset < 0)
return 0;
err = fdt_setprop(fdt, nodeoffset, "kaslr-seed", rand,
sizeof(rand));
if (err < 0) {
printf("WARNING: can't set kaslr-seed %s.\n",
fdt_strerror(err));
return 0;
}
ret = 1;
#endif
return ret;
}

View File

@@ -41,6 +41,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-jerry.dtb \
rk3288-veyron-mickey.dtb \
rk3288-veyron-minnie.dtb \
rk3288-vyasa.dtb \
rk3328-evb.dtb \
rk3368-lion.dtb \
rk3368-sheep.dtb \
@@ -119,8 +120,6 @@ dtb-$(CONFIG_ARCH_UNIPHIER_PXS2) += \
uniphier-pxs2-vodka.dtb
dtb-$(CONFIG_ARCH_UNIPHIER_PXS3) += \
uniphier-pxs3-ref.dtb
dtb-$(CONFIG_ARCH_UNIPHIER_SLD3) += \
uniphier-sld3-ref.dtb
dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \
uniphier-sld8-ref.dtb
@@ -175,9 +174,10 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_cyclone5_vining_fpga.dtb
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
dra72-evm-revc.dtb dra71-evm.dtb
dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb
dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \
am57xx-beagle-x15-revb1.dtb \
am57xx-beagle-x15-revc.dtb \
am572x-idk.dtb \
am571x-idk.dtb
dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
@@ -189,7 +189,9 @@ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2080a-rdb.dtb \
fsl-ls2081a-rdb.dtb \
fsl-ls2088a-rdb-qspi.dtb
fsl-ls2088a-rdb-qspi.dtb \
fsl-ls1088a-rdb.dtb \
fsl-ls1088a-qds.dtb
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
@@ -204,6 +206,8 @@ dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \
stm32f769-disco.dtb
dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \
stm32h743i-eval.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
@@ -305,12 +309,13 @@ dtb-$(CONFIG_MACH_SUN8I_A33) += \
sun8i-a33-olinuxino.dtb \
sun8i-a33-q8-tablet.dtb \
sun8i-a33-sinlinx-sina33.dtb \
sun8i-r16-bananapi-m2m.dtb \
sun8i-r16-nintendo-nes-classic-edition.dtb \
sun8i-r16-parrot.dtb
dtb-$(CONFIG_MACH_SUN8I_A83T) += \
sun8i-a83t-allwinner-h8homlet-v2.dtb \
sun8i-a83t-cubietruck-plus.dtb \
sun8i-a83t-sinovoip-bpi-m3.dtb
sun8i-a83t-bananapi-m3.dtb \
sun8i-a83t-cubietruck-plus.dtb
dtb-$(CONFIG_MACH_SUN8I_H3) += \
sun8i-h2-plus-orangepi-zero.dtb \
sun8i-h3-bananapi-m2-plus.dtb \
@@ -336,6 +341,8 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \
sun50i-h5-orangepi-zero-plus2.dtb
dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-bananapi-m64.dtb \
sun50i-a64-nanopi-a64.dtb \
sun50i-a64-olinuxino.dtb \
sun50i-a64-orangepi-win.dtb \
sun50i-a64-pine64-plus.dtb \
sun50i-a64-pine64.dtb
@@ -357,6 +364,7 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
imx6sll-evk.dtb \
imx6dl-icore.dtb \
imx6dl-icore-rqs.dtb \
imx6q-cm-fx6.dtb \
imx6q-icore.dtb \
imx6q-icore-rqs.dtb \
imx6q-logicpd.dtb \
@@ -416,6 +424,9 @@ dtb-$(CONFIG_TARGET_OMAP3_LOGIC) += \
dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \
at91-sama5d2_xplained.dtb
dtb-$(CONFIG_TARGET_SAMA5D27_SOM1_EK) += \
at91-sama5d27_som1_ek.dtb
dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \
sama5d31ek.dtb \
sama5d33ek.dtb \

View File

@@ -315,7 +315,6 @@
&edma 25>;
dma-names = "tx", "rx";
interrupts = <64>;
interrupt-parent = <&intc>;
reg = <0x48060000 0x1000>;
status = "disabled";
};
@@ -328,7 +327,6 @@
&edma 3>;
dma-names = "tx", "rx";
interrupts = <28>;
interrupt-parent = <&intc>;
reg = <0x481d8000 0x1000>;
status = "disabled";
};
@@ -338,7 +336,6 @@
ti,hwmods = "mmc3";
ti,needs-special-reset;
interrupts = <29>;
interrupt-parent = <&intc>;
reg = <0x47810000 0x1000>;
status = "disabled";
};
@@ -724,7 +721,6 @@
0x4a101200 0x100>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
/*
* c0_rx_thresh_pend
* c0_rx_pend
@@ -787,7 +783,6 @@
lcdc: lcdc@4830e000 {
compatible = "ti,am33xx-tilcdc";
reg = <0x4830e000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <36>;
ti,hwmods = "lcdc";
status = "disabled";
@@ -796,7 +791,6 @@
tscadc: tscadc@44e0d000 {
compatible = "ti,am3359-tscadc";
reg = <0x44e0d000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <16>;
ti,hwmods = "adc_tsc";
status = "disabled";

View File

@@ -0,0 +1,12 @@
/*
* Copyright (C) 2017
* Logic PD - http://www.logicpd.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
/ {
chosen {
stdout-path = &uart3;
};
};

View File

@@ -0,0 +1,61 @@
/*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "am3517.dtsi"
/ {
model = "TI AM3517 EVM (AM3517/05 TMDSEVM3517)";
compatible = "ti,am3517-evm", "ti,am3517", "ti,omap3";
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};
vmmc_fixed: vmmc {
compatible = "regulator-fixed";
regulator-name = "vmmc_fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&davinci_emac {
status = "okay";
};
&davinci_mdio {
status = "okay";
};
&i2c1 {
clock-frequency = <400000>;
};
&i2c2 {
clock-frequency = <400000>;
};
&i2c3 {
clock-frequency = <400000>;
};
&mmc1 {
vmmc-supply = <&vmmc_fixed>;
bus-width = <4>;
};
&mmc2 {
status = "disabled";
};
&mmc3 {
status = "disabled";
};

View File

@@ -0,0 +1,10 @@
/*
* Copyright (C) 2017
* Logic PD - http://www.logicpd.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
&uart4 {
reg-shift = <2>;
};

107
arch/arm/dts/am3517.dtsi Normal file
View File

@@ -0,0 +1,107 @@
/*
* Device Tree Source for am3517 SoC
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include "omap3.dtsi"
/ {
aliases {
serial3 = &uart4;
can = &hecc;
};
ocp@68000000 {
am35x_otg_hs: am35x_otg_hs@5c040000 {
compatible = "ti,omap3-musb";
ti,hwmods = "am35x_otg_hs";
status = "disabled";
reg = <0x5c040000 0x1000>;
interrupts = <71>;
interrupt-names = "mc";
};
davinci_emac: ethernet@0x5c000000 {
compatible = "ti,am3517-emac";
ti,hwmods = "davinci_emac";
status = "disabled";
reg = <0x5c000000 0x30000>;
interrupts = <67 68 69 70>;
syscon = <&scm_conf>;
ti,davinci-ctrl-reg-offset = <0x10000>;
ti,davinci-ctrl-mod-reg-offset = <0>;
ti,davinci-ctrl-ram-offset = <0x20000>;
ti,davinci-ctrl-ram-size = <0x2000>;
ti,davinci-rmii-en = /bits/ 8 <1>;
local-mac-address = [ 00 00 00 00 00 00 ];
};
davinci_mdio: ethernet@0x5c030000 {
compatible = "ti,davinci_mdio";
ti,hwmods = "davinci_mdio";
status = "disabled";
reg = <0x5c030000 0x1000>;
bus_freq = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
uart4: serial@4809e000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart4";
status = "disabled";
reg = <0x4809e000 0x400>;
interrupts = <84>;
dmas = <&sdma 55 &sdma 54>;
dma-names = "tx", "rx";
clock-frequency = <48000000>;
};
omap3_pmx_core2: pinmux@480025d8 {
compatible = "ti,omap3-padconf", "pinctrl-single";
reg = <0x480025d8 0x24>;
#address-cells = <1>;
#size-cells = <0>;
#pinctrl-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0xff1f>;
};
hecc: can@5c050000 {
compatible = "ti,am3517-hecc";
status = "disabled";
reg = <0x5c050000 0x80>,
<0x5c053000 0x180>,
<0x5c052000 0x200>;
reg-names = "hecc", "hecc-ram", "mbx";
interrupts = <24>;
clocks = <&hecc_ck>;
};
};
};
&iva {
status = "disabled";
};
&mailbox {
status = "disabled";
};
&mmu_isp {
status = "disabled";
};
&smartreflex_mpu_iva {
status = "disabled";
};
/include/ "am35xx-clocks.dtsi"
/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"

View File

@@ -0,0 +1,128 @@
/*
* Device Tree Source for OMAP3 clock data
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&scm_clocks {
emac_ick: emac_ick@32c {
#clock-cells = <0>;
compatible = "ti,am35xx-gate-clock";
clocks = <&ipss_ick>;
reg = <0x032c>;
ti,bit-shift = <1>;
};
emac_fck: emac_fck@32c {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&rmii_ck>;
reg = <0x032c>;
ti,bit-shift = <9>;
};
vpfe_ick: vpfe_ick@32c {
#clock-cells = <0>;
compatible = "ti,am35xx-gate-clock";
clocks = <&ipss_ick>;
reg = <0x032c>;
ti,bit-shift = <2>;
};
vpfe_fck: vpfe_fck@32c {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&pclk_ck>;
reg = <0x032c>;
ti,bit-shift = <10>;
};
hsotgusb_ick_am35xx: hsotgusb_ick_am35xx@32c {
#clock-cells = <0>;
compatible = "ti,am35xx-gate-clock";
clocks = <&ipss_ick>;
reg = <0x032c>;
ti,bit-shift = <0>;
};
hsotgusb_fck_am35xx: hsotgusb_fck_am35xx@32c {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_ck>;
reg = <0x032c>;
ti,bit-shift = <8>;
};
hecc_ck: hecc_ck@32c {
#clock-cells = <0>;
compatible = "ti,am35xx-gate-clock";
clocks = <&sys_ck>;
reg = <0x032c>;
ti,bit-shift = <3>;
};
};
&cm_clocks {
ipss_ick: ipss_ick@a10 {
#clock-cells = <0>;
compatible = "ti,am35xx-interface-clock";
clocks = <&core_l3_ick>;
reg = <0x0a10>;
ti,bit-shift = <4>;
};
rmii_ck: rmii_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
pclk_ck: pclk_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <27000000>;
};
uart4_ick_am35xx: uart4_ick_am35xx@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
reg = <0x0a10>;
ti,bit-shift = <23>;
};
uart4_fck_am35xx: uart4_fck_am35xx@a00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_48m_fck>;
reg = <0x0a00>;
ti,bit-shift = <23>;
};
};
&cm_clockdomains {
core_l3_clkdm: core_l3_clkdm {
compatible = "ti,clockdomain";
clocks = <&sdrc_ick>, <&ipss_ick>, <&emac_ick>, <&vpfe_ick>,
<&hsotgusb_ick_am35xx>, <&hsotgusb_fck_am35xx>,
<&hecc_ck>;
};
core_l4_clkdm: core_l4_clkdm {
compatible = "ti,clockdomain";
clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
<&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
<&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
<&uart4_ick_am35xx>, <&uart4_fck_am35xx>;
};
};

View File

@@ -11,6 +11,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "am57xx-idk-common.dtsi"
#include "dra72x-mmc-iodelay.dtsi"
/ {
model = "TI AM5718 IDK";
@@ -62,20 +63,57 @@
linux,default-trigger = "mmc0";
};
};
extcon_usb2: extcon_usb2 {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
};
};
&mmc1 {
status = "okay";
vmmc-supply = <&ldo1_reg>;
bus-width = <4>;
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
};
&omap_dwc3_2 {
extcon = <&extcon_usb2>;
};
&extcon_usb2 {
id-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
vbus-gpio = <&gpio7 22 GPIO_ACTIVE_HIGH>;
};
&mailbox5 {
status = "okay";
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
status = "okay";
};
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
status = "okay";
};
};
&mailbox6 {
status = "okay";
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
status = "okay";
};
};
&pcie1_rc {
status = "okay";
gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
};
&pcie1_ep {
gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
};
&mmc1 {
pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
pinctrl-0 = <&mmc1_pins_default>;
pinctrl-1 = <&mmc1_pins_hs>;
pinctrl-2 = <&mmc1_pins_sdr12>;
pinctrl-3 = <&mmc1_pins_sdr25>;
pinctrl-4 = <&mmc1_pins_sdr50>;
pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;
pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
};
&mmc2 {
pinctrl-names = "default", "hs", "ddr_1_8v";
pinctrl-0 = <&mmc2_pins_default>;
pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
};

View File

@@ -12,6 +12,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "am57xx-idk-common.dtsi"
#include "dra74x-mmc-iodelay.dtsi"
/ {
model = "TI AM5728 IDK";
@@ -23,11 +24,6 @@
reg = <0x0 0x80000000 0x0 0x80000000>;
};
extcon_usb2: extcon_usb2 {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
};
status-leds {
compatible = "gpio-leds";
cpu0-led {
@@ -72,14 +68,62 @@
};
};
&mmc1 {
pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
pinctrl-0 = <&mmc1_pins_default>;
pinctrl-1 = <&mmc1_pins_hs>;
pinctrl-2 = <&mmc1_pins_sdr12>;
pinctrl-3 = <&mmc1_pins_sdr25>;
pinctrl-4 = <&mmc1_pins_sdr50>;
pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;
pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
};
&mmc2 {
pinctrl-names = "default", "hs", "ddr_1_8v";
pinctrl-0 = <&mmc2_pins_default>;
pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr_rev20>;
};
&omap_dwc3_2 {
extcon = <&extcon_usb2>;
};
&mmc1 {
status = "okay";
vmmc-supply = <&v3_3d>;
vmmc_aux-supply = <&ldo1_reg>;
bus-width = <4>;
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
&extcon_usb2 {
id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
vbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>;
};
&sn65hvs882 {
load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
};
&pcie1_rc {
status = "okay";
gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
};
&pcie1_ep {
gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
};
&mailbox5 {
status = "okay";
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
status = "okay";
};
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
status = "okay";
};
};
&mailbox6 {
status = "okay";
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
status = "okay";
};
mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
status = "okay";
};
};

View File

@@ -9,16 +9,13 @@
#include "dra74x.dtsi"
#include "am57xx-commercial-grade.dtsi"
#include "dra74x-mmc-iodelay.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
chosen {
stdout-path = &uart3;
};
aliases {
rtc0 = &mcp_rtc;
rtc1 = &tps659038_rtc;
@@ -26,6 +23,10 @@
display0 = &hdmi0;
};
chosen {
stdout-path = &uart3;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
@@ -166,34 +167,6 @@
};
};
&dra7_pmx_core {
mmc1_pins_default: mmc1_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc2_pins_default: mmc2_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
@@ -208,6 +181,7 @@
interrupt-controller;
ti,system-power-controller;
ti,palmas-override-powerhold;
tps659038_pmic {
compatible = "ti,tps659038-pmic";
@@ -387,7 +361,7 @@
};
eeprom: eeprom@50 {
compatible = "at,24c32";
compatible = "atmel,24c32";
reg = <0x50>;
};
};
@@ -424,19 +398,29 @@
<&dra7_pmx_core 0x3f8>;
};
&davinci_mdio {
phy0: ethernet-phy@1 {
reg = <1>;
};
phy1: ethernet-phy@2 {
reg = <2>;
};
};
&mac {
status = "okay";
dual_emac;
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <1>;
phy-handle = <&phy0>;
phy-mode = "rgmii";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <2>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
dual_emac_res_vlan = <2>;
};
@@ -559,7 +543,12 @@
};
};
&pcie1 {
&pcie1_rc {
status = "ok";
gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
};
&pcie1_ep {
gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
};

View File

@@ -19,6 +19,26 @@
};
&mmc1 {
pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
pinctrl-0 = <&mmc1_pins_default>;
pinctrl-1 = <&mmc1_pins_hs>;
pinctrl-2 = <&mmc1_pins_sdr12>;
pinctrl-3 = <&mmc1_pins_sdr25>;
pinctrl-4 = <&mmc1_pins_sdr50>;
pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>;
pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>;
vmmc-supply = <&vdd_3v3>;
vmmc-aux-supply = <&ldo1_reg>;
vqmmc-supply = <&ldo1_reg>;
};
&mmc2 {
pinctrl-names = "default", "hs", "ddr_1_8v";
pinctrl-0 = <&mmc2_pins_default>;
pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>;
};
/* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */
&phy1 {
max-speed = <100>;
};

View File

@@ -0,0 +1,39 @@
/*
* Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "am57xx-beagle-x15-common.dtsi"
/ {
model = "TI AM5728 BeagleBoard-X15 rev C";
};
&tpd12s015 {
gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */
<&gpio2 30 GPIO_ACTIVE_HIGH>, /* gpio2_30, LS OE */
<&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
};
&mmc1 {
pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
pinctrl-0 = <&mmc1_pins_default>;
pinctrl-1 = <&mmc1_pins_hs>;
pinctrl-2 = <&mmc1_pins_sdr12>;
pinctrl-3 = <&mmc1_pins_sdr25>;
pinctrl-4 = <&mmc1_pins_sdr50>;
pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;
pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
vmmc-supply = <&vdd_3v3>;
vqmmc-supply = <&ldo1_reg>;
};
&mmc2 {
pinctrl-names = "default", "hs", "ddr_1_8v";
pinctrl-0 = <&mmc2_pins_default>;
pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr_rev20>;
};

View File

@@ -20,5 +20,21 @@
};
&mmc1 {
pinctrl-names = "default", "hs";
pinctrl-0 = <&mmc1_pins_default>;
pinctrl-1 = <&mmc1_pins_hs>;
vmmc-supply = <&ldo1_reg>;
};
&mmc2 {
pinctrl-names = "default", "hs", "ddr_1_8v";
pinctrl-0 = <&mmc2_pins_default>;
pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>;
};
/* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */
&phy1 {
max-speed = <100>;
};

View File

@@ -0,0 +1,617 @@
/*
* Support for CompuLab CL-SOM-AM57x System-on-Module
*
* Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/
* Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "dra74x.dtsi"
/ {
model = "CompuLab CL-SOM-AM57x";
compatible = "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
memory@0 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x20000000>; /* 512 MB - minimal configuration */
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&leds_pins_default>;
led0 {
label = "cl-som-am57x:green";
gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
};
vdd_3v3: fixedregulator-vdd_3v3 {
compatible = "regulator-fixed";
regulator-name = "vdd_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ads7846reg: fixedregulator-ads7846-reg {
compatible = "regulator-fixed";
regulator-name = "ads7846-reg";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
sound0: sound0 {
compatible = "simple-audio-card";
simple-audio-card,name = "CL-SOM-AM57x-Sound-Card";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&dailink0_master>;
simple-audio-card,frame-master = <&dailink0_master>;
simple-audio-card,widgets =
"Headphone", "Headphone Jack",
"Microphone", "Microphone Jack",
"Line", "Line Jack";
simple-audio-card,routing =
"Headphone Jack", "RHPOUT",
"Headphone Jack", "LHPOUT",
"LLINEIN", "Line Jack",
"MICIN", "Mic Bias",
"Mic Bias", "Microphone Jack";
dailink0_master: simple-audio-card,cpu {
sound-dai = <&mcasp3>;
};
simple-audio-card,codec {
sound-dai = <&wm8731>;
system-clock-frequency = <12000000>;
};
};
};
&dra7_pmx_core {
leds_pins_default: leds_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x347c, PIN_OUTPUT | MUX_MODE14) /* gpmc_a15.gpio2_5 */
>;
};
i2c1_pins_default: i2c1_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */
DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */
>;
};
i2c3_pins_default: i2c3_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x36a4, PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */
DRA7XX_CORE_IOPAD(0x36a8, PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */
>;
};
i2c4_pins_default: i2c4_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x36ac, PIN_INPUT| MUX_MODE10) /* mcasp1_acl.i2c4_sda */
DRA7XX_CORE_IOPAD(0x36b0, PIN_INPUT| MUX_MODE10) /* mcasp1_fsr.i2c4_scl */
>;
};
tps659038_pins_default: tps659038_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3818, PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */
>;
};
mmc2_pins_default: mmc2_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
qspi1_pins: pinmux_qspi1_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3474, PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d0 */
DRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d1 */
DRA7XX_CORE_IOPAD(0x3488, PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
DRA7XX_CORE_IOPAD(0x34b8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
DRA7XX_CORE_IOPAD(0x34bc, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
>;
};
cpsw_pins_default: cpsw_pins_default {
pinctrl-single,pins = <
/* Slave at addr 0x0 */
DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii0_tclk */
DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0) /* rgmii0_tctl */
DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3 */
DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td2 */
DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td1 */
DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td0 */
DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rclk */
DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rctl */
DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd3 */
DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd2 */
DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd1 */
DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd0 */
/* Slave at addr 0x1 */
DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_tclk */
DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
>;
};
cpsw_pins_sleep: cpsw_pins_sleep {
pinctrl-single,pins = <
/* Slave 1 */
DRA7XX_CORE_IOPAD(0x3650, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3654, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3658, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x365c, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3660, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3664, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE15)
/* Slave 2 */
DRA7XX_CORE_IOPAD(0x3598, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x359c, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35a0, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35a4, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35a8, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35ac, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE15)
>;
};
davinci_mdio_pins_default: davinci_mdio_pins_default {
pinctrl-single,pins = <
/* MDIO */
DRA7XX_CORE_IOPAD(0x3590, PIN_OUTPUT_PULLUP | MUX_MODE3)/* vin2a_d10.mdio_mclk */
DRA7XX_CORE_IOPAD(0x3594, PIN_INPUT_PULLUP | MUX_MODE3) /* vin2a_d11.mdio_d */
>;
};
davinci_mdio_pins_sleep: davinci_mdio_pins_sleep {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3590, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3594, PIN_INPUT | MUX_MODE15)
>;
};
ads7846_pins: pinmux_ads7846_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3464, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpmc_a9.gpio1_31 */
>;
};
mcasp3_pins_default: mcasp3_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx.mcasp3_aclkx */
DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx.mcasp3_fsx */
DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0.mcasp3_axr0 */
DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1.mcasp3_axr1 */
>;
};
mcasp3_pins_sleep: mcasp3_pins_sleep {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT | MUX_MODE15)
>;
};
};
&i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_default>;
clock-frequency = <400000>;
};
&i2c3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins_default>;
clock-frequency = <400000>;
};
&i2c4 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins_default>;
clock-frequency = <400000>;
tps659038: tps659038@58 {
compatible = "ti,tps659038";
reg = <0x58>;
interrupt-parent = <&gpio1>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&tps659038_pins_default>;
#interrupt-cells = <2>;
interrupt-controller;
ti,system-power-controller;
tps659038_pmic {
compatible = "ti,tps659038-pmic";
regulators {
smps12_reg: smps12 {
/* VDD_MPU */
regulator-name = "smps12";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
smps3_reg: smps3 {
/* VDD_DDR */
regulator-name = "smps3";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
};
smps45_reg: smps45 {
/* VDD_DSPEVE */
regulator-name = "smps45";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
smps6_reg: smps6 {
/* VDD_GPU */
regulator-name = "smps6";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
smps7_reg: smps7 {
/* VDD_CORE */
regulator-name = "smps7";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1160000>;
regulator-always-on;
regulator-boot-on;
};
smps8_reg: smps8 {
/* VDD_IVA */
regulator-name = "smps8";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
smps9_reg: smps9 {
/* PMIC_3V3 */
regulator-name = "smps9";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
ldo1_reg: ldo1 {
/* VDD_SD / VDDSHV8 */
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: ldo2 {
/* VDD_1V8 */
regulator-name = "ldo2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo3_reg: ldo3 {
/* VDDA_1V8_PHYA - supplies VDDA_SATA, VDDA_USB1/2/3 */
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo4_reg: ldo4 {
/* VDDA_1V8_PHYB - supplies VDDA_HDMI, VDDA_PCIE/0/1 */
regulator-name = "ldo4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo9_reg: ldo9 {
/* VDD_RTC */
regulator-name = "ldo9";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
regulator-always-on;
regulator-boot-on;
};
ldoln_reg: ldoln {
/* VDDA_1V8_PLL */
regulator-name = "ldoln";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldousb_reg: ldousb {
/* VDDA_3V_USB: VDDA_USBHS33 */
regulator-name = "ldousb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
/* regen1 not used */
};
};
tps659038_pwr_button: tps659038_pwr_button {
compatible = "ti,palmas-pwrbutton";
interrupt-parent = <&tps659038>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
wakeup-source;
ti,palmas-long-press-seconds = <12>;
};
tps659038_gpio: tps659038_gpio {
compatible = "ti,palmas-gpio";
gpio-controller;
#gpio-cells = <2>;
};
};
rtc0: rtc@56 {
compatible = "emmicro,em3027";
reg = <0x56>;
};
eeprom_module: atmel@50 {
compatible = "atmel,24c08";
reg = <0x50>;
pagesize = <16>;
};
wm8731: wm8731@1a {
#sound-dai-cells = <0>;
compatible = "wlf,wm8731";
reg = <0x1a>;
status = "okay";
};
};
&cpu0 {
cpu0-supply = <&smps12_reg>;
voltage-tolerance = <1>;
};
&sata {
status = "okay";
};
&mailbox5 {
status = "okay";
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
status = "okay";
};
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
status = "okay";
};
};
&mailbox6 {
status = "okay";
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
status = "okay";
};
mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
status = "okay";
};
};
&mmc2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins_default>;
vmmc-supply = <&vdd_3v3>;
bus-width = <8>;
ti,non-removable;
cap-mmc-dual-data-rate;
};
&qspi {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&qspi1_pins>;
spi-max-frequency = <48000000>;
spi_flash: spi_flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,m25p80", "jedec,spi-nor";
reg = <0>; /* CS0 */
spi-max-frequency = <48000000>;
partition@0 {
label = "uboot";
reg = <0x0 0xc0000>;
};
partition@c0000 {
label = "uboot environment";
reg = <0xc0000 0x40000>;
};
partition@100000 {
label = "reserved";
reg = <0x100000 0x0>;
};
};
/* touch controller */
ads7846@0 {
pinctrl-names = "default";
pinctrl-0 = <&ads7846_pins>;
compatible = "ti,ads7846";
vcc-supply = <&ads7846reg>;
reg = <1>; /* CS1 */
spi-max-frequency = <1500000>;
interrupt-parent = <&gpio1>;
interrupts = <31 0>;
pendown-gpio = <&gpio1 31 0>;
ti,x-min = /bits/ 16 <0x0>;
ti,x-max = /bits/ 16 <0x0fff>;
ti,y-min = /bits/ 16 <0x0>;
ti,y-max = /bits/ 16 <0x0fff>;
ti,x-plate-ohms = /bits/ 16 <180>;
ti,pressure-max = /bits/ 16 <255>;
ti,debounce-max = /bits/ 16 <30>;
ti,debounce-tol = /bits/ 16 <10>;
ti,debounce-rep = /bits/ 16 <1>;
wakeup-source;
};
};
&mac {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_pins_default>;
pinctrl-1 = <&cpsw_pins_sleep>;
dual_emac;
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rgmii-txid";
dual_emac_res_vlan = <0>;
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "rgmii-txid";
dual_emac_res_vlan = <1>;
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_pins_default>;
pinctrl-1 = <&davinci_mdio_pins_sleep>;
};
&usb2_phy1 {
phy-supply = <&ldousb_reg>;
};
&usb2_phy2 {
phy-supply = <&ldousb_reg>;
};
&usb1 {
dr_mode = "host";
};
&usb2 {
dr_mode = "host";
};
&mcasp3 {
#sound-dai-cells = <0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mcasp3_pins_default>;
pinctrl-1 = <&mcasp3_pins_sleep>;
status = "okay";
op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
/* 4 serializers */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1 2 0 0
>;
};
&gpio3 {
status = "okay";
ti,no-reset-on-init;
};
&gpio2 {
status = "okay";
ti,no-reset-on-init;
};

View File

@@ -47,6 +47,74 @@
regulator-always-on;
regulator-boot-on;
};
leds-iio {
status = "disabled";
compatible = "gpio-leds";
led-out0 {
label = "out0";
gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-out1 {
label = "out1";
gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-out2 {
label = "out2";
gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-out3 {
label = "out3";
gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-out4 {
label = "out4";
gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-out5 {
label = "out5";
gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-out6 {
label = "out6";
gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-out7 {
label = "out7";
gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
};
&dra7_pmx_core {
dcan1_pins_default: dcan1_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
DRA7XX_CORE_IOPAD(0x37d4, PIN_INPUT_PULLUP | MUX_MODE0) /* dcan1_rx */
>;
};
dcan1_pins_sleep: dcan1_pins_sleep {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
DRA7XX_CORE_IOPAD(0x37d4, MUX_MODE15 | PULL_UP) /* dcan1_rx.off */
>;
};
};
&i2c1 {
@@ -61,6 +129,7 @@
#interrupt-cells = <2>;
interrupt-controller;
ti,system-power-controller;
ti,palmas-override-powerhold;
tps659038_pmic {
compatible = "ti,tps659038-pmic";
@@ -254,6 +323,35 @@
gpio-controller;
#gpio-cells = <2>;
};
extcon_usb2: tps659038_usb {
compatible = "ti,palmas-usb-vid";
ti,enable-vbus-detection;
ti,enable-id-detection;
/* ID & VBUS GPIOs provided in board dts */
};
};
tpic2810: tpic2810@60 {
compatible = "ti,tpic2810";
reg = <0x60>;
gpio-controller;
#gpio-cells = <2>;
};
};
&mcspi3 {
status = "okay";
ti,pindir-d0-out-d1-in;
sn65hvs882: sn65hvs882@0 {
compatible = "pisosr-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0>;
spi-max-frequency = <1000000>;
spi-cpol;
};
};
@@ -298,7 +396,15 @@
};
&usb2 {
dr_mode = "otg";
dr_mode = "peripheral";
};
&mmc1 {
status = "okay";
vmmc-supply = <&v3_3d>;
vqmmc-supply = <&ldo1_reg>;
bus-width = <4>;
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
};
&mmc2 {
@@ -309,12 +415,20 @@
max-frequency = <96000000>;
};
&dcan1 {
status = "okay";
pinctrl-names = "default", "sleep", "active";
pinctrl-0 = <&dcan1_pins_sleep>;
pinctrl-1 = <&dcan1_pins_sleep>;
pinctrl-2 = <&dcan1_pins_default>;
};
&qspi {
status = "okay";
spi-max-frequency = <76800000>;
m25p80@0 {
compatible = "s25fl256s1", "spi-flash", "jedec,spi-nor";
compatible = "s25fl256s1", "jedec,spi-nor";
spi-max-frequency = <76800000>;
reg = <0>;
spi-tx-bus-width = <1>;

View File

@@ -0,0 +1,179 @@
/*
* Support for CompuLab SBC-AM57x single board computer
*
* Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/
* Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*/
#include "am57xx-cl-som-am57x.dts"
#include "compulab-sb-som.dtsi"
/ {
model = "CompuLab CL-SOM-AM57x on SB-SOM-AM57x";
compatible = "compulab,sbc-am57x", "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
aliases {
display0 = &lcd0;
display1 = &hdmi;
};
};
&dra7_pmx_core {
uart3_pins_default: uart3_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
>;
};
mmc1_pins_default: mmc1_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1_sdcd.gpio6_27 */
DRA7XX_CORE_IOPAD(0x377c, PIN_INPUT | MUX_MODE14) /* mmc1_sdwp.gpio6_28 */
>;
};
usb1_pins: pinmux_usb1_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
>;
};
i2c5_pins_default: i2c5_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT| MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT| MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
>;
};
lcd_pins_default: lcd_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3564, PIN_OUTPUT | MUX_MODE14) /* vin2a_vsync0.gpio4_0 */
>;
};
hdmi_pins: pinmux_hdmi_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
>;
};
hdmi_conn_pins: pinmux_hdmi_conn_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT | MUX_MODE14) /* spi1_cs2.gpio7_12 */
>;
};
};
&uart3 {
status = "okay";
interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<&dra7_pmx_core 0x3f8>;
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins_default>;
};
&mmc1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_default>;
vmmc-supply = <&ldo1_reg>;
bus-width = <4>;
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>;
};
&usb1 {
pinctrl-names = "default";
pinctrl-0 = <&usb1_pins>;
};
&i2c5 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins_default>;
clock-frequency = <400000>;
eeprom_base: atmel@54 {
compatible = "atmel,24c08";
reg = <0x54>;
pagesize = <16>;
};
pca9555: pca9555@20 {
compatible = "nxp,pca9555";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
};
&dss {
status = "ok";
vdda_video-supply = <&ldoln_reg>;
port {
dpi_lcd_out: endpoint {
remote-endpoint = <&lcd_in>;
data-lines = <24>;
};
};
};
&lcd0 {
pinctrl-names = "default";
pinctrl-0 = <&lcd_pins_default>;
enable-gpios = <&pca9555 14 GPIO_ACTIVE_HIGH
&gpio4 0 GPIO_ACTIVE_HIGH>;
port {
lcd_in: endpoint {
remote-endpoint = <&dpi_lcd_out>;
data-lines = <24>;
};
};
};
&hdmi {
status = "ok";
vdda-supply = <&ldo4_reg>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_pins>;
port {
hdmi_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
lanes = <1 0 3 2 5 4 7 6>;
};
};
};
&hdmi_conn {
pinctrl-names = "default";
pinctrl-0 = <&hdmi_conn_pins>;
hpd-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_out>;
};
};
};

View File

@@ -154,7 +154,7 @@
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p128", "jedec,spi-nor";
compatible = "st,m25p128", "jedec,spi-nor", "spi-flash";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
m25p,fast-read;

View File

@@ -0,0 +1,215 @@
/*
* at91-sama5d27_som1_ek.dts - Device Tree file for SAMA5D27 SOM1 EK board
*
* Copyright (C) 2017 Microchip Corporation
* Wenyou Yang <wenyou.yang@microchip.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sama5d27_som1.dtsi"
/ {
model = "Atmel SAMA5D27 SOM1 EK";
compatible = "atmel,sama5d27-som1-ek", "atmel,sama5d2", "atmel,sama5";
chosen {
u-boot,dm-pre-reloc;
stdout-path = &uart1;
};
ahb {
usb1: ohci@00400000 {
num-ports = <3>;
atmel,vbus-gpio = <&pioA 42 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_default>;
status = "okay";
};
usb2: ehci@00500000 {
status = "okay";
};
sdmmc0: sdio-host@a0000000 {
bus-width = <8>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>;
status = "okay";
u-boot,dm-pre-reloc;
};
sdmmc1: sdio-host@b0000000 {
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default &pinctrl_sdmmc1_ck_cd_default>;
status = "okay"; /* conflict with qspi0 */
u-boot,dm-pre-reloc;
};
apb {
hlcdc: hlcdc@f0000000 {
atmel,vl-bpix = <4>;
atmel,guard-time = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_pwm &pinctrl_lcd_rgb666>;
status = "okay";
u-boot,dm-pre-reloc;
display-timings {
u-boot,dm-pre-reloc;
480x272 {
clock-frequency = <9000000>;
hactive = <480>;
vactive = <272>;
hsync-len = <41>;
hfront-porch = <2>;
hback-porch = <2>;
vfront-porch = <2>;
vback-porch = <2>;
vsync-len = <11>;
u-boot,dm-pre-reloc;
};
};
};
uart1: serial@f8020000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
status = "okay";
u-boot,dm-pre-reloc;
};
pioA: gpio@fc038000 {
pinctrl {
pinctrl_lcd_base: pinctrl_lcd_base {
pinmux = <PIN_PC5__LCDVSYNC>,
<PIN_PC6__LCDHSYNC>,
<PIN_PC8__LCDDEN>,
<PIN_PC7__LCDPCK>;
bias-disable;
};
pinctrl_lcd_pwm: pinctrl_lcd_pwm {
pinmux = <PIN_PC3__LCDPWM>;
bias-disable;
};
pinctrl_lcd_rgb666: pinctrl_lcd_rgb666 {
pinmux = <PIN_PB13__LCDDAT2>,
<PIN_PB14__LCDDAT3>,
<PIN_PB15__LCDDAT4>,
<PIN_PB16__LCDDAT5>,
<PIN_PB17__LCDDAT6>,
<PIN_PB18__LCDDAT7>,
<PIN_PB21__LCDDAT10>,
<PIN_PB22__LCDDAT11>,
<PIN_PB23__LCDDAT12>,
<PIN_PB24__LCDDAT13>,
<PIN_PB25__LCDDAT14>,
<PIN_PB26__LCDDAT15>,
<PIN_PB29__LCDDAT18>,
<PIN_PB30__LCDDAT19>,
<PIN_PB31__LCDDAT20>,
<PIN_PC0__LCDDAT21>,
<PIN_PC1__LCDDAT22>,
<PIN_PC2__LCDDAT23>;
bias-disable;
};
pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default {
pinmux = <PIN_PA1__SDMMC0_CMD>,
<PIN_PA2__SDMMC0_DAT0>,
<PIN_PA3__SDMMC0_DAT1>,
<PIN_PA4__SDMMC0_DAT2>,
<PIN_PA5__SDMMC0_DAT3>,
<PIN_PA6__SDMMC0_DAT4>,
<PIN_PA7__SDMMC0_DAT5>,
<PIN_PA8__SDMMC0_DAT6>,
<PIN_PA9__SDMMC0_DAT7>;
bias-pull-up;
u-boot,dm-pre-reloc;
};
pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default {
pinmux = <PIN_PA0__SDMMC0_CK>,
<PIN_PA10__SDMMC0_RSTN>,
<PIN_PA13__SDMMC0_CD>;
bias-disable;
u-boot,dm-pre-reloc;
};
pinctrl_sdmmc1_cmd_dat_default: sdmmc1_cmd_dat_default {
pinmux = <PIN_PA28__SDMMC1_CMD>,
<PIN_PA18__SDMMC1_DAT0>,
<PIN_PA19__SDMMC1_DAT1>,
<PIN_PA20__SDMMC1_DAT2>,
<PIN_PA21__SDMMC1_DAT3>;
bias-pull-up;
u-boot,dm-pre-reloc;
};
pinctrl_sdmmc1_ck_cd_default: sdmmc1_ck_cd_default {
pinmux = <PIN_PA22__SDMMC1_CK>,
<PIN_PA30__SDMMC1_CD>;
bias-disable;
u-boot,dm-pre-reloc;
};
pinctrl_uart1_default: uart1_default {
pinmux = <PIN_PD2__URXD1>,
<PIN_PD3__UTXD1>;
bias-disable;
u-boot,dm-pre-reloc;
};
pinctrl_usb_default: usb_default {
pinmux = <PIN_PB10__GPIO>;
bias-disable;
};
pinctrl_usba_vbus: usba_vbus {
pinmux = <PIN_PA31__GPIO>;
bias-disable;
};
};
};
};
};
};

View File

@@ -41,6 +41,31 @@
};
apb {
hlcdc: hlcdc@f0000000 {
atmel,vl-bpix = <4>;
atmel,guard-time = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_pwm &pinctrl_lcd_rgb666>;
status = "okay";
u-boot,dm-pre-reloc;
display-timings {
u-boot,dm-pre-reloc;
480x272 {
clock-frequency = <9000000>;
hactive = <480>;
vactive = <272>;
hsync-len = <41>;
hfront-porch = <2>;
hback-porch = <2>;
vfront-porch = <2>;
vback-porch = <2>;
vsync-len = <11>;
u-boot,dm-pre-reloc;
};
};
};
qspi0: spi@f0020000 {
status = "okay";
@@ -102,6 +127,11 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_default>;
status = "okay";
i2c_eeprom: i2c_eeprom@5c {
compatible = "atmel,24mac402";
reg = <0x5c>;
};
};
pioA: gpio@fc038000 {
@@ -112,6 +142,41 @@
bias-disable;
};
pinctrl_lcd_base: pinctrl_lcd_base {
pinmux = <PIN_PC30__LCDVSYNC>,
<PIN_PC31__LCDHSYNC>,
<PIN_PD1__LCDDEN>,
<PIN_PD0__LCDPCK>;
bias-disable;
};
pinctrl_lcd_pwm: pinctrl_lcd_pwm {
pinmux = <PIN_PC28__LCDPWM>;
bias-disable;
};
pinctrl_lcd_rgb666: pinctrl_lcd_rgb666 {
pinmux = <PIN_PC10__LCDDAT2>,
<PIN_PC11__LCDDAT3>,
<PIN_PC12__LCDDAT4>,
<PIN_PC13__LCDDAT5>,
<PIN_PC14__LCDDAT6>,
<PIN_PC15__LCDDAT7>,
<PIN_PC16__LCDDAT10>,
<PIN_PC17__LCDDAT11>,
<PIN_PC18__LCDDAT12>,
<PIN_PC19__LCDDAT13>,
<PIN_PC20__LCDDAT14>,
<PIN_PC21__LCDDAT15>,
<PIN_PC22__LCDDAT18>,
<PIN_PC23__LCDDAT19>,
<PIN_PC24__LCDDAT20>,
<PIN_PC25__LCDDAT21>,
<PIN_PC26__LCDDAT22>,
<PIN_PC27__LCDDAT23>;
bias-disable;
};
pinctrl_macb0_phy_irq: macb0_phy_irq {
pinmux = <PIN_PC9__GPIO>;
bias-disable;

View File

@@ -74,6 +74,31 @@
ahb {
apb {
hlcdc: hlcdc@f0000000 {
atmel,vl-bpix = <4>;
atmel,guard-time = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_pwm &pinctrl_lcd_rgb888>;
status = "okay";
u-boot,dm-pre-reloc;
display-timings {
u-boot,dm-pre-reloc;
480x272 {
clock-frequency = <9000000>;
hactive = <480>;
vactive = <272>;
hsync-len = <41>;
hfront-porch = <2>;
hback-porch = <2>;
vfront-porch = <2>;
vback-porch = <2>;
vsync-len = <11>;
u-boot,dm-pre-reloc;
};
};
};
spi0: spi@f8010000 {
u-boot,dm-pre-reloc;
cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
@@ -88,6 +113,11 @@
i2c0: i2c@f8014000 {
status = "okay";
i2c_eeprom: i2c_eeprom@5c {
compatible = "atmel,24mac402";
reg = <0x5c>;
};
};
macb0: ethernet@f8020000 {

View File

@@ -75,6 +75,32 @@
ahb {
apb {
hlcdc: hlcdc@f0000000 {
atmel,vl-bpix = <4>;
atmel,output-mode = <18>;
atmel,guard-time = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_pwm &pinctrl_lcd_rgb666>;
status = "okay";
u-boot,dm-pre-reloc;
display-timings {
u-boot,dm-pre-reloc;
800x480 {
clock-frequency = <33260000>;
hactive = <800>;
vactive = <480>;
hsync-len = <5>;
hfront-porch = <128>;
hback-porch = <0>;
vfront-porch = <23>;
vback-porch = <22>;
vsync-len = <5>;
u-boot,dm-pre-reloc;
};
};
};
adc0: adc@fc034000 {
pinctrl-names = "default";
pinctrl-0 = <

58
arch/arm/dts/axp223.dtsi Normal file
View File

@@ -0,0 +1,58 @@
/*
* Copyright 2016 Free Electrons
*
* Quentin Schulz <quentin.schulz@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* AXP223 Integrated Power Management Chip
* http://www.x-powers.com/product/AXP22X.php
* http://dl.linux-sunxi.org/AXP/AXP223-en.pdf
*
* The AXP223 shares most of its logic with the AXP221 but it has some
* differences, for the VBUS driver for example.
*/
#include "axp22x.dtsi"
&usb_power_supply {
compatible = "x-powers,axp223-usb-power-supply";
};

View File

@@ -52,6 +52,16 @@
interrupt-controller;
#interrupt-cells = <1>;
ac_power_supply: ac-power-supply {
compatible = "x-powers,axp221-ac-power-supply";
status = "disabled";
};
battery_power_supply: battery-power-supply {
compatible = "x-powers,axp221-battery-power-supply";
status = "disabled";
};
regulators {
/* Default work frequency for buck regulators */
x-powers,dcdc-freq = <3000>;

View File

@@ -1,6 +1,7 @@
/dts-v1/;
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
/ {
compatible = "raspberrypi,model-a-plus", "brcm,bcm2835";
@@ -21,7 +22,72 @@
};
&gpio {
pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>;
/*
* This is based on the unreleased schematic for the Model A+.
*
* Legend:
* "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
gpio-line-names = "SDA0",
"SCL0",
"SDA1",
"SCL1",
"GPIO_GCLK",
"GPIO5",
"GPIO6",
"SPI_CE1_N",
"SPI_CE0_N",
"SPI_MISO",
"SPI_MOSI",
"SPI_SCLK",
"GPIO12",
"GPIO13",
/* Serial port */
"TXD0",
"RXD0",
"GPIO16",
"GPIO17",
"GPIO18",
"GPIO19",
"GPIO20",
"GPIO21",
"GPIO22",
"GPIO23",
"GPIO24",
"GPIO25",
"GPIO26",
"GPIO27",
"SDA0",
"SCL0",
"NC", /* GPIO30 */
"NC", /* GPIO31 */
"CAM_GPIO1", /* GPIO32 */
"NC", /* GPIO33 */
"NC", /* GPIO34 */
"PWR_LOW_N", /* GPIO35 */
"NC", /* GPIO36 */
"NC", /* GPIO37 */
"USB_LIMIT", /* GPIO38 */
"NC", /* GPIO39 */
"PWM0_OUT", /* GPIO40 */
"CAM_GPIO0", /* GPIO41 */
"NC", /* GPIO42 */
"NC", /* GPIO43 */
"NC", /* GPIO44 */
"PWM1_OUT", /* GPIO45 */
"HDMI_HPD_N",
"STATUS_LED",
/* Used by SD Card */
"SD_CLK_R",
"SD_CMD_R",
"SD_DATA0_R",
"SD_DATA1_R",
"SD_DATA2_R",
"SD_DATA3_R";
pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
/* I2S interface */
i2s_alt0: i2s_alt0 {
@@ -33,3 +99,9 @@
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio14>;
status = "okay";
};

View File

@@ -1,6 +1,7 @@
/dts-v1/;
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
/ {
compatible = "raspberrypi,model-a", "brcm,bcm2835";
@@ -14,7 +15,74 @@
};
&gpio {
pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>;
/*
* Taken from Raspberry-Pi-Rev-1.0-Model-AB-Schematics.pdf
* RPI00021 sheet 02
*
* Legend:
* "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
gpio-line-names = "SDA0",
"SCL0",
"SDA1",
"SCL1",
"GPIO_GCLK",
"CAM_GPIO1",
"LAN_RUN",
"SPI_CE1_N",
"SPI_CE0_N",
"SPI_MISO",
"SPI_MOSI",
"SPI_SCLK",
"NC", /* GPIO12 */
"NC", /* GPIO13 */
/* Serial port */
"TXD0",
"RXD0",
"STATUS_LED_N",
"GPIO17",
"GPIO18",
"NC", /* GPIO19 */
"NC", /* GPIO20 */
"GPIO21",
"GPIO22",
"GPIO23",
"GPIO24",
"GPIO25",
"NC", /* GPIO26 */
"CAM_GPIO0",
/* Binary number representing build/revision */
"CONFIG0",
"CONFIG1",
"CONFIG2",
"CONFIG3",
"NC", /* GPIO32 */
"NC", /* GPIO33 */
"NC", /* GPIO34 */
"NC", /* GPIO35 */
"NC", /* GPIO36 */
"NC", /* GPIO37 */
"NC", /* GPIO38 */
"NC", /* GPIO39 */
"PWM0_OUT",
"NC", /* GPIO41 */
"NC", /* GPIO42 */
"NC", /* GPIO43 */
"NC", /* GPIO44 */
"PWM1_OUT",
"HDMI_HPD_P",
"SD_CARD_DET",
/* Used by SD Card */
"SD_CLK_R",
"SD_CMD_R",
"SD_DATA0_R",
"SD_DATA1_R",
"SD_DATA2_R",
"SD_DATA3_R";
pinctrl-0 = <&gpioout &alt0 &i2s_alt2>;
/* I2S interface */
i2s_alt2: i2s_alt2 {
@@ -26,3 +94,9 @@
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio14>;
status = "okay";
};

View File

@@ -2,6 +2,7 @@
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi"
#include "bcm283x-rpi-smsc9514.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
/ {
compatible = "raspberrypi,model-b-plus", "brcm,bcm2835";
@@ -22,7 +23,73 @@
};
&gpio {
pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>;
/*
* Taken from Raspberry-Pi-B-Plus-V1.2-Schematics.pdf
* RPI-BPLUS sheet 1
*
* Legend:
* "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
gpio-line-names = "SDA0",
"SCL0",
"SDA1",
"SCL1",
"GPIO_GCLK",
"GPIO5",
"GPIO6",
"SPI_CE1_N",
"SPI_CE0_N",
"SPI_MISO",
"SPI_MOSI",
"SPI_SCLK",
"GPIO12",
"GPIO13",
/* Serial port */
"TXD0",
"RXD0",
"GPIO16",
"GPIO17",
"GPIO18",
"GPIO19",
"GPIO20",
"GPIO21",
"GPIO22",
"GPIO23",
"GPIO24",
"GPIO25",
"GPIO26",
"GPIO27",
"SDA0",
"SCL0",
"NC", /* GPIO30 */
"LAN_RUN", /* GPIO31 */
"CAM_GPIO1", /* GPIO32 */
"NC", /* GPIO33 */
"NC", /* GPIO34 */
"PWR_LOW_N", /* GPIO35 */
"NC", /* GPIO36 */
"NC", /* GPIO37 */
"USB_LIMIT", /* GPIO38 */
"NC", /* GPIO39 */
"PWM0_OUT", /* GPIO40 */
"CAM_GPIO0", /* GPIO41 */
"NC", /* GPIO42 */
"NC", /* GPIO43 */
"ETHCLK", /* GPIO44 */
"PWM1_OUT", /* GPIO45 */
"HDMI_HPD_N",
"STATUS_LED",
/* Used by SD Card */
"SD_CLK_R",
"SD_CMD_R",
"SD_DATA0_R",
"SD_DATA1_R",
"SD_DATA2_R",
"SD_DATA3_R";
pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
/* I2S interface */
i2s_alt0: i2s_alt0 {
@@ -34,3 +101,9 @@
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio14>;
status = "okay";
};

View File

@@ -2,6 +2,7 @@
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi"
#include "bcm283x-rpi-smsc9512.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
/ {
compatible = "raspberrypi,model-b-rev2", "brcm,bcm2835";
@@ -15,7 +16,73 @@
};
&gpio {
pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>;
/*
* Taken from Raspberry-Pi-Rev-2.0-Model-AB-Schematics.pdf
* RPI00022 sheet 02
*
* Legend:
* "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
gpio-line-names = "SDA0",
"SCL0",
"SDA1",
"SCL1",
"GPIO_GCLK",
"CAM_CLK",
"LAN_RUN",
"SPI_CE1_N",
"SPI_CE0_N",
"SPI_MISO",
"SPI_MOSI",
"SPI_SCLK",
"NC", /* GPIO12 */
"NC", /* GPIO13 */
/* Serial port */
"TXD0",
"RXD0",
"STATUS_LED_N",
"GPIO17",
"GPIO18",
"NC", /* GPIO19 */
"NC", /* GPIO20 */
"CAM_GPIO",
"GPIO22",
"GPIO23",
"GPIO24",
"GPIO25",
"NC", /* GPIO26 */
"GPIO27",
"GPIO28",
"GPIO29",
"GPIO30",
"GPIO31",
"NC", /* GPIO32 */
"NC", /* GPIO33 */
"NC", /* GPIO34 */
"NC", /* GPIO35 */
"NC", /* GPIO36 */
"NC", /* GPIO37 */
"NC", /* GPIO38 */
"NC", /* GPIO39 */
"PWM0_OUT",
"NC", /* GPIO41 */
"NC", /* GPIO42 */
"NC", /* GPIO43 */
"NC", /* GPIO44 */
"PWM1_OUT",
"HDMI_HPD_P",
"SD_CARD_DET",
/* Used by SD Card */
"SD_CLK_R",
"SD_CMD_R",
"SD_DATA0_R",
"SD_DATA1_R",
"SD_DATA2_R",
"SD_DATA3_R";
pinctrl-0 = <&gpioout &alt0 &i2s_alt2>;
/* I2S interface */
i2s_alt2: i2s_alt2 {
@@ -27,3 +94,9 @@
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio14>;
status = "okay";
};

View File

@@ -2,6 +2,7 @@
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi"
#include "bcm283x-rpi-smsc9512.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
/ {
compatible = "raspberrypi,model-b", "brcm,bcm2835";
@@ -15,9 +16,82 @@
};
&gpio {
pinctrl-0 = <&gpioout &alt0 &alt3>;
/*
* Taken from Raspberry-Pi-Rev-1.0-Model-AB-Schematics.pdf
* RPI00021 sheet 02
*
* Legend:
* "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
gpio-line-names = "SDA0",
"SCL0",
"SDA1",
"SCL1",
"GPIO_GCLK",
"CAM_GPIO1",
"LAN_RUN",
"SPI_CE1_N",
"SPI_CE0_N",
"SPI_MISO",
"SPI_MOSI",
"SPI_SCLK",
"NC", /* GPIO12 */
"NC", /* GPIO13 */
/* Serial port */
"TXD0",
"RXD0",
"STATUS_LED_N",
"GPIO17",
"GPIO18",
"NC", /* GPIO19 */
"NC", /* GPIO20 */
"GPIO21",
"GPIO22",
"GPIO23",
"GPIO24",
"GPIO25",
"NC", /* GPIO26 */
"CAM_GPIO0",
/* Binary number representing build/revision */
"CONFIG0",
"CONFIG1",
"CONFIG2",
"CONFIG3",
"NC", /* GPIO32 */
"NC", /* GPIO33 */
"NC", /* GPIO34 */
"NC", /* GPIO35 */
"NC", /* GPIO36 */
"NC", /* GPIO37 */
"NC", /* GPIO38 */
"NC", /* GPIO39 */
"PWM0_OUT",
"NC", /* GPIO41 */
"NC", /* GPIO42 */
"NC", /* GPIO43 */
"NC", /* GPIO44 */
"PWM1_OUT",
"HDMI_HPD_P",
"SD_CARD_DET",
/* Used by SD Card */
"SD_CLK_R",
"SD_CMD_R",
"SD_DATA0_R",
"SD_DATA1_R",
"SD_DATA2_R",
"SD_DATA3_R";
pinctrl-0 = <&gpioout &alt0>;
};
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio14>;
status = "okay";
};

View File

@@ -39,22 +39,21 @@
};
alt0: alt0 {
brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>;
brcm,pins = <4 5 7 8 9 10 11>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
alt3: alt3 {
brcm,pins = <48 49 50 51 52 53>;
brcm,function = <BCM2835_FSEL_ALT3>;
};
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_gpio0>;
status = "okay";
clock-frequency = <100000>;
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_gpio2>;
status = "okay";
clock-frequency = <100000>;
};
@@ -64,11 +63,21 @@
};
&sdhci {
pinctrl-names = "default";
pinctrl-0 = <&emmc_gpio48>;
status = "okay";
bus-width = <4>;
};
&sdhost {
pinctrl-names = "default";
pinctrl-0 = <&sdhost_gpio48>;
bus-width = <4>;
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>;
status = "okay";
};
@@ -84,3 +93,16 @@
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
status = "okay";
};
&vec {
power-domains = <&power RPI_POWER_DOMAIN_VEC>;
status = "okay";
};
&dsi0 {
power-domains = <&power RPI_POWER_DOMAIN_DSI0>;
};
&dsi1 {
power-domains = <&power RPI_POWER_DOMAIN_DSI1>;
};

View File

@@ -23,3 +23,13 @@
};
};
};
&cpu_thermal {
coefficients = <(-538) 407000>;
};
/* enable thermal sensor with the correct compatible property set */
&thermal {
compatible = "brcm,bcm2835-thermal";
status = "okay";
};

View File

@@ -2,6 +2,7 @@
#include "bcm2836.dtsi"
#include "bcm2835-rpi.dtsi"
#include "bcm283x-rpi-smsc9514.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
/ {
compatible = "raspberrypi,2-model-b", "brcm,bcm2836";
@@ -26,7 +27,7 @@
};
&gpio {
pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>;
pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
/* I2S interface */
i2s_alt0: i2s_alt0 {
@@ -38,3 +39,9 @@
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio14>;
status = "okay";
};

View File

@@ -36,6 +36,7 @@
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "brcm,bcm2836-smp";
v7_cpu0: cpu@0 {
device_type = "cpu";
@@ -76,3 +77,13 @@
interrupt-parent = <&local_intc>;
interrupts = <8>;
};
&cpu_thermal {
coefficients = <(-538) 407000>;
};
/* enable thermal sensor with the correct compatible property set */
&thermal {
compatible = "brcm,bcm2836-thermal";
status = "okay";
};

View File

@@ -2,6 +2,7 @@
#include "bcm2837.dtsi"
#include "bcm2835-rpi.dtsi"
#include "bcm283x-rpi-smsc9514.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
/ {
compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
@@ -15,16 +16,36 @@
act {
gpios = <&gpio 47 0>;
};
pwr {
label = "PWR";
gpios = <&gpio 35 0>;
default-state = "keep";
linux,default-trigger = "default-on";
};
};
};
&uart1 {
/* uart0 communicates with the BT module */
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio32 &gpclk2_gpio43>;
status = "okay";
};
/* uart1 is mapped to the pin header */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_gpio14>;
status = "okay";
};
/* SDHCI is used to control the SDIO for wireless */
&sdhci {
pinctrl-names = "default";
pinctrl-0 = <&emmc_gpio34>;
status = "okay";
bus-width = <4>;
non-removable;
};
/* SDHOST is used to drive the SD card */
&sdhost {
pinctrl-names = "default";
pinctrl-0 = <&sdhost_gpio48>;
status = "okay";
bus-width = <4>;
};

View File

@@ -1,7 +1,7 @@
#include "bcm283x.dtsi"
/ {
compatible = "brcm,bcm2836";
compatible = "brcm,bcm2837";
soc {
ranges = <0x7e000000 0x3f000000 0x1000000>,
@@ -30,6 +30,7 @@
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
cpu0: cpu@0 {
device_type = "cpu";
@@ -74,3 +75,13 @@
interrupt-parent = <&local_intc>;
interrupts = <8>;
};
&cpu_thermal {
coefficients = <(-538) 412000>;
};
/* enable thermal sensor with the correct compatible property set */
&thermal {
compatible = "brcm,bcm2837-thermal";
status = "okay";
};

View File

@@ -1,6 +1,6 @@
/ {
aliases {
ethernet = &ethernet;
ethernet0 = &ethernet;
};
};

View File

@@ -1,6 +1,6 @@
/ {
aliases {
ethernet = &ethernet;
ethernet0 = &ethernet;
};
};

View File

@@ -0,0 +1,3 @@
&usb {
dr_mode = "host";
};

View File

@@ -3,6 +3,11 @@
#include <dt-bindings/clock/bcm2835-aux.h>
#include <dt-bindings/gpio/gpio.h>
/* firmware-provided startup stubs live here, where the secondary CPUs are
* spinning.
*/
/memreserve/ 0x00000000 0x00001000;
/* This include file covers the common peripherals and configuration between
* bcm2835 and bcm2836 implementations, leaving the CPU configuration to
* bcm2835.dtsi and bcm2836.dtsi.
@@ -19,6 +24,26 @@
bootargs = "earlyprintk console=ttyAMA0";
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <0>;
polling-delay = <1000>;
thermal-sensors = <&thermal>;
trips {
cpu-crit {
temperature = <80000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
};
};
};
soc: soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -93,10 +118,13 @@
#clock-cells = <1>;
reg = <0x7e101000 0x2000>;
/* CPRMAN derives everything from the platform's
* oscillator.
/* CPRMAN derives almost everything from the
* platform's oscillator. However, the DSI
* pixel clocks come from the DSI analog PHY.
*/
clocks = <&clk_osc>;
clocks = <&clk_osc>,
<&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
<&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
};
rng@7e104000 {
@@ -104,7 +132,7 @@
reg = <0x7e104000 0x10>;
};
mailbox: mailbox@7e00b800 {
mailbox: mailbox@7e00b880 {
compatible = "brcm,bcm2835-mbox";
reg = <0x7e00b880 0x40>;
interrupts = <0 1>;
@@ -132,6 +160,213 @@
interrupt-controller;
#interrupt-cells = <2>;
/* Defines pin muxing groups according to
* BCM2835-ARM-Peripherals.pdf page 102.
*
* While each pin can have its mux selected
* for various functions individually, some
* groups only make sense to switch to a
* particular function together.
*/
dpi_gpio0: dpi_gpio0 {
brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27>;
brcm,function = <BCM2835_FSEL_ALT2>;
};
emmc_gpio22: emmc_gpio22 {
brcm,pins = <22 23 24 25 26 27>;
brcm,function = <BCM2835_FSEL_ALT3>;
};
emmc_gpio34: emmc_gpio34 {
brcm,pins = <34 35 36 37 38 39>;
brcm,function = <BCM2835_FSEL_ALT3>;
brcm,pull = <BCM2835_PUD_OFF
BCM2835_PUD_UP
BCM2835_PUD_UP
BCM2835_PUD_UP
BCM2835_PUD_UP
BCM2835_PUD_UP>;
};
emmc_gpio48: emmc_gpio48 {
brcm,pins = <48 49 50 51 52 53>;
brcm,function = <BCM2835_FSEL_ALT3>;
};
gpclk0_gpio4: gpclk0_gpio4 {
brcm,pins = <4>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
gpclk1_gpio5: gpclk1_gpio5 {
brcm,pins = <5>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
gpclk1_gpio42: gpclk1_gpio42 {
brcm,pins = <42>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
gpclk1_gpio44: gpclk1_gpio44 {
brcm,pins = <44>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
gpclk2_gpio6: gpclk2_gpio6 {
brcm,pins = <6>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
gpclk2_gpio43: gpclk2_gpio43 {
brcm,pins = <43>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
i2c0_gpio0: i2c0_gpio0 {
brcm,pins = <0 1>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
i2c0_gpio28: i2c0_gpio28 {
brcm,pins = <28 29>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
i2c0_gpio44: i2c0_gpio44 {
brcm,pins = <44 45>;
brcm,function = <BCM2835_FSEL_ALT1>;
};
i2c1_gpio2: i2c1_gpio2 {
brcm,pins = <2 3>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
i2c1_gpio44: i2c1_gpio44 {
brcm,pins = <44 45>;
brcm,function = <BCM2835_FSEL_ALT2>;
};
i2c_slave_gpio18: i2c_slave_gpio18 {
brcm,pins = <18 19 20 21>;
brcm,function = <BCM2835_FSEL_ALT3>;
};
jtag_gpio4: jtag_gpio4 {
brcm,pins = <4 5 6 12 13>;
brcm,function = <BCM2835_FSEL_ALT4>;
};
jtag_gpio22: jtag_gpio22 {
brcm,pins = <22 23 24 25 26 27>;
brcm,function = <BCM2835_FSEL_ALT4>;
};
pcm_gpio18: pcm_gpio18 {
brcm,pins = <18 19 20 21>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
pcm_gpio28: pcm_gpio28 {
brcm,pins = <28 29 30 31>;
brcm,function = <BCM2835_FSEL_ALT2>;
};
pwm0_gpio12: pwm0_gpio12 {
brcm,pins = <12>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
pwm0_gpio18: pwm0_gpio18 {
brcm,pins = <18>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
pwm0_gpio40: pwm0_gpio40 {
brcm,pins = <40>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
pwm1_gpio13: pwm1_gpio13 {
brcm,pins = <13>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
pwm1_gpio19: pwm1_gpio19 {
brcm,pins = <19>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
pwm1_gpio41: pwm1_gpio41 {
brcm,pins = <41>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
pwm1_gpio45: pwm1_gpio45 {
brcm,pins = <45>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
sdhost_gpio48: sdhost_gpio48 {
brcm,pins = <48 49 50 51 52 53>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
spi0_gpio7: spi0_gpio7 {
brcm,pins = <7 8 9 10 11>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
spi0_gpio35: spi0_gpio35 {
brcm,pins = <35 36 37 38 39>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
spi1_gpio16: spi1_gpio16 {
brcm,pins = <16 17 18 19 20 21>;
brcm,function = <BCM2835_FSEL_ALT4>;
};
spi2_gpio40: spi2_gpio40 {
brcm,pins = <40 41 42 43 44 45>;
brcm,function = <BCM2835_FSEL_ALT4>;
};
uart0_gpio14: uart0_gpio14 {
brcm,pins = <14 15>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
/* Separate from the uart0_gpio14 group
* because it conflicts with spi1_gpio16, and
* people often run uart0 on the two pins
* without flow control.
*/
uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
brcm,pins = <16 17>;
brcm,function = <BCM2835_FSEL_ALT3>;
};
uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
brcm,pins = <30 31>;
brcm,function = <BCM2835_FSEL_ALT3>;
};
uart0_gpio32: uart0_gpio32 {
brcm,pins = <32 33>;
brcm,function = <BCM2835_FSEL_ALT3>;
};
uart0_gpio36: uart0_gpio36 {
brcm,pins = <36 37>;
brcm,function = <BCM2835_FSEL_ALT2>;
};
uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
brcm,pins = <38 39>;
brcm,function = <BCM2835_FSEL_ALT2>;
};
uart1_gpio14: uart1_gpio14 {
brcm,pins = <14 15>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
brcm,pins = <16 17>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
uart1_gpio32: uart1_gpio32 {
brcm,pins = <32 33>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
brcm,pins = <30 31>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
uart1_gpio40: uart1_gpio40 {
brcm,pins = <40 41>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
brcm,pins = <42 43>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
};
uart0: serial@7e201000 {
@@ -144,6 +379,16 @@
arm,primecell-periphid = <0x00241011>;
};
sdhost: mmc@7e202000 {
compatible = "brcm,bcm2835-sdhost";
reg = <0x7e202000 0x100>;
interrupts = <2 24>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
dmas = <&dma 13>;
dma-names = "rx-tx";
status = "disabled";
};
i2s: i2s@7e203000 {
compatible = "brcm,bcm2835-i2s";
reg = <0x7e203000 0x20>,
@@ -187,6 +432,33 @@
interrupts = <2 14>; /* pwa1 */
};
dsi0: dsi@7e209000 {
compatible = "brcm,bcm2835-dsi0";
reg = <0x7e209000 0x78>;
interrupts = <2 4>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
clocks = <&clocks BCM2835_PLLA_DSI0>,
<&clocks BCM2835_CLOCK_DSI0E>,
<&clocks BCM2835_CLOCK_DSI0P>;
clock-names = "phy", "escape", "pixel";
clock-output-names = "dsi0_byte",
"dsi0_ddr2",
"dsi0_ddr";
};
thermal: thermal@7e212000 {
compatible = "brcm,bcm2835-thermal";
reg = <0x7e212000 0x8>;
clocks = <&clocks BCM2835_CLOCK_TSENS>;
#thermal-sensor-cells = <0>;
status = "disabled";
};
aux: aux@0x7e215000 {
compatible = "brcm,bcm2835-aux";
#clock-cells = <1>;
@@ -246,6 +518,26 @@
interrupts = <2 1>;
};
dsi1: dsi@7e700000 {
compatible = "brcm,bcm2835-dsi1";
reg = <0x7e700000 0x8c>;
interrupts = <2 12>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
clocks = <&clocks BCM2835_PLLD_DSI1>,
<&clocks BCM2835_CLOCK_DSI1E>,
<&clocks BCM2835_CLOCK_DSI1P>;
clock-names = "phy", "escape", "pixel";
clock-output-names = "dsi1_byte",
"dsi1_ddr2",
"dsi1_ddr";
status = "disabled";
};
i2c1: i2c@7e804000 {
compatible = "brcm,bcm2835-i2c";
reg = <0x7e804000 0x1000>;
@@ -266,6 +558,14 @@
status = "disabled";
};
vec: vec@7e806000 {
compatible = "brcm,bcm2835-vec";
reg = <0x7e806000 0x1000>;
clocks = <&clocks BCM2835_CLOCK_VEC>;
interrupts = <2 27>;
status = "disabled";
};
pixelvalve@7e807000 {
compatible = "brcm,bcm2835-pixelvalve2";
reg = <0x7e807000 0x100>;
@@ -281,6 +581,8 @@
clocks = <&clocks BCM2835_PLLH_PIX>,
<&clocks BCM2835_CLOCK_HSM>;
clock-names = "pixel", "hdmi";
dmas = <&dma 17>;
dma-names = "audio-rx";
status = "disabled";
};
@@ -290,6 +592,10 @@
interrupts = <1 9>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk_usb>;
clock-names = "otg";
phys = <&usbphy>;
phy-names = "usb2-phy";
};
v3d: v3d@7ec00000 {
@@ -317,6 +623,17 @@
clock-frequency = <19200000>;
};
clk_usb: clock@4 {
compatible = "fixed-clock";
reg = <4>;
#clock-cells = <0>;
clock-output-names = "otg";
clock-frequency = <480000000>;
};
};
usbphy: phy {
compatible = "usb-nop-xceiv";
};
};

View File

@@ -0,0 +1,23 @@
/*
* da850-evm U-Boot Additions
*
* Copyright (C) 2017 Logic PD, Inc.
* Copyright (C) Adam Ford
*
* SPDX-License-Identifier: GPL-2.0+
*/
/ {
chosen {
stdout-path = &serial2;
};
aliases {
i2c0 = &i2c0;
spi0 = &spi1;
};
};
&flash {
compatible = "m25p64", "spi-flash";
};

304
arch/arm/dts/da850-evm.dts Normal file
View File

@@ -0,0 +1,304 @@
/*
* Device Tree for DA850 EVM board
*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation, version 2.
*/
/dts-v1/;
#include "da850.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "ti,da850-evm", "ti,da850";
model = "DA850/AM1808/OMAP-L138 EVM";
soc@1c00000 {
pmx_core: pinmux@14120 {
status = "okay";
mcasp0_pins: pinmux_mcasp0_pins {
pinctrl-single,bits = <
/*
* AHCLKX, ACLKX, AFSX, AHCLKR, ACLKR,
* AFSR, AMUTE
*/
0x00 0x11111111 0xffffffff
/* AXR11, AXR12 */
0x04 0x00011000 0x000ff000
>;
};
nand_pins: nand_pins {
pinctrl-single,bits = <
/* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[4], EMA_CS[3] */
0x1c 0x10110110 0xf0ff0ff0
/*
* EMA_D[0], EMA_D[1], EMA_D[2],
* EMA_D[3], EMA_D[4], EMA_D[5],
* EMA_D[6], EMA_D[7]
*/
0x24 0x11111111 0xffffffff
/* EMA_A[1], EMA_A[2] */
0x30 0x01100000 0x0ff00000
>;
};
};
serial0: serial@42000 {
status = "okay";
};
serial1: serial@10c000 {
status = "okay";
};
serial2: serial@10d000 {
status = "okay";
};
rtc0: rtc@23000 {
status = "okay";
};
i2c0: i2c@22000 {
status = "okay";
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
tps: tps@48 {
reg = <0x48>;
};
tlv320aic3106: tlv320aic3106@18 {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic3106";
reg = <0x18>;
status = "okay";
/* Regulators */
IOVDD-supply = <&vdcdc2_reg>;
/* Derived from VBAT: Baseboard 3.3V / 1.8V */
AVDD-supply = <&vbat>;
DRVDD-supply = <&vbat>;
DVDD-supply = <&vbat>;
};
tca6416: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
};
wdt: wdt@21000 {
status = "okay";
};
mmc0: mmc@40000 {
max-frequency = <50000000>;
bus-width = <4>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
};
spi1: spi@30e000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins &spi1_cs0_pin>;
flash: m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p64";
spi-max-frequency = <30000000>;
m25p,fast-read;
reg = <0>;
partition@0 {
label = "U-Boot-SPL";
reg = <0x00000000 0x00010000>;
read-only;
};
partition@1 {
label = "U-Boot";
reg = <0x00010000 0x00080000>;
read-only;
};
partition@2 {
label = "U-Boot-Env";
reg = <0x00090000 0x00010000>;
read-only;
};
partition@3 {
label = "Kernel";
reg = <0x000a0000 0x00280000>;
};
partition@4 {
label = "Filesystem";
reg = <0x00320000 0x00400000>;
};
partition@5 {
label = "MAC-Address";
reg = <0x007f0000 0x00010000>;
read-only;
};
};
};
mdio: mdio@224000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
bus_freq = <2200000>;
};
eth0: ethernet@220000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mii_pins>;
};
gpio: gpio@226000 {
status = "okay";
};
};
vbat: fixedregulator0 {
compatible = "regulator-fixed";
regulator-name = "vbat";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "DA850/OMAP-L138 EVM";
simple-audio-card,widgets =
"Line", "Line In",
"Line", "Line Out";
simple-audio-card,routing =
"LINE1L", "Line In",
"LINE1R", "Line In",
"Line Out", "LLOUT",
"Line Out", "RLOUT";
simple-audio-card,format = "dsp_b";
simple-audio-card,bitclock-master = <&link0_codec>;
simple-audio-card,frame-master = <&link0_codec>;
simple-audio-card,bitclock-inversion;
simple-audio-card,cpu {
sound-dai = <&mcasp0>;
system-clock-frequency = <24576000>;
};
link0_codec: simple-audio-card,codec {
sound-dai = <&tlv320aic3106>;
system-clock-frequency = <24576000>;
};
};
};
/include/ "tps6507x.dtsi"
&tps {
vdcdc1_2-supply = <&vbat>;
vdcdc3-supply = <&vbat>;
vldo1_2-supply = <&vbat>;
regulators {
vdcdc1_reg: regulator@0 {
regulator-name = "VDCDC1_3.3V";
regulator-min-microvolt = <3150000>;
regulator-max-microvolt = <3450000>;
regulator-always-on;
regulator-boot-on;
};
vdcdc2_reg: regulator@1 {
regulator-name = "VDCDC2_3.3V";
regulator-min-microvolt = <1710000>;
regulator-max-microvolt = <3450000>;
regulator-always-on;
regulator-boot-on;
ti,defdcdc_default = <1>;
};
vdcdc3_reg: regulator@2 {
regulator-name = "VDCDC3_1.2V";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
ti,defdcdc_default = <1>;
};
ldo1_reg: regulator@3 {
regulator-name = "LDO1_1.8V";
regulator-min-microvolt = <1710000>;
regulator-max-microvolt = <1890000>;
regulator-always-on;
regulator-boot-on;
};
ldo2_reg: regulator@4 {
regulator-name = "LDO2_1.2V";
regulator-min-microvolt = <1140000>;
regulator-max-microvolt = <1320000>;
regulator-always-on;
regulator-boot-on;
};
};
};
&mcasp0 {
#sound-dai-cells = <0>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcasp0_pins>;
op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
/* 4 serializer */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
0 0 0 0
0 0 0 0
0 0 0 1
2 0 0 0
>;
tx-num-evt = <32>;
rx-num-evt = <32>;
};
&edma0 {
ti,edma-reserved-slot-ranges = <32 50>;
};
&edma1 {
ti,edma-reserved-slot-ranges = <32 90>;
};
&aemif {
pinctrl-names = "default";
pinctrl-0 = <&nand_pins>;
status = "ok";
cs3 {
#address-cells = <2>;
#size-cells = <1>;
clock-ranges;
ranges;
ti,cs-chipselect = <3>;
nand@2000000,0 {
compatible = "ti,davinci-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0 0x02000000 0x02000000
1 0x00000000 0x00008000>;
ti,davinci-chipselect = <1>;
ti,davinci-mask-ale = <0>;
ti,davinci-mask-cle = <0>;
ti,davinci-mask-chipsel = <0>;
ti,davinci-ecc-mode = "hw";
ti,davinci-ecc-bits = <4>;
ti,davinci-nand-use-bbt;
};
};
};
&vpif {
pinctrl-names = "default";
pinctrl-0 = <&vpif_capture_pins>, <&vpif_display_pins>;
status = "okay";
};

581
arch/arm/dts/da850.dtsi Normal file
View File

@@ -0,0 +1,581 @@
/*
* Copyright 2012 DENX Software Engineering GmbH
* Heiko Schocher <hs@denx.de>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
/ {
arm {
#address-cells = <1>;
#size-cells = <1>;
ranges;
intc: interrupt-controller@fffee000 {
compatible = "ti,cp-intc";
interrupt-controller;
#interrupt-cells = <1>;
ti,intc-size = <101>;
reg = <0xfffee000 0x2000>;
};
};
aliases {
spi0 = &spi0;
};
soc@1c00000 {
compatible = "simple-bus";
model = "da850";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x01c00000 0x400000>;
interrupt-parent = <&intc>;
pmx_core: pinmux@14120 {
compatible = "pinctrl-single";
reg = <0x14120 0x50>;
#address-cells = <1>;
#size-cells = <0>;
#pinctrl-cells = <2>;
pinctrl-single,bit-per-mux;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xf>;
status = "disabled";
serial0_rtscts_pins: pinmux_serial0_rtscts_pins {
pinctrl-single,bits = <
/* UART0_RTS UART0_CTS */
0x0c 0x22000000 0xff000000
>;
};
serial0_rxtx_pins: pinmux_serial0_rxtx_pins {
pinctrl-single,bits = <
/* UART0_TXD UART0_RXD */
0x0c 0x00220000 0x00ff0000
>;
};
serial1_rtscts_pins: pinmux_serial1_rtscts_pins {
pinctrl-single,bits = <
/* UART1_CTS UART1_RTS */
0x00 0x00440000 0x00ff0000
>;
};
serial1_rxtx_pins: pinmux_serial1_rxtx_pins {
pinctrl-single,bits = <
/* UART1_TXD UART1_RXD */
0x10 0x22000000 0xff000000
>;
};
serial2_rtscts_pins: pinmux_serial2_rtscts_pins {
pinctrl-single,bits = <
/* UART2_CTS UART2_RTS */
0x00 0x44000000 0xff000000
>;
};
serial2_rxtx_pins: pinmux_serial2_rxtx_pins {
pinctrl-single,bits = <
/* UART2_TXD UART2_RXD */
0x10 0x00220000 0x00ff0000
>;
};
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,bits = <
/* I2C0_SDA,I2C0_SCL */
0x10 0x00002200 0x0000ff00
>;
};
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,bits = <
/* I2C1_SDA, I2C1_SCL */
0x10 0x00440000 0x00ff0000
>;
};
mmc0_pins: pinmux_mmc_pins {
pinctrl-single,bits = <
/* MMCSD0_DAT[3] MMCSD0_DAT[2]
* MMCSD0_DAT[1] MMCSD0_DAT[0]
* MMCSD0_CMD MMCSD0_CLK
*/
0x28 0x00222222 0x00ffffff
>;
};
ehrpwm0a_pins: pinmux_ehrpwm0a_pins {
pinctrl-single,bits = <
/* EPWM0A */
0xc 0x00000002 0x0000000f
>;
};
ehrpwm0b_pins: pinmux_ehrpwm0b_pins {
pinctrl-single,bits = <
/* EPWM0B */
0xc 0x00000020 0x000000f0
>;
};
ehrpwm1a_pins: pinmux_ehrpwm1a_pins {
pinctrl-single,bits = <
/* EPWM1A */
0x14 0x00000002 0x0000000f
>;
};
ehrpwm1b_pins: pinmux_ehrpwm1b_pins {
pinctrl-single,bits = <
/* EPWM1B */
0x14 0x00000020 0x000000f0
>;
};
ecap0_pins: pinmux_ecap0_pins {
pinctrl-single,bits = <
/* ECAP0_APWM0 */
0x8 0x20000000 0xf0000000
>;
};
ecap1_pins: pinmux_ecap1_pins {
pinctrl-single,bits = <
/* ECAP1_APWM1 */
0x4 0x40000000 0xf0000000
>;
};
ecap2_pins: pinmux_ecap2_pins {
pinctrl-single,bits = <
/* ECAP2_APWM2 */
0x4 0x00000004 0x0000000f
>;
};
spi0_pins: pinmux_spi0_pins {
pinctrl-single,bits = <
/* SIMO, SOMI, CLK */
0xc 0x00001101 0x0000ff0f
>;
};
spi0_cs0_pin: pinmux_spi0_cs0 {
pinctrl-single,bits = <
/* CS0 */
0x10 0x00000010 0x000000f0
>;
};
spi0_cs3_pin: pinmux_spi0_cs3_pin {
pinctrl-single,bits = <
/* CS3 */
0xc 0x01000000 0x0f000000
>;
};
spi1_pins: pinmux_spi1_pins {
pinctrl-single,bits = <
/* SIMO, SOMI, CLK */
0x14 0x00110100 0x00ff0f00
>;
};
spi1_cs0_pin: pinmux_spi1_cs0 {
pinctrl-single,bits = <
/* CS0 */
0x14 0x00000010 0x000000f0
>;
};
mdio_pins: pinmux_mdio_pins {
pinctrl-single,bits = <
/* MDIO_CLK, MDIO_D */
0x10 0x00000088 0x000000ff
>;
};
mii_pins: pinmux_mii_pins {
pinctrl-single,bits = <
/*
* MII_TXEN, MII_TXCLK, MII_COL
* MII_TXD_3, MII_TXD_2, MII_TXD_1
* MII_TXD_0
*/
0x8 0x88888880 0xfffffff0
/*
* MII_RXER, MII_CRS, MII_RXCLK
* MII_RXDV, MII_RXD_3, MII_RXD_2
* MII_RXD_1, MII_RXD_0
*/
0xc 0x88888888 0xffffffff
>;
};
lcd_pins: pinmux_lcd_pins {
pinctrl-single,bits = <
/*
* LCD_D[2], LCD_D[3], LCD_D[4], LCD_D[5],
* LCD_D[6], LCD_D[7]
*/
0x40 0x22222200 0xffffff00
/*
* LCD_D[10], LCD_D[11], LCD_D[12], LCD_D[13],
* LCD_D[14], LCD_D[15], LCD_D[0], LCD_D[1]
*/
0x44 0x22222222 0xffffffff
/* LCD_D[8], LCD_D[9] */
0x48 0x00000022 0x000000ff
/* LCD_PCLK */
0x48 0x02000000 0x0f000000
/* LCD_AC_ENB_CS, LCD_VSYNC, LCD_HSYNC */
0x4c 0x02000022 0x0f0000ff
>;
};
vpif_capture_pins: vpif_capture_pins {
pinctrl-single,bits = <
/* VP_DIN[2..7], VP_CLKIN1, VP_CLKIN0 */
0x38 0x11111111 0xffffffff
/* VP_DIN[10..15,0..1] */
0x3c 0x11111111 0xffffffff
/* VP_DIN[8..9] */
0x40 0x00000011 0x000000ff
>;
};
vpif_display_pins: vpif_display_pins {
pinctrl-single,bits = <
/* VP_DOUT[2..7] */
0x40 0x11111100 0xffffff00
/* VP_DOUT[10..15,0..1] */
0x44 0x11111111 0xffffffff
/* VP_DOUT[8..9] */
0x48 0x00000011 0x000000ff
/*
* VP_CLKOUT3, VP_CLKIN3,
* VP_CLKOUT2, VP_CLKIN2
*/
0x4c 0x00111100 0x00ffff00
>;
};
};
prictrl: priority-controller@14110 {
compatible = "ti,da850-mstpri";
reg = <0x14110 0x0c>;
status = "disabled";
};
cfgchip: chip-controller@1417c {
compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";
reg = <0x1417c 0x14>;
usb_phy: usb-phy {
compatible = "ti,da830-usb-phy";
#phy-cells = <1>;
status = "disabled";
};
};
edma0: edma@0 {
compatible = "ti,edma3-tpcc";
/* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */
reg = <0x0 0x8000>;
reg-names = "edma3_cc";
interrupts = <11 12>;
interrupt-names = "edma3_ccint", "edma3_ccerrint";
#dma-cells = <2>;
ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>;
};
edma0_tptc0: tptc@8000 {
compatible = "ti,edma3-tptc";
reg = <0x8000 0x400>;
interrupts = <13>;
interrupt-names = "edm3_tcerrint";
};
edma0_tptc1: tptc@8400 {
compatible = "ti,edma3-tptc";
reg = <0x8400 0x400>;
interrupts = <32>;
interrupt-names = "edm3_tcerrint";
};
edma1: edma@230000 {
compatible = "ti,edma3-tpcc";
/* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */
reg = <0x230000 0x8000>;
reg-names = "edma3_cc";
interrupts = <93 94>;
interrupt-names = "edma3_ccint", "edma3_ccerrint";
#dma-cells = <2>;
ti,tptcs = <&edma1_tptc0 7>;
};
edma1_tptc0: tptc@238000 {
compatible = "ti,edma3-tptc";
reg = <0x238000 0x400>;
interrupts = <95>;
interrupt-names = "edm3_tcerrint";
};
serial0: serial@42000 {
compatible = "ti,da830-uart", "ns16550a";
reg = <0x42000 0x100>;
reg-io-width = <4>;
reg-shift = <2>;
interrupts = <25>;
status = "disabled";
};
serial1: serial@10c000 {
compatible = "ti,da830-uart", "ns16550a";
reg = <0x10c000 0x100>;
reg-io-width = <4>;
reg-shift = <2>;
interrupts = <53>;
status = "disabled";
};
serial2: serial@10d000 {
compatible = "ti,da830-uart", "ns16550a";
reg = <0x10d000 0x100>;
reg-io-width = <4>;
reg-shift = <2>;
interrupts = <61>;
status = "disabled";
};
rtc0: rtc@23000 {
compatible = "ti,da830-rtc";
reg = <0x23000 0x1000>;
interrupts = <19
19>;
status = "disabled";
};
i2c0: i2c@22000 {
compatible = "ti,davinci-i2c";
reg = <0x22000 0x1000>;
interrupts = <15>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@228000 {
compatible = "ti,davinci-i2c";
reg = <0x228000 0x1000>;
interrupts = <51>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
wdt: wdt@21000 {
compatible = "ti,davinci-wdt";
reg = <0x21000 0x1000>;
status = "disabled";
};
mmc0: mmc@40000 {
compatible = "ti,da830-mmc";
reg = <0x40000 0x1000>;
cap-sd-highspeed;
cap-mmc-highspeed;
interrupts = <16>;
dmas = <&edma0 16 0>, <&edma0 17 0>;
dma-names = "rx", "tx";
status = "disabled";
};
vpif: video@217000 {
compatible = "ti,da850-vpif";
reg = <0x217000 0x1000>;
interrupts = <92>;
status = "disabled";
/* VPIF capture port */
port@0 {
#address-cells = <1>;
#size-cells = <0>;
};
/* VPIF display port */
port@1 {
#address-cells = <1>;
#size-cells = <0>;
};
};
mmc1: mmc@21b000 {
compatible = "ti,da830-mmc";
reg = <0x21b000 0x1000>;
cap-sd-highspeed;
cap-mmc-highspeed;
interrupts = <72>;
dmas = <&edma1 28 0>, <&edma1 29 0>;
dma-names = "rx", "tx";
status = "disabled";
};
ehrpwm0: pwm@300000 {
compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x300000 0x2000>;
status = "disabled";
};
ehrpwm1: pwm@302000 {
compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x302000 0x2000>;
status = "disabled";
};
ecap0: ecap@306000 {
compatible = "ti,da850-ecap", "ti,am3352-ecap",
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x306000 0x80>;
status = "disabled";
};
ecap1: ecap@307000 {
compatible = "ti,da850-ecap", "ti,am3352-ecap",
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x307000 0x80>;
status = "disabled";
};
ecap2: ecap@308000 {
compatible = "ti,da850-ecap", "ti,am3352-ecap",
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x308000 0x80>;
status = "disabled";
};
spi0: spi@41000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "ti,da830-spi";
reg = <0x41000 0x1000>;
num-cs = <6>;
ti,davinci-spi-intr-line = <1>;
interrupts = <20>;
dmas = <&edma0 14 0>, <&edma0 15 0>;
dma-names = "rx", "tx";
status = "disabled";
};
spi1: spi@30e000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "ti,da830-spi";
reg = <0x30e000 0x1000>;
num-cs = <4>;
ti,davinci-spi-intr-line = <1>;
interrupts = <56>;
dmas = <&edma0 18 0>, <&edma0 19 0>;
dma-names = "rx", "tx";
status = "disabled";
};
usb0: usb@200000 {
compatible = "ti,da830-musb";
reg = <0x200000 0x1000>;
ranges;
interrupts = <58>;
interrupt-names = "mc";
dr_mode = "otg";
phys = <&usb_phy 0>;
phy-names = "usb-phy";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
dmas = <&cppi41dma 0 0 &cppi41dma 1 0
&cppi41dma 2 0 &cppi41dma 3 0
&cppi41dma 0 1 &cppi41dma 1 1
&cppi41dma 2 1 &cppi41dma 3 1>;
dma-names =
"rx1", "rx2", "rx3", "rx4",
"tx1", "tx2", "tx3", "tx4";
cppi41dma: dma-controller@201000 {
compatible = "ti,da830-cppi41";
reg = <0x201000 0x1000
0x202000 0x1000
0x204000 0x4000>;
reg-names = "controller",
"scheduler", "queuemgr";
interrupts = <58>;
#dma-cells = <2>;
#dma-channels = <4>;
status = "okay";
};
};
sata: sata@218000 {
compatible = "ti,da850-ahci";
reg = <0x218000 0x2000>, <0x22c018 0x4>;
interrupts = <67>;
status = "disabled";
};
mdio: mdio@224000 {
compatible = "ti,davinci_mdio";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x224000 0x1000>;
status = "disabled";
};
eth0: ethernet@220000 {
compatible = "ti,davinci-dm6467-emac";
reg = <0x220000 0x4000>;
ti,davinci-ctrl-reg-offset = <0x3000>;
ti,davinci-ctrl-mod-reg-offset = <0x2000>;
ti,davinci-ctrl-ram-offset = <0>;
ti,davinci-ctrl-ram-size = <0x2000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <33
34
35
36
>;
status = "disabled";
};
usb1: usb@225000 {
compatible = "ti,da830-ohci";
reg = <0x225000 0x1000>;
interrupts = <59>;
phys = <&usb_phy 1>;
phy-names = "usb-phy";
status = "disabled";
};
gpio: gpio@226000 {
compatible = "ti,dm6441-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x226000 0x1000>;
interrupts = <42 IRQ_TYPE_EDGE_BOTH
43 IRQ_TYPE_EDGE_BOTH 44 IRQ_TYPE_EDGE_BOTH
45 IRQ_TYPE_EDGE_BOTH 46 IRQ_TYPE_EDGE_BOTH
47 IRQ_TYPE_EDGE_BOTH 48 IRQ_TYPE_EDGE_BOTH
49 IRQ_TYPE_EDGE_BOTH 50 IRQ_TYPE_EDGE_BOTH>;
ti,ngpio = <144>;
ti,davinci-gpio-unbanked = <0>;
status = "disabled";
interrupt-controller;
#interrupt-cells = <2>;
};
pinconf: pin-controller@22c00c {
compatible = "ti,da850-pupd";
reg = <0x22c00c 0x8>;
status = "disabled";
};
mcasp0: mcasp@100000 {
compatible = "ti,da830-mcasp-audio";
reg = <0x100000 0x2000>,
<0x102000 0x400000>;
reg-names = "mpu", "dat";
interrupts = <54>;
interrupt-names = "common";
status = "disabled";
dmas = <&edma0 1 1>,
<&edma0 0 1>;
dma-names = "tx", "rx";
};
lcdc: display@213000 {
compatible = "ti,da850-tilcdc";
reg = <0x213000 0x1000>;
interrupts = <52>;
max-pixelclock = <37500>;
status = "disabled";
};
};
aemif: aemif@68000000 {
compatible = "ti,da850-aemif";
#address-cells = <2>;
#size-cells = <1>;
reg = <0x68000000 0x00008000>;
ranges = <0 0 0x60000000 0x08000000
1 0 0x68000000 0x00008000>;
status = "disabled";
};
memctrl: memory-controller@b0000000 {
compatible = "ti,da850-ddr-controller";
reg = <0xb0000000 0xe8>;
status = "disabled";
};
};

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@@ -0,0 +1,258 @@
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clk/ti-dra7-atl.h>
#include <dt-bindings/input/input.h>
/ {
chosen {
stdout-path = &uart1;
};
extcon_usb1: extcon_usb1 {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
};
sound0: sound0 {
compatible = "simple-audio-card";
simple-audio-card,name = "DRA7xx-EVM";
simple-audio-card,widgets =
"Headphone", "Headphone Jack",
"Line", "Line Out",
"Microphone", "Mic Jack",
"Line", "Line In";
simple-audio-card,routing =
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT",
"Line Out", "LLOUT",
"Line Out", "RLOUT",
"MIC3L", "Mic Jack",
"MIC3R", "Mic Jack",
"Mic Jack", "Mic Bias",
"LINE1L", "Line In",
"LINE1R", "Line In";
simple-audio-card,format = "dsp_b";
simple-audio-card,bitclock-master = <&sound0_master>;
simple-audio-card,frame-master = <&sound0_master>;
simple-audio-card,bitclock-inversion;
sound0_master: simple-audio-card,cpu {
sound-dai = <&mcasp3>;
system-clock-frequency = <5644800>;
};
simple-audio-card,codec {
sound-dai = <&tlv320aic3106>;
clocks = <&atl_clkin2_ck>;
};
};
leds {
compatible = "gpio-leds";
led0 {
label = "dra7:usr1";
gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led1 {
label = "dra7:usr2";
gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led2 {
label = "dra7:usr3";
gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led3 {
label = "dra7:usr4";
gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
USER1 {
label = "btnUser1";
linux,code = <BTN_0>;
gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
};
USER2 {
label = "btnUser2";
linux,code = <BTN_1>;
gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
};
};
};
&i2c3 {
status = "okay";
clock-frequency = <400000>;
};
&mcspi1 {
status = "okay";
};
&mcspi2 {
status = "okay";
};
&uart1 {
status = "okay";
interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<&dra7_pmx_core 0x3e0>;
};
&uart2 {
status = "okay";
};
&uart3 {
status = "okay";
};
&qspi {
status = "okay";
spi-max-frequency = <76800000>;
m25p80@0 {
compatible = "s25fl256s1";
spi-max-frequency = <76800000>;
reg = <0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
/* MTD partition table.
* The ROM checks the first four physical blocks
* for a valid file to boot and the flash here is
* 64KiB block size.
*/
partition@0 {
label = "QSPI.SPL";
reg = <0x00000000 0x000010000>;
};
partition@1 {
label = "QSPI.SPL.backup1";
reg = <0x00010000 0x00010000>;
};
partition@2 {
label = "QSPI.SPL.backup2";
reg = <0x00020000 0x00010000>;
};
partition@3 {
label = "QSPI.SPL.backup3";
reg = <0x00030000 0x00010000>;
};
partition@4 {
label = "QSPI.u-boot";
reg = <0x00040000 0x00100000>;
};
partition@5 {
label = "QSPI.u-boot-spl-os";
reg = <0x00140000 0x00080000>;
};
partition@6 {
label = "QSPI.u-boot-env";
reg = <0x001c0000 0x00010000>;
};
partition@7 {
label = "QSPI.u-boot-env.backup1";
reg = <0x001d0000 0x0010000>;
};
partition@8 {
label = "QSPI.kernel";
reg = <0x001e0000 0x0800000>;
};
partition@9 {
label = "QSPI.file-system";
reg = <0x009e0000 0x01620000>;
};
};
};
&omap_dwc3_1 {
extcon = <&extcon_usb1>;
};
&usb1 {
dr_mode = "otg";
extcon = <&extcon_usb1>;
};
&usb2 {
dr_mode = "host";
};
&atl {
assigned-clocks = <&abe_dpll_sys_clk_mux>,
<&atl_gfclk_mux>,
<&dpll_abe_ck>,
<&dpll_abe_m2x2_ck>,
<&atl_clkin2_ck>;
assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
status = "okay";
atl2 {
bws = <DRA7_ATL_WS_MCASP2_FSX>;
aws = <DRA7_ATL_WS_MCASP3_FSX>;
};
};
&mcasp3 {
#sound-dai-cells = <0>;
assigned-clocks = <&mcasp3_ahclkx_mux>;
assigned-clock-parents = <&atl_clkin2_ck>;
status = "okay";
op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
/* 4 serializer */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1 2 0 0
>;
tx-num-evt = <32>;
rx-num-evt = <32>;
};
&mailbox5 {
status = "okay";
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
status = "okay";
};
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
status = "okay";
};
};
&mailbox6 {
status = "okay";
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
status = "okay";
};
mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
status = "okay";
};
};

View File

@@ -0,0 +1,15 @@
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "omap5-u-boot.dtsi"
&pcf_gpio_21{
u-boot,i2c-offset-len = <0>;
};
&pcf_hdmi{
u-boot,i2c-offset-len = <0>;
};

View File

@@ -8,24 +8,26 @@
/dts-v1/;
#include "dra74x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clk/ti-dra7-atl.h>
#include <dt-bindings/input/input.h>
#include "dra7-evm-common.dtsi"
#include "dra74x-mmc-iodelay.dtsi"
/ {
model = "TI DRA742";
compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
chosen {
stdout-path = &uart1;
tick-timer = &timer2;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */
};
evm_1v8_sw: fixedregulator-evm_1v8 {
compatible = "regulator-fixed";
regulator-name = "evm_1v8";
vin-supply = <&smps9_reg>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
evm_3v3_sd: fixedregulator-sd {
compatible = "regulator-fixed";
regulator-name = "evm_3v3_sd";
@@ -52,11 +54,6 @@
regulator-max-microvolt = <1800000>;
};
extcon_usb1: extcon_usb1 {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
};
extcon_usb2: extcon_usb2 {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
@@ -74,286 +71,9 @@
gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
};
sound0: sound0 {
compatible = "simple-audio-card";
simple-audio-card,name = "DRA7xx-EVM";
simple-audio-card,widgets =
"Headphone", "Headphone Jack",
"Line", "Line Out",
"Microphone", "Mic Jack",
"Line", "Line In";
simple-audio-card,routing =
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT",
"Line Out", "LLOUT",
"Line Out", "RLOUT",
"MIC3L", "Mic Jack",
"MIC3R", "Mic Jack",
"Mic Jack", "Mic Bias",
"LINE1L", "Line In",
"LINE1R", "Line In";
simple-audio-card,format = "dsp_b";
simple-audio-card,bitclock-master = <&sound0_master>;
simple-audio-card,frame-master = <&sound0_master>;
simple-audio-card,bitclock-inversion;
sound0_master: simple-audio-card,cpu {
sound-dai = <&mcasp3>;
system-clock-frequency = <5644800>;
};
simple-audio-card,codec {
sound-dai = <&tlv320aic3106>;
clocks = <&atl_clkin2_ck>;
};
};
leds {
compatible = "gpio-leds";
led0 {
label = "dra7:usr1";
gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led1 {
label = "dra7:usr2";
gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led2 {
label = "dra7:usr3";
gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led3 {
label = "dra7:usr4";
gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
USER1 {
label = "btnUser1";
linux,code = <BTN_0>;
gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
};
USER2 {
label = "btnUser2";
linux,code = <BTN_1>;
gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
};
};
};
&dra7_pmx_core {
pinctrl-names = "default";
pinctrl-0 = <&vtt_pin>;
vtt_pin: pinmux_vtt_pin {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x37b4, PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
>;
};
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda */
DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl */
>;
};
i2c2_pins: pinmux_i2c2_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
>;
};
i2c3_pins: pinmux_i2c3_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3688, PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
DRA7XX_CORE_IOPAD(0x368c, PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
>;
};
mcspi1_pins: pinmux_mcspi1_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x37a4, PIN_INPUT | MUX_MODE0) /* spi1_sclk */
DRA7XX_CORE_IOPAD(0x37a8, PIN_INPUT | MUX_MODE0) /* spi1_d1 */
DRA7XX_CORE_IOPAD(0x37ac, PIN_INPUT | MUX_MODE0) /* spi1_d0 */
DRA7XX_CORE_IOPAD(0x37b0, PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
DRA7XX_CORE_IOPAD(0x37bc, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
>;
};
mcspi2_pins: pinmux_mcspi2_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x37c0, PIN_INPUT | MUX_MODE0) /* spi2_sclk */
DRA7XX_CORE_IOPAD(0x37c4, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
DRA7XX_CORE_IOPAD(0x37c8, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
DRA7XX_CORE_IOPAD(0x37cc, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
>;
};
uart1_pins: pinmux_uart1_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x37e0, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
DRA7XX_CORE_IOPAD(0x37e4, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
>;
};
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT | MUX_MODE0) /* uart2_rxd */
DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT | MUX_MODE0) /* uart2_txd */
DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
>;
};
uart3_pins: pinmux_uart3_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
>;
};
usb1_pins: pinmux_usb1_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
>;
};
usb2_pins: pinmux_usb2_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
>;
};
nand_flash_x16: nand_flash_x16 {
/* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
* So NAND flash requires following switch settings:
* SW5.1 (NAND_BOOTn) = ON (LOW)
* SW5.9 (GPMC_WPN) = OFF (HIGH)
*/
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
>;
};
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
/* Slave 2 */
DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 */
DRA7XX_CORE_IOPAD(0x3650, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3654, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3658, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x365c, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3660, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3664, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3668, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x366c, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3670, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3674, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3678, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x367c, MUX_MODE15)
/* Slave 2 */
DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15)
>;
};
dcan1_pins_default: dcan1_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
@@ -368,41 +88,43 @@
>;
};
atl_pins: pinmux_atl_pins {
mmc1_pins_default: mmc1_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */
DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */
DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mcasp3_pins: pinmux_mcasp3_pins {
mmc2_pins_default: mmc2_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */
DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */
DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */
DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */
>;
};
mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3724, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3728, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x372c, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3730, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
};
&i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
tps659038: tps659038@58 {
compatible = "ti,tps659038";
reg = <0x58>;
ti,palmas-override-powerhold;
ti,system-power-controller;
tps659038_pmic {
compatible = "ti,tps659038-pmic";
@@ -566,7 +288,6 @@
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
u-boot,i2c-offset-len = <0>;
};
tlv320aic3106: tlv320aic3106@19 {
@@ -587,8 +308,6 @@
&i2c2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
clock-frequency = <400000>;
pcf_hdmi: gpio@26 {
@@ -606,156 +325,60 @@
};
};
&i2c3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
clock-frequency = <400000>;
};
&mcspi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcspi1_pins>;
};
&mcspi2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcspi2_pins>;
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<&dra7_pmx_core 0x3e0>;
};
&uart2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
};
&uart3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
};
&mmc1 {
status = "okay";
vmmc-supply = <&evm_3v3_sd>;
vmmc_aux-supply = <&ldo1_reg>;
vqmmc-supply = <&ldo1_reg>;
bus-width = <4>;
/*
* SDCD signal is not being used here - using the fact that GPIO mode
* is always hardwired.
*/
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104";
pinctrl-0 = <&mmc1_pins_default>;
pinctrl-1 = <&mmc1_pins_hs>;
pinctrl-2 = <&mmc1_pins_sdr12>;
pinctrl-3 = <&mmc1_pins_sdr25>;
pinctrl-4 = <&mmc1_pins_sdr50>;
pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>;
pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>;
pinctrl-7 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;
pinctrl-8 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
};
&mmc2 {
status = "okay";
vmmc-supply = <&evm_3v3_sw>;
vmmc-supply = <&evm_1v8_sw>;
bus-width = <8>;
pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v";
pinctrl-0 = <&mmc2_pins_default>;
pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr_1_8v_rev11 &mmc2_iodelay_ddr_1_8v_rev11_conf>;
pinctrl-3 = <&mmc2_pins_ddr_rev20>;
pinctrl-4 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev11_conf>;
pinctrl-5 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
};
&cpu0 {
cpu0-supply = <&smps123_reg>;
};
&qspi {
status = "okay";
spi-max-frequency = <76800000>;
m25p80@0 {
compatible = "s25fl256s1", "spi-flash";
spi-max-frequency = <76800000>;
reg = <0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
/* MTD partition table.
* The ROM checks the first four physical blocks
* for a valid file to boot and the flash here is
* 64KiB block size.
*/
partition@0 {
label = "QSPI.SPL";
reg = <0x00000000 0x000010000>;
};
partition@1 {
label = "QSPI.SPL.backup1";
reg = <0x00010000 0x00010000>;
};
partition@2 {
label = "QSPI.SPL.backup2";
reg = <0x00020000 0x00010000>;
};
partition@3 {
label = "QSPI.SPL.backup3";
reg = <0x00030000 0x00010000>;
};
partition@4 {
label = "QSPI.u-boot";
reg = <0x00040000 0x00100000>;
};
partition@5 {
label = "QSPI.u-boot-spl-os";
reg = <0x00140000 0x00080000>;
};
partition@6 {
label = "QSPI.u-boot-env";
reg = <0x001c0000 0x00010000>;
};
partition@7 {
label = "QSPI.u-boot-env.backup1";
reg = <0x001d0000 0x0010000>;
};
partition@8 {
label = "QSPI.kernel";
reg = <0x001e0000 0x0800000>;
};
partition@9 {
label = "QSPI.file-system";
reg = <0x009e0000 0x01620000>;
};
};
};
&omap_dwc3_1 {
extcon = <&extcon_usb1>;
};
&omap_dwc3_2 {
extcon = <&extcon_usb2>;
};
&usb1 {
dr_mode = "peripheral";
pinctrl-names = "default";
pinctrl-0 = <&usb1_pins>;
};
&usb2 {
dr_mode = "host";
pinctrl-names = "default";
pinctrl-0 = <&usb2_pins>;
};
&elm {
status = "okay";
};
&gpmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nand_flash_x16>;
/*
* For the existing IOdelay configuration via U-Boot we don't
* support NAND on dra7-evm. Keep it disabled. Enabling it
* requires a different configuration by U-Boot.
*/
status = "disabled";
ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
nand@0,0 {
compatible = "ti,omap2-nand";
@@ -764,6 +387,7 @@
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
ti,nand-xfer-type = "prefetch-dma";
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <16>;
@@ -851,9 +475,6 @@
&mac {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
dual_emac;
};
@@ -869,12 +490,6 @@
dual_emac_res_vlan = <2>;
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
};
&dcan1 {
status = "ok";
pinctrl-names = "default", "sleep", "active";
@@ -883,63 +498,6 @@
pinctrl-2 = <&dcan1_pins_default>;
};
&atl {
pinctrl-names = "default";
pinctrl-0 = <&atl_pins>;
assigned-clocks = <&abe_dpll_sys_clk_mux>,
<&atl_gfclk_mux>,
<&dpll_abe_ck>,
<&dpll_abe_m2x2_ck>,
<&atl_clkin2_ck>;
assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
&pcie1_rc {
status = "okay";
atl2 {
bws = <DRA7_ATL_WS_MCASP2_FSX>;
aws = <DRA7_ATL_WS_MCASP3_FSX>;
};
};
&mcasp3 {
#sound-dai-cells = <0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mcasp3_pins>;
pinctrl-1 = <&mcasp3_sleep_pins>;
assigned-clocks = <&mcasp3_ahclkx_mux>;
assigned-clock-parents = <&atl_clkin2_ck>;
status = "okay";
op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
/* 4 serializer */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1 2 0 0
>;
tx-num-evt = <32>;
rx-num-evt = <32>;
};
&mailbox5 {
status = "okay";
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
status = "okay";
};
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
status = "okay";
};
};
&mailbox6 {
status = "okay";
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
status = "okay";
};
mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
status = "okay";
};
};

View File

@@ -18,6 +18,7 @@
compatible = "ti,dra7xx";
interrupt-parent = <&crossbar_mpu>;
chosen { };
aliases {
i2c0 = &i2c1;
@@ -56,7 +57,7 @@
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x0 0x48211000 0x0 0x1000>,
<0x0 0x48212000 0x0 0x1000>,
<0x0 0x48212000 0x0 0x2000>,
<0x0 0x48214000 0x0 0x2000>,
<0x0 0x48216000 0x0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
@@ -80,11 +81,7 @@
compatible = "arm,cortex-a15";
reg = <0>;
operating-points = <
/* kHz uV */
1000000 1060000
1176000 1160000
>;
operating-points-v2 = <&cpu0_opp_table>;
clocks = <&dpll_mpu_ck>;
clock-names = "cpu";
@@ -98,6 +95,24 @@
};
};
cpu0_opp_table: opp-table {
compatible = "operating-points-v2-ti-cpu";
syscon = <&scm_wkup>;
opp_nom-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <1060000 850000 1150000>;
opp-supported-hw = <0xFF 0x01>;
opp-suspend;
};
opp_od-1176000000 {
opp-hz = /bits/ 64 <1176000000>;
opp-microvolt = <1160000 885000 1160000>;
opp-supported-hw = <0xFF 0x02>;
};
};
/*
* The soc node represents the soc top level view. It is used for IPs
* that are not memory mapped in the MPU view or for the MPU itself.
@@ -171,6 +186,7 @@
reg = <0x1400 0x0468>;
#address-cells = <1>;
#size-cells = <0>;
#pinctrl-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <32>;
@@ -180,6 +196,7 @@
scm_conf1: scm_conf@1c04 {
compatible = "syscon";
reg = <0x1c04 0x0020>;
#syscon-cells = <2>;
};
scm_conf_pcie: scm_conf@1c24 {
@@ -271,7 +288,11 @@
#address-cells = <1>;
ranges = <0x51000000 0x51000000 0x3000
0x0 0x20000000 0x10000000>;
pcie1: pcie@51000000 {
/**
* To enable PCI endpoint mode, disable the pcie1_rc
* node and enable pcie1_ep mode.
*/
pcie1_rc: pcie@51000000 {
compatible = "ti,dra7-pcie";
reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
reg-names = "rc_dbics", "ti_conf", "config";
@@ -281,6 +302,7 @@
device_type = "pci";
ranges = <0x81000000 0 0 0x03000 0 0x00010000
0x82000000 0 0x20013000 0x13000 0 0xffed000>;
bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
num-lanes = <1>;
linux,pci-domain = <0>;
@@ -292,12 +314,28 @@
<0 0 0 2 &pcie1_intc 2>,
<0 0 0 3 &pcie1_intc 3>,
<0 0 0 4 &pcie1_intc 4>;
status = "disabled";
pcie1_intc: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
pcie1_ep: pcie_ep@51000000 {
compatible = "ti,dra7-pcie-ep";
reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
interrupts = <0 232 0x4>;
num-lanes = <1>;
num-ib-windows = <4>;
num-ob-windows = <16>;
ti,hwmods = "pcie1";
phys = <&pcie1_phy>;
phy-names = "pcie-phy0";
ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
status = "disabled";
};
};
axi@1 {
@@ -317,6 +355,7 @@
device_type = "pci";
ranges = <0x81000000 0 0 0x03000 0 0x00010000
0x82000000 0 0x30013000 0x13000 0 0xffed000>;
bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
num-lanes = <1>;
linux,pci-domain = <1>;
@@ -400,6 +439,14 @@
reg = <0x40d00000 0x100>;
};
dra7_iodelay_core: padconf@4844a000 {
compatible = "ti,dra7-iodelay";
reg = <0x4844a000 0x0d1c>;
#address-cells = <1>;
#size-cells = <0>;
#pinctrl-cells = <2>;
};
sdma: dma-controller@4a056000 {
compatible = "ti,omap4430-sdma";
reg = <0x4a056000 0x1000>;
@@ -542,7 +589,6 @@
uart1: serial@4806a000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x4806a000 0x100>;
reg-shift = <2>;
interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart1";
clock-frequency = <48000000>;
@@ -554,7 +600,6 @@
uart2: serial@4806c000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x4806c000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart2";
clock-frequency = <48000000>;
@@ -566,7 +611,6 @@
uart3: serial@48020000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48020000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart3";
clock-frequency = <48000000>;
@@ -578,7 +622,6 @@
uart4: serial@4806e000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x4806e000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart4";
clock-frequency = <48000000>;
@@ -590,7 +633,6 @@
uart5: serial@48066000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48066000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart5";
clock-frequency = <48000000>;
@@ -602,7 +644,6 @@
uart6: serial@48068000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48068000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart6";
clock-frequency = <48000000>;
@@ -614,7 +655,6 @@
uart7: serial@48420000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48420000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart7";
clock-frequency = <48000000>;
@@ -624,7 +664,6 @@
uart8: serial@48422000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48422000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart8";
clock-frequency = <48000000>;
@@ -634,7 +673,6 @@
uart9: serial@48424000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48424000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart9";
clock-frequency = <48000000>;
@@ -644,7 +682,6 @@
uart10: serial@4ae2b000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x4ae2b000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart10";
clock-frequency = <48000000>;
@@ -1029,6 +1066,7 @@
dma-names = "tx", "rx";
status = "disabled";
pbias-supply = <&pbias_mmc_reg>;
max-frequency = <192000000>;
};
mmc2: mmc@480b4000 {
@@ -1040,6 +1078,7 @@
dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
dma-names = "tx", "rx";
status = "disabled";
max-frequency = <192000000>;
};
mmc3: mmc@480ad000 {
@@ -1051,6 +1090,8 @@
dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
dma-names = "tx", "rx";
status = "disabled";
/* Errata i887 limits max-frequency of MMC3 to 64 MHz */
max-frequency = <64000000>;
};
mmc4: mmc@480d1000 {
@@ -1062,6 +1103,7 @@
dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
dma-names = "tx", "rx";
status = "disabled";
max-frequency = <192000000>;
};
mmu0_dsp1: mmu@40d01000 {
@@ -1386,6 +1428,7 @@
phy-names = "sata-phy";
clocks = <&sata_ref_clk>;
ti,hwmods = "sata";
ports-implemented = <0x1>;
};
rtc: rtc@48838000 {
@@ -1716,13 +1759,11 @@
cpdma_channels = <8>;
ale_entries = <1024>;
bd_ram_size = <0x2000>;
no_bd_ram = <0>;
mac_control = <0x20>;
slaves = <2>;
active_slave = <0>;
cpts_clock_mult = <0x784CFE14>;
cpts_clock_shift = <29>;
syscon = <&scm_conf>;
reg = <0x48484000 0x1000
0x48485200 0x2E00>;
#address-cells = <1>;
@@ -1748,6 +1789,7 @@
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
ranges;
syscon = <&scm_conf>;
status = "disabled";
davinci_mdio: mdio@48485000 {
@@ -1990,6 +2032,27 @@
&cpu_thermal {
polling-delay = <500>; /* milliseconds */
coefficients = <0 2000>;
};
&gpu_thermal {
coefficients = <0 2000>;
};
&core_thermal {
coefficients = <0 2000>;
};
&dspeve_thermal {
coefficients = <0 2000>;
};
&iva_thermal {
coefficients = <0 2000>;
};
&cpu_crit {
temperature = <120000>; /* milli Celsius */
};
/include/ "dra7xx-clocks.dtsi"

View File

@@ -0,0 +1,23 @@
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "omap5-u-boot.dtsi"
&pcf_gpio_21{
u-boot,i2c-offset-len = <0>;
};
&pcf_hdmi{
u-boot,i2c-offset-len = <0>;
};
&cpsw_emac0 {
phy-handle = <&dp83867_0>;
};
&cpsw_emac1 {
phy-handle = <&dp83867_1>;
};

View File

@@ -7,6 +7,7 @@
*/
#include "dra72-evm-common.dtsi"
#include "dra72x-mmc-iodelay.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
/ {
@@ -32,6 +33,16 @@
3000000 0x1>;
};
evm_1v8_sw: fixedregulator-evm_1v8 {
compatible = "regulator-fixed";
regulator-name = "evm_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&lp8732_buck0_reg>;
regulator-always-on;
regulator-boot-on;
};
poweroff: gpio-poweroff {
compatible = "gpio-poweroff";
gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>;
@@ -138,6 +149,11 @@
};
};
&pcf_lcd {
interrupt-parent = <&gpio7>;
interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
};
&pcf_gpio_21 {
interrupt-parent = <&gpio7>;
interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
@@ -157,7 +173,24 @@
};
&mmc1 {
vmmc_aux-supply = <&vpo_sd_1v8_3v3>;
pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
pinctrl-0 = <&mmc1_pins_default>;
pinctrl-1 = <&mmc1_pins_hs>;
pinctrl-2 = <&mmc1_pins_sdr12>;
pinctrl-3 = <&mmc1_pins_sdr25>;
pinctrl-4 = <&mmc1_pins_sdr50>;
pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;
pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
vqmmc-supply = <&vpo_sd_1v8_3v3>;
};
&mmc2 {
pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
pinctrl-0 = <&mmc2_pins_default>;
pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
vmmc-supply = <&evm_1v8_sw>;
};
&mac {
@@ -168,13 +201,13 @@
};
&cpsw_emac0 {
phy-handle = <&dp83867_0>;
phy_id = <&davinci_mdio>, <2>;
phy-mode = "rgmii-id";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
phy-handle = <&dp83867_1>;
phy_id = <&davinci_mdio>, <3>;
phy-mode = "rgmii-id";
dual_emac_res_vlan = <2>;
};
@@ -185,7 +218,8 @@
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,impedance-control = <0x1f>;
ti,min-output-impedance;
ti,dp83867-rxctrl-strap-quirk;
};
dp83867_1: ethernet-phy@3 {
@@ -193,7 +227,8 @@
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,impedance-control = <0x1f>;
ti,min-output-impedance;
ti,dp83867-rxctrl-strap-quirk;
};
};

View File

@@ -20,7 +20,6 @@
chosen {
stdout-path = &uart1;
tick-timer = &timer2;
};
evm_12v0: fixedregulator-evm12v0 {
@@ -221,9 +220,17 @@
status = "okay";
clock-frequency = <400000>;
pcf_lcd: gpio@20 {
compatible = "nxp,pcf8575";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pcf_gpio_21: gpio@21 {
compatible = "ti,pcf8575", "nxp,pcf8575";
u-boot,i2c-offset-len = <0>;
reg = <0x21>;
lines-initial-states = <0x1408>;
gpio-controller;
@@ -254,7 +261,6 @@
pcf_hdmi: pcf8575@26 {
compatible = "ti,pcf8575", "nxp,pcf8575";
u-boot,i2c-offset-len = <0>;
reg = <0x26>;
gpio-controller;
#gpio-cells = <2>;
@@ -287,7 +293,12 @@
};
&gpmc {
status = "okay";
/*
* For the existing IOdelay configuration via U-Boot we don't
* support NAND on dra72-evm. Keep it disabled. Enabling it
* requires a different configuration by U-Boot.
*/
status = "disabled";
ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
nand@0,0 {
/* To use NAND, DIP switch SW5 must be set like so:
@@ -300,6 +311,7 @@
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
ti,nand-xfer-type = "prefetch-dma";
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <16>;
@@ -381,7 +393,8 @@
};
&usb1 {
dr_mode = "peripheral";
dr_mode = "otg";
extcon = <&extcon_usb1>;
};
&usb2 {
@@ -407,8 +420,6 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins_default>;
vmmc-supply = <&evm_3v3_sw>;
bus-width = <8>;
ti,non-removable;
max-frequency = <192000000>;
@@ -431,7 +442,7 @@
spi-max-frequency = <76800000>;
m25p80@0 {
compatible = "s25fl256s1", "spi-flash";
compatible = "s25fl256s1";
spi-max-frequency = <76800000>;
reg = <0>;
spi-tx-bus-width = <1>;
@@ -552,3 +563,7 @@
status = "okay";
};
};
&pcie1_rc {
status = "okay";
};

View File

@@ -0,0 +1,23 @@
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "omap5-u-boot.dtsi"
&pcf_gpio_21{
u-boot,i2c-offset-len = <0>;
};
&pcf_hdmi{
u-boot,i2c-offset-len = <0>;
};
&cpsw_emac0 {
phy-handle = <&dp83867_0>;
};
&cpsw_emac1 {
phy-handle = <&dp83867_1>;
};

View File

@@ -6,6 +6,7 @@
* published by the Free Software Foundation.
*/
#include "dra72-evm-common.dtsi"
#include "dra72x-mmc-iodelay.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
/ {
@@ -15,6 +16,16 @@
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
};
evm_1v8_sw: fixedregulator-evm_1v8 {
compatible = "regulator-fixed";
regulator-name = "evm_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&smps4_reg>;
regulator-always-on;
regulator-boot-on;
};
};
&i2c1 {
@@ -50,13 +61,13 @@
};
&cpsw_emac0 {
phy-handle = <&dp83867_0>;
phy_id = <&davinci_mdio>, <2>;
phy-mode = "rgmii-id";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
phy-handle = <&dp83867_1>;
phy_id = <&davinci_mdio>, <3>;
phy-mode = "rgmii-id";
dual_emac_res_vlan = <2>;
};
@@ -68,6 +79,9 @@
ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,min-output-impedance;
interrupt-parent = <&gpio6>;
interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
ti,dp83867-rxctrl-strap-quirk;
};
dp83867_1: ethernet-phy@3 {
@@ -76,5 +90,29 @@
ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,min-output-impedance;
interrupt-parent = <&gpio6>;
interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
ti,dp83867-rxctrl-strap-quirk;
};
};
&mmc1 {
pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
pinctrl-0 = <&mmc1_pins_default>;
pinctrl-1 = <&mmc1_pins_hs>;
pinctrl-2 = <&mmc1_pins_sdr12>;
pinctrl-3 = <&mmc1_pins_sdr25>;
pinctrl-4 = <&mmc1_pins_sdr50>;
pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;
pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
vqmmc-supply = <&ldo1_reg>;
};
&mmc2 {
pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
pinctrl-0 = <&mmc2_pins_default>;
pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
vmmc-supply = <&evm_1v8_sw>;
};

View File

@@ -132,3 +132,19 @@
ti,palmas-long-press-seconds = <6>;
};
};
&usb2_phy1 {
phy-supply = <&ldo4_reg>;
};
&usb2_phy2 {
phy-supply = <&ldo4_reg>;
};
&dss {
vdda_video-supply = <&ldo5_reg>;
};
&mmc1 {
vqmmc-supply = <&ldo1_reg>;
};

View File

@@ -6,6 +6,7 @@
* published by the Free Software Foundation.
*/
#include "dra72-evm-common.dtsi"
#include "dra72x-mmc-iodelay.dtsi"
/ {
model = "TI DRA722";
@@ -13,6 +14,16 @@
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */
};
evm_1v8_sw: fixedregulator-evm_1v8 {
compatible = "regulator-fixed";
regulator-name = "evm_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&smps4_reg>;
regulator-always-on;
regulator-boot-on;
};
};
&i2c1 {
@@ -43,3 +54,24 @@
phy_id = <&davinci_mdio>, <3>;
phy-mode = "rgmii";
};
&mmc1 {
pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
pinctrl-0 = <&mmc1_pins_default>;
pinctrl-1 = <&mmc1_pins_hs>;
pinctrl-2 = <&mmc1_pins_sdr12>;
pinctrl-3 = <&mmc1_pins_sdr25>;
pinctrl-4 = <&mmc1_pins_sdr50>;
pinctrl-5 = <&mmc1_pins_ddr50_rev10>;
pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev10_conf>;
vqmmc-supply = <&ldo1_reg>;
};
&mmc2 {
pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
pinctrl-0 = <&mmc2_pins_default>;
pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr_rev10>;
pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev10_conf>;
vmmc-supply = <&evm_1v8_sw>;
};

View File

@@ -0,0 +1,350 @@
/*
* MMC IOdelay values for TI's DRA72x, DRA71x and AM571x SoCs.
*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* Rules for modifying this file:
* a) Update of this file should typically correspond to a datamanual revision.
* Datamanual revision that was used should be updated in comment below.
* If there is no update to datamanual, do not update the values. If you
* need to use values different from that recommended by the datamanual
* for your design, then you should consider adding values to the device-
* -tree file for your board directly.
* b) We keep the mode names as close to the datamanual as possible. So
* if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,
* we follow that in code too.
* c) If the values change between multiple revisions of silicon, we add
* a revision tag to both the new and old entry. Use 'rev10' for PG 1.0,
* 'rev20' for PG 2.0 and so on.
* d) The node name and node label should be the exact same string. This is
* to curb naming creativity and achieve consistency.
* e) If in future, DRA71x and DRA72x values differ, then add 'dra71_' and
* 'dra72_' tag to entries. Both the new and old entries should gain a tag.
*
* Datamanual Revisions:
*
* AM571x Silicon Revision 2.0: SPRS957D, Revised January 2017
* AM571x Silicon Revision 1.0: SPRS919M, Revised November 2017
* DRA71x : SPRS960B, Revised February 2017
*/
&dra7_pmx_core {
mmc1_pins_default: mmc1_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc1_pins_sdr12: mmc1_pins_sdr12 {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc1_pins_hs: mmc1_pins_hs {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc1_pins_sdr25: mmc1_pins_sdr25 {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc1_pins_sdr50: mmc1_pins_sdr50 {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_clk.clk */
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_cmd.cmd */
DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat0.dat0 */
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat1.dat1 */
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat2.dat2 */
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc1_pins_ddr50_rev10: mmc1_pins_ddr50_rev10 {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_clk.mmc1_clk */
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */
DRA7XX_CORE_IOPAD(0x375C, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */
>;
};
mmc1_pins_ddr50_rev20: mmc1_pins_ddr50_rev20 {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */
DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc1_pins_sdr104: mmc1_pins_sdr104 {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */
DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc2_pins_default: mmc2_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
mmc2_pins_hs: mmc2_pins_hs {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
mmc2_pins_ddr_rev10: mmc2_pins_ddr_rev10 {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
>;
};
mmc2_pins_ddr_rev20: mmc2_pins_ddr_rev20 {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
mmc2_pins_hs200: mmc2_pins_hs200 {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
};
&dra7_iodelay_core {
/* Corresponds to MMC1_MANUAL1 in datamanual */
mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf {
pinctrl-pin-array = <
0x618 A_DELAY_PS(588) G_DELAY_PS(0) /* CFG_MMC1_CLK_IN */
0x624 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */
0x630 A_DELAY_PS(1375) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */
0x63C A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */
0x648 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */
0x654 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */
0x620 A_DELAY_PS(1230) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */
0x62C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
0x638 A_DELAY_PS(56) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
0x644 A_DELAY_PS(76) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
0x650 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
0x65C A_DELAY_PS(99) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
0x64C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
>;
};
/* Corresponds to MMC1_MANUAL2 in datamanual */
mmc1_iodelay_sdr104_rev10_conf: mmc1_iodelay_sdr104_rev10_conf {
pinctrl-pin-array = <
0x620 A_DELAY_PS(560) G_DELAY_PS(365) /* CFG_MMC1_CLK_OUT */
0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
0x638 A_DELAY_PS(29) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
0x650 A_DELAY_PS(47) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
0x65c A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
0x628 A_DELAY_PS(125) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
0x634 A_DELAY_PS(43) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
0x640 A_DELAY_PS(433) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
0x64c A_DELAY_PS(287) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
0x658 A_DELAY_PS(351) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
>;
};
/* Corresponds to MMC1_MANUAL2 in datamanual */
mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf {
pinctrl-pin-array = <
0x620 A_DELAY_PS(520) G_DELAY_PS(320) /* CFG_MMC1_CLK_OUT */
0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
0x638 A_DELAY_PS(40) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
0x644 A_DELAY_PS(83) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
0x650 A_DELAY_PS(98) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
0x65c A_DELAY_PS(106) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
0x628 A_DELAY_PS(51) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
0x640 A_DELAY_PS(363) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
0x64c A_DELAY_PS(199) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
0x658 A_DELAY_PS(273) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
>;
};
/* Corresponds to MMC2_MANUAL1 in datamanual */
mmc2_iodelay_ddr_conf: mmc2_iodelay_ddr_conf {
pinctrl-pin-array = <
0x18c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_IN */
0x1a4 A_DELAY_PS(119) G_DELAY_PS(0) /* CFG_GPMC_A20_IN */
0x1b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_IN */
0x1bc A_DELAY_PS(18) G_DELAY_PS(0) /* CFG_GPMC_A22_IN */
0x1c8 A_DELAY_PS(894) G_DELAY_PS(0) /* CFG_GPMC_A23_IN */
0x1d4 A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_GPMC_A24_IN */
0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */
0x1ec A_DELAY_PS(23) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */
0x1f8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_IN */
0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */
0x194 A_DELAY_PS(152) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */
0x1ac A_DELAY_PS(206) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
0x1b8 A_DELAY_PS(78) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
0x1c4 A_DELAY_PS(2) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
0x1d0 A_DELAY_PS(266) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */
0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
0x1f4 A_DELAY_PS(43) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
0x368 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
>;
};
/* Corresponds to MMC2_MANUAL3 in datamanual */
mmc2_iodelay_hs200_rev10_conf: mmc2_iodelay_hs200_rev10_conf {
pinctrl-pin-array = <
0x194 A_DELAY_PS(150) G_DELAY_PS(95) /* CFG_GPMC_A19_OUT */
0x1ac A_DELAY_PS(250) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
0x1b8 A_DELAY_PS(125) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
0x1c4 A_DELAY_PS(100) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
0x1d0 A_DELAY_PS(870) G_DELAY_PS(415) /* CFG_GPMC_A23_OUT */
0x1dc A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
0x1e8 A_DELAY_PS(200) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
0x1f4 A_DELAY_PS(200) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
0x368 A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
0x190 A_DELAY_PS(695) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
0x1a8 A_DELAY_PS(924) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
0x1b4 A_DELAY_PS(719) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
0x1c0 A_DELAY_PS(824) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
0x1d8 A_DELAY_PS(877) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
0x1e4 A_DELAY_PS(446) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
0x1f0 A_DELAY_PS(847) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
0x1fc A_DELAY_PS(586) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
0x364 A_DELAY_PS(1039) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
>;
};
/* Corresponds to MMC2_MANUAL3 in datamanual */
mmc2_iodelay_hs200_rev20_conf: mmc2_iodelay_hs200_rev20_conf {
pinctrl-pin-array = <
0x194 A_DELAY_PS(285) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */
0x1ac A_DELAY_PS(189) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
0x1b8 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_OUT */
0x1c4 A_DELAY_PS(0) G_DELAY_PS(70) /* CFG_GPMC_A22_OUT */
0x1d0 A_DELAY_PS(730) G_DELAY_PS(360) /* CFG_GPMC_A23_OUT */
0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
0x1f4 A_DELAY_PS(70) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
0x368 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_CS1_OUT */
0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
0x1a8 A_DELAY_PS(231) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
0x1b4 A_DELAY_PS(39) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
0x1c0 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
0x1d8 A_DELAY_PS(176) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
0x1f0 A_DELAY_PS(101) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
0x364 A_DELAY_PS(360) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
>;
};
};

View File

@@ -12,22 +12,6 @@
/ {
compatible = "ti,dra722", "ti,dra72", "ti,dra7";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
/* cooling options */
cooling-min-level = <0>;
cooling-max-level = <2>;
#cooling-cells = <2>; /* min followed by max */
};
};
pmu {
compatible = "arm,cortex-a15-pmu";
interrupt-parent = <&wakeupgen>;
@@ -45,3 +29,24 @@
<&dss_video1_clk>;
clock-names = "fck", "video1_clk";
};
&mailbox5 {
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
ti,mbox-tx = <6 2 2>;
ti,mbox-rx = <4 2 2>;
status = "disabled";
};
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
ti,mbox-tx = <5 2 2>;
ti,mbox-rx = <1 2 2>;
status = "disabled";
};
};
&mailbox6 {
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
ti,mbox-tx = <6 2 2>;
ti,mbox-rx = <4 2 2>;
status = "disabled";
};
};

View File

@@ -0,0 +1,647 @@
/*
* MMC IOdelay values for TI's DRA74x, DRA75x and AM572x SoCs.
*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* Rules for modifying this file:
* a) Update of this file should typically correspond to a datamanual revision.
* Datamanual revision that was used should be updated in comment below.
* If there is no update to datamanual, do not update the values. If you
* need to use values different from that recommended by the datamanual
* for your design, then you should consider adding values to the device-
* -tree file for your board directly.
* b) We keep the mode names as close to the datamanual as possible. So
* if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,
* we follow that in code too.
* c) If the values change between multiple revisions of silicon, we add
* a revision tag to both the new and old entry. Use 'rev11' for PG 1.1,
* 'rev20' for PG 2.0 and so on.
* d) The node name and node label should be the exact same string. This is
* to curb naming creativity and achieve consistency.
*
* Datamanual Revisions:
*
* AM572x Silicon Revision 2.0: SPRS953B, Revised November 2016
* AM572x Silicon Revision 1.1: SPRS915R, Revised November 2016
*
*/
&dra7_pmx_core {
mmc1_pins_default: mmc1_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc1_pins_sdr12: mmc1_pins_sdr12 {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc1_pins_hs: mmc1_pins_hs {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc1_pins_sdr25: mmc1_pins_sdr25 {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc1_pins_sdr50: mmc1_pins_sdr50 {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */
DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat0.dat0 */
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat1.dat1 */
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat2.dat2 */
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc1_pins_ddr50: mmc1_pins_ddr50 {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */
DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc1_pins_sdr104: mmc1_pins_sdr104 {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */
DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc2_pins_default: mmc2_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
mmc2_pins_hs: mmc2_pins_hs {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
mmc2_pins_ddr_3_3v_rev11: mmc2_pins_ddr_3_3v_rev11 {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
mmc2_pins_ddr_1_8v_rev11: mmc2_pins_ddr_1_8v_rev11 {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
mmc2_pins_ddr_rev20: mmc2_pins_ddr_rev20 {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
mmc2_pins_hs200: mmc2_pins_hs200 {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
mmc4_pins_default: mmc4_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
>;
};
mmc4_pins_hs: mmc4_pins_hs {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
>;
};
mmc3_pins_default: mmc3_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
>;
};
mmc3_pins_hs: mmc3_pins_hs {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
>;
};
mmc3_pins_sdr12: mmc3_pins_sdr12 {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
>;
};
mmc3_pins_sdr25: mmc3_pins_sdr25 {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
>;
};
mmc3_pins_sdr50: mmc3_pins_sdr50 {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
>;
};
mmc4_pins_sdr12: mmc4_pins_sdr12 {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
>;
};
mmc4_pins_sdr25: mmc4_pins_sdr25 {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
>;
};
};
&dra7_iodelay_core {
/* Corresponds to MMC1_DDR_MANUAL1 in datamanual */
mmc1_iodelay_ddr_rev11_conf: mmc1_iodelay_ddr_rev11_conf {
pinctrl-pin-array = <
0x618 A_DELAY_PS(572) G_DELAY_PS(540) /* CFG_MMC1_CLK_IN */
0x620 A_DELAY_PS(1525) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */
0x624 A_DELAY_PS(0) G_DELAY_PS(600) /* CFG_MMC1_CMD_IN */
0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
0x62c A_DELAY_PS(55) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
0x630 A_DELAY_PS(403) G_DELAY_PS(120) /* CFG_MMC1_DAT0_IN */
0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
0x63c A_DELAY_PS(23) G_DELAY_PS(60) /* CFG_MMC1_DAT1_IN */
0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
0x648 A_DELAY_PS(25) G_DELAY_PS(60) /* CFG_MMC1_DAT2_IN */
0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */
0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
>;
};
/* Corresponds to MMC1_DDR_MANUAL1 in datamanual */
mmc1_iodelay_ddr_rev20_conf: mmc1_iodelay_ddr50_rev20_conf {
pinctrl-pin-array = <
0x618 A_DELAY_PS(1076) G_DELAY_PS(330) /* CFG_MMC1_CLK_IN */
0x620 A_DELAY_PS(1271) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */
0x624 A_DELAY_PS(722) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */
0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
0x62C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
0x630 A_DELAY_PS(751) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */
0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
0x638 A_DELAY_PS(20) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
0x63C A_DELAY_PS(256) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */
0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
0x648 A_DELAY_PS(263) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */
0x64C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */
0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
0x65C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
>;
};
/* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */
mmc1_iodelay_sdr104_rev11_conf: mmc1_iodelay_sdr104_rev11_conf {
pinctrl-pin-array = <
0x620 A_DELAY_PS(1063) G_DELAY_PS(17) /* CFG_MMC1_CLK_OUT */
0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
0x62c A_DELAY_PS(23) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
0x644 A_DELAY_PS(2) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
>;
};
/* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */
mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf {
pinctrl-pin-array = <
0x620 A_DELAY_PS(600) G_DELAY_PS(400) /* CFG_MMC1_CLK_OUT */
0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
0x638 A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
>;
};
/* Corresponds to MMC2_HS200_MANUAL1 in datamanual */
mmc2_iodelay_hs200_rev11_conf: mmc2_iodelay_hs200_rev11_conf {
pinctrl-pin-array = <
0x190 A_DELAY_PS(621) G_DELAY_PS(600) /* CFG_GPMC_A19_OEN */
0x194 A_DELAY_PS(300) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */
0x1a8 A_DELAY_PS(739) G_DELAY_PS(600) /* CFG_GPMC_A20_OEN */
0x1ac A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
0x1b4 A_DELAY_PS(812) G_DELAY_PS(600) /* CFG_GPMC_A21_OEN */
0x1b8 A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
0x1c0 A_DELAY_PS(954) G_DELAY_PS(600) /* CFG_GPMC_A22_OEN */
0x1c4 A_DELAY_PS(60) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
0x1d0 A_DELAY_PS(1340) G_DELAY_PS(420) /* CFG_GPMC_A23_OUT */
0x1d8 A_DELAY_PS(935) G_DELAY_PS(600) /* CFG_GPMC_A24_OEN */
0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
0x1e4 A_DELAY_PS(525) G_DELAY_PS(600) /* CFG_GPMC_A25_OEN */
0x1e8 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
0x1f0 A_DELAY_PS(767) G_DELAY_PS(600) /* CFG_GPMC_A26_OEN */
0x1f4 A_DELAY_PS(225) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
0x1fc A_DELAY_PS(565) G_DELAY_PS(600) /* CFG_GPMC_A27_OEN */
0x200 A_DELAY_PS(60) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
0x364 A_DELAY_PS(969) G_DELAY_PS(600) /* CFG_GPMC_CS1_OEN */
0x368 A_DELAY_PS(180) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
>;
};
/* Corresponds to MMC2_HS200_MANUAL1 in datamanual */
mmc2_iodelay_hs200_rev20_conf: mmc2_iodelay_hs200_rev20_conf {
pinctrl-pin-array = <
0x190 A_DELAY_PS(274) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
0x194 A_DELAY_PS(162) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */
0x1a8 A_DELAY_PS(401) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
0x1ac A_DELAY_PS(73) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
0x1b4 A_DELAY_PS(465) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
0x1b8 A_DELAY_PS(115) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
0x1c0 A_DELAY_PS(633) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
0x1c4 A_DELAY_PS(47) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
0x1d0 A_DELAY_PS(935) G_DELAY_PS(280) /* CFG_GPMC_A23_OUT */
0x1d8 A_DELAY_PS(621) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
0x1e4 A_DELAY_PS(183) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
0x1f0 A_DELAY_PS(467) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
0x1f4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
0x1fc A_DELAY_PS(262) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
0x200 A_DELAY_PS(46) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
0x364 A_DELAY_PS(684) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
0x368 A_DELAY_PS(76) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
>;
};
/* Correspnds to MMC2_DDR_3V3_MANUAL1 in datamanual */
mmc2_iodelay_ddr_3_3v_rev11_conf: mmc2_iodelay_ddr_3_3v_rev11_conf {
pinctrl-pin-array = <
0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */
0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
0x194 A_DELAY_PS(174) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */
0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */
0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
0x1ac A_DELAY_PS(168) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */
0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
0x1b8 A_DELAY_PS(136) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */
0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
0x1c4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */
0x1d0 A_DELAY_PS(879) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */
0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */
0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */
0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
0x1e8 A_DELAY_PS(34) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
0x1ec A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A26_IN */
0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
0x1f4 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
0x1f8 A_DELAY_PS(120) G_DELAY_PS(180) /* CFG_GPMC_A27_IN */
0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */
0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
0x368 A_DELAY_PS(11) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
>;
};
/* Corresponds to MMC2_DDR_1V8_MANUAL1 in datamanual */
mmc2_iodelay_ddr_1_8v_rev11_conf: mmc2_iodelay_ddr_1_8v_rev11_conf {
pinctrl-pin-array = <
0x18c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_IN */
0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
0x194 A_DELAY_PS(174) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */
0x1a4 A_DELAY_PS(274) G_DELAY_PS(240) /* CFG_GPMC_A20_IN */
0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
0x1ac A_DELAY_PS(168) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
0x1b0 A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A21_IN */
0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
0x1b8 A_DELAY_PS(136) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
0x1bc A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A22_IN */
0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
0x1c4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
0x1c8 A_DELAY_PS(514) G_DELAY_PS(360) /* CFG_GPMC_A23_IN */
0x1d0 A_DELAY_PS(879) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */
0x1d4 A_DELAY_PS(187) G_DELAY_PS(120) /* CFG_GPMC_A24_IN */
0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */
0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
0x1e8 A_DELAY_PS(34) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
0x1ec A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A26_IN */
0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
0x1f4 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
0x1f8 A_DELAY_PS(121) G_DELAY_PS(60) /* CFG_GPMC_A27_IN */
0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */
0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
0x368 A_DELAY_PS(11) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
>;
};
/* Corresponds to MMC3_MANUAL1 in datamanual */
mmc3_iodelay_manual1_rev20_conf: mmc3_iodelay_manual1_conf {
pinctrl-pin-array = <
0x678 A_DELAY_PS(0) G_DELAY_PS(386) /* CFG_MMC3_CLK_IN */
0x680 A_DELAY_PS(605) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */
0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */
0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */
0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */
0x690 A_DELAY_PS(171) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */
0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */
0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */
0x69c A_DELAY_PS(221) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */
0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */
0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */
0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */
0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */
0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */
0x6b4 A_DELAY_PS(474) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */
0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */
0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */
>;
};
/* Corresponds to MMC3_MANUAL1 in datamanual */
mmc3_iodelay_manual1_rev11_conf: mmc3_iodelay_manual1_conf {
pinctrl-pin-array = <
0x678 A_DELAY_PS(406) G_DELAY_PS(0) /* CFG_MMC3_CLK_IN */
0x680 A_DELAY_PS(659) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */
0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */
0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */
0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */
0x690 A_DELAY_PS(130) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */
0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */
0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */
0x69c A_DELAY_PS(169) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */
0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */
0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */
0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */
0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */
0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */
0x6b4 A_DELAY_PS(457) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */
0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */
0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */
>;
};
/* Corresponds to MMC4_DS_MANUAL1 in datamanual */
mmc4_iodelay_ds_rev11_conf: mmc4_iodelay_ds_rev11_conf {
pinctrl-pin-array = <
0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */
0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */
0x84c A_DELAY_PS(96) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */
0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */
0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */
0x870 A_DELAY_PS(582) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */
0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */
0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */
0x87c A_DELAY_PS(391) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */
0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */
0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */
0x888 A_DELAY_PS(561) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */
0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */
0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */
0x894 A_DELAY_PS(588) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */
0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */
0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */
>;
};
/* Corresponds to MMC4_DS_MANUAL1 in datamanual */
mmc4_iodelay_ds_rev20_conf: mmc4_iodelay_ds_rev20_conf {
pinctrl-pin-array = <
0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */
0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */
0x84c A_DELAY_PS(307) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */
0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */
0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */
0x870 A_DELAY_PS(785) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */
0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */
0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */
0x87c A_DELAY_PS(613) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */
0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */
0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */
0x888 A_DELAY_PS(683) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */
0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */
0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */
0x894 A_DELAY_PS(835) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */
0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */
0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */
>;
};
/* Corresponds to MMC4_MANUAL1 in datamanual */
mmc4_iodelay_sdr12_hs_sdr25_rev11_conf: mmc4_iodelay_sdr12_hs_sdr25_rev11_conf {
pinctrl-pin-array = <
0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */
0x848 A_DELAY_PS(2651) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */
0x84c A_DELAY_PS(1572) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */
0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */
0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */
0x870 A_DELAY_PS(1913) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */
0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */
0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */
0x87c A_DELAY_PS(1721) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */
0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */
0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */
0x888 A_DELAY_PS(1891) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */
0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */
0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */
0x894 A_DELAY_PS(1919) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */
0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */
0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */
>;
};
/* Corresponds to MMC4_MANUAL1 in datamanual */
mmc4_iodelay_sdr12_hs_sdr25_rev20_conf: mmc4_iodelay_sdr12_hs_sdr25_rev20_conf {
pinctrl-pin-array = <
0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */
0x848 A_DELAY_PS(1147) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */
0x84c A_DELAY_PS(1834) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */
0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */
0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */
0x870 A_DELAY_PS(2165) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */
0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */
0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */
0x87c A_DELAY_PS(1929) G_DELAY_PS(64) /* CFG_UART2_RTSN_IN */
0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */
0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */
0x888 A_DELAY_PS(1935) G_DELAY_PS(128) /* CFG_UART2_RXD_IN */
0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */
0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */
0x894 A_DELAY_PS(2172) G_DELAY_PS(44) /* CFG_UART2_TXD_IN */
0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */
0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */
>;
};
};

View File

@@ -13,34 +13,11 @@
compatible = "ti,dra742", "ti,dra74", "ti,dra7";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
operating-points = <
/* kHz uV */
1000000 1060000
1176000 1160000
>;
clocks = <&dpll_mpu_ck>;
clock-names = "cpu";
clock-latency = <300000>; /* From omap-cpufreq driver */
/* cooling options */
cooling-min-level = <0>;
cooling-max-level = <2>;
#cooling-cells = <2>; /* min followed by max */
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <1>;
operating-points-v2 = <&cpu0_opp_table>;
};
};
@@ -52,6 +29,11 @@
};
ocp {
dsp2_system: dsp_system@41500000 {
compatible = "syscon";
reg = <0x41500000 0x100>;
};
omap_dwc3_4: omap_dwc3_4@48940000 {
compatible = "ti,dwc3";
ti,hwmods = "usb_otg_ss4";
@@ -65,21 +47,49 @@
usb4: usb@48950000 {
compatible = "snps,dwc3";
reg = <0x48950000 0x17000>;
interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
tx-fifo-resize;
interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "peripheral",
"host",
"otg";
maximum-speed = "high-speed";
dr_mode = "otg";
};
};
mmu0_dsp2: mmu@41501000 {
compatible = "ti,dra7-dsp-iommu";
reg = <0x41501000 0x100>;
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu0_dsp2";
#iommu-cells = <0>;
ti,syscon-mmuconfig = <&dsp2_system 0x0>;
status = "disabled";
};
mmu1_dsp2: mmu@41502000 {
compatible = "ti,dra7-dsp-iommu";
reg = <0x41502000 0x100>;
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu1_dsp2";
#iommu-cells = <0>;
ti,syscon-mmuconfig = <&dsp2_system 0x1>;
status = "disabled";
};
};
};
&cpu0_opp_table {
opp-shared;
};
&dss {
reg = <0x58000000 0x80>,
<0x58004054 0x4>,
<0x58004300 0x20>,
<0x58005054 0x4>,
<0x58005300 0x20>;
<0x58009054 0x4>,
<0x58009300 0x20>;
reg-names = "dss", "pll1_clkctrl", "pll1",
"pll2_clkctrl", "pll2";
@@ -88,3 +98,29 @@
<&dss_video2_clk>;
clock-names = "fck", "video1_clk", "video2_clk";
};
&mailbox5 {
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
ti,mbox-tx = <6 2 2>;
ti,mbox-rx = <4 2 2>;
status = "disabled";
};
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
ti,mbox-tx = <5 2 2>;
ti,mbox-rx = <1 2 2>;
status = "disabled";
};
};
&mailbox6 {
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
ti,mbox-tx = <6 2 2>;
ti,mbox-rx = <4 2 2>;
status = "disabled";
};
mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
ti,mbox-tx = <5 2 2>;
ti,mbox-rx = <1 2 2>;
status = "disabled";
};
};

View File

@@ -0,0 +1,15 @@
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "omap5-u-boot.dtsi"
&cpsw_emac0 {
phy-handle = <&dp83867_0>;
};
&cpsw_emac1 {
phy-handle = <&dp83867_1>;
};

423
arch/arm/dts/dra76-evm.dts Normal file
View File

@@ -0,0 +1,423 @@
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "dra76x.dtsi"
#include "dra7-evm-common.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
/ {
model = "TI DRA762 EVM";
compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7";
memory@0 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
};
vsys_12v0: fixedregulator-vsys12v0 {
/* main supply */
compatible = "regulator-fixed";
regulator-name = "vsys_12v0";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
regulator-boot-on;
};
vsys_5v0: fixedregulator-vsys5v0 {
/* Output of Cntlr B of TPS43351-Q1 on dra76-evm */
compatible = "regulator-fixed";
regulator-name = "vsys_5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vsys_12v0>;
regulator-always-on;
regulator-boot-on;
};
vsys_3v3: fixedregulator-vsys3v3 {
/* Output of Cntlr A of TPS43351-Q1 on dra76-evm */
compatible = "regulator-fixed";
regulator-name = "vsys_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vsys_12v0>;
regulator-always-on;
regulator-boot-on;
};
vio_3v3: fixedregulator-vio_3v3 {
compatible = "regulator-fixed";
regulator-name = "vio_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vsys_3v3>;
regulator-always-on;
regulator-boot-on;
};
vio_3v3_sd: fixedregulator-sd {
compatible = "regulator-fixed";
regulator-name = "vio_3v3_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vio_3v3>;
enable-active-high;
gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
};
vio_1v8: fixedregulator-vio_1v8 {
compatible = "regulator-fixed";
regulator-name = "vio_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&smps5_reg>;
};
vtt_fixed: fixedregulator-vtt {
compatible = "regulator-fixed";
regulator-name = "vtt_fixed";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
vin-supply = <&vsys_3v3>;
regulator-always-on;
regulator-boot-on;
};
aic_dvdd: fixedregulator-aic_dvdd {
/* TPS77018DBVT */
compatible = "regulator-fixed";
regulator-name = "aic_dvdd";
vin-supply = <&vio_3v3>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
&dra7_pmx_core {
mmc1_pins_default: mmc1_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc2_pins_default: mmc2_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
tps65917: tps65917@58 {
compatible = "ti,tps65917";
reg = <0x58>;
ti,system-power-controller;
interrupt-controller;
#interrupt-cells = <2>;
tps65917_pmic {
compatible = "ti,tps65917-pmic";
smps12-in-supply = <&vsys_3v3>;
smps3-in-supply = <&vsys_3v3>;
smps4-in-supply = <&vsys_3v3>;
smps5-in-supply = <&vsys_3v3>;
ldo1-in-supply = <&vsys_3v3>;
ldo2-in-supply = <&vsys_3v3>;
ldo3-in-supply = <&vsys_5v0>;
ldo4-in-supply = <&vsys_5v0>;
ldo5-in-supply = <&vsys_3v3>;
tps65917_regulators: regulators {
smps12_reg: smps12 {
/* VDD_DSPEVE */
regulator-name = "smps12";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
smps3_reg: smps3 {
/* VDD_CORE */
regulator-name = "smps3";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-boot-on;
regulator-always-on;
};
smps4_reg: smps4 {
/* VDD_IVA */
regulator-name = "smps4";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
smps5_reg: smps5 {
/* VDDS1V8 */
regulator-name = "smps5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: ldo1 {
/* LDO1_OUT --> VDA_PHY1_1V8 */
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-allow-bypass;
};
ldo2_reg: ldo2 {
/* LDO2_OUT --> VDA_PHY2_1V8 */
regulator-name = "ldo2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-allow-bypass;
regulator-always-on;
};
ldo3_reg: ldo3 {
/* VDA_USB_3V3 */
regulator-name = "ldo3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo5_reg: ldo5 {
/* VDDA_1V8_PLL */
regulator-name = "ldo5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo4_reg: ldo4 {
/* VDD_SDIO_DV */
regulator-name = "ldo4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
tps65917_power_button {
compatible = "ti,palmas-pwrbutton";
interrupt-parent = <&tps65917>;
interrupts = <1 IRQ_TYPE_NONE>;
wakeup-source;
ti,palmas-long-press-seconds = <6>;
};
};
lp87565: lp87565@60 {
compatible = "ti,lp87565-q1";
reg = <0x60>;
buck10-in-supply =<&vsys_3v3>;
buck23-in-supply =<&vsys_3v3>;
regulators: regulators {
buck10_reg: buck10 {
/*VDD_MPU*/
regulator-name = "buck10";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
buck23_reg: buck23 {
/* VDD_GPU*/
regulator-name = "buck23";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-boot-on;
regulator-always-on;
};
};
};
pcf_lcd: pcf8757@20 {
compatible = "ti,pcf8575", "nxp,pcf8575";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
};
pcf_gpio_21: pcf8757@21 {
compatible = "ti,pcf8575", "nxp,pcf8575";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
};
pcf_hdmi: pcf8575@26 {
compatible = "ti,pcf8575", "nxp,pcf8575";
reg = <0x26>;
gpio-controller;
#gpio-cells = <2>;
p1 {
/* vin6_sel_s0: high: VIN6, low: audio */
gpio-hog;
gpios = <1 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "vin6_sel_s0";
};
};
tlv320aic3106: tlv320aic3106@19 {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic3106";
reg = <0x19>;
adc-settle-ms = <40>;
ai3x-micbias-vg = <1>; /* 2.0V */
status = "okay";
/* Regulators */
AVDD-supply = <&vio_3v3>;
IOVDD-supply = <&vio_3v3>;
DRVDD-supply = <&vio_3v3>;
DVDD-supply = <&aic_dvdd>;
};
};
&cpu0 {
vdd-supply = <&buck10_reg>;
};
&mmc1 {
status = "okay";
vmmc-supply = <&vio_3v3_sd>;
vmmc_aux-supply = <&ldo4_reg>;
bus-width = <4>;
/*
* SDCD signal is not being used here - using the fact that GPIO mode
* is always hardwired.
*/
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_default>;
};
&mmc2 {
status = "okay";
vmmc-supply = <&vio_1v8>;
bus-width = <8>;
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins_default>;
};
/* No RTC on this device */
&rtc {
status = "disabled";
};
&mac {
status = "okay";
dual_emac;
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <2>;
phy-mode = "rgmii-id";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <3>;
phy-mode = "rgmii-id";
dual_emac_res_vlan = <2>;
};
&davinci_mdio {
dp83867_0: ethernet-phy@2 {
reg = <2>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,min-output-impedance;
ti,dp83867-rxctrl-strap-quirk;
};
dp83867_1: ethernet-phy@3 {
reg = <3>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,min-output-impedance;
ti,dp83867-rxctrl-strap-quirk;
};
};
&usb2_phy1 {
phy-supply = <&ldo3_reg>;
};
&usb2_phy2 {
phy-supply = <&ldo3_reg>;
};
&qspi {
spi-max-frequency = <96000000>;
m25p80@0 {
spi-max-frequency = <96000000>;
};
};

19
arch/arm/dts/dra76x.dtsi Normal file
View File

@@ -0,0 +1,19 @@
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "dra74x.dtsi"
/ {
compatible = "ti,dra762", "ti,dra7";
};
/* MCAN interrupts are hard-wired to irqs 67, 68 */
&crossbar_mpu {
ti,irqs-skip = <10 67 68 133 139 140>;
};

View File

@@ -338,6 +338,8 @@
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
assigned-clocks = <&dpll_dsp_ck>;
assigned-clock-rates = <600000000>;
};
dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 {
@@ -349,6 +351,8 @@
reg = <0x0244>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
assigned-clocks = <&dpll_dsp_m2_ck>;
assigned-clock-rates = <600000000>;
};
iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
@@ -372,6 +376,8 @@
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
assigned-clocks = <&dpll_iva_ck>;
assigned-clock-rates = <1165000000>;
};
dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 {
@@ -383,6 +389,8 @@
reg = <0x01b0>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
assigned-clocks = <&dpll_iva_m2_ck>;
assigned-clock-rates = <388333334>;
};
iva_dclk: iva_dclk {
@@ -406,6 +414,8 @@
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
assigned-clocks = <&dpll_gpu_ck>;
assigned-clock-rates = <1277000000>;
};
dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 {
@@ -417,6 +427,8 @@
reg = <0x02e8>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
assigned-clocks = <&dpll_gpu_m2_ck>;
assigned-clock-rates = <425666667>;
};
dpll_core_m2_ck: dpll_core_m2_ck@130 {
@@ -659,6 +671,8 @@
reg = <0x0248>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
assigned-clocks = <&dpll_dsp_m3x2_ck>;
assigned-clock-rates = <400000000>;
};
dpll_gmac_x2_ck: dpll_gmac_x2_ck {
@@ -791,6 +805,8 @@
clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
ti,bit-shift = <24>;
reg = <0x0520>;
assigned-clocks = <&ipu1_gfclk_mux>;
assigned-clock-parents = <&dpll_core_h22x2_ck>;
};
mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 {
@@ -1748,6 +1764,8 @@
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
ti,bit-shift = <24>;
reg = <0x1220>;
assigned-clocks = <&gpu_core_gclk_mux>;
assigned-clock-parents = <&dpll_gpu_m2_ck>;
};
gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 {
@@ -1756,6 +1774,8 @@
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
ti,bit-shift = <26>;
reg = <0x1220>;
assigned-clocks = <&gpu_hyd_gclk_mux>;
assigned-clock-parents = <&dpll_gpu_m2_ck>;
};
l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {

View File

@@ -84,6 +84,8 @@
};
i2c-gpio-0 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
pcf8563@50 {

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