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828 Commits

Author SHA1 Message Date
Tom Rini
f14de0014c Prepare v2019.04-rc2
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-02-18 21:36:39 -05:00
Jean-Jacques Hiblot
3c5aa6cacc configs: Enable CONFIG_BLK in am57xx_evm and am57xx_hs_evm
Enable CONFIG_DM_SCSI and CONFIG_BLK.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-02-18 15:53:09 -05:00
Jean-Jacques Hiblot
fb2cedb262 configs: k2g_evm: Enable CONFIG_BLK
CONFIG_BLK can be safely enabled as DM_MMC and DM_USB are already enabled.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Vignesh R <vigneshr@ti.com>
2019-02-18 15:53:09 -05:00
Alexander Graf
7590f907da efi_loader: Swap roles with Heinrich
Heinrich is going to take over maintainership of the efi_loader tree
going forward.

To ensure that I will still receive review mails at least, add me as
reviewer with a stable email address.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-02-18 15:53:09 -05:00
Alexander Graf
3157bbfa18 rpi: Make Matthias maintainer
Matthias Brugger agreed to take over maintainership from me for the
Raspberry Pi tree. Add him to the MAINTAINERS file instead.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-02-18 15:53:09 -05:00
Hannes Schmelzer
d3a78cb7ea board/BuR/brppt1: fix ethernet support on brppt1 boards
The commit 1bac199e8c ("configs: Resync with savedefconfig")
did remove ethernet driver from following boards defconfig:

- brppt1_mmc
- brppt1_nand
- brppt1_spi

With this commit we add ethernet and responsible phy support again.

Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
2019-02-18 15:53:09 -05:00
Tom Rini
beff8e34b2 Merge tag 'efi-2019-04-rc2' of https://github.com/xypron2/u-boot
The patches fix multiple errors. Mentionable are:
- EFI unit tests (bootefi selftest) can run on i386.
- `make tests` executes the Unicode unit tests.

The LoadImage patch is preparing for further rework to be delivered
in v2019.07.
2019-02-18 15:48:01 -05:00
Tom Rini
500ad54e35 Merge tag 'video-for-2019.04-rc2' of git://git.denx.de/u-boot-video
- sunxi display DDC probe fallback
- support 24bpp BMP files on 16bpp displays
2019-02-16 18:10:53 -05:00
Tom Rini
7a2ab3778c Merge branch 'master' of git://git.denx.de/u-boot-sh
- Various MMC fixes
2019-02-16 17:05:51 -05:00
Marek Vasut
261445dfaf mmc: tmio: sdhi: Configure DT2FF register for HS400 mode
The DT2FF register must be configured differently for HS400 mode
and for HS200/SDR104 mode. Configure the DT2FF register according
to the recommended datasheet settings for each mode.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-02-16 18:12:17 +01:00
Marek Vasut
4c80f111c0 mmc: tmio: Configure HOST_MODE WMODE according to bus width
Set the HOST_MODE register WMODE bit according to the SDHI bus width,
that is 0 for 64bit bus and 1 for 16/32bit bus.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-02-16 18:12:17 +01:00
Marek Vasut
fceea99268 mmc: Downgrade SD/MMC from UHS/HS200/HS400 modes before boot
Older kernel versions or systems which do not connect eMMC reset line
properly may not be able to handle situations where either the eMMC
is left in HS200/HS400 mode or SD card in UHS modes by the bootloader
and may misbehave. Downgrade the eMMC to HS/HS52 mode and/or SD card
to non-UHS mode before booting the kernel to allow such older kernels
to work with modern U-Boot.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
2019-02-16 18:12:17 +01:00
Heinrich Schuchardt
997fc12ec9 efi_loader: do not miss last relocation block
If the last block in the relocation table contains only a single
relocation, the current coding ignores it.

Fix the determination of the end of the relocation table.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-02-16 15:51:14 +01:00
Heinrich Schuchardt
1db561e11f efi_loader: documentation of image loader
- Add missing function descriptions.
- Update existing function descriptions to match Sphinx style.
- Add lib/efi_loader/efi_image_loader.c to the input files for Sphinx
  generated documentation.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-02-16 15:48:58 +01:00
Heinrich Schuchardt
1504bb0d96 efi_loader: clean up bootefi_test_prepare()
Free resources upon failure.

Correct the function description.

As there is no need for any special address in the dummy memory device
path passed via the EFI_LOADED_IMAGE_PROTOCOL simply use 0 as address.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-02-16 15:42:20 +01:00
Heinrich Schuchardt
914df75b0c efi_loader: fix EFI entry counting
`bootefi selftest` fails on qemu-x86_defconfig if efi_selftest() is not
invoked using EFI_CALL().

Likewise we call the entry point of EFI payloads with
EFI_CALL(efi_start_image()).

entry_count indicates if we are in U-Boot (1) or in EFI payload code (0).
As we start in U-Boot code the initial value has to be 1.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-02-16 15:42:20 +01:00
Heinrich Schuchardt
f69d63fae2 efi_loader: use efi_start_image() for bootefi
Remove the duplicate code in efi_do_enter() and use efi_start_image() to
start the image invoked by the bootefi command.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-02-16 15:42:20 +01:00
Heinrich Schuchardt
8f7e2b2980 efi_loader: set entry point in efi_load_pe()
Up to now efi_load_pe() returns the entry point or NULL in case of an
error. This does not allow to return correct error codes from LoadImage().

Let efi_load_pe() return a status code and fill in the entry point in the
corresponding field of the image object.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-02-16 15:42:20 +01:00
Heinrich Schuchardt
0e18f584de efi_loader: LoadImage: always allocate new pages
If we want to properly unload images in Exit() the memory should always be
allocated in the same way. As we allocate memory when reading from file we
should do the same when the original image is in memory.

A further patch will be needed to free the memory when Exit() is called.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-02-16 15:42:20 +01:00
Heinrich Schuchardt
16112f9f48 efi_loader: error handling in efi_setup_loaded_image()
In case of an error we should set the returned pointers to NULL. This
ensures that an illegal free does not occur even if the caller calls
free() for the handles.

If protocols cannot be installed, release all resources.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-02-16 15:42:20 +01:00
Heinrich Schuchardt
bc19681acf test: adjust names of Unicode test functions
In test/py/conftest.py the assumption is made that for if a test is called
with `ut unicode` the test function name starts with 'unicode_test_'. As
the Unicode tests did not follow this naming scheme they were not executed
by `make tests`.

Rename the Unicode test functions.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-02-16 15:42:20 +01:00
Heinrich Schuchardt
60c4454ddb lib/vsprintf: print '?' for illegal Unicode sequence
Commit 0e66c10a7d ("lib: vsprintf: avoid overflow printing UTF16
strings") broke the Unicode unit tests: an illegal UTF16 code point
should be printed as '?'.

Fixes: 0e66c10a7d ("lib: vsprintf: avoid overflow printing UTF16 strings")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-02-16 15:42:20 +01:00
Heinrich Schuchardt
d787caddf1 efi_selftest: LoadImage from file device path
Provide a unit test that calls LoadImage() with a file device path and
executes the application via StartImage().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-02-16 15:42:19 +01:00
Heinrich Schuchardt
95288b1e94 efi_loader: comments for efi_file_from_path()
Add more comments for efi_file_from_path().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-02-16 15:42:19 +01:00
Heinrich Schuchardt
caf6d2fd1a efi_loader: efi_dp_split_file_path() error handling
If the path passed to efi_dp_split_file_path() does not contain a
reference to a file it returns EFI_OUT_OF_RESOURCES. This does not properly
indicate the kind of the problem that occurred. Return
EFI_INVALID_PARAMETER instead.

Update function description.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-02-16 15:42:19 +01:00
Heinrich Schuchardt
ee3c8ba855 efi_selftest: fix memory allocation in HII tests
In efi_selftest we are in EFI land. We cannot call U-Boot library
functions malloc() and free() but should use the boot time services
instead.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Alexander Graf <agraf@suse.de>
2019-02-16 15:42:19 +01:00
Heinrich Schuchardt
afa17aa23f efi_selftest: do not use efi_free_pool()
In efi_selftest we are in EFI land. We should not use U-Boot library
functions but boot time services for memory management.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Alexander Graf <agraf@suse.de>
2019-02-16 15:42:19 +01:00
Tom Rini
b89074f650 Merge tag 'u-boot-imx-2019-02-16' of git://git.denx.de/u-boot-imx
u-boot-imx-2019-02-16
---------------------

- vhybrid: add calibration
- gw_ventana: fixes
- Improve documentation for Secure Boot (HABv4)
- Fix Marvell Switch
- MX6 Sabre, switch to DM
- Fixes for NAND
2019-02-16 08:31:05 -05:00
Tom Rini
d391c13c99 Merge tag 'xilinx-for-v2019.04-rc2' of git://git.denx.de/u-boot-microblaze
Xilinx changes for v2019.04-rc2

xilinx:
- Start to use distro boot commands first
- Setup fdtfile on ZynqMP
- Move mac addr eeprom read to common location
- Convert to OF_SEPARATE
- Switch all board to DM_I2C
- Some DT syncs

i2c:
- Remove !DM_I2C zynq driver

versal:
- Enable some more features
- Add mini configurations
2019-02-15 21:21:28 -05:00
Tom Rini
e35171e94e Merge tag '2019.01-next' of https://github.com/mbgg/u-boot
- add compute module 3+
- fix 64 bit warning in bmp command
2019-02-15 20:10:15 -05:00
Max Krummenacher
6ed4d26c21 imx: cpu.c: give access to reset cause in spl
This makes get_imx_reset_cause() accessible in SPL, but keeps the SRSR
register content intact so that U-Boot proper can evaluated the
reset_cause again should this be needed.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2019-02-15 22:01:15 +01:00
Max Krummenacher
a24532083c imx: serial_mxc: disable ri and dcd irq in dte mode
If the UART is used in DTE mode the RI and DCD bits in UCR3 become
irq enable bits. Both are set to enabled after reset and both likely
are pending.

Disable the bits to prevent an interrupt storm when Linux enables
the UART interrupts.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2019-02-15 22:01:15 +01:00
Marcel Ziswiler
63c918d188 ARM: dts: i.MX6Q, i.MX6QDL: fix address/size-cells warnings
This fixes the following warnings:

arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size):
 /clocks: unnecessary #address-cells/#size-cells without "ranges" or
 child "reg" property
arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size):
 /soc/aips-bus@02100000/mipi@021e0000: unnecessary #address-cells/
 #size-cells without "ranges" or child "reg" property
arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size):
 /soc/ipu@02400000/port@2: unnecessary #address-cells/#size-cells
 without "ranges" or child "reg" property
arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size):
 /soc/ipu@02400000/port@3: unnecessary #address-cells/#size-cells
 without "ranges" or child "reg" property
arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size):
 /soc/ipu@02800000/port@2: unnecessary #address-cells/#size-cells
 without "ranges" or child "reg" property
arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size):
 /soc/ipu@02800000/port@3: unnecessary #address-cells/#size-cells
 without "ranges" or child "reg" property

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2019-02-15 22:01:15 +01:00
Tim Harvey
1d23f7b1ae imx: ventana: fix usage of dt paths with leading 0s (Linux 4.15+)
device-tree paths should never be used that reference node addresses
making an assumption about leading zeros. They should not be there per
the device-tree specification however they have been there until Linux
4.15 when they were removed via kernel commit
8dccafaa281aa1d240a58bbcdff338aec114a021.

This fixes various issues which will occur when using Linux 4.15+
that are being fixed up on a per model per PCB revision basis such as:
 - enabling MMC UHS-I on board revisions that support it
 - enabling PWM based on hwconfig
 - fixing PCIe reset on GW552x
 - removing cpu external watchdog reset on boards that do not support it
 - populate PCI dt nodes based on PCI scan in order to fix GW16082
   interrupt mapping and inject MAC address for PCI based GbE

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2019-02-15 22:01:15 +01:00
Tim Harvey
ad2efa3a28 imx: ventana: gw5904/gw5909: disable RS485
The GW5904/GW5909 have a SP33E multi-protocol serial transceiver which we
want to configure to RS232 by default (by de-asserting RS485_EN)

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2019-02-15 22:01:15 +01:00
Tim Harvey
9cdb1c6e99 imx: ventana: add support for GW5901/GW5902
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2019-02-15 22:01:15 +01:00
Tim Harvey
2285094ea9 imx: ventana: add support for GW5909
The GW5909 is a small single board computer based on the i.MX6DL SoC
with the same peripheral set as the GW5904 but with half the DRAM loaded
and an additional RS232 transceiver off UART2.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2019-02-15 22:01:15 +01:00
Tim Harvey
ebe07ef754 imx: ventana: add support for GW5908
The GW5908 is a small single board computer based on the i.MX6DL SoC
with the same peripheral set as the GW530x but with 1GiB density DRAM
(64bit 512MiB).

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2019-02-15 22:01:15 +01:00
Tim Harvey
00606b51cc imx: ventana: add support for GW5907
The GW5907 is a small single board computer based on the i.MX6DL SoC
with the following peripheral set:
 - DDR3 memory (512MB default)
 - 1x GigE (i.MX6 FEC)
 - Gateworks System Controller

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2019-02-15 22:01:15 +01:00
Tim Harvey
988916ad1b imx: ventana: add support for GW5906
The GW5906 is a GW552x with mechanical and power supply connector
differences.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2019-02-15 22:01:15 +01:00
Tim Harvey
64bdd120a0 imx: ventana: add i2c detect for all LVDS displays
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2019-02-15 22:01:15 +01:00
Tim Harvey
fd10b3b176 imx: ventana: skip nand init for nandless boards
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2019-02-15 22:01:15 +01:00
Tim Harvey
b81c07bcc3 imx: ventana: add support for Z101WX01 LVDS display
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2019-02-15 22:01:15 +01:00
Tim Harvey
d1c3867a08 imx: ventana: add support for GW5905
The GW5905 is single-board tablet computer based on the i.MX6 SoC with the
following peripheral set:
 - eMMC flash (boot device)
 - microSD expansion
 - LVDS display connector for off-board 3D+1C with PWM backlight
   and I2C based touch controller
 - MIPI camera connector supporting the TRULY CM8487-B500SA-E (OV5640)
 - ublox EMMY-W1 WiFi/Bluetooth/NFC module (SDIO/UART)
 - ublox ZOE-M8Q GPS
 - LSM9DS1 9-DOF IMU
 - 1x 1-lane miniPCIe socket with USB 2.0
 - Gateworks System Controller
 - Audio jack with TLV320AIC Audio Codec, Speaker AMP
   and TSA227E Headphone detect
 - MAX8607 3-mode LED camera flash
 - DECT ULE module
 - FUSB302 USB-C PD and ISL9238 Battery charger

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2019-02-15 22:01:15 +01:00
Tim Harvey
3f0da8748a imx: ventana: remove setup of I2C3 from SPL
Do not setup I2C3 in the SPL for Ventana as some devices on that bus
(aic3x codecs) can hang the bus causing i2c_setup to spin endlessly until
they are put into reset. Removing the setup of I2C3 from the SPL allows
the board-specific GPIO to be configured to take care of putting codecs
in reset prior to U-Boot setting up I2C3.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2019-02-15 22:01:15 +01:00
Tim Harvey
ff3568fcfe imx: ventana: do not iomux UART1
The only UART that is garunteed on Ventana boards is UART2 (serial-console).

Remove UART1 pinmux as that it is not consistent across all Ventana boards
and U-Boot doesn't need it.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2019-02-15 22:01:15 +01:00
Tim Harvey
9dde167edb imx: ventana: mv88e61xx change LED configuration
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2019-02-15 22:01:15 +01:00
Abel Vesa
c2a3d261f4 configs: mx6sabresd: Reduce SPL size by disabling DOS, EXT and EFI support
With DM and FIT enabled in SPL, there is an sram overflow. By disabling
CONFIG_SPL_DOS_PARTITION, CONFIG_SPL_EXT_SUPPORT and
CONFIG_SPL_EFI_PARTITION, we get to keep the 'one binary to fit all'
for imx6[q|qp|dl] on sabresd since the final SPL image is now under 64KB.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-02-15 22:01:15 +01:00
Abel Vesa
6b0c174d52 board: mx6sabresd: Remove the enet reset gpio handling
Rely on the phy-reset-gpios which is set in imx6qdl-sabresd dtsi
and get rid of the enet reset gpio handling from the board file.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-02-15 22:01:15 +01:00
Abel Vesa
9da2dae03e board: mx6sabresd: Remove non-DM code
Since the mx6sabreauto has DM support, remove the unused non-DM code
from mx6sabresd board file.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-02-15 22:01:15 +01:00
Abel Vesa
4926c68b0e configs: mx6sabresd: Add DM_SPI_FLASH necessary configs
Enable all neceassary configs to support DM_SPI_FLASH on mx6sabresd.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-02-15 22:01:15 +01:00
Abel Vesa
9e41cbf133 board: mx6sabreauto: Remove the non-DM code
Since the mx6sabreauto has DM support, remove the unused non-DM code
from mx6sabreauto board file.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-02-15 22:01:15 +01:00
Abel Vesa
ef4749f085 configs: mx6sabreauto: Add DM_SPI_FLASH necessary configs
Enable all neceassary configs to support DM_SPI_FLASH on mx6sabreauto.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-02-15 22:01:15 +01:00
Abel Vesa
991f2771d2 mx6sabreauto: Add DM_GPIO support
Add the DM_GPIO related config for mx6sabreauto.
Also add the gpio request calls.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-02-15 22:01:15 +01:00
Abel Vesa
bae31167e5 mx6sabresd: Add DM_GPIO support
Add the DM_GPIO related config for mx6sabresd.
Also add the gpio request calls.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-02-15 22:01:15 +01:00
Abel Vesa
1ca12f034e configs: mx6sabresd: Add SPL FIT and DM support
Enable all the necessary configs for SPL DM and FIT support for
mx6sabresd.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-02-15 22:01:15 +01:00
Abel Vesa
1f56947e6b configs: mx6sabreauto: Add SPL FIT and DM support
Enable all the necessary configs for SPL DM and FIT support for
mx6sabreauto.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-02-15 22:01:15 +01:00
Abel Vesa
67f165ddfd arm: dts: Update all the dts[i] files for imx6[q|qp|dl] sabre[auto|sd]
Update all the dts[i] files for imx6[q|qp|dl] sabre[auto|sd] to the ones
from kernel v4.20 (commit 8fe28cb58bcb2).

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-02-15 22:01:15 +01:00
Abel Vesa
e72e3549a8 arm: dts: Add all the imx6[q|qp|dl] sabre[auto|sd] u-boot dts[i] files
This allows us to keep the basic dts[i] files up-to-date with
the ones in kernel, but at the same time allowing the u-boot
to add its own properties to the existing nodes.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-02-15 22:01:15 +01:00
Abel Vesa
90571a4a19 board: mx6sabreauto: Add board_fit_config_name_match to support FIT in SPL
This matches one of the following three boards (or fails):
 - imx6q-sabreauto
 - imx6qp-sabreauto
 - imx6dl-sabreauto

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-02-15 22:01:15 +01:00
Abel Vesa
10917c4e8d board: mx6sabresd: Add board_fit_config_name_match to support FIT in SPL
This matches one of the following three boards (or fails):
 - imx6q-sabresd
 - imx6qp-sabresd
 - imx6dl-sabresd

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-02-15 22:01:15 +01:00
Abel Vesa
d76706c89a mmc: fsl_esdhc: Fix DM_REGULATOR ifdefs for SPL builds
Since the fsl_esdhc will also be used by SPL, make the
preprocessor switches more generic to allow any kind of build.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-02-15 22:01:15 +01:00
Abel Vesa
3ad186fbe9 configs: imx6sabreauto: Add DM_USB support
Add the DM support for USB. For that, DM_REGULATOR is needed.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-02-15 22:01:15 +01:00
Abel Vesa
90dcd0bc17 configs: imx6sabreauto: Add DM_MMC support
Add DM_MMC config to imx6sabreauto defconfig.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-02-15 22:01:15 +01:00
Abel Vesa
921208ebca usb: ehci-mx6: Make regulator DM_REGULATOR dependent
Do the regulator related work only if the build has the DM_REGULATOR.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-02-15 22:01:15 +01:00
Abel Vesa
79536013a3 usb: Rename SPL_USB_SUPPORT to SPL_USB_STORAGE
Since there is the SPL_USB_HOST_SUPPORT for enabling USB support in SPL,
makes more sense to rename the SPL_USB_SUPPORT as SPL_USB_STORAGE.
Everything that is not part of the usb storage support in SPL is now
build under SPL_USB_HOST_SUPPORT.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-02-15 22:01:15 +01:00
Stefan Roese
e25710305d video: bmp: Add support for 24bpp BMP files on 16bpp displays
This patch adds support to load 24bpp BMP files on 16bpp displays. This
will be used by the theadorable board. The "old" bmp command did support
this operartion mode and to not break compatibility with the move to
DM_VIDEO, we need to add this support to the "new" bmp code.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
2019-02-15 16:51:12 +01:00
Priit Laes
0220f8c223 sunxi: display: Implement fallback to ddc probe when hpd fails
There are HDMI displays where hpd pin is not connected, thus
we cannot get it to work unless we specifically set the resolution.

Rework the display probing, so hotplug detect failure causes
fallback to probing ddc for EDID data.

Signed-off-by: Priit Laes <priit.laes@paf.com>
2019-02-15 16:30:44 +01:00
Priit Laes
361604d658 sunxi: display: Move DDC PLL setup to HDMI init
Move PLL initialization code to single place so
we won't call it every time we query for EDID data.

Signed-off-by: Priit Laes <priit.laes@paf.com>
2019-02-15 16:28:58 +01:00
Michal Simek
91d7e0c47f arm64: zynqmp: Create fdtfile from compatible string
distro boot expects that fdtfile name is setup for alternative DTB.
Create this file based on the first platform compatible string.
This should ensure that one rootfs can store multiple DTBs for different
boards.
Reflect structure which is used in Linux kernel. It means dtbs are
strored in xilinx folder.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
2019-02-15 15:04:01 +01:00
Venkatesh Yadav Abbarapu
053d4bd472 arm64: zynqmp: Change the spi-rx-bus-width property to x1
As per the zc1275 design x1 mode is enabled so changing the
spi-rx-bus-width property to x1.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-15 15:04:01 +01:00
Shubhrajyoti Datta
ccc8a11935 arm64: zynqmp: Fix i2c boot warning
Fix the below warning as the core looks for the compatible
string.

[    5.198919] i2c i2c-18: of_i2c: modalias failure on
/amba/i2c@ff030000/i2c-mux@75/i2c@3/dev@19
[    5.207454] i2c i2c-18: Failed to create I2C device for
/amba/i2c@ff030000/i2c-mux@75/i2c@3/dev@19
[    5.216394] i2c i2c-18: of_i2c: modalias failure on
/amba/i2c@ff030000/i2c-mux@75/i2c@3/dev@30
[    5.224986] i2c i2c-18: Failed to create I2C device for
/amba/i2c@ff030000/i2c-mux@75/i2c@3/dev@30
[    5.233927] i2c i2c-18: of_i2c: modalias failure on
/amba/i2c@ff030000/i2c-mux@75/i2c@3/dev@35
[    5.242527] i2c i2c-18: Failed to create I2C device for
/amba/i2c@ff030000/i2c-mux@75/i2c@3/dev@35
[    5.263880] i2c i2c-18: of_i2c: modalias failure on
/amba/i2c@ff030000/i2c-mux@75/i2c@3/dev@36
[    5.272477] i2c i2c-18: Failed to create I2C device for
/amba/i2c@ff030000/i2c-mux@75/i2c@3/dev@36
[    5.281415] i2c i2c-18: of_i2c: modalias failure on
/amba/i2c@ff030000/i2c-mux@75/i2c@3/dev@51
[    5.290008] i2c i2c-18: Failed to create I2C device for
/amba/i2c@ff030000/i2c-mux@75/i2c@3/dev@51

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-15 15:04:01 +01:00
Michal Simek
1317a5e5ea arm64: zynqmp: Remove autodetected devices without description
It will never reach mainline that's why remove it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-15 15:04:01 +01:00
Amit Kucheria
9a06ed88f4 arm64: dts: Fix various entry-method properties to reflect documentation
The idle-states binding documentation[1] mentions that the
'entry-method' property is required on 64-bit platforms and must be
set to "psci".

Linux commit a13f18f59d26 ("Documentation: arm: Fix typo in the idle-states
bindings examples") attempted to fix this earlier but clearly more is
needed.

Linux docs:
Documentation/devicetree/bindings/arm/idle-states.txt (see
idle-states node)

Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-15 15:04:01 +01:00
Michal Simek
91af22bc6b xilinx: dts: Remove additional empty lines
Trivial fix.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-15 15:04:01 +01:00
Mounika Grace Akula
3c8ee337eb arm64: zynqmp: Add reset-on-timeout for all boards and modify default timeout value
This patch adds reset-on-timeout to FPD WDT which will trigger an
interrupt to PMU when watchdog expiry happens and PMU takes the
necessary action. If this property is not enabled, reason will not be
known when watchdog expiry happens.
This patch also modifies the default timeout to 60 seconds. Reason is
that if u-boot enables WDT, it will set the timeout to 10 seconds and
this is not enough to boot till Linux and start the WDT application in
Linux. 60 seconds is the maximum safest value to boot till Linux and
start the WDT application.

Users need to change this timeout value to fit their needs.

Signed-off-by: Mounika Grace Akula <mounika.grace.akula@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-15 15:04:01 +01:00
Luis Araneda
9896dc6558 ARM: dts: zynq: correct and improve the model property of dt files
Replace the current value of the model property by a more accurate
description of each board (which includes the manufacturer), as some
of the boards had the same value ("Xilinx Zynq")

Signed-off-by: Luis Araneda <luaraneda@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-15 15:04:00 +01:00
Luis Araneda
cd6160b9c1 ARM: dts: zynq: Set correct manufacturer for ZedBoard and MicroZed boards
Both boards are made by Avnet, Inc. So add an additional
value to the compatible property

Signed-off-by: Luis Araneda <luaraneda@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-15 15:04:00 +01:00
Michal Simek
7b85f7901d ARM: dts: Use mmc@ instead sdhci@
mmc name is recommended based on devicetree specification.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-15 15:04:00 +01:00
Tim Harvey
69280961d7 net: mv88e61xx: fix autonegotiation on ports
phy_reset should be called before autoneg is setup

The only boards using MV88E61XX_SWITCH are:
 - alliedtelesis/SBx81LIFKW
 - alliedtelesis/SBx81LIFXCAT
 - gateworks/gw_ventana

Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2019-02-15 13:01:28 +01:00
Breno Matheus Lima
2dd652e665 doc: imx: habv4: Remove secure_boot.txt guide
The secure_boot.txt guide was replaced by mx6_mx7_secure_boot.txt and
mx6_mx7_spl_secure_boot.txt documents.

Both documents covers all steps needed for SPL and non-SPL tagets,
so remove secure_boot.txt file to avoid duplicated content.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
2019-02-15 12:55:39 +01:00
Jonathan Gray
7e2ae620e1 rpi: add Compute Module 3+
Add Raspberry Pi Compute Module 3+ to list of models, the revision code
is 0x10 according to the list on raspberrypi.org.

v2: Use the same dtb name as CM3 as CM3+ is a drop in replacement
    for CM3.

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-02-15 12:49:13 +01:00
Adam Heinrich
77195216ff cmd: bmp: Make integer-to-pointer cast platform, independent
This patch fixes the int-to-pointer-cast warning on aarch64.

Signed-off-by: Adam Heinrich <adam@adamh.cz>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-02-15 12:48:02 +01:00
Breno Matheus Lima
364c0a89bc doc: imx: habv4: Move encrypted boot guide
All guides are currently located at doc/imx/habv4/guides/ directory.

Move encrypted_boot.txt document to guides directory.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
2019-02-15 12:47:13 +01:00
Breno Matheus Lima
cfb50207e5 doc: imx: habv4: Add Secure Boot guide for i.MX6 and i.MX7 SPL targets
The current U-Boot implementation includes SPL targets for
some NXP development boards:

- mx6sabreauto_defconfig
- mx6sabresd_defconfig
- mx6ul_14x14_evk_defconfig
- mx6ul_9x9_evk_defconfig

Add additional steps needed to completly secure the
bootloader image.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
2019-02-15 12:46:59 +01:00
Breno Matheus Lima
872cfa20cd doc: imx: habv4: Add Secure Boot guide for i.MX6 and i.MX7 non-SPL targets
Add HABv4 documentation for non-SPL targets covering the
following topics:

- How to sign an securely boot an u-boot-dtb.imx image.
- How to extend the root of trust for additional boot images.
- Add 3 CSF examples.
- Add IVT generation script example.

Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Utkarsh Gupta <utkarsh.gupta@nxp.com>
Signed-off-by: Breno Lima <breno.lima@nxp.com>
2019-02-15 12:46:45 +01:00
Breno Matheus Lima
cbc4b0418c doc: imx: habv4: Add HABv4 introduction
The HABv4 is supported in i.MX50, i.MX53, i.MX6, i.MX7,
series and i.MX 8M, i.MX8MM devices.

Add an introductory document containing the following topics:

- HABv4 Introduction
- HABv4 Secure Boot
- HABv4 Encrypted Boot
- HAB PKI tree generation
- HAB Fast Authentication PKI tree generation
- SRK Table and SRK Hash generation

Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Utkarsh Gupta <utkarsh.gupta@nxp.com>
Signed-off-by: Breno Lima <breno.lima@nxp.com>
2019-02-15 12:46:31 +01:00
Breno Matheus Lima
8a23fc9c94 doc: imx: habv4: Remove extra hab directory for a cleaner documentation structure
There is no need to have an extra hab directory under doc/imx/.

Habv4 and AHAB documentation can be added directly in doc/imx/ for a
cleaner documentation structure.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
2019-02-15 12:46:18 +01:00
Marcin Niestroj
c4f225d19f ARM: dts: imx6ul-lite*: add DTS files for liteSOM and liteboard
Import liteSOM and liteboard dts files from Linux v4.20. They will
be used after transition to driver model and device-tree based boot.

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
2019-02-15 12:45:15 +01:00
Adam Ford
04568bd0b6 MTD: nand: mxs_nand: Allow driver to auto setup ECC in SPL
The initialization of the NAND in SPL hard-coded ecc.bytes,
ecc.size, and ecc.strength which may work for some NAND parts,
but it not appropriate for others.  With the pending patch
"mxs_nand: Fix BCH read timeout error on boards requiring ECC"
the driver can auto configure the ECC when these entries are
blank.  This patch has been tested in NAND flash with oob 64
and oob 128.

Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Jörg Krause <joerg.krause@embedded.rocks>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
2019-02-15 12:42:13 +01:00
Adam Ford
8f1a5ac797 net: dm: fec: Fix regulator enable when using DM_REGULATOR
When DM_REGULATOR is enabled, the driver attempts to call
regulator_autoset() which expects the regulators to be on at boot
and/or always on and fails if they are not true.
For a more generic approach, this patch just calls
regulator_set_enable() which shouldn't have such restrictions.

Fixes: ad8c43cbca ("net: dm: fec: Support the phy-supply
binding")

Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-02-15 12:41:12 +01:00
Adam Ford
8dd0dff269 ARM: imx6q_logic: Correct phy fixup for broken ethernet
The Ethernet has been broken for some time.  This patch unifies
this board with a few others that use a similar approach to
enabling phy.  This fixes ar8031 Ethernet controller so it works.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-02-15 12:40:34 +01:00
Adam Ford
64f8340d62 ARM: imx6q_logic: Enable SPL Booting from NAND
This patch fixes a few values that were incorrect, and this
now lets SPL boot from NAND.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-02-15 12:40:02 +01:00
Adam Ford
5645df9e00 MTD: NAND: mxs_nand_init_dma: Make mxs_nand_init_dma static
mxs_nand_init_dma is only referenced from mxs_nand.c.  It's not
referenced in any headers or outside code, so this patch
defines it as static.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-02-15 12:36:44 +01:00
Adam Ford
5ae585ba3a MTD: mxs_nand: Fix BCH read timeout error on boards requiring ECC
The LogicPD board uses a Micron Flash with ECC.  To boot this from
SPL, the ECC needs to be correctly configured or the BCH engine
times out.

Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
Tested-by: Jörg Krause <joerg.krause@embedded.rocks>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
2019-02-15 12:36:08 +01:00
Lukasz Majewski
dc619924c7 ddr: vybrid: Add calibration code to memory controler's (DDRMC) setup code
This patch extends the vf610 DDR memory controller code to support SW
leveling.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
2019-02-15 12:16:50 +01:00
Lukasz Majewski
548cc1095f ddr: vybrid: Provide code to perform on-boot calibration
This patch provides the code to calibrate the DDR's
DQS to DQ signals (RDLVL).

It is based on:
VFxxx Controller Reference Manual, Rev. 0, 10/2016, page 1600
10.1.6.16.4.1 "Software Read Leveling in MC Evaluation Mode"

and NXP's community thread:
"Vybrid: About DDR leveling feature on DDRMC."
https://community.nxp.com/thread/395323

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-02-15 12:16:50 +01:00
Lukasz Majewski
c5b22a5360 ddr: vybrid: Add DDRMC calibration related registers (DQS to DQ)
This commit provides extra defines needed for DDR memory controller
calibration (read leveling performing).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
2019-02-15 12:16:50 +01:00
Tom Rini
c59786f21a Merge branch 'master' of git://git.denx.de/u-boot-sunxi
- MMC CD pin fix on Orangepi Zero plus
- SPI boot for  Olinuxino Lime2-eMMC boards
- Change in dram frequnecy for tbs_a711
2019-02-14 20:14:51 -05:00
Michal Simek
06efd3e53c arm64: zynqmp: Remove board config files
All options have been moved to Kconfig and there is no need to have
board header files. Mini configurations require them that's why they are
still there.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-14 14:31:11 +01:00
Michal Simek
f6b71d830f arm64: zynqmp: Remove SPD related configurations
SPD autodetection hasn't been enabled that's why there is zero size
difference if that options are enabled/disabled.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-14 14:31:10 +01:00
Michal Simek
35e2b92344 arm64: zynqmp: Fix logic around CONFIG_ZYNQ_SDHCI
Replace SDHCI controller listing by Kconfig symbol to let SPL know that
this board is using multiple SDHCIs controllers.
Kconfig help message should explain why this is needed.
Origin symbols were used in full u-boot but with moving to distro boot
this was fixed already.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-14 14:31:10 +01:00
Michal Simek
027b1134b2 xilinx: common: Remove !DM_i2C code for reading mac from eeprom
All platforms are converted to DM_I2C that's why there is no reason to
keep this code here.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-02-14 14:31:10 +01:00
Michal Simek
f88185bcc3 i2c: Remove ancient zynq_i2c driver
This driver is replaced by drivers/i2c/i2c-cdns.c DM based driver.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Heiko Schocher <hs@denx.de>
2019-02-14 14:31:10 +01:00
Michal Simek
6a9a7b81c6 arm64: zynqmp: Remove addresses for i2c controllers
All platforms have been converted to DM that's why there is no reason to
keep addresses in headers. They are all read from DT now.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-02-14 14:31:10 +01:00
Michal Simek
8bdad43333 arm64: zynqmp: Switch all platforms to DM_I2C
CONFIG_PCA953X is not needed because of PCA953X is integrated in gpio
subsystem already. That's why also remove CMD_PCA953X which is only for
this driver.

zcu102/zcu104-revC/zcu106/zcu111 contain links to eeprom which stores MAC address.

DM_I2C is not enabled for the whole SoC because it increase size for
mini configurations and there is no I2C symbol present to setup
dependencies.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-02-14 14:31:10 +01:00
Michal Simek
e0bc7574fa ARM: zynq: Remove addresses for i2c controllers
All platforms have been converted to DM that's why there is no reason to
keep addresses in headers. They are all read from DT now.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-02-14 14:31:10 +01:00
Michal Simek
217bb295e2 ARM: zynq: Convert dlc20 and zc70x board to DM_I2C
All these board have also eeprom enabled that's why it is also enabled
via defconfig.
There is also no need to have zc70x specific config file that's why also
remove it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-02-14 14:31:10 +01:00
Michal Simek
aeac8921ab ARM: zynq: Convert Syzygy to DM_I2C
Boards have only one controller enabled that's why move to DM_I2C is
easy.
Add also i2c alias for not to be shown as i2c bus -1 because alias
doesn't exist.
Config file points to MAC stored in eeprom but it is not listed that's
why I have added 24c08 part.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-02-14 14:31:10 +01:00
Siva Durga Prasad Paladugu
eebbfd865b arm64: versal: Add mini configuration for Versal
This patch adds new mini target for versal.
This configuration is very minimal in size which runs
from OCM. It contains support for mtest which can be
used for running DDR memory tests.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-14 14:31:10 +01:00
Michal Simek
47a766f950 arm64: versal: Move IOU_SWITCH_DIVISOR0 to Kconfig
Move hardcoded IOU_SWITCH_DIVISOR0 to Kconfig to be able to set it up
for different platforms.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-14 14:31:10 +01:00
Michal Simek
fb771793bd arm64: versal: Remove one level of indentation in board_early_init_r()
Simplify code indentation.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-14 14:31:10 +01:00
Siva Durga Prasad Paladugu
a318b93929 arm64: versal: Define distro boot commnads for qspi ospi and mmc
This patch adds distro boot commands for qspi, ospi and mmc.
The distro boot commands now reads the script from flash offset
of 63.5MB  for qspi and ospi and executes it. For mmc its same
as generic distro boot command. As either one of the qspi or ospi can
exist on hardware, defined a single distroboot command as xspi
that works for both.

Setup default location via script_offset_f to 63.5MB to match the most
xilinx reference boards for qspi, ospi for now.
512kB allocated space for script size (script_size_f) should be more
than enough to cover custom boot logic.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-14 14:31:10 +01:00
Michal Simek
fed6b06480 arm64: versal: Disable showing information about console
There is no need to see this info. It is just wasting of space/time.
It saves 308Bytes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-14 14:31:09 +01:00
Siva Durga Prasad Paladugu
3c7b4c359d arm: zynq: Update boot_targets based on bootmode
Update boot_targets based on bootmode to run corresponding
distroboot command first.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-14 14:31:09 +01:00
Siva Durga Prasad Paladugu
90e97ab31e arm: zynq: Define distro boot commnads for qspi, nand and nor
This patch adds distro boot commands for qspi, nand and nor.
The distro boot commands now reads the script from flash offset
of 15.75MB and executes it.

Setup default location via script_offset_f to 15.75MB to match the most
xilinx reference boards for qspi, nand and set the same using
script_offset_nor to 0xE2EC0000 for nor.
256kB allocated space for script size (script_size_f) should be more
than enough to cover custom boot logic.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-14 14:31:09 +01:00
Michal Simek
f3976cc61f spi: zynqmp_gqspi: Enable versal compatible string
Trivial patch.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-14 14:31:09 +01:00
Siva Durga Prasad Paladugu
0fbd2a8225 arm64: versal: Add mini eMMC configuration
This patch adds mini eMMC configuration which has only
emmc0 and emmc1 functionalities and can run from small
amount of memory. This is required for memory constraint
devices.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-14 14:31:09 +01:00
Michal Simek
5541d6d054 arm64: versal: Enable different ethernet phy for virt platform
This platform is going to become generic that's why it is necessary also
enable different PHY vendors.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-14 14:31:09 +01:00
Siva Durga Prasad Paladugu
4244f2b7e8 arm64: versal: Add new Kconfig SYS_MEM_RSVD_FOR_MMU
This patch adds new config option which is used for
reserving a specific memory for MMU Table and in this
case we are using TCM for that purpose.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-14 14:31:09 +01:00
Michal Simek
6c8788f228 ARM: zynq: Convert Antminer to OF_SEPARATE
Convert board from OF_EMBED to OF_SEPARATE.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-14 14:31:09 +01:00
Michal Simek
829e8c73dd xilinx: common: Add support for DM_I2C zynq_board_read_rom_ethaddr()
It is much easier to point to eeprom which stores information like MAC
address directly via DT. eeprom which contains this information is
pointed by /chosen/xlnx,eeprom parameter.

For example:
        chosen {
                bootargs = "earlycon";
                stdout-path = "serial0:115200n8";
+               xlnx,eeprom = &eeprom;
        };

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-14 14:31:09 +01:00
Michal Simek
9755e3db8b xilinx: Move zynq_board_read_rom_ethaddr to shared location
Zynq and ZynqMP are sharing similar code and there is no reason to do
code duplication. Move zynq_board_read_rom_ethaddr() to common file for
easier conversion to DM.
Use ZynqMP version that's why also add CONFIG_ZYNQ_EEPROM_BUS to Syzygy
which is only one Zynq board which is using this feature.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-14 14:31:09 +01:00
Siva Durga Prasad Paladugu
ad78d2641f arm64: zynqmp: Define distro boot commnads for qspi and nand
This patch adds distro boot commands for qspi and nand. The
distro boot commands now reads the script from flash offset
of 63.5MB and executes it.

Setup default location via script_offset_f to 63.5MB to match the most
xilinx reference boards. 512kB allocated space for script size
(script_size_f) should be more than enough to cover custom boot logic.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-14 14:31:09 +01:00
Michal Simek
d13f92b742 ARM: zynq: Run distribution boot commands first
This patch is doing two things.
1. Exchanging order of boot commands. distro_bootcmd is run first
followed by Xilinx boot command.
2. Remove CONFIG_BOOTCOMMAND from configs (and follow mainline) by
creating Xilinx distribution bootcommand and wiring it as the last
bootcommand.

QSPI, NAND distribution boot command will be added later.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-14 14:31:09 +01:00
Tom Rini
63f7e3fca3 Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot
Patch queue for efi - 2019-02-13

Goodness this time around:

  - HII protocol, finally allows us to run the UEFI Shell!
    (experimantal, disabled by default)
  - efi selftest now available on Cortex-M
  - NVMe support for distro boot
  - Lots of code cleanup
2019-02-13 07:12:29 -05:00
Heinrich Schuchardt
823c233b7a efi_loader: fix EFI_FILE_PROTOCOL.GetInfo()
We check the existence of files with fs_exist(). This function calls
fs_close(). If we do not set the active block device again fs_opendir()
fails and we do not set the flag EFI_FILE_DIRECTORY. Due to this error the
`cd` command in the EFI shell fails.

So let's add the missing set_blk_dev(fh) call.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
Heinrich Schuchardt
0e66c10a7d lib: vsprintf: avoid overflow printing UTF16 strings
We have to ensure while printing UTF16 strings that we do not exceed the
end of the print buffer.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
Alexander Graf
5fbb28958b efi_loader: Make HII a config option
Heinrich ran into issues with HII and iPXE which lead to #SErrors on
his Odroid-C2 system. We definitely do not want to regress just yet,
so let's not expose the HII protocols by default.

Instead, let's make it a config option that people can play with
This way, we can stabilize the code in tree without breaking any
users.

Once someone figures out, why this breaks iPXE (probably a NULL
dereference), we can enable it by default.

Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>

---

v1 -> v2:

  - Remove HII selftest as well

v2 -> v3:

  - Make config option
2019-02-13 09:40:06 +01:00
Alexander Graf
2f8ab1218f arm: Leave smccc calls in .text when efi_loader=n
Commit 81ea00838c ("efi_loader: PSCI reset and shutdown") put the SMCCC
assembly code into the efi specific code section. This is wrong when we
do not have EFI_LOADER enabled, as that strips efi runtime sections from
the output binary

Reported-by: Michal Simek <monstr@monstr.eu>
Reported-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Tested-by: Michal Simek <monstr@monstr.eu>
Fixes: 81ea00838c ("efi_loader: PSCI reset and shutdown")
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
Heinrich Schuchardt
6f8f4217e7 efi_loader: debug output for HII protocols
For correct indention use EFI_PRINT() instead of debug().

For printing efi_uintn_t or size_t use the %zu or %zx format code.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
Heinrich Schuchardt
f38753d2ef efi_selftest: fix HII tests
efi_st_printf() does not support format code %ld. Anyway the format code
for size_t would be %zu which isn't supported either.

We do not want any divisions to avoid invalid references to integer
arithmetic routines, cf.
https://gcc.gnu.org/onlinedocs/gccint/Integer-library-routines.html.

As a simple remedy remove the noisy messages from the output.
They are not relevant for automated testing.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
AKASHI Takahiro
4c4fb10da2 efi_selftest: add HII database protocols test
This efi_selftest tests HII database protocol and HII string protocol.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
AKASHI Takahiro
cb728e51a7 efi: hii: add HII config routing/access protocols
This patch is a place holder for HII configuration routing protocol and
HII configuration access protocol.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
AKASHI Takahiro
8d3b77e36e efi: hii: add keyboard layout package support
Allow for handling keyboard layout package in HII database protocol.

A package can be added or deleted in HII database protocol, but
we don't set 'current' keyboard layout as there is no driver that
requests a keyboard layout.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
AKASHI Takahiro
9ab0bdd9fe efi: hii: add guid package support
Allow for handling GUID package in HII database protocol.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
Leif Lindholm
c9bfb22296 efi_loader: Initial HII database protocols
This patch provides enough implementation of the following protocols to
run EDKII's Shell.efi and UEFI SCT:

  * EfiHiiDatabaseProtocol
  * EfiHiiStringProtocol

Not implemented are:
  * ExportPackageLists()
  * RegisterPackageNotify()/UnregisterPackageNotify()
  * SetKeyboardLayout() (i.e. *current* keyboard layout)

HII database protocol in this patch series can handle only:
  * GUID package
  * string package
  * keyboard layout package
  (The other packages, except Device path package, will be necessary
   for interactive and graphical UI.)

Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
Heinrich Schuchardt
6b59607f10 x86: do not use i386 code for x86_64 memory functions
arch/x86/lib/string.c contains assembler implementations of memcpy(),
memmove(), and memset() written for i386. Don't use it on x86_64.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
Heinrich Schuchardt
dba5148049 efi_loader: GetNextVariableName() relies on REGEX
Our implementation of GetNextVariableName() relies on
CONFIG_REGEX=y. So EFI_LOADER has to select it.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
Heinrich Schuchardt
eefb790e90 efi_loader: fix GetNextVariableName
Our current implementation of GetNextVariableName() first collects all EFI
variables. If none is found at all hexport_r() returns a zero length string
terminated by \0 and the value 1 as number of bytes in the returned buffer.

In this case GetNextVariableName() has to return EFI_NOT_FOUND.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
Heinrich Schuchardt
6c75db07f4 efi_loader: do not use symbolic links
Symbolic links are not supported on all file systems, e.g. not on FAT. So
it is not wise to use them in our source tree.

Use a qualified path to refer to lib/efi_loader/efi_freestanding.c in
scripts/Makefile.lib instead.

Reported-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
[agraf: Fix build with O=]
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
Heinrich Schuchardt
6446304460 efi_loader: use library memcpy() in helloworld.efi
Helloworld does not need its own memcpy() implementation anymore. Use the
one provided in efi_freestanding.c.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
Heinrich Schuchardt
2013c6850e efi_loader: use freestanding library for efi apps
GCC requires that freestanding programs provide memcpy(), memmove(),
memset(), and memcmp().

Add the library functions when building a *.efi files.

The EFI selftests might use other compilation flags. So use a symbolic
link to provide lib/efi_selftest/efi_freestanding.c and compile it
separately.

Reported-by: Alexander Graf <agraf@suse.de>
Fixes: 5be444d14b38 ("efi_loader: consistent build flags for EFI applications")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
Heinrich Schuchardt
f51a226436 efi_loader: provide freestanding library
GCC requires that freestanding programs provide memcpy(), memmove(),
memset(), and memcmp().

Provide the required library functions.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
AKASHI Takahiro
1170fee695 efi_selftest: fix variables test for GetNextVariableName()
There is a bug in efi variables test.
Fix it with some cosmetic improvements.

Please note that efi variables test still fails at QueryVariableInfo()
and GetVariable(), but this is not due to a change in this patch.
  ==8<==
  Testing EFI API implementation

  Selected test: 'variables'

  Setting up 'variables'
  Setting up 'variables' succeeded

  Executing 'variables'
  .../u-boot/lib/efi_selftest/efi_selftest_variables.c(60):
  TODO: QueryVariableInfo failed
  .../u-boot/lib/efi_selftest/efi_selftest_variables.c(131):
  TODO: GetVariable returned wrong length 7
  .../u-boot/lib/efi_selftest/efi_selftest_variables.c(133):
  TODO: GetVariable returned wrong value
  Executing 'variables' succeeded

  Boot services terminated

  Summary: 0 failures
  ==>8==

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
AKASHI Takahiro
d99a87f84b efi_loader: implement GetNextVariableName()
The current GetNextVariableName() is a placeholder.
With this patch, it works well as expected.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
rebased on efi-next
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
Heinrich Schuchardt
77d4d39656 efi_loader: comments for variable services
Comment the functions implementing the runtime variable services.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
Heinrich Schuchardt
8377ee36d6 efi_loader: remove duplicate function mem2hex()
Replace duplicate function mem2hex() by inline function bin2hex().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
Heinrich Schuchardt
6e37fa2293 efi_loader: eliminate duplicate function hex2mem()
Use existing inline function hex2bin() instead of defining a new one.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
Heinrich Schuchardt
bc867951a2 efi_loader: remove duplicate GUID definition
Remove duplicate definition o EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
Heinrich Schuchardt
0e3dc01eb7 efi_loader: consistent build flags for EFI applications
At the same time adding and removing the -Os flag does not make any sense.
Actually it leads to -Os not being used.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
Heinrich Schuchardt
c82f8f600a efi_loader: use u16* for file name
UTF-16 strings in our code should all be u16 *. Fix an inconsistency for
file names which may lead to a warning for printf("%ls", ).

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
Heinrich Schuchardt
0bc81a717d efi_loader: fix CopyMem()
CopyMem() must support overlapping buffers. So replace memcpy() by
memmove().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
Heinrich Schuchardt
f6c6df7ebc efi_loader: refactor switch to non-secure mode
Refactor the switch from supervisor to hypervisor to a new function called
at the beginning of do_bootefi().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
Heinrich Schuchardt
b4f471f18e efi_driver: simplify error message
Stating the function module is sufficient. We don't need file and line
number. Anyway the format code for the line number was incorrect (should
be %d).

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:05 +01:00
Heinrich Schuchardt
44e7c62a82 efi_selftest: tpl unit test, check return values
For some API calls checks for the return values are missing.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:05 +01:00
Heinrich Schuchardt
1309a159ce efi_selftest: events unit test, check return values
For some API calls checks for the return values are missing.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:05 +01:00
Heinrich Schuchardt
8a42641a3e efi_selftest: SNP unit test on sandbox
Running the simple network protocol test on the sandbox requires setting
the environment variable ethact to a network interface connected to a DHCP
server and ethrotate to 'no'. So let's make it an on-request test on the
sandbox (selectable by setting environment variable efi_selftest).

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:05 +01:00
Heinrich Schuchardt
452257a34a efi_loader: efi_set_variable use const void *
The SetVariable() runtime service does not change the data passed to it.
So mark the parameter as constant.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:05 +01:00
Heinrich Schuchardt
0bda81bfdc efi_loader: use const efi_guid_t * for variable services
The runtime variable services never change GUIDs. So we should declare
the GUID parameters as constant.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:05 +01:00
AKASHI Takahiro
056b45bc50 efi_loader: move efi_init_obj_list() to a new efi_setup.c
The function, efi_init_obj_list(), can be shared in different pseudo efi
applications, like bootefi/bootmgr as well as my efishell. Moreover, it
will be utilized to extend efi initialization, for example, my "removable
disk support" patch and "capsule-on-disk support" patch in the future.

So with this patch, it will be moved to a new file, efi_setup.c, under
lib/efi_loader and exported, making no changes in functionality.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Remove lines deactivated by #if 1 #else
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:05 +01:00
Heinrich Schuchardt
4f3cb4d578 doc: README.uefi: fix typos
%s/specfication/specification/
%s/selftest/self-test/
%s/little endian/little-endian/

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:05 +01:00
Heinrich Schuchardt
e4fd695645 efi_selftest: allow building on ARMv7-M
ARMv7-M only supports the Thumb instruction set. Our current crt0 code does
not support it. With the patch we can build all unit tests of the EFI
subsystem that do not require crt0.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:05 +01:00
Heinrich Schuchardt
cc8e34178b efi_loader: signature of StartImage and Exit
We use u16* for Unicode strings and efi_uintn_t for UINTN. Correct the
signature of efi_exit() and efi_start_image().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:05 +01:00
Heinrich Schuchardt
c6d876fa2d efi_loader: avoid unnecessary pointer to long conversion
debug() support supports %p to print pointers.

The debug message is unique. So there is not need to write a possibly
distracting line number.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:05 +01:00
Heinrich Schuchardt
23f5f4abf7 efi_loader: fix memory allocation on sandbox
Commit 7b78d6438a ("efi_loader: Reserve unaccessible memory") introduced
a comparison between RAM top and RAM start that was not known at the time
when the patch of commit 49759743bf ("efi_loader: eliminate sandbox
addresses") was written.

The sandbox uses an address space that is only relevant in the sandbox
context. We have to map ram_top from the sandbox address space to the
physical address space before using it in the EFI subsystem.

Fixes: 49759743bf ("efi_loader: eliminate sandbox addresses")
Fixes: 7b78d6438a ("efi_loader: Reserve unaccessible memory")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:05 +01:00
Heinrich Schuchardt
0ea8741ff6 efi_loader: CMD_BOOTEFI_HELLO_COMPILE in configs
It should not be necessary to adjust CMD_BOOTEFI_HELLO_COMPILE in config
files.

arch/arm/lib/crt0_arm_efi.S cannot be compiled in thumbs mode. We can
disable CMD_BOOTEFI_HELLO_COMPILE for CONFIG_CPU_V7M. So there is no longer
a need to disable it in stm32 configs.

helloworld.efi can be built without problems on x86_64. So there is no need
to disable it in chromebook_link64_defconfig and qemu-x86_64_defconfig.

Same is true for ARM V7A. So do not disable CMD_BOOTEFI_HELLO_COMPILE in
kp_imx6q_tpc_defconfig.

Some architecture checks are already make for EFI_LOADER. There is no need
to repeat them for CMD_BOOTEFI_HELLO_COMPILE

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrice.Chotard@st.com
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:05 +01:00
Heinrich Schuchardt
0a76ba6556 efi_loader: use named constant for efi_dp_from_mem()
When calling efi_dp_from_mem() use a named constant for the memory type.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:05 +01:00
AKASHI Takahiro
13dd6665ed distro: not taint environment variables if possible
The aim of this patch is not to have temporary variables used in
distro_bootcmd left as environment variables after run something.
See the discussion[1].
Without this patch, saveenv command also saves those variables, too.
While they are apparently safe, scsi_need_init can be harmful.

Please note that, in most cases, a variable should be converted to
hush's local variable, while "devplist" cannot because it is created
by "part" command as an environment variable.

[1] https://lists.denx.de/pipermail/u-boot/2018-December/350209.html

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:05 +01:00
Heinrich Schuchardt
d178836bd2 efi_loader: efi_connect_controller() use %pD
EFI_ENTRY in efi_connect_controller() should use %pD to print the remaining
device path.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:05 +01:00
Heinrich Schuchardt
fb34f298e6 efi_loader: efi_add_runtime_mmio()
The first parameter of efi_add_runtime_mmio() is a pointer to a
pointer. This should be reflected in the documentation.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:05 +01:00
Heinrich Schuchardt
9493e39cd4 distro_bootcmd: add NVME support
Some boards support NVME drives. We should be able to use them as boot
devices.

NVME access requires running 'nvme scan'.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:05 +01:00
Heinrich Schuchardt
abb93cb0e5 test: tests for u16_strdup() and u16_strcpy()
Provide unit tests for u16_strdup() and u16_strcpy().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:05 +01:00
Akashi, Takahiro
2a3537ae22 lib: add u16_strcpy/strdup functions
Add u16_strcpy() and u16_strdup(). The latter function will be
used later in implementing efi HII database protocol.

Signed-off-by: Akashi Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:05 +01:00
Heinrich Schuchardt
2859f446b0 efi_loader: struct efi_configuration_table
Commit 393fccdf6c73 ("efi_loader: efi_guid_t must be 64-bit aligned")
has changed the alignment of efi_guid_t. This changed the size of
struct efi_configuration_table on 32-bit systems form 20 to 24 bytes. As
an array of this type is pointed to by the system table this breaks
compatibility with existing versions of GRUB and Linux. Let's get back the
original size by using the attribute __packed.

Fixes: 393fccdf6c73 ("efi_loader: efi_guid_t must be 64-bit aligned")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:05 +01:00
Heinrich Schuchardt
4b05fe9c55 efi_loader: efi_guid_t must be 64-bit aligned
The UEFI Specification Version 2.7 Errata A defines:

"EFI_GUID
128-bit buffer containing a unique identifier value.
Unless otherwise specified, aligned on a 64-bit boundary."

Before this patch efi_guid_t was 8-bit aligned.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:05 +01:00
Heinrich Schuchardt
b1b1bab7f9 test/py: use default load address for tftp
On x86_64 the size of the file u-boot loaded by the tftp test has grown in
size such that when loading the file to 0x200000 it overwrites a memory
area reserved for PCI.

If no load address is specified for tftp do not use the ram base address
(or if zero 0x200000) but the default address.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-02-12 07:19:24 -05:00
Tom Rini
49a97162ea Merge git://git.denx.de/u-boot-x86
- Edison switch to CONFIG_OF_SEPARATE.
- Tangier initial ACPI support for PMIC device.
- TSC timer driver update to support native calibration.
- Fixes to 64-bit U-Boot proper.
2019-02-12 07:16:46 -05:00
Tomas Novotny
d065a6c00a configs: tbs_a711: lower dram frequency
The dram chip on the tablet was changed. The new one requires a lower
frequency, so change it.

Frequency 564MHz was also stable in the tests, but use slightly lower one
to be on a safe side.

Signed-off-by: Tomas Novotny <tomas@novotny.cz>
[jagan: add MHz in commit message]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-02-12 17:25:44 +05:30
Andy Shevchenko
24b56e2bf3 x86: tangier: Add initial ACPI support for PMIC device
Basin Cove PMIC is connected to I2C0 bus which is hidden from the OS
and access is going via SCU device, enumerated via PCI.

For now, we add just a minimum support of PMIC device to allow enabling,
e.g. USB OTG, in the OS.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-12 14:37:17 +08:00
Bin Meng
bc1a8f0d7a x86: Use the existing GDT in the ROM for 64-bit U-Boot proper
It is unnecessary to use a RAM version GDT for 64-bit U-Boot proper.
In fact we can just use the ROM version directly, which not only
eliminates the risk of being overwritten by application, but also
removes the complexity of patching the cpu_call64().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-12 14:37:17 +08:00
Bin Meng
9168326037 x86: Don't copy the cpu_call64() function to a hardcoded address
Before jumping to 64-bit U-Boot proper, SPL copies the cpu_call64()
function to a hardcoded address 0x3000000. This can have potential
conflicts with application usage. Switch the destination address
to be allocated from the heap to avoid such risk.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-12 14:37:16 +08:00
Bin Meng
dbb0696ba0 x86: Change 4-level page table base address to low memory
At present the 4-level page table base address for 64-bit U-Boot
proper is assigned an address that conflicts with CONFIG_LOADADDR.
Change it to an address within the low memory range instead.

Fixes crashes seen when 'dhcp' on QEMU x86_64 with
"-net nic -net user,tftp=.,bootfile=u-boot".

Reported-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-12 14:37:16 +08:00
Bernhard Messerklinger
ca7db866fe x86: tsc: Add support for native calibration of TSC freq
Add native tsc calibration function. Calibrate the tsc timer the same
way as linux does in arch/x86/kernel/tsc.c.

Fixes booting for Apollo Lake processors.

Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-12 14:37:16 +08:00
Andy Shevchenko
2436396a11 doc: Fix CONFIG_OF_SEPARATE description
CONFIG_OF_SEPARATE description is not in align with actual code in Makefile and
thus has misleading instructions and explanation.

Make it aligned with the actual code.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-12 14:37:16 +08:00
Andy Shevchenko
2c8811b757 x86: edison: Switch to CONFIG_OF_SEPARATE
There is no need for Intel Edison to have CONFIG_OF_EMBED to be enabled.
Replace it with CONFIG_OF_SEPARATE.

There is no functional change since u-boot.bin always contains DTB
either embedded or attached.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Ferry Toth <ftoth@exalondelft.nl>
2019-02-12 14:37:16 +08:00
Tom Rini
f94fa0e94f Merge branch 'master' of git://git.denx.de/u-boot-i2c
- DM I2C improvements
2019-02-11 11:15:34 -05:00
Tom Rini
f49929772c Merge git://git.denx.de/u-boot-marvell
- Fix BUILD_TARGET for ARCH_MVEBU from Baruch
- Fix MVEBU PCIe reset issues from Baruch
- Increase DDR stability on x530 from Chris
2019-02-11 10:35:52 -05:00
Chris Packham
a6ac775bae ARM: mvebu: x530: use MV_DDR_FREQ_SAR
MV_DDR_FREQ_SAR lets the DDR frequency be determined by hardware
strapping. This also has the side effect of running the DDR clock in
synchronous mode with the CPU core clock rather than from an independent
PLL. We've seen this improve reliability in operation across a number of
boards and temperature ranges.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-02-11 09:39:12 +01:00
Baruch Siach
0ef6920843 Kconfig: fix BUILD_TARGET for ARCH_MVEBU
Commit dc146ca111 ("Kconfig: Migrate CONFIG_BUILD_TARGET") made the
mvebu default build target depend on CONFIG_SPL_BUILD. Unfortunately,
there is no such Kconfig symbol. Use the CONFIG_SPL symbol instead to
fix that.

Cc: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-02-11 09:39:12 +01:00
Baruch Siach
d7f165cf67 arm: mvebu: cf gt-8k: dts: add PCIe slot reset support
Describe the mini-PCIe slot gpio reset signal. This enables PCIe devices
on Clearfog GT-8K.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-02-11 09:39:12 +01:00
Baruch Siach
6664a0e5f3 pcie: designware: mvebu: fix reset release polarity
The dm_gpio_set_value() routine sets signal logical level, with
GPIO_ACTIVE_LOW/HIGH value taken into account. Reset active value is 1
(asserted), while reset inactive value is 0 (de-asserted). Fix the reset
toggle code to set the correct reset logic value.

Reported-by: Sven Auhagen <sven.auhagen@voleatech.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-02-11 09:39:12 +01:00
Baruch Siach
f301ba55c8 arm: mvebu: mcbin: dts: fix PCIe reset polarity
The PCIe slot PERST signal is active low. Fix the gpio signal
description in the dts.

This happened to work because the pcie_dw_mvebu driver sets the reset
gpio level to 1 (high) to release the reset. The following commit will
fix that.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-02-11 09:39:12 +01:00
Michal Simek
c4bd12a7da i2c: mux: Generate longer i2c mux name
For !DM case busses are listed as
ZynqMP> i2c bus
Bus 0:	zynq_0
Bus 1:	zynq_0->PCA9544A@0x75:0
Bus 2:	zynq_0->PCA9544A@0x75:1
Bus 3:	zynq_0->PCA9544A@0x75:2
Bus 4:	zynq_1
Bus 5:	zynq_1->PCA9548@0x74:0
Bus 6:	zynq_1->PCA9548@0x74:1
Bus 7:	zynq_1->PCA9548@0x74:2
Bus 8:	zynq_1->PCA9548@0x74:3
Bus 9:	zynq_1->PCA9548@0x74:4
Bus 10:	zynq_1->PCA9548@0x75:0
Bus 11:	zynq_1->PCA9548@0x75:1
Bus 12:	zynq_1->PCA9548@0x75:2
Bus 13:	zynq_1->PCA9548@0x75:3
Bus 14:	zynq_1->PCA9548@0x75:4
Bus 15:	zynq_1->PCA9548@0x75:5
Bus 16:	zynq_1->PCA9548@0x75:6
Bus 17:	zynq_1->PCA9548@0x75:7

where is exactly describing i2c bus topology.
By moving to DM case i2c mux buses are using names from DT and because
i2c-muxes describing sub busses with the same names like i2c@0, etc it
is hard to identify which bus is where.
Linux is adding topology information to i2c-mux busses to identify them
better.
This patch is doing the same and composing bus name with topology
information.

When patch is applied with topology information on zcu102-revA.
ZynqMP> i2c bus
Bus 0:	i2c@ff020000
   20: gpio@20, offset len 1, flags 0
   21: gpio@21, offset len 1, flags 0
   75: i2c-mux@75, offset len 1, flags 0
Bus 2:	i2c@ff020000->i2c-mux@75->i2c@0
Bus 3:	i2c@ff020000->i2c-mux@75->i2c@1
Bus 4:	i2c@ff020000->i2c-mux@75->i2c@2
Bus 1:	i2c@ff030000  (active 1)
   74: i2c-mux@74, offset len 1, flags 0
   75: i2c-mux@75, offset len 1, flags 0
Bus 5:	i2c@ff030000->i2c-mux@74->i2c@0  (active 5)
   54: eeprom@54, offset len 1, flags 0
Bus 6:	i2c@ff030000->i2c-mux@74->i2c@1
Bus 7:	i2c@ff030000->i2c-mux@74->i2c@2
Bus 8:	i2c@ff030000->i2c-mux@74->i2c@3
Bus 9:	i2c@ff030000->i2c-mux@74->i2c@4
Bus 10:	i2c@ff030000->i2c-mux@75->i2c@0
Bus 11:	i2c@ff030000->i2c-mux@75->i2c@1
Bus 12:	i2c@ff030000->i2c-mux@75->i2c@2
Bus 13:	i2c@ff030000->i2c-mux@75->i2c@3
Bus 14:	i2c@ff030000->i2c-mux@75->i2c@4
Bus 15:	i2c@ff030000->i2c-mux@75->i2c@5
Bus 16:	i2c@ff030000->i2c-mux@75->i2c@6
Bus 17:	i2c@ff030000->i2c-mux@75->i2c@7

Behavior before the patch is applied.
ZynqMP> i2c bus
Bus 0:	i2c@ff020000
   20: gpio@20, offset len 1, flags 0
   21: gpio@21, offset len 1, flags 0
   75: i2c-mux@75, offset len 1, flags 0
Bus 2:	i2c@0
Bus 3:	i2c@1
Bus 4:	i2c@2
Bus 1:	i2c@ff030000  (active 1)
   74: i2c-mux@74, offset len 1, flags 0
   75: i2c-mux@75, offset len 1, flags 0
Bus 5:	i2c@0  (active 5)
   54: eeprom@54, offset len 1, flags 0
Bus 6:	i2c@1
Bus 7:	i2c@2
Bus 8:	i2c@3
Bus 9:	i2c@4
Bus 10:	i2c@0
Bus 11:	i2c@1
Bus 12:	i2c@2
Bus 13:	i2c@3
Bus 14:	i2c@4
Bus 15:	i2c@5
Bus 16:	i2c@6
Bus 17:	i2c@7

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-02-11 09:38:23 +01:00
Michal Simek
61607225d1 i2c: Fill req_seq in i2c_post_bind()
For i2c controllers which are missing alias in DT there is no req_seq
setup. This function is setting up proper ID based on highest found
alias ID.

On zcu102 this is the behavior when patch is applied.
ZynqMP> i2c bus
Bus 0:	i2c@ff020000
   20: gpio@20, offset len 1, flags 0
   21: gpio@21, offset len 1, flags 0
   75: i2c-mux@75, offset len 1, flags 0
Bus 2:	i2c@0
Bus 3:	i2c@1
Bus 4:	i2c@2
Bus 1:	i2c@ff030000  (active 1)
   74: i2c-mux@74, offset len 1, flags 0
   75: i2c-mux@75, offset len 1, flags 0
Bus 5:	i2c@0  (active 5)
   54: eeprom@54, offset len 1, flags 0
Bus 6:	i2c@1
Bus 7:	i2c@2
Bus 8:	i2c@3
Bus 9:	i2c@4
Bus 10:	i2c@0
Bus 11:	i2c@1
Bus 12:	i2c@2
Bus 13:	i2c@3
Bus 14:	i2c@4
Bus 15:	i2c@5
Bus 16:	i2c@6
Bus 17:	i2c@7

Before this patch applied (controllers have -1 ID)
ZynqMP> i2c bus
Bus 0:	i2c@ff020000
   20: gpio@20, offset len 1, flags 0
   21: gpio@21, offset len 1, flags 0
   75: i2c-mux@75, offset len 1, flags 0
Bus -1:	i2c@0
Bus -1:	i2c@1
Bus -1:	i2c@2
Bus 1:	i2c@ff030000  (active 1)
   74: i2c-mux@74, offset len 1, flags 0
   75: i2c-mux@75, offset len 1, flags 0
Bus -1:	i2c@0  (active 0)
   54: eeprom@54, offset len 1, flags 0
Bus -1:	i2c@1
Bus -1:	i2c@2
Bus -1:	i2c@3
Bus -1:	i2c@4
Bus -1:	i2c@0
Bus -1:	i2c@1
Bus -1:	i2c@2
Bus -1:	i2c@3
Bus -1:	i2c@4
Bus -1:	i2c@5
Bus -1:	i2c@6
Bus -1:	i2c@7

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-02-11 09:38:23 +01:00
Michal Simek
6bfacc8aad i2c: dm: Record maximum id of devices before probing devices
There is a need to find out the first free i2c ID which can be used for
i2s buses (including i2c buses connected to i2c mux). Do it early in
init and share this variable with other i2c classes for uniq bus
identification.

add from hs:
fix build problem in i2c-uclass.c for omap devices

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-02-11 09:37:27 +01:00
Hauke Mehrtens
9b83787c0c sun50i: h5: Orange Pi Zero Plus: Fix SdCard detection
The Detection pin is at PF6 and not at PH13 like defined before. I
checked the schematics and now I am am not seeing this error message any
more:
Loading Environment from FAT... Card did not respond to voltage select!

CONFIG_MMC_SUNXI_SLOT_EXTRA is also not needed because the second MCC
slot is for the Wifi card.

Fixes: 76d69eb01d ("sun50i: h5: Add initial Orange Pi Zero Plus support")
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-02-11 13:03:07 +05:30
Priit Laes
58e9502e6d arm: sunxi: Enable SPL/SPI boot for Olinuxino Lime2-eMMC boards
Starting from revision K the Olimex-Lime2-eMMC boards include
eMMC 5.x chip. Unfortunately, the internal brom in the A20
cannot reliably initialize those chips resulting in random
boot failures on those boards.

To overcome this, all the latest Lime2-eMMC boards are
populated with 16MB SPI flash and therefore enable support
for SPI SPL boot.

For now, SPI flash can be managed using sunxi-fel's spiflash tools.

Signed-off-by: Priit Laes <priit.laes@paf.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-02-11 13:02:44 +05:30
Tom Rini
dbe70c7d4e Merge branch 'master' of git://git.denx.de/u-boot-sh
- SD/MMC fixes and ext4 memory leak fix
2019-02-10 08:11:53 -05:00
Tom Rini
151b8339cc Merge tag 'dm-pull-10feb19' of git://git.denx.de/u-boot-dm
Samsung sound patches (applied for Samsung maintainer)
Common sound support
buildman environment support
of-platdata documentation improvements
2019-02-10 08:11:32 -05:00
Tom Rini
2e8560797f Merge branch '2019-02-08-master-imports'
- bcm6345 watchdog, bcm63158/bcm963158 initial support.
- Various TI platform resyncs and improvements.
- FDT support in Android-format images.
- stm32mp1 improvements.
2019-02-10 08:04:53 -05:00
Simon Glass
afcd645794 sound: Allow audio codecs to be used by other SoCs
At present there is still some samsung-specific code in the audio codecs.
Remove it so that these can be used by other SoCs.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-02-09 12:50:22 -07:00
Simon Glass
f0b02f3dd6 sound: i2s: Tidy up a few comments
Fix a struct typo and drop a comment (and function prototype) which is not
actually used.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-02-09 12:50:22 -07:00
Simon Glass
4a68a60e53 sound: samsung: Fix 'regiter' typo
Fix a typo that appears many times in this file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-02-09 12:50:22 -07:00
Simon Glass
e5d611671d misc: Allow child devices
Allow misc devices to have children, so that we can use this uclass for
cases where a child device (e.g. I2S) needs to access a misc driver for
transferring data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-02-09 12:50:22 -07:00
Chris Packham
58804b8cf2 buildman: fix typo
Fix a typo in the error message from CheckOutputDir().

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-09 12:50:22 -07:00
Simon Goldschmidt
3600b46117 of-platdata: improve documentation
Improve some things in the documentation of OF_PLATDATA that I found
while porting socfgpa_gen5 to it.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-09 12:50:22 -07:00
Simon Glass
e5fc79ea71 buildman: Write the environment out to an 'env' file
Sometimes it is useful to see the environment that was used to build
U-Boot. Write this out to a file in the build directory.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-02-09 12:50:22 -07:00
Lokesh Vutla
d3de38554a mmc: omap_hsmmc: Use regulator_set_enable_if_allowed for enabling regulator
Use regulator_set_enable_if_allowed() api instead of regulator_set_enable()
while enabling io regulators. This way the driver doesn't see an error
when disabling an always-on regulator and when enabling is not supported.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-02-09 12:50:22 -07:00
Lokesh Vutla
cc4a224af2 power: regulator: Introduce regulator_set_enable_if_allowed api
regulator_set_enable() api throws an error in the following three cases:
- when requested to disable an always-on regulator
- when set_enable() ops not provided by regulator driver
- when enabling is actually failed.(Error returned by the regulator driver)

Sometimes consumer drivers doesn't want to track the first two scenarios
and just need to worry about the case where enabling is actually failed.
But it is also a good practice to have an error value returned in the
first two cases.

So introduce an api regulator_set_enable_if_allowed() which ignores the
first two error cases and returns an error as given by regulator driver.
Consumer drivers can use this api need not worry about the first two
error conditions.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-09 12:50:22 -07:00
Lokesh Vutla
f93fab3126 Revert "power: regulator: Return success on attempt to disable an always-on regulator"
This reverts commit e17e0ceb83.

It is advised to return an error when trying to disable an always-on
regulator and let the consumer driver handle the error if needed.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-02-09 12:50:22 -07:00
Simon Glass
91b3a1866b fdt: tegra: Drop COMPAT_AMS_AS3722
This is no-longer used. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-02-09 12:50:22 -07:00
Simon Glass
38b043d452 fdt: samsung: Drop unused fdt_compat_id values
This enum still exists but we can shrink it a little based on recent
driver-model conversions with samsung. Update it to remove unused items.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-02-09 12:50:22 -07:00
Simon Glass
e898799ce4 samsung: mmc: Drop old MMC init code
Now that these boards use driver model we can drop the old code. At
present s5p_mmc_init() is still used by goni and smdkv310 so cannot be
removed unless we remove those boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2019-02-09 12:50:22 -07:00
Simon Glass
cdc033136e samsung: Drop board_enable_audio_codec()
This function is not needed now since the audio codecs have been converted
to proper drivers. The codec-enable GPIO is handled there.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2019-02-09 12:50:22 -07:00
Simon Glass
f656daea64 spring: Update flashmap details
Update the flashmap so that this board can be started over USB A-A. It
is slightly different from snow.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-02-09 12:50:22 -07:00
Simon Glass
8d135f5c6f spring: Update sound to use max98088 codec
Update the spring settings to use this codec, which is what it actually
shipped with.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-02-09 12:50:22 -07:00
Simon Glass
9a7210f6a4 sound: Add a driver for max98088
This chip is used by spring. Add a driver for it and update the
samsung_sound driver to pick it up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-02-09 12:50:22 -07:00
Simon Glass
e2932310a5 exynos: Convert to use CONFIG_BLK
Move all exynos boards over to use CONFIG_BLK.

This converts s5p_goni also, but adding dummy functions for pinmux and
peripheral ID. This will not function correctly, but gives the maintainer
more time to convert the board if desired.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2019-02-09 12:50:21 -07:00
Simon Glass
a42ff927a7 exynos: Drop duplicate 'model' line
At present the model is shown twice, once in the generic code and once
in the exynos code. Drop the latter.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2019-02-09 12:50:21 -07:00
Simon Glass
bed44f499f Convert CONFIG_BOARD_TYPES to Kconfig
This converts the following to Kconfig:
   CONFIG_BOARD_TYPES

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2019-02-09 12:50:21 -07:00
Andreas Dannenberg
4a1fa524e9 arm: mach-k3: common: Clean up ATF image startup function
Perform some cosmetic cleanup of the ATF image startup function, namely
fixing a spelling mistake, capitalization of a few words, spacing, as
well aligning how errors are printed and as using panic() for cases that
were using a combination of printf() + hang().

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-02-09 07:51:02 -05:00
Philippe Reynes
eefc01d590 bcm968580xref: switch to CONFIG_OF_SEPARATE
The option OF_EMBED is deprecated,
so we switch to CONFIG_OF_SEPARATE

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-02-09 07:51:02 -05:00
Philippe Reynes
5f137b5a58 bcm968580: rename to bcm968580xref
The name of the board is bcm968580xref,
so rename the config to bcm968580xref too.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-02-09 07:51:02 -05:00
Andrew F. Davis
45b7f5b408 armv7R: K3: am654: Fix order of debug elements in x509 template
The first element in the debug section is expected to be debugUID.
ROM will not parse this correctly when out of order, fix this here.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-02-09 07:51:01 -05:00
Andrew F. Davis
64176a8f5c am65x_evm: Allow bootm to load larger kernels
Bootm will fail to load kernels over 8MB, this is not enough
for our 64bit kernel images. Increase this to 64MB.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-02-09 07:51:01 -05:00
Andrew F. Davis
e8cc366ca7 configs: am65x_evm_r5: Enable GPT support
The second loader stages may be stored on GPT partitions,
enable support for this here.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-02-09 07:51:01 -05:00
Marcel Ziswiler
b3860bfe77 cmd: sata: add null pointer check for dev
Calling sata_scan() with a null pointer probably won't make much sense.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-09 07:51:00 -05:00
Marcel Ziswiler
f388564965 dm: device: fail uclass_find_first_device() if list_empty
While uclass_find_device() fails with -ENODEV in case of list_empty
strangely uclass_find_first_device() returns 0.

Fix uclass_find_first_device() to also fail with -ENODEV instead.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-09 07:51:00 -05:00
Philippe Reynes
a765adc08f bcm963158: enable watchdog and reboot with watchdog
Enable watchdog and reboot with watchdog in the configuration.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-02-09 07:51:00 -05:00
Philippe Reynes
2f4a686f21 dt: bcm63158: add watchdog
This commit add watchdog and sysreset watchdog
in the bcm63158 device tree.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-02-09 07:51:00 -05:00
Philippe Reynes
dcae39e55f watchdog: bcm6345: allow to use this driver on arm bcm63158
This IP is also used on some arm SoC, so we allow to
use it on arm bcm63158 too.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-02-09 07:50:59 -05:00
Philippe Reynes
be2fc084d9 bcm963158: add initial support
This add the initial support of the broadcom reference
board bcm963158 with a bcm63158 SoC.

This board has 1 GB of ram, 512 MB of flash (nand),
2 usb port, 1 uart, 4 ethernet ports (LAN), 1 ethernet port (WAN).

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-02-09 07:50:59 -05:00
Philippe Reynes
ea1a7de532 bcm63158: add initial support
This add the initial support of the broadcom bcm63158 SoC family,
only the cpu, dram and uart are supported.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-02-09 07:50:59 -05:00
Alexander Graf
47870afab9 initcall: Move to inline function
The board_r init function was complaining that we are looping through
an array, calling all our tiny init stubs sequentially via indirect
function calls (which can't be speculated, so they are slow).

The solution to that is pretty easy though. All we need to do is inline
the function that loops through the functions and the compiler will
automatically convert almost all indirect calls into direct inlined code.

With this patch, the overall code size drops (by 40 bytes on riscv64)
and boot time should become measurably faster for every target.

Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-09 07:50:58 -05:00
Hannes Schmelzer
a9484aa769 board/BuR/brppt1: drop DM_I2C_COMPAT
The TPS62517 PMIC driver has been partially converted to DM, so the
legacy I2C access layer isn't needed anymore.

Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
2019-02-09 07:50:58 -05:00
Faiz Abbas
351a4aa050 mmc: omap_hsmmc: Workaround errata regarding SDR104/HS200 tuning failures (i929)
Errata i929 in certain OMAP5/DRA7XX/AM57XX silicon revisions
(SPRZ426D - November 2014 - Revised February 2018 [1]) mentions
unexpected tuning pattern errors. A small failure band may be present
in the tuning range which may be missed by the current algorithm.
Furthermore, the failure bands vary with temperature leading to
different optimum tuning values for different temperatures.

As suggested in the related Application Report (SPRACA9B - October 2017
- Revised July 2018 [2]), tuning should be done in two stages.
In stage 1, assign the optimum ratio in the maximum pass window for the
current temperature. In stage 2, if the chosen value is close to the
small failure band, move away from it in the appropriate direction.

References:
[1] http://www.ti.com/lit/pdf/sprz426
[2] http://www.ti.com/lit/pdf/SPRACA9

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-02-09 07:50:58 -05:00
Patrick Delaunay
bbd108a082 clk: stm32mp1: correctly handle Clock Spreading Generator
To activate the csg option, the driver need to set the bit2
of PLLNCR register = SSCG_CTRL: Spread Spectrum Clock Generator
of PLLn enable.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-09 07:50:57 -05:00
Patrick Delaunay
e74b74c528 dts: stm32mp1: clock tree update
- Add st,digbypass on clk_hse node (needed for board rev.C)
- MLAHB/AHB max frequency increased from 200 to 209MHz, with:
  - PLL3P set to 208.8MHz for MCU sub-system
  - PLL3Q set to 24.57MHz for 48kHz SAI/SPI2S
  - PLL3R set to 11.29MHz for 44.1kHz SAI/SPI2S
  - PLL4P set to 99MHz for SDMMC and SPDIFRX
  - PLL4Q set to 74.25MHz for EVAL board

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-09 07:50:57 -05:00
Patrick Delaunay
8d6310aa0b clk: stm32mp1: add debug information
Add support of clk dump command and
display information during probe (under CONFIG_DISPLAY_CPUINFO).

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-09 07:50:57 -05:00
Patrick Delaunay
f3a23c2609 clk: stm32mp1: recalculate counter when switching freq
Because stgen is initialized with HSI clock, we need to
recalculate the counter when changing frequency.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-09 07:50:56 -05:00
Patrick Delaunay
63201281e5 clk: stm32mp1: correct access to RCC_OCENSETR/RCC_OCENCLRR
Remove unnecessary setbits on set/clear registers.
Avoid to deactivate HSI with HSE.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-09 07:50:56 -05:00
Patrick Delaunay
d661f61847 clk: stm32mp1: add IPCC clock
Add support for enable/disable of IPCC clock using AHB3 registers

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-09 07:50:56 -05:00
Patrick Delaunay
86617dd140 clk: stm32mp1: no more get ck_usbo_48m in device tree
Remove support of ck_usbo_48m clock node in device tree,
but force 48MHz frequency to prepare alignment
with kernel device tree.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-09 07:50:55 -05:00
Vabhav Sharma
ba8ba69b66 drivers: serial: dm: Enable DM_FLAG_PRE_RELOC in SBSA pl011 uart driver
The DM_FLAG_PRE_RELOC shall be enabled in SBSA PL011 uart driver
as this driver is used in NXP based SoCs

It is necessary to have Serial console running before relocation

The !CONFIG_IS_ENABLED(OF_CONTROL) [*] check is set as "workaround"
for DM problem : 4687919684

This flag is set if board does not support device-tree and using
platform data, In DM Model either of device tree or platform data
can be used to fetch device configuration

It is possible to use SBSA UART with CONFIG_DM_SERIAL but witout
corresponding device tree description (OF_CONTROL)

Other board/SoCs have this flag set unconditionally

Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
2019-02-09 07:50:55 -05:00
Roman Kapl
9dfdbd9f0c hashtable: fix environment variable corruption
Only first previously deleted entry was recognized, leading hsearch_r
to think that there was no previously deleted entry. It then conluded
that a free entry was found, even if there were no free entries and it
overwrote a random entry.

This patch makes sure all deleted or free entries are always found and
also introduces constants for the 0 and -1 numbers. Unit tests to excersise a
simple hash table usage and catch the corruption were added.

To trash your environment, simply run this loop:

setenv i 0
while true; do
    setenv v_$i $i
    setenv v_$i
    setexpr i $i + 1
done

Signed-off-by: Roman Kapl <rka@sysgo.com>
2019-02-09 07:50:54 -05:00
Chris Packham
4d9dbb1fbb moveconfig: add a second pass for empty #if/#endif blocks
Moveconfig already attempts to remove empty #if/#endif blocks when there
is a matching CONFIG_ being moved. Add a second pass which covers files
without a match.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
2019-02-09 07:50:54 -05:00
Chris Packham
36fddec14b omap3_cairo: remove empty #ifdef/#endif block
The content between these guards was removed in commit 9baa2bce28
("Removed unused references to CONFIG_SERIALx"). Remove the now
empty #ifdef/#endif block and the accompanying comment.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
2019-02-09 07:50:54 -05:00
Heinrich Schuchardt
2dd0111adc test: provide unit test for memory functions
Memory functions may have architecture specific implementations. These
should be tested.

Provide unit tests for memset(), memcpy(), memmove().

Provide a 'ut lib' sub-command to execute the tests.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-09 07:50:53 -05:00
Andrew F. Davis
eca61ae70c doc: ti-secure: Add ULO info for AM57xx/DRA7xx secure devices from TI
Booting from UART and USB on HS devices is now supported for this
platform. Update documentation for the same.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-02-09 07:50:53 -05:00
Andrew F. Davis
995985c1fc defconfigs: Add config for AM57xx High Security EVM with USB/UART Boot support
Add a new defconfig file for the AM57xx High Security EVM. This config
is specific for the case of USB/UART booting.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-02-09 07:50:53 -05:00
Andrew F. Davis
83ae647512 defconfigs: Add config for DRA7xx High Security EVM with USB Boot support
Add a new defconfig file for the DRA7xx High Security EVM. This config
is specific for the case of USB booting.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-02-09 07:50:52 -05:00
Andrew F. Davis
f5ca1cf79b defconfigs: am57xx_hs_evm: Sync HS and non-HS defconfigs
Additions have been made to the non-HS defconfig without the same
being made to the HS defconfig, sync them.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2019-02-09 07:50:52 -05:00
Andrew F. Davis
d8d250673d defconfigs: dra7xx_hs_evm: Sync HS and non-HS defconfigs
Additions have been made to the non-HS defconfig without the same
being made to the HS defconfig, sync them.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2019-02-09 07:50:52 -05:00
Philippe Reynes
23463faa13 bcm968580: enable watchdog and reboot with watchdog
Enable watchdog and reboot with watchdog in the configuration.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-02-09 07:50:51 -05:00
Philippe Reynes
c62bc60f11 bcm968380gerg: enable watchdog and reboot with watchdog
Enable watchdog and reboot with watchdog in the configuration.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-02-09 07:50:51 -05:00
Philippe Reynes
8d6006f2ac dt: bcm6858: add watchdog
This commit add watchdog and sysreset watchdog
in the bcm6858 device tree.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-02-09 07:50:50 -05:00
Philippe Reynes
0900036561 dt: bcm6838: add watchdog
This commit add watchdog and sysreset watchdog
in the bcm6838 device tree.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-02-09 07:50:50 -05:00
Philippe Reynes
47b68d00a3 watchdog: bcm6345: allow to use this driver on arm bcm6858
This IP is also used on some arm SoC, so we allow to
use it on arm bcm6858 too.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-02-09 07:50:50 -05:00
Philippe Reynes
771ee9b6ed watchdog: bcm6345: switch to raw I/O functions
This driver is used on several big endian mips board.
So we could use raw I/O function instead of forcing
big endian access.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-02-09 07:50:50 -05:00
Marek Vasut
e531c6731b fs: ext4: Unmount FS in do_fs_type()
Unlike other generic FS accessors, fs_get_info() does not call fs_close()
at the end of it's operation. Thus, using fs_get_info() in do_fs_type()
without calling fs_close() causes potential memory leak by creating new
filesystem structures on each call of do_fs_type().

The test case to trigger this problem is as follows. It is required to
have ext4 filesystem on the first partition of the SDMMC device, since
ext4 requires stateful mount and causes memory allocation.
=> while true ; do mmc rescan ; fstype mmc 1 ; done
Eventually, the mounting of ext4 will fail due to malloc failures
and the filesystem will not be correctly detected.

This patch fixes the problem by adding the missing fs_close().

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
2019-02-09 11:08:40 +01:00
Marek Vasut
6892550c4a mmc: Do not poll using CMD13 when changing timing
When using CMD6 to switch eMMC card timing from HS200/HS400 to HS/legacy,
do not poll for the completion status using CMD13, but rather wait 50mS.

Once the card receives the CMD6 and starts executing it, the bus is in
undefined state until both the card finishes executing the command and
until the controller switches the bus to matching timing configuration.
During this time, it is not possible to transport any commands or data
across the bus, which includes the CMD13.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
2019-02-09 11:08:40 +01:00
Marek Vasut
cbbe69483e mmc: tmio: renesas: Add 1uS delay after DMA completion on older IPs
The internal DMAC asserts DMA transfer end bit too early on older
version of the TMIO IPs which use bit 17 for DTRAEND. Add 1uS
delay after the completion of DMA transfer and before invalidating
the cache to let the DMAC fully complete the transfer. Otherwise,
it could happen that the last few bytes of a transferred data are
not available.

A test case to trigger this behavior is the following command, ran
on the U-Boot command line, with Sandisk 16 GiB UHS-I card inserted
into SDHI slot 0 and with first partition being of type FAT:
=> while true ; do mmc rescan ; fstype mmc 0:1 ; done

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-02-09 11:08:40 +01:00
Marek Vasut
992bcf4f27 mmc: tmio: Make DMA transfer end bit configurable
Different versions of the SDHI core use either bit 17 or bit 20 for the
DTRAEND indication, which can differ even between SoC revisions. Make
the DTRAEND bit position part of the driver private data, so that the
probe function can set this accordingly. Set this to 20 on Socionext
SoCs and either 17 or 20 on Renesas SoCs, depending on the SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-02-09 11:08:40 +01:00
Shawn Guo
6a7b406aa8 fdt: support booting with dtb in Android image
Some platforms choose to store device tree blob in Android image second
area.  Let's try to look for dtb from there when booting an Android
image, and use it for booting if found.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2019-02-08 19:18:23 -05:00
Michal Simek
a93eb577b9 dm: core: Add tests for dev_read_alias_highest_id()
It is checking the highest alias ID for eth, gpio, pci, i2c and error
code on non existing alias.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-08 06:25:49 +01:00
Michal Simek
83e4c7e9ff dm: core: Introduce dev_read_alias_highest_id()
It is wrapper for calling of_alias_get_highest_id() when live tree is
enabled and fdtdec_get_alias_highest_id() if not.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-08 06:25:32 +01:00
Michal Simek
003c9dc891 fdt: Introduce fdtdec_get_alias_highest_id()
Find out the highest alias ID used for certain subsystem.
This call will be used for alocating IDs for i2c buses which are not
described in DT.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-08 06:25:15 +01:00
Michal Simek
5ebc7c7e27 dm: core: Add of_alias_get_highest_id()
The same functionality was added to Linux for i2c bus registration with this
commit message:

"
of: base: add function to get highest id of an alias stem

I2C supports adding adapters using either a dynamic or fixed id. The
latter is provided by aliases in the DT case. To prevent id collisions
of those two types, install this function which gives us the highest
fixed id, so we can then let the dynamically created ones come after
this highest number.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
"

Add it also to U-Boot for DM I2C support.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-08 06:24:57 +01:00
Tom Rini
97276a91db Prepare v2019.04-rc1
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-02-07 21:32:19 -05:00
Tom Rini
7ae2729401 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2019-02-07 14:53:03 -05:00
Tom Rini
50e24381c0 Merge branch 'master' of git://git.denx.de/u-boot-spi
- SPI-NOR support
2019-02-07 14:48:56 -05:00
Vignesh R
4d40e009c0 MAINTAINERS: Add an entry for SPI NOR
Add myself as co-maintainer for U-Boot SPI NOR subsystem.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
[jagan: drop mtd/spi file from SPI entry]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-02-07 15:36:00 +05:30
Vignesh R
6d82517836 configs: Don't use SPI_FLASH_BAR as default
Now that new SPI NOR layer uses stateless 4 byte opcodes by default,
don't enable SPI_FLASH_BAR. For SPI controllers that cannot support
4-byte addressing, (stm32_qspi.c, fsl_qspi.c, mtk_qspi.c, ich.c,
renesas_rpc_spi.c) add an imply clause to enable SPI_FLASH_BAR so as to
not break functionality.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:22 +05:30
Vignesh R
75b2ec2a22 configs: Remove SF_DUAL_FLASH
SF_DUAL_FLASH claims to enable support for SF_DUAL_STACKED_FLASH and
SF_DUAL_PARALLEL_FLASH. But, in current U-Boot code, grepping for above
enums yield no user and therefore support seems to be incomplete. Remove
these configs so as to avoid confusion.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
7287597870 spl: Kconfig: Enable SPI_FLASH_TINY by default for SPL
SPL only needs to be able to read from SPI Flash to load next stage and
does not really need write/erase etc. Therefore in order to reduce SPI
Flash code size in SPL, enable SPI_FLASH_TINY, that only supports
reading from SPI flash, as default.

Note: Since, SPI_FLASH_TINY does not support SPI_FLASH_BAR,
SPI_FLASH_TINY is not enabled for boards with SPI controllers that
cannot support 4 byte addressing.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
778572d7cb mtd: spi: Add lightweight SPI flash stack for SPL
Add a tiny SPI flash stack that just supports reading data/images from
SPI flash. This is useful for boards that have SPL size constraints and
would need to use SPI flash framework just to read images/data from
flash. There is approximately 1.5 to 2KB savings with this.

Based on prior work of reducing spi flash id table by
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
5b66fdb29d mtd: spi: Remove unused files
spi_flash and spi_flash_ids are no longer needed after SPI NOR
migration. Remove them.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
c4e8862308 mtd: spi: Switch to new SPI NOR framework
Switch spi_flash_* interfaces to call into new SPI NOR framework via MTD
layer. Fix up sf_dataflash to work in legacy way. And update sandbox to
use new interfaces/definitions

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
2ee6705be0 mtd: spi: sf_probe: Add "jedec, spi-nor" compatible string
Linux uses "jedec,spi-nor" as compatible string for JEDEC compatible
SPI Flash device nodes. Therefore make U-Boot also to look for the same
compatible string so that we can use Linux DTS files as is.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
8c927809ea mtd: spi: spi-nor-core: Add back U-Boot specific features
For legacy reasons, we will have to keep around U-Boot specific
SPI_FLASH_BAR and SPI_TX_BYTE. Add them back to the new framework

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
0c6f187cdb mtd: spi: spi-nor-core: Add SFDP support
Sync Serial Flash Discoverable Parameters (SFDP) parsing support from
Linux. This allows auto detection and configuration of Flash parameters.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
61059bc55a mtd: spi: spi-nor-core: Add 4 Byte addressing support
Sync changes from Linux SPI NOR framework to add 4 byte addressing
support. This is required in order to support flashes like MT35x
that no longer support legacy Bank Address Register(BAR) way of accessing
>16MB region.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
492e65b29b mtd: spi: spi-nor-core: Add SPI MEM support
Many SPI controllers have special MMIO interfaces which provide
accelerated read/write access but require knowledge of flash parameters
to make use of it. Recent spi-mem layer provides a way to support such
controllers.
Therefore, add spi-mem support to spi-nor-core as a way to support SPI
controllers with MMIO interface. SPI MEM layer takes care of translating
spi_mem_ops to spi_xfer()s in case of legacy SPI controllers.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
7aeedac015 mtd: spi: Port SPI NOR framework from Linux
Current U-Boot SPI NOR support (sf layer) is quite outdated as it does not
support 4 byte addressing opcodes, SFDP table parsing and different types of
quad mode enable sequences. Many newer flashes no longer support BANK
registers used by sf layer to a access >16MB of flash address space.
So, sync SPI NOR framework from Linux v4.19 that supports all the
above features. Start with basic sync up that brings in basic framework
subsequent commits will bring in more features.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
ce13c19f4c sh: bitops: add hweight*() macros
Add hweight*() macros required for moving to new SF layer

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-02-07 15:33:21 +05:30
Vignesh R
6430eea639 spi: Add non DM version of SPI_MEM
Add non DM version of SPI_MEM to support easy migration to new SPI NOR
framework. This can be removed once DM_SPI conversion is complete.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
76094485e4 spi: spi-mem: Claim SPI bus before spi mem access
It is necessary to call spi_claim_bus() before starting any SPI
transactions and this restriction would also apply when calling spi-mem
operations. Therefore claim and release bus before requesting transfer
via exec_op.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
12563f768e spi: spi-mem: Extend spi_mem_adjust_op_size() to honor max xfer size
Extend spi_mem_adjust_op_size() to take spi->max_write_size and
spi->max_read_size into account.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
6d373e523f spi: spi-mem: Allow use of spi_mem_exec_op for all SPI modes
SPI controllers support all types of SPI modes including dual/quad bus
widths. Therefore remove constraint wrt SPI mode from spi-mem layer.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
e519c61606 bitops: Fix GENMASK definition for Sandbox
In arch/sandbox/include/asm/types.h we have
Therefore for 32 bit Sandbox build BITS_PER_LONG turns out to be 32 as
CONFIG_PHYS64 is not set

This messes up the current logic of GENMASK macro due to mismatch b/w
size of unsigned long (64 bit) and that of BITS_PER_LONG.
Fix this by using CONFIG_SANDBOX_BITS_PER_LONG which is set to 64/32
based on the host machine on which its being compiled.

Without this patch:
GENMASK(14,0) => 0x7fffffffffff
After this patch:
GENMASK(14,0) => 0x7fff

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-07 15:33:21 +05:30
Vignesh R
ea4805d6b2 configs: Move CONFIG_SPI_FLASH into defconfigs
Completely move CONFIG_SPI_FLASH from remaining board header files to
defconfigs

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Hannes Schmelzer
4dfe43849a arm: dts: am33xx: introduce 'am33xx-u-boot.dtsi'
commit fdce9d35dc ("arm: dts: am33xx: Sync dts with Linux 4.20.0")
did remove the "u-boot,dm-spl" flag from the 'ocp' bus which was
introduced with
commit 19aa4ac09d ("dts: am33xx: add u-boot, dm-spl to ocp bus")

Due to this all boards having CONFIG_SPL_OF_CONTROL enabled are broken
because they cannot bind/probe the boot-media interface during SPL
stage.

This commit introduces the 'am33xx-u-boot.dtsi' which is included with
the auto include mechanism. The am33xx-u-boot-dtsi adds the important
"u-boot,dm-pre-reloc" to the 'ocp bus' (the root bus of almost all
peripherals, at least the bootable ones).

The peripherials (mmc, spi, ...) needed during SPL stage need to be
equipped with the 'u-boot,dm-pre-reloc' in their responsible dts file.

Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
2019-02-06 14:07:23 -05:00
Eugen Hristev
413ca72022 MAINTAINERS: update u-boot-atmel tree
Update Atmel AT91 maintainership

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2019-02-05 12:31:19 -05:00
York Sun
44c21e94de MAINTAINERS: Change fsl-qoriq, mpc85xx, mpc86xx maintainers
Change maintainers to Prabhakar Kushwaha for fsl-qoriq, mpc85xx
and mpc86xx.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-05 12:31:19 -05:00
Tom Rini
bdac5e18a8 Merge git://git.denx.de/u-boot-marvell
- Move Armada XP / 38x PCIe driver to DM_PCI from me
- Move Armada XP / 38x LCD driver to DM_VIDEO from me
- Add uDPU board (Armada-3720) from Vladimir

[trini: Fix warning in pci-uclass.c by removing ret from
	pci_uclass_child_post_bind as it no longer calls functions with
        a return code to catch.]
Signed-off-by: Tom Rini <trini@konsulko.com>II
2019-02-05 12:29:59 -05:00
Tom Rini
c0bf3968d7 Merge tag 'for-master-20190205' of git://git.denx.de/u-boot-rockchip
Removes artifacts (.rej-files) from the last merge.
2019-02-05 08:32:52 -05:00
Stefan Roese
f182209190 arm: mvebu: theadorable: Enable video / LCD support with the new DM driver
With the new DM_VIDEO support in the Armada XP LCD driver, this patch
adds the needed DT node for the LCD controller to the theadorable dts
file. This DT property is not added to the Armada XP dtsi files, as this
LCD feature is pretty unusual for this SoC and I personally know of no
other board that uses this controller.

This patch also enables CONFIG_BMP_16BPP/24BPP/32BPP, as the "old" bmp
command supported these BMP files.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
2019-02-05 14:23:27 +01:00
Stefan Roese
6d9a98c583 video: Armada XP: Move driver to DM_VIDEO
This patch moves the Armada XP video / LCD driver to DM_VIDEO. With this
move, the legacy interface board_video_init() is removed from the
theadorable board code (only user of this video driver). The support
via DT will be added in a separate patch.

This patch also enables DM_VIDEO for the theadorable board, as this is
needed to not break git bisect'ability.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
2019-02-05 14:23:21 +01:00
Vladimir Vid
32c9e1c269 arm64: mvebu: Add basic support for uDPU board
This adds initial support for micro-DPU (uDPU) board which is based on Armada-3720 SoC.
micro-DPU is the single-port FTTdp "distribution point unit" made by Methode Electronics
which offers complete modularity with replaceable SFP modules both for uplink and downlink
(G.hn over twisted-pair, G.hn over coax, 1G and 2.5G Ethernet over Cat-5e cable).

On-board features:
- 512 MiB DDR3
- 2 x 2.5G SFP via HSGMII SERDES interface to the A3720 SoC
- USB 2.0 Type-C connector
- 4GB eMMC
- ETSI TS 101548 reverse powering via twisted pair (RJ45) or coax (F Type)

Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Luis Torres <luis.torres@methode.com>
Cc: Scott Roberts <scott.roberts@telus.com>
Cc: Paul Arola <paul.arola@telus.com>
Signed-off-by: Vladimir Vid <vladimir.vid@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-02-05 14:23:06 +01:00
Stefan Roese
9b276e90d6 arm: mvebu: armada-xp-theadorable.dts: Enable PCIe DT nodes
Now that the PCIe driver supports DM and DT parsing, enable the PCIe DT
nodes that are used by this board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Marek Behún <marek.behun@nic.cz>
Cc: VlaoMao <vlaomao@gmail.com>
2019-02-05 14:22:56 +01:00
Stefan Roese
6f139becf6 arm: mvebu: armada-xp/37x.dtsi: Sync PCIe DT nodes with Linux v4.20
This patch sync's the PCIe DT nodes with the recent Linux v4.20 version.
This change makes it easier to reference specific PCIe nodes in the
board dts files to e.g. enable a PCIe port as this is now necessary with
the new DM PCI driver for these platforms.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Marek Behún <marek.behun@nic.cz>
Cc: VlaoMao <vlaomao@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
2019-02-05 14:22:49 +01:00
Stefan Roese
94f453ea38 pci: pci_mvebu: Add DM_PCI support and move CONFIG_PCI_MVEBU to defconfig
This patch adds DM_PCI support to the MVEBU PCIe driver. This is
necessary, since all PCI drivers have to be moved to DM (driver model)
until the v2019.07 release.

To not break git bisect'ablility, this patch also moves CONFIG_PCI_MVEBU
from config headers to the defconfig files.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Marek Behún <marek.behun@nic.cz>
Cc: VlaoMao <vlaomao@gmail.com>
2019-02-05 14:22:38 +01:00
Stefan Roese
b52142004f pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr
This function will be used by the Marvell Armada XP/38x PCIe driver,
which is moved to DM right now. So let's extract the functionality
from pci_uclass_child_post_bind() to make it available.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-05 14:22:24 +01:00
Michal Simek
30477f0500 rockchip: Remove rejected files with .rej suffix
Probably output of incorrect applying introduced by

"rockchip: defconfig: Clean the unused pinctrl config"
(sha1: 2ec3d25f8f)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-05 10:34:04 +01:00
Tom Rini
e5fd39c886 Merge tag 'for-master-20190201' of git://git.denx.de/u-boot-rockchip
u-boot-rockchip changes for 2019.04-rc1:
  * support for Chromebook Bob
  * full pinctrl driver using DTS properties
  * documentation improvements
  * I2S support for some Rockchip SoCs
2019-02-02 10:11:20 -05:00
Tom Rini
544d5e98f3 Merge tag 'mips-pull-2019-02-01' of git://git.denx.de/u-boot-mips
- MIPS: mscc: jr2: small fixes
- MIPS: mscc: luton: add ethernet and switch driver
- MIPS: mt76xx: fix timer frequency
2019-02-02 10:11:12 -05:00
Tom Rini
1b0769f2ed Merge branch '2019-02-01-master-imports'
- Various TI platforms have been updated and DTS files re-synced and
  options disabled if not used or migrated to the DM versions
- Improvements to the dumpimage tool
- Rename SPL FAT/EXT filesystem support symbols for consistency and then
  allow them to be used to save more space in SPL.
- More lmb fixes
- Partial migration of CONFIG_BUILD_TARGET
2019-02-02 10:08:50 -05:00
Chris Packham
d5512a32f6 Kconfig: set default BUILD_TARGET for kirkwood
Now that BUILD_TARGET is in Kconfig we can define a default for boards
using the Kirkwood SoC.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
2019-02-02 08:23:57 -05:00
Jagan Teki
dc146ca111 Kconfig: Migrate CONFIG_BUILD_TARGET
Migrate CONFIG_BUILD_TARGET into Kconfig.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-02-02 08:23:57 -05:00
Simon Goldschmidt
dc57be51e9 test: lib: lmb: add lmb test for multiple RAM banks
This adds one test case that checks that allocation with multiple
DRAM banks works correctly.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-02 08:23:33 -05:00
Simon Goldschmidt
9cc2323fee lmb: handle more than one DRAM BANK
This fixes the automatic lmb initialization and reservation for boards
with more than one DRAM bank.

This fixes the CVE-2018-18439 and -18440 fixes that only allowed to load
files into the firs DRAM bank from fs and via tftp.

Found-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-02 08:19:17 -05:00
Martyn Welch
e3b4fc9598 tools: dumpimage: Clarify help
Help message isn't clear over the use of the "-T" option (it's to declare
the type of image that the tool is operating on), which also is optional
as it defaults to the default image type. It's also missing a description
of the "-o" option, so add it.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
2019-02-01 14:13:46 -05:00
Martyn Welch
65a80b43b3 tools: dumpimage: Add help option and make error paths consistent
The utility dumpimage has error paths that display the usage and others
that exit without displaying usage. Add an explicit help option to
dumpimage to display the usage and remove it's use in error paths to make
the error messages more obvious and errors paths more consistent.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
2019-02-01 14:13:46 -05:00
Martyn Welch
11e3c1fd3b tools: dumpimage: Simplify internal logic
There are 3 supported modes of operation:

1) Show version
2) List image contents
3) Extract image component

Option (1) terminates early, so only options (2) and (3) remain. Remove
redundant check for these modes.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
2019-02-01 14:13:46 -05:00
Martyn Welch
12b831879a tools: dumpimage: Simplify arguments
The dump image utility has very confusing syntax. If called to list image
contents ("-l") it takes the image name as a positional argument. If the
utility is called to extract something from the image, the image must be
provided via the optional argument "-i" as well as the positional argument
but the value passed in the positional argument will be completely
ignored.

Simplify dumpimage by always providing the image as the first positional
argument. Assume we want to dump something from the image if we do not
provide the "-l" option for now.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
2019-02-01 14:13:46 -05:00
Martyn Welch
57a608e969 tools: dumpimage: Provide more feedback on error
The dumpimage utility errors out in a number of places without providing
sufficient feedback to allow the user to easily determine what they have
done wrong. Add addtional error messages to make the cause of the failure
more obvious.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
2019-02-01 14:13:45 -05:00
Adam Ford
3c29a56736 regulator: pbias: Handle extended drain IO when changing omap36 PBIAS
The OMAP36 and DM37 TRM state to disable extneded drain IO before
changing the PBIAS.  This patch does this before pmic writes if
the CONFIG_MMC_OMAP36XX_PINS flag is set and the cpu family is
omap36xx

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-02-01 14:13:45 -05:00
Philipp Tomsich
73ced87e9a rockchip: rk3399: spl: ensure that debug_uart_init is called
With the latest changes to add support for the Chromebook Bob,
initialisation through debug_uart_init() did no longer get called for
other targets.

Fix this, by moving debug_uart_init() out of the Bob-specific

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:14 +01:00
Philipp Tomsich
c869d63f27 rockchip: rk3399-puma: enable SPL_ATF_NO_PLATFORM_PARAM
As we're working on the next update of our ATF (and U-Boot and the ATF
are out-of-sync), let's temporarily enable SPL_ATF_NO_PLATFORM_PARAM to
reduce compatibility issues.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:14 +01:00
Philipp Tomsich
5a127325f0 pinctrl: Kconfig: fix missing include of rockchip/Kconfig
After the merge of the new, generic pinctrl-code, the include for
rockchip/Kconfig was missing.  Add it here, so we can select the
pinctrl-driver for SPL.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:14 +01:00
Philipp Tomsich
efc4677171 pinctrl: Kconfig: sort includes alphabetically
To make adding new subdirectories easier, let's enforce alphabetical
ordering of the includes of Kconfig files in the respective
subdirectories.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:14 +01:00
Philipp Tomsich
77871e69cf rockchip: Add MAINTAINER entry for chromebook_speedy
This adds a MAINTAINER entry for chromebook_speedy.

Without this, we get the following warnings from the maintainers
check:
    WARNING: no status info for 'chromebook_minnie'
    WARNING: no maintainers for 'chromebook_minnie'

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:14 +01:00
Simon Glass
9e92116bc8 rockchip: Add support for chromebook_bob
Bob is a 10-inch chromebook produced by Asus. It has two USB 3.0 type-C
ports, 4GB of SDRAM, WiFi and a 1280x800 display. It uses its USB ports
for both power and external display. It includes a Chrome OS EC
(Cortex-M3) to provide access to the keyboard and battery functions.

Support so far includes only:
- UART
- SDRAM
- MMC, SD card
- Cros EC (but not keyboard)

Not included:
- Keyboard
- Display
- Sound
- USB
- TPM

Bob is quite similar to Kevin, the Samsung Chromebook Plus, but support
for this is not provided in this series.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:13 +01:00
Simon Glass
08c85b57a5 rockchip: gru: Add extra device-tree settings
Add some U-Boot-specific settings. These should really go in the
*u-boot.dtsi file, but it seems that rk3399 does not use that yet.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:13 +01:00
Simon Glass
aa48c94ca8 rockchip: Implement spl_gpio in the GPIO driver
Allow rockchip boards to use GPIOs before driver model is ready. This is
really only useful for setting GPIOs to enable the early debug console, if
needed on some platforms.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:13 +01:00
Simon Glass
3ec6f11c7d rockchip: Move pull-up/down enum into a common file
At present this enum is only available to rk3288. Move it so that other
rockchip SoCs can access it. It is needed for the SPL GPIO driver for
rk3999 in a later patch.

Also adjust the enum name to lower case.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:13 +01:00
Simon Glass
8a0c6aa33f rockchip: rk3399: Add ROCKCHIP_DEVICE_SETTINGS to set env
Some boards use different stdio environment variables from the default.
Provide a #define for this which can be set before including the header
file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:13 +01:00
Simon Glass
c35f8e5017 rockchip: Tidy up board include-file ordering
These board files have inconsistent #include ordering. Fix them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:13 +01:00
Simon Glass
5328af1774 rockchip: clk: Add mention of four new clocks
These clocks are needed to get MMC running. We don't actually support
setting them yet.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:13 +01:00
Simon Glass
cf5c8d1880 rockchip: Add settings for Samsung LPDDR3 4GB SDRAM 1866MHz
This memory is used on Bob. Add settings for this, taken from coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:13 +01:00
Simon Glass
3523c07867 rockchip: Allow booting from SPI
The u-boot,spl-boot-device property only allows MMC at present. Add SPI as
well for boards that boot from SPI flash.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:13 +01:00
Simon Glass
6cecc2b556 rockchip: Clarify docs on SPI writing
We use every second block when creating a SPI image, so update the text to
say this explicitly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:12 +01:00
Simon Glass
60853a9b5c rockchip: evb_rk3399: Tidy up the README
Add mention of a prerequisite needed to build the image. Also adjust the
English wording in a few places.

Ideally this should move to using binman to produce images, and avoid the
manual steps.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:12 +01:00
Simon Glass
0a09f2f117 rockchip: Adjust rk3399 device tree to be closer to linux
This file has changed upstream, with some additions and changes. Move the
U-Boot version towards this.

Some USB changes seem to be incompatible with how the bindings work on
rockchip in U-Boot. Testing is needed to make sure that USB still works
correct, and adjust the code (not device tree) if not.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:12 +01:00
Simon Glass
d244474f38 rockchip: Bring in device tree files for rk3399-gru
Bring in these files from Linux v4.20.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:12 +01:00
Simon Glass
0c14c36605 rockchip: Drop note about supporting other SoCs
Quite a wide range of Rockchip SoCs are supported in mainline U-Boot now,
so drop the comment about needing to add more.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:12 +01:00
Simon Glass
16217f965d rockchip: Add mention of other boards
At present some Rockchip SoCs and boards are not mentioned in the README.
So that people can see which SoCs are supported, expand the list to
include everything.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:12 +01:00
Simon Glass
5c01d1c0d0 gpio: Add a simple GPIO API for SPL
In space-constrained environments or before driver model is available, it
is sometimes necessary to set GPIO values. Add an SPL API for this, to
allow early board code to change GPIOs. The caller must provide the
register address, so that the drivers can be fairly generic.

This API can be implemented by GPIO drivers, behind a suitable guard,
like #ifdef CONFIG_SPL_BUILD.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:12 +01:00
Simon Glass
66f657d15b gpio: Use more command-specific enums values
At present this file uses GPIO_OUTPUT and GPIO_INPUT as its sub-command
values. These are pretty generic names. Add a 'C' suffix to avoid possible
conflicts.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:12 +01:00
Simon Glass
6831616063 clk: Improve debug message in clk_set_default_rates()
It is helpful to print the clock number as well as the index, so that this
can be looked up in the binding file. Update the debug() statement to do
this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:12 +01:00
Simon Glass
f60662de77 lib: Allow using display_buffer() in SPL
At present this function uses printf() format strings that are not
supported in SPL, so the output just consists of %llx strings on 64-bit.
machines. Fix this by adding a special case.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:11 +01:00
David Wu
e5b29d870b ARM: dts: rk322x: Correct the uart2 default pin configuration
To match the iomux setting of uart2 at SPL, correct the uart2
default pin configuration, if not changed, the evb-rk3229 can't
output the log message.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:11 +01:00
David Wu
96f73e0d24 pinctrl: rockchip: Clean the unused rockchip pinctrl drivers
If we used the pinctrl-rockchip driver, these code is not needed,
so remove them.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:11 +01:00
David Wu
2ec3d25f8f rockchip: defconfig: Clean the unused pinctrl config
If we used the pinctrl-rockchip driver, these config is not needed,
so remove them.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:11 +01:00
David Wu
e7ae4cf27a pinctrl: rockchip: Add common rockchip pinctrl driver
Use this driver to fit all Rockchip SOCs and to support
the desired pinctrl configuration via DTS.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:11 +01:00
David Wu
2409e47b3f rk3288: chrome: defconfig: Enable FDT for new pinctrl driver
The FDT is requested for new pinctrl driver, disable SPL_OF_PLATDATA
and enable SPL_OF_LIBFDT to make FDT be built in.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:11 +01:00
David Wu
08c817c399 ARM: rockchip: Remove the pinctrl request at rk3288-board-spl
If we use the new pinctrl driver, the pinctrl setup will be done
by device probe. Remove the pinctrl setup at rk3288-board-spl.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:11 +01:00
David Wu
bfb11abef2 ARM: rockchip: Kconfig: Remove the SPL_PINCTRL for rk3188
It seems that pinctrl is not requested for rk3188 SPL, remove it so
that can save more space for SPL image size.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:11 +01:00
David Wu
c0b163e908 ARM: rockchip: rk3188: Remove the pinctrl setup and enable uart at SPL
When the boot ROM sets up MMC we don't need to do it again. Remove the
MMC setup code entirely, but we also need to enable uart for debug message.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:11 +01:00
David Wu
cb5950788c rockchip: rk3399-evb: defconfig: Enable FDT for new pinctrl driver
The FDT is requested for new pinctrl driver, disable SPL_OF_PLATDATA
to make FDT be built in.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:10 +01:00
Marty E. Plummer
8e2e601c5f rockchip: add support for veyron-speedy (ASUS Chromebook C201)
This adds support for the ASUS C201, a RK3288-based clamshell
device. The device tree comes from linus's linux tree at
3f16503b7d2274ac8cbab11163047ac0b4c66cfe. The SDRAM parameters
are for 4GB Samsung LPDDR3, decoded from coreboot's
src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc

Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:10 +01:00
Mark Kettenis
09056c94a1 rockchip: dts: rk3399-firely: add 'same-as-spl'
Like on rk3399-puma we want to continue booting the fill U-Boot from
the same device as the SPL stage.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:10 +01:00
Simon Glass
0d968ceb1f rockchip: Drop call to rockchip_dnl_mode_check() for now
This function causes a 5-second delay and stops the display working on
minnie. This code should be in a driver and should only be enabled by
a device-tree property, so that it does not affect devices which do not
have this feature.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:10 +01:00
Simon Glass
2d0c01b8f0 sound: rockchip: Add sound support for jerry
Jerry uses a max98090 audio codec and the internal SoC I2S peripheral.
Enable sound support and add the required device-tree pieces.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:10 +01:00
Simon Glass
bcea0e1e81 rockchip: Add a sound driver
Add a sound driver for rk3288 supporting chromebook_jerry. This uses the
I2S driver, and existing audio codec and the clock/pinmux support.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:10 +01:00
Simon Glass
2665f09115 rockchip: Add an I2S driver
Add a driver for I2S which allows audio data to be sent from the SoC to
the audio codec. The sample rate and other settings are hard-coded for now
as there is no suitable device-tree binding available.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:10 +01:00
Simon Glass
3dbfe5ae61 rockchip: rk3288: Add i2s pinctrl and clock support
Add support for setting pinctrl and clock for I2S on rk3288. This allows
the sound driver to operate. These settings were created by rkmux.py

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:10 +01:00
Jean-Jacques Hiblot
341e5a2752 ARM: DTS: am43xx: Enable the DTS entries for USB port #2 in SPL
This is required to enable the USB port #2 in SPL when DM_USB is used.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-02-01 09:14:21 -05:00
Jean-Jacques Hiblot
64c59926ad ARM: DTS: am43xx: Add aliases for the USB ports
Although not required, it doesn't hurt to explicitly map the USB ports to
a USB controller. Without this, the port number will be derived from the
binding order of the peripheral devices.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-02-01 09:14:21 -05:00
Adam Ford
dd5b0e229b ARM: DTS: Resync am3517-evm.dts with Linux 5.0-rc3
The chosen node was added in the kernel.  This may come in handy
in the future, so resync with 5.0-rc3

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-02-01 09:14:21 -05:00
Adam Ford
13756ebb98 ARM: dts: da850-evm: Re-sync with Kernel 5.0
Resync with Kernel 5.0-rc3

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-02-01 09:14:21 -05:00
Adam Ford
c97ae7be80 ARM: am3517_evm: Enable DM_SPI and DM_USB
To comply with pending requirements, this sets the flags to
enable DM_SPI and DM_USB.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-02-01 09:14:21 -05:00
Tien Fong Chee
cafc429fa8 spl: fat/fs: Add control to build FS EXT4 in SPL
CONFIG_SPL_FS_EXT4 can be used to include/exclude the FS EXT4 from
SPL build. Excluding the FS EXT4 from SPL build can help to save 20KiB
memory.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-02-01 09:14:21 -05:00
Tien Fong Chee
f4b4092474 spl: Kconfig: Replace CONFIG_SPL_EXT_SUPPORT to CONFIG_SPL_FS_EXT4
Replace CONFIG_SPL_EXT_SUPPORT to CONFIG_SPLY_FS_EXT4 so both
obj-$(CONFIG_$(SPL_)FS_EXT4) and CONFIG_IS_ENABLED(FS_EXT4) can be
used to control the build in both SPL and U-Boot.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-02-01 09:14:21 -05:00
Tien Fong Chee
d8c3ea9982 spl: fat/fs: Add option to include/exclude FAT write build in SPL
Most of the time SPL only needs very simple FAT reading, so having
CONFIG_IS_ENABLED(FAT_WRITE) to exclude it from SPL build would help
to save 64KiB default max clustersize from memory.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-02-01 09:12:48 -05:00
Tien Fong Chee
0c3a9ed409 spl: Kconfig: Replace CONFIG_SPL_FAT_SUPPORT with CONFIG_SPL_FS_FAT
Replace CONFIG_SPL_FAT_SUPPORT with CONFIG_SPL_FS_FAT so
obj-$(CONFIG_$(SPL_)FS_FAT) can be used to control the build in both
SPL and U-Boot.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-02-01 09:12:48 -05:00
Jean-Jacques Hiblot
0e036484db configs: removing am335x_evm_usbspl_defconfig
This feature is now supported by the main config for am335x_evm:
am335x_evm_defconfig

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-02-01 09:09:40 -05:00
Jean-Jacques Hiblot
94f0d13c9b configs: am335x_evm: enable DM_USB_GADGET and USB_ETHER in u-boot and SPL
The AM335x ROM boot is able to download the SPL from a RNDIS connection
on USB0. To enable a full RNDIS boot flow (romboot -> SPL -> u-boot -> ..),
we can use USB_ETHER in SPL and u-boot.
However this increase the size of the SPL past its limit. So removing the
unused SPL_EXT_SUPPORT.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-02-01 09:09:40 -05:00
Jean-Jacques Hiblot
db34e0ede0 ARM: DTS: am335x-evm: Use USB0 in peripheral mode
This USB port is mainly used for RNDIS and DFU. To be able to use it with
DM_USB and DM_USB_GADGET, we need to provide a dr_mode value in the DTS.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-02-01 09:09:40 -05:00
Jean-Jacques Hiblot
1c1464c2b1 usb: ether: call _usb_eth_halt() if initialization fails
If the host does not respond in time, the initialization fails. However
the usb ether driver will still be registered. This will make
usb_gadget_probe_driver() fail the next time the initialization is
attempted because it cannot find an available UDC.

Fixing this by calling _usb_eth_halt() when the init fails.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
2019-02-01 09:09:40 -05:00
Heiko Schocher
a36c70a36d am335x, shc: adapt shc board to DM
port the am335x based shc board to DM, to get rid
of DW warnings when compiling U-Boot.

- remove uneccessary board code
- adapt defconfigs
- remove unneeded defconfigs
  configs/am335x_shc_prompt_defconfig
  configs/am335x_shc_sdboot_prompt_defconfig

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-02-01 09:09:40 -05:00
Heiko Schocher
46c43714a9 ARM: dts: am335x-shc: add u-boot specific dtsi
add u-boot specific am335x-shc-u-boot.dtsi file,
in which we add u-boot specific adaptions.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-02-01 09:09:40 -05:00
Heiko Schocher
e535014580 arm: dts: add am335x-shc.dts for shc board
add DTS from linux tree commit
"47bfa6d9dc8c060bf56554a465c9031e286d2f80"

change for U-Boot:
switch to SPDX-license identifier.

Signed-off-by: Heiko Schocher <hs@denx.de>
2019-02-01 09:09:40 -05:00
Horatiu Vultur
364e407f3c configs: mscc_luton: Add network support.
Update default config to use network driver for Luton SoCs.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01 14:13:36 +01:00
Horatiu Vultur
c5620aeea4 net: Add MSCC Luton networkd driver.
Add network driver for Microsemi Ethernet switch, it is
present on Luton SoCs.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01 14:13:36 +01:00
Horatiu Vultur
ee7b65f2cc mips: mscc: luton: Add ethernet nodes for Luton.
Add nodes for pcb090 and pcb091. There is currently no support
in Linux for this SoC.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01 14:13:36 +01:00
Horatiu Vultur
0b8f34dc8c net: mscc: Remove unused variables
Remove unused variables in the struct ocelot_private and make
miim variable static.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01 14:13:36 +01:00
Horatiu Vultur
45f2748c50 net: mscc: Move mac_table_add function into different file.
Move the function mac_table_add into a different file,
so it can be reused.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01 14:13:36 +01:00
Horatiu Vultur
36d04f52ff net: mscc: Move ocelot_send and ocelot_recv in a different file.
This functions can be reused by other MSCC SoCs therefore,
make them more generic and move them in separate files.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01 14:13:36 +01:00
Horatiu Vultur
2fff4a9b59 net: mscc: Move miim commands into separate file.
Move miim functions that can be shared in a different file inside
mscc_eswitch.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01 14:13:36 +01:00
Horatiu Vultur
4c66157f42 net: mscc: Move ocelot_switch to mscc_eswitch folder
Move file ocelot_switch to mscc_eswitch to prepare to add
new net drivers for other MSCC SoCs.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01 14:13:36 +01:00
Stefan Roese
fdceb0d735 mips: mt76xx: Use correct timer frequency
Testing has shown that the timer on the MT7688 platforms does not run
correctly (too fast timeout). This patch changes
CONFIG_SYS_MIPS_TIMER_FREQ from 200MHz to 290MHz which is the correct
value, as its also used in Linux.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-02-01 14:12:36 +01:00
Horatiu Vultur
78b5431410 MSCC: Fix Jaguar2 board detection.
When power cycle the Jaguar2 boards, it couldn't read the
phys, therefore it always deduce that the board type is
pcb111.

Add a small delay after setting the gpio pins, fix the
issue.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01 14:09:31 +01:00
Horatiu Vultur
45988b123c MSCC: Jaguar2 enable debug uart
Enable debug uart for Jaguar2 SoC family.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01 14:08:54 +01:00
Tom Rini
db4a29993d Merge tag 'video-updates-for-2019.04-rc1' of git://git.denx.de/u-boot-video
- ihs and imx driver fixes
- relax EDID validation checks for 0 hsync/vsync
  pulse width (support some quirky displays)
2019-01-31 16:07:37 -05:00
Tom Rini
ab0ec15f77 Merge tag 'u-boot-amlogic-20190131' of git://git.denx.de/u-boot-amlogic
- Add features and fixups to support video on Amlogic GX SoCs
- Add video support for Amlogic GX SoC
- Add DT fixups
- Enable Video and USB Console for libretech-cc board
2019-01-31 07:19:52 -05:00
Maxime Jourdan
fce1069bfb arm: libretech-cc: enable video by default
libretech-cc being the main device tested with CONFIG_VIDEO_MESON, let's
enable it by default.

Also enable:
 - CONFIG_SYS_WHITE_ON_BLACK for prettiness
 - CONFIG_VIDEO_DT_SIMPLEFB for framebuffer sharing with kernel

Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-01-31 09:35:01 +01:00
Maxime Jourdan
01790b016e arm: meson64: enable console mux and console env by default
With the recent addition of the meson VPU driver, enable the following
config entries by default for meson-64 targets: CONFIG_CONSOLE_MUX,
CONFIG_SYS_CONSOLE_IS_IN_ENV.

This allows outputting the console via video if CONFIG_VIDEO_MESON is
selected.

Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-01-31 09:35:01 +01:00
Neil Armstrong
f0d090442b configs: meson64: use vidconsole and usbkbd if enabled
Allows displaying the console via video and using a USB keyboard.

Also enables CONFIG_SPLASH_SCREEN if using video.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-01-31 09:35:01 +01:00
Maxime Jourdan
0cc53faf59 arm: meson: board-gx: Setup VPU in fdt
If VIDEO_MESON is enabled, we need to setup the fdt for the framebuffer.

Call meson_vpu_rsv_fb() which reserves the framebuffer memory region for
EFI, and sets up simple-framebuffer nodes if simplefb support is
enabled.

Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-01-31 09:35:01 +01:00
Maxime Jourdan
2ebade0d57 arm64: dts: meson-gx: add hhi reg entry to hdmi_tx
There's no reliable way to reuse the hhi entry from the vpu as is done
in the linux kernel, so we duplicate it here.

We will be able to sync against kernel DTS in the future when the VPU
gets based on the clock framework rather than the HHI reg.

Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-01-31 09:35:01 +01:00
Neil Armstrong
bce59f918e arm64: dts: meson-gx: Add hdmi_5v regulator as hdmi tx supply
The hdmi_5v regulator must be enabled to provide power to the physical HDMI
PHY and enables the HDMI 5V presence loopback for the monitor.

Fixes: b409f625a6d5 ("ARM64: dts: meson-gx: Add HDMI_5V regulator on selected boards")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
[backport of linux commit e1f2163deac059ad39f07aba9e314ebe605d5a7a]
2019-01-31 09:35:01 +01:00
Maxime Jourdan
671b1db8f8 arm64: dts: meson-gx: vpu should be probed before relocation
Flag the appropriate nodes with u-boot,dm-pre-reloc

Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-01-31 09:35:01 +01:00
Neil Armstrong
3bed422094 video: Add Meson Video Processing Unit Driver
This adds video output support for Amlogic GXBB/GXL/GXM chips.
The supported ports are CVBS and HDMI (based on DW_HDMI).

When using HDMI, only DMT modes are supported.

There is support for simple-framebuffer (CONFIG_VIDEO_DT_SIMPLEFB)

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jorge Ramire-Ortiz <jramirez@baylibre.com>
Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
[narmstrong: fixed defines alignment in meson_canvas.c]
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-01-31 09:35:01 +01:00
Jorge Ramirez-Ortiz
56dd8d87e5 video: dw_hdmi: add support for color conversion
Some IPs like the meson VPU can only feed a particular pixel format to
dw_hdmi. As of now, the driver is hardcoded to use RGB888 as input.

This commit enables different pixel format inputs, with the appropriate
CSC configuration.

Signed-off-by: Jorge Ramire-Ortiz <jramirez@baylibre.com>
Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-01-31 09:35:01 +01:00
Jorge Ramirez-Ortiz
fd99841808 video: dw_hdmi: support SoC specific read/write ops
Some IPs like the meson VPU have a specific way to write to dw_hdmi
registers. Make it configurable.

Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
[added commit description]
Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-01-31 09:35:01 +01:00
Maxime Jourdan
335d287327 power: domain: meson-gx-pwrc-vpu: add missing depends
MESON_GX_VPU_POWER_DOMAIN should depend on POWER_DOMAIN.

Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-01-31 09:35:01 +01:00
Neil Armstrong
535d74a8ae MAINTAINERS: Add Amlogic entry
Add entry for Amlogic SoC maintained files and the freshly
created mailing-list.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-01-30 21:22:53 -05:00
Heinrich Schuchardt
1249fa8fc2 Makefile: remove generated font files
If `make mrproper` does not delete the generated drivers/video/fonts/*.S
files a following `make tests` fails.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-30 21:22:53 -05:00
Simon Goldschmidt
1f92c074cb dfu: mmc: call fs functions instead of run_command
This unbreaks dfu mmc_file_op which is currently broken since using the
load cmd on a buffer from heap is not allowed - added with
commit aa3c609e2b ("fs: prevent overwriting reserved memory")

Fixes: commit aa3c609e2b ("fs: prevent overwriting reserved memory")
Reported-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
2019-01-30 21:22:53 -05:00
Tom Rini
552452f80c Merge branch 'master' of git://git.denx.de/u-boot-sunxi
- Enable DM_MMC support
2019-01-30 12:24:32 -05:00
Jagan Teki
a7cca57937 arm: sunxi: Enable DM_MMC
Enable DM_MMC for all Allwinner SoCs, this will eventually
enable BLK.

Also removed DM_MMC enablement in few parts of sunxi
configurations.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2019-01-30 18:22:18 +05:30
Jagan Teki
cebeba9fdf sunxi: A64: pinebook-u-boot: Include sunxi-u-boot.dtsi
Like other Allwinner A64 boards, pinebook also need altering
auto-numbering of mmc2 to mmc1 which is available in common
sunxi dsti file, sunxi-u-boot.dtsi

Pinebook has a separate sun50i-a64-pinebook-u-boot.dtsi which
takes more precedence for u-boot.dtsi inclusion and it eventually
failed to include the sunxi-u-boot.dtsi.

So, this patch add support to include the sunxi-u-boot.dtsi in the
sun50i-a64-pinebook-u-boot.dtsi

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com> # Pinebook
2019-01-30 18:22:18 +05:30
Jagan Teki
708b5da38a arm: dts: sunxi: Alter mmc2 auto-numbering to mmc1
Environment and fastboot mmc devices are configured based on the number
of mmc slots defined on particular board configs, MMC_SUNXI_SLOT_EXTRA.

If MMC_SUNXI_SLOT_EXTRA is more than 1, the default env and fastboot
mmc devices is mmc1 by assuming mmc0 is SD and mmc1 is emmc device.

But with DM_MMC the mmc devices are numbered as per the dts node
enablement. If there is a chance of having enabling all mmc nodes
in dts say mmc0, mmc1, mmc2 then the default env and fastboot devices
will failed to assign proper emmc device since mmc2 is emmc in most
of the Allwinner platforms.

So, we need to alter the auto-numbering by aliasing mmc2 to mmc1 since
aliases take precedence over auto-numbering.

If the dts enables mmc0, mmc1, mmc2, then all the nodes will probe
sequentially and auto-numbered as it is. but when aliases mmc1 with mmc2
the resulting number should be that mmc0 is till mmc0, mmc2 become mmc1
and mmc2 become mmc1

Without aliases of mmc1 = &mmc2;
-------------------------------
MMC:   mmc@1c0f000: 0, mmc@1c10000: 1, mmc@1c11000: 2

With aliases of mmc1 = &mmc2;
----------------------------
MMC:   Device 'mmc@1c11000': seq 1 is in use by 'mmc@1c10000'
mmc@1c0f000: 0, mmc@1c10000: 2, mmc@1c11000: 1
Loading Environment from FAT... OK

Some platforms like A20 has mmc0...mmc3, but there is no usecases now
for enabling all mmc controllers in any of A20 board dts files.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-01-30 18:22:18 +05:30
Andre Przywara
13b0867dc3 sunxi: clk: enable clk and reset for CCU devices
Some Allwinner clock devices have parent clocks and reset gates itself,
which need to be activated for them to work.

Add some code to just assert all resets and enable all clocks given.
This should enable the A80 MMC config clock, which requires both to be
activated. The full CCU devices typically don't require resets, and have
just fixed clocks as their parents. Since we treat both as optional and
enabling fixed clocks is a NOP, this works for all cases, without the need
to differentiate between those clock types.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2019-01-30 18:21:35 +05:30
Tom Rini
748ad078ee Merge tag 'u-boot-imx-20190129' of git://git.denx.de/u-boot-imx
For 2019.04
2019-01-30 07:22:12 -05:00
Andre Przywara
4233698dd3 mmc: sunxi: Honour non-removable property in DT
If a board DT describes a cd-gpios property, but also marks the storage
as non-removable, we must ignore the GPIO (as Linux does).

Teach the DM_MMC part of the Allwinner MMC driver about the
non-removable DT property, to fix DM_MMC access on the SoPine and
Pine64-LTS board.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2019-01-29 23:49:41 +05:30
Andre Przywara
a7ae159978 sunxi: board: do MMC pinmux setup for DM_MMC builds
Enabling DM_MMC skips the call to mmc_pinmux_setup() in board.c, as this
is supposed to be handled by the MMC driver, using DT information.

However we don't have a pinctrl driver yet, but would still like to keep
the working pinmux setup for our MMC devices. So bring this particular
call back to the DM_MMC code flow.

When booting from either SD card or eMMC, the SPL does the setup for us,
but when booting from SPI or USB we must not skip this part.

Fixes, boot via FEL or SPI flash, where the SPL won't setup the pinmux

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jagan Teki <jagan@openedev.com>
[jagan: add Fix details on commit message]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-01-29 23:46:14 +05:30
Andre Przywara
c57572eb5a mmc: sunxi: Add DM clk and reset support
Now that we have the gate clocks and the reset gates in our new
Allwinner clock driver, let's make use of them in the MMC driver, when
DM_MMC is defined.
We treat the reset device as optional now, as the older SoCs don't
implement it.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-29 23:44:03 +05:30
Jagan Teki
3c8c7da6fc mmc: sunxi: Add DM_MMC support for A80
A80 gates clock already be part of CLK framework, so just
add mod_clk offset with A80 compatible string.

Cc: Rask Ingemann Lambertsen <rask@formelder.dk>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-01-29 23:41:57 +05:30
Jagan Teki
9e23338268 mmc: sunxi: Add DM_MMC support for H6
Unlike other Allwinner SoC's, H6 uses a different MMC mod clock offset.
Connect that with the respective compatible string.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2019-01-29 23:35:18 +05:30
Jagan Teki
a1925a64d5 mmc: sunxi: Add remaining compatible strings
Add MMC compatible strings for A83T, A64, H5.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2019-01-29 23:34:58 +05:30
Andre Przywara
e0c7ce7e52 sunxi: clk: A80: add MMC clock support
The A80 handles resets and clock gates for the MMC devices differently,
outside of the CCU IP block. Consequently we have a separate clock
device with a separate binding for that.

Implement that with the respective clock gates and resets to allow the
A80 taking part in the DM_MMC game.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[jagan: fix a80 mmc clock config compatible]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-29 23:33:08 +05:30
Andre Przywara
bb3e5aa289 sunxi: clk: add MMC gates/resets
Add the MMC clock gates and reset bits for all the Allwinner SoCs.
This allows them to be used by the MMC driver.

We don't advertise the mod clock yet, as this is still handled by the
MMC driver.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[jagan: add V3S, A80 gates/resets]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-29 23:30:11 +05:30
Jagan Teki
1659156c74 sunxi: amarula_a64_relic: Enable USB host
Enable USB host controllers for Amarula A64-Relic board,
the respective nodes are already present in DTS.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-01-29 23:27:00 +05:30
Patrick Delaunay
1b35c90836 arm: stm32mp1: deploy spl in root folder
Update generation of spl binaries
- continue to generate all SPL files in spl sub-directory
- copy in root folder the needed file for user (YOCTO, buildroot):
  u-boot-spl.stm32

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-01-29 09:41:37 -05:00
Tom Rini
5548c7a165 Merge tag 'u-boot-amlogic-20190129' of git://git.denx.de/u-boot-amlogic
Adds pinconf support for the Amlogic pinctrl driver (fixed)
2019-01-29 09:40:31 -05:00
Jerome Brunet
c4c726c26b pinctrl: meson: add pinconf support
Adding pinconf support is necessary to enable boot from SPI
without breaking the eMMC. When booting from SPI, the ROM code
leave pull downs on the eMMC pad.

We need to set pinconf provided in DT to solve this

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[narmstrong: added missing comma in pinctrl-meson-axg-pmx.c]
2019-01-29 11:19:15 +01:00
Mario Six
6df07d854b ihs_video_out: Fix error handling
The ihs_video_out driver's error handling is incorrect in two places
(one is a missing negation, and in one place a error should be ignored).

Fix these two instances.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-01-28 21:29:25 +01:00
Priit Laes
0307d95d52 videomodes: Relax EDID validation checks for hsync/vsync pulse width
Current EDID detailed timing parser errors out when either
horizontal or vertical pulse sync width is 0, thus not
allowing a display with EDID listed below work properly.

EDID below works ok within Linux although it warns about
these two fields being 0. Therefore relax the checks a bit
so we can actually use this the screen out of the box.

Of-course, this display itself is somewhat quirky display with
following anti-features:
- HPD pin is not usable
- although resolution is 640x480, only top 240 pixels are visible

$ xxd -p display.edid
00ffffffffffff0005a1e00301000000150f0103800f05780a0f6ea05748
9a2610474f200000010101010101010101010101010101012a08804520e0
0b1020004000953600000018000000fd0034441a2403000a202020202020
0000001000310a20202020202020202020200000001000002a4030701300
782d1100001e006b

$ edid-decode display.edid
EDID version: 1.3
Manufacturer: AMA Model 3e0 Serial Number 1
Digital display
Maximum image size: 15 cm x 5 cm
Gamma: 2.20
RGB color display
First detailed timing is preferred timing
Display x,y Chromaticity:
  Red:   0.6250, 0.3398
  Green: 0.2841, 0.6044
  Blue:  0.1494, 0.0644
  White: 0.2802, 0.3105
Established timings supported:
  640x480@60Hz 4:3 HorFreq: 31469 Hz Clock: 25.175 MHz
Standard timings supported:
Detailed mode: Clock 20.900 MHz, 149 mm x 54 mm
                640  672  672  709 hborder 0
                480  484  484  491 vborder 0
               -hsync -vsync
               VertFreq: 60 Hz, HorFreq: 29478 Hz
Monitor ranges (GTF): 52-68Hz V, 26-36kHz H, max dotclock 30MHz
Dummy block
Dummy block
Checksum: 0x6b (valid)

Signed-off-by: Priit Laes <priit.laes@paf.com>
Signed-off-by: Priit Laes <plaes@plaes.org>
2019-01-28 21:20:05 +01:00
Ye Li
3fd39937b1 imx: video: Fix return value issue
When framebuffer driver init is failed, we should return the err value not 0.
So the video init can exit immediately.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-01-28 21:13:33 +01:00
Adam Ford
6d69e53511 ARM: imx6q_logic: Enable Falcon Mode and fatwrite
This patch enables Falcon Mode by default and updates the README
file to show instructions on how to run from the micro SD card
or eMMC.  This patch also enables fatwrite to help assist with
writing the 'args' to the microSD card.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-01-28 21:11:14 +01:00
Adam Ford
13baee30d3 ARM: imx6q_logic: Enable DM_USB and dependent regulators
With the updated device trees in place, this patch enables
DM_USB which uses several regulators also enabled with this patch.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-01-28 21:10:28 +01:00
Adam Ford
b64b5ad115 ARM: DTS: imx6q-logicpd: Update DTS/DTSI files
The i.MX6 SOM and development kits have undergone significant
updates and changes over the past few months.  This re-sync's
the U-Boot with Logic PD's BSP.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-01-28 21:09:44 +01:00
Adam Ford
79ae06ff58 imx6q_logic: Enable MMC booting from SPL
The MMC booting wasn't previously fitting into the codespace.
This patch enables MMC booting from the baseboard by reducing
some DM overhead during SPL.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-01-28 21:09:14 +01:00
Bryan O'Donoghue
8ba377321c arm: imx7s-warp: Convert to DM PMIC
This patch converts the warp7 and warp7_bl33 board ports over to using the
DM PMIC model.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2019-01-28 20:55:46 +01:00
Bryan O'Donoghue
ce36f56aca warp7: defconfig: Switch to DM for I2C
This commit switches to DM I2C for warp7 and warp7_bl33 defconfigs.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2019-01-28 20:55:46 +01:00
Bryan O'Donoghue
4b319237ad warp7: defconfig: Switch on IMX7 GPIO/pinctrl for both ports
Switches on the IMX7 pinctrl driver for the warp7 and warp7_bl33 ports,
necessary to convert over to DM for this board.

It is necessary to switch on pinctrl and GPIO in one go.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2019-01-28 20:55:46 +01:00
Bryan O'Donoghue
e4d8dac4bb arm: dts: imx7s-warp: Create alias for mmc0 to &usdhc3
This patch sets up an alias for mmc0 to usdhc3.

Before the DM conversion only usdhc3 was enabled and therefore it appeared
as MMC 0 to u-boot. After enabling MMC DM though usdhc3 defaults to MMC 2,
which left unattended would drive changes to existing warp7 bootscripts and
environment variables that rely on mmc 0.

Setup the alias of mmc0 and usdhc3 so that existing warp7 boot code will
work unmodified.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2019-01-28 20:55:46 +01:00
Bryan O'Donoghue
764d94736c arm: imx7s-warp: Convert to DM MMC initialization
Converts from fixed initialization of MMC to DM initialization of MMC.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2019-01-28 20:55:46 +01:00
Bryan O'Donoghue
a627f43868 arm: imx7s-warp: Add DT file hooks
This patch adds DT file hooks for imx7s-warp.dtb to the warp7 and
warp7_bl33 builds.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2019-01-28 20:55:46 +01:00
Bryan O'Donoghue
e6f7c58dfe arm: dts: imx7s-warp: Import Linux warp7 dts
This patch imports the Linux kernel warp7 dts as at upstream kernel commit
cf76c364a1e1.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2019-01-28 20:55:46 +01:00
Bryan O'Donoghue
8bdb575b0e arm: dts: imx7: Correct spelling mistake in GPIO name
As pointed out by Lucas WDOD1_WDOG_ANY should be WDOG1_WDOG_ANY. Once
corrected we can import the latest kernel DTS unmodified.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reported-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-01-28 20:55:46 +01:00
Peng Fan
9382f73bb0 imx8: cpu: restrict checking ROM passover info for revA
Passover info only for revA.

move get_cpu_rev out of CONFIG_CPU to avoid build failure when using
get_cpu_rev in SPL.
Add a CONFIG_SPL_BUILD for passover usage, no need to execute it again
in normal U-Boot stage. Also if still checking passover info in normal
U-Boot stage, need to make the passover code executed after
arch_cpu_init_dm.
So to make it easy and clean, only execute the code for SPL stage.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-28 20:55:46 +01:00
Ye Li
d8bbf362f3 imx: Check the PL310 version for applying errata
Apply errata based on PL310 version instead of compile
time. Also set Prefetch offset to 15, since it improves
memcpy performance by 35%. Don't enable Incr double
Linefill enable since it adversely affects memcpy
performance by about 32MB/s and reads by 90MB/s. Tested
with 4K to 16MB sized src and dst aligned buffer.

Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
2019-01-28 20:55:46 +01:00
Lukasz Majewski
56ac8104e3 ARM: imx: fix: Provide correct enum values for ONENAND/NOR boot recognition
According to "Table 5-1. Boot Device Select" (page 335,
i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 4, 09/2017)
the BOOT_CFG1[3] have following values (regarding EIM booting):
0 - NOR flash and 1 - ONENAND

This commit provides correct identification of the boot medium for IMX6Q
boards booting from NOR memory (MCCMON6 is one of them).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-01-28 20:55:46 +01:00
Patrick Bruenn
7e04b4c751 dm: arm: imx: migrate cx9020 to CONFIG_DM_MMC
Enable esdhc1/2 device nodes for cx9020 and build with CONFIG_DM_MMC=y

Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
2019-01-28 20:55:46 +01:00
Patrick Bruenn
77fd72ff8f arm: imx: Add esdhc1/2 nodes to imx53.dtsi
These nodes are required by CX9020 when build with CONFIG_DM_MMC=y
They are copied from Linux 4.20

Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
2019-01-28 20:55:46 +01:00
Patrick Bruenn
791c88da31 mmc: fsl_esdhc: add compatible for fsl, imx53-esdhc
Add compatible "fsl,imx53-esdhc" to keep mmc working on i.MX53 platforms
with CONFIG_DM_MMC=y

Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
2019-01-28 20:55:46 +01:00
Baruch Siach
430630cb03 imx8mq_evk/README: remove ARCH environment variable
There is no need to set the ARCH variable when building U-Boot. In fact,
the ARCH name in U-Boot is 'arm'.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
2019-01-28 20:55:46 +01:00
Adam Ford
96d0be07e7 MTD: nand: mxs_nand_spl: Fix empty function pointer for BBT
The initialization function calls a nand_chip.scan_bbt(mtd) but
scan_bbt is never initialized resulting in an undefined function
pointer.  This will direct the function pointer to nand_default_bbt
defined in the same file.

Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
2019-01-28 20:55:46 +01:00
Ye Li
65a106e36f spi: mxc_spi: Fix build warning on ARM64 platforms
When building mxc_spi driver on ARM64 platforms, get below build warnings.
Fix it in this patch.

In file included from include/common.h:48:0,
 from drivers/spi/mxc_spi.c:9:
 drivers/spi/mxc_spi.c: In function ‘spi_xchg_single’:
drivers/spi/mxc_spi.c:232:21: warning: cast from pointer to integer of
different size [-Wpointer-to-int-cast]
 _func_, bitlen, (u32)dout, (u32)din);
 ^
 include/log.h:135:26: note: in definition of macro ‘debug_cond’
printf(pr_fmt(fmt), ##args); \
 ^~~~
 drivers/spi/mxc_spi.c:231:2: note: in expansion of macro ‘debug’
debug("%s: bitlen %d dout 0x%x din 0x%x\n",
 ^~~~~
 drivers/spi/mxc_spi.c:232:32: warning: cast from pointer to integer of
different size [-Wpointer-to-int-cast]
 _func_, bitlen, (u32)dout, (u32)din);
 ^
 include/log.h:135:26: note: in definition of macro ‘debug_cond’
printf(pr_fmt(fmt), ##args); \
 ^~~~
 drivers/spi/mxc_spi.c:231:2: note: in expansion of macro ‘debug’
debug("%s: bitlen %d dout 0x%x din 0x%x\n",
 ^~~~~

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-01-28 20:35:47 +01:00
Ye Li
528915c717 imx: Fix potential lmb memory overwritten by stack
At default, u-boot reserves the memory from SP - 4KB to DRAM end for
lmb in arch_lmb_reserve. So lmb won't allocate any memory from it.
But we found the 4K gap for SP is not enough now, because some FDT
updating operations are added in our u-boot before jumping to kernel,
which needs larger stack. This causes the lmb allocated memory is overwritten
by stack.

Fix the issue by implementing the board_lmb_reserve to reserve from
SP - 16KB to memory end for lmb.

Signed-off-by: Ye Li <ye.li@nxp.com>
2019-01-28 20:35:47 +01:00
Ye Li
11a1c27eb4 pinctrl: imx: Fix select input issue
The pinctrl supports to set any bit in input register on iMX6 if
the MSB of input value is 0xff. But the driver uses signed int for
input value, so when executing the codes below, it won't meet.
Because this is arithmetic right shift.

    if (input_val >> 24 == 0xff)

Fix the issue by changing the input_val, config_val and mux_mode to u32.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-01-28 20:35:47 +01:00
Peng Fan
59ceb152f8 imx8qxp: mek: update README
Update README after we switch to use SPL

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-28 20:35:47 +01:00
Peng Fan
018e3fd2d1 imx8qxp: mek: default enable SPL
Enable SPL for i.MX8QXP MEK, and currently use SPL FIT.
The SPL enable SPL_DM to use MMC/PINCTRL/POWER DOMAIN/CLK.

Note: SPL FIT could not support secure boot chain, because i.MX8/8X
only support i.MX container format. This container format has
not been upstreamed, so we use FIT for now. When SPL container
supported, we could switch to that.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-28 20:35:47 +01:00
Peng Fan
caceb739ea imx: build flash.bin for i.MX8
Build flash.bin for i.MX8 when SPL enabled.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-28 20:35:47 +01:00
Peng Fan
b184a796a0 imx: mkimage_fit_atf: introduce BL33_BASE_ADDR
Introduce BL33_BASE_ADDR, then we could reuse this script for i.MX8QXP.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-28 20:35:47 +01:00
Peng Fan
8e0d963b19 dts: imx8qxp-mek: introduce u-boot dtsi
Introduce u-boot dtsi for i.MX8QXP MEK board.
we do not introduce a common dtsi for SoC, because different board
has different requirement on which needs to be enabled in SPL DM.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-28 20:35:47 +01:00
Peng Fan
f541796af9 spl: imx8: add spl boot device
Add spl_boot_device for i.MX8, also add BOOT_DEVICE_MMC2_2 for
spl_boot_mode.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-28 20:35:47 +01:00
Peng Fan
1610368234 gpio: introduce CONFIG_SPL_DM_PCA953X
Introduce CONFIG_SPL_DM_PCA953X for SPL usage.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-28 20:35:47 +01:00
Peng Fan
c1e0940f7c arm: imx: build mach-imx for i.MX8
To enable SPL for i.MX8, we could reuse code in arch/arm/mach-imx.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-28 20:35:47 +01:00
Peng Fan
04b249656e imx8: scu: use dedicated MU for SPL
SPL runs in EL3 mode, except MU0_A, others are not powered on,
and could not be used. However normal U-Boot use MU1_A, so we
could not reuse the one in dts. And we could not replace the one
in dts with MU0_A, because MU0_A is reserved in secure world.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-28 20:35:47 +01:00
Peng Fan
3bd888b55e imx8qxp: add SUPPORT_SPL option
Enable SUPPORT_SPL option for i.MX8QXP, then we could enable SPL.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-28 20:35:47 +01:00
Fabio Estevam
73127e9099 MAINTAINERS: imx: Change Fabio's email address
I prefer to use my personal email address for U-Boot related work.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-01-28 20:35:47 +01:00
Stefan Agner
e0558a2cc0 configs: add default configuraiton for Colibri iMX7 with eMMC
Add a default configuration for Colibri iMX7D 1GB (with eMMC
NAND flash).

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2019-01-28 20:35:47 +01:00
Stefan Agner
a0411da993 configs: colibri_imx7: use distro defaults
The defconfig already use most features implied by distro defaults.
Make sure we enable all features required by distro boot by making
use of CONFIG_DISTRO_DEFAULTS.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2019-01-28 20:35:41 +01:00
Stefan Agner
4849f7def2 configs: colibri_imx7: use DFU for NAND instead of MMC
The colibri_imx7_defconfig is for Colibri iMX7 raw NAND devices.
Hence DFU for NAND is more useful then for MMC devices.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2019-01-28 13:02:08 +01:00
Stefan Agner
edb411e2e6 configs: colibri_imx7: enable CAAM driver
Access to CAAM in non-secure mode must be enabled by the boot
loader first. The U-Boot CAAM driver enables access to CAAM in
non-secure mode by default. Hence enable the CAAM driver to
allow Linux accessing CAAM directly. This prevents error
messages like the following on Linux boot:
  caam 30900000.caam: Entropy delay = 3200
  caam 30900000.caam: failed to acquire DECO 0
  caam 30900000.caam: failed to instantiate RNG

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2019-01-28 13:02:08 +01:00
Stefan Agner
72a1d11388 colibri_imx7: drop legacy usdhc support
Drop legacy pinmux/usdhc board configuration.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2019-01-28 13:02:08 +01:00
Stefan Agner
22204f52c7 configs: colibri_imx7: use DM_MMC
Now that device tree is in place use DM_MMC for Colibri iMX7
devices.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2019-01-28 13:02:08 +01:00
Stefan Agner
b6fd4fccb4 arm: dts: imx7: colibri: add usdhci peripherals to device tree
Add usdhci peripherals to device tree. This allows to use DM_MMC
for Colibri iMX7 devices.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2019-01-28 13:02:08 +01:00
Stefan Agner
afca5841fc configs: colibri_imx7: use separate device tree
Use OF_SEPARATE as suggested by the build system.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2019-01-28 13:02:08 +01:00
Stefan Agner
23f61b81d8 configs: colibri_imx7: enable DM for raw NAND devices
Use DM and device trees for raw NAND devices by default. This
fixes -74 NAND read errors since it makes sure the ECC settings
are the same as used in Linux and our downstream U-Boot.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2019-01-28 13:02:08 +01:00
Stefan Agner
d8a32f52a6 arm: dts: imx7: colibri: split dt for raw NAND and eMMC devices
In preparation of adding CONFIG_DM_MMC support use separate device
trees for raw NAND and eMMC devices.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2019-01-28 13:02:08 +01:00
Stefan Agner
2bc18ce570 colibri_imx7: fix boot commands
Fix mixed up boot commands between raw NAND and eMMC variant. Also
make sure that the boot_file is defined for the eMMC boot command.

Fixes: a62c60610f ("colibri_imx7_emmc: add Colibri iMX7D 1GB (eMMC) module support")
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2019-01-28 13:02:07 +01:00
Fabio Estevam
9ec1791e6a Revert "tools: imx8image: set dcd_skip to true"
This reverts commit f7e475db40.

This commit breaks the boot on imx8qxp evk and it should only
be re-applied after imx8qxp evk is converted to SPL.

Revert it for now, so that imx8qxp evk can be functional.

Reported-by: Breno Lima <breno.lima@nxp.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Breno Lima <breno.lima@nxp.com>
2019-01-28 12:59:03 +01:00
Heinrich Schuchardt
eb7f908a16 tools: imx8image: use correct printf escape sequence
core is of type uint64_t. So for printing we need "%"PRIu64 (not "%lu").

Without the patch a warning is issued when building on a 32bit system.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-01-28 12:55:14 +01:00
Olaf Mandel
88b5002b34 m53menlo: fix addmtd cmd in default environment
The original definition added the string mtdparts= to the Linux Kernel
args twice: mtdparts=mtdparts=. Fix that.

Signed-off-by: Olaf Mandel <o.mandel@menlosystems.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2019-01-28 12:54:30 +01:00
Olaf Mandel
de5def1cf5 m53menlo: fix splashfile location
After merging the boot partition into the root partition, the splashfile
resides in the /boot subdirectory: update the default environment to
reflect that.

Signed-off-by: Olaf Mandel <o.mandel@menlosystems.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2019-01-28 12:54:15 +01:00
Fabio Estevam
9e3c0174da pico-imx7d: Add LCD support
Add support for the VXT VL050-8048NT-C01 panel connected through
the 24 bit parallel LCDIF interface.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2019-01-28 12:53:48 +01:00
Fabio Estevam
bab289cbe9 mx7: Do not call lcdif_power_down() in the SPL case
Like it was done on imx6 in commit 9236269de5 ("imx: mx6: Fix
implementantion reset_misc")

Do not call lcdif_power_down() in the SPL case to fix the following
build error:

  LD      spl/u-boot-spl
  MKIMAGE u-boot.img
arch/arm/mach-imx/built-in.o: In function `reset_misc':
/home/fabio/ossystems/u-boot/arch/arm/mach-imx/mx7/soc.c:372: undefined reference to `lcdif_power_down'
scripts/Makefile.spl:375: recipe for target 'spl/u-boot-spl' failed

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-01-28 12:53:21 +01:00
Martyn Welch
0963060c99 imx: Add PHYTEC phyBOARD-i.MX6UL-Segin
Port for the PHYTEC phyBOARD-i.MX6UL-Segin single board computer. Based on
the PHYTEC phyCORE-i.MX6UL SOM (PCL063).

CPU:   Freescale i.MX6UL rev1.2 528 MHz (running at 396 MHz)
CPU:   Industrial temperature grade (-40C to 105C) at 44C
Reset cause: POR
Board: PHYTEC phyCORE-i.MX6UL
I2C:   ready
DRAM:  256 MiB
NAND:  512 MiB
MMC:   FSL_SDHC: 0
In:    serial
Out:   serial
Err:   serial
Net:   FEC0

Working:
 - Eth0
 - i2C
 - MMC/SD
 - NAND
 - UART (1 & 5)
 - USB (host & otg)

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
2019-01-28 12:47:27 +01:00
Martyn Welch
774ec60b74 Enable FEC driver to retrieve PHY address from device tree
Currently if we have more than one phy on the MDIO bus, we do not have a
good mechanism for determining which should be used at runtime. Enable the
FEC driver to determine the address for the PHY from the device tree.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-01-28 12:47:15 +01:00
Breno Matheus Lima
b2ca8907d9 imx: hab: Convert non-NULL IVT DCD pointer warning to an error
The following NXP application notes and manual recommend to ensure the
IVT DCD pointer is Null prior to calling HAB API authenticate_image()
function:

- AN12263: HABv4 RVT Guidelines and Recommendations
- AN4581: Secure Boot on i.MX50, i.MX53, i.MX 6 and i.MX7 Series using
  HABv4
- CST docs: High Assurance Boot Version 4 Application Programming
  Interface Reference Manual

Commit ca89df7dd4 ("imx: hab: Convert DCD non-NULL error to warning")
converted DCD non-NULL error to warning due to the lack of documentation
at the time of first patch submission. We have warned U-Boot users since
v2018.03, and it makes sense now to follow the NXP recommendation to
ensure the IVT DCD pointer is Null.

DCD commands should only be present in the initial boot image loaded by
the SoC ROM. Starting in HAB v4.3.7 the HAB code  will generate an error
if a DCD pointer is present in an image being authenticated by calling the
HAB RVT API. Older versions of HAB will process and run DCD if it is
present, and this could lead to an incorrect authentication boot flow.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-01-28 12:45:45 +01:00
Tom Rini
2f41ade79e linker: Modify linker scripts to be more generic
Make use of "IMAGE_MAX_SIZE" and "IMAGE_TEXT_BASE" rather than
CONFIG_SPL_MAX_SIZE and CONFIG_SPL_TEXT_BASE.  This lets us re-use the
same script for both SPL and TPL.  Add logic to scripts/Makefile.spl to
pass in the right value when preprocessing the script.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Jagan Teki <jagan@openedev.com>
Cc: Maxime Ripard <maxime.ripard@bootlin.com>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Adam Ford <aford173@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tested-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tested-by: Adam Ford <aford173@gmail.com> #da850evm & omap3_logic_somlv
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-01-26 22:55:53 -05:00
Tom Rini
b32ba6f12e rockchip: Add TPL_MAX_SIZE for RK3288
Per Kever Yang, 32768 is a reasonable max size for TPL on RK3288.

Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-01-26 22:55:53 -05:00
Tom Rini
a6d6812a21 PowerPC: Stop re-using CONFIG_SPL_TEXT_BASE for TPL
Rather than checking for CONFIG_TPL_BUILD and then re-defining
CONFIG_SPL_TEXT_BASE make use of CONFIG_TPL_TEXT_BASE directly.

Cc: York Sun <york.sun@nxp.com>
Cc: Po Liu <po.liu@nxp.com>
Cc: Qiang Zhao <qiang.zhao@nxp.com>
Cc: Timur Tabi <timur@tabi.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-01-26 22:55:53 -05:00
Tom Rini
0da9025508 Merge branch '2019-01-25-master-imports'
- snapdragon 820c improvements
- poplar updates
- DFU + SPL cleanups
- Improve the mediatek mmc driver
- Other minor cleanups / improvements
2019-01-26 22:47:55 -05:00
Heinrich Schuchardt
320194ae35 hashtable: remove caps buffer
slre_match() checks if caps == NULL. In this case it does not try to
update it. So there is no need to create a buffer caps which we do not
evaluate.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-01-26 08:13:58 -05:00
Simon Goldschmidt
e35d2a7553 lib: lmb: cleanup var names and patman warnings
Change multiple usages of 'j' into 'rgn'; fix whitespace/coding style
reported by patman.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-01-26 08:13:57 -05:00
Simon Goldschmidt
65304aade8 lib: lmb: rename lmb_get_unreserved_size to lmb_get_free_size
As a follow-up, change the name of the newly introduced function
'lmb_get_unreserved_size' to 'lmb_get_free_size', which is more
appropriate.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
[trini: Fix test/lib/lmb.c]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-01-26 08:13:57 -05:00
Philippe Reynes
eba0c26f07 bcm968380gerg: disable SPI_FLASH
The board bcm968380gerg don't have a spi flash so
we disable the spi flash support.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-01-26 08:13:57 -05:00
Patrick Delaunay
67eea68a34 MAINTAINERS: update stm32mp1 path for arch
Handle correctly directory arch/arm/mach-stm32mp/ :
Add a trailing slash to include all files
and subdirectory files.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-01-26 08:13:57 -05:00
Michal Simek
e38cef9f6e misc: i2c_eeprom: Add atmel,24c08 to the list
Linux kernel binding is using atmel,24c08 compatible string. On the
other hand there is atmel,24c08a which is not listed in the kernel.
Add compatible string without "a" suffix to be compatible with Linux
kernel binding.

These eeproms are available on several ZynqMP development boards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-26 08:13:57 -05:00
Simon Goldschmidt
e4478d9ac8 tests: dtoc: adapt tests to changed dtoc output
The dtoc tests need to be adapted to dtoc being changed to output platdata
structs as const, which has been introduced in commit 7d05d3a8e3 ("dtoc:
make generated platdata structs const").

Fixes: 7d05d3a8e3 ("dtoc: make generated platdata structs const")
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2019-01-26 08:13:56 -05:00
Greg Czerniak
b8fea5e8dd atmel: add CMD_FS_GENERIC to SAMA5D3 for EFI boot
I'm working on getting OpenBSD to run on the Atmel SAMA5D3 Xplained.
OpenBSD uses an EFI bootloader, which requires the "load" command to
work, since "fatload" doesn't initialize the EFI memory addresses
properly. To get "load" on the SAMA5D3 version of U-Boot, I propose
adding the CONFIG_CMD_FS_GENERIC option.

Signed-off-by: Greg Czerniak <greg@czerniak.info>
2019-01-26 08:13:56 -05:00
Angelo Dureghello
1f15cb8f5b drivers: esdhc: add support for ColdFire mcf5441x family
This patch has been tested on the mcf54415-based stmark2
board. The eSDHC driver works reliably using DMA mode.

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
2019-01-26 08:13:56 -05:00
Sam Protsenko
293a172b67 env: Fix saving environment to "bad CRC" location
In case when the environment on some location is malformed (CRC isn't
matching), there is a chance we won't be able to save the environment to
that location. For example, consider the case when we only have the
environment on eMMC, but it's zeroed out. In that case, we won't be able
to "env save" to it, because of "bad CRC" error. That's happening
because in env_load() function we consider malformed environment as
incorrect one, and  defaulting to the location with highest (0)
priority, which can be different from one we are dealing with right now
(e.g., highest priority can be ENV_FAT on SD card, which is not
inserted, but we want to use ENV_MMC on eMMC, where we were booted
from).

This issue began to reproduce after commit d30ba2315a ("u-boot: remove
driver lookup loop from env_save()") on BeagleBone Black, but that
commit didn't introduce the wrong logic, it just changed the behavior
for default location to use, merely revealing this issue.

To fix that, let's implement next logic in env_load():
  1. Try to find out correct environment; if found -- use it
  2. If working environment wasn't found, but we found malformed one
     (with bad CRC), let's use it for further "env save". But make sure
     to use malformed environment location with highest priority.
  3. If neither correct nor malformed environment was found, let's
     default to environment location with highest priority (0)

Steps to reproduce mentioned issue on BeagleBone Black (fixed in this
patch):

1. Boot from SD card and erase eMMC in U-Boot shell:
   => mmc dev 1
   => mmc erase 0 100000
   => gpt write mmc 1 $partitions
2. Write new SPL and U-Boot to eMMC; the rest of eMMC will stay filled
   with zeroes
3. Boot from eMMC; try to do:
   => env save
4. Observe the error (incorrect behavior). Correct behavior: environment
   should be stored correctly on eMMC, in spite of it has "bad CRC"

Fixes: d30ba2315a ("u-boot: remove driver lookup loop from env_save()")
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-01-26 08:13:56 -05:00
Sam Protsenko
49d04c589c env: common: Return specific error code on bad CRC
Callers of env_import*() functions might want to check the case when we
have incorrect environment (with bad CRC). For example, when environment
location is being defined in env_load(), call chain may look like this:

    env_load() -> drv->load() = env_mmc_load() -> env_import()

Return code will be passed from env_import() all way up to env_load().
Right now both env_mmc_load() and env_import() return -EIO error code,
so env_load() can't differentiate between two cases:
  1. Driver reports the error, because device is not accessible
  2. Device is actually accessible, but environment is broken

Let's return -ENOMSG in env_import(), so we can distinguish two cases
mentioned above. It will make it possible to continue working with "bad
CRC" environment (like doing "env save"), instead of considering it not
functional (implemented in subsequent patch).

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-01-26 08:13:56 -05:00
Marcin Niestroj
f68bc629f4 ARM: chiliboard: enable DM_SPI
Add DM_SPI to suppress build warning about dm conversion.

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
2019-01-26 08:13:55 -05:00
Robert P. J. Day
c1180aa254 Makefile: have "make distclean" remove CHANGELOG
Ensure that "make distclean" deletes an existing CHANGELOG file.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2019-01-26 08:13:55 -05:00
Andrew F. Davis
0fd1359c5a ARM: mach-omap2: Kconfig: Allow OMAP5 devices to set entry point
Like AM33xx and AM43xx, DRA7xx and AM57xx devices may need to
have an non-standard boot address in memory. This may be due
to the device being a high security variant, which place the
Initial SoftWare (ISW) after certificates and secure software.

Allow these devices to set this from Kconfig.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2019-01-26 08:13:55 -05:00
Andrew F. Davis
2dd468dbe1 dfu: Remove dependency on HUSH parser in SPL
CLI support with the HUSH parser is not currently SPL safe due to it's
use of realloc. That function is not defined for SPLs that use
SYS_MALLOC_SIMPLE. CLI support can be built in to SPL and some functions
do work, but use of some like run_command() will cause build to fail.
When no SPL code calls this function build works as the compiler removes
this unreachable code so the unresolved symbols are ignored.

If DFU support is enabled in SPL then MMU DFU support may get brought in
also, this code does make a call to run_command() causing build to fail
if the HUSH parser is not built-in. To break this odd and unneeded
dependency chain we use CONFIG_IS_ENABLED where appropriate to prevent
calls into HUSH code from SPL. This also removes our need to pull in the
rather unrelated source file when SPL_DFU is defined.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-01-26 08:13:55 -05:00
Andrew F. Davis
2d59ec8482 dfu: Make DFU support more SPL friendly
Do this by using $(SPL_) in Makefiles and CONFIG_IS_ENABLED in C code.
This ensures the files and features are only built into the right build
for which they are enabled. Using the macros to simplify this patch was
made possible by the config symbol rename done in the last patch.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
2019-01-26 08:13:55 -05:00
Andrew F. Davis
6536ca4d66 spl: Kconfig: Drop the _SUPPORT postfix from SPL_DFU
The symbol CONFIG_SPL_DFU_SUPPORT in SPL build has the same
meaning as CONFIG_DFU in regular U-Boot. Drop the _SUPPORT
to allow for cleaner use in code.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
2019-01-26 08:13:54 -05:00
Fabien Parent
70dbbd7269 mmc: mtk-sd: fix SPL compilation when GPIO=y and SPL_GPIO=n
It is not possible to link the SPL image when CONFIG_GPIO is enabled
but CONFIG_SPL_GPIO is not.  Use the IS_ENABLED macro instead to
correctly check whether CONFIG_{SPL_}GPIO is enabled.

This commit fixes the following errors:
	* undefined reference to `dm_gpio_get_value
	* undefined reference to `gpio_request_by_name'

Signed-off-by: Fabien Parent <fparent@baylibre.com>
[trini: Move guard to fix warning in msdc_ops_get_wp()]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-01-26 08:13:54 -05:00
Fabien Parent
924ed344a7 mmc: mtk-sd: fix possible incomplete read ops
The code is checking for incomplete read when it see the INT_XFER_COMPL
flag, but it forget to first check whether there is anything left in the
FIFO to copy to the RX buffer. This means that sometimes we will get
errors because of erroneous incomplete read operation.

This commit fixes the driver re-ordering the code so that we first
check for data inside the RX fifo and only after check the status
of the INT_XFER_COMPL flag.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
2019-01-26 08:13:54 -05:00
Igor Opaniuk
246fb9dd9c arm64: dt: poplar: add optee node
As Poplar supports running TF-A with OP-TEE as BL32
payload, add op-tee node in DT, which enables usage of
OP-TEE driver (which provides an interface for requesting services
from OP-TEE).

Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-26 08:13:54 -05:00
Shawn Guo
7fa6d33684 poplar: clean up board level mmc initialization code
We have converted mmc to driver model on Poplar.  So let's clean up
board level mmc initialization code.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2019-01-25 12:12:57 -05:00
Shawn Guo
94f139a9ce mmc: hi6220_dw_mmc: add compatible for Poplar support
It adds compatible "hisilicon,hi3798cv200-dw-mshc" for Poplar SoC
Hi3798CV200 to probe this mmc driver.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2019-01-25 12:12:57 -05:00
Shawn Guo
8eef803a27 poplar: sync up device tree with kernel 4.20
It adds missing pinctrl headers, updates clock header and sync up Poplar
device tree with kernel 4.20 release.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2019-01-25 12:12:56 -05:00
Ramon Fried
fbf4152ba6 dts: 820c: Add pinctrl node and uart mux
* Add pinctrl node for TLMM and add mux request for uart node.
* Rename uart to the actual board uart port.
* Fix indentendation of sdhc2 node.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2019-01-25 12:12:56 -05:00
Ramon Fried
ea7bf8fb08 arm: mach-snapdragon: pinctrl: clarify gpio disable bit
The TLMM_GPIO_ENABLE bit is actually use to disable
the GPIO. change it to TLMM_GPIO_DISABLE so it's clearer.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2019-01-25 12:12:56 -05:00
Ramon Fried
b1cd785755 configs: dragonboard820c: Enable pinctrl/mux config
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2019-01-25 12:12:55 -05:00
Ramon Fried
94268f1ab2 arm: mach-snapdragon: add pinctrl driver for db820c
Add pinctrl driver for Dragonboard820c, currently with only
one mux func to initialize pins for serial console.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2019-01-25 12:12:55 -05:00
Ramon Fried
604aa9d30b arm: mach-snapdragon: db820c: Actually init PLL for serial
The PLL for the UART was not set, and relied on previous
initializtion made by LK. add the appropriate initialization.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2019-01-25 12:12:55 -05:00
Stefan Theil
240e58ee53 cmd: ximg: Invert check for fit image compression
The imgextract command runs a number of checks of
the specified fit. Where it checks for a load address
for compressed images the logic in the expression
is inverted as fit_image_check_comp returns 1 on
success and not 0.
2019-01-25 12:12:55 -05:00
Sean Nyekjær
29e1a64c06 arm: stm32mp1: deploy spl in root folder
Deploy u-boot-spl.stm32 binary in u-boot root folder like
the rest of the boards.
This makes it more streamlined when building in Yocto, Buildroot etc..

Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
2019-01-25 12:12:52 -05:00
Tom Rini
7196ce7ab7 configs: Migrate CONFIG_DFU_MMC again
A few platforms recently added in CONFIG_DFU_MMC under include/configs
rather than via the defconfig, update them.

Signed-off-by: Tom Rini <trini@konsulko.com>
2019-01-25 12:04:16 -05:00
Tom Rini
87f78478a4 Merge tag 'arc-fixes-for-2019.04-rc1' of git://git.denx.de/u-boot-arc
A couple of trivial fixes and improvements for ARC

Most notable are:
 * Move of ENV_SIZE/ENV_OFFSET to Kconfig
 * Fix with private structure allocation for arc_uart
 * Definition of CONFIG_SYS_CACHELINE_SIZE useful for building drivers
2019-01-25 10:41:24 -05:00
Alexey Brodkin
fae3798ac9 ARC: cache: define CONFIG_SYS_CACHELINE_SIZE as ARCH_DMA_MINALIGN
Even though we don't use CONFIG_SYS_CACHELINE_SIZE in ARC-specific code
it is used a lot in different drivers for alignment purposes.

So we define it and make much more drivers at least compilable for ARC.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2019-01-25 08:41:09 +03:00
Alexey Brodkin
7181a6d1cf ARC: Fix iteration in arc_xx_version()
"i" gets incremented before we're entering loop body
and effectively we iterate from 1 to 8 instead of 0 to 7.

This way we:
 a) Skip the first line of struct hs_versions
 b) Go over it and access memory beyond the structure

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2019-01-25 08:40:53 +03:00
Alexey Brodkin
d771dd531a serial_arc: Allocate buffer for private data
Apparently we never allocated buffer for arc_serial_platdata
which for some reason never caused problems when executed in nSIM.
But in Qemu this causes expected problems.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2019-01-25 08:40:26 +03:00
Alexey Brodkin
70b5ea7406 ARC: Move ENV_SIZE and ENV_OFFSET to Kconfig
Join the party of some ARM boards and drop more
items from include/configs/xxx.h.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-01-25 08:38:18 +03:00
Alexey Brodkin
31e00acdc7 serial: Get rid of CONFIG_DW_SERIAL
CONFIG_DW_SERIAL is no longer used anywhere so let's forget about it.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Adam Ford <aford173@gmail.com>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Cc: Alex Kiernan <alex.kiernan@gmail.com>
Cc: "Jorg Krause" <joerg.krause@embedded.rocks>
Cc: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-25 08:38:18 +03:00
Tom Rini
d01806a8fc Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2019-01-24 15:30:48 -05:00
Tom Rini
68489ed037 Merge branch 'master' of git://git.denx.de/u-boot-net 2019-01-24 15:30:06 -05:00
Tom Rini
0c3b301f79 Merge tag 'mpc85xx-for-v2019.04-rc1' of git://git.denx.de/u-boot-mpc85xx
mpc85xx config.mk: Add support for -msingle-pic-base
2019-01-24 15:29:45 -05:00
Valentin-catalin Neacsu
91c9cbabf9 net: phy: aquantia: Print information on config
Print information about Aquantia system interface and firmware loaded
on the phy.

Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:30 -06:00
Valentin-catalin Neacsu
c54bfbf96f net: phy: aquantia: Enable autoneg when on USXGMII
If System Interface protocol is USXGMII then enable USXGMII autoneg

Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:30 -06:00
Chris Packham
67bb984249 net: remove CONFIG_MCAST_TFTP
No mainline board enables CONFIG_MCAST_TFTP and there have been
compilation issues with the code for some time. Additionally, it has a
potential buffer underrun issue (reported as a side note in
CVE-2018-18439).

Remove the multicast TFTP code but keep the driver API for the future
addition of IPv6.

Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:30 -06:00
Chris Packham
1a4af5c562 net: move ether_crc to tsec driver
ether_crc was added to the core net code in commit 53a5c424bf
("multicast tftp: RFC2090") so that other drivers could use it. However
the only current user of it is tsec.c so move it there.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:29 -06:00
Carlo Caione
e57c9fdb04 net: phy: realtek: Add functions to read PHY's extended registers
According to the datasheet to access the extended registers we have to:

1. Write Register 31 Data = 0x0XYZ (Page 0xXYZ)
2. Read/Write the target Register Data
3. Write Register 31 Data = 0x0000 or 0xa42 (switch back to IEEE
   Standard Registers)

Hook the missing functions so that we can use the `mdio rx/wx` command to
easily access the extended registers.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:29 -06:00
Ramon Fried
9043c4e0fc net: macb: fix mapping of registers
Some architectures (MIPS) needs mapping to access IOMEM.
Fix that.

Fixes: f1dcc19b21 ("net: macb: Convert to driver model")

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:29 -06:00
Aditya Prayoga
18bfc8fa84 net: mvneta: Add GPIO configuration support
This patch add GPIO configuration support in mvneta driver.
Driver will handle PHY reset. GPIO pins should be set in device tree.

Ported from mvpp2x
[https://patchwork.ozlabs.org/patch/799654/]

Initial discussion to port the changes into mvneta
[https://patchwork.ozlabs.org/patch/1005765/]

Signed-off-by: Aditya Prayoga <aditya@kobol.io>
Tested-by: Dennis Gilmore <dgilmore@redhat.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:29 -06:00
Chris Packham
92f129f4a0 net: mvgbe: fallback phy-mode to GMII
Some existing device trees don't specify a phy-mode so fallback to GMII
when a phy-mode is not provided.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:29 -06:00
Andreas Pretzsch
3b4cda34d4 net: phy: micrel: fix KSZ9031 clock skew for values greater 0ps
For KSZ9021, all skew register fields are 4-bit wide.
For KSZ9031, the clock skew register fields are 5-bit wide.

The common code in ksz90x1_of_config_group calculating the combined
register value checks if the requested value is above the maximum
and uses this maximum if so. The calculation of this maximum uses
the register width, but the check itself does not. It uses a hardcoded
value of 0xf, which is too low in case of the 5-bit clock (0x1f).
This detail was probably lost during driver unification.

Effect (only for KSZ9031 clock skews): For values greater 900 (== 0ps),
this silently results in 1860 (== +960ps) instead of the requested one.

Fix the check by using the bit width instead of hardcoded value(s).

Signed-off-by: Andreas Pretzsch <apr@cn-eng.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:28 -06:00
Simon Goldschmidt
be09f5bc7c net: fix env flags for eth10addr and above
With CONFIG_REGEX enabled, ETHADDR_WILDCARD is set up for up to 10
interfaces (0..9) as the number can only have one digit.

On boards with more than 10 interfaces, this leads to the protection
and format checks being absent for eth10addr and above.

Fix this by changing ETHADDR_WILDCARD from "\\d?" to "\\d*" to allow
more than one digit.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:28 -06:00
Simon Goldschmidt
6880efdf5a net: remove duplicate definition of ETHADDR_WILDCARD
ETHADDR_WILDCARD is defined as the same value in both env_flags.h
and env_callback.h

As env_callback.h includes env_flags.h, remove the duplicate definition
from env_callback.h

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:28 -06:00
Thomas RIENOESSL
a735e6e9d6 net: explicitly assign errno to return code in case of network failure
When dealing with two ethernet ports and having "netretry" set
to "once", it could occur that the connection (e.g. an ARP
request) failed, hence the status of the netloop was
"NETLOOP_FAIL". Due to the setting of "netretry", the network
logic would then switch to the other network interface,
assigning "ret" with the return value of "net_start_again()".
If this call succeeded we would return 0 (i.e. success) to
the caller when in reality the network action failed.

Signed-off-by: Thomas RIENOESSL <thomas.rienoessl@bachmann.info>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:28 -06:00
Baruch Siach
21586cdd50 net: mvpp2: mdio device per port
Current code forces all ports on a given Ethernet device to use the same
mdio device. In practice different ports might be wired to separate mdio
devices. Move the mdio device from the container struct mvpp2 to the per
port struct mvpp2_port.

Cc: Ken Ma <make@marvell.com>
Cc: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:28 -06:00
Baruch Siach
acce753dfb net: mvpp2: fix lookup of mdio registers base address
Current mdio base lookup code relies on a 'reg' property at the upper CP
node. There is no 'reg' property there in current DT files of Armada
CP110. Use ofnode_get_addr() instead since it provides proper DT address
translation.

Cc: Ken Ma <make@marvell.com>
Cc: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:27 -06:00
Simon Goldschmidt
7efb75b114 net: designware: clear padding bytes
Short frames are padded to the minimum allowed size of 60 bytes.
However, the designware driver sends old data in these padding bytes.
It is common practice to zero out these padding bytes ro prevent
leaking memory contents to other hosts.

Fix the padding code to zero out the padded bytes at the end.

Tested on socfpga gen5.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:27 -06:00
Simon Goldschmidt
ae8ac8d423 net: designware: fix tx packet length
The designware driver has a bug in setting the tx length into the dma
descriptor: it always or's the length into the descriptor without
zeroing out the length mask before.

This results in occasional packets being transmitted with a length
greater than they should be (trailer). Due to the nature of Ethernet
allowing such a trailer, most packets seem to be parsed fine by remote
hosts, which is probably why this hasn't been noticed.

Fix this by correctly clearing the size mask before setting the new
length.

Tested on socfpga gen5.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-01-24 11:35:27 -06:00
Pankaj Bansal
b3eabd82f2 net: phy: Add clause 45 identifier to phy_device
The phy devices can be accessed via clause 22 or via clause 45.
This information can be deduced when we read phy id. if the phy id
is read without giving any MDIO Manageable Device Address (MMD), then
it conforms to clause 22. otherwise it conforms to clause 45.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:26 -06:00
Tom Rini
ce0d1e4816 Merge tag 'xilinx-for-v2019.04' of git://git.denx.de/u-boot-microblaze
Xilinx changes for v2019.04

tools:
- Fix zynqmpimage generation

zynq:
- Some configs/Kconfig/DT updates
- Enable REMAKE_ELF and OF_SEPARATE
- Topic boards update
- i2c cleanups and conversion to DM_I2C

zynqmp:
- Some configs/Kconfig/DT updates
- Board config cleanup
- Move arch folder to mach-zynqmp

versal:
- Enable DM_I2C, CMD_DM

zynq-gem:
- Fix driver cache handling

i2c:
- Live tree simple update

phy:
- Fixed phy cleanup

travis:
- Wire Versal SoC
2019-01-24 10:47:05 -05:00
Michal Simek
4efdbc88b7 ARM: zynq: Convert Topic Miami to DM_I2C
Both boards have only controllers enabled that's why move to DM_I2C is
easy.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:45 +01:00
Michal Simek
8d932736f5 ARM: zynq: Disable i2c for Zybo/Zybo Z7
There is no i2c connected in base DT that's why disable I2C commands.
Also remove zynq_zybo which is not needed now.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:45 +01:00
Michal Simek
2e530511fa ARM: zynq: Remove unused GEM addresses
With DM in place there is no need to have GEM addresses in headers. None
is using them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:45 +01:00
Michal Simek
73d52b066a arm64: zynqmp: Remove unused GEM addresses
With DM in place there is no need to have GEM addresses in headers. None
is using them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:45 +01:00
Anton Gerasimov
8a2607020c zynq: Kconfig: extend the bootstrap malloc() pool
Most of the memory is being consumed by device binding code,
more space needed for other data structures.

Z-turn board has already hit the limit, others may follow soon.

Measuring only the memory consumed in device_bind_common, I've got
the following results (in decimal):

  root_driver:               108
  mod_exp_sw:                108
  amba:                      120
  serial@e0000000 aka uart0: 112
  serial@e0001000 aka uart1: 88
  spi@e000d000 aka qspi:     120
  sdhci@e0100000 aka mmc0:   455
  sdhci@e0100000.blk:        208
  slcr@f8000000:             96
  clkc@100:                  72
  (total)                    1487 = 0x5cf of 0x600

Signed-off-by: Anton Gerasimov <tossel@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:45 +01:00
Mike Looijmans
acc58a4aca board: topic-miamiplus: Run IO PLL at 1000 MHz
The miamiplus can use GEM0 through MIO pins, which requires a 125 MHz TX
clock to be generated. With the IO PLL at 1200 MHz this isn't possible, so
change it to run at 1000 and adjust the divisors accordingly. Also set the
GEM0 clock source to MIO instead of EMIO.

Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:45 +01:00
Mike Looijmans
5820590309 topic-miamiplus: Run CPU at 800MHz for speedgrade-2
The miamiplus contains a speedgrade-2 device, which may run the CPU at 800MHz.
Change the PLL setting to 800MHz, and adapt the setpoints in the devicetree.

Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:45 +01:00
Michal Simek
84de0f9188 i2c: cdns: Convert to livetree function
Update cadence i2c driver to support livetree
Similar changes were done by:
"net: zynq_gem: convert to use livetree"
(sha1: 26026e695a)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:45 +01:00
Michal Simek
89fe08bb88 arm64: versal: Enable dm command
It is useful to have this command enable to see which devices are
bind/probed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:44 +01:00
Michal Simek
c447a17d9e arm64: versal: Enable i2c cadence controller and i2c command
Enable communication over i2c.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:44 +01:00
Michal Simek
274ccb5b11 arm64: zynqmp: Move SoC sources to mach-zynqmp
Similar changes was done for Zynq in past and this patch just follow
this pattern to separate cpu code from SoC code.

Move arch/arm/cpu/armv8/zynqmp/* -> arch/arm/mach-zynqmp/*
And also fix references to these files.

Based on
"ARM: zynq: move SoC sources to mach-zynq"
(sha1: 0107f24036)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:44 +01:00
Michal Simek
495c7303a9 ARM: zynq: Convert all boards to OF_SEPARATE
Build warning was added by:
"fdt: Add warning about CONFIG_OF_EMBED"
(sha1: 841d5fbae4)

Zynq mini configurations are not moved yet and it is questionable if
make sense to move them too.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:44 +01:00
Siva Durga Prasad Paladugu
e2321f0b3c arm: zynq: Enable CONFIG_REMAKE_ELF
This patch enables CONFIG_REMAKE_ELF for Zynq platform
so that it generates u-boot.elf from binary which works
for all Zynq boards with OF_SEPARATE option enabled.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:44 +01:00
Michal Simek
e9dc39915a arm64: zynqmp: Convert all reference boards to OF_SEPARATE
Build warning was added by:
"fdt: Add warning about CONFIG_OF_EMBED"
(sha1: 841d5fbae4)

ZynqMP mini configurations are not moved yet and it is questionable if
make sense to move them too.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:44 +01:00
Michal Simek
a903dcf7de arm64: zynqmp: Align u-boot-spl.bin for boot.bin creation
Bootrom is not capable to work with non align bootloader partition
that's why it is necessary to align it before boot.bin creation.
The patch is creating new spl/u-boot-spl-align.bin which is used only
for boot.bin.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-24 10:03:44 +01:00
Michal Simek
775ed87ac4 tools: zynqmpimage: Align image_size/image_stored_size
Bootrom is not capable to work with non aligned bootloader sizes.
SPL with OF_SEPARATE generates non-align images quite often that's
why this change is required before OF_SEPARATE enableding.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:44 +01:00
Michal Simek
d9eaae3bae travis: Wire Xilinx Versal Virt platform
Test Xilinx Versal Virt platform running on the v3.1.0 Qemu.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:44 +01:00
Michal Simek
5d93e886f8 arm64: zynqmp: Disable MMC for for zc12xx_revA boards
All these boards have no SD enabled.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:43 +01:00
Michal Simek
871ad9253f arm64: zynqmp: Enable FPGA_LOAD_SECURE command
Enable fpga load secure feature for xilinx platforms.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:43 +01:00
Michal Simek
f854004f95 arm64: zynqmp: Enable ISSI flash for some platforms
Enable ISSI flash for platforms. Xilinx reference boards are also used
internally with different flash part to increase coverage that's why
enable also ISSI parts for all these boards even if that board is
released only with one part.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:43 +01:00
Michal Simek
8ae3fd6609 arm64: zynqmp: Enable SPI on several boards
Enable GQSPI driver, SF command and SPL support for some platforms.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:43 +01:00
Michal Simek
088f83ee3a arm64: zynqmp: Setup proper SPI dependency
Select DM_SPI/DM_SPI_FLASH for the whole SoC.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:43 +01:00
Michal Simek
6f96fb508d ARM: zynqmp_r5: Setup DM_ETH/MMC if NET/MMC is enabled
Setup proper ETH/MMC dependency for the whole platform.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:43 +01:00
Siva Durga Prasad Paladugu
2ae587b86f arm64: zynqmp: Enable net configs for zc1275
This patch enable net configs for zc1275 board.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:43 +01:00
Michal Simek
fb69310850 arm64: zynqmp: Setup DM_ETH/MMC if NET/MMC is enabled
Setup proper ETH/MMC dependency for the whole platform.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:43 +01:00
Michal Simek
fa7971574c arm64: versal: Setup DM_ETH/MMC if NET/MMC is enabled
Setup proper ETH/MMC dependency for the whole platform.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:43 +01:00
Luca Ceresoli
8df324a20b fpga: zynqmp: show an error message when FPGA programming fails
When FPGA programming fails, it does so silently, unless debugging
code is enabled. This makes it hard to detect problems in production
environments.

Print the error message unconditionally so the error doesn't go
unnoticed.

Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:43 +01:00
Michal Simek
4c84844715 arm64: zynqmp: Fix tcminit help text alignment
Trivial patch.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:43 +01:00
Siva Durga Prasad Paladugu
c256d3f7c5 net: phy: Move fixed link code to separate routine
This patch moves fixed-link functionality code to a separate
routine inorder to make it more modular and cleaner.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 10:03:43 +01:00
Siva Durga Prasad Paladugu
e7c9de6617 arm64: zynqmp: Fix mmc node names to be in sync with kernel
This patches renames sd nodes in dts to be in line with
kernel. This patch also modifies the references for the same
in code.
It checks mmc first to have no time penalty for new DT node names based
on left-to-right expression evaluation.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:42 +01:00
Stefan Theil
1059858061 zynq-gem: Use appropriate cache flush/invalidate for RX and TX
The cache was only flushed before *transmitting* packets, but not
when receiving them, leading to an issue where new packets were
handed to the receive handler with old contents in cache. This
only happens when a lot of packets are received without sending
packages every now and then. Also flushing the receive buffers
in the transmit function makes no sense and can be removed.

Signed-off-by: Stefan Theil <stefan.theil@mixed-mode.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:42 +01:00
Michal Simek
0bf3f9cb27 arm64: zynqmp: Protect board_late_init function
Function should be compiled only when CONFIG_BOARD_LATE_INIT is defined.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:42 +01:00
Michal Simek
f11d4ab0b3 arm64: zynqmp: Do not protect zynqmp_pmufw_version()
There is hard dependency for CLK_ZYNQMP to have zynqmp_pmufw_version()
but also FPGA code is calling this function which is possible to use
without actual CLK_ZYNQMP firmware driver to be enabled.
This patch enables the case where only fixed-clock CLK setup is used.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:42 +01:00
Michal Simek
25aed77f51 mmc: zynq: Remove unused pwrseq variable
This variable was incorrectly added by:
"mmc: zynq_sdhci: Add support for SD3.0"
(sha1: d1f4e39d58)
which had nothing to do with MMC power sequence provider.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:42 +01:00
Michal Simek
a19eb356cc arm64: zynqmp: Enable 2 NAND chips for zc1751 dc2
This board contains 2 nand chips that's why enable this feature.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:42 +01:00
T Karthik Reddy
97fca6a146 mtd: nand: arasan_nfc: Add support for nand multi chip select
This patch adds support for nand multi chip select.
Also adding CONFIG_SYS_NAND_MAX_CHIPS to Kconfig to specify maximum number
of nand chips.

Signed-off-by: Tummala Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:42 +01:00
Michael Tretter
16c78cba92 tools: zynqmpimage: round up partition size
The FSBL copies "Total Partition Word Length" * 4 bytes from the boot.bin,
which implies that the partition size is 4 byte aligned. When writing the
partition, mkimage calculates "Total Partition Word Length" by dividing
the size by 4. This implicitly cuts unaligned bytes at the end of the
added binary.

Instead of rounding down, the size must be round up to 4 bytes and the
binary padded accordingly.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Reviewed-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:42 +01:00
Tom Rini
aff66f22d6 Merge tag 'mips-pull-2019-01-23' of git://git.denx.de/u-boot-mips
- MIPS: mscc: ocelot: add ethernet switch and network support
- MIPS: mscc: add support for ServalT SoC family
- MIPS: mscc: add support for Serval SoC family
2019-01-23 17:24:31 -05:00
Joakim Tjernlund
45e81f9ab3 mpc85xx: Add support for -msingle-pic-base
-msingle-pic-base is a new gcc(from 4.6) option for ppc and
it reduces the size of my u-boot with about 4-5 KB.
While at it, add -fno-jump-tables too to save a
few more bytes.

e5500 core:
size u-boot.bef
   text	   data	    bss	    dec	    hex	filename
 473043	  23772	 307104	 803919	  c444f	u-boot.bef
size u-boot.aft
   text	   data	    bss	    dec	    hex	filename
 453195	  23772	 307104	 784071	  bf6c7	u-boot.aft

e500 core:
size u-boot.bef
   text	   data	    bss	    dec	    hex	filename
 292998	  17868	  24968	 335834	  51fda	u-boot.bef
size u-boot.aft
   text	   data	    bss	    dec	    hex	filename
 288002	  17868	  24968	 330838	  50c56	u-boot.aft

Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-23 10:48:48 -08:00
Horatiu Vultur
a834cb817f MSCC: Add board support for Serval SoC family.
Add board support and configuration for Jaguar2 SoC family.
The detection of the board type is based on the phy ids.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-23 18:28:09 +01:00
Horatiu Vultur
6621288838 MSCC: Add device tree for Serval pcb106 board
Add device tree based on evaluation board pcb106.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-23 18:28:09 +01:00
Horatiu Vultur
dda17e39c1 MSCC: add device tree for Serval pcb105 board
Add device tree based on evaluation board pcb105.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-23 18:28:09 +01:00
Horatiu Vultur
1895b87e84 MSCC: Add support for Serval SoC family.
As Ocelot, Servalt, Luton and Jaguar2, this family of SoCs are
found in Microsemi Switches solution.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-23 18:28:09 +01:00
Horatiu Vultur
5c31ce36e3 pinctrl: mscc: Add gpio and pinctrl for Serval SoC family.
The Serval SoC family has 32 pins. Currently there is no
support for Serval in Linux kernel.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-23 18:28:09 +01:00
Horatiu Vultur
036d95958b MSCC: Add board support for Servalt SoC family
Add board support, configuration and DTS for Servalt SoC
family. Currently there is one board in this family.

Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-23 18:27:26 +01:00
Horatiu Vultur
055125171a MSCC: Add support for Servalt SoC family.
As Ocelot, Luton and Jaguar2, this family of SoCs are found
in Microsemi Switches solution.

Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-23 18:27:26 +01:00
Horatiu Vultur
177c07f829 pinctrl: mscc: Add gpio and pinctrl for Servalt SoC family.
The Servalt SoC family has 36 pins. Currently there is not support
for Servalt pinctrl in Linux kernel.

Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-23 18:27:26 +01:00
Gregory CLEMENT
37dd373f82 configs: mscc_ocelot: add network support
Now that network support is added for the ocelot platform, let's add it
in the default configuration.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-01-23 18:26:44 +01:00
Gregory CLEMENT
2f8d067736 MIPS: mscc: ocelot: add switch reset support
On some ocelots platform a workaround is needed in order to be able to
reset the switch without resetting the DDR.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-01-23 18:26:44 +01:00
Gregory CLEMENT
c8546163fa net: add MSCC Ocelot switch support
This patch adds support for the Microsemi Ethernet switch present on
Ocelot SoCs.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-23 18:26:44 +01:00
Gregory CLEMENT
55037902b8 MIPS: mscc: ocelot: Add ethernet nodes for Ocelot
Import Ethernet related nodes from Linux

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-01-23 18:25:43 +01:00
Tom Rini
7794fe2c8c Merge git://git.denx.de/u-boot-nds32
- Support nds32 prebuilt toolchain.
- Fix some compile issues.
- Fix dts mmc node compatible string.
2019-01-22 22:00:20 -05:00
Rick Chen
866ab879c9 nds32: dts: Fix mmc node compatible string
In the two commits:
cf3922dddc
mmc: ftsdc010_mci: Sync compatible with DT mmc node

c14e90e844
riscv: dts: Sync DT with Linux Kernel

ftsdc010_mci's compatible has been modified as
"andestech,atfsdc010" for RISC-V synchronization.
But ae3xx.dts and ag101p.dts which are used for
nds32 adp-ae3xx and adp-ag101p platforms did not
be modified correctly at that time. It will cause
mmc detection failure. Fix it here.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
2019-01-22 17:36:20 +08:00
Rick Chen
e690148223 nds32: Fix boot fail issue when build with elf-mculib.
Add -mcmodel=large can let elf-mculib have
the same default behavior just like linux-glibc.
And it help to pass U-Boot booting sequence.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
2019-01-22 17:36:04 +08:00
Rick Chen
9135858fb8 nds32: Generate SW fpu instruction.
Force it to generate SW fup instruction.
It help to avoid bugs when running on no-HW-fpu board, but
compile with v3f which support HW fpu instruction.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
2019-01-22 17:35:57 +08:00
Rick Chen
28c107f05e nds32: Remove gcc unused option
-G0 is an old option, not support now,
So remove it.
It can help to fix compile error when
build with nds32 pre-build toolchain.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
2019-01-22 17:35:53 +08:00
Rick Chen
f715ed4591 .travis.yml: Support nds32 prebuilt toolchain
Download nds32 prebuild toolchain from github
which is base on gcc 8.0.1 version for regression.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
2019-01-22 17:35:47 +08:00
Tom Rini
e8ddbefccd Merge git://git.denx.de/u-boot-marvell
- Sync Armada-38x dts with Linux 4.20 from Chris
- Misc changes and enhancements to Turris Mox (v4) from Marek
- Reserve PSCI area for Armada 8k from Heinrich
- New Allied Telesis x530 board (Armada-385) from Chris
- Misc minor changes (defconfig etc)
2019-01-21 11:59:21 -05:00
Tom Rini
27fb313dd6 Merge git://git.denx.de/u-boot-mpc83xx 2019-01-21 11:59:00 -05:00
Tom Rini
82eeb71ae9 Revert "env: sf: fix environment in SPI NOR"
Per Heiko the original changes were correct and something is misbehaving
on his hardware.

This reverts commit 3d5931e598.

Signed-off-by: Tom Rini <trini@konsulko.com>
2019-01-21 11:57:58 -05:00
Derald D. Woods
49ad40298c ARM: at91: Convert SPL_GENERATE_ATMEL_PMECC_HEADER to Kconfig
This commit converts the following items to Kconfig:

CONFIG_ATMEL_NAND_HWECC
CONFIG_ATMEL_NAND_HW_PMECC
CONFIG_PMECC_CAP
CONFIG_PMECC_SECTOR_SIZE
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER

[PMECC References]
https://www.at91.com/linux4sam/bin/view/Linux4SAM/PmeccConfigure
https://www.at91.com/linux4sam/bin/view/Linux4SAM/AT91Bootstrap

[Mailing List Thread]
https://lists.denx.de/pipermail/u-boot/2018-December/350666.html

Fixes: 5541543f ("configs: at91: Remove CONFIG_SYS_EXTRA_OPTIONS assignment")
[trini: Make the migration be size neutral and possibly not fix the
above in all cases]
Reported-by: Daniel Evans <photonthunder@gmail.com>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-01-21 08:36:11 -05:00
Chris Packham
0e31666dfa ARM: mvebu: add support for Allied Telesis x530
This is a range of stackable network switches. The SoC is Armada-385 and
there are a number of variants with differing network port
configurations. The DP variants are intended for a harsher operating
environment so they use a different i2c mux and fit industrial-temp
parts.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-01-21 11:39:50 +01:00
Baruch Siach
0e62072968 board: mvebu: drop unused ETH_PHY macro definitions
These macros are not used anywhere in the boards code.

Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Dennis Gilmore <dgilmore@redhat.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-01-21 11:39:50 +01:00
Heinrich Schuchardt
357766365d arm64: mvebu: defconfig: enable CONFIG_CMD_NVME
An NVME drive may be installed on the MACCHIATObin board using the PCIe
slot or on the Clearfog Pro using mini a PCI-e slot. With the configuration
change it becomes usable.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-01-21 11:39:50 +01:00
Heinrich Schuchardt
cf63dad014 arm64: dts: marvell: armada-ap806: reserve PSCI area
The memory area [0x4000000-0x4200000[ is occupied by the PSCI firmware. Any
attempt to access it from U-Boot leads to an immediate crash.

So let's make the same memory reservation as the vendor device tree.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-01-21 11:39:50 +01:00
Marek Behún
7a6f60d6fe arm: mvebu: configs: turris_mox: Add 64 MiB of boot memory
This is needed for some scenarios, such as booting large FIT image.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-01-21 11:39:50 +01:00
Marek Behún
3b281aca41 arm: mvebu: turris_mox: Support 1 GB version of Turris Mox
Use get_ram_size to determine if the RAM size on Turris Mox is 512 MiB
or 1 GiB.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-01-21 11:39:50 +01:00
Marek Behún
c87b87006b arm: mvebu: turris_mox: Read info (and ethaddrs) from OTP
Add support for reading One-Time Programmable memory via mailbox, which
communicates with CZ.NIC's firmware on the Secure Processor (Cortex-M3)
of Armada 3720.

Display product serial number and additional info, and also set MAC
addresses.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-01-21 11:39:50 +01:00
Marek Behún
da1f799700 MAINTAINERS: Add entry for CZ.NIC's Turris project
Add myself as the maintainer of CZ.NIC's Turris Omnia and Turris Mox
projects.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-01-21 11:39:50 +01:00
Marek Behún
7b03e9969c watchdog: armada_37xx: Fix compliance with kernel's driver
The Armada 37xx watchdog driver was recently accepted for mainline
kernel by watchdog subsystem maintainer, but the driver works a little
different than the one in U-Boot. This patch fixes this.

In the previous implementation there was a tiny period of time when the
watchdog was disabled and the system was vulnerables - this was during
pinging, which was done by disabling, setting, and enabling the counter.

Now pinging is done without disabling the watchdog. We use 2 counters:
Counter 1 is the watchdog counter - on expiry, the system is reset.
Counter 0 is used to reset Counter 1 to start counting from the set
timeout again. So Counter 1 is set to be reset on Counter 0 expiry event
event and pinging is done by forcing an immediate expiry event on
Counter 0.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-01-21 11:39:49 +01:00
Marek Behún
6e8e1dcf7d arm: mvebu: turris_mox: Update defconfig
Add gpio command to defconfig - this can be used to detect whether the
button is pressed or light LEDs.
Add DS1307 RTC driver and the date command.
Add CONFIG_WATCHDOG, so that U-Boot calls watchdog_reset.
Add CONFIG_MISC_INIT_R so that ethernet addresses are read from OTP
before network controller is initialized.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-01-21 11:39:49 +01:00
Marek Behún
3dc2f4549c arm: mvebu: dts: Fix Turris Mox device tree
DTC issues a warning because #address-cells and #size-cells properties
are not set in the mdio node.
Also add ethernet1 alias.
Also add RTC node.
Also fix USB3 regulator startup delay time.
Also fix PCI Express SERDES speed to 5 GHz (this is only cosmetic, the
speed value is not used byt the comphy driver for PCI Express, but
should be 5 GHz nonetheless).

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-01-21 11:39:49 +01:00
Marek Behún
7dd7c2e796 arm: mvebu: turris_mox: Check and configure modules
Check if Mox modules are connected in supported mode, then configure
the MDIO addresses of switch modules.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-01-21 11:39:49 +01:00
Marek Behún
9433cd1109 arm: mvebu: turris_mox: Change SERDES map depending on module topology
When SFP module is connected directly to CPU module we want the SGMII
lane speed at 1.25 Gbps.

This is a temporary solution till there is a comphy driver in the kernel
capable of changing SGMII speed at runtime.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-01-21 11:39:49 +01:00
Marek Behún
296c64ea41 arm: mvebu: turris_mox: Cosmetic restructurization
Restructure the board initialization source.
Remove the module_topology environment variable since it won't be
needed.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-01-21 11:39:49 +01:00
Chris Packham
30c4383da3 ARM: mvebu: sync Armada-38x dts with Linux 4.20
Sync the Armada-38x device tree files with Linux 4.20-rc5. The changes
not taken are new compatible strings for the uart and nand flash
controller. The nand binding is best updated if/when the mtd/nand
infrastructure is updated.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-01-21 11:39:49 +01:00
Joakim Tjernlund
64d68dcdd7 mpc83xx: Add support for -msingle-pic-base
-msingle-pic-base is a new gcc(from 4.6) option for ppc and
it reduces the size of my u-boot with about 4 KB.
While at it, add -fno-jump-tables too to save a
few more bytes.

Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com>
Reviewed-by: Mario Six <mario.six@gdsys.cc>
Tested-by: Mario Six <mario.six@gdsys.cc> (on MPC8308)
2019-01-21 08:33:42 +01:00
Philipp Tomsich
2acc24fc28 Kconfig: Migrate BOUNCE_BUFFER
The bounce buffer is used by a few drivers (most of the MMC drivers)
to overcome limitations in their respective DMA implementation.

This moves the configuration to Kconfig and makes it user-selectable
(even though it will be a required feature to make those drivers
work): the expected usage is for drivers depending on this to 'select'
it unconditionally from their respective Kconfig (see follow-up
patches).

This commit includes a full migration using moveconfig.py to ensure
that each commit compiles.  To ensure bisectability we update
dependencies of various drivers to now select BOUNCE_BUFFER when needed.

[trini: Squash all patches to ensure bisectability]
Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Otavio Salvador <otavio@ossystems.com.br> [dw_mmc portion]
Reviewed-by: Fabio Estevam <festevam@gmail.com> [mxsmmc portion]
Reviewed-by: Simon Glass <sjg@chromium.org> [tegra portion]
2019-01-19 09:49:26 -05:00
Tom Rini
599fb3bc95 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2019-01-19 09:39:42 -05:00
Tom Rini
77c07e7ed3 Merge tag 'fsl-qoriq-for-v2019.04-rc1' of git://git.denx.de/u-boot-fsl-qoriq
Add TFA boot flow for more boards

Add TFA boot defconfig for ls1088a and ls2088a.
Add dts fixup for PCIe endpoint and root complex.
2019-01-18 23:11:51 -05:00
Tom Rini
c4d323793b Merge branch '2019-01-18-master-imports'
- Bugfix for SPI environment optimization
- Spelling fixes
- Remove some defconfigs per various maintainers
- Minor db410, bananapi r2 fixes
- Bump QEMU to v3.1.0 for most platforms
2019-01-18 13:40:41 -05:00
Heiko Schocher
3d5931e598 env: sf: fix environment in SPI NOR
commit 9a9d66f5ef ("env: add spi_flash_read_env function")

breaks Environment functionality, as it reads only
until 2 \0 are found, but fills the buffer with 0x0
instead 0xff which leads in an incorrect crc sum.

Fix: init the read buffer with 0xff instead 0x00

Signed-off-by: Heiko Schocher <hs@denx.de>
2019-01-18 13:40:36 -05:00
Felix Brack
2c3ec20fcc arm: dts: am335x-pdu001: Sync with Linux 5.0-rc2
This patch synchronizes the PDU001 board DTS file with the one used by
Linux 5.0-rc2.
Signed-off-by: Felix Brack <fb@ltec.ch>
2019-01-18 13:40:35 -05:00
Faiz Abbas
8fa7f65dd0 configs: Remove am335x_boneblack_defconfig
The am335x_evm_defconfig supports all am335x_boneblack variants. Remove
the redundant am335x_boneblack_defconfig.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-01-18 13:40:35 -05:00
Felix Brack
8f0d44cb3e arm: am335x-pdu001: Remove SPI support
On this board SPI is only used to configure the SoC driving the LC TFT
display which is not used in U-Boot. Hence remove SPI support.

Signed-off-by: Felix Brack <fb@ltec.ch>
2019-01-18 13:40:35 -05:00
Quentin Schulz
a645831ca0 cmd: mtd: fix compilation warning for help when SYS_LONGHELP=n
cmd/mtd.c:447:13: warning: ‘mtd_help_text’ defined but not used [-Wunused-variable]
static char mtd_help_text[] =
            ^~~~~~~~~~~~~

When SYS_LONGHELP is not defined. After looking at how other commands
work, we should surround the whole help text (even its declaration) with
an #ifdef CONFIG_SYS_LONGHELP, since it's compiled out when calling
_CMD_HELP[1] on the help text variable argument to U_BOOT_CMD.

[1] https://elixir.bootlin.com/u-boot/latest/source/include/command.h#L181

Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-01-18 13:40:34 -05:00
Michal Simek
facdc5fb83 travis: Switch QEMU to 3.1.0 version
Vexpress ca15_tc2 is failing with 3.1.0 because of QEMU issue.
When this patch is applied
https://patchwork.kernel.org/patch/10754401/
Vexpress can be also turn to newer QEMU version.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-01-18 13:40:34 -05:00
Michal Simek
984a1feb71 travis: Setup QEMU_VERSION as variable
This change enables setting up specific Qemu version or sha1 for new
targets which are added after (current) v3.0.0 version.
This changes is preparation step for adding new Xilinx Versal Virt
platform which was merge after v3.0.0.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-01-18 13:40:34 -05:00
Tom Rini
aa13261215 travis: Break up the NXP Layerscape jobs more
The single job for all Layerscape 10xx platforms is close to, and
sometimes exceeds the time limit for a single job configuration.  Break
this down into jobs for LS101x, LS104x and LS108x instead.  While in
here, in the name portion of these jobs, refer to them as NXP for ARM
and not Freescale as they've been NXP for quite some time.

Signed-off-by: Tom Rini <trini@konsulko.com>
2019-01-18 13:40:30 -05:00
Jagan Teki
543049ab59 usb: host: Drop [e-o]hci-sunxi drivers
Now Allwinner platform is all set to use Generic USB
controller drivers, so remove the legacy sunxi drivers.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
29d280c88a sunxi: usb: Switch to Generic host controllers
Onc of key blocker for using USB Generic host controller
drivers in Allwinner are CLK and RESET drivers, now these
available for USB usage.

So switch sunxi USB use EHCI and OHCI Generic controllers.

Enabling USB is wisely a board choise, So Enable USB_OHCI_HCD
where it already have USB_EHCI_HCD

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
b9aa0a9332 musb-new: sunxi: Use CLK and RESET support
Now clock and reset drivers are available for respective
SoC's so use clk and reset ops on musb driver.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2019-01-18 22:19:09 +05:30
Jagan Teki
652ee2788f reset: Add reset valid
Add reset_valid to check whether given reset is valid
or not.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
089ffd0aed phy: sun4i-usb: Use CLK and RESET support
Now clock and reset drivers are available for respective
SoC's so use clk and reset ops on phy driver.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2019-01-18 22:19:09 +05:30
Jagan Teki
e236ff0a51 arm: sunxi: Enable CLK, RESET
CLK and DM_RESET drivers are now available for all of
the Allwinner platforms, so enable them in arch/arm/Kconfig

Enabling CLK will select DM_RESET by default.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
aa86bf90d1 sunxi: A64: Update sun50i-a64-ccu.h
Update sun50i-a64-ccu.h from the Linux sunxi/dt64-for-4.20 tree:
commit 679294497be31596e1c9c61507746d72b6b05f26
Author: Rodrigo Exterckötter Tjäder <rodrigo@tjader.xyz>
Date:   Wed Sep 26 19:48:24 2018 +0000
    arm64: dts: allwinner: a64: a64-olinuxino: set the PHY TX delay

This should be a part of previous sync patch from
commit 1b39a1834e
Author: Andre Przywara <andre.przywara@arm.com>
Date:   Mon Oct 29 00:56:47 2018 +0000

    sunxi: A64: Update .dts/.dtsi files

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
6901aab8e3 clk: sunxi: Add Allwinner A80 CLK driver
Add initial clock driver for Allwinner A80.

- Implement UART bus clocks via ccu_clk_gate table for
  A80, so it can accessed in common clk enable and disable
  functions from clk_sunxi.c
- Implement UART bus resets via ccu_reset table for A80,
  so it can accessed in common reset deassert and assert
  functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
8dcc7e6922 ARM: dts: sun8i: Update A80 dts(i) from Linux-v4.18-rc3
Update all A80 devicetree dtsi and dtsi files from
Linux-v4.18-rc3 with below commits.

arch/arm/boot/dts/sun9i-a80*:

commit 190e3138f9577885691540dca59c2f07540bde04
Merge: cafc87023b0d a7affb13b271
Author: Arnd Bergmann <arnd@arndb.de>
Date:   Tue Mar 27 14:58:00 2018 +0200

    Merge tag 'sunxi-h3-h5-for-4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt

include/dt-bindings/*/sun9i-a80-*:

commit 783ab76ae553abc23f80ef7511052d055697531b
Author: Chen-Yu Tsai <wens@csie.org>
Date:   Sat Jan 28 20:22:36 2017 +0800

    clk: sunxi-ng: Add A80 Display Engine CCU

Note: sun9i-a80-cx-a99.dts is updated only uart0, since the same
dts is not available in Linux.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
337fcdc06b clk: sunxi: Add Allwinner H6 CLK driver
Add initial clock driver for Allwinner H6.

- Implement UART bus clocks via ccu_clk_gate table for
  H6, so it can accessed in common clk enable and disable
  functions from clk_sunxi.c
- Implement UART bus resets via ccu_reset table for H6,
  so it can accessed in common reset deassert and assert
  functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
8606f960d4 clk: sunxi: Implement UART resets
Implement UART resets for all relevant Allwinner SoC
clock drivers via ccu reset table.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
4acc711930 clk: sunxi: Implement UART clocks
Implement UART clocks for all Allwinner SoC
clock drivers via ccu clock gate table.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
6239a6d092 clk: sunxi: Add Allwinner V3S CLK driver
Add initial clock driver for Allwinner V3S.

- Implement USB bus and USB clocks via ccu_clk_gate table
  for V3S, so it can accessed in common clk enable and disable
  functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table
  for V3S, so it can accessed in common reset deassert
  and assert functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
78eb2a41f3 clk: sunxi: Add Allwinner R40 CLK driver
Add initial clock driver for Allwinner R40.

- Implement USB bus and USB clocks via ccu_clk_gate
  for R40, so it can accessed in common clk enable
  and disable functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table
  for R40, so it can accessed in common reset deassert
  and assert functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
03d87f5909 clk: sunxi: Add Allwinner A83T CLK driver
Add initial clock driver for Allwinner A83T.

- Implement USB bus and USB clocks via ccu_clk_gate table
  for A83T, so it can accessed in common clk enable and
  disable functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table
  for A83T, so it can accessed in common reset deassert
  and assert functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
3ab029368a clk: sunxi: Add Allwinner A23/A33 CLK driver
Add initial clock driver for Allwinner A23/A33.

- Implement USB bus and USB clocks via ccu_clk_gate table
  for A23/A33, so it can accessed in common clk enable and
  disable functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table
  for A23/A33, so it can accessed in common reset deassert
  and assert functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
4927e2e8d3 clk: sunxi: Add Allwinner A31 CLK driver
Add initial clock driver for Allwinner A31.

- Implement USB ahb1 and USB clocks via ccu_clk_gate table
  for A31, so it can accessed in common clk enable and disable
  functions from clk_sunxi.c
- Implement USB ahb1 and USB resets via ccu_reset table
  for A31, so it can accessed in common reset deassert
  and assert functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
c8e743c1e8 clk: sunxi: Add Allwinner A10s/A13 CLK driver
Add initial clock driver for Allwinner A10s/A13.

- Implement USB ahb and USB clocks via ccu_clk_gate table
  for A10s/A13, so it can accessed in common clk enable and
  disable functions from clk_sunxi.c
- Implement USB resets via ccu_reset table for A10s/A13,
  so it can accessed in common reset deassert and assert
  functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:08 +05:30
Jagan Teki
6590bd8c47 clk: sunxi: Add Allwinner A10/A20 CLK driver
Add initial clock driver for Allwinner A10/A20.

- Implement USB ahb and USB clocks via ccu_clk_gate table
  for A10/A20, so it can accessed in common clk enable and
  disable functions from clk_sunxi.c
- Implement USB resets via ccu_reset table for A10/A20,
  so it can accessed in common reset deassert and assert
  functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:08 +05:30
Jagan Teki
e945816efb clk: sunxi: Add Allwinner H3/H5 CLK driver
Add initial clock driver for Allwinner H3/H5.

- Implement USB bus and USB clocks via ccu_clk_gate table for
  H3/H5, so it can accessed in common clk enable and disable
  functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table for
  H3/H5, so it can accessed in common reset deassert and assert
  functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:08 +05:30
Jagan Teki
99ba430870 reset: Add Allwinner RESET driver
Add common reset driver for all Allwinner SoC's.

Since CLK and RESET share common DT compatible, it is CLK driver
job is to bind the reset driver. So add CLK bind call on respective
SoC driver by passing ccu map descriptor so-that reset deassert,
deassert operations held based on ccu reset table defined from
CLK driver.

Select DM_RESET via CLK_SUNXI, this make hidden section of RESET
since CLK and RESET share common DT compatible and code.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:08 +05:30
Jagan Teki
0d47bc7056 clk: Add Allwinner A64 CLK driver
Add initial clock driver for Allwinner A64.

Implement USB clock enable and disable functions for
OHCI, EHCI, OTG and USBPHY gate and clock registers
via ccu clk gate table.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:08 +05:30
Aleksandr Aleksandrov
7d659573ce board: sun50i-h5: Add Emlid Neutis N5 support
Emlid Neutis N5 is a SoM based on Allwinner H5, has a WiFi & BT
module, DDR3 RAM and eMMC.

- add neutis-devboard target to dtb makefile
- add dtsi file for Neutis N5 needs
- add config file for Neutis N5 Dev board

Signed-off-by: Aleksandr Aleksandrov <aleksandr.aleksandrov@emlid.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
[jagan: update proper commit head]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-01-18 22:19:08 +05:30
Stefan Mavrodiev
da1ae5905e sunxi: board: Add i2c initialization for sun50i
To use TWI0/1/2 the user can select CONFIG_I2C#_ENABLE.
However even the controller is enabled, the mux for the pins
are not set.

This patch follows the existing mux method. Since the pads are
different, separate check is added for each i2c.

Tested with A64-SOM204 board.

Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-18 22:19:08 +05:30
Vignesh R
cec96b83a0 configs: Remove am43xx_evm_ethboot_defconfig
am43xx_evm_ethboot_defconfig is not being actively used and has not been
moved to DM or DT. Also, ethboot cannot be tested on AM43xx EVM as such
due EVM limitations. Therefore delete it.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-01-18 09:26:14 -05:00
Vignesh R
311e658ef3 configs: Remove unused am335x_evm defconfigs
These defconfigs don't seem be actively used any more, and have not been
moved to adapt DM or DT. Therefore delete them.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-01-18 09:26:14 -05:00
Vignesh R
4a1e5f92f7 configs: am335x_evm: Enable DM_SPI and DM_SPI_FLASH
Enable DM_SPI and DM_SPI_FLASH for actively used defconfigs for
am335x_evm.

Signed-off-by: Vignesh R <vigneshr@ti.com>
2019-01-18 09:26:14 -05:00
Frank Wunderlich
f3af98eca5 adding saveenv-command for bananapi r2
bananapi r2 can be booted from sd-card and emmc
saving the environment have to choose the storage
from which the device has booted

also the offset is set to 1MB to make sure env is written
to block "user data area" between uboot and first partition

https://www.fw-web.de/dokuwiki/lib/exe/fetch.php?cache=&media=bpi-r2:boot-structure.png

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2019-01-18 09:26:04 -05:00
Patrick Wildt
5d94158aa9 mkimage: fixup CONFIG_FIT_EXTERNAL_OFFSET
The last parameter is expected to be the imagefile.  Since -E is a
flag having the output name before -p will make mkimage ignore the
external offset option.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
2019-01-18 09:16:15 -05:00
Chris Packham
6e7051144f lib: Kconfig: spelling fixes
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-18 09:16:15 -05:00
Chris Packham
8e34c1d34a video: Kconfig: spelling fixes
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-01-18 09:16:15 -05:00
Chris Packham
cb4d1bbe51 pinctrl: Kconfig: spelling fixes
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-18 09:16:15 -05:00
Chris Packham
7475145449 i2c: Kconfig: spelling fixes
Signed-off-by: Chris Packham <judge.packham@gmail.com>
2019-01-18 09:16:15 -05:00
Chris Packham
83e7a4d597 drivers: Kconfig: spelling fixes
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-18 09:16:15 -05:00
Chris Packham
d7a4af45c5 work_92105: Kconfig: spelling fixes
Signed-off-by: Chris Packham <judge.packham@gmail.com>
2019-01-18 09:16:15 -05:00
Chris Packham
9259c92386 x86: Kconfig: spelling fixes
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-18 09:16:15 -05:00
Chris Packham
d7cf868f88 arm: Kconfig: spelling fixes
Signed-off-by: Chris Packham <judge.packham@gmail.com>
2019-01-18 09:16:15 -05:00
Chris Packham
2dcfa05852 common: spl: Kconfig: spelling fixes
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-18 09:16:15 -05:00
Chris Packham
3aeb771cbc Kconfig: fix spelling
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-18 09:16:15 -05:00
Heinrich Schuchardt
7de24b27d2 disk: efi: GUIDs should be const
Make system_guid const.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-18 09:16:15 -05:00
Ramon Fried
8d24a4776a mach-snapdragon: db410: pinctrl: fix pin count
Pin count in APQ8016 was wrong, fix that.

Fixes: ad97051b7f ("mach-snapdragon: Introduce pinctrl driver")
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2019-01-18 09:16:15 -05:00
Ramon Fried
b12e6945e9 dts: db410: fix indentation
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2019-01-18 09:16:15 -05:00
Tom Rini
f83ef0dac8 Merge tag 'mips-pull-2019-11-16' of git://git.denx.de/u-boot-mips
- MIPS: mscc: various enhancements for Luton and Ocelot platforms
- MIPS: mscc: added support for Jaguar2 platform
- MIPS: optimised SPL linker script
- MIPS: bcm6368: fix restart flow issues
- MIPS: fixed CONFIG_OF_EMBED warnings for all MIPS boards
- MIPS: mt7688: small fixes and enhancements
- mmc: compile-out write support if disabled
2019-01-17 19:12:55 -05:00
Tom Rini
e964df1e2a Merge branch '2019-01-16-master-imports'
- Fixes for CVE-2018-18440 and CVE-2018-18439
- Patch to allow disabling unneeded NAND ECC layouts
- Optimize SPI flash env read process
2019-01-17 17:42:03 -05:00
York Sun
a200ebea63 armv8: ls2088ardb: Update MAINTAINERS
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Rajesh Bhagat <rajesh.bhagat@nxp.com>
2019-01-17 13:17:51 -08:00
York Sun
55dbfdadd2 armv8: ls1088ardb: Update MAINTAINERS
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Rajesh Bhagat <rajesh.bhagat@nxp.com>
2019-01-17 13:17:51 -08:00
Rajesh Bhagat
220ce489a4 armv7: dts: ls1021a: Remove aliases property name warning
Remove aliases property name warning while compilation:
Warning (alias_paths): /aliases: aliases property name must
include only lowercase and '-'

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:17:45 -08:00
Xiaowei Bao
59a557f360 pci: layerscape: Add the dts fixup for EP and RC
Add the dts fixup when PCI controller work diffferent mode.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:17:40 -08:00
Xiaowei Bao
87e0d2b9ac pci: layerscape: Do not scan when PEX work in EP mode
Don't scan the bus when the PEX work in EP mode.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:17:33 -08:00
Xiaowei Bao
5bd3c9d556 pci: layerscape: Modify the EP and RC mode judge method
Modify the RC and EP mode judge method, save the mode as a variable,
the variable will be used by other function.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:17:28 -08:00
Florinel Iordache
bae54ac99e ls1046aqds: Bypass xfi port fixup for KR mode
u-boot makes a fixup for LS1046AQDS board to setup the properties
'fixed-link' and 'phy-connection-type' to 'xgmii' but in case of
backplane mode this fixup is not correct because it causes the KR link
to fail and so it must be bypassed in order to keep the link in KR
mode as it is defined in DTS.

Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
[YS: Fix compiling warning]
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:17:21 -08:00
Laurentiu Tudor
a954f6fe70 armv8: fsl-layerscape: properly configure qdma ICID
The ICIDs for the qdma device are not configured through SCFG but
through some registers found in the actual device register block.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:17:15 -08:00
Yinbo Zhu
7a0425dd96 mmc: fsl_esdhc: make get_cd work well in dm_mmc_ops
This patch is to make get_cd work well when DM_MMC enabled

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:17:10 -08:00
Mian Yousaf Kaukab
7e96804975 fsl-layerscape: dpaa: fix fsl-mc status in fdt with bootefi
fsl-mc lazyapply command applies dpl from efi_exit_boot_services().
Status of fsl-mc node in working fdt is updated at this stage.
However, an efi application like grub may already have copied the fdt.
So the updates to fdt done at efi_exit_boot_services() may not be
visible to the OS. Fix it by updating fdt earlier if fsl-mc lazyapply
command is used.

Fixes: b7b8410a8f (ls2080: Exit dpaa only right before exiting U-Boot)
Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:16:49 -08:00
Hou Zhiqiang
5b994e85a5 armv8: ls1043a: correct the PCIe INTx fixup
On LS1043A rev1.0 there are 4 interrupt pins for INTx, and on
rev1.1 there is only 1 for INTx, so the current fixup is inverse
of the fact.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:16:44 -08:00
Hou Zhiqiang
ec88ff80ff armv8: ls1043a: add SVR definitions for 23x23 package silicon
LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:16:40 -08:00
Rajesh Bhagat
fc16f99949 configs: update TFABOOT defconfigs for SD boot support
update TFABOOT defconfig for SD boot on below NXP chasis2
and chasis3 platforms:

ls1043a, ls1046a, ls1088a and ls2088a.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:16:35 -08:00
Rajesh Bhagat
43d17c485f env: fix allow to build multiple environments
Patch fixes build error when enabling CONFIG_ENV_IS_IN_SPI_FLAS
and CONFIG_ENV_IS_IN_MMC at the same time mentioned issue in
below link:

Refer: https://lists.denx.de/pipermail/u-boot/2018-February/319565.html

build error when enabling CONFIG_ENV_IS_IN_SPI_FLASH and
CONFIG_ENV_IS_IN_MMC at the same time.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:16:31 -08:00
Rajesh Bhagat
1908201cae armv8: ls2088aqds: Add TFABOOT support
TFABOOT support includes:
 - ls2088aqds_tfa_defconfig to be loaded by trusted firmware
 - environment address and size changes for TFABOOT

Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:16:26 -08:00
Rajesh Bhagat
9570df03ee armv8: ls2088ardb: Add TFABOOT support
TFABOOT support includes:
  - ls2088ardb_tfa_defconfig to be loaded by trusted firmware
  - environment address and size changes for TFABOOT
  - define BOOTCOMMAND for TFABOOT
  - remove EL3 specific erratas for TFABOOT

Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:16:22 -08:00
Pankit Garg
1a12b4a0ac armv8: ls1088aqds: Add TFABOOT support
TFABOOT support includes:
 - ls1088aqds_tfa_defconfig to be loaded by trusted firmware
 - environment address and size changes for TFABOOT
 - MC address changes for TFABOOT
 - define BOOTCOMMAND for TFABOOT
 - ifc chip select changes for TFABOOT

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:16:11 -08:00
Pankit Garg
143af3c6d5 armv8: ls1088ardb: Add TFABOOT support
TFABOOT support includes:
- ls1088ardb_tfa_defconfig to be loaded by trusted firmware
- environment address and size changes for TFABOOT
- MC address changes for TFABOOT
- define BOOTCOMMAND for TFABOOT
- ifc chip select changes for TFABOOT

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:16:04 -08:00
Pankit Garg
1f3d739a23 ls1043a: add support for nand-boot cmd for TFA
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:15:59 -08:00
Rajesh Bhagat
bf0f791087 drivers: ifc: restore the legacy flow for IFC config
Restore the legacy flow along with TFABOOT flow for
IFC configuration.

Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:15:53 -08:00
Rajesh Bhagat
d23da2ae21 armv8: fsl-layerscape: fixes for TFABOOT framework
Fixes for TFABOOT framework
- update eMMC bootsrc to SD_MMC
- Increase buffer size for mcinitcmd from 256 to 512
- Fix mcinitcmd and bootcmd for Secure Boot

Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:15:25 -08:00
Simon Goldschmidt
f8878da557 arm: bootm: fix sp detection at end of address range
This fixes  'arch_lmb_reserve()' for ARM that tries to detect in which
DRAM bank 'sp' is in.

This code failed if a bank was at the end of physical address range
(i.e. size + length overflowed to 0).

To fix this, calculate 'bank_end' as 'size + length - 1' so that such
banks end at 0xffffffff, not 0.

Fixes: 15751403b6 ("ARM: bootm: don't assume sp is in DRAM bank 0")
Reported-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2019-01-16 23:16:25 -05:00
Simon Goldschmidt
a156c47e39 tftp: prevent overwriting reserved memory
This fixes CVE-2018-18439 ("insufficient boundary checks in network
image boot") by using lmb to check for a valid range to store
received blocks.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
[trini: Always build lib/lmb.o on LMB and lib/fdtdec.o on OF_LIBFDT]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-01-16 23:15:53 -05:00
Simon Goldschmidt
a85c213f47 lmb: remove unused extern declaration
lmb.h includes an extern declaration of "struct lmb lmb;" which
is not used anywhere, so remove it.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-01-16 16:37:06 -05:00
Simon Goldschmidt
5b978dab7b bootm: use new common function lmb_init_and_reserve
This reduces duplicate code only.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-16 16:37:06 -05:00
Simon Goldschmidt
aa3c609e2b fs: prevent overwriting reserved memory
This fixes CVE-2018-18440 ("insufficient boundary checks in filesystem
image load") by using lmb to check the load size of a file against
reserved memory addresses.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-16 16:37:05 -05:00
Simon Goldschmidt
4cc8af8037 lib: lmb: extend lmb for checks at load time
This adds two new functions, lmb_alloc_addr and
lmb_get_unreserved_size.

lmb_alloc_addr behaves like lmb_alloc, but it tries to allocate a
pre-specified address range. Unlike lmb_reserve, this address range
must be inside one of the memory ranges that has been set up with
lmb_add.

lmb_get_unreserved_size returns the number of bytes that can be
used up to the next reserved region or the end of valid ram. This
can be 0 if the address passed is reserved.

Added test for these new functions.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-01-16 16:37:04 -05:00
Simon Goldschmidt
e2237a2c26 fdt: parse "reserved-memory" for memory reservation
boot_fdt_add_mem_rsv_regions() adds reserved memory sections to an lmb
struct. Currently, it only parses regions described by /memreserve/
entries.

Extend this to the more commonly used scheme of the "reserved-memory"
node.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-16 16:37:03 -05:00
Simon Goldschmidt
0f7c51a676 lib: lmb: reserving overlapping regions should fail
lmb_add_region handles overlapping regions wrong: instead of merging
or rejecting to add a new reserved region that overlaps an existing
one, it just adds the new region.

Since internally the same function is used for lmb_alloc, change
lmb_add_region to reject overlapping regions.

Also, to keep reserved memory correct after 'free', reserved entries
created by allocating memory must not set their size to a multiple
of alignment but to the original size. This ensures the reserved
region is completely removed when the caller calls 'lmb_free', as
this one takes the same size as passed to 'lmb_alloc' etc.

Add test to assert this.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-01-16 16:37:00 -05:00
Simon Goldschmidt
d67f33cf4e lmb: fix allocation at end of address range
The lmb code fails if base + size of RAM overflows to zero.

Fix this by calculating end as 'base + size - 1' instead of 'base + size'
where appropriate.

Added tests to assert this is fixed.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-01-16 16:36:48 -05:00
Simon Goldschmidt
a01ae0c23f test: add test for lib/lmb.c
Add basic tests for the lmb memory allocation code used to reserve and
allocate memory during boot.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-16 16:14:46 -05:00
Horatiu Vultur
9a9d66f5ef env: add spi_flash_read_env function
The spi_flash_read_env function is a wrapper over spi_flash_read, which
enables the env to read multiple flash page size from flash until '\0\0'
is read or the end of env partition is reached. Instead of reading the
entire env size. When it reads '\0\0', it stops reading further the env
and assumes that the rest of env is '\0'.

This is an optimization for large environments that contain few bytes
environment variables. In this case it doesn't need to read the entire
environment and only few pages.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-16 16:14:46 -05:00
Stefan Agner
a38c3af868 mtd: nand: raw: allow to disable unneeded ECC layouts
Each ECC layout consumes about 2984 bytes in the .data section. Allow
to disable the default ECC layouts if a driver is known to provide its
own ECC layout.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-01-16 16:14:45 -05:00
Stefan Roese
49f0b6bab9 mips: mt7688: gardena-smart-gateway: Enable green power LED on startup
Set the correct power-up state (default-state) of the green power LED.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16 14:00:26 +01:00
Stefan Roese
7b31c0a91d mips: mt7688: gardena-smart-gateway: Update mtdparts/mtdids for Kernel 4.19
With the new SPI NOR framework in v4.19, we need to adapt the MTD parts
so that the kernel cmdline parameter "mtdparts=" uses the correct naming
for the devices.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16 14:00:26 +01:00
Daniel Schwierzeck
10b5e96d54 MIPS: bmips: switch to CONFIG_OF_SEPARATE
Fix the Kconfig warning to not use CONFIG_OF_EMBED in defconfigs.

Based on https://patchwork.ozlabs.org/patch/1019791/

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16 13:59:46 +01:00
Daniel Schwierzeck
c285e269a2 MIPS: xilfpga: switch to CONFIG_OF_SEPARATE
Fix the Kconfig warning to not use CONFIG_OF_EMBED in defconfigs.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16 13:59:46 +01:00
Daniel Schwierzeck
764d7b33e6 MIPS: pic32mzdask: switch to CONFIG_OF_SEPARATE
Fix the Kconfig warning to not use CONFIG_OF_EMBED in defconfigs.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16 13:59:46 +01:00
Daniel Schwierzeck
a6fde6bd69 MIPS: malta: switch to CONFIG_OF_SEPARATE
Fix the Kconfig warning to not use CONFIG_OF_EMBED in defconfigs.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16 13:59:46 +01:00
Daniel Schwierzeck
7bdb526d01 MIPS: boston: switch to CONFIG_OF_SEPARATE
Fix the Kconfig warning to not use CONFIG_OF_EMBED in defconfigs.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16 13:59:46 +01:00
Horatiu Vultur
c75c908316 MSCC: Add board support for Jaguar2 SOC family
Add board support and configuration for Jaguar2 SOC family.
The detection of the board type in this family is based on the phy ids.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-16 13:56:43 +01:00
Horatiu Vultur
393b77d8f9 MSCC: add device tree for Serval2 board
Add device tree based on evaluation board pcb112.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-16 13:56:43 +01:00
Horatiu Vultur
297edaec12 MSCC: Add device tree for Jaguar2-48 board
Add device tree based on evaluation board pcb111.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-16 13:56:43 +01:00
Horatiu Vultur
d1182056d3 MSCC: Add device tree for Jaguar2 board
Add device tree based on evaluation board pcb110.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-16 13:56:43 +01:00
Horatiu Vultur
e7a0de2c31 MSCC: Add support for Jaguar2 SOC family
As the Ocelot and Luton SoCs, this family of SoCs are found
in Microsemi Switches solution.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-16 13:56:43 +01:00
Horatiu Vultur
051de9b3eb pinctrl: mscc: Add gpio and pinctrl for Jaguar2 SOC family
The Jaguar2 SOC family has 63 gpio pins therefore I extended mscc-common
to support new numbe of pins and remove any platform dependency from
mscc-common.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-16 13:56:43 +01:00
Lars Povlsen
ace9c103df mips: gpio: mscc: Obsoleted gpio-mscc-bitbang-spi.c
With the new mscc_bb_spi.c driver, there is no longer use for the
gpio-mscc-bitbang-spi.c driver.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16 13:56:43 +01:00
Lars Povlsen
6492c9168a mips: mscc: DT: Update luton device tree to use fast SPI driver
Thes patch change the luton base device tree to use the newly added
SPI bitbang driver.

It also updates the "mscc_luton_defconfig" to use the new driver.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16 13:56:43 +01:00
Lars Povlsen
fd6e0b0525 mips: spi: mscc: Add fast bitbang SPI driver
This patch add a new SPI driver for MSCC SOCs that does not sport the
designware SPI hardware controller.

Performance gain: 7.664 seconds vs. 17.633 for 1 Mbyte write.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16 13:56:43 +01:00
Ezequiel Garcia
82d5464788 mmc: jz_mmc: Compile-out write support if disabled
Do not build write support, unless it's enabled.

In the SPL case, this change will typically remove
precious bytes (as write support is most often
not needed in SPL).

This is important on this platform, where the maximum
SPL size is 14 KiB.

With gcc v7.3, this change saves 144 bytes producing:

size spl/u-boot-spl
   text	   data	    bss	    dec	    hex	filename
   9240	    752	    712	  10704	   29d0	spl/u-boot-spl

To make the code easier to compile-out and more
readable, a pair of read_data/write_data helpers are created.

Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16 13:56:43 +01:00
Ezequiel Garcia
2a4bb3d271 mmc: Use proper IS_ENABLED macro to check block support
Use CONFIG_IS_ENABLED(BLK) instead of CONFIG_BLK,
in order to fix the following build issues when
CONFIG_SPL_MMC_WRITE is selected:

drivers/mmc/mmc_write.c:69:7: error: conflicting types for 'mmc_berase'
 ulong mmc_berase(struct udevice *dev, lbaint_t start, lbaint_t blkcnt)
       ^~~~~~~~~~
In file included from drivers/mmc/mmc_write.c:15:0:
drivers/mmc/mmc_private.h:39:7: note: previous declaration of 'mmc_berase' was here
 ulong mmc_berase(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt);
       ^~~~~~~~~~
drivers/mmc/mmc_write.c:187:7: error: conflicting types for 'mmc_bwrite'
 ulong mmc_bwrite(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
       ^~~~~~~~~~
In file included from drivers/mmc/mmc_write.c:15:0:
drivers/mmc/mmc_private.h:37:7: note: previous declaration of 'mmc_bwrite' was here
 ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
       ^~~~~~~~~~

Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16 13:56:43 +01:00
Álvaro Fernández Rojas
a4ae422570 net: bcm6368: fix restart flow issues
Correctly enable/disable bcm6368-net controller to avoid flow issues.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16 13:56:43 +01:00
Daniel Schwierzeck
b8e7e5d8c5 MIPS: jz47xx: remove custom u-boot-spl.lds
There is no real difference between the generic variant and
the custom variant except that the generic variant is more
optimised. This also saves 24 Bytes in the SPL binary.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tested-by: Ezequiel Garcia <ezequiel@collabora.com>
2019-01-16 13:56:43 +01:00
Daniel Schwierzeck
2fdadc0f82 MIPS: optimize and fix ELF sections
Discard ABI related sections which are not required for debugging.
Rearrange debug sections similar to Linux. Remove the remaining
explicitely specified sections in the unused part because those
sections are not created anymore or because the linker puts them
by default at the end of the ELF binary.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tested-by: Ezequiel Garcia <ezequiel@collabora.com>
2019-01-16 13:56:43 +01:00
Lars Povlsen
4deb09632d mips: ocelot: Enable use of serial gpio for LED
This enables the use of the MSCC serial GPIO driver to control the
LEDs on the MSCC VCoreIII 'ocelot' pcb123 and pcb120.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
2019-01-16 13:56:43 +01:00
Lars Povlsen
26ad3c43a7 mips: ocelot: DT: Enable use of serial gpio
This enables the use of the MSCC serial GPIO driver on the MSCC
VCoreIII 'ocelot' SOC, and add gpio-leds nodes to the pcb123 and
pcb120 DT.

Signed-off-by: Lars Povlsen <lars.povlsen@microsemi.com>
2019-01-16 13:56:43 +01:00
Lars Povlsen
711f2dc08d mips: luton: Enable use of serial gpio for LED
This enables the use of the MSCC serial GPIO driver to control the
LEDs on the MSCC VCoreIII 'luton' SoC.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
2019-01-16 13:56:43 +01:00
Lars Povlsen
738f2b148d mips: luton: DT: Enable use of serial gpio
This enables the use of the MSCC serial GPIO driver, and add gpio-leds
nodes to the 'luton' pcb090 and pcb091 DT.

Signed-off-by: Lars Povlsen <lars.povlsen@microsemi.com>
2019-01-16 13:56:43 +01:00
Lars Povlsen
2a48c15d2e mips: mscc_sgpio: Add DT bindings documentation
This add device tree binding documentation for the MSCC serial GPIO
driver.

Signed-off-by: Lars Povlsen <lars.povlsen@microsemi.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2019-01-16 13:56:43 +01:00
Lars Povlsen
be8313feee mips: mscc_sgpio: Add the MSCC serial GPIO device (SIO)
This add support for the the MSCC serial GPIO driver in MSCC
VCoreIII-based SOCs.

By using a serial interface, the SIO controller significantly extends
the number of available GPIOs with a minimum number of additional pins
on the device. The primary purpose of the SIO controller is to connect
control signals from SFP modules and to act as an LED controller.

This adds the base driver.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
2019-01-16 13:56:43 +01:00
Lars Povlsen
e9f1492bca mips: mscc: luton+ocelot: Remove board config options, do probing
As we are moving to multi-dtb and board detection, remove static board
config options, and introduce board probing instead.

Luton: This add single-binary support for the two MSCC luton-based
reference boards - pcb090 and pcb091. The SoC chip ID is used to
determine the board type.

Ocelot: This add single-binary support for the two MSCC ocelot-based
reference boards - pcb120 and pcb123. The PHY ids on specific ports
are used to determine the board type.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
2019-01-16 13:56:43 +01:00
Lars Povlsen
e39c6783d3 mips: luton: DT: Add pcb090
This prepares individual device trees for MSCC luton-based reference
boards - pcb090 and pcb091.

Note: Even though the devices trees are quite common, they will differ
significantly in coming patches.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
2019-01-16 13:56:43 +01:00
Lars Povlsen
e58031acdc mips: mscc: Add generic GPIO control utility function
The GPIO control function can be used for controlling alternate
functions associated with a GPIO.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
2019-01-16 13:56:43 +01:00
Lars Povlsen
3098ade229 mips: mscc: Add generic PHY MIIM utility functions
The PHY MIIM utility functions can/will be used for board detection
purposes.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
2019-01-16 13:56:43 +01:00
Tom Rini
aac0c29d4b Merge tag 'dm-pull-15jan19' of git://git.denx.de/u-boot-dm
Fix recent changes to serial API for driver model
Buildman clang support and a few fixes
Small fixes to 'dm tree' and regmap test
Improve sandbox build compatibility
A few other minor fixes
2019-01-15 22:05:34 -05:00
Tom Rini
f4cfd73943 Merge branch 'master' of git://git.denx.de/u-boot-i2c 2019-01-15 22:05:28 -05:00
Tom Rini
0cd35f3920 Merge git://git.denx.de/u-boot-riscv
1. Improve cache implementation.
2. Fix and improve standalone applications
2019-01-15 22:05:05 -05:00
Tom Rini
e807f6b5f9 Merge branch '2019-01-14-master-imports'
- MediaTek improvements (eth support)
- DM conversion for HI6220
- ISEE, Toby Churchill, other platform updates
- Various format code printf fixes
- Build race fixes
- Command repeat functionality enhanced, command autocomplete support
  enhanced.
2019-01-15 20:33:07 -05:00
Boris Brezillon
03dcf17dba common: command: Add support for $ auto-completion
Add the dollar_complete() function to auto-complete arguments starting
with a '$' and use it in the cmd_auto_complete() path such that all
args starting with a $ can be auto-completed based on the available env
vars.

Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
[trini: Fix some linking problems]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-01-15 15:38:28 -05:00
Tien Fong Chee
31a2cf1ca4 misc: fs_loader: Switching private data allocation to DM auto allocation
Switching private data manual allocation to driver model auto allocation
so users no longer need to deallocate themself because this would be
deallocated by driver model when the device is no longer required.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-15 15:28:54 -05:00
Boris Brezillon
9652cfd9ee cmd: adc: Use the sub-command infrastructure
And you get sub-command auto-completion for free.

Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-01-15 15:28:54 -05:00
Boris Brezillon
9671243e8d cmd: mtd: Use the subcmd infrastructure to declare mtd sub-commands
It's way simpler this way, and we also gain auto-completion support for
free (MTD name auto-completion has been added with mtd_name_complete())

Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-01-15 15:28:54 -05:00
Boris Brezillon
c0cf06e523 command: commands: Add macros to declare commands with subcmds
Most cmd/xxx.c source files expose several commands through a single
entry point. Some of them are doing the sub-command parsing manually in
their do_<cmd>() function, others are declaring a table of sub-commands
and then use find_cmd_tbl() to delegate the request to the sub command
handler.

In either case, the amount of code to do that is not negligible and
repetitive, not to mention that almost no commands are implementing
the auto-completion hook, which means most u-boot commands lack
auto-completion.

Provide several macros to easily define commands exposing sub-commands.

Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-01-15 15:28:54 -05:00
Boris Brezillon
80a48dd47e common: command: Rework the 'cmd is repeatable' logic
The repeatable property is currently attached to the main command and
sub-commands have no way to change the repeatable value (the
->repeatable field in sub-command entries is ignored).

Replace the ->repeatable field by an extended ->cmd() hook (called
->cmd_rep()) which takes a new int pointer to store the repeatable cap
of the command being executed.

With this trick, we can let sub-commands decide whether they are
repeatable or not.

We also patch mmc and dtimg who are testing the ->repeatable field
directly (they now use cmd_is_repeatable() instead), and fix the help
entry manually since it doesn't use the U_BOOT_CMD() macro.

Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-01-15 15:28:54 -05:00
Boris Brezillon
6fb61445bb common: command: Expose a generic helper to auto-complete sub commands
Some commands have a table of sub-commands. With minor adjustments,
complete_cmdv() is able to provide auto-completion for sub-commands
(it's just about passing the table of commands instead of taking the
global one).
We rename this function into complete_subcmd() and implement
complete_cmdv() as a wrapper around complete_subcmdv().

Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-01-15 15:28:53 -05:00
Boris Brezillon
cbe07ebeaf common: command: Fix command auto-completion
When auto-completing command arguments, the last argument is not
necessarily the one we need to auto-complete. When the last character is
a space, a tab or '\0' what we want instead is list all possible values,
or if there's only one possible value, place this value on the command
line instead of trying to suffix the last valid argument with missing
chars.

Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-01-15 15:28:53 -05:00
Marek Vasut
2e89bbefdc blk: Increase cache element size
Cache up to 4 kiB entries. 4 kiB is the default block size on ext4, yet
the underlying block layer devices usually report support for 512B . In
most cases, the 512B support is emulated (ie. SD cards, SSDs, USB sticks
etc.) and the real block size of those devices is much bigger.

To avoid performance degradation with such devices and FS setup, bump
the maximum cache entry size to 4 kiB.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-01-15 15:28:53 -05:00
Simon Goldschmidt
45297e2ab2 Makefile: run CONFIG_BOARD_SIZE_LIMIT against .img
With the current Makefile, CONFIG_BOARD_SIZE_LIMIT is used to check
the U-Boot binary without devicetree only. This produces wrong results
when OF_SEPARATE is used.

To fix this, run the CONFIG_BOARD_SIZE_LIMIT check on all .img binaries
as well.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-15 15:28:53 -05:00
Masahiro Yamada
c16b137e49 kbuild: add .SECONDARY special target to scripts/Kbuild.include
Based on the following Linux commits:

 - 54a702f70589 ("kbuild: mark $(targets) as .SECONDARY and remove
   .PRECIOUS markers")

 - 8e9b61b293d9 ("kbuild: move .SECONDARY special target to
   Kbuild.include")

GNU Make automatically deletes intermediate files that are updated
in a chain of pattern rules.

Example 1) %.dtb.o <- %.dtb.S <- %.dtb <- %.dts
Example 2) %.o <- %.c <- %.c_shipped

A couple of makefiles mark such targets as .PRECIOUS to prevent Make
from deleting them, but the correct way is to use .SECONDARY.

  .SECONDARY
    Prerequisites of this special target are treated as intermediate
    files but are never automatically deleted.

  .PRECIOUS
    When make is interrupted during execution, it may delete the target
    file it is updating if the file was modified since make started.
    If you mark the file as precious, make will never delete the file
    if interrupted.

Both can avoid deletion of intermediate files, but the difference is
the behavior when Make is interrupted; .SECONDARY deletes the target,
but .PRECIOUS does not.

The use of .PRECIOUS is relatively rare since we do not want to keep
partially constructed (possibly corrupted) targets.

.SECONDARY with no prerequisites causes all targets to be treated as
secondary. This agrees the policy of Kbuild.

scripts/Kbuild.include seems a suitable place to add it because it is
included from almost all sub-makes.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-01-15 15:28:53 -05:00
Masahiro Yamada
368a0dfbf8 kbuild: add .DELETE_ON_ERROR special target
Linux commit 9c2af1c7377a8a6ef86e5cabf80978f3dbbb25c0

If Make gets a fatal signal while a shell is executing, it may delete
the target file that the recipe was supposed to update.  This is needed
to make sure that it is remade from scratch when Make is next run; if
Make is interrupted after the recipe has begun to write the target file,
it results in an incomplete file whose time stamp is newer than that
of the prerequisites files.  Make automatically deletes the incomplete
file on interrupt unless the target is marked .PRECIOUS.

The situation is just the same as when the shell fails for some reasons.
Usually when a recipe line fails, if it has changed the target file at
all, the file is corrupted, or at least it is not completely updated.
Yet the file’s time stamp says that it is now up to date, so the next
time Make runs, it will not try to update that file.

However, Make does not cater to delete the incomplete target file in
this case.  We need to add .DELETE_ON_ERROR somewhere in the Makefile
to request it.

scripts/Kbuild.include seems a suitable place to add it because it is
included from almost all sub-makes.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-01-15 15:28:52 -05:00
Chris Packham
f75977303d common: Kconfig: miscellaneous spelling fixes
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-15 15:28:52 -05:00
Masahiro Yamada
0b588deffe kbuild: fix parallel build race caused by u-boot.cfg regeneration
Multiple people have reported intermittent build failure in parallel
building.

Kever Yang reported this issue some time ago [1], but I could not
get enough clue at that time.

This time, Richard Purdie provided a full build log [2], which was
very helpful for me to root-cause it.

The cause of the problem is commit 0d982c5853 ("Makefile: add
dependencies to regenerate u-boot.cfg when lost").

That commit added the 'cfg' as the prerequisite of the 'all' target,
so the parallel build tries to run it simultaneously, then regenerates
a symlink while building objects.

When u-boot.cfg is accidentally lost, let's rebuild it before
descending into any subdirectories.

Also, what is annoying is u-boot.cfg is currently regenerated every
time since it depends on FORCE. We can get rid of all the prerequisites
of u-boot.cfg because u-boot.cfg is rebuilt anyway as the byproduct of
auto.conf when a user updates the .config file.

[1] https://lists.denx.de/pipermail/u-boot/2018-June/330341.html
[2] https://autobuilder.yoctoproject.org/typhoon/#/builders/65/builds/160/steps/7/logs/step1b

Fixes: 0d982c5853 ("Makefile: add dependencies to regenerate u-boot.cfg when lost")
Reported-by: Kever Yang <kever.yang@rock-chips.com>
Reported-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-15 15:28:52 -05:00
Simon Goldschmidt
c4448bdc4f serial: ns16550: fix debug uart putc called before init
If _debug_uart_putc() is called before _debug_uart_init(), the
ns16550 debug uart driver hangs in a tight loop waiting for the
tx FIFO to get empty.

As this can happen via a printf sneaking in before the port calls
debug_uart_init(), introduce a config option to ignore characters
before the debug uart is initialized.

This is done by reading the baudrate divisor and aborting if is zero.

The Kconfig option is required as reading the baudrate divisor does
not seem to work for all ns16500 compatibles (which is why the last
attempt on this has been reverted in 1a67969a99).

Tested on socfpga_cyclone5_socrates.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-15 15:28:52 -05:00
Simon Goldschmidt
7828e3cf70 drivers: serial: DEBUG_UART_SKIP_INIT depends on DEBUG_UART
DEBUG_UART_SKIP_INIT is used only by debug UART and thus should depend
on DEBUG_UART.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-15 15:28:52 -05:00
Vagrant Cascadian
bb5835bc01 Fix typo: missmatched -> mismatched.
Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-01-15 15:28:51 -05:00
Lokesh Vutla
a4773c5559 xyz-modem: Fix timeout loop waiting with WATCHDOG
Commit 2c77c0d652 ("xyz-modem: Change getc timeout loop waiting")
fixes the loop delay when using a hw watchdog, assuming that watchdog
kicking is taken care of by getc(). But the xyzmodem driver tries to
do a getc only after confirming that a character is available like below:
	while (!tstc()) {
		till timeout;
	}
	if (tstc())
		*c = getc();

and getc() does a watchdog reset only if it fails to see a character.
In this case, getc() always sees a character and never does a
watchdog reset. So to make sure that watchdog doesn't get reset
while loading the file, do a watchdog reset just before starting the
image loading.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-15 15:28:51 -05:00
Josef Lusticky
03e6151d5b pylibfdt: Use Python 2 in Makefile
pylibfdt needs Python 2 to build.
Replace $(PYTHON) with $(PYTHON2) in pylibfdt Makefile
to ensure Python 2 is used to build it.

This fixes build on systems where Python 3 is the default version
of the "python" interpreter.
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-15 15:28:45 -05:00
Marek Vasut
05f6da3fac lib: uuid: Do not enable UUID command SPL
The uuid command is only really useful in U-Boot, but it's useless in
SPL. Worse yet, it pulls in various environment manipulation functions
as it call env_set(). Do not compile the command in in SPL.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
2019-01-15 15:28:45 -05:00
Marek Vasut
92e5cb804a spl: ymodem: Add support for loading gzip compressed uImage
Add support for gunzip-ing gzip-compressed uImages in the SPL Ymodem code.
Loading data over Ymodem can be gruelingly slow, gzip-ing the data can
reduce that aggravating slowness at least slightly (depends on the data,
u-boot.bin compresses to ~1/3 of it's original size on ARM64), hence add
optional support for decompressing gzip-compressed uImages.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
2019-01-15 15:28:45 -05:00
Simon Goldschmidt
7d05d3a8e3 dtoc: make generated platdata structs const
The platdata initialization structs are currently generated into .rwdata.
Make sure the are put into .rodata by generating them as const.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-15 15:28:45 -05:00
Heinrich Schuchardt
d667090999 cmd: zip: use correct format code
dst_len is defined as unsigned long. So use %lu for printf().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-01-15 15:28:44 -05:00
Heinrich Schuchardt
9ae2ddc82e cmd: unzip: use correct format code
src_len is defined as unsigned long. So use %lu for printf().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-01-15 15:28:44 -05:00
Heinrich Schuchardt
76428561b3 cmd: ubi: remove unreachable code
It does not make sense to check if argc < 2 a second time, especially after
accessing argv[1].

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-01-15 15:28:44 -05:00
Heinrich Schuchardt
1d1af2ae5a cmd: tpm-v2: use correct format code
updates is defined as unsigned int. So use %u for printf().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-01-15 15:28:44 -05:00
Heinrich Schuchardt
c6b2ea379c cmd: sf: use correct printf code
test->time_ms[] is defined as unsigned. So use %u for printf().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-15 15:28:44 -05:00
Heinrich Schuchardt
82919517fb cmd: nvedit: use correct format code
len is defined as unsigned. So use %u for printf().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-01-15 15:28:43 -05:00
Heinrich Schuchardt
b1970013d4 cmd: gpio: use correct printf code
gpio is defined as unsigned int. So we should use %u when calling printf().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-15 15:28:43 -05:00
Patrice Chotard
6e00104880 configs: stm32: Remove CONFIG_OF_EMBED
Building with CONFIG_OF_EMBED generates build warnings, as it should
only be used for debugging purposes.

Remove CONFIG_OF_EMBED from all stm32 config files which are using
this flag.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-01-15 15:28:43 -05:00
Marek Vasut
1d044d323d cmd: mmc: Invalidate MMC block cache after init
Make sure the block cache is cleared for the MMC device after it was
reinitialized to avoid having any stale data in the cache, like e.g.
partition tables or such.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
2019-01-15 15:28:43 -05:00
Marek Vasut
d2a083696e cmd: mmc: Force mmc reinit when no card present
In case the card is removed, force-init the MMC to start the internal
machinery which deregisters and invalidate the MMC device.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
2019-01-15 15:28:43 -05:00
Marek Vasut
b9a2a0e2e9 mmc: Add support for downgrading HS200/HS400 to HS mode
The mmc_select_mode_and_width() function can be called while the card
is in HS200/HS400 mode and can be used to downgrade the card to lower
mode, e.g. HS. This is used for example by mmc_boot_part_access_chk()
which cannot access the card in HS200/HS400 mode and which is in turn
called by saveenv if env is in the MMC.

In such case, forcing the card clock to legacy frequency cannot work.
Instead, the card must be switched to HS mode first, from which it can
then be reprogrammed as needed.

However, this procedure needs additional code changes, since the current
implementation checks whether the card correctly switched to HS mode in
mmc_set_card_speed(). The check only expects that the card will be going
to HS mode from lower modes, not from higher modes, hence add a parameter
which indicates that the HS200/HS400 to HS downgrade is happening. This
makes the code send the switch command first, reconfigure the controller
next and finally perform the EXT_CSD readback check. The last two steps
cannot be done in reverse order as the card is already in HS mode when
the clock are being switched on the controller side.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
2019-01-15 15:28:42 -05:00
Enric Balletbo i Serra
9a878e8f17 am335x: igep003x: Add Device Tree Support and DM_MMC driver
This adds device tree and the DM_MMC driver for the AM335x IGEP based
boards.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
2019-01-15 15:28:42 -05:00
Enric Balletbo i Serra
e5f0878c07 am335x: sl50: Add Device Tree Support and DM_MMC driver
This adds device tree and the DM_MMC driver for the SL50 board.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
2019-01-15 15:28:42 -05:00
Enric Balletbo i Serra
8fd8f2e4fc omap3: igep00x0: Add Device Tree Support and DM_MMC driver
This adds device tree for OMAP3 IGEP based boards and the DM_MMC driver.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-01-15 15:28:42 -05:00
Enric Balletbo i Serra
94b9a0cc46 omap3: igep00x0: Switch to simple malloc in SPL
To save more space, switch to simple malloc here.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
2019-01-15 15:28:42 -05:00
Enric Balletbo i Serra
829d6465b0 omap3: igep00x0: Switch to using TI_COMMON_CMD_OPTION
Enable TI_COMMON_CMD_OPTIONS and remove similar options
from the defconfig.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
2019-01-15 15:28:42 -05:00
Enric Balletbo i Serra
2432dace11 omap3: igep00x0: Remove USB support due DM_USB deadline
The USB support for this board was never really tested, in fact, the
presence of these options are more a copy & paste error from the
Beagleboard than a feature that really was used. As doesn't work, remove
for now. If someone at some point want to add this support he'll need to
migrate the board to use CONFIG_DM_USB instead.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
2019-01-15 15:28:41 -05:00
Enric Balletbo i Serra
f88a34defe omap3: igep00x0: Remove unmaintained IGEP0032 defconfig
The IGEP0032 board was never officially pushed upstream and actually I
don't have access to this hardware, unless someone with the hardware
wants to start working on this doesn't makes sense have this defconfig
here. So remove it.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
2019-01-15 15:28:41 -05:00
Simon Glass
871bf7d9ba test: Use single quote consistently
Some tests have ended up using double quotes where single quotes could be
used. Adjust this for consistency with the rest of U-Boot's Python code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-01-15 15:28:41 -05:00
Manivannan Sadhasivam
a50eb64915 arm: dts: Add MMC nodes for HiKey board
Add MMC nodes for HiKey board based on HI6220 SoC. There are three MMC
controllers in this SoC, first one used for eMMC, second one used
for SD card and third one is not used by u-boot.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-01-15 15:28:21 -05:00
Manivannan Sadhasivam
6240e64f92 mmc: Convert HI6220 MMC driver to driver model
Convert HiSilicon HI6220 MMC driver based on DWMMC IP to driver
model.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Enable this on poplar]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-01-15 15:28:10 -05:00
Michal Simek
1d7b6a5c4f i2c: Reflect correct dependency for !DM cadence driver
Setup proper DM_I2C dependency.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-15 09:06:46 +01:00
Michal Simek
58dc4a99b7 i2c: mux: Covert to livetree functions
Updates i2c muxes drivers to support livetree.
Similar changes were done by:
"net: zynq_gem: convert to use livetree"
(sha1: 26026e695a)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-15 09:06:28 +01:00
Tomasz Gorochowik
f48ef0d81a i2c: i2c-cdns: Use proper input frequency
This is needed to properly calculate i2c bus speed divisors.

Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
Signed-off-by: Wojciech Tatarski <wtatarski@antmicro.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-15 09:04:49 +01:00
Marek Vasut
ad827a500b i2c: xiic: Add Xilinx AXI I2C driver
Add Xilinx AXI I2C controller driver based on the Linux i2c-xiic driver.
This driver is stripped of all the IRQ handling and uses pure polling,
yet tries to retain most of the structure of the Linux driver to make
backporting of fixes easy.

Note that the IP has a known limitation on 255 bytes read and write,
according to xilinx this is still being worked on [1].

[1] https://forums.xilinx.com/t5/Embedded-Processor-System-Design/AXI-IIC-V2-0-I2C-Master-Reading-multiple-bytes-from-I2C-slave/m-p/854419/highlight/true#M39387

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-01-15 09:04:49 +01:00
Lukas Auer
91882c472d riscv: qemu: define standalone load address
We need to define the standalone load address to use standalone
application on qemu-riscv. Define it and set it equal to
CONFIG_SYS_LOAD_ADDR.

To not overwrite it, change the assigned of CONFIG_STANDALONE_LOAD_ADDR
in arch/riscv/config.mk to a conditional one.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-01-15 09:36:31 +08:00
Lukas Auer
7eb792970e riscv: support standalone applications on RV64I systems
Add an implementation of EXPORT_FUNC() for RV64I systems to support them
in standalone applications.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-01-15 09:36:31 +08:00
Lukas Auer
cbb860f2c8 riscv: replace use of callee-saved register in standalone
Register x19 (s3) is a callee-saved register. It must not be used to
load and jump to exported functions without saving it beforehand.
Replace it with t0, a temporary and caller-saved register.

Change the code comment to reflect this and fix it to correctly list gp
as the register with the pointer to global data.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-01-15 09:36:31 +08:00
Lukas Auer
3c37278ff1 riscv: remove RISC-V standalone linker script
Standalone applications do not require a separate linker script and can
use the default linker script of the compiler instead. Remove the RISC-V
standalone linker script.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-01-15 09:36:31 +08:00
Lukas Auer
f74c416e62 riscv: use invalidate/flush_*cache_range functions in cache.c
The flush_cache() function in lib/cache.c ignores its arguments and
flushes the complete data and instruction caches. Use the
invalidate/flush_*cache_range() functions instead to only flush the
requested memory region.

This patch does not change the current behavior of U-Boot, since the
implementation of the invalidate/flush_*cache_range() functions flush
the complete data and instruction caches. It is in preparation for CPUs
with the necessary functionality for flushing a selectable memory range.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-01-15 09:36:31 +08:00
Lukas Auer
c9056653ec riscv: move the AX25-specific implementation of flush_dcache_all
The fence instruction is used to enforce device I/O and memory ordering
constraints in RISC-V. It can not be relied on to directly affect the
data cache on every CPU.
Andes' AX25 does not have a coherence agent. Its fence instruction
flushes the data cache and is used to keep data in the system coherent.
The implementation of flush_dcache_all in lib/cache.c is therefore
specific to the AX25. Move it into the AX25-specific cache.c in
cpu/ax25/.

This also adds a missing new line between flush_dcache_all and
flush_dcache_range in lib/cache.c.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-01-15 09:36:31 +08:00
Lukas Auer
0c85c113c4 riscv: clarify error message on undefined exceptions
Undefined exceptions are treated as reserved. This is not clearly
communicated to the user. Adjust the error message to clarify that a
reserved exception has occurred and add additional details.

Fixes: e8b522b ("riscv: treat undefined exception codes as reserved")
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-01-15 09:36:31 +08:00
Keerthy
f51f6715a5 lib: fdtdec: fdtdec_get_addr_size_fixed remove checks
With 8 bytes addressing even on 32 bit machines these checks
are no longer valid. Remove them.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-14 17:47:20 -07:00
Heinrich Schuchardt
d0a30a8ae2 sandbox: i2c_emul_find() No emulators for device 'rtc@43'
when running the date command on sandbox_defconfig an error occurs:

    ./u-boot -D u-boot.dtb

    => date
    i2c_emul_find() No emulators for device 'rtc@43'
    ## Get date failed

Correct the references to the emulator devices in the sandbox device trees
using test.dts as a reference.

Fixes: 031a650e13 ("dm: sandbox: i2c: Use new emulator parent uclass")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Dropped unnecessary #address/size-cells property in i2c_emul:
Signed-off-by: Simon Glass <sjg@chromium.org>
2019-01-14 17:47:13 -07:00
Simon Glass
eab647d5e7 dm: serial: Tidy up header file comments
The getconfig() comment is out of date. Fix this and add comments for
recently added functions.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
2019-01-14 17:47:13 -07:00
Simon Glass
a61cbad78e dm: serial: Adjust serial_getinfo() to use proper API
All driver-model functions should have a device as the first parameter.
Update this function accordingly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
2019-01-14 17:47:13 -07:00
Simon Glass
3de04e771c dm: serial: Adjust serial_setconfig() to use proper API
All driver-model functions should have a device as the first parameter.
Update this function accordingly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
2019-01-14 17:47:13 -07:00
Simon Glass
67d1b05130 dm: serial: Adjust serial_getconfig() to use proper API
All driver-model functions should have a device as the first parameter.
Update this function accordingly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
2019-01-14 17:47:13 -07:00
Simon Glass
0171f43204 serial: Move new functions to serial.h
We should not be adding new functions to common.h. Move these recently
added functions to serial.h.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
2019-01-14 17:47:13 -07:00
Simon Glass
ccd2979a8d buildman: Fix tabs in GetWrapper()
This function has tabs instead of spaces. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-01-14 17:47:13 -07:00
Simon Glass
8405452e6a net: Fix error handling in sb_eth_raw_ofdata_to_platdata()
At present this stores the error number in an unsigned int so an error is
never detected. Use the existing signed variable instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-14 17:47:13 -07:00
Simon Glass
e9500f49ea travis: Use buildman for building with clang
Now that buildman supports clang, use it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-01-14 17:47:13 -07:00
Simon Glass
00beb2485f buildman: Add support for building with clang
Add a -O option which allows building with clang.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-01-14 17:47:13 -07:00
Simon Glass
ed4e933d13 log: Check printf() arguments
At present logging does not check printf() arguments. Now that all users
have been corrected, enable this to prevent further problems.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-01-14 17:47:13 -07:00
Simon Glass
0c89a318dc efi_loader: Add a wchar_t cast in efi_file_open()
The printf() string here is not actually correct. Add a cast to avoid
a warning when checking is enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-01-14 17:47:13 -07:00
Simon Glass
398ae02669 sandbox: Correct SDL build flags
The check for CONFIG_SANDBOX_SDL in config.mk does not work since the
build config is not available by the time that file is included. Remove it
so that we always call sdl-config except when NO_SDL is used.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-01-14 17:47:13 -07:00
Simon Glass
e74429bb17 buildman: Deal nicely with invalid build-status file
The 'done' files created by buildman may end up being empty if buildman
runs out of disk space while writing them. This error is then persistent,
since even if disk space is reclaimed and the build retries, the empty
file causes an exception in the builder thread.

Deal with this silently by doing a rebuild.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-01-14 17:47:13 -07:00
Simon Glass
df9cf1cc08 test: dm: regmap: Fix the long test delay
At present one of the regmap tests takes 5 seconds to run since it waits
for a timeout. This should be handled using sandbox_timer_add_offset()
which advances time for test purposes.

This requires a little change to make the regmap_read_poll_timeout()
testable.

Update the macro and the test.

Fixes: ebe3497c9c ("test: regmap: add regmap_read_poll_timeout test")

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-01-14 17:47:13 -07:00
Sekhar Nori
d8e9cf4d47 common: fdt_support: print hexadecimal numbers in debug
We usually deal with hexadecimal addresses and sizes in
device-tree. Its much easier if debug logs print hexadecimal
values too.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-01-14 17:47:13 -07:00
Simon Glass
54d2cfe6ee dm: Tidy up 'dm tree' output when there are many devices
At present the 'Index' column assumes there is only one digit. But on some
devices (e.g. snow) there are a lot of regulators and GPIO banks. Adjust
the output to allow for two digits without messing up the display.

Also capatalise the heading to match.

Fixes: 5197dafc42 (dm: core: Widen the dump tree to show more of the
driver's name.)

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Liviu Dudau <liviu.dudau@foss.arm.com>
2019-01-14 17:47:13 -07:00
Simon Glass
90a29fcc1f buildman: Drop comment about Ctrl-C problem
This bug is now fixed, so drop this comment.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-01-14 17:47:13 -07:00
Christian GMEINER
9814430128 sandbox: add memset_io(..), memcpy_fromio(..) and memcpy_toio(..)
These functions could be used by drivers.

Signed-off-by: Christian GMEINER <christian.GMEINER@bachmann.info>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-14 17:47:13 -07:00
Manivannan Sadhasivam
5bb409c1ba include: configs: Add gunzip size for HiKey board
Default 8MB gunzip size is not enough to load the release kernel, hence
fix 64MB size for uncompressing the kernel.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-14 17:43:18 -05:00
Weijie Gao
b5d29e4390 configs: MediaTek: use OF_SEPARATE instead of OF_EMBED
This patch replace OF_EMBED with OF_SEPARATE of defconfig files of
MediaTek boards because now OF_EMBED is only used for debugging purpose.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-14 17:43:18 -05:00
Weijie Gao
d049ff9ca5 MAINTAINERS: ARM MEDIATEK: update file entries
This patch adds new file entries for MediaTek SoCs

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-01-14 17:43:18 -05:00
Weijie Gao
d7fe0ad285 arm: MediaTek: add ethernet support for MT7629 boards
Enable ethernet related configs to mt7629_rfb_defconfig.
Add default IP addresses.
Enable noncached memory region required by ethernet driver.

Signed-off-by: Mark Lee <Mark-MC.Lee@mediatek.com>
2019-01-14 17:43:18 -05:00
Weijie Gao
8505cdde8e arm: MediaTek: add ethernet support for MT7623 boards
Enable ethernet related configs to mt7623n_bpir2_defconfig.
Add default IP addresses.
Enable noncached memory region required by ethernet driver.

Signed-off-by: Mark Lee <Mark-MC.Lee@mediatek.com>
2019-01-14 17:43:18 -05:00
Weijie Gao
9d42b613a8 arm: dts: add ethernet related node for MT7629 SoC
This patch adds ethernet gmac node for MT7629 with internal gigabit phy.

Signed-off-by: Mark Lee <Mark-MC.Lee@mediatek.com>
2019-01-14 17:43:18 -05:00
Weijie Gao
d9506a6fdd arm: dts: add ethernet related node for MT7623 SoC
This patch adds ethernet gmac node for MT7623 with MT7530 gigabit switch.

Signed-off-by: Mark Lee <Mark-MC.Lee@mediatek.com>
2019-01-14 17:43:18 -05:00
Weijie Gao
23f17164d9 ethernet: MediaTek: add ethernet driver for MediaTek ARM-based SoCs
This patch adds ethernet support for Mediatek ARM-based SoCs, including
a minimum setup of the integrated switch.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Mark Lee <Mark-MC.Lee@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-By: "Frank Wunderlich" <frank-w@public-files.de>
2019-01-14 17:43:18 -05:00
Weijie Gao
2dca3cc2a9 clk: MediaTek: bind ethsys reset controller
The ethsys contains not only the clock gating controller, but also the
reset controller for the whole ethernet subsystem and its components.

This patch adds binding of the reset controller so that the ethernet node
can have references on it.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-01-14 17:43:18 -05:00
Weijie Gao
3e066bcaef reset: MedaiTek: add reset controller driver for MediaTek SoCs
This patch adds reset controller driver for MediaTek SoCs.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-01-14 17:43:18 -05:00
Shawn Guo
37cbd8918c poplar_defconfig: enable fastboot support
It enables fastboot support on Poplar board by using DWC2 OTG gadget
driver.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2019-01-14 17:43:18 -05:00
Shawn Guo
e7ab6dfc65 poplar: add DWC2 OTG gadget support
It enables DWC2 OTG gadget driver support for Poplar board.  As
usb2_phy_init() is being always called from board_init(), we can save
the call from board_usb_init().

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2019-01-14 17:42:44 -05:00
Simon Goldschmidt
596be5f327 image: fix compiling without CMD_FDT
Booting an image currently sets the environment variable "fdtaddr"
by calling into 'cmd/fdt.c'. As a result, linking U-Boot fails if
CMD_FDT is not enabled.

Fix this by adding 'if (CONFIG_IS_ENABLED(CMD_FDT))' to the two
places where 'set_working_fdt_addr()' is called.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-01-14 17:42:32 -05:00
Yan Liu
eddb7278d7 am57xx_evm_defconfig: Enable YMODEM support
Enable CONFIG_SPL_YMODEM_SUPPORT to support UART boot

Signed-off-by: Yan Liu <yan-liu@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-01-14 17:41:23 -05:00
Philipp Tomsich
6f2d59cb7f test: bootcount: add bootcount-uclass test
Add a test for the bootcount uclass, which uses the RTC bootcount backend
(i.e. drivers/bootcount/rtc.c is implictly also tested).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-14 17:41:23 -05:00
1557 changed files with 58070 additions and 17368 deletions

View File

@@ -63,6 +63,7 @@ env:
- BUILD_DIR=build
- HOSTCC="cc"
- HOSTCXX="c++"
- QEMU_VERSION="v3.1.0"
before_script:
# install toolchains based on TOOLCHAIN} variable
@@ -78,6 +79,11 @@ before_script:
wget https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/download/arc-2018.09-release/arc_gnu_2018.09_prebuilt_uclibc_le_archs_linux_install.tar.gz &&
tar -C /tmp -xf arc_gnu_2018.09_prebuilt_uclibc_le_archs_linux_install.tar.gz;
fi
- if [[ "${TOOLCHAIN}" == "nds32" ]]; then
wget https://github.com/vincentzwc/prebuilt-nds32-toolchain/releases/download/20180521/nds32le-linux-glibc-v3-upstream.tar.gz &&
tar -C /tmp -xf nds32le-linux-glibc-v3-upstream.tar.gz &&
echo -e "\n[toolchain-prefix]\nnds32 = /tmp/nds32le-linux-glibc-v3-upstream/bin/nds32le-linux-" >> ~/.buildman;
fi
- if [[ "${TOOLCHAIN}" == *xtensa* ]]; then
wget https://github.com/foss-xtensa/toolchain/releases/download/2018.02/x86_64-2018.02-${TOOLCHAIN}.tar.gz &&
tar -C /tmp -xf x86_64-2018.02-${TOOLCHAIN}.tar.gz &&
@@ -97,7 +103,7 @@ before_script:
git clone git://git.qemu.org/qemu.git /tmp/qemu;
pushd /tmp/qemu;
git submodule update --init dtc &&
git checkout v3.0.0 &&
git checkout ${QEMU_VERSION} &&
./configure --prefix=/tmp/qemu-install --target-list=${QEMU_TARGET} &&
make -j4 all install;
popd;
@@ -109,16 +115,9 @@ script:
#
# From buildman, exit code 129 means warnings only. If we've been asked to
# use clang only do one configuration.
- if [[ "${TOOLCHAIN}" == "clang" ]]; then
- if [[ "${BUILDMAN}" != "" ]]; then
ret=0;
make O=../.bm-work/${TEST_PY_BD} HOSTCC=clang-7 CC=clang-7 -j$(nproc)
KCFLAGS=-Werror sandbox_config all || ret=$?;
if [[ $ret -ne 0 ]]; then
exit $ret;
fi;
elif [[ "${BUILDMAN}" != "" ]]; then
ret=0;
tools/buildman/buildman -P -E ${BUILDMAN} || ret=$?;
tools/buildman/buildman -P -E ${BUILDMAN} ${OVERRIDE}|| ret=$?;
if [[ $ret -ne 0 && $ret -ne 129 ]]; then
tools/buildman/buildman -sdeP ${BUILDMAN};
exit $ret;
@@ -164,7 +163,7 @@ matrix:
- name: "buildman arm11 arm7 arm920t arm946es"
env:
- BUILDMAN="arm11 arm7 arm920t arm946es"
- name: "buildman arm926ejs (non-freescale,siemens,atmel,kirkwood,spear)"
- name: "buildman arm926ejs (non-NXP,siemens,atmel,kirkwood,spear)"
env:
- JOB="arm926ejs"
BUILDMAN="arm926ejs -x freescale,siemens,atmel,kirkwood,spear"
@@ -174,19 +173,25 @@ matrix:
- name: "buildman boundary engicam toradex"
env:
- BUILDMAN="boundary engicam toradex"
- name: "buildman Freescale ARM32"
- name: "buildman NXP ARM32"
env:
- BUILDMAN="freescale -x powerpc,m68k,aarch64"
- name: "buildman Freescale AArch64 LS10xx"
- name: "buildman NXP AArch64 LS101x"
env:
- BUILDMAN="freescale&aarch64&&ls1"
- name: "buildman Freescale AArch64 LS20xx"
- BUILDMAN="freescale&aarch64&ls101"
- name: "buildman NXP AArch64 LS104x"
env:
- BUILDMAN="freescale&aarch64&&ls2"
- name: "buildman i.MX6 (non-Freescale)"
- BUILDMAN="freescale&aarch64&ls104"
- name: "buildman NXP AArch64 LS108x"
env:
- BUILDMAN="freescale&aarch64&ls108"
- name: "buildman NXP AArch64 LS20xx"
env:
- BUILDMAN="freescale&aarch64&&ls20"
- name: "buildman i.MX6 (non-NXP)"
env:
- BUILDMAN="mx6 -x freescale,toradex,boundary,engicam"
- name: "buildman i.MX (non-Freescale,i.MX6,toradex)"
- name: "buildman i.MX (non-NXP,i.MX6,toradex)"
env:
- BUILDMAN="mx -x freescale,mx6,toradex"
- name: "buildman k2"
@@ -311,6 +316,10 @@ matrix:
env:
- BUILDMAN="riscv"
TOOLCHAIN="riscv"
- name: "buildman nds32"
env:
- BUILDMAN="nds32"
TOOLCHAIN="nds32"
# QA jobs for code analytics
# static code analysis with cppcheck (we can add --enable=all later)
@@ -351,7 +360,7 @@ matrix:
env:
- TEST_PY_BD="sandbox"
BUILDMAN="^sandbox$"
TOOLCHAIN="clang"
OVERRIDE="clang-7"
- name: "test/py sandbox_spl"
env:
- TEST_PY_BD="sandbox_spl"
@@ -369,6 +378,7 @@ matrix:
- TEST_PY_BD="vexpress_ca15_tc2"
TEST_PY_ID="--id qemu"
QEMU_TARGET="arm-softmmu"
QEMU_VERSION="v3.0.0"
BUILDMAN="^vexpress_ca15_tc2$"
- name: "test/py vexpress_ca9x4"
env:
@@ -453,6 +463,13 @@ matrix:
QEMU_TARGET="arm-softmmu"
TEST_PY_ID="--id qemu"
BUILDMAN="^zynq_zc702$"
- name: "test/py xilinx_versal_virt"
env:
- TEST_PY_BD="xilinx_versal_virt"
TEST_PY_TEST_SPEC="not sleep"
QEMU_TARGET="aarch64-softmmu"
TEST_PY_ID="--id qemu"
BUILDMAN="^xilinx_versal_virt$"
- name: "test/py xtfpga"
env:
- TEST_PY_BD="xtfpga"

View File

@@ -9,6 +9,12 @@ Boot services
.. kernel-doc:: lib/efi_loader/efi_boottime.c
:internal:
Image relocation
~~~~~~~~~~~~~~~~
.. kernel-doc:: lib/efi_loader/efi_image_loader.c
:internal:
Runtime services
----------------

16
Kconfig
View File

@@ -213,7 +213,7 @@ config PHYS_64BIT
help
Say Y here to support 64bit physical memory address.
This can be used not only for 64bit SoCs, but also for
large physical address extention on 32bit SoCs.
large physical address extension on 32bit SoCs.
config BUILD_ROM
bool "Build U-Boot as BIOS replacement"
@@ -224,6 +224,20 @@ config BUILD_ROM
which are not shipped in the U-Boot source tree.
Please, see doc/README.x86 for details.
config BUILD_TARGET
string "Build target special images"
default "u-boot-with-spl.sfp" if ARCH_SOCFPGA
default "u-boot-spl.kwb" if ARCH_MVEBU && SPL
default "u-boot-elf.srec" if RCAR_GEN3
default "u-boot.itb" if SPL_LOAD_FIT && ARCH_SUNXI
default "u-boot.kwb" if KIRKWOOD
help
Some SoCs need special image types (e.g. U-Boot binary
with a special header) as build targets. By defining
CONFIG_BUILD_TARGET in the SoC / board header, this
special image will be automatically built upon calling
make / buildman.
endmenu # General setup
menu "Boot images"

View File

@@ -91,14 +91,30 @@ S: Maintainted
T: git git://git.denx.de/u-boot-socfpga.git
F: arch/arm/mach-socfpga/
ARM ATMEL AT91
M: Andreas Bießmann <andreas@biessmann.org>
ARM AMLOGIC SOC SUPPORT
M: Neil Armstrong <narmstrong@baylibre.com>
S: Maintained
T: git git://git.denx.de/u-boot-atmel.git
F: arch/arm/mach-at91/
L: u-boot-amlogic@groups.io
T: git git://git.denx.de/u-boot-amlogic.git
F: arch/arm/mach-meson/
F: arch/arm/include/asm/arch-meson/
F: drivers/clk/clk_meson*
F: drivers/serial/serial_meson.c
F: drivers/reset/reset-meson.c
F: drivers/i2c/meson_i2c.c
F: drivers/net/phy/meson-gxl.c
F: drivers/adc/meson-saradc.c
F: drivers/phy/meson*
F: drivers/mmc/meson_gx_mmc.c
F: drivers/spi/meson_spifc.c
F: drivers/pinctrl/meson/
F: drivers/power/domain/meson-gx-pwrc-vpu.c
F: drivers/video/meson/
F: include/configs/meson64.h
N: meson
ARM BROADCOM BCM283X
M: Alexander Graf <agraf@suse.de>
M: Matthias Brugger <mbrugger@suse.com>
S: Maintained
F: arch/arm/mach-bcm283x/
F: drivers/gpio/bcm2835_gpio.c
@@ -120,9 +136,17 @@ F: doc/README.bcm7xxx
F: drivers/mmc/bcmstb_sdhci.c
F: drivers/spi/bcmstb_spi.c
ARM/CZ.NIC TURRIS MOX SUPPORT
M: Marek Behun <marek.behun@nic.cz>
S: Maintained
F: arch/arm/dts/armada-3720-turris-mox.dts
F: board/CZ.NIC/
F: configs/turris_*_defconfig
F: include/configs/turris_*.h
ARM FREESCALE IMX
M: Stefano Babic <sbabic@denx.de>
M: Fabio Estevam <fabio.estevam@nxp.com>
M: Fabio Estevam <festevam@gmail.com>
R: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
S: Maintained
T: git git://git.denx.de/u-boot-imx.git
@@ -176,10 +200,19 @@ F: drivers/ram/mediatek/
F: drivers/spi/mtk_qspi.c
F: drivers/timer/mtk_timer.c
F: drivers/watchdog/mtk_wdt.c
F: drivers/net/mtk_eth.c
F: drivers/reset/reset-mediatek.c
F: tools/mtk_image.c
F: tools/mtk_image.h
N: mediatek
ARM MICROCHIP/ATMEL AT91
M: Eugen Hristev <eugen.hristev@microchip.com>
S: Maintained
T: git git://git.denx.de/u-boot-atmel.git
F: arch/arm/mach-at91/
F: board/atmel/
ARM OWL
M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
S: Maintained
@@ -257,7 +290,7 @@ M: Christophe Kerello <christophe.kerello@st.com>
M: Patrice Chotard <patrice.chotard@st.com>
L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-stm32mp
F: arch/arm/mach-stm32mp/
F: drivers/clk/clk_stm32mp1.c
F: drivers/i2c/stm32f7_i2c.c
F: drivers/misc/stm32mp_fuse.c
@@ -352,7 +385,7 @@ ARM ZYNQMP
M: Michal Simek <michal.simek@xilinx.com>
S: Maintained
T: git git://git.denx.de/u-boot-microblaze.git
F: arch/arm/cpu/armv8/zynqmp/
F: arch/arm/mach-zynqmp/
F: drivers/clk/clk_zynqmp.c
F: drivers/fpga/zynqpl.c
F: drivers/gpio/zynq_gpio.c
@@ -420,8 +453,8 @@ F: include/dm/
F: test/dm/
EFI PAYLOAD
M: Alexander Graf <agraf@suse.de>
R: Heinrich Schuchardt <xypron.glpk@gmx.de>
M: Heinrich Schuchardt <xypron.glpk@gmx.de>
R: Alexander Graf <agraf@csgraf.de>
S: Maintained
T: git git://github.com/agraf/u-boot.git
F: doc/README.uefi
@@ -465,7 +498,7 @@ S: Maintained
T: git git://git.denx.de/u-boot-freebsd.git
FREESCALE QORIQ
M: York Sun <york.sun@nxp.com>
M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
S: Maintained
T: git git://git.denx.de/u-boot-fsl-qoriq.git
@@ -521,9 +554,15 @@ F: arch/mips/mach-mscc/
F: arch/mips/dts/luton*
F: arch/mips/dts/mscc*
F: arch/mips/dts/ocelot*
F: arch/mips/dts/jr2*
F: arch/mips/dts/serval*
F: board/mscc/
F: configs/mscc*
F: drivers/gpio/mscc_sgpio.c
F: drivers/spi/mscc_bb_spi.c
F: include/configs/vcoreiii.h
F: drivers/pinctrl/mscc/
F: drivers/net/mscc_eswitch/
MIPS JZ4780
M: Ezequiel Garcia <ezequiel@collabora.com>
@@ -608,13 +647,13 @@ F: arch/powerpc/cpu/mpc83xx/
F: arch/powerpc/include/asm/arch-mpc83xx/
POWERPC MPC85XX
M: York Sun <york.sun@nxp.com>
M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
S: Maintained
T: git git://git.denx.de/u-boot-mpc85xx.git
F: arch/powerpc/cpu/mpc85xx/
POWERPC MPC86XX
M: York Sun <york.sun@nxp.com>
M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
S: Maintained
T: git git://git.denx.de/u-boot-mpc86xx.git
F: arch/powerpc/cpu/mpc86xx/
@@ -648,10 +687,18 @@ SPI
M: Jagan Teki <jagan@openedev.com>
S: Maintained
T: git git://git.denx.de/u-boot-spi.git
F: drivers/mtd/spi/
F: drivers/spi/
F: include/spi*
SPI-NOR
M: Jagan Teki <jagan@openedev.com>
M: Vignesh R <vigneshr@ti.com>
S: Maintained
F: drivers/mtd/spi/
F: include/spi_flash.h
F: include/linux/mtd/cfi.h
F: include/linux/mtd/spi-nor.h
SPMI
M: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
S: Maintained
@@ -673,7 +720,9 @@ F: configs/am335x_hs_evm_defconfig
F: configs/am335x_hs_evm_uart_defconfig
F: configs/am43xx_hs_evm_defconfig
F: configs/am57xx_hs_evm_defconfig
F: configs/am57xx_hs_evm_usb_defconfig
F: configs/dra7xx_hs_evm_defconfig
F: configs/dra7xx_hs_evm_usb_defconfig
F: configs/k2hk_hs_evm_defconfig
F: configs/k2e_hs_evm_defconfig
F: configs/k2g_hs_evm_defconfig

View File

@@ -1,9 +1,9 @@
# SPDX-License-Identifier: GPL-2.0+
VERSION = 2019
PATCHLEVEL = 01
PATCHLEVEL = 04
SUBLEVEL =
EXTRAVERSION =
EXTRAVERSION = -rc2
NAME =
# *DOCUMENTATION*
@@ -534,7 +534,7 @@ include/config/%.conf: $(KCONFIG_CONFIG) include/config/auto.conf.cmd
@# Otherwise, 'make silentoldconfig' would be invoked twice.
$(Q)touch include/config/auto.conf
u-boot.cfg spl/u-boot.cfg tpl/u-boot.cfg: include/config.h FORCE
u-boot.cfg spl/u-boot.cfg tpl/u-boot.cfg:
$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.autoconf $(@)
-include include/autoconf.mk
@@ -893,7 +893,7 @@ cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
>$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT))
quiet_cmd_mkfitimage = MKIMAGE $@
cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -f $(U_BOOT_ITS) -E $@ -p $(CONFIG_FIT_EXTERNAL_OFFSET)\
cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -f $(U_BOOT_ITS) -E -p $(CONFIG_FIT_EXTERNAL_OFFSET) $@\
>$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT))
quiet_cmd_cat = CAT $@
@@ -910,7 +910,7 @@ quiet_cmd_cfgcheck = CFGCHK $2
cmd_cfgcheck = $(srctree)/scripts/check-config.sh $2 \
$(srctree)/scripts/config_whitelist.txt $(srctree)
all: $(ALL-y) cfg
all: $(ALL-y)
ifeq ($(CONFIG_DM_I2C_COMPAT)$(CONFIG_SANDBOX),y)
@echo >&2 "===================== WARNING ======================"
@echo >&2 "This board uses CONFIG_DM_I2C_COMPAT. Please remove"
@@ -1198,6 +1198,7 @@ MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \
$(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin dts/dt.dtb,u-boot.bin) FORCE
$(call if_changed,mkimage)
$(BOARD_SIZE_CHECK)
u-boot.itb: u-boot-nodtb.bin dts/dt.dtb $(U_BOOT_ITS) FORCE
$(call if_changed,mkfitimage)
@@ -1253,7 +1254,7 @@ tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE
SPL: spl/u-boot-spl.bin FORCE
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
ifeq ($(CONFIG_ARCH_IMX8M), y)
ifeq ($(CONFIG_ARCH_IMX8M)$(CONFIG_ARCH_IMX8), y)
flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
endif
@@ -1555,7 +1556,7 @@ ifneq ($(KBUILD_SRC),)
endif
# prepare2 creates a makefile if using a separate output directory
prepare2: prepare3 outputmakefile
prepare2: prepare3 outputmakefile cfg
prepare1: prepare2 $(version_h) $(timestamp_h) \
include/config/auto.conf
@@ -1739,7 +1740,8 @@ CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \
MRPROPER_DIRS += include/config include/generated spl tpl \
.tmp_objdiff
MRPROPER_FILES += .config .config.old include/autoconf.mk* include/config.h \
ctags etags tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS
ctags etags tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS \
drivers/video/fonts/*.S
# clean - Delete most, but leave enough to build external modules
#
@@ -1794,7 +1796,7 @@ distclean: mrproper
-o -name '.*.rej' -o -name '*%' -o -name 'core' \
-o -name '*.pyc' \) \
-type f -print | xargs rm -f
@rm -f boards.cfg
@rm -f boards.cfg CHANGELOG
backup:
F=`basename $(srctree)` ; cd .. ; \

24
README
View File

@@ -1146,9 +1146,6 @@ The following options need to be configured:
CONFIG_DFU_OVER_USB
This enables the USB portion of the DFU USB class
CONFIG_DFU_MMC
This enables support for exposing (e)MMC devices via DFU.
CONFIG_DFU_NAND
This enables support for exposing NAND devices via DFU.
@@ -1429,15 +1426,6 @@ The following options need to be configured:
forwarded through a router.
(Environment variable "netmask")
- Multicast TFTP Mode:
CONFIG_MCAST_TFTP
Defines whether you want to support multicast TFTP as per
rfc-2090; for example to work with atftp. Lets lots of targets
tftp down the same boot image concurrently. Note: the Ethernet
driver in use must provide a function: mcast() to join/leave a
multicast group.
- BOOTP Recovery Mode:
CONFIG_BOOTP_RANDOM_DELAY
@@ -1708,11 +1696,6 @@ The following options need to be configured:
- CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4
- CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4
- drivers/i2c/zynq_i2c.c
- activate this driver with CONFIG_SYS_I2C_ZYNQ
- set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting
- set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr
- drivers/i2c/s3c24x0_i2c.c:
- activate this driver with CONFIG_SYS_I2C_S3C24X0
- This driver adds i2c buses (11 for Exynos5250, Exynos5420
@@ -1998,13 +1981,6 @@ The following options need to be configured:
200 ms.
- Configuration Management:
CONFIG_BUILD_TARGET
Some SoCs need special image types (e.g. U-Boot binary
with a special header) as build targets. By defining
CONFIG_BUILD_TARGET in the SoC / board header, this
special image will be automatically built upon calling
make / buildman.
CONFIG_IDENT_STRING

View File

@@ -146,9 +146,11 @@ config TARGET_NSIM
config TARGET_AXS101
bool "Support Synopsys Designware SDP board AXS101"
select BOUNCE_BUFFER if CMD_NAND
config TARGET_AXS103
bool "Support Synopsys Designware SDP board AXS103"
select BOUNCE_BUFFER if CMD_NAND
config TARGET_EMSDP
bool "Synopsys EM Software Development Platform"

View File

@@ -16,6 +16,9 @@
*/
#define ARCH_DMA_MINALIGN 128
/* CONFIG_SYS_CACHELINE_SIZE is used a lot in drivers */
#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
#if defined(ARC_MMU_ABSENT)
#define CONFIG_ARC_MMU_VER 0
#elif defined(CONFIG_ARC_MMU_V2)

View File

@@ -87,7 +87,7 @@ const char *arc_em_version(int arcver, char *name, int name_len)
bool xymem = ARC_FEATURE_EXISTS(ARC_AUX_XY_BUILD);
int i;
for (i = 0; i++ < sizeof(em_versions) / sizeof(struct em_template_t);) {
for (i = 0; i < sizeof(em_versions) / sizeof(struct em_template_t); i++) {
if (em_versions[i].cache == cache &&
em_versions[i].dsp == dsp &&
em_versions[i].xymem == xymem) {
@@ -147,7 +147,7 @@ const char *arc_hs_version(int arcver, char *name, int name_len)
bool dual_issue = arcver == 0x54 ? true : false;
int i;
for (i = 0; i++ < sizeof(hs_versions) / sizeof(struct hs_template_t);) {
for (i = 0; i < sizeof(hs_versions) / sizeof(struct hs_template_t); i++) {
if (hs_versions[i].cache == cache &&
hs_versions[i].mmu == mmu &&
hs_versions[i].dual_issue == dual_issue &&

View File

@@ -528,6 +528,12 @@ config ARCH_BCM283X
imply CMD_DM
imply FAT_WRITE
config ARCH_BCM63158
bool "Broadcom BCM63158 family"
select DM
select OF_CONTROL
imply CMD_DM
config ARCH_BCM6858
bool "Broadcom BCM6858 family"
select DM
@@ -846,10 +852,12 @@ config ARCH_SUNXI
select CMD_GPIO
select CMD_MMC if MMC
select CMD_USB if DISTRO_DEFAULTS
select CLK
select DM
select DM_ETH
select DM_GPIO
select DM_KEYBOARD
select DM_MMC if MMC
select DM_SERIAL
select DM_USB if DISTRO_DEFAULTS
select OF_BOARD_SETUP
@@ -886,6 +894,8 @@ config ARCH_VERSAL
select ARM64
select CLK
select DM
select DM_ETH if NET
select DM_MMC if MMC
select DM_SERIAL
select OF_CONTROL
@@ -929,6 +939,8 @@ config ARCH_ZYNQMP_R5
select CLK
select CPU_V7R
select DM
select DM_ETH if NET
select DM_MMC if MMC
select DM_SERIAL
select OF_CONTROL
imply CMD_DM
@@ -939,7 +951,11 @@ config ARCH_ZYNQMP
select ARM64
select CLK
select DM
select DM_ETH if NET
select DM_MMC if MMC
select DM_SERIAL
select DM_SPI if SPI
select DM_SPI_FLASH if DM_SPI
select DM_USB if USB
select OF_CONTROL
select SPL_BOARD_INIT if SPL
@@ -1495,14 +1511,14 @@ source "arch/arm/cpu/armv7/vf610/Kconfig"
source "arch/arm/mach-zynq/Kconfig"
source "arch/arm/mach-zynqmp/Kconfig"
source "arch/arm/mach-versal/Kconfig"
source "arch/arm/mach-zynqmp-r5/Kconfig"
source "arch/arm/cpu/armv7/Kconfig"
source "arch/arm/cpu/armv8/zynqmp/Kconfig"
source "arch/arm/cpu/armv8/Kconfig"
source "arch/arm/mach-imx/Kconfig"
@@ -1516,6 +1532,7 @@ source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"
source "board/broadcom/bcm23550_w1d/Kconfig"
source "board/broadcom/bcm28155_ap/Kconfig"
source "board/broadcom/bcm963158/Kconfig"
source "board/broadcom/bcm968580xref/Kconfig"
source "board/broadcom/bcmcygnus/Kconfig"
source "board/broadcom/bcmnsp/Kconfig"

View File

@@ -81,6 +81,7 @@ machine-$(CONFIG_ARCH_STM32MP) += stm32mp
machine-$(CONFIG_TEGRA) += tegra
machine-$(CONFIG_ARCH_UNIPHIER) += uniphier
machine-$(CONFIG_ARCH_ZYNQ) += zynq
machine-$(CONFIG_ARCH_ZYNQMP) += zynqmp
machine-$(CONFIG_ARCH_VERSAL) += versal
machine-$(CONFIG_ARCH_ZYNQMP_R5) += zynqmp-r5
@@ -103,7 +104,7 @@ libs-y += arch/arm/cpu/
libs-y += arch/arm/lib/
ifeq ($(CONFIG_SPL_BUILD),y)
ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m))
ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8))
libs-y += arch/arm/mach-imx/
endif
else

View File

@@ -8,8 +8,8 @@
* Aneesh V <aneesh@ti.com>
*/
MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
LENGTH = CONFIG_SPL_MAX_SIZE }
MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
LENGTH = IMAGE_MAX_SIZE }
MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
LENGTH = CONFIG_SPL_BSS_MAX_SIZE }

View File

@@ -15,7 +15,7 @@ OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = CONFIG_SPL_TEXT_BASE;
. = IMAGE_TEXT_BASE;
. = ALIGN(4);
.text :

View File

@@ -16,8 +16,8 @@
* Texas Instruments, <www.ti.com>
* Aneesh V <aneesh@ti.com>
*/
MEMORY { .nor : ORIGIN = CONFIG_SPL_TEXT_BASE,\
LENGTH = CONFIG_SPL_MAX_SIZE }
MEMORY { .nor : ORIGIN = IMAGE_TEXT_BASE,\
LENGTH = IMAGE_MAX_SIZE }
MEMORY { .bss : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
LENGTH = CONFIG_SPL_BSS_MAX_SIZE }

View File

@@ -12,8 +12,8 @@
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*/
MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
LENGTH = CONFIG_SPL_MAX_SIZE }
MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
LENGTH = IMAGE_MAX_SIZE }
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)

View File

@@ -14,6 +14,7 @@ obj-$(CONFIG_SYS_ARM_MPU) += mpu_v7r.o
ifneq ($(CONFIG_SPL_BUILD),y)
obj-$(CONFIG_EFI_LOADER) += sctlr.o
obj-$(CONFIG_ARMV7_NONSEC) += exception_level.o
endif
ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)

View File

@@ -0,0 +1,56 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Switch to non-secure mode
*
* Copyright (c) 2018 Heinrich Schuchardt
*
* This module contains the ARMv7 specific code required for leaving the
* secure mode before booting an operating system.
*/
#include <common.h>
#include <bootm.h>
#include <asm/armv7.h>
#include <asm/secure.h>
#include <asm/setjmp.h>
/**
* entry_non_secure() - entry point when switching to non-secure mode
*
* When switching to non-secure mode switch_to_non_secure_mode() calls this
* function passing a jump buffer. We use this jump buffer to restore the
* original stack and register state.
*
* @non_secure_jmp: jump buffer for restoring stack and registers
*/
static void entry_non_secure(struct jmp_buf_data *non_secure_jmp)
{
dcache_enable();
debug("Reached non-secure mode\n");
/* Restore stack and registers saved in switch_to_non_secure_mode() */
longjmp(non_secure_jmp, 1);
}
/**
* switch_to_non_secure_mode() - switch to non-secure mode
*
* Operating systems may expect to run in non-secure mode. Here we check if
* we are running in secure mode and switch to non-secure mode if necessary.
*/
void switch_to_non_secure_mode(void)
{
static bool is_nonsec;
struct jmp_buf_data non_secure_jmp;
if (armv7_boot_nonsec() && !is_nonsec) {
if (setjmp(&non_secure_jmp))
return;
dcache_disable(); /* flush cache before switch to HYP */
armv7_init_nonsec();
is_nonsec = true;
secure_ram_addr(_do_nonsec_entry)(entry_non_secure,
(uintptr_t)&non_secure_jmp,
0, 0);
}
}

View File

@@ -7,7 +7,9 @@
#include <asm/opcodes-sec.h>
#include <asm/opcodes-virt.h>
#ifdef CONFIG_EFI_LOADER
.section .text.efi_runtime
#endif
#define UNWIND(x...)
/*

View File

@@ -13,8 +13,8 @@
* Texas Instruments, <www.ti.com>
* Aneesh V <aneesh@ti.com>
*/
MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
LENGTH = CONFIG_SPL_MAX_SIZE }
MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
LENGTH = IMAGE_MAX_SIZE }
MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
LENGTH = CONFIG_SPL_BSS_MAX_SIZE }

View File

@@ -14,6 +14,7 @@ ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) += exceptions.o
else
obj-y += exceptions.o
obj-y += exception_level.o
endif
obj-y += cache.o
obj-y += tlb.o
@@ -29,7 +30,6 @@ obj-$(CONFIG_$(SPL_)ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o sec_firmware_a
obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
obj-$(CONFIG_S32V234) += s32v234/
obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
obj-$(CONFIG_ARMV8_PSCI) += psci.o
obj-$(CONFIG_ARCH_SUNXI) += lowlevel_init.o

View File

@@ -0,0 +1,55 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Switch to non-secure mode
*
* Copyright (c) 2018 Heinrich Schuchardt
*
* This module contains the ARMv8 specific code required to adjust the exception
* level before booting an operating system.
*/
#include <common.h>
#include <bootm.h>
#include <asm/setjmp.h>
/**
* entry_non_secure() - entry point when switching to non-secure mode
*
* When switching to non-secure mode switch_to_non_secure_mode() calls this
* function passing a jump buffer. We use this jump buffer to restore the
* original stack and register state.
*
* @non_secure_jmp: jump buffer for restoring stack and registers
*/
static void entry_non_secure(struct jmp_buf_data *non_secure_jmp)
{
dcache_enable();
debug("Reached non-secure mode\n");
/* Restore stack and registers saved in switch_to_non_secure_mode() */
longjmp(non_secure_jmp, 1);
}
/**
* switch_to_non_secure_mode() - switch to non-secure mode
*
* Exception level EL3 is meant to be used by the secure monitor only (ARM
* trusted firmware being one embodiment). The operating system shall be
* started at exception level EL2. So here we check the exception level
* and switch it if necessary.
*/
void switch_to_non_secure_mode(void)
{
struct jmp_buf_data non_secure_jmp;
/* On AArch64 we need to make sure we call our payload in < EL3 */
if (current_el() == 3) {
if (setjmp(&non_secure_jmp))
return;
dcache_disable(); /* flush cache before switch to EL2 */
/* Move into EL2 and keep running there */
armv8_switch_to_el2((uintptr_t)&non_secure_jmp, 0, 0, 0,
(uintptr_t)entry_non_secure, ES_TO_AARCH64);
}
}

View File

@@ -89,7 +89,7 @@ config ARCH_LS1046A
config ARCH_LS1088A
bool
select ARMV8_SET_SMPEN
select ARM_ERRATA_855873
select ARM_ERRATA_855873 if !TFABOOT
select FSL_LSCH3
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
@@ -98,11 +98,11 @@ config ARCH_LS1088A
select SYS_FSL_DDR_VER_50
select SYS_FSL_EC1
select SYS_FSL_EC2
select SYS_FSL_ERRATUM_A009803
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A008511
select SYS_FSL_ERRATUM_A008850
select SYS_FSL_ERRATUM_A009803 if !TFABOOT
select SYS_FSL_ERRATUM_A009942 if !TFABOOT
select SYS_FSL_ERRATUM_A010165 if !TFABOOT
select SYS_FSL_ERRATUM_A008511 if !TFABOOT
select SYS_FSL_ERRATUM_A008850 if !TFABOOT
select SYS_FSL_ERRATUM_A009007
select SYS_FSL_HAS_CCI400
select SYS_FSL_HAS_DDR4
@@ -145,20 +145,20 @@ config ARCH_LS2080A
select SYS_FSL_SRDS_2
select FSL_TZASC_1
select FSL_TZASC_2
select SYS_FSL_ERRATUM_A008336
select SYS_FSL_ERRATUM_A008511
select SYS_FSL_ERRATUM_A008514
select SYS_FSL_ERRATUM_A008336 if !TFABOOT
select SYS_FSL_ERRATUM_A008511 if !TFABOOT
select SYS_FSL_ERRATUM_A008514 if !TFABOOT
select SYS_FSL_ERRATUM_A008585
select SYS_FSL_ERRATUM_A008997
select SYS_FSL_ERRATUM_A009007
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009635
select SYS_FSL_ERRATUM_A009663
select SYS_FSL_ERRATUM_A009663 if !TFABOOT
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A009801
select SYS_FSL_ERRATUM_A009803
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A009803 if !TFABOOT
select SYS_FSL_ERRATUM_A009942 if !TFABOOT
select SYS_FSL_ERRATUM_A010165 if !TFABOOT
select SYS_FSL_ERRATUM_A009203
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F

View File

@@ -51,7 +51,9 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
CPU_TYPE_ENTRY(LS1043A, LS1043A_P23, 4),
CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
CPU_TYPE_ENTRY(LS1023A, LS1023A_P23, 2),
CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
@@ -675,7 +677,7 @@ enum boot_src __get_boot_src(u32 porsr1)
break;
case RCW_SRC_EMMC_VAL:
/* RCW SRC EMMC */
src = BOOT_SOURCE_SD_MMC2;
src = BOOT_SOURCE_SD_MMC;
break;
case RCW_SRC_I2C1_VAL:
/* RCW SRC I2C1 Extended */

View File

@@ -327,7 +327,7 @@ static int _fdt_fixup_pci_msi(void *blob, const char *name, int rev)
memcpy((char *)tmp, p, len);
val = fdt32_to_cpu(tmp[0][6]);
if (rev > REV1_0) {
if (rev == REV1_0) {
tmp[1][6] = cpu_to_fdt32(val + 1);
tmp[2][6] = cpu_to_fdt32(val + 2);
tmp[3][6] = cpu_to_fdt32(val + 3);

View File

@@ -684,7 +684,7 @@ int qspi_ahb_init(void)
#endif
#ifdef CONFIG_TFABOOT
#define MAX_BOOTCMD_SIZE 256
#define MAX_BOOTCMD_SIZE 512
int fsl_setenv_bootcmd(void)
{
@@ -812,6 +812,17 @@ int board_late_init(void)
fsl_setenv_bootcmd();
fsl_setenv_mcinitcmd();
}
/*
* If the boot mode is secure, default environment is not present then
* setenv command needs to be run by default
*/
#ifdef CONFIG_CHAIN_OF_TRUST
if ((fsl_check_boot_mode_secure() == 1)) {
fsl_setenv_bootcmd();
fsl_setenv_mcinitcmd();
}
#endif
#endif
#ifdef CONFIG_QSPI_AHB_INIT
qspi_ahb_init();

View File

@@ -6,7 +6,9 @@
#include <linux/arm-smccc.h>
#include <generated/asm-offsets.h>
#ifdef CONFIG_EFI_LOADER
.section .text.efi_runtime
#endif
.macro SMCCC instr
.cfi_startproc

View File

@@ -11,8 +11,8 @@
* Aneesh V <aneesh@ti.com>
*/
MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,
LENGTH = CONFIG_SPL_MAX_SIZE }
MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,
LENGTH = IMAGE_MAX_SIZE }
MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR,
LENGTH = CONFIG_SPL_BSS_MAX_SIZE }

View File

@@ -78,8 +78,8 @@ SECTIONS
.ARM.exidx : { *(.ARM.exidx*) }
}
#if defined(CONFIG_SPL_MAX_SIZE)
ASSERT(__image_copy_end - __image_copy_start < (CONFIG_SPL_MAX_SIZE), \
#if defined(IMAGE_MAX_SIZE)
ASSERT(__image_copy_end - __image_copy_start < (IMAGE_MAX_SIZE), \
"SPL image too big");
#endif

View File

@@ -40,6 +40,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-jerry.dtb \
rk3288-veyron-mickey.dtb \
rk3288-veyron-minnie.dtb \
rk3288-veyron-speedy.dtb \
rk3288-vyasa.dtb \
rk3328-evb.dtb \
rk3399-ficus.dtb \
@@ -95,6 +96,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
armada-3720-db.dtb \
armada-3720-espressobin.dtb \
armada-3720-turris-mox.dtb \
armada-3720-uDPU.dts \
armada-375-db.dtb \
armada-388-clearfog.dtb \
armada-388-gp.dtb \
@@ -109,7 +111,9 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
armada-xp-maxbcm.dtb \
armada-xp-synology-ds414.dtb \
armada-xp-theadorable.dtb \
armada-38x-controlcenterdc.dtb
armada-38x-controlcenterdc.dtb \
armada-385-atl-x530.dtb \
armada-385-atl-x530DP.dtb
dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
uniphier-ld11-global.dtb \
@@ -182,6 +186,10 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-zc1751-xm017-dc3.dtb \
zynqmp-zc1751-xm018-dc4.dtb \
zynqmp-zc1751-xm019-dc5.dtb
dtb-$(CONFIG_ARCH_VERSAL) += \
versal-mini.dtb \
versal-mini-emmc0.dtb \
versal-mini-emmc1.dtb
dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \
zynqmp-r5.dtb
dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \
@@ -192,8 +200,11 @@ dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \
am335x-icev2.dtb \
am335x-pxm50.dtb \
am335x-rut.dtb \
am335x-shc.dtb \
am335x-pdu001.dtb \
am335x-chiliboard.dtb
am335x-chiliboard.dtb \
am335x-sl50.dtb \
am335x-base0033.dtb
dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \
am43x-epos-evm.dtb \
am437x-idk-evm.dtb \
@@ -395,6 +406,7 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \
dtb-$(CONFIG_MACH_SUN8I_V3S) += \
sun8i-v3s-licheepi-zero.dtb
dtb-$(CONFIG_MACH_SUN50I_H5) += \
sun50i-h5-emlid-neutis-n5-devboard.dtb \
sun50i-h5-libretech-all-h3-cc.dtb \
sun50i-h5-nanopi-neo2.dtb \
sun50i-h5-nanopi-neo-plus2.dtb \
@@ -438,7 +450,13 @@ dtb-$(CONFIG_MX6QDL) += \
imx6q-icore.dtb \
imx6q-icore-mipi.dtb \
imx6q-icore-rqs.dtb \
imx6q-logicpd.dtb
imx6q-logicpd.dtb \
imx6q-sabreauto.dtb \
imx6q-sabresd.dtb \
imx6dl-sabreauto.dtb \
imx6dl-sabresd.dtb \
imx6qp-sabreauto.dtb \
imx6qp-sabresd.dtb
dtb-$(CONFIG_MX6SL) += imx6sl-evk.dtb
@@ -454,12 +472,14 @@ dtb-$(CONFIG_MX6UL) += \
imx6ul-isiot-nand.dtb \
imx6ul-opos6uldev.dtb \
imx6ul-14x14-evk.dtb \
imx6ul-9x9-evk.dtb
imx6ul-9x9-evk.dtb \
imx6ul-9x9-evk.dtb \
imx6ul-liteboard.dtb \
imx6ul-phycore-segin.dtb
dtb-$(CONFIG_MX6ULL) += imx6ull-14x14-evk.dtb
dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
imx7d-sdb.dtb \
dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
imx7d-sdb-qspi.dtb
dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
@@ -522,6 +542,9 @@ dtb-$(CONFIG_TARGET_OMAP3_BEAGLE) += \
omap3-beagle-xm.dtb \
omap3-beagle.dtb
dtb-$(CONFIG_TARGET_OMAP3_IGEP00X0) += \
omap3-igep0020.dtb
dtb-$(CONFIG_TARGET_SAMA5D2_PTC_EK) += \
at91-sama5d2_ptc_ek.dtb

View File

@@ -0,0 +1,95 @@
/*
* am335x-base0033.dts - Device Tree file for IGEP AQUILA EXPANSION
*
* Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "am335x-igep0033.dtsi"
/ {
model = "IGEP COM AM335x on AQUILA Expansion";
compatible = "isee,am335x-base0033", "isee,am335x-igep0033", "ti,am33xx";
hdmi {
compatible = "ti,tilcdc,slave";
i2c = <&i2c0>;
pinctrl-names = "default", "off";
pinctrl-0 = <&nxp_hdmi_pins>;
pinctrl-1 = <&nxp_hdmi_off_pins>;
status = "okay";
};
leds_base {
pinctrl-names = "default";
pinctrl-0 = <&leds_base_pins>;
compatible = "gpio-leds";
led0 {
label = "base:red:user";
gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; /* gpio1_21 */
default-state = "off";
};
led1 {
label = "base:green:user";
gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; /* gpio2_0 */
default-state = "off";
};
};
};
&am33xx_pinmux {
nxp_hdmi_pins: pinmux_nxp_hdmi_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */
AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0 */
AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1 */
AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2 */
AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3 */
AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4 */
AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5 */
AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6 */
AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7 */
AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8 */
AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9 */
AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10 */
AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11 */
AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12 */
AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13 */
AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14 */
AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15 */
AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync */
AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync */
AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk */
AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en */
>;
};
nxp_hdmi_off_pins: pinmux_nxp_hdmi_off_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */
>;
};
leds_base_pins: pinmux_leds_base_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
AM33XX_IOPAD(0x888, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.gpio2_0 */
>;
};
};
&lcdc {
status = "okay";
};
&i2c0 {
eeprom: eeprom@50 {
compatible = "atmel,24c256";
reg = <0x50>;
};
};

View File

@@ -7,3 +7,7 @@
&mmc3 {
status = "disabled";
};
&usb0 {
dr_mode = "peripheral";
};

View File

@@ -0,0 +1,323 @@
/*
* am335x-igep0033.dtsi - Device Tree file for IGEP COM AQUILA AM335x
*
* Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "am33xx.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
/ {
cpus {
cpu@0 {
cpu0-supply = <&vdd1_reg>;
};
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};
leds {
pinctrl-names = "default";
pinctrl-0 = <&leds_pins>;
compatible = "gpio-leds";
led0 {
label = "com:green:user";
gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
vbat: fixedregulator0 {
compatible = "regulator-fixed";
regulator-name = "vbat";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
};
vmmc: fixedregulator1 {
compatible = "regulator-fixed";
regulator-name = "vmmc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&am33xx_pinmux {
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};
nandflash_pins: pinmux_nandflash_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};
leds_pins: pinmux_leds_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */
>;
};
};
&mac {
status = "okay";
};
&davinci_mdio {
status = "okay";
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rmii";
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "rmii";
};
&phy_sel {
rmii-clock-ext;
};
&elm {
status = "okay";
};
&gpmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nandflash_pins>;
ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
nand-bus-width = <8>;
ti,nand-ecc-opt = "bch8";
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <40>;
gpmc,oe-on-ns = <0>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
#address-cells = <1>;
#size-cells = <1>;
ti,elm-id = <&elm>;
/* MTD partition table */
partition@0 {
label = "SPL";
reg = <0x00000000 0x000080000>;
};
partition@1 {
label = "U-boot";
reg = <0x00080000 0x001e0000>;
};
partition@2 {
label = "U-Boot Env";
reg = <0x00260000 0x00020000>;
};
partition@3 {
label = "Kernel";
reg = <0x00280000 0x00500000>;
};
partition@4 {
label = "File System";
reg = <0x00780000 0x007880000>;
};
};
};
&i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
clock-frequency = <400000>;
tps: tps@2d {
reg = <0x2d>;
};
};
&mmc1 {
status = "okay";
vmmc-supply = <&vmmc>;
bus-width = <4>;
};
&uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
dr_mode = "host";
};
&cppi41dma {
status = "okay";
};
#include "tps65910.dtsi"
&tps {
vcc1-supply = <&vbat>;
vcc2-supply = <&vbat>;
vcc3-supply = <&vbat>;
vcc4-supply = <&vbat>;
vcc5-supply = <&vbat>;
vcc6-supply = <&vbat>;
vcc7-supply = <&vbat>;
vccio-supply = <&vbat>;
regulators {
vrtc_reg: regulator@0 {
regulator-always-on;
};
vio_reg: regulator@1 {
regulator-always-on;
};
vdd1_reg: regulator@2 {
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
regulator-name = "vdd_mpu";
regulator-min-microvolt = <912500>;
regulator-max-microvolt = <1312500>;
regulator-boot-on;
regulator-always-on;
};
vdd2_reg: regulator@3 {
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
regulator-name = "vdd_core";
regulator-min-microvolt = <912500>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
vdd3_reg: regulator@4 {
regulator-always-on;
};
vdig1_reg: regulator@5 {
regulator-always-on;
};
vdig2_reg: regulator@6 {
regulator-always-on;
};
vpll_reg: regulator@7 {
regulator-always-on;
};
vdac_reg: regulator@8 {
regulator-always-on;
};
vaux1_reg: regulator@9 {
regulator-always-on;
};
vaux2_reg: regulator@10 {
regulator-always-on;
};
vaux33_reg: regulator@11 {
regulator-always-on;
};
vmmc_reg: regulator@12 {
regulator-always-on;
};
};
};

View File

@@ -1,4 +1,3 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* pdu001.dts
*
@@ -7,6 +6,8 @@
* Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
@@ -17,7 +18,7 @@
/ {
model = "EETS,PDU001";
compatible = "eets,pdu001", "ti,am33xx";
compatible = "ti,am33xx";
chosen {
stdout-path = &uart3;
@@ -303,12 +304,12 @@
clock-frequency = <100000>;
board_24aa025e48: board_24aa025e48@50 {
compatible = "microchip,24aa025e48";
compatible = "atmel,24c02";
reg = <0x50>;
};
backplane_24aa025e48: backplane_24aa025e48@53 {
compatible = "microchip,24aa025e48";
compatible = "atmel,24c02";
reg = <0x53>;
};
@@ -372,8 +373,8 @@
ti,pindir-d0-out-d1-in;
status = "okay";
cfaf240320a032t {
compatible = "orise,otm3225a";
display-controller@0 {
compatible = "orisetech,otm3225a";
reg = <0>;
spi-max-frequency = <1000000>;
// SPI mode 3
@@ -532,16 +533,24 @@
pinctrl-names = "default";
pinctrl-0 = <&davinci_mdio_default>;
status = "okay";
ethphy0: ethernet-phy@0 {
reg = <0>;
};
ethphy1: ethernet-phy@1 {
reg = <1>;
};
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-handle = <&ethphy0>;
phy-mode = "mii";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-handle = <&ethphy1>;
phy-mode = "mii";
dual_emac_res_vlan = <2>;
};

View File

@@ -0,0 +1,51 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
*/
/ {
ocp {
u-boot,dm-pre-reloc;
};
};
&l4_wkup {
u-boot,dm-pre-reloc;
};
&scm {
u-boot,dm-pre-reloc;
};
&am33xx_pinmux {
u-boot,dm-pre-reloc;
};
&uart0_pins {
u-boot,dm-pre-reloc;
};
&uart0 {
u-boot,dm-pre-reloc;
};
&mmc1 {
u-boot,dm-pre-reloc;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
};
&emmc_pins {
u-boot,dm-pre-reloc;
};
&mmc2 {
u-boot,dm-pre-reloc;
};
&mmc1_pins {
u-boot,dm-pre-reloc;
};
&mmc3 {
status = "disabled";
};

575
arch/arm/dts/am335x-shc.dts Normal file
View File

@@ -0,0 +1,575 @@
// SPDX-License-Identifier: GPL-2.0
/*
* support for the bosch am335x based shc c3 board
*
* Copyright, (C) 2015 Heiko Schocher <hs@denx.de>
*
*/
/dts-v1/;
#include "am33xx.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Bosch SHC";
compatible = "ti,am335x-shc", "ti,am335x-bone", "ti,am33xx";
aliases {
mmcblk0 = &mmc1;
mmcblk1 = &mmc2;
};
cpus {
cpu@0 {
/*
* To consider voltage drop between PMIC and SoC,
* tolerance value is reduced to 2% from 4% and
* voltage value is increased as a precaution.
*/
operating-points = <
/* kHz uV */
594000 1225000
294000 1125000
>;
voltage-tolerance = <2>; /* 2 percentage */
cpu0-supply = <&dcdc2_reg>;
};
};
gpio_keys {
compatible = "gpio-keys";
back_button {
label = "Back Button";
gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_BACK>;
debounce-interval = <1000>;
wakeup-source;
};
front_button {
label = "Front Button";
gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_FRONT>;
debounce-interval = <1000>;
wakeup-source;
};
};
leds {
pinctrl-names = "default";
pinctrl-0 = <&user_leds_s0>;
compatible = "gpio-leds";
led1 {
label = "shc:power:red";
gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led2 {
label = "shc:power:bl";
gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "timer";
default-state = "on";
};
led3 {
label = "shc:lan:red";
gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led4 {
label = "shc:lan:bl";
gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led5 {
label = "shc:cloud:red";
gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led6 {
label = "shc:cloud:bl";
gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512 MB */
};
vmmcsd_fixed: fixedregulator0 {
compatible = "regulator-fixed";
regulator-name = "vmmcsd_fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&aes {
status = "okay";
};
&cppi41dma {
status = "okay";
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
ethernetphy0: ethernet-phy@0 {
reg = <0>;
smsc,disable-energy-detect;
};
};
&epwmss1 {
status = "okay";
ehrpwm1: pwm@48302200 {
pinctrl-names = "default";
pinctrl-0 = <&ehrpwm1_pins>;
status = "okay";
};
};
&gpio1 {
hmtc_rst {
gpio-hog;
gpios = <24 GPIO_ACTIVE_LOW>;
output-high;
line-name = "homematic_reset";
};
hmtc_prog {
gpio-hog;
gpios = <27 GPIO_ACTIVE_LOW>;
output-high;
line-name = "homematic_program";
};
};
&gpio3 {
zgb_rst {
gpio-hog;
gpios = <18 GPIO_ACTIVE_LOW>;
output-low;
line-name = "zigbee_reset";
};
zgb_boot {
gpio-hog;
gpios = <19 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "zigbee_boot";
};
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
clock-frequency = <400000>;
tps: tps@24 {
reg = <0x24>;
};
at24@50 {
compatible = "atmel,24c32";
pagesize = <32>;
reg = <0x50>;
};
pcf8563@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
&mac {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
status = "okay";
slaves = <1>;
cpsw_emac0: slave@4a100200 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "mii";
phy-handle = <&ethernetphy0>;
};
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
bus-width = <0x4>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
cd-inverted;
max-frequency = <26000000>;
vmmc-supply = <&vmmcsd_fixed>;
status = "okay";
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&emmc_pins>;
bus-width = <8>;
max-frequency = <26000000>;
sd-uhs-sdr25;
vmmc-supply = <&vmmcsd_fixed>;
status = "okay";
};
&mmc3 {
pinctrl-names = "default";
pinctrl-0 = <&mmc3_pins>;
bus-width = <4>;
cap-power-off-card;
max-frequency = <26000000>;
sd-uhs-sdr25;
vmmc-supply = <&vmmcsd_fixed>;
status = "okay";
};
&rtc {
ti,no-init;
};
&sham {
status = "okay";
};
&tps {
compatible = "ti,tps65217";
ti,pmic-shutdown-controller;
regulators {
#address-cells = <1>;
#size-cells = <0>;
dcdc1_reg: regulator@0 {
reg = <0>;
regulator-name = "vdds_dpr";
regulator-compatible = "dcdc1";
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1450000>;
regulator-boot-on;
regulator-always-on;
};
dcdc2_reg: regulator@1 {
reg = <1>;
/*
* VDD_MPU voltage limits 0.95V - 1.26V with
* +/-4% tolerance
*/
regulator-compatible = "dcdc2";
regulator-name = "vdd_mpu";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1375000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <70000>;
};
dcdc3_reg: regulator@2 {
reg = <2>;
/*
* VDD_CORE voltage limits 0.95V - 1.1V with
* +/-4% tolerance
*/
regulator-name = "vdd_core";
regulator-compatible = "dcdc3";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1125000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: regulator@3 {
reg = <3>;
regulator-name = "vio,vrtc,vdds";
regulator-compatible = "ldo1";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo2_reg: regulator@4 {
reg = <4>;
regulator-name = "vdd_3v3aux";
regulator-compatible = "ldo2";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
ldo3_reg: regulator@5 {
reg = <5>;
regulator-name = "vdd_1v8";
regulator-compatible = "ldo3";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo4_reg: regulator@6 {
reg = <6>;
regulator-name = "vdd_3v3a";
regulator-compatible = "ldo4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins>;
status = "okay";
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb1_phy {
status = "okay";
};
&usb1 {
status = "okay";
dr_mode = "host";
};
&am33xx_pinmux {
pinctrl-names = "default";
pinctrl-0 = <&clkout2_pin>;
clkout2_pin: pinmux_clkout2_pin {
pinctrl-single,pins = <
/* xdma_event_intr1.clkout2 */
AM33XX_IOPAD(0x9b4, PIN_INPUT | MUX_MODE6)
>;
};
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE0)
AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE0)
AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE0)
AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE0)
AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0)
AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE0)
AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE0)
AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE0)
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE0)
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE0)
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 reset value */
AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* mdio_data.mdio_data */
AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
/* mdio_clk.mdio_clk */
AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
/* MDIO reset value */
AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
ehrpwm1_pins: pinmux_ehrpwm1 {
pinctrl-single,pins = <
AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE6) /* gpmc_a3.gpio1_19 */
>;
};
emmc_pins: pinmux_emmc_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x880, PIN_INPUT | MUX_MODE2)
AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2)
AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1)
AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1)
AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1)
AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1)
AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1)
AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1)
AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1)
AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1)
>;
};
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0)
AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0)
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE5)
>;
};
mmc3_pins: pinmux_mmc3_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x830, PIN_INPUT | MUX_MODE3)
AM33XX_IOPAD(0x834, PIN_INPUT | MUX_MODE3)
AM33XX_IOPAD(0x838, PIN_INPUT | MUX_MODE3)
AM33XX_IOPAD(0x83c, PIN_INPUT | MUX_MODE3)
AM33XX_IOPAD(0x888, PIN_INPUT | MUX_MODE3)
AM33XX_IOPAD(0x88c, PIN_INPUT | MUX_MODE3)
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x968, PIN_INPUT_PULLDOWN | MUX_MODE0)
AM33XX_IOPAD(0x96c, PIN_OUTPUT | MUX_MODE0)
AM33XX_IOPAD(0x970, PIN_INPUT_PULLDOWN | MUX_MODE0)
AM33XX_IOPAD(0x974, PIN_OUTPUT | MUX_MODE0)
>;
};
uart1_pins: pinmux_uart1 {
pinctrl-single,pins = <
AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE0)
AM33XX_IOPAD(0x97C, PIN_OUTPUT | MUX_MODE0)
AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0)
AM33XX_IOPAD(0x984, PIN_OUTPUT | MUX_MODE0)
>;
};
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1)
AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1)
>;
};
uart4_pins: pinmux_uart4_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6)
AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE6)
>;
};
user_leds_s0: user_leds_s0 {
pinctrl-single,pins = <
AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x844, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLUP | MUX_MODE7)
AM33XX_IOPAD(0x860, PIN_INPUT | MUX_MODE7)
AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE7)
AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE7)
AM33XX_IOPAD(0x86c, PIN_INPUT | MUX_MODE7)
AM33XX_IOPAD(0x878, PIN_OUTPUT_PULLUP | MUX_MODE7)
AM33XX_IOPAD(0x87c, PIN_INPUT | MUX_MODE7)
AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x894, PIN_INPUT | MUX_MODE7)
AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x958, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x964, PIN_OUTPUT_PULLUP | MUX_MODE7)
AM33XX_IOPAD(0x9a0, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLUP | MUX_MODE7)
>;
};
};

View File

@@ -0,0 +1,549 @@
/*
* Copyright (C) 2015 Toby Churchill - http://www.toby-churchill.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "am33xx.dtsi"
/ {
model = "Toby Churchill SL50 Series";
compatible = "tcl,am335x-sl50", "ti,am33xx";
cpus {
cpu@0 {
cpu0-supply = <&dcdc2_reg>;
};
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512 MB */
};
chosen {
stdout-path = &uart0;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins>;
led0 {
label = "sl50:green:usr0";
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led1 {
label = "sl50:red:usr1";
gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led2 {
label = "sl50:green:usr2";
gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led3 {
label = "sl50:red:usr3";
gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
backlight0: disp0 {
compatible = "pwm-backlight";
pwms = <&ehrpwm1 0 500000 0>;
brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>;
default-brightness-level = <6>;
};
backlight1: disp1 {
compatible = "pwm-backlight";
pwms = <&ehrpwm1 1 500000 0>;
brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>;
default-brightness-level = <6>;
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
/* audio external oscillator */
tlv320aic3x_mclk: oscillator@0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>; /* 24.576MHz */
};
};
sound {
compatible = "ti,da830-evm-audio";
ti,model = "AM335x-SL50";
ti,audio-codec = <&audio_codec>;
ti,mcasp-controller = <&mcasp0>;
clocks = <&tlv320aic3x_mclk>;
clock-names = "mclk";
ti,audio-routing =
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT",
"LINE1R", "Line In",
"LINE1L", "Line In";
};
emmc_pwrseq: pwrseq@0 {
compatible = "mmc-pwrseq-emmc";
pinctrl-names = "default";
pinctrl-0 = <&emmc_pwrseq_pins>;
reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
};
vmmcsd_fixed: fixedregulator0 {
compatible = "regulator-fixed";
regulator-name = "vmmcsd_fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&am33xx_pinmux {
pinctrl-names = "default";
pinctrl-0 = <&lwb_pins>;
led_pins: pinmux_led_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7) /* gpmc_a5.gpio1_21 */
AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7) /* gpmc_a6.gpio1_22 */
AM33XX_IOPAD(0x85c, PIN_OUTPUT | MUX_MODE7) /* gpmc_a7.gpio1_23 */
AM33XX_IOPAD(0x860, PIN_OUTPUT | MUX_MODE7) /* gpmc_a8.gpio1_24 */
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};
uart1_pins: pinmux_uart1_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
>;
};
uart4_pins: pinmux_uart4_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6) /* gpmc_wait0.uart4_rxd */
AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* gpmc_wpn.uart4_txd */
>;
};
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};
i2c2_pins: pinmux_i2c2_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda */
AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl */
>;
};
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */
AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
AM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */
AM33XX_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
AM33XX_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 reset value */
AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
/* MDIO reset value */
AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x96c, PIN_INPUT | MUX_MODE7) /* uart0_rtsn.gpio1_9 */
>;
};
emmc_pwrseq_pins: pinmux_emmc_pwrseq_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a4.gpio1_20 */
>;
};
emmc_pins: pinmux_emmc_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
>;
};
audio_pins: pinmux_audio_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */
AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */
AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */
AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */
AM33XX_IOPAD(0x99c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2 */
>;
};
ehrpwm1_pins: pinmux_ehrpwm1a_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE6) /* gpmc_a2.ehrpwm1a */
AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE6) /* gpmc_a3.ehrpwm1b */
>;
};
spi0_pins: pinmux_spi0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* SPI0_MOSI - spi0_d0.spi0_d0 */
AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* SPI0_MISO - spi0_d1.spi0_d1 */
AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* SPI0_CLK - spi0_clk.spi0_clk */
AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* SPI0_CS0 (NBATTSS) - spi0_cs0.spi0_cs0 */
AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE0) /* SPI0_CS1 (FPGA_FLASH_NCS) - spi0_cs1.spi0_cs1 */
>;
};
lwb_pins: pinmux_lwb_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x9a4, PIN_OUTPUT | MUX_MODE7) /* SoundPA_en - mcasp0_fsr.gpio3_19 */
AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7) /* nKbdOnC - gpmc_ad10.gpio0_26 */
AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE7) /* nKbdInt - gpmc_ad12.gpio1_12 */
AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE7) /* nKbdReset - gpmc_ad13.gpio1_13 */
AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE7) /* nDispReset - gpmc_ad14.gpio1_14 */
AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* USB1_enPower - gpmc_a1.gpio1_17 */
/* PDI Bus - Battery system */
AM33XX_IOPAD(0x840, PIN_INPUT_PULLUP | MUX_MODE7) /* nBattReset gpmc_a0.gpio1_16 */
AM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE7) /* BattPDIData gpmc_ad15.gpio1_15 */
>;
};
};
&i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
clock-frequency = <400000>;
tps: tps@24 {
reg = <0x24>;
};
bq32000: rtc@68 {
compatible = "ti,bq32000";
trickle-resistor-ohms = <1120>;
reg = <0x68>;
};
eeprom: eeprom@50 {
compatible = "atmel,24c256";
reg = <0x50>;
};
gpio_exp: mcp23017@20 {
compatible = "microchip,mcp23017";
reg = <0x20>;
};
};
&i2c2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
clock-frequency = <400000>;
audio_codec: tlv320aic3106@1b {
status = "okay";
compatible = "ti,tlv320aic3106";
reg = <0x1b>;
AVDD-supply = <&ldo4_reg>;
IOVDD-supply = <&ldo4_reg>;
DRVDD-supply = <&ldo4_reg>;
DVDD-supply = <&ldo3_reg>;
};
/* Ambient Light Sensor */
als: isl29023@44 {
compatible = "isil,isl29023";
reg = <0x44>;
};
};
&rtc {
status = "disabled";
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "peripheral";
};
&usb1 {
status = "okay";
dr_mode = "host";
};
&cppi41dma {
status = "okay";
};
&mmc1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
bus-width = <4>;
cd-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
vmmc-supply = <&vmmcsd_fixed>;
};
&mmc2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&emmc_pins>;
bus-width = <8>;
vmmc-supply = <&vmmcsd_fixed>;
mmc-pwrseq = <&emmc_pwrseq>;
};
&mcasp0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&audio_pins>;
op-mode = <0>; /* MCASP_ISS_MODE */
tdm-slots = <2>;
serial-dir = <
2 0 1 0
0 0 0 0
0 0 0 0
0 0 0 0
>;
tx-num-evt = <1>;
rx-num-evt = <1>;
};
&uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
};
&uart4 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins>;
};
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
flash: n25q032@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q032";
reg = <1>;
spi-max-frequency = <5000000>;
};
};
#include "tps65217.dtsi"
&tps {
ti,pmic-shutdown-controller;
interrupt-parent = <&intc>;
interrupts = <7>; /* NNMI */
regulators {
dcdc1_reg: regulator@0 {
/* VDDS_DDR */
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
};
dcdc2_reg: regulator@1 {
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
regulator-name = "vdd_mpu";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1325000>;
regulator-boot-on;
regulator-always-on;
};
dcdc3_reg: regulator@2 {
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
regulator-name = "vdd_core";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: regulator@3 {
/* VRTC / VIO / VDDS*/
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo2_reg: regulator@4 {
/* VDD_3V3AUX */
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldo3_reg: regulator@5 {
/* VDD_1V8 */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo4_reg: regulator@6 {
/* VDD_3V3A */
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "mii";
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "mii";
};
&mac {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
};
&davinci_mdio {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
};
&sham {
status = "okay";
};
&aes {
status = "okay";
};
&epwmss1 {
status = "okay";
};
&ehrpwm1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ehrpwm1_pins>;
};

View File

@@ -0,0 +1,11 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 B&R Industrial Automation GmbH -
* https://www.br-automation.com/
*/
/ {
ocp {
u-boot,dm-pre-reloc;
};
};

View File

@@ -20,6 +20,10 @@
display0 = &lcd0;
};
chosen {
stdout-path = &uart3;
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */

View File

@@ -3,6 +3,13 @@
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
*/
/{
aliases {
usb0 = &usb1;
usb1 = &usb2;
};
};
&am43xx_control_usb2phy1 {
compatible = "ti,control-phy-usb2-am437", "syscon";
};
@@ -38,3 +45,23 @@
&ocp2scp0 {
u-boot,dm-spl;
};
&dwc3_2 {
u-boot,dm-spl;
};
&usb2 {
u-boot,dm-spl;
};
&usb2_phy2 {
u-boot,dm-spl;
};
&am43xx_control_usb2phy2 {
u-boot,dm-spl;
};
&ocp2scp1 {
u-boot,dm-spl;
};

View File

@@ -24,6 +24,7 @@
aliases {
ethernet0 = &eth0;
ethernet1 = &eth1;
i2c0 = &i2c0;
spi0 = &spi0;
};
@@ -38,12 +39,16 @@
regulator-name = "usb3-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
startup-delay-us = <2000000>;
shutdown-delay-us = <1000000>;
gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
regulator-boot-on;
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
eth_phy1: ethernet-phy@1 {
reg = <1>;
};
@@ -59,7 +64,7 @@
phy1 {
phy-type = <PHY_TYPE_PEX0>;
phy-speed = <PHY_SPEED_2_5G>;
phy-speed = <PHY_SPEED_5G>;
};
phy2 {
@@ -80,6 +85,11 @@
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
rtc@6f {
compatible = "microchip,mcp7941x";
reg = <0x6f>;
};
};
&sdhci1 {
@@ -110,6 +120,17 @@
spi-max-frequency = <20000000>;
m25p,fast-read;
};
moxtet@1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "cznic,moxtet";
reg = <1>;
reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
spi-max-frequency = <1000000>;
spi-cpol;
spi-cpha;
};
};
&uart0 {

View File

@@ -0,0 +1,13 @@
// SPDX-License-Identifier: GPL-2.0+
&spi0 {
u-boot,dm-pre-reloc;
spi-flash@0 {
u-boot,dm-pre-reloc;
};
};
&sdhci1 {
u-boot,dm-pre-reloc;
};

View File

@@ -0,0 +1,200 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device tree for the uDPU board.
* Based on Marvell Armada 3720 development board (DB-88F3720-DDR3)
* Copyright (C) 2016 Marvell
* Copyright (C) 2018 Methode
* Copyright (C) 2018 Telus
*
* Vladimir Vid <vladimir.vid@sartura.hr>
*/
/dts-v1/;
#include "armada-37xx.dtsi"
#include "armada-3720-uDPU-u-boot.dtsi"
/ {
model = "Methode uDPU Board";
compatible = "methode,udpu";
chosen {
stdout-path = "serial0:115200n8";
bootargs = "console=ttyMV0,115200 earlycon=ar3700_uart,0xd0012000";
};
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
spi0 = &spi0;
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
};
mdio: mdio@32004 {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
reg = <0>;
};
ethphy1: ethernet-phy@1 {
reg = <1>;
};
};
scsi: scsi {
compatible = "marvell,mvebu-scsi";
#address-cells = <1>;
#size-cells = <1>;
max-id = <1>;
max-lun = <1>;
status = "okay";
};
i2c1: i2c@11080 {
compatible = "marvell,armada-3700-i2c", "simple-bus";
reg = <0x0 0x11080 0x0 0x80>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
#address-cells = <2>;
#size-cells = <2>;
status = "okay";
};
uart1: serial@12200 {
compatible = "marvell,armada-3700-uart-ext";
reg = <0x0 0x12200 0x0 0x30>;
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
#address-cells = <2>;
#size-cells = <2>;
};
vcc_sd_reg0: regulator@0 {
compatible = "regulator-gpio";
regulator-name = "vcc_sd0";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-type = "voltage";
states = <1800000 0x1
3300000 0x0>;
gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
};
sfp_eth0: sfp-eth0 {
compatible = "sff,sfp";
i2c-bus = <&i2c0>;
los-gpio = <&gpiosb 2 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpiosb 3 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpiosb 4 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&gpiosb 5 GPIO_ACTIVE_HIGH>;
};
sfp_eth1: sfp-eth1 {
compatible = "sff,sfp";
i2c-bus = <&i2c1>;
sfp,ethernet = <&eth1>;
los-gpio = <&gpiosb 7 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpiosb 8 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpiosb 9 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&gpiosb 10 GPIO_ACTIVE_HIGH>;
};
};
&comphy {
phy0 {
phy-type = <PHY_TYPE_SGMII1>;
phy-speed = <PHY_SPEED_1_25G>;
};
phy1 {
phy-type = <PHY_TYPE_SGMII0>;
phy-speed = <PHY_SPEED_1_25G>;
};
phy2 {
phy-type = <PHY_TYPE_USB3_HOST1>;
phy-speed = <PHY_SPEED_5G>;
};
};
&eth0 {
pinctrl-0 = <&pcie_pins>;
status = "okay";
phy-mode = "sgmii";
phy = <&ethphy0>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&eth1 {
status = "okay";
phy-mode = "sgmii";
phy = <&ethphy1>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
};
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi_quad_pins>;
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q1024a","n25q512a";
reg = <0>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
m25p,fast-read;
partition@0 {
label = "uboot";
reg = <0 0x400000>;
};
};
};
&sdhci1 {
non-removable;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
bus-width = <4>;
vqmmc-supply = <&vcc_sd_reg0>;
pinctrl-names = "default";
pinctrl-0 = <&sdio_pins>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
mmccard: mmccard@0 {
compatible = "mmc-card";
reg = <0>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
&usb3 {
status = "okay";
};

View File

@@ -582,7 +582,7 @@
};
};
pcie-controller {
pciec: pcie@82000000 {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
@@ -601,7 +601,7 @@
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
pcie@1,0 {
pcie0: pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
@@ -610,6 +610,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <0>;
@@ -618,7 +619,7 @@
status = "disabled";
};
pcie@2,0 {
pcie1: pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
@@ -627,6 +628,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <0>;

View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 380 SoC.
*
@@ -6,44 +7,6 @@
* Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "armada-38x.dtsi"
@@ -71,7 +34,7 @@
};
};
pcie-controller {
pcie {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
@@ -104,6 +67,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <0>;
@@ -122,6 +86,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <1>;
@@ -140,6 +105,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <2>;

View File

@@ -0,0 +1,13 @@
// SPDX-License-Identifier: GPL-2.0
&spi1 {
u-boot,dm-pre-reloc;
spi-flash@0 {
u-boot,dm-pre-reloc;
};
};
&uart0 {
u-boot,dm-pre-reloc;
};

View File

@@ -0,0 +1,50 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "armada-385-atl-x530.dtsi"
#include "armada-385-atl-x530-u-boot.dtsi"
/ {
model = "Allied Telesis x530";
compatible = "alliedtelesis,x530", "marvell,armada385", "marvell,armada380";
nand-protect {
compatible = "atl,nand-protect";
protect-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
};
usb-enable {
compatible = "atl,usb-enable";
enable-gpio = <&gpio0 19 GPIO_ACTIVE_HIGH>;
};
boot-board {
compatible = "atl,boot-board";
present-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
override-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
};
phy-reset {
compatible = "atl,phy-reset";
reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>,
<&gpio1 21 GPIO_ACTIVE_HIGH>;
};
led-enable {
compatible = "atl,led-enable";
enable-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
};
led_7seg {
compatible = "atl,of-led-7seg";
segment-gpios = <
&led_7seg_gpio 0 0
&led_7seg_gpio 1 0
&led_7seg_gpio 2 0
&led_7seg_gpio 3 0
&led_7seg_gpio 4 0
&led_7seg_gpio 5 0
&led_7seg_gpio 6 0
&led_7seg_gpio 7 0>;
};
};

View File

@@ -0,0 +1,266 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/gpio/gpio.h>
#include "armada-385.dtsi"
/ {
model = "Allied Telesis x530";
compatible = "alliedtelesis,x530", "marvell,armada385", "marvell,armada380";
chosen {
stdout-path = "serial0:115200n8";
bootargs = "console=ttyS0,115200 earlyprintk";
};
aliases {
spi1 = &spi1;
i2c0 = &i2c0;
};
memory {
device_type = "memory";
reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x3d) 0 0xf4800000 0x80000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
pcie-mem-aperture = <0xa0000000 0x40000000>;
};
eco-button-interrupt {
compatible = "atl,eco-button-interrupt";
eco-button-gpio = <&gpio0 14 GPIO_ACTIVE_LOW>;
};
board-reset {
compatible = "atl,phy_reset";
/* Physical board layout of reset pin is active-low but for the
* current driver we have to set it to active-high here.
*/
phy-reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>,
<&gpio1 21 GPIO_ACTIVE_HIGH>;
};
phy-int {
compatible = "linux,uio-pdrv-genirq";
interrupt-parent = <&gpio0>;
interrupts = <6 IRQ_TYPE_EDGE_BOTH>;
};
led-enable {
compatible = "atl,led-enable";
led-enable-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
};
led_7seg {
compatible = "atl,of-led-7seg";
segment-gpios = <
&led_7seg_gpio 0 0
&led_7seg_gpio 1 0
&led_7seg_gpio 2 0
&led_7seg_gpio 3 0
&led_7seg_gpio 4 0
&led_7seg_gpio 5 0
&led_7seg_gpio 6 0
&led_7seg_gpio 7 0>;
};
poe {
compatible = "atl,periph-poe";
poe-reset-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
interrupt-parent = <&gpio0>;
interrupts = <20 IRQ_TYPE_EDGE_BOTH>;
};
};
&pciec {
status = "okay";
};
&pcie1 {
status = "okay";
};
&devbus_cs1 {
compatible = "marvell,mvebu-devbus";
status = "okay";
devbus,bus-width = <8>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>;
/* Write parameters */
devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>;
nvs@0 {
status = "okay";
compatible = "mtd-ram";
reg = <0 0x00080000>;
bank-width = <1>;
label = "nvs";
};
};
&gpio0 {
poe-disable {
gpio-hog;
gpios = <16 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "poe-disable";
};
};
&gpio1 {
poe-mezz-reset {
gpio-hog;
gpios = <15 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "poe-mezz-reset";
};
};
&i2c0 {
clock-frequency = <100000>;
status = "okay";
mux@71 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nxp,pca9544";
reg = <0x71>;
i2c-mux-idle-disconnect;
i2c@0 { /* POE devices MUX */
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
rng@3b {
compatible = "maxim,ds2476";
reg = <0x3b>;
};
hwmon@2e {
compatible = "adi,adt7476";
reg = <0x2e>;
};
hwmon@2d {
compatible = "adi,adt7476";
reg = <0x2d>;
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
rtc@68 {
compatible = "dallas,ds1340";
reg = <0x68>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
led_7seg_gpio: gpio@20 {
compatible = "nxp,pca9554";
gpio-controller;
#gpio-cells = <2>;
reg = <0x20>;
};
sfpgpio: gpio@27 { /* I2C to GPIO */
compatible = "nxp,pca9555";
gpio-controller;
#gpio-cells = <2>;
reg = <0x27>;
interrupt-parent = <&gpio0>;
interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
};
sfpmux: mux@77 { /* SFP I2C MUX */
#address-cells = <1>;
#size-cells = <0>;
compatible = "nxp,pca9544";
reg = <0x77>;
i2c-mux-idle-disconnect;
};
};
};
};
&spi1 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
m25p,fast-read;
partition@u-boot {
reg = <0x00000000 0x00100000>;
label = "u-boot";
};
partition@u-boot-env {
reg = <0x00100000 0x00040000>;
label = "u-boot-env";
};
partition@unused {
reg = <0x00140000 0x00e80000>;
label = "unused";
};
partition@idprom {
reg = <0x00fc0000 0x00040000>;
label = "idprom";
};
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&usb0 {
status = "okay";
};
&refclk {
clock-frequency = <25000000>;
};
&nand_controller { /* 256 MB */
status = "okay";
num-cs = <1>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
};

View File

@@ -0,0 +1,51 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "armada-385-atl-x530.dtsi"
#include "armada-385-atl-x530-u-boot.dtsi"
#include "armada-385-atl-x530DP.dtsi"
/ {
model = "Allied Telesis x530DP";
compatible = "alliedtelesis,x530DP", "alliedtelesis,x530", "marvell,armada385", "marvell,armada380";
nand-protect {
compatible = "atl,nand-protect";
protect-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
};
usb-enable {
compatible = "atl,usb-enable";
enable-gpio = <&gpio0 19 GPIO_ACTIVE_HIGH>;
};
boot-board {
compatible = "atl,boot-board";
present-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
override-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
};
phy-reset {
compatible = "atl,phy-reset";
reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>,
<&gpio1 21 GPIO_ACTIVE_HIGH>;
};
led-enable {
compatible = "atl,led-enable";
enable-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
};
led_7seg {
compatible = "atl,of-led-7seg";
segment-gpios = <
&led_7seg_gpio 0 0
&led_7seg_gpio 1 0
&led_7seg_gpio 2 0
&led_7seg_gpio 3 0
&led_7seg_gpio 4 0
&led_7seg_gpio 5 0
&led_7seg_gpio 6 0
&led_7seg_gpio 7 0>;
};
};

View File

@@ -0,0 +1,149 @@
// SPDX-License-Identifier: GPL-2.0
&i2c0 {
mux@71 {
compatible = "nxp,pca9548";
i2c@1 {
hwmon@2c {
compatible = "ti,lm87";
reg = <0x2c>;
};
hwmon@2d {
compatible = "ti,lm87";
reg = <0x2d>;
};
hwmon@2e {
pwm-polarity = <1>;
};
};
psu_a_adapter: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
psu_b_adapter: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
misc_gpio: gpio@26 {
compatible = "nxp,pca9555";
gpio-controller;
#gpio-cells = <2>;
reg = <0x26>;
interrupt-parent = <&gpio0>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
status = "okay";
interrupt-controller;
#interrupt-cells = <2>;
psu_bank2 {
gpio-hog;
gpios = <0 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "psu-bank2";
};
};
};
};
};
/ {
psu_slot_a {
compatible = "atl,dts-overlay-gpio-psu-slot";
slot-name = "PSU Bay A";
board-index = <1>;
present-gpio = <&misc_gpio 1 GPIO_ACTIVE_LOW>;
output-ok-gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>;
interrupt-parent = <&misc_gpio>;
interrupts = <1 IRQ_TYPE_EDGE_BOTH>;
overlay = <&psu_a_overlay>;
};
psu_slot_b {
compatible = "atl,dts-overlay-gpio-psu-slot";
slot-name = "PSU Bay B";
board-index = <2>;
present-gpio = <&misc_gpio 2 GPIO_ACTIVE_LOW>;
output-ok-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
interrupt-parent = <&misc_gpio>;
interrupts = <2 IRQ_TYPE_EDGE_BOTH>;
overlay = <&psu_b_overlay>;
};
fan_slot_a {
compatible = "atl,fan05-slot";
slot-name = "Fan Bay A";
board-index = <3>;
present-gpio = <&misc_gpio 3 GPIO_ACTIVE_LOW>;
fault-gpio = <&misc_gpio 11 GPIO_ACTIVE_LOW>;
interrupt-parent = <&misc_gpio>;
interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
overlay = <&fan_a_overlay>;
};
};
/ {
psu_a_overlay: psu_a {
fragment@0 {
target = <&psu_a_adapter>;
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
psu@51 {
compatible = "atl,atl-pwr-gen2";
reg = <0x51>;
board-index = <1>;
};
};
};
};
};
/ {
psu_b_overlay: psu_b {
fragment@0 {
target = <&psu_b_adapter>;
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
psu@51 {
compatible = "atl,atl-pwr-gen2";
reg = <0x51>;
board-index = <2>;
};
};
};
};
};
/ {
fan_a_overlay:fan_a {
fragment@1 {
target-path = "/";
__overlay__ {
fan@1 {
compatible = "atl,fan05";
board-index = <3>;
module-id-gpios =
<&misc_gpio 4 GPIO_ACTIVE_HIGH>,
<&misc_gpio 5 GPIO_ACTIVE_HIGH>,
<&misc_gpio 6 GPIO_ACTIVE_HIGH>;
};
};
};
};
};

View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 385 SoC.
*
@@ -6,44 +7,6 @@
* Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "armada-38x.dtsi"
@@ -70,13 +33,7 @@
};
soc {
internal-regs {
pinctrl@18000 {
compatible = "marvell,mv88f6820-pinctrl";
};
};
pcie-controller {
pciec: pcie {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
@@ -106,7 +63,7 @@
* configured in x4 by the bootloader, then
* pcie@4,0 is not available.
*/
pcie@1,0 {
pcie1: pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
@@ -115,6 +72,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <0>;
@@ -124,7 +82,7 @@
};
/* x1 port */
pcie@2,0 {
pcie2: pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
@@ -133,6 +91,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <1>;
@@ -142,7 +101,7 @@
};
/* x1 port */
pcie@3,0 {
pcie3: pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
@@ -151,6 +110,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <2>;
@@ -163,7 +123,7 @@
* x1 port only available when pcie@1,0 is
* configured as a x1 port
*/
pcie@4,0 {
pcie4: pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
@@ -172,6 +132,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <3>;
@@ -182,3 +143,7 @@
};
};
};
&pinctrl {
compatible = "marvell,mv88f6820-pinctrl";
};

View File

@@ -118,18 +118,7 @@
status = "okay";
};
spi1: spi@10680 {
/*
* CS0: W25Q32
* CS1:
* CS2: mikrobus
*/
pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>;
pinctrl-names = "default";
status = "okay";
};
usb0: usb3@f8000 {
usb3@f8000 {
/* CON7, USB-A port on back of device */
status = "okay";
};
@@ -322,6 +311,18 @@
};
};
&spi1 {
/*
* Add SPI CS pins for clearfog:
* CS0: W25Q32
* CS1:
* CS2: mikrobus
*/
pinctrl-0 = <&spi1_pins &mikro_spi_pins>;
pinctrl-names = "default";
status = "okay";
};
/*
+#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011
MPP18: gpio ? (pca9655 int?)

View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 388 SoC.
*
@@ -5,39 +6,6 @@
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*
* The main difference with the Armada 385 is that the 388 can handle two more
* SATA ports. So we can reuse the dtsi of the Armada 385, override the pinctrl
* property and the name of the SoC, and add the second SATA host which control
@@ -50,13 +18,8 @@
model = "Marvell Armada 388 family SoC";
compatible = "marvell,armada388", "marvell,armada385",
"marvell,armada380";
soc {
internal-regs {
pinctrl@18000 {
compatible = "marvell,mv88f6828-pinctrl";
};
sata@e0000 {
compatible = "marvell,armada-380-ahci";
reg = <0xe0000 0x2000>;
@@ -68,3 +31,7 @@
};
};
};
&pinctrl {
compatible = "marvell,mv88f6828-pinctrl";
};

View File

@@ -72,40 +72,6 @@
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
internal-regs {
spi0: spi@10600 {
status = "okay";
sc16is741: sc16is741@0 {
compatible = "nxp,sc16is741";
reg = <0>;
clocks = <&sc16isclk>;
spi-max-frequency = <4000000>;
interrupt-parent = <&gpio0>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
};
};
spi1: spi@10680 {
status = "okay";
u-boot,dm-pre-reloc;
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q016a", "spi-flash";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
spi-flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a11", "spi-flash";
reg = <1>; /* Chip select 1 */
spi-max-frequency = <108000000>;
u-boot,dm-pre-reloc;
};
};
I2C0: i2c@11000 {
status = "okay";
clock-frequency = <1000000>;
@@ -586,3 +552,37 @@
};
};
};
&spi0 {
status = "okay";
sc16is741: sc16is741@0 {
compatible = "nxp,sc16is741";
reg = <0>;
clocks = <&sc16isclk>;
spi-max-frequency = <4000000>;
interrupt-parent = <&gpio0>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
};
};
&spi1 {
status = "okay";
u-boot,dm-pre-reloc;
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q016a", "spi-flash";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
spi-flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a11", "spi-flash";
reg = <1>; /* Chip select 1 */
spi-max-frequency = <108000000>;
u-boot,dm-pre-reloc;
};
};

View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 38x family of SoCs.
*
@@ -6,44 +7,6 @@
* Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "skeleton.dtsi"
@@ -83,7 +46,7 @@
reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
};
devbus-bootcs {
devbus_bootcs: devbus-bootcs {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
@@ -93,7 +56,7 @@
status = "disabled";
};
devbus-cs0 {
devbus_cs0: devbus-cs0 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
@@ -103,7 +66,7 @@
status = "disabled";
};
devbus-cs1 {
devbus_cs1: devbus-cs1 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
@@ -113,7 +76,7 @@
status = "disabled";
};
devbus-cs2 {
devbus_cs2: devbus-cs2 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
@@ -123,7 +86,7 @@
status = "disabled";
};
devbus-cs3 {
devbus_cs3: devbus-cs3 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
@@ -145,6 +108,10 @@
reg = <0x8000 0x1000>;
cache-unified;
cache-level = <2>;
arm,double-linefill-incr = <0>;
arm,double-linefill-wrap = <0>;
arm,double-linefill = <0>;
prefetch-data = <1>;
};
scu@c000 {
@@ -152,6 +119,13 @@
reg = <0xc000 0x58>;
};
timer@c200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0xc200 0x20>;
interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
clocks = <&coreclk 2>;
};
timer@c600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xc600 0x20>;
@@ -168,32 +142,8 @@
<0xc100 0x100>;
};
spi0: spi@10600 {
compatible = "marvell,armada-380-spi",
"marvell,orion-spi";
reg = <0x10600 0x50>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coreclk 0>;
status = "disabled";
};
spi1: spi@10680 {
compatible = "marvell,armada-380-spi",
"marvell,orion-spi";
reg = <0x10680 0x50>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coreclk 0>;
status = "disabled";
};
i2c0: i2c@11000 {
compatible = "marvell,mv64xxx-i2c";
compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
reg = <0x11000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
@@ -204,7 +154,7 @@
};
i2c1: i2c@11100 {
compatible = "marvell,mv64xxx-i2c";
compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
reg = <0x11100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
@@ -258,19 +208,6 @@
marvell,function = "i2c0";
};
nand_pins: nand-pins {
marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33",
"mpp38", "mpp28", "mpp40", "mpp42",
"mpp35", "mpp36", "mpp25", "mpp30",
"mpp32";
marvell,function = "dev";
};
nand_rb: nand-rb {
marvell,pins = "mpp41";
marvell,function = "nand";
};
mdio_pins: mdio-pins {
marvell,pins = "mpp4", "mpp5";
marvell,function = "ge";
@@ -298,6 +235,20 @@
marvell,function = "spi1";
};
nand_pins: nand-pins {
marvell,pins = "mpp22", "mpp34", "mpp23",
"mpp33", "mpp38", "mpp28",
"mpp40", "mpp42", "mpp35",
"mpp36", "mpp25", "mpp30",
"mpp32";
marvell,function = "dev";
};
nand_rb: nand-rb {
marvell,pins = "mpp41";
marvell,function = "nand";
};
uart0_pins: uart-pins-0 {
marvell,pins = "mpp0", "mpp1";
marvell,function = "ua0";
@@ -338,34 +289,42 @@
};
gpio0: gpio@18100 {
compatible = "marvell,orion-gpio";
reg = <0x18100 0x40>;
compatible = "marvell,armada-370-gpio",
"marvell,orion-gpio";
reg = <0x18100 0x40>, <0x181c0 0x08>;
reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
#pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coreclk 0>;
};
gpio1: gpio@18140 {
compatible = "marvell,orion-gpio";
reg = <0x18140 0x40>;
compatible = "marvell,armada-370-gpio",
"marvell,orion-gpio";
reg = <0x18140 0x40>, <0x181c8 0x08>;
reg-names = "gpio", "pwm";
ngpios = <28>;
gpio-controller;
#gpio-cells = <2>;
#pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coreclk 0>;
};
system-controller@18200 {
systemc: system-controller@18200 {
compatible = "marvell,armada-380-system-controller",
"marvell,armada-370-xp-system-controller";
reg = <0x18200 0x100>;
@@ -386,7 +345,8 @@
mbusc: mbus-controller@20000 {
compatible = "marvell,mbus-controller";
reg = <0x20000 0x100>, <0x20180 0x20>;
reg = <0x20000 0x100>, <0x20180 0x20>,
<0x20250 0x8>;
};
mpic: interrupt-controller@20a00 {
@@ -399,7 +359,7 @@
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
timer@20300 {
timer: timer@20300 {
compatible = "marvell,armada-380-timer",
"marvell,armada-xp-timer";
reg = <0x20300 0x30>, <0x21040 0x30>;
@@ -413,14 +373,14 @@
clock-names = "nbclk", "fixed";
};
watchdog@20300 {
watchdog: watchdog@20300 {
compatible = "marvell,armada-380-wdt";
reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed";
};
cpurst@20800 {
cpurst: cpurst@20800 {
compatible = "marvell,armada-370-cpu-reset";
reg = <0x20800 0x10>;
};
@@ -430,16 +390,37 @@
reg = <0x20d20 0x6c>;
};
coherency-fabric@21010 {
coherencyfab: coherency-fabric@21010 {
compatible = "marvell,armada-380-coherency-fabric";
reg = <0x21010 0x1c>;
};
pmsu@22000 {
pmsu: pmsu@22000 {
compatible = "marvell,armada-380-pmsu";
reg = <0x22000 0x1000>;
};
/*
* As a special exception to the "order by
* register address" rule, the eth0 node is
* placed here to ensure that it gets
* registered as the first interface, since
* the network subsystem doesn't allow naming
* interfaces using DT aliases. Without this,
* the ordering of interfaces is different
* from the one used in U-Boot and the
* labeling of interfaces on the boards, which
* is very confusing for users.
*/
eth0: ethernet@70000 {
compatible = "marvell,armada-370-neta";
reg = <0x70000 0x4000>;
interrupts-extended = <&mpic 8>;
clocks = <&gateclk 4>;
tx-csum-limit = <9800>;
status = "disabled";
};
eth1: ethernet@30000 {
compatible = "marvell,armada-370-neta";
reg = <0x30000 0x4000>;
@@ -456,7 +437,7 @@
status = "disabled";
};
usb@58000 {
usb0: usb@58000 {
compatible = "marvell,orion-ehci";
reg = <0x58000 0x500>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
@@ -464,8 +445,8 @@
status = "disabled";
};
xor@60800 {
compatible = "marvell,orion-xor";
xor0: xor@60800 {
compatible = "marvell,armada-380-xor", "marvell,orion-xor";
reg = <0x60800 0x100
0x60a00 0x100>;
clocks = <&gateclk 22>;
@@ -484,8 +465,8 @@
};
};
xor@60900 {
compatible = "marvell,orion-xor";
xor1: xor@60900 {
compatible = "marvell,armada-380-xor", "marvell,orion-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
clocks = <&gateclk 28>;
@@ -504,14 +485,6 @@
};
};
eth0: ethernet@70000 {
compatible = "marvell,armada-370-neta";
reg = <0x70000 0x4000>;
interrupts-extended = <&mpic 8>;
clocks = <&gateclk 4>;
status = "disabled";
};
mdio: mdio@72004 {
#address-cells = <1>;
#size-cells = <0>;
@@ -520,14 +493,29 @@
clocks = <&gateclk 4>;
};
rtc@a3800 {
cesa: crypto@90000 {
compatible = "marvell,armada-38x-crypto";
reg = <0x90000 0x10000>;
reg-names = "regs";
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 23>, <&gateclk 21>,
<&gateclk 14>, <&gateclk 16>;
clock-names = "cesa0", "cesa1",
"cesaz0", "cesaz1";
marvell,crypto-srams = <&crypto_sram0>,
<&crypto_sram1>;
marvell,crypto-sram-size = <0x800>;
};
rtc: rtc@a3800 {
compatible = "marvell,armada-380-rtc";
reg = <0xa3800 0x20>, <0x184a0 0x0c>;
reg-names = "rtc", "rtc-soc";
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
};
sata@a8000 {
ahci0: sata@a8000 {
compatible = "marvell,armada-380-ahci";
reg = <0xa8000 0x2000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
@@ -535,7 +523,15 @@
status = "disabled";
};
sata@e0000 {
bm: bm@c8000 {
compatible = "marvell,armada-380-neta-bm";
reg = <0xc8000 0xac>;
clocks = <&gateclk 13>;
internal-mem = <&bm_bppi>;
status = "disabled";
};
ahci1: sata@e0000 {
compatible = "marvell,armada-380-ahci";
reg = <0xe0000 0x2000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
@@ -551,23 +547,23 @@
clock-output-names = "nand";
};
thermal@e8078 {
thermal: thermal@e8078 {
compatible = "marvell,armada380-thermal";
reg = <0xe4078 0x4>, <0xe4074 0x4>;
reg = <0xe4078 0x4>, <0xe4070 0x8>;
status = "okay";
};
flash@d0000 {
nand_controller: nand-controller@d0000 {
compatible = "marvell,armada370-nand","marvell,mvebu-pxa3xx-nand";
reg = <0xd0000 0x54>;
#address-cells = <1>;
#size-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coredivclk 0>;
status = "disabled";
};
sdhci@d8000 {
sdhci: sdhci@d8000 {
compatible = "marvell,armada-380-sdhci";
reg-names = "sdhci", "mbus", "conf-sdio3";
reg = <0xd8000 0x1000>,
@@ -579,7 +575,7 @@
status = "disabled";
};
usb3@f0000 {
usb3_0: usb3@f0000 {
compatible = "marvell,armada-380-xhci";
reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
@@ -587,7 +583,7 @@
status = "disabled";
};
usb3@f8000 {
usb3_1: usb3@f8000 {
compatible = "marvell,armada-380-xhci";
reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
@@ -595,10 +591,63 @@
status = "disabled";
};
};
crypto_sram0: sa-sram0 {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x19) 0 0x800>;
clocks = <&gateclk 23>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>;
};
crypto_sram1: sa-sram1 {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x15) 0 0x800>;
clocks = <&gateclk 21>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
};
bm_bppi: bm-bppi {
compatible = "mmio-sram";
reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&gateclk 13>;
no-memory-wc;
status = "disabled";
};
spi0: spi@10600 {
compatible = "marvell,armada-380-spi",
"marvell,orion-spi";
reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coreclk 0>;
status = "disabled";
};
spi1: spi@10680 {
compatible = "marvell,armada-380-spi",
"marvell,orion-spi";
reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coreclk 0>;
status = "disabled";
};
};
clocks {
/* 2 GHz fixed main PLL */
/* 1 GHz fixed main PLL */
mainpll: mainpll {
compatible = "fixed-clock";
#clock-cells = <0>;

View File

@@ -99,6 +99,11 @@
0 0 0 0 0 0 0xe 0xe 0xe 0xe
0xe 0xe 0 >;
cpm_pcie_reset_pins: cpm-pcie-reset-pins {
marvell,pins = < 32 >;
marvell,function = <0>;
};
cpm_xhci_vbus_pins: cpm-xhci-vbus-pins {
marvell,pins = < 47 >;
marvell,function = <0>;
@@ -120,6 +125,9 @@
&cpm_pcie0 {
num-lanes = <1>;
pinctrl-names = "default";
pinctrl-0 = <&cpm_pcie_reset_pins>;
marvell,reset-gpio = <&cpm_gpio1 0 GPIO_ACTIVE_LOW>;
status = "okay";
};

View File

@@ -132,7 +132,7 @@
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&cpm_pcie_reset_pins>;
marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_HIGH>; /* GPIO[52] */
marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */
status = "okay";
};

View File

@@ -64,6 +64,17 @@
method = "smc";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
psci-area@4000000 {
reg = <0x0 0x4000000 0x0 0x200000>;
no-map;
};
};
ap806 {
#address-cells = <2>;
#size-cells = <2>;

View File

@@ -86,7 +86,7 @@
* configured as x4 or quad x1 lanes. One unit is
* x1 only.
*/
pcie-controller {
pciec: pcie@82000000 {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
@@ -114,7 +114,7 @@
0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
pcie@1,0 {
pcie1: pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
@@ -123,6 +123,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
@@ -131,7 +132,7 @@
status = "disabled";
};
pcie@2,0 {
pcie2: pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
@@ -140,6 +141,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>;
@@ -148,7 +150,7 @@
status = "disabled";
};
pcie@3,0 {
pcie3: pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
@@ -157,6 +159,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
marvell,pcie-port = <0>;
@@ -165,7 +168,7 @@
status = "disabled";
};
pcie@4,0 {
pcie4: pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
@@ -174,6 +177,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
marvell,pcie-port = <0>;
@@ -182,7 +186,7 @@
status = "disabled";
};
pcie@5,0 {
pcie5: pcie@5,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
reg = <0x2800 0 0 0 0>;
@@ -191,6 +195,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
0x81000000 0 0 0x81000000 0x5 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 62>;
marvell,pcie-port = <1>;

View File

@@ -87,7 +87,7 @@
* configured as x4 or quad x1 lanes. One unit is
* x4 only.
*/
pcie-controller {
pciec: pcie@82000000 {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
@@ -129,7 +129,7 @@
0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
pcie@1,0 {
pcie1: pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
@@ -138,6 +138,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
@@ -146,7 +147,7 @@
status = "disabled";
};
pcie@2,0 {
pcie2: pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
@@ -155,6 +156,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>;
@@ -163,7 +165,7 @@
status = "disabled";
};
pcie@3,0 {
pcie3: pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
@@ -172,6 +174,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
marvell,pcie-port = <0>;
@@ -180,7 +183,7 @@
status = "disabled";
};
pcie@4,0 {
pcie4: pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
@@ -189,6 +192,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
marvell,pcie-port = <0>;
@@ -197,7 +201,7 @@
status = "disabled";
};
pcie@5,0 {
pcie5: pcie@5,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
reg = <0x2800 0 0 0 0>;
@@ -206,6 +210,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
0x81000000 0 0 0x81000000 0x5 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 62>;
marvell,pcie-port = <1>;
@@ -214,7 +219,7 @@
status = "disabled";
};
pcie@6,0 {
pcie6: pcie@6,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
reg = <0x3000 0 0 0 0>;
@@ -223,6 +228,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
0x81000000 0 0 0x81000000 0x6 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 63>;
marvell,pcie-port = <1>;
@@ -231,7 +237,7 @@
status = "disabled";
};
pcie@7,0 {
pcie7: pcie@7,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
reg = <0x3800 0 0 0 0>;
@@ -240,6 +246,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
0x81000000 0 0 0x81000000 0x7 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 64>;
marvell,pcie-port = <1>;
@@ -248,7 +255,7 @@
status = "disabled";
};
pcie@8,0 {
pcie8: pcie@8,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
reg = <0x4000 0 0 0 0>;
@@ -257,6 +264,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
0x81000000 0 0 0x81000000 0x8 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 65>;
marvell,pcie-port = <1>;
@@ -265,7 +273,7 @@
status = "disabled";
};
pcie@9,0 {
pcie9: pcie@9,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
reg = <0x4800 0 0 0 0>;
@@ -274,6 +282,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
0x81000000 0 0 0x81000000 0x9 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>;
marvell,pcie-port = <2>;

View File

@@ -104,7 +104,7 @@
* configured as x4 or quad x1 lanes. Two units are
* x4/x1.
*/
pcie-controller {
pciec: pcie@82000000 {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
@@ -150,7 +150,7 @@
0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
pcie@1,0 {
pcie1: pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
@@ -159,6 +159,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
@@ -167,7 +168,7 @@
status = "disabled";
};
pcie@2,0 {
pcie2: pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
@@ -176,6 +177,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>;
@@ -184,7 +186,7 @@
status = "disabled";
};
pcie@3,0 {
pcie3: pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
@@ -193,6 +195,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
marvell,pcie-port = <0>;
@@ -201,7 +204,7 @@
status = "disabled";
};
pcie@4,0 {
pcie4: pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
@@ -210,6 +213,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
marvell,pcie-port = <0>;
@@ -218,7 +222,7 @@
status = "disabled";
};
pcie@5,0 {
pcie5: pcie@5,0 {
device_type = "pci";
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
reg = <0x2800 0 0 0 0>;
@@ -227,6 +231,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
0x81000000 0 0 0x81000000 0x5 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 62>;
marvell,pcie-port = <1>;
@@ -235,7 +240,7 @@
status = "disabled";
};
pcie@6,0 {
pcie6: pcie@6,0 {
device_type = "pci";
assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
reg = <0x3000 0 0 0 0>;
@@ -244,6 +249,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
0x81000000 0 0 0x81000000 0x6 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 63>;
marvell,pcie-port = <1>;
@@ -252,7 +258,7 @@
status = "disabled";
};
pcie@7,0 {
pcie7: pcie@7,0 {
device_type = "pci";
assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
reg = <0x3800 0 0 0 0>;
@@ -261,6 +267,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
0x81000000 0 0 0x81000000 0x7 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 64>;
marvell,pcie-port = <1>;
@@ -269,7 +276,7 @@
status = "disabled";
};
pcie@8,0 {
pcie8: pcie@8,0 {
device_type = "pci";
assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
reg = <0x4000 0 0 0 0>;
@@ -278,6 +285,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
0x81000000 0 0 0x81000000 0x8 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 65>;
marvell,pcie-port = <1>;
@@ -286,7 +294,7 @@
status = "disabled";
};
pcie@9,0 {
pcie9: pcie@9,0 {
device_type = "pci";
assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
reg = <0x4800 0 0 0 0>;
@@ -295,6 +303,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
0x81000000 0 0 0x81000000 0x9 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>;
marvell,pcie-port = <2>;
@@ -303,7 +312,7 @@
status = "disabled";
};
pcie@10,0 {
pcie10: pcie@a,0 {
device_type = "pci";
assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
reg = <0x5000 0 0 0 0>;
@@ -312,6 +321,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
0x81000000 0 0 0x81000000 0xa 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 103>;
marvell,pcie-port = <3>;

View File

@@ -159,6 +159,45 @@
spi-max-frequency = <27777777>;
};
};
/* The LCD controller is only used on this board */
lcd0: lcd-controller@e0000 {
compatible = "marvell,armada-xp-lcd";
reg = <0xe0000 0x10000>;
status = "okay";
u-boot,dm-pre-reloc;
display-timings {
native-mode = <&timing0>;
timing0: panel0 {
hactive = <240>;
vactive = <320>;
hfront-porch = <1>;
hback-porch = <45>;
vfront-porch = <1>;
vback-porch = <3>;
/* Some dummy parameters */
clock-frequency = <0>;
hsync-len = <0>;
vsync-len = <0>;
};
};
};
};
};
};
&pciec {
status = "okay";
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@9,0 {
/* Port 2, Lane 0 */
status = "okay";
};
};

102
arch/arm/dts/bcm63158.dtsi Normal file
View File

@@ -0,0 +1,102 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
*/
#include "skeleton64.dtsi"
/ {
compatible = "brcm,bcm63158";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
u-boot,dm-pre-reloc;
cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x0>;
next-level-cache = <&l2>;
u-boot,dm-pre-reloc;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x1>;
next-level-cache = <&l2>;
u-boot,dm-pre-reloc;
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x2>;
next-level-cache = <&l2>;
u-boot,dm-pre-reloc;
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x3>;
next-level-cache = <&l2>;
u-boot,dm-pre-reloc;
};
l2: l2-cache0 {
compatible = "cache";
u-boot,dm-pre-reloc;
};
};
clocks {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
u-boot,dm-pre-reloc;
periph_osc: periph-osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0xbebc200>;
u-boot,dm-pre-reloc;
};
};
ubus {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
uart0: serial@ff812000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xff812000 0x0 0x1000>;
clock = <50000000>;
status = "disabled";
};
wdt1: watchdog@ff800480 {
compatible = "brcm,bcm6345-wdt";
reg = <0x0 0xff800480 0x0 0x14>;
clocks = <&periph_osc>;
};
wdt2: watchdog@ff8004c0 {
compatible = "brcm,bcm6345-wdt";
reg = <0x0 0xff8004c0 0x0 0x14>;
clocks = <&periph_osc>;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdt1>;
};
};
};

View File

@@ -81,5 +81,22 @@
status = "disabled";
};
wdt1: watchdog@ff802780 {
compatible = "brcm,bcm6345-wdt";
reg = <0x0 0xff802780 0x0 0x14>;
clocks = <&periph_osc>;
};
wdt2: watchdog@ff8027c0 {
compatible = "brcm,bcm6345-wdt";
reg = <0x0 0xff8027c0 0x0 0x14>;
clocks = <&periph_osc>;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdt1>;
};
};
};

View File

@@ -0,0 +1,31 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
*/
/dts-v1/;
#include "bcm63158.dtsi"
/ {
model = "Broadcom bcm963158";
compatible = "broadcom,bcm963158", "brcm,bcm63158";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
};
&uart0 {
u-boot,dm-pre-reloc;
status = "okay";
};

View File

@@ -94,6 +94,28 @@
regulator-boot-on;
};
baseboard_3v3: fixedregulator-3v3 {
/* TPS73701DCQ */
compatible = "regulator-fixed";
regulator-name = "baseboard_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vbat>;
regulator-always-on;
regulator-boot-on;
};
baseboard_1v8: fixedregulator-1v8 {
/* TPS73701DCQ */
compatible = "regulator-fixed";
regulator-name = "baseboard_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vbat>;
regulator-always-on;
regulator-boot-on;
};
backlight_lcd: backlight-regulator {
compatible = "regulator-fixed";
regulator-name = "lcd_backlight_pwr";
@@ -105,7 +127,7 @@
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "DA850/OMAP-L138 EVM";
simple-audio-card,name = "DA850-OMAPL138 EVM";
simple-audio-card,widgets =
"Line", "Line In",
"Line", "Line Out";
@@ -210,10 +232,9 @@
/* Regulators */
IOVDD-supply = <&vdcdc2_reg>;
/* Derived from VBAT: Baseboard 3.3V / 1.8V */
AVDD-supply = <&vbat>;
DRVDD-supply = <&vbat>;
DVDD-supply = <&vbat>;
AVDD-supply = <&baseboard_3v3>;
DRVDD-supply = <&baseboard_3v3>;
DVDD-supply = <&baseboard_1v8>;
};
tca6416: gpio@20 {
compatible = "ti,tca6416";

View File

@@ -28,8 +28,8 @@
serial@78b0000 {
u-boot,dm-pre-reloc;
};
};
};
};

View File

@@ -13,14 +13,22 @@
soc {
u-boot,dm-pre-reloc;
qcom,tlmm@1010000 {
u-boot,dm-pre-reloc;
uart {
u-boot,dm-pre-reloc;
};
};
clock-controller@300000 {
u-boot,dm-pre-reloc;
};
serial@75b0000 {
u-boot,dm-pre-reloc;
};
};
};
};
&pm8994_pon {

View File

@@ -8,6 +8,7 @@
/dts-v1/;
#include "skeleton64.dtsi"
#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
/ {
model = "Qualcomm Technologies, Inc. DB820c";
@@ -16,7 +17,7 @@
#size-cells = <2>;
aliases {
serial0 = &blsp2_uart1;
serial0 = &blsp2_uart2;
};
chosen {
@@ -63,18 +64,32 @@
reg = <0x300000 0x90000>;
};
blsp2_uart1: serial@75b0000 {
pinctrl: qcom,tlmm@1010000 {
compatible = "qcom,tlmm-apq8096";
reg = <0x1010000 0x400000>;
blsp8_uart: uart {
function = "blsp_uart8";
pins = "GPIO_4", "GPIO_5";
drive-strength = <DRIVE_STRENGTH_8MA>;
bias-disable;
};
};
blsp2_uart2: serial@75b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x75b0000 0x1000>;
clock = <&gcc 4>;
pinctrl-names = "uart";
pinctrl-0 = <&blsp8_uart>;
};
sdhc2: sdhci@74a4900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
index = <0x0>;
bus-width = <4>;
clock = <&gcc 0>;
compatible = "qcom,sdhci-msm-v4";
reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
index = <0x0>;
bus-width = <4>;
clock = <&gcc 0>;
clock-frequency = <200000000>;
};

View File

@@ -40,9 +40,46 @@
reg = <0x40000000 0x80000000>;
};
iram {
reg = <0x02020000 0x60000>;
};
config {
samsung,bl1-offset = <0x1400>;
samsung,bl2-offset = <0x3400>;
u-boot-memory = "/memory";
u-boot-offset = <0x3e00000 0x100000>;
};
flash@0 {
spl { /* spl size override */
size = <0x8000>;
reg = <0 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
pre-boot {
label = "bl1 pre-boot";
reg = <0 0x2000>;
read-only;
filename = "e5250.nbl1.bin";
type = "blob exynos-bl1";
required;
};
spl {
label = "bl2 spl";
reg = <0x2000 0x8000>;
read-only;
filename = "bl2.bin";
type = "blob exynos-bl2 boot,dtb";
payload = "/flash/ro-boot";
required;
};
ro-boot {
label = "u-boot";
reg = <0xa000 0xb0000>;
read-only;
type = "blob boot,dtb";
required;
};
};
@@ -93,6 +130,22 @@
samsung,vbus-gpio = <&gpx2 7 GPIO_ACTIVE_HIGH>;
};
sound {
compatible = "google,spring-audio-max98088";
samsung,model = "Spring-I2S-MAX98088";
samsung,audio-codec = <&max98088>;
codec-enable-gpio = <&gpx1 7 0>;
cpu {
sound-dai = <&i2s1 0>;
};
codec {
sound-dai = <&max98088 0>;
};
};
spi@12d30000 {
spi-max-frequency = <50000000>;
firmware_storage_spi: flash@0 {
@@ -638,27 +691,11 @@
};
};
max98095: soundcodec@10 {
max98088: soundcodec@10 {
reg = <0x10>;
compatible = "maxim,max98095";
compatible = "maxim,max98088";
#sound-dai-cells = <1>;
};
sound {
compatible = "google,spring-audio-max98095";
samsung,model = "Spring-I2S-MAX98095";
samsung,audio-codec = <&max98095>;
cpu {
sound-dai = <&i2s0 0>;
};
codec {
sound-dai = <&max98095 0>;
};
};
};
#include "cros-ec-keyboard.dtsi"

View File

@@ -0,0 +1,112 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
&mu {
u-boot,dm-spl;
};
&clk {
u-boot,dm-spl;
};
&iomuxc {
u-boot,dm-spl;
};
&pd_lsio {
u-boot,dm-spl;
};
&pd_lsio_gpio0 {
u-boot,dm-spl;
};
&pd_lsio_gpio1 {
u-boot,dm-spl;
};
&pd_lsio_gpio2 {
u-boot,dm-spl;
};
&pd_lsio_gpio3 {
u-boot,dm-spl;
};
&pd_lsio_gpio4 {
u-boot,dm-spl;
};
&pd_lsio_gpio5 {
u-boot,dm-spl;
};
&pd_lsio_gpio6 {
u-boot,dm-spl;
};
&pd_lsio_gpio7 {
u-boot,dm-spl;
};
&pd_conn {
u-boot,dm-spl;
};
&pd_conn_sdch0 {
u-boot,dm-spl;
};
&pd_conn_sdch1 {
u-boot,dm-spl;
};
&pd_conn_sdch2 {
u-boot,dm-spl;
};
&gpio0 {
u-boot,dm-spl;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&gpio5 {
u-boot,dm-spl;
};
&gpio6 {
u-boot,dm-spl;
};
&gpio7 {
u-boot,dm-spl;
};
&lpuart0 {
u-boot,dm-spl;
};
&usdhc1 {
u-boot,dm-spl;
};
&usdhc2 {
u-boot,dm-spl;
};

View File

@@ -6,6 +6,7 @@
/dts-v1/;
#include "fsl-imx8qxp.dtsi"
#include "fsl-imx8qxp-mek-u-boot.dtsi"
/ {
model = "Freescale i.MX8QXP MEK";

View File

@@ -56,3 +56,7 @@
reg = <1>;
};
};
&sata {
status = "okay";
};

View File

@@ -1,14 +1,17 @@
// SPDX-License-Identifier: GPL-2.0
/*
* DTS File for HiSilicon Poplar Development Board
*
* Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
*
* Released under the GPLv2 only.
* SPDX-License-Identifier: GPL-2.0
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "hi3798cv200.dtsi"
#include "poplar-pinctrl.dtsi"
/ {
model = "HiSilicon Poplar Development Board";
@@ -28,6 +31,13 @@
reg = <0x0 0x0 0x0 0x80000000>;
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
leds {
compatible = "gpio-leds";
@@ -59,6 +69,33 @@
default-state = "off";
};
};
reg_pcie: regulator-pcie {
compatible = "regulator-fixed";
regulator-name = "3V3_PCIE0";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio6 7 0>;
enable-active-high;
};
};
&ehci {
status = "okay";
};
&emmc {
pinctrl-names = "default";
pinctrl-0 = <&emmc_pins_1 &emmc_pins_2
&emmc_pins_3 &emmc_pins_4>;
fifo-depth = <256>;
clock-frequency = <200000000>;
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
non-removable;
bus-width = <8>;
status = "okay";
};
&gmac1 {
@@ -76,17 +113,17 @@
&gpio1 {
status = "okay";
gpio-line-names = "LS-GPIO-E", "",
gpio-line-names = "GPIO-E", "",
"", "",
"", "LS-GPIO-F",
"", "LS-GPIO-J";
"", "GPIO-F",
"", "GPIO-J";
};
&gpio2 {
status = "okay";
gpio-line-names = "LS-GPIO-H", "LS-GPIO-I",
"LS-GPIO-L", "LS-GPIO-G",
"LS-GPIO-K", "",
gpio-line-names = "GPIO-H", "GPIO-I",
"GPIO-L", "GPIO-G",
"GPIO-K", "",
"", "";
};
@@ -94,15 +131,15 @@
status = "okay";
gpio-line-names = "", "",
"", "",
"LS-GPIO-C", "",
"", "LS-GPIO-B";
"GPIO-C", "",
"", "GPIO-B";
};
&gpio4 {
status = "okay";
gpio-line-names = "", "",
"", "",
"", "LS-GPIO-D",
"", "GPIO-D",
"", "";
};
@@ -110,7 +147,7 @@
status = "okay";
gpio-line-names = "", "USER-LED-1",
"USER-LED-2", "",
"", "LS-GPIO-A",
"", "GPIO-A",
"", "";
};
@@ -144,6 +181,22 @@
status = "okay";
};
&ohci {
status = "okay";
};
&pcie {
reset-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
vpcie-supply = <&reg_pcie>;
status = "okay";
};
&sd0 {
bus-width = <4>;
cap-sd-highspeed;
status = "okay";
};
&spi0 {
status = "okay";
label = "LS-SPI0";

View File

@@ -1,12 +1,16 @@
// SPDX-License-Identifier: GPL-2.0
/*
* DTS File for HiSilicon Hi3798cv200 SoC.
*
* Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
*
* Released under the GPLv2 only.
* SPDX-License-Identifier: GPL-2.0
*/
#include <dt-bindings/clock/histb-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/reset/ti-syscon.h>
/ {
@@ -104,6 +108,113 @@
#reset-cells = <2>;
};
perictrl: peripheral-controller@8a20000 {
compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
"simple-mfd";
reg = <0x8a20000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x8a20000 0x1000>;
usb2_phy1: usb2-phy@120 {
compatible = "hisilicon,hi3798cv200-usb2-phy";
reg = <0x120 0x4>;
clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
resets = <&crg 0xbc 4>;
#address-cells = <1>;
#size-cells = <0>;
usb2_phy1_port0: phy@0 {
reg = <0>;
#phy-cells = <0>;
resets = <&crg 0xbc 8>;
};
usb2_phy1_port1: phy@1 {
reg = <1>;
#phy-cells = <0>;
resets = <&crg 0xbc 9>;
};
};
usb2_phy2: usb2-phy@124 {
compatible = "hisilicon,hi3798cv200-usb2-phy";
reg = <0x124 0x4>;
clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
resets = <&crg 0xbc 6>;
#address-cells = <1>;
#size-cells = <0>;
usb2_phy2_port0: phy@0 {
reg = <0>;
#phy-cells = <0>;
resets = <&crg 0xbc 10>;
};
};
combphy0: phy@850 {
compatible = "hisilicon,hi3798cv200-combphy";
reg = <0x850 0x8>;
#phy-cells = <1>;
clocks = <&crg HISTB_COMBPHY0_CLK>;
resets = <&crg 0x188 4>;
assigned-clocks = <&crg HISTB_COMBPHY0_CLK>;
assigned-clock-rates = <100000000>;
hisilicon,fixed-mode = <PHY_TYPE_USB3>;
};
combphy1: phy@858 {
compatible = "hisilicon,hi3798cv200-combphy";
reg = <0x858 0x8>;
#phy-cells = <1>;
clocks = <&crg HISTB_COMBPHY1_CLK>;
resets = <&crg 0x188 12>;
assigned-clocks = <&crg HISTB_COMBPHY1_CLK>;
assigned-clock-rates = <100000000>;
hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
};
};
pmx0: pinconf@8a21000 {
compatible = "pinconf-single";
reg = <0x8a21000 0x180>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <7>;
pinctrl-single,gpio-range = <
&range 0 8 2 /* GPIO 0 */
&range 8 1 0 /* GPIO 1 */
&range 9 4 2
&range 13 1 0
&range 14 1 1
&range 15 1 0
&range 16 5 0 /* GPIO 2 */
&range 21 3 1
&range 24 4 1 /* GPIO 3 */
&range 28 2 2
&range 86 1 1
&range 87 1 0
&range 30 4 2 /* GPIO 4 */
&range 34 3 0
&range 37 1 2
&range 38 3 2 /* GPIO 6 */
&range 41 5 0
&range 46 8 1 /* GPIO 7 */
&range 54 8 1 /* GPIO 8 */
&range 64 7 1 /* GPIO 9 */
&range 71 1 0
&range 72 6 1 /* GPIO 10 */
&range 78 1 0
&range 79 1 1
&range 80 6 1 /* GPIO 11 */
&range 70 2 1
&range 88 8 0 /* GPIO 12 */
>;
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
};
uart0: serial@8b00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x8b00000 0x1000>;
@@ -190,13 +301,30 @@
status = "disabled";
};
emmc: mmc@9830000 {
sd0: mmc@9820000 {
compatible = "snps,dw-mshc";
reg = <0x9820000 0x10000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_SDIO0_CIU_CLK>,
<&crg HISTB_SDIO0_BIU_CLK>;
clock-names = "ciu", "biu";
resets = <&crg 0x9c 4>;
reset-names = "reset";
status = "disabled";
};
emmc: mmc@9830000 {
compatible = "hisilicon,hi3798cv200-dw-mshc";
reg = <0x9830000 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_MMC_CIU_CLK>,
<&crg HISTB_MMC_BIU_CLK>;
clock-names = "ciu", "biu";
<&crg HISTB_MMC_BIU_CLK>,
<&crg HISTB_MMC_SAMPLE_CLK>,
<&crg HISTB_MMC_DRV_CLK>;
clock-names = "ciu", "biu", "ciu-sample", "ciu-drive";
resets = <&crg 0xa0 4>;
reset-names = "reset";
status = "disabled";
};
gpio0: gpio@8b20000 {
@@ -207,6 +335,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&pmx0 0 0 8>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
@@ -220,6 +349,13 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <
&pmx0 0 8 1
&pmx0 1 9 4
&pmx0 5 13 1
&pmx0 6 14 1
&pmx0 7 15 1
>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
@@ -233,6 +369,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&pmx0 0 16 5 &pmx0 5 21 3>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
@@ -246,6 +383,12 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <
&pmx0 0 24 4
&pmx0 4 28 2
&pmx0 6 86 1
&pmx0 7 87 1
>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
@@ -259,6 +402,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&pmx0 0 30 4 &pmx0 4 34 3 &pmx0 7 37 1>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
@@ -285,6 +429,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&pmx0 0 38 3 &pmx0 0 41 5>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
@@ -298,6 +443,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&pmx0 0 46 8>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
@@ -311,6 +457,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&pmx0 0 54 8>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
@@ -324,6 +471,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&pmx0 0 64 7 &pmx0 71 1>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
@@ -337,6 +485,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&pmx0 0 72 6 &pmx0 6 78 1 &pmx0 7 79 1>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
@@ -350,6 +499,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&pmx0 0 80 6 &pmx0 6 70 2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
@@ -363,6 +513,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&pmx0 0 88 8>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
@@ -405,5 +556,67 @@
clocks = <&sysctrl HISTB_IR_CLK>;
status = "disabled";
};
pcie: pcie@9860000 {
compatible = "hisilicon,hi3798cv200-pcie";
reg = <0x9860000 0x1000>,
<0x0 0x2000>,
<0x2000000 0x01000000>;
reg-names = "control", "rc-dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0 15>;
num-lanes = <1>;
ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000
0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_PCIE_AUX_CLK>,
<&crg HISTB_PCIE_PIPE_CLK>,
<&crg HISTB_PCIE_SYS_CLK>,
<&crg HISTB_PCIE_BUS_CLK>;
clock-names = "aux", "pipe", "sys", "bus";
resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
reset-names = "soft", "sys", "bus";
phys = <&combphy1 PHY_TYPE_PCIE>;
phy-names = "phy";
status = "disabled";
};
ohci: ohci@9880000 {
compatible = "generic-ohci";
reg = <0x9880000 0x10000>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_USB2_BUS_CLK>,
<&crg HISTB_USB2_12M_CLK>,
<&crg HISTB_USB2_48M_CLK>;
clock-names = "bus", "clk12", "clk48";
resets = <&crg 0xb8 12>;
reset-names = "bus";
phys = <&usb2_phy1_port0>;
phy-names = "usb";
status = "disabled";
};
ehci: ehci@9890000 {
compatible = "generic-ehci";
reg = <0x9890000 0x10000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_USB2_BUS_CLK>,
<&crg HISTB_USB2_PHY_CLK>,
<&crg HISTB_USB2_UTMI_CLK>;
clock-names = "bus", "phy", "utmi";
resets = <&crg 0xb8 12>,
<&crg 0xb8 16>,
<&crg 0xb8 13>;
reset-names = "bus", "phy", "utmi";
phys = <&usb2_phy1_port0>;
phy-names = "usb";
status = "disabled";
};
};
};

View File

@@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* U-Boot additions
*
* Copyright (c) 2018 Linaro Ltd.
*/
&mmc0 {
u-boot,dm-pre-reloc;
};
&mmc1 {
u-boot,dm-pre-reloc;
};

View File

@@ -40,6 +40,17 @@
};
};
&mmc0 {
status = "okay";
non-removable;
bus-width = <8>;
};
&mmc1 {
status = "okay";
bus-width = <4>;
};
&uart2 {
label = "LS-UART0";
};

View File

@@ -162,6 +162,24 @@
#clock-cells = <1>;
};
mmc0: dwmmc@f723d000 {
compatible = "hisilicon,hi6220-dw-mshc";
reg = <0x0 0xf723d000 0x0 0x1000>;
interrupts = <0x0 0x48 0x4>;
clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
clock-names = "ciu", "biu";
status = "disabled";
};
mmc1: dwmmc@f723e000 {
compatible = "hisilicon,hi6220-dw-mshc";
reg = <0x0 0xf723e000 0x0 0x1000>;
interrupts = <0x0 0x49 0x4>;
clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
clock-names = "ciu", "biu";
status = "disabled";
};
uart0: uart@f8015000 { /* console */
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xf8015000 0x0 0x1000>;

View File

@@ -99,20 +99,6 @@
MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
MX53_PAD_FEC_MDC__FEC_MDC 0x4
MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
@@ -162,6 +148,28 @@
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
>;
};
pinctrl_esdhc2: esdhc2grp {
fsl,pins = <
MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX53_PAD_EIM_D26__UART2_RXD_MUX 0x1e4
@@ -181,6 +189,22 @@
status = "okay";
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
bus-width = <4>;
status = "okay";
};
&esdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc2>;
cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
bus-width = <4>;
status = "okay";
};
&fec {
pinctrl-names = "default";
phy-mode = "rmii";

View File

@@ -31,6 +31,8 @@
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
mmc0 = &esdhc1;
mmc1 = &esdhc2;
};
tzic: tz-interrupt-controller@fffc000 {
@@ -54,6 +56,38 @@
reg = <0x50000000 0x10000000>;
ranges;
spba@50000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x50000000 0x40000>;
ranges;
esdhc1: esdhc@50004000 {
compatible = "fsl,imx53-esdhc";
reg = <0x50004000 0x4000>;
interrupts = <1>;
clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC1_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
esdhc2: esdhc@50008000 {
compatible = "fsl,imx53-esdhc";
reg = <0x50008000 0x4000>;
interrupts = <2>;
clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC2_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
};
iomuxc: iomuxc@53fa8000 {
compatible = "fsl,imx53-iomuxc";
reg = <0x53fa8000 0x4000>;

View File

@@ -0,0 +1,596 @@
/*
* Copyright 2018 Logic PD, Inc.
* Based on SabreSD, Copyright 2016 Freescale Semiconductor, Inc.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/ {
keyboard {
compatible = "gpio-keys";
btn0 {
gpios = <&pcf8575 0 GPIO_ACTIVE_LOW>;
label = "btn0";
linux,code = <KEY_WAKEUP>;
debounce-interval = <10>;
wakeup-source;
};
btn1 {
gpios = <&pcf8575 1 GPIO_ACTIVE_LOW>;
label = "btn1";
linux,code = <KEY_WAKEUP>;
debounce-interval = <10>;
wakeup-source;
};
btn2 {
gpios = <&pcf8575 2 GPIO_ACTIVE_LOW>;
label = "btn2";
linux,code = <KEY_WAKEUP>;
debounce-interval = <10>;
wakeup-source;
};
btn3 {
gpios = <&pcf8575 3 GPIO_ACTIVE_LOW>;
label = "btn3";
linux,code = <KEY_WAKEUP>;
debounce-interval = <10>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
gen_led0 {
label = "led0";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led0>;
gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "cpu0";
};
gen_led1 {
label = "led1";
gpios = <&pcf8575 8 GPIO_ACTIVE_HIGH>;
};
gen_led2 {
label = "led2";
gpios = <&pcf8575 9 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
gen_led3 {
label = "led3";
gpios = <&pcf8575 10 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
};
reg_usb_otg_vbus: regulator-otg-vbus@0 {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_h1_vbus: regulator-usbh1vbus@1 {
compatible = "regulator-fixed";
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_3v3: regulator-3v3@2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_3v3>;
compatible = "regulator-fixed";
regulator-name = "reg_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_enet: regulator-ethernet@3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_pwr>;
compatible = "regulator-fixed";
regulator-name = "ethernet-supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
startup-delay-us = <70000>;
enable-active-high;
vin-supply = <&sw4_reg>;
};
reg_audio: regulator-audio@4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_audio>;
compatible = "regulator-fixed";
regulator-name = "3v3_aud";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
vin-supply = <&reg_3v3>;
};
reg_hdmi: regulator-hdmi@5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_hdmi>;
compatible = "regulator-fixed";
regulator-name = "hdmi-supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&reg_3v3>;
};
reg_uart3: regulator-uart3@6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_uart3>;
compatible = "regulator-fixed";
regulator-name = "uart3-supply";
gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
vin-supply = <&reg_3v3>;
};
reg_1v8: regulator-1v8@7 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_1v8>;
compatible = "regulator-fixed";
regulator-name = "1v8-supply";
gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
vin-supply = <&reg_3v3>;
};
reg_pcie: regulator@8 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie_reg>;
regulator-name = "MPCIE_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
mipi_pwr: regulator@9 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mipi_pwr>;
regulator-name = "mipi_pwr_en";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
sound {
compatible = "fsl,imx-audio-wm8962";
model = "wm8962-audio";
ssi-controller = <&ssi2>;
audio-codec = <&codec>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"AMIC", "MICBIAS",
"IN3R", "AMIC";
mux-int-port = <2>;
mux-ext-port = <4>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "disabled";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-reset-duration = <10>;
phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
phy-supply = <&reg_enet>;
interrupt-parent = <&gpio1>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
no-1-8-v;
keep-power-in-suspend;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clock-frequency = <400000>;
status = "okay";
codec: wm8962@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clks IMX6QDL_CLK_CKO>;
clock-names = "xclk";
DCVDD-supply = <&reg_audio>;
DBVDD-supply = <&reg_audio>;
AVDD-supply = <&reg_audio>;
CPVDD-supply = <&reg_audio>;
MICVDD-supply = <&reg_audio>;
PLLVDD-supply = <&reg_audio>;
SPKVDD1-supply = <&reg_audio>;
SPKVDD2-supply = <&reg_audio>;
gpio-cfg = <
0x0000 /* 0:Default */
0x0000 /* 1:Default */
0x0013 /* 2:FN_DMICCLK */
0x0000 /* 3:Default */
0x8014 /* 4:FN_DMICCDAT */
0x0000 /* 5:Default */
>;
};
};
&i2c3 {
ov5640: camera@10 {
compatible = "ovti,ov5640";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ov5640>;
reg = <0x10>;
clocks = <&clks IMX6QDL_CLK_CKO>;
clock-names = "xclk";
DOVDD-supply = <&mipi_pwr>;
AVDD-supply = <&mipi_pwr>;
DVDD-supply = <&mipi_pwr>;
reset-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
powerdown-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
port {
ov5640_to_mipi_csi2: endpoint {
remote-endpoint = <&mipi_csi2_in>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
pcf8575: gpio@20 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcf8574>;
compatible = "nxp,pcf8575";
reg = <0x20>;
interrupt-parent = <&gpio6>;
interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
lines-initial-states = <0x0710>;
wakeup-source;
};
};
&mipi_csi {
status = "okay";
port@0 {
reg = <0>;
mipi_csi2_in: endpoint {
remote-endpoint = <&ov5640_to_mipi_csi2>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
status = "okay";
vpcie-supply = <&reg_pcie>;
/* fsl,max-link-speed = <2>; */
};
&ssi2 {
status = "okay";
};
&iomuxc {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0
MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
>;
};
pinctrl_i2c1: i2c1 {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_enet_pwr: enet_pwr {
fsl,pins = <
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0
>;
};
pinctrl_mipi_pwr: pwr_mipi {
fsl,pins = <MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b1>;
};
pinctrl_ov5640: ov5640grp {
fsl,pins = <
MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b1
MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b1
>;
};
pinctrl_reg_hdmi: reg_hdmi {
fsl,pins = <
MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0xd17059
MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x130b0
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x100b1
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17069
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17069
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17069
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17069
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17069
>;
};
pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz {
fsl,pins = <
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
>;
};
pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz {
fsl,pins = <
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* ENET_INT */
MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1b0b0 /* ETHR_nRST */
>;
};
pinctrl_reg_audio: audio-reg {
fsl,pins = <
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
>;
};
pinctrl_pcie: pcie {
fsl,pins = <
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
>;
};
pinctrl_pcie_reg: pciereggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
>;
};
pinctrl_pcf8574: pcf8575-pins {
fsl,pins = <
MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
>;
};
pinctrl_lcd: lcdgrp {
fsl,pins = <
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 /* R_LCD_DCLK */
MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x100b0 /* R_LCD_PANEL_PWR */
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 /* R_LCD_HSYNC */
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 /* R_LCD_VSYNC */
MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 /* R_LCD_MDISP */
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_reg_uart3: uart3reg {
fsl,pins = <
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
>;
};
pinctrl_reg_3v3: reg-3v3 {
fsl,pins = <
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0
>;
};
pinctrl_reg_1v8: reg-1v8 {
fsl,pins = <
MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0
>;
};
pinctrl_led0: led0 {
fsl,pins = <
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
>;
};
};

View File

@@ -1,5 +1,5 @@
/*
* Copyright 2016 Logic PD
* Copyright 2018 Logic PD
* This file is adapted from imx6qdl-sabresd.dtsi.
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
@@ -14,7 +14,6 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "imx6q.dtsi"
/ {
chosen {
@@ -24,6 +23,16 @@
memory {
reg = <0x10000000 0x80000000>;
};
reg_wl18xx_vmmc: regulator-wl18xx {
compatible = "regulator-fixed";
regulator-name = "vwl1837";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio7 0 GPIO_ACTIVE_HIGH>;
startup-delay-us = <70000>;
enable-active-high;
};
};
/* Reroute power feeding the CPU to come from the external PMIC */
@@ -44,6 +53,13 @@
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
status = "okay";
nand-on-flash-bbt;
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
@@ -78,7 +94,7 @@
regulator-max-microvolt = <3300000>;
regulator-name = "gen_3v3";
regulator-boot-on;
regulator-always-on;
/* regulator-always-on; */
};
sw3a_reg: sw3a {
@@ -98,12 +114,11 @@
};
sw4_reg: sw4 {
regulator-min-microvolt = <800000>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "gen_rgmii";
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
@@ -161,9 +176,33 @@
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
coin_reg: coin {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
};
};
temp_sense0: tmp102@4a {
compatible = "ti,tmp102";
reg = <0x4a>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tempsense>;
interrupt-parent = <&gpio6>;
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
#thermal-sensor-cells = <1>;
};
temp_sense1: tmp102@49 {
compatible = "ti,tmp102";
reg = <0x49>;
interrupt-parent = <&gpio6>;
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
#thermal-sensor-cells = <1>;
};
mfg_eeprom: at24@51 {
compatible = "atmel,24c64";
pagesize = <32>;
@@ -184,91 +223,46 @@
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x1b0b0
MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x1b0b0
MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x1b0b0
MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x1b0b0
MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x1b0b0
MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x1b0b0
MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x1b0b0
MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x1b0b0
MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x1b0b0
MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x1b0b0
MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x1b0b0
MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x1b0b0
MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x1b0b0
MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x1b0b0
MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x1b0b0
MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x1b0b0
MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x1b0b0
MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x1b0b0
MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x1b0b0
MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x1b0b0
MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x1b0b0
MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x1b0b0
MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x80000000
MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x80000000
MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x80000000
MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x80000000
MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000
MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x80000000
MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000
MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x80000000
MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000
MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000
MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x80000000
MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x80000000
MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x80000000
MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x80000000
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000
MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x80000000
MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x80000000
MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x80000000
MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x80000000
MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x80000000
MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x80000000
MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x80000000
MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x80000000
MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x80000000
MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000
MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x80000000
MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x80000000
MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x80000000
MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x80000000
MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x80000000
MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x80000000
MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x80000000
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000
MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x80000000
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000
MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x80000000
MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x80000000
MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x80000000
MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x80000000
MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x80000000
MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x80000000
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x80000000
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x80000000
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000
MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x80000000
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000
MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x80000000
MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x80000000
MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x80000000
MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x80000000
MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x80000000
MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x80000000
MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x80000000
MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x80000000
MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x80000000
MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000
MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x1b0b0
MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x1b0b0
MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x1b0b0
MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x1b0b0
MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x1b0b0
MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x1b0b0
MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x1b0b0
MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x1b0b0
MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x1b0b0
MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x1b0b0
MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x1b0b0
MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x1b0b0
MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x1b0b0
MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x1b0b0
MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x1b0b0
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
>;
};
@@ -288,6 +282,7 @@
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x13059 /* BT_EN */
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
@@ -297,28 +292,37 @@
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170B9
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100B9
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170B9
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170B9
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170B9
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170B9
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* WL_IRQ */
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1f0b0 /* WLAN_EN */
MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1f0b0 /* BT_EN */
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17049
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10049
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17049
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17049
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17049
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17049
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x130b0 /* WL_IRQ */
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* WLAN_EN */
>;
};
pinctrl_tempsense: tempsensegrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Temp Sense Alert */
>;
};
};
&snvs_poweroff {
status = "okay";
};
&uart1 {
@@ -331,31 +335,39 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
uart-has-rtscts;
bluetooth {
compatible = "ti,wl1837-st";
enable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
};
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
non-removable;
keep-power-in-suspend;
enable-sdio-wakeup;
status = "okay";
vmmc-supply = <&sw2_reg>;
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
non-removable;
cap-power-off-card;
keep-power-in-suspend;
enable-sdio-wakeup;
vmmc-supply = <&sw2_reg>;
wakeup-source;
vmmc-supply = <&reg_wl18xx_vmmc>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
wlcore: wlcore@0 {
wlcore: wlcore@2 {
compatible = "ti,wl1837";
reg = <2>;
interrupt-parent = <&gpio7>;
interrupts = <1 GPIO_ACTIVE_HIGH>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
tcxo-clock-frequency = <26000000>;
};
};

View File

@@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 NXP
*/
#include "imx6qdl-sabreauto-u-boot.dtsi"

View File

@@ -0,0 +1,13 @@
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2013 Freescale Semiconductor, Inc.
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-sabreauto.dtsi"
/ {
model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board";
compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
};

View File

@@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 NXP
*/
#include "imx6qdl-sabresd-u-boot.dtsi"

View File

@@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2013 Freescale Semiconductor, Inc.
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-sabresd.dtsi"
/ {
model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
};
&ipu1_csi1_from_ipu1_csi1_mux {
clock-lanes = <0>;
data-lanes = <1 2>;
};

View File

@@ -1,12 +1,6 @@
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2013 Freescale Semiconductor, Inc.
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6dl-pinfunc.h"
@@ -39,6 +33,7 @@
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
#cooling-cells = <2>;
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
@@ -56,39 +51,57 @@
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
operating-points = <
/* kHz uV */
996000 1250000
792000 1175000
396000 1150000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC-PU uV */
996000 1175000
792000 1175000
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
<&clks IMX6QDL_CLK_PLL1_SW>,
<&clks IMX6QDL_CLK_PLL1_SYS>;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys";
arm-supply = <&reg_arm>;
pu-supply = <&reg_pu>;
soc-supply = <&reg_soc>;
};
};
soc {
ocram: sram@00900000 {
ocram: sram@900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x20000>;
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
aips1: aips-bus@02000000 {
iomuxc: iomuxc@020e0000 {
aips1: aips-bus@2000000 {
iomuxc: iomuxc@20e0000 {
compatible = "fsl,imx6dl-iomuxc";
};
pxp: pxp@020f0000 {
pxp: pxp@20f0000 {
reg = <0x020f0000 0x4000>;
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
};
epdc: epdc@020f4000 {
epdc: epdc@20f4000 {
reg = <0x020f4000 0x4000>;
interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
};
lcdif: lcdif@020f8000 {
reg = <0x020f8000 0x4000>;
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
};
};
aips2: aips-bus@02100000 {
i2c4: i2c@021f8000 {
aips2: aips-bus@2100000 {
i2c4: i2c@21f8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
@@ -100,14 +113,177 @@
};
};
capture-subsystem {
compatible = "fsl,imx-capture-subsystem";
ports = <&ipu1_csi0>, <&ipu1_csi1>;
};
display-subsystem {
compatible = "fsl,imx-display-subsystem";
ports = <&ipu1_di0>, <&ipu1_di1>;
};
};
gpu-subsystem {
compatible = "fsl,imx-gpu-subsystem";
cores = <&gpu_2d>, <&gpu_3d>;
&gpio1 {
gpio-ranges = <&iomuxc 0 131 2>, <&iomuxc 2 137 8>, <&iomuxc 10 189 2>,
<&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>,
<&iomuxc 15 191 1>, <&iomuxc 16 185 2>, <&iomuxc 18 184 1>,
<&iomuxc 19 187 1>, <&iomuxc 20 183 1>, <&iomuxc 21 188 1>,
<&iomuxc 22 123 3>, <&iomuxc 25 121 1>, <&iomuxc 26 127 1>,
<&iomuxc 27 126 1>, <&iomuxc 28 128 1>, <&iomuxc 29 130 1>,
<&iomuxc 30 129 1>, <&iomuxc 31 122 1>;
};
&gpio2 {
gpio-ranges = <&iomuxc 0 161 8>, <&iomuxc 8 208 8>, <&iomuxc 16 74 1>,
<&iomuxc 17 73 1>, <&iomuxc 18 72 1>, <&iomuxc 19 71 1>,
<&iomuxc 20 70 1>, <&iomuxc 21 69 1>, <&iomuxc 22 68 1>,
<&iomuxc 23 79 2>, <&iomuxc 25 118 2>, <&iomuxc 27 117 1>,
<&iomuxc 28 113 4>;
};
&gpio3 {
gpio-ranges = <&iomuxc 0 97 2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>,
<&iomuxc 16 81 16>;
};
&gpio4 {
gpio-ranges = <&iomuxc 5 136 1>, <&iomuxc 6 145 1>, <&iomuxc 7 150 1>,
<&iomuxc 8 146 1>, <&iomuxc 9 151 1>, <&iomuxc 10 147 1>,
<&iomuxc 11 152 1>, <&iomuxc 12 148 1>, <&iomuxc 13 153 1>,
<&iomuxc 14 149 1>, <&iomuxc 15 154 1>, <&iomuxc 16 39 7>,
<&iomuxc 23 56 1>, <&iomuxc 24 61 7>, <&iomuxc 31 46 1>;
};
&gpio5 {
gpio-ranges = <&iomuxc 0 120 1>, <&iomuxc 2 77 1>, <&iomuxc 4 76 1>,
<&iomuxc 5 47 9>, <&iomuxc 14 57 4>, <&iomuxc 18 37 1>,
<&iomuxc 19 36 1>, <&iomuxc 20 35 1>, <&iomuxc 21 38 1>,
<&iomuxc 22 29 6>, <&iomuxc 28 19 4>;
};
&gpio6 {
gpio-ranges = <&iomuxc 0 23 6>, <&iomuxc 6 75 1>, <&iomuxc 7 156 1>,
<&iomuxc 8 155 1>, <&iomuxc 9 170 1>, <&iomuxc 10 169 1>,
<&iomuxc 11 157 1>, <&iomuxc 14 158 3>, <&iomuxc 17 204 1>,
<&iomuxc 18 203 1>, <&iomuxc 19 182 1>, <&iomuxc 20 177 4>,
<&iomuxc 24 175 1>, <&iomuxc 25 171 1>, <&iomuxc 26 181 1>,
<&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31 78 1>;
};
&gpio7 {
gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc 1 201 1>, <&iomuxc 2 196 1>,
<&iomuxc 3 195 1>, <&iomuxc 4 197 4>, <&iomuxc 8 205 1>,
<&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>;
};
&gpr {
ipu1_csi0_mux {
compatible = "video-mux";
mux-controls = <&mux 0>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ipu1_csi0_mux_from_mipi_vc0: endpoint {
remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
};
};
port@1 {
reg = <1>;
ipu1_csi0_mux_from_mipi_vc1: endpoint {
remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>;
};
};
port@2 {
reg = <2>;
ipu1_csi0_mux_from_mipi_vc2: endpoint {
remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>;
};
};
port@3 {
reg = <3>;
ipu1_csi0_mux_from_mipi_vc3: endpoint {
remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>;
};
};
port@4 {
reg = <4>;
ipu1_csi0_mux_from_parallel_sensor: endpoint {
};
};
port@5 {
reg = <5>;
ipu1_csi0_mux_to_ipu1_csi0: endpoint {
remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
};
};
};
ipu1_csi1_mux {
compatible = "video-mux";
mux-controls = <&mux 1>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ipu1_csi1_mux_from_mipi_vc0: endpoint {
remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>;
};
};
port@1 {
reg = <1>;
ipu1_csi1_mux_from_mipi_vc1: endpoint {
remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>;
};
};
port@2 {
reg = <2>;
ipu1_csi1_mux_from_mipi_vc2: endpoint {
remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>;
};
};
port@3 {
reg = <3>;
ipu1_csi1_mux_from_mipi_vc3: endpoint {
remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>;
};
};
port@4 {
reg = <4>;
ipu1_csi1_mux_from_parallel_sensor: endpoint {
};
};
port@5 {
reg = <5>;
ipu1_csi1_mux_to_ipu1_csi1: endpoint {
remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>;
};
};
};
};
@@ -119,6 +295,12 @@
compatible = "fsl,imx6dl-hdmi";
};
&ipu1_csi1 {
ipu1_csi1_from_ipu1_csi1_mux: endpoint {
remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;
};
};
&ldb {
clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
@@ -128,6 +310,82 @@
"di0", "di1";
};
&mipi_csi {
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi_vc0_to_ipu1_csi0_mux: endpoint@0 {
reg = <0>;
remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
};
mipi_vc0_to_ipu1_csi1_mux: endpoint@1 {
reg = <1>;
remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>;
};
};
port@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
mipi_vc1_to_ipu1_csi0_mux: endpoint@0 {
reg = <0>;
remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>;
};
mipi_vc1_to_ipu1_csi1_mux: endpoint@1 {
reg = <1>;
remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>;
};
};
port@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
mipi_vc2_to_ipu1_csi0_mux: endpoint@0 {
reg = <0>;
remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>;
};
mipi_vc2_to_ipu1_csi1_mux: endpoint@1 {
reg = <1>;
remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>;
};
};
port@4 {
reg = <4>;
#address-cells = <1>;
#size-cells = <0>;
mipi_vc3_to_ipu1_csi0_mux: endpoint@0 {
reg = <0>;
remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>;
};
mipi_vc3_to_ipu1_csi1_mux: endpoint@1 {
reg = <1>;
remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>;
};
};
};
&mux {
mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */
<0x34 0x00000038>, /* IPU_CSI1_MUX */
<0x0c 0x0000000c>, /* HDMI_MUX_CTL */
<0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
<0x0c 0x00000300>, /* LVDS1_MUX_CTL */
<0x28 0x00000003>, /* DCIC1_MUX_CTL */
<0x28 0x0000000c>; /* DCIC2_MUX_CTL */
};
&vpu {
compatible = "fsl,imx6dl-vpu", "cnm,coda960";
};

View File

@@ -1,5 +1,5 @@
/*
* Copyright 2017 Logic PD, Inc.
* Copyright 2018 Logic PD, Inc.
* Based on SabreSD, Copyright 2016 Freescale Semiconductor, Inc.
*
* This file is dual-licensed: you can use it either under the terms
@@ -42,149 +42,137 @@
*/
/dts-v1/;
#include "imx6qdl-logicpd.dtsi"
#include "imx6q.dtsi"
#include "imx6-logicpd-som.dtsi"
#include "imx6-logicpd-baseboard.dtsi"
/ {
model = "Logic PD i.MX6QDL SOM";
model = "Logic PD i.MX6QD SOM-M3 (HDMI)";
compatible = "fsl,imx6q";
reg_usb_otg_vbus: regulator-otg-vbus@0 {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
enable-active-high;
backlight: backlight_lvds {
compatible = "pwm-backlight";
pwms = <&pwm3 0 20000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
power-supply = <&reg_lcd>;
};
reg_usb_h1_vbus: regulator-usbh1vbus@1 {
reg_lcd: regulator-lcd {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_reg>;
compatible = "regulator-fixed";
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
};
reg_3v3: regulator-3v3@2 {
compatible = "regulator-fixed";
regulator-name = "reg_3v3";
regulator-name = "lcd_panel_pwr";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
vin-supply = <&reg_3v3>;
startup-delay-us = <500000>;
};
lcd_reset: lcd_reset {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_reset>;
compatible = "regulator-fixed";
regulator-name = "nLCD_RESET";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
vin-supply = <&reg_lcd>;
};
panel-lvds0 {
compatible = "ampire,am800480b3tmqw";
backlight = <&backlight>;
port {
panel_in_lvds0: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
};
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
&hdmi {
ddc-i2c-bus = <&i2c3>;
status = "okay";
};
&usbh1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
vbus-supply = <&reg_usb_h1_vbus>;
status = "okay";
&i2c1 {
ili_touch: ilitouch@26 {
compatible = "ili,ili2117a";
reg = <0x26>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touchscreen>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_RISING>;
ili2117a,poll-period = <10>;
ili2117a,max-touch = <2>;
};
};
&usbh2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh2>;
phy_type = "hsic";
disable-over-current;
status = "okay";
&reg_hdmi {
regulator-always-on;
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
&ldb {
status = "okay";
lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
status = "okay";
port@4 {
reg = <4>;
lvds0_out: endpoint {
remote-endpoint = <&panel_in_lvds0>;
};
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rmii";
phy-speed = <10>;
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
<&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
<&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
};
&pwm3 {
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
no-1-8-v;
keep-power-in-suspend;
status = "okay";
};
&iomuxc {
pinctrl_enet: enetgrp {
pinctrl_lcd_reg: lcdreg {
fsl,pins = <
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 /* nINT */
MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 /* Ethernet Reset */
MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x100b0 /* R_LCD_PANEL_PWR */
>;
};
pinctrl_gpio_leds: gpioledsgrp {
pinctrl_lcd_reset: lcdreset {
fsl,pins = <
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x130b0
MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x130b0
MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x130b0
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 /* LCD_nRESET */
>;
};
pinctrl_usbh1: usbh1grp {
pinctrl_touchscreen: touchscreengrp {
fsl,pins = <
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* USB_H1_PWR_EN */
>;
};
pinctrl_usbh2: usbh2grp {
fsl,pins = <
MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x17030
MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x13030
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0 /* USB_OTG_PWR_EN */
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* TOUCH_nPINTDAV */
>;
};
};

View File

@@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 NXP
*/
#include "imx6qdl-sabreauto-u-boot.dtsi"

View File

@@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2012 Freescale Semiconductor, Inc.
// Copyright 2011 Linaro Ltd.
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-sabreauto.dtsi"
/ {
model = "Freescale i.MX6 Quad SABRE Automotive Board";
compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
};
&sata {
status = "okay";
};

View File

@@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 NXP
*/
#include "imx6qdl-sabresd-u-boot.dtsi"

View File

@@ -0,0 +1,23 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2012 Freescale Semiconductor, Inc.
// Copyright 2011 Linaro Ltd.
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-sabresd.dtsi"
/ {
model = "Freescale i.MX6 Quad SABRE Smart Device Board";
compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
};
&sata {
status = "okay";
};
&ipu1_csi1_from_mipi_vc1 {
clock-lanes = <0>;
data-lanes = <1 2>;
};

View File

@@ -1,12 +1,6 @@
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2013 Freescale Semiconductor, Inc.
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6q-pinfunc.h"
@@ -44,6 +38,7 @@
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
#cooling-cells = <2>;
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
@@ -56,38 +51,119 @@
soc-supply = <&reg_soc>;
};
cpu@1 {
cpu1: cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
operating-points = <
/* kHz uV */
1200000 1275000
996000 1250000
852000 1250000
792000 1175000
396000 975000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC-PU uV */
1200000 1275000
996000 1250000
852000 1250000
792000 1175000
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
<&clks IMX6QDL_CLK_PLL1_SW>,
<&clks IMX6QDL_CLK_PLL1_SYS>;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys";
arm-supply = <&reg_arm>;
pu-supply = <&reg_pu>;
soc-supply = <&reg_soc>;
};
cpu@2 {
cpu2: cpu@2 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <2>;
next-level-cache = <&L2>;
operating-points = <
/* kHz uV */
1200000 1275000
996000 1250000
852000 1250000
792000 1175000
396000 975000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC-PU uV */
1200000 1275000
996000 1250000
852000 1250000
792000 1175000
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
<&clks IMX6QDL_CLK_PLL1_SW>,
<&clks IMX6QDL_CLK_PLL1_SYS>;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys";
arm-supply = <&reg_arm>;
pu-supply = <&reg_pu>;
soc-supply = <&reg_soc>;
};
cpu@3 {
cpu3: cpu@3 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <3>;
next-level-cache = <&L2>;
operating-points = <
/* kHz uV */
1200000 1275000
996000 1250000
852000 1250000
792000 1175000
396000 975000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC-PU uV */
1200000 1275000
996000 1250000
852000 1250000
792000 1175000
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
<&clks IMX6QDL_CLK_PLL1_SW>,
<&clks IMX6QDL_CLK_PLL1_SYS>;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys";
arm-supply = <&reg_arm>;
pu-supply = <&reg_pu>;
soc-supply = <&reg_soc>;
};
};
soc {
ocram: sram@00900000 {
ocram: sram@900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x40000>;
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
aips-bus@02000000 { /* AIPS1 */
spba-bus@02000000 {
ecspi5: ecspi@02018000 {
aips-bus@2000000 { /* AIPS1 */
spba-bus@2000000 {
ecspi5: spi@2018000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -96,18 +172,18 @@
clocks = <&clks IMX6Q_CLK_ECSPI5>,
<&clks IMX6Q_CLK_ECSPI5>;
clock-names = "ipg", "per";
dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
dmas = <&sdma 11 8 1>, <&sdma 12 8 2>;
dma-names = "rx", "tx";
status = "disabled";
};
};
iomuxc: iomuxc@020e0000 {
iomuxc: iomuxc@20e0000 {
compatible = "fsl,imx6q-iomuxc";
};
};
sata: sata@02200000 {
sata: sata@2200000 {
compatible = "fsl,imx6q-ahci";
reg = <0x02200000 0x4000>;
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
@@ -118,17 +194,17 @@
status = "disabled";
};
gpu_vg: gpu@02204000 {
gpu_vg: gpu@2204000 {
compatible = "vivante,gc";
reg = <0x02204000 0x4000>;
interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
<&clks IMX6QDL_CLK_GPU2D_CORE>;
clock-names = "bus", "core";
power-domains = <&gpc 1>;
power-domains = <&pd_pu>;
};
ipu2: ipu@02800000 {
ipu2: ipu@2800000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ipu";
@@ -143,69 +219,181 @@
ipu2_csi0: port@0 {
reg = <0>;
ipu2_csi0_from_mipi_vc2: endpoint {
remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
};
};
ipu2_csi1: port@1 {
reg = <1>;
ipu2_csi1_from_ipu2_csi1_mux: endpoint {
remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
};
};
ipu2_di0: port@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
ipu2_di0_disp0: disp0-endpoint {
ipu2_di0_disp0: endpoint@0 {
reg = <0>;
};
ipu2_di0_hdmi: hdmi-endpoint {
ipu2_di0_hdmi: endpoint@1 {
reg = <1>;
remote-endpoint = <&hdmi_mux_2>;
};
ipu2_di0_mipi: mipi-endpoint {
ipu2_di0_mipi: endpoint@2 {
reg = <2>;
remote-endpoint = <&mipi_mux_2>;
};
ipu2_di0_lvds0: lvds0-endpoint {
ipu2_di0_lvds0: endpoint@3 {
reg = <3>;
remote-endpoint = <&lvds0_mux_2>;
};
ipu2_di0_lvds1: lvds1-endpoint {
ipu2_di0_lvds1: endpoint@4 {
reg = <4>;
remote-endpoint = <&lvds1_mux_2>;
};
};
ipu2_di1: port@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
ipu2_di1_hdmi: hdmi-endpoint {
ipu2_di1_hdmi: endpoint@1 {
reg = <1>;
remote-endpoint = <&hdmi_mux_3>;
};
ipu2_di1_mipi: mipi-endpoint {
ipu2_di1_mipi: endpoint@2 {
reg = <2>;
remote-endpoint = <&mipi_mux_3>;
};
ipu2_di1_lvds0: lvds0-endpoint {
ipu2_di1_lvds0: endpoint@3 {
reg = <3>;
remote-endpoint = <&lvds0_mux_3>;
};
ipu2_di1_lvds1: lvds1-endpoint {
ipu2_di1_lvds1: endpoint@4 {
reg = <4>;
remote-endpoint = <&lvds1_mux_3>;
};
};
};
};
capture-subsystem {
compatible = "fsl,imx-capture-subsystem";
ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
};
display-subsystem {
compatible = "fsl,imx-display-subsystem";
ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
};
};
gpu-subsystem {
compatible = "fsl,imx-gpu-subsystem";
cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>;
&gpio1 {
gpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>,
<&iomuxc 4 142 2>, <&iomuxc 6 140 1>, <&iomuxc 7 144 2>,
<&iomuxc 9 138 1>, <&iomuxc 10 213 3>, <&iomuxc 13 20 1>,
<&iomuxc 14 19 1>, <&iomuxc 15 21 1>, <&iomuxc 16 208 1>,
<&iomuxc 17 207 1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
<&iomuxc 22 116 10>;
};
&gpio2 {
gpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
<&iomuxc 31 44 1>;
};
&gpio3 {
gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
};
&gpio4 {
gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
};
&gpio5 {
gpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>,
<&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
};
&gpio6 {
gpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>,
<&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19 22 12>,
<&iomuxc 31 86 1>;
};
&gpio7 {
gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
};
&gpr {
ipu1_csi0_mux {
compatible = "video-mux";
mux-controls = <&mux 0>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ipu1_csi0_mux_from_mipi_vc0: endpoint {
remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
};
};
port@1 {
reg = <1>;
ipu1_csi0_mux_from_parallel_sensor: endpoint {
};
};
port@2 {
reg = <2>;
ipu1_csi0_mux_to_ipu1_csi0: endpoint {
remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
};
};
};
ipu2_csi1_mux {
compatible = "video-mux";
mux-controls = <&mux 1>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ipu2_csi1_mux_from_mipi_vc3: endpoint {
remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
};
};
port@1 {
reg = <1>;
ipu2_csi1_mux_from_parallel_sensor: endpoint {
};
};
port@2 {
reg = <2>;
ipu2_csi1_mux_to_ipu2_csi1: endpoint {
remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
};
};
};
};
@@ -229,6 +417,12 @@
};
};
&ipu1_csi1 {
ipu1_csi1_from_mipi_vc1: endpoint {
remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
};
};
&ldb {
clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
@@ -275,6 +469,40 @@
};
};
&mipi_csi {
port@1 {
reg = <1>;
mipi_vc0_to_ipu1_csi0_mux: endpoint {
remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
};
};
port@2 {
reg = <2>;
mipi_vc1_to_ipu1_csi1: endpoint {
remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
};
};
port@3 {
reg = <3>;
mipi_vc2_to_ipu2_csi0: endpoint {
remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
};
};
port@4 {
reg = <4>;
mipi_vc3_to_ipu2_csi1_mux: endpoint {
remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
};
};
};
&mipi_dsi {
ports {
port@2 {
@@ -295,6 +523,16 @@
};
};
&mux {
mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
<0x04 0x00100000>, /* MIPI_IPU2_MUX */
<0x0c 0x0000000c>, /* HDMI_MUX_CTL */
<0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
<0x0c 0x00000300>, /* LVDS1_MUX_CTL */
<0x28 0x00000003>, /* DCIC1_MUX_CTL */
<0x28 0x0000000c>; /* DCIC2_MUX_CTL */
};
&vpu {
compatible = "fsl,imx6q-vpu", "cnm,coda960";
};

View File

@@ -0,0 +1,21 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 NXP
*/
#include "imx6qdl-u-boot.dtsi"
/ {
aliases {
mmc0 = &usdhc3;
};
};
&usdhc3 {
no-1-8-v;
u-boot,dm-spl;
};
&pinctrl_usdhc3 {
u-boot,dm-spl;
};

View File

@@ -0,0 +1,810 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2012 Freescale Semiconductor, Inc.
// Copyright 2011 Linaro Ltd.
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
chosen {
stdout-path = &uart4;
};
memory@10000000 {
reg = <0x10000000 0x80000000>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
user {
label = "debug";
gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
home {
label = "Home";
gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
wakeup-source;
};
back {
label = "Back";
gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
wakeup-source;
};
program {
label = "Program";
gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
linux,code = <KEY_PROGRAM>;
wakeup-source;
};
volume-up {
label = "Volume Up";
gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
wakeup-source;
};
volume-down {
label = "Volume Down";
gpios = <&gpio5 14 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
wakeup-source;
};
};
clocks {
codec_osc: anaclk2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_audio: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "cs42888_supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb_h1_vbus: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg_vbus: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
sound-cs42888 {
compatible = "fsl,imx6-sabreauto-cs42888",
"fsl,imx-audio-cs42888";
model = "imx-cs42888";
audio-cpu = <&esai>;
audio-asrc = <&asrc>;
audio-codec = <&codec>;
audio-routing =
"Line Out Jack", "AOUT1L",
"Line Out Jack", "AOUT1R",
"Line Out Jack", "AOUT2L",
"Line Out Jack", "AOUT2R",
"Line Out Jack", "AOUT3L",
"Line Out Jack", "AOUT3R",
"Line Out Jack", "AOUT4L",
"Line Out Jack", "AOUT4R",
"AIN1L", "Line In Jack",
"AIN1R", "Line In Jack",
"AIN2L", "Line In Jack",
"AIN2R", "Line In Jack";
};
sound-spdif {
compatible = "fsl,imx-audio-spdif",
"fsl,imx-sabreauto-spdif";
model = "imx-spdif";
spdif-controller = <&spdif>;
spdif-in;
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm3 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
status = "okay";
};
i2cmux {
compatible = "i2c-mux-gpio";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3mux>;
mux-gpios = <&gpio5 4 0>;
i2c-parent = <&i2c3>;
idle-state = <0>;
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
adv7180: camera@21 {
compatible = "adi,adv7180";
reg = <0x21>;
powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio1>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
port {
adv7180_to_ipu1_csi0_mux: endpoint {
remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
bus-width = <8>;
};
};
};
max7310_a: gpio@30 {
compatible = "maxim,max7310";
reg = <0x30>;
gpio-controller;
#gpio-cells = <2>;
};
max7310_b: gpio@32 {
compatible = "maxim,max7310";
reg = <0x32>;
gpio-controller;
#gpio-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_max7310>;
reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
max7310_c: gpio@34 {
compatible = "maxim,max7310";
reg = <0x34>;
gpio-controller;
#gpio-cells = <2>;
};
light-sensor@44 {
compatible = "isil,isl29023";
reg = <0x44>;
interrupt-parent = <&gpio5>;
interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
};
magnetometer@e {
compatible = "fsl,mag3110";
reg = <0x0e>;
interrupt-parent = <&gpio2>;
interrupts = <29 IRQ_TYPE_EDGE_RISING>;
};
accelerometer@1c {
compatible = "fsl,mma8451";
reg = <0x1c>;
interrupt-parent = <&gpio6>;
interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
};
};
};
};
&ipu1_csi0_from_ipu1_csi0_mux {
bus-width = <8>;
};
&ipu1_csi0_mux_from_parallel_sensor {
remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
bus-width = <8>;
};
&ipu1_csi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu1_csi0>;
};
&clks {
assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
<&clks IMX6QDL_PLL4_BYPASS>,
<&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>,
<&clks IMX6QDL_CLK_PLL4_POST_DIV>;
assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
<&clks IMX6QDL_PLL4_BYPASS_SRC>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>;
};
&ecspi1 {
cs-gpios = <&gpio3 19 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
status = "disabled"; /* pin conflict with WEIM NOR */
flash: m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p32", "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&esai {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esai>;
assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>,
<&clks IMX6QDL_CLK_ESAI_EXTAL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
assigned-clock-rates = <0>, <24576000>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;
status = "okay";
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
status = "okay";
};
&hdmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi_cec>;
ddc-i2c-bus = <&i2c2>;
status = "okay";
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
pmic: pfuze100@8 {
compatible = "fsl,pfuze100";
reg = <0x08>;
regulators {
sw1a_reg: sw1ab {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw1c_reg: sw1c {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
sw3a_reg: sw3a {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-boot-on;
regulator-always-on;
};
sw3b_reg: sw3b {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-boot-on;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-boot-on;
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen2_reg: vgen2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen3_reg: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
vgen4_reg: vgen4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen5_reg: vgen5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen6_reg: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
codec: cs42888@48 {
compatible = "cirrus,cs42888";
reg = <0x48>;
clocks = <&codec_osc>;
clock-names = "mclk";
VA-supply = <&reg_audio>;
VD-supply = <&reg_audio>;
VLS-supply = <&reg_audio>;
VLC-supply = <&reg_audio>;
};
touchscreen@4 {
compatible = "eeti,egalax_ts";
reg = <0x04>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_egalax_int>;
interrupt-parent = <&gpio2>;
interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
};
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx6qdl-sabreauto {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
>;
};
pinctrl_ecspi1_cs: ecspi1cs {
fsl,pins = <
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
>;
};
pinctrl_egalax_int: egalax-intgrp {
fsl,pins = <
MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0xb0b1
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
pinctrl_esai: esaigrp {
fsl,pins = <
MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
>;
};
pinctrl_gpio_keys: gpiokeysgrp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0
MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0
MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0
MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
>;
};
pinctrl_hdmi_cec: hdmicecgrp {
fsl,pins = <
MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_i2c3mux: i2c3muxgrp {
fsl,pins = <
MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1
>;
};
pinctrl_ipu1_csi0: ipu1csi0grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
>;
};
pinctrl_max7310: max7310grp {
fsl,pins = <
MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
>;
};
pinctrl_pwm3: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_gpt_input_capture0: gptinputcapture0grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x1b0b0
>;
};
pinctrl_gpt_input_capture1: gptinputcapture1grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x1b0b0
>;
};
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
>;
};
pinctrl_weim_cs0: weimcs0grp {
fsl,pins = <
MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
>;
};
pinctrl_weim_nor: weimnorgrp {
fsl,pins = <
MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
>;
};
};
};
&ldb {
status = "okay";
lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
};
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&spdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spdif>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&weim {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
ranges = <0 0 0x08000000 0x08000000>;
status = "disabled"; /* pin conflict with SPI NOR */
nor@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x02000000>;
#address-cells = <1>;
#size-cells = <1>;
bank-width = <2>;
fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
0x0000c000 0x1404a38e 0x00000000>;
};
};

View File

@@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 NXP
*/
#include "imx6qdl-u-boot.dtsi"
&usdhc3 {
u-boot,dm-spl;
};
&pinctrl_usdhc3 {
u-boot,dm-spl;
};

View File

@@ -0,0 +1,741 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2012 Freescale Semiconductor, Inc.
// Copyright 2011 Linaro Ltd.
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
aliases {
mmc1 = &usdhc3;
};
chosen {
stdout-path = &uart1;
};
memory@10000000 {
reg = <0x10000000 0x40000000>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usb_otg_vbus: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 0>;
enable-active-high;
vin-supply = <&swbst_reg>;
};
reg_usb_h1_vbus: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 29 0>;
enable-active-high;
vin-supply = <&swbst_reg>;
};
reg_audio: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "wm8962-supply";
gpio = <&gpio4 10 0>;
enable-active-high;
};
reg_pcie: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie_reg>;
regulator-name = "MPCIE_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 19 0>;
enable-active-high;
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
power {
label = "Power Button";
gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
wakeup-source;
linux,code = <KEY_POWER>;
};
volume-up {
label = "Volume Up";
gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
wakeup-source;
linux,code = <KEY_VOLUMEUP>;
};
volume-down {
label = "Volume Down";
gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
wakeup-source;
linux,code = <KEY_VOLUMEDOWN>;
};
};
sound {
compatible = "fsl,imx6q-sabresd-wm8962",
"fsl,imx-audio-wm8962";
model = "wm8962-audio";
ssi-controller = <&ssi2>;
audio-codec = <&codec>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"AMIC", "MICBIAS",
"IN3R", "AMIC";
mux-int-port = <2>;
mux-ext-port = <3>;
};
backlight_lvds: backlight-lvds {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
status = "okay";
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
red {
gpios = <&gpio1 2 0>;
default-state = "on";
};
};
panel {
compatible = "hannstar,hsd100pxn1";
backlight = <&backlight_lvds>;
port {
panel_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
};
};
&ipu1_csi0_from_ipu1_csi0_mux {
bus-width = <8>;
data-shift = <12>; /* Lines 19:12 used */
hsync-active = <1>;
vsync-active = <1>;
};
&ipu1_csi0_mux_from_parallel_sensor {
remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
};
&ipu1_csi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu1_csi0>;
};
&mipi_csi {
status = "okay";
port@0 {
reg = <0>;
mipi_csi2_in: endpoint {
remote-endpoint = <&ov5640_to_mipi_csi2>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&ecspi1 {
cs-gpios = <&gpio4 9 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
flash: m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p32", "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
status = "okay";
};
&hdmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi_cec>;
ddc-i2c-bus = <&i2c2>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
codec: wm8962@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clks IMX6QDL_CLK_CKO>;
DCVDD-supply = <&reg_audio>;
DBVDD-supply = <&reg_audio>;
AVDD-supply = <&reg_audio>;
CPVDD-supply = <&reg_audio>;
MICVDD-supply = <&reg_audio>;
PLLVDD-supply = <&reg_audio>;
SPKVDD1-supply = <&reg_audio>;
SPKVDD2-supply = <&reg_audio>;
gpio-cfg = <
0x0000 /* 0:Default */
0x0000 /* 1:Default */
0x0013 /* 2:FN_DMICCLK */
0x0000 /* 3:Default */
0x8014 /* 4:FN_DMICCDAT */
0x0000 /* 5:Default */
>;
};
ov5642: camera@3c {
compatible = "ovti,ov5642";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ov5642>;
clocks = <&clks IMX6QDL_CLK_CKO>;
clock-names = "xclk";
reg = <0x3c>;
DOVDD-supply = <&vgen4_reg>; /* 1.8v */
AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3
rev B board is VGEN5 */
DVDD-supply = <&vgen2_reg>; /* 1.5v*/
powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
status = "disabled";
port {
ov5642_to_ipu1_csi0_mux: endpoint {
remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
bus-width = <8>;
hsync-active = <1>;
vsync-active = <1>;
};
};
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
ov5640: camera@3c {
compatible = "ovti,ov5640";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ov5640>;
reg = <0x3c>;
clocks = <&clks IMX6QDL_CLK_CKO>;
clock-names = "xclk";
DOVDD-supply = <&vgen4_reg>; /* 1.8v */
AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3
rev B board is VGEN5 */
DVDD-supply = <&vgen2_reg>; /* 1.5v*/
powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
port {
ov5640_to_mipi_csi2: endpoint {
remote-endpoint = <&mipi_csi2_in>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
pmic: pfuze100@8 {
compatible = "fsl,pfuze100";
reg = <0x08>;
regulators {
sw1a_reg: sw1ab {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw1c_reg: sw1c {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw3a_reg: sw3a {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-boot-on;
regulator-always-on;
};
sw3b_reg: sw3b {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-boot-on;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-boot-on;
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen2_reg: vgen2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen3_reg: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
vgen4_reg: vgen4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen5_reg: vgen5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen6_reg: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
egalax_ts@4 {
compatible = "eeti,egalax_ts";
reg = <0x04>;
interrupt-parent = <&gpio6>;
interrupts = <7 2>;
wakeup-gpios = <&gpio6 7 0>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx6qdl-sabresd {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>;
};
pinctrl_gpio_keys: gpio_keysgrp {
fsl,pins = <
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
>;
};
pinctrl_hdmi_cec: hdmicecgrp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_ipu1_csi0: ipu1csi0grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
>;
};
pinctrl_ov5640: ov5640grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0
MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0
>;
};
pinctrl_ov5642: ov5642grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
>;
};
pinctrl_pcie_reg: pciereggrp {
fsl,pins = <
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
>;
};
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0
>;
};
};
gpio_leds {
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
>;
};
};
};
&ldb {
status = "okay";
lvds-channel@1 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
port@4 {
reg = <4>;
lvds0_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_pcie>;
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&reg_arm {
vin-supply = <&sw1a_reg>;
};
&reg_pu {
vin-supply = <&sw1c_reg>;
};
&reg_soc {
vin-supply = <&sw1c_reg>;
};
&snvs_poweroff {
status = "okay";
};
&ssi2 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <8>;
cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
bus-width = <8>;
cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
bus-width = <8>;
non-removable;
no-1-8-v;
status = "okay";
};
&wdog1 {
status = "disabled";
};
&wdog2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};

View File

@@ -7,11 +7,11 @@
soc {
u-boot,dm-spl;
aips-bus@02000000 {
aips-bus@2000000 {
u-boot,dm-spl;
};
aips-bus@02100000 {
aips-bus@2100000 {
u-boot,dm-spl;
};
};

File diff suppressed because it is too large Load Diff

View File

@@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 NXP
*/
#include "imx6qdl-sabreauto-u-boot.dtsi"

View File

@@ -0,0 +1,55 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Copyright 2016 Freescale Semiconductor, Inc.
/dts-v1/;
#include "imx6qp.dtsi"
#include "imx6qdl-sabreauto.dtsi"
/ {
model = "Freescale i.MX6 Quad Plus SABRE Automotive Board";
compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp";
};
&i2c2 {
max7322: gpio@68 {
compatible = "maxim,max7322";
reg = <0x68>;
gpio-controller;
#gpio-cells = <2>;
};
};
&iomuxc {
imx6qdl-sabreauto {
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b018
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b018
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b018
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b018
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b018
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b018
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b018
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b018
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b018
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b018
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b018
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b018
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
};
};
&pcie {
status = "disabled";
};
&vgen3_reg {
regulator-always-on;
};

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