currently gpio hog function is not tested with "ut dm gpio"
so add some basic tests for gpio hog functionality.
For this enable GPIO_HOG in sandbox_defconfig, add
in DTS some gpio hog entries, and add testcase in
"ut dm gpio" command.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
- sbi: Add newline to error message
- fu540: dts: Correct reg size of otp and dmc nodes
- Enhance reserved memory fixup about PMP information passed from OpenSBI
- sifive: fu540: Add gpio-restart support
- qemu-riscv: Update QEMU run command
- Assorted fixes related to reserved memory
- fu540: enable all cache ways from U-Boot proper
- use log functions in fdt_fixup
Replace printf() and debug() by log_err() and log_debug().
"No reserved memory region found in source FDT\n" is not an error but a
debug information.
%s/can not/cannot/ - use the more common spelling.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
fdtdec_get_addr_size_no_parent is not an optimized version if parent
node is already available with the caller.
Use fdtdec_get_addr_size_auto_parent to read the "reg" property
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Not all errors are fatal. If a reserved memory node already exists in the
destination device tree, we can continue to boot without failing.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Explicitly pass the "-bios" option to QEMU to run U-Boot, instead
of the "-kernel" option, as we know that "-bios" behavior will be
changed since QEMU 5.1.0.
This also updates validated QEMU version to 5.0.0.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Starting from OpenSBI v0.7, the SBI firmware inserts/fixes up the
reserved memory node for PMP protected memory regions. All RISC-V
boards need to copy the reserved memory node from the device tree
provided by the firmware to the device tree used by U-Boot.
Turn on CONFIG_OF_BOARD_FIXUP by default for OF_SEPARATE.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Rick Chen <rick@andestech.com>
The copy of reserved memory node from source dtb to destination dtb
can be avoided if they point to the same place. This is useful when
OF_PRIOR_STAGE is used.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Pull request for UEFI sub-system for efi-2020-07-rc6 (2)
Fix an incorrect update of the GD register in efi_get_variable_common().
Fix an incorrect check for an FDT reg property.
Fix a device tree used for Python testing.
test_efi_fit tests fail on RISC-V currently. This is due to the
RISC-V arch_fixup_fdt() checks the #size-cells of the root node
in order to correctly fix up the reserved memory node.
Per the DT binding, the /reserved-memory node requires both
<#address-cells> and <#size-cells> and they should use the same
values as the root node. For the root node, it's not very useful
if <#size-cells> is zero.
Update #size-cells to 1 so tests can pass.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
With commit 0d7c2913fd ("cmd: bootefi: Honor the address & size cells
properties correctly") addr was replaced by fdt_addr. But not in the check
against FDT_ADDR_T_NONE.
Fixes: 0d7c2913fd ("cmd: bootefi: Honor the address & size cells properties
correctly")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
efi_get_variable_common() does not use EFI_ENTRY(). So we should not use
EFI_EXIT() either.
Fixes: 767f6eeb01 ("efi_loader: variable: support variable authentication")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
- fix logo on mx6ul_14x14_evk with DM_VIDEO enabled
- fix banner string overwriting the logo on small displays
- fix splash warning when building for ARM64
- fix STM32 DSI driver to probe only on supported hardware
- fix memory corruption with DSI panel drivers
The EDP_LCDC_SEL bit has to be set correctly to select vop0 or
vop1, but so far we have set it in both conditions, which is not
correct.
Can someone verify this is the correct way round? vop1 -> set,
vop0 -> clear?
Signed-off-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Fill characteristics of DSI data link to platform data instead of
mipi device to avoid memory corruption.
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Fill characteristics of DSI data link to platform data instead of
mipi device to avoid memory corruption.
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Copy the DSI data link characteristics from panel
platform data to mipi DSI device.
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Add new fields "lanes, format & mode_flags" to structure
mipi_dsi_panel_plat.
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Get below warning on ARM64 platform, because the bmp_load_addr
is defined to u32.
common/splash.c: In function ‘splash_video_logo_load’:
common/splash.c:74:9: warning: cast to pointer from integer
of different size [-Wint-to-pointer-cast]
74 | memcpy((void *)bmp_load_addr, bmp_logo_bitmap,
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # bpi-m1+, bpi-m64
The commit 84a6a27ae3 ("rockchip: rk3188: init CPU freq in clock
driver") changed ARM clock from 600MHz to 1600MHz. It made boot
unstable due to the fact that PMIC at the start generates insufficient
voltage for operation. See also: commit f4f57c58b5 ("rockchip:
rk3188: Setup the armclk in spl").
Fixes commit 84a6a27ae3 ("rockchip: rk3188: init CPU freq in clock
driver").
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Move the setting for noc remap out of SPL code. Changing
noc remap inside SPL results in breaking back to BROM
boot.
Fixes commit c14fe2a8e1 ("rockchip: rk3188: Move SoC
one time setting into arch_cpu_init()").
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Fix EMAC register address calculation, address need to multiply
with sizeof(u32) or 4.
This fixes write to invalid address.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Pull request for UEFI sub-system for efi-2020-07-rc6
Corrections for variable definitions are provided:
* Correct size of secure boot related UEFI variables.
* Do not use int for storing an enum.
* Replace fdt_addr by fdt_size where needed.
Since commit:
commit 6333cbb381
Author: Michael Walle <michael@walle.cc>
Date: Thu May 7 00:11:58 2020 +0200
phy: atheros: ar8035: remove static clock config
We can configure the clock output in the device tree. Disable the
hardcoded one in here. This is highly board-specific and should have
never been enabled in the PHY driver.
If bisecting shows that this commit breaks your board it probably
depends on the clock output of your Atheros AR8035 PHY. Please have a
look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set
"clk-out-frequency = <125000000>" because that value was the hardcoded
value until this commit.
Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
, the clock output setting for the AR803x driver is removed from being
hardcoded in the PHY driver and should be passed via device tree instead.
Update the device tree with the "qca,clk-out-frequency" property so that
Ethernet can work again.
Reported-by: Soeren Moch <smoch@web.de>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Soeren Moch <smoch@web.de>
The variables SetupMode, AuditMode, DeployedMode are explicitly defined as
UINT8 in the UEFI specification. The type of SecureBoot is UINT8 in EDK2.
Use variable name secure_boot instead of sec_boot for the value of the
UEFI variable SecureBoot.
Avoid abbreviations in function descriptions.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Variable efi_secure_mode is meant to hold a value of enum efi_secure_mode.
So it should not be defined as int but as enum efi_secure_mode.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Variable fdt_size should be of type 'fdt_size_t', not 'fdt_addr_t'.
Fixes 0d7c2913fd: ("cmd: bootefi: Honor the address & size cells properties correctly")
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
SDHCI HISPD bits need to be configured based on desired mmc
timings mode and some HISPD quirks.
So, handle the HISPD bit based on the mmc computed selected
mode(timing parameter) rather than fixed mmc card clock
frequency.
Linux handle the HISPD similar like this in below commit but no
SDHCI_QUIRK_BROKEN_HISPD_MODE,
commit <501639bf2173> ("mmc: sdhci: fix SDHCI_QUIRK_NO_HISPD_BIT handling")
This eventually fixed the mmc write issue observed in
rk3399 sdhci controller.
Bug log for refernece,
=> gpt write mmc 0 $partitions
Writing GPT: mmc write failed
** Can't write to device 0 **
** Can't write to device 0 **
error!
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Peng Fan <peng.fan@nxp.com>
Peng Fan: added back "ctrl &= ~SDHCI_CTRL_HISPD;" per Jaehoon's suggestion
Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> # roc-rk3399-pc
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
According to eMMC specification v5.1 section 6.4.3, we should issue
CMD1 repeatedly in the idle state until the eMMC is ready even if
mmc_send_op_cond() send CMD1 with argument = 0. Otherwise some eMMC
devices seems to enter the inactive mode after mmc_complete_op_cond()
issued CMD0 when the eMMC device is busy.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
In current code, we add 1ms dealy after each tuning command for standard
tuning method. Adding this 1ms dealy is because USDHC default check the
CMD CRC and DATA line. If detect the CMD CRC, USDHC standard tuning
IC logic do not wait for the tuning data sending out by the card, trigger
the buffer read ready interrupt immediately, and step to next cycle. So
when next time the new tuning command send out by USDHC, card may still
not send out the tuning data of the upper command，then some eMMC cards
may stuck, can't response to any command, block the whole tuning procedure.
If do not check the CMD CRC for tuning, then do not has this issue. USDHC
will wait for the tuning data of each tuning command and check them. If the
tuning data pass the check, it also means the CMD line also okay for tuning.
So this patch disable the CMD CRC check for tuning, save some time for the
whole tuning procedure.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
According the RM, the bit[6~0] of register ESDHC_TUNING_CTRL is
TUNING_START_TAP, bit[7] of this register is to disable the command
CRC check for standard tuning. So fix it here.
Fixes: fa33d20749 ("mmc: split fsl_esdhc driver for i.MX")
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
The extcsd read target must be cache aligned in case the controller
uses DMA to read the extcsd register, make it so.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
This patch try to avoids eviction of dirty lines during DMA
transfer. The code right now execute the following step:
- allocate the buffer
- start a dma operation using the non-coherent dma buffer
- invalidate cache lines associated with the buffer
- read the buffer
This can lead to reading back not valid information, because the cache
controller could evict dirty cache lines belonging to the buffer *after*
the DMA operation has started to fill the DRAM.
In order to avoid this, a new invalidation is required *before* starting
the DMA operation. The patch just adds an invalidation before submitting
the DMA command.
Example below shows the nvme disk scan result without the following
patch
=> nvme scan
nvme_get_info_from_identify: nn = 544502629, vwc = 100,
sn = dev_0T, mn = `�\�, fr = t_part, mdts = 105
So, invalidating the cache before submitting the admin command,
fix the cpu read.
Cc: André Przywara <andre.przywara@arm.com>
Reported-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Suniel Mahesh <sunil@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The correct name for the property is "qca,clk-out-frequency", so fix
it accordingly.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Michael Walle <michael@walle.cc>
Commit 0528979fa7 ("part: Drop disk_partition_t typedef") changed to
a struct. As a result it uncovered an apparent missing include in
zfs_common.h for part.h which actually contains the definition. The ZFS
handles the struct exclusively as pointers so it was only a warning.
warning: ‘struct disk_partition’ declared inside parameter list
will not be visible outside of this definition or declaration
void zfs_set_blk_dev(struct blk_desc *rbdd, struct disk_partition *info);
Signed-off-by: Joel Johnson <mrjoel@lixil.net>
Series-CC: Simon Glass <sjg@chromium.org>
After enabling SPL_OF_CONTROL, SPL_DM and SPL_DM_MMC the MMC
initialization code is not longer needed.
This patch removes the unused code.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
In order to take the beneficts of DT and DM in SPL, like reusing the code
and avoid redundancy, enable SPL_OF_CONTROL, SPL_DM and SPL_DM_MMC.
With this new configuration SPL image is 50 KB, higher than the
38 KB from the previous version, but it still under the 68 KB limit.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
In SPL legacy code only one MMC device is created, based on BOOT_CFG
register, which can be either SD or eMMC. In this context
board_boot_order return always MMC1 when configure to boot from
SD/eMMC. After switching to DM both SD and eMMC devices are created
based on the information available on DT, but as board_boot_order
only returns MMC1 is not possible to boot from eMMC.
This patch customizes board_boot_order taking into account BOOT_CFG
register to point to correct MMC1 / MMC2 device. Additionally, handle
IO mux for the desired boot device.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Current aliases missed gpio0 node, and this node shoud be
aliased to gpio index 0 to align with i.MX8QXP. Otherwise, we
will get below message when running "gpio status" command, and
see the reason by "dm uclass".
=> gpio status
Device 'gpio@5d090000': seq 0 is in use by 'gpio@5d080000'
Device 'gpio@5d0a0000': seq 1 is in use by 'gpio@5d090000'
Device 'gpio@5d0b0000': seq 2 is in use by 'gpio@5d0a0000'
=> dm uclass
uclass 36: gpio
0 * gpio@5d080000 @ fbaefb90, seq 0, (req -1)
1 * gpio@5d090000 @ fbaefc70, seq 1, (req 0)
2 * gpio@5d0a0000 @ fbaefd50, seq 2, (req 1)
3 * gpio@5d0b0000 @ fbaefe30, seq 5, (req 2)
4 * gpio@5d0c0000 @ fbaeff10, seq 3, (req 3)
5 * gpio@5d0d0000 @ fbaefff0, seq 4, (req 4)
6 * gpio@5d0e0000 @ fbaf00d0, seq 6, (req 5)
7 * gpio@5d0f0000 @ fbaf01b0, seq 7, (req 6)
Signed-off-by: Ye Li <ye.li@nxp.com>
Since the i.MX8 GPIO banks are indexed from 0 not 1 on other i.MX
platforms, so we have to adjust the index accordingly.
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
We need to change the environment offset to avoid corrupting the U-Boot
binary when saving it.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
This fixes the boot from USB loader, which is critical to easy the
manufacture process.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Select default U-Boot and SPL text base for the MX7 SoC. The U-Boot
text base is picked as the one used by various MX7 boards. The SPL
text base however is different.
The SPL text base is set to 0x912000 instead of the usual 0x911000,
that is because the 0x911000 value cannot work. Using 0x911000 as a
SPL text base will result in the DCD header being placed below the
0x911000 address, which is a reserved SRAM area which must not be
used. This will actually trigger eMMC boot failure on MX7D at least.
Hence the increment.
Update all boards affected by this SPL problem to the new SPL_TEXT_BASE.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
There are systems where board_early_init_f() is plain empty. Switch
the config option from "select" to "imply", to permit user to unset
the BOARD_EARLY_INIT_F if it were to be empty.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
The iMX7 defines further DDRC ZQCTLx registers, however those were
thus far missing from the list of registers and not programmed. On
systems with LPDDR2 or DDR3, those registers must be programmed with
correct values, otherwise the DRAM may not work. However, existing
systems which worked without programming these registers before are
now setting those registers to 0, which is the default value, so no
functional change there.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
This is needed to obtain the MAC from EEPROM/OTP only after the final
env is populated, otherwise the ethaddr might be overriden.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Claudius Heine <ch@denx.de>
Cc: Harald Seiler <hws@denx.de>
Cc: Ludwig Zenz <lzenz@dh-electronics.com>
Cc: Stefano Babic <sbabic@denx.de>
For using a debug UART on the Wandboard CONFIG_MXC_UART=y must be set in
the .config file.
To avoid duplicate definitions move the setting from
include/configs/wandboard.h to configs/wandboard_defconfig.
Document the debug UART settings in the README.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
It appears that MMC access on the Sabrelite has been broken since
cdcaee9518:
Loading Environment from MMC... Card did not respond to voltage select!
*** Warning - No block device, using default environment
Remove the board_mmc_init() and related entries now that we should be
using DM_MMC, add PINCTRL so that things work as expected.
Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Troy Kisky <troy.kisky@boundarydevices.com>
1. Drop legacy emmcboot wrapper from env.
2. Change the "boot try" order. Default one is: SD -> eMMC -> USB -> DHCP
3. Drop DFU defines
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
1. Drop legacy emmcboot wrapper from env.
2. Change the "boot try" order. Default one is: SD -> eMMC -> USB -> DHCP
3. Drop DFU defines
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
1. Drop legacy emmcboot wrapper from env.
2. Change the "boot try" order. Default one is: SD -> eMMC -> USB -> DHCP
3. Drop DFU defines
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
This introduces automatic boot counter that increases after every
reset.After a power-on reset, it will be initialized with 1,
and each reboot will increment the value by 1. By default it's
disabled if bootlimit isn't set.
To enable this feature you have set bootcount limit ("bootlimit"),
alternate boot action ("altbootcmd") that will be performed if
the new value of bootcount exceeds the value of bootlimit, and
"upgrade_available" to let U-Boot automatically increase and save
the counter value after every reset:
> setenv bootlimit 5
> setenv upgrade_available 1
> setenv altbootcmd "bootm ..."
In case the bootlimit exceeds, the message will be shown and
albootcmd executed:
Warning: Bootlimit (5) exceeded. Using altbootcmd.
To reset bootcount run:
> bootcount reset
Print current value:
> bootcount print
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
s/fdt-module/fdt_module/g, as we don't use dash in fdt_file anymore.
Fixes: 4c63a601("apalis-tk1: support v1.2 hardware revision")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
1. Use distro_bootcmd as default boot command instead of
legacy emmcboot wrapper.
2. Drop emmcboot and sdboot wrappers.
3. Provide proper boot order for Distro Boot.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
The distro bootscript uses kernel_image to get the file name of
the kernel, so change that variable name.
UBI boot has precedence in the default boot command. If one wants
to boot from SD with a working NAND installation stop in U-Boot
and enter:
setenv fdtfile ${soc}-colibri-${fdt_board}.dtb && run distro_bootcmd
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
When using distro boot to boot from UBI volumes the boot partition
has been hardcoded to "UBI" (capital letters). However, our default
MTD layout uses "ubi" (lower case letter). Define "ubi" as the
default UBI partition for distro boot for Toradex. This allows to
use distro boot without having to redefine the MTD partition layout
which is useful for TorizonCore.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
This got dropped by a global 'make savedefconfig' resync as
required patches are still in flight.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
As per kernel commit 0672d22a1924 ("ARM: dts: imx: Fix the AR803X phy-mode)
the correct phy-mode should be "rgmii-id", so fix it accordingly
to fix the Ethernet regression.
This problem has been exposed by commit:
commit 13114f38e2
Author: Vladimir Oltean <vladimir.oltean@nxp.com>
Date: Thu May 7 00:11:51 2020 +0200
phy: atheros: Explicitly disable RGMII delays
To eliminate any doubts about the out-of-reset value of the PHY, that
the driver previously relied on.
If bisecting shows that this commit breaks your board you probably have
a wrong PHY interface mode. You probably want the
PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
As per kernel commit 0672d22a1924 ("ARM: dts: imx: Fix the AR803X phy-mode)
the correct phy-mode should be "rgmii-id", so fix it accordingly
to fix the Ethernet regression.
This problem has been exposed by commit:
commit 13114f38e2
Author: Vladimir Oltean <vladimir.oltean@nxp.com>
Date: Thu May 7 00:11:51 2020 +0200
phy: atheros: Explicitly disable RGMII delays
To eliminate any doubts about the out-of-reset value of the PHY, that
the driver previously relied on.
If bisecting shows that this commit breaks your board you probably have
a wrong PHY interface mode. You probably want the
PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Fix the phy-mode accordingly to fix the regression.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Migration to DM_ETH is mandatory, so convert mx6cuboxi to Ethernet
Driver Model.
This also brings the benefit of restoring Ethernet functionality.
Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Tom Rini <trini@konsulko.com>
Sync the device tree with 5.8-rc1.
It basically contains the following extra kernel commit:
commit 86b08bd5b99480b79a25343f24c1b8c4ddcb5c09
Author: Russell King <rmk+kernel@armlinux.org.uk>
Date: Wed Apr 15 16:44:17 2020 +0100
ARM: dts: imx6-sr-som: add ethernet PHY configuration
Add ethernet PHY configuration ahead of removing the quirk that
configures the clocking mode for the PHY. The RGMII delay is
already set correctly.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
, which passes the 'qca,clk-out-frequency' property and it is important
to specify the correct frequency generated by the AR8035.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Tom Rini <trini@konsulko.com>
As we move towards driver model, it is required to let the FEC driver
know how to properly deal with an Ethernet PHY subnode in the device tree.
For example:
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
phy-handle = <&phy>;
phy-mode = "rgmii-id";
phy-reset-duration = <2>;
phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy: ethernet-phy@0 {
reg = <0>;
qca,clk-out-frequency = <125000000>;
};
};
};
Currently the PHY node pointer is incorrectly associated with the
Ethernel controller instead of the PHY node itself.
This causes the PHY properties, such as "qca,clk-out-frequency" in
the example above to not get parsed.
Fix this problem by populating the phy_of_node node.
Suggested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Tom Rini <trini@konsulko.com>
The clock ouput frequency is calculated incorrectly for AR8035 due to
wrong masking of priv->clk_25m_reg and priv->clk_25m_mask.
This same issue has been already fixed in the kernel by:
commit b1f4c209d84057b6d40b939b6e4404854271d797
Author: Oleksij Rempel <o.rempel@pengutronix.de>
Date: Wed Apr 1 11:57:32 2020 +0200
net: phy: at803x: fix clock sink configuration on ATH8030 and ATH8035
The masks in priv->clk_25m_reg and priv->clk_25m_mask are one-bits-set
for the values that comprise the fields, not zero-bits-set.
This patch fixes the clock frequency configuration for ATH8030 and
ATH8035 Atheros PHYs by removing the erroneous "~".
To reproduce this bug, configure the PHY with the device tree binding
"qca,clk-out-frequency" and remove the machine specific PHY fixups.
Fixes: 2f664823a47021 ("net: phy: at803x: add device tree binding")
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Reported-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk>
Tested-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
Apply the same fix in the U-Boot driver.
Tested on a i.MX6 Hummingboard.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Michael Walle <michael@walle.cc>
Tested-by: Tom Rini <trini@konsulko.com>
The cd-gpios with (GPIO_ACTIVE_LOW | GPIO_PULL_UP) gpio is thus far
unsupported, reinstate the old cd-gpios behavior until this handling
is fully implemented. This avoid potential issue for SDCard boot:
the card detect fails with floating gpio.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
The cd-gpios with (GPIO_ACTIVE_LOW | GPIO_PULL_UP) gpio is thus far
unsupported, reinstate the old cd-gpios behavior until this handling
is fully implemented. This permits the DHSOM to boot from SD again,
without this patch the card detect fails.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
fdtdec_get_addr_size reads the uses a fixed value for address & size
cell properties which may not be correct always.
Use the auto variant of the function which automatically reads
#address-cells & #size-cells from parent and uses to read the "reg"
property.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
On 32 bit systems fdt_addr_t may be 4 bytes long but size is defined as
u64. Avoid filling the upper 4 bytes of the sizep parameter of
fdtdec_get_addr_size_auto_parent() with random bytes from the stack by
defining a separate variable fdt_size.
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
This allows Nano to use the key M.2 on the CVB to connect and use a M.2
NVMe SSD stick. Works on my Nano B00, WD SN750 NVMe SSD shows up
w/'nvme' commands. Will add booting from NVMe via distro cmds in a future
patch.
Signed-off-by: Tom Warren <twarren@nvidia.com>
The PSCI nodes are currently not populated for the Tegra210 and Tegra186
devices. This prevents the PSCI driver from being able to identify the
PSCI method used by these devices and causes the probe of the PSCI
driver to fail.
Since commit 81ea00838c ("efi_loader: PSCI reset and shutdown") was
added, which moves the PSCI EFI system reset handler into the PSCI
driver, this has prevented the EFI system reset from working for
Tegra210 and Tegra186. Therefore, populating these nodes is necessary
to fix the EFI system reset for Tegra210 and Tegra186.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
When CONFIG_OF_LIVE is enabled, dev_of_offset() cannot be used and
if used returns an invalid offset. This causes the call to
fdt_stringlist_get() in the psci_probe() to fail to read the 'method'
property from the PSCI node for the device and hence prevents PSCI
from working. Fix this by using the ofnode_read_string() API instead
of the fdt_stringlist_get() because this will handle reading the
property both when CONFIG_OF_LIVE is enabled or disabled.
Due to the above problem and since commit 81ea00838c ("efi_loader:
PSCI reset and shutdown") was added, the EFI system reset has been
broken for Tegra210 and Tegra196 platforms. This also fixes the EFI
system reset for these Tegra platforms.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
The ethernet PHY on all known Gen3 boards takes a while to come out
of reset, increase the auto-negotiation timeout to prevent it from
timing out in case the ethernet is used right after the board was
reset.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
After migration to DM 'vga' name is not longer supported,
change it to 'vidconsole' in the default environment.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Igor Opaniuk <igor.opaniuk@toradex.com>
After migration to DM 'vga' name is not longer supported,
change it to 'vidconsole' in the default environment.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Igor Opaniuk <igor.opaniuk@toradex.com>
After migration to DM 'vga' name is not longer supported,
change it to 'vidconsole' in the default environment.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Add the recently added reStructuredText board documentation in the
appropriate MAINTAINERS files.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Move the natural text Amlogic board README files to doc/board/amlogic
into reStructuredText and :
- add reStructuredText markup for bash code
- fix secondary titles markup
- move board support into global support matrix
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add OP-TEE firmware node in stm32mp15 U-Boot DTSI. This node is
needed since commit [1] that changed U-Boot/stm32mp15 to detect
OP-TEE availability by probing the resource instead of relying on
U-Boot configuration. The software sequence implemented by [1] is
fine but U-Boot DTS/DTSI files were not updated accordingly since,
hence OP-TEE presence is never detected by U-Boot, preventing Linux
kernel from using OP-TEE resources.
For consistency and to synchronize stm32mp15 DTSI files (excluding
U-Boot specific DTSI files) with the Linux kernel ones, this change
also moves the OP-TEE reserved memory nodes from board generic DTSI
files to U-Boot specific board DTSI files.
Link: [1] commit 43df0a159d ("stm32mp1: dynamically detect op-tee presence")
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Fix the sequence in stm32mp1 fdt.c that disables OP-TEE resources
defined in FDT when U-boot detects OP-TEE firmware is not present.
Before this change, helper function stm32_fdt_disable_optee()
set property status to "disabled" for the OP-TEE reserved memory
nodes but this has no impact since Linux kernel does not consider
the status property for reserved-memory subnodes. This change
make U-Boot to attempt to delete the node instead.
Fixes: 4a1b975dac ("board: stm32mp1: reserve memory for OP-TEE in device tree")
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
The fix in commit b7adcdd073 has the side-effect that the regulator
will be disabled when requesting the relevant gpio in
regulator_common_ofdata_to_platdata() and enabled in
regulator_pre_probe() when the regulator was already enabled.
This leads to a short interruption in the 3.3V power to the PCIe
slot on the firefly-rk3399 which makes an ADATA SX8000NP NVMe SSD
unhappy.
Fix this by setting the GPIOD_IS_OUT_ACTIVE flag again when the
'regulator-boot-on' property is set, but check for this property
explicitly instead of relying on the "boot_on" member of
the uclass platdata.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Tested-by: Patrice Chotard <patrice.chotard@st.com>
Update the comment for SYS_RELOC_GD_ENV_ADDR as gd->env_addr is updated
in board_r.c::initr_reloc_global_data() under the compilation flags
CONFIG_SYS_RELOC_GD_ENV_ADDR
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Several configutation options require additional memory before relocation:
* CONSOLE_RECORD
* LOG
* RSA
The current default of 0x400 is too small to encompass them all. Increase
the value of SYS_MALLOC_F_LEN to 0x2000 for ARCH_QEMU.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
This reverts commit 0486497e2b.
The strtoul has well-defined semantics. It is defined by the C standard and
POSIX. To quote the relevant section of the man pages,
> If base is zero or 16, the string may then include a "0x" prefix, and the
> number will be read in base 16; otherwise, a zero base is taken as 10
> (decimal) unless the next character is '0', in which case it is taken as
> 8 (octal).
Keeping these semantics is important for several reasons. First, it is very
surprising for standard library functions to behave differently than usual.
Every other implementation of strtoul has different semantics than the
implementation in U-Boot at the moment. Second, it can result in very
surprising results from small changes. For example, changing the string
"1f" to "20" causes the parsed value to *decrease*. Forcing use of the "0x"
prefix to specify hexidecimal numbers is a feature, not a bug. Lastly, this
is slightly less performant, since the entire number is parsed twice.
This fixes the str_simple_strtoul test failing with
test/str_ut.c:29, run_strtoul(): expect_val == val: Expected 0x44b (1099), got 0x1099ab (1087915)
test/str_ut.c:46, str_simple_strtoul(): 0 == run_strtoul(uts, str2, 0, 1099, 4): Expected 0x0 (0), got 0x1 (1)
Signed-off-by: Sean Anderson <seanga2@gmail.com>
CC: Michal Simek <michal.simek@xilinx.com>
CC: Shiril Tichkule <shirilt@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
s/booot/boot/g
The first ase is booot instead of boot and second u-booot instead of
u-boot.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Fix the loop that parses FDT for a reserved memory node named "optee".
Before this change, if at least one subnode was found in the
reserved-memory node, the function endlessly looped since instruction
continue returned back in the loop without updating variable subnode.
This change fixes the issue by using a for loop.
Fixes: 6ccb05eae0 ("image: fdt: copy possible optee nodes to a loaded devicetree")
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Unsupported voltage on voltage switch is not an error, do not
print error message in such a case. This happens e.g. if the
eMMC is already in 1V8 mode or when testing 1V2 mode operation
on systems which only do 3V3/1V8 switching.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
The 3V3/1V8 switching could never have worked on any of the iMXes
ever since 51313b49f2 ("mmc: fsl_esdhc: support SDR104 and HS200"),
because that commit uses priv->vqmmc_dev when switching voltages on
mode switch, while local vqmmc_dev in probe to store the regulator
pointer. Those are two different variables with the same name. So
the priv->vqmmc_dev was always NULL and thus voltage switch between
modes never really suceeded.
Fix this by assigning priv->vqmmc_dev with value of the vqmmc_dev
in probe.
Fixes: 51313b49f2 ("mmc: fsl_esdhc: support SDR104 and HS200")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
When eSDHC operates at 3.3v, damage can accumulate in an internal
level shifter at a higher than expected rate. The faster the interface
runs, the more damage accumulates. This issue now is found on LX2160A
eSDHC1 for only SD card.
The hardware workaround is recommended to use an on-board level shifter
that is 1.8v on SoC side and 3.3v on SD card side.
For boards without hardware workaround, this option could be enabled,
ensuring 1.8v IO voltage and disabling eSDHC if no card.
This option assumes no hotplug, and u-boot has to make all the way to
to linux to use 1.8v UHS-I speed mode if has card.
If you do not want the workaround for better user experience, of course
you can choose to not select it running eSDHC in unsafe mode.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
For size_t we have to use %zu for printing not %lu.
Fixes: 4540dabdca ("efi_loader: image_loader: support image
authentication")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Commit e71b6f6622 ("i2c: designware_i2c: Rewrite timing calculation")
change the hcnt and lcnt timing calculation. New timing calculation is
based on calculation from Designware i2c databook.
After this new timing calculation, hcnt will have negative value
with i2c-scl-falling-time-ns 5000 that set in socfpga_cyclone5_socdk.dts.
This patch overwrite i2c-scl-falling-time-ns to 300ns (default SCL fall
time used in Designware i2c driver) for Uboot.
Before the fix:
=> i2c dev 0
Setting bus to 0
Failure changing bus number (-22)
After the fix:
=> i2c dev 0
Setting bus to 0
=> i2c probe
Valid chip addresses: 17 51 55 5B 5C 5E 66 68 70
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Update the firmware to improve compatibility for none-intel USB
host controller. The more information is as following.
The device has auto-installed driver feature - via switch CD-ROM/NIC
mode. But in some corner cases, it would switch to CD-ROM unexpected.
This issue results in Lan Function Disabled.
While USB PHY transits to P3 from P0 due to the absent of transmitter
control, it would issues undefined signal to its link partner.
Some Down Stream Port misidentify the undefined signal as wakeup
signal. So the link state will not keep in suspend even the system
is idle.
Signed-off-by: Hayes Wang <hayeswang@realtek.com>
OF_CONTROL, DM_SPI and other driver model migration deadlines
are expired for this board.
Remove it.
Acked-by: Lars Poeschel <poeschel@lemonage.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
OF_CONTROL, DM_SPI and other driver model migration deadlines
are expired for this board.
Remove it.
Acked-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
This would make SPL build to DM_SPL, SPL_OF_CONTROL.
Build fine with but not tested.
Cc: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
atmel_spi.h has register offsets, and atmel_spi_slave
structure, move it into .c file for better readability
and drop atmel_spi.h
Cc: Wenyou Yang <wenyou.yang@atmel.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
- Deadline for DM migration already passed by months.
- Sent couple of zap patches and
- No response on dm conversation
hence removed the driver.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Order the macros, private structures and simple functions
in a proper way to have more code readability.
No functionality changed.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Deadline for DM migration already passed by months
and no response on full dm conversation hence removed
the nondm code.
Note: Look like there is no user for nondm code
for this driver.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
This reverts commit 1f63ee6566.
As reported by Ye Li on ML:
1. Removing the image_offset will break secondary (redundant) boot support for sd and emmc.
2. When booting from emmc boot partition, the image_offset is 0. But the flash.bin
generated by mkimage with imximage-8mp-lpddr4.cfg is for sd. It expects to be burn at 32KB offset.
The fit offset 0x60000 has already included the 32KB offset. So when you burn this flash.bin
to emmc boot partition at offset 0, the fit offset should subtract the 32KB (0x60000 - 0x8000).
Signed-off-by: Stefano Babic <sbabic@denx.de>
This displays incorrect data at present due to a missing header file
in display_options. Fix it.
Fixes: 0914011310 ("command: Remove the cmd_tbl_t typedef")
Signed-off-by: Simon Glass <sjg@chromium.org>
Convert the board to DM_ETH instead of legacy networking. This requires
a minor addition to the DT to satisfy the requirement for specifying a
PHY node. No functional change from board user perspective.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
None of these splash screen loading errors are so critical as to
justify complete failure to boot, so just print error message as
needed and return 0, the boot can very likely continue without
the splash.
Fix a couple of missing free(dst) instances as well.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
The iMX7D RM 9.2.4.9.3 Power removal flow Table 9-11. Re-enabling power
explicitly says both the DDR controller and the PHY must be reset in the
correct sequence. Currently the code only resets the controller. This
leads to a misbehavior where the system brings the DRAM up after reboot,
but the DRAM is unstable. Add the missing reset.
The easiest way to trigger this is by triggering WDT without having the
WDT assert WDOG_B signal, i.e. mw.w 0x30280000 0x25 .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
The u-boot-spl.bin pad with ddr firmware conflicts with the
CONFIG_MALLOC_F_ADDR area, the ddr firmware will be overwritten
by malloc in SPL stage and cause ddr initialization not able
to finish. So update the related addresses to fix the issue.
Reported-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
We no need invoke the code, since spl framework could help
us do that.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Use spl_early_init to replace spl_init, spl_init will be invoked
in board_init_r, we only need use spl_early_init to setup malloc
and scan early dt.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
timer_init has been invoked in arch_cpu_init, no need to invoke
it again in board code.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Drop useless getting ccm device, there is no need to explicted do this
in board code, and we not enable SPL CLK currently.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
When not booting from FlexSPI, the offset computation is:
offset = image_offset + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8000;
When booting from SD card or eMMC user partition, image_offset is
0x8000. It is useless to add and remove 0x8000.
When booting from other device, image_offset is 0 so this computation is wrong.
Simplfy this computation to work on all booting devices.
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Currently watchdog driver is not selected, which causes system to reboot
after staying 60s in the U-Boot prompt.
Fix this problem by enabling CONFIG_WATCHDOG so that watchdog can be
properly serviced.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Currently watchdog driver is not selected, which causes system to reboot
after staying 60s in the U-Boot prompt.
Fix this problem by enabling CONFIG_WATCHDOG so that watchdog can be
properly serviced.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Currently watchdog driver is not selected, which causes system to reboot
after staying 60s in the U-Boot prompt.
Fix this problem by enabling CONFIG_WATCHDOG so that watchdog can be
properly serviced.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Adam Ford <aford173@gmail.com>
Currently watchdog driver is not selected, which causes system to reboot
after staying 60s in the U-Boot prompt.
Fix this problem by enabling CONFIG_WATCHDOG so that watchdog can be
properly serviced.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Currently the watchdog driver is not selected, which causes the following
warnings in both SPL and U-Boot proper:
U-Boot SPL 2020.07-rc1-00387-g67887903af (May 07 2020 - 23:49:27 -0300)
Normal Boot
WDT: Started without servicing (60s timeout)
Trying to boot from MMC1
U-Boot 2020.07-rc1-00387-g67887903af (May 07 2020 - 23:49:27 -0300)
CPU: Freescale i.MX8MMQ rev1.0 at 1200 MHz
Reset cause: POR
Model: FSL i.MX8MM EVK board
DRAM: 2 GiB
WDT: Started without servicing (60s timeout)
....
System reboots after staying 60s in the U-Boot prompt.
Fix this problem by enabling CONFIG_WATCHDOG so that watchdog can be
properly serviced.
Suggested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
With yModem the FIT Image is only supplied once, so we can only
seek forward in the yModem supplied image and never backwards.
With the recent changes to the SPL mechanism, including loading
U-Boot first, FDT after, then the loadables, we must also reorder
the FIT image script to make sure that the loadables are last in
the FIT image.
Signed-off-by: Patrick Wildt <patrick@blueri.se>
Tested-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Enable CONFIG_PCI and CONFIG_NVME and related configs for the
Pinebook Pro.
Signed-off-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
With the current usb stack in u-boot, all host ports on puma work
flawlessly without any additional special handling, so drop that
usb hub hacking from the puma board.
Tested with mass-storage and usb-ethernet on both usb3 and usb2 ports.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The introduction of the puma-specific generator was mainly a way
to split the pmu firmware from the ATF binary and not having to
distribute that 4GB (sparse) image that was created before moving
to the bl31.elf as base.
Looking at the publically available repository for that separate
pmu firmware
https://git.theobroma-systems.com/rk3399-cortex-m0.git/
there is also no activity for 3 years and apart from some build
customizations no other changes were done.
And even then, if changes need to be made, this can very well also
happen in the atf context itself, so there is no real need to
diverge from the established build procedure and we can just go
back to using the main make_fit_atf.py script.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
So far the puma dts files only just included the main puma dtsi without
handling the actual baseboard and rk3399-puma.dtsi was very much
detached from the variant in the mainline Linux kernel.
Recent changes resulted in a strange situation with nonworking puma boards.
Commit ab800e5a6f ("arm: dts: rockchip: puma: move U-Boot specific bits to u-boot.dtsi")
moved the sdram include from rk3399-puma-ddrX.dts to new files
rk3399-puma-ddrx-u-boot.dtsi which were never included anywhere though.
Commit 167efc2c7a ("arm64: dts: rk3399: Sync v5.7-rc1 from Linux")
replaced the rk3399-puma.dtsi nearly completely, but in the kernel
it definitly depends on a baseboard dts to actually enable peripherals
like sd-slot, uarts, etc.
So to untagle this and bring the whole thing more in line with mainline
Linux, bring the rk3399-puma-haikou.dts over as well, drop the separate
DDR-option devicetrees and instead replace them with a puma Kconfig option
to select and include the needed DDR variant.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Mark the default U-Boot environment as SPI flash since
this is an on board flash device.
Updated env offset, size in contrast with default since
the U-Boot proper has to start from 384K.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
On rockchip platforms, SPI boot image creation is not
straightforward like MMC boot image creation where former
requires to specify tpl, spl in multimage format in mkimage,
and later simply do a concatenate mkimaged-tpl with spl.
On this note, let drop rkspi image type creation via kbuild
and let inform via rockchip.rst
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The 'stdout-path' is missing after dts sync.
Fixes: 167efc2c7a ("arm64: dts: rk3399: Sync v5.7-rc1 from Linux")
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
The ROCK-PI-E is a credit card size SBC based on Rockchip RK3328
Quad-Core ARM Cortex A53.
Net - Dual ethernet port, 1 X Gbe, 1 X 100M
USB - USB 3.0
DC - USB-Type C, 5V 2A
Storage - TF card, eMMC
Just build idbloader.img and u-boot.itb for Rockpi E board and
follow the blow steps to replace the relevant partition.
dd if=idbloader.img of=/dev/sdcard seek=64 conv=notrunc
dd if=u-boot.itb of=/dev/sdcard seek=16384 conv=notrunc
Signed-off-by: Banglang Huang <banglang.huang@foxmail.com>
Enable CONFIG_PCI and CONFIG_NVME and related configs for the
ROCKPro64 board.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Pull request for UEFI sub-system for efi-2020-07-rc4 (2)
The following problems are resolved:
* When booting via UEFI an SMBIOS table is presented to the operating
system. If U-Boot tries to add an empty string, this results in corrupted
SMBIOS information. We will now use "Unknown" as property value.
* The EFI_RNG_PROTOCOL uses the DM_RNG drivers. For the virtio RNG driver
the missing DM_RNG Kconfig dependency is added.
* Missing function descriptions for the EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL are
added.
Add the missing Kconfig dependency and let VIRTIO_RNG default to yes.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
smbios_add_string() cannot deal with empty strings. This leads to incorrect
property values and invalid tables. E.g. for the pine64-lts_defconfig
CONFIG_SMBIOS_MANUFACTURER="". Linux command dmidecode shows:
Table 1:
Manufacturer: sunxi
Product Name: sunxi
Table 3:
Invalid entry length (2). DMI table is broken! Stop.
Replace empty strings by "Unknown".
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
- Resync checkpatch.pl (largely) with v5.7 and introduce U-Boot specific
checks in a localized area, so they aren't lost in the future.
- Complete / re-migrate some options from config headers to defconfigs
- Add dependencies to the various debug uart drivers
All of our cmds have a Kconfig entry. Making enabling a CMD via the
config file an error to checkpatch.pl.
Signed-off-by: Tom Rini <trini@konsulko.com>
There is a lot of use of #ifdefs in U-Boot. In an effort reduce this,
suggest using the compile-time construct.
Signed-off-by: Simon Glass <sjg@chromium.org>
A common problem when submitting a new uclass is to forget to add sandbox
tests. Add a warning for this.
Of course tests should always be added for new code, but this one seems to
be missed by nearly every new contributor.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add an option to indicate that U-Boot-specific checks should be enabled.
Add a function to house the code that will be added.
Signed-off-by: Simon Glass <sjg@chromium.org>
Keep the U-Boot changes to $logFunctions
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Resync with v5.7 release which changed the default max line
length, update commit to reflect]
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_BZIP2
CONFIG_GZIP
CONFIG_LZO
CONFIG_ZLIB
CONFIG_LZMA
CONFIG_LZO
Signed-off-by: Tom Rini <trini@konsulko.com>
Per the boards config header file, there is no useful GPIO on these
boards. Remove CONFIG_CMD_GPIO from the defconfigs.
Cc: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Tom Rini <trini@konsulko.com>
The config header for this platform disables both CMD_SF and CMD_SPI and
the defconfig leaves them enabled. Disable them from the defconfig and
enable them in the header.
Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masakazu Mochizuki <masakazu.mochizuki.wd@hitachi.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
The common config header for bcm7260 and bcm7445 enable
CONFIG_CMD_EXT2/EXT4 but the defconfigs do not. This results in the
commands being disabled. Enable them via the defconfig.
Cc: Thomas Fitzsimmons <fitzsim@fitzsim.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
The config header for this platform uses '#undef' in a number of cases.
All of the MMC related ones were already handled correctly in the
defconfig file. In the case of CONFIG_CMD_FUSE, the command was being
built and enabled via defconfig. Disable it in the defconfig, cleanup
the header.
Reviewed-by: Eric Nelson <eric@nelint.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Rather than only enable CONFIG_CMD_NAND for non-SPL builds, move the CMD
options to defconfig and rework the guards to not try and call the
function in SPL builds.
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Debug console is the part of serial driver in the same file. It means to be
able to enable debug console you also need to enable driver itself.
That's why add all dependecies and list only debug consoles which are
enabled based on driver selection to avoid compilation error when user
asks for certain debug console but driver is not enable for it.
Error:
aarch64-linux-gnu-ld.bfd: common/built-in.o: in function `putc':
/home/monstr/data/disk/u-boot/common/console.c:513: undefined reference to `printch'
aarch64-linux-gnu-ld.bfd: common/built-in.o: in function `puts':
/home/monstr/data/disk/u-boot/common/console.c:563: undefined reference to `printch'
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Fix ns16550 dependency, add ZYNQ_SERIAL, change S5P]
Signed-off-by: Tom Rini <trini@konsulko.com>
When an eTSEC is configured to use TBI, configuration of the
TBI is done through the MIIM registers for that eTSEC.
For example, if a TBI interface is required on eTSEC2, then
the MIIM registers starting at offset 0x2_5520 are used to
configure it.
Fixes: 9a1d6af55e ("net: tsec: Add driver model ethernet support")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The current code accesses eTSEC registers using physical
address directly, it's not correct, though no problem on
current platforms. It won't work on platforms, which does
not support 1:1 virtual-physical address map.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Change the compatible string to "fsl,etsec2" for the Ethernet ports,
which is used in the current driver's match table.
Fixes: 69a00875e3 ("doc: dt-bindings: Describe Freescale TSEC ethernet controller")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Acked-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Introduce the QorIQ DPAA 1 Frame Manager nodes in the T1024RDB
device tree. The device tree fragments are copied over with little
modification from the Linux kernel source code.
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Add the QorIQ DPAA 1 Frame Manager v3 device tree nodes for the
T102x SoCs. The device tree fragments are copied over with little
modification from the Linux kernel source code.
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Introduce the QorIQ DPAA 1 Frame Manager nodes in the P5040DS
device tree. The device tree fragments are copied over with little
modification from the Linux kernel source code.
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The device tree fragments are copied over with little
modification from the Linux kernel source code.
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Introduce the QorIQ DPAA 1 Frame Manager nodes in the P3041DS
device tree. The device tree fragments are copied over with little
modification from the Linux kernel source code.
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The device tree fragments are copied over with little
modification from the Linux kernel source code.
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Introduce the QorIQ DPAA 1 Frame Manager nodes in the P2041RDB
device tree. The device tree fragments are copied over with little
modification from the Linux kernel source code.
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The device tree fragments are copied over with little
modification from the Linux kernel source code.
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The device tree fragments are copied over with little
modification from the Linux kernel source code.
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Add the QorIQ DPAA Frame Manager version 3 device tree nodes
description. The device tree fragments are copied over with little
modification from the Linux kernel source code.
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Add the QorIQ DPAA Frame Manager device tree nodes description.
The device tree fragments are copied over with little modification
from the Linux kernel source code.
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Add the QorIQ GPIO device tree nodes description. The device tree
fragments are copied over with little modification from the Linux
kernel source code.
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
sbi_probe_extension() is an API defined in SBI v0.2, not v0.1.
Fixes 7e249bc13a: ("riscv: Move all SMP related SBI calls to SBI_v01")
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
U-Boot defaults to use SBI v0.2. Howerver there is a global variable
sbi_spec_version that stills refers to v0.1. Since it is not used
anywhere, let's remove it.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
OpenSBI generic platform support provides platform specific
functionality based on the FDT passed by previous booting stage.
Depends on OpenSBI commit:
platform: Add generic FDT based platform support
(sha1: f1aa9e54e00006ae70aeac638d5b75093520f65d)
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
With sifive_fu540_defconfig:
User can use FSBL or u-boot-spl.bin anyone at a time.
For FSBL,
fsbl->fw_payload.bin (opensbi + U-Boot)
For u-boot-spl.bin,
u-boot-spl.bin->FIT image (opensbi + U-Boot proper + dtb)
U-Boot SPL will be loaded by ZSBL from SD card (replace fsbl.bin with
u-boot-spl.bin) and runs in L2 LIM in machine mode and then load FIT
image u-boot.itb from SD card into RAM.
U-Boot SPL expects u-boot.itb FIT image at the starting of SD card sector
number (0x822) of GUID type "2E54B353-1271-4842-806F-E436D6AF6985"
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add U-Boot proper sector start offset for SiFive FU540.
This value is based on the partition layout supported
by SiFive FU540.
u-boot.itb need to write on this specific offset so-that
the SPL will retrieve it from here and load.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
This is a sample GPT partition layout for SD card,
right now three important partitions are added to
make the system bootable.
partition layout:
Part Start LBA End LBA Name
Attributes
Type GUID
Partition GUID
1 0x00000022 0x00000821 "loader1"
attrs: 0x0000000000000000
type: 5b193300-fc78-40cd-8002-e86c45580b47
guid: cbcbef44-e627-42bc-b134-93b6f3784b8c
2 0x00000822 0x00002821 "loader2"
attrs: 0x0000000000000000
type: 2e54b353-1271-4842-806f-e436d6af6985
guid: f54eba28-d8de-4852-978d-1a673777e2ae
3 0x00002822 0x00020821 "rootfs"
attrs: 0x0000000000000004
type: 0fc63daf-8483-4772-8e79-3d69d8477de4
type: linux
guid: 9561df46-8d55-4799-a83b-cfee9ef6ff93
Note:
- loader1 would be fsbl or spl
- loader2 would be U-Boot or U-Boot proper
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
This sync has changes required to use GPIO in U-Boot and
U-Boot SPL.
Sync dts from linux v5.7-rc2 commit:
"riscv: dts: Add GPIO reboot method to HiFive Unleashed DTS file"
(sha1: 0a91330b2af9f71ceeeed483f92774182b58f6d9)
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Set ethernet clock rate to 125 Mhz so that it will work with 1000Mbps,
Earlier this is done by FSBL. With this change We can remove the
ethernet clock rate code from FSBL.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
U-Boot ethernet works with FSBL flow where releasing ethernet clock
reset is part of FSBL itself but with the SPL, We need to release
ethernet clock reset explicitly for U-Boot proper. With this change
Release ethernet clock reset code in FSBL might not be needed or
unaffected.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Devicetree files in FU540 platform is synced from Linux, like other
platforms does. Apart from these U-Boot in FU540 would also require
some U-Boot specific node like clint.
So, create board specific -u-boot.dtsi files. This would help of
maintain U-Boot specific changes separately without touching Linux
dts(i) files which indeed easy for syncing from Linux between
releases.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
When build U-Boot SPL, meet an issue of undefined reference to
'crc7' for drivers/mmc/mmc_spi.c, so let's compile crc7.c when
CONFIG_MMC_SPI selected.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Pull request for UEFI sub-system for efi-2020-07-rc4
This patch series addresses the following issues:
* allow compiling with clang
* add missing function descriptions to the HTML documentation
* simplify the validation of UEFI images
* validate load options in the UEFI boot manager
In a preparatory patch a structure definition is moved.
- Update various docs to not have 'ARCH=' in them as that's not part of
how U-Boot builds.
- Add macOS tools-only build to Azure to help catch problems on BSD
hosts with tools.
- Bugfixes from the latest header cleanup around ARCH_DMA_MINALIGN
- Assorted small Kconfig logic/typo corrections
- Add a default hash to FIT images that have their its auto generated.
- Other assorted fixes
The global variable, efi_guid_cert_type_pkcs7, will also be used in
efi_image_loader.c in a succeeding patch so as to correctly handle
a signature type of authenticode in signed image.
Meanwhile, it is currently defined in efi_variable.c. Once some secure
storage solution for UEFI variables is introduced, efi_variable.c may
not always be compiled in.
So move the definition to efi_signature.c as a common place.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Knowing that at least one section header follows the optional header we
only need to check for the length of the 64bit header which is longer than
the 32bit header.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
We want to follow the Linux kernel style for function descriptions.
Add missing parentheses after function names.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
On ARM systems gd is stored in register r9 or x18. When compiling with
clang gd is defined as a macro calling function gd_ptr(). So we can not
make assignments to gd.
In the UEFI sub-system we need to save gd when leaving to UEFI binaries and
have to restore gd when reentering U-Boot.
Define a new function set_gd() for setting gd and use it in the UEFI
sub-system.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Tom Rini <trini@konsulko.com>
For passing the optional data of the load option to the loaded imaged
protocol we need its size.
efi_deserialize_load_option() is changed to return the size of the optional
data.
As a by-product we get a partial validation of the load option.
Checking the length of the device path remains to be implemented.
Some Coverity defects identified the load options as user input because
get_unaligned_le32() and get_unaligned_le16() is called. But non of these
Coverity defects can be resolved without marking functions with Coverity
specific tags.
Reported-by: Coverity (CID 303760)
Reported-by: Coverity (CID 303768)
Reported-by: Coverity (CID 303776)
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Add the required changes for compiling with DM_ETH on the PPC
DPAA platforms.
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
A compilation error appears when QE is compiled with DM_ETH
enabled:
drivers/qe/uec.c: In function 'init_phy':
drivers/qe/uec.c:425:28: error: dereferencing pointer to incomplete type 'struct eth_device'
uec = (uec_private_t *)dev->priv;
^~
drivers/qe/uec.c: In function 'uec_initialize':
drivers/qe/uec.c:1357:43: error: invalid application of 'sizeof' to incomplete type 'struct eth_device'
dev = (struct eth_device *)malloc(sizeof(struct eth_device));
^~~~~~
The patch disables CONFIG_QE when CONFIG_DM_ETH is set.
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
P4080DS compilation fails with DM_GPIO enabled:
drivers/gpio/gpio-uclass.c:355:5: error: redefinition of 'gpio_request'
int gpio_request(unsigned gpio, const char *label)
^~~~~~~~~~~~
In file included from ./arch/powerpc/include/asm/arch/gpio.h:17:0,
from ./arch/powerpc/include/asm/gpio.h:1,
from drivers/gpio/gpio-uclass.c:16:
./arch/powerpc/include/asm/mpc85xx_gpio.h:68:19: note: previous definition of 'gpio_request' was here
static inline int gpio_request(unsigned gpio, const char *label)
^~~~~~~~~~~~
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
arch/arm/include/asm/system.h declares psci_arch_init(), but it is
surrounded by #ifdef CONFIG_ARMV8_PSCI.
psci_arch_init() is called for CONFIG_ARMV7_PSCI too. Add the missing
function declaration.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This config option depends on EXT4 support.
If Ext4 write capability is not selected, it generate write error messages
and is unable to maintain boot counter.
Signed-off-by: Frédéric Danis <frederic.danis@collabora.com>
Configuration checks should not be in the C files but in the Kconfig files.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
When building U-Boot we select the architecture via Kconfig and not ARCH
being passed in via the environment or make cmdline.
While in here, add the doc file to the MAINTAINERS entry.
Cc: Amit Singh Tomar <amittomer25@gmail.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Amit Singh Tomar <amittomer25@gmail.com>
When building U-Boot we select the architecture via Kconfig and not ARCH
being passed in via the environment or make cmdline.
While in here, add the doc file to the MAINTAINERS entry.
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Anup Patel <anup.patel@wdc.com>
Cc: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
When building U-Boot we select the architecture via Kconfig and not ARCH
being passed in via the environment or make cmdline.
While in here, add the doc file to the MAINTAINERS entry for coldfire.
Cc: Huan Wang <alison.wang@nxp.com>
Cc: Angelo Dureghello <angelo@sysam.it>
Signed-off-by: Tom Rini <trini@konsulko.com>
When building U-Boot we select the architecture via Kconfig and not ARCH
being passed in via the environment or make cmdline.
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
When building U-Boot we select the architecture via Kconfig and not ARCH
being passed in via the environment or make cmdline.
Cc: Po Liu <po.liu@nxp.com>
Cc: Qiang Zhao <qiang.zhao@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Add building the 'tools-only' target on macOS X 'Catalina'. Hopefully
this will catch changes to host tools that are incompatible on BSD style
environments.
Signed-off-by: Tom Rini <trini@konsulko.com>
This option currently does not add any sort of hash to the images in the
FIT.
Add a hash node requesting a crc32 checksum, which at least provides some
protection.
The crc32 value is easily ignored (e.g. in SPL) if not needed. and takes
up only about 48 bytes per image, including overhead.
Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Denk <wd@denx.de>
When using CONFIG_ENV_IS_IN_FAT and the config-file specifies a size
larger than what U-Boot wrote into the env-file, a confusing error
message is shown:
$ fw_printenv
Read error on /boot/uboot.env: Success
Fix this by showing a different error message when read returns too
little data.
Signed-off-by: Harald Seiler <hws@denx.de>
This is defined in the asm/cache.h header file. Update this header file to
include it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Adam Ford <aford173@gmail.com> #da850-evm
This is defined in the asm/cache.h header file. Update this header file to
include it so it gets the same value consistently across U-Boot.
This fixes 'usb host' on omapl138_lcdk.
Fixes: 90526e9fba ("common: Drop net.h from common header")
Reported-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
When building U-Boot we should not blindly use make -j8 but consider the
actual core count given by os.cpu_count().
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
- Corrected some FSP-M/FSP-S settings for Chromebook Coral
- ICH SPI driver and mrccache fixes for obtaining the SPI memory map
- Fixed various warnings generated by latest version IASL when compiling
ACPI tables
PCI Firmware specification requires _UID() and doesn't require _ADR()
to be set. Replace latter by former. This fixes the following warning
reported by ACPICA 20200430:
Warning 3073 - Multiple types (Device object requires either a _HID
or _ADR, but not both)
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
PCI Firmware specification requires _UID() and doesn't require _ADR()
to be set. Replace latter by former. This fixes the following warning
reported by ACPICA 20200430:
Warning 3073 - Multiple types (Device object requires either a _HID
or _ADR, but not both)
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Create buffers outside of the methods as ACPICA 20200430 complains
about this:
Remark 2173 - Creation of named objects within a method is highly
inefficient, use globals or method local variables instead
(\_SB.PCI0.LPCB.IURT._CRS)
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
ACPICA complains that either _HID() or _ADR() should be used.
For General Purpose DMA we may not drop the _ADR() because
the device is enumerated by PCI. Thus, simple drop _HID().
Reported-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Create buffers outside of the methods as ACPICA 20200214 complains about this:
Remark 2173 - Creation of named objects within a method is
highly inefficient, use globals or method local variables
instead
Reported-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
This allows the use of the Dediprog em100pro so I can test SPI flash on
this board in my lab.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When comparing hex dumps it is useful to see the offsets of the registers.
Add them in where they correspond to a multiple of 16.
Possibly it would be useful to have a a command to output the FSP values
in human-readable form, making use of the fsp_bindings implementation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Some settings were modified slightly in the device-tree conversion. Return
these to their original values. This includes some audio settings and a
few others that have changed.
Note that we still rely on the FSP defaults for most values, so there is
no need to specify a value if the FSP default is suitable.
This makes WiFi work again.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
When comparing hex dumps it is useful to see the offsets of the registers.
Add them in where they correspond to a multiple of 16.
Possibly it would be useful to have a a command to output the FSP values
in human-readable form, making use of the fsp_bindings implementation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Some settings were modified slightly in the device-tree conversion. Return
these to their original values.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
The change to avoid searching the device tree does not work on boards
wich don't have driver model set up this early, for example minnowmax.
Put back the old code (converted to livetree) as a fallback for these
devices. Also update the documentation.
This is tested on minnowmax, link, samus and coral.
Fixes: 87f1084a63 (x86: Adjust mrccache_get_region() to use livetree)
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com> (on Intel minnowmax)
The error code is often useful to figure out what is going on. Printing it
does not increase code size much, so print out the error and then hang.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present this logic does not work on link and samus, since their SPI
controller is not a PCI device, but a child of the PCH.
Unfortunately, fixing this involves a lot of extra logic. Still, this was
requested in the review of the fix-up patch, so here it is.
Fixes: 92842147c3 ("spi: ich: Add support for get_mmap() method")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com> (on Intel minnowmax)
At present the PCI BDF (bus/device/function) is needed to access the SPI
mapping, since the registers are at BAR0. This doesn't work when PCI
auto-config has not been done yet, since BARs are unassigned.
Add another way to find the mapping, using the MMIO base, if the caller
knows this.
Also add a missing function comment.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Now that the EMAC driver supports the H6 SoC, we can enable the Ethernet
hardware on the Pine H64 board.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
The H6 EMAC is very similar to the H3 variant, except that it uses the
same pinmux as R40. Add support for it.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
While the R40 uses a different register for EMAC clock configuration
than other chips, the register has a very similar layout. Reuse the
existing bitfield definitions in this file, since they match.
This allows the driver to compile on the H6 platform, where the
CCM_GMAC_CTRL definitions are not present.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
When compiling with CONFIG_SPL_SERIAL=n, gcc warns about
mbus_configure_port not being marked as static:
In file included from include/common.h:34,
from arch/arm/mach-sunxi/dram_sunxi_dw.c:11:
include/log.h:185:4: warning: 'printf' is static but used in inline function 'mbus_configure_port' which is not static
185 | printf(pr_fmt(fmt), ##args); \
| ^~~~~~
include/log.h:192:2: note: in expansion of macro 'debug_cond'
192 | debug_cond(_DEBUG, fmt, ##args)
| ^~~~~~~~~~
arch/arm/mach-sunxi/dram_sunxi_dw.c:100:2: note: in expansion of macro 'debug'
100 | debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1);
| ^~~~~
Fix this by updating the function accordingly.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
dm_spi_slave_platdata used in sf_probe for printing
plat->cs value and there is no relevant usage apart
from this.
We have enough debug messages available in SPI and SF
areas so drop this plat get and associated bug statement.
Cc: Simon Glass <sjg@chromium.org>
Cc: Vignesh R <vigneshr@ti.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
env_flash is a global flash pointer, and the probe would
happen only if env_flash is NULL, but there is no checking
and free the pointer if is not NULL.
So, this patch frees the old env_flash, and get the probed
flash in to env_flash pointer and finally check if is not NULL.
Cc: Simon Glass <sjg@chromium.org>
Cc: Vignesh R <vigneshr@ti.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
The new pointer points to flash found and that would
assign it to global 'flash' pointer for further flash
operations and also keep track of old flash pointer.
This would happen if the probe is successful or even
failed, but current code assigning new into flash before
and after checking the new.
So, drop the assignment after new checks so flash always
latest new pointer even if probe failed or succeed.
Cc: Simon Glass <sjg@chromium.org>
Cc: Vignesh R <vigneshr@ti.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Currently spi-nor code is assigning _write ops for SST
and other flashes separately.
Just call the sst_write from generic write ops and return
if SST flash found, this way it avoids the confusion of
multiple write ops assignment during the scan and makes
it more feasible for code readability.
No functionality changes.
Cc: Simon Glass <sjg@chromium.org>
Cc: Vignesh R <vigneshr@ti.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
The get_sw_write_prot API is used to get the write-protected
bits of flash by reading the status register and other wards
it's API for reading register bits.
1) This kind of requirement can be achieved using existing
flash operations and flash locking API calls instead of
making a separate flash API.
2) Technically there is no real hardware user for this API to
use in the source tree.
3) Having a flash operations API for simple register read bits
also make difficult to extend the flash operations.
4) Instead of touching generic code, it is possible to have
this functionality inside spinor operations in the form of
flash hooks or fixups for associated flash chips.
Considering all these points, this patch drops the get_sw_write_prot
and associated code bases.
Cc: Simon Glass <sjg@chromium.org>
Cc: Vignesh R <vigneshr@ti.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
CF_SPI kconfig option defined twice with DM_SPI
and non DM_SPI.
Drop the non DM_SPI side kconfig definition.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
- Fix mmc of path after syncfrom kernel dts;
- Add dwc3 host support with DM for rk3399;
- Add usb2phy and typec phy for rockchip platform;
- Migrate board list doc to rockchip.rst;
- Add rk3399 Pinebook Pro board support;
- Update dram_init in board_init and add memory node in SPL;
In a loading chain SPL -> ATF (->OP-TEE) -> U-Boot, ATF and a subsequent
OP-TEE will re-use the same fdt as the U-Boot target and may need the
information about usable memory ranges.
Especially OP-TEE needs this to initialize dynamic shared memory
(the only type U-Boot implements when talking to OP-TEE).
So allow spl_fixup_fdt() to take a fdt_blob argument, falling back to
the existing CONFIG_SYS_SPL_ARGS_ADDR if needed and call it from the
ATF path as well.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Parts of later SPL may need RAM information as well, so do full
dram_init() call, which includes the existing dram probing but also
initializes the ram information in gd.
dram_init() from sdram.c does the following steps:
- uclass_get_device(UCLASS_RAM, ...) like the current code
- ret = ram_get_info(dev, &ram);
- gd->ram_size = ram.size;
CONFIG_SPL_RAM already makes sure that sdram.c gets compiled
and thus no other variant of dram_init() can exist.
So it's the same functionality as before and only adds that the
SPL now aquires knowledge about the amount of available ram,
which it didn't know about before.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
With the new RPi4 which has 8 GB of RAM, we can have up to four DRAM
banks. Bump up the configuration files to detect all the memory in
U-Boot.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
i2c changes for v2020.07-rc4
- fix eeprom issue with AT24MAC402 (address != 0)
- fix in i2c-uclass.c when compiling compiling with -Wtype-limits
- designware_i2c: small fixes:
- check if the device is powered
- tidy up use of NULL priv
This patch adds or modifies functional tests for the Cover-changes,
Commit-changes, and Series-process-log tags in order to account for new
behavior added in the previous few patches. The '(no changes since v1)'
case is not tested for, since that would need an additional commit to test
in addition to testing the existing code paths.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds support to multi-line changes. That is, if one has a line
in a changelog like
- Do a thing but
it spans multiple lines
Using Series-process-log sort would sort as if those lines were unrelated.
With this patch, any change line starting with whitespace will be
considered part of the change before it.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
By default patman generates a combined changelog for the cover letter. This
may not always be desirable.
Many patches may have the same changes. These can be coalesced with
"Series-process-log: uniq", but this is imperfect. Similar changes like
"Move foo to patch 7" will not be merged with the similar "Move foo to this
patch from patch 6".
Changes may not make sense outside of the patch they are written for. For
example, a change line of "Add check for bar" does not make sense outside
of the context in which bar might be checked for. Some changes like "New"
or "Lint" may be repeated many times throughout different change logs, but
carry no useful information in a summary.
Lastly, I like to summarize the broad strokes of the changes I have made in
the cover letter, while documenting all the details in the appropriate
patches. I think this makes it easier to get a good feel for what has
changed, without making it difficult to wade through every change in the
whole series.
This patch adds two new tags to add changelog entries which only appear in
the cover letter, or only appear in the commit. Changes documented with
"Commit-changes" will only appear in the commit, and will not appear in the
cover letter. Changes documented with "Cover-changes" will not appear in
any commit, and will only appear in the cover letter.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Patman outputs a line for every edition of the series in every patch,
regardless of whether any changes were made. This can result in many
redundant lines in patch changelogs, especially when a patch did not exist
before a certain revision. For example, the existing behaviour could result
in a changelog of
Changes in v7: None
Changes in v6: None
Changes in v5:
- Make a change
Changes in v4: None
Changes in v3:
- New
Changes in v2: None
With this patch applied and with --no-empty-changes, the same patch would
look like
(no changes since v5)
Changes in v5:
- Make a change
Changes in v3:
- New
This is entirely aesthetic, but I think it reduces clutter, especially for
patches added later on in a series.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Some mailing lists have size limits and when we add binary contents
to our patches it's easy to exceed the size limits.
Git supports a command line option "--no-binary" to generate patches
without any binary contents. Add an option in patman to handle this.
Note with this option patches cannot be applied properly, but they
are still useful for code review.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Sort the existing command line options by:
- help comes first
- option starts with '-'
- option starts with '--'
Lower case followed by upper case letters, in alphabetical order.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Including the assembler headers before including common.h etc leads to
compilation errors upon MIPS64 based platforms using OF_LIVE. This
patch reorders the include files to the "correct" oder.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Since the commit 1289e96797 ("sandbox: spi: Drop command-line SPI
option"), "--spi_sf" command line option is no longer supported.
So update the following documents to sync them up with the change.
doc/arch/sandbox.rst
doc/SPI/README.sandbox-spi
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Enable USB3.0 Host support for ROC-RK3399-PC boards.
Tested USB3.0 SSD on Type C1 port on board.
=> usb start
starting USB...
Bus usb@fe380000: USB EHCI 1.00
Bus usb@fe3c0000: USB EHCI 1.00
Bus dwc3: usb maximum-speed not found
Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
scanning bus usb@fe380000 for devices... 1 USB Device(s) found
scanning bus usb@fe3c0000 for devices... 2 USB Device(s) found
scanning bus dwc3 for devices... 6 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
=> usb tree
USB device tree:
1 Hub (480 Mb/s, 0mA)
u-boot EHCI Host Controller
1 Hub (480 Mb/s, 0mA)
| u-boot EHCI Host Controller
|
+-2 Hub (480 Mb/s, 100mA)
USB 2.0 Hub [MTT]
1 Hub (5 Gb/s, 0mA)
| U-Boot XHCI Host Controller
|
+-2 Hub (480 Mb/s, 0mA)
| | VIA Labs, Inc. USB2.0 Hub
| |
| +-4 Hub (480 Mb/s, 100mA)
| | USB 2.0 Hub
| |
| +-5 (480 Mb/s, 100mA)
| VIA Technologies Inc. USB 2.0 BILLBOARD 0000000000000001
|
+-3 Hub (5 Gb/s, 0mA)
| VIA Labs, Inc. USB3.0 Hub
|
+-6 Mass Storage (5 Gb/s, 224mA)
JMicron External Disk 3.0 DB12345678A2
=> usb reset
resetting USB...
Bus usb@fe380000: USB EHCI 1.00
Bus usb@fe3c0000: USB EHCI 1.00
Bus dwc3: usb maximum-speed not found
Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
scanning bus usb@fe380000 for devices... 1 USB Device(s) found
scanning bus usb@fe3c0000 for devices... 2 USB Device(s) found
scanning bus dwc3 for devices... 6 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
RK3399 Type-C PHY is required that must hold whole USB3.0 OTG controller
in resetting to hold pipe power state in P2 before initializing the PHY.
This commit fixed it and added device compatible for rockchip platform.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Print the error code if the regulator enable fails, otherwise the error
message is rather useless and confusing.
Signed-off-by: Marek Vasut <marex@denx.de>
The board_eth_init() is not used for DM case, enable it only for
the non-DM case. This function should eventually be removed.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The regulator-fixed would return -ENOSYS when enabled/disabled,
because this operation is not supported, but this is not an error
e.g. on systems where the VBUS cannot be controlled, so if this
is the error code reported by the regulator core, consider it a
success and continue.
Signed-off-by: Marek Vasut <marex@denx.de>
Although I think it never occurs, the code doesn't make sense, because
it may allow to assign an IN endpoint to ss->ep_out.
Signed-off-by: Hayes Wang <hayeswang@realtek.com>
By default when core sees any transaction error (CRC or overflow) it
replies with terminating retry ACK (Retry=1 and Nump == 0).
Enabling this Auto Retry feature in controller will make the core send
a non-terminanting ACK upon such transaction errors. That is, ACK TP
with Retry=1 and Nump != 0.
Doing so will give controller a chance to recover from transient error
conditions.
Reference from below Linux commit,
commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature
in the controller")
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This patch adds a quirk to disable USB 2.0 MAC linestate check
during HS transmit. Refer the dwc3 databook, we can use it for
some special platforms if the linestate not reflect the expected
line state(J) during transmission.
When use this quirk, the controller implements a fixed 40-bit
TxEndDelay after the packet is given on UTMI and ignores the
linestate during the transmit of a token (during token-to-token
and token-to-data IPGAP).
On some rockchip platforms (e.g. rk3399), it requires to disable
the u2mac linestate check to decrease the SSPLIT token to SETUP
token inter-packet delay from 566ns to 466ns, and fix the issue
that FS/LS devices not recognized if inserted through USB 3.0 HUB.
Reference from below Linux commit,
commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate
check quirk")
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk")
in Linux Rockchip Kernel.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls
whether the PHY receives the suspend signal from the controller.
Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk")
in Linux Kernel.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Add USB TYPEC PHY driver for rockchip platform.
Referenced from Linux TypeC PHY driver, currently
supporting usb3-port and dp-port need to add it
in the future.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add Rockchip USB2PHY driver with initial support.
This will help to use it for EHCI controller in host
mode, and USB 3.0 controller in otg mode.
More functionality like charge, vbus detection will
add it in future changes.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Due to v5.7-rc1 sync the SD controller nodes in rk3399.dtsi
have SCLK_UPHY0_TCPDCORE, SCLK_UPHY1_TCPDCORE assigned-clocks
which are usually required for Linux and don't require to
handle them in U-Boot.
assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
So, mark them as empty in clock otherwise device probe on
those typec phy driver would fail.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable/Disable the USB2PHY clk for rk3399.
CLK is clear in enable and set in disable functionality.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
As documentation is being moved to doc/boards/rockchip create a warning
message and remove the redundant list of supported boards.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
As an additional step to move documentation to doc/boards/rockchip
improve format of the supported board list to make it more readable.
Additionally, add the configuration files used to build them based on
doc/README.rockchip.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
U-Boot has video output enabled so time to get keyboard working.
=> usb reset;usb tree
resetting USB...
Bus usb@fe380000: USB EHCI 1.00
Bus usb@fe3a0000: USB OHCI 1.0
Bus usb@fe3c0000: USB EHCI 1.00
Bus usb@fe3e0000: USB OHCI 1.0
Bus dwc3: usb maximum-speed not found
Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
scanning bus usb@fe380000 for devices... 1 USB Device(s) found
scanning bus usb@fe3a0000 for devices... 1 USB Device(s) found
scanning bus usb@fe3c0000 for devices... 1 USB Device(s) found
scanning bus usb@fe3e0000 for devices... 3 USB Device(s) found
scanning bus dwc3 for devices... cannot reset port 1!?
2 USB Device(s) found
scanning usb for storage devices... 2 Storage Device(s) found
USB device tree:
1 Hub (480 Mb/s, 0mA)
u-boot EHCI Host Controller
1 Hub (12 Mb/s, 0mA)
U-Boot Root Hub
1 Hub (480 Mb/s, 0mA)
u-boot EHCI Host Controller
1 Hub (12 Mb/s, 0mA)
| U-Boot Root Hub
|
+-2 Hub (12 Mb/s, 100mA)
| ALCOR Generic USB Hub
|
+-3 Mass Storage (12 Mb/s, 200mA)
Kingston DT 101 G2 001478544887BB3157380157
1 Hub (5 Gb/s, 0mA)
| U-Boot XHCI Host Controller
|
+-2 Mass Storage (5 Gb/s, 76mA)
ADATA ADATA USB Flash Drive 1520405012240002
Signed-off-by: Marcin Juszkiewicz <marcin@juszkiewicz.com.pl>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The vpcie*-supply properties are optional and these are absent on
boards like the ROCKPro64 and Firefly RK3399 where the voltage is
supplied by always-on regulators that are already enabled upon
boot. Make these regulators optional and properly check their
presence before attempting to enable them.
Makes PCIe work on un U-Boot on the boards mentioned above.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Marcin Juszkiewicz <marcin@juszkiewicz.com.pl>
Linux v5.7-rc1 dts(i) sync has changed the sdmmc node from
dwmmc@fe320000 to mmc@fe320000 and this ofpath is being
used in rockchip spl bootdevice code.
So, update the ofpath with a new node name and prefix "same-as-spl"
to missing u-boot,spl-boot-order.
Bug log:
U-Boot SPL 2020.07-rc2-00256-g9c5fef5774 (May 24 2020 - 20:20:43 +0530)
Trying to boot from MMC2
mmc_load_image_raw_sector: mmc block read error
Trying to boot from MMC1
mmc_load_image_raw_sector: mmc block read error
SPL: failed to boot from all boot devices
Fixes: 167efc2c7a ("arm64: dts: rk3399: Sync v5.7-rc1 from Linux"
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The khadas-vim, khadas-vim2, libretech-ac & libretech-*-pc boards were missing
DT tweak to enable USB gadget.
Add them to their -u-boot.dtsi files and include the right gxl-u-boot.dtsi.
Fixes: a19e8a0f03 ("arm: dts: meson-gxl: Add USB Gadget nodes for U-Boot")
Reported-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Include the common g12 u-boot tweaks to permit enabling video output tweaks
on Khadas VIM3 boards.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The I2C2 uses different pinmux on AV96, use correct pinmux and
also add comments about the I2C being present on the "low-speed"
expansion connector X6.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Because of this commit :
5ae84860b0 ("misc: i2c_eeprom: verify that the chip is functional at probe()")
at probe time, each eeprom is tested for read at offset 0.
The Atmel AT24MAC402 eeprom has different mapping. One i2c slave address is
used for the lower 0x80 bytes and another i2c slave address is used for the
upper 0x80 bytes. Because of this basically the i2c master sees 2 different
slaves. We need the upper bytes because we read the unique MAC address from
this EEPROM area.
However this implies that our slave address will return error on reads
from address 0x0 to 0x80.
To solve this, implemented an offset field inside platform data that is by
default 0 (as it is used now), but can be changed in the compatible table.
The probe function will now read at this offset and use it, instead of blindly
checking offset 0.
This will fix the regression noticed on these EEPROMs since the commit
abovementioned that introduces the probe failed issue.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
When compiling with -Wtype-limits we see this error:
drivers/i2c/i2c-uclass.c: In function ‘i2c_deblock_gpio_loop’:
drivers/i2c/i2c-uclass.c:517:21: error: comparison of
unsigned expression >= 0 is always true [-Werror=type-limits]
517 | while (scl_count-- >= 0) {
|
Don't loop forever.
Fixes: 1f746a2c82 ("i2c: Make deblock delay and SCL clock configurable")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
If the device doesn't return a version that means the device is
non-functional.
The dw_i2c_regs had invalid offsets for the version field. I got the
correct value from the DesignWare databook. It also matches what the
Picasso PPR says.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Tested on chromebook_coral:
Signed-off-by: Simon Glass <sjg@chromium.org>
At present we still have pre-driver-model code in this driver and it makes
things a bit confusing. In particular calc_bus_speed() is called with priv
as NULL if not using driver model.
This results in spk_cnt and comp_param1 being read from an invalid address
if not using driver model. For comp_param1 this may not cause problems if
reading from addresses close to 0 happens to be allowed, as high speed is
only supported by DM code. But spk_cnt is subsequently used to calculate
the bus periods and so this may cause problems (e.g. on spear600 board
which has not been migrated yet).
Add a new parameter regs parameter to calc_bus_speed() and add more
comments to this function and to _dw_i2c_set_bus_speed(), which calls it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
- Use device tree for FSP-M and FSP-S configuration on Intel Apollo Lake
- Add SMBIOS cbmem entry parsing for coreboot
- Various clean-ups to CBFS implementation
The size is not actually used since it is present in the header. Drop this
parameter. Also tidy up error handling while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Currently we support reading a file from CBFS given the address of the end
of the ROM. Sometimes we only know the start of the CBFS. Add a function
to find a file given that.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This function currently returns a node pointer so there is no way to know
the error code. Also it uses data in BSS which seems unnecessary since the
caller might prefer to use a local variable.
Update the function and split its body out into a separate function so we
can use it later.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We may as well return the error code and use it directly in the command
code. CBFS still uses its own error enum which we may be able to remove,
but leave it for now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The start address of the CBFS is used when scanning for files. It makes
sense to put this in our cbfs_priv struct and calculate it when we read
the header.
Update the code accordingly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
It doesn't make sense to use u8 * as the pointer type for accessing the
CBFS since we do not access it as bytes, but via structures. Change it to
void *, which allows us to avoid a cast.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
These two functions have mostly the same code. Pull this out into a common
function.
Also make this function zero the private data so that callers don't have
to do it. Finally, update cbfs_load_header_ptr() to take the base of the
ROM as its parameter, which makes more sense than passing the address of
the header within the ROM.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This function is strange at the moment in that it takes a header pointer
but then accesses the cbfs_s global. Currently clients have their own priv
pointer, so update the function to take that as a parameter instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This function is strange at the moment in that it takes a header pointer
but then accesses the cbfs_s global. Currently clients have their own priv
pointer, so update the function to take that as a parameter instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present this uses a true return to indicate it found a file. Adjust it
to use 0 for this, so it is consistent with other functions.
Update its callers accordingly and add a check for malloc() failure in
file_cbfs_fill_cache().
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present this uses an int type. U-Boot now supports bool so use this
instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
U-Boot uses ulong for addresses but there are a few places in this driver
that don't use it. Convert this driver over to follow this convention
fully.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present the result variable in the cbfs_priv is called 'result' as is
the local variable in a few functions. Change the latter to 'ret' which is
more common in U-Boot and avoids confusion.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
A the moment the FSP-M configuration is a mix of hard coded values and
devicetree properties.
This patch makes FSP-M full configurable from devicetree by adding
binding properties for all FSP-M parameters.
Co-developed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> (Tested on coral)
[sjg: Fix a build error for coral]
Signed-off-by: Simon Glass <sjg@chromium.org>
[bmeng: Add __maybe_unused to fsp_update_config_from_dtb()]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
We don't need to print this information since it is shown when the MTRRs
are displayed. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Convert the CRS305-1G-4S board to CRS3xx-98DX3236 to enable easier
implementation of new CRS3xx series boards, based on Marvell Prestera
98DX3236.
Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Jakov Petrina <jakov.petrina@sartura.hr>
Commit f49ac7e1c4 switched the default PHY speed to 3.125Gbit to resolve
issues with SFP modules. However, U-Boot does not have a "2500base-x"
phy-mode.
Resolve this by using "sgmii-2500" instead.
Signed-off-by: Jakov Petrina <jakov.petrina@sartura.hr>
Signed-off-by: Vladimir Vid <vladimir.vid@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Stefan Roese <sr@denx.de>
Without CONFIG_SYS_U_BOOT_OFFS set to CONFIG_SYS_SPI_U_BOOT_OFFS, U-Boot
will be located at address 0x16000. But, SPL will try to load the
payload from 0x24000 causing the boot to hang.
Signed-off-by: Ezra Buehler <ezra@easyb.ch>
Reviewed-by: Stefan Roese <sr@denx.de>
Without this U-Boot-specific property, booting on the Synology DS414
(or DS214+) fails in SPL. The spi0 DT node is not scanned, as a result
the SPI flash cannot be found.
Signed-off-by: Ezra Buehler <ezra@easyb.ch>
Reviewed-by: Stefan Roese <sr@denx.de>
SMP support for S-mode U-Boot is enabled only if SBI_V01 is enabled.
There is no point in supporting SMP related (IPI and fences) SBI calls
when SBI_V02 is enabled.
Modify all the SMP related SBI calls to be defined only for SBI_V01.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Wrap definition of board_usb_hw_init() around with #ifdef CONFIG_CMD_USB
to avoid warning: 'board_usb_hw_init' defined but not used
[-Wunused-function] when compiling without CONFIG_CMD_USB.
This patch makes sama5d27_som1_ek, sama5d2_ptc_ek and sama5d2_xplained
consistent with other boards that use the same #ifdef to avoid the warning.
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Ludovic Desroches <ludovic.desroches@microchip.com>
Signed-off-by: Josef Lusticky <josef@lusticky.cz>
Reviewed-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-05-06 16:18:53 +03:00
1246 changed files with 18972 additions and 9051 deletions
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan 1g port #2 device tree stub [ controller @ offset 0x500000 ]
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman@500000 {
fman1_rx_0x0a: port@8a000 {
cell-index = <0xa>;
compatible = "fsl,fman-v2-port-rx";
reg = <0x8a000 0x1000>;
};
fman1_tx_0x2a: port@aa000 {
cell-index = <0x2a>;
compatible = "fsl,fman-v2-port-tx";
reg = <0xaa000 0x1000>;
};
ethernet@e4000 {
cell-index = <2>;
compatible = "fsl,fman-dtsec";
reg = <0xe4000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x0a &fman1_tx_0x2a>;
tbi-handle = <&tbi7>;
ptp-timer = <&ptp_timer1>;
};
mdio@e5120 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-mdio";
reg = <0xe5120 0xee0>;
tbi7: tbi-phy@8 {
reg = <0x8>;
device_type = "tbi-phy";
};
};
};
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