Compare commits

...

274 Commits

Author SHA1 Message Date
Tom Rini
866ca972d6 Prepare v2024.01
Signed-off-by: Tom Rini <trini@konsulko.com>
2024-01-08 10:37:48 -05:00
Jan Kiszka
82750ce442 arm: dts: iot2050: Fix by syncing from Linux
This restores support for IOT2050 by widely synchronizing its DT files
with the Linux kernel. We additionally need to add the alias restoration
that is still waiting for its upstream merge and the not-yet-upstreamed
bits needed for watchdog reboot detection.

Fixes: 4dbdc84754 ("arm: dts: k3-am654: pull in dtb update from Linux")
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2024-01-06 09:18:44 -05:00
Nishanth Menon
dbb124cf68 configs: j7200: Remove HBMC_AM654 config
Kernel commit 1b77265626a4 ("arm64: dts: ti: k3-j7200-mcu-wakeup: Add
HyperBus node") was merged to kernel without its dependent patch [1].
Similar fix is needed in U-Boot, and hbmc currently breaks boot. Till
this gets fixed in U-Boot, disable the config by default so that the
hbmc probe that happens in board/ti/j721e/evm.c will not take place
and lead to boot failure.

This is similar to the approach in commit 5b2671594b ("configs:
j721e: Remove HBMC_AM654 config"), introduced to j7200 evm platform.

[1] https://lore.kernel.org/all/20230424184810.29453-1-afd@ti.com/

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2024-01-04 11:23:19 -05:00
Anthony Loiseau
1e108762b4 MAINTAINERS: fix folders within glob pattern
A "F: foo*" entry does not match any foo*/ folder nor its subtree,
another "F: foo*/" entry is needed for that.

Add missing foo*/ entries where an existing folder was ignored,
so this folder and its subtree is properly covered.

Arm tegra, Arm TI and Environment sections are affected.

Cc: Tom Rini <trini@konsulko.com>
Cc: Thierry Reding <treding@nvidia.com>
Cc: Svyatoslav Ryhel <clamor95@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Anthony Loiseau <anthony.loiseau@allcircuits.com>
2024-01-03 11:49:30 -05:00
Mattijs Korpershoek
9466b3cf2c MAINTAINERS: Fix ANDROID AB unknown file entry
Commit 19a91f2464 ("Create a new boot/ directory") moved the
android_ab.c code under boot/android_ab but did not update
the MAINTAINERS entry.

Update it so that the maintainer will get cc'ed again.

Fixes: 19a91f2464 ("Create a new boot/ directory")
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
2024-01-03 11:47:07 -05:00
Tom Rini
80cb22c58b Prepare v2024.01-rc6
Signed-off-by: Tom Rini <trini@konsulko.com>
2024-01-03 09:11:33 -05:00
Tom Rini
b2cbf968dd configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-01-03 09:09:56 -05:00
Nishanth Menon
e703bfcb38 arm: dts: k3-am62a*: Sync with kernel v6.7-rc1
Sync with kernel v6.7-rc1 and sync up the u-boot dts files accordingly.

Signed-off-by: Nishanth Menon <nm@ti.com>
2024-01-03 08:52:19 -05:00
Nishanth Menon
244c9fd1a5 arm: mach-k3: am62a: Add main_timer0 id to the dev list
main_timer0 is used by u-boot as the tick-timer. Add it to the soc
devices list so it an be enabled via the k3 power controller.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2024-01-03 08:52:19 -05:00
Tom Rini
3f662af87d Merge patch series "sync am65x device tree with Linux v6.7-rc1"
Bryan Brattlof <bb@ti.com> says:

Hello Again Everyone!

This series gets the am65x booting again along with syncing the device
tree files with v6.7-rc1 Linux.

The bulk of these patches unify the WKUP SPL board file with the arm64
files to make future syncs from Linux much easier. In the end the DTBs
should look a lot like what the DTBs look like for the am64x which
is fairly similar to the am65x.

For those interested in what UART boot looks like:
   https://paste.sr.ht/~bryanb/7df8a645dc548912cd806abd5ecab967ef3287bc
2024-01-03 08:38:40 -05:00
Bryan Brattlof
37a1a4074b arm: dts: k3-am654: convert bootph-pre-ram to bootph-all
Many nodes are reused between WKUP SPL, MAIN SPL, and U-Boot. Using
bootph-pre-ram is causing these nodes to be present in SPL builds but
pruned away during the U-Boot build. Convert these nodes to bootph-all
so they will remain no matter which dtb build is happening.

Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2024-01-03 08:36:37 -05:00
Bryan Brattlof
4aea536754 arm: dts: k3-am654: remove duplicate mcu secure proxy node
With the Linux and U-Boot board dtb files unified, we now have a
duplicate mcu secure proxy node. Remove it

Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2024-01-03 08:36:37 -05:00
Bryan Brattlof
e055622bd7 arm: dts: k3-am654: move dummy_clock to root node
The dummy_clock node is used to help the drivers probe the IO needed to
setup consoles and boot media to load firmware into the SoC.

This dummy_clock isn't a device that exists nor does it exist in the
mcu domain. So move it from cbass_mcu to the root node to avoid any
confusion.

Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2024-01-03 08:36:37 -05:00
Bryan Brattlof
5baad5521d arm: dts: k3-am654: remove un-needed aliases
These aliases are not needed in U-Boot. Remove them

Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2024-01-03 08:36:37 -05:00
Bryan Brattlof
dabf30a2bf arm: dts: k3-am654: remove duplicate root properties
With the Linux and U-Boot board dtb files unified, we have duplicate
properties in the root node. Remove them

Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2024-01-03 08:36:37 -05:00
Bryan Brattlof
d23582d052 arm: dts: k3-am654: remove duplicate vtt pinmux
With the Linux and U-Boot board dtb files unified, we now have a
duplicate vtt_pinmux node. Remove it

Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2024-01-03 08:36:37 -05:00
Bryan Brattlof
c7b075074f arm: dts: k3-am654: remove duplicate mdio
With the Linux and U-Boot board dtb files unified, we now have a
duplicate mdio node. Remove it

Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2024-01-03 08:36:37 -05:00
Bryan Brattlof
9a6fab6d82 arm: dts: k3-am654: remove usb0
The pinmux for usb0 is missing from the Linux board dtb file. Remove it
until we can introduce it in Linux

Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2024-01-03 08:36:37 -05:00
Bryan Brattlof
755db5fc7c arm: dts: k3-am654: remove duplicate ospi0 node
With the Linux and U-Boot board dtb files unified, we now have a
duplicate ospi0 node. Remove it

Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2024-01-03 08:36:37 -05:00
Bryan Brattlof
41ae2c6fb7 arm: dts: k3-am654: remove duplicate wkup_i2c0
With the Linux and U-Boot board dtb files unified, we now have a
duplicate wkup_i2c0 node. Remove it

Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2024-01-03 08:36:37 -05:00
Bryan Brattlof
7f66ec50ad arm: dts: k3-am654: remove duplicate sdhci1 pinmux node
With the Linux and U-Boot board dtb files unified, we now have a
duplicate sdhci1 pinmux node. Remove it

Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2024-01-03 08:36:37 -05:00
Bryan Brattlof
52d87efd02 arm: dts: k3-am654: remove duplicate sdhci0 pinmux node
With the Linux and U-Boot board dtb files unified, we now have
a duplicate sdhci0 pinmux node. Remove it

Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2024-01-03 08:36:37 -05:00
Bryan Brattlof
3e00c8b82e arm: dts: k3-am654: remove duplicate main_uart0
With the Linux and U-Boot board dtb files unified, we now have a
duplicate main_uart0 node. Remove it

Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2024-01-03 08:36:37 -05:00
Bryan Brattlof
bdf8a2c040 arm: dts: k3-am654: remove duplicate mcu_uart0 node
With the Linux and U-Boot board dtb files unified we now have a
duplicate mcu_uart0 node. Remove it

Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2024-01-03 08:36:37 -05:00
Bryan Brattlof
5e00547e58 arm: dts: k3-am654: add needed regs to udmap nodes
Ethernet is one of a few IPs in U-Boot that depend on DMA to operate.
However there are a few missing registers ranges in the udmap nodes
need to properly setup DMA for the am65x.

A fix has been added to the Linux kernel[0] to add these ranges however
they have not made it to a Linux tag. To keep DMA operational until the
next DT sync from Linux, add these ranges to the *-u-boot.dtsi with a
note for our future selves.

[0] https://lore.kernel.org/r/20231213135138.929517-2-vigneshr@ti.com

Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2024-01-03 08:36:37 -05:00
Bryan Brattlof
194641300c arm: dts: k3-am654: remove duplicate mcu_udmap
With the Linux and U-Boot board dtb files unified, we now have a
duplicate mcu_udmap node. Remove it

Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2024-01-03 08:36:37 -05:00
Bryan Brattlof
afb7fb6ba7 arm: dts: k3-am654: remove duplicate mcu_ringacc
With the Linux and U-Boot board dtb files unified, we now have a
duplicate mcu_ringacc node. Remove it

Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2024-01-03 08:36:37 -05:00
Bryan Brattlof
7cf2fa8096 arm: dts: k3-am654: remove duplicate timer
timer1 is really just the mcu_timer0 node redefined for the WKUP SPL.
Remove the timer1 and replace it with the mcu_timer0 from the Linux
device tree we imported into U-Boot.

Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2024-01-03 08:36:37 -05:00
Bryan Brattlof
3bf9f9a35f arm: dts: k3-am654: remove duplicate wkup_uart0
With the Linux and U-Boot board files unified, we now have a duplicate
wkup_uart0 node. Remove it

Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2024-01-03 08:36:37 -05:00
Bryan Brattlof
a67443efc7 arm: dts: k3-am654: remove duplicate vtt_supply
With the Linux and U-Boot board dtb files unified we now have a
duplicate vtt_supply node. Remove it

Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2024-01-03 08:36:37 -05:00
Bryan Brattlof
e72ece5894 arm: dts: k3-am654: include a53 board dtb for r5 build
To make things as organized as possible, start from the Linux board dtbs
and apply all properties needed for U-Boot in our *-u-boot.dtsi file for
the MAIN SPL and U-Boot builds.

We can then include these files for the WKUP SPL build making further
edits to the needed properties and nodes for the WKUP SPL bootloader's
view of the am65x.

Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2024-01-03 08:36:37 -05:00
Bryan Brattlof
b65ea697d7 arm: dts: k3-am654: copy bootph properties to a53 dts
In order to unify the R5 board dtb file with the Linux board dtb file,
we will need to copy all bootph-pre-ram properties to the *-u-boot.dtsi
overlay.

Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2024-01-03 08:36:37 -05:00
Bryan Brattlof
4dbdc84754 arm: dts: k3-am654: pull in dtb update from Linux
Pull in dtb updates for the am654 base board from v6.7-rc1 of Linux

Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2024-01-03 08:36:37 -05:00
Bryan Brattlof
b53f19061f arm: dts: k3-am654-r5: Merge board file and U-Boot overlay
The R5 board file for U-Boot should be the same as the board file copied
from Linux with a few alterations to work with the R5's view of the SoC.

First we need to unify the R5 board file and it's U-Boot overlay before
we can unify the Linux board file with this one.

Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2024-01-03 08:36:37 -05:00
Bryan Brattlof
60f04320c0 configs: am65x_evm_a53: disable CONSOLE_MUX
We do not have a need to share a single console with the evaluation
board and disabling this option reduces the complexity of configuring
the consoles. Disable CONSOLE_MUX

Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2024-01-03 08:36:37 -05:00
Bryan Brattlof
88af4d46c6 configs: am65x_evm_r5: enable driver for fixed regulators
Some of the regulators we need to successfully boot are fixed
regulators. Enable the driver to properly probe them.

Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2024-01-03 08:36:37 -05:00
Mark Kettenis
0a0ceea226 arm: apple: Disable SMBIOS again
Apple machines do not have memory below 4G.  Since U-Boot does
not support the SMBIOS 3 header structures this means we can't
support SMBIOS on these machines.  Unfortunately the refactoring
of the SMBIOS code this cycle accidentally enabled it again.

Fixes: 53fab13a7b ("efi: Use the installed SMBIOS tables")
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-26 14:41:56 -05:00
Jim Liu
f03e3f0b8b spi: npcm_pspi: Fix the wrong clock divider calculation
Fix the wrong clock divider calculation.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2023-12-26 14:41:46 -05:00
Tom Rini
2c9ee3f226 Merge tag 'u-boot-imx-master-20231220' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
- Make DRAM stable on i.MX8MP DHCOM SoM by using FPWM mode and updating
  the DRAM timing
- Fix display artifacts when booting Linux on i.MX8M Mini/Plus eDM SBC
2023-12-20 14:14:12 -05:00
Marek Vasut
8f5043ee6d get_maintainer.pl: Add --git to look up CCed in git history
Add the --git parameter, else recent contributors are left out of the CC list.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-19 08:03:14 -05:00
Baruch Siach
b5712acb97 net: fix NetConsole documentation reference
Fixes: d0253f7e5c ("doc: move README.NetConsole to HTML documentation")
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-12-19 08:02:37 -05:00
Marek Vasut
4caacb2f29 net: wget: Support non-default HTTP port
Currently the wget command is hard wired to HTTP port 80. This is
inconvenient, as it is extremely easy to start trivial HTTP server
as an unprivileged user using e.g. python http module to serve the
files, but such a server has to run on one of the higher ports:
"
$ python3 -m http.server -d $(pwd) 8080
"

Make it possible to configure HTTP server port the same way it is
possible to configure TFTP server port, using environment variable
'httpdstp' (similar to 'tftpdstp'). Retain port 80 as the default
fallback port. This way, users can start their own trivial server
and conveniently download whatever files they need into U-Boot.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-12-19 08:01:59 -05:00
Emanuele Ghidoli
fac5308d27 arm: dts: k3-am625-verdin: fix DDRSS configuration
The current DDR subsystem configuration occasionally results in write failures,
impacting memory stability, on Verdin AM62 Solo 512MB WB IT 0072 SKU.
This commit addresses the issue by adjusting Drive Pull-Up/Down and
Write Latency to improve the eye diagram and ensure reliable write operations.
This configuration is shared with all Verdin AM62 SoM and
it does not introduce regressions.

Configurations changes from previous / default values:
- Drive Pull-Up/Down from 40 to 34.3 Ohm
- Write Latency from 8 to 10
- ODTLon / ODTLoff latency from 0 / 0 to 4 / 20 nCK
- VREF control range 1 at 27 %
- tFAW from 30 to 40 ns

Configuration is output from SysConfig [1] web tool, currently at version
1.18.1+3343 (DDR SubSystem v9.10).

[1] https://dev.ti.com/sysconfig

Fixes: 7d1a10659f ("board: toradex: add verdin am62 support")
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2023-12-19 08:01:05 -05:00
Peter Robinson
38003ab25c doc: Remove README.sha1 file
The contents of README.sha1 only refer to process around verification
of the pcs440ep board firmware in flash. The device was removed in
commit 242836a893 ("powerpc: ppc4xx: remove pcs440ep support") in
2015 so this readme isn't really relevant anymore so can be removed.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-19 07:26:36 -05:00
Marek Vasut
1f25c75619 ARM: dts: imx: Power off display output on Data Modul i.MX8M Mini/Plus eDM SBC
Turn display connector power off on boot and reboot to prevent any
bogus start up sequence of any panel potentially attached to the
display connector.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-12-18 20:25:57 -03:00
Tom Rini
97a8974442 Prepare v2024.01-rc5
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-12-18 07:49:45 -05:00
Marek Vasut
31757f2bea ARM: imx: Update DRAM timings with inline ECC on DH i.MX8MP DHCOM SoM
Import DRAM timings generated by the DDR tool 3.31 which introduce assorted
tweaks to the DRAM controller settings. Furthermore, enable DBI to improve
noise resilience of the DRAM bus by reducing the number of bit changes on
the bus.

Reduce the DRAM rate to 3600 MTps to remove all remaining correctable errors
reported by EDAC . It is not entirely clear why the slightly faster setting
does produce sporadic correctable errors, while this one does not, but this
could be related to simpler PLL setting at 3600 MTps.

Enable inline ECC which is necessary to detect ECC errors and collect
statistics by the EDAC driver in Linux. This reduces the DRAM size by
64 MiB for each 512 MiB of DRAM, so for a 4 GiB device the available
DRAM size becomes 3.5 GiB and for 2 GiB device the available DRAM size
becomes 1.8 GiB.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-12-16 07:45:07 -03:00
Marek Vasut
d953ef8a24 ARM: imx: Force DRAM regulators into FPWM mode on DH i.MX8MP DHCOM SoM
In case the Buck5 and Buck6 regulators which supply DRAM Vdd1 and Vdd2/Vddq
respectively operate in automatic PWM/PFM mode, the DRAM EDAC detects more
correctable errors than if the regulators operate in forced PWM only mode.
Force DRAM regulators to forced PWM mode only to stop tempting the DRAM.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-12-16 07:45:02 -03:00
Tom Rini
39b4b2d9ec Merge tag 'clk-2024.01-rc5' of https://source.denx.de/u-boot/custodians/u-boot-clk
clock changes for u-boot/master

This has some clock fixes which should go in before the release. It's a bit
late in the cycle, but most of these have tests to go along with them.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2023-12-15 17:48:52 -05:00
Yang Xiwen
97d65b32d7 test: dm: clk_ccf: fix building error
Fix unused variable error produced by building tests

Fixes: d3061824 (test: dm: clk_ccf: test ccf_clk_ops)
Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20231216-b4-fix_build-v1-1-b8e79c94744f@outlook.com
2023-12-15 15:30:12 -05:00
Yang Xiwen
d306182439 test: dm: clk_ccf: test ccf_clk_ops
Assign ccf_clk_ops to .ops of clk_ccf driver so that it can act as an
clk provider. Also add "#clock-cells=<1>" to its device tree node.

Add "i2c_root" to clk_test in the device tree and driver for testing.

Get "i2c_root" clock in CCF unit tests and add tests for it.

Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20231111-enable_count-v3-2-08a821892fa9@outlook.com
2023-12-15 13:50:44 -05:00
Igor Prusov
9e0250321a dm: test: clk: Add test for ccf clk_set_rate()
Add a simple test case which sets clock rate to its current value.

Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20231205232334.2931-3-ivprusov@salutedevices.com
2023-12-15 12:32:00 -05:00
Igor Prusov
54d7da7730 clk: Check that composite clock's div has set_rate()
It's possible for composite clocks to have a divider that does not
implement set_rate() operation. For example, sandbox_clk_composite()
registers composite clock with a divider that only has get_rate().
Currently clk_composite_set_rate() only checks thate rate_ops are
present, so for sandbox it will cause NULL dereference during
clk_set_rate().

This patch adds rate_ops->set_rate check tp clk_composite_set_rate().

Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20231205232334.2931-2-ivprusov@salutedevices.com
2023-12-15 12:32:00 -05:00
Yang Xiwen
3fb2d3d6ac clk: get correct ops for clk_enable() and clk_disable()
assign clk_dev_ops(clkp->dev) to ops to ensure correct clk operations
are called on clocks.

This fixes the incorrect enable_count issue as described in [1].

[1]: https://lore.kernel.org/all/SEZPR06MB695927A6DEEEF8489A06897396A7A@SEZPR06MB6959.apcprd06.prod.outlook.com/

Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20231111-enable_count-v2-2-20e3728600b5@outlook.com
2023-12-15 12:31:47 -05:00
Yang Xiwen
09844d0de5 clk: check parent_name in clk_register to avoid confusing log_error() output
For some gate clocks and fixed clocks without a parent, calling
clk_register will print an useless error message indicating that parent
is missing. Fix that by gaurding log_xxx() with an if-statement.

Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
Suggested-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20230807-clk-fix-v2-1-0b688e21fb4e@outlook.com
2023-12-15 12:31:15 -05:00
Tom Rini
3ac22891cf Merge tag 'u-boot-imx-20231214' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
- Fix for i.MX8M Plus eDM SBC DDR timings with inline ECC
- Switch to FPWM mode on Data Modul i.MX8M Plus eDM SBC so that DRAM
  EDAC detects more correctable errors
- Fix for imx8mp-venice board DDR initialization
2023-12-15 08:22:31 -05:00
Tim Harvey
4f7122ca15 imx8mp-venice: update DRAM config for 2000MHz
The imx8mp venice boards can support 2000Mhz DRAM.
Update the DRAM config to support this.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2023-12-14 15:34:12 -03:00
Tim Harvey
f51559cc58 imx8mp-venice: fix DRAM bus configuration
The DRAM configuration for the 1GB and 4GB imx8mp venice boards had a
bus mapping issue (channel A and B swapped) which creates an invalid
deskewing configuration during training causing the DRAM to not be able
to run at its full bus speed.

Update the various config structures to resolve this.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2023-12-14 15:34:12 -03:00
Tim Harvey
9c288d569c board: gateworks: venice: remove extra file
Remove lpddr4_timing_imx8mm_512mb.c mistakenly committed

Fixes: a1c711046b "(board: gateworks: venice: add imx8mm-gw7903 support)"
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2023-12-14 15:34:12 -03:00
Marek Vasut
cfdbdf7842 ARM: imx: Update DRAM timings with inline ECC on Data Modul i.MX8M Plus eDM SBC
Import DRAM timings generated by the DDR tool 3.31 which introduce assorted
tweaks to the DRAM controller settings. Furthermore, enable DBI to improve
noise resilience of the DRAM bus by reducing the number of bit changes on
the bus.

Reduce the DRAM rate to 3600 MTps to remove all remaining correctable errors
reported by EDAC . It is not entirely clear why the slightly faster setting
does produce sporadic correctable errors, while this one does not, but this
could be related to simpler PLL setting at 3600 MTps.

Enable inline ECC which is necessary to detect ECC errors and collect
statistics by the EDAC driver in Linux. This reduces the DRAM size by
64 MiB for each 512 MiB of DRAM, so for a 4 GiB device the available
DRAM size becomes 3.5 GiB .

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-14 15:29:08 -03:00
Marek Vasut
c4cc14433d ARM: imx: Force DRAM regulators into FPWM mode on Data Modul i.MX8M Plus eDM SBC
In case the Buck5 and Buck6 regulators which supply DRAM Vdd1 and Vdd2/Vddq
respectively operate in automatic PWM/PFM mode, the DRAM EDAC detects more
correctable errors than if the regulators operate in forced PWM only mode.
Force DRAM regulators to forced PWM mode only to stop tempting the DRAM.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-14 15:29:08 -03:00
Marek Vasut
f4d15df831 ARM: imx: Enable CAAM on DH i.MX8M Plus DHCOM
Enable CAAM in U-Boot to make crypto available early in the boot process.

This has a side-effect that in case an older kernel version contains a
broken CAAM initialization timeout code, initialization in bootloader
will help that old kernel version function correctly.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-14 15:29:08 -03:00
Marek Vasut
bb10cd224c ARM: imx: Enable CAAM on Data Modul i.MX8M Mini/Plus eDM SBC
Enable CAAM in U-Boot to make crypto available early in the boot process.

This has a side-effect that in case an older kernel version contains a
broken CAAM initialization timeout code, initialization in bootloader
will help that old kernel version function correctly.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-14 15:29:08 -03:00
Marek Vasut
41b0f3454b ddr: imx: Add 3600 MTps rate support
Add PLL settings for DDR 3600 MTps . This is very similar to 3200 MTps
PLL setting, except the divider is not 9 but 8 .

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-14 15:29:08 -03:00
Marek Vasut
88db55b054 ddr: imx: Handle 3734 in addition to 3733 and 3732 MTps rates
The new MX8M DDR tool 3.31 now generates a programming file which uses
data rate 3734 instead of 3733 or 3732 . Handle another rounding option .

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-14 15:29:08 -03:00
Marek Vasut
4a03cf38d8 arm64: imx8mp: Inhibit DTC warning on DH i.MX8MP DHCOM rev.100 DTO
Inhibit DTC warning in imx8mp-dhcom-pdk3-overlay-rev100.dts:
"
arch/arm/dts/imx8mp-dhcom-pdk3-overlay-rev100.dtbo: Warning (reg_format): /fragment@0/__overlay__:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
arch/arm/dts/imx8mp-dhcom-pdk3-overlay-rev100.dtbo: Warning (avoid_default_addr_size): /fragment@0/__overlay__: Relying on default #address-cells value
arch/arm/dts/imx8mp-dhcom-pdk3-overlay-rev100.dtbo: Warning (avoid_default_addr_size): /fragment@0/__overlay__: Relying on default #size-cells value
"

The DTO overwrites the 'reg' property of an ethernet PHY and is only
used on specific combination of old prototype SoM and old prototype
PDK3 carrier board, which had incorrectly placed pull resistor, which
made the PHY change its MDIO address in that specific combination and
which is already fixed on production hardware.

The DTO is implemented in this simple manner because if it contained a
full MDIO bus node reference to define #address-cells and #size-cells,
it would also require a full new copy of the PHY node, i.e.
ethernet-phy@5 { ... reg = <5>; ... }, to avoid DTC warnings about
mismatch between node unit and reg value. The node unit in SoM DT is
ethernet-phy@7 { ... }; .

This simpler approach avoids unnecessary duplication without adverse
side effects.

Reported-by: Fabio Estevam <festevam@denx.de>
Reported-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Tested-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-14 15:29:08 -03:00
Tom Rini
27089f1e4d Merge branch '2023-12-13-assorted-minor-fixes'
- A few MAINTAINERS updates and Kconfig wording fixes
2023-12-13 09:57:28 -05:00
Shantur Rathore
87635a4d68 maintainers: rk3399: remove maintainer
Remove Akash Gajjar <akash@openedev.com> from
MAINTAINERS as email is bouncing.

Signed-off-by: Shantur Rathore <i@shantur.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-12-13 09:57:02 -05:00
Peter Robinson
dcb014b61f maintainers: bcmns3: remove maintainer
Remove Bharat Gooty as a maintainer as his mail is
bouncing.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Cc: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
2023-12-13 09:57:02 -05:00
Moritz Fischer
c5e9a4166d MAINTAINERS: Fix ARCH_APPLE file paths
Fixes a filepath in MAINTAINERS file that wasn't updated when
renaming the files to match the new SoC name.

Fixes: a4bd5e4120 ('arm: apple: Change SoC name from "m1" into "apple"')
Signed-off-by: Moritz Fischer <moritzf@google.com>
2023-12-13 09:57:02 -05:00
Alexander Gendin
b68d2865f1 drivers: misc: Kconfig: Fix SPL_FS_LOADER prompt
Both FS_LOADER and SPL_FS_LOADER have the same menu prompt.
To avoid confusion, make prompt for SPL_FS_LOADER different.

Signed-off-by: Alexander Gendin <agendin@matrox.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-13 09:57:02 -05:00
Tom Rini
253f939aa1 lib/Kconfig: Correct typo about SYSINFO_SMBIOS in help message
The correct symbol to enable to have SMBIOS populate fields based on the
device tree is SYSINFO_SMBIOS and not SMBIOS_SYSINFO.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-13 09:57:02 -05:00
Tom Rini
20d0464300 Merge tag 'u-boot-imx-20231212' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
- Fix emmc detection on colibri_imx7
- Fix DDR configuration on tqma6 to improve Ethernet performance
- Fix aliases and chosen nodes indentation on imx7s-warp
- Convert pico-imx6ul to DM_SERIAL
- Convert pico-pi-imx7d to watchdog driver model to fix 'reset' command
- Select CONFIG_NET_RANDOM_ETHADDR on imx8mp_evk to fix networking on
  older boards
- Add USBH_EN gpio hog to fix USB host interface not working on some
  Apalis Toradex carrier boards with Apalis iMX8 SoM
- Add PCI fixup for GW73xx-F+
- Fix broken EEPROM read on imx8mn-var-som
2023-12-12 16:33:57 -05:00
Marcel Ziswiler
29e31c549d board: colibri_imx7: fix emmc detection
Later versions of Colibri iMX7D V1.1B modules use a "new" SoC fusing. The
difference lies in whether we enable the boot ROM to use the eMMC reset
signal. Depending on the SoC fuse, the boot ROM configures this pin as a
GPIO output to drive the reset signal. Our eMMC vs NAND detection
currently only sets that signal to a GPIO without explicitly setting any
direction. Previously, by default, it was set as an input. As the boot ROM
now configures it as an output, we receive a value of zero instead of one,
indicating the absence of the pull-up on eMMC modules.

To fix this, set the SION bit, allowing the reading back of the value
even if it is configured as an output by the boot ROM. It's important to
note that with the new SoC fusing, we now read back what the boot ROM
drives rather than the real value caused by the pull-up resistor. However,
if it were ever driven low, the eMMC would permanently be reset.

In addition, remove hard-coded variant in the eMMC build case as since the
commit 0c39564d02 ("toradex: colibri_imx7: Enable nand/emmc detection
and set boot variant") will anyways always get overridden by the detection
routing in board code.

Fixes: 0c39564d ("toradex: colibri_imx7: Enable nand/emmc detection and set boot variant")
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Hiago De Franco <hiago.franco@toradex.com>
2023-12-12 16:33:57 -05:00
Miquel Raynal
49a3e0b9e2 tqma6: Fix DDR configuration
Initially investigating a Linux network issue causing a lot of drop and
poor network performances on a custom system based on a TQMA6A module
(based on an iMX6Q), [1st link below].

I eventually correlated my observations with a contention at the NIC
level when in concurrency with the graphics pipeline. Troubleshooting
this in the kernel lead to disabling DMA bursts accesses made by the IPU
in order to avoid triggering the QoS at the interconnect level, reducing
from 50 to 10% the drop rate on eth0, [2nd link below]. The solution
worked on my setup but not on others, which still suffered from
abnormally high drop rates even with this "fix".

After looking a while into TQ Systems BSP I figured out a number of
differences in recent U-Boot out-of-tree patches they had in their
repository [3rd link]. Parsing the differences one after the other lead
me to this final solution.

The reset pad of the DDR controller was apparently misconfigured, Bit
18-19 picturing the "DDR select field". The current value b11 is
reserved. The only defined value as of version 6 of the iMX6Q manual was
b00 "DDR3 and LPDDR2 mode". In practice no register difference has been
spotted after changing this configuration but all issues tracked thus
far just vanished. All previous fixes have been proven irrelevant. Just
clearing this field solved all our network issues and the drop rate as
measured by iperf3 felt back to 0%.

Link: https://lore.kernel.org/netdev/20231012193410.3d1812cf@xps-13/
Link: https://lists.freedesktop.org/archives/dri-devel/2023-October/428251.html
Link: 15eb6abbef
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-12 16:33:57 -05:00
Fabio Estevam
5e13f5db4c imx7s-warp-u-boot: Fix aliases and chosen nodes indentation
The aliases and chosen nodes are currently indented using spaces.

Fix them to use the standard tab indentation.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-12-12 16:33:57 -05:00
Fabio Estevam
04b53f1249 pico-pi-imx6ul: Connvert to DM_SERIAL
The conversion to DM_SERIAL is mandatory, so select this option.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-12-12 16:33:57 -05:00
Fabio Estevam
43bf6a692f pico-pi-imx7d: Convert to watchdog driver model
Commit 68dcbdd594 ("ARM: imx: Add weak default reset_cpu()") caused
the 'reset' command in U-Boot to not cause a board reset.

Fix it by switching to the watchdog driver model via sysreset, which
is the preferred method for implementing the watchdog reset

Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-12-12 16:33:57 -05:00
Fabio Estevam
e0dfb34173 imx8mp_evk: Select CONFIG_NET_RANDOM_ETHADDR
On an early revision of the imx8mp-evk that I have access to,
the MAC addresses fuses are not programmed, causing failure to bring
the Ethernet interfaces.

Fix this problema by selecting CONFIG_NET_RANDOM_ETHADDR so that
random MAC addresses are assigned and the Ethernet ports become
functional out of the box.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-12-12 16:33:57 -05:00
Andrejs Cainikovs
32c9dfcc56 apalis-imx8: add USBH_EN gpio hog
USB host interface is not working on some Apalis Toradex carrier
boards with Apalis iMX8 SoM. This is due to USBH_EN pin, which
powers USB peripherals, having a strong pull-down on some boards,
and a weak pull-down on the others. This USBH_EN pin is left
unconfigured, which means it is in its default state at cold boot:
input with a strong pull-up. As a result, carrier boards with a
weak pull-down have this signal high enough to trigger power
delivery to USB peripherals, and opposite - boards with strong
pull-down on USBH_EN have this signal below the threshold needed
to trigger USB power delivery.
This change configures the USBH_EN pin as gpio hog, fixing this
issue for all Apalis carrier boards regardless of pull-down
resistor value.

Also, update apalis-imx8_defconfig via savedefconfig.

Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-12 16:33:53 -05:00
Tim Harvey
ad3a4f91e7 board: gateworks: venice: add fixup for GW73xx-F+
GW73xx-F board revision switched back to the original PCIe switch due to
part availability.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-12 09:21:48 -03:00
Hugo Villeneuve
3d91bc90de arm: dts: imx8mn-var-som: Fix broken EEPROM read
On branch WIP/17Oct2023, the EEPROM can no longer be read:

    U-Boot 2023.10-latest (Oct 17 2023 - 15:53:43 -0400)
    CPU:   Freescale i.MX8MNano Quad rev1.0 at 1200 MHz
    Reset cause: POR
    Model: Variscite VAR-SOM-MX8MN Symphony evaluation board
    var_read_som_eeprom: uclass_get_device_by_of_offset() failed: -19
    initcall failed at call 000000004022207c (err=-19)

Convert EEPROM-related properties to bootph-all so that the EEPROM can
also be read outside of SPL.

Fixes: 9e644284ab ("dm: core: Report bootph-pre-ram/sram node as pre-reloc after relocation")
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-12 09:21:20 -03:00
Tom Rini
65eed68772 test/py: Disable error E0611 in two cases for pylint
Recently pylint has started to complain about:
No name 'fs_helper' in module 'tests' (no-name-in-module)

Due to:
from tests import fs_helper

However, we have:
test/py/tests/fs_helper.py

And since we do not want to add a dummy test/py/tests/__init__.py to
silence this warning we instead just disable it as needed.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-12-09 14:58:21 -05:00
Tom Rini
8737914336 Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
- StarFive: Add StarFive watchdog driver
- VisionFive2: Support device tree overlay for VisionFive2 board
- Andes: Fix PLIC-SW setting
- RISC-V: Fix NVMe support by implying NVME_PCI for QEMU
- RISC-V: Fix binman for 64 bit format load address
2023-12-09 14:35:44 -05:00
Tom Rini
dd29208815 Merge patch series "bootflow: bootmeth_efi: Fix network efi boot."
To quote the author:

Currently bootmeth_efi crashes while doing a network (dhcp) boot.
This patch series fixes issues and both network and disk boot works.

# Do not modify or remove the line above.
# Everything below it will be ignored.
#
# Please enter a commit message to explain why this merge is necessary,
# especially if it merges an updated upstream into a topic branch.
#
# An empty message aborts the commit.
2023-12-09 13:16:14 -05:00
Shantur Rathore
37503b0c0c bootflow: bootmeth_efi: don't free buffer
bootmeth_efi doesn't allocate any buffer to load efi in any case.
enable static buffer flag for all cases.

Reviewed-by: Simon Glass <sjg@chromium.org>

Signed-off-by: Shantur Rathore <i@shantur.com>
2023-12-09 13:16:08 -05:00
Shantur Rathore
184fc0379d bootflow: bootmeth_efi: Handle fdt not available.
While booting with efi, if fdt isn't available externally,
just use the built-in one.

Reviewed-by: Simon Glass <sjg@chromium.org>

Signed-off-by: Shantur Rathore <i@shantur.com>
2023-12-09 13:16:08 -05:00
Shantur Rathore
e31317e161 bootflow: bootmeth_efi: set bflow->fname from bootfile name
We need to set boot->fname before calling efi_set_bootdev
otherwise this crashes as bflow->fname is null.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Shantur Rathore <i@shantur.com>
2023-12-09 13:16:08 -05:00
Shantur Rathore
c5440a6ae8 bootflow: bootmeth_efi: Set bootp_arch as hex
bootmeth_efi sets up bootp_arch which is read later in bootp.c
Currently bootp_arch is being set as integer string and being
read in bootp.c as hex, this sends incorrect arch value to dhcp server
which in return sends wrong file for network boot.

For ARM64 UEFI Arch value is 0xb (11), here we set environment as 11
and later is read as 0x11 and 17 is sent to dhcp server.

Setting it as hex string fixes the problem.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Shantur Rathore <i@shantur.com>
2023-12-09 13:16:08 -05:00
Janne Grunau
6bfd07bf64 arm: apple: t602x: Add missing MMIO regions to memmap
The memory maps for Apple's M2 Pro/Max/Ultra left MMIO space out which
was not used by any driver at the time. The display out exposed as
simple-framebuffer use a power-domain controlled by a device in an
unmapped region.
Add a map covering this region as well as another MMIO region in the
range 0x4'0000'0000 - 0x5'0000'0000. The added regions cover all MMIO
annotated in Apple's device tree in this range.

Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Eric Curtin <ecurtin@redhat.com>
Reviewed-by: Neal Gompa <neal@gompa.dev>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
2023-12-09 09:17:20 -05:00
Tom Rini
cbf048f2b3 Merge tag 'u-boot-amlogic-20231207' of https://source.denx.de/u-boot/custodians/u-boot-amlogic
- Add missing DM_USB_GADGET to amlogic boards
2023-12-08 22:00:24 -05:00
Tom Rini
e9742cb67f Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
The first four patches are actual fixes. The last three patches add
support for the apparently popular OrangePi Zero 3 board: multiple
people seem to be champing at the bit, so I'd rather give them
something real instead of people using random trees they found on the
Internet. It's actually mostly the new defconfig file anyway, so the
chances for regressions are very slim.
2023-12-08 22:00:01 -05:00
Tom Rini
dd638467a4 Merge tag 'efi-2024-01-rc5' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2024-01-rc5

Documentation:

* Update and correct support notes on clang
* sandbox: Fix VPL instructions

UEFI:

* Fix a bug in DisconnectController
* Provide better error messages for missing CONFIG_EFI_CAPSULE_ESL_FILE
* Create EFI memory reservations when booting via ACPI
* Make ACPI tables accessible in EFI app
2023-12-08 19:03:03 -05:00
Neil Armstrong
4005729c0d configs: meson: enable missing DM_USB_GADGET
Since commit b96640cbfb ("ARM: meson: g12a: switch dwc2 otg to DM")
and commit e327e2affd ("ARM: meson: switch AXG & GX dwc2 otg to DM")
Amlogic boards now requires DM_USB_GADGET to have USB Gadget to work.

Add it to the boards configs as returned by:
$ grep -L DM_USB_GADGET $(grep -l CONFIG_USB_GADGET $(grep -l MESON configs/*))

Fixes: b96640cbfb ("ARM: meson: g12a: switch dwc2 otg to DM")
Fixes: e327e2affd ("ARM: meson: switch AXG & GX dwc2 otg to DM")
Link: https://lore.kernel.org/r/20231206-u-boot-m2s-fix-usb-gadget-v1-1-1c4c66cd10f3@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-12-07 09:36:19 +01:00
Andre Przywara
d2e1cc69a2 sunxi: H616: Add OrangePi Zero 3 board support
The OrangePi Zero 3 is a small development board featuring the Allwinner
H618 SoC, shipping with up to 4GB of DRAM, Gigabit Ethernet, a micro-HDMI
connector and two USB sockets.
The board uses LPDDR4 DRAM and an X-Powers AXP313a PMIC, support for
which was recently added to U-Boot.

Add a defconfig file selecting the right drivers and DRAM options.
Since the .dts file was synced from the Linux kernel repo already, we
just need to add one line to the Makefile to actually build the .dtb.

The DRAM parameters were derived from the values found in the BSP DRAM
drivers on the SPI NOR flash.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Mikhail Kalashnikov <iuncuim@gmail.com>
Tested-by: Bob McChesney <bob@electricworry.net>
Tested-by: Stephen Graf <stephen.graf@gmail.com>
2023-12-06 23:09:17 +00:00
Andre Przywara
929f198d07 sunxi: H616: remove default AXP305 selection
The original H616 devices released about three years ago were typically
paired with an X-Powers AXP305 PMIC. Newer devices uses the smaller
AXP313, and there seem to be far more systems with this PMIC around now.

Remove the default AXP305 selection for the H616 SoC from the Kconfig,
and move the PMIC selection into the board defconfig files instead.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-12-06 23:09:17 +00:00
Andre Przywara
9ac57fb3a2 mtd: spi-nor: Add support for zBIT ZB25VQ128
Add support for the zBIT ZB25VQ128 (128M-bit) SPI NOR flash memory chip,
as used on the Xunlong Orange Pi Zero 3 board.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
2023-12-06 23:09:01 +00:00
Chukun Pan
4bf34135fe sunxi: dts: arm64: update emac for Orange Pi Zero 3
The current emac setting is not suitable for Orange Pi Zero 3,
move it back to Orange Pi Zero 2 DT. Also update phy mode and
delay values for emac on Orange Pi Zero 3.
With these changes, Ethernet now looks stable.

Fixes: 95c3b0635e ("sunxi: dts: arm64: update devicetree files from Linux-v6.6-rc6")
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-12-06 23:08:37 +00:00
Stephen Graf
21b8051939 sunxi: correct documentation for SPI flashing
The mtd_debug write does not work in this context. The flashcp command does
work, provides both the erase and write functions and with the verbose
option gives good feedback.

Signed-off-by: Stephen Graf <stephen.graf@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2023-12-06 23:08:37 +00:00
Andre Przywara
0d8ac5644e sunxi: h616: (really) lower SPL stack address to avoid BROM data
When using the USB OTG FEL mode on the Allwinner H616, the BootROM
stores some data at the end of SRAM C. This is also the location where
we place the initial SPL stack, so it will overwrite this data.
We still need the BROM code after running the SPL, so should leave that
area alone.
Interestingly this does not seem to have an adverse effect, I guess on
the "way out" (when we return to FEL after the SPL has run), this data
is not needed by the BROM, for just the trailing end of the USB operation.
However this is still wrong, and we should not clobber BROM data.

Lower the SPL stack address to be situated right below the swap buffers
we use in sunxi-fel: that should be out of the way of everyone else.

This obsoletes a previous commit (eb53e7743c) with the same name:
that one was changing the address in an *unused* macro in sunxi_common.h,
so the previous patch didn't have any effect at all.

Fixes: eb53e7743c ("sunxi: h616: lower SPL stack address to avoid BROM data")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-12-06 23:08:37 +00:00
Andre Przywara
cb3e29805c sunxi: H616: OrangePi Zero 2: enable USB power supply
The OrangePi Zero 2 has a USB VBUS regulator, controlled by pin PC16.
This is correctly described in the DT, but the patches for supporting
this are still pending.

Meanwhile add our good old CONFIG_USB1_VBUS_PIN to the defconfig file,
to enable power on the USB port and allow using a USB flash drive, for
instance.

Fixes: 6acc5fa581 ("sunxi: H616: enable USB support for H616 boards")
Reported-by: Mikhail Kalashnikov <iuncuim@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-12-06 23:08:37 +00:00
John Clark
94533cd9c1 starfive: visionfive2: add device tree overlay support
device tree overlay support requires fdtoverlay_addr_r to be set

before
~~~~~~
Invalid fdtoverlay_addr_r for loading overlays

after
~~~~~
Retrieving file: /boot/overlay/rtc-ds3231.dtbo

Signed-off-by: John Clark <inindev@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-12-06 16:05:39 +08:00
Randolph
866dcd88a0 riscv: binman: fix the load field format
Using /bits/ 64 prefix for 64 bits address

Signed-off-by: Randolph <randolph@andestech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-06 16:05:39 +08:00
Yu Chien Peter Lin
d1b24a6140 riscv: andes: Fix enable register settings of PLICSW
On 32-core platform, hart31 gets stuck at secondary_hart_loop
as the corresponding enable bit is not set in enable_ipi().
We should program the next word (0x2f84) which is assigned
as the enable register of hart31. It should be done in the same
way when we invoke riscv_send_ipi() to trigger software interrupt
on hart31.

The following diagram shows the enable bits of the fixed PLICSW
scheme.

   Pending regs: 0x1000  x---0---0---0---0------0---0
Pending hart ID:             0   1   2   3 ... 30  31
   Interrupt ID:         0   1   2   3   4 ... 31  32
                         |   |   |   |   |      |   |
    Enable regs: 0x2000  x---1---0---0---0-...--0---0---> hart0
                         |   |   |   |   |      |   |
                 0x2080  x---0---1---0---0-...--0---0---> hart1
                         |   |   |   |   |      |   |
                 0x2100  x---0---0---1---0-...--0---0---> hart2
                         |   |   |   |   |      |   |
                 0x2180  x---0---0---0---1-...--0---0---> hart3
                         .   .   .   .   .      .   .
                         .   .   .   .   .      .   .
                         .   .   .   .   .      .   .
                 0x2f00  x---0---0---0---0-...--1---0---> hart30
                         |   |   |   |   |      |   |
                 0x2f80  x---0---0---0---0-...--0---1---> hart31
                         <-------- word 0 -------><--- word 1 --->

This patch includes some cleanups to macros/functions.

Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy")
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Randolph <randolph@andestech.com>
2023-12-06 16:05:39 +08:00
Heinrich Schuchardt
3980baa411 risc-v: qemu: imply NVME_PCI
CONFIG_NVME=y without CONFIG_NVME_PCI=y does not provide working NVMe
support. Instead of implying CONFIG_NVME we must imply CONFIG_NVME_PCI
which will select CONFIG_NVME.

Fixes: e64db0d92e ("riscv: qemu: Enable e1000 and nvme support")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
2023-12-06 16:05:39 +08:00
Chanho Park
21ea9a9dd7 configs: visionfive2: Enable watchdog driver
Enables StarFive Watchdog driver and WDT command.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-12-05 16:40:16 +08:00
Chanho Park
a31622cd64 riscv: dts: jh7110: Add watchdog device tree node
Adds jh7110 watchdog device tree node.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-12-05 16:40:16 +08:00
Chanho Park
da26455098 watchdog: Add StarFive Watchdog driver
Add to support StarFive watchdog driver. The driver is imported from
linux kernel's drivers/watchdog/starfive-wdt.c without jh7100 support
because there is no support of jh7100 SoC in u-boot yet.
Howver, this patch has been kept the variant coding style because JH7100
can be added later and have a consistency with the linux driver.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-12-05 16:40:16 +08:00
Chanho Park
8ef2d7926f clk: starfive: jh7110: Add watchdog clocks
Add JH7110_SYSCLK_WDT_APB and JH7110_SYSCLK_WDT_CORE clocks for JH7110
watchdog device.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-12-05 16:40:16 +08:00
Ilias Apalodimas
6805b4dbad efi_loader: Make DisconnectController follow the EFI spec
commit 239d59a65e ("efi_loader: reconnect drivers on failure")
tried to fix the UninstallProtocol interface which must reconnect
any controllers it disconnected by calling ConnectController()
in case of failure. However, the reconnect functionality was wired in
efi_disconnect_all_drivers() instead of efi_uninstall_protocol().

As a result some SCT tests started failing.
Specifically, BBTestOpenProtocolInterfaceTest333CheckPoint3() test
 - Calls ConnectController for DriverImageHandle1
 - Calls DisconnectController for DriverImageHandle1 which will
   disconnect everything apart from TestProtocol4. That will remain
   open on purpose.
 - Calls ConnectController for DriverImageHandle2. TestProtocol4
   which was explicitly preserved was installed wth BY_DRIVER attributes.
   The new protocol will call DisconnectController since its attributes
   are BY_DRIVER|EXCLUSIVE, but TestProtocol4 will not be removed. The
   test expects EFI_ACCESS_DENIED which works fine.

   The problem is that DisconnectController, will eventually call
   EFI_DRIVER_BINDING_PROTOCOL.Stop(). But on the aforementioned test
   this will call CloseProtocol -- the binding protocol is defined in
   'DBindingDriver3.c' and the .Stop function uses CloseProtocol.
   If that close protocol call fails with EFI_NOT_FOUND, the current code
   will try to mistakenly reconnect all drivers and the subsequent tests
   that rely on the device being disconnected will fail.

Move the reconnection in efi_uninstall_protocol() were it belongs.

Fixes: commit 239d59a65e ("efi_loader: reconnect drivers on failure")
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-12-05 01:38:56 +01:00
Heinrich Schuchardt
1be415b21b efi_loader: create memory reservations in ACPI case
ACPI tables cannot convey memory reservations for ARM and RISC-V.
x86 uses the BIOS E820 table for this purpose. We cannot simply ignore the
device-tree when booting via ACPI. We have to assign EfiReservedMemory
according to the prior stage device-tree ($fdtaddr) or as fallback the
control device-tree ($fdtcontroladdr).

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-05 01:38:56 +01:00
Simon Glass
8c06b27eec efi: Correct display of table GUIDs
The printf() %pU option decodes GUIDs so it is not necessary to do this
first. Drop the incorrect code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-12-05 01:38:56 +01:00
Simon Glass
a900d88e1a efi: Collect the ACPI tables in the app
Locate these so that they can be displayed using the 'acpi' command.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-12-05 01:38:56 +01:00
Masahisa Kojima
f32fee0359 scripts/Makefile.lib: print error when no public key is specified
The current build system embeds the EFI Signature List(ESL)
into the dtb to be used in the EFI capsule authentication.
This ESL file is specified through the CONFIG_EFI_CAPSULE_ESL_FILE
Kconfig option. If CONFIG_EFI_CAPSULE_ESL_FILE is not specified,
U-boot build ends up with failure but the cause of failure is not
easily understandable. Current error message is as follows.

FATAL ERROR: Error reading file into data: Is a directoryCheck /home/ubuntu/src/ledge/u-boot/arch/arm/dts/.synquacer-sc2a11-developerbox.dtb.pre.tmp for errors
make[2]: *** [scripts/Makefile.lib:355: arch/arm/dts/synquacer-sc2a11-developerbox.dtb] Error 1
make[1]: *** [dts/Makefile:44: arch-dtbs] Error 2
make: *** [Makefile:1165: dts/dt.dtb] Error 2
make: *** Waiting for unfinished jobs....

This commit shows the error message that CONFIG_EFI_CAPSULE_ESL_FILE
must be specified when the EFI capsule authentication is enabled, then
terminate the build with error.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Weizhao Ouyang <o451686892@gmail.com>
2023-12-05 01:38:56 +01:00
Mattijs Korpershoek
1e8a8f3232 doc: sending_patches.rst: s/Superseeded/Superseded
This is a common typo listed in scripts/spelling.txt. Fix it to match the
patchwork status, which is superseded.

Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-12-05 01:38:56 +01:00
Tom Rini
463e341348 doc: clang: Update and correct support notes
At this point, clang can be used on both 32bit and 64bit targets without
issue. Make note of logic we have that will inform clang of the
architecture to build for.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-12-05 01:38:56 +01:00
Simon Glass
a6ac50cad5 sandbox: Fix VPL instructions
Fix the devicetree used with sandbox. This is needed because the
default (full) devicetree must be used by all phases of boot, with
sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-12-05 01:38:56 +01:00
Tom Rini
2f0282922b Prepare v2024.01-rc4
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-12-04 13:46:56 -05:00
Heinrich Schuchardt
89cb3a9f0a efi_loader: generated SMBIOS table below 4 GiB
We currently use an outdated format 32-bit format for SMBIOS tables.
So we must allocate SMBIOS tables below 4 GiB.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Tested-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-12-04 13:42:40 -05:00
Tom Rini
e37e6f181e Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-watchdog
- Correct watchdog timeout print message (Chanho Park)
2023-12-04 13:37:18 -05:00
Chanho Park
a341a0e01f watchdog: Correct watchdog timeout print message
The wdt_start function takes timeout_ms as a parameter and starts the
watchdog with this value. However, when you output the message, it shows
the default timeout value for the watchdog device.
So this patch fixes that part to output the correct timeout value.

Before -->
StarFive # wdt start 3000
WDT:   Started watchdog@13070000 without servicing  (60s timeout)

After -->
StarFive # wdt start 3000
WDT:   Started watchdog@13070000 without servicing  (3s timeout)

Fixes: c2fd0ca1a8 ("watchdog: Integrate watchdog triggering into the cyclic framework")
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-12-04 08:09:09 +01:00
Tom Rini
5c4e9d0c74 Merge branch 'master-rpc-off' of https://source.denx.de/u-boot/custodians/u-boot-sh 2023-12-03 16:30:32 -05:00
Tom Rini
b56d21f3bb Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-usb
- USB XHCI fixes
2023-12-02 13:37:27 -05:00
Cong Dang
13bdb6a269 ARM: dts: renesas: Disable RPC driver on R8A779G0 V4H White Hawk board
As requirement of CR side, QSPI Flash usage via RPC driver shall
be disabled and leaving the control of this module to CR side.
Perform DT modification to disable the RPC SPI.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Do not modify defconfig, modify the DT instead, this way
        the RPC SPI can be enabled without recompiling the U-Boot
	itself. Update commit message accordingly.]
2023-12-02 17:16:01 +01:00
Marek Vasut
b95a250805 ARM: dts: renesas: Clean up R8A779G0 V4H RPC SPI DT node
Use the phandle reference to &rpc node in arch/arm/dts/r8a779g0.dtsi
and remove properties which are already in arch/arm/dts/r8a779g0.dtsi.
No functional change and no resulting DT change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-12-02 17:16:01 +01:00
Heinrich Schuchardt
493e0e2577 usb: USB_XHCI_PCI depends on PCI
Compiling with CONFIG_USB_XHCI_PCI and CONFIG_PCI=n results in

    usb/host/xhci-pci.c:48:(.text.xhci_pci_probe+0x44):
    undefined reference to `dm_pci_write_config32

Add the missing Kconfig dependency.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-12-01 16:01:59 +01:00
Jonas Karlman
6e91df96dc usb: dwc3-generic: Use combined glue and ctrl node for RK3588
Like Rockchip RK3328 and RK3568, the RK3588 also have a single node to
represent the glue and ctrl for USB 3.0.

Use rk_ops as driver data to select correct ctrl node for RK3588 DWC3.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-12-01 14:06:12 +01:00
Hector Martin
75aabe595f usb: storage: Use the correct CBW lengths
USB UFI uses fixed 12-byte commands (as does RBC, which is not
supported), but SCSI does not have this limitation. Use the correct
command block lengths depending on the subclass.

Signed-off-by: Hector Martin <marcan@marcan.st>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-12-01 14:06:12 +01:00
Hector Martin
b5999f8f6c usb: hub: Add missing reset recovery delay
Some devices like YubiKeys need more time before SET_ADDRESS. The spec
says we need to wait 10ms.

Signed-off-by: Hector Martin <marcan@marcan.st>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-12-01 14:06:12 +01:00
Hector Martin
a14843fdac usb: xhci: Fix DMA address calculation in queue_trb
We need to get the DMA address before incrementing the pointer, as that
might move us onto another segment.

Signed-off-by: Hector Martin <marcan@marcan.st>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-12-01 14:06:04 +01:00
Hector Martin
2fd7037122 usb: xhci: Do not panic on event timeouts
Now that we always check the return value, just return NULL on timeouts.
We can still log the error since this is a problem, but it's not reason
to panic.

Signed-off-by: Hector Martin <marcan@marcan.st>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-12-01 14:06:04 +01:00
Hector Martin
fb5502be25 usb: xhci: Fail on attempt to queue TRBs to a halted endpoint
This isn't going to work, don't pretend it will and then end up timing
out.

Signed-off-by: Hector Martin <marcan@marcan.st>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-12-01 14:06:04 +01:00
Hector Martin
9d88bd4dcf usb: xhci: Recover from halted bulk endpoints
There is currently no codepath to recover from this case. In principle
we could require that the upper layer do this explicitly, but let's just
do it in xHCI when the next bulk transfer is started, since that
reasonably implies whatever caused the problem has been dealt with.

Signed-off-by: Hector Martin <marcan@marcan.st>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-12-01 14:06:04 +01:00
Hector Martin
6f64f0ae23 usb: xhci: Allow context state errors when halting an endpoint
There is a race where an endpoint may halt by itself while we are trying
to halt it, which results in a context state error. See xHCI 4.6.9 which
mentions this case.

This also avoids BUGging when we attempt to stop an endpoint which was
already stopped to begin with, which is probably a bug elsewhere but
not a good reason to crash.

Signed-off-by: Hector Martin <marcan@marcan.st>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-12-01 14:06:04 +01:00
Hector Martin
2526cd9932 usb: xhci: Better error handling in abort_td()
If the xHC has a problem with our STOP ENDPOINT command, it is likely to
return a completion directly instead of first a transfer event for the
in-progress transfer. Handle that more gracefully.

We still BUG() on the error code, but at least we don't end up timing
out on the event and ending up with unexpected event errors.

Signed-off-by: Hector Martin <marcan@marcan.st>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-12-01 14:06:04 +01:00
Hector Martin
8d1e03f984 usb: xhci: Guard all calls to xhci_wait_for_event
xhci_wait_for_event returns NULL on timeout, so the caller always has to
check for that. This addresses immediate explosions in this part
of the code when timeouts happen, but not the root cause for the
timeout.

Signed-off-by: Hector Martin <marcan@marcan.st>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-12-01 14:06:04 +01:00
Svyatoslav Ryhel
43f2873fa9 MAINTAINERS: Step up as co-maintainer of Tegra SOC platform
Update maintainers for Tegra SoC platform. Include device trees
and drivers which contain tegra in the name.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-11-28 11:23:02 -05:00
Tom Rini
b2bf18d5e5 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-samsung 2023-11-28 10:05:25 -05:00
Philip Oberfichtner
acae7eb5fe i2c: Bugfix in i2c_get_chip_by_phandle()
The "i2cbcdev" sneaked in when implementing this function for the
bootcounter use case. Obviously the intention was to use prop_name
instead.

Fixes: b483552773 (i2c: Implement i2c_get_chip_by_phandle())

Signed-off-by: Philip Oberfichtner <pro@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
2023-11-27 18:54:56 -05:00
Sam Protsenko
470682ace1 configs: Remove unneeded SYS_CONFIG_NAME from a*y17lte defconfigs
As correct default SYS_CONFIG_NAME value is now set in
board/samsung/axy17lte/Kconfig (in commit "board: samsung: Fix
SYS_CONFIG_NAME configs in axy17lte Kconfig"), the SYS_CONFIG_NAME
option can be safely removed from all a*y17lte defconfigs. That removal
doesn't change resulting .config files.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2023-11-27 18:57:35 +09:00
Sam Protsenko
6219b47c4d board: samsung: Fix SYS_CONFIG_NAME configs in axy17lte Kconfig
There is a couple of issues related to SYS_CONFIG_NAME config in
axy17lte Kconfig.

1. The global SYS_CONFIG_NAME in axy17lte Kconfig overrides
   SYS_CONFIG_NAME for all boards specified after this line in
   arch/arm/mach-exynos/Kconfig:

       source "board/samsung/axy17lte/Kconfig"

   Right now it's the last 'source' line there, so the issue is not
   reproducible. But once some board is moved or added after this line
   the next build error will happen:

       GEN     include/autoconf.mk.dep
     In file included from ./include/common.h:16:
     include/config.h:3:10: fatal error: configs/exynos78x0-common.h.h:
                            No such file or directory
         3 | #include <configs/exynos78x0-common.h.h>
           |          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     compilation terminated.

   That's happening because axy17lte Kconfig defines SYS_CONFIG_NAME
   option in global namespace (not guarded with any "if TARGET_..."), so
   it basically rewrites the correct SYS_CONFIG_NAME defined in the
   hypothetical boards which might appear after axy17lte in mach-exynos
   Kconfig.

2. Another side of the issue is that SYS_CONFIG_NAME is defined
   incorrectly in axy17lte Kconfig:

       config SYS_CONFIG_NAME
           default "exynos78x0-common.h"

   The .h extension should not have been specified there. It's leading
   to a build error, as the generated include file has a double '.h'
   extension.

3. Each target in axy17lte/Kconfig defines its own SYS_CONFIG_NAME. But
   all of those in fact incorrect, as corresponding
   include/configs/<CONFIG_SYS_CONFIG_NAME>.h header files don't exist.

4. The global SYS_CONFIG_NAME pretty much repeats the help description
   from arch/Kconfig and doc/README.kconfig.

Corresponding defconfig files (a*y17lte_defconfig) fix above issues by
overriding SYS_CONFIG_NAME and correctly setting it to
"exynos78x0-common".

Fix all mentioned issues by removing the incorrect global
SYS_CONFIG_NAME and instead specifying it (correctly) in SYS_CONFIG_NAME
options for each target instead.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Fixes: 3e2095e960 ("board: samsung: add support for Galaxy A series of 2017 (a5y17lte)")
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2023-11-27 18:57:35 +09:00
Sam Protsenko
33e7ca5a9b serial: s5p: Use dev_read_addr_ptr() to get base address
As the address read from device tree is being cast to a pointer, it's
better to use dev_read_addr_ptr() API for getting that address. The more
detailed explanation can be found in commit a12a73b664 ("drivers: use
dev_read_addr_ptr when cast to pointer").

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2023-11-27 18:04:11 +09:00
Tom Rini
1fcf078f54 Merge tag 'u-boot-dfu-20231124' of https://source.denx.de/u-boot/custodians/u-boot-dfu
u-boot-dfu-20231124

- Fix reinit for ChipIdea controller
- Add missing newline in fastboot error handling
2023-11-25 17:38:43 -05:00
Sam Protsenko
a627f2802a serial: s5p: Improve coding style
Just some minor style fixes. No functional change.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2023-11-23 15:24:18 +09:00
Sam Protsenko
e79f630dbf serial: s5p: Use named constants for register values
Get rid of magic numbers in s5p_serial_init() when writing to UART
registers. While at it, use BIT() macro for existing constants when
appropriate.

No functional change.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2023-11-23 15:24:18 +09:00
Sam Protsenko
5ad21de6ba serial: s5p: Use livetree API to get "id" property
Use dev_read_u8_default() instead of fdtdec_get_int() to read the "id"
property from device tree, as suggested in [1]. dev_* API is already
used in this driver, so there is no reason to stick to fdtdec_* API.
This also fixes checkpatch warning:

    WARNING: Use the livetree API (dev_read_...)

[1] doc/develop/driver-model/livetree.rst

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2023-11-23 15:24:18 +09:00
Sam Protsenko
a0615ffc99 serial: s5p: Remove common.h inclusion
It's not really needed here anymore. Remove it, as common.h is going
away at some point.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2023-11-23 15:24:18 +09:00
Tom Rini
9e53e45292 Merge tag 'efi-2024-01-rc4' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2024-01-rc4

Documentation

* Add HiSilicon board documentation to HTML docs
* Fix building with Sphinx 6.0

UEFI

* Increase default variable store size to 128K
* Check return value of efi_append_scrtm version
* Create shortened boot options in eficonfig command

Other

* Avoid incorrect error message in mkimage
2023-11-21 09:10:15 -05:00
Simon Holesch
6f68dcd025 usb: fastboot: Add missing newline in pr_err
Add missing newline in pr_err.

Signed-off-by: Simon Holesch <simon@holesch.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20231120002024.32865-2-simon@holesch.de
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2023-11-21 09:19:48 +01:00
Simon Holesch
b272c87925 usb: ci: Fix gadget reinit
The ChipIdea device controller wasn't properly cleaned up when disabled.
So enabling it again left it in a broken state. The problem occurred for
example when the host unbinds the driver and binds it again.

During the first setup, when the out request is queued, the endpoint is
primed (`epprime`). If the endpoint is then disabled, it stayed primed
with the initial buffer. So after the endpoint is re-enabled, the device
controller and device driver were out of sync: the new out request was
in the driver queue head, yet not submitted, but the "complete" function
was still called, since the endpoint was primed with the old buffer.

With the fastboot function this error led to the (rather confusing)
error message "buffer overflow".

Fixed by clearing the primed buffers with the `epflush` (`ENDPTFLUSH`)
register.

Signed-off-by: Simon Holesch <simon@holesch.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20231120002024.32865-1-simon@holesch.de
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2023-11-21 09:19:48 +01:00
Heinrich Schuchardt
64658007f3 cmd: eficonfig: create shortened boot options
The boot options created by eficonfig should use shortened device-paths to
avoid problems if drives are enumerated in a different sequence.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-11-20 19:06:22 +01:00
Heinrich Schuchardt
ce68a25448 efi_loader: improve efi_var_from_file() description
It is unclear to developers why efi_var_from_file() returns EFI_SUCCESS if
file ubootefi.var is missing or corrupted. Improve the description.

Reported-by: Weizhao Ouyang <o451686892@gmail.com>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Weizhao Ouyang <o451686892@gmail.com>
2023-11-20 19:06:22 +01:00
Ilias Apalodimas
229f9e77fe efi_loader: Correctly account the SCRTM event creation
The result of efi_append_scrtm_version() is overwritten before anyone
checks its result. Check it and exit the function on failures

Addresses-Coverity-ID: 467399 Code maintainability issues (UNUSED_VALUE)
Fixes: commit 97707f12fd ("tpm: Support boot measurements")
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-11-20 19:06:22 +01:00
Ilias Apalodimas
a8062549d6 efi_loader: Increase default variable store size to 128K
In commit 9fd3f881c6 ("efi_loader: Increase default variable store size to 64KiB")
Alper has a detailed explanation of why the size needs to be bumped to at
least 64K.  However enabling Secure boot, writing db, KEK, PK etc keys
will further increase the size so bump it to 128K.

It's worth noting that when U-Boot stores the EFI variables in an RPMB the
available storage is defined statically in StandAloneMM at build time.
The U-Boot code is detecting the available true size on the fly during
writes. When StandAloneMM is present this size defines the reserved
memory U-Boot can use to copy any runtime variables, before booting an
OS.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-11-20 19:06:22 +01:00
Heinrich Schuchardt
9781ec9840 doc: typo fdtaddr_addr_r
%s/fdtaddr_addr_r/fdt_addr_r/

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-20 19:06:22 +01:00
Jonathan Corbet
dc23eb8e0e docs: Fix the docs build with Sphinx 6.0
Sphinx 6.0 removed the execfile_() function, which we use as part of the
configuration process.  They *did* warn us...  Just open-code the
functionality as is done in Sphinx itself.

Tested (using SPHINX_CONF, since this code is only executed with an
alternative config file) on various Sphinx versions from 2.5 through 6.0.

Reported-by: Martin Liška <mliska@suse.cz>
Cc: stable@vger.kernel.org
Signed-off-by: Jonathan Corbet <corbet@lwn.net>

Rebased for U-Boot
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-11-20 19:06:22 +01:00
Heinrich Schuchardt
63e41659f2 doc: add HiSilicon board documentation to HTML docs
Add the README files for the HiSilicon boards to the HTML documentation.
This required a bit of reformatting.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-11-20 19:06:22 +01:00
Heinrich Schuchardt
2b3b3511bd mkimage: do not write incorrect error message
When running 'mkimage -l' is called for a valid StarFive file an error
message "Error: invalid marker bytes" is written by the Renesas SPKG
driver.

mkimage -l may be invoked without specifying an image type. In this case
mkimage iterates over all image type drivers to find the one that matches.
None of the non-matching drivers should write an error message.

Fix the Renesas SPKG driver.

Fixes: afdfcb11f9 ("tools: spkgimage: add Renesas SPKG format")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-20 19:06:22 +01:00
Tom Rini
24ca49b33a Prepare v2024.01-rc3
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-20 08:43:46 -05:00
Tom Rini
f629d50419 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-20 08:37:27 -05:00
Nikita Yushchenko
beeb91aa64 scsi: set dma direction to NONE for TEST UNIT READY
SCSI device scan code was executing TEST UNIT READY command without
explicitly setting dma direction in struct scsi_cmd to NONE, so command
was passed to driver with dma direction set to DMA_FROM_DEVICE,
inherited from older usage.

With WDC SDINDDH6-64G ufs device, that caused TEST UNIT READY to
return error.

Fix that, by explicitly setting dma direction to NONE for
TEST UNIT READY, and restoring it back DMA_FROM_DEVICE for the
following READ CAPACITY.

Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-11-20 08:34:08 -05:00
Tom Rini
d5ff806cb5 Merge branch 'master-mmc-clock' of https://source.denx.de/u-boot/custodians/u-boot-sh 2023-11-18 10:25:48 -05:00
Tom Rini
cc7bc8237a Merge branch '2023-11-17-assorted-important-fixes'
- Revert HAFDBS changes, correct spl_imx_romapi for eMMC, fix the virtio
  rng in one case, fix bootstd in one case, and correct a Kconfig
  description.
2023-11-17 13:15:33 -05:00
Simon Glass
741d1e9d3f bootstd: Avoid freeing a non-allocated buffer
EFI applications can be very large and thus used to cause boot failures
when malloc() space was exhausted.

A recent changed fixed this by using the kernel_addr_r environment var
as the address of the buffer. However, it still frees the buffer when
the bootflow is discarded.

Fix this by introducing a flag to indicate whether the buffer was
allocated, or not.

Note that kernel_addr_r is not the last word here. It might be better
to use lmb to place images. But there is a lot of refactoring to do
before we can remove the environment variables. The distro scripts rely
on them so it is safe for bootstd to do so too.

Fixes: 6a8c2f9781 bootstd: Avoid allocating memory for the EFI file

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported by: Simon Glass <sjg@chromium.org>
Reported by: Shantur Rathore <i@shantur.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Shantur Rathore <i@shantur.com>
2023-11-17 11:58:26 -05:00
Chris Packham
0585c28fda Revert "arm64: Use FEAT_HAFDBS to track dirty pages when available"
This reverts commit 6cdf6b7a34. This is
part of a series trying to make use of the arm64 hardware features for
tracking dirty pages. Unfortunately this series causes problems for the
AC5/AC5X SoCs. Having exhausted other options the consensus seems to be
reverting this series is the best course of action.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
2023-11-17 11:58:26 -05:00
Chris Packham
eed8294b75 Revert "arm64: Use level-2 for largest block mappings when FEAT_HAFDBS is present"
This reverts commit 836b8d4b20. This is
part of a series trying to make use of the arm64 hardware features for
tracking dirty pages. Unfortunately this series causes problems for the
AC5/AC5X SoCs. Having exhausted other options the consensus seems to be
reverting this series is the best course of action.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
2023-11-17 11:58:26 -05:00
Chris Packham
ee23d7466c Revert "armv8: enable HAFDBS for other ELx when FEAT_HAFDBS is present"
This reverts commit c1da6fdb5c. This is
part of a series trying to make use of the arm64 hardware features for
tracking dirty pages. Unfortunately this series causes problems for the
AC5/AC5X SoCs. Having exhausted other options the consensus seems to be
reverting this series is the best course of action.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
2023-11-17 11:58:26 -05:00
Marcel Ziswiler
ac33a7976a imx: spl_imx_romapi: fix emmc fast boot mode case
This fixes a regression in the eMMC fast boot mode case where the buffer
was missing 464 bytes.

The code figures out how many bytes must at least be fetched to honor
the current read, rounds that up to the ss->pagesize [which is a no-op
in the USB download case because that has ->pagesize==1], fetches that
many bytes, but then recorded the original upper bound as the new end of
the valid data. However, this did not take into account the rounding up
to the ss->pagesize. Fix this by recording the actual bytes downloaded.

Fixes: 4b4472438f ("imx: spl_imx_romapi: avoid tricky use of spl_load_simple_fit() to get full FIT size")
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-11-17 11:58:26 -05:00
Marcel Ziswiler
e2dcadbba4 imx: spl_imx_romapi: fix comment about stream(usb) download failure
Fix comment about Stream(USB) download failure.

Fixes: 1cbebc7862 ("imx: add rom api support")
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-11-17 11:58:26 -05:00
John Keeping
e319ef02fb spl: fix TPL_SYS_MALLOC_F description
This config option enables the malloc() pool in TPL not the SPL.  Fix
the description to accurately reflect this.

Fixes: fd8497dae5 (spl: Create proper symbols for enabling the malloc() pool)
Signed-off-by: John Keeping <jkeeping@inmusicbrands.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-17 11:58:26 -05:00
Andre Przywara
45c4b276f0 virtio: rng: gracefully handle 0 byte returns
According to the virtio v1.x "entropy device" specification, a virtio-rng
device is supposed to always return at least one byte of entropy.
However the virtio v0.9 spec does not mention such a requirement.

The Arm Fixed Virtual Platform (FVP) implementation of virtio-rng always
returns 8 bytes less of entropy than requested. If 8 bytes or less are
requested, it will return 0 bytes.
This behaviour makes U-Boot's virtio_rng_read() implementation go into an
endless loop, hanging the system.

Work around this problem by always requesting 8 bytes more than needed,
but only if a previous call to virtqueue_get_buf() returned 0 bytes.

This should never trigger on a v1.x spec compliant implementation, but
fixes the hang on the Arm FVP.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reported-by: Peter Hoyes <peter.hoyes@arm.com>
2023-11-17 11:58:26 -05:00
Tom Rini
169c3cc49e Merge tag 'dm-pull-15nov23' of https://source.denx.de/u-boot/custodians/u-boot-dm
patman correct import of u_boot_pylib
correct long-standing EFI framebuffer bug
minor test refactor
2023-11-15 14:15:21 -05:00
Simon Glass
0d4d9f94c5 bootstage: Correct exhasuted typo
Correct this typo in the warning message shown when no more bootstage
records can be added.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-14 20:04:01 -07:00
Sean Anderson
f6d76e6878 sandbox: Close file after mmaping it
After opening pathname, we must close ifd once we are done with it.

Fixes: b9274095c2 ("sandbox: Add a way to map a file into memory")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-14 20:04:01 -07:00
Heinrich Schuchardt
2c61c0eb14 dm: Do not enable debug messages by default
CONFIG_DM_WARN has a text indicating that these messages should only
provided when debugging. This implies that the setting must be default no.

We should still create debug messages.

Reported-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-14 20:04:01 -07:00
Simon Glass
abf7004321 patman: Correct Python 3.6 behaviour
The importlib_resources import is not actually used. Fix this so that
patman can run on Python 3.6 to some extent, once
'pip3 install importlib-resources' has been run.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-11-14 20:04:01 -07:00
Simon Glass
dfdf621ff2 patman: Avoid using func_test at top level
Import this only when it is needed, since it is not present when
installed via 'pip install'.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: https://source.denx.de/u-boot/u-boot/-/issues/26
2023-11-14 20:04:01 -07:00
Simon Glass
21229c921b patman: Correct easy pylint warnings in __main__
Tidy up the code a little to reduce the number of pylint warnings.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-11-14 20:04:00 -07:00
Simon Glass
e296a3c73d patman: Move the main program into a function
Add a new run_patman() function to hold the main logic.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-11-14 20:04:00 -07:00
Simon Glass
18f8830ab9 patman: Split out arg parsing into its own file
Move this code into a separate cmdline module, as is done with the
other tools.

Use the same HAS_TESTS check as buildman

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-11-14 20:04:00 -07:00
Simon Glass
cac91b0b72 expo: Correct background colour
Use the correct background colour when using white-on-black.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-11-14 20:04:00 -07:00
Simon Glass
3fa53b9531 bootstd: Add a return code to bootflow menu
Return an error when the user does not select an OS, so we know whether
to boot or not.

Move calling of bootflow_menu_run() into a separate function so we can
call it from other places.

Expand the test to cover these cases.

Add some documentation also, while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-11-14 20:04:00 -07:00
Simon Glass
baea7ec6a6 bootstd: Refactor mmc prep to allow a different scan
Adjust scan_mmc4_bootdev() and related function so that the caller can
do its own 'bootflow scan' command. This allows it to change the flags
if needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-11-14 20:04:00 -07:00
Simon Glass
a75cf70d23 efi: Correct handling of frame buffer
The efi_gop driver uses private fields from the video uclass to obtain a
pointer to the frame buffer. Use the platform data instead.

Check the VIDEO_COPY setting to determine which frame buffer to use. Once
the next stage is running (and making use of U-Boot's EFI boot services)
U-Boot does not handle copying from priv->fb to the hardware framebuffer,
so we must allow EFI to write directly to the hardware framebuffer.

We could provide a function to read this, but it seems better to just
document how it works. The original change ignored an explicit comment
in the video.h file ("Things that are private to the uclass: don't use
these in the driver") which is why this was missed when the VIDEO_COPY
feature was added.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 8f661a5b66 ("efi_loader: gop: Expose fb when 32bpp")
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-11-14 20:04:00 -07:00
Sam Protsenko
f655090901 clk: exynos: Add header guard for clk-pll.h
The clk-pll.h is going to be included in multiple files soon. Add
missing header guard to prevent possible build errors in future.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Fixes: 166097e877 ("clk: exynos: add clock driver for Exynos7420 Soc")
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2023-11-13 16:39:05 +09:00
Sam Protsenko
2227f4c0af serial: s5p: Fix clk_get_by_index() error code check
clk_get_by_index() returns negative number on error. Assigning it to
unsigned int makes the subsequent "ret < 0" check always false, leading
in turn to possible unhandled errors. Change 'ret' variable type to
signed int so the code checks and handles clk_get_by_index() return code
properly.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Fixes: cf75cdf96e ("serial: s5p: use clock api to get clock rate")
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2023-11-13 16:20:58 +09:00
Sam Protsenko
08cfa971a7 exynos: Avoid duplicate reset_cpu with SYSRESET enabled
The sysreset uclass unconditionally provides a definition of the
reset_cpu() function. So does the exynos soc code. Fix the build with
SYSRESET enabled by omitting the function from the soc code in that
case. The code still needs to be kept around for use in SPL.

This commit was inspired by commit 6e19dc84c1 ("sunxi: Avoid duplicate
reset_cpu with SYSRESET enabled").

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2023-11-13 16:19:04 +09:00
Sam Protsenko
11bd2787de watchdog: s5p_wdt: Include missing CPU header
s5p watchdog driver calls samsung_get_base_watchdog() function, but its
prototype is not included. That might lead to build warnings like this:

    drivers/watchdog/s5p_wdt.c: In function 'wdt_stop':
    drivers/watchdog/s5p_wdt.c:16:26:
        warning: implicit declaration of function
        'samsung_get_base_watchdog' [-Wimplicit-function-declaration]
             16 |   (struct s5p_watchdog *)samsung_get_base_watchdog();
                |                          ^~~~~~~~~~~~~~~~~~~~~~~~~

Include asm/arch/cpu.h to fix that issue.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2023-11-13 16:18:01 +09:00
Sam Protsenko
c9ab9f30c8 arm: exynos: Include missing CPU header in gpio.h
arch/arm/include/asm/arch/gpio.h relies on definitions from cpu.h.
Include it explicitly in gpio.h. Otherwise next build error may occur:

    In file included from ./arch/arm/include/asm/gpio.h:7,
                     from include/cros_ec.h:14,
                     from board/samsung/common/board.c:8:
        ./arch/arm/include/asm/arch/gpio.h:1357:4:
              error: 'EXYNOS4_GPIO_PART1_BASE' undeclared here
              (not in a function); did you mean 'EXYNOS4_GPIO_MAX_PORT'?
         1357 |  { EXYNOS4_GPIO_PART1_BASE, EXYNOS4_GPIO_MAX_PORT_PART_1 },
              |    ^~~~~~~~~~~~~~~~~~~~~~~

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2023-11-13 16:18:01 +09:00
Sam Protsenko
585a2aaac2 arm: exynos: Include missing CPU header in soc.c
samsung_get_base_swreset() is called in soc.c, but corresponding header
with its prototype is not included. Fix this to avoid possible build
errors.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2023-11-13 16:18:01 +09:00
Marek Vasut
70d2c9940e mmc: renesas-sdhi: Disable clock after tuning reset when possible
Currently the renesas_sdhi_reset_tuning() unconditionally leaves SDHI
clock enabled after the tuning reset. This is not always necessary.

After the driver performed tuning reset at the end of probe function,
or in the unlikely case that tuning failed during regular operation,
the SDHI clock can be disabled after the tuning reset. The following
set_ios call would reconfigure the clock as needed.

In case of regular set_ios call which requires a tuning reset, keep
the clock enabled or disabled according to the mmc->clk_disable state.

With this in place, the controllers which have not been accessed via
block subsystem after boot are left in quiescent state. However, if an
MMC device is used e.g. for environment storage, that controller would
be accessed during the environment load and left active, including its
clock which would still be generated. This is due to the design of the
MMC subsystem, which does not deinit a controller after it was started
once, the controller is only deinited in case of mmc rescan, or before
OS boot.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Tested-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Thuan Nguyen Hong <thuan.nguyen-hong@banvien.com.vn>
2023-11-13 04:12:47 +01:00
Tom Rini
92b27528d7 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
To quote Andre:

The first few patches are some easy refactorings and fixes, most of them
actually don't change the generated binaries at all. Then there is a
defconfig for a new board, for which we just gained the .dts file from
the last kernel DT sync.
On top there is support for a new PMIC (AXP313), and LPDDR4 support for
the Allwinner H616 SoC, both of which are needed to support new devices
that appeared lately, especially cheap TV boxes.

While those are technically new features, they don't affect existing
boards, for instance the LPDDR4 support code is guarded by a new DRAM
type Kconfig variable. So the risk for regressions is very slim.

Gitlab CI passed, and I booted that briefly on some boards, including an
H616 and an H618 one (with LPDDR4).
2023-11-12 16:36:52 -05:00
Mikhail Kalashnikov
4b02f0120a sunxi: H616: add LPDDR4 DRAM support
The H616 SoC family has support for several types of DRAM: DDR3,
LPDDR3, DDR4 and LPDDR4.
At the moment, the driver only supports DDR3 and LPDDR3 memory.
Let's extend the driver to support the LPDDR4 memory. This type
of memory widely used in device with T507(-H) SoC and new orangepi
zero3 with H618.
The compatibility with T507 is not yet complete, because there
is difference in the phy_init array.
The LPDDR4-2133 timings correspond to DRAM Rayson RS1G32LO4D2BDS-53BT
found on the NOR SPI from the Orangepi Zero 3 4GB.

Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
Tested-by: Piotr Oniszczuk <piotr.oniszczuk@gmail.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Acked-by: Andre Przywara <andre.przywara@arm.com>
2023-11-12 18:04:32 +00:00
Andre Przywara
b71129ca3b sunxi: H616: DRAM: refactor mctl_phy_configure_odt()
The original H616 DDR3 ODT configuration code wrote board specific values
into a sequence of paired registers.
For LPDDR3 support we needed to special-case one group of registers,
because for that DRAM type we need to write 0 into the lower register of
each pair. That already made the code less readable.

LPDDR4 support will make things even messier, so let's refactor that
code now: We allow to write different values into the lower and upper
half of each pair. The masking is moved into a macro, and use in each
write statement.

The effect is not as obvious yet, as we don't need the full flexibility at
the moment, but the motivation will become clearer with LPDDR4 support.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Mikhail Kalashnikov <iuncuim@gmail.com>
2023-11-12 18:03:37 +00:00
Andre Przywara
fafedff350 power: regulator: add AXP313 support
The X-Powers AXP313a is a small PMIC with just three buck converters and
three LDOs, one of which is actually fixed (so not modelled here).

Add the compatible string and the respective regulator ranges to allow
drivers to adjust voltages.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-11-12 16:47:16 +00:00
Andre Przywara
d17d051c54 power: pmic: sunxi: add AXP313 SPL driver
On boards using the AXP313 PMIC, the DRAM rail is often not setup
correctly at reset time, so we have to program the PMIC very early in
the SPL, before running the DRAM initialisation.

Add a simple AXP313 PMIC driver that knows about DCDC2(CPU) and
DCDC3(DRAM), so that we can bump up the voltage before the DRAM init.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-11-12 16:47:16 +00:00
Ludwig Kormann
1f6c98c2d3 arm: dts: icnova-a20-adb4006: Add board support
Add board support for ICnova A20 SomPi compute module on
ICnova ADB4006 development board.

Specification:
SoM
- Processor: Allwinner A20 Cortex-A7 Dual Core at 1GHz
- 512MB DDR3 RAM
- Fast Ethernet (Phy: Realtek RTL8201CP)
ADB4006
- I2C
- 2x USB 2.0
- 1x Fast Ethernet port
- 1x SATA
- 2x buttons (PWRON, Boot)
- 2x LEDS
- serial console
- HDMI
- µSD-Card slot
- Audio Line-In / Line-Out
- GPIO pinheaders

https://wiki.in-circuit.de/index.php5?title=ICnova_ADB4006
https://wiki.in-circuit.de/index.php5?title=ICnova_A20_SODIMM

devicetree upstreamed with linux 6.5

Signed-off-by: Ludwig Kormann <ludwig.kormann@ict42.de>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2023-11-12 16:47:00 +00:00
Samuel Holland
0070d57c33 pinctrl: sunxi: Avoid using .bss for SPL
sunxi platforms put .bss in DRAM, so .bss is not available in SPL before
DRAM controller initialization. Therefore, this buffer must be placed in
the .data section.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2023-11-12 16:46:46 +00:00
Samuel Holland
d379bcbfaf sunxi: mmc: Sort compatible strings numerically
commit 95168d77d3 ("sunxi: add Allwinner R528/T113 SoC support") added
the new entry out of order.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-11-12 16:46:32 +00:00
Samuel Holland
ca43266562 clk: sunxi: Use the right symbol in the Makefile
CONFIG_ARCH_SUNXI will not be enabled for RISC-V SoCs using this driver.
Use the symbol for the driver itself instead.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2023-11-12 16:46:16 +00:00
Samuel Holland
43b573df33 sunxi: mmc: Move header to the driver directory
The MMC controller driver is (and ought to be) the only user of these
register definitions. Put them in a header next to the driver to remove
the dependency on a specific ARM platform's headers.

Due to the sunxi_mmc_init() prototype, the file was not renamed. None of
the register definitions were changed.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-11-12 16:45:08 +00:00
Samuel Holland
7b252df7ca net: sun8i_emac: Drop DM_GPIO checks
DM_GPIO is always enable in U-Boot proper for ARCH_SUNXI, and this
driver is never enabled in SPL, so the condition is always true.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2023-11-12 16:45:03 +00:00
Tom Rini
f054f12089 arm: sunxi: Correct warning in board_fit_config_name_match
When building this with clang, we get a warning about having excess
parenthesis here, or that we're incorrectly using "==" when we want "=".
Correct these by using the common size macro.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[Andre: Use SZ_512M as per Simon's suggestion]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-11-12 12:03:42 +00:00
Andre Przywara
ffb02942fa sunxi: board: simplify early PMIC setup conditions
So far we have a convoluted #ifdef mesh that guards the early AXP PMIC
setup in board.c. That combination of &&, || and negations is very hard
to read, maintain and especially to extend.

Fortunately we have those same conditions already modelled in the
Kconfig file, so they are actually redundant. On top of that the real
reason we have those preprocessor guards in the first place is about the
symbols that are *conditionally* defined: without #ifdefs the build
would break because of them being undefined for many boards.

To simplify this, just change the guards to actually look at the symbols
needed, so CONFIG_AXP_xxx_VOLT instead of CONFIG_AXPyyy_POWER.
This drastically improves the readability of this code, and makes adding
PMIC support a pure Kconfig matter.

Doing this revealed one bug in Kconfig: there is no axp_set_dcdc4() for
the AXP818, even though CONFIG_AXP_DCDC4_VOLT includes that PMIC.
Since the AXP818 wasn't included when calling axp_set_dcdc4() in board.c,
this wasn't an issue, but becomes one now, so also remove the AXP818 from
the DCDC4 Kconfig symbol.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-11-12 12:03:42 +00:00
Tom Rini
17e9db18f1 Merge tag 'doc-2024-01-rc3' of https://source.denx.de/u-boot/custodians/u-boot-efi
Documentation:

* hikey960: update link URLs
* j7200_evm: Fix OPTEE platform name
* ti: fix style of examples
* fix typos
2023-11-11 09:22:54 -05:00
Heinrich Schuchardt
cfaf05839f doc: typo 'form' in qfw.rst
%s/form/from/

Fixes: d46bee8c2d ("doc: qfw man-page")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-11-11 01:44:09 +01:00
Nishanth Menon
ca845d20e6 doc: board: ti: k3 docs: Use ::prompt
Use prompt instead of code-block to have copy-paste friendly command
documentation.

Signed-off-by: Nishanth Menon <nm@ti.com>
2023-11-11 01:44:08 +01:00
Nishanth Menon
81cf99e723 doc: board: ti: Use prompt prompt_style to simplify documentation
The sphinx-prompt documentation[0] provides examples on how we can use
prompt as a parameter to simplify the description. Use the same.

While at it, ensure to make all relevant prompts clarified such as gdb
prompts.

[0] http://sbrunner.github.io/sphinx-prompt/

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-11-11 01:44:08 +01:00
Milan P. Stanić
bd00ef74f3 doc: build: fix wrongly written targests instead of targets
Signed-off-by: Milan P. Stanić <mps@arvanta.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-11-11 01:44:08 +01:00
Heinrich Schuchardt
b214e88071 doc: shorten overlong title underlines
Title underlines should match the length of the title. Unfortunately
docutils only catches underlines that are too short.

Add some missing empty lines after titles.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-11-11 01:44:08 +01:00
Nishanth Menon
0e20948598 doc: ti: j7200_evm: Fix OPTEE platform name
k3-j7200 does not exist in upstream OPTEE. Use j721e as the platform
name. Using k3-j7200 as OPTEE name results in broken boot due to wrong
configuration being picked.

Fixes: c727b81d65 ("doc: board: ti: k3: Reuse build instructions")
Signed-off-by: Nishanth Menon <nm@ti.com>
2023-11-11 01:44:08 +01:00
Dylan Corrales
550a9ffecd hikey960: Fix 404 links
The build instructions for the hikey960 had some broken links. Update
the links to use new vendor URLs. Also change build instructions to
reference a different file name.

Signed-off-by: Dylan Corrales <deathcamel58@gmail.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2023-11-11 01:44:08 +01:00
Tom Rini
da2e3196e4 Merge patch series "arm: dts: k3-am6: Fix Ethernet/DMA"
To quote the author:

Since commit [1], Ethernet is broken on TI AM62 and AM64 platforms.

The commit [1] is not the culprit. It just unearths the problem by fixing
the error check in k3-udma.c. This issue was silently being ignored earlier
due to wrong error check. [NULL instead of FDT_ADDR_T_NONE].

Fix the issue by adding the necessary register spaces for the u-boot K3-UDMA
driver for AM62 and AM64 platforms.

These properties will eventually make it into the SoC DTSi files [2] after
which these can be dropped from k3-*-u-boot.dtsi files.

[1] - 5fecea171de3dd ("treewide: use dev_read_addr_*_ptr() where appropriate")
[2] - https://lore.kernel.org/linux-arm-kernel/20230810174356.3322583-1-vigneshr@ti.com/
2023-11-10 15:25:47 -05:00
Siddharth Vadapalli
62be808183 arm: dts: k3-am642: Update main_bcdma and main_pktdma nodes
Update main_bcdma and main_pktdma nodes for native configuration in the
absence of DM services.

Drop duplicate main_pktdma node in k3-am642-sk-u-boot.dtsi.

Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
2023-11-10 15:25:25 -05:00
Roger Quadros
9a3f2b6798 arm: dts: k3-am625-verdin-wifi-dev-u-boot.dtsi: Fix DMA/Ethernet
Update main_bcdma and main_pktdma nodes for native configuration in the
absence of DM services. u-boot k3-udma driver expects these additional
register fields else probe will fail.

Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2023-11-10 15:25:25 -05:00
Siddharth Vadapalli
d4f148774b arm: dts: k3-am625-sk-u-boot.dtsi: Update main_bcdma and main_pktdma nodes
Update main_bcdma and main_pktdma nodes for native configuration in the
absence of DM services.

Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
2023-11-10 15:25:25 -05:00
Tom Rini
3b913c1482 Merge tag 'u-boot-stm32-20231110' of https://source.denx.de/u-boot/custodians/u-boot-stm
_ Fix compilation issue when SYS_DCACHE_OFF and/or SYS_DCACHE_SYS are enabled
_ Fix issue following DT sync with kernel 6.3 for stm32mp15xx-ev1 and DHSOM SoM
_ Enable TCP, IPv6, wget on DH STM32MP15 DHSOM
_ Limit u-boot.itb size to 0x160000 bytes on DH STM32MP15 DHSOM
_ Read auth stats and boot_partition from tamp
2023-11-10 11:01:51 -05:00
Tom Rini
bb7121f6aa Merge branch '2023-11-10-assorted-fixes'
- Fix some issues Coverity has reported, update MAINTAINERS file,
  another bootstd fix, typo fix in error message, gitignore fix and
  update TI's URL in many places.
2023-11-10 11:01:51 -05:00
Hugo Villeneuve
a3a884c697 boot: Fix syntax in fdt_overlay_apply_verbose() error message
Remove superfluous "did".

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
2023-11-10 11:01:50 -05:00
Sam Protsenko
aff5dddd42 tools: gitignore: Fix tools/generated path
'git status' shows 'tools/generated/' after running the build, which is
wrong. The corresponding .gitignore rule was already added in commit
c623642d29 ("Adjust gitignore for tools/generated/"), but because of
superfluous 'tools/' part it wasn't in effect. Remove incorrect 'tools/'
part to fix it.

While at it, remove tools/ path incorrectly added to the top-level
.gitignore in commit 801c482207 (".gitignore: ignore misc include,
simple-bin, and tools/generated build artifacts"), as it's required in
the comment on the top of .gitignore:

    # NOTE! Don't add files that are generated in specific
    # subdirectories here. Add them in the ".gitignore" file
    # in that subdirectory instead.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Fixes: c623642d29 ("Adjust gitignore for tools/generated/")
Fixes: 801c482207 (".gitignore: ignore misc include, simple-bin, and tools/generated build artifacts")
2023-11-10 11:01:50 -05:00
Tony Dinh
ee2ce29223 bootstd: Skip over bad device during bootflows scanning
During bootstd scanning for bootdevs, if bootdev_hunt_drv() encounters
a device not found error (e.g. ENOENT), let it return a successful status
so that bootstd will continue scanning the next devices, not stopping
prematurely.

Background:

During scanning for bootflows, it's possible for bootstd to encounter a
faulty device controller. Also when the same u-boot is used for another
variant of the same board, some device controller such as SATA might
not exist.

I've found this issue while converting the Marvell Sheevaplug board to
use bootstd. This board has 2 variants, the original Sheevaplug has MMC and
USB only, but the later variant comes with USB, MMC, and eSATA ports. We
have been using the same u-boot (starting with CONFIG_IDE and later with DM
CONFIG_SATA) for both variants. This worked well with the old
envs-scripting booting scheme.

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-10 11:01:50 -05:00
Nishanth Menon
a94a4071d4 tree-wide: Replace http:// link with https:// link for ti.com
Replace instances of http://www.ti.com with https://www.ti.com

Signed-off-by: Nishanth Menon <nm@ti.com>
2023-11-10 11:01:50 -05:00
Alexander Gendin
a40f35f069 test: cmd: mbr: Remove unreachable code
Fix an issue reported by Coverity scan, and fix code indentation.

Addresses-Coverity-ID: 467404 ("Control flow issues (DEADCODE)")
Signed-off-by: Alexander Gendin <agendin@matrox.com>
2023-11-10 11:01:10 -05:00
AKASHI Takahiro
4808d16333 firmware: scmi: correct a validity check against power domain id
A power domain id on sandbox should be in the range from zero to
ARRAY_SIZE(scmi_pwdom) - 1. Correct the validity check logic.

Addresses-Coverity-ID: 467401 ("Out-of-bounds write")
Addresses-Coverity-ID: 467405 ("Out-of-bounds read")
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2023-11-10 10:59:28 -05:00
Tom Rini
d2174dbff1 scsi: Have scsi_init_dev_desc_priv() use memset
When we do not have CONFIG_BOUNCE_BUFFER enabled, inside of
scsi_init_dev_desc_priv we never set the 'bb' field to false, we only
initialize it to true when CONFIG_BOUNCE_BUFFER is set. Given that we
have a number of other fields here we had been explicitly setting to
zero, change to first calling memset to clear the struct and then
initialize only the fields that need non-zero default values.

Addresses-Coverity-ID: 467407 ("Uninitialized variables (UNINIT)")
Fixes: 81bd22e935 ("rockchip: block: blk-uclass: add bounce buffer flag to blk_desc")
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-10 10:59:24 -05:00
Tom Rini
eda45ee3cb Merge tag 'u-boot-rockchip-20231110' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Add Board: rk3588 Pine64 QuartzPro64;
- Fix rk3066 enter download mode;
- Fix for ringneck-px30 board;
2023-11-10 10:58:56 -05:00
Johan Jonker
8ffa9ed295 rockchip: include: asm: fix entering download mode rk3066
Keep track of the re-entries with help of the lr register.
This binary can be re-used and called from various BROM functions.
Only when it's called from the part that handles SPI, NAND or EMMC
hardware it needs to early return to BROM ones.
In download mode when it handles data on USB OTG and UART0
this section must be skipped.

Unlike newer Rockchip SoC models the rk3066 BROM code does not have built-in
support to enter download mode on return to BROM. This binary must check
the boot mode register for the BOOT_BROM_DOWNLOAD flag and reset if it's set.
It then returns to BROM to the end of the function that reads boot blocks.
From there the BROM code goes into a download mode and waits for data
on USB OTG and UART0.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-11-10 10:58:56 -05:00
Quentin Schulz
c7b4881ca4 rockchip: ringneck-px30: enable SPL_BOARD_INIT
Now that Ringneck requires some board-specific code (namely resetting
the MCU companion controller) to be run during SPL stage, let's enable
SPL_BOARD_INIT.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-11-10 10:58:56 -05:00
Quentin Schulz
6acdd63e87 rockchip: ringneck-px30: always reset STM32 companion controller on boot
It's happened that glitches on the STM32_RST and STM32_BOOT lines have
put the STM32 companion microcontroller into DFU mode making it not boot
its FW, rendering it useless for the user.

Considering that the STM32 companion microcontroller is always reset on
a reboot or power cycle, resetting it once again in U-Boot SPL isn't
going to hurt it any more.

For ATtiny companion microcontroller, the situation is a bit different
because a reboot or power cycle doesn't reset it. Additionally, since it
can only be reset with a UPDI reset on the STM32_RST line, and that is
virtually impossible to mistakenly trigger, the ATtiny is unlikely to be
in unwanted reset or enter reset because U-Boot toggles STM32_RST line.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-11-10 10:58:56 -05:00
Tim Lunn
b01adfe59d rockchip: rv1126: Read cpuid from otp and set ethaddr
Provide configuration to read cpuid and generate a persistent
MAC address in ethaddr

Signed-off-by: Tim Lunn <tim@feathertop.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-11-10 10:58:44 -05:00
Tim Lunn
455ad75cb2 rockchip: otp: Add support for RV1126
Extend the otp driver to read rv1126 otp. This driver code was
adapted from the Rockchip BSP stack.

Signed-off-by: Tim Lunn <tim@feathertop.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-11-10 10:58:44 -05:00
Tim Lunn
dae79b870a rockchip: dts: fix bootph tags for rv1126
RV1126 fails to boot on 2024.01-rc1.

Commit 9e644284ab ("dm: core: Report bootph-pre-ram/sram node as
pre-reloc after relocation") changed the behaviour of bootph-pre-ram, to
limit nodes to spl phase. This caused rv1126 boards to fail to boot with
the current dts.

This patch updates the pmu/grf nodes to bootph-all tags as they are
needed in all phases. This fixes the boot issue on rv1126 boards.

Signed-off-by: Tim Lunn <tim@feathertop.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-11-10 10:57:58 -05:00
Sam Protsenko
5069436419 MAINTAINERS: Fix Sam Protsenko mail
Sam works for Linaro again. Use his work e-mail address for ANDROID AB
subsystem.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
2023-11-10 08:44:02 -05:00
Igor Opaniuk
c205fe979e stm32mp1: read auth stats and boot_partition from tamp
Obtain from TAMP backup register information about image authorization
status and partition id used for booting. Store this info in
environmental variables ("boot_auth" and "boot_part" correspondingly).

Image authorization supported values:
0x0 - No authentication done
0x1 - Authentication done and failed
0x2 - Authentication done and succeeded

These values are stored to TAMP backup register by Trusted Firmware-A [1].

Testing:
STM32MP> print boot_part
boot_part=1
STM32MP> print boot_auth
boot_auth=2

[1] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?h=refs/heads/integration&id=ab2b325c1ab895e626d4e11a9f26b9e7c968f8d8

Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Co-developed-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-11-10 13:34:10 +01:00
Marek Vasut
6d84f6bc75 arm: stm32: Limit u-boot.itb size to 0x160000 bytes on DH STM32MP15 DHSOM
The maximum size of u-boot.itb in SPI NOR on DH STM32MP15 DHSOM is
0x160000 . Define this size in U-Boot config to prevent misconfigured
builds from emitting larger u-boot.itb than the one which fits the
SPI NOR area reserved for the blob.

The SPI NOR layout is as follows:
0x00_0000..0x03_ffff ... SPL 1
0x04_0000..0x07_ffff ... SPL 2
0x08_0000..0x1d_ffff ... U-Boot
0x1e_0000..0x1e_ffff ... Environment 1
0x1f_0000..0x1f_ffff ... Environment 2

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-11-10 13:25:18 +01:00
Marek Vasut
55a3faada7 arm: stm32: Enable TCP, IPv6, wget on DH STM32MP15 DHSOM
Enable support for TCP protocol, wget, and IPv6 on this platform.
The former two allow users download payload into the U-Boot from
a web server, which may be more convenient or easier to set up
than TFTP server. The later is enabled to future proof the IP
stack on this platform.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-11-10 13:25:18 +01:00
Marek Vasut
5846ef86f8 ARM: dts: stm32mp: Repair damage from alignment with v6.3
The patch fixed by this commit renders ST STM32MP15xx EV1 board and
all DHSOM SoM based boards unbootable from SPI NOR. Fix the damage
by updating -u-boot.dtsi to match the stm32mp15-pinctrl.dtsi update.

Fixes: 08002ffd08 ("ARM: dts: stm32mp: alignment with v6.3")
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-11-10 13:23:02 +01:00
Bhupesh Sharma
68ea9f0bf1 arm: stm32mp: Really fix compilation issue when SYS_DCACHE_OFF and/or SYS_DCACHE_SYS are enabled
While 23e20b2fa6 ("arm: stm32mp: Fix compilation issue when
SYS_DCACHE_OFF and/or SYS_DCACHE_SYS are enabled") tried fixing
this issue, fix it really by adding #if checks for SYS_ICACHE_OFF
and SYS_DCACHE_OFF.

Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-11-10 13:12:20 +01:00
Quentin Schulz
c41a6deaf2 rockchip: ringneck-px30: enable i2c command
This is a useful tool to check the presence of a device on a specific
i2c bus, so let's enable it.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-11-09 11:19:05 +08:00
Tom Fitzhenry
6761cb5bc2 board: rockchip: add Pine64 QuartzPro64 RK3588 board
QuartzPro64 is a Rockchip RK3588 based SBC by Pine64.

UART and boot over SD/eMMC/RJ45 are tested to work.

Linux commits from next-20231013:
8152d3d070a9 ("arm64: dts: rockchip: Add QuartzPro64 SBC device tree")

Signed-off-by: Tom Fitzhenry <tom@tom-fitzhenry.me.uk>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Cc: Eugen Hristev <eugen.hristev@collabora.com>
Cc: Jonas Karlman <jonas@kwiboo.se>
Cc: Ondrej Jirman <megi@xff.cz>
2023-11-09 11:19:05 +08:00
Tom Rini
e17d174773 Merge tag 'xilinx-for-v2024.01-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2024.01-rc3

xilinx:
- Disable lock in mini spi configurations

zynq:
- DTS syncups
- Kconfig updates

zynqmp:
- DTS syncups
- Kconfig fixups

versal:
- Make 30MHz as default freq for spi

versal net:
- Enable ADMA for mmc

serial:
- Read baudrate from DT

spi:
- Put spi lock under one Kconfig
- Support 64bit addresses in cadance_ospi
- zynqmp_gqspi - change logging support

firmware:
- Handle errors in zynqmp_pm_feature()

include:
- Sync vsc8531 dt binding with kernel
2023-11-07 10:36:23 -05:00
Mattijs Korpershoek
37229edccc MAINTAINERS: fastboot: add Mattijs
Fastboot has been marked as orphaned since 2021.
Since I'm interested in maintaining this, assign myself.

Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Lukasz Majewski <lukma@denx.de>
2023-11-07 08:19:18 -05:00
Mattijs Korpershoek
56fe8f1288 MAINTAINERS: usb gadget: add Mattijs
It seems that Lukasz and Marek could get some help in maintaining the
usb gadget drivers.

Assign myself as maintainer.

Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Lukasz Majewski <lukma@denx.de>
2023-11-07 08:19:17 -05:00
Michal Simek
37f500d711 dt-bindings: Remove VSC8531 specific RGMII delay definitions
Based on Linux upstream discussion value enumeration shouldn't be used.
Instead of it delay in pS should be used that's why remove it from the
header.

Link: https://lore.kernel.org/all/YNsm%2F0dmpBgO8mqr@lunn.ch/
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/bbd343474856a67252f3b31d22b3b5a80ad04043.1698851109.git.michal.simek@amd.com
2023-11-07 13:47:09 +01:00
Michal Simek
6504242df3 arm64: zynqmp: Add description for nvmem efuse layout
Based on discussion with DT folks at link below there is not going to be
any name restrictions for child names. That's why add description for
current nvmem layout.

Link: https://lore.kernel.org/lkml/20231013101450.573-3-praveen.teja.kundanala@amd.com/
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/af81299cafc2bd13ed30dcd69bdf6efb5fbb7f68.1698840373.git.michal.simek@amd.com
2023-11-07 13:47:09 +01:00
Michal Simek
1332a781e1 ARM: zynq: Add partition description
Xilinx is using standard mtd partition layout for quite a long time. It is
used for testing purpose on evaluation boards.
Also #address/size-cells shouldn't be present without nodes which should
use them that's why move them from zynq-7000.dtsi to nand/nor nodes
directly.

The patch was tested on zc706 and zedboard(with also increasing max
frequency and rx bus width).

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/4c3348981bba32d3892194420d78fe8621c47534.1698837725.git.michal.simek@amd.com
2023-11-07 13:47:09 +01:00
Michal Simek
7a64be2ba2 xilinx: Enable SPI_FLASH_MTD by default
Provide access to qspi flash layout via mtd command.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b3c4a3eddb71aab9535b034380d0dbae770828d4.1698837725.git.michal.simek@amd.com
2023-11-07 13:47:09 +01:00
Michal Simek
6e3dbaa0b5 arm64: zynqmp: Comment all smmu entries
SMMU is disabled by default and not all masters can be enabled at the same
time because of limited number of entries. That's why comment all iommu
properties but keep them for reference in DT. In XEN case they should be
added back and Xen should have SMMU enabled by default.
Also add IDs for DP and DPDMA.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/e868c27c52ded5d8ef25f75ba394b1ab3b31b80a.1698825657.git.michal.simek@amd.com
2023-11-07 13:47:09 +01:00
Michal Simek
7faa6b9069 arm64: versal-net: Add DTSes for mini qspi/ospi configuration
Mini U-Boot is running out of OCM and it's only purpose is to program non
volatile memories. There are different configurations which ospi/qspi can
be that's why describe them via DT.
DT binding is already approved that's why there is no reason not to add it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a99a8d72201a782fc811715942dea97fb5ab583b.1698329087.git.michal.simek@amd.com
2023-11-07 13:47:09 +01:00
Michal Simek
0274447bae arm64: versal: Add DTSes for mini qspi/ospi configuration
Mini U-Boot is running out of OCM and it's only purpose is to program non
volatile memories. There are different configurations which ospi/qspi can
be that's why describe them via DT.
DT binding is already approved that's why there is no reason not to add it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/9518ab1c4299a45e800b8611172edd78c9243132.1698329087.git.michal.simek@amd.com
2023-11-07 13:47:09 +01:00
Michal Simek
a787618057 ARM: zynq: Add DTSes for mini qspi configurations
Mini U-Boot is running out of OCM and it's only purpose is to program non
volatile memories. There are different configurations which qspi can be
that's why describe them via DT.
DT binding is already approved that's why there is no reason not to add it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/e7d31a9d9c4a76e171eefc619f31fabd0831a614.1698329087.git.michal.simek@amd.com
2023-11-07 13:47:09 +01:00
Michal Simek
da10dd10e0 ARM: zynq: Add DTSes for mini qspi configurations
Mini U-Boot is running out of OCM and it's only purpose is to program non
volatile memories. There are different configurations which qspi can be
that's why describe them via DT.
DT binding is already approved that's why there is no reason not to add it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/28b3cdd7e91b2b4c3c36d0bf65aa5bac042f248c.1698329087.git.michal.simek@amd.com
2023-11-07 13:47:09 +01:00
Michal Simek
1cd59c571c xilinx: versal: Setup 30MHz as default spi frequency
Align default SPI configuration with ZynqMP/Versal NET.
There is no reason to run on lower frequencies.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c1d6ebd659f3002649b1200c926f8b9ed3132085.1698749448.git.michal.simek@amd.com
2023-11-07 13:47:09 +01:00
Venkatesh Yadav Abbarapu
83cab0b30f arm64: versal-net: enable CONFIG_MMC_SDHCI_ADMA
The Standard Host Controller Interface (SDHCI) specification version
3.00 adds support for Advanced DMA (ADMA) for both 64 and 32 bit
widths of DMA. This significantly improves read and write throughput.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20231027030446.4009-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-11-07 13:47:09 +01:00
Michal Simek
a156b6ce0f arm64: zynqmp: Fix Kconfig entry indentation
Use tabs instead of space for entry indentation which is standard coding
style.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ff28e719de82258c066f1fedae87f88597f367b5.1698302068.git.michal.simek@amd.com
2023-11-07 13:47:09 +01:00
Michal Simek
0d3399dfd8 arm: xilinx: Add missing dual parallel flash description
Describe flash memories based on the latest DT binding.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/cddf2909d0445eba08b998d42ffc31c1fa3132b9.1698045694.git.michal.simek@amd.com
2023-11-07 13:47:09 +01:00
Tejas Bhumkar
820bad0271 arm64: zynqmp: Disable Tri-state for MIO38 Pin
gpio38 is used in SOM's kv260 to reset the Ethernet PHY.
At present, HW reset is not working properly as Tri-state 
is enabled for MIO38, causing inappropriate PHY register reads.

Disabled Tri-state for MIO38 to make HW reset work.

Tri-state disable :
ZynqMP> md 0xFF180208 2
ff180208: 00bfe7a3 00000540

Tri-state enable :
ZynqMP> md 0xFF180208 2
ff180208: 00bfe7e3 00000540

Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar@amd.com>
Link: https://lore.kernel.org/r/20231020050622.972750-1-tejas.arvind.bhumkar@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-11-07 13:47:09 +01:00
Ibai Erkiaga
3e89144892 zynqmp: migrate gqspi debug to logging
The following patch migrates the usage of debug and printf functions
to the relevant logging function as per U-Boot DM guidelines.

Additionally some of the debugging statements have been rearanged for
a more meaningfull debug experience.

aarch64-linux-gnu-size reports 229 bytes less when debug is enabled at
file level, while is just 5bytes more when disabled.

Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@amd.com>
Link: https://lore.kernel.org/r/20231013123739.2757979-1-ibai.erkiaga-elorza@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-11-07 13:47:09 +01:00
Amit Kumar Mahapatra
fdff4b3c48 arm64: dts: zynqmp: make hw-ecc as the default ecc mode
Except for Linux no other component (i.e., u-boot, fsbl or BootRom) of the
software stack supports software ecc engine. So, make hw-ecc as the default
ecc mode.

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/f47b95616eb40d3a9908ca60df94ec6e873b071c.1697119098.git.michal.simek@amd.com
2023-11-07 13:47:09 +01:00
Venkatesh Yadav Abbarapu
03cc435539 ARM: zynq: Disable the config CONFIG_SPI_FLASH_USE_4K_SECTORS
Lock size for the flashes will be in terms of sector size, so
disable the CONFIG_SPI_FLASH_USE_4K_SECTORS and read it from the
flash itself.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/8e5c2bf3b7e5f366c4e261e8055ea254bda53aa9.1697117993.git.michal.simek@amd.com
2023-11-07 13:47:09 +01:00
Venkatesh Yadav Abbarapu
ed1b1dd3bf arm64: zynqmp: Disable the lock option for mini qspi
As mini configs are required only for flashing the images, so
disabling the lock config which will save nearly 6KB of memory.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/374d6b3a46d19b7ee171dfe8071676098db93e25.1697117869.git.michal.simek@amd.com
2023-11-07 13:47:09 +01:00
Piyush Mehta
1bccde607e arm64: zynqmp: remove snps, xhci-stream-quirk property for usb
To sync up with the upstream bulk-stream feature, removed
'snps,xhci-stream-quirk' DT property for usb.

Signed-off-by: Piyush Mehta <piyush.mehta@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1f4ecfe3ea6a4d0d8d8de324f5dffd3efc86656a.1697115523.git.michal.simek@amd.com
2023-11-07 13:47:09 +01:00
Michal Simek
fa6106f989 arm64: zynqmp: Remove address/size-cells from ams node
Remove unused address/size-cells which is also done upstream that's why
this is pretty much sync patch with upstream.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/0ca8d8fe245ad7cb665f5333202d83f70acfc11f.1697115523.git.michal.simek@amd.com
2023-11-07 13:47:09 +01:00
Michal Simek
e6b5c01a6c Revert "arm64: zynqmp: Add power domain description for PL"
This reverts commit d59fac2f3f.

This power domain shouldn't be enabled by default. Power domain behavior
should be handled on case by case basis. Adding this property to
zynqmp.dtsi is breaking some suspend/resume cases that's why remove it
from this file.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/7ed2a46383c6918fbbaca2d618459b1ee58f865c.1697115523.git.michal.simek@amd.com
2023-11-07 13:47:09 +01:00
Michal Simek
ff31d0330d arm64: zynqmp: Remove xlnx,zynqmp-aes node
AES can be discovered via firmware interface that's why remove node for it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/eaf575a6ca92f8c10cefb447c08c1292025deb74.1697115523.git.michal.simek@amd.com
2023-11-07 13:47:09 +01:00
Michal Simek
f87696afa0 arm64: zynqmp: Use mdio node by vp-x-a2785-00-revA and vpk120-revA
All boards have been converted to use mdio node that's why move ethernet
phys under mdio node too.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/6c60f5d29b9d9992bd0130fd263c8ed13cb8166c.1697115523.git.michal.simek@amd.com
2023-11-07 13:47:09 +01:00
Michal Simek
971a772624 arm64: zynqmp: Remove fclk driver
fclk will never go upstream that's why removing this node from DT.
All PL (programmable logic) based IPs should handle clocks self without
using this workaround.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/fbb8665b8a58dbe96349abfe5492a509939e165b.1697098930.git.michal.simek@amd.com
2023-11-07 13:47:08 +01:00
Venkatesh Yadav Abbarapu
20d1836eea spi: cadence_ospi_versal: Add support for 64-bit address
When 64-bit address is passed only lower 32-bit address
is getting updated. Program the upper 32-bit address in the
DMA destination memory address MSBs register.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20231011031515.4151-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-11-07 13:47:08 +01:00
Venkatesh Yadav Abbarapu
ba9bdfd959 drivers: firmware: Handle error case in the zynqmp_pm_feature
Unhandled error coming from xilinx_pm_request() but return
value is not read back that's why getting sparse warning
as below:
warning: variable 'ret' set but not used [-Wunused-but-set-variable].
In case of error return the "ret" value.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20231011025647.17200-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-11-07 13:47:08 +01:00
Venkatesh Yadav Abbarapu
dea1c089cf arm64: versal_net: Disable the lock option for mini ospi and qspi
As mini configs are required only for flashing the images, so
disabling the lock config which will save nearly 6KB of memory.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20231003031715.5343-4-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-11-07 13:47:08 +01:00
Venkatesh Yadav Abbarapu
534892c22c arm64: versal: Disable the lock option for mini ospi and qspi
As mini configs are required only for flashing the images, so
disabling the lock config which will save nearly 6KB of memory.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20231003031715.5343-3-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-11-07 13:47:08 +01:00
Venkatesh Yadav Abbarapu
188c803d08 mtd: spi-nor: Add spi flash lock config option
Provide an explicit configuration option to disable default "lock"
of any flash chip which supports locking. By disabling the lock
config will save some amount of memory and also don't expose the
lock functionality to the users i.e., via sf protect command.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20231003031715.5343-2-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-11-07 13:47:08 +01:00
Algapally Santosh Sagar
bd9ff681bd serial: zynqmp: Fetch baudrate from dtb and update
The baudrate configured in .config is taken by default by serial. If
change of baudrate is required then the .config needs to changed and
u-boot recompilation is required or the u-boot environment needs to be
updated.

To avoid this, support is added to fetch the baudrate directly from the
device tree file and update.
The serial, prints the log with the configured baudrate in the dtb.
The commit c4df0f6f31 ("arm: mvebu: Espressobin: Set default value for
$fdtfile env variable") is taken as reference for changing the default
environment variable.

The default environment stores the default baudrate value, When default
baudrate and dtb baudrate are not same glitches are seen on the serial.
So, the environment also needs to be updated with the dtb baudrate to
avoid the glitches on the serial.

Also add test to cover this new function.

Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20230921112043.3144726-3-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-11-07 13:47:08 +01:00
Algapally Santosh Sagar
8819892bdb configs: Add support in Kconfig and convert for armada boards
Move the DEFAULT_ENV_IS_RW to Kconfig for easier configuration.
Hence, add the CONFIG_DEFAULT_ENV_IS_RW config to the defconfig files
to allow enabling them for armada boards.

Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20230921112043.3144726-2-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-11-07 13:47:08 +01:00
747 changed files with 10249 additions and 5698 deletions

View File

@@ -1 +1 @@
--find-maintainer-files --maintainer-path=.
--find-maintainer-files --git --maintainer-path=.

1
.gitignore vendored
View File

@@ -61,7 +61,6 @@ fit-dtb.blob*
# Generated files
#
/spl/
/tools/generated/
/tpl/
/defconfig

View File

@@ -327,7 +327,7 @@ config SPL_SYS_MALLOC_F_LEN
malloc() region in SDRAM once it is inited.
config TPL_SYS_MALLOC_F
bool "Enable malloc() pool in SPL"
bool "Enable malloc() pool in TPL"
depends on SYS_MALLOC_F && TPL
default y if SPL_SYS_MALLOC_F
help

View File

@@ -58,10 +58,10 @@ F: lib/acpi/
ANDROID AB
M: Igor Opaniuk <igor.opaniuk@gmail.com>
R: Sam Protsenko <joe.skb7@gmail.com>
R: Sam Protsenko <semen.protsenko@linaro.org>
S: Maintained
F: boot/android_ab.c
F: cmd/ab_select.c
F: common/android_ab.c
F: doc/android/ab.rst
F: include/android_ab.h
F: test/py/tests/test_android/test_ab.py
@@ -117,7 +117,7 @@ F: drivers/mmc/snps_dw_mmc.c
APPLE M1 SOC SUPPORT
M: Mark Kettenis <kettenis@openbsd.org>
S: Maintained
F: arch/arm/include/asm/arch-m1/
F: arch/arm/include/asm/arch-apple/
F: arch/arm/mach-apple/
F: configs/apple_m1_defconfig
F: drivers/iommu/apple_dart.c
@@ -667,11 +667,15 @@ F: drivers/video/sunxi/
F: tools/sunxi*
ARM TEGRA
M: Tom Warren <twarren@nvidia.com>
M: Thierry Reding <treding@nvidia.com>
M: Svyatoslav Ryhel <clamor95@gmail.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-tegra.git
F: arch/arm/mach-tegra/
F: arch/arm/dts/tegra*
F: arch/arm/include/asm/arch-tegra*/
F: arch/arm/mach-tegra/
F: drivers/*/tegra*
F: drivers/*/tegra*/
ARM TI
M: Tom Rini <trini@konsulko.com>
@@ -687,6 +691,7 @@ F: arch/arm/include/asm/arch-omap*/
F: arch/arm/include/asm/ti-common/
F: board/ti/
F: drivers/dma/ti*
F: drivers/dma/ti*/
F: drivers/firmware/ti_sci.*
F: drivers/gpio/omap_gpio.c
F: drivers/memory/ti-aemif.c
@@ -698,6 +703,7 @@ F: drivers/phy/omap-usb2-phy.c
F: drivers/phy/phy-ti-am654.c
F: drivers/phy/ti-pipe3-phy.c
F: drivers/ram/k3*
F: drivers/ram/k3*/
F: drivers/remoteproc/ipu_rproc.c
F: drivers/remoteproc/k3_system_controller.c
F: drivers/remoteproc/pruc_rpoc.c
@@ -950,6 +956,7 @@ F: include/cyclic.h
DFU
M: Lukasz Majewski <lukma@denx.de>
M: Mattijs Korpershoek <mkorpershoek@baylibre.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-dfu.git
F: cmd/dfu.c
@@ -1025,8 +1032,10 @@ ENVIRONMENT
M: Joe Hershberger <joe.hershberger@ni.com>
S: Maintained
F: env/
F: include/env/
F: include/env*
F: test/env/
F: tools/env/
F: tools/env*
F: tools/mkenvimage.c
@@ -1056,7 +1065,8 @@ F: test/common/event.c
F: test/py/tests/test_event_dump.py
FASTBOOT
S: Orphaned
M: Mattijs Korpershoek <mkorpershoek@baylibre.com>
S: Maintained
F: cmd/fastboot.c
F: doc/android/fastboot*.rst
F: include/fastboot.h
@@ -1523,7 +1533,6 @@ F: cmd/stackprot_test.c
F: test/py/tests/test_stackprotector.py
TARGET_BCMNS3
M: Bharat Gooty <bharat.gooty@broadcom.com>
M: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
S: Maintained
F: board/broadcom/bcmns3/

View File

@@ -3,7 +3,7 @@
VERSION = 2024
PATCHLEVEL = 01
SUBLEVEL =
EXTRAVERSION = -rc2
EXTRAVERSION =
NAME =
# *DOCUMENTATION*

View File

@@ -2,7 +2,7 @@
/*
* Cortex-R Memory Protection Unit specific code
*
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/

View File

@@ -93,16 +93,10 @@ u64 get_tcr(u64 *pips, u64 *pva_bits)
if (el == 1) {
tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE;
if (gd->arch.has_hafdbs)
tcr |= TCR_EL1_HA | TCR_EL1_HD;
} else if (el == 2) {
tcr = TCR_EL2_RSVD | (ips << 16);
if (gd->arch.has_hafdbs)
tcr |= TCR_EL2_HA | TCR_EL2_HD;
} else {
tcr = TCR_EL3_RSVD | (ips << 16);
if (gd->arch.has_hafdbs)
tcr |= TCR_EL3_HA | TCR_EL3_HD;
}
/* PTWs cacheable, inner/outer WBWA and inner shareable */
@@ -206,9 +200,6 @@ static void __cmo_on_leaves(void (*cmo_fn)(unsigned long, unsigned long),
attrs != PTE_BLOCK_MEMTYPE(MT_NORMAL_NC))
continue;
if (gd->arch.has_hafdbs && (pte & (PTE_RDONLY | PTE_DBM)) != PTE_DBM)
continue;
end = va + BIT(level2shift(level)) - 1;
/* No intersection with RAM? */
@@ -318,7 +309,7 @@ static void map_range(u64 virt, u64 phys, u64 size, int level,
for (i = idx; size; i++) {
u64 next_size, *next_table;
if (level >= gd->arch.first_block_level &&
if (level >= 1 &&
size >= map_size && !(virt & (map_size - 1))) {
if (level == 3)
table[i] = phys | attrs | PTE_TYPE_PAGE;
@@ -357,12 +348,6 @@ static void add_map(struct mm_region *map)
if (va_bits < 39)
level = 1;
if (!gd->arch.first_block_level)
gd->arch.first_block_level = 1;
if (gd->arch.has_hafdbs)
attrs |= PTE_DBM | PTE_RDONLY;
map_range(map->virt, map->phys, map->size, level,
(u64 *)gd->arch.tlb_addr, attrs);
}
@@ -376,7 +361,7 @@ static void count_range(u64 virt, u64 size, int level, int *cntp)
for (i = idx; size; i++) {
u64 next_size;
if (level >= gd->arch.first_block_level &&
if (level >= 1 &&
size >= map_size && !(virt & (map_size - 1))) {
virt += map_size;
size -= map_size;
@@ -414,16 +399,7 @@ static int count_ranges(void)
__weak u64 get_page_table_size(void)
{
u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
u64 size, mmfr1;
asm volatile("mrs %0, id_aa64mmfr1_el1" : "=r" (mmfr1));
if ((mmfr1 & 0xf) == 2) {
gd->arch.has_hafdbs = true;
gd->arch.first_block_level = 2;
} else {
gd->arch.has_hafdbs = false;
gd->arch.first_block_level = 1;
}
u64 size;
/* Account for all page tables we would need to cover our memory map */
size = one_pt * count_ranges();

View File

@@ -194,6 +194,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3588) += \
rk3588-nanopc-t6.dtb \
rk3588s-orangepi-5.dtb \
rk3588-orangepi-5-plus.dtb \
rk3588-quartzpro64.dtb \
rk3588s-rock-5a.dtb \
rk3588-rock-5b.dtb
@@ -376,6 +377,12 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-cse-nand.dtb \
zynq-cse-nor.dtb \
zynq-cse-qspi-single.dtb \
zynq-cse-qspi-parallel.dtb \
zynq-cse-qspi-stacked.dtb \
zynq-cse-qspi-x1-single.dtb \
zynq-cse-qspi-x1-stacked.dtb \
zynq-cse-qspi-x2-single.dtb \
zynq-cse-qspi-x2-stacked.dtb \
zynq-dlc20-rev1.0.dtb \
zynq-microzed.dtb \
zynq-minized.dtb \
@@ -417,6 +424,13 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-mini-emmc1.dtb \
zynqmp-mini-nand.dtb \
zynqmp-mini-qspi.dtb \
zynqmp-mini-qspi-parallel.dtb \
zynqmp-mini-qspi-single.dtb \
zynqmp-mini-qspi-stacked.dtb \
zynqmp-mini-qspi-x1-single.dtb \
zynqmp-mini-qspi-x1-stacked.dtb \
zynqmp-mini-qspi-x2-single.dtb \
zynqmp-mini-qspi-x2-stacked.dtb \
zynqmp-sc-revB.dtb \
zynqmp-sc-revC.dtb \
zynqmp-sc-vek280-revA.dtbo \
@@ -467,13 +481,27 @@ dtb-$(CONFIG_ARCH_VERSAL) += \
versal-mini-emmc0.dtb \
versal-mini-emmc1.dtb \
versal-mini-ospi-single.dtb \
versal-mini-ospi-stacked.dtb \
versal-mini-qspi-parallel.dtb \
versal-mini-qspi-single.dtb \
versal-mini-qspi-stacked.dtb \
versal-mini-qspi-x1-single.dtb \
versal-mini-qspi-x1-stacked.dtb \
versal-mini-qspi-x2-single.dtb \
versal-mini-qspi-x2-stacked.dtb \
xilinx-versal-virt.dtb
dtb-$(CONFIG_ARCH_VERSAL_NET) += \
versal-net-mini.dtb \
versal-net-mini-emmc.dtb \
versal-net-mini-ospi-single.dtb \
versal-net-mini-ospi-stacked.dtb \
versal-net-mini-qspi-single.dtb \
versal-net-mini-qspi-parallel.dtb \
versal-net-mini-qspi-stacked.dtb \
versal-net-mini-qspi-x1-single.dtb \
versal-net-mini-qspi-x1-stacked.dtb \
versal-net-mini-qspi-x2-single.dtb \
versal-net-mini-qspi-x2-stacked.dtb \
xilinx-versal-net-virt.dtb
dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \
zynqmp-r5.dtb
@@ -693,6 +721,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-haoyu-marsboard.dtb \
sun7i-a20-hummingbird.dtb \
sun7i-a20-i12-tvbox.dtb \
sun7i-a20-icnova-a20-adb4006.dtb \
sun7i-a20-icnova-swac.dtb \
sun7i-a20-itead-ibox.dtb \
sun7i-a20-lamobo-r1.dtb \
@@ -806,6 +835,7 @@ dtb-$(CONFIG_MACH_SUN50I_H6) += \
sun50i-h6-tanix-tx6-mini.dtb
dtb-$(CONFIG_MACH_SUN50I_H616) += \
sun50i-h616-orangepi-zero2.dtb \
sun50i-h618-orangepi-zero3.dtb \
sun50i-h616-x96-mate.dtb
dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-amarula-relic.dtb \
@@ -1480,6 +1510,8 @@ targets += $(dtb-y)
# Add any required device tree compiler flags here
DTC_FLAGS += -a 0x8
DTC_FLAGS_imx8mp-dhcom-pdk3-overlay-rev100 += -Wno-avoid_default_addr_size -Wno-reg_format
PHONY += dtbs
dtbs: $(addprefix $(obj)/, $(dtb-y))
@:

View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am33xx-u-boot.dtsi"

View File

@@ -5,7 +5,7 @@
/*
* AM335x Starter Kit
* http://www.ti.com/tool/tmdssk3358
* https://www.ti.com/tool/tmdssk3358
*/
/dts-v1/;

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am33xx-u-boot.dtsi"

View File

@@ -5,7 +5,7 @@
/*
* AM335x ICE V2 board
* http://www.ti.com/tool/tmdsice3359
* https://www.ti.com/tool/tmdsice3359
*/
/dts-v1/;

View File

@@ -3,7 +3,7 @@
* Heiko Schocher <hs@denx.de>
*
* Based on:
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as

View File

@@ -2,7 +2,7 @@
* Copyright (C) 2014 DENX Software Engineering GmbH
* Heiko Schocher <hs@denx.de>
*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as

View File

@@ -3,7 +3,7 @@
* Heiko Schocher <hs@denx.de>
*
* Based on:
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as

View File

@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2021 Sancloud Ltd
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2021 SanCloud Ltd
*/

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2021 SanCloud Ltd
*/
/dts-v1/;

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am4372-u-boot.dtsi"

View File

@@ -2,7 +2,7 @@
/*
* Device Tree Source for Generic AM4372 EVM
*
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
/{

View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am4372-u-boot.dtsi"

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am4372-u-boot.dtsi"

View File

@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am57xx-idk-common-u-boot.dtsi"

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2014-2019 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2014-2019 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;

View File

@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am57xx-idk-common-u-boot.dtsi"

View File

@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am57xx-idk-common-u-boot.dtsi"

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"

View File

@@ -52,6 +52,8 @@
&nfc0 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
nand@0 {
reg = <0>;
};

View File

@@ -2,7 +2,7 @@
/*
* da850-lcdk U-Boot Additions
*
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"

View File

@@ -93,6 +93,12 @@
&gpio4 {
bootph-some-ram;
usbh_en {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-high;
};
};
&gpio5 {

View File

@@ -6,6 +6,12 @@
usb0 = &usbotg1;
display0 = &lcdif;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
bootph-pre-ram;
};
};
&usbotg1 {
@@ -45,6 +51,10 @@
};
};
&wdog1 {
bootph-pre-ram;
};
&iomuxc {
pinctrl_backlight: backlight {
fsl,pins = <

View File

@@ -1,12 +1,12 @@
/ {
aliases {
mmc0 = &usdhc3;
usb0 = &usbotg1;
};
aliases {
mmc0 = &usdhc3;
usb0 = &usbotg1;
};
chosen {
stdout-path = &uart1;
};
chosen {
stdout-path = &uart1;
};
};
&aips3 {

View File

@@ -77,10 +77,59 @@
&gpio2 {
bootph-pre-ram;
dsi-reset-hog {
bootph-pre-ram;
gpio-hog;
output-high;
gpios = <2 GPIO_ACTIVE_LOW>;
line-name = "DSI_RESET_1V8#";
};
dsi-irq-hog {
bootph-pre-ram;
gpio-hog;
input;
gpios = <3 GPIO_ACTIVE_LOW>;
line-name = "DSI_IRQ_1V8#";
};
graphics-prsnt-hog {
bootph-pre-ram;
gpio-hog;
input;
gpios = <7 GPIO_ACTIVE_LOW>;
line-name = "GRAPHICS_PRSNT_1V8#";
};
};
&gpio3 {
bootph-pre-ram;
bl-enable-hog {
bootph-pre-ram;
gpio-hog;
output-low;
gpios = <0 GPIO_ACTIVE_HIGH>;
line-name = "BL_ENABLE_1V8";
};
tft-enable-hog {
bootph-pre-ram;
gpio-hog;
output-low;
gpios = <6 GPIO_ACTIVE_HIGH>;
line-name = "TFT_ENABLE_1V8";
};
graphics-gpio0-hog {
bootph-pre-ram;
gpio-hog;
input;
gpios = <7 GPIO_ACTIVE_HIGH>;
line-name = "GRAPHICS_GPIO0_1V8";
};
};
&gpio4 {

View File

@@ -39,11 +39,11 @@
};
&i2c1 {
bootph-pre-ram;
bootph-all;
};
&pinctrl_i2c1 {
bootph-pre-ram;
bootph-all;
};
&pinctrl_pmic {
@@ -83,5 +83,5 @@
};
&eeprom_som {
bootph-pre-ram;
bootph-all;
};

View File

@@ -67,10 +67,58 @@
&gpio3 {
bootph-pre-ram;
bl-enable-hog {
bootph-pre-ram;
gpio-hog;
output-low;
gpios = <0 GPIO_ACTIVE_HIGH>;
line-name = "BL_ENABLE_1V8";
};
tft-enable-hog {
bootph-pre-ram;
gpio-hog;
output-low;
gpios = <6 GPIO_ACTIVE_HIGH>;
line-name = "TFT_ENABLE_1V8";
};
graphics-gpio0-hog {
bootph-pre-ram;
gpio-hog;
input;
gpios = <7 GPIO_ACTIVE_HIGH>;
line-name = "GRAPHICS_GPIO0_1V8";
};
};
&gpio4 {
bootph-pre-ram;
dsi-reset-hog {
bootph-pre-ram;
gpio-hog;
output-high;
gpios = <0 GPIO_ACTIVE_LOW>;
line-name = "DSI_RESET_1V8#";
};
graphics-prsnt-hog {
bootph-pre-ram;
gpio-hog;
input;
gpios = <18 GPIO_ACTIVE_LOW>;
line-name = "GRAPHICS_PRSNT_1V8#";
};
dsi-irq-hog {
bootph-pre-ram;
gpio-hog;
input;
gpios = <19 GPIO_ACTIVE_LOW>;
line-name = "DSI_IRQ_1V8#";
};
};
&gpio5 {

View File

@@ -126,7 +126,30 @@
bootph-all;
};
&main_bcdma {
reg = <0x00 0x485c0100 0x00 0x100>,
<0x00 0x4c000000 0x00 0x20000>,
<0x00 0x4a820000 0x00 0x20000>,
<0x00 0x4aa40000 0x00 0x20000>,
<0x00 0x4bc00000 0x00 0x100000>,
<0x00 0x48600000 0x00 0x8000>,
<0x00 0x484a4000 0x00 0x2000>,
<0x00 0x484c2000 0x00 0x2000>;
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt",
"ringrt" , "cfg", "tchan", "rchan";
};
&main_pktdma {
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
<0x00 0x4aa00000 0x00 0x20000>,
<0x00 0x4b800000 0x00 0x200000>,
<0x00 0x485e0000 0x00 0x10000>,
<0x00 0x484a0000 0x00 0x2000>,
<0x00 0x484c0000 0x00 0x2000>,
<0x00 0x48430000 0x00 0x1000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
"cfg", "tchan", "rchan", "rflow";
bootph-all;
};

View File

@@ -1,19 +1,20 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* This file was generated with the
* AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.08
* Fri Jun 09 2023 08:01:37 GMT+0200 (Central European Summer Time)
* AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.10
* Mon Dec 11 2023 17:07:35 GMT+0100 (Central European Standard Time)
* DDR Type: LPDDR4
* F0 = 50MHz F1 = NA F2 = 800MHz
* Density (per channel): 16Gb
* Write DBI: Enable
* Number of Ranks: 1
*/
*/
#define DDRSS_PLL_FHS_CNT 3
#define DDRSS_PLL_FREQUENCY_1 400000000
#define DDRSS_PLL_FREQUENCY_2 400000000
#define DDRSS_CTL_0_DATA 0x00000B00
#define DDRSS_CTL_1_DATA 0x00000000
#define DDRSS_CTL_2_DATA 0x00000000
@@ -54,20 +55,20 @@
#define DDRSS_CTL_37_DATA 0x00000000
#define DDRSS_CTL_38_DATA 0x0000040C
#define DDRSS_CTL_39_DATA 0x00000000
#define DDRSS_CTL_40_DATA 0x0000081C
#define DDRSS_CTL_40_DATA 0x00000A1C
#define DDRSS_CTL_41_DATA 0x00000000
#define DDRSS_CTL_42_DATA 0x0000081C
#define DDRSS_CTL_42_DATA 0x00000A1C
#define DDRSS_CTL_43_DATA 0x00000000
#define DDRSS_CTL_44_DATA 0x05000804
#define DDRSS_CTL_45_DATA 0x00000B00
#define DDRSS_CTL_46_DATA 0x09090004
#define DDRSS_CTL_47_DATA 0x00000204
#define DDRSS_CTL_47_DATA 0x00000304
#define DDRSS_CTL_48_DATA 0x00370008
#define DDRSS_CTL_49_DATA 0x09090024
#define DDRSS_CTL_50_DATA 0x00001910
#define DDRSS_CTL_50_DATA 0x00002110
#define DDRSS_CTL_51_DATA 0x00370008
#define DDRSS_CTL_52_DATA 0x09090024
#define DDRSS_CTL_53_DATA 0x09001910
#define DDRSS_CTL_53_DATA 0x09002110
#define DDRSS_CTL_54_DATA 0x000A0A09
#define DDRSS_CTL_55_DATA 0x0400036D
#define DDRSS_CTL_56_DATA 0x09092004
@@ -223,19 +224,19 @@
#define DDRSS_CTL_206_DATA 0x00000000
#define DDRSS_CTL_207_DATA 0x00000000
#define DDRSS_CTL_208_DATA 0x00000024
#define DDRSS_CTL_209_DATA 0x00000012
#define DDRSS_CTL_209_DATA 0x0000001A
#define DDRSS_CTL_210_DATA 0x00000000
#define DDRSS_CTL_211_DATA 0x00000024
#define DDRSS_CTL_212_DATA 0x00000012
#define DDRSS_CTL_212_DATA 0x0000001A
#define DDRSS_CTL_213_DATA 0x00000000
#define DDRSS_CTL_214_DATA 0x00000004
#define DDRSS_CTL_215_DATA 0x00000000
#define DDRSS_CTL_216_DATA 0x00000000
#define DDRSS_CTL_217_DATA 0x00000024
#define DDRSS_CTL_218_DATA 0x00000012
#define DDRSS_CTL_218_DATA 0x0000001A
#define DDRSS_CTL_219_DATA 0x00000000
#define DDRSS_CTL_220_DATA 0x00000024
#define DDRSS_CTL_221_DATA 0x00000012
#define DDRSS_CTL_221_DATA 0x0000001A
#define DDRSS_CTL_222_DATA 0x00000000
#define DDRSS_CTL_223_DATA 0x00000000
#define DDRSS_CTL_224_DATA 0x00000031
@@ -268,21 +269,21 @@
#define DDRSS_CTL_251_DATA 0x00000000
#define DDRSS_CTL_252_DATA 0x00000000
#define DDRSS_CTL_253_DATA 0x00000000
#define DDRSS_CTL_254_DATA 0x46004646
#define DDRSS_CTL_255_DATA 0x00002746
#define DDRSS_CTL_256_DATA 0x00000027
#define DDRSS_CTL_257_DATA 0x00000027
#define DDRSS_CTL_258_DATA 0x00000027
#define DDRSS_CTL_259_DATA 0x00000027
#define DDRSS_CTL_260_DATA 0x00000027
#define DDRSS_CTL_254_DATA 0x44004444
#define DDRSS_CTL_255_DATA 0x00004D44
#define DDRSS_CTL_256_DATA 0x0000004D
#define DDRSS_CTL_257_DATA 0x0000004D
#define DDRSS_CTL_258_DATA 0x0000004D
#define DDRSS_CTL_259_DATA 0x0000004D
#define DDRSS_CTL_260_DATA 0x0000004D
#define DDRSS_CTL_261_DATA 0x00000000
#define DDRSS_CTL_262_DATA 0x00000000
#define DDRSS_CTL_263_DATA 0x0000000F
#define DDRSS_CTL_264_DATA 0x0000000F
#define DDRSS_CTL_265_DATA 0x0000000F
#define DDRSS_CTL_266_DATA 0x0000000F
#define DDRSS_CTL_267_DATA 0x0000000F
#define DDRSS_CTL_268_DATA 0x0000000F
#define DDRSS_CTL_263_DATA 0x0000004D
#define DDRSS_CTL_264_DATA 0x0000004D
#define DDRSS_CTL_265_DATA 0x0000004D
#define DDRSS_CTL_266_DATA 0x0000004D
#define DDRSS_CTL_267_DATA 0x0000004D
#define DDRSS_CTL_268_DATA 0x0000004D
#define DDRSS_CTL_269_DATA 0x00000000
#define DDRSS_CTL_270_DATA 0x00001000
#define DDRSS_CTL_271_DATA 0x00000015
@@ -388,13 +389,13 @@
#define DDRSS_CTL_371_DATA 0x01000101
#define DDRSS_CTL_372_DATA 0x01010001
#define DDRSS_CTL_373_DATA 0x00010101
#define DDRSS_CTL_374_DATA 0x01050503
#define DDRSS_CTL_374_DATA 0x01070703
#define DDRSS_CTL_375_DATA 0x05020201
#define DDRSS_CTL_376_DATA 0x08080C0C
#define DDRSS_CTL_377_DATA 0x00080308
#define DDRSS_CTL_378_DATA 0x000B030E
#define DDRSS_CTL_379_DATA 0x000B0310
#define DDRSS_CTL_380_DATA 0x0B0B0810
#define DDRSS_CTL_378_DATA 0x0009030E
#define DDRSS_CTL_379_DATA 0x00090312
#define DDRSS_CTL_380_DATA 0x09090806
#define DDRSS_CTL_381_DATA 0x01000000
#define DDRSS_CTL_382_DATA 0x03020301
#define DDRSS_CTL_383_DATA 0x04000102
@@ -416,7 +417,7 @@
#define DDRSS_CTL_399_DATA 0x00003690
#define DDRSS_CTL_400_DATA 0x00007940
#define DDRSS_CTL_401_DATA 0x070D0402
#define DDRSS_CTL_402_DATA 0x00260405
#define DDRSS_CTL_402_DATA 0x00260607
#define DDRSS_CTL_403_DATA 0x00000C20
#define DDRSS_CTL_404_DATA 0x00000200
#define DDRSS_CTL_405_DATA 0x00000200
@@ -425,7 +426,7 @@
#define DDRSS_CTL_408_DATA 0x00003690
#define DDRSS_CTL_409_DATA 0x00007940
#define DDRSS_CTL_410_DATA 0x070D0402
#define DDRSS_CTL_411_DATA 0x00000405
#define DDRSS_CTL_411_DATA 0x00000607
#define DDRSS_CTL_412_DATA 0x00000000
#define DDRSS_CTL_413_DATA 0x0302000A
#define DDRSS_CTL_414_DATA 0x01000500
@@ -609,8 +610,8 @@
#define DDRSS_PI_169_DATA 0x00020043
#define DDRSS_PI_170_DATA 0x02000200
#define DDRSS_PI_171_DATA 0x00000004
#define DDRSS_PI_172_DATA 0x0000080C
#define DDRSS_PI_173_DATA 0x00081C00
#define DDRSS_PI_172_DATA 0x00000A0C
#define DDRSS_PI_173_DATA 0x000A1C00
#define DDRSS_PI_174_DATA 0x001C0000
#define DDRSS_PI_175_DATA 0x00000013
#define DDRSS_PI_176_DATA 0x00000059
@@ -624,15 +625,15 @@
#define DDRSS_PI_184_DATA 0x01000100
#define DDRSS_PI_185_DATA 0x00000100
#define DDRSS_PI_186_DATA 0x00000000
#define DDRSS_PI_187_DATA 0x05050503
#define DDRSS_PI_187_DATA 0x05070703
#define DDRSS_PI_188_DATA 0x01010C0C
#define DDRSS_PI_189_DATA 0x01010101
#define DDRSS_PI_190_DATA 0x000C0C0A
#define DDRSS_PI_191_DATA 0x00000000
#define DDRSS_PI_192_DATA 0x00000000
#define DDRSS_PI_193_DATA 0x04000000
#define DDRSS_PI_194_DATA 0x04020808
#define DDRSS_PI_195_DATA 0x04040204
#define DDRSS_PI_194_DATA 0x06020808
#define DDRSS_PI_195_DATA 0x04040206
#define DDRSS_PI_196_DATA 0x00090031
#define DDRSS_PI_197_DATA 0x00110039
#define DDRSS_PI_198_DATA 0x00110039
@@ -661,13 +662,13 @@
#define DDRSS_PI_221_DATA 0x00001900
#define DDRSS_PI_222_DATA 0x32000056
#define DDRSS_PI_223_DATA 0x06000101
#define DDRSS_PI_224_DATA 0x001D0204
#define DDRSS_PI_225_DATA 0x32120058
#define DDRSS_PI_224_DATA 0x001F0204
#define DDRSS_PI_225_DATA 0x72400056
#define DDRSS_PI_226_DATA 0x05000101
#define DDRSS_PI_227_DATA 0x001D0408
#define DDRSS_PI_228_DATA 0x32120058
#define DDRSS_PI_227_DATA 0x001F0608
#define DDRSS_PI_228_DATA 0x72400056
#define DDRSS_PI_229_DATA 0x05000101
#define DDRSS_PI_230_DATA 0x00000408
#define DDRSS_PI_230_DATA 0x00000608
#define DDRSS_PI_231_DATA 0x05040900
#define DDRSS_PI_232_DATA 0x00060900
#define DDRSS_PI_233_DATA 0x00000315
@@ -741,23 +742,23 @@
#define DDRSS_PI_301_DATA 0x00000000
#define DDRSS_PI_302_DATA 0x00000000
#define DDRSS_PI_303_DATA 0x00000000
#define DDRSS_PI_304_DATA 0x00100F27
#define DDRSS_PI_304_DATA 0x00104D4D
#define DDRSS_PI_305_DATA 0x00000000
#define DDRSS_PI_306_DATA 0x00000024
#define DDRSS_PI_307_DATA 0x00000012
#define DDRSS_PI_307_DATA 0x0000001A
#define DDRSS_PI_308_DATA 0x000000B1
#define DDRSS_PI_309_DATA 0x00000000
#define DDRSS_PI_310_DATA 0x00000000
#define DDRSS_PI_311_DATA 0x46000000
#define DDRSS_PI_312_DATA 0x00150F27
#define DDRSS_PI_311_DATA 0x44000000
#define DDRSS_PI_312_DATA 0x00154D4D
#define DDRSS_PI_313_DATA 0x00000000
#define DDRSS_PI_314_DATA 0x00000024
#define DDRSS_PI_315_DATA 0x00000012
#define DDRSS_PI_315_DATA 0x0000001A
#define DDRSS_PI_316_DATA 0x000000B1
#define DDRSS_PI_317_DATA 0x00000000
#define DDRSS_PI_318_DATA 0x00000000
#define DDRSS_PI_319_DATA 0x46000000
#define DDRSS_PI_320_DATA 0x00150F27
#define DDRSS_PI_319_DATA 0x44000000
#define DDRSS_PI_320_DATA 0x00154D4D
#define DDRSS_PI_321_DATA 0x00000000
#define DDRSS_PI_322_DATA 0x00000004
#define DDRSS_PI_323_DATA 0x00000000
@@ -765,23 +766,23 @@
#define DDRSS_PI_325_DATA 0x00000000
#define DDRSS_PI_326_DATA 0x00000000
#define DDRSS_PI_327_DATA 0x00000000
#define DDRSS_PI_328_DATA 0x00100F27
#define DDRSS_PI_328_DATA 0x00104D4D
#define DDRSS_PI_329_DATA 0x00000000
#define DDRSS_PI_330_DATA 0x00000024
#define DDRSS_PI_331_DATA 0x00000012
#define DDRSS_PI_331_DATA 0x0000001A
#define DDRSS_PI_332_DATA 0x000000B1
#define DDRSS_PI_333_DATA 0x00000000
#define DDRSS_PI_334_DATA 0x00000000
#define DDRSS_PI_335_DATA 0x46000000
#define DDRSS_PI_336_DATA 0x00150F27
#define DDRSS_PI_335_DATA 0x44000000
#define DDRSS_PI_336_DATA 0x00154D4D
#define DDRSS_PI_337_DATA 0x00000000
#define DDRSS_PI_338_DATA 0x00000024
#define DDRSS_PI_339_DATA 0x00000012
#define DDRSS_PI_339_DATA 0x0000001A
#define DDRSS_PI_340_DATA 0x000000B1
#define DDRSS_PI_341_DATA 0x00000000
#define DDRSS_PI_342_DATA 0x00000000
#define DDRSS_PI_343_DATA 0x46000000
#define DDRSS_PI_344_DATA 0x00150F27
#define DDRSS_PI_343_DATA 0x44000000
#define DDRSS_PI_344_DATA 0x00154D4D
#define DDRSS_PHY_0_DATA 0x04F00000
#define DDRSS_PHY_1_DATA 0x00000000
#define DDRSS_PHY_2_DATA 0x00030200
@@ -856,8 +857,8 @@
#define DDRSS_PHY_71_DATA 0x00000000
#define DDRSS_PHY_72_DATA 0x041F07FF
#define DDRSS_PHY_73_DATA 0x00000000
#define DDRSS_PHY_74_DATA 0x01CC0B01
#define DDRSS_PHY_75_DATA 0x1003CC0B
#define DDRSS_PHY_74_DATA 0x01FF0B01
#define DDRSS_PHY_75_DATA 0x1003FF0B
#define DDRSS_PHY_76_DATA 0x20000140
#define DDRSS_PHY_77_DATA 0x07FF0200
#define DDRSS_PHY_78_DATA 0x0000DD01
@@ -872,7 +873,7 @@
#define DDRSS_PHY_87_DATA 0x02020010
#define DDRSS_PHY_88_DATA 0x51516041
#define DDRSS_PHY_89_DATA 0x31C06000
#define DDRSS_PHY_90_DATA 0x07AB0340
#define DDRSS_PHY_90_DATA 0x06B60340
#define DDRSS_PHY_91_DATA 0x0000C0C0
#define DDRSS_PHY_92_DATA 0x04050000
#define DDRSS_PHY_93_DATA 0x00000504
@@ -1112,8 +1113,8 @@
#define DDRSS_PHY_327_DATA 0x00000000
#define DDRSS_PHY_328_DATA 0x041F07FF
#define DDRSS_PHY_329_DATA 0x00000000
#define DDRSS_PHY_330_DATA 0x01CC0B01
#define DDRSS_PHY_331_DATA 0x1003CC0B
#define DDRSS_PHY_330_DATA 0x01FF0B01
#define DDRSS_PHY_331_DATA 0x1003FF0B
#define DDRSS_PHY_332_DATA 0x20000140
#define DDRSS_PHY_333_DATA 0x07FF0200
#define DDRSS_PHY_334_DATA 0x0000DD01
@@ -1128,7 +1129,7 @@
#define DDRSS_PHY_343_DATA 0x02020010
#define DDRSS_PHY_344_DATA 0x51516041
#define DDRSS_PHY_345_DATA 0x31C06000
#define DDRSS_PHY_346_DATA 0x07AB0340
#define DDRSS_PHY_346_DATA 0x06B60340
#define DDRSS_PHY_347_DATA 0x0000C0C0
#define DDRSS_PHY_348_DATA 0x04050000
#define DDRSS_PHY_349_DATA 0x00000504
@@ -1326,7 +1327,7 @@
#define DDRSS_PHY_541_DATA 0x003F0000
#define DDRSS_PHY_542_DATA 0x000F013F
#define DDRSS_PHY_543_DATA 0x0000000F
#define DDRSS_PHY_544_DATA 0x020002CC
#define DDRSS_PHY_544_DATA 0x020002FF
#define DDRSS_PHY_545_DATA 0x00030000
#define DDRSS_PHY_546_DATA 0x00000300
#define DDRSS_PHY_547_DATA 0x00000300
@@ -1582,7 +1583,7 @@
#define DDRSS_PHY_797_DATA 0x00000000
#define DDRSS_PHY_798_DATA 0x000F0000
#define DDRSS_PHY_799_DATA 0x0000000F
#define DDRSS_PHY_800_DATA 0x020002CC
#define DDRSS_PHY_800_DATA 0x020002FF
#define DDRSS_PHY_801_DATA 0x00030000
#define DDRSS_PHY_802_DATA 0x00000300
#define DDRSS_PHY_803_DATA 0x00000300
@@ -1838,7 +1839,7 @@
#define DDRSS_PHY_1053_DATA 0x10000000
#define DDRSS_PHY_1054_DATA 0x000F0000
#define DDRSS_PHY_1055_DATA 0x0000000F
#define DDRSS_PHY_1056_DATA 0x020002CC
#define DDRSS_PHY_1056_DATA 0x020002FF
#define DDRSS_PHY_1057_DATA 0x00030000
#define DDRSS_PHY_1058_DATA 0x00000300
#define DDRSS_PHY_1059_DATA 0x00000300
@@ -2169,22 +2170,22 @@
#define DDRSS_PHY_1384_DATA 0x00000300
#define DDRSS_PHY_1385_DATA 0x00000300
#define DDRSS_PHY_1386_DATA 0x00000300
#define DDRSS_PHY_1387_DATA 0x3183BF77
#define DDRSS_PHY_1387_DATA 0x31833F77
#define DDRSS_PHY_1388_DATA 0x00000000
#define DDRSS_PHY_1389_DATA 0x0C000DFF
#define DDRSS_PHY_1390_DATA 0x30000DFF
#define DDRSS_PHY_1391_DATA 0x3F0DFF11
#define DDRSS_PHY_1392_DATA 0x01990000
#define DDRSS_PHY_1393_DATA 0x780DFFCC
#define DDRSS_PHY_1389_DATA 0x0C000DBF
#define DDRSS_PHY_1390_DATA 0x30000DBF
#define DDRSS_PHY_1391_DATA 0x3F0DBF11
#define DDRSS_PHY_1392_DATA 0x01FF0000
#define DDRSS_PHY_1393_DATA 0x780DBFFF
#define DDRSS_PHY_1394_DATA 0x00000C11
#define DDRSS_PHY_1395_DATA 0x00018011
#define DDRSS_PHY_1396_DATA 0x0089FF00
#define DDRSS_PHY_1397_DATA 0x000C3F11
#define DDRSS_PHY_1398_DATA 0x01990000
#define DDRSS_PHY_1399_DATA 0x000C3F11
#define DDRSS_PHY_1400_DATA 0x01990000
#define DDRSS_PHY_1401_DATA 0x3F0DFF11
#define DDRSS_PHY_1402_DATA 0x01990000
#define DDRSS_PHY_1398_DATA 0x01FF0000
#define DDRSS_PHY_1399_DATA 0x000C3F91
#define DDRSS_PHY_1400_DATA 0x01FF0000
#define DDRSS_PHY_1401_DATA 0x3F0DBF11
#define DDRSS_PHY_1402_DATA 0x01FF0000
#define DDRSS_PHY_1403_DATA 0x00018011
#define DDRSS_PHY_1404_DATA 0x0089FF00
#define DDRSS_PHY_1405_DATA 0x20040004

View File

@@ -42,6 +42,33 @@
bootph-all;
};
&main_bcdma {
reg = <0x00 0x485c0100 0x00 0x100>,
<0x00 0x4c000000 0x00 0x20000>,
<0x00 0x4a820000 0x00 0x20000>,
<0x00 0x4aa40000 0x00 0x20000>,
<0x00 0x4bc00000 0x00 0x100000>,
<0x00 0x48600000 0x00 0x8000>,
<0x00 0x484a4000 0x00 0x2000>,
<0x00 0x484c2000 0x00 0x2000>;
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt",
"ringrt" , "cfg", "tchan", "rchan";
};
&main_pktdma {
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
<0x00 0x4aa00000 0x00 0x20000>,
<0x00 0x4b800000 0x00 0x200000>,
<0x00 0x485e0000 0x00 0x10000>,
<0x00 0x484a0000 0x00 0x2000>,
<0x00 0x484c0000 0x00 0x2000>,
<0x00 0x48430000 0x00 0x1000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
"cfg", "tchan", "rchan", "rflow";
bootph-all;
};
&cpsw3g {
bootph-all;
};

View File

@@ -48,6 +48,18 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00 0x00 0x00100000 0x20000>;
phy_gmii_sel: phy@4044 {
compatible = "ti,am654-phy-gmii-sel";
reg = <0x4044 0x8>;
#phy-cells = <1>;
};
epwm_tbclk: clock-controller@4130 {
compatible = "ti,am62-epwm-tbclk";
reg = <0x4130 0x4>;
#clock-cells = <1>;
};
};
dmss: bus@48000000 {
@@ -69,6 +81,67 @@
interrupt-names = "rx_012";
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
};
inta_main_dmss: interrupt-controller@48000000 {
compatible = "ti,sci-inta";
reg = <0x00 0x48000000 0x00 0x100000>;
#interrupt-cells = <0>;
interrupt-controller;
interrupt-parent = <&gic500>;
msi-controller;
ti,sci = <&dmsc>;
ti,sci-dev-id = <28>;
ti,interrupt-ranges = <6 70 34>;
ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
};
main_bcdma: dma-controller@485c0100 {
compatible = "ti,am64-dmss-bcdma";
reg = <0x00 0x485c0100 0x00 0x100>,
<0x00 0x4c000000 0x00 0x20000>,
<0x00 0x4a820000 0x00 0x20000>,
<0x00 0x4aa40000 0x00 0x20000>,
<0x00 0x4bc00000 0x00 0x100000>;
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
msi-parent = <&inta_main_dmss>;
#dma-cells = <3>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <26>;
ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
};
main_pktdma: dma-controller@485c0000 {
compatible = "ti,am64-dmss-pktdma";
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
<0x00 0x4aa00000 0x00 0x40000>,
<0x00 0x4b800000 0x00 0x400000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
msi-parent = <&inta_main_dmss>;
#dma-cells = <2>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <30>;
ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
<0x24>, /* CPSW_TX_CHAN */
<0x25>, /* SAUL_TX_0_CHAN */
<0x26>; /* SAUL_TX_1_CHAN */
ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
<0x11>, /* RING_CPSW_TX_CHAN */
<0x12>, /* RING_SAUL_TX_0_CHAN */
<0x13>; /* RING_SAUL_TX_1_CHAN */
ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
<0x2b>, /* CPSW_RX_CHAN */
<0x2d>, /* SAUL_RX_0_CHAN */
<0x2f>, /* SAUL_RX_1_CHAN */
<0x31>, /* SAUL_RX_2_CHAN */
<0x33>; /* SAUL_RX_3_CHAN */
ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
<0x2c>, /* FLOW_CPSW_RX_CHAN */
<0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
<0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
};
};
dmsc: system-controller@44043000 {
@@ -77,8 +150,8 @@
reg-names = "debug_messages";
ti,host-id = <12>;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 12>,
<&secure_proxy_main 13>;
mboxes = <&secure_proxy_main 12>,
<&secure_proxy_main 13>;
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
@@ -96,6 +169,21 @@
};
};
secure_proxy_sa3: mailbox@43600000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
reg = <0x00 0x43600000 0x00 0x10000>,
<0x00 0x44880000 0x00 0x20000>,
<0x00 0x44860000 0x00 0x20000>;
/*
* Marked Disabled:
* Node is incomplete as it is meant for bootloaders and
* firmware on non-MPU processors
*/
status = "disabled";
};
main_pmx0: pinctrl@f4000 {
compatible = "pinctrl-single";
reg = <0x00 0xf4000 0x00 0x2ac>;
@@ -104,6 +192,102 @@
pinctrl-single,function-mask = <0xffffffff>;
};
main_timer0: timer@2400000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2400000 0x00 0x400>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 36 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 36 2>;
assigned-clock-parents = <&k3_clks 36 3>;
power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer1: timer@2410000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2410000 0x00 0x400>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 37 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 37 2>;
assigned-clock-parents = <&k3_clks 37 3>;
power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer2: timer@2420000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2420000 0x00 0x400>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 38 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 38 2>;
assigned-clock-parents = <&k3_clks 38 3>;
power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer3: timer@2430000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2430000 0x00 0x400>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 39 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 39 2>;
assigned-clock-parents = <&k3_clks 39 3>;
power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer4: timer@2440000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2440000 0x00 0x400>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 40 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 40 2>;
assigned-clock-parents = <&k3_clks 40 3>;
power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer5: timer@2450000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2450000 0x00 0x400>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 41 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 41 2>;
assigned-clock-parents = <&k3_clks 41 3>;
power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer6: timer@2460000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2460000 0x00 0x400>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 42 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 42 2>;
assigned-clock-parents = <&k3_clks 42 3>;
power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer7: timer@2470000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2470000 0x00 0x400>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 43 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 43 2>;
assigned-clock-parents = <&k3_clks 43 3>;
power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_uart0: serial@2800000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
@@ -222,6 +406,39 @@
status = "disabled";
};
main_spi0: spi@20100000 {
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
reg = <0x00 0x20100000 0x00 0x400>;
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 141 0>;
status = "disabled";
};
main_spi1: spi@20110000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x20110000 0x00 0x400>;
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 142 0>;
status = "disabled";
};
main_spi2: spi@20120000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x20120000 0x00 0x400>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 143 0>;
status = "disabled";
};
main_gpio_intr: interrupt-controller@a00000 {
compatible = "ti,sci-intr";
reg = <0x00 0x00a00000 0x00 0x800>;
@@ -295,4 +512,368 @@
no-1-8-v;
status = "disabled";
};
usbss0: dwc3-usb@f900000 {
compatible = "ti,am62-usb";
reg = <0x00 0x0f900000 0x00 0x800>;
clocks = <&k3_clks 161 3>;
clock-names = "ref";
ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>;
#address-cells = <2>;
#size-cells = <2>;
power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
ranges;
status = "disabled";
usb0: usb@31000000 {
compatible = "snps,dwc3";
reg = <0x00 0x31000000 0x00 0x50000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
interrupt-names = "host", "peripheral";
maximum-speed = "high-speed";
dr_mode = "otg";
};
};
usbss1: dwc3-usb@f910000 {
compatible = "ti,am62-usb";
reg = <0x00 0x0f910000 0x00 0x800>;
clocks = <&k3_clks 162 3>;
clock-names = "ref";
ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
#address-cells = <2>;
#size-cells = <2>;
power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
ranges;
status = "disabled";
usb1: usb@31100000 {
compatible = "snps,dwc3";
reg = <0x00 0x31100000 0x00 0x50000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
<GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
interrupt-names = "host", "peripheral";
maximum-speed = "high-speed";
dr_mode = "otg";
};
};
fss: bus@fc00000 {
compatible = "simple-bus";
reg = <0x00 0x0fc00000 0x00 0x70000>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
ospi0: spi@fc40000 {
compatible = "ti,am654-ospi", "cdns,qspi-nor";
reg = <0x00 0x0fc40000 0x00 0x100>,
<0x05 0x00000000 0x01 0x00000000>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x0>;
clocks = <&k3_clks 75 7>;
assigned-clocks = <&k3_clks 75 7>;
assigned-clock-parents = <&k3_clks 75 8>;
assigned-clock-rates = <166666666>;
power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
};
};
cpsw3g: ethernet@8000000 {
compatible = "ti,am642-cpsw-nuss";
#address-cells = <2>;
#size-cells = <2>;
reg = <0x0 0x8000000 0x0 0x200000>;
reg-names = "cpsw_nuss";
ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
clocks = <&k3_clks 13 0>;
assigned-clocks = <&k3_clks 13 3>;
assigned-clock-parents = <&k3_clks 13 11>;
clock-names = "fck";
power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
dmas = <&main_pktdma 0xc600 15>,
<&main_pktdma 0xc601 15>,
<&main_pktdma 0xc602 15>,
<&main_pktdma 0xc603 15>,
<&main_pktdma 0xc604 15>,
<&main_pktdma 0xc605 15>,
<&main_pktdma 0xc606 15>,
<&main_pktdma 0xc607 15>,
<&main_pktdma 0x4600 15>;
dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
"tx7", "rx";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
cpsw_port1: port@1 {
reg = <1>;
ti,mac-only;
label = "port1";
phys = <&phy_gmii_sel 1>;
mac-address = [00 00 00 00 00 00];
ti,syscon-efuse = <&wkup_conf 0x200>;
};
cpsw_port2: port@2 {
reg = <2>;
ti,mac-only;
label = "port2";
phys = <&phy_gmii_sel 2>;
mac-address = [00 00 00 00 00 00];
};
};
cpsw3g_mdio: mdio@f00 {
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
reg = <0x0 0xf00 0x0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 13 0>;
clock-names = "fck";
bus_freq = <1000000>;
};
cpts@3d000 {
compatible = "ti,j721e-cpts";
reg = <0x0 0x3d000 0x0 0x400>;
clocks = <&k3_clks 13 3>;
clock-names = "cpts";
interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cpts";
ti,cpts-ext-ts-inputs = <4>;
ti,cpts-periodic-outputs = <2>;
};
};
hwspinlock: spinlock@2a000000 {
compatible = "ti,am64-hwspinlock";
reg = <0x00 0x2a000000 0x00 0x1000>;
#hwlock-cells = <1>;
};
mailbox0_cluster0: mailbox@29000000 {
compatible = "ti,am64-mailbox";
reg = <0x00 0x29000000 0x00 0x200>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
};
mailbox0_cluster1: mailbox@29010000 {
compatible = "ti,am64-mailbox";
reg = <0x00 0x29010000 0x00 0x200>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
};
mailbox0_cluster2: mailbox@29020000 {
compatible = "ti,am64-mailbox";
reg = <0x00 0x29020000 0x00 0x200>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
};
mailbox0_cluster3: mailbox@29030000 {
compatible = "ti,am64-mailbox";
reg = <0x00 0x29030000 0x00 0x200>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
};
main_mcan0: can@20701000 {
compatible = "bosch,m_can";
reg = <0x00 0x20701000 0x00 0x200>,
<0x00 0x20708000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 98 6>, <&k3_clks 98 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
main_rti0: watchdog@e000000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x0e000000 0x00 0x100>;
clocks = <&k3_clks 125 0>;
power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 125 0>;
assigned-clock-parents = <&k3_clks 125 2>;
};
main_rti1: watchdog@e010000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x0e010000 0x00 0x100>;
clocks = <&k3_clks 126 0>;
power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 126 0>;
assigned-clock-parents = <&k3_clks 126 2>;
};
main_rti2: watchdog@e020000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x0e020000 0x00 0x100>;
clocks = <&k3_clks 127 0>;
power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 127 0>;
assigned-clock-parents = <&k3_clks 127 2>;
};
main_rti3: watchdog@e030000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x0e030000 0x00 0x100>;
clocks = <&k3_clks 128 0>;
power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 128 0>;
assigned-clock-parents = <&k3_clks 128 2>;
};
main_rti4: watchdog@e040000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x0e040000 0x00 0x100>;
clocks = <&k3_clks 205 0>;
power-domains = <&k3_pds 205 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 205 0>;
assigned-clock-parents = <&k3_clks 205 2>;
};
epwm0: pwm@23000000 {
compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x00 0x23000000 0x00 0x100>;
power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
clock-names = "tbclk", "fck";
status = "disabled";
};
epwm1: pwm@23010000 {
compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x00 0x23010000 0x00 0x100>;
power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
clock-names = "tbclk", "fck";
status = "disabled";
};
epwm2: pwm@23020000 {
compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x00 0x23020000 0x00 0x100>;
power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
clock-names = "tbclk", "fck";
status = "disabled";
};
ecap0: pwm@23100000 {
compatible = "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x00 0x23100000 0x00 0x100>;
power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 51 0>;
clock-names = "fck";
status = "disabled";
};
ecap1: pwm@23110000 {
compatible = "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x00 0x23110000 0x00 0x100>;
power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 52 0>;
clock-names = "fck";
status = "disabled";
};
ecap2: pwm@23120000 {
compatible = "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x00 0x23120000 0x00 0x100>;
power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 53 0>;
clock-names = "fck";
status = "disabled";
};
mcasp0: audio-controller@2b00000 {
compatible = "ti,am33xx-mcasp-audio";
reg = <0x00 0x02b00000 0x00 0x2000>,
<0x00 0x02b08000 0x00 0x400>;
reg-names = "mpu", "dat";
interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
dma-names = "tx", "rx";
clocks = <&k3_clks 190 0>;
clock-names = "fck";
assigned-clocks = <&k3_clks 190 0>;
assigned-clock-parents = <&k3_clks 190 2>;
power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
mcasp1: audio-controller@2b10000 {
compatible = "ti,am33xx-mcasp-audio";
reg = <0x00 0x02b10000 0x00 0x2000>,
<0x00 0x02b18000 0x00 0x400>;
reg-names = "mpu", "dat";
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
dma-names = "tx", "rx";
clocks = <&k3_clks 191 0>;
clock-names = "fck";
assigned-clocks = <&k3_clks 191 0>;
assigned-clock-parents = <&k3_clks 191 2>;
power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
mcasp2: audio-controller@2b20000 {
compatible = "ti,am33xx-mcasp-audio";
reg = <0x00 0x02b20000 0x00 0x2000>,
<0x00 0x02b28000 0x00 0x400>;
reg-names = "mpu", "dat";
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
dma-names = "tx", "rx";
clocks = <&k3_clks 192 0>;
clock-names = "fck";
assigned-clocks = <&k3_clks 192 0>;
assigned-clock-parents = <&k3_clks 192 2>;
power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
};

View File

@@ -15,6 +15,51 @@
status = "disabled";
};
/*
* The MCU domain timer interrupts are routed only to the ESM module,
* and not currently available for Linux. The MCU domain timers are
* of limited use without interrupts, and likely reserved by the ESM.
*/
mcu_timer0: timer@4800000 {
compatible = "ti,am654-timer";
reg = <0x00 0x4800000 0x00 0x400>;
clocks = <&k3_clks 35 2>;
clock-names = "fck";
power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
status = "reserved";
};
mcu_timer1: timer@4810000 {
compatible = "ti,am654-timer";
reg = <0x00 0x4810000 0x00 0x400>;
clocks = <&k3_clks 48 2>;
clock-names = "fck";
power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
status = "reserved";
};
mcu_timer2: timer@4820000 {
compatible = "ti,am654-timer";
reg = <0x00 0x4820000 0x00 0x400>;
clocks = <&k3_clks 49 2>;
clock-names = "fck";
power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
status = "reserved";
};
mcu_timer3: timer@4830000 {
compatible = "ti,am654-timer";
reg = <0x00 0x4830000 0x00 0x400>;
clocks = <&k3_clks 50 2>;
clock-names = "fck";
power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
status = "reserved";
};
mcu_uart0: serial@4a00000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a00000 0x00 0x100>;
@@ -36,4 +81,90 @@
clock-names = "fck";
status = "disabled";
};
mcu_spi0: spi@4b00000 {
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
reg = <0x00 0x04b00000 0x00 0x400>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 147 0>;
status = "disabled";
};
mcu_spi1: spi@4b10000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x04b10000 0x00 0x400>;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 148 0>;
status = "disabled";
};
mcu_gpio_intr: interrupt-controller@4210000 {
compatible = "ti,sci-intr";
reg = <0x00 0x04210000 0x00 0x200>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <1>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <5>;
ti,interrupt-ranges = <0 104 4>;
};
mcu_gpio0: gpio@4201000 {
compatible = "ti,am64-gpio", "ti,keystone-gpio";
reg = <0x00 0x04201000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&mcu_gpio_intr>;
interrupts = <30>, <31>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <24>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 79 0>;
clock-names = "gpio";
status = "disabled";
};
mcu_rti0: watchdog@4880000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x04880000 0x00 0x100>;
clocks = <&k3_clks 131 0>;
power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 131 0>;
assigned-clock-parents = <&k3_clks 131 2>;
/* Tightly coupled to M4F */
status = "reserved";
};
mcu_mcan0: can@4e08000 {
compatible = "bosch,m_can";
reg = <0x00 0x4e08000 0x00 0x200>,
<0x00 0x4e00000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 188 6>, <&k3_clks 188 1>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
mcu_mcan1: can@4e18000 {
compatible = "bosch,m_can";
reg = <0x00 0x4e18000 0x00 0x200>,
<0x00 0x4e10000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 189 6>, <&k3_clks 189 1>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
};

View File

@@ -0,0 +1,47 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/thermal/thermal.h>
thermal_zones: thermal-zones {
main0_thermal: main0-thermal {
polling-delay-passive = <250>; /* milliSeconds */
polling-delay = <500>; /* milliSeconds */
thermal-sensors = <&wkup_vtm0 0>;
trips {
main0_crit: main0-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
main1_thermal: main1-thermal {
polling-delay-passive = <250>; /* milliSeconds */
polling-delay = <500>; /* milliSeconds */
thermal-sensors = <&wkup_vtm0 1>;
trips {
main1_crit: main1-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
main2_thermal: main2-thermal {
polling-delay-passive = <250>; /* milliSeconds */
polling-delay = <500>; /* milliSeconds */
thermal-sensors = <&wkup_vtm0 2>;
trips {
main2_crit: main2-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
};

View File

@@ -31,7 +31,7 @@
wkup_i2c0: i2c@2b200000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x00 0x02b200000 0x00 0x100>;
reg = <0x00 0x2b200000 0x00 0x100>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -51,4 +51,23 @@
wakeup-source;
status = "disabled";
};
wkup_rti0: watchdog@2b000000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2b000000 0x00 0x100>;
clocks = <&k3_clks 132 0>;
power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 132 0>;
assigned-clock-parents = <&k3_clks 132 2>;
/* Used by DM firmware */
status = "reserved";
};
wkup_vtm0: temperature-sensor@b00000 {
compatible = "ti,j7200-vtm";
reg = <0x00 0xb00000 0x00 0x400>,
<0x00 0xb01000 0x00 0x400>;
power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
#thermal-sensor-cells = <1>;
};
};

View File

@@ -8,9 +8,10 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
#include "k3-pinctrl.h"
/ {
model = "Texas Instruments K3 AM62A SoC";
compatible = "ti,am62a7";
@@ -114,6 +115,8 @@
<0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
};
};
#include "k3-am62a-thermal.dtsi"
};
/* Now include the peripherals for each bus segments */

View File

@@ -7,7 +7,6 @@
#include "k3-am62a7-sk.dts"
#include "k3-am62a-ddr-1866mhz-32bit.dtsi"
#include "k3-am62a-ddr.dtsi"
#include "k3-am62a-sk-binman.dtsi"
#include "k3-am62a7-sk-u-boot.dtsi"
@@ -15,33 +14,6 @@
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
serial0 = &wkup_uart0;
serial3 = &main_uart1;
};
chosen {
stdout-path = "serial2:115200n8";
tick-timer = &timer1;
};
memory@80000000 {
device_type = "memory";
/* 4G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
<0x00000008 0x80000000 0x00000000 0x80000000>;
bootph-pre-ram;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
alignment = <0x1000>;
no-map;
};
};
a53_0: a53@0 {
@@ -81,67 +53,39 @@
ti,secure-host;
};
&cbass_main {
sa3_secproxy: secproxy@44880000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg = <0x00 0x44880000 0x00 0x20000>,
<0x0 0x44860000 0x0 0x20000>,
<0x0 0x43600000 0x0 0x10000>;
reg-names = "rt", "scfg", "target_data";
bootph-pre-ram;
};
&secure_proxy_sa3 {
/* Needed for initial handshake with ROM */
status = "okay";
bootph-pre-ram;
};
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
mboxes= <&secure_proxy_main 1>,
<&secure_proxy_main 0>,
<&sa3_secproxy 0>;
<&secure_proxy_sa3 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-pre-ram;
};
};
&mcu_pmx0 {
status = "okay";
&wkup_uart0_pins_default {
bootph-pre-ram;
wkup_uart0_pins_default: wkup-uart0-pins-default {
pinctrl-single,pins = <
AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6) WKUP_UART0_CTSn */
AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */
AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4) WKUP_UART0_RXD */
AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */
>;
bootph-pre-ram;
};
};
&main_pmx0 {
&main_uart1_pins_default {
bootph-pre-ram;
main_uart1_pins_default: main-uart1-pins-default {
pinctrl-single,pins = <
AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */
AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */
AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */
AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */
>;
bootph-pre-ram;
};
};
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
status = "okay";
bootph-pre-ram;
};
/* Main UART1 is used for TIFS firmware logs */
&main_uart1 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
status = "okay";
bootph-pre-ram;
};

View File

@@ -4,137 +4,186 @@
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-am62a-sk-binman.dtsi"
/ {
chosen {
stdout-path = "serial2:115200n8";
tick-timer = &timer1;
tick-timer = &main_timer0;
};
memory@80000000 {
bootph-pre-ram;
bootph-all;
};
};
&cbass_main{
bootph-pre-ram;
&main_timer0 {
bootph-all;
};
timer1: timer@2400000 {
compatible = "ti,omap5430-timer";
reg = <0x00 0x2400000 0x00 0x80>;
ti,timer-alwon;
clock-frequency = <25000000>;
bootph-pre-ram;
};
&cbass_main {
bootph-all;
};
&dmss {
bootph-pre-ram;
bootph-all;
};
&secure_proxy_main {
bootph-pre-ram;
bootph-all;
};
&dmsc {
bootph-pre-ram;
bootph-all;
};
&k3_pds {
bootph-pre-ram;
bootph-all;
};
&k3_clks {
bootph-pre-ram;
bootph-all;
};
&k3_reset {
bootph-pre-ram;
bootph-all;
};
&wkup_conf {
bootph-pre-ram;
bootph-all;
};
&chipid {
bootph-pre-ram;
bootph-all;
};
&main_pmx0 {
bootph-pre-ram;
bootph-all;
};
&main_uart0 {
bootph-pre-ram;
bootph-all;
};
&main_uart0_pins_default {
bootph-pre-ram;
};
&main_uart1 {
bootph-pre-ram;
bootph-all;
};
&cbass_mcu {
bootph-pre-ram;
bootph-all;
};
&cbass_wakeup {
bootph-pre-ram;
bootph-all;
};
&mcu_pmx0 {
bootph-pre-ram;
};
&wkup_uart0 {
bootph-pre-ram;
bootph-all;
};
&main_gpio0 {
bootph-pre-ram;
bootph-all;
};
&main_i2c0 {
bootph-pre-ram;
bootph-all;
};
&main_i2c0_pins_default {
bootph-pre-ram;
bootph-all;
};
&main_i2c1 {
bootph-pre-ram;
bootph-all;
};
&main_i2c1_pins_default {
bootph-pre-ram;
bootph-all;
};
&exp1 {
bootph-pre-ram;
bootph-all;
};
&sdhci1 {
bootph-pre-ram;
bootph-all;
};
&main_mmc1_pins_default {
bootph-pre-ram;
bootph-all;
};
&k3_reset {
bootph-pre-ram;
bootph-all;
};
&dmsc {
bootph-pre-ram;
bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
bootph-pre-ram;
bootph-all;
};
};
&vdd_mmc1 {
bootph-pre-ram;
bootph-all;
};
&main_bcdma {
reg = <0x00 0x485c0100 0x00 0x100>,
<0x00 0x4c000000 0x00 0x20000>,
<0x00 0x4a820000 0x00 0x20000>,
<0x00 0x4aa40000 0x00 0x20000>,
<0x00 0x4bc00000 0x00 0x100000>,
<0x00 0x48600000 0x00 0x8000>,
<0x00 0x484a4000 0x00 0x2000>,
<0x00 0x484c2000 0x00 0x2000>;
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt",
"ringrt" , "cfg", "tchan", "rchan";
bootph-all;
};
&main_pktdma {
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
<0x00 0x4aa00000 0x00 0x20000>,
<0x00 0x4b800000 0x00 0x200000>,
<0x00 0x485e0000 0x00 0x10000>,
<0x00 0x484a0000 0x00 0x2000>,
<0x00 0x484c0000 0x00 0x2000>,
<0x00 0x48430000 0x00 0x1000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
"cfg", "tchan", "rchan", "rflow";
bootph-all;
};
&main_mdio1_pins_default {
bootph-all;
};
&cpsw3g_mdio {
bootph-all;
};
&cpsw3g_phy0 {
bootph-all;
};
&main_rgmii1_pins_default {
bootph-all;
};
&phy_gmii_sel {
bootph-all;
};
&cpsw3g {
bootph-all;
ethernet-ports {
bootph-all;
};
};
&cpsw_port1 {
bootph-all;
};

View File

@@ -9,15 +9,17 @@
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am62a7.dtsi"
#include "k3-am62a-sk-binman.dtsi"
/ {
compatible = "ti,am62a7-sk", "ti,am62a7";
compatible = "ti,am62a7-sk", "ti,am62a7";
model = "Texas Instruments AM62A7 SK";
aliases {
serial0 = &wkup_uart0;
serial2 = &main_uart0;
serial3 = &main_uart1;
mmc1 = &sdhci1;
};
@@ -77,10 +79,10 @@
regulator-boot-on;
};
vcc_3v3_sys: regulator-2 {
vcc_3v3_main: regulator-2 {
/* output of LM5141-Q1 */
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_sys";
regulator-name = "vcc_3v3_main";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vmain_pd>;
@@ -99,6 +101,17 @@
gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
};
vcc_3v3_sys: regulator-4 {
/* output of TPS222965DSGT */
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_sys";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_3v3_main>;
regulator-always-on;
regulator-boot-on;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -112,38 +125,100 @@
default-state = "off";
};
};
tlv320_mclk: clk-0 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <12288000>;
};
codec_audio: sound {
compatible = "simple-audio-card";
simple-audio-card,name = "AM62Ax-SKEVM";
simple-audio-card,widgets =
"Headphone", "Headphone Jack",
"Line", "Line In",
"Microphone", "Microphone Jack";
simple-audio-card,routing =
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT",
"LINE1L", "Line In",
"LINE1R", "Line In",
"MIC3R", "Microphone Jack",
"Microphone Jack", "Mic Bias";
simple-audio-card,format = "dsp_b";
simple-audio-card,bitclock-master = <&sound_master>;
simple-audio-card,frame-master = <&sound_master>;
simple-audio-card,bitclock-inversion;
simple-audio-card,cpu {
sound-dai = <&mcasp1>;
};
sound_master: simple-audio-card,codec {
sound-dai = <&tlv320aic3106>;
clocks = <&tlv320_mclk>;
};
};
};
&mcu_pmx0 {
wkup_uart0_pins_default: wkup-uart0-default-pins {
pinctrl-single,pins = <
AM62AX_MCU_IOPAD(0x0024, PIN_INPUT, 0) /* (C9) WKUP_UART0_RXD */
AM62AX_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (E9) WKUP_UART0_TXD */
AM62AX_MCU_IOPAD(0x002c, PIN_INPUT, 0) /* (C10) WKUP_UART0_CTSn */
AM62AX_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (C8) WKUP_UART0_RTSn */
>;
};
};
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
status = "reserved";
};
&main_pmx0 {
main_uart0_pins_default: main-uart0-pins-default {
main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (E14) UART0_RXD */
AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (D15) UART0_TXD */
>;
};
main_i2c0_pins_default: main-i2c0-pins-default {
main_uart1_pins_default: main-uart1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x01e8, PIN_INPUT, 1) /* (C17) I2C1_SCL.UART1_RXD */
AM62AX_IOPAD(0x01ec, PIN_OUTPUT, 1) /* (E17) I2C1_SDA.UART1_TXD */
AM62AX_IOPAD(0x0194, PIN_INPUT, 2) /* (C19) MCASP0_AXR3.UART1_CTSn */
AM62AX_IOPAD(0x0198, PIN_OUTPUT, 2) /* (B19) MCASP0_AXR2.UART1_RTSn */
>;
};
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
AM62AX_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
>;
};
main_i2c1_pins_default: main-i2c1-pins-default {
main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
AM62AX_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
>;
};
main_i2c2_pins_default: main-i2c2-pins-default {
main_i2c2_pins_default: main-i2c2-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */
AM62AX_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
>;
};
main_mmc1_pins_default: main-mmc1-pins-default {
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
AM62AX_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
@@ -155,11 +230,64 @@
>;
};
usr_led_pins_default: usr-led-pins-default {
usr_led_pins_default: usr-led-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x244, PIN_OUTPUT, 7) /* (D18) MMC1_SDWP.GPIO1_49 */
>;
};
main_usb1_pins_default: main-usb1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */
>;
};
main_mdio1_pins_default: main-mdio1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */
AM62AX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */
>;
};
main_rgmii1_pins_default: main-rgmii1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x14c, PIN_INPUT, 0) /* (AB16) RGMII1_RD0 */
AM62AX_IOPAD(0x150, PIN_INPUT, 0) /* (V15) RGMII1_RD1 */
AM62AX_IOPAD(0x154, PIN_INPUT, 0) /* (W15) RGMII1_RD2 */
AM62AX_IOPAD(0x158, PIN_INPUT, 0) /* (V14) RGMII1_RD3 */
AM62AX_IOPAD(0x148, PIN_INPUT, 0) /* (AA16) RGMII1_RXC */
AM62AX_IOPAD(0x144, PIN_INPUT, 0) /* (AA15) RGMII1_RX_CTL */
AM62AX_IOPAD(0x134, PIN_INPUT, 0) /* (Y17) RGMII1_TD0 */
AM62AX_IOPAD(0x138, PIN_INPUT, 0) /* (V16) RGMII1_TD1 */
AM62AX_IOPAD(0x13c, PIN_INPUT, 0) /* (Y16) RGMII1_TD2 */
AM62AX_IOPAD(0x140, PIN_INPUT, 0) /* (AA17) RGMII1_TD3 */
AM62AX_IOPAD(0x130, PIN_INPUT, 0) /* (AB17) RGMII1_TXC */
AM62AX_IOPAD(0x12c, PIN_INPUT, 0) /* (W16) RGMII1_TX_CTL */
>;
};
main_mcasp1_pins_default: main-mcasp1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x090, PIN_INPUT, 2) /* (L19) GPMC0_BE0n_CLE.MCASP1_ACLKX */
AM62AX_IOPAD(0x098, PIN_INPUT, 2) /* (R18) GPMC0_WAIT0.MCASP1_AFSX */
AM62AX_IOPAD(0x08c, PIN_OUTPUT, 2) /* (K19) GPMC0_WEn.MCASP1_AXR0 */
AM62AX_IOPAD(0x084, PIN_INPUT, 2) /* (L18) GPMC0_ADVn_ALE.MCASP1_AXR2 */
>;
};
};
&mcu_pmx0 {
status = "okay";
pmic_irq_pins_default: pmic-irq-default-pins {
pinctrl-single,pins = <
AM62AX_MCU_IOPAD(0x000, PIN_INPUT, 7) /* (E11) MCU_GPIO0_0 */
>;
};
};
&mcu_gpio0 {
status = "okay";
};
&main_i2c0 {
@@ -167,13 +295,112 @@
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
typec_pd0: usb-power-controller@3f {
compatible = "ti,tps6598x";
reg = <0x3f>;
connector {
compatible = "usb-c-connector";
label = "USB-C";
self-powered;
data-role = "dual";
power-role = "sink";
port {
usb_con_hs: endpoint {
remote-endpoint = <&usb0_hs_ep>;
};
};
};
};
tps659312: pmic@48 {
compatible = "ti,tps6593-q1";
reg = <0x48>;
ti,primary-pmic;
system-power-controller;
gpio-controller;
#gpio-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_irq_pins_default>;
interrupt-parent = <&mcu_gpio0>;
interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
buck123-supply = <&vcc_3v3_sys>;
buck4-supply = <&vcc_3v3_sys>;
buck5-supply = <&vcc_3v3_sys>;
ldo1-supply = <&vcc_3v3_sys>;
ldo2-supply = <&vcc_3v3_sys>;
ldo3-supply = <&buck5>;
ldo4-supply = <&vcc_3v3_sys>;
regulators {
buck123: buck123 {
regulator-name = "vcc_core";
regulator-min-microvolt = <715000>;
regulator-max-microvolt = <895000>;
regulator-boot-on;
regulator-always-on;
};
buck4: buck4 {
regulator-name = "vcc_1v1";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
buck5: buck5 {
regulator-name = "vcc_1v8_sys";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: ldo1 {
regulator-name = "vddshv5_sdio";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo2: ldo2 {
regulator-name = "vpp_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo3: ldo3 {
regulator-name = "vcc_0v85";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: ldo4 {
regulator-name = "vdda_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&main_i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
clock-frequency = <100000>;
exp1: gpio@22 {
compatible = "ti,tca6424";
@@ -194,6 +421,19 @@
"MCASP1_FET_SEL", "UART1_FET_SEL",
"PD_I2C_IRQ", "IO_EXP_TEST_LED";
};
tlv320aic3106: audio-codec@1b {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic3106";
reg = <0x1b>;
ai3x-micbias-vg = <1>; /* 2.0V */
/* Regulators */
AVDD-supply = <&vcc_3v3_sys>;
IOVDD-supply = <&vcc_3v3_sys>;
DRVDD-supply = <&vcc_3v3_sys>;
DVDD-supply = <&buck5>;
};
};
&sdhci1 {
@@ -223,3 +463,84 @@
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
};
/* Main UART1 is used for TIFS firmware logs */
&main_uart1 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
status = "reserved";
};
&usbss0 {
status = "okay";
ti,vbus-divider;
};
&usb0 {
usb-role-switch;
port {
usb0_hs_ep: endpoint {
remote-endpoint = <&usb_con_hs>;
};
};
};
&usbss1 {
status = "okay";
};
&usb1 {
dr_mode = "host";
pinctrl-names = "default";
pinctrl-0 = <&main_usb1_pins_default>;
};
&cpsw3g {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_rgmii1_pins_default>;
};
&cpsw_port1 {
status = "okay";
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy0>;
};
&cpsw_port2 {
status = "disabled";
};
&cpsw3g_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mdio1_pins_default>;
cpsw3g_phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,min-output-impedance;
};
};
&mcasp1 {
status = "okay";
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&main_mcasp1_pins_default>;
op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1 0 2 0
0 0 0 0
0 0 0 0
0 0 0 0
>;
tx-num-evt = <32>;
rx-num-evt = <32>;
};

View File

@@ -95,8 +95,9 @@
L2_0: l2-cache0 {
compatible = "cache";
cache-unified;
cache-level = <2>;
cache-size = <0x40000>;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
};

View File

@@ -116,7 +116,30 @@
bootph-all;
};
&main_bcdma {
reg = <0x00 0x485c0100 0x00 0x100>,
<0x00 0x4c000000 0x00 0x20000>,
<0x00 0x4a820000 0x00 0x20000>,
<0x00 0x4aa40000 0x00 0x20000>,
<0x00 0x4bc00000 0x00 0x100000>,
<0x00 0x48600000 0x00 0x8000>,
<0x00 0x484a4000 0x00 0x2000>,
<0x00 0x484c2000 0x00 0x2000>;
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
"cfg", "tchan", "rchan";
};
&main_pktdma {
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
<0x00 0x4aa00000 0x00 0x40000>,
<0x00 0x4b800000 0x00 0x400000>,
<0x00 0x485e0000 0x00 0x20000>,
<0x00 0x484a0000 0x00 0x4000>,
<0x00 0x484c0000 0x00 0x2000>,
<0x00 0x48430000 0x00 0x4000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", "cfg",
"tchan", "rchan", "rflow";
bootph-all;
};

View File

@@ -96,10 +96,6 @@
bootph-all;
};
&main_pktdma {
bootph-all;
};
&mdio1_pins_default {
bootph-all;
};
@@ -141,10 +137,30 @@
};
&main_bcdma {
reg = <0x00 0x485c0100 0x00 0x100>,
<0x00 0x4c000000 0x00 0x20000>,
<0x00 0x4a820000 0x00 0x20000>,
<0x00 0x4aa40000 0x00 0x20000>,
<0x00 0x4bc00000 0x00 0x100000>,
<0x00 0x48600000 0x00 0x8000>,
<0x00 0x484a4000 0x00 0x2000>,
<0x00 0x484c2000 0x00 0x2000>;
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
"cfg", "tchan", "rchan";
bootph-all;
};
&main_pktdma {
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
<0x00 0x4aa00000 0x00 0x40000>,
<0x00 0x4b800000 0x00 0x400000>,
<0x00 0x485e0000 0x00 0x20000>,
<0x00 0x484a0000 0x00 0x4000>,
<0x00 0x484c0000 0x00 0x2000>,
<0x00 0x48430000 0x00 0x4000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", "cfg",
"tchan", "rchan", "rflow";
bootph-all;
};

View File

@@ -10,7 +10,7 @@
*/
&main_pmx0 {
cp2102n_reset_pin_default: cp2102n-reset-pin-default {
cp2102n_reset_pin_default: cp2102n-reset-default-pins {
pinctrl-single,pins = <
/* (AF12) GPIO1_24, used as cp2102 reset */
AM65X_IOPAD(0x01e0, PIN_OUTPUT, 7)

View File

@@ -14,6 +14,16 @@
/ {
aliases {
serial0 = &wkup_uart0;
serial1 = &mcu_uart0;
serial2 = &main_uart0;
serial3 = &main_uart1;
i2c0 = &wkup_i2c0;
i2c1 = &mcu_i2c0;
i2c2 = &main_i2c0;
i2c3 = &main_i2c1;
i2c4 = &main_i2c2;
i2c5 = &main_i2c3;
spi0 = &mcu_spi0;
mmc0 = &sdhci1;
mmc1 = &sdhci0;
@@ -21,7 +31,6 @@
chosen {
stdout-path = "serial3:115200n8";
bootargs = "earlycon=ns16550a,mmio32,0x02810000";
};
reserved-memory {
@@ -111,7 +120,7 @@
};
&wkup_pmx0 {
wkup_i2c0_pins_default: wkup-i2c0-pins-default {
wkup_i2c0_pins_default: wkup-i2c0-default-pins {
pinctrl-single,pins = <
/* (AC7) WKUP_I2C0_SCL */
AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0)
@@ -120,7 +129,7 @@
>;
};
mcu_i2c0_pins_default: mcu-i2c0-pins-default {
mcu_i2c0_pins_default: mcu-i2c0-default-pins {
pinctrl-single,pins = <
/* (AD8) MCU_I2C0_SCL */
AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT, 0)
@@ -129,21 +138,21 @@
>;
};
arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-pins-default {
arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-default-pins {
pinctrl-single,pins = <
/* (R2) WKUP_GPIO0_21 */
AM65X_WKUP_IOPAD(0x0024, PIN_OUTPUT, 7)
>;
};
push_button_pins_default: push-button-pins-default {
push_button_pins_default: push-button-default-pins {
pinctrl-single,pins = <
/* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */
AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7)
>;
};
arduino_uart_pins_default: arduino-uart-pins-default {
arduino_uart_pins_default: arduino-uart-default-pins {
pinctrl-single,pins = <
/* (P4) MCU_UART0_RXD */
AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4)
@@ -152,7 +161,7 @@
>;
};
arduino_io_d2_to_d3_pins_default: arduino-io-d2-to-d3-pins-default {
arduino_io_d2_to_d3_pins_default: arduino-io-d2-to-d3-default-pins {
pinctrl-single,pins = <
/* (P1) WKUP_GPIO0_31 */
AM65X_WKUP_IOPAD(0x004C, PIN_OUTPUT, 7)
@@ -161,7 +170,7 @@
>;
};
arduino_io_oe_pins_default: arduino-io-oe-pins-default {
arduino_io_oe_pins_default: arduino-io-oe-default-pins {
pinctrl-single,pins = <
/* (N4) WKUP_GPIO0_34 */
AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 7)
@@ -176,7 +185,7 @@
>;
};
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
pinctrl-single,pins = <
/* (V1) MCU_OSPI0_CLK */
AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0)
@@ -191,7 +200,7 @@
>;
};
db9_com_mode_pins_default: db9-com-mode-pins-default {
db9_com_mode_pins_default: db9-com-mode-default-pins {
pinctrl-single,pins = <
/* (AD3) WKUP_GPIO0_5, used as uart0 mode 0 */
AM65X_WKUP_IOPAD(0x00c4, PIN_OUTPUT, 7)
@@ -204,7 +213,7 @@
>;
};
leds_pins_default: leds-pins-default {
leds_pins_default: leds-default-pins {
pinctrl-single,pins = <
/* (T2) WKUP_GPIO0_17, used as user led1 red */
AM65X_WKUP_IOPAD(0x0014, PIN_OUTPUT, 7)
@@ -217,7 +226,7 @@
>;
};
mcu_spi0_pins_default: mcu-spi0-pins-default {
mcu_spi0_pins_default: mcu-spi0-default-pins {
pinctrl-single,pins = <
/* (Y1) MCU_SPI0_CLK */
AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 0)
@@ -230,7 +239,7 @@
>;
};
minipcie_pins_default: minipcie-pins-default {
minipcie_pins_default: minipcie-default-pins {
pinctrl-single,pins = <
/* (P2) MCU_OSPI1_DQS.WKUP_GPIO0_27 */
AM65X_WKUP_IOPAD(0x003C, PIN_OUTPUT, 7)
@@ -239,7 +248,7 @@
};
&main_pmx0 {
main_uart1_pins_default: main-uart1-pins-default {
main_uart1_pins_default: main-uart1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0174, PIN_INPUT, 6) /* (AE23) UART1_RXD */
AM65X_IOPAD(0x014c, PIN_OUTPUT, 6) /* (AD23) UART1_TXD */
@@ -248,14 +257,14 @@
>;
};
main_i2c3_pins_default: main-i2c3-pins-default {
main_i2c3_pins_default: main-i2c3-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01c0, PIN_INPUT, 2) /* (AF13) I2C3_SCL */
AM65X_IOPAD(0x01d4, PIN_INPUT, 2) /* (AG12) I2C3_SDA */
>;
};
main_mmc1_pins_default: main-mmc1-pins-default {
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
@@ -268,19 +277,19 @@
>;
};
usb0_pins_default: usb0-pins-default {
usb0_pins_default: usb0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
>;
};
usb1_pins_default: usb1-pins-default {
usb1_pins_default: usb1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
>;
};
arduino_io_d4_to_d9_pins_default: arduino-io-d4-to-d9-pins-default {
arduino_io_d4_to_d9_pins_default: arduino-io-d4-to-d9-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0084, PIN_OUTPUT, 7) /* (AG18) GPIO0_33 */
AM65X_IOPAD(0x008C, PIN_OUTPUT, 7) /* (AF17) GPIO0_35 */
@@ -291,7 +300,7 @@
>;
};
dss_vout1_pins_default: dss-vout1-pins-default {
dss_vout1_pins_default: dss-vout1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0000, PIN_OUTPUT, 1) /* VOUT1_DATA0 */
AM65X_IOPAD(0x0004, PIN_OUTPUT, 1) /* VOUT1_DATA1 */
@@ -324,13 +333,13 @@
>;
};
dp_pins_default: dp-pins-default {
dp_pins_default: dp-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0078, PIN_OUTPUT, 7) /* (AF18) DP rst_n */
>;
};
main_i2c2_pins_default: main-i2c2-pins-default {
main_i2c2_pins_default: main-i2c2-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) I2C2_SCL */
AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) I2C2_SDA */
@@ -339,21 +348,21 @@
};
&main_pmx1 {
main_i2c0_pins_default: main-i2c0-pins-default {
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */
AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */
>;
};
main_i2c1_pins_default: main-i2c1-pins-default {
main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */
AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */
>;
};
ecap0_pins_default: ecap0-pins-default {
ecap0_pins_default: ecap0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
>;
@@ -366,15 +375,13 @@
};
&main_uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
};
&main_uart2 {
status = "disabled";
};
&mcu_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&arduino_uart_pins_default>;
};
@@ -393,13 +400,12 @@
&wkup_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <
&arduino_io_d2_to_d3_pins_default
&arduino_i2c_aio_switch_pins_default
&arduino_io_oe_pins_default
&push_button_pins_default
&db9_com_mode_pins_default
>;
pinctrl-0 =
<&arduino_io_d2_to_d3_pins_default>,
<&arduino_i2c_aio_switch_pins_default>,
<&arduino_io_oe_pins_default>,
<&push_button_pins_default>,
<&db9_com_mode_pins_default>;
gpio-line-names =
/* 0..9 */
"wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0",
@@ -419,19 +425,21 @@
};
&wkup_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
};
&mcu_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_i2c0_pins_default>;
clock-frequency = <400000>;
psu: regulator@60 {
compatible = "ti,tps62363";
reg = <0x60>;
reg = <0x60>;
regulator-name = "tps62363-vout";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1500000>;
@@ -484,11 +492,12 @@
};
&main_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
rtc: rtc8564@51 {
rtc: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
@@ -501,18 +510,21 @@
};
&main_i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
};
&main_i2c2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c2_pins_default>;
clock-frequency = <400000>;
};
&main_i2c3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c3_pins_default>;
clock-frequency = <400000>;
@@ -552,6 +564,7 @@
};
&ecap0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins_default>;
};
@@ -576,25 +589,24 @@
};
&mcu_spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_spi0_pins_default>;
#address-cells = <1>;
#size-cells= <0>;
#size-cells = <0>;
ti,pindir-d0-out-d1-in;
};
&tscadc0 {
status = "disabled";
};
&tscadc1 {
status = "okay";
adc {
ti,adc-channels = <0 1 2 3 4 5>;
};
};
&ospi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
@@ -609,8 +621,52 @@
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <2>;
#address-cells = <1>;
#size-cells = <1>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
seboot@0 {
label = "seboot";
reg = <0x0 0x180000>; /* 1.5M */
};
tispl@180000 {
label = "tispl";
reg = <0x180000 0x200000>; /* 2M */
};
u-boot@380000 {
label = "u-boot";
reg = <0x380000 0x300000>; /* 3M */
};
env@680000 {
label = "env";
reg = <0x680000 0x20000>; /* 128K */
};
env-backup@6a0000 {
label = "env.backup";
reg = <0x6a0000 0x20000>; /* 128K */
};
otpcmd@6c0000 {
label = "otpcmd";
reg = <0x6c0000 0x10000>; /* 64K */
};
unused@6d0000 {
label = "unused";
reg = <0x6d0000 0x7b0000>; /* 7872K */
};
seboot-backup@e80000 {
label = "seboot.backup";
reg = <0xe80000 0x180000>; /* 1.5M */
};
};
};
};
@@ -634,15 +690,8 @@
};
};
&pcie0_rc {
status = "disabled";
};
&pcie0_ep {
status = "disabled";
};
&pcie1_rc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&minipcie_pins_default>;
@@ -652,11 +701,8 @@
reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>;
};
&pcie1_ep {
status = "disabled";
};
&mailbox0_cluster0 {
status = "okay";
interrupts = <436>;
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
@@ -666,6 +712,7 @@
};
&mailbox0_cluster1 {
status = "okay";
interrupts = <432>;
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
@@ -674,71 +721,18 @@
};
};
&mailbox0_cluster2 {
status = "disabled";
};
&mailbox0_cluster3 {
status = "disabled";
};
&mailbox0_cluster4 {
status = "disabled";
};
&mailbox0_cluster5 {
status = "disabled";
};
&mailbox0_cluster6 {
status = "disabled";
};
&mailbox0_cluster7 {
status = "disabled";
};
&mailbox0_cluster8 {
status = "disabled";
};
&mailbox0_cluster9 {
status = "disabled";
};
&mailbox0_cluster10 {
status = "disabled";
};
&mailbox0_cluster11 {
status = "disabled";
};
&mcu_r5fss0_core0 {
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
};
&mcu_r5fss0_core1 {
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>;
};
&mcu_rti1 {
memory-region = <&wdt_reset_memory_region>;
};
&icssg0_mdio {
status = "disabled";
};
&icssg1_mdio {
status = "disabled";
};
&icssg2_mdio {
status = "disabled";
};

View File

@@ -35,7 +35,10 @@
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
<0x00 0x01880000 0x00 0x90000>; /* GICR */
<0x00 0x01880000 0x00 0x90000>, /* GICR */
<0x00 0x6f000000 0x00 0x2000>, /* GICC */
<0x00 0x6f010000 0x00 0x1000>, /* GICH */
<0x00 0x6f020000 0x00 0x2000>; /* GICV */
/*
* vcpumntirq:
* virtual CPU interface maintenance interrupt
@@ -88,6 +91,7 @@
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_uart1: serial@2810000 {
@@ -96,6 +100,7 @@
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_uart2: serial@2820000 {
@@ -104,29 +109,47 @@
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
crypto: crypto@4e00000 {
compatible = "ti,am654-sa2ul";
reg = <0x0 0x4e00000 0x0 0x1200>;
power-domains = <&k3_pds 136 TI_SCI_PD_EXCLUSIVE>;
power-domains = <&k3_pds 136 TI_SCI_PD_SHARED>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
<&main_udmap 0x4001>;
dmas = <&main_udmap 0xc001>, <&main_udmap 0x4002>,
<&main_udmap 0x4003>;
dma-names = "tx", "rx1", "rx2";
dma-coherent;
rng: rng@4e10000 {
compatible = "inside-secure,safexcel-eip76";
reg = <0x0 0x4e10000 0x0 0x7d>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 136 1>;
status = "disabled"; /* Used by OP-TEE */
};
};
/* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
main_timerio_input: pinctrl@104200 {
compatible = "pinctrl-single";
reg = <0x0 0x104200 0x0 0x30>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000001ff>;
};
/* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
main_timerio_output: pinctrl@104280 {
compatible = "pinctrl-single";
reg = <0x0 0x104280 0x0 0x20>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000000f>;
};
main_pmx0: pinctrl@11c000 {
compatible = "pinctrl-single";
reg = <0x0 0x11c000 0x0 0x2e4>;
@@ -152,6 +175,7 @@
clock-names = "fck";
clocks = <&k3_clks 110 1>;
power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_i2c1: i2c@2010000 {
@@ -163,6 +187,7 @@
clock-names = "fck";
clocks = <&k3_clks 111 1>;
power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_i2c2: i2c@2020000 {
@@ -174,6 +199,7 @@
clock-names = "fck";
clocks = <&k3_clks 112 1>;
power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_i2c3: i2c@2030000 {
@@ -185,6 +211,7 @@
clock-names = "fck";
clocks = <&k3_clks 113 1>;
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
ecap0: pwm@3100000 {
@@ -194,6 +221,7 @@
power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 39 0>;
clock-names = "fck";
status = "disabled";
};
main_spi0: spi@2100000 {
@@ -206,6 +234,7 @@
#size-cells = <0>;
dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
dma-names = "tx0", "rx0";
status = "disabled";
};
main_spi1: spi@2110000 {
@@ -218,6 +247,7 @@
#size-cells = <0>;
assigned-clocks = <&k3_clks 137 1>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
main_spi2: spi@2120000 {
@@ -228,6 +258,7 @@
power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
main_spi3: spi@2130000 {
@@ -238,6 +269,7 @@
power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
main_spi4: spi@2140000 {
@@ -248,6 +280,151 @@
power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
main_timer0: timer@2400000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2400000 0x00 0x400>;
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 23 0>;
clock-names = "fck";
assigned-clocks = <&k3_clks 23 0>;
assigned-clock-parents = <&k3_clks 23 1>;
power-domains = <&k3_pds 23 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer1: timer@2410000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2410000 0x00 0x400>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 24 0>;
clock-names = "fck";
assigned-clocks = <&k3_clks 24 0>;
assigned-clock-parents = <&k3_clks 24 1>;
power-domains = <&k3_pds 24 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer2: timer@2420000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2420000 0x00 0x400>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 27 0>;
clock-names = "fck";
assigned-clocks = <&k3_clks 27 0>;
assigned-clock-parents = <&k3_clks 27 1>;
power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer3: timer@2430000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2430000 0x00 0x400>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 28 0>;
clock-names = "fck";
assigned-clocks = <&k3_clks 28 0>;
assigned-clock-parents = <&k3_clks 28 1>;
power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer4: timer@2440000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2440000 0x00 0x400>;
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 29 0>;
clock-names = "fck";
assigned-clocks = <&k3_clks 29 0>;
assigned-clock-parents = <&k3_clks 29 1>;
power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer5: timer@2450000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2450000 0x00 0x400>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 30 0>;
clock-names = "fck";
assigned-clocks = <&k3_clks 30 0>;
assigned-clock-parents = <&k3_clks 30 1>;
power-domains = <&k3_pds 30 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer6: timer@2460000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2460000 0x00 0x400>;
interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 31 0>;
assigned-clocks = <&k3_clks 31 0>;
assigned-clock-parents = <&k3_clks 31 1>;
clock-names = "fck";
power-domains = <&k3_pds 31 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer7: timer@2470000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2470000 0x00 0x400>;
interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 32 0>;
clock-names = "fck";
assigned-clocks = <&k3_clks 32 0>;
assigned-clock-parents = <&k3_clks 32 1>;
power-domains = <&k3_pds 32 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer8: timer@2480000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2480000 0x00 0x400>;
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 33 0>;
clock-names = "fck";
assigned-clocks = <&k3_clks 33 0>;
assigned-clock-parents = <&k3_clks 33 1>;
power-domains = <&k3_pds 33 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer9: timer@2490000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2490000 0x00 0x400>;
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 34 0>;
clock-names = "fck";
assigned-clocks = <&k3_clks 34 0>;
assigned-clock-parents = <&k3_clks 34 1>;
power-domains = <&k3_pds 34 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer10: timer@24a0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24a0000 0x00 0x400>;
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 25 0>;
clock-names = "fck";
assigned-clocks = <&k3_clks 25 0>;
assigned-clock-parents = <&k3_clks 25 1>;
power-domains = <&k3_pds 25 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer11: timer@24b0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24b0000 0x00 0x400>;
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 26 0>;
clock-names = "fck";
assigned-clocks = <&k3_clks 26 0>;
assigned-clock-parents = <&k3_clks 26 1>;
power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
sdhci0: mmc@4f80000 {
@@ -292,7 +469,6 @@
ti,otap-del-sel-ddr52 = <0x4>;
ti,otap-del-sel-hs200 = <0x7>;
ti,clkbuf-sel = <0x7>;
ti,otap-del-sel = <0x2>;
ti,trm-icp = <0x8>;
dma-coherent;
};
@@ -304,21 +480,6 @@
#size-cells = <1>;
ranges = <0x0 0x0 0x00100000 0x1c000>;
pcie0_mode: pcie-mode@4060 {
compatible = "syscon";
reg = <0x00004060 0x4>;
};
pcie1_mode: pcie-mode@4070 {
compatible = "syscon";
reg = <0x00004070 0x4>;
};
pcie_devid: pcie-devid@210 {
compatible = "syscon";
reg = <0x00000210 0x4>;
};
serdes0_clk: clock@4080 {
compatible = "syscon";
reg = <0x00004080 0x4>;
@@ -338,11 +499,11 @@
dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 {
compatible = "syscon";
reg = <0x0000041e0 0x14>;
reg = <0x000041e0 0x14>;
};
ehrpwm_tbclk: clock@4140 {
compatible = "ti,am654-ehrpwm-tbclk", "syscon";
ehrpwm_tbclk: clock-controller@4140 {
compatible = "ti,am654-ehrpwm-tbclk";
reg = <0x4140 0x18>;
#clock-cells = <1>;
};
@@ -439,7 +600,7 @@
};
main_navss: bus@30800000 {
compatible = "simple-mfd";
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>;
@@ -497,6 +658,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
status = "disabled";
};
mailbox0_cluster1: mailbox@31f81000 {
@@ -506,6 +668,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
status = "disabled";
};
mailbox0_cluster2: mailbox@31f82000 {
@@ -515,6 +678,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
status = "disabled";
};
mailbox0_cluster3: mailbox@31f83000 {
@@ -524,6 +688,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
status = "disabled";
};
mailbox0_cluster4: mailbox@31f84000 {
@@ -533,6 +698,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
status = "disabled";
};
mailbox0_cluster5: mailbox@31f85000 {
@@ -542,6 +708,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
status = "disabled";
};
mailbox0_cluster6: mailbox@31f86000 {
@@ -551,6 +718,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
status = "disabled";
};
mailbox0_cluster7: mailbox@31f87000 {
@@ -560,6 +728,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
status = "disabled";
};
mailbox0_cluster8: mailbox@31f88000 {
@@ -569,6 +738,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
status = "disabled";
};
mailbox0_cluster9: mailbox@31f89000 {
@@ -578,6 +748,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
status = "disabled";
};
mailbox0_cluster10: mailbox@31f8a000 {
@@ -587,6 +758,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
status = "disabled";
};
mailbox0_cluster11: mailbox@31f8b000 {
@@ -596,15 +768,17 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
status = "disabled";
};
ringacc: ringacc@3c000000 {
compatible = "ti,am654-navss-ringacc";
reg = <0x0 0x3c000000 0x0 0x400000>,
<0x0 0x38000000 0x0 0x400000>,
<0x0 0x31120000 0x0 0x100>,
<0x0 0x33000000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
reg = <0x0 0x3c000000 0x0 0x400000>,
<0x0 0x38000000 0x0 0x400000>,
<0x0 0x31120000 0x0 0x100>,
<0x0 0x33000000 0x0 0x40000>,
<0x0 0x31080000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
ti,num-rings = <818>;
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
ti,sci = <&dmsc>;
@@ -614,9 +788,9 @@
main_udmap: dma-controller@31150000 {
compatible = "ti,am654-navss-main-udmap";
reg = <0x0 0x31150000 0x0 0x100>,
<0x0 0x34000000 0x0 0x100000>,
<0x0 0x35000000 0x0 0x100000>;
reg = <0x0 0x31150000 0x0 0x100>,
<0x0 0x34000000 0x0 0x100000>,
<0x0 0x35000000 0x0 0x100000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
msi-parent = <&inta_main_udmass>;
#dma-cells = <1>;
@@ -687,15 +861,15 @@
pcie0_rc: pcie@5500000 {
compatible = "ti,am654-pcie-rc";
reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
reg-names = "app", "dbics", "config", "atu";
power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000
0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
ti,syscon-pcie-id = <&pcie_devid>;
ti,syscon-pcie-mode = <&pcie0_mode>;
ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>,
<0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
ti,syscon-pcie-id = <&scm_conf 0x210>;
ti,syscon-pcie-mode = <&scm_conf 0x4060>;
bus-range = <0x0 0xff>;
num-viewport = <16>;
max-link-speed = <2>;
@@ -703,32 +877,34 @@
interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
msi-map = <0x0 &gic_its 0x0 0x10000>;
device_type = "pci";
status = "disabled";
};
pcie0_ep: pcie-ep@5500000 {
compatible = "ti,am654-pcie-ep";
reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
reg-names = "app", "dbics", "addr_space", "atu";
power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
ti,syscon-pcie-mode = <&pcie0_mode>;
ti,syscon-pcie-mode = <&scm_conf 0x4060>;
num-ib-windows = <16>;
num-ob-windows = <16>;
max-link-speed = <2>;
dma-coherent;
interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
pcie1_rc: pcie@5600000 {
compatible = "ti,am654-pcie-rc";
reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
reg-names = "app", "dbics", "config", "atu";
power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000
0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
ti,syscon-pcie-id = <&pcie_devid>;
ti,syscon-pcie-mode = <&pcie1_mode>;
ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>,
<0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
ti,syscon-pcie-id = <&scm_conf 0x210>;
ti,syscon-pcie-mode = <&scm_conf 0x4070>;
bus-range = <0x0 0xff>;
num-viewport = <16>;
max-link-speed = <2>;
@@ -736,19 +912,21 @@
interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
msi-map = <0x0 &gic_its 0x10000 0x10000>;
device_type = "pci";
status = "disabled";
};
pcie1_ep: pcie-ep@5600000 {
compatible = "ti,am654-pcie-ep";
reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
reg-names = "app", "dbics", "addr_space", "atu";
power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
ti,syscon-pcie-mode = <&pcie1_mode>;
ti,syscon-pcie-mode = <&scm_conf 0x4070>;
num-ib-windows = <16>;
num-ob-windows = <16>;
max-link-speed = <2>;
dma-coherent;
interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
mcasp0: mcasp@2b00000 {
@@ -766,6 +944,7 @@
clocks = <&k3_clks 104 0>;
clock-names = "fck";
power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
mcasp1: mcasp@2b10000 {
@@ -783,6 +962,7 @@
clocks = <&k3_clks 105 0>;
clock-names = "fck";
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
mcasp2: mcasp@2b20000 {
@@ -800,6 +980,7 @@
clocks = <&k3_clks 106 0>;
clock-names = "fck";
power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
cal: cal@6f03000 {
@@ -826,13 +1007,13 @@
dss: dss@4a00000 {
compatible = "ti,am65x-dss";
reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
<0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
<0x0 0x04a06000 0x0 0x1000>, /* vid */
<0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
<0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
<0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
<0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
<0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
<0x0 0x04a06000 0x0 0x1000>, /* vid */
<0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
<0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
<0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
<0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
reg-names = "common", "vidl1", "vid",
"ovr1", "ovr2", "vp1", "vp2";
@@ -840,9 +1021,9 @@
power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 67 1>,
<&k3_clks 216 1>,
<&k3_clks 67 2>;
clocks = <&k3_clks 67 1>,
<&k3_clks 216 1>,
<&k3_clks 67 2>;
clock-names = "fck", "vp1", "vp2";
/*
@@ -870,6 +1051,7 @@
power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
clock-names = "tbclk", "fck";
status = "disabled";
};
ehrpwm1: pwm@3010000 {
@@ -879,6 +1061,7 @@
power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
clock-names = "tbclk", "fck";
status = "disabled";
};
ehrpwm2: pwm@3020000 {
@@ -888,6 +1071,7 @@
power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
clock-names = "tbclk", "fck";
status = "disabled";
};
ehrpwm3: pwm@3030000 {
@@ -897,6 +1081,7 @@
power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
clock-names = "tbclk", "fck";
status = "disabled";
};
ehrpwm4: pwm@3040000 {
@@ -906,6 +1091,7 @@
power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
clock-names = "tbclk", "fck";
status = "disabled";
};
ehrpwm5: pwm@3050000 {
@@ -915,6 +1101,7 @@
power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
clock-names = "tbclk", "fck";
status = "disabled";
};
icssg0: icssg@b000000 {
@@ -964,6 +1151,18 @@
};
};
icssg0_iep0: iep@2e000 {
compatible = "ti,am654-icss-iep";
reg = <0x2e000 0x1000>;
clocks = <&icssg0_iepclk_mux>;
};
icssg0_iep1: iep@2f000 {
compatible = "ti,am654-icss-iep";
reg = <0x2f000 0x1000>;
clocks = <&icssg0_iepclk_mux>;
};
icssg0_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
@@ -1055,6 +1254,7 @@
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
status = "disabled";
};
};
@@ -1105,6 +1305,18 @@
};
};
icssg1_iep0: iep@2e000 {
compatible = "ti,am654-icss-iep";
reg = <0x2e000 0x1000>;
clocks = <&icssg1_iepclk_mux>;
};
icssg1_iep1: iep@2f000 {
compatible = "ti,am654-icss-iep";
reg = <0x2f000 0x1000>;
clocks = <&icssg1_iepclk_mux>;
};
icssg1_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
@@ -1196,6 +1408,7 @@
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
status = "disabled";
};
};
@@ -1246,6 +1459,18 @@
};
};
icssg2_iep0: iep@2e000 {
compatible = "ti,am654-icss-iep";
reg = <0x2e000 0x1000>;
clocks = <&icssg2_iepclk_mux>;
};
icssg2_iep1: iep@2f000 {
compatible = "ti,am654-icss-iep";
reg = <0x2f000 0x1000>;
clocks = <&icssg2_iepclk_mux>;
};
icssg2_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
@@ -1337,6 +1562,7 @@
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
status = "disabled";
};
};
};

View File

@@ -20,13 +20,32 @@
};
};
/* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
mcu_timerio_input: pinctrl@40f04200 {
compatible = "pinctrl-single";
reg = <0x0 0x40f04200 0x0 0x10>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x00000101>;
};
/* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
mcu_timerio_output: pinctrl@40f04280 {
compatible = "pinctrl-single";
reg = <0x0 0x40f04280 0x0 0x8>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x00000003>;
};
mcu_uart0: serial@40a00000 {
compatible = "ti,am654-uart";
reg = <0x00 0x40a00000 0x00 0x100>;
interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <96000000>;
current-speed = <115200>;
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
reg = <0x00 0x40a00000 0x00 0x100>;
interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <96000000>;
current-speed = <115200>;
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
mcu_ram: sram@41c00000 {
@@ -46,6 +65,7 @@
clock-names = "fck";
clocks = <&k3_clks 114 1>;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
mcu_spi0: spi@40300000 {
@@ -56,6 +76,7 @@
power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
mcu_spi1: spi@40310000 {
@@ -66,6 +87,7 @@
power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
mcu_spi2: spi@40320000 {
@@ -76,6 +98,7 @@
power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
tscadc0: tscadc@40200000 {
@@ -85,10 +108,11 @@
clocks = <&k3_clks 0 2>;
assigned-clocks = <&k3_clks 0 2>;
assigned-clock-rates = <60000000>;
clock-names = "adc_tsc_fck";
clock-names = "fck";
dmas = <&mcu_udmap 0x7100>,
<&mcu_udmap 0x7101 >;
dma-names = "fifo0", "fifo1";
status = "disabled";
adc {
#io-channel-cells = <1>;
@@ -103,10 +127,11 @@
clocks = <&k3_clks 1 2>;
assigned-clocks = <&k3_clks 1 2>;
assigned-clock-rates = <60000000>;
clock-names = "adc_tsc_fck";
clock-names = "fck";
dmas = <&mcu_udmap 0x7102>,
<&mcu_udmap 0x7103>;
dma-names = "fifo0", "fifo1";
status = "disabled";
adc {
#io-channel-cells = <1>;
@@ -114,8 +139,53 @@
};
};
/*
* The MCU domain timer interrupts are routed only to the ESM module,
* and not currently available for Linux. The MCU domain timers are
* of limited use without interrupts, and likely reserved by the ESM.
*/
mcu_timer0: timer@40400000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40400000 0x00 0x400>;
clocks = <&k3_clks 35 0>;
clock-names = "fck";
power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
status = "reserved";
};
mcu_timer1: timer@40410000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40410000 0x00 0x400>;
clocks = <&k3_clks 36 0>;
clock-names = "fck";
power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
status = "reserved";
};
mcu_timer2: timer@40420000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40420000 0x00 0x400>;
clocks = <&k3_clks 37 0>;
clock-names = "fck";
power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
status = "reserved";
};
mcu_timer3: timer@40430000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40430000 0x00 0x400>;
clocks = <&k3_clks 38 0>;
clock-names = "fck";
power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
status = "reserved";
};
mcu_navss: bus@28380000 {
compatible = "simple-mfd";
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
@@ -126,11 +196,13 @@
mcu_ringacc: ringacc@2b800000 {
compatible = "ti,am654-navss-ringacc";
reg = <0x0 0x2b800000 0x0 0x400000>,
<0x0 0x2b000000 0x0 0x400000>,
<0x0 0x28590000 0x0 0x100>,
<0x0 0x2a500000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
reg = <0x0 0x2b800000 0x0 0x400000>,
<0x0 0x2b000000 0x0 0x400000>,
<0x0 0x28590000 0x0 0x100>,
<0x0 0x2a500000 0x0 0x40000>,
<0x0 0x28440000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg",
"proxy_target", "cfg";
ti,num-rings = <286>;
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
ti,sci = <&dmsc>;
@@ -140,9 +212,9 @@
mcu_udmap: dma-controller@285c0000 {
compatible = "ti,am654-navss-mcu-udmap";
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x2a800000 0x0 0x40000>,
<0x0 0x2aa00000 0x0 0x40000>;
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x2a800000 0x0 0x40000>,
<0x0 0x2aa00000 0x0 0x40000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
msi-parent = <&inta_main_udmass>;
#dma-cells = <1>;
@@ -159,7 +231,54 @@
};
};
fss: fss@47000000 {
secure_proxy_mcu: mailbox@2a480000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
reg = <0x0 0x2a480000 0x0 0x80000>,
<0x0 0x2a380000 0x0 0x80000>,
<0x0 0x2a400000 0x0 0x80000>;
/*
* Marked Disabled:
* Node is incomplete as it is meant for bootloaders and
* firmware on non-MPU processors
*/
status = "disabled";
};
m_can0: can@40528000 {
compatible = "bosch,m_can";
reg = <0x0 0x40528000 0x0 0x400>,
<0x0 0x40500000 0x0 0x4400>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 102 5>, <&k3_clks 102 0>;
clock-names = "hclk", "cclk";
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
m_can1: can@40568000 {
compatible = "bosch,m_can";
reg = <0x0 0x40568000 0x0 0x400>,
<0x0 0x40540000 0x0 0x4400>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 103 5>, <&k3_clks 103 0>;
clock-names = "hclk", "cclk";
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
fss: bus@47000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
@@ -180,6 +299,7 @@
power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
ospi1: spi@47050000 {
@@ -194,6 +314,7 @@
power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
@@ -243,6 +364,7 @@
clocks = <&k3_clks 5 10>;
clock-names = "fck";
bus_freq = <1000000>;
status = "disabled";
};
cpts@3d000 {

View File

@@ -12,8 +12,8 @@
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 11>,
<&secure_proxy_main 13>;
mboxes = <&secure_proxy_main 11>,
<&secure_proxy_main 13>;
reg-names = "debug_messages";
reg = <0x44083000 0x1000>;
@@ -54,6 +54,7 @@
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
wkup_i2c0: i2c@42120000 {
@@ -65,6 +66,7 @@
clock-names = "fck";
clocks = <&k3_clks 115 1>;
power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
intr_wkup_gpio: interrupt-controller@42200000 {
@@ -100,8 +102,4 @@
power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
#thermal-sensor-cells = <1>;
};
thermal_zones: thermal-zones {
#include "k3-am654-industrial-thermal.dtsi"
};
};

View File

@@ -8,9 +8,10 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
#include "k3-pinctrl.h"
/ {
model = "Texas Instruments K3 AM654 SoC";
compatible = "ti,am654";
@@ -18,21 +19,6 @@
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &wkup_uart0;
serial1 = &mcu_uart0;
serial2 = &main_uart0;
serial3 = &main_uart1;
serial4 = &main_uart2;
i2c0 = &wkup_i2c0;
i2c1 = &mcu_i2c0;
i2c2 = &main_i2c0;
i2c3 = &main_i2c1;
i2c4 = &main_i2c2;
i2c5 = &main_i2c3;
ethernet0 = &cpsw_port1;
};
chosen { };
firmware {
@@ -84,6 +70,7 @@
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
<0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>,
<0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A53 PERIPHBASE */
<0x00 0x70000000 0x00 0x70000000 0x00 0x200000>,
<0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
<0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;

View File

@@ -35,7 +35,7 @@
};
&main_pmx0 {
main_uart0_pins_default: main-uart0-pins-default {
main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
@@ -50,6 +50,7 @@
};
&main_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
};

View File

@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
* This file was generated by AM65x_DRA80xM_EMIF_Tool_2.02.xlsm
* http://www.ti.com/lit/pdf/spracj0
* https://www.ti.com/lit/pdf/spracj0
* Configuration Parameters
* Memory Type: DDR4
* Data Rate: 1600 MT/s

View File

@@ -1,11 +1,170 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018-2021 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-am654-r5-base-board-u-boot.dtsi"
#include "k3-am65x-binman.dtsi"
/ {
chosen {
tick-timer = &mcu_timer0;
};
};
&mcu_timer0 {
ti,timer-alwon;
clock-frequency = <25000000>;
bootph-all;
};
&vtt_supply {
bootph-all;
};
&cbass_main {
bootph-all;
};
&main_navss {
bootph-all;
};
&cbass_mcu {
bootph-all;
};
&mcu_navss {
bootph-all;
};
&mcu_ringacc {
bootph-all;
};
&mcu_udmap {
bootph-all;
};
&wkup_gpio0 {
bootph-all;
};
&secure_proxy_main {
bootph-all;
};
&cbass_wakeup {
bootph-all;
chipid@43000014 {
bootph-all;
};
};
&dmsc {
bootph-all;
};
&k3_pds {
bootph-all;
};
&k3_clks {
bootph-all;
};
&k3_reset {
bootph-all;
};
&main_uart0 {
bootph-all;
};
&wkup_vtm0 {
bootph-all;
};
&wkup_pmx0 {
bootph-all;
};
&wkup_uart0_pins_default {
bootph-all;
};
&ddr_vtt_pins_default {
bootph-all;
};
&mcu_uart0_pins_default {
bootph-all;
};
&wkup_i2c0_pins_default {
bootph-all;
};
&mcu_fss0_ospi0_pins_default {
bootph-all;
};
&main_pmx0 {
bootph-all;
};
&main_uart0_pins_default {
bootph-all;
};
&main_mmc0_pins_default {
bootph-all;
};
&main_mmc1_pins_default {
bootph-all;
};
&main_pmx1 {
bootph-all;
};
&sdhci0 {
bootph-all;
};
&sdhci1 {
bootph-all;
};
&wkup_i2c0 {
bootph-all;
};
&vdd_mpu {
bootph-all;
};
&ospi0 {
bootph-all;
flash@0 {
bootph-all;
};
};
&dwc3_0 {
bootph-all;
};
&scm_conf {
bootph-all;
};
&fss {
bootph-all;
};
&pru0_0 {
remoteproc-name = "pru0_0";
};
@@ -81,3 +240,37 @@
&mcu_r5fss0 {
ti,cluster-mode = <0>;
};
/*
* The DMA driver requires a few extra register ranges
* which are missing for the am65x. A patch has been
* sent and will be synced after the v6.8-rc1 linux
* tag is published
*/
&main_udmap {
reg = <0x0 0x31150000 0x0 0x100>,
<0x0 0x34000000 0x0 0x100000>,
<0x0 0x35000000 0x0 0x100000>,
<0x0 0x30b00000 0x0 0x10000>,
<0x0 0x30c00000 0x0 0x10000>,
<0x0 0x30d00000 0x0 0x8000>;
reg-names = "gcfg", "rchanrt", "tchanrt",
"tchan", "rchan", "rflow";
};
/*
* The DMA driver requires a few extra register ranges
* which are missing for the am65x. A patch has been
* sent and will be synced after the v6.8-rc1 linux
* tag is published
*/
&mcu_udmap {
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x2a800000 0x0 0x40000>,
<0x0 0x2aa00000 0x0 0x40000>,
<0x0 0x284a0000 0x0 0x4000>,
<0x0 0x284c0000 0x0 0x4000>,
<0x0 0x28400000 0x0 0x2000>;
reg-names = "gcfg", "rchanrt", "tchanrt",
"tchan", "rchan", "rflow";
};

View File

@@ -10,12 +10,25 @@
#include <dt-bindings/net/ti-dp83867.h>
/ {
compatible = "ti,am654-evm", "ti,am654";
compatible = "ti,am654-evm", "ti,am654";
model = "Texas Instruments AM654 Base Board";
aliases {
serial0 = &wkup_uart0;
serial1 = &mcu_uart0;
serial2 = &main_uart0;
i2c0 = &wkup_i2c0;
i2c1 = &mcu_i2c0;
i2c2 = &main_i2c0;
i2c3 = &main_i2c1;
i2c4 = &main_i2c2;
ethernet0 = &cpsw_port1;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
};
chosen {
stdout-path = "serial2:115200n8";
bootargs = "earlycon=ns16550a,mmio32,0x02800000";
};
memory@80000000 {
@@ -73,20 +86,20 @@
pinctrl-names = "default";
pinctrl-0 = <&push_button_pins_default>;
sw5 {
switch-5 {
label = "GPIO Key USER1";
linux,code = <BTN_0>;
gpios = <&wkup_gpio0 24 GPIO_ACTIVE_LOW>;
};
sw6 {
switch-6 {
label = "GPIO Key USER2";
linux,code = <BTN_1>;
gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>;
};
};
evm_12v0: fixedregulator-evm12v0 {
evm_12v0: regulator-0 {
/* main supply */
compatible = "regulator-fixed";
regulator-name = "evm_12v0";
@@ -96,7 +109,7 @@
regulator-boot-on;
};
vcc3v3_io: fixedregulator-vcc3v3io {
vcc3v3_io: regulator-1 {
/* Output of TPS54334 */
compatible = "regulator-fixed";
regulator-name = "vcc3v3_io";
@@ -107,7 +120,7 @@
vin-supply = <&evm_12v0>;
};
vdd_mmc1_sd: fixedregulator-sd {
vdd_mmc1_sd: regulator-2 {
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1_sd";
regulator-min-microvolt = <3300000>;
@@ -117,24 +130,53 @@
vin-supply = <&vcc3v3_io>;
gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>;
};
vtt_supply: regulator-3 {
compatible = "regulator-fixed";
regulator-name = "vtt";
pinctrl-names = "default";
pinctrl-0 = <&ddr_vtt_pins_default>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc3v3_io>;
gpio = <&wkup_gpio0 28 GPIO_ACTIVE_HIGH>;
};
};
&wkup_pmx0 {
wkup_i2c0_pins_default: wkup-i2c0-pins-default {
wkup_uart0_pins_default: wkup-uart0-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT, 0) /* (AB1) WKUP_UART0_RXD */
AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT, 0) /* (AB5) WKUP_UART0_TXD */
AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT, 1) /* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */
AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */
>;
};
ddr_vtt_pins_default: ddr-vtt-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP, 7) /* WKUP_GPIO0_28 */
>;
};
wkup_i2c0_pins_default: wkup-i2c0-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
>;
};
push_button_pins_default: push-button-pins-default {
push_button_pins_default: push-button-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */
AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */
>;
};
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */
@@ -150,13 +192,22 @@
>;
};
wkup_pca554_default: wkup-pca554-default {
wkup_pca554_default: wkup-pca554-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */
>;
};
mcu_cpsw_pins_default: mcu-cpsw-pins-default {
mcu_uart0_pins_default: mcu-uart0-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) /* (P4) MCU_OSPI1_D1.MCU_UART0_RXD */
AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) /* (P5) MCU_OSPI1_D2.MCU_UART0_TXD */
AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) /* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */
AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) /* (N3) MCU_OSPI1_CSn1.MCU_UART0_RTSn */
>;
};
mcu_cpsw_pins_default: mcu-cpsw-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
@@ -173,16 +224,23 @@
>;
};
mcu_mdio_pins_default: mcu-mdio1-pins-default {
mcu_mdio_pins_default: mcu-mdio1-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
>;
};
mcu_i2c0_pins_default: mcu-i2c0-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT, 0) /* (AD8) MCU_I2C0_SCL */
AM65X_WKUP_IOPAD(0x00ec, PIN_INPUT, 0) /* (AD7) MCU_I2C0_SDA */
>;
};
};
&main_pmx0 {
main_uart0_pins_default: main-uart0-pins-default {
main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
@@ -191,14 +249,14 @@
>;
};
main_i2c2_pins_default: main-i2c2-pins-default {
main_i2c2_pins_default: main-i2c2-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) GPMC0_CSn3.I2C2_SCL */
AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */
>;
};
main_spi0_pins_default: main-spi0-pins-default {
main_spi0_pins_default: main-spi0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */
AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */
@@ -207,7 +265,7 @@
>;
};
main_mmc0_pins_default: main-mmc0-pins-default {
main_mmc0_pins_default: main-mmc0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
@@ -224,7 +282,7 @@
>;
};
main_mmc1_pins_default: main-mmc1-pins-default {
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
@@ -237,7 +295,7 @@
>;
};
usb1_pins_default: usb1-pins-default {
usb1_pins_default: usb1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
>;
@@ -245,21 +303,21 @@
};
&main_pmx1 {
main_i2c0_pins_default: main-i2c0-pins-default {
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */
AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */
>;
};
main_i2c1_pins_default: main-i2c1-pins-default {
main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */
AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */
>;
};
ecap0_pins_default: ecap0-pins-default {
ecap0_pins_default: ecap0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
>;
@@ -269,19 +327,55 @@
&wkup_uart0 {
/* Wakeup UART is used by System firmware */
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
};
&mcu_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
};
&main_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};
&wkup_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
eeprom@50 {
/* AT24CM01 */
compatible = "atmel,24c1024";
reg = <0x50>;
};
vdd_mpu: regulator@60 {
compatible = "ti,tps62363";
reg = <0x60>;
regulator-name = "VDD_MPU";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1770000>;
regulator-always-on;
regulator-boot-on;
ti,vsel0-state-high;
ti,vsel1-state-high;
ti,enable-vout-discharge;
};
gpio@38 {
compatible = "nxp,pca9554";
reg = <0x38>;
gpio-controller;
#gpio-cells = <2>;
};
pca9554: gpio@39 {
compatible = "nxp,pca9554";
reg = <0x39>;
@@ -296,7 +390,15 @@
};
};
&mcu_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_i2c0_pins_default>;
clock-frequency = <400000>;
};
&main_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
@@ -310,37 +412,39 @@
};
&main_i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
};
&main_i2c2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c2_pins_default>;
clock-frequency = <400000>;
};
&ecap0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins_default>;
};
&main_spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_spi0_pins_default>;
#address-cells = <1>;
#size-cells= <0>;
#size-cells = <0>;
ti,pindir-d0-out-d1-in;
flash@0{
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
spi-max-frequency = <48000000>;
#address-cells = <1>;
#size-cells= <1>;
};
};
@@ -381,12 +485,14 @@
};
&tscadc0 {
status = "okay";
adc {
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
};
&tscadc1 {
status = "okay";
adc {
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
@@ -400,23 +506,8 @@
status = "disabled";
};
&pcie0_rc {
status = "disabled";
};
&pcie0_ep {
status = "disabled";
};
&pcie1_rc {
status = "disabled";
};
&pcie1_ep {
status = "disabled";
};
&mailbox0_cluster0 {
status = "okay";
interrupts = <436>;
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
@@ -426,6 +517,7 @@
};
&mailbox0_cluster1 {
status = "okay";
interrupts = <432>;
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
@@ -434,63 +526,24 @@
};
};
&mailbox0_cluster2 {
status = "disabled";
};
&mailbox0_cluster3 {
status = "disabled";
};
&mailbox0_cluster4 {
status = "disabled";
};
&mailbox0_cluster5 {
status = "disabled";
};
&mailbox0_cluster6 {
status = "disabled";
};
&mailbox0_cluster7 {
status = "disabled";
};
&mailbox0_cluster8 {
status = "disabled";
};
&mailbox0_cluster9 {
status = "disabled";
};
&mailbox0_cluster10 {
status = "disabled";
};
&mailbox0_cluster11 {
status = "disabled";
};
&mcu_r5fss0_core0 {
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
};
&mcu_r5fss0_core1 {
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>;
};
&ospi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
flash@0{
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
@@ -501,17 +554,65 @@
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <0>;
#address-cells = <1>;
#size-cells = <1>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "ospi.tiboot3";
reg = <0x0 0x80000>;
};
partition@80000 {
label = "ospi.tispl";
reg = <0x80000 0x200000>;
};
partition@280000 {
label = "ospi.u-boot";
reg = <0x280000 0x400000>;
};
partition@680000 {
label = "ospi.env";
reg = <0x680000 0x20000>;
};
partition@6a0000 {
label = "ospi.env.backup";
reg = <0x6a0000 0x20000>;
};
partition@6c0000 {
label = "ospi.sysfw";
reg = <0x6c0000 0x100000>;
};
partition@800000 {
label = "ospi.rootfs";
reg = <0x800000 0x37c0000>;
};
partition@3fe0000 {
label = "ospi.phypattern";
reg = <0x3fe0000 0x20000>;
};
};
};
};
&mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
pinctrl-0 = <&mcu_cpsw_pins_default>;
};
&davinci_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_mdio_pins_default>;
phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
@@ -524,30 +625,6 @@
phy-handle = <&phy0>;
};
&mcasp0 {
status = "disabled";
};
&mcasp1 {
status = "disabled";
};
&mcasp2 {
status = "disabled";
};
&dss {
status = "disabled";
};
&icssg0_mdio {
status = "disabled";
};
&icssg1_mdio {
status = "disabled";
};
&icssg2_mdio {
status = "disabled";
};

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {

View File

@@ -1,208 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018-2021 Texas Instruments Incorporated - http://www.ti.com/
*/
#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am65x-binman.dtsi"
/ {
chosen {
stdout-path = "serial2:115200n8";
};
aliases {
serial2 = &main_uart0;
ethernet0 = &cpsw_port1;
usb0 = &usb0;
usb1 = &usb1;
spi0 = &ospi0;
spi1 = &ospi1;
};
};
&cbass_main{
bootph-pre-ram;
main_navss: bus@30800000 {
bootph-pre-ram;
};
};
&cbass_mcu {
bootph-pre-ram;
mcu_navss: bus@28380000 {
bootph-pre-ram;
ringacc@2b800000 {
reg = <0x0 0x2b800000 0x0 0x400000>,
<0x0 0x2b000000 0x0 0x400000>,
<0x0 0x28590000 0x0 0x100>,
<0x0 0x2a500000 0x0 0x40000>,
<0x0 0x28440000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
bootph-pre-ram;
ti,dma-ring-reset-quirk;
};
dma-controller@285c0000 {
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x284c0000 0x0 0x4000>,
<0x0 0x2a800000 0x0 0x40000>,
<0x0 0x284a0000 0x0 0x4000>,
<0x0 0x2aa00000 0x0 0x40000>,
<0x0 0x28400000 0x0 0x2000>;
reg-names = "gcfg", "rchan", "rchanrt", "tchan",
"tchanrt", "rflow";
bootph-pre-ram;
};
};
};
&cbass_wakeup {
bootph-pre-ram;
chipid@43000014 {
bootph-pre-ram;
};
};
&secure_proxy_main {
bootph-pre-ram;
};
&dmsc {
bootph-pre-ram;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
bootph-pre-ram;
};
};
&k3_pds {
bootph-pre-ram;
};
&k3_clks {
bootph-pre-ram;
};
&k3_reset {
bootph-pre-ram;
};
&wkup_pmx0 {
bootph-pre-ram;
wkup_i2c0_pins_default {
bootph-pre-ram;
};
};
&main_pmx0 {
bootph-pre-ram;
usb0_pins_default: usb0_pins_default {
pinctrl-single,pins = <
AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
>;
bootph-pre-ram;
};
};
&main_uart0_pins_default {
bootph-pre-ram;
};
&main_pmx1 {
bootph-pre-ram;
};
&wkup_pmx0 {
mcu-fss0-ospi0-pins-default {
bootph-pre-ram;
};
};
&main_uart0 {
bootph-pre-ram;
};
&main_mmc0_pins_default {
bootph-pre-ram;
};
&main_mmc1_pins_default {
bootph-pre-ram;
};
&sdhci0 {
bootph-pre-ram;
};
&sdhci1 {
bootph-pre-ram;
};
&davinci_mdio {
phy0: ethernet-phy@0 {
reg = <0>;
/* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};
&mcu_cpsw {
reg = <0x0 0x46000000 0x0 0x200000>,
<0x0 0x40f00200 0x0 0x2>;
reg-names = "cpsw_nuss", "mac_efuse";
/delete-property/ ranges;
cpsw-phy-sel@40f04040 {
compatible = "ti,am654-cpsw-phy-sel";
reg= <0x0 0x40f04040 0x0 0x4>;
reg-names = "gmii-sel";
};
};
&wkup_i2c0 {
bootph-pre-ram;
};
&usb1 {
dr_mode = "peripheral";
};
&fss {
bootph-pre-ram;
};
&ospi0 {
bootph-pre-ram;
flash@0{
bootph-pre-ram;
};
};
&dwc3_0 {
status = "okay";
bootph-pre-ram;
};
&usb0_phy {
status = "okay";
bootph-pre-ram;
};
&usb0 {
pinctrl-names = "default";
pinctrl-0 = <&usb0_pins_default>;
dr_mode = "peripheral";
bootph-pre-ram;
};
&scm_conf {
bootph-pre-ram;
};

View File

@@ -1,29 +1,16 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include "k3-am654.dtsi"
#include "k3-am654-base-board.dts"
#include "k3-am654-base-board-u-boot.dtsi"
#include "k3-am654-base-board-ddr4-1600MTs.dtsi"
#include "k3-am654-ddr.dtsi"
/ {
compatible = "ti,am654-evm", "ti,am654";
model = "Texas Instruments AM654 R5 Base Board";
aliases {
serial0 = &wkup_uart0;
serial1 = &mcu_uart0;
serial2 = &main_uart0;
};
chosen {
stdout-path = "serial2:115200n8";
tick-timer = &timer1;
};
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
@@ -44,51 +31,6 @@
bootph-pre-ram;
};
vtt_supply: vtt_supply {
compatible = "regulator-gpio";
regulator-name = "vtt";
regulator-min-microvolt = <0>;
regulator-max-microvolt = <3300000>;
gpios = <&wkup_gpio0 28 GPIO_ACTIVE_HIGH>;
states = <0 0x0 3300000 0x1>;
bootph-pre-ram;
};
};
&cbass_main {
timer1: timer@40400000 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x40400000 0x0 0x80>;
ti,timer-alwon;
clock-frequency = <25000000>;
bootph-all;
};
};
&cbass_mcu {
mcu_secproxy: secproxy@28380000 {
compatible = "ti,am654-secure-proxy";
reg = <0x0 0x2a380000 0x0 0x80000>,
<0x0 0x2a400000 0x0 0x80000>,
<0x0 0x2a480000 0x0 0x80000>;
reg-names = "rt", "scfg", "target_data";
#mbox-cells = <1>;
bootph-pre-ram;
};
};
&wkup_gpio0 {
bootph-pre-ram;
};
&cbass_wakeup {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
mbox-names = "tx", "rx";
bootph-pre-ram;
};
clk_200mhz: dummy_clock {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -97,237 +39,120 @@
};
};
&secure_proxy_mcu {
status = "okay";
bootph-pre-ram;
};
&cbass_wakeup {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>;
mbox-names = "tx", "rx";
bootph-pre-ram;
};
};
/*
* timer init is called as part of rproc_start() while
* starting System Firmware, so any clock/power-domain
* operations will fail as SYSFW is not yet up and running.
* Delete all clock/power-domain properties to avoid
* timer init failure.
* This is an always on timer at 20MHz.
*/
&mcu_timer0 {
/delete-property/ clocks;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ power-domains;
};
&dmsc {
mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
mboxes = <&secure_proxy_mcu 8>,
<&secure_proxy_mcu 6>,
<&secure_proxy_mcu 5>;
mbox-names = "tx", "rx", "notify";
ti,host-id = <4>;
ti,secure-host;
};
&wkup_uart0 {
bootph-pre-ram;
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
status = "okay";
bootph-pre-ram;
};
&mcu_uart0 {
bootph-pre-ram;
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
clock-frequency = <48000000>;
/delete-property/ power-domains;
status = "okay";
};
&main_uart0 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
status = "okay";
bootph-pre-ram;
};
&wkup_vtm0 {
compatible = "ti,am654-vtm", "ti,am654-avs";
vdd-supply-3 = <&vdd_mpu>;
vdd-supply-4 = <&vdd_mpu>;
bootph-pre-ram;
};
&wkup_pmx0 {
bootph-pre-ram;
wkup_uart0_pins_default: wkup_uart0_pins_default {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT, 0) /* (AB1) WKUP_UART0_RXD */
AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT, 0) /* (AB5) WKUP_UART0_TXD */
AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT, 1) /* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */
AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */
>;
bootph-pre-ram;
};
wkup_vtt_pins_default: wkup_vtt_pins_default {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP, 7) /* WKUP_GPIO0_28 */
>;
bootph-pre-ram;
};
mcu_uart0_pins_default: mcu_uart0_pins_default {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) /* (P4) MCU_OSPI1_D1.MCU_UART0_RXD */
AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) /* (P5) MCU_OSPI1_D2.MCU_UART0_TXD */
AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) /* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */
AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) /* (N3) MCU_OSPI1_CSn1.MCU_UART0_RTSn */
>;
bootph-pre-ram;
};
wkup_i2c0_pins_default: wkup-i2c0-pins-default {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
>;
};
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins_default {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */
AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* (U4) MCU_OSPI0_D0 */
AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* (U5) MCU_OSPI0_D1 */
AM65X_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* (T2) MCU_OSPI0_D2 */
AM65X_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* (T3) MCU_OSPI0_D3 */
AM65X_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* (T4) MCU_OSPI0_D4 */
AM65X_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* (T5) MCU_OSPI0_D5 */
AM65X_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* (R2) MCU_OSPI0_D6 */
AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* (R3) MCU_OSPI0_D7 */
AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */
>;
};
};
&main_pmx0 {
bootph-pre-ram;
main_uart0_pins_default: main-uart0-pins-default {
pinctrl-single,pins = <
AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
>;
bootph-pre-ram;
};
main_mmc0_pins_default: main_mmc0_pins_default {
pinctrl-single,pins = <
AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
>;
bootph-pre-ram;
};
main_mmc1_pins_default: main_mmc1_pins_default {
pinctrl-single,pins = <
AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
>;
bootph-pre-ram;
};
};
&memorycontroller {
vtt-supply = <&vtt_supply>;
pinctrl-names = "default";
pinctrl-0 = <&wkup_vtt_pins_default>;
};
/*
* MMC is probed to pull in firmware, so any clock
* or power-domain operation will fail as we do not
* have the firmware running at this point. Delete the
* power-domain properties to avoid making calls to
* SYSFW before it is loaded. Public ROM has already
* set it up for us anyway.
*/
&sdhci0 {
clock-names = "clk_xin";
clocks = <&clk_200mhz>;
pinctrl-0 = <&main_mmc0_pins_default>;
/delete-property/ power-domains;
ti,driver-strength-ohm = <50>;
};
/*
* MMC is probed to pull in firmware, so any clock
* or power-domain operation will fail as we do not
* have the firmware running at this point. Delete the
* power-domain properties to avoid making calls to
* SYSFW before it is loaded. Public ROM has already
* set it up for us anyway.
*/
&sdhci1 {
clock-names = "clk_xin";
clocks = <&clk_200mhz>;
pinctrl-0 = <&main_mmc1_pins_default>;
/delete-property/ power-domains;
ti,driver-strength-ohm = <50>;
};
&wkup_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
bootph-pre-ram;
vdd_mpu: tps62363@60 {
compatible = "ti,tps62363";
reg = <0x60>;
regulator-name = "VDD_MPU";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1770000>;
regulator-always-on;
regulator-boot-on;
ti,vsel0-state-high;
ti,vsel1-state-high;
bootph-pre-ram;
};
};
&ospi0 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
reg = <0x0 0x47040000 0x0 0x100>,
<0x0 0x50000000 0x0 0x8000000>;
flash@0{
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <8>;
spi-max-frequency = <50000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <0>;
#address-cells = <1>;
#size-cells = <1>;
};
};
&main_pmx0 {
bootph-pre-ram;
usb0_pins_default: usb0_pins_default {
pinctrl-single,pins = <
AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
>;
bootph-pre-ram;
};
};
&dwc3_0 {
status = "okay";
bootph-pre-ram;
/delete-property/ clocks;
/delete-property/ power-domains;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
};
&usb0_phy {
status = "okay";
bootph-pre-ram;
/delete-property/ clocks;
&mcu_cpsw {
reg = <0x0 0x46000000 0x0 0x200000>,
<0x0 0x40f00200 0x0 0x2>;
reg-names = "cpsw_nuss", "mac_efuse";
/delete-property/ ranges;
cpsw-phy-sel@40f04040 {
compatible = "ti,am654-cpsw-phy-sel";
reg= <0x0 0x40f04040 0x0 0x4>;
reg-names = "gmii-sel";
};
};
&usb0 {
pinctrl-names = "default";
pinctrl-0 = <&usb0_pins_default>;
&usb1 {
dr_mode = "peripheral";
bootph-pre-ram;
};
&scm_conf {
bootph-pre-ram;
};

View File

@@ -93,6 +93,7 @@
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
@@ -102,6 +103,7 @@
L2_1: l2-cache1 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
@@ -111,5 +113,10 @@
msmc_l3: l3-cache0 {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
thermal_zones: thermal-zones {
#include "k3-am654-industrial-thermal.dtsi"
};
};

View File

@@ -22,7 +22,7 @@
};
&main_pmx0 {
main_mmc0_pins_default: main-mmc0-pins-default {
main_mmc0_pins_default: main-mmc0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
@@ -50,7 +50,3 @@
ti,driver-strength-ohm = <50>;
disable-wp;
};
&main_uart0 {
status = "disabled";
};

View File

@@ -27,26 +27,26 @@
};
&main_pmx0 {
main_m2_enable_pins_default: main-m2-enable-pins-default {
main_m2_enable_pins_default: main-m2-enable-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */
>;
};
main_bkey_pcie_reset: main-bkey-pcie-reset {
main_bkey_pcie_reset: main-bkey-pcie-reset-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01bc, PIN_OUTPUT_PULLUP, 7) /* (AG13) GPIO1_15 */
>;
};
main_pmx0_m2_config_pins_default: main-pmx0-m2-config-pins-default {
main_pmx0_m2_config_pins_default: main-pmx0-m2-config-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01c8, PIN_INPUT_PULLUP, 7) /* (AE13) GPIO1_18 */
AM65X_IOPAD(0x01cc, PIN_INPUT_PULLUP, 7) /* (AD13) GPIO1_19 */
>;
};
main_m2_pcie_mux_control: main-m2-pcie-mux-control {
main_m2_pcie_mux_control: main-m2-pcie-mux-control-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0148, PIN_INPUT_PULLUP, 7) /* (AG22) GPIO0_82 */
AM65X_IOPAD(0x0160, PIN_INPUT_PULLUP, 7) /* (AE20) GPIO0_88 */
@@ -56,7 +56,7 @@
};
&main_pmx1 {
main_pmx1_m2_config_pins_default: main-pmx1-m2-config-pins-default {
main_pmx1_m2_config_pins_default: main-pmx1-m2-config-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0018, PIN_INPUT_PULLUP, 7) /* (B22) GPIO1_88 */
AM65X_IOPAD(0x001c, PIN_INPUT_PULLUP, 7) /* (C23) GPIO1_89 */
@@ -66,20 +66,18 @@
&main_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <
&main_m2_pcie_mux_control
&arduino_io_d4_to_d9_pins_default
>;
pinctrl-0 =
<&main_m2_pcie_mux_control>,
<&arduino_io_d4_to_d9_pins_default>;
};
&main_gpio1 {
pinctrl-names = "default";
pinctrl-0 = <
&main_m2_enable_pins_default
&main_pmx0_m2_config_pins_default
&main_pmx1_m2_config_pins_default
&cp2102n_reset_pin_default
>;
pinctrl-0 =
<&main_m2_enable_pins_default>,
<&main_pmx0_m2_config_pins_default>,
<&main_pmx1_m2_config_pins_default>,
<&cp2102n_reset_pin_default>;
};
/*

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
* This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.6.0
* This file was generated on 06/01/2021
*/

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-j721e-binman.dtsi"

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
* This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.9.1
* This file was generated on 07/17/2022
*/

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
* This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.6.1
* This file was generated on 07/19/2021
*/

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;

View File

@@ -2,7 +2,7 @@
/*
* Device Tree Source for Keystone 2 clock tree
*
* Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
clocks {

View File

@@ -2,7 +2,7 @@
/*
* Keystone 2 Edison SoC specific device tree
*
* Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
clocks {

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/{

View File

@@ -2,7 +2,7 @@
/*
* Keystone 2 Edison EVM device tree
*
* Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;

View File

@@ -2,7 +2,7 @@
/*
* Device Tree Source for Keystone 2 Edison Netcp driver
*
* Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
qmss: qmss@2a40000 {

View File

@@ -2,7 +2,7 @@
/*
* Keystone 2 Edison soc device tree
*
* Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/{

View File

@@ -2,7 +2,7 @@
/*
* Device Tree Source for K2G EVM
*
* Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/{

View File

@@ -2,7 +2,7 @@
/*
* Device Tree Source for Generic 66AK2G0X EVM
*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/{

View File

@@ -2,7 +2,7 @@
/*
* Device Tree Source for K2G Industrial Communication Engine EVM
*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;

View File

@@ -2,7 +2,7 @@
/*
* Device Tree Source for K2G Netcp driver
*
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
qmss: qmss@4020000 {

View File

@@ -2,7 +2,7 @@
/*
* Device Tree Source for K2G SOC
*
* Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>

View File

@@ -2,7 +2,7 @@
/*
* Keystone 2 Kepler/Hawking SoC clock nodes
*
* Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
clocks {

Some files were not shown because too many files have changed in this diff Show More