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Reformat spacing/comments in src/jtagmkI_private.h
This commit is contained in:
Stefan Rueger
@@ -17,73 +17,66 @@
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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// JTAG ICE mkI definitions
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/*
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* JTAG ICE mkI definitions
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*/
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// ICE command codes
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/* ICE command codes */
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/* 0x20 Get Synch [Resp_OK] */
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// 0x20 Get Synch [Resp_OK]
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#define CMD_GET_SYNC ' '
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/* 0x31 Single Step [Sync_CRC/EOP] [Resp_OK] */
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/* 0x32 Read PC [Sync_CRC/EOP] [Resp_OK] [program counter]
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* [Resp_OK] */
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/* 0x33 Write PC [program counter] [Sync_CRC/EOP] [Resp_OK]
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* [Resp_OK] */
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/* 0xA2 Firmware Upgrade [upgrade string] [Sync_CRC/EOP] [Resp_OK]
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* [Resp_OK] */
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/* 0xA0 Set Device Descriptor [device info] [Sync_CRC/EOP] [Resp_OK]
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* [Resp_OK] */
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// 0x31 Single Step [Sync_CRC/EOP] [Resp_OK]
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// 0x32 Read PC [Sync_CRC/EOP] [Resp_OK] [program counter] [Resp_OK]
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// 0x33 Write PC [program counter] [Sync_CRC/EOP] [Resp_OK] [Resp_OK]
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// 0xA2 Firmware Upgrade [upgrade string] [Sync_CRC/EOP] [Resp_OK] [Resp_OK]
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// 0xA0 Set Device Descriptor [device info] [Sync_CRC/EOP] [Resp_OK] [Resp_OK]
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#define CMD_SET_DEVICE_DESCRIPTOR 0xA0
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/* 0x42 Set Parameter [parameter] [setting] [Sync_CRC/EOP] [Resp_OK]
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* [Resp_OK] */
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// 0x42 Set Parameter [parameter] [setting] [Sync_CRC/EOP] [Resp_OK] [Resp_OK]
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#define CMD_SET_PARAM 'B'
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/* 0x46 Forced Stop [Sync_CRC/EOP] [Resp_OK] [checksum][program
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* counter] [Resp_OK] */
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// 0x46 Forced Stop [Sync_CRC/EOP] [Resp_OK] [checksum][program counter] [Resp_OK]
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#define CMD_STOP 'F'
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/* 0x47 Go [Sync_CRC/EOP] [Resp_OK] */
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// 0x47 Go [Sync_CRC/EOP] [Resp_OK]
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#define CMD_GO 'G'
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/* 0x52 Read Memory [memory type] [word count] [start address]
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* [Sync_CRC/EOP] [Resp_OK] [word 0] ... [word n] [checksum]
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* [Resp_OK] */
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// 0x52 Read Memory [memory type] [word count] [start address] [Sync_CRC/EOP] [Resp_OK] [word 0] ... [word n] [checksum] [Resp_OK]
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#define CMD_READ_MEM 'R'
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/* 0x53 Get Sign On [Sync_CRC/EOP] [Resp_OK] ["AVRNOCD"] [Resp_OK] */
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// 0x53 Get Sign On [Sync_CRC/EOP] [Resp_OK] ["AVRNOCD"] [Resp_OK]
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#define CMD_GET_SIGNON 'S'
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/* 0XA1 Erase Page spm [address] [Sync_CRC/EOP] [Resp_OK] [Resp_OK] */
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// 0xa1 Erase Page spm [address] [Sync_CRC/EOP] [Resp_OK] [Resp_OK]
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/* 0x57 Write Memory [memory type] [word count] [start address]
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* [Sync_CRC/EOP] [Resp_OK] [Cmd_DATA] [word 0] ... [word n] */
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// 0x57 Write Memory [memory type] [word count] [start address] [Sync_CRC/EOP] [Resp_OK] [Cmd_DATA] [word 0] ... [word n]
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#define CMD_WRITE_MEM 'W'
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/* Second half of write memory: the data command. Undocumented. */
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// Second half of write memory: the data command; undocumented
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#define CMD_DATA 'h'
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/* 0x64 Get Debug Info [Sync_CRC/EOP] [Resp_OK] [0x00] [Resp_OK] */
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// 0x64 Get Debug Info [Sync_CRC/EOP] [Resp_OK] [0x00] [Resp_OK]
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/* 0x71 Get Parameter [parameter] [Sync_CRC/EOP] [Resp_OK] [setting]
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* [Resp_OK] */
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#define CMD_GET_PARAM 'q'
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/* 0x78 Reset [Sync_CRC/EOP] [Resp_OK] [Resp_OK] */
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// 0x78 Reset [Sync_CRC/EOP] [Resp_OK] [Resp_OK]
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#define CMD_RESET 'x'
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/* 0xA3 Enter Progmode [Sync_CRC/EOP] [Resp_OK] [Resp_OK] */
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// 0xA3 Enter Progmode [Sync_CRC/EOP] [Resp_OK] [Resp_OK]
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#define CMD_ENTER_PROGMODE 0xa3
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/* 0xA4 Leave Progmode [Sync_CRC/EOP] [Resp_OK] [Resp_OK] */
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// 0xA4 Leave Progmode [Sync_CRC/EOP] [Resp_OK] [Resp_OK]
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#define CMD_LEAVE_PROGMODE 0xa4
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/* 0xA5 Chip Erase [Sync_CRC/EOP] [Resp_OK] [Resp_OK] */
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// 0xA5 Chip Erase [Sync_CRC/EOP] [Resp_OK] [Resp_OK]
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#define CMD_CHIP_ERASE 0xa5
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/* ICE responses */
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// ICE responses
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#define RESP_OK 'A'
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#define RESP_BREAK 'B'
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#define RESP_INFO 'G'
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@@ -130,37 +123,33 @@
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#define JTAG_BITRATE_250_kHz 0xfd
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#define JTAG_BITRATE_125_kHz 0xfb
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/* memories for CMND_{READ,WRITE}_MEMORY */
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#define MTYPE_IO_SHADOW 0x30 /* cached IO registers? */
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#define MTYPE_SRAM 0x20 /* target's SRAM or [ext.] IO registers */
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#define MTYPE_EEPROM 0x22 /* EEPROM, what way? */
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#define MTYPE_EVENT 0x60 /* ICE event memory */
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#define MTYPE_SPM 0xA0 /* flash through LPM/SPM */
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#define MTYPE_FLASH_PAGE 0xB0 /* flash in programming mode */
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#define MTYPE_EEPROM_PAGE 0xB1 /* EEPROM in programming mode */
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#define MTYPE_FUSE_BITS 0xB2 /* fuse bits in programming mode */
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#define MTYPE_LOCK_BITS 0xB3 /* lock bits in programming mode */
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#define MTYPE_SIGN_JTAG 0xB4 /* signature in programming mode */
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#define MTYPE_OSCCAL_BYTE 0xB5 /* osccal cells in programming mode */
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// Memories for CMND_{READ,WRITE}_MEMORY
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#define MTYPE_IO_SHADOW 0x30 // Cached IO registers?
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#define MTYPE_SRAM 0x20 // Target's SRAM or [ext.] IO registers
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#define MTYPE_EEPROM 0x22 // EEPROM, what way?
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#define MTYPE_EVENT 0x60 // ICE event memory
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#define MTYPE_SPM 0xA0 // Flash through LPM/SPM
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#define MTYPE_FLASH_PAGE 0xB0 // Flash in programming mode
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#define MTYPE_EEPROM_PAGE 0xB1 // EEPROM in programming mode
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#define MTYPE_FUSE_BITS 0xB2 // Fuse bits in programming mode
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#define MTYPE_LOCK_BITS 0xB3 // Lock bits in programming mode
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#define MTYPE_SIGN_JTAG 0xB4 // Signature in programming mode
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#define MTYPE_OSCCAL_BYTE 0xB5 // Osccal cells in programming mode
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struct device_descriptor
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{
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unsigned char ucReadIO[8]; /*LSB = IOloc 0, MSB = IOloc63 */
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unsigned char ucWriteIO[8]; /*LSB = IOloc 0, MSB = IOloc63 */
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unsigned char ucReadIOShadow[8]; /*LSB = IOloc 0, MSB = IOloc63 */
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unsigned char ucWriteIOShadow[8]; /*LSB = IOloc 0, MSB = IOloc63 */
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unsigned char ucReadExtIO[20]; /*LSB = IOloc 96, MSB = IOloc255 */
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unsigned char ucWriteExtIO[20]; /*LSB = IOloc 96, MSB = IOloc255 */
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unsigned char ucReadIOExtShadow[20]; /*LSB = IOloc 96, MSB = IOloc255 */
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unsigned char ucWriteIOExtShadow[20];/*LSB = IOloc 96, MSB = IOloc255 */
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unsigned char ucIDRAddress; /*IDR address */
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unsigned char ucSPMCRAddress; /*SPMCR Register address and dW BasePC */
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unsigned char ucRAMPZAddress; /*RAMPZ Register address in SRAM I/O */
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/*space */
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unsigned char uiFlashPageSize[2]; /*Device Flash Page Size, Size = */
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/*2 exp ucFlashPageSize */
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unsigned char ucEepromPageSize; /*Device Eeprom Page Size in bytes */
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unsigned char ulBootAddress[4]; /*Device Boot Loader Start Address */
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unsigned char uiUpperExtIOLoc; /*Topmost (last) extended I/O */
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/*location, 0 if no external I/O */
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struct device_descriptor {
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unsigned char ucReadIO[8]; // LSB = IOloc 0, MSB = IOloc63
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unsigned char ucWriteIO[8]; // LSB = IOloc 0, MSB = IOloc63
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unsigned char ucReadIOShadow[8]; // LSB = IOloc 0, MSB = IOloc63
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unsigned char ucWriteIOShadow[8]; // LSB = IOloc 0, MSB = IOloc63
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unsigned char ucReadExtIO[20]; // LSB = IOloc 96, MSB = IOloc255
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unsigned char ucWriteExtIO[20]; // LSB = IOloc 96, MSB = IOloc255
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unsigned char ucReadIOExtShadow[20]; // LSB = IOloc 96, MSB = IOloc255
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unsigned char ucWriteIOExtShadow[20]; // LSB = IOloc 96, MSB = IOloc255
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unsigned char ucIDRAddress; // IDR address
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unsigned char ucSPMCRAddress; // SPMCR Register address and dW BasePC
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unsigned char ucRAMPZAddress; // RAMPZ Register address in SRAM I/O space
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unsigned char uiFlashPageSize[2]; // Device Flash Page Size, Size = 2 exp ucFlashPageSize
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unsigned char ucEepromPageSize; // Device Eeprom Page Size in bytes
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unsigned char ulBootAddress[4]; // Device Boot Loader Start Address
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unsigned char uiUpperExtIOLoc; // Topmost (last) extended I/O location, 0 if no external I/O
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};
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