build from:
9fffbe1e78 rk3588: ddr: adjust hash description
update feature:
1. Modify the LPDDR5 frequency to improve stability.
2. Add support dram with CS0 capacity less than CS1 capacity.
3. Modify the DERATEINT.mr4_read_interval configuration.
4. Fixed derate issue with LPDDR5 of one rank.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Change-Id: Id6f200c8ed9ec4f71f79b8050608cb928658a276
build from:
d5483af87d rk3588: ddr: update to v1.15
update feature:
1. avoid PHY skew value greater than dll lock value
2. fix the data training process
3. resume ZQ background calibration for LPDDR5
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Change-Id: I5857feb0a51e13d432f5bc8026263f4b57a64d6d
Build from:
e4e124926e rockchip: spl: Fix fwver prefix
Build command:
./make.sh rk3588 --spl-new --spl-fwver v1.13
Update features:
1. Print and pass the firmware version number.
2. Solve the issue that the backup image is not loaded when
the SPL load or check u-boot.dtb fails.
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>
Change-Id: If05e0578a67032ee2ff3ee24822dbdf2bc73f831
build from:
25cee80c4f rk3588: ddr: fix LPDDR5 528MHz write training issue
update feature:
1. fix LPDDR5 528MHz write training issue
2. fsp_param update vref_inner for each channel
3. Support both per-bank refresh and derating enabled
Note: BL31 should be update to V1.41
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Change-Id: I78f0d2ab4f10b71330ce677c4f6ae0d31d982ef2
build from:
52218f4949 rk3588: ddr: add support print_train_result and print_mr
update feature:
1. Add support print_train_result and print_mr
1. Fixed init fail issue that max freq between 1066-1600MHz.
2. Fixed the issue panic in ddrbin caused by multiple initialization of DDR.
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Change-Id: I6fd0bf78a17321ebf2a58608e6fbc173bc895c5b
build from:
f1474cf52f rk3588: ddr: add support spread spectrum mode
update feature:
1. Added more print info when initialization fails to help locate
soldering issues.
2. Optimizing boot time.
3. enable per bank refresh function.
4. LPDDR5 4 channels use different write vref values to improve
stability.
5. First init LPDDR4x.
6. LPDDR5 cavref update to 36%.
7. Add support spread spectrum mode.
Note: BL31 should be update to V1.38
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: Ie822436500e3d778ba8787e7155e561091d1d997
from commit:
f04a3d: platform: rk3588: pmu os reg change to pmu0.
update feature:
Support spiflash.
Change-Id: I396e408307061c059c32292c3264c35faf6169f6
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
build from:
bdb740d4da rockchip: board: update with new envf support
build command:
./make.sh rk3588
update feature:
clk: rockchip: rk3588: set b0pll b1pll to 1200M in SPL
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Iafdd118cb70d363d636803c06b25f90140a1d290
The WORD_2[4:0] is used to assign boot cpu hwid,
ie. 0, 1, 2 ... 31, etc.
This feature depends on:
(d7ff10e rk3588: ddr: update ddr bin to v1.06)
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I9675f6eae088dc2d55bf172774806648ba86e668
build from:
74cb20d2b7 rk3588: ddr: update ddr bin to v1.04
build command:
./make.sh rk3588
update feature:
9ff0a6b00f rk3588: ddr: phy preset assert time add to 10us
5b8bbbb17c rk3588: ddr: ddr useful address 1MB align for kernel
c573e8eee3 rk3588: ddr: set EN_LOW_POWER(0) to disable dfi lp cfg
39846fffa8 rk3588: ddr: enable change frequency for LPDDR4
363a13da91 rk3588: ddr: fix the code about test for DFS/SUSPEND/REBOOT
65dd9468d2 rk3588: ddr: set DFILPCFG0.dfi_lp_en_data to 0
574deae90a rk3588: ddr: add memset for sdram_params_fsp in ddr_set_rate
4872d02a4e rk3588: ddr: enable PHY VTC at any frequency
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Change-Id: Id4854bed49b79eae8947952f46892b8d10ef0f0c
