Don't copy 1024 bits RSA_KEY_DATA to uboot, that means not
support soft sign.
Change-Id: I9abc52d9630c188b2d13a9a6f3512586d5dbbc03
Signed-off-by: William Zhang <william.zhang@rock-chips.com>
1. enable read efuse_non_secure data for kernel
2. config SGRF according to efuse_non_secure data
Change-Id: Ica3ca04ba1d8dbbfed256bb1ee270fea2db5bab2
Signed-off-by: William Zhang <william.zhang@rock-chips.com>
when detect gpio wakeup before wfi instruction, give up system
suspend and resume plls
Change-Id: I70713d6e5e25e654ea0a4089e7690dc72591515d
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>
This patch intend to support save the registers of the DDR controller
and PHY before suspend, and restore them after resume.
Change-Id: Ia2cc6664baa4116be4587e6ad3023ce325270fc0
Signed-off-by: Shengfei xu <xsf@rock-chips.com>
To fix suspend issue during ddr changing frequency, build based on
the commit of arm-trusted-firmware:
6b958c9c6fced39be0e86ccbbc5aa61aef8b3315
Change-Id: Ib1df36e4a706a782262b9ad24c8f5c12c74e751c
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Support soft sign 1024bits RSA key only
Change-Id: Ie1e9aaf6cbe362e1c9e4739ce44bd2548b97bd59
Signed-off-by: William Zhang <william.zhang@rock-chips.com>
compile cmd:
make px5_defconfig
make ARCHV=aarch64
ini, must modify this two file:
tools/rk_tools/RKBOOT/PX5MINIALL.ini
tools/rk_tools/RKTRUST/PX5TRUST.ini
Change-Id: I81250ebc3b49b59cff64a05f86d7ed19a13a6a7d
Signed-off-by: Jason Song <sxj@rock-chips.com>
Amend msch ddrconfig register write error and make sure row numbers
configure in msch is equal to row numbers configure in ddr controller
Change-Id: I03f673075ffc68f177a65e08a50896144eda1b4b
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
All DRAM type init frequency increase to 400MHz,
because some type of screen display gilitter before
kernel set DDR rate to high frequency.
Change-Id: I519b606db92e10ae6807efecf361fe2379cbf28d
Signed-off-by: Hecanyang <hcy@rock-chips.com>
1. enable lpddr4 mask write
2. support only one channel
Change-Id: I64eec491abb35203d8055c8dffa111bcfdb1a710
Signed-off-by: Hecanyang <hcy@rock-chips.com>
1) Open RPMB support for rk322x_tee_ta.bin
2) Only modify build options (CFG_RPMB_FS for RPMB support),
don't need to change version
Change-Id: I4629621a0e99235da2f96b181c1cb622b0595511
Signed-off-by: csx <csx@rock-chips.com>
1) increase tee_ta_v1.5.bin for with ta
2) change version number to v1.5
Change-Id: I2b793b30a6282c0842a909908dfc709eddd8f567
Signed-off-by: csx <csx@rock-chips.com>
2GB/1cs per channel, ddr init error.
fix this bug to support 2GB/1cs per channel.
2GB/1cs that is: row=16, col=10, bank=3, bw=2, cs=1
Change-Id: I222d1615d3df2c01312a04e5e0beab96fc1c2354
Signed-off-by: Hecanyang <hcy@rock-chips.com>
customer find 4GB LPDDR3 performance is poor than 2GB, after analyse,
we find the reason is: 4GB just select a more low power setting, but
it effect the performance. so this version we just select the more
performance setting, no longer select the more low power setting.
Change-Id: I8899d19d6b8456e6a67f3cccbfbdd27c31b821f9
Signed-off-by: Hecanyang <hcy@rock-chips.com>
ddr init bin update to version 1.17 20160513 to fix bug about 4GB dram
detect fail.
Change-Id: Ib1ddc6409cda1040f4e8dd37ac8f0433ea2c217d
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
