Build from ATF commit:
bc02fdb23 plat: rk3588: support booting from the cpu according to atags.
Update feature:
bc02fdb23 plat: rk3588: support booting from the cpu according to atags.
3f58c537b rockchip: common: Add boot1 param for atags
a8b89552b plat: rockchip: rk3588: dmc: ddr_m0: fix the mistake about idle_ddrsch
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I98cebd043832600634aa37fcb55eedccd78256ff
build from:
bdb740d4da rockchip: board: update with new envf support
build command:
./make.sh rk3588
update feature:
clk: rockchip: rk3588: set b0pll b1pll to 1200M in SPL
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Iafdd118cb70d363d636803c06b25f90140a1d290
The WORD_2[4:0] is used to assign boot cpu hwid,
ie. 0, 1, 2 ... 31, etc.
This feature depends on:
(d7ff10e rk3588: ddr: update ddr bin to v1.06)
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I9675f6eae088dc2d55bf172774806648ba86e668
Build from OPTEE commit in develop-next branch:
9d22c1e96 rk3588: support R&W oem ns otp
Update features:
9d22c1e96 rk3588: support R&W oem ns otp
3f0f0b052 pta: support check oem otp key is written
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: I7fb445fb1202e32ddbbc37cde78ccac79b5e8c32
build from RK3326_DDR_Init_Simple:
c8ac34ce rk3326/rk3326-s: Update DDR bin to V2.04 20220121
update feature:
255e5ca0 rk3326/rk3326-s: Set dfi_lp_wakeup_sr/pd to 0x0
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: I267bf5c6c1389695112b665371d57fccadb9a5d4
build from RK3326_DDR_Init_Simple:
980d865192 rk3326/rk3326-s: Update DDR bin to V2.03 20220121
update feature:
da0ff2abaa rk3326-s: Set ca_odt(REG0x40[13:12]) of LPDDR4 according to bw
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: I3b8f9bcf96841815b88e3772d7a3a808eb2435d5
Build from ATF commit:
378cb8595 plat: rockchip: rk3588: dmc: support ddr frequency scan after dmc resume
The ATF code for this version is same with The ATF code for v1.12.
Change-Id: Ibdf3603321ed5155c7623bfcf9b2200a3af45a81
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
build from RK3326_DDR_Init_Simple:
d6f4cb05c9 rk3326/rk3326-s: Update DDR bin to V2.02 20220118
update feature:
6faa6a326a rk3326-s: Set VDD_logic to 1.0V
8e81392239 rk3326-s: Disable some low power functions to prevent sleep and resume
(level 2) fail
9590d94add px30s: can not support row = 17 of lp4
c699c118bb px30s: modify dfi_tlp_resp to 0xa
df3d5d15fc px30s: modify vdd_logic to 0.9v
0fa00910a4 px30s: clear ddr clk gate for soft reset
08f7c28847 rk3326/rk3326s: Optimize the size of ddr bin
153b747d5f rk3326-s: Fix get_uboot_params() when sdram_params->ch.row_3_4 == 1
3b83b56391 rk3326s: set logic to 1.0V
a8eced54fb rk3326/s: all dram bring up ok
b280140e97 rk3326/s: add debug info
c4b391e8b4 rk3326/rk3326s: modify dfi timing for lp3/2
cec9c2868b rk3326/rk3326s: diff dfi tctrl_delay setting
de967f4b65 rk3326/rk3326s: modify dfi timing
fa9c9e3f4f rk3326s: add fix drv odt config
c534fef2c6 rk3326s: add support lp4
69776fa864 rk3326: inc: add rk3326s phy reg
3a1078c07d RK3326S: modify to PHY_REG_3326S define
fc7426a9a7 rk3326/S: save and restore arm special reg
2651ce4f97 rk3326/S: add check return to smc code
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: Id91158b3d6decc57366dc3259e232f24da6b64ce
Build from OPTEE commit in develop-next branch:
631d7ed9a pta: modify secure boot enable flag for rk3568
Update features:
631d7ed9a pta: modify secure boot enable flag for rk3568
be93c3390 Revert "pta: modify secure boot enable flag length for rk3568"
3f0f0b052 pta: support check oem otp key is written
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: I3e8f84e6c20bf452ce486e61f3ac63f64e80239e
build from:
74cb20d2b7 rk3588: ddr: update ddr bin to v1.04
build command:
./make.sh rk3588
update feature:
9ff0a6b00f rk3588: ddr: phy preset assert time add to 10us
5b8bbbb17c rk3588: ddr: ddr useful address 1MB align for kernel
c573e8eee3 rk3588: ddr: set EN_LOW_POWER(0) to disable dfi lp cfg
39846fffa8 rk3588: ddr: enable change frequency for LPDDR4
363a13da91 rk3588: ddr: fix the code about test for DFS/SUSPEND/REBOOT
65dd9468d2 rk3588: ddr: set DFILPCFG0.dfi_lp_en_data to 0
574deae90a rk3588: ddr: add memset for sdram_params_fsp in ddr_set_rate
4872d02a4e rk3588: ddr: enable PHY VTC at any frequency
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Change-Id: Id4854bed49b79eae8947952f46892b8d10ef0f0c
from commit:
rk_boot_all: c8f9c9884801: rockchip: px30s: set the emmc drive strength
update feature:
- set the emmc data(GPIO1A0-A7) drive strength to 14.2ma
- set the emmc clock(GPIO1B1) drive strength to 23.7ma
- set the emmc cmd(GPIO1B2) drive strength to 14.2ma
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I476fa0b93b6abf801ac837b67ff1a0dbd7ddeeaa
from commit:
rk_boot_all: a9c0f paltform: rk3326: Update to v1.35
update feature:
Support GD9F4GxF2A device
Change-Id: Ib0923ac0917e2cca63eef85acc2731ca9887cd88
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from OPTEE commit in develop-next branch:
3f0f0b0528 pta: support check oem otp key is written
Update features:
3f0f0b0528 pta: support check oem otp key is written
9af9076b0b rockchip: sys_ctrl: move sys ctrl code to common/ dir
b3f212d172 drivers: rockchip: hal_crypto: add pd crypto enable for rv1126
Signed-off-by: xb.wang <xb.wang@rock-chips.com>
Change-Id: If055254b1f90393600afe56178b0fdd2944f4690
Build from OPTEE commit in develop-next branch:
3f0f0b052 pta: support check oem otp key is written
Update features:
3f0f0b052 pta: support check oem otp key is written
1c3940902 drivers: rockchip: keylad: enable dst ip clk when copy key
9af9076b0 rockchip: sys_ctrl: move sys ctrl code to common/ dir
4afa4e8c1 pta: modify secure boot enable flag length for rk3568
48b7c13e2 pta: uboot_storedata_otp: modify parameter check
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: Ibebe59e45e26d96b64773e32c7cab14d77eb9bfa
Build from OPTEE commit in develop-next branch:
3f0f0b052 pta: support check oem otp key is written
Update features:
3f0f0b052 pta: support check oem otp key is written
1c3940902 drivers: rockchip: keylad: enable dst ip clk when copy key
16d1058cf drivers: crypto: use system control interface on rk3588
6f2a478ad rk3588: otp: use system control interface
946794c64 drivers: rockchip: keylad: use system control interface on rk3588
464a252af drivers: rockchip: trng: use system control interface on rk3588
9af9076b0 rockchip: sys_ctrl: move sys ctrl code to common/ dir
48b7c13e2 pta: uboot_storedata_otp: modify parameter check
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: I9c8d363f266146949d130aa08e8a4b907e897ebe
Build from ATF commit:
a91da4072 plat: rk3588: don't check cpu wfe/wfi status in nonboot_cpus_off_check
update features:
a91da4072 plat: rk3588: don't check cpu wfe/wfi status in nonboot_cpus_off_check
4212c266b plat: rk3588: use external 32k clock by default
fb149d4cb plat: rockchip: rk3588: scmi: Make dsu clk come from lpll
c73f5cbd4 plat: rockchip: rk3588: scmi: set pclk dsu clk rate to 200MHz
a24e55c55 plat: rk3588: enable hptimer calibrate with 32k clock
Change-Id: I7594aeb76317f60a9c0d1b3642654e436f3a03f4
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
build from:
0b7dfcad0 bsp: rockchip: drivers: camera: os04c: set target setpoint as same as IQ
update feature:
0b7dfcad0 bsp: rockchip: drivers: camera: os04c: set target setpoint as same as IQ
8758b55cb [bsp] rockchip: tools: add FastAE parameter generator
64a0a2678 stream/camera_drv: declare cfg_ae_info for each sensor
fe9acc89d isp_app/stream: make log meaningfully
d80c4e475 isp_app/stream: enqueue raw buffer whilst the frame is vaild
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: Ic06e853a59a1de6d273f5ef1d177ff1e45e2f989
