Build from u-boot-ddr:
c44e2c2649 drivers: ram: rv1106: Initial version v1.02 20220330
(https://10.10.10.29/c/rk/u-boot-ddr/+/145841/37)
and change baudrate to 115200
Update feature:
Change baudrate to 115200
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: Ic18c28757ae38670e27e5a1a0f6cc94ba4271f27
from commit:
rk_boot_all: fb9f8e: src: spinor: Support new spiflash
update feature:
Support new spiflash
Change-Id: I634d9f1707da419bafa3bf8d42778c8e758fe7c7
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from u-boot-ddr:
c44e2c2649 drivers: ram: rv1106: Initial version v1.02 20220330
(https://10.10.10.29/c/rk/u-boot-ddr/+/145841/37)
Update feature:
c44e2c2649 drivers: ram: rv1106: Initial version v1.02 20220330
(https://10.10.10.29/c/rk/u-boot-ddr/+/145841/37)
1. Fix 328MHz to 324MHz, 664MHz to 660MHz, 784MHz to 780MHz
2. Fix ReadLatency of NOC (-50)
3. Delete DQ skew cfg of DDR2
4. Set DeviceSize of NOC
5. Fix PHY PLL set
6. Fix wrong calc of wrlvl_info.tdqss_min/max
7. Fix wrong set of tRFC
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: I78755018346355647a28e5b85ee2ee390c49605d
Build from ATF commit:
7380d9813 plat: rockchip: rk3588: dmc: configure sr_en and pd_en based on idle value
update feature:
7380d9813 plat: rockchip: rk3588: dmc: configure sr_en and pd_en based on idle value
fedf3922d plat: rockchip: rk3588: dmc: add support LPDDR5 frequency scan
9328b4ce3 plat: rockchip: rk3588: dmc: clrbit RD_CAL_MODE if rd deskew is 0
Change-Id: Id5c38d95b2f74a17c03c7b3ff04345ddc66c947b
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
from commit:
rk_boot_all: 209c77: src: spinand: Add SNAND tag for spinand PC tools
Update feature:
src: spinand: Add SNAND tag for spinand PC tools
Change-Id: Id03fc440a9d987c974bce0736e4494b5e0e939d5
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from u-boot-ddr:
0cc2c5d0bd drivers: ram: rv1106: Initial version v1.01 20220325
(https://10.10.10.29/c/rk/u-boot-ddr/+/145841/33)
Update feature:
0cc2c5d0bd drivers: ram: rv1106: Initial version v1.01 20220325
(https://10.10.10.29/c/rk/u-boot-ddr/+/145841/33)
1. Fix wrong calc of ddrconf, which ignore col
2. Do not init UART2 when in UART download
3. Fix wrong of memcpy of NOC
4. Fix wrong of update_dq_tx_skew/update_dq_tx_skew
5. Fix wrong of Disable PVT
6. Enable 2T of PHY_REG 0x1c
7. Return error if changing freq fail
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: I4e564b8322623834d8e117efd4dc1387f66fbffa
Build from ATF commit:
edf5c3fbb plat: px30-s:workaround LP3 can not open cs1 odt in wr train
Update feature:
edf5c3fbb plat: px30-s:workaround LP3 can not open cs1 odt in wr train
05922004b plat: px30-s: suspend: remove ddr_sr_fix_clk_phase() func
c088d3cc9 plat: px30-s: dram: remove phy dfi low power set
aa70ad066 plat: px30: don't init stimer1 if stimer1 is enabled
2877a2c9e plat: px30: support vdd_log off in suspend
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: I0436f3141234820fd31f959f122b1db1cd60d746
Build from ATF commit:
edf5c3fbb plat: px30-s:workaround LP3 can not open cs1 odt in wr train
Update feature:
edf5c3fbb plat: px30-s:workaround LP3 can not open cs1 odt in wr train
05922004b plat: px30-s: suspend: remove ddr_sr_fix_clk_phase() func
c088d3cc9 plat: px30-s: dram: remove phy dfi low power set
aa70ad066 plat: px30: don't init stimer1 if stimer1 is enabled
2877a2c9e plat: px30: support vdd_log off in suspend
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: I6db79ea74891ee56c1f886eeb749c7b4ad308aad
Build from ATF commit:
6a656152a plat: rk3588: save/restore all GICR in suspend
update feature:
6a656152a plat: rk3588: save/restore all GICR in suspend
9ae9e1a3f plat: rk3588: hdmirx: Speed up stopping CPUs
0b9f28efc plat: rockchip: rk3588: Add HDMIRX_HDMI interrupt handler
b604a56ff rockchip: support stop_cpu_fast function
021f3e1d6 plat: rk3588: don't flash cache in stop cpu
93e449183 plat: rk3588: enable EHF
302a312d3 plat: rk3588: mask all irqs before entry into opteed
fc6a6b092 rockchip: plat_pm: add functions for cpu on/suspend resume
0c6866c6d plat: rk3588: support EHF and SDEI
ab808d19f plat: rockchip: support config a fiq
c0152bd35 opteed: Mask non-secure interrupts if the cpus will be off
Change-Id: I7e37c17087a783ea8ab22bb598d5b36c0eef597c
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Build from OPTEE commit in develop-next branch:
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
Update features:
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
b61fa300d scripts: commit_bin: intercept the first 8 characters for LAST_CM
91c4147e7 pta: crypto_service: change some return code to be accurate
d40f7e8a8 drivers: crypto: clk: rv1126: fix the clock enablement logic
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: I2ec32c7094a57f8d7913eff935e4172abeac634f
Build from OPTEE commit in develop-next branch:
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
Update features:
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
b61fa300d scripts: commit_bin: intercept the first 8 characters for LAST_CM
91c4147e7 pta: crypto_service: change some return code to be accurate
3167e3733 drivers: rockchip: hal_crypto: mask lockstep interrupt
3f0f0b052 pta: support check oem otp key is written
48b7c13e2 pta: uboot_storedata_otp: modify parameter check
65daed964 pta: crypto_service: support oem otp key phys cipher
f5add58be core: TEE_GenerateKey support RSA key e = 3
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: Ia5c0776c1f207814a19095bfa5fda1f1f369902d
Build from OPTEE commit in develop-next branch:
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
Update features:
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
b61fa300d scripts: commit_bin: intercept the first 8 characters for LAST_CM
8e053a881 rockchip: remove duplicate definitions for toybrick seed
3f0f0b052 pta: support check oem otp key is written
9af9076b0 rockchip: sys_ctrl: move sys ctrl code to common/ dir
48b7c13e2 pta: uboot_storedata_otp: modify parameter check
65daed964 pta: crypto_service: support oem otp key phys cipher
60973cf4d drivers: crypto: hal: add crypto calc with phys addr
f5add58be core: TEE_GenerateKey support RSA key e = 3
af506d32e ta verify: close default key for sign ta
b05135511 pta: rk_os_service: support R&W oem hardware read otp
50cc53fd1 pta: support R&W oem non-secure otp
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: I738d31d3b329a0f6259d2546856d0599fd1e8089
Build from OPTEE commit in develop-next branch:
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
Update features:
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
b61fa300d scripts: commit_bin: intercept the first 8 characters for LAST_CM
8e053a881 rockchip: remove duplicate definitions for toybrick seed
91c4147e7 pta: crypto_service: change some return code to be accurate
3167e3733 drivers: rockchip: hal_crypto: mask lockstep interrupt
3f0f0b052 pta: support check oem otp key is written
9af9076b0 rockchip: sys_ctrl: move sys ctrl code to common/ dir
48b7c13e2 pta: uboot_storedata_otp: modify parameter check
65daed964 pta: crypto_service: support oem otp key phys cipher
7a0581630 scripts: commit_bin: support more platforms
f5add58be core: TEE_GenerateKey support RSA key e = 3
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: Icafc92b96494b0005a9663578b240b817c5a2bac
Build from OPTEE commit in develop-next branch:
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
Update features:
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
b61fa300d scripts: commit_bin: intercept the first 8 characters for LAST_CM
8e053a881 rockchip: remove duplicate definitions for toybrick seed
91c4147e7 pta: crypto_service: change some return code to be accurate
3167e3733 drivers: rockchip: hal_crypto: mask lockstep interrupt
3f0f0b052 pta: support check oem otp key is written
9af9076b0 rockchip: sys_ctrl: move sys ctrl code to common/ dir
48b7c13e2 pta: uboot_storedata_otp: modify parameter check
65daed964 pta: crypto_service: support oem otp key phys cipher
f5add58be core: TEE_GenerateKey support RSA key e = 3
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: I3f52db2bbfe52310a8798607f30da904ed96ebb7
Build from OPTEE commit in develop-next branch:
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
Update features:
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
b61fa300d scripts: commit_bin: intercept the first 8 characters for LAST_CM
91c4147e7 pta: crypto_service: change some return code to be accurate
d40f7e8a8 drivers: crypto: clk: rv1126: fix the clock enablement logic
3167e3733 drivers: rockchip: hal_crypto: mask lockstep interrupt
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: I07fc6e96c654f16c7ade1fed6dd513d86a0f52f1
from commit:
rk_boot_all: e48799: src: spinor: Support 4KB erase aligned
update feature:
Support spinor 4KB erase aligned
Change-Id: Id0fc2751744a7ff1555e919623bc5b57cb650120
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from OPTEE commit in develop-next branch:
7ef2a818a5 rk3588: otp: set life cycle to provisioned when writing otp key3
Update features:
7ef2a818a5 rk3588: otp: set life cycle to provisioned when writing otp key3
91c4147e75 pta: crypto_service: change some return code to be accurate
3167e37331 drivers: rockchip: hal_crypto: mask lockstep interrupt
911282ad2b plat-rockchip: rk3588: add for init HDCP key by keylad
Signed-off-by: xb.wang <xb.wang@rock-chips.com>
Change-Id: Ieab9c39458c1986ccd0cf8633098f76dc43a4b7b
from commit:
f04a3d: platform: rk3588: pmu os reg change to pmu0.
update feature:
Support spiflash.
Change-Id: I396e408307061c059c32292c3264c35faf6169f6
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from ATF commit:
b5f843fe1 plat: rockchip: rk3588: Don't change clock source to gpll when use pvtpll
update feature:
b5f843fe1 plat: rockchip: rk3588: Don't change clock source to gpll when use pvtpll
3c0a51aa4 plat: rockchip: rk3588: scmi: Add pvtpll config for cpul and dsu
5cc577ea0 plat: rockchip: rk3588: Add support set intermediate rate for npu
a029dd681 plat: rockchip: rk3588: Add support set intermediate rate for gpu
fdaa54cbb plat: rockchip: rk3588: Add support set intermediate rate for cpub
90c6c51f7 plat: rockchip: rk3588: Set gpll source clock div to 0
5ac4bc169 plat: rk3588: support vpu reset
00ba5738d plat: rk3588: support stop cpu
Change-Id: I3cbf062958c3a78526de5a4cf6df4b94e5b5b9a3
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
from commit:
rk_boot_all: c7de69a673: rk3326s: add usb phy tuning
update feature:
support rk3326s.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Icc5fd6153df1f18d02a58b6f0862fb2c2b457918
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from OPTEE commit:
c1514b9e rockchip: rv1126: fastboot: update mmu map table
update feature:
c1514b9e rockchip: rv1126: fastboot: update mmu map table
3ff3b774 rv1126: fix build error without ta
bea79573
700bd12a
40f5fcb2 pta: uboot_storedata: check the value of size when read head
cef03957 otp_support: add func to get ta encryption key
994a45d4 BACKPORT: core: add framework to load REE-FS encrypted TAs
1276ad6e pta: add support for write TA encryption key
2f186b1c core: supply hash length for salt length in rockchip and oem verify
c8e0eeb3 core: arm: support Thumb entry point
416c89b5 rockchip: sip: add share mem page type define
61053b11 rv1126: monitor: don't panic if cpu_feature err
b500cf9c rv1126: monitor: motify some debug code
a53a7d99 rv1126: only register fiq_cpu_stop_handler one time
cab1372b plat-rockchip: only register fiq_debugger_irq_handler one time
9c3b5fd9 plat-rockchip: map TEE_PLAT_SHMEM as MEM_AREA_RAM_NSEC
8cd72983 rv1126: fix macro RG_MAP_SECURE
ef89b5c2 rockchip: fix err of parsing ddr_parameter
2c6573a7 rockchip: rv1126: fix error of parenthesis matching in sgrf_init
1e75c939 plat-rockchip: fiq-debugger: adjust the usage of fiq_debugger.tgt_cpu
9f935616 pta: unnecessary to free share memory when close session
7fcbc47e plat-rockchip: fix CFG_RK_STATIC_MEM_PARAM define err
d9140b1b rv1126: conf.mk: use atags to pass parameter
715df903 plat-rockchip: conf.mk: enable CFG_RK_RPMB_NO_DIRF_HASH
59d68db8 rv1126: modify otp size for oem
10ff881f scripts: modify supported platforms
ee120571 rv1126: conf.mk: enable CFG_VENDOR_PROPS
e4d16707 plat-rockchip: vendor_props: add needed head files
5da82304 rv1126: support get seed for vendor props
1e6e6afa rv1126: pta: support write toybrick seed
36e572e8 rv1126: pta: support R&W attribute hash and vbootkey hash
867c532c plat-rockchip: rv1126: dmc: add support lp4x
8fc0f55b plat-rockchip: rv1126: dmc: fix MR14 setting err for lp4
4a1a9c4d plat-rockchip: common: dram: add LP4x support
23f06a39 rockchip: rv1126: don't close usb powerdomain when suspend
36d1043e plat-rockchip: rv1126: dmc: remove dsmpd when pll setting
44c0c0f1 rockchip: rv1126: support suspend from uboot
6ae5d629
380b79bf
e3cdf903 rv1126: otp: oem ns-otp prog mask value rely on ns-otp[504-511]
d4636cc1 rv1126: pta: add support for R&W oem OTP
Change-Id: Ie6156f1cc81fc3cea0efe17e7e9dfcecf262b061
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
