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Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh

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Two trivial fixes for 2026.04 , one fix for possible NULL pointer
dereference which was not triggered thus far but got detected on Gen5
RSIP, and one basic disablement of SCIF1 in DT to which a driver was
never bound. But it would be nice to have them corrected.
This commit is contained in:
Tom Rini
2026-04-05 09:10:21 -06:00
parent 214aababe0 d8bd70741f
commit 47e064f131
2 changed files with 3 additions and 3 deletions
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2
arch/arm/dts/r8a78000.dtsi
View File

@@ -763,7 +763,7 @@
interrupts = <GIC_SPI 4075 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
status = "okay";
status = "disabled";
};
scif3: serial@c0708000 {

4
drivers/net/rswitch.c
View File

@@ -482,7 +482,7 @@ static int rswitch_mii_read_c45(struct mii_dev *miidev, int phyad, int devad, in
/* Access PHY register */
if (devad != MDIO_DEVAD_NONE) /* Definitelly C45 */
val = rswitch_mii_access_c45(etha_mii, true, phyad, devad, regad, 0);
else if (etha->phydev->is_c45) /* C22 access to C45 PHY */
else if (etha->phydev && etha->phydev->is_c45) /* C22 access to C45 PHY */
val = rswitch_mii_access_c45(etha_mii, true, phyad, 1, regad, 0);
else
val = rswitch_mii_access_c22(etha_mii, true, phyad, regad, 0);
@@ -516,7 +516,7 @@ int rswitch_mii_write_c45(struct mii_dev *miidev, int phyad, int devad, int rega
/* Access PHY register */
if (devad != MDIO_DEVAD_NONE) /* Definitelly C45 */
rswitch_mii_access_c45(etha_mii, false, phyad, devad, regad, data);
else if (etha->phydev->is_c45) /* C22 access to C45 PHY */
else if (etha->phydev && etha->phydev->is_c45) /* C22 access to C45 PHY */
rswitch_mii_access_c45(etha_mii, false, phyad, 1, regad, data);
else
rswitch_mii_access_c22(etha_mii, false, phyad, regad, data);