* Patches by Udi Finkelstein, 2 June 2003:

- Added support for custom keyboards, initialized by defining a
    board-specific drv_keyboard_init as well as defining CONFIG_KEYBOARD .
  - Added support for the RBC823 board.
  - cpu/mpc8xx/lcd.c now automatically calculates the
    Horizontal Pixel Count field.

* Fix alignment problem in BOOTP (dhcp_leasetime option)
  [pointed out by Nicolas Lacressonni�re, 2 Jun 2003]

* Patch by Mark Rakes, 14 May 2003:
  add support for Intel e1000 gig cards.

* Patch by Nye Liu, 3 Jun 2003:
  fix critical typo in MAMR definition (include/mpc8xx.h)

* Fix requirement to align U-Boot image on 16 kB boundaries on PPC.

* Patch by Klaus Heydeck, 2 Jun 2003
  Minor changes for KUP4K configuration

CHANGELOG

@@ -2,6 +2,76 @@
 Changes since U-Boot 0.3.1:
 ======================================================================
 
+* Patches by Udi Finkelstein, 2 June 2003:
+  - Added support for custom keyboards, initialized by defining a
+    board-specific drv_keyboard_init as well as defining CONFIG_KEYBOARD .
+  - Added support for the RBC823 board.
+  - cpu/mpc8xx/lcd.c now automatically calculates the
+    Horizontal Pixel Count field.
+
+* Fix alignment problem in BOOTP (dhcp_leasetime option)
+  [pointed out by Nicolas Lacressonnière, 2 Jun 2003]
+
+* Patch by Mark Rakes, 14 May 2003:
+  add support for Intel e1000 gig cards.
+
+* Patch by Nye Liu, 3 Jun 2003:
+  fix critical typo in MAMR definition (include/mpc8xx.h)
+
+* Fix requirement to align U-Boot image on 16 kB boundaries on PPC.
+
+* Patch by Klaus Heydeck, 2 Jun 2003
+  Minor changes for KUP4K configuration
+
+* Patch by Marc Singer, 29 May 2003:
+  Fixed rarp boot method for IA32 and other little-endian CPUs.
+
+* Patch by Marc Singer, 28 May 2003:
+  Added port I/O commands.
+
+* Patch by Matthew McClintock, 28 May 2003
+  - cpu/mpc824x/start.S: fix relocation code when booting from RAM
+  - minor patches for utx8245
+
+* Patch by Daniel Engström, 28 May 2003:
+  x86 update
+
+* Patch by Dave Ellis, 9 May 2003 + 27 May 2003:
+  add nand flash support to SXNI855T configuration
+  fix/extend nand flash support:
+  - fix 'nand erase' command so does not erase bad blocks
+  - fix 'nand write' command so does not write to bad blocks
+  - fix nand_probe() so handles no flash detected properly
+  - add doc/README.nand
+  - add .jffs2 and .oob options to nand read/write
+  - add 'nand bad' command to list bad blocks
+  - add 'clean' option to 'nand erase' to write JFFS2 clean markers
+  - make NAND read/write faster
+
+* Patch by Rune Torgersen, 23 May 2003:
+  Update for MPC8266ADS board
+
+* Get (mostly) rid of CFG_MONITOR_LEN definition; compute real length
+  instead CFG_MONITOR_LEN is now only used to determine  _at_compile_
+  _time_  (!) if the environment is embedded within the U-Boot image,
+  or in a separate flash sector.
+
+* Cleanup CFG_DER #defines in config files (wd maintained only)
+
+* Fix data abort exception handling for arm920t CPU
+
+* Fix alignment problems with flash driver for TRAB board
+
+* Patch by Donald White, 21 May 2003:
+  fix calculation of base address in pci_hose_config_device()
+
+* Fix bug in command line parsing: "cmd1;cmd2" is supposed to always
+  execute "cmd2", even if "cmd1" fails. Note that this is different
+  to "run var1 var2" where the contents of "var2" will NOT be
+  executed when a command in "var1" fails.
+
+* Add zero-copy ramdisk support (requires corresponding kernel support!)
+
 * Patch by Kyle Harris, 20 May 2003:
   In preparation for an ixp port, rename cpu/xscale and arch-xscale
   into cpu/pxa and arch-pxa.

MAKEALL

@@ -32,11 +32,11 @@ LIST_8xx="	\
 	IVMS8		IVMS8_128	IVMS8_256	KUP4K           \
 	LANTEC	        lwmon   	MBX		MBX860T		\
 	MHPC		MVS1		NETVIA		NX823		\
-	pcu_e		R360MPI		RPXClassic	RPXlite		\
-	RRvision	SM850		SPD823TS	svm_sc8xx	\
-	SXNI855T	TOP860		TQM823L		TQM823L_LCD	\
-	TQM850L		TQM855L		TQM860L		TTTech		\
-	v37								\
+	pcu_e		R360MPI		RBC823		RPXClassic	\
+	RPXlite		RRvision	SM850		SPD823TS	\
+	svm_sc8xx	SXNI855T	TOP860		TQM823L		\
+	TQM823L_LCD	TQM850L		TQM855L		TQM860L		\
+	TTTech		v37						\
 "
 
 #########################################################################
@@ -129,6 +129,15 @@ LIST_mips5kc="purple"
 
 LIST_mips="${LIST_mips4kc} ${LIST_mips5kc}"
 
+#########################################################################
+## i386 Systems
+#########################################################################
+
+LIST_I486="sc520_cdp sc520_spunk sc520_spunk_rel"
+
+LIST_x86="${LIST_I486}"
+
+#-----------------------------------------------------------------------
 
 #----- for now, just run PPC by default -----
 [ $# = 0 ] && set $LIST_ppc
@@ -150,7 +159,7 @@ build_target() {
 for arg in $@
 do
 	case "$arg" in
-	5xx|8xx|824x|8260|4xx|7xx|74xx|SA|ARM7|ARM9|ppc|arm|pxa|mips)
+	5xx|8xx|824x|8260|4xx|7xx|74xx|SA|ARM7|ARM9|ppc|arm|pxa|mips|I486|x86)
 			for target in `eval echo '$LIST_'${arg}`
 			do
 				build_target ${target}

Makefile

@@ -60,7 +60,11 @@ ifeq ($(ARCH),arm)
 CROSS_COMPILE = arm-linux-
 endif
 ifeq ($(ARCH),i386)
-#CROSS_COMPILE = i386-elf-
+ifeq ($(HOSTARCH),i386)
+CROSS_COMPILE =
+else
+CROSS_COMPILE = i386-linux-
+endif
 endif
 ifeq ($(ARCH),mips)
 CROSS_COMPILE = mips_4KC-
@@ -310,6 +314,9 @@ pcu_e_config:		unconfig
 R360MPI_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx r360mpi
 
+RBC823_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc8xx rbc823
+
 RPXClassic_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx RPXClassic
 
@@ -729,6 +736,12 @@ wepep250_config	:	unconfig
 sc520_cdp_config	:	unconfig
 	@./mkconfig $(@:_config=) i386 i386 sc520_cdp
 
+sc520_spunk_config	:	unconfig
+	@./mkconfig $(@:_config=) i386 i386 sc520_spunk
+
+sc520_spunk_rel_config	:	unconfig
+	@./mkconfig $(@:_config=) i386 i386 sc520_spunk
+
 #========================================================================
 # MIPS
 #========================================================================
@@ -752,7 +765,8 @@ clean:
 		| xargs rm -f
 	rm -f examples/hello_world examples/timer \
 	      examples/eepro100_eeprom examples/sched \
-	      examples/mem_to_mem_idma2intr
+	      examples/mem_to_mem_idma2intr examples/82559_eeprom
+
 	rm -f tools/img2srec tools/mkimage tools/envcrc tools/gen_eth_addr
 	rm -f tools/easylogo/easylogo tools/bmp_logo
 	rm -f tools/gdb/astest tools/gdb/gdbcont tools/gdb/gdbsend

README

@@ -344,7 +344,7 @@ The following options need to be configured:
 		CONFIG_IAD210,     CONFIG_RPXlite,    CONFIG_sbc8260,
 		CONFIG_EBONY,      CONFIG_sacsng,     CONFIG_FPS860L,
 		CONFIG_V37,        CONFIG_ELPT860,    CONFIG_CMI,
-		CONFIG_NETVIA
+		CONFIG_NETVIA,     CONFIG_RBC823
 
 		ARM based boards:
 		-----------------
@@ -688,6 +688,9 @@ The following options need to be configured:
 		CFG_SCSI_SYM53C8XX_CCF to fix clock timing (80Mhz)
 
 - NETWORK Support (PCI):
+		CONFIG_E1000
+		Support for Intel 8254x gigabit chips.
+		
 		CONFIG_EEPRO100
 		Support for Intel 82557/82559/82559ER chips.
 		Optional CONFIG_EEPRO100_SROM_WRITE enables eeprom
@@ -766,6 +769,13 @@ The following options need to be configured:
 		and 16bpp modes defined by CONFIG_VIDEO_SED13806_8BPP
 		or CONFIG_VIDEO_SED13806_16BPP
 
+- Keyboard Support:
+                CONFIG_KEYBOARD
+
+                Define this to enable a custom keyboard support.
+                This simply calls drv_keyboard_init() which must be
+                defined in your board-specific files.
+                The only board using this so far is RBC823.
 
 - LCD Support:	CONFIG_LCD
 
@@ -1183,13 +1193,13 @@ The following options need to be configured:
 
 	Note:
 
-		In the current implementation, the local variables
-		space and global environment variables space are
-		separated. Local variables are those you define by
-		simply typing like `name=value'. To access a local
-		variable later on, you have write `$name' or
-		`${name}'; variable directly by typing say `$name' at
-		the command prompt.
+                In the current implementation, the local variables
+                space and global environment variables space are
+                separated. Local variables are those you define by
+                simply typing `name=value'. To access a local
+                variable later on, you have write `$name' or
+                `${name}'; to execute the contents of a variable
+                directly type `$name' at the command prompt.
 
 		Global environment variables are those you use
 		setenv/printenv to work with. To run a command stored
@@ -1389,7 +1399,10 @@ Configuration Settings:
 		CFG_FLASH_BASE when booting from flash.
 
 - CFG_MONITOR_LEN:
-		Size of memory reserved for monitor code
+                Size of memory reserved for monitor code, used to
+                determine _at_compile_time_ (!) if the environment is
+                embedded within the U-Boot image, or in a separate
+                flash sector.
 
 - CFG_MALLOC_LEN:
 		Size of DRAM reserved for malloc() use.
@@ -1988,6 +2001,14 @@ Some configuration options can be set using Environment Variables:
 
 		  setenv initrd_high 00c00000
 
+                  If you set initrd_high to 0xFFFFFFFF, this is an
+                  indication to U-Boot that all addresses are legal
+                  for the Linux kernel, including addresses in flash
+                  memory. In this case U-Boot will NOT COPY the
+                  ramdisk at all. This may be useful to reduce the
+                  boot time on your system, but requires that this
+                  feature is supported by your Linux kernel.
+
   ipaddr	- IP address; needed for tftpboot command
 
   loadaddr	- Default load address for commands like "bootp",
@@ -2040,6 +2061,48 @@ Please note that changes to some configuration parameters may take
 only effect after the next boot (yes, that's just like Windoze :-).
 
 
+Command Line Parsing:
+=====================
+
+There are two different command line parsers available  with  U-Boot:
+the old "simple" one, and the much more pwerful "hush" shell:
+
+Old, simple command line parser:
+--------------------------------
+
+- supports environment variables (through setenv / saveenv commands)
+- several commands on one line, separated by ';'
+- variable substitution using "... $(name) ..." syntax
+- special characters ('$', ';') can be escaped by prefixing with '\',
+  for example:
+	setenv bootcmd bootm \$(address)
+- You can also escape text by enclosing in single apostrophes, for example:
+	setenv addip 'setenv bootargs $bootargs ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off'
+
+Hush shell:
+-----------
+
+- similar to Bourne shell, with control structures like
+  if...then...else...fi, for...do...done; while...do...done,
+  until...do...done, ...
+- supports environment ("global") variables (through setenv / saveenv
+  commands) and local shell variables (through standard shell syntax
+  "name=value"); only environment variables can be used with "run"
+  command
+
+General rules:
+--------------
+
+(1) If a command line (or an environment variable executed by a "run"
+    command) contains several commands separated by semicolon, and
+    one of these commands fails, then the remaining commands will be
+    executed anyway.
+
+(2) If you execute several variables with one call to run (i. e.
+    calling run with a list af variables as arguments), any failing
+    command will cause "run" to terminate, i. e. the remaining
+    variables are not executed.
+
 Note for Redundant Ethernet Interfaces:
 =======================================
 
@@ -2555,9 +2618,9 @@ Minicom warning:
 ================
 
 Over time, many people have reported problems when trying to used the
-"minicom" terminal emulation program  for  serial  download.  I  (wd)
-consider  minicom  to  be  broken, and recommend not to use it. Under
-Unix, I recommend  to  use  CKermit  for  general  purpose  use  (and
+"minicom" terminal emulation program for serial download. I (wd)
+consider minicom to be broken, and recommend not to use it. Under
+Unix, I recommend to use C-Kermit for general purpose use (and
 especially for kermit binary protocol download ("loadb" command), and
 use "cu" for S-Record download ("loads" command).
 

board/LEOX/elpt860/flash.c

@@ -118,7 +118,7 @@ flash_init (void)
   /* monitor protection ON by default */
   flash_protect (FLAG_PROTECT_SET,
 		 CFG_MONITOR_BASE,
-		 CFG_MONITOR_BASE + CFG_MONITOR_LEN-1,
+		 CFG_MONITOR_BASE + monitor_flash_len-1,
 		 &flash_info[0]);
 #endif
   

board/MAI/AmigaOneG3SE/flash_new.c

@@ -120,7 +120,7 @@ unsigned long flash_init (void)
 		/* monitor protection ON by default */
 		flash_protect(FLAG_PROTECT_SET,
 			      CFG_MONITOR_BASE,
-			      CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+			      CFG_MONITOR_BASE + monitor_flash_len - 1,
 			      &flash_info[0]);
 #endif
 

board/MAI/bios_emulator/scitech/src/v86bios/command.c

@@ -36,6 +36,3 @@ getline(char *buf,int *num,int max_num)
     line_pointer = line_pointer + *num;
     len = len - *num;
 }
-
-
-

board/RPXClassic/flash.c

@@ -64,7 +64,7 @@ unsigned long flash_init (void)
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
 		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 

board/RPXlite/flash.c

@@ -85,7 +85,7 @@ unsigned long flash_init (void)
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
 		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 

board/RRvision/flash.c

@@ -73,7 +73,7 @@ unsigned long flash_init (void)
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
 		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 

board/atc/flash.c

@@ -91,7 +91,7 @@ unsigned long flash_init (void)
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
 		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
 		      flash_get_info(CFG_MONITOR_BASE));
 #endif
 

board/bmw/flash.c

@@ -219,7 +219,7 @@ flash_init(void)
 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
     flash_protect(FLAG_PROTECT_SET,
 		CFG_MONITOR_BASE,
-		CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+		CFG_MONITOR_BASE + monitor_flash_len - 1,
 		&flash_info[0]);
 #endif
 

board/c2mon/flash.c

@@ -91,7 +91,7 @@ unsigned long flash_init (void)
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
 		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -118,7 +118,7 @@ unsigned long flash_init (void)
 		/* monitor protection ON by default */
 		flash_protect(FLAG_PROTECT_SET,
 			      CFG_MONITOR_BASE,
-			      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+			      CFG_MONITOR_BASE+monitor_flash_len-1,
 			      &flash_info[1]);
 #endif
 

board/cmi/flash.c

@@ -106,7 +106,7 @@ unsigned long flash_init (void)
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
 		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 

board/cogent/flash.c

@@ -323,7 +323,7 @@ flash_init(void)
 #if CFG_MONITOR_BASE == CFG_FLASH_BASE
 	flash_protect(FLAG_PROTECT_SET,
 		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 

board/cpc45/flash.c

@@ -132,12 +132,12 @@ unsigned long flash_init(void)
 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE
     flash_protect(FLAG_PROTECT_SET,
               CFG_MONITOR_BASE,
-              CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+              CFG_MONITOR_BASE + monitor_flash_len - 1,
               &flash_info[1]);
 #else
     flash_protect(FLAG_PROTECT_SET,
               CFG_MONITOR_BASE,
-              CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+              CFG_MONITOR_BASE + monitor_flash_len - 1,
               &flash_info[0]);
 #endif
 #endif

board/cpu86/flash.c

@@ -218,14 +218,14 @@ unsigned long flash_init (void)
 
 		flash_protect  (FLAG_PROTECT_SET,
 				CFG_MONITOR_BASE,
-				CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, &flash_info[1]
+				CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1]
 		);
 	}
 #else
 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
 	flash_protect (FLAG_PROTECT_SET,
 		       CFG_MONITOR_BASE,
-		       CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, &flash_info[0]
+		       CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]
 	);
 #endif
 #endif

board/cradle/flash.c

@@ -73,7 +73,7 @@ ulong flash_init(void)
     */
    flash_protect(FLAG_PROTECT_SET,
                   CFG_FLASH_BASE,
-                  CFG_FLASH_BASE + _armboot_end_data - _armboot_start,
+                  CFG_FLASH_BASE + monitor_flash_len - 1,
                   &flash_info[0]);
 
    flash_protect(FLAG_PROTECT_SET,

board/cray/L1/flash.c

@@ -88,7 +88,7 @@ unsigned long flash_init (void)
 	    /* Monitor protection ON by default */
 	    (void)flash_protect(FLAG_PROTECT_SET,
 				FLASH_BASE0_PRELIM,
-				FLASH_BASE0_PRELIM+CFG_MONITOR_LEN-1,
+				FLASH_BASE0_PRELIM+monitor_flash_len-1,
 				&flash_info[0]);
 #endif
 	    size_b1 = 0 ;

board/csb226/flash.c

@@ -74,7 +74,7 @@ ulong flash_init(void)
 	/* Protect monitor and environment sectors */
 	flash_protect(FLAG_PROTECT_SET,
 			CFG_FLASH_BASE,
-			CFG_FLASH_BASE + _armboot_end_data - _armboot_start,
+			CFG_FLASH_BASE + monitor_flash_len - 1,
 			&flash_info[0]);
 
 	flash_protect(FLAG_PROTECT_SET,

board/cu824/flash.c

@@ -125,12 +125,12 @@ unsigned long flash_init(void)
 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE
     flash_protect(FLAG_PROTECT_SET,
               CFG_MONITOR_BASE,
-              CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+              CFG_MONITOR_BASE + monitor_flash_len - 1,
               &flash_info[1]);
 #else
     flash_protect(FLAG_PROTECT_SET,
               CFG_MONITOR_BASE,
-              CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+              CFG_MONITOR_BASE + monitor_flash_len - 1,
               &flash_info[0]);
 #endif
 #endif

board/dnp1110/flash.c

@@ -84,7 +84,7 @@ unsigned long flash_init (void)
      */
     flash_protect(FLAG_PROTECT_SET,
 		  CFG_FLASH_BASE,
-		  CFG_FLASH_BASE + _armboot_end_data - _armboot_start,
+		  CFG_FLASH_BASE + monitor_flash_len  - 1,
 		  &flash_info[0]);
 
     flash_protect(FLAG_PROTECT_SET,

board/eltec/bab7xx/flash.c

@@ -83,21 +83,21 @@ unsigned long flash_init (void)
     {
         (void)flash_protect(FLAG_PROTECT_SET,
                 FLASH_BASE0_PRELIM,
-                FLASH_BASE0_PRELIM+CFG_MONITOR_LEN-1,
+                FLASH_BASE0_PRELIM+monitor_flash_len-1,
                 &flash_info[0]);
     }
     if (size2 == 512*1024)
     {
         (void)flash_protect(FLAG_PROTECT_SET,
                 FLASH_BASE1_PRELIM,
-                FLASH_BASE1_PRELIM+CFG_MONITOR_LEN-1,
+                FLASH_BASE1_PRELIM+monitor_flash_len-1,
                 &flash_info[1]);
     }
     if (size2 == 4*1024*1024)
     {
         (void)flash_protect(FLAG_PROTECT_SET,
                 CFG_FLASH_BASE,
-                CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+                CFG_FLASH_BASE+monitor_flash_len-1,
                 &flash_info[1]);
     }
 

board/eltec/elppc/flash.c

@@ -83,21 +83,21 @@ unsigned long flash_init (void)
     {
         (void)flash_protect(FLAG_PROTECT_SET,
                 FLASH_BASE0_PRELIM,
-                FLASH_BASE0_PRELIM+CFG_MONITOR_LEN-1,
+                FLASH_BASE0_PRELIM+monitor_flash_len-1,
                 &flash_info[0]);
     }
     if (size2 == 512*1024)
     {
         (void)flash_protect(FLAG_PROTECT_SET,
                 FLASH_BASE1_PRELIM,
-                FLASH_BASE1_PRELIM+CFG_MONITOR_LEN-1,
+                FLASH_BASE1_PRELIM+monitor_flash_len-1,
                 &flash_info[1]);
     }
     if (size2 == 4*1024*1024)
     {
         (void)flash_protect(FLAG_PROTECT_SET,
                 CFG_FLASH_BASE,
-                CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+                CFG_FLASH_BASE+monitor_flash_len-1,
                 &flash_info[1]);
     }
 

board/eltec/mhpc/flash.c

@@ -92,7 +92,7 @@ unsigned long flash_init (void)
 	/* monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
 			    CFG_FLASH_BASE,
-			    CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+			    CFG_FLASH_BASE+monitor_flash_len-1,
 			    &flash_info[0]);
 
 	flash_info[0].size = size_b0;

board/ep7312/flash.c

@@ -61,7 +61,7 @@ ulong flash_init (void)
 	 */
 	flash_protect ( FLAG_PROTECT_SET,
 			CFG_FLASH_BASE,
-			CFG_FLASH_BASE + _armboot_end_data - _armboot_start,
+			CFG_FLASH_BASE + monitor_flash_len - 1,
 			&flash_info[0]);
 
 	flash_protect ( FLAG_PROTECT_SET,

board/ep8260/flash.c

@@ -140,7 +140,7 @@ unsigned long flash_init (void)
 #if CFG_MONITOR_BASE >= CFG_FLASH0_BASE
     flash_protect(FLAG_PROTECT_SET,
 		  CFG_MONITOR_BASE,
-		  CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		  CFG_MONITOR_BASE+monitor_flash_len-1,
 		  &flash_info[0]);
 #endif
 

board/eric/flash.c

@@ -83,13 +83,13 @@ unsigned long flash_init (void)
 	    /* Monitor protection ON by default */
 #if 0	    /* sand: */
 	    (void)flash_protect(FLAG_PROTECT_SET,
-				FLASH_BASE0_PRELIM-CFG_MONITOR_LEN+size_b0,
+				FLASH_BASE0_PRELIM-monitor_flash_len+size_b0,
 				FLASH_BASE0_PRELIM-1+size_b0,
 				&flash_info[0]);
 #else
 	    (void)flash_protect(FLAG_PROTECT_SET,
 		      		CFG_MONITOR_BASE,
-		      		CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      		CFG_MONITOR_BASE+monitor_flash_len-1,
 		      		&flash_info[0]);
 #endif
 	    size_b1 = 0 ;
@@ -132,13 +132,13 @@ unsigned long flash_init (void)
 	    /* monitor protection ON by default */
 #if 0	    /* sand: */
 	    (void)flash_protect(FLAG_PROTECT_SET,
-				FLASH_BASE0_PRELIM-CFG_MONITOR_LEN+size_b0,
+				FLASH_BASE0_PRELIM-monitor_flash_len+size_b0,
 				FLASH_BASE0_PRELIM-1+size_b0,
 				&flash_info[0]);
 #else
 	    (void)flash_protect(FLAG_PROTECT_SET,
 		      		CFG_MONITOR_BASE,
-		      		CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      		CFG_MONITOR_BASE+monitor_flash_len-1,
 		      		&flash_info[0]);
 #endif
 
@@ -150,12 +150,12 @@ unsigned long flash_init (void)
 
 	      /* monitor protection ON by default */
 	      (void)flash_protect(FLAG_PROTECT_SET,
-				  base_b1+size_b1-CFG_MONITOR_LEN,
+				  base_b1+size_b1-monitor_flash_len,
 				  base_b1+size_b1-1,
 				  &flash_info[1]);
 	      /* monitor protection OFF by default (one is enough) */
 	      (void)flash_protect(FLAG_PROTECT_CLEAR,
-				  base_b0+size_b0-CFG_MONITOR_LEN,
+				  base_b0+size_b0-monitor_flash_len,
 				  base_b0+size_b0-1,
 				  &flash_info[0]);
 	    } else {

board/esd/adciop/flash.c

@@ -80,7 +80,7 @@ unsigned long flash_init (void)
 
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      FLASH_BASE0_PRELIM+size_b0-CFG_MONITOR_LEN,
+		      FLASH_BASE0_PRELIM+size_b0-monitor_flash_len,
 		      FLASH_BASE0_PRELIM+size_b0-1,
 		      &flash_info[0]);
 
@@ -93,12 +93,12 @@ unsigned long flash_init (void)
 
 		/* monitor protection ON by default */
 		flash_protect(FLAG_PROTECT_SET,
-			      FLASH_BASE0_PRELIM+size_b0+size_b1-CFG_MONITOR_LEN,
+			      FLASH_BASE0_PRELIM+size_b0+size_b1-monitor_flash_len,
 			      FLASH_BASE0_PRELIM+size_b0+size_b1-1,
 			      &flash_info[1]);
                 /* monitor protection OFF by default (one is enough) */
                 flash_protect(FLAG_PROTECT_CLEAR,
-			      FLASH_BASE0_PRELIM+size_b0-CFG_MONITOR_LEN,
+			      FLASH_BASE0_PRELIM+size_b0-monitor_flash_len,
 			      FLASH_BASE0_PRELIM+size_b0-1,
 			      &flash_info[0]);
 	} else {

board/esd/ar405/flash.c

@@ -94,7 +94,7 @@ unsigned long flash_init (void)
 
 	/* monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
-			    base_b0+size_b0-CFG_MONITOR_LEN,
+			    base_b0+size_b0-monitor_flash_len,
 			    base_b0+size_b0-1,
 			    &flash_info[0]);
 
@@ -106,12 +106,12 @@ unsigned long flash_init (void)
 
 		/* monitor protection ON by default */
 		(void)flash_protect(FLAG_PROTECT_SET,
-				    base_b1+size_b1-CFG_MONITOR_LEN,
+				    base_b1+size_b1-monitor_flash_len,
 				    base_b1+size_b1-1,
 				    &flash_info[1]);
                 /* monitor protection OFF by default (one is enough) */
                 (void)flash_protect(FLAG_PROTECT_CLEAR,
-                                    base_b0+size_b0-CFG_MONITOR_LEN,
+                                    base_b0+size_b0-monitor_flash_len,
                                     base_b0+size_b0-1,
                                     &flash_info[0]);
 	} else {

board/esd/canbt/flash.c

@@ -74,7 +74,7 @@ unsigned long flash_init (void)
 
         /* Monitor protection ON by default */
         (void)flash_protect(FLAG_PROTECT_SET,
-                            -CFG_MONITOR_LEN,
+                            -monitor_flash_len,
                             0xffffffff,
                             &flash_info[0]);
 

board/esd/cpci405/flash.c

@@ -125,7 +125,7 @@ unsigned long flash_init (void)
 
 	/* monitor protection ON by default */
 	flash_protect (FLAG_PROTECT_SET,
-			base_b0 + size_b0 - CFG_MONITOR_LEN,
+			base_b0 + size_b0 - monitor_flash_len,
 			base_b0 + size_b0 - 1, &flash_info[0]);
 
 	if (size_b1) {
@@ -136,11 +136,11 @@ unsigned long flash_init (void)
 
 		/* monitor protection ON by default */
 		flash_protect (FLAG_PROTECT_SET,
-				base_b1 + size_b1 - CFG_MONITOR_LEN,
+				base_b1 + size_b1 - monitor_flash_len,
 				base_b1 + size_b1 - 1, &flash_info[1]);
 		/* monitor protection OFF by default (one is enough) */
 		flash_protect (FLAG_PROTECT_CLEAR,
-				base_b0 + size_b0 - CFG_MONITOR_LEN,
+				base_b0 + size_b0 - monitor_flash_len,
 				base_b0 + size_b0 - 1, &flash_info[0]);
 	} else {
 		flash_info[1].flash_id = FLASH_UNKNOWN;

board/esd/cpci440/strataflash.c

@@ -200,7 +200,7 @@ unsigned long flash_init (void)
 #if 0 /* test-only */
 	/* Monitor protection ON by default */
 #if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
-	for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+CFG_MONITOR_LEN-1; i++)
+	for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+monitor_flash_len-1; i++)
 		(void)flash_real_protect(&flash_info[0], i, 1);
 #endif
 #endif

board/esd/cpciiser4/flash.c

@@ -74,7 +74,7 @@ unsigned long flash_init (void)
 
         /* Monitor protection ON by default */
         (void)flash_protect(FLAG_PROTECT_SET,
-                            -CFG_MONITOR_LEN,
+                            -monitor_flash_len,
                             0xffffffff,
                             &flash_info[0]);
 

board/esd/dasa_sim/flash.c

@@ -67,7 +67,7 @@ unsigned long flash_init (void)
 
         /* Monitor protection ON by default */
         (void)flash_protect(FLAG_PROTECT_SET,
-                            -CFG_MONITOR_LEN,
+                            -monitor_flash_len,
                             0xffffffff,
                             &flash_info[0]);
 

board/esd/du405/flash.c

@@ -94,7 +94,7 @@ unsigned long flash_init (void)
 
 	/* monitor protection ON by default */
 	flash_protect (FLAG_PROTECT_SET,
-			base_b0 + size_b0 - CFG_MONITOR_LEN,
+			base_b0 + size_b0 - monitor_flash_len,
 			base_b0 + size_b0 - 1, &flash_info[0]);
 
 	if (size_b1) {
@@ -105,11 +105,11 @@ unsigned long flash_init (void)
 
 		/* monitor protection ON by default */
 		flash_protect (FLAG_PROTECT_SET,
-				base_b1 + size_b1 - CFG_MONITOR_LEN,
+				base_b1 + size_b1 - monitor_flash_len,
 				base_b1 + size_b1 - 1, &flash_info[1]);
 		/* monitor protection OFF by default (one is enough) */
 		flash_protect (FLAG_PROTECT_CLEAR,
-				base_b0 + size_b0 - CFG_MONITOR_LEN,
+				base_b0 + size_b0 - monitor_flash_len,
 				base_b0 + size_b0 - 1, &flash_info[0]);
 	} else {
 		flash_info[1].flash_id = FLASH_UNKNOWN;

board/esd/ocrtc/flash.c

@@ -127,7 +127,7 @@ unsigned long flash_init (void)
 
 	/* monitor protection ON by default */
 	flash_protect (FLAG_PROTECT_SET,
-			base_b0 + size_b0 - CFG_MONITOR_LEN,
+			base_b0 + size_b0 - monitor_flash_len,
 			base_b0 + size_b0 - 1, &flash_info[0]);
 
 	if (size_b1) {
@@ -138,11 +138,11 @@ unsigned long flash_init (void)
 
 		/* monitor protection ON by default */
 		flash_protect (FLAG_PROTECT_SET,
-				base_b1 + size_b1 - CFG_MONITOR_LEN,
+				base_b1 + size_b1 - monitor_flash_len,
 				base_b1 + size_b1 - 1, &flash_info[1]);
 		/* monitor protection OFF by default (one is enough) */
 		flash_protect (FLAG_PROTECT_CLEAR,
-				base_b0 + size_b0 - CFG_MONITOR_LEN,
+				base_b0 + size_b0 - monitor_flash_len,
 				base_b0 + size_b0 - 1, &flash_info[0]);
 	} else {
 		flash_info[1].flash_id = FLASH_UNKNOWN;

board/esd/pci405/flash.c

@@ -91,7 +91,7 @@ unsigned long flash_init (void)
 
         /* Monitor protection ON by default */
         (void)flash_protect(FLAG_PROTECT_SET,
-                            -CFG_MONITOR_LEN,
+                            -monitor_flash_len,
                             0xffffffff,
                             &flash_info[0]);
 

board/esteem192e/flash.c

@@ -104,7 +104,7 @@ unsigned long flash_init (void)
 	/* monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
 			    CFG_MONITOR_BASE,
-			    CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+			    CFG_MONITOR_BASE+monitor_flash_len-1,
 			    &flash_info[0]);
 #endif
 
@@ -124,7 +124,7 @@ unsigned long flash_init (void)
 		/* monitor protection ON by default */
 		(void)flash_protect(FLAG_PROTECT_SET,
 				    CFG_MONITOR_BASE,
-				    CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+				    CFG_MONITOR_BASE+monitor_flash_len-1,
 				    &flash_info[1]);
 #endif
 	} else {

board/etx094/flash.c

@@ -91,7 +91,7 @@ unsigned long flash_init (void)
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
 		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -115,7 +115,7 @@ unsigned long flash_init (void)
 		/* monitor protection ON by default */
 		flash_protect(FLAG_PROTECT_SET,
 			      CFG_MONITOR_BASE,
-			      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+			      CFG_MONITOR_BASE+monitor_flash_len-1,
 			      &flash_info[1]);
 #endif
 	} else {

board/fads/flash.c

@@ -112,7 +112,7 @@ unsigned long flash_init (void)
 		/* monitor protection ON by default */
 		flash_protect(FLAG_PROTECT_SET,
 			      CFG_MONITOR_BASE,
-			      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+			      CFG_MONITOR_BASE+monitor_flash_len-1,
 			      &flash_info[i]);
 #endif
 

board/flagadm/flash.c

@@ -77,7 +77,7 @@ unsigned long flash_init (void)
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
 		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 

board/gen860t/flash.c

@@ -157,7 +157,7 @@ flash_init (void)
 	 */
 	flash_protect(FLAG_PROTECT_SET,
 		      	  CFG_MONITOR_BASE,
-		      	  CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+		      	  CFG_MONITOR_BASE + monitor_flash_len - 1,
 		      	  &flash_info[0]);
 #endif
 

board/genietv/flash.c

@@ -55,7 +55,7 @@ unsigned long flash_init (void)
 	/* Monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
 		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 

board/gth/flash.c

@@ -102,7 +102,7 @@ unsigned long flash_init (void)
 	  /* monitor protection ON by default */
 	  (void)flash_protect(FLAG_PROTECT_SET,
 			    CFG_MONITOR_BASE,
-			    CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+			    CFG_MONITOR_BASE+monitor_flash_len-1,
 			    &flash_info[0]);
 #endif
 
@@ -121,7 +121,7 @@ unsigned long flash_init (void)
 		/* monitor protection ON by default */
 		(void)flash_protect(FLAG_PROTECT_SET,
 				    CFG_MONITOR_BASE,
-				    CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+				    CFG_MONITOR_BASE+monitor_flash_len-1,
 				    &flash_info[1]);
 #endif
 	}

board/gw8260/flash.c

@@ -96,7 +96,7 @@ unsigned long flash_init (void)
 #if CFG_MONITOR_BASE >= CFG_FLASH0_BASE
     flash_protect(FLAG_PROTECT_SET,
 		  CFG_MONITOR_BASE,
-		  CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		  CFG_MONITOR_BASE+monitor_flash_len-1,
 		  &flash_info[0]);
 #endif
 

board/hermes/flash.c

@@ -71,7 +71,7 @@ unsigned long flash_init (void)
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
 		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 

board/hymod/flash.c

@@ -321,7 +321,7 @@ flash_init(void)
 #if CFG_MONITOR_BASE == CFG_FLASH_BASE
 	(void)flash_protect(FLAG_PROTECT_SET,
 		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 

board/icu862/flash.c

@@ -104,7 +104,7 @@ unsigned long flash_init (void)
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
 		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 

board/impa7/flash.c

@@ -72,7 +72,7 @@ ulong flash_init(void)
      */
     flash_protect(FLAG_PROTECT_SET,
 		  CFG_FLASH_BASE,
-		  CFG_FLASH_BASE + _armboot_end_data - _armboot_start,
+		  CFG_FLASH_BASE + monitor_flash_len - 1,
 		  &flash_info[0]);
 
     flash_protect(FLAG_PROTECT_SET,

board/incaip/flash.c

@@ -100,7 +100,7 @@ unsigned long flash_init (void)
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
 		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
 		      flash_get_info(CFG_MONITOR_BASE));
 #endif
 

board/ip860/flash.c

@@ -90,7 +90,7 @@ unsigned long flash_init (void)
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
 		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 

board/iphase4539/flash.c

@@ -71,7 +71,7 @@ unsigned long flash_init (void)
 		/* monitor protection ON by default */
 		flash_protect(FLAG_PROTECT_SET,
 			      CFG_MONITOR_BASE,
-			      CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+			      CFG_MONITOR_BASE + monitor_flash_len - 1,
 			      flash_info + bank);
 #endif
 

board/ivm/flash.c

@@ -87,7 +87,7 @@ unsigned long flash_init (void)
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
 		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 

board/kup4k/flash.c

@@ -74,7 +74,7 @@ unsigned long flash_init (void)
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
 		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -172,6 +172,9 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 	value = value|(value<<16);
 
 	switch (value) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
 	case FUJ_MANUFACT:
 		info->flash_id = FLASH_MAN_FUJ;
 		break;
@@ -191,6 +194,16 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		info->sector_count = 19;
 		info->size = 0x00100000;
 		break;				/* => 1 MB		*/
+	case AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+	case AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
 	default:
 		info->flash_id = FLASH_UNKNOWN;
 		return (0);			/* => no or unknown flash */

board/kup4k/kup4k.c

@@ -54,10 +54,7 @@ const uint sdram_table[] =
 	/*
 	 * Single Read. (Offset 0 in UPMA RAM)
 	 */
-	0x1F07FC04,
-	0xEEAEFC04,
-	0x11ADFC04,
-	0xEFBBBC00,
+	0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
 	0x1FF77C47, /* last */
 
 	/*
@@ -68,57 +65,37 @@ const uint sdram_table[] =
 	 * sequence, which is executed by a RUN command.
 	 *
 	 */
-	0x1FF77C35,
-	0xEFEABC34,
-	0x1FB57C35,  /* last */
+		    0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
 
 	/*
 	 * Burst Read. (Offset 8 in UPMA RAM)
 	 */
-	0x1F07FC04,
-	0xEEAEFC04,
-	0x10ADFC04,
-	0xF0AFFC00,
-	0xF0AFFC00,
-	0xF1AFFC00,
-	0xEFBBBC00,
-	0x1FF77C47, /* last */
+	0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
+	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 
 	/*
 	 * Single Write. (Offset 18 in UPMA RAM)
 	 */
-	0x1F27FC04,
-	0xEEAEBC00,
-	0x01B93C04,
-    0x1FF77C47, /* last */
+	0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 
 	/*
 	 * Burst Write. (Offset 20 in UPMA RAM)
 	 */
-	0x1F07FC04,
-	0xEEAEBC00,
-	0x10AD7C00,
-	0xF0AFFC00,
-	0xF0AFFC00,
-	0xE1BBBC04,
-	0x1FF77C47, /* last */
-    _NOT_USED_,
+	0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
+	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
+					    _NOT_USED_,
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 
 	/*
 	 * Refresh  (Offset 30 in UPMA RAM)
 	 */
-	0x1FF5FC84,
-	0xFFFFFC04,
-	0xFFFFFC04,
-	0xFFFFFC04,
-	0xFFFFFC84,
-	0xFFFFFC07, /* last */
-	_NOT_USED_, _NOT_USED_,
+	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07, /* last */
+				_NOT_USED_, _NOT_USED_,
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 
 	/*
@@ -146,89 +123,96 @@ int checkboard (void)
 
 long int initdram (int board_type)
 {
-    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
-    volatile memctl8xx_t *memctl = &immap->im_memctl;
-    long int size_b0 = 0;
-    long int size_b1 = 0;
-    long int size_b2 = 0;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size_b0 = 0;
+	long int size_b1 = 0;
+	long int size_b2 = 0;
 
-    upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+	upmconfig (UPMA, (uint *) sdram_table,
+			 sizeof (sdram_table) / sizeof (uint));
 
-    /*
-     * Preliminary prescaler for refresh (depends on number of
-     * banks): This value is selected for four cycles every 62.4 us
-     * with two SDRAM banks or four cycles every 31.2 us with one
-     * bank. It will be adjusted after memory sizing.
-     */
-    memctl->memc_mptpr = CFG_MPTPR;
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CFG_MPTPR;
 
-    memctl->memc_mar  = 0x00000088;
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at
+	 * preliminary addresses - these have to be modified after the
+	 * SDRAM size has been determined.
+	 */
+/*	memctl->memc_or1 = CFG_OR1_PRELIM;	*/
+/*	memctl->memc_br1 = CFG_BR1_PRELIM;	*/
 
-    /*
-     * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at
-     * preliminary addresses - these have to be modified after the
-     * SDRAM size has been determined.
-     */
-/*    memctl->memc_or1 = CFG_OR1_PRELIM;	*/
-/*    memctl->memc_br1 = CFG_BR1_PRELIM;	*/
- 
 /*	memctl->memc_or2 = CFG_OR2_PRELIM;	*/
 /*	memctl->memc_br2 = CFG_BR2_PRELIM;	*/
 
 
-    memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
+	memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE));	/* no refresh yet */
 
-    udelay(200);
+	udelay (200);
 
-    /* perform SDRAM initializsation sequence */
+	/* perform SDRAM initializsation sequence */
 
-    memctl->memc_mcr  = 0x80002105;	/* SDRAM bank 0 */
-    udelay(1);
-    memctl->memc_mcr  = 0x80002830;	/* SDRAM bank 0 - execute twice */
-    udelay(1);
-    memctl->memc_mcr  = 0x80002106;	/* SDRAM bank 0 - RUN MRS Pattern from loc 6 */
-    udelay(1);
+	memctl->memc_mcr = 0x80002105;	/* SDRAM bank 0 */
+	udelay (1);
+	memctl->memc_mcr = 0x80002830;	/* SDRAM bank 0 - execute twice */
+	udelay (1);
+	memctl->memc_mcr = 0x80002106;	/* SDRAM bank 0 - RUN MRS Pattern from loc 6 */
+	udelay (1);
 
-	memctl->memc_mcr  = 0x80004105;	/* SDRAM bank 1 */
-	udelay(1);
-	memctl->memc_mcr  = 0x80004830;	/* SDRAM bank 1 - execute twice */
-	udelay(1);
-    memctl->memc_mcr  = 0x80004106;	/* SDRAM bank 1 - RUN MRS Pattern from loc 6 */
-    udelay(1);
+	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 1 */
+	udelay (1);
+	memctl->memc_mcr = 0x80004830;	/* SDRAM bank 1 - execute twice */
+	udelay (1);
+	memctl->memc_mcr = 0x80004106;	/* SDRAM bank 1 - RUN MRS Pattern from loc 6 */
+	udelay (1);
 
-	memctl->memc_mcr  = 0x80006105;	/* SDRAM bank 2 */
-	udelay(1);
-	memctl->memc_mcr  = 0x80006830;	/* SDRAM bank 2 - execute twice */
-	udelay(1);
-    memctl->memc_mcr  = 0x80006106;	/* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
-    udelay(1);
-
-
-    memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
-
-    udelay (1000);
-
-    size_b0 = 0x00800000;
-    size_b1 = 0x00800000;
-    size_b2 = 0x00800000;
+	memctl->memc_mcr = 0x80006105;	/* SDRAM bank 2 */
+	udelay (1);
+	memctl->memc_mcr = 0x80006830;	/* SDRAM bank 2 - execute twice */
+	udelay (1);
+	memctl->memc_mcr = 0x80006106;	/* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
+	udelay (1);
 
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+	udelay (1000);
 
+#if 0							/* 3 x 8MB */
+	size_b0 = 0x00800000;
+	size_b1 = 0x00800000;
+	size_b2 = 0x00800000;
 	memctl->memc_mptpr = CFG_MPTPR;
-	udelay(1000);
-
+	udelay (1000);
 	memctl->memc_or1 = 0xFF800A00;
 	memctl->memc_br1 = 0x00000081;
-
-    memctl->memc_or2 = 0xFF000A00;
-    memctl->memc_br2 = 0x00800081;
-
+	memctl->memc_or2 = 0xFF000A00;
+	memctl->memc_br2 = 0x00800081;
 	memctl->memc_or3 = 0xFE000A00;
 	memctl->memc_br3 = 0x01000081;
+#else							/* 3 x 16 MB */
+	size_b0 = 0x01000000;
+	size_b1 = 0x01000000;
+	size_b2 = 0x01000000;
+	memctl->memc_mptpr = CFG_MPTPR;
+	udelay (1000);
+	memctl->memc_or1 = 0xFF000A00;
+	memctl->memc_br1 = 0x00000081;
+	memctl->memc_or2 = 0xFE000A00;
+	memctl->memc_br2 = 0x01000081;
+	memctl->memc_or3 = 0xFC000A00;
+	memctl->memc_br3 = 0x02000081;
+#endif
 
-    udelay(10000);
+	udelay (10000);
 
-
-    return (size_b0 + size_b1 + size_b2);
+	return (size_b0 + size_b1 + size_b2);
 }
 
 /* ------------------------------------------------------------------------- */
@@ -241,46 +225,47 @@ long int initdram (int board_type)
  * - short between data lines
  */
 #if 0
-static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+static long int dram_size (long int mamr_value, long int *base,
+						   long int maxsize)
 {
-    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
-    volatile memctl8xx_t *memctl = &immap->im_memctl;
-    volatile long int	 *addr;
-    ulong		  cnt, val;
-    ulong		  save[32];	/* to make test non-destructive */
-    unsigned char	  i = 0;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	volatile long int *addr;
+	ulong cnt, val;
+	ulong save[32];				/* to make test non-destructive */
+	unsigned char i = 0;
 
-    memctl->memc_mamr = mamr_value;
+	memctl->memc_mamr = mamr_value;
 
-    for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
-	addr = base + cnt;	/* pointer arith! */
+	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
+		addr = base + cnt;		/* pointer arith! */
 
-	save[i++] = *addr;
-	*addr = ~cnt;
-    }
-
-    /* write 0 to base address */
-    addr = base;
-    save[i] = *addr;
-    *addr = 0;
-
-    /* check at base address */
-    if ((val = *addr) != 0) {
-	*addr = save[i];
-	return (0);
-    }
-
-    for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
-	addr = base + cnt;	/* pointer arith! */
-
-	val = *addr;
-	*addr = save[--i];
-
-	if (val != (~cnt)) {
-	    return (cnt * sizeof(long));
+		save[i++] = *addr;
+		*addr = ~cnt;
 	}
-    }
-    return (maxsize);
+
+	/* write 0 to base address */
+	addr = base;
+	save[i] = *addr;
+	*addr = 0;
+
+	/* check at base address */
+	if ((val = *addr) != 0) {
+		*addr = save[i];
+		return (0);
+	}
+
+	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+		addr = base + cnt;		/* pointer arith! */
+
+		val = *addr;
+		*addr = save[--i];
+
+		if (val != (~cnt)) {
+			return (cnt * sizeof (long));
+		}
+	}
+	return (maxsize);
 }
 #endif
 
@@ -289,155 +274,175 @@ int misc_init_r (void)
 	DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_STATUS_LED
-	volatile immap_t	*immap = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 #endif
 #ifdef CONFIG_KUP4K_LOGO
 	bd_t *bd = gd->bd;
 
 
-	lcd_logo(bd);
-#endif /* CONFIG_KUP4K_LOGO */
+	lcd_logo (bd);
+#endif							/* CONFIG_KUP4K_LOGO */
 #ifdef CONFIG_IDE_LED
 	/* Configure PA8 as output port */
 	immap->im_ioport.iop_padir |= 0x80;
 	immap->im_ioport.iop_paodr |= 0x80;
 	immap->im_ioport.iop_papar &= ~0x80;
-	immap->im_ioport.iop_padat |= 0x80; /* turn it off */
+	immap->im_ioport.iop_padat |= 0x80;	/* turn it off */
 #endif
-	return(0);
+	return (0);
 }
 
 #ifdef CONFIG_KUP4K_LOGO
-void lcd_logo(bd_t *bd){
 
-    FB_INFO_S1D13xxx fb_info;
-    S1D_INDEX s1dReg;
-    S1D_VALUE s1dValue;
-    volatile immap_t     *immr  = (immap_t *)CFG_IMMR;
-    volatile	memctl8xx_t     *memctl;
+
+#define PB_LCD_PWM	((uint)0x00004000)	/* PB 17 */
+
+void lcd_logo (bd_t * bd)
+{
+
+
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
+
+
+	FB_INFO_S1D13xxx fb_info;
+	S1D_INDEX s1dReg;
+	S1D_VALUE s1dValue;
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl;
 	ushort i;
 	uchar *fb;
-    int rs, gs, bs;
-    int r = 8, g = 8, b = 4;
-    int r1,g1,b1;
+	int rs, gs, bs;
+	int r = 8, g = 8, b = 4;
+	int r1, g1, b1;
+
+	immr->im_cpm.cp_pbpar &= ~PB_LCD_PWM;
+	immr->im_cpm.cp_pbodr &= ~PB_LCD_PWM;
+	immr->im_cpm.cp_pbdat &= ~PB_LCD_PWM;	/* set to 0 = enabled */
+	immr->im_cpm.cp_pbdir |= PB_LCD_PWM;
+
 
 /*----------------------------------------------------------------------------- */
-/**/
+	 /**/
 /* Initialize the chip and the frame buffer driver. */
-/**/
+			 /**/
 /*----------------------------------------------------------------------------- */
-    memctl = &immr->im_memctl;
+			memctl = &immr->im_memctl;
 /*    memctl->memc_or5 = 0xFFC007F0;    / * 4 MB  17 WS or externel TA */
 /*    memctl->memc_br5 = 0x80000801;    / * Start at 0x80000000 */
 
-    memctl->memc_or5 = 0xFFC00708;    /* 4 MB  17 WS or externel TA */
-    memctl->memc_br5 = 0x80080801;    /* Start at 0x80080000 */
+	memctl->memc_or5 = 0xFFC00708;	/* 4 MB  17 WS or externel TA */
+	memctl->memc_br5 = 0x80080801;	/* Start at 0x80080000 */
 
 
 
 
 
-    fb_info.VmemAddr = (unsigned char*)(S1D_PHYSICAL_VMEM_ADDR);
-    fb_info.RegAddr =  (unsigned char*)(S1D_PHYSICAL_REG_ADDR);
+	fb_info.VmemAddr = (unsigned char *) (S1D_PHYSICAL_VMEM_ADDR);
+	fb_info.RegAddr = (unsigned char *) (S1D_PHYSICAL_REG_ADDR);
 
-    if ((((S1D_VALUE*)fb_info.RegAddr)[0] != 0x28) || (((S1D_VALUE*)fb_info.RegAddr)[1] != 0x14))
-    {
-	  printf("Warning:LCD Controller S1D13706 not found\n");
-	  return;
-    }
+	if ((((S1D_VALUE *) fb_info.RegAddr)[0] != 0x28)
+		|| (((S1D_VALUE *) fb_info.RegAddr)[1] != 0x14)) {
+		printf ("Warning:LCD Controller S1D13706 not found\n");
+		return;
+	}
 
-    /* init controller */
-    for (i = 0; i < sizeof(aS1DRegs)/sizeof(aS1DRegs[0]); i++)
-    {
-        s1dReg = aS1DRegs[i].Index;
-        s1dValue = aS1DRegs[i].Value;
+	/* init controller */
+	for (i = 0; i < sizeof (aS1DRegs) / sizeof (aS1DRegs[0]); i++) {
+		s1dReg = aS1DRegs[i].Index;
+		s1dValue = aS1DRegs[i].Value;
 /*      printf("sid1 Index: %02x Register: %02x Wert: %02x\n",i, aS1DRegs[i].Index, aS1DRegs[i].Value); */
-        ((S1D_VALUE*)fb_info.RegAddr)[s1dReg/sizeof(S1D_VALUE)] = s1dValue;
-    }
+		((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] =
+				s1dValue;
+	}
 
 #undef MONOCHROME
 #ifdef MONOCHROME
-   	switch(bd->bi_busfreq){
+	switch (bd->bi_busfreq) {
 #if 0
-		case 24000000:
-			((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
-			((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x28;
-			break;
-		case 32000000:
-			((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
-			((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x33;
-			break;
+	case 24000000:
+		((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
+		((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x28;
+		break;
+	case 32000000:
+		((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
+		((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x33;
+		break;
 #endif
-		case 40000000:
-			((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
-			((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x40;
-			break;
-		case 48000000:
-			((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
-			((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x4C;
-			break;
-		default:
-			printf("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n",bd->bi_busfreq);
-		case 64000000:
-			((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
-			((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x69;
-			break;
+	case 40000000:
+		((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
+		((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x40;
+		break;
+	case 48000000:
+		((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
+		((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x4C;
+		break;
+	default:
+		printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n",
+				bd->bi_busfreq);
+	case 64000000:
+		((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
+		((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x69;
+		break;
 	}
-	((S1D_VALUE*)fb_info.RegAddr)[0x10] = 0x00;
+	((S1D_VALUE *) fb_info.RegAddr)[0x10] = 0x00;
 #else
-	   	switch(bd->bi_busfreq){
+	switch (bd->bi_busfreq) {
 #if 0
-		case 24000000:
-			((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x22;
-			((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x34;
-			break;
-		case 32000000:
-			((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
-			((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x34;
-			break;
+	case 24000000:
+		((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22;
+		((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34;
+		break;
+	case 32000000:
+		((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
+		((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34;
+		break;
 #endif
-		case 40000000:
-			((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
-			((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x41;
-			break;
-		case 48000000:
-			((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x22;
-			((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x34;
-			break;
-		default:
-			printf("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n",bd->bi_busfreq);
-		case 64000000:
-			((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
-			((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x66;
-			break;
+	case 40000000:
+		((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
+		((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x41;
+		break;
+	case 48000000:
+		((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22;
+		((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34;
+		break;
+	default:
+		printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n",
+				bd->bi_busfreq);
+	case 64000000:
+		((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
+		((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x66;
+		break;
 	}
 #endif
 
-    
-    /* create and set colormap */
-    rs = 256 / (r - 1);
-    gs = 256 / (g - 1);
-    bs = 256 / (b - 1);
-	for(i=0;i<256;i++){
-       r1=(rs * ((i / (g * b)) % r)) * 255;
-       g1=(gs * ((i / b) % g)) * 255;
-       b1=(bs * ((i) % b)) * 255;
-/*     printf("%d %04x %04x %04x\n",i,r1>>4,g1>>4,b1>>4); */
-       S1D_WRITE_PALETTE(fb_info.RegAddr,i,(r1>>4),(g1>>4),(b1>>4));
-    }
 
-    /* copy bitmap */
-	fb   = (char *) (fb_info.VmemAddr);
-	memcpy (fb, (uchar *)CONFIG_KUP4K_LOGO, 320 * 240);
+	/* create and set colormap */
+	rs = 256 / (r - 1);
+	gs = 256 / (g - 1);
+	bs = 256 / (b - 1);
+	for (i = 0; i < 256; i++) {
+		r1 = (rs * ((i / (g * b)) % r)) * 255;
+		g1 = (gs * ((i / b) % g)) * 255;
+		b1 = (bs * ((i) % b)) * 255;
+/*     printf("%d %04x %04x %04x\n",i,r1>>4,g1>>4,b1>>4); */
+		S1D_WRITE_PALETTE (fb_info.RegAddr, i, (r1 >> 4), (g1 >> 4),
+						   (b1 >> 4));
+	}
+
+	/* copy bitmap */
+	fb = (char *) (fb_info.VmemAddr);
+	memcpy (fb, (uchar *) CONFIG_KUP4K_LOGO, 320 * 240);
 }
-#endif /* CONFIG_KUP4K_LOGO */
+#endif							/* CONFIG_KUP4K_LOGO */
 
 #ifdef CONFIG_IDE_LED
 void ide_led (uchar led, uchar status)
 {
-	volatile immap_t	*immap = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
 	/* We have one led for both pcmcia slots */
-	if (status) { /* led on */
+	if (status) {				/* led on */
 		immap->im_ioport.iop_padat &= ~0x80;
 	} else {
 		immap->im_ioport.iop_padat |= 0x80;

board/kup4k/s1d13706.h

@@ -50,66 +50,64 @@ typedef struct
 
 static S1D_REGS aS1DRegs[] =
 {
-
-
-    {0x04,0x10},   /* BUSCLK MEMCLK Config Register */
+	{0x04,0x10},	/* BUSCLK MEMCLK Config Register */
 #if 0
-    {0x05,0x32},   /* PCLK Config  Register  */
+	{0x05,0x32},	/* PCLK Config  Register  */
 #endif
-    {0x10,0xD0},   /* PANEL Type Register */
-    {0x11,0x00},   /* MOD Rate Register */
+	{0x10,0xD0},	/* PANEL Type Register */
+	{0x11,0x00},	/* MOD Rate Register */
 #if 0
-    {0x12,0x34},   /* Horizontal Total Register */
+	{0x12,0x34},	/* Horizontal Total Register */
 #endif
-    {0x14,0x27},   /* Horizontal Display Period Register */
-    {0x16,0x00},   /* Horizontal Display Period Start Pos Register 0 */
-    {0x17,0x00},   /* Horizontal Display Period Start Pos Register 1 */
-    {0x18,0xF0},   /* Vertical Total Register 0  */
-    {0x19,0x00},   /* Vertical Total Register 1 */
-    {0x1C,0xEF},   /* Vertical Display Period Register 0 */
-    {0x1D,0x00},   /* Vertical Display Period Register 1 */
-    {0x1E,0x00},   /* Vertical Display Period Start Pos Register 0 */
-    {0x1F,0x00},   /* Vertical Display Period Start Pos Register 1 */
-    {0x20,0x87},   /* Horizontal Sync Pulse Width Register */
-    {0x22,0x00},   /* Horizontal Sync Pulse Start Pos Register 0 */
-    {0x23,0x00},   /* Horizontal Sync Pulse Start Pos Register 1 */
-    {0x24,0x80},   /* Vertical Sync Pulse Width Register */
-    {0x26,0x01},   /* Vertical Sync Pulse Start Pos Register 0 */
-    {0x27,0x00},   /* Vertical Sync Pulse Start Pos Register 1 */
-    {0x70,0x83},   /* Display Mode Register */
-    {0x71,0x00},   /* Special Effects Register */
-    {0x74,0x00},   /* Main Window Display Start Address Register 0 */
-    {0x75,0x00},   /* Main Window Display Start Address Register 1 */
-    {0x76,0x00},   /* Main Window Display Start Address Register 2 */
-    {0x78,0x50},   /* Main Window Address Offset Register 0 */
-    {0x79,0x00},   /* Main Window Address Offset Register 1 */
-    {0x7C,0x00},   /* Sub Window Display Start Address Register 0 */
-    {0x7D,0x00},   /* Sub Window Display Start Address Register 1 */
-    {0x7E,0x00},   /* Sub Window Display Start Address Register 2 */
-    {0x80,0x50},   /* Sub Window Address Offset Register 0 */
-    {0x81,0x00},   /* Sub Window Address Offset Register 1 */
-    {0x84,0x00},   /* Sub Window X Start Pos Register 0 */
-    {0x85,0x00},   /* Sub Window X Start Pos Register 1 */
-    {0x88,0x00},   /* Sub Window Y Start Pos Register 0 */
-    {0x89,0x00},   /* Sub Window Y Start Pos Register 1 */
-    {0x8C,0x4F},   /* Sub Window X End Pos Register 0 */
-    {0x8D,0x00},   /* Sub Window X End Pos Register 1 */
-    {0x90,0xEF},   /* Sub Window Y End Pos Register 0 */
-    {0x91,0x00},   /* Sub Window Y End Pos Register 1 */
-    {0xA0,0x00},   /* Power Save Config Register */
-    {0xA1,0x00},   /* CPU Access Control Register */
-    {0xA2,0x00},   /* Software Reset Register */
-    {0xA3,0x00},   /* BIG Endian Support Register */
-    {0xA4,0x00},   /* Scratch Pad Register 0 */
-    {0xA5,0x00},   /* Scratch Pad Register 1 */
-    {0xA8,0x01},   /* GPIO Config Register 0 */
-    {0xA9,0x80},   /* GPIO Config Register 1 */
-    {0xAC,0x01},   /* GPIO Status Control Register 0 */
-    {0xAD,0x00},   /* GPIO Status Control Register 1 */
-    {0xB0,0x00},   /* PWM CV Clock Control Register */
-    {0xB1,0x00},   /* PWM CV Clock Config Register */
-    {0xB2,0x00},   /* CV Clock Burst Length Register */
-    {0xB3,0x00},   /* PWM Clock Duty Cycle Register */
-    {0xAD,0x80},   /* reset seq */
-	{0x70,0x03},   /*  */
+	{0x14,0x27},	/* Horizontal Display Period Register */
+	{0x16,0x00},	/* Horizontal Display Period Start Pos Register 0 */
+	{0x17,0x00},	/* Horizontal Display Period Start Pos Register 1 */
+	{0x18,0xF0},	/* Vertical Total Register 0  */
+	{0x19,0x00},	/* Vertical Total Register 1 */
+	{0x1C,0xEF},	/* Vertical Display Period Register 0 */
+	{0x1D,0x00},	/* Vertical Display Period Register 1 */
+	{0x1E,0x00},	/* Vertical Display Period Start Pos Register 0 */
+	{0x1F,0x00},	/* Vertical Display Period Start Pos Register 1 */
+	{0x20,0x87},	/* Horizontal Sync Pulse Width Register */
+	{0x22,0x00},	/* Horizontal Sync Pulse Start Pos Register 0 */
+	{0x23,0x00},	/* Horizontal Sync Pulse Start Pos Register 1 */
+	{0x24,0x80},	/* Vertical Sync Pulse Width Register */
+	{0x26,0x01},	/* Vertical Sync Pulse Start Pos Register 0 */
+	{0x27,0x00},	/* Vertical Sync Pulse Start Pos Register 1 */
+	{0x70,0x83},	/* Display Mode Register */
+	{0x71,0x00},	/* Special Effects Register */
+	{0x74,0x00},	/* Main Window Display Start Address Register 0 */
+	{0x75,0x00},	/* Main Window Display Start Address Register 1 */
+	{0x76,0x00},	/* Main Window Display Start Address Register 2 */
+	{0x78,0x50},	/* Main Window Address Offset Register 0 */
+	{0x79,0x00},	/* Main Window Address Offset Register 1 */
+	{0x7C,0x00},	/* Sub Window Display Start Address Register 0 */
+	{0x7D,0x00},	/* Sub Window Display Start Address Register 1 */
+	{0x7E,0x00},	/* Sub Window Display Start Address Register 2 */
+	{0x80,0x50},	/* Sub Window Address Offset Register 0 */
+	{0x81,0x00},	/* Sub Window Address Offset Register 1 */
+	{0x84,0x00},	/* Sub Window X Start Pos Register 0 */
+	{0x85,0x00},	/* Sub Window X Start Pos Register 1 */
+	{0x88,0x00},	/* Sub Window Y Start Pos Register 0 */
+	{0x89,0x00},	/* Sub Window Y Start Pos Register 1 */
+	{0x8C,0x4F},	/* Sub Window X End Pos Register 0 */
+	{0x8D,0x00},	/* Sub Window X End Pos Register 1 */
+	{0x90,0xEF},	/* Sub Window Y End Pos Register 0 */
+	{0x91,0x00},	/* Sub Window Y End Pos Register 1 */
+	{0xA0,0x00},	/* Power Save Config Register */
+	{0xA1,0x00},	/* CPU Access Control Register */
+	{0xA2,0x00},	/* Software Reset Register */
+	{0xA3,0x00},	/* BIG Endian Support Register */
+	{0xA4,0x00},	/* Scratch Pad Register 0 */
+	{0xA5,0x00},	/* Scratch Pad Register 1 */
+	{0xA8,0x01},	/* GPIO Config Register 0 */
+	{0xA9,0x80},	/* GPIO Config Register 1 */
+	{0xAC,0x01},	/* GPIO Status Control Register 0 */
+	{0xAD,0x00},	/* GPIO Status Control Register 1 */
+	{0xB0,0x10},	/* PWM CV Clock Control Register */
+	{0xB1,0x80},	/* PWM CV Clock Config Register */
+	{0xB2,0x00},	/* CV Clock Burst Length Register */
+	{0xB3,0xA0},	/* PWM Clock Duty Cycle Register */
+	{0xAD,0x80},	/* reset seq */
+	{0x70,0x03},	/*  */
 };

board/lantec/flash.c

@@ -134,7 +134,7 @@ unsigned long flash_init (void)
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
 		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -166,7 +166,7 @@ unsigned long flash_init (void)
 		/* monitor protection ON by default */
 		flash_protect(FLAG_PROTECT_SET,
 			      CFG_MONITOR_BASE,
-			      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+			      CFG_MONITOR_BASE+monitor_flash_len-1,
 			      &flash_info[1]);
 #endif
 

board/lart/flash.c

@@ -105,7 +105,7 @@ ulong flash_init(void)
      */
     flash_protect(FLAG_PROTECT_SET,
 		  CFG_FLASH_BASE,
-		  CFG_FLASH_BASE + _armboot_end_data - _armboot_start,
+		  CFG_FLASH_BASE + monitor_flash_len - 1,
 		  &flash_info[0]);
 
     flash_protect(FLAG_PROTECT_SET,

board/lubbock/flash.c

@@ -86,7 +86,7 @@ unsigned long flash_init (void)
 	 */
 	flash_protect ( FLAG_PROTECT_SET,
 			CFG_FLASH_BASE,
-			CFG_FLASH_BASE + _armboot_end_data - _armboot_start,
+			CFG_FLASH_BASE + monitor_flash_len - 1,
 			&flash_info[0] );
 
 	flash_protect ( FLAG_PROTECT_SET,

board/lwmon/flash.c

@@ -123,7 +123,7 @@ unsigned long flash_init (void)
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
 		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -156,7 +156,7 @@ unsigned long flash_init (void)
 		/* monitor protection ON by default */
 		flash_protect(FLAG_PROTECT_SET,
 			      CFG_MONITOR_BASE,
-			      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+			      CFG_MONITOR_BASE+monitor_flash_len-1,
 			      &flash_info[1]);
 #endif
 

board/mbx8xx/flash.c

@@ -79,7 +79,7 @@ unsigned long flash_init (void)
     /* monitor protection ON by default */
     flash_protect(FLAG_PROTECT_SET,
 		  CFG_MONITOR_BASE,
-		  CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		  CFG_MONITOR_BASE+monitor_flash_len-1,
 		  &flash_info[0]);
 #endif
 

board/mpc8260ads/flash.c

@@ -100,7 +100,7 @@ unsigned long flash_init (void)
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
 		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 

board/mpc8266ads/flash.c

@@ -101,7 +101,7 @@ unsigned long flash_init (void)
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
 		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 

board/mpc8266ads/mpc8266ads.c

@@ -489,10 +489,13 @@ long int initdram(int board_type)
      * The appropriate BRx/ORx registers have already been set when we
      * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
      */
-#if 1
+
     memctl->memc_mptpr = CFG_MPTPR;
     memctl->memc_psrt  = psrt;
 
+    memctl->memc_br2 = CFG_BR2_PRELIM;
+    memctl->memc_or2 = or;
+    
     memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
     *ramaddr = c;
 
@@ -530,41 +533,7 @@ long int initdram(int board_type)
 		memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
 		*ramaddr = c;
     }
-#endif
-	/*
-    printf("memctl->memc_mptpr = 0x%08x\n", CFG_MPTPR);
-    printf("memctl->memc_psrt  = 0x%08x\n", psrt);
 
-    printf("memctl->memc_psdmr = 0x%08x\n", psdmr | PSDMR_OP_PREA);
-    printf("ramaddr = 0x%08x\n", ramaddr);
-
-    printf("memctl->memc_psdmr = 0x%08x\n", psdmr | PSDMR_OP_CBRR);
-
-    printf("memctl->memc_psdmr = 0x%08x\n", psdmr | PSDMR_OP_MRW);
-
-    printf("memctl->memc_psdmr = 0x%08x\n", psdmr | PSDMR_OP_NORM | PSDMR_RFEN);
-
-    immap->im_siu_conf.sc_ppc_acr   = 0x00000002;
-    immap->im_siu_conf.sc_ppc_alrh  = 0x01267893;
-    immap->im_siu_conf.sc_tescr1    = 0x00004000;
-	*/
-#if 0
-    /* init sdram dimm */
-    ramaddr                         = (uchar *)CFG_SDRAM_BASE;
-    memctl->memc_psrt               = 0x00000010;
-    immap->im_memctl.memc_or2       = 0xFF000CA0;
-    immap->im_memctl.memc_br2       = 0x00000041;
-    memctl->memc_psdmr              = 0x296EB452;
-    *ramaddr                        = c;
-    memctl->memc_psdmr              = 0x096EB452;
-    for (i = 0; i < 8; i++)
-        *ramaddr                    = c;
-
-    memctl->memc_psdmr              = 0x196EB452;
-    *ramaddr                        = c;
-    memctl->memc_psdmr              = 0x416EB452;
-    *ramaddr                        = c;
-#endif	
 	/* print info */
 	printf("SDRAM configuration read from SPD\n");
 	printf("\tSize per side = %dMB\n", sdram_size >> 20);
@@ -576,6 +545,7 @@ long int initdram(int board_type)
 	/*return (16 * 1024 * 1024);*/
 }
 
+
 #ifdef	CONFIG_PCI
 struct pci_controller hose;
 

board/mpl/common/flash.c

@@ -102,7 +102,7 @@ unsigned long flash_init (void)
 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
 	flash_protect(FLAG_PROTECT_SET,
 			CFG_MONITOR_BASE,
-			CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+			CFG_MONITOR_BASE+monitor_flash_len-1,
 			&flash_info[0]);
 #endif
 	size_b1 = 0 ;

board/mpl/vcma9/flash.c

@@ -113,7 +113,7 @@ ulong flash_init(void)
 
     flash_protect(FLAG_PROTECT_SET,
 		  CFG_FLASH_BASE,
-		  CFG_FLASH_BASE + _armboot_end - _armboot_start,
+		  CFG_FLASH_BASE + monitor_flash_len - 1,
 		  &flash_info[0]);
 
     flash_protect(FLAG_PROTECT_SET,

board/musenki/flash.c

@@ -146,11 +146,11 @@ unsigned long flash_init (void)
 	flash_info[0].size = size_b0;
 
 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
-	DEBUGF("protect monitor %x @ %x\n", CFG_MONITOR_BASE, CFG_MONITOR_LEN);
+	DEBUGF("protect monitor %x @ %x\n", CFG_MONITOR_BASE, monitor_flash_len);
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
 		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -171,7 +171,7 @@ unsigned long flash_init (void)
 		/* monitor protection ON by default */
 		flash_protect(FLAG_PROTECT_SET,
 			      CFG_MONITOR_BASE,
-			      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+			      CFG_MONITOR_BASE+monitor_flash_len-1,
 			      &flash_info[1]);
 #endif
 

board/mvs1/flash.c

@@ -115,7 +115,7 @@ unsigned long flash_init (void)
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
 		      CFG_FLASH_BASE,
-		      CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+		      CFG_FLASH_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 
 	if (size_b1) {
@@ -136,7 +136,7 @@ unsigned long flash_init (void)
 		/* monitor protection ON by default */
 		flash_protect(FLAG_PROTECT_SET,
 			      CFG_FLASH_BASE,
-			      CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+			      CFG_FLASH_BASE+monitor_flash_len-1,
 			      &flash_info[1]);
 	} else {
 		memctl->memc_br1 = 0;		/* invalidate bank */

board/netvia/flash.c

@@ -66,7 +66,7 @@ unsigned long flash_init(void)
 	flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]);
 
 	/* monitor protection ON by default */
-	flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE, CFG_FLASH_BASE + CFG_MONITOR_LEN - 1, &flash_info[0]);
+	flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
 
 	flash_info[0].size = size;
 

board/nx823/flash.c

@@ -93,7 +93,7 @@ unsigned long flash_init (void)
 	/* monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
 			    CFG_FLASH_BASE,
-			    CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+			    CFG_FLASH_BASE+monitor_flash_len-1,
 			    &flash_info[0]);
 
 	flash_info[0].size = size_b0;

board/oxc/flash.c

@@ -69,7 +69,7 @@ unsigned long flash_init (void)
     /* monitor protection ON by default */
     flash_protect(FLAG_PROTECT_SET,
 		  CFG_MONITOR_BASE,
-		  CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		  CFG_MONITOR_BASE+monitor_flash_len-1,
 		  &flash_info[0]);
 #endif
 

board/pcippc2/flash.c

@@ -70,7 +70,7 @@ unsigned long flash_init (void)
 		/* monitor protection ON by default */
 		flash_protect(FLAG_PROTECT_SET,
 			      CFG_MONITOR_BASE,
-			      CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+			      CFG_MONITOR_BASE + monitor_flash_len - 1,
 			      &flash_info[0]);
 #endif
 

board/pm826/flash.c

@@ -133,7 +133,7 @@ unsigned long flash_init (void)
 # if CFG_MONITOR_BASE >= CFG_FLASH0_BASE
 	flash_protect (FLAG_PROTECT_SET,
 		       CFG_MONITOR_BASE,
-		       CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, &flash_info[0]
+		       CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]
 	);
 # endif
 #endif	/* CONFIG_BOOT_ROM */

board/ppmc8260/strataflash.c

@@ -201,7 +201,7 @@ unsigned long flash_init (void)
 
 	/* Monitor protection ON by default */
 #if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
-	for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+CFG_MONITOR_LEN-1; i++)
+	for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+monitor_flash_len-1; i++)
 		(void)flash_real_protect(&flash_info[0], i, 1);
 #endif
 

board/purple/flash.c

@@ -233,7 +233,7 @@ unsigned long flash_init (void)
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
 		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
 		      flash_get_info(CFG_MONITOR_BASE));
 #endif
 

board/purple/purple.c

@@ -232,6 +232,7 @@ static void programLoad(void)
 */
 void copy_code (ulong dest_addr)
 {
+	extern long uboot_end_data;
 	unsigned long start;
 	unsigned long end;
 
@@ -243,7 +244,7 @@ void copy_code (ulong dest_addr)
 	 */
 	copyLongs((ulong *)CFG_MONITOR_BASE,
 		  (ulong *)dest_addr,
-		  (CFG_MONITOR_LEN + 3) / 4);
+		  ((ulong)&uboot_end_data - CFG_MONITOR_BASE + 3) / 4);
 
 
 	/* flush caches

board/r360mpi/flash.c

@@ -107,7 +107,7 @@ unsigned long flash_init (void)
 	/* monitor protection ON by default */
 	(void) flash_protect (FLAG_PROTECT_SET,
 				CFG_FLASH_BASE,
-				CFG_FLASH_BASE + CFG_MONITOR_LEN - 1,
+				CFG_FLASH_BASE + monitor_flash_len - 1,
 				&flash_info[0]);
 #endif
 

board/rbc823/Makefile

@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o kbd.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $^
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/rbc823/config.mk

@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# RBC823 boards
+#
+
+TEXT_BASE = 0xFFF00000

board/rbc823/flash.c

@@ -0,0 +1,470 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i)
+	    flash_info[i].flash_id = FLASH_UNKNOWN;
+
+	/* Detect size */
+	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	/* Setup offsets */
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* Monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+	size_b1 = 0 ;
+
+	flash_info[1].flash_id = FLASH_UNKNOWN;
+	flash_info[1].sector_count = -1;
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ * Fix this to support variable sector sizes
+*/
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		/* set sector offsets for bottom boot block type	*/
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+	{
+		puts ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK)
+	{
+		case FLASH_MAN_AMD:	printf ("AMD ");		break;
+		case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+		case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+		default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK)
+	{
+		case FLASH_AM040:	printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
+			break;
+		case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+					break;
+		case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+					break;
+		case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+					break;
+		case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+					break;
+		case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+					break;
+		case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+					break;
+		case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+					break;
+		case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+					break;
+		default:		printf ("Unknown Chip Type\n");
+					break;
+	}
+
+	if (info->size >> 20) {
+	    printf ("  Size: %ld MB in %d Sectors\n",
+	    	info->size >> 20,
+		info->sector_count);
+	} else {
+	    printf ("  Size: %ld KB in %d Sectors\n",
+	    	info->size >> 10,
+		info->sector_count);
+	}
+
+	puts ("  Sector Start Addresses:");
+
+	for (i=0; i<info->sector_count; ++i)
+	{
+		if ((i % 5) == 0)
+		{
+			puts ("\n   ");
+		}
+
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+
+	putc ('\n');
+	return;
+}
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	volatile unsigned char *caddr;
+	char value;
+
+	caddr = (volatile unsigned char *)addr ;
+
+	/* Write auto select command: read Manufacturer ID */
+
+#if 0
+	printf("Base address is: %08x\n", caddr);
+#endif
+
+	caddr[0x0555] = 0xAA;
+	caddr[0x02AA] = 0x55;
+	caddr[0x0555] = 0x90;
+
+	value = caddr[0];
+
+#if 0
+	printf("Manufact ID: %02x\n", value);
+#endif
+	switch (value)
+	{
+		case 0x01:
+		case AMD_MANUFACT:
+			info->flash_id = FLASH_MAN_AMD;
+		break;
+
+		case FUJ_MANUFACT:
+			info->flash_id = FLASH_MAN_FUJ;
+		break;
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			break;
+	}
+
+	value = caddr[1];			/* device ID		*/
+#if 0
+	printf("Device ID: %02x\n", value);
+#endif
+	switch (value)
+	{
+		case AMD_ID_LV040B:
+			info->flash_id += FLASH_AM040;
+			info->sector_count = 8;
+			info->size = 0x00080000;
+			break;				/* => 512Kb 		*/
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			return (0);			/* => no or unknown flash */
+
+	}
+
+	flash_get_offsets ((ulong)addr, &flash_info[0]);
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++)
+	{
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		caddr = (volatile unsigned char *)(info->start[i]);
+		info->protect[i] = caddr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN)
+	{
+		caddr = (volatile unsigned char *)info->start[0];
+		*caddr = 0xF0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0x80;
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (volatile unsigned char *)(info->start[sect]);
+			addr[0] = 0x30;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (volatile unsigned char *)(info->start[l_sect]);
+
+	while ((addr[0] & 0xFF) != 0xFF)
+	{
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned char *)info->start[0];
+
+	addr[0] = 0xF0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	volatile unsigned char *addr = (volatile unsigned char*)(info->start[0]),
+				*cdest,*cdata;
+	ulong start;
+	int flag, count = 4 ;
+
+	cdest = (volatile unsigned char *)dest ;
+	cdata = (volatile unsigned char *)&data ;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+
+	while(count--)
+	{
+	    /* Disable interrupts which might cause a timeout here */
+	    flag = disable_interrupts();
+
+	    addr[0x0555] = 0xAA;
+	    addr[0x02AA] = 0x55;
+	    addr[0x0555] = 0xA0;
+
+	    *cdest = *cdata;
+
+	    /* re-enable interrupts if necessary */
+	    if (flag)
+	    	enable_interrupts();
+
+	    /* data polling for D7 */
+	    start = get_timer (0);
+	    while ((*cdest ^ *cdata) & 0x80)
+	    {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	    }
+
+	    cdata++ ;
+	    cdest++ ;
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */

board/rbc823/kbd.c

@@ -0,0 +1,269 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Modified by Udi Finkelstein
+ *
+ * This file includes communication routines for SMC1 that can run even if
+ * SMC2 have already been initialized.
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <commproc.h>
+#include <devices.h>
+#include <lcd.h>
+
+#define	SMC_INDEX	0
+#define PROFF_SMC	PROFF_SMC1
+#define CPM_CR_CH_SMC	CPM_CR_CH_SMC1
+
+#define RBC823_KBD_BAUDRATE	38400
+#define CPM_KEYBOARD_BASE	0x1000
+/*
+ * Minimal serial functions needed to use one of the SMC ports
+ * as serial console interface.
+ */
+
+void smc1_setbrg (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+        volatile immap_t *im = (immap_t *)CFG_IMMR;
+	volatile cpm8xx_t *cp = &(im->im_cpm);
+
+	/* Set up the baud rate generator.
+	 * See 8xx_io/commproc.c for details.
+	 *
+	 * Wire BRG2 to SMC1, BRG1 to SMC2
+	 */
+
+	cp->cp_simode = 0x00001000;
+
+	cp->cp_brgc2 =
+		(((gd->cpu_clk / 16 / RBC823_KBD_BAUDRATE)-1) << 1) | CPM_BRG_EN;
+}
+
+int smc1_init (void)
+{
+        volatile immap_t *im = (immap_t *)CFG_IMMR;
+	volatile smc_t *sp;
+	volatile smc_uart_t *up;
+	volatile cbd_t *tbdf, *rbdf;
+	volatile cpm8xx_t *cp = &(im->im_cpm);
+	uint	dpaddr;
+
+	/* initialize pointers to SMC */
+
+	sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
+	up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
+
+	/* Disable transmitter/receiver.
+	*/
+	sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
+
+	/* Enable SDMA.
+	*/
+	im->im_siu_conf.sc_sdcr = 1;
+
+	/* clear error conditions */
+#ifdef	CFG_SDSR
+	im->im_sdma.sdma_sdsr = CFG_SDSR;
+#else
+	im->im_sdma.sdma_sdsr = 0x83;
+#endif
+
+	/* clear SDMA interrupt mask */
+#ifdef	CFG_SDMR
+	im->im_sdma.sdma_sdmr = CFG_SDMR;
+#else
+	im->im_sdma.sdma_sdmr = 0x00;
+#endif
+
+	/* Use Port B for SMC1 instead of other functions.
+	*/
+	cp->cp_pbpar |=  0x000000c0;
+	cp->cp_pbdir &= ~0x000000c0;
+	cp->cp_pbodr &= ~0x000000c0;
+
+	/* Set the physical address of the host memory buffers in
+	 * the buffer descriptors.
+	 */
+
+#ifdef CFG_ALLOC_DPRAM
+	dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
+#else
+	dpaddr = CPM_KEYBOARD_BASE ;
+#endif
+
+	/* Allocate space for two buffer descriptors in the DP ram.
+	 * For now, this address seems OK, but it may have to
+	 * change with newer versions of the firmware.
+	 * damm: allocating space after the two buffers for rx/tx data
+	 */
+
+	rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
+	rbdf->cbd_bufaddr = (uint) (rbdf+2);
+	rbdf->cbd_sc = 0;
+	tbdf = rbdf + 1;
+	tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
+	tbdf->cbd_sc = 0;
+
+	/* Set up the uart parameters in the parameter ram.
+	*/
+	up->smc_rbase = dpaddr;
+	up->smc_tbase = dpaddr+sizeof(cbd_t);
+	up->smc_rfcr = SMC_EB;
+	up->smc_tfcr = SMC_EB;
+
+	/* Set UART mode, 8 bit, no parity, one stop.
+	 * Enable receive and transmit.
+	 */
+	sp->smc_smcmr = smcr_mk_clen(9) |  SMCMR_SM_UART;
+
+	/* Mask all interrupts and remove anything pending.
+	*/
+	sp->smc_smcm = 0;
+	sp->smc_smce = 0xff;
+
+	/* Set up the baud rate generator.
+	*/
+	smc1_setbrg ();
+
+	/* Make the first buffer the only buffer.
+	*/
+	tbdf->cbd_sc |= BD_SC_WRAP;
+	rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
+
+	/* Single character receive.
+	*/
+	up->smc_mrblr = 1;
+	up->smc_maxidl = 0;
+
+	/* Initialize Tx/Rx parameters.
+	*/
+
+	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
+	  ;
+
+	cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
+
+	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
+	  ;
+
+	/* Enable transmitter/receiver.
+	*/
+	sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
+
+	return (0);
+}
+
+void smc1_putc(const char c)
+{
+	volatile cbd_t		*tbdf;
+	volatile char		*buf;
+	volatile smc_uart_t	*up;
+        volatile immap_t	*im = (immap_t *)CFG_IMMR;
+	volatile cpm8xx_t	*cpmp = &(im->im_cpm);
+
+	up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
+
+	tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase];
+
+	/* Wait for last character to go.
+	*/
+
+	buf = (char *)tbdf->cbd_bufaddr;
+
+	*buf = c;
+	tbdf->cbd_datlen = 1;
+	tbdf->cbd_sc |= BD_SC_READY;
+	__asm__("eieio");
+
+	while (tbdf->cbd_sc & BD_SC_READY) {
+		WATCHDOG_RESET ();
+		__asm__("eieio");
+	}
+}
+
+int smc1_getc(void)
+{
+	volatile cbd_t		*rbdf;
+	volatile unsigned char	*buf;
+	volatile smc_uart_t	*up;
+        volatile immap_t	*im = (immap_t *)CFG_IMMR;
+	volatile cpm8xx_t	*cpmp = &(im->im_cpm);
+	unsigned char		c;
+
+	up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
+
+	rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
+
+	/* Wait for character to show up.
+	*/
+	buf = (unsigned char *)rbdf->cbd_bufaddr;
+
+	while (rbdf->cbd_sc & BD_SC_EMPTY)
+		WATCHDOG_RESET ();
+
+	c = *buf;
+	rbdf->cbd_sc |= BD_SC_EMPTY;
+
+	return(c);
+}
+
+int smc1_tstc(void)
+{
+	volatile cbd_t		*rbdf;
+	volatile smc_uart_t	*up;
+        volatile immap_t	*im = (immap_t *)CFG_IMMR;
+	volatile cpm8xx_t	*cpmp = &(im->im_cpm);
+
+	up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
+
+	rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
+
+	return(!(rbdf->cbd_sc & BD_SC_EMPTY));
+}
+
+/* search for keyboard and register it if found */
+int drv_keyboard_init(void)
+{
+	int error = 0;
+	device_t kbd_dev;
+
+	if (0) {
+		/* register the keyboard */
+		memset (&kbd_dev, 0, sizeof(device_t));
+		strcpy(kbd_dev.name, "kbd");
+		kbd_dev.flags =  DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
+		kbd_dev.putc = NULL;
+		kbd_dev.puts = NULL;
+		kbd_dev.getc = smc1_getc;
+		kbd_dev.tstc = smc1_tstc;
+		error = device_register (&kbd_dev);
+	} else {
+		lcd_is_enabled = 0;
+		lcd_disable();
+	}
+	return error;
+}

board/rbc823/rbc823.c

@@ -0,0 +1,292 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include "mpc8xx.h"
+#include <linux/mtd/doc2000.h>
+
+extern int kbd_init(void);
+extern int drv_kbd_init(void);
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] =
+{
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
+	0x1FF77C47, /* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+		    0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
+	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
+	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
+					    _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07, /* last */
+				_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x1FF7FC07, /* last */
+		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+const uint static_table[] =
+{
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x0FFFFC04, 0x0FF3FC04, 0x0FF3CC04, 0x0FF3CC04,
+	0x0FF3EC04, 0x0FF3CC00, 0x0FF7FC04, 0x3FFFFC04,
+	0xFFFFFC04, 0xFFFFFC05, /* last */
+	                        _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x0FFFFC04, 0x00FFFC04, 0x00FFFC04, 0x00FFFC04,
+	0x01FFFC00, 0x3FFFFC04, 0xFFFFFC04, 0xFFFFFC05, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ *
+ * Test TQ ID string (TQM8xx...)
+ * If present, check for "L" type (no second DRAM bank),
+ * otherwise "L" type is assumed as default.
+ *
+ * Return 1 for "L" type, 0 else.
+ */
+
+int checkboard (void)
+{
+    unsigned char *s = getenv("serial#");
+
+    if (!s || strncmp(s, "TQM8", 4)) {
+	printf ("### No HW ID - assuming RBC823\n");
+	return (0);
+    }
+
+    puts(s);
+    putc ('\n');
+
+    return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile memctl8xx_t *memctl = &immap->im_memctl;
+    long int size_b0, size8, size9;
+
+    upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+    /*
+     * 1 Bank of 64Mbit x 2 devices 
+     */
+    memctl->memc_mptpr = CFG_MPTPR_1BK_4K;
+    memctl->memc_mar  = 0x00000088;
+
+    /*
+     * Map controller SDRAM bank 0
+     */
+    memctl->memc_or4 = CFG_OR4_PRELIM;
+    memctl->memc_br4 = CFG_BR4_PRELIM;
+    memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
+    udelay(200);
+
+    /* 
+     * Perform SDRAM initializsation sequence 
+     */
+    memctl->memc_mcr  = 0x80008105;	/* SDRAM bank 0 */
+    udelay(1);
+    memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_8X;
+    udelay(200);
+    memctl->memc_mcr  = 0x80008130;	/* SDRAM bank 0 - execute twice */
+    udelay(1);
+    memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_4X;
+    udelay(200); 
+
+    memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+    udelay (1000);
+
+    /*
+     * Preliminary prescaler for refresh (depends on number of
+     * banks): This value is selected for four cycles every 62.4 us
+     * with two SDRAM banks or four cycles every 31.2 us with one
+     * bank. It will be adjusted after memory sizing.
+     */
+    memctl->memc_mptpr = CFG_MPTPR_2BK_4K; // 16: but should be: CFG_MPTPR_1BK_4K
+
+    /*
+     * Check Bank 0 Memory Size for re-configuration
+     *
+     * try 8 column mode
+     */
+    size8 = dram_size (CFG_MAMR_8COL, (ulong *)SDRAM_BASE4_PRELIM, SDRAM_MAX_SIZE);
+    udelay (1000);
+
+    /*
+     * try 9 column mode
+     */
+    size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE4_PRELIM, SDRAM_MAX_SIZE);
+
+    if (size8 < size9) {		/* leave configuration at 9 columns	*/
+	size_b0 = size9;
+/*	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
+    } else {				/* back to 8 columns			*/
+	size_b0 = size8;
+	memctl->memc_mamr = CFG_MAMR_8COL;
+	udelay(500);
+/*	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
+    }
+
+    udelay (1000);
+
+    /*
+     * Adjust refresh rate depending on SDRAM type, both banks
+     * For types > 128 MBit leave it at the current (fast) rate
+     */
+    if ((size_b0 < 0x02000000) ) {
+	/* reduce to 15.6 us (62.4 us / quad) */
+	memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+	udelay(1000);
+    }
+
+    /* SDRAM Bank 0 is bigger - map first	*/
+
+    memctl->memc_or4 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+    memctl->memc_br4 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+    udelay(10000);
+
+    return (size_b0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+{
+    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile memctl8xx_t *memctl = &immap->im_memctl;
+    volatile long int	 *addr;
+    long int		  cnt, val;
+
+    memctl->memc_mamr = mamr_value;
+
+    for (cnt = maxsize/sizeof(long)/2; cnt > 0; cnt >>= 1) {
+	addr = base + cnt;	/* pointer arith! */
+
+	*addr = ~cnt;
+    }
+
+    /* write 0 to base address */
+    addr = base;
+    *addr = 0;
+
+    /* check at base address */
+    if ((val = *addr) != 0) {
+	return (0);
+    }
+
+    for (cnt = 1; cnt < maxsize/sizeof(long) ; cnt <<= 1) {
+	addr = base + cnt;	/* pointer arith! */
+
+	val = *addr;
+
+	if (val != (~cnt)) {
+	    return (cnt * sizeof(long));
+	}
+    }
+    return cnt * sizeof(long);
+    /* NOTREACHED */
+}
+
+void doc_init(void)
+{
+    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+    upmconfig(UPMB, (uint *)static_table, sizeof(static_table)/sizeof(uint));
+    memctl->memc_mbmr = MAMR_DSA_1_CYCL;
+
+    doc_probe(FLASH_BASE1_PRELIM);
+}
+

board/rbc823/u-boot.lds

@@ -0,0 +1,133 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+

board/rpxsuper/flash.c

@@ -67,7 +67,7 @@ unsigned long flash_init (void)
 #if CFG_MONITOR_BASE >= CFG_FLASH0_BASE
     flash_protect(FLAG_PROTECT_SET,
 		  CFG_MONITOR_BASE,
-		  CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		  CFG_MONITOR_BASE+monitor_flash_len-1,
 		  &flash_info[0]);
 #endif
 

board/rsdproto/flash.c

@@ -123,11 +123,11 @@ unsigned long flash_init (void)
 #if CFG_MONITOR_BASE >= PHYS_FLASH
 	flash_protect(FLAG_PROTECT_SET,
 		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 	flash_protect(FLAG_PROTECT_SET,
 		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[1]);
 #endif
 

board/sacsng/flash.c

@@ -69,7 +69,7 @@ unsigned long flash_init (void)
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
 		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -86,7 +86,7 @@ unsigned long flash_init (void)
 		/* monitor protection ON by default */
 		flash_protect(FLAG_PROTECT_SET,
 			      CFG_MONITOR_BASE,
-			      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+			      CFG_MONITOR_BASE+monitor_flash_len-1,
 			      &flash_info[1]);
 #endif
 

board/sandpoint/flash.c

@@ -228,7 +228,7 @@ flash_init(void)
 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
     flash_protect(FLAG_PROTECT_SET,
 		CFG_MONITOR_BASE,
-		CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+		CFG_MONITOR_BASE + monitor_flash_len - 1,
 		&flash_info[0]);
 #endif
 

board/sbc8260/flash.c

@@ -63,7 +63,7 @@ unsigned long flash_init (void)
 #if CFG_MONITOR_BASE >= CFG_FLASH0_BASE
     flash_protect(FLAG_PROTECT_SET,
 		  CFG_MONITOR_BASE,
-		  CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		  CFG_MONITOR_BASE+monitor_flash_len-1,
 		  &flash_info[0]);
 #endif
 

board/sc520_cdp/config.mk

@@ -22,4 +22,4 @@
 #
 
 
-TEXT_BASE = 0x387e0000
+TEXT_BASE = 0x387c0000

board/sc520_cdp/flash.c

@@ -1,4 +1,7 @@
 /*
+ * (C) Copyright 2002, 2003
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
+ * 
  * (C) Copyright 2002
  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  * Alex Zuepke <azu@sysgo.de>
@@ -23,31 +26,23 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
+#include <pci.h>
+#include <asm/ic/sc520.h>
 
-ulong myflush(void);
+#define PROBE_BUFFER_SIZE 1024
+static unsigned char buffer[PROBE_BUFFER_SIZE];
 
+#define SC520_MAX_FLASH_BANKS  3
+#define SC520_FLASH_BANK0_BASE 0x38000000  /* BOOTCS */
+#define SC520_FLASH_BANK1_BASE 0x30000000  /* ROMCS0 */
+#define SC520_FLASH_BANK2_BASE 0x28000000  /* ROMCS1 */
+#define SC520_FLASH_BANKSIZE   0x8000000
 
-#define FLASH_BANK_SIZE 0x400000	/* 4 MB */
-#define MAIN_SECT_SIZE  0x20000		/* 128 KB */
+#define AMD29LV016B_SIZE        0x200000
+#define AMD29LV016B_SECTORS     32
 
-flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
-
-
-#define CMD_READ_ARRAY		0x00F000F0
-#define CMD_UNLOCK1		0x00AA00AA
-#define CMD_UNLOCK2		0x00550055
-#define CMD_ERASE_SETUP		0x00800080
-#define CMD_ERASE_CONFIRM	0x00300030
-#define CMD_PROGRAM		0x00A000A0
-#define CMD_UNLOCK_BYPASS	0x00200020
-
-#define MEM_FLASH_ADDR1		(*(volatile u32 *)(CFG_FLASH_BASE + (0x00000555 << 2)))
-#define MEM_FLASH_ADDR2		(*(volatile u32 *)(CFG_FLASH_BASE + (0x000002AA << 2)))
-
-#define BIT_ERASE_DONE		0x00800080
-#define BIT_RDY_MASK		0x00800080
-#define BIT_PROGRAM_ERROR	0x00200020
-#define BIT_TIMEOUT		0x80000000 /* our flag */
+flash_info_t    flash_info[SC520_MAX_FLASH_BANKS];
 
 #define READY 1
 #define ERR   2
@@ -56,394 +51,592 @@ flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
 /*-----------------------------------------------------------------------
  */
 
+
+static u32 _probe_flash(u32 addr, u32 bw, int il)
+{
+	u32 result=0;
+	
+	/* First do an unlock cycle for the benefit of
+	 * devices that need it */
+	
+	switch (bw) {
+		
+	case 1:
+		*(volatile u8*)(addr+0x5555) = 0xaa;
+		*(volatile u8*)(addr+0x2aaa) = 0x55;
+		*(volatile u8*)(addr+0x5555) = 0x90;
+		
+		/* Read vendor */
+		result = *(volatile u8*)addr;
+		result <<= 16;
+		
+		/* Read device */
+		result |= *(volatile u8*)(addr+2);
+		
+		/* Return device to data mode */
+		*(volatile u8*)addr = 0xff;
+		*(volatile u8*)(addr+0x5555), 0xf0;  
+		break;
+		
+	case 2:
+		*(volatile u16*)(addr+0xaaaa) = 0xaaaa;
+		*(volatile u16*)(addr+0x5554) = 0x5555;
+		
+		/* Issue identification command */
+		if (il == 2) {
+			*(volatile u16*)(addr+0xaaaa) = 0x9090;
+			
+			/* Read vendor */
+			result = *(volatile u8*)addr;
+			result <<= 16;
+			
+			/* Read device */
+			result |= *(volatile u8*)(addr+2);
+			
+			/* Return device to data mode */
+			*(volatile u16*)addr =  0xffff;
+			*(volatile u16*)(addr+0xaaaa), 0xf0f0;  
+			
+		} else {
+			*(volatile u8*)(addr+0xaaaa) = 0x90;
+			/* Read vendor */
+			result = *(volatile u16*)addr;
+			result <<= 16;
+			
+			/* Read device */
+			result |= *(volatile u16*)(addr+2);
+			
+			/* Return device to data mode */
+			*(volatile u8*)addr = 0xff;
+			*(volatile u8*)(addr+0xaaaa), 0xf0;  			
+		}
+		
+		break;
+		
+	 case 4:
+		*(volatile u32*)(addr+0x5554) = 0xaaaaaaaa;
+		*(volatile u32*)(addr+0xaaa8) = 0x55555555;
+		
+		switch (il) {
+		case 1:
+			/* Issue identification command */
+			*(volatile u8*)(addr+0x5554) = 0x90;
+			
+			/* Read vendor */
+			result = *(volatile u16*)addr;
+			result <<= 16;
+		
+			/* Read device */
+			result |= *(volatile u16*)(addr+4);
+			
+			/* Return device to data mode */
+			*(volatile u8*)addr =  0xff;
+			*(volatile u8*)(addr+0x5554), 0xf0;  
+			break;
+			
+		case 2:
+			/* Issue identification command */
+			*(volatile u32*)(addr + 0x5554) = 0x00900090;
+			
+			/* Read vendor */
+			result = *(volatile u16*)addr;
+			result <<= 16;
+			
+			/* Read device */
+			result |= *(volatile u16*)(addr+4);
+			
+			/* Return device to data mode */
+			*(volatile u32*)addr =  0x00ff00ff;
+			*(volatile u32*)(addr+0x5554), 0x00f000f0;  
+			break;
+			
+		case 4:
+			/* Issue identification command */
+			*(volatile u32*)(addr+0x5554) = 0x90909090;
+			
+			/* Read vendor */
+			result = *(volatile u8*)addr;
+			result <<= 16;
+			
+			/* Read device */
+			result |= *(volatile u8*)(addr+4);
+			
+			/* Return device to data mode */
+			*(volatile u32*)addr =  0xffffffff;
+			*(volatile u32*)(addr+0x5554), 0xf0f0f0f0; 
+			break;
+		}
+		break;
+	}
+	
+	
+	
+	return result;
+}
+
+extern int _probe_flash_end;
+asm ("_probe_flash_end:\n"
+     ".long 0\n");
+
+static int identify_flash(unsigned address, int width)
+{
+	int is;	
+	int device;
+	int vendor;	
+	int size;
+	unsigned res;
+	
+	u32 (*_probe_flash_ptr)(u32 a, u32 bw, int il);
+	
+	size = (unsigned)&_probe_flash_end - (unsigned)_probe_flash; 
+	
+	if (size > PROBE_BUFFER_SIZE) {
+		printf("_probe_flash() routine too large (%d) %p - %p\n",
+		       size, &_probe_flash_end, _probe_flash);
+		return 0;
+	}
+	
+	memcpy(buffer, _probe_flash, size);
+	_probe_flash_ptr = (void*)buffer;
+	
+	is = disable_interrupts();
+	res = _probe_flash_ptr(address, width, 1);
+	if (is) {
+		enable_interrupts();
+	}
+	
+	
+        vendor = res >> 16;
+	device = res & 0xffff;
+	
+		
+	return res;
+}
+
 ulong flash_init(void)
 {
-    int i, j;
-    ulong size = 0;
-
-    for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
-    {
-	ulong flashbase = 0;
-	flash_info[i].flash_id =
-	  (AMD_MANUFACT & FLASH_VENDMASK) |
-	  (AMD_ID_LV160B & FLASH_TYPEMASK);
-	flash_info[i].size = FLASH_BANK_SIZE;
-	flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-	memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
-	if (i == 0)
-	  flashbase = PHYS_FLASH_1;
-	else
-	  panic("configured to many flash banks!\n");
-	for (j = 0; j < flash_info[i].sector_count; j++)
-	{
-
-	    if (j <= 3)
-	    {
-		/* 1st one is 32 KB */
-		if (j == 0)
-		{
-			flash_info[i].start[j] = flashbase + 0;
+	int i, j;
+	ulong size = 0;
+	
+	for (i = 0; i < SC520_MAX_FLASH_BANKS; i++) {
+		unsigned id;
+		ulong flashbase = 0;
+		int sectsize = 0; 
+		
+		memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		switch (i) {
+		case 0:
+			flashbase = SC520_FLASH_BANK0_BASE;
+			break;
+		case 1:
+			flashbase = SC520_FLASH_BANK1_BASE;
+			break;
+		case 2:
+			flashbase = SC520_FLASH_BANK2_BASE;
+			break;
+		default:
+			panic("configured to many flash banks!\n");
 		}
-
-		/* 2nd and 3rd are both 16 KB */
-		if ((j == 1) || (j == 2))
-		{
-			flash_info[i].start[j] = flashbase + 0x8000 + (j-1)*0x4000;
+		
+		id = identify_flash(flashbase, 4);
+		switch (id & 0x00ff00ff) {
+		case 0x000100c8:
+			/* 29LV016B/29LV017B */
+			flash_info[i].flash_id =
+				(AMD_MANUFACT & FLASH_VENDMASK) |
+				(AMD_ID_LV016B & FLASH_TYPEMASK);
+			
+			flash_info[i].size = AMD29LV016B_SIZE*4;
+			flash_info[i].sector_count = AMD29LV016B_SECTORS;
+			sectsize = (AMD29LV016B_SIZE*4)/AMD29LV016B_SECTORS;
+			printf("Bank %d: 4 x AMD 29LV017B\n", i);
+			break;
+			
+			
+		default:
+			printf("Bank %d have unknown flash %08x\n", i, id);
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+			continue;
 		}
-
-		/* 4th 64 KB */
-		if (j == 3)
-		{
-			flash_info[i].start[j] = flashbase + 0x10000;
+		
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] = flashbase + j * sectsize;
 		}
-	    }
-	    else
-	    {
-		flash_info[i].start[j] = flashbase + (j - 3)*MAIN_SECT_SIZE;
-	    }
+		size += flash_info[i].size;
+		
+		flash_protect(FLAG_PROTECT_CLEAR,
+			      flash_info[i].start[0],
+			       flash_info[i].start[0] + flash_info[i].size - 1,
+			      &flash_info[i]);
 	}
-	size += flash_info[i].size;
-    }
-
-    /*
-     * Protect monitor and environment sectors
-     */
-    flash_protect(FLAG_PROTECT_SET,
-		  i386boot_start-CFG_FLASH_BASE,
-		  i386boot_end-CFG_FLASH_BASE,
-		  &flash_info[0]);
-
-    flash_protect(FLAG_PROTECT_SET,
-		  CFG_ENV_ADDR,
-		  CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
-		  &flash_info[0]);
-    return size;
+	
+	/*
+	 * Protect monitor and environment sectors
+	 */
+	flash_protect(FLAG_PROTECT_SET,
+		      i386boot_start,
+		      i386boot_end,
+		      &flash_info[0]);
+#ifdef CFG_ENV_ADDR
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+		      &flash_info[0]);
+#endif	
+	return size;
 }
 
 /*-----------------------------------------------------------------------
  */
-void flash_print_info  (flash_info_t *info)
+void flash_print_info(flash_info_t *info)
 {
-    int i;
-
-    switch (info->flash_id & FLASH_VENDMASK)
-    {
-    case (AMD_MANUFACT & FLASH_VENDMASK):
-	printf("AMD: ");
-	break;
-    default:
-	printf("Unknown Vendor ");
-	break;
-    }
-
-    switch (info->flash_id & FLASH_TYPEMASK)
-    {
-    case (AMD_ID_LV160B & FLASH_TYPEMASK):
-	printf("2x Amd29F160BB (16Mbit)\n");
-	break;
-    default:
-	printf("Unknown Chip Type\n");
-	goto Done;
-	break;
-    }
-
-    printf("  Size: %ld MB in %d Sectors\n",
-	   info->size >> 20, info->sector_count);
-
-    printf("  Sector Start Addresses:");
-    for (i = 0; i < info->sector_count; i++)
-    {
-	if ((i % 5) == 0)
-	{
-	    printf ("\n   ");
+	int i;
+	
+	switch (info->flash_id & FLASH_VENDMASK) {
+		
+	case (AMD_MANUFACT & FLASH_VENDMASK):
+		printf("AMD:   ");
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		case (AMD_ID_LV016B & FLASH_TYPEMASK):
+			printf("4x AMD29LV017B (4x16Mbit)\n");
+			break;
+		default:
+			printf("Unknown Chip Type\n");
+			goto done;
+			break;
+		}
+		
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
 	}
-	printf (" %08lX%s", info->start[i],
-		info->protect[i] ? " (RO)" : "     ");
-    }
-    printf ("\n");
-
-Done:
+	
+	
+	printf("  Size: %ld MB in %d Sectors\n",
+	       info->size >> 20, info->sector_count);
+	
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	
+	done:
 }
 
 /*-----------------------------------------------------------------------
  */
 
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
+/* this needs to be inlined, the SWTMRMMILLI register is reset by each read */
+#define __udelay(delay) \
+{	\
+	unsigned micro; \
+	unsigned milli=0; \
+	\
+	micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \
+         \
+	for (;;) { \
+		\
+		milli += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \
+		micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMICRO); \
+		\
+		if ((delay) <= (micro + (milli * 1000))) { \
+			break; \
+		} \
+	} \
+} while (0) 
+
+static u32 _amd_erase_flash(u32 addr, u32 sector)
 {
-    ulong result;
-    int iflag, prot, sect;
-    int rc = ERR_OK;
-    int chip1, chip2;
-
-    /* first look for protection bits */
-
-    if (info->flash_id == FLASH_UNKNOWN)
-	return ERR_UNKNOWN_FLASH_TYPE;
-
-    if ((s_first < 0) || (s_first > s_last)) {
-	return ERR_INVAL;
-    }
-
-    if ((info->flash_id & FLASH_VENDMASK) !=
-	(AMD_MANUFACT & FLASH_VENDMASK)) {
-	return ERR_UNKNOWN_FLASH_VENDOR;
-    }
-
-    prot = 0;
-    for (sect=s_first; sect<=s_last; ++sect) {
-	if (info->protect[sect]) {
-	    prot++;
-	}
-    }
-    if (prot)
-	return ERR_PROTECTED;
-
-    /*
-     * Disable interrupts which might cause a timeout
-     * here. Remember that our exception vectors are
-     * at address 0 in the flash, and we don't want a
-     * (ticker) exception to happen while the flash
-     * chip is in programming mode.
-     */
-    iflag = disable_interrupts();
-
-    /* Start erase on unprotected sectors */
-    for (sect = s_first; sect<=s_last && !ctrlc(); sect++)
-    {
-	printf("Erasing sector %2d ... ", sect);
-
-	/* arm simple, non interrupt dependent timer */
-	reset_timer();
-
-	if (info->protect[sect] == 0)
-	{	/* not protected */
-	    vu_long *addr = (vu_long *)(info->start[sect]);
-
-	    MEM_FLASH_ADDR1 = CMD_UNLOCK1;
-	    MEM_FLASH_ADDR2 = CMD_UNLOCK2;
-	    MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
-
-	    MEM_FLASH_ADDR1 = CMD_UNLOCK1;
-	    MEM_FLASH_ADDR2 = CMD_UNLOCK2;
-	    *addr = CMD_ERASE_CONFIRM;
-
-	    /* wait until flash is ready */
-	    chip1 = chip2 = 0;
-
-	    do
-	    {
-		result = *addr;
-
-		/* check timeout */
-		if (get_timer(0) > CFG_FLASH_ERASE_TOUT)
-		{
-		    MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
-		    chip1 = TMO;
-		    break;
+	unsigned elapsed;
+	
+	/* Issue erase */
+	*(volatile u32*)(addr + 0x5554) = 0xAAAAAAAA;
+	*(volatile u32*)(addr + 0xaaa8) = 0x55555555;
+	*(volatile u32*)(addr + 0x5554) = 0x80808080;
+	/* And one unlock */
+	*(volatile u32*)(addr + 0x5554) = 0xAAAAAAAA;
+	*(volatile u32*)(addr + 0xaaa8) = 0x55555555;
+	/* Sector erase command comes last */
+	*(volatile u32*)(addr + sector) = 0x30303030;
+	
+	elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */
+	elapsed = 0;
+	__udelay(50);
+	while (((*(volatile u32*)(addr + sector)) & 0x80808080) != 0x80808080) {
+		
+		elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI);
+		if (elapsed > ((CFG_FLASH_ERASE_TOUT/CFG_HZ) * 1000)) {
+			*(volatile u32*)(addr) = 0xf0f0f0f0;
+			return 1;			
 		}
-
-		if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE)
-			chip1 = READY;
-
-		if (!chip1 && (result & 0xFFFF) & BIT_PROGRAM_ERROR)
-			chip1 = ERR;
-
-		if (!chip2 && (result >> 16) & BIT_ERASE_DONE)
-			chip2 = READY;
-
-		if (!chip2 && (result >> 16) & BIT_PROGRAM_ERROR)
-			chip2 = ERR;
-
-	    }  while (!chip1 || !chip2);
-
-	    MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
-
-	    if (chip1 == ERR || chip2 == ERR)
-	    {
-		rc = ERR_PROG_ERROR;
-		goto outahere;
-	    }
-	    if (chip1 == TMO)
-	    {
-		rc = ERR_TIMOUT;
-		goto outahere;
-	    }
-
-	    printf("ok.\n");
 	}
-	else /* it was protected */
-	{
-	    printf("protected!\n");
+	
+	*(volatile u32*)(addr) = 0xf0f0f0f0;
+	
+	return 0;
+}
+
+extern int _amd_erase_flash_end;
+asm ("_amd_erase_flash_end:\n"
+     ".long 0\n");
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	u32 (*_erase_flash_ptr)(u32 a, u32 so);
+	int prot;
+	int sect;
+	unsigned size;
+	
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+	
+	if ((info->flash_id & FLASH_VENDMASK) == (AMD_MANUFACT & FLASH_VENDMASK)) {
+		size = (unsigned)&_amd_erase_flash_end - (unsigned)_amd_erase_flash; 
+		
+		if (size > PROBE_BUFFER_SIZE) {
+			printf("_amd_erase_flash() routine too large (%d) %p - %p\n",
+			       size, &_amd_erase_flash_end, _amd_erase_flash);
+			return 0;
+		}
+		
+		memcpy(buffer, _amd_erase_flash, size);
+		_erase_flash_ptr = (void*)buffer;
+	
+	}  else {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+	
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+		
+	
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		
+		if (info->protect[sect] == 0) { /* not protected */
+			int res;
+			int flag;
+			
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+			
+			res = _erase_flash_ptr(info->start[0], info->start[sect]-info->start[0]);
+			
+			/* re-enable interrupts if necessary */
+			if (flag) {
+				enable_interrupts();
+			}
+			
+			
+			if (res) {
+				printf("Erase timed out, sector %d\n", sect);
+				return res;
+			}
+			
+			putc('.');			
+		}		
 	}
-    }
 
-    if (ctrlc())
-      printf("User Interrupt!\n");
-
-outahere:
-    /* allow flash to settle - wait 10 ms */
-    udelay(10000);
-
-    if (iflag)
-      enable_interrupts();
-
-
-    return rc;
+	
+	return 0;
 }
 
 /*-----------------------------------------------------------------------
- * Copy memory to flash
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
  */
-
-volatile static int write_word (flash_info_t *info, ulong dest, ulong data)
+static int _amd_write_word(unsigned start, unsigned dest, unsigned data)
 {
-    vu_long *addr = (vu_long *)dest;
-    ulong result;
-    int rc = ERR_OK;
-    int iflag;
-    int chip1, chip2;
-
-    /*
-     * Check if Flash is (sufficiently) erased
-     */
-    result = *addr;
-    if ((result & data) != data)
-        return ERR_NOT_ERASED;
-
-
-    /*
-     * Disable interrupts which might cause a timeout
-     * here. Remember that our exception vectors are
-     * at address 0 in the flash, and we don't want a
-     * (ticker) exception to happen while the flash
-     * chip is in programming mode.
-     */
-    iflag = disable_interrupts();
-
-    MEM_FLASH_ADDR1 = CMD_UNLOCK1;
-    MEM_FLASH_ADDR2 = CMD_UNLOCK2;
-    MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
-    *addr = CMD_PROGRAM;
-    *addr = data;
-
-    /* arm simple, non interrupt dependent timer */
-    reset_timer();
-
-    /* wait until flash is ready */
-    chip1 = chip2 = 0;
-    do
-    {
-	result = *addr;
-
-	/* check timeout */
-	if (get_timer(0) > CFG_FLASH_ERASE_TOUT)
-	{
-	    chip1 = ERR | TMO;
-	    break;
+	volatile u32 *addr2 = (u32*)start;
+	volatile u32 *dest2 = (u32*)dest;
+	volatile u32 *data2 = (u32*)&data;
+	unsigned elapsed;
+	
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((volatile u32*)dest) & (u32)data) != (u32)data) {
+		return 2;
 	}
-	if (!chip1 && ((result & 0x80) == (data & 0x80)))
-		chip1 = READY;
-
-	if (!chip1 && ((result & 0xFFFF) & BIT_PROGRAM_ERROR))
-	{
-		result = *addr;
-
-		if ((result & 0x80) == (data & 0x80))
-			chip1 = READY;
-		else
-			chip1 = ERR;
+		
+	addr2[0x5554] = 0xAAAAAAAA;
+	addr2[0xaaa8] = 0x55555555;
+	addr2[0x5554] = 0xA0A0A0A0;
+	
+	dest2[0] = data;
+	
+	elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */
+	elapsed = 0;
+	
+	/* data polling for D7 */
+	while ((dest2[0] & 0x80808080) != (data2[0] & 0x80808080)) {
+		elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI);
+		if (elapsed > ((CFG_FLASH_WRITE_TOUT/CFG_HZ) * 1000)) {
+			addr2[0] = 0xf0f0f0f0;
+			return 1;			
+		}
 	}
 
-	if (!chip2 && ((result & (0x80 << 16)) == (data & (0x80 << 16))))
-		chip2 = READY;
-
-	if (!chip2 && ((result >> 16) & BIT_PROGRAM_ERROR))
-	{
-		result = *addr;
-
-		if ((result & (0x80 << 16)) == (data & (0x80 << 16)))
-			chip2 = READY;
-		else
-			chip2 = ERR;
-	}
-
-    }  while (!chip1 || !chip2);
-
-    *addr = CMD_READ_ARRAY;
-
-    if (chip1 == ERR || chip2 == ERR || *addr != data)
-        rc = ERR_PROG_ERROR;
-
-    if (iflag)
-      enable_interrupts();
-
-
-    return rc;
+	
+	addr2[0] = 0xf0f0f0f0;
+	
+	return 0;
 }
 
+extern int _amd_write_word_end;
+asm ("_amd_write_word_end:\n"
+     ".long 0\n");
+
+
+
+
 /*-----------------------------------------------------------------------
- * Copy memory to flash.
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 3 - Unsupported flash type
  */
 
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 {
-    ulong cp, wp, data;
-    int l;
-    int i, rc;
+	ulong cp, wp, data;
+	int i, l, rc;
+	int flag;
+	u32 (*_write_word_ptr)(unsigned start, unsigned dest, unsigned data);
+	unsigned size;
+	
+	if ((info->flash_id & FLASH_VENDMASK) == (AMD_MANUFACT & FLASH_VENDMASK)) {
+		size = (unsigned)&_amd_write_word_end - (unsigned)_amd_write_word; 
+		
+		if (size > PROBE_BUFFER_SIZE) {
+			printf("_amd_write_word() routine too large (%d) %p - %p\n",
+			       size, &_amd_write_word_end, _amd_write_word);
+			return 0;
+		}
+		
+		memcpy(buffer, _amd_write_word, size);
+		_write_word_ptr = (void*)buffer;
+	
+	} else {
+		printf ("Can't program unknown flash type - aborted\n");
+		return 3;
+	}
 
-    wp = (addr & ~3);	/* get lower word aligned address */
 
-    /*
-     * handle unaligned start bytes
-     */
-    if ((l = addr - wp) != 0) {
+	wp = (addr & ~3);	/* get lower word aligned address */
+	
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data |= (*(uchar *)cp) << (8*i);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data |= *src++ << (8*i);
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data |= (*(uchar *)cp)  << (8*i);
+		}
+		
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+		
+		rc = _write_word_ptr(info->start[0], wp, data);
+		
+		/* re-enable interrupts if necessary */
+		if (flag) {
+			enable_interrupts();
+		}
+		if (rc != 0) {
+			return rc;
+		}
+		wp += 4;
+	}
+	
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+			       
+		for (i=0; i<4; ++i) {
+			data |= *src++ << (8*i);
+		}
+		
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		rc = _write_word_ptr(info->start[0], wp, data);
+		
+		/* re-enable interrupts if necessary */
+		if (flag) {
+			enable_interrupts();
+		}
+		if (rc != 0) {
+			return rc;
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+	
+	if (cnt == 0) {
+		return 0;
+	}
+	
+	/*
+	 * handle unaligned tail bytes
+	 */
 	data = 0;
-	for (i=0, cp=wp; i<l; ++i, ++cp) {
-	    data = (data >> 8) | (*(uchar *)cp << 24);
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data |= *src++ << (8*i);
+		--cnt;
 	}
-	for (; i<4 && cnt>0; ++i) {
-	    data = (data >> 8) | (*src++ << 24);
-	    --cnt;
-	    ++cp;
-	}
-	for (; cnt==0 && i<4; ++i, ++cp) {
-	    data = (data >> 8) | (*(uchar *)cp << 24);
+	
+	for (; i<4; ++i, ++cp) {
+		data |= (*(uchar *)cp) << (8*i);
 	}
 
-	if ((rc = write_word(info, wp, data)) != 0) {
-	    return (rc);
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	rc = _write_word_ptr(info->start[0], wp, data);
+	
+	/* re-enable interrupts if necessary */
+	if (flag) {
+		enable_interrupts();
 	}
-	wp += 4;
-    }
-
-    /*
-     * handle word aligned part
-     */
-    while (cnt >= 4) {
-	data = *((vu_long*)src);
-	if ((rc = write_word(info, wp, data)) != 0) {
-	    return (rc);
-	}
-	src += 4;
-	wp  += 4;
-	cnt -= 4;
-    }
-
-    if (cnt == 0) {
-	return ERR_OK;
-    }
-
-    /*
-     * handle unaligned tail bytes
-     */
-    data = 0;
-    for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
-	data = (data >> 8) | (*src++ << 24);
-	--cnt;
-    }
-    for (; i<4; ++i, ++cp) {
-	data = (data >> 8) | (*(uchar *)cp << 24);
-    }
-
-    return write_word(info, wp, data);
+	
+	return rc;
+	
 }
+
+

board/sc520_cdp/flash_old.c

@@ -0,0 +1,458 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
+ * 
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+ulong myflush(void);
+
+
+#define SC520_MAX_FLASH_BANKS  3
+#define SC520_FLASH_BANK0_BASE 0x38000000  /* BOOTCS */
+#define SC520_FLASH_BANK1_BASE 0x30000000  /* ROMCS0 */
+#define SC520_FLASH_BANK2_BASE 0x28000000  /* ROMCS1 */
+#define SC520_FLASH_BANKSIZE   0x8000000
+
+#define AMD29LV016_SIZE        0x200000
+#define AMD29LV016_SECTORS     32
+
+flash_info_t    flash_info[SC520_MAX_FLASH_BANKS];
+
+#define CMD_READ_ARRAY		0x00F000F0
+#define CMD_UNLOCK1		0x00AA00AA
+#define CMD_UNLOCK2		0x00550055
+#define CMD_ERASE_SETUP		0x00800080
+#define CMD_ERASE_CONFIRM	0x00300030
+#define CMD_PROGRAM		0x00A000A0
+#define CMD_UNLOCK_BYPASS	0x00200020
+
+
+#define BIT_ERASE_DONE		0x00800080
+#define BIT_RDY_MASK		0x00800080
+#define BIT_PROGRAM_ERROR	0x00200020
+#define BIT_TIMEOUT		0x80000000 /* our flag */
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init(void)
+{
+	int i, j;
+	ulong size = 0;
+	
+	for (i = 0; i < SC520_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+		int sectsize = 0; 
+		if (i==0 || i==2) {
+			/* FixMe: this assumes that bank 0 and 2 
+			 * are mapped to the two 8Mb banks */
+			flash_info[i].flash_id =
+				(AMD_MANUFACT & FLASH_VENDMASK) |
+				(AMD_ID_LV016B & FLASH_TYPEMASK);
+			
+			flash_info[i].size = AMD29LV016_SIZE*4;
+			flash_info[i].sector_count = AMD29LV016_SECTORS;
+			sectsize = (AMD29LV016_SIZE*4)/AMD29LV016_SECTORS;
+		} else {
+			/* FixMe: this assumes that bank1 is unmapped 
+			 * (or mapped to the same flash bank as BOOTCS) */
+			flash_info[i].flash_id = 0;
+			flash_info[i].size = 0;
+			flash_info[i].sector_count = 0;
+			sectsize=0;
+		}
+		memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		switch (i) {
+		case 0:
+			flashbase = SC520_FLASH_BANK0_BASE;
+			break;
+		case 1:
+			flashbase = SC520_FLASH_BANK1_BASE;
+			break;
+		case 2:
+			flashbase = SC520_FLASH_BANK0_BASE;
+			break;
+		default:
+			panic("configured to many flash banks!\n");
+		}
+		
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] = sectsize;
+			flash_info[i].start[j] = flashbase + j * sectsize;
+		}
+		size += flash_info[i].size;
+	}
+	
+	/*
+	 * Protect monitor and environment sectors
+	 */
+	flash_protect(FLAG_PROTECT_SET,
+		      i386boot_start-SC520_FLASH_BANK0_BASE,
+		      i386boot_end-SC520_FLASH_BANK0_BASE,
+		      &flash_info[0]);
+	
+#ifdef CFG_ENV_ADDR
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+		      &flash_info[0]);
+#endif
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t *info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (AMD_MANUFACT & FLASH_VENDMASK):
+		printf("AMD: ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+	
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (AMD_ID_LV016B & FLASH_TYPEMASK):
+		printf("4x Amd29LV016B (16Mbit)\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		goto done;
+		break;
+	}
+	
+	printf("  Size: %ld MB in %d Sectors\n",
+	       info->size >> 20, info->sector_count);
+	
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	
+	done:
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	ulong result;
+	int iflag, prot, sect;
+	int rc = ERR_OK;
+	int chip1, chip2;
+
+	/* first look for protection bits */
+	
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return ERR_UNKNOWN_FLASH_TYPE;
+	}
+	
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+	
+	if ((info->flash_id & FLASH_VENDMASK) !=
+	    (AMD_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+	
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		return ERR_PROTECTED;
+	}
+	
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	iflag = disable_interrupts();
+	
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last && !ctrlc(); sect++) {
+		printf("Erasing sector %2d ... ", sect);
+		
+		/* arm simple, non interrupt dependent timer */
+		reset_timer();
+		
+		if (info->protect[sect] == 0) {	
+			/* not protected */
+			ulong addr = info->start[sect];
+			
+			writel(CMD_UNLOCK1, addr + 1);
+			writel(CMD_UNLOCK2, addr + 2);
+			writel(CMD_ERASE_SETUP, addr + 1);
+			
+			writel(CMD_UNLOCK1, addr + 1);
+			writel(CMD_UNLOCK2, addr + 2);
+			writel(CMD_ERASE_CONFIRM, addr);
+
+			
+			/* wait until flash is ready */
+			chip1 = chip2 = 0;
+			
+			do {
+				result = readl(addr);
+				
+				/* check timeout */
+				if (get_timer(0) > CFG_FLASH_ERASE_TOUT) {
+					writel(CMD_READ_ARRAY, addr + 1);
+					chip1 = TMO;
+					break;
+				}
+				
+				if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE) {
+					chip1 = READY;
+				}
+				
+				if (!chip1 && (result & 0xFFFF) & BIT_PROGRAM_ERROR) {
+					chip1 = ERR;
+				}
+				
+				if (!chip2 && (result >> 16) & BIT_ERASE_DONE) {
+					chip2 = READY;
+				}
+				
+				if (!chip2 && (result >> 16) & BIT_PROGRAM_ERROR) {
+					chip2 = ERR;
+				}
+				
+			}  while (!chip1 || !chip2);
+			
+			writel(CMD_READ_ARRAY, addr + 1);
+			
+			if (chip1 == ERR || chip2 == ERR) {
+				rc = ERR_PROG_ERROR;
+				goto outahere;
+			}
+			
+			if (chip1 == TMO) {
+				rc = ERR_TIMOUT;
+				goto outahere;
+			}
+			
+			printf("ok.\n");
+		} else { /* it was protected */
+			
+			printf("protected!\n");
+		}
+	}
+	
+	if (ctrlc()) {
+		printf("User Interrupt!\n");
+	}
+
+outahere:
+	/* allow flash to settle - wait 10 ms */
+	udelay(10000);
+	
+	if (iflag) {
+		enable_interrupts();
+	}
+	
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+volatile static int write_word(flash_info_t *info, ulong dest, ulong data)
+{
+	ulong addr = dest;
+	ulong result;
+	int rc = ERR_OK;
+	int iflag;
+	int chip1, chip2;
+	
+	/*
+	 * Check if Flash is (sufficiently) erased
+	 */
+	result = readl(addr);
+	if ((result & data) != data) {
+		return ERR_NOT_ERASED;
+	}
+	
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	iflag = disable_interrupts();
+
+	writel(CMD_UNLOCK1, addr + 1);
+	writel(CMD_UNLOCK2, addr + 2);
+	writel(CMD_UNLOCK_BYPASS, addr + 1);
+	writel(addr, CMD_PROGRAM);
+	writel(addr, data);
+	
+	/* arm simple, non interrupt dependent timer */
+	reset_timer();
+	
+	/* wait until flash is ready */
+	chip1 = chip2 = 0;
+	do {
+		result = readl(addr);
+		
+		/* check timeout */
+		if (get_timer(0) > CFG_FLASH_ERASE_TOUT) {
+			chip1 = ERR | TMO;
+			break;
+		}
+		
+		if (!chip1 && ((result & 0x80) == (data & 0x80))) {
+			chip1 = READY;
+		}
+		
+		if (!chip1 && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) {
+			result = readl(addr);
+			
+			if ((result & 0x80) == (data & 0x80)) {
+				chip1 = READY;
+			} else {
+				chip1 = ERR;
+			}
+		}
+		
+		if (!chip2 && ((result & (0x80 << 16)) == (data & (0x80 << 16)))) {
+			chip2 = READY;
+		}
+		
+		if (!chip2 && ((result >> 16) & BIT_PROGRAM_ERROR)) {
+			result = readl(addr);
+			
+			if ((result & (0x80 << 16)) == (data & (0x80 << 16))) {
+				chip2 = READY;
+			} else {
+				chip2 = ERR;
+			}
+		}
+		
+	}  while (!chip1 || !chip2);
+	
+	writel(CMD_READ_ARRAY, addr);
+	
+	if (chip1 == ERR || chip2 == ERR || readl(addr) != data) {
+		rc = ERR_PROG_ERROR;
+	}
+	
+	if (iflag) {
+		enable_interrupts();
+	}
+	
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int l;
+	int i, rc;
+	
+	wp = (addr & ~3);	/* get lower word aligned address */
+	
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *)cp << 24);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data >> 8) | (*src++ << 24);
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *)cp << 24);
+		}
+		
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return rc;
+		}
+		wp += 4;
+	}
+	
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = *((vu_long*)src);
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return rc;
+		}
+		src += 4;
+		wp  += 4;
+		cnt -= 4;
+	}
+	
+	if (cnt == 0) {
+		return ERR_OK;
+	}
+	
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 24);
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *)cp << 24);
+	}
+	
+	return write_word(info, wp, data);
+}

board/sc520_cdp/sc520_cdp.c

@@ -1,4 +1,5 @@
 /*
+ * 
  * (C) Copyright 2002
  * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
  *
@@ -24,109 +25,162 @@
 #include <common.h>
 #include <pci.h>
 #include <asm/io.h>
+#include <asm/pci.h>
 #include <asm/ic/sc520.h>
 #include <asm/ic/ali512x.h>
+#include <ssi.h>
+
+#undef SC520_CDP_DEBUG
+
+#ifdef	SC520_CDP_DEBUG
+#define	PRINTF(fmt,args...)	printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
 
 /* ------------------------------------------------------------------------- */
 
+	
+/* 
+ * Theory:
+ * We first set up all IRQs to be non-pci, edge triggered,
+ * when we later enumerate the pci bus and pci_sc520_fixup_irq() gets 
+ * called we reallocate irqs to the pci bus with sc520_pci_set_irq()
+ * as needed. Whe choose the irqs to gram from a configurable list
+ * inside pci_sc520_fixup_irq() (If this list contains stupid irq's
+ * such as 0 thngas will not work)
+ */
+
 static void irq_init(void)
 {
-	
 	/* disable global interrupt mode */
 	write_mmcr_byte(SC520_PICICR, 0x40); 
 	
-	/* set irq0-7 to edge */
+	/* set all irqs to edge */
 	write_mmcr_byte(SC520_MPICMODE, 0x00);
-	
-	/* set irq9-12 to level, all the other (8, 13-15) are edge */
-	write_mmcr_byte(SC520_SL1PICMODE, 0x1e);
-	
-	/* set irq16-24 (unused slave pic2) to level */
-	write_mmcr_byte(SC520_SL2PICMODE, 0xff);
+	write_mmcr_byte(SC520_SL1PICMODE, 0x00);
+	write_mmcr_byte(SC520_SL2PICMODE, 0x00);
 	
 	/* active low polarity on PIC interrupt pins, 
-	   active high polarity on all other irq pins */
-	write_mmcr_word(SC520_INTPINPOL, 0);
+	 *  active high polarity on all other irq pins */
+	write_mmcr_word(SC520_INTPINPOL, 0x0000);
 
 	/* set irq number mapping */
-	write_mmcr_byte(SC520_GPTMR0MAP,0);            /* disable GP timer 0 INT */       
-	write_mmcr_byte(SC520_GPTMR1MAP,0);            /* disable GP timer 1 INT */
-	write_mmcr_byte(SC520_GPTMR2MAP,0);            /* disable GP timer 2 INT */
-	write_mmcr_byte(SC520_PIT0MAP,0x1);            /* Set PIT timer 0 INT to IRQ0 */ 
-	write_mmcr_byte(SC520_PIT1MAP,0);              /* diable PIT timer 1 INT */
-	write_mmcr_byte(SC520_PIT2MAP,0);              /* diable PIT timer 2 INT */
-	write_mmcr_byte(SC520_PCIINTAMAP,0x4);         /* Set PCI INT A to IRQ9 */
-	write_mmcr_byte(SC520_PCIINTBMAP,0x5);         /* Set PCI INT B to IRQ10 */
-	write_mmcr_byte(SC520_PCIINTCMAP,0x6);         /* Set PCI INT C to IRQ11 */
-	write_mmcr_byte(SC520_PCIINTDMAP,0x7);         /* Set PCI INT D to IRQ12 */
-	write_mmcr_byte(SC520_DMABCINTMAP,0);          /* disable DMA INT */ 
-	write_mmcr_byte(SC520_SSIMAP,0);               /* disable Synchronius serial INT */
-	write_mmcr_byte(SC520_WDTMAP,0);               /* disable Watchdor INT */
-	write_mmcr_byte(SC520_RTCMAP,0x3);             /* Set RTC int to 8 */
-	write_mmcr_byte(SC520_WPVMAP,0);               /* disable write protect INT */
-	write_mmcr_byte(SC520_ICEMAP,0x2);             /* Set ICE Debug Serielport INT to IRQ1 */
-	write_mmcr_byte(SC520_FERRMAP,0x8);            /* Set FP error INT to IRQ13 */
-	write_mmcr_byte(SC520_GP0IMAP,6);              /* Set GPIRQ0 (ISA IRQ2) to IRQ9 */
-	write_mmcr_byte(SC520_GP1IMAP,2);              /* Set GPIRQ1 (SIO IRQ1) to IRQ1 */
-	write_mmcr_byte(SC520_GP2IMAP,7);              /* Set GPIRQ2 (ISA IRQ12) to IRQ12 */
+	write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED);   /* disable GP timer 0 INT */       
+	write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED);   /* disable GP timer 1 INT */
+	write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED);   /* disable GP timer 2 INT */
+	write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0);             /* Set PIT timer 0 INT to IRQ0 */ 
+	write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED);     /* disable PIT timer 1 INT */
+	write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED);     /* disable PIT timer 2 INT */
+	write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED);  /* disable PCI INT A */
+	write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED);  /* disable PCI INT B */
+	write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED);  /* disable PCI INT C */
+	write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED);  /* disable PCI INT D */
+	write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */ 
+	write_mmcr_byte(SC520_SSIMAP, SC520_IRQ_DISABLED);      /* disable Synchronius serial INT */
+	write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED);      /* disable Watchdog INT */
+	write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8);              /* Set RTC int to 8 */
+	write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED);      /* disable write protect INT */
+	write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1);              /* Set ICE Debug Serielport INT to IRQ1 */
+	write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13);             /* Set FP error INT to IRQ13 */
 	
 	if (CFG_USE_SIO_UART) {
-		write_mmcr_byte(SC520_UART1MAP,0);     /* disable internal UART1 INT */
-		write_mmcr_byte(SC520_UART2MAP,0);     /* disable internal UART2 INT */
-		write_mmcr_byte(SC520_GP3IMAP,11);     /* Set GPIRQ3 (ISA IRQ3) to IRQ3 */ 
-		write_mmcr_byte(SC520_GP4IMAP,12);     /* Set GPIRQ4 (ISA IRQ4) to IRQ4 */
+		write_mmcr_byte(SC520_UART1MAP, SC520_IRQ_DISABLED); /* disable internal UART1 INT */
+		write_mmcr_byte(SC520_UART2MAP, SC520_IRQ_DISABLED); /* disable internal UART2 INT */
+		write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ3);          /* Set GPIRQ3 (ISA IRQ3) to IRQ3 */ 
+		write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ4);          /* Set GPIRQ4 (ISA IRQ4) to IRQ4 */
 	} else {
-		write_mmcr_byte(SC520_UART1MAP,12);    /* Set internal UART2 INT to IRQ4 */
-		write_mmcr_byte(SC520_UART2MAP,11);    /* Set internal UART2 INT to IRQ3 */
-		write_mmcr_byte(SC520_GP3IMAP,0);      /* disable GPIRQ3 (ISA IRQ3) */ 
-		write_mmcr_byte(SC520_GP4IMAP,0);      /* disable GPIRQ4 (ISA IRQ4) */
+		write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4);         /* Set internal UART2 INT to IRQ4 */
+		write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3);         /* Set internal UART2 INT to IRQ3 */
+		write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ_DISABLED);  /* disable GPIRQ3 (ISA IRQ3) */ 
+		write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED);  /* disable GPIRQ4 (ISA IRQ4) */
 	}
 	
-	write_mmcr_byte(SC520_GP5IMAP,13);             /* Set GPIRQ5 (ISA IRQ5) to IRQ5 */
-	write_mmcr_byte(SC520_GP6IMAP,21);             /* Set GPIRQ6 (ISA IRQ6) to IRQ6 */
-	write_mmcr_byte(SC520_GP7IMAP,22);             /* Set GPIRQ7 (ISA IRQ7) to IRQ7 */
-	write_mmcr_byte(SC520_GP8IMAP,3);              /* Set GPIRQ8 (SIO IRQ8) to IRQ8 */
-	write_mmcr_byte(SC520_GP9IMAP,4);              /* Set GPIRQ9 (ISA IRQ9) to IRQ9 */
-	write_mmcr_byte(SC520_GP10IMAP,9);             /* Set GPIRQ10 (ISA IRQ10) to IRQ10 */          
-	write_mmcr_word(SC520_PCIHOSTMAP,0x11f);       /* Map PCI hostbridge INT to NMI */
-	write_mmcr_word(SC520_ECCMAP,0x100);           /* Map SDRAM ECC failure INT to NMI */
+	write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ1);             /* Set GPIRQ1 (SIO IRQ1) to IRQ1 */
+	write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ5);             /* Set GPIRQ5 (ISA IRQ5) to IRQ5 */
+	write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ6);             /* Set GPIRQ6 (ISA IRQ6) to IRQ6 */
+	write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ7);             /* Set GPIRQ7 (ISA IRQ7) to IRQ7 */
+	write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ8);             /* Set GPIRQ8 (SIO IRQ8) to IRQ8 */
+	write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ9);             /* Set GPIRQ9 (ISA IRQ2) to IRQ9 */
+	write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ11);            /* Set GPIRQ0 (ISA IRQ11) to IRQ10 */
+	write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ12);            /* Set GPIRQ2 (ISA IRQ12) to IRQ12 */
+	write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ14);            /* Set GPIRQ10 (ISA IRQ14) to IRQ14 */          
+	
+	write_mmcr_word(SC520_PCIHOSTMAP, 0x11f);                /* Map PCI hostbridge INT to NMI */
+	write_mmcr_word(SC520_ECCMAP, 0x100);                    /* Map SDRAM ECC failure INT to NMI */
  
 }
 
+	
 /* PCI stuff */
 static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 {
-	char pin;
-	int irq;
+	/* a configurable lists of irqs to steal
+	 * when we need one (a board with more pci interrupt pins
+	 * would use a larger table */
+	static int irq_list[] = {
+		CFG_FIRST_PCI_IRQ,
+		CFG_SECOND_PCI_IRQ,
+		CFG_THIRD_PCI_IRQ,
+		CFG_FORTH_PCI_IRQ
+	};
+	static int next_irq_index=0;
+	
+	char tmp_pin;	
+	int pin;
+	
+	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
+	pin = tmp_pin;
+	
+	pin-=1; /* pci config space use 1-based numbering */
+	if (-1 == pin) {
+		return; /* device use no irq */
+	}
 	
 	
-	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
-	irq = pin-1;
-	
+       
+	/* map device number +  pin to a pin on the sc520 */
 	switch (PCI_DEV(dev)) {
 	case 20:
+		pin+=SC520_PCI_INTA;
 		break;
+		
 	case 19:
-		irq+=1;
+		pin+=SC520_PCI_INTB;
 		break;
+		
 	case 18:
-		irq+=2;
+		pin+=SC520_PCI_INTC;
 		break;
+		
 	case 17:
-		irq+=3;
+		pin+=SC520_PCI_INTD;
 		break;
+		
 	default: 
 		return;
 	}
 	
-	irq&=3; /* wrap around */
-	irq+=9; /* lowest IRQ is 9 */
+	pin&=3; /* wrap around */
 	
-	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, irq);
-#if 0	
-	printf("fixup_irq: device %d pin %c irq %d\n", 
-	       PCI_DEV(dev), 'A' + pin -1, irq);
-#endif
+	if (sc520_pci_ints[pin] == -1) {
+		/* re-route one interrupt for us */		
+		if (next_irq_index > 3) {
+			return;
+		}
+		if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) { 
+			return;
+		}
+		next_irq_index++;
+	}
+
+	
+	if (-1 != sc520_pci_ints[pin]) {
+		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 
+					   sc520_pci_ints[pin]);
+	}
+	PRINTF("fixup_irq: device %d pin %c irq %d\n", 
+	       PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
 }
  
 static struct pci_controller sc520_cdp_hose = {
@@ -162,8 +216,8 @@ void setup_ali_sio(int uart_primary)
 	
 	/* SSI chip select pins */
 	ali512x_cio_function(14, 0, 0, 0);  /* SSI_CS */
-	ali512x_cio_function(15, 0, 0, 0);  /* SSI_MV */					     
-	ali512x_cio_function(16, 0, 1, 0);  /* SSI_SPI# (inverted) */
+	ali512x_cio_function(15, 0, 0, 0);  /* SSI_MV */ 
+	ali512x_cio_function(16, 0, 0, 0);  /* SSI_SPI# */
 
 	/* Board REV pins */
 	ali512x_cio_function(20, 0, 0, 1);
@@ -202,6 +256,7 @@ static void bus_init(void)
 	 * we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */ 
 	
 		
+	
 	/* SRAM = GPCS3 128k @ d0000-effff*/
 	write_mmcr_long(SC520_PAR2,  0x4e00400d);		
 	
@@ -219,13 +274,15 @@ static void bus_init(void)
 	/* 680 LEDS */
 	write_mmcr_long(SC520_PAR15, 0x30000640);		
 	
+	write_mmcr_byte(SC520_ADDDECCTL, 0);
+	
 	asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */	
 
 	if (CFG_USE_SIO_UART) {
 		write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) | UART2_DIS|UART1_DIS);	
 		setup_ali_sio(1);
 	} else {
-		write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS));	
+		write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS));
 		setup_ali_sio(0);
 		silence_uart(0x3e8);
 		silence_uart(0x2e8);
@@ -233,8 +290,193 @@ static void bus_init(void)
 
 }
 
+/* GPCS usage
+ * GPCS0       PIO27 (NMI)
+ * GPCS1       ROMCS1
+ * GPCS2       ROMCS2
+ * GPCS3       SRAMCS       PAR2
+ * GPCS4       unused       PAR3
+ * GPCS5       unused       PAR4
+ * GPCS6       IDE
+ * GPCS7       IDE
+ */
 
 
+/* par usage:
+ * PAR0   legacy_video
+ * PAR1   PCI ROM mapping
+ * PAR2   SRAM
+ * PAR3   IDE
+ * PAR4   IDE
+ * PAR5   legacy_video
+ * PAR6   legacy_video
+ * PAR7   legacy_video
+ * PAR8   legacy_video
+ * PAR9   legacy_video
+ * PAR10  legacy_video
+ * PAR11  ISAROM
+ * PAR12  BOOTCS
+ * PAR13  ROMCS1
+ * PAR14  ROMCS2
+ * PAR15  Port 0x680 LED display
+ */
+
+/* 
+ * This function should map a chunk of size bytes
+ * of the system address space to the ISA bus
+ * 
+ * The function will return the memory address
+ * as seen by the host (which may very will be the
+ * same as the bus address)
+ */
+u32 isa_map_rom(u32 bus_addr, int size) 
+{
+	u32 par;
+	
+	PRINTF("isa_map_rom asked to map %d bytes at %x\n", 
+	       size, bus_addr);
+	
+	par = size;
+	if (par < 0x80000) {
+		par = 0x80000;
+	}
+	par >>= 12;
+	par--;
+	par&=0x7f;
+	par <<= 18;
+	par |= (bus_addr>>12);
+	par |= 0x50000000;
+	
+	PRINTF ("setting PAR11 to %x\n", par);
+	
+	/* Map rom 0x10000 with PAR1 */
+	write_mmcr_long(SC520_PAR11,  par);
+	
+	return bus_addr;
+}
+
+/*
+ * this function removed any mapping created
+ * with pci_get_rom_window()
+ */
+void isa_unmap_rom(u32 addr)
+{
+	PRINTF("isa_unmap_rom asked to unmap %x", addr);
+	if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) {
+		write_mmcr_long(SC520_PAR11, 0);
+		PRINTF(" done\n");
+		return;
+	}
+	PRINTF(" not ours\n");
+}
+
+#ifdef CONFIG_PCI
+#define PCI_ROM_TEMP_SPACE 0x10000
+/* 
+ * This function should map a chunk of size bytes
+ * of the system address space to the PCI bus,
+ * suitable to map PCI ROMS (bus address < 16M)
+ * the function will return the host memory address
+ * which should be converted into a bus address
+ * before used to configure the PCI rom address 
+ * decoder
+ */
+u32 pci_get_rom_window(struct pci_controller *hose, int size) 
+{
+	u32 par;
+	
+	par = size;
+	if (par < 0x80000) {
+		par = 0x80000;
+	}
+	par >>= 16;
+	par--;
+	par&=0x7ff;
+	par <<= 14;
+	par |= (PCI_ROM_TEMP_SPACE>>16);
+	par |= 0x72000000;
+	
+	PRINTF ("setting PAR1 to %x\n", par);
+	
+	/* Map rom 0x10000 with PAR1 */
+	write_mmcr_long(SC520_PAR1,  par);
+	
+	return PCI_ROM_TEMP_SPACE;
+}
+
+/*
+ * this function removed any mapping created
+ * with pci_get_rom_window()
+ */
+void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
+{
+	PRINTF("pci_remove_rom_window: %x", addr);
+	if (addr == PCI_ROM_TEMP_SPACE) {
+		write_mmcr_long(SC520_PAR1, 0);
+		PRINTF(" done\n");
+		return;
+	}
+	PRINTF(" not ours\n");
+	
+}
+
+/*
+ * This function is called in order to provide acces to the
+ * legacy video I/O ports on the PCI bus. 
+ * After this function accesses to I/O ports 0x3b0-0x3bb and 
+ * 0x3c0-0x3df shuld result in transactions on the PCI bus.
+ * 
+ */
+int pci_enable_legacy_video_ports(struct pci_controller *hose)
+{
+	/* Map video memory to 0xa0000*/
+	write_mmcr_long(SC520_PAR0,  0x7200400a);
+	
+	/* forward all I/O accesses to PCI */
+	write_mmcr_byte(SC520_ADDDECCTL, 
+			read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI);	
+	
+	
+	/* so we map away all io ports to pci (only way to access pci io
+	 * below 0x400. But then we have to map back the portions that we dont
+	 * use so that the generate cycles on the GPIO bus where the sio and
+	 * ISA slots are connected, this requre the use of several PAR registers 
+	 */
+	
+	/* bring 0x100 - 0x1ef back to ISA using PAR5 */
+	write_mmcr_long(SC520_PAR5, 0x30ef0100);		
+	
+	/* IDE use 1f0-1f7 */
+	
+	/* bring 0x1f8 - 0x2f7 back to ISA using PAR6 */
+	write_mmcr_long(SC520_PAR6, 0x30ff01f8);		
+	
+	/* com2 use 2f8-2ff */
+	
+	/* bring 0x300 - 0x3af back to ISA using PAR7 */
+	write_mmcr_long(SC520_PAR7, 0x30af0300);		
+	
+	/* vga use 3b0-3bb */
+	
+	/* bring 0x3bc - 0x3bf back to ISA using PAR8 */
+	write_mmcr_long(SC520_PAR8, 0x300303bc);		
+	
+	/* vga use 3c0-3df */
+	
+	/* bring 0x3e0 - 0x3f5 back to ISA using PAR9 */
+	write_mmcr_long(SC520_PAR9, 0x301503e0);		
+	
+	/* ide use 3f6 */
+	
+	/* bring 0x3f7  back to ISA using PAR10 */
+	write_mmcr_long(SC520_PAR10, 0x300003f7);		
+	
+	/* com1 use 3f8-3ff */		
+
+	return 0;
+}
+#endif
+
 /*
  * Miscelaneous platform dependent initialisations
  */
@@ -252,7 +494,6 @@ int board_init(void)
 		
 	/* enter debug mode after next reset (only if jumper is also set) */
 	write_mmcr_byte(SC520_RESCFG, 0x08);
-	
 	/* configure the software timer to 33.333MHz */
 	write_mmcr_byte(SC520_SWTMRCFG, 0);
 	gd->bus_clk = 33333000;
@@ -288,3 +529,87 @@ int last_stage_init(void)
 	
 	return 0;
 }
+
+
+
+void ssi_chip_select(int dev) 
+{
+	
+	/* Spunk board: SPI EEPROM is active-low, MW EEPROM and AUX are active high */
+	switch (dev) {
+	case 1: /* SPI EEPROM */
+		ali512x_cio_out(16, 0);
+		break;
+		
+	case 2: /* MW EEPROM */
+		ali512x_cio_out(15, 1);
+		break;
+		
+	case 3: /* AUX */				
+		ali512x_cio_out(14, 1);
+		break;
+		
+	case 0:
+		ali512x_cio_out(16, 1);
+		ali512x_cio_out(15, 0);
+		ali512x_cio_out(14, 0);
+		break;
+		
+	default:
+		printf("Illegal SSI device requested: %d\n", dev);
+	}
+}
+
+
+void spi_init_f(void) 
+{
+#ifdef CONFIG_SC520_CDP_USE_SPI
+	spi_eeprom_probe(1); 
+#endif	
+#ifdef CONFIG_SC520_CDP_USE_MW
+	mw_eeprom_probe(2);
+#endif		
+}
+
+ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len) 
+{
+	int offset;
+	int i;
+	ssize_t res;
+	
+	offset = 0;
+	for (i=0;i<alen;i++) {
+		offset <<= 8;
+		offset |= addr[i];
+	}
+ 
+#ifdef CONFIG_SC520_CDP_USE_SPI
+	res = spi_eeprom_read(1, offset, buffer, len); 
+#endif	
+#ifdef CONFIG_SC520_CDP_USE_MW
+	res = mw_eeprom_read(2, offset, buffer, len);
+#endif	
+	return res;
+}
+
+ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len) 
+{
+	int offset;
+	int i;
+	ssize_t res;
+	
+	offset = 0;
+	for (i=0;i<alen;i++) {
+		offset <<= 8;
+		offset |= addr[i];
+	}
+		
+#ifdef CONFIG_SC520_CDP_USE_SPI
+	res = spi_eeprom_write(1, offset, buffer, len);
+#endif	
+#ifdef CONFIG_SC520_CDP_USE_MW
+	res = mw_eeprom_write(2, offset, buffer, len);
+#endif	
+	return res;
+}
+

board/sc520_cdp/sc520_cdp_asm16.S

@@ -60,3 +60,25 @@ board_init16:
 	/* the return address is tored in bp */
 	jmp	*%bp
 	
+
+.section .bios, "ax"
+.code16
+.globl realmode_reset
+realmode_reset:
+	/* Alias MMCR to 0xdf000 */
+	movw	$0xfffc, %dx
+	movl	$0x800df0cb, %eax	
+	outl	%eax, %dx		
+	
+	/* Set ds to point to MMCR alias */
+	movw	$0xdf00, %ax		
+	movw	%ax, %ds		 
+		
+	/* issue software reset thorugh MMCR */
+	movl    $0xd72, %edi
+        movb	$0x01, %al
+        movb	%al, (%di)		
+
+1:	hlt
+	jmp	1
+	

board/sc520_cdp/u-boot.lds

@@ -27,7 +27,7 @@ ENTRY(_start)
 
 SECTIONS
 {	
-	. = 0x387e0000;                     /* Where bootcode in the flash is mapped */
+	. = 0x387c0000;                     /* Where bootcode in the flash is mapped */
 	.text  : { *(.text); }
 	
         . = ALIGN(4);

board/sc520_spunk/Makefile

@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2002
+# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= sc520_spunk.o flash.o
+SOBJS	:= sc520_spunk_asm.o sc520_spunk_asm16.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/sc520_spunk/config.mk

@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2002
+# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+
+TEXT_BASE = 0x387c0000

board/sc520_spunk/flash.c

@@ -0,0 +1,813 @@
+/*
+ * (C) Copyright 2002, 2003
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
+ * 
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <pci.h>
+#include <asm/ic/sc520.h>
+
+#define PROBE_BUFFER_SIZE 1024
+static unsigned char buffer[PROBE_BUFFER_SIZE];
+
+
+#define SC520_MAX_FLASH_BANKS  1
+#define SC520_FLASH_BANK0_BASE 0x38000000  /* BOOTCS */
+#define SC520_FLASH_BANKSIZE   0x8000000
+
+#define A29LV641DH_SIZE        0x800000
+#define A29LV641DH_SECTORS     128
+
+#define A29LV641MH_SIZE        0x800000
+#define A29LV641MH_SECTORS     128
+
+#define I28F320J3A_SIZE        0x400000
+#define I28F320J3A_SECTORS     32
+
+#define I28F640J3A_SIZE        0x800000
+#define I28F640J3A_SECTORS     64
+
+#define I28F128J3A_SIZE        0x1000000
+#define I28F128J3A_SECTORS     128
+
+flash_info_t    flash_info[SC520_MAX_FLASH_BANKS];
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+/*-----------------------------------------------------------------------
+ */
+
+
+static u32 _probe_flash(u32 addr, u32 bw, int il)
+{
+	u32 result=0;
+	
+	/* First do an unlock cycle for the benefit of
+	 * devices that need it */
+	
+	switch (bw) {
+		
+	case 1:
+		*(volatile u8*)(addr+0x5555) = 0xaa;
+		*(volatile u8*)(addr+0x2aaa) = 0x55;
+		*(volatile u8*)(addr+0x5555) = 0x90;
+		
+		/* Read vendor */
+		result = *(volatile u8*)addr;
+		result <<= 16;
+		
+		/* Read device */
+		result |= *(volatile u8*)(addr+2);
+		
+		/* Return device to data mode */
+		*(volatile u8*)addr = 0xff;
+		*(volatile u8*)(addr+0x5555), 0xf0;  
+		break;
+		
+	case 2:
+		*(volatile u16*)(addr+0xaaaa) = 0xaaaa;
+		*(volatile u16*)(addr+0x5554) = 0x5555;
+		
+		/* Issue identification command */
+		if (il == 2) {
+			*(volatile u16*)(addr+0xaaaa) = 0x9090;
+			
+			/* Read vendor */
+			result = *(volatile u8*)addr;
+			result <<= 16;
+			
+			/* Read device */
+			result |= *(volatile u8*)(addr+2);
+			
+			/* Return device to data mode */
+			*(volatile u16*)addr =  0xffff;
+			*(volatile u16*)(addr+0xaaaa), 0xf0f0;  
+			
+		} else {
+			*(volatile u8*)(addr+0xaaaa) = 0x90;
+			/* Read vendor */
+			result = *(volatile u16*)addr;
+			result <<= 16;
+			
+			/* Read device */
+			result |= *(volatile u16*)(addr+2);
+			
+			/* Return device to data mode */
+			*(volatile u8*)addr = 0xff;
+			*(volatile u8*)(addr+0xaaaa), 0xf0;  			
+		}
+		
+		break;
+		
+	 case 4:
+		*(volatile u32*)(addr+0x5554) = 0xaaaaaaaa;
+		*(volatile u32*)(addr+0xaaa8) = 0x55555555;
+		
+		switch (il) {
+		case 1:
+			/* Issue identification command */
+			*(volatile u8*)(addr+0x5554) = 0x90;
+			
+			/* Read vendor */
+			result = *(volatile u16*)addr;
+			result <<= 16;
+		
+			/* Read device */
+			result |= *(volatile u16*)(addr+4);
+			
+			/* Return device to data mode */
+			*(volatile u8*)addr =  0xff;
+			*(volatile u8*)(addr+0x5554), 0xf0;  
+			break;
+			
+		case 2:
+			/* Issue identification command */
+			*(volatile u32*)(addr + 0x5554) = 0x00900090;
+			
+			/* Read vendor */
+			result = *(volatile u16*)addr;
+			result <<= 16;
+			
+			/* Read device */
+			result |= *(volatile u16*)(addr+4);
+			
+			/* Return device to data mode */
+			*(volatile u32*)addr =  0x00ff00ff;
+			*(volatile u32*)(addr+0x5554), 0x00f000f0;  
+			break;
+			
+		case 4:
+			/* Issue identification command */
+			*(volatile u32*)(addr+0x5554) = 0x90909090;
+			
+			/* Read vendor */
+			result = *(volatile u8*)addr;
+			result <<= 16;
+			
+			/* Read device */
+			result |= *(volatile u8*)(addr+4);
+			
+			/* Return device to data mode */
+			*(volatile u32*)addr =  0xffffffff;
+			*(volatile u32*)(addr+0x5554), 0xf0f0f0f0; 
+			break;
+		}
+		break;
+	}
+	
+	
+	
+	return result;
+}
+
+extern int _probe_flash_end;
+asm ("_probe_flash_end:\n"
+     ".long 0\n");
+
+static int identify_flash(unsigned address, int width)
+{
+	int is;	
+	int device;
+	int vendor;	
+	int size;
+	unsigned res;
+	
+	u32 (*_probe_flash_ptr)(u32 a, u32 bw, int il);
+	
+	size = (unsigned)&_probe_flash_end - (unsigned)_probe_flash; 
+	
+	if (size > PROBE_BUFFER_SIZE) {
+		printf("_probe_flash() routine too large (%d) %p - %p\n",
+		       size, &_probe_flash_end, _probe_flash);
+		return 0;
+	}
+	
+	memcpy(buffer, _probe_flash, size);
+	_probe_flash_ptr = (void*)buffer;
+	
+	is = disable_interrupts();
+	res = _probe_flash_ptr(address, width, 1);
+	if (is) {
+		enable_interrupts();
+	}
+	
+	
+        vendor = res >> 16;
+	device = res & 0xffff;
+	
+		
+	return res;
+}
+
+ulong flash_init(void)
+{
+	int i, j;
+	ulong size = 0;
+	
+	for (i = 0; i < SC520_MAX_FLASH_BANKS; i++) {
+		unsigned id;
+		ulong flashbase = 0;
+		int sectsize = 0; 
+		
+		memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		switch (i) {
+		case 0:
+			flashbase = SC520_FLASH_BANK0_BASE;
+			break;
+		default:
+			panic("configured to many flash banks!\n");
+		}
+		
+		id = identify_flash(flashbase, 2);
+		switch (id) {
+		case 0x000122d7:
+			/* 29LV641DH */
+			flash_info[i].flash_id =
+				(AMD_MANUFACT & FLASH_VENDMASK) |
+				(AMD_ID_LV640U & FLASH_TYPEMASK);
+			
+			flash_info[i].size = A29LV641DH_SIZE;
+			flash_info[i].sector_count = A29LV641DH_SECTORS;
+			sectsize = A29LV641DH_SIZE/A29LV641DH_SECTORS;
+			printf("Bank %d: AMD 29LV641DH\n", i);
+			break;
+			
+		case 0x0001227E:
+			/* 29LV641MH */
+			flash_info[i].flash_id =
+				(AMD_MANUFACT & FLASH_VENDMASK) |
+				(AMD_ID_DL640 & FLASH_TYPEMASK);
+			
+			flash_info[i].size = A29LV641MH_SIZE;
+			flash_info[i].sector_count = A29LV641MH_SECTORS;
+			sectsize = A29LV641MH_SIZE/A29LV641MH_SECTORS;
+			printf("Bank %d: AMD 29LV641MH\n", i);
+			break;
+			
+		case 0x00890016:
+			/* 28F320J3A */
+			flash_info[i].flash_id =
+				(INTEL_MANUFACT & FLASH_VENDMASK) |
+				(INTEL_ID_28F320J3A & FLASH_TYPEMASK);
+			
+			flash_info[i].size = I28F320J3A_SIZE;
+			flash_info[i].sector_count = I28F320J3A_SECTORS;
+			sectsize = I28F320J3A_SIZE/I28F320J3A_SECTORS;
+			printf("Bank %d: Intel 28F320J3A\n", i);
+			break;
+			
+		case 0x00890017:
+			/* 28F640J3A */
+			flash_info[i].flash_id =
+				(INTEL_MANUFACT & FLASH_VENDMASK) |
+				(INTEL_ID_28F640J3A & FLASH_TYPEMASK);
+			
+			flash_info[i].size = I28F640J3A_SIZE;
+			flash_info[i].sector_count = I28F640J3A_SECTORS;
+			sectsize = I28F640J3A_SIZE/I28F640J3A_SECTORS;
+			printf("Bank %d: Intel 28F640J3A\n", i);
+			break;
+			
+		case 0x00890018:
+			/* 28F128J3A */
+			flash_info[i].flash_id =
+				(INTEL_MANUFACT & FLASH_VENDMASK) |
+				(INTEL_ID_28F128J3A & FLASH_TYPEMASK);
+			
+			flash_info[i].size = I28F128J3A_SIZE;
+			flash_info[i].sector_count = I28F128J3A_SECTORS;
+			sectsize = I28F128J3A_SIZE/I28F128J3A_SECTORS;
+			printf("Bank %d: Intel 28F128J3A\n", i);
+			break;
+			
+		default:
+			printf("Bank %d have unknown flash %08x\n", i, id);
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+			continue;
+		}
+		
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] = flashbase + j * sectsize;
+		}
+		size += flash_info[i].size;
+		
+		flash_protect(FLAG_PROTECT_CLEAR,
+			      flash_info[i].start[0],
+			       flash_info[i].start[0] + flash_info[i].size - 1,
+			      &flash_info[i]);
+	}
+	
+	/*
+	 * Protect monitor and environment sectors
+	 */
+	flash_protect(FLAG_PROTECT_SET,
+		      i386boot_start,
+		      i386boot_end,
+		      &flash_info[0]);
+#ifdef CFG_ENV_ADDR
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+		      &flash_info[0]);
+#endif	
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t *info)
+{
+	int i;
+	
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (INTEL_MANUFACT & FLASH_VENDMASK):
+		printf("INTEL: ");
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		case (INTEL_ID_28F320J3A & FLASH_TYPEMASK):
+			printf("1x I28F320J3A (32Mbit)\n");
+			break;
+		case (INTEL_ID_28F640J3A & FLASH_TYPEMASK):
+			printf("1x I28F640J3A (64Mbit)\n");
+			break;
+		case (INTEL_ID_28F128J3A & FLASH_TYPEMASK):
+			printf("1x I28F128J3A (128Mbit)\n");
+			break;
+		default:
+			printf("Unknown Chip Type\n");
+			goto done;
+			break;
+		}
+		
+		break;
+		
+	case (AMD_MANUFACT & FLASH_VENDMASK):
+		printf("AMD:   ");
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		case (AMD_ID_LV640U & FLASH_TYPEMASK):
+			printf("1x AMD29LV641DH (64Mbit)\n");
+			break;
+		case (AMD_ID_DL640 & FLASH_TYPEMASK):
+			printf("1x AMD29LV641MH (64Mbit)\n");
+			break;
+		default:
+			printf("Unknown Chip Type\n");
+			goto done;
+			break;
+		}
+		
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+	
+	
+	printf("  Size: %ld MB in %d Sectors\n",
+	       info->size >> 20, info->sector_count);
+	
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	
+	done:
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+static u32 _amd_erase_flash(u32 addr, u32 sector)
+{
+	unsigned elapsed;
+	
+	/* Issue erase */
+	*(volatile u16*)(addr + 0xaaaa) = 0x00AA;
+	*(volatile u16*)(addr + 0x5554) = 0x0055;
+	*(volatile u16*)(addr + 0xaaaa) = 0x0080;
+	/* And one unlock */
+	*(volatile u16*)(addr + 0xaaaa) = 0x00AA;
+	*(volatile u16*)(addr + 0x5554) = 0x0055;
+	/* Sector erase command comes last */
+	*(volatile u16*)(addr + sector) = 0x0030;
+	
+	elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */
+	elapsed = 0;
+	while (((*(volatile u16*)(addr + sector)) & 0x0080) != 0x0080) {
+		
+		elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI);
+		if (elapsed > ((CFG_FLASH_ERASE_TOUT/CFG_HZ) * 1000)) {
+			*(volatile u16*)(addr) = 0x00f0;
+			return 1;			
+		}
+	}
+	
+	*(volatile u16*)(addr) = 0x00f0;
+	
+	return 0;
+}
+
+extern int _amd_erase_flash_end;
+asm ("_amd_erase_flash_end:\n"
+     ".long 0\n");
+
+/* this needs to be inlined, the SWTMRMMILLI register is reset by each read */
+#define __udelay(delay) \
+{	\
+	unsigned micro; \
+	unsigned milli=0; \
+	\
+	micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \
+         \
+	for (;;) { \
+		\
+		milli += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \
+		micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMICRO); \
+		\
+		if ((delay) <= (micro + (milli * 1000))) { \
+			break; \
+		} \
+	} \
+} while (0) 
+
+static u32 _intel_erase_flash(u32 addr, u32 sector)
+{	
+	unsigned elapsed;
+	
+	*(volatile u16*)(addr + sector) = 0x0050;   /* clear status register */
+	*(volatile u16*)(addr + sector) = 0x0020;   /* erase setup */
+	*(volatile u16*)(addr + sector) = 0x00D0;   /* erase confirm */
+
+	
+	/* Wait at least 80us - let's wait 1 ms */
+	__udelay(1000);
+	
+	elapsed = 0;
+	while (((*(volatile u16*)(addr + sector)) & 0x0080) != 0x0080) {
+		elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI);
+		if (elapsed > ((CFG_FLASH_ERASE_TOUT/CFG_HZ) * 1000)) {
+			*(volatile u16*)(addr + sector) = 0x00B0;  /* suspend erase      */
+			*(volatile u16*)(addr + sector) = 0x00FF;  /* reset to read mode */
+			return 1;			
+		}
+	}
+	
+	*(volatile u16*)(addr + sector) = 0x00FF;  /* reset to read mode */
+	
+	return 0;
+}
+
+
+extern int _intel_erase_flash_end;
+asm ("_intel_erase_flash_end:\n"
+     ".long 0\n");
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	u32 (*_erase_flash_ptr)(u32 a, u32 so);
+	int prot;
+	int sect;
+	unsigned size;
+	
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+	
+	if ((info->flash_id & FLASH_VENDMASK) == (AMD_MANUFACT & FLASH_VENDMASK)) {
+		size = (unsigned)&_amd_erase_flash_end - (unsigned)_amd_erase_flash; 
+		
+		if (size > PROBE_BUFFER_SIZE) {
+			printf("_amd_erase_flash() routine too large (%d) %p - %p\n",
+			       size, &_amd_erase_flash_end, _amd_erase_flash);
+			return 0;
+		}
+		
+		memcpy(buffer, _amd_erase_flash, size);
+		_erase_flash_ptr = (void*)buffer;
+	
+	} else if ((info->flash_id & FLASH_VENDMASK) == (INTEL_MANUFACT & FLASH_VENDMASK)) {
+		size = (unsigned)&_intel_erase_flash_end - (unsigned)_intel_erase_flash; 
+		
+		if (size > PROBE_BUFFER_SIZE) {
+			printf("_intel_erase_flash() routine too large (%d) %p - %p\n",
+			       size, &_intel_erase_flash_end, _intel_erase_flash);
+			return 0;
+		}
+		
+		memcpy(buffer, _intel_erase_flash, size);
+		_erase_flash_ptr = (void*)buffer;
+	} else {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+	
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+		
+	
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		
+		if (info->protect[sect] == 0) { /* not protected */
+			int res;
+			int flag;
+			
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+			
+			res = _erase_flash_ptr(info->start[0], info->start[sect]-info->start[0]);
+			
+			/* re-enable interrupts if necessary */
+			if (flag) {
+				enable_interrupts();
+			}
+			
+			
+			if (res) {
+				printf("Erase timed out, sector %d\n", sect);
+				return res;
+			}
+			
+			putc('.');			
+		}		
+	}
+
+	
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int _amd_write_word(unsigned start, unsigned dest, unsigned data)
+{
+	volatile u16 *addr2 = (u16*)start;
+	volatile u16 *dest2 = (u16*)dest;
+	volatile u16 *data2 = (u16*)&data;
+	int i;
+	unsigned elapsed;
+	
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((volatile u16*)dest) & (u16)data) != (u16)data) {
+		return 2;
+	}
+	
+	for (i = 0; i < 2; i++) {
+		
+		
+		addr2[0x5555] = 0x00AA;
+		addr2[0x2aaa] = 0x0055;
+		addr2[0x5555] = 0x00A0;
+		
+		dest2[i] = (data >> (i*16)) & 0xffff;
+		
+		elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */
+		elapsed = 0;
+		
+		/* data polling for D7 */
+		while ((dest2[i] & 0x0080) != (data2[i] & 0x0080)) {
+			elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI);
+			if (elapsed > ((CFG_FLASH_WRITE_TOUT/CFG_HZ) * 1000)) {
+				addr2[i] = 0x00f0;
+				return 1;			
+			}
+		}
+	}
+	
+	addr2[i] = 0x00f0;
+	
+	return 0;
+}
+
+extern int _amd_write_word_end;
+asm ("_amd_write_word_end:\n"
+     ".long 0\n");
+
+
+
+static int _intel_write_word(unsigned start, unsigned dest, unsigned data)
+{
+	int i;
+	unsigned elapsed;
+	
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((volatile u16*)dest) & (u16)data) != (u16)data) {
+		return 2;
+	}
+	
+	for (i = 0; i < 2; i++) {
+		
+		*(volatile u16*)(dest+2*i) = 0x0040; /* write setup */		
+		*(volatile u16*)(dest+2*i) = (data >> (i*16)) & 0xffff;
+		
+		elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */
+		elapsed = 0;
+		
+		/* data polling for D7 */
+		while ((*(volatile u16*)dest & 0x0080) != 0x0080) {
+			elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI);
+			if (elapsed > ((CFG_FLASH_WRITE_TOUT/CFG_HZ) * 1000)) {
+				*(volatile u16*)dest = 0x00ff;
+				return 1;			
+			}
+		}
+	}
+	
+	*(volatile u16*)dest = 0x00ff;
+	
+	
+	return 0;
+
+}
+
+extern int _intel_write_word_end;
+asm ("_intel_write_word_end:\n"
+     ".long 0\n");
+
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 3 - Unsupported flash type
+ */
+
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+	int flag;
+	u32 (*_write_word_ptr)(unsigned start, unsigned dest, unsigned data);
+	unsigned size;
+	
+	if ((info->flash_id & FLASH_VENDMASK) == (AMD_MANUFACT & FLASH_VENDMASK)) {
+		size = (unsigned)&_amd_write_word_end - (unsigned)_amd_write_word; 
+		
+		if (size > PROBE_BUFFER_SIZE) {
+			printf("_amd_write_word() routine too large (%d) %p - %p\n",
+			       size, &_amd_write_word_end, _amd_write_word);
+			return 0;
+		}
+		
+		memcpy(buffer, _amd_write_word, size);
+		_write_word_ptr = (void*)buffer;
+	
+	} else if ((info->flash_id & FLASH_VENDMASK) == (INTEL_MANUFACT & FLASH_VENDMASK)) {
+		size = (unsigned)&_intel_write_word_end - (unsigned)_intel_write_word; 
+		
+		if (size > PROBE_BUFFER_SIZE) {
+			printf("_intel_write_word() routine too large (%d) %p - %p\n",
+			       size, &_intel_write_word_end, _intel_write_word);
+			return 0;
+		}
+		
+		memcpy(buffer, _intel_write_word, size);
+		_write_word_ptr = (void*)buffer;
+	} else {
+		printf ("Can't program unknown flash type - aborted\n");
+		return 3;
+	}
+
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+	
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data |= (*(uchar *)cp) << (8*i);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data |= *src++ << (8*i);
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data |= (*(uchar *)cp)  << (8*i);
+		}
+		
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+		
+		rc = _write_word_ptr(info->start[0], wp, data);
+		
+		/* re-enable interrupts if necessary */
+		if (flag) {
+			enable_interrupts();
+		}
+		if (rc != 0) {
+			return rc;
+		}
+		wp += 4;
+	}
+	
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+			       
+		for (i=0; i<4; ++i) {
+			data |= *src++ << (8*i);
+		}
+		
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		rc = _write_word_ptr(info->start[0], wp, data);
+		
+		/* re-enable interrupts if necessary */
+		if (flag) {
+			enable_interrupts();
+		}
+		if (rc != 0) {
+			return rc;
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+	
+	if (cnt == 0) {
+		return 0;
+	}
+	
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data |= *src++ << (8*i);
+		--cnt;
+	}
+	
+	for (; i<4; ++i, ++cp) {
+		data |= (*(uchar *)cp) << (8*i);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	rc = _write_word_ptr(info->start[0], wp, data);
+	
+	/* re-enable interrupts if necessary */
+	if (flag) {
+		enable_interrupts();
+	}
+	
+	return rc;
+	
+}
+
+

board/sc520_spunk/sc520_spunk.c

@@ -0,0 +1,686 @@
+/*
+ * 
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <ssi.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/ic/sc520.h>
+
+
+/* ------------------------------------------------------------------------- */
+
+	
+/* 
+ * Theory:
+ * We first set up all IRQs to be non-pci, edge triggered,
+ * when we later enumerate the pci bus and pci_sc520_fixup_irq() gets 
+ * called we reallocate irqs to the pci bus with sc520_pci_set_irq()
+ * as needed. Whe choose the irqs to gram from a configurable list
+ * inside pci_sc520_fixup_irq() (If this list contains stupid irq's
+ * such as 0 thngas will not work)
+ */
+
+static void irq_init(void)
+{
+	/* disable global interrupt mode */
+	write_mmcr_byte(SC520_PICICR, 0x40); 
+	
+	/* set all irqs to edge */
+	write_mmcr_byte(SC520_MPICMODE, 0x00);
+	write_mmcr_byte(SC520_SL1PICMODE, 0x00);
+	write_mmcr_byte(SC520_SL2PICMODE, 0x00);
+	
+	/* active low polarity on PIC interrupt pins, 
+	 *  active high polarity on all other irq pins */
+	write_mmcr_word(SC520_INTPINPOL, 0x0000);
+
+	/* set irq number mapping */
+	write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED);   /* disable GP timer 0 INT */       
+	write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED);   /* disable GP timer 1 INT */
+	write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED);   /* disable GP timer 2 INT */
+	write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0);             /* Set PIT timer 0 INT to IRQ0 */ 
+	write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED);     /* disable PIT timer 1 INT */
+	write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED);     /* disable PIT timer 2 INT */
+	write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED);  /* disable PCI INT A */
+	write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED);  /* disable PCI INT B */
+	write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED);  /* disable PCI INT C */
+	write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED);  /* disable PCI INT D */
+	write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */ 
+	write_mmcr_byte(SC520_SSIMAP, SC520_IRQ6);              /* Set Synchronius serial INT to IRQ6*/
+	write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED);      /* disable Watchdog INT */
+	write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8);              /* Set RTC int to 8 */
+	write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED);      /* disable write protect INT */
+	write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1);              /* Set ICE Debug Serielport INT to IRQ1 */
+	write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13);             /* Set FP error INT to IRQ13 */
+	
+	write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4);            /* Set internal UART2 INT to IRQ4 */
+	write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3);            /* Set internal UART2 INT to IRQ3 */
+	
+	write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ7);             /* Set GPIRQ0 (PC-Card AUX IRQ) to IRQ7 */
+	write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ14);            /* Set GPIRQ1 (CF IRQ) to IRQ14 */
+	write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ5);             /* Set GPIRQ3 ( CAN IRQ ) ti IRQ5 */ 
+	write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED);     /* disbale GIRQ4 ( IRR IRQ ) */
+	write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ5 */
+	write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ6 */
+	write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ7 */
+	write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ8 */
+	write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ9 */
+	write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ2 */
+	write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ_DISABLED);     /* disable GPIRQ10 */          
+	
+	write_mmcr_word(SC520_PCIHOSTMAP, 0x11f);               /* Map PCI hostbridge INT to NMI */
+	write_mmcr_word(SC520_ECCMAP, 0x100);                   /* Map SDRAM ECC failure INT to NMI */
+ 
+}
+
+	
+/* PCI stuff */
+static void pci_sc520_spunk_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	int version = read_mmcr_byte(SC520_SYSINFO);
+	
+	/* a configurable lists of irqs to steal
+	 * when we need one (a board with more pci interrupt pins
+	 * would use a larger table */
+	static int irq_list[] = {
+		CFG_FIRST_PCI_IRQ,
+		CFG_SECOND_PCI_IRQ,
+		CFG_THIRD_PCI_IRQ,
+		CFG_FORTH_PCI_IRQ
+	};
+	static int next_irq_index=0;
+	
+	char tmp_pin;	
+	int pin;
+	
+	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
+	pin = tmp_pin;
+	
+	pin-=1; /* pci config space use 1-based numbering */
+	if (-1 == pin) {
+		return; /* device use no irq */
+	}
+	
+	
+       
+	/* map device number +  pin to a pin on the sc520 */
+	switch (PCI_DEV(dev)) {
+	case 6:  /* ETH0 */		  
+		pin+=SC520_PCI_INTA;
+		break;
+		
+	case 7:  /* ETH1 */
+		pin+=SC520_PCI_INTB;
+		break;
+		
+	case 8:  /* Crypto */
+		pin+=SC520_PCI_INTC;
+		break;
+		
+	case 9: /* PMC slot */
+		pin+=SC520_PCI_INTD;
+		break;
+		
+	case 10: /* PC-Card */
+		
+		if (version < 10) {			
+			pin+=SC520_PCI_INTD;
+		} else {
+			pin+=SC520_PCI_INTC;
+		}
+		break;
+		
+	default: 
+		return;
+	}
+	
+	pin&=3; /* wrap around */
+	
+	if (sc520_pci_ints[pin] == -1) {
+		/* re-route one interrupt for us */		
+		if (next_irq_index > 3) {
+			return;
+		}
+		if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) { 
+			return;
+		}
+		next_irq_index++;
+	}
+
+	
+	if (-1 != sc520_pci_ints[pin]) {
+		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 
+					   sc520_pci_ints[pin]);
+	}
+#if 0	
+	printf("fixup_irq: device %d pin %c irq %d\n", 
+	       PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
+#endif
+}
+
+
+static void pci_sc520_spunk_configure_cardbus(struct pci_controller *hose, 
+					      pci_dev_t dev, struct pci_config_table *te)
+{
+	u32 io_base;
+	u32 temp;
+	
+	pciauto_config_device(hose, dev);
+	
+	pci_hose_write_config_word(hose, dev, PCI_COMMAND, 0x07);  /* enable device */
+	pci_hose_write_config_byte(hose, dev, 0x0c, 0x10);         /* cacheline size */
+	pci_hose_write_config_byte(hose, dev, 0x0d, 0x40);         /* latency timer */
+	pci_hose_write_config_byte(hose, dev, 0x1b, 0x40);         /* cardbus latency timer */
+	pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0040);  /* reset cardbus */
+	pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0080);  /* route interrupts though ExCA */
+	pci_hose_write_config_word(hose, dev,  0x44, 0x3e0); /* map legacy I/O port to 0x3e0 */
+	
+	pci_hose_read_config_dword(hose, dev,  0x80, &temp); /* System control */ 
+	pci_hose_write_config_dword(hose, dev,  0x80, temp | 0x60); /* System control: disable clockrun */ 
+	/* route MF0 to ~INT and MF3 to IRQ7 
+	 * reserve all others */
+	pci_hose_write_config_dword(hose, dev, 0x8c, 0x00007002); 
+	pci_hose_write_config_byte(hose, dev, 0x91, 0x00);    /* card control */
+	pci_hose_write_config_byte(hose, dev, 0x92, 0x62);    /* device control */
+	
+	if (te->device != 0xac56) {
+		pci_hose_write_config_byte(hose, dev, 0x93, 0x21);    /* async interrupt enable */
+		pci_hose_write_config_word(hose, dev, 0xa8, 0x0000);  /* reset GPIO */
+		pci_hose_write_config_word(hose, dev, 0xac, 0x0000);  /* reset GPIO */
+		pci_hose_write_config_word(hose, dev, 0xaa, 0x0000);  /* reset GPIO */
+		pci_hose_write_config_word(hose, dev, 0xae, 0x0000);  /* reset GPIO */
+	} else {
+		pci_hose_write_config_byte(hose, dev, 0x93, 0x20);    /*  */
+	}
+	pci_hose_write_config_word(hose, dev, 0xa4, 0x8000);  /* reset power management */
+	
+	
+	pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &io_base);
+	io_base &= ~0xfL;
+	
+	writeb(0x07, io_base+0x803); /* route CSC irq though ExCA and enable IRQ7 */
+	writel(0, io_base+0x10);     /* CLKRUN default */
+	writel(0, io_base+0x20);     /* CLKRUN default */
+	
+}
+
+
+
+static struct pci_config_table pci_sc520_spunk_config_table[] = {
+	{ 0x104c, 0xac50, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} }, 
+	{ 0x104c, 0xac56, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} }, 
+	{ 0, 0, 0, 0, 0, 0, NULL, {0,0,0}}
+};
+
+static struct pci_controller sc520_spunk_hose = {
+	fixup_irq: pci_sc520_spunk_fixup_irq,
+	config_table: pci_sc520_spunk_config_table,
+	first_busno: 0x00,
+	last_busno: 0xff,
+};
+
+void pci_init_board(void)
+{
+	pci_sc520_init(&sc520_spunk_hose);
+}
+
+
+/* set up the ISA bus timing and system address mappings */
+static void bus_init(void)
+{
+	/* versions 
+	 * 0   Hyglo versions 0.95 and 0.96 (large baords)
+	 * ??  Hyglo version 0.97 (small board)
+	 * 10  Spunk board
+	 */
+	int version = read_mmcr_byte(SC520_SYSINFO);
+	
+	if (version) {
+		/* set up the GP IO pins (for the Spunk board) */
+		write_mmcr_word(SC520_PIOPFS31_16, 0xfff0); 	/* set the GPIO pin function 31-16 reg */
+		write_mmcr_word(SC520_PIOPFS15_0,  0x000f);  	/* set the GPIO pin function 15-0 reg */
+		write_mmcr_word(SC520_PIODIR31_16, 0x000f); 	/* set the GPIO direction 31-16 reg */
+		write_mmcr_word(SC520_PIODIR15_0,  0x1ff0);  	/* set the GPIO direction 15-0 reg */
+		write_mmcr_byte(SC520_CSPFS, 0xc0);  		/* set the CS pin function reg */	
+		write_mmcr_byte(SC520_CLKSEL, 0x70);
+		
+		write_mmcr_word(SC520_PIOCLR31_16, 0x0003);     /* reset SSI chip-selects */
+		write_mmcr_word(SC520_PIOSET31_16, 0x000c);
+
+	} else {
+		/* set up the GP IO pins (for the Hyglo board) */
+		write_mmcr_word(SC520_PIOPFS31_16, 0xffc0); 	/* set the GPIO pin function 31-16 reg */
+		write_mmcr_word(SC520_PIOPFS15_0, 0x1e7f);  	/* set the GPIO pin function 15-0 reg */
+		write_mmcr_word(SC520_PIODIR31_16, 0x003f); 	/* set the GPIO direction 31-16 reg */
+		write_mmcr_word(SC520_PIODIR15_0, 0xe180);  	/* set the GPIO direction 15-0 reg */
+		write_mmcr_byte(SC520_CSPFS, 0x00);  		/* set the CS pin function reg */	
+		write_mmcr_byte(SC520_CLKSEL, 0x70);
+		
+		write_mmcr_word(SC520_PIOCLR15_0, 0x0180);      /* reset SSI chip-selects */
+	}
+	
+	write_mmcr_byte(SC520_GPCSRT, 1);   /* set the GP CS offset */    	
+	write_mmcr_byte(SC520_GPCSPW, 3);   /* set the GP CS pulse width */
+	write_mmcr_byte(SC520_GPCSOFF, 1);  /* set the GP CS offset */
+	write_mmcr_byte(SC520_GPRDW, 3);    /* set the RD pulse width */
+	write_mmcr_byte(SC520_GPRDOFF, 1);  /* set the GP RD offset */
+        write_mmcr_byte(SC520_GPWRW, 3);    /* set the GP WR pulse width */
+	write_mmcr_byte(SC520_GPWROFF, 1);  /* set the GP WR offset */
+
+	write_mmcr_word(SC520_BOOTCSCTL, 0x0407);		/* set up timing of BOOTCS */ 
+	
+	/* adjust the memory map:
+	 * by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM
+	 * and 256MB to 1G-128k  (0x1000000 - 0x37ffffff) is mapped to PCI mmio
+	 * we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */ 
+	
+		
+	
+	/* bootcs */
+	write_mmcr_long(SC520_PAR12, 0x8bffe800);		
+	
+	/* IDE0 = GPCS6 1f0-1f7 */
+	write_mmcr_long(SC520_PAR3,  0x380801f0);		
+
+	/* IDE1 = GPCS7 3f6 */
+	write_mmcr_long(SC520_PAR4,  0x3c0003f6);		
+
+	asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */	
+
+	write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS));	
+
+}
+
+
+
+/* par usage:
+ * PAR0   (legacy_video)
+ * PAR1   (PCI ROM mapping)
+ * PAR2 
+ * PAR3   IDE 
+ * PAR4   IDE
+ * PAR5   (legacy_video)
+ * PAR6 
+ * PAR7   (legacy_video)
+ * PAR8   (legacy_video)
+ * PAR9   (legacy_video)
+ * PAR10
+ * PAR11  (ISAROM)
+ * PAR12  BOOTCS
+ * PAR13
+ * PAR14
+ * PAR15
+ */
+
+/* 
+ * This function should map a chunk of size bytes
+ * of the system address space to the ISA bus
+ * 
+ * The function will return the memory address
+ * as seen by the host (which may very will be the
+ * same as the bus address)
+ */
+u32 isa_map_rom(u32 bus_addr, int size) 
+{
+	u32 par;
+	
+	printf("isa_map_rom asked to map %d bytes at %x\n", 
+	       size, bus_addr);
+	
+	par = size;
+	if (par < 0x80000) {
+		par = 0x80000;
+	}
+	par >>= 12;
+	par--;
+	par&=0x7f;
+	par <<= 18;
+	par |= (bus_addr>>12);
+	par |= 0x50000000;
+	
+	printf ("setting PAR11 to %x\n", par);
+	
+	/* Map rom 0x10000 with PAR1 */
+	write_mmcr_long(SC520_PAR11,  par);
+	
+	return bus_addr;
+}
+
+/*
+ * this function removed any mapping created
+ * with pci_get_rom_window()
+ */
+void isa_unmap_rom(u32 addr)
+{
+	printf("isa_unmap_rom asked to unmap %x", addr);
+	if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) {
+		write_mmcr_long(SC520_PAR11, 0);
+		printf(" done\n");
+		return;
+	}
+	printf(" not ours\n");
+}
+
+#ifdef CONFIG_PCI
+#define PCI_ROM_TEMP_SPACE 0x10000
+/* 
+ * This function should map a chunk of size bytes
+ * of the system address space to the PCI bus,
+ * suitable to map PCI ROMS (bus address < 16M)
+ * the function will return the host memory address
+ * which should be converted into a bus address
+ * before used to configure the PCI rom address 
+ * decoder
+ */
+u32 pci_get_rom_window(struct pci_controller *hose, int size) 
+{
+	u32 par;
+	
+	par = size;
+	if (par < 0x80000) {
+		par = 0x80000;
+	}
+	par >>= 16;
+	par--;
+	par&=0x7ff;
+	par <<= 14;
+	par |= (PCI_ROM_TEMP_SPACE>>16);
+	par |= 0x72000000;
+	
+	printf ("setting PAR1 to %x\n", par);
+	
+	/* Map rom 0x10000 with PAR1 */
+	write_mmcr_long(SC520_PAR1,  par);
+	
+	return PCI_ROM_TEMP_SPACE;
+}
+
+/*
+ * this function removed any mapping created
+ * with pci_get_rom_window()
+ */
+void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
+{
+	printf("pci_remove_rom_window: %x", addr);
+	if (addr == PCI_ROM_TEMP_SPACE) {
+		write_mmcr_long(SC520_PAR1, 0);
+		printf(" done\n");
+		return;
+	}
+	printf(" not ours\n");
+	
+}
+
+/*
+ * This function is called in order to provide acces to the
+ * legacy video I/O ports on the PCI bus. 
+ * After this function accesses to I/O ports 0x3b0-0x3bb and 
+ * 0x3c0-0x3df shuld result in transactions on the PCI bus.
+ * 
+ */
+int pci_enable_legacy_video_ports(struct pci_controller *hose)
+{
+	/* Map video memory to 0xa0000*/
+	write_mmcr_long(SC520_PAR0,  0x7200400a);
+	
+	/* forward all I/O accesses to PCI */
+	write_mmcr_byte(SC520_ADDDECCTL, 
+			read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI);	
+	
+	
+	/* so we map away all io ports to pci (only way to access pci io
+	 * below 0x400. But then we have to map back the portions that we dont
+	 * use so that the generate cycles on the GPIO bus where the sio and
+	 * ISA slots are connected, this requre the use of several PAR registers 
+	 */
+	
+	/* bring 0x100 - 0x2f7 back to ISA using PAR5 */
+	write_mmcr_long(SC520_PAR5, 0x31f70100);		
+		
+	/* com2 use 2f8-2ff */
+	
+	/* bring 0x300 - 0x3af back to ISA using PAR7 */
+	write_mmcr_long(SC520_PAR7, 0x30af0300);		
+	
+	/* vga use 3b0-3bb */
+	
+	/* bring 0x3bc - 0x3bf back to ISA using PAR8 */
+	write_mmcr_long(SC520_PAR8, 0x300303bc);		
+	
+	/* vga use 3c0-3df */
+	
+	/* bring 0x3e0 - 0x3f7 back to ISA using PAR9 */
+	write_mmcr_long(SC520_PAR9, 0x301703e0);		
+		
+	/* com1 use 3f8-3ff */		
+
+	return 0;
+}
+#endif
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	
+	init_sc520();	
+	bus_init();
+	irq_init();
+		
+	/* max drive current on SDRAM */
+	write_mmcr_word(SC520_DSCTL, 0x0100);
+		
+	/* enter debug mode after next reset (only if jumper is also set) */
+	write_mmcr_byte(SC520_RESCFG, 0x08);
+	/* configure the software timer to 33.000MHz */
+	write_mmcr_byte(SC520_SWTMRCFG, 1);
+	gd->bus_clk = 33000000;
+	
+	return 0;
+}
+
+int dram_init(void)
+{
+	init_sc520_dram();
+	return 0;
+}
+
+void show_boot_progress(int val)
+{
+ 	int version = read_mmcr_byte(SC520_SYSINFO);
+	
+	if (version == 0) {
+		/* PIO31-PIO16 Data */
+		write_mmcr_word(SC520_PIODATA31_16,                                           
+				(read_mmcr_word(SC520_PIODATA31_16) & 0xffc0)| ((val&0x7e)>>1)); /* 0x1f8 >> 3 */
+		
+		/* PIO0-PIO15 Data */
+		write_mmcr_word(SC520_PIODATA15_0, 
+				(read_mmcr_word(SC520_PIODATA15_0) & 0x1fff)| ((val&0x7)<<13));
+	} else {
+		/* newer boards use PIO4-PIO12 */
+		/* PIO0-PIO15 Data */
+#if 0		
+		val = (val & 0x007) | ((val & 0x038) << 3) | ((val & 0x1c0) >> 3); 
+#else
+		val = (val & 0x007) | ((val & 0x07e) << 2); 
+#endif
+		write_mmcr_word(SC520_PIODATA15_0, 
+				(read_mmcr_word(SC520_PIODATA15_0) & 0xe00f) | ((val&0x01ff)<<4));
+	}
+}
+
+
+int last_stage_init(void)
+{
+	
+	int version = read_mmcr_byte(SC520_SYSINFO);
+	
+	printf("Omicron Ceti SC520 Spunk revision %x\n", version);
+	
+#if 0
+	if (version) {
+		int x, y;
+		
+		printf("eeprom probe %d\n", spi_eeprom_probe(1));
+		
+		spi_eeprom_read(1, 0, (u8*)&x, 2);
+		spi_eeprom_read(1, 1, (u8*)&y, 2);
+		printf("eeprom bytes %04x%04x\n", x, y);
+		x ^= 0xffff;
+		y ^= 0xffff;
+		spi_eeprom_write(1, 0, (u8*)&x, 2);
+		spi_eeprom_write(1, 1, (u8*)&y, 2);
+		
+		spi_eeprom_read(1, 0, (u8*)&x, 2);
+		spi_eeprom_read(1, 1, (u8*)&y, 2);
+		printf("eeprom bytes %04x%04x\n", x, y);
+		
+	} else {
+		int x, y;
+		
+		printf("eeprom probe %d\n", mw_eeprom_probe(1));
+		
+		mw_eeprom_read(1, 0, (u8*)&x, 2);
+		mw_eeprom_read(1, 1, (u8*)&y, 2);
+		printf("eeprom bytes %04x%04x\n", x, y);
+		
+		x ^= 0xffff;
+		y ^= 0xffff;
+		mw_eeprom_write(1, 0, (u8*)&x, 2);
+		mw_eeprom_write(1, 1, (u8*)&y, 2);
+		
+		mw_eeprom_read(1, 0, (u8*)&x, 2);
+		mw_eeprom_read(1, 1, (u8*)&y, 2);
+		printf("eeprom bytes %04x%04x\n", x, y);
+		
+		
+	}
+#endif
+
+	ds1722_probe(2);
+	
+	return 0;
+}
+
+void ssi_chip_select(int dev) 
+{
+	int version = read_mmcr_byte(SC520_SYSINFO);
+	
+	if (version) {
+		/* Spunk board: EEPROM and CAN are actove-low, TEMP and AUX are active high */
+		switch (dev) {
+		case 1: /* EEPROM */
+			write_mmcr_word(SC520_PIOCLR31_16, 0x0004);
+			break;
+			
+		case 2: /* Temp Probe */
+			write_mmcr_word(SC520_PIOSET31_16, 0x0002);
+			break;
+			
+		case 3: /* CAN */
+			write_mmcr_word(SC520_PIOCLR31_16, 0x0008);
+			break;
+			
+		case 4: /* AUX */				
+			write_mmcr_word(SC520_PIOSET31_16, 0x0001);
+			break;
+		
+		case 0:
+			write_mmcr_word(SC520_PIOCLR31_16, 0x0003);
+			write_mmcr_word(SC520_PIOSET31_16, 0x000c);
+			break;
+			
+		default:
+			printf("Illegal SSI device requested: %d\n", dev);
+		}
+	} else {
+		
+		/* Globox board: Both EEPROM and TEMP are active-high */
+
+		switch (dev) {
+		case 1: /* EEPROM */
+			write_mmcr_word(SC520_PIOSET15_0, 0x0100);
+			break;
+			
+		case 2: /* Temp Probe */
+			write_mmcr_word(SC520_PIOSET15_0, 0x0080);
+			break;
+		
+		case 0:
+			write_mmcr_word(SC520_PIOCLR15_0, 0x0180);
+			break;
+			
+		default:
+			printf("Illegal SSI device requested: %d\n", dev);
+		}
+	}	
+}
+
+
+void spi_init_f(void) 
+{
+	read_mmcr_byte(SC520_SYSINFO) ?
+		spi_eeprom_probe(1) : 
+	mw_eeprom_probe(1);
+	
+}
+
+ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len) 
+{
+	int offset;
+	int i;
+	
+	offset = 0;
+	for (i=0;i<alen;i++) {
+		offset <<= 8;
+		offset |= addr[i];
+	}
+	
+	return 	read_mmcr_byte(SC520_SYSINFO) ?
+		spi_eeprom_read(1, offset, buffer, len) : 
+	mw_eeprom_read(1, offset, buffer, len);
+}
+
+ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len) 
+{
+	int offset;
+	int i;
+	
+	offset = 0;
+	for (i=0;i<alen;i++) {
+		offset <<= 8;
+		offset |= addr[i];
+	}
+	
+	return 	read_mmcr_byte(SC520_SYSINFO) ?
+		spi_eeprom_write(1, offset, buffer, len) : 
+	mw_eeprom_write(1, offset, buffer, len);
+}
+

board/sc520_spunk/sc520_spunk_asm.S

@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* now setup the General purpose bus to give us access to the LEDs.
+ * We can then use the leds to display status information.
+ */ 
+
+sc520_cdp_registers:
+/* size    offset        value */
+.word 1 ; .word 0x040 ; .long 0x00       /* SDRAM buffer control */
+.word 2 ; .word 0xc08 ; .long 0x0001     /* GP CS offset */
+.word 2 ; .word 0xc09 ; .long 0x0003     /* GP CS width */
+.word 2 ; .word 0xc0a ; .long 0x0001     /* GP CS width */
+.word 2 ; .word 0xc0b ; .long 0x0003     /* GP RD pulse width */
+.word 2 ; .word 0xc0c ; .long 0x0001     /* GP RD offse */
+.word 2 ; .word 0xc0d ; .long 0x0003     /* GP WR pulse width */
+.word 2 ; .word 0xc0e ; .long 0x0001     /* GP WR offset */
+.word 2 ; .word 0xc2c ; .long 0x003f     /* GPIO directionreg 31-16 */
+.word 2 ; .word 0xc2a ; .long 0xe000     /* GPIO directionreg 15-0 */
+.word 2 ; .word 0xc22 ; .long 0xffc0     /* GPIO pin function 31-16 reg */
+.word 2 ; .word 0xc20 ; .long 0x1fff     /* GPIO pin function 15-0 reg */
+.word 0 ; .word 0x000 ; .long 0x00
+
+/* board early intialization */
+.globl early_board_init
+early_board_init:
+        movl    $sc520_cdp_registers,%esi
+init_loop:	
+        movl    $0xfffef000,%edi     /* MMCR base to edi */					
+	movw	(%esi), %bx          /* load size to bx */
+	cmpw	$0, %bx              /* if size is 0 we're done */
+	je	done 
+	xorl	%edx,%edx
+	movw	2(%esi), %dx        /* load MMCR offset to dx */
+	addl	%edx, %edi          /* add offset to base in edi */
+	movl	4(%esi), %eax       /* load value in eax */
+	cmpw	$1, %bx
+	je	byte                 /* byte op? */
+	cmpw	$2, %bx
+	je	word                 /* word op? */
+	movl	%eax, (%edi)         /* must be long, then */
+	jmp	next
+byte:   movb    %al,(%edi)        
+	jmp	next
+word:	movw	%ax,(%edi)
+next:	addl	$8, %esi             /* advance esi */
+	jmp	init_loop
+
+	/* light all leds */
+done:   movl    $0xfffefc32,%edx 
+	movw    $0000,(%edx)              
+
+	jmp 	*%ebp		     /* return to caller */
+
+
+.globl __show_boot_progress
+__show_boot_progress:
+	movl    $0xfffefc32,%edx 
+	xorw    $0xffff, %ax 
+	movw    %ax,(%edx)              
+	jmp	*%ebp
+