* Patch by Martin Krause, 11 Sep 2003:

add burn-in tests for TRAB board

* Enable instruction cache on MPC5200 board

CHANGELOG

@@ -1,7 +1,55 @@
 ======================================================================
-Changes for U-Boot 0.4.7:
+Changes for U-Boot 1.0.0:
 ======================================================================
 
+* Patch by Martin Krause, 11 Sep 2003:
+  add burn-in tests for TRAB board
+
+* Enable instruction cache on MPC5200 board
+
+* Patch by Denis Peter, 11 Sep 2003:
+  - fix USB data pointer assignment for bulk only transfer.
+  - prevent to display erased directories in FAT filesystem.
+
+* Change output format for NAND flash - make it look like for other
+  memory, too
+
+======================================================================
+Changes for U-Boot 0.4.8:
+======================================================================
+
+* Patches by Denis Peter, 9 Sep 2003:
+  add FAT support for IDE, SCSI and USB
+
+* Patches by Gleb Natapov, 2 Sep 2003:
+  - cleanup of POST code for unsupported architectures
+  - MPC824x locks way0 of data cache for use as initial RAM;
+    this patch unlocks it after relocation to RAM and invalidates
+    the locked entries.
+
+* Patch by Gleb Natapov, 30 Aug 2003:
+  new I2C driver for mpc107 bridge. Now works from flash.
+
+* Patch by Dave Ellis, 11 Aug 2003:
+  - JFFS2: fix typo in common/cmd_jffs2.c
+  - JFFS2: fix CFG_JFFS2_SORT_FRAGMENTS option
+  - JFFS2: remove node version 0 warning
+  - JFFS2: accept JFFS2 PADDING nodes
+  - SXNI855T: add AM29LV800 support
+  - SXNI855T: move environment from EEPROM to flash
+  - SXNI855T: boot from JFFS2 in NOR or NAND flash
+
+* Patch by Bill Hargen, 11 Aug 2003:
+  fixes for I2C on MPC8240
+  - fix i2c_write routine
+  - fix iprobe command
+  - eliminates use of global variables, plus dead code, cleanup.
+
+* Add support for USB Mass Storage Devices (BBB)
+  (tested with USB memory sticks only)
+
+* Avoid flicker on TRAB's VFD
+
 * Add support for SK98xx driver
 
 * Add PCI support for SL8245 board
@@ -27,6 +75,10 @@ Changes for U-Boot 0.4.7:
 * Patch by Yuli Barcohen, 7 Aug 2003:
   check BCSR to detect if the board is configured in PCI mode
 
+======================================================================
+Changes for U-Boot 0.4.7:
+======================================================================
+
 * Patch by Raghu Krishnaprasad, 7 Aug 2003:
   add support for Adder II MPC852T module
 
@@ -263,7 +315,7 @@ Changes for U-Boot 0.4.1:
   - PIC on LWMON board needs delay after power-on
   - Add missing RSR definitions for MPC8xx
   - Improve log buffer handling: guarantee clean reset after power-on
-  - Add support for EXBITGEN board
+  - Add support for EXBITGEN board (aka "genie")
   - Add support for SL8245 board
 
 * Code cleanup:

CREDITS

@@ -302,3 +302,9 @@ W: www.elinos.com
 N: Pantelis Antoniou
 E: panto@intracom.gr
 D: NETVIA board support, ARTOS support.
+
+N: Raghu Krishnaprasad
+E: Raghu.Krishnaprasad@fci.com
+D: Support for Adder-II MPC852T evaluation board
+W: http://www.forcecomputers.com
+

MAINTAINERS

@@ -89,6 +89,7 @@ Wolfgang Denk <wd@denx.de>
 	TQM8255			MPC8255
 
 	CPU86			MPC8260
+	PM825			MPC8250
 	PM826			MPC8260
 	TQM8260			MPC8260
 
@@ -107,6 +108,10 @@ Dave Ellis <DGE@sixnetio.com>
 
 	SXNI855T		MPC8xx
 
+Raghu Krishnaprasad <raghu.krishnaprasad@fci.com>
+	
+	ADDERII			MPC852T
+
 Thomas Frieden <ThomasF@hyperion-entertainment.com>
 
 	AmigaOneG3SE		MPC7xx

Makefile

@@ -117,6 +117,8 @@ LIBS += drivers/sk98lin/libsk98lin.a
 LIBS += post/libpost.a post/cpu/libcpu.a
 LIBS += common/libcommon.a
 LIBS += lib_generic/libgeneric.a
+# Add GCC lib
+PLATFORM_LIBS += -L $(shell dirname `$(CC) -print-libgcc-file-name`) -lgcc
 
 #########################################################################
 #########################################################################

board/at91rm9200dk/at91rm9200dk.c

@@ -66,7 +66,7 @@ int dram_init (void)
  * The NAND lives in the CS2* space
  */
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
-extern void nand_probe (ulong physadr);
+extern ulong nand_probe (ulong physadr);
 
 #define AT91_SMARTMEDIA_BASE 0x40000000	/* physical address to access memory on NCS3 */
 void nand_init (void)
@@ -103,10 +103,12 @@ void nand_init (void)
 	*AT91C_PIOB_ODR = AT91C_PIO_PB1;	/* disable output */
 
 	if (*AT91C_PIOB_PDSR & AT91C_PIO_PB1)
-		printf ("No ");
-	printf ("SmartMedia card inserted\n");
+		printf ("  No SmartMedia card inserted\n");
+#ifdef DEBUG
+	printf ("  SmartMedia card inserted\n");
 
 	printf ("Probing at 0x%.8x\n", AT91_SMARTMEDIA_BASE);
-	nand_probe (AT91_SMARTMEDIA_BASE);
+#endif
+	printf ("%4lu MB\n", nand_probe(AT91_SMARTMEDIA_BASE) >> 20);
 }
 #endif

board/dave/PPChameleonEVB/PPChameleonEVB.c

@@ -255,16 +255,20 @@ int testdram (void)
 /* ------------------------------------------------------------------------- */
 
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
-extern void
+extern ulong
 nand_probe(ulong physadr);
 
 void
 nand_init(void)
 {
+	ulong totlen;
+
 	debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE);
-	nand_probe (CFG_NAND0_BASE);
+	totlen = nand_probe (CFG_NAND0_BASE);
 
 	debug ("Probing at 0x%.8x\n", CFG_NAND1_BASE);
-	nand_probe (CFG_NAND1_BASE);
+	totlen += nand_probe (CFG_NAND1_BASE);
+
+	printf ("%4lu MB\n", totlen >>20);
 }
 #endif

board/esd/ash405/ash405.c

@@ -239,15 +239,11 @@ int testdram (void)
 /* ------------------------------------------------------------------------- */
 
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
-#include <linux/mtd/nand.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
 
 void nand_init(void)
 {
-	nand_probe(CFG_NAND_BASE);
-	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
-		puts("NAND:  ");
-		print_size(nand_dev_desc[0].totlen, "\n");
-	}
+	unsigned long totlen = nand_probe(CFG_NAND_BASE);
+
+	printf ("%4lu MB\n", totlen >> 20);
 }
 #endif

board/mpc8260ads/mpc8260ads.c

@@ -238,7 +238,9 @@ int board_pre_init (void)
 
 long int initdram (int board_type)
 {
+#if CONFIG_ADSTYPE == CFG_PQ2FADS
 	vu_long *bcsr = (vu_long *)CFG_BCSR;
+#endif
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 	volatile uchar *ramaddr, c = 0xff;

board/mpl/common/common_util.c

@@ -375,138 +375,6 @@ void show_stdio_dev(void)
 	}
 }
 
-/* ------------------------------------------------------------------------- */
-
-	/* switches the cs0 and the cs1 to the locations.
-	   When boot is TRUE, the the mapping is switched
-	   to the boot configuration, If it is FALSE, the
-	   flash will be switched in the boot area */
-
-#undef SW_CS_DBG
-#ifdef SW_CS_DBG
-#define	SW_CS_PRINTF(fmt,args...)	printf (fmt ,##args)
-#else
-#define SW_CS_PRINTF(fmt,args...)
-#endif
-
-#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405)
-int switch_cs(unsigned char boot)
-{
-	unsigned long pbcr;
-	int mode;
-
-	mode=get_boot_mode();
-	mtdcr(ebccfga, pb0cr);
-	pbcr = mfdcr (ebccfgd);
-	if (mode & BOOT_MPS) {
-		/* Boot width = 8 bit MPS Boot, set up MPS on CS0 */
-		/* we need only to switch if boot from MPS */
-		/* printf(" MPS boot mode detected. ");*/
-		/* printf("cs0 cfg: %lx\n",pbcr); */
-		if(boot) {
-			/* switch to boot configuration */
-			/* this is a 8bit boot, switch cs0 to flash location */
-			SW_CS_PRINTF("switch to boot mode (MPS on High address\n");
-			pbcr&=0x000FFFFF; /*mask base address of the cs0 */
-			pbcr|=(FLASH_BASE0_PRELIM & 0xFFF00000);
-			mtdcr(ebccfga, pb0cr);
-			mtdcr(ebccfgd, pbcr);
-			SW_CS_PRINTF("  new cs0 cfg: %lx\n",pbcr);
-			mtdcr(ebccfga, pb1cr); /* get cs1 config reg (flash) */
-			pbcr = mfdcr(ebccfgd);
-			SW_CS_PRINTF(" old cs1 cfg: %lx\n",pbcr);
-			pbcr&=0x000FFFFF; /*mask base address of the cs1 */
-			pbcr|=(MULTI_PURPOSE_SOCKET_ADDR & 0xFFF00000);
-			mtdcr(ebccfga, pb1cr);
-			mtdcr(ebccfgd, pbcr);
-			SW_CS_PRINTF("  new cs1 cfg: %lx, MPS is on High Address\n",pbcr);
-		}
-		else {
-			/* map flash to boot area, */
-			SW_CS_PRINTF("map Flash to boot area\n");
-			pbcr&=0x000FFFFF; /*mask base address of the cs0 */
-			pbcr|=(MULTI_PURPOSE_SOCKET_ADDR & 0xFFF00000);
-			mtdcr(ebccfga, pb0cr);
-			mtdcr(ebccfgd, pbcr);
-			SW_CS_PRINTF("  new cs0 cfg: %lx\n",pbcr);
-			mtdcr(ebccfga, pb1cr); /* get cs1 config reg (flash) */
-			pbcr = mfdcr(ebccfgd);
-			SW_CS_PRINTF("  cs1 cfg: %lx\n",pbcr);
-			pbcr&=0x000FFFFF; /*mask base address of the cs1 */
-			pbcr|=(FLASH_BASE0_PRELIM & 0xFFF00000);
-			mtdcr(ebccfga, pb1cr);
-			mtdcr(ebccfgd, pbcr);
-			SW_CS_PRINTF("  new cs1 cfg: %lx Flash is on High Address\n",pbcr);
-		}
-		return 1;
-	}
-	else {
-		SW_CS_PRINTF("Normal boot, no switching necessary\n");
-		return 0;
-	}
-
-}
-
-int get_boot_mode(void)
-{
-	unsigned long pbcr;
-	int res = 0;
-	pbcr = mfdcr (strap);
-	if ((pbcr & PSR_ROM_WIDTH_MASK) == 0)
-		/* boot via MPS or MPS mapping */
-		res = BOOT_MPS;
-	if(pbcr & PSR_ROM_LOC)
-		/* boot via PCI.. */
-		res |= BOOT_PCI;
-	 return res;
-}
-
-/* Setup cs0 parameter finally.
-   Map the flash high (in boot area)
-   This code can only be executed from SDRAM (after relocation).
-*/
-void setup_cs_reloc(void)
-{
-	unsigned long pbcr;
-	/* Since we are relocated, we can set-up the CS finaly
-	 * but first of all, switch off PCI mapping (in case it was a PCI boot) */
-	out32r(PMM0MA,0L);
-	icache_enable (); /* we are relocated */
-	/* for PCI Boot, we have to set-up the remaining CS correctly */
-	pbcr = mfdcr (strap);
-	if(pbcr & PSR_ROM_LOC) {
-		/* boot via PCI.. */
-		if ((pbcr & PSR_ROM_WIDTH_MASK) == 0) {
-		/* Boot width = 8 bit MPS Boot, set up MPS on CS0 */
-			#ifdef DEBUG
-			printf("Mapping MPS to CS0 @ 0x%lx\n",(MPS_CR_B & 0xfff00000));
-			#endif
-			mtdcr (ebccfga, pb0ap);
-			mtdcr (ebccfgd, MPS_AP);
-			mtdcr (ebccfga, pb0cr);
-			mtdcr (ebccfgd, MPS_CR_B);
-		}
-		else {
-			/* Flash boot, set up the Flash on CS0 */
-			#ifdef DEBUG
-			printf("Mapping Flash to CS0 @ 0x%lx\n",(FLASH_CR_B & 0xfff00000));
-			#endif
-			mtdcr (ebccfga, pb0ap);
-			mtdcr (ebccfgd, FLASH_AP);
-			mtdcr (ebccfga, pb0cr);
-			mtdcr (ebccfgd, FLASH_CR_B);
-		}
-	}
-	switch_cs(0); /* map Flash High */
-}
-
-
-#elif defined(CONFIG_VCMA9)
-int switch_cs(unsigned char boot)
-{
-    return 0;
-}
-#endif /* CONFIG_VCMA9 */
 
 int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
@@ -625,6 +493,7 @@ void doc_init (void)
 
 #ifdef CONFIG_CONSOLE_EXTRA_INFO
 extern GraphicDevice ctfb;
+extern int get_boot_mode(void);
 
 void video_get_info_str (int line_number, char *info)
 {

board/mpl/common/common_util.h

@@ -31,10 +31,8 @@ typedef struct {
 } backup_t;
 
 void get_backup_values(backup_t *buf);
-int switch_cs(unsigned char boot);
+
 #if defined(CONFIG_PIP405) || defined(CONFIG_MIP405)
-int get_boot_mode(void);
-void setup_cs_reloc(void);
 #define BOOT_MPS	0x01
 #define BOOT_PCI	0x02
 #endif

board/mpl/common/flash.c

@@ -39,6 +39,13 @@
 #include <ppc4xx.h>
 #include <asm/processor.h>
 #include "common_util.h"
+#if defined(CONFIG_MIP405)
+#include "../mip405/mip405.h"
+#endif
+#if defined(CONFIG_PIP405)
+#include "../pip405/pip405.h"
+#endif
+#include <405gp_pci.h>
 
 flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 /*-----------------------------------------------------------------------
@@ -66,23 +73,102 @@ void unlock_intel_sectors(flash_info_t *info,ulong addr,ulong cnt);
 #define TRUE            1
 
 /*-----------------------------------------------------------------------
+ * Some CS switching routines:
+ *
+ * On PIP/MIP405 we have 3 (4) possible boot mode
+ *
+ * - Boot from Flash (Flash CS = CS0, MPS CS = CS1)
+ * - Boot from MPS   (Flash CS = CS1, MPS CS = CS0)
+ * - Boot from PCI with Flash map (Flash CS = CS0, MPS CS = CS1)
+ * - Boot from PCI with MPS map   (Flash CS = CS1, MPS CS = CS0)
+ * The flash init is the first board specific routine which is called
+ * after code relocation (running from SDRAM)
+ * The first thing we do is to map the Flash CS to the Flash area and
+ * the MPS CS to the MPS area. Since the flash size is unknown at this
+ * point, we use the max flash size and the lowest flash address as base.
+ * 
+ * After flash detection we adjust the size of the CS area accordingly.
+ * The board_init_r will fill in wrong values in the board init structure,
+ * but this will be fixed in the misc_init_r routine:
+ * bd->bi_flashstart=0-flash_info[0].size
+ * bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN
+ * bd->bi_flashoffset=0
+ * 
  */
+int get_boot_mode(void)
+{
+	unsigned long pbcr;
+	int res = 0;
+	pbcr = mfdcr (strap);
+	if ((pbcr & PSR_ROM_WIDTH_MASK) == 0)
+		/* boot via MPS or MPS mapping */
+		res = BOOT_MPS;
+	if(pbcr & PSR_ROM_LOC)
+		/* boot via PCI.. */
+		res |= BOOT_PCI;
+	 return res;
+}
+
+/* Map the flash high (in boot area)
+   This code can only be executed from SDRAM (after relocation).
+*/
+void setup_cs_reloc(void)
+{
+	int mode;
+	/* Since we are relocated, we can set-up the CS finaly
+	 * but first of all, switch off PCI mapping (in case it was a PCI boot) */
+	out32r(PMM0MA,0L);
+	icache_enable (); /* we are relocated */
+	/* get boot mode */
+	mode=get_boot_mode();
+	/* we map the flash high in every case */
+	/* first findout on which cs the flash is */
+	if(mode & BOOT_MPS) {
+		/* map flash high on CS1 and MPS on CS0 */
+		mtdcr (ebccfga, pb0ap);
+		mtdcr (ebccfgd, MPS_AP);
+		mtdcr (ebccfga, pb0cr);
+		mtdcr (ebccfgd, MPS_CR);
+		/* we use the default values (max values) for the flash
+		 * because its real size is not yet known */
+		mtdcr (ebccfga, pb1ap);
+		mtdcr (ebccfgd, FLASH_AP);
+		mtdcr (ebccfga, pb1cr);
+		mtdcr (ebccfgd, FLASH_CR_B);
+	}
+	else {
+		/* map flash high on CS0 and MPS on CS1 */
+		mtdcr (ebccfga, pb1ap);
+		mtdcr (ebccfgd, MPS_AP);
+		mtdcr (ebccfga, pb1cr);
+		mtdcr (ebccfgd, MPS_CR);
+		/* we use the default values (max values) for the flash
+		 * because its real size is not yet known */
+		mtdcr (ebccfga, pb0ap);
+		mtdcr (ebccfgd, FLASH_AP);
+		mtdcr (ebccfga, pb0cr);
+		mtdcr (ebccfgd, FLASH_CR_B);
+	}
+}
+
 
 
 unsigned long flash_init (void)
 {
-	unsigned long size_b0, size_b1;
-	int i;
+	unsigned long size_b0, size_b1,flashcr;
+	int mode, i;
+	extern char version_string;
+	char *p=&version_string;
 
 	/* Since we are relocated, we can set-up the CS finally */
 	setup_cs_reloc();
 	/* get and display boot mode */
-	i=get_boot_mode();
-	if(i & BOOT_PCI)
-		printf("(PCI Boot %s Map) ",(i & BOOT_MPS) ?
+	mode=get_boot_mode();
+	if(mode & BOOT_PCI)
+		printf("(PCI Boot %s Map) ",(mode & BOOT_MPS) ?
 			"MPS" : "Flash");
 	else
-		printf("(%s Boot) ",(i & BOOT_MPS) ?
+		printf("(%s Boot) ",(mode & BOOT_MPS) ?
 			"MPS" : "Flash");
 	/* Init: no FLASHes known */
 	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
@@ -91,7 +177,7 @@ unsigned long flash_init (void)
 
 	/* Static FLASH Bank configuration here - FIXME XXX */
 
-	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+	size_b0 = flash_get_size((vu_long *)CFG_MONITOR_BASE, &flash_info[0]);
 
 	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
 		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
@@ -109,8 +195,31 @@ unsigned long flash_init (void)
 	flash_info[0].protect[flash_info[0].sector_count-1] = 1;
 	size_b1 = 0 ;
 	flash_info[0].size = size_b0;
+	/* set up flash cs according to the size */
+	if(mode & BOOT_MPS) {
+		/* flash is on CS1 */
+		mtdcr(ebccfga, pb1cr);
+		flashcr = mfdcr (ebccfgd);
+		/* we map the flash high in every case */
+		flashcr&=0x0001FFFF; /* mask out address bits */
+		flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */
+		flashcr|= (((flash_info[0].size >>21) & 0x07) << 17); /* size addr */
+		mtdcr(ebccfga, pb1cr);
+		mtdcr(ebccfgd, flashcr);
+	}
+	else {
+		/* flash is on CS0 */
+		mtdcr(ebccfga, pb0cr);
+		flashcr = mfdcr (ebccfgd);
+		/* we map the flash high in every case */
+		flashcr&=0x0001FFFF; /* mask out address bits */
+		flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */
+		flashcr|= (((flash_info[0].size >>21) & 0x07) << 17); /* size addr */
+		mtdcr(ebccfga, pb0cr);
+		mtdcr(ebccfgd, flashcr);
+	}
 #if 0
-	/* include this if you want to test if
+	/* enable this if you want to test if
 	   the relocation has be done ok.
 	   This will disable both Chipselects */
 	mtdcr (ebccfga, pb0cr);
@@ -119,6 +228,14 @@ unsigned long flash_init (void)
 	mtdcr (ebccfgd, 0L);
 	printf("CS0 & CS1 switched off for test\n");
 #endif
+	/* patch version_string */
+	for(i=0;i<0x100;i++) {
+		if(*p=='\n') {
+			*p=0;
+			break;
+		}
+		p++;
+	}
 	return (size_b0);
 }
 
@@ -171,6 +288,8 @@ void flash_print_info  (flash_info_t *info)
 				break;
 	case FLASH_INTEL320T:	printf ("TE28F320C3 (32 Mbit, top sector size)\n");
 				break;
+	case FLASH_AM640U:	printf ("AM29LV640U (64 Mbit, uniform sector size)\n");
+				break;
 	default:		printf ("Unknown Chip Type\n");
 				break;
 	}
@@ -211,7 +330,8 @@ void flash_print_info  (flash_info_t *info)
 
 
 /*-----------------------------------------------------------------------
- */
+ 
+*/
 
 /*
  * The following code cannot be run from FLASH!
@@ -220,7 +340,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 {
 	short i;
 	FLASH_WORD_SIZE value;
-	ulong base = (ulong)addr;
+	ulong base;
 	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
 
 	/* Write auto select command: read Manufacturer ID */
@@ -250,7 +370,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		return (0);			/* no or unknown flash	*/
 	}
 	value = addr2[1];			/* device ID		*/
-	/*	printf("Device value %x\n",value); */
+	/*	printf("Device value %x\n",value); 		    */
 	switch (value) {
 	case (FLASH_WORD_SIZE)AMD_ID_F040B:
 		info->flash_id += FLASH_AM040;
@@ -292,12 +412,17 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		info->sector_count = 35;
 		info->size = 0x00200000;
 		break;				/* => 2 MB		*/
-#if 0	/* enable when device IDs are available */
 	case (FLASH_WORD_SIZE)AMD_ID_LV320T:
 		info->flash_id += FLASH_AM320T;
 		info->sector_count = 67;
 		info->size = 0x00400000;
 		break;				/* => 4 MB		*/
+	case (FLASH_WORD_SIZE)AMD_ID_LV640U:
+		info->flash_id += FLASH_AM640U;
+		info->sector_count = 128;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+#if 0	/* enable when device IDs are available */
 
 	case (FLASH_WORD_SIZE)AMD_ID_LV320B:
 		info->flash_id += FLASH_AM320B;
@@ -328,10 +453,12 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		return (0);			/* => no or unknown flash */
 
 	}
-
+	/* base address calculation */
+	base=0-info->size;
 	/* set up sector start address table */
 	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
-	     (info->flash_id  == FLASH_AM040)){
+	     (info->flash_id  == FLASH_AM040) ||
+	     (info->flash_id  == FLASH_AM640U)){
 		for (i = 0; i < info->sector_count; i++)
 			info->start[i] = base + (i * 0x00010000);
 	}

board/mpl/common/isa.c

@@ -32,7 +32,6 @@
 #include "kbd.h"
 #include "video.h"
 
-extern int drv_isa_kbd_init (void);
 
 #undef	ISA_DEBUG
 
@@ -49,6 +48,9 @@ extern int drv_isa_kbd_init (void);
 #define FALSE           0
 #endif
 
+#if defined(CONFIG_PIP405)
+
+extern int drv_isa_kbd_init (void);
 
 /* fdc (logical device 0) */
 const SIO_LOGDEV_TABLE sio_fdc[] = {
@@ -183,7 +185,7 @@ void isa_sio_setup(void)
 		close_cfg_super_IO(0x3F0);
 	}
 }
-
+#endif
 
 /******************************************************************************
  * IRQ Controller
@@ -202,7 +204,7 @@ static struct isa_irq_action isa_irqs[16];
 /*
  * This contains the irq mask for both 8259A irq controllers,
  */
-static unsigned int cached_irq_mask = 0xffff;
+static unsigned int cached_irq_mask = 0xfff9;
 
 #define cached_imr1	(unsigned char)cached_irq_mask
 #define cached_imr2	(unsigned char)(cached_irq_mask>>8)
@@ -387,19 +389,22 @@ int handle_isa_int(void)
 	isr2=in8(ISR_2);
 	isr1=in8(ISR_1);
 	irq=(unsigned char)irqack;
-	if((irq==7)&&((isr1&0x80)==0)) {
+	irq-=32;
+/*	if((irq==7)&&((isr1&0x80)==0)) {
 		PRINTF("IRQ7 detected but not in ISR\n");
 	}
 	else {
-		/* we should handle cascaded interrupts here also */
-		/* printf("ISA Irq %d\n",irq); */
-		isa_irqs[irq].count++;
-	if (isa_irqs[irq].handler != NULL)
-		(*isa_irqs[irq].handler)(isa_irqs[irq].arg);      /* call isr */
-	else
+*/		/* we should handle cascaded interrupts here also */
 	{
-	PRINTF ("bogus interrupt vector 0x%x\n", irq);
-	}
+/*		printf("ISA Irq %d\n",irq); */
+		isa_irqs[irq].count++;
+		if(irq!=2) { /* just swallow the cascade irq 2 */
+			if (isa_irqs[irq].handler != NULL)
+				(*isa_irqs[irq].handler)(isa_irqs[irq].arg);      /* call isr */
+			else {
+				PRINTF ("bogus interrupt vector 0x%x\n", irq);
+			}
+		}
 	}
 	/* issue EOI instruction to clear the IRQ */
 	mask_and_ack_8259A(irq);
@@ -413,13 +418,13 @@ int handle_isa_int(void)
 
 void isa_irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
 {
-  if (isa_irqs[vec].handler != NULL) {
-   printf ("ISA Interrupt vector %d: handler 0x%x replacing 0x%x\n",
-	   vec, (uint)handler, (uint)isa_irqs[vec].handler);
-  }
-  isa_irqs[vec].handler = handler;
-  isa_irqs[vec].arg     = arg;
-  enable_8259A_irq(vec);
+	if (isa_irqs[vec].handler != NULL) {
+		printf ("ISA Interrupt vector %d: handler 0x%x replacing 0x%x\n",
+			vec, (uint)handler, (uint)isa_irqs[vec].handler);
+	}
+	isa_irqs[vec].handler = handler;
+	isa_irqs[vec].arg     = arg;
+	enable_8259A_irq(vec);
 	PRINTF ("Install ISA IRQ %d ==> %p, @ %p mask=%04x\n", vec, handler, &isa_irqs[vec].handler,cached_irq_mask);
 
 }
@@ -427,9 +432,9 @@ void isa_irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
 void isa_irq_free_handler(int vec)
 {
 	disable_8259A_irq(vec);
-  isa_irqs[vec].handler = NULL;
-  isa_irqs[vec].arg     = NULL;
-	printf ("Free ISA IRQ %d mask=%04x\n", vec, cached_irq_mask);
+	isa_irqs[vec].handler = NULL;
+	isa_irqs[vec].arg     = NULL;
+	PRINTF ("Free ISA IRQ %d mask=%04x\n", vec, cached_irq_mask);
 
 }
 
@@ -448,16 +453,42 @@ void isa_init_irq_contr(void)
 	init_8259A();
 	out8(IMR_2,0xFF);
 }
+/*************************************************************************/
 
+void isa_show_irq(void)
+{
+	int vec;
+
+	printf ("\nISA Interrupt-Information:\n");
+	printf ("Nr  Routine   Arg       Count\n");
+
+	for (vec=0; vec<16; vec++) {
+		if (isa_irqs[vec].handler != NULL) {
+			printf ("%02d  %08lx  %08lx  %d\n",
+				vec,
+				(ulong)isa_irqs[vec].handler,
+				(ulong)isa_irqs[vec].arg,
+				isa_irqs[vec].count);
+		}
+	}
+}
+
+int isa_irq_get_count(int vec)
+{
+	return(isa_irqs[vec].count);
+}
 
 /******************************************************************
  * Init the ISA bus and devices.
  */
 
+#if defined(CONFIG_PIP405)
 
 int isa_init(void)
 {
 	isa_sio_setup();
+	isa_init_irq_contr();
 	drv_isa_kbd_init();
 	return 0;
 }
+#endif

board/mpl/common/isa.h

@@ -21,12 +21,12 @@
  * MA 02111-1307 USA
  */
 
-#ifndef _PIP405_ISA_H_
-#define _PIP405_ISA_H_
+#ifndef _ISA_H_
+#define _ISA_H_
 /* Super IO */
 #define SIO_CFG_PORT	0x3F0	/* Config Port Address */
 
-
+#if defined(CONFIG_PIP405)
 /* table fore SIO initialization */
 typedef struct {
 	const uchar index;
@@ -44,10 +44,14 @@ unsigned char read_cfg_super_IO(int address, unsigned char function, unsigned ch
 void write_cfg_super_IO(int address, unsigned char function, unsigned char regaddr, unsigned char data);
 void close_cfg_super_IO(int address);
 void isa_sio_setup(void);
-void isa_sio_setup(void);
+#endif
+
 void isa_irq_install_handler(int vec, interrupt_handler_t *handler, void *arg);
 void isa_irq_free_handler(int vec);
 int handle_isa_int(void);
+void isa_init_irq_contr(void);
+void isa_show_irq(void);
+int isa_irq_get_count(int vec);
 
 
 #endif

board/mpl/common/pci_parts.h

@@ -92,7 +92,7 @@ extern void pci_pip405_write_regs(struct pci_controller *,
 /* PIIX4 ISA Bridge Function 0 */
 static struct pci_pip405_config_entry piix4_isa_bridge_f0[] = {
 	{PCI_CFG_PIIX4_SERIRQ,	0xD0,		1}, /* enable Continous SERIRQ Pin */
-	{PCI_CFG_PIIX4_GENCFG,	0x00010041,	4}, /* enable SERIRQs, ISA, PNP	*/
+	{PCI_CFG_PIIX4_GENCFG,	0x00018041,	4}, /* enable SERIRQs, ISA, PNP, GPI11 */
 	{PCI_CFG_PIIX4_TOM,	0xFE,		1}, /* Top of Memory		*/
 	{PCI_CFG_PIIX4_XBCS,	0x02C4,		2}, /* disable all peri CS	*/
 	{PCI_CFG_PIIX4_RTCCFG,	0x21,		1}, /* enable RTC	   	*/
@@ -106,6 +106,7 @@ static struct pci_pip405_config_entry piix4_isa_bridge_f0[] = {
 
 /* PIIX4 IDE Controller Function 1 */
 static struct pci_pip405_config_entry piix4_ide_cntrl_f1[] = {
+	{PCI_CFG_PIIX4_BMIBA,	0x0001000,	4}, /* set BMI to a valid address */
 	{PCI_COMMAND,		0x0001,		2}, /* enable IO access 	*/
 #if !defined(CONFIG_MIP405T)
 	{PCI_CFG_PIIX4_IDETIM,	0x80008000,	4}, /* enable Both IDE channels	*/
@@ -129,10 +130,10 @@ static struct pci_pip405_config_entry piix4_usb_cntrl_f2[] = {
 
 /* PIIX4 Power Management Function 3 */
 static struct pci_pip405_config_entry piix4_pmm_cntrl_f3[] = {
-	{PCI_COMMAND,		0x0001,		2}, /* enable IO access 	*/
-	{PCI_CFG_PIIX4_PMAB,	0x00004000,	4}, /* set PMBA to "valid" value */
-	{PCI_CFG_PIIX4_PMMISC,	0x01,		1}, /* enable PMBA IO access	*/
+	{PCI_CFG_PIIX4_PMBA,	0x00004000,	4}, /* set PMBA to "valid" value */
 	{PCI_CFG_PIIX4_SMBBA,	0x00005000,	4}, /* set SMBBA to "valid" value */
+	{PCI_CFG_PIIX4_PMMISC,	0x01,		1}, /* enable PMBA IO access	*/
+	{PCI_COMMAND,		0x0001,		2}, /* enable IO access 	*/
 	{ }					    /* end of device table 	*/
 };
 /* PPC405 Dummy only used to prevent autosetup on this host bridge */

board/mpl/common/piix4_pci.h

@@ -143,7 +143,7 @@
 #define	PCI_CFG_PIIX4_LEGSUP	0xC0
 
 /* Function 3 Power Management */
-#define	PCI_CFG_PIIX4_PMAB		0x40
+#define	PCI_CFG_PIIX4_PMBA		0x40
 #define	PCI_CFG_PIIX4_CNTA		0x44
 #define	PCI_CFG_PIIX4_CNTB		0x48
 #define	PCI_CFG_PIIX4_GPICTL	0x4C

board/mpl/mip405/cmd_mip405.c

@@ -54,10 +54,13 @@ int do_mip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return (do_mplcommon(cmdtp, flag, argc, argv));
 }
 U_BOOT_CMD(
-	mip405,	6,	1,	do_mip405,
+	mip405,	8,	1,	do_mip405,
 	"mip405  - MIP405 specific Cmds\n",
 	"flash mem [SrcAddr] - updates U-Boot with image in memory\n"
 	"mip405 flash mps - updates U-Boot with image from MPS\n"
+	"mip405 info      - displays board information\n"
+	"mip405 led <on>  - switches LED on (on=1) or off (on=0)\n"
+	"mip405 mem [cnt] - Memory Test <cnt>-times, <cnt> = -1 loop forever\n"
 );
 
 /* ------------------------------------------------------------------------- */

board/mpl/mip405/init.S

@@ -87,19 +87,15 @@ ext_bus_cntlr_init:
 	mfdcr		r4,ebccfgd
 
 	andi.		r0, r4, 0x2000			/* mask out irrelevant bits */
-	beq			0f						/* jump if 8 bit bus width */
+	beq		0f				/* jump if 8 bit bus width */
 
-	/* setup 16 bit things (Flash Boot)
+	/* setup 16 bit things
    *-----------------------------------------------------------------------
    * Memory Bank 0 (16 Bit Flash) initialization
    *---------------------------------------------------------------------- */
 
 	addi    r4,0,pb0ap
 	mtdcr   ebccfga,r4
-/*	addis   r4,0,0xFF8F */
-/*	ori     r4,r4,0xFE80 */
-/*	addis   r4,0,0x9B01 */
-/*	ori     r4,r4,0x5480 */
 	addis   r4,0,(FLASH_AP_B)@h
 	ori     r4,r4,(FLASH_AP_B)@l
 	mtdcr   ebccfgd,r4
@@ -107,8 +103,6 @@ ext_bus_cntlr_init:
 	addi    r4,0,pb0cr
 	mtdcr   ebccfga,r4
 	/* BS=0x010(4MB),BU=0x3(R/W), */
-/*	addis   r4,0,((FLASH_BASE0_PRELIM & 0xFFF00000) | 0x00050000)@h */
-/*	ori     r4,r4,0xA000          / * BW=0x01(16 bits) */
 	addis   r4,0,(FLASH_CR_B)@h
 	ori     r4,r4,(FLASH_CR_B)@l
 	mtdcr   ebccfgd,r4
@@ -123,21 +117,13 @@ ext_bus_cntlr_init:
 	/* 0x7F8FFE80 slowest boot */
 	addi    r4,0,pb0ap
 	mtdcr   ebccfga,r4
-#if 0
-	addis   r4,0,0x9B01
-	ori     r4,r4,0x5480
-#else
 	addis   r4,0,(MPS_AP_B)@h
 	ori     r4,r4,(MPS_AP_B)@l
-#endif
 	mtdcr   ebccfgd,r4
 
 	addi    r4,0,pb0cr
 	mtdcr   ebccfga,r4
 	/* BS=0x010(4MB),BU=0x3(R/W), */
-/*	addis   r4,0,((FLASH_BASE0_PRELIM & 0xFFF00000) | 0x00050000)@h */
-/*	ori     r4,r4,0x8000          / * BW=0x0( 8 bits) */
-
 	addis   r4,0,(MPS_CR_B)@h
 	ori     r4,r4,(MPS_CR_B)@l
 
@@ -178,18 +164,18 @@ ext_bus_cntlr_init:
   ori     r4,r4,0x0000
   mtdcr   ebccfgd,r4
 
-	addi    r4,0,pb6cr
+  addi    r4,0,pb6cr
   mtdcr   ebccfga,r4
   addis   r4,0,0x0000
   ori     r4,r4,0x0000
   mtdcr   ebccfgd,r4
 
-	addi    r4,0,pb7cr
+  addi    r4,0,pb7cr
   mtdcr   ebccfga,r4
   addis   r4,0,0x0000
   ori     r4,r4,0x0000
   mtdcr   ebccfgd,r4
-	nop				/* pass2 DCR errata #8 */
+  nop				/* pass2 DCR errata #8 */
   blr
 
 /*-----------------------------------------------------------------------------

board/mpl/mip405/mip405.c

@@ -667,9 +667,16 @@ static int test_dram (unsigned long ramsize)
 /* used to check if the time in RTC is valid */
 static unsigned long start;
 static struct rtc_time tm;
+extern flash_info_t flash_info[];	/* info for FLASH chips */
 
 int misc_init_r (void)
 {
+	DECLARE_GLOBAL_DATA_PTR;
+	/* adjust flash start and size as well as the offset */
+	gd->bd->bi_flashstart=0-flash_info[0].size;
+	gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN;
+	gd->bd->bi_flashoffset=0;
+
 	/* check, if RTC is running */
 	rtc_get (&tm);
 	start=get_timer(0);

board/mpl/mip405/mip405.h

@@ -137,13 +137,13 @@ void user_led0(unsigned char on);
 					(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
 
 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define FLASH_BS	2	/* 4 MByte */
+#define FLASH_BS	FLASH_SIZE_PRELIM	/* 4 MByte */
 /* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
 #define FLASH_BU	3	/* R/W */
 /* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
 #define FLASH_BW	1	/* 16Bit */
 /* CR register for Boot */
-#define FLASH_CR_B	((FLASH_BASE0_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
+#define FLASH_CR_B	((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
 /* CR register for non Boot */
 #define FLASH_CR	((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
 
@@ -172,11 +172,12 @@ void user_led0(unsigned char on);
 
 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
 #define MPS_BS		2	/* 4 MByte */
+#define MPS_BS_B		FLASH_SIZE_PRELIM	/* 1 MByte */
 /* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
 #define MPS_BU		3	/* R/W */
 /* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
 #define MPS_BW		0	/* 8Bit */
 /* CR register for Boot */
-#define MPS_CR_B	((FLASH_BASE0_PRELIM & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
+#define MPS_CR_B	((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS_B << 17) + (MPS_BU << 15) + (MPS_BW << 13))
 /* CR register for non Boot */
 #define MPS_CR		((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))

board/mpl/pip405/init.S

@@ -41,17 +41,21 @@
 
 #define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
 
-#include "configs/PIP405.h"
+#include <configs/PIP405.h>
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
 #include <asm/cache.h>
 #include <asm/mmu.h>
+#include "pip405.h"
 
+  .globl ext_bus_cntlr_init
+ ext_bus_cntlr_init:
+  mflr   r4                      /* save link register */
+  mfdcr  r3,strap                /* get strapping reg */
+  andi.  r0, r3, PSR_ROM_LOC     /* mask out irrelevant bits */
+  bnelr                          /* jump back if PCI boot */
 
-	.globl	ext_bus_cntlr_init
-ext_bus_cntlr_init:
-  mflr    r4                      /* save link register */
   bl      ..getAddr
 ..getAddr:
   mflr    r3                      /* get address of ..getAddr */
@@ -82,7 +86,7 @@ ext_bus_cntlr_init:
 	mfdcr		r4,ebccfgd
 
 	andi.		r0, r4, 0x2000			/* mask out irrelevant bits */
-	beq			0f									/* jump if 8 bit bus width */
+	beq		0f				/* jump if 8 bit bus width */
 
 	/* setup 16 bit things
    *-----------------------------------------------------------------------
@@ -90,74 +94,49 @@ ext_bus_cntlr_init:
    *---------------------------------------------------------------------- */
 
 	addi    r4,0,pb0ap
-  mtdcr   ebccfga,r4
-  addis   r4,0,0x9B01
-  ori     r4,r4,0x5480
-  mtdcr   ebccfgd,r4
+	mtdcr   ebccfga,r4
+	addis   r4,0,(FLASH_AP_B)@h
+	ori     r4,r4,(FLASH_AP_B)@l
+	mtdcr   ebccfgd,r4
 
-  addi    r4,0,pb0cr
-  mtdcr   ebccfga,r4
-	/* BS=0x011(8MB),BU=0x3(R/W), */
-  addis   r4,0,((FLASH_BASE0_PRELIM & 0xFFF00000) | 0x00050000)@h
-  ori     r4,r4,0xA000          /* BW=0x01(16 bits) */
-  mtdcr   ebccfgd,r4
-
-  /*-----------------------------------------------------------------------
-   * Memory Bank 1 (Multi Purpose Socket) initialization
-   *----------------------------------------------------------------------*/
-  addi    r4,0,pb1ap
-  mtdcr   ebccfga,r4
-  addis   r4,0,0x0281
-  ori     r4,r4,0x5480
-  mtdcr   ebccfgd,r4
-
-  addi    r4,0,pb1cr
-  mtdcr   ebccfga,r4
-  /* BS=0x011(8MB),BU=0x3(R/W), */
-  addis   r4,0,((MULTI_PURPOSE_SOCKET_ADDR & 0xFFF00000) | 0x00050000)@h
-  ori     r4,r4,0x8000          /* BW=0x0( 8 bits) */
-  mtdcr   ebccfgd,r4
+	addi    r4,0,pb0cr
+	mtdcr   ebccfga,r4
+	/* BS=0x010(4MB),BU=0x3(R/W), */
+	addis   r4,0,(FLASH_CR_B)@h
+	ori     r4,r4,(FLASH_CR_B)@l
+	mtdcr   ebccfgd,r4
 	b				1f
 
 0:
-  /* 8Bit boot mode: */
+	/* 8Bit boot mode: */
 	/*-----------------------------------------------------------------------
-   * Memory Bank 0 Multi Purpose Socket initialization
-   *----------------------------------------------------------------------- */
-
+	* Memory Bank 0 Multi Purpose Socket initialization
+	*----------------------------------------------------------------------- */
+	/* 0x7F8FFE80 slowest boot */
 	addi    r4,0,pb0ap
-  mtdcr   ebccfga,r4
-  addis   r4,0,0x9B01
-  ori     r4,r4,0x5480
-  mtdcr   ebccfgd,r4
+	mtdcr   ebccfga,r4
+	addis   r4,0,(MPS_AP_B)@h
+	ori     r4,r4,(MPS_AP_B)@l
+	mtdcr   ebccfgd,r4
 
-  addi    r4,0,pb0cr
-  mtdcr   ebccfga,r4
-	/* BS=0x011(4MB),BU=0x3(R/W), */
-  addis   r4,0,((FLASH_BASE0_PRELIM & 0xFFF00000) | 0x00050000)@h
-  ori     r4,r4,0x8000          /* BW=0x0( 8 bits) */
-  mtdcr   ebccfgd,r4
+	addi    r4,0,pb0cr
+	mtdcr   ebccfga,r4
+	/* BS=0x010(4MB),BU=0x3(R/W), */
+	addis   r4,0,(MPS_CR_B)@h
+	ori     r4,r4,(MPS_CR_B)@l
+	mtdcr   ebccfgd,r4
 
-  /*-----------------------------------------------------------------------
-   * Memory Bank 1 (Flash) initialization
-   *-----------------------------------------------------------------------*/
-  addi    r4,0,pb1ap
-  mtdcr   ebccfga,r4
-  addis   r4,0,0x0281
-  ori     r4,r4,0x5480
-  mtdcr   ebccfgd,r4
-
-  addi    r4,0,pb1cr
-  mtdcr   ebccfga,r4
-  /* BS=0x011(8MB),BU=0x3(R/W), */
-  addis   r4,0,((MULTI_PURPOSE_SOCKET_ADDR & 0xFFF00000) | 0x00050000)@h
-  ori     r4,r4,0xA000          /* BW=0x0( 8 bits) */
-  mtdcr   ebccfgd,r4
 
 1:
   /*-----------------------------------------------------------------------
    * Memory Bank 2-3-4-5-6 (not used) initialization
    *-----------------------------------------------------------------------*/
+  addi    r4,0,pb1cr
+  mtdcr   ebccfga,r4
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
+  mtdcr   ebccfgd,r4
+
   addi    r4,0,pb2cr
   mtdcr   ebccfga,r4
   addis   r4,0,0x0000
@@ -182,28 +161,18 @@ ext_bus_cntlr_init:
   ori     r4,r4,0x0000
   mtdcr   ebccfgd,r4
 
-	addi    r4,0,pb6cr
+  addi    r4,0,pb6cr
   mtdcr   ebccfga,r4
   addis   r4,0,0x0000
   ori     r4,r4,0x0000
-  mtdcr   ebccfgd,r4
-
-	/*-----------------------------------------------------------------------
-   * Memory Bank 7 (Config Register) initialization
-   *----------------------------------------------------------------------- */
-  addi    r4,0,pb7ap
-  mtdcr   ebccfga,r4
-  addis   r4,0,0x0181	      /* Doc says TWT=3 and Openios TWT=3!! */
-  ori     r4,r4,0x5280          /* disable Ready, BEM=0 */
   mtdcr   ebccfgd,r4
 
   addi    r4,0,pb7cr
   mtdcr   ebccfga,r4
-	/* BS=0x0(1MB),BU=0x3(R/W), */
-  addis   r4,0,((CONFIG_PORT_ADDR & 0xFFF00000) | 0x00010000)@h
-  ori     r4,r4,0x8000            /* BW=0x0(8 bits) */
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
   mtdcr   ebccfgd,r4
-	nop				/* pass2 DCR errata #8 */
+  nop				/* pass2 DCR errata #8 */
   blr
 
 /*-----------------------------------------------------------------------------
@@ -217,3 +186,45 @@ sdram_init:
 
 
   blr
+
+
+#if defined(CONFIG_BOOT_PCI)
+    .section .bootpg,"ax"
+    .globl _start_pci
+/*******************************************
+ */
+
+_start_pci:
+  /* first handle errata #68 / PCI_18 */
+  iccci   r0, r0          /* invalidate I-cache */
+  lis     r31, 0
+  mticcr  r31             /* ICCR = 0 (all uncachable) */
+  isync
+
+  mfccr0  r28             /* set CCR0[24] = 1 */
+  ori     r28, r28, 0x0080
+  mtccr0  r28
+
+  /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */
+  lis     r28, 0xEF40
+  addi    r28, r28, 0x0004
+  stw     r31, 0x0C(r28)  /* clear PMM0PCIHA */
+  lis     r29, 0xFFF8     /* open 512 kByte */
+  addi    r29, r29, 0x0001/* and enable this region */
+  stwbrx  r29, r0, r28    /* write PMM0MA */
+
+  lis     r28, 0xEEC0     /* address of PCIC0_CFGADDR */
+  addi    r29, r28, 4     /* add 4 to r29 -> PCIC0_CFGDATA */
+
+  lis     r31, 0x8000     /* set en bit bus 0 */
+  ori     r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */
+  stwbrx  r31, r0, r28    /* write it */
+
+  lwbrx   r31, r0, r29    /* load XBCS register */
+  oris    r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */
+  stwbrx  r31, r0, r29    /* write back XBCS register */
+
+  nop
+  nop
+  b	_start		/* normal start */
+#endif

board/mpl/pip405/pip405.c

@@ -194,6 +194,11 @@ int board_pre_init (void)
 #ifdef SDRAM_DEBUG
 	DECLARE_GLOBAL_DATA_PTR;
 #endif
+	/* set up the config port */
+	mtdcr (ebccfga, pb7ap);
+	mtdcr (ebccfgd, CONFIG_PORT_AP);
+	mtdcr (ebccfga, pb7cr);
+	mtdcr (ebccfgd, CONFIG_PORT_CR);
 
 	memclk = get_bus_freq (tmemclk);
 	tmemclk = 1000000000 / (memclk / 100);	/* in 10 ps units */
@@ -657,8 +662,20 @@ static int test_dram (unsigned long ramsize)
 }
 
 
+extern flash_info_t flash_info[];	/* info for FLASH chips */
+
 int misc_init_r (void)
 {
+	DECLARE_GLOBAL_DATA_PTR;
+	/* adjust flash start and size as well as the offset */
+	gd->bd->bi_flashstart=0-flash_info[0].size;
+	gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN;
+	gd->bd->bi_flashoffset=0;
+
+	/* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
+	if (mfdcr(strap) & PSR_ROM_LOC)
+	       mtspr(ccr0, (mfspr(ccr0) & ~0x80));
+
 	return (0);
 }
 

board/mpl/pip405/pip405.h

@@ -25,6 +25,7 @@
  * Global routines used for PIP405
  *****************************************************************************/
 
+#ifndef __ASSEMBLY__
 
 extern int  mem_test(unsigned long start, unsigned long ramsize,int mode);
 
@@ -35,13 +36,13 @@ void user_led1(unsigned char on);
 
 
 #define PLD_BASE_ADDRESS		CFG_ISA_IO_BASE_ADDRESS + 0x800
-#define PLD_PART_REG				PLD_BASE_ADDRESS + 0
-#define PLD_VERS_REG				PLD_BASE_ADDRESS + 1
+#define PLD_PART_REG			PLD_BASE_ADDRESS + 0
+#define PLD_VERS_REG			PLD_BASE_ADDRESS + 1
 #define PLD_BOARD_CFG_REG		PLD_BASE_ADDRESS + 2
 #define PLD_LED_USER_REG		PLD_BASE_ADDRESS + 3
 #define PLD_SYS_MAN_REG			PLD_BASE_ADDRESS + 4
 #define PLD_FLASH_COM_REG		PLD_BASE_ADDRESS + 5
-#define PLD_CAN_REG					PLD_BASE_ADDRESS + 6
+#define PLD_CAN_REG			PLD_BASE_ADDRESS + 6
 #define PLD_SER_PWR_REG			PLD_BASE_ADDRESS + 7
 #define PLD_COM_PWR_REG			PLD_BASE_ADDRESS + 8
 #define PLD_NIC_VGA_REG			PLD_BASE_ADDRESS + 9
@@ -50,86 +51,32 @@ void user_led1(unsigned char on);
 #define PIIX4_VENDOR_ID			0x8086
 #define PIIX4_IDE_DEV_ID		0x7111
 
-
-/* timings */
-/* PLD (CS7) */
-#define PLD_BME	0 	/* Burst disable */
-#define PLD_TWE	5	/* 5 * 30ns 120ns Waitstates (access=TWT+1+TH) */
-#define PLD_CSN	1	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
-#define PLD_OEN	1	/* Cycles from CS low to OE low   */
-#define PLD_WBN	1	/* Cycles from CS low to WE low   */
-#define PLD_WBF	1	/* Cycles from WE high to CS high */
-#define PLD_TH	2	/* Number of hold cycles after transfer */
-#define PLD_RE	0	/* Ready disabled */
-#define PLD_SOR	1	/* Sample on Ready disabled */
-#define PLD_BEM	0	/* Byte Write only active on Write cycles */
-#define PLD_PEN	0	/* Parity disable */
-#define PLD_AP 	((PLD_BME << 31) + (PLD_TWE << 23) + (PLD_CSN << 18) + (PLD_OEN << 16) + (PLD_WBN << 14) + \
-					(PLD_WBF << 12) + (PLD_TH << 9) + (PLD_RE << 8) + (PLD_SOR << 7) + (PLD_BEM << 6) + (PLD_PEN << 5))
-
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define PLD_BS	0	/* 1 MByte */
-/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
-#define PLD_BU	3	/* R/W */
-/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
-#define PLD_BW	0	/* 16Bit */
-#define PLD_CR	((PER_PLD_ADDR & 0xfff00000) + (PLD_BS << 17) + (PLD_BU << 15) + (PLD_BW << 13))
-
+#endif
 
 /* timings */
 
-#define PER_BOARD_ADDR (PER_UART1_ADDR+(1024*1024))
-/* Dummy CS to get the board revision */
-#define BOARD_BME	0 	/* Burst disable */
-#define BOARD_TWE	255	/* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */
-#define BOARD_CSN	1	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
-#define BOARD_OEN	1	/* Cycles from CS low to OE low   */
-#define BOARD_WBN	1	/* Cycles from CS low to WE low   */
-#define BOARD_WBF	1	/* Cycles from WE high to CS high */
-#define BOARD_TH	2	/* Number of hold cycles after transfer */
-#define BOARD_RE	0	/* Ready disabled */
-#define BOARD_SOR	1	/* Sample on Ready disabled */
-#define BOARD_BEM	0	/* Byte Write only active on Write cycles */
-#define BOARD_PEN	0	/* Parity disable */
-#define BOARD_AP 	((BOARD_BME << 31) + (BOARD_TWE << 23) + (BOARD_CSN << 18) + (BOARD_OEN << 16) + (BOARD_WBN << 14) + \
-					(BOARD_WBF << 12) + (BOARD_TH << 9) + (BOARD_RE << 8) + (BOARD_SOR << 7) + (BOARD_BEM << 6) + (BOARD_PEN << 5))
+/* CS Config register (CS7) */
+#define CONFIG_PORT_BME	0 	/* Burst disable */
+#define CONFIG_PORT_TWE	255	/* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */
+#define CONFIG_PORT_CSN	1	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
+#define CONFIG_PORT_OEN	1	/* Cycles from CS low to OE low   */
+#define CONFIG_PORT_WBN	1	/* Cycles from CS low to WE low   */
+#define CONFIG_PORT_WBF	1	/* Cycles from WE high to CS high */
+#define CONFIG_PORT_TH	2	/* Number of hold cycles after transfer */
+#define CONFIG_PORT_RE	0	/* Ready disabled */
+#define CONFIG_PORT_SOR	1	/* Sample on Ready disabled */
+#define CONFIG_PORT_BEM	0	/* Byte Write only active on Write cycles */
+#define CONFIG_PORT_PEN	0	/* Parity disable */
+#define CONFIG_PORT_AP 	((CONFIG_PORT_BME << 31) + (CONFIG_PORT_TWE << 23) + (CONFIG_PORT_CSN << 18) + (CONFIG_PORT_OEN << 16) + (CONFIG_PORT_WBN << 14) + \
+				(CONFIG_PORT_WBF << 12) + (CONFIG_PORT_TH << 9) + (CONFIG_PORT_RE << 8) + (CONFIG_PORT_SOR << 7) + (CONFIG_PORT_BEM << 6) + (CONFIG_PORT_PEN << 5))
 
 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define BOARD_BS	0	/* 1 MByte */
+#define CONFIG_PORT_BS	0	/* 1 MByte */
 /* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
-#define BOARD_BU	3	/* R/W */
+#define CONFIG_PORT_BU	3	/* R/W */
 /* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
-#define BOARD_BW	0	/* 16Bit */
-#define BOARD_CR	((PER_BOARD_ADDR & 0xfff00000) + (BOARD_BS << 17) + (BOARD_BU << 15) + (BOARD_BW << 13))
-
-
-/* UART0 CS2 */
-#define UART0_BME	0 	/* Burst disable */
-#define UART0_TWE	7	/* 7 * 30ns 210ns Waitstates (access=TWT+1+TH) */
-#define UART0_CSN	1	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
-#define UART0_OEN	1	/* Cycles from CS low to OE low   */
-#define UART0_WBN	1	/* Cycles from CS low to WE low   */
-#define UART0_WBF	1	/* Cycles from WE high to CS high */
-#define UART0_TH	2	/* Number of hold cycles after transfer */
-#define UART0_RE	0	/* Ready disabled */
-#define UART0_SOR	1	/* Sample on Ready disabled */
-#define UART0_BEM	0	/* Byte Write only active on Write cycles */
-#define UART0_PEN	0	/* Parity disable */
-#define UART0_AP 	((UART0_BME << 31) + (UART0_TWE << 23) + (UART0_CSN << 18) + (UART0_OEN << 16) + (UART0_WBN << 14) + \
-					(UART0_WBF << 12) + (UART0_TH << 9) + (UART0_RE << 8) + (UART0_SOR << 7) + (UART0_BEM << 6) + (UART0_PEN << 5))
-
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define UART0_BS	0	/* 1 MByte */
-/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
-#define UART0_BU	3	/* R/W */
-/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
-#define UART0_BW	0	/* 8Bit */
-#define UART0_CR	((PER_UART0_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13))
-
-/* UART1 CS3 */
-#define UART1_AP UART0_AP /* same timing as UART0 */
-#define UART1_CR	((PER_UART1_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13))
-
+#define CONFIG_PORT_BW	0	/* 16Bit */
+#define CONFIG_PORT_CR	((CONFIG_PORT_ADDR & 0xfff00000) + (CONFIG_PORT_BS << 17) + (CONFIG_PORT_BU << 15) + (CONFIG_PORT_BW << 13))
 
 /* Flash CS0 or CS 1 */
 /* 0x7F8FFE80 slowest timing at all... */
@@ -149,19 +96,19 @@ void user_led1(unsigned char on);
 #define FLASH_PEN	0	/* Parity disable */
 /* Access Parameter Register for non Boot */
 #define FLASH_AP 	((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
-					(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
+				(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
 /* Access Parameter Register for Boot */
 #define FLASH_AP_B 	((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
-					(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
+				(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
 
 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define FLASH_BS	2	/* 4 MByte */
+#define FLASH_BS	FLASH_SIZE_PRELIM	/* 4 MByte */
 /* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
 #define FLASH_BU	3	/* R/W */
 /* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
 #define FLASH_BW	1	/* 16Bit */
 /* CR register for Boot */
-#define FLASH_CR_B	((FLASH_BASE0_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
+#define FLASH_CR_B	((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
 /* CR register for non Boot */
 #define FLASH_CR	((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
 
@@ -183,18 +130,19 @@ void user_led1(unsigned char on);
 #define MPS_PEN		0	/* Parity disable */
 /* Access Parameter Register for non Boot */
 #define MPS_AP 		((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
-					(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
+				(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
 /* Access Parameter Register for Boot */
-#define MPS_AP_B 		((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
-					(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
+#define MPS_AP_B 	((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
+				(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
 
 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
 #define MPS_BS		2	/* 4 MByte */
+#define MPS_BS_B		FLASH_SIZE_PRELIM	/* 1 MByte */
 /* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
 #define MPS_BU		3	/* R/W */
 /* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
 #define MPS_BW		0	/* 8Bit */
 /* CR register for Boot */
-#define MPS_CR_B	((FLASH_BASE0_PRELIM & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
+#define MPS_CR_B	((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
 /* CR register for non Boot */
 #define MPS_CR		((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))

board/mpl/vcma9/vcma9.c

@@ -144,7 +144,7 @@ int dram_init(void)
  * NAND flash initialization.
  */
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
-extern void
+extern ulong
 nand_probe(ulong physadr);
 
 
@@ -177,10 +177,15 @@ void
 nand_init(void)
 {
 	S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+	unsigned totlen;
 
 	NF_Init();
+#ifdef DEBUG
 	printf("NAND flash probing at 0x%.8lX\n", (ulong)nand);
-	nand_probe((ulong)nand);
+#endif
+	totlen = nand_probe((ulong)nand) >> 20;
+
+	printf ("%4lu MB\n", totlen >> 20);
 }
 #endif
 

board/netvia/netvia.c

@@ -420,16 +420,13 @@ int board_pre_init(void)
 
 #include <linux/mtd/nand.h>
 
-extern void nand_probe(ulong physadr);
+extern ulong nand_probe(ulong physadr);
 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
 
 void nand_init(void)
 {
-	nand_probe(CFG_NAND_BASE);
-	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
-		nand_dev_desc[0].name = "NetVia NAND flash";
-		puts("NAND:  ");
-		print_size(nand_dev_desc[0].totlen, "\n");
-	}
+	unsigned long totlen = nand_probe(CFG_NAND_BASE);
+
+	printf ("%4lu MB\n", totlen >> 20);
 }
 #endif

board/sixnet/flash.c

@@ -23,6 +23,10 @@
 
 #include <common.h>
 #include <mpc8xx.h>
+/* environment.h defines the various CFG_ENV_... values in terms
+ * of whichever ones are given in the configuration file.
+ */
+#include <environment.h>
 
 flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
@@ -104,6 +108,19 @@ unsigned long flash_init (void)
 		      &flash_info[0]);
 #endif
 
+#ifdef CFG_ENV_ADDR
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+#endif
+
+#ifdef CFG_ENV_ADDR_REDUND
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR_REDUND,
+			CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
+			&flash_info[0]);
+#endif
+
 	return (size_b);
 }
 
@@ -154,6 +171,21 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
 		for( i = 0; i < info->sector_count; i++ )
 			info->start[i] = base + (i * sect_size);
 	}
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
+		 && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM800T) {
+
+		int sect_size;		/* number of bytes/sector */
+
+		sect_size = 0x00010000 * (sizeof(FPW)/2);
+
+		/* set up sector start address table (top boot sector type) */
+		for (i = 0; i < info->sector_count - 3; i++)
+			info->start[i] = base + (i * sect_size);
+		i = info->sector_count - 1;
+		info->start[i--] = base + (info->size - 0x00004000) * (sizeof(FPW)/2);
+		info->start[i--] = base + (info->size - 0x00006000) * (sizeof(FPW)/2);
+		info->start[i--] = base + (info->size - 0x00008000) * (sizeof(FPW)/2);
+	}
 }
 
 /*-----------------------------------------------------------------------
@@ -196,6 +228,9 @@ void flash_print_info (flash_info_t *info)
 	}
 
 	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM800T:
+		fmt = "29LV800B%s (8 Mbit, %s)\n";
+		break;
 	case FLASH_AM640U:
 		fmt = "29LV641D (64 Mbit, uniform sectors)\n";
 		break;
@@ -295,6 +330,12 @@ ulong flash_get_size (FPWV *addr, flash_info_t *info)
 	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
 	if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) {
 
+	case (FPW)AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000 * (sizeof(FPW)/2);
+		break;				/* => 1 or 2 MiB	*/
+
 	case (FPW)AMD_ID_LV640U:	/* 29LV640 and 29LV641 have same ID */
 		info->flash_id += FLASH_AM640U;
 		info->sector_count = 128;
@@ -401,6 +442,7 @@ static void flash_sync_real_protect(flash_info_t *info)
 	break;
 
     case FLASH_AM640U:
+    case FLASH_AM800T:
     default:
 	/* no hardware protect that we support */
 	break;
@@ -438,6 +480,7 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 	case FLASH_28F320C3B:
 	case FLASH_28F640C3B:
 	case FLASH_AM640U:
+	case FLASH_AM800T:
 		break;
 	case FLASH_UNKNOWN:
 	default:
@@ -735,6 +778,7 @@ int flash_real_protect (flash_info_t * info, long sector, int prot)
 		break;
 
 	case FLASH_AM640U:
+	case FLASH_AM800T:
 	default:
 		/* no hardware protect that we support */
 		info->protect[sector] = prot;

board/sixnet/sixnet.c

@@ -24,6 +24,7 @@
 
 #include <common.h>
 #include <config.h>
+#include <jffs2/jffs2.h>
 #include <mpc8xx.h>
 #include <net.h>	/* for eth_init() */
 #include <rtc.h>
@@ -329,11 +330,9 @@ int misc_init_r (void)
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
 void nand_init(void)
 {
-	nand_probe(CFG_DFLASH_BASE);	/* see if any NAND flash present */
-	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
-		puts("NAND:  ");
-		print_size(nand_dev_desc[0].totlen, "\n");
-	}
+	unsigned long totlen = nand_probe(CFG_NAND_BASE);
+
+	printf ("%4lu MB\n", totlen >> 20);
 }
 #endif
 
@@ -602,3 +601,70 @@ long int initdram(int board_type)
 
 	return (size_sdram);
 }
+
+#ifdef CFG_JFFS_CUSTOM_PART
+
+static struct part_info part;
+
+#define jffs2_block(i)	\
+	((struct jffs2_unknown_node*)(CFG_JFFS2_BASE + (i) * 65536))
+
+struct part_info* jffs2_part_info(int part_num)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	bd_t *bd = gd->bd;
+	char* s;
+	int i;
+	int bootnor = 0;	/* assume booting from NAND flash */
+
+	if (part_num != 0)
+		return 0;	/* only support one partition */
+
+	if (part.usr_priv == (void*)1)
+		return &part;	/* already have part info */
+
+	memset(&part, 0, sizeof(part));
+
+	if (nand_dev_desc[0].ChipID == NAND_ChipID_UNKNOWN)
+		bootnor = 1;
+	else if (bd->bi_flashsize < 0x800000)
+		bootnor = 0;
+	else for (i = 0; !bootnor && i < 4; ++i) {
+		/* boot from NOR if JFFS2 info in any of
+		 * first 4 erase blocks
+		 */
+
+		if (jffs2_block(i)->magic == JFFS2_MAGIC_BITMASK)
+			bootnor = 1;
+	}
+
+	if (bootnor) {
+		/* no NAND flash or boot in NOR, use NOR flash */
+		part.offset = (unsigned char *)CFG_JFFS2_BASE;
+		part.size = CFG_JFFS2_SIZE;
+	}
+	else {
+		char readcmd[60];
+
+		/* boot info in NAND flash, get and use copy in RAM */
+
+		/* override info from environment if present */
+		s = getenv("fsaddr");
+		part.offset = s ? (void *)simple_strtoul(s, NULL, 16)
+				: (void *)CFG_JFFS2_RAMBASE;
+		s = getenv("fssize");
+		part.size = s ? simple_strtoul(s, NULL, 16)
+			      : CFG_JFFS2_RAMSIZE;
+
+		/* read from nand flash */
+		sprintf(readcmd, "nand read.jffs2 %x 0 %x",
+			(uint32_t)part.offset, part.size);
+		run_command(readcmd, 0);
+	}
+
+	part.erasesize = 0;	/* unused */
+	part.usr_priv=(void*)1;	/* ready */
+
+	return &part;
+}
+#endif /* ifdef CFG_JFFS_CUSTOM_PART */

board/trab/Makefile

@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= lib$(BOARD).a
 
-OBJS	:= trab.o flash.o vfd.o
+OBJS	:= trab.o flash.o vfd.o cmd_trab.o memory.o tsc2000.o
 SOBJS	:= memsetup.o
 
 $(LIB):	$(OBJS) $(SOBJS)

board/trab/Pt1000_temp_data.h

@@ -0,0 +1,71 @@
+/*
+ * Data file for tsc2000 driver.
+ * Copyright (C) 2002, 2003 DENX Software Engineering, Wolfgang Denk, wd@denx.de
+ */
+
+#ifndef _PT1000_TEMP_DATA_H
+#define _PT1000_TEMP_DATA_H
+
+long Pt1000_temp_table[][2] = {
+	/* For quick range checking the largest element
+	 * is placed at index 0.
+	 * U, nV    T, C*100
+	 */
+	{ 44000000 , 12165 },
+	{ -10000000 , -2644 },
+	{ -9000000 , -2381 },
+	{ -8000000 , -2118 },
+	{ -7000000 , -1855 },
+	{ -6000000 , -1591 },
+	{ -5000000 , -1327 },
+	{ -4000000 , -1063 },
+	{ -3000000 , -798 },
+	{ -2000000 , -532 },
+	{ -1000000 , -266 },
+	{ 0 , 000 },
+	{ 1000000 , 267 },
+	{ 2000000 , 534 },
+	{ 3000000 , 802 },
+	{ 4000000 , 1070 },
+	{ 5000000 , 1338 },
+	{ 6000000 , 1607 },
+	{ 7000000 , 1876 },
+	{ 8000000 , 2146 },
+	{ 9000000 , 2416 },
+	{ 10000000 , 2687 },
+	{ 11000000 , 2958 },
+	{ 12000000 , 3230 },
+	{ 13000000 , 3502 },
+	{ 14000000 , 3774 },
+	{ 15000000 , 4047 },
+	{ 16000000 , 4321 },
+	{ 17000000 , 4595 },
+	{ 18000000 , 4869 },
+	{ 19000000 , 5144 },
+	{ 20000000 , 5419 },
+	{ 21000000 , 5694 },
+	{ 22000000 , 5971 },
+	{ 23000000 , 6247 },
+	{ 24000000 , 6524 },
+	{ 25000000 , 6802 },
+	{ 26000000 , 7080 },
+	{ 27000000 , 7358 },
+	{ 28000000 , 7637 },
+	{ 29000000 , 7916 },
+	{ 30000000 , 8196 },
+	{ 31000000 , 8476 },
+	{ 32000000 , 8757 },
+	{ 33000000 , 9039 },
+	{ 34000000 , 9320 },
+	{ 35000000 , 9602 },
+	{ 36000000 , 9885 },
+	{ 37000000 , 10168 },
+	{ 38000000 , 10452 },
+	{ 39000000 , 10736 },
+	{ 40000000 , 11021 },
+	{ 41000000 , 11306 },
+	{ 42000000 , 11592 },
+	{ 43000000 , 11879 },
+	{ 44000000 , 12165 },
+};
+#endif /* _PT1000_TEMP_DATA_H */

board/trab/cmd_trab.c

@@ -0,0 +1,821 @@
+/*
+ * (C) Copyright 2003
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <s3c2400.h>
+
+/*
+ * TRAB board specific commands. Especially commands for burn-in and function
+ * test.
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+
+/* limits for valid range of VCC5V in mV  */
+#define VCC5V_MIN       4500
+#define VCC5V_MAX       5500
+
+/*
+ * Test strings for EEPROM test. Length of string 2 must not exceed length of
+ * string 1. Otherwise a buffer overrun could occur!
+ */
+#define EEPROM_TEST_STRING_1    "0987654321 :tset a si siht"
+#define EEPROM_TEST_STRING_2    "this is a test: 1234567890"
+
+/*
+ * min/max limits for valid contact temperature during burn in test (in
+ * degree Centigrade * 100)
+ */
+#define MIN_CONTACT_TEMP        -1000
+#define MAX_CONTACT_TEMP        +9000
+
+/* blinking frequency of status LED */
+#define LED_BLINK_FREQ          5
+
+/* delay time between burn in cycles in seconds */
+#ifndef BURN_IN_CYCLE_DELAY     /* if not defined in include/configs/trab.h */
+#define BURN_IN_CYCLE_DELAY     5
+#endif
+
+/* physical SRAM parameters */
+#define SRAM_ADDR       0x02000000 /* GCS1 */
+#define SRAM_SIZE       0x40000 /* 256 kByte */
+
+/* CPLD-Register for controlling TRAB hardware functions */
+#define CPLD_BUTTONS            ((volatile unsigned long *)0x04020000)
+#define CPLD_FILL_LEVEL         ((volatile unsigned long *)0x04008000)
+#define CPLD_ROTARY_SWITCH      ((volatile unsigned long *)0x04018000)
+#define CPLD_RS485_RE           ((volatile unsigned long *)0x04028000)
+
+/* I2C EEPROM device address */
+#define I2C_EEPROM_DEV_ADDR     0x54
+
+/* EEPROM address map */
+#define EE_ADDR_TEST                    128
+#define EE_ADDR_MAX_CYCLES              256
+#define EE_ADDR_STATUS                  258
+#define EE_ADDR_PASS_CYCLES             259
+#define EE_ADDR_FIRST_ERROR_CYCLE       261
+#define EE_ADDR_FIRST_ERROR_NUM         263
+#define EE_ADDR_FIRST_ERROR_NAME        264
+#define EE_ADDR_ACT_CYCLE               280
+
+/* Bit definitions for ADCCON */
+#define ADC_ENABLE_START     0x1
+#define ADC_READ_START       0x2
+#define ADC_STDBM            0x4
+#define ADC_INP_AIN0         (0x0 << 3)
+#define ADC_INP_AIN1         (0x1 << 3)
+#define ADC_INP_AIN2         (0x2 << 3)
+#define ADC_INP_AIN3         (0x3 << 3)
+#define ADC_INP_AIN4         (0x4 << 3)
+#define ADC_INP_AIN5         (0x5 << 3)
+#define ADC_INP_AIN6         (0x6 << 3)
+#define ADC_INP_AIN7         (0x7 << 3)
+#define ADC_PRSCEN           0x4000
+#define ADC_ECFLG            0x800
+
+/* misc */
+
+/* externals */
+extern int memory_post_tests (unsigned long start, unsigned long size);
+extern int i2c_write (uchar, uint, int , uchar* , int);
+extern int i2c_read (uchar, uint, int , uchar* , int);
+extern void tsc2000_reg_init (void);
+extern s32 tsc2000_contact_temp (void);
+extern void spi_init(void);
+
+/* function declarations */
+int do_dip (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+int do_vcc5v (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+int do_burn_in (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+int do_contact_temp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+int do_burn_in_status (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
+/* helper functions */
+static void adc_init (void);
+static int adc_read (unsigned int channel);
+static int read_dip (void);
+static int read_vcc5v (void);
+static int test_dip (void);
+static int test_vcc5v (void);
+static int test_rotary_switch (void);
+static int test_sram (void);
+static int test_eeprom (void);
+static int test_contact_temp (void);
+static int i2c_write_multiple (uchar chip, uint addr, int alen,
+                               uchar *buffer, int len);
+static int i2c_read_multiple (uchar chip, uint addr, int alen,
+                              uchar *buffer, int len);
+static void led_set (unsigned int);
+static void led_blink (void);
+static void led_init (void);
+static void sdelay (unsigned long seconds); /* delay in seconds */
+static int dummy (void);
+static int read_max_cycles(void);
+static void test_function_table_init (void);
+static void global_vars_init (void);
+static int global_vars_write_to_eeprom (void);
+
+/* globals */
+u16 max_cycles;
+u8 status;
+u16 pass_cycles;
+u16 first_error_cycle;
+u8 first_error_num;
+unsigned char first_error_name[16];
+u16 act_cycle;
+
+typedef struct test_function_s {
+	unsigned char *name;
+        int (*pf)(void);
+} test_function_t;
+
+/* max number of Burn In Functions */
+#define BIF_MAX 6
+
+/* table with burn in functions */
+test_function_t test_function[BIF_MAX];
+
+
+int do_burn_in (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+        int i;
+        int cycle_status;
+
+        if (argc > 1) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+        led_init ();
+        global_vars_init ();
+        test_function_table_init ();
+
+        if (global_vars_write_to_eeprom () != 0) {
+                printf ("%s: error writing global_vars to eeprom\n",
+                        __FUNCTION__);
+                return (1);
+        }
+
+        if (read_max_cycles () != 0) {
+                printf ("%s: error reading max_cycles from eeprom\n",
+                        __FUNCTION__);
+                return (1);
+        }
+
+        if (max_cycles == 0) {
+                printf ("%s: error, burn in max_cycles = 0\n", __FUNCTION__);
+                return (1);
+        }
+
+        status = 0;
+        for (act_cycle = 1; act_cycle <= max_cycles; act_cycle++) {
+
+                cycle_status = 0;
+                for (i = 0; i < BIF_MAX; i++) {
+
+                        /* call test function */
+                        if ((*test_function[i].pf)() != 0) {
+                                printf ("error in %s test\n",
+                                        test_function[i].name);
+
+                                /* is it the first error? */
+                                if (status == 0) {
+                                        status = 1;
+                                        first_error_cycle = act_cycle;
+
+                                        /* do not use error_num 0 */
+                                        first_error_num = i+1;
+                                        strncpy (first_error_name,
+                                                 test_function[i].name,
+                                                 sizeof (first_error_name));
+                                        led_set (0);
+                                }
+                                cycle_status = 1;
+                        }
+                }
+                /* were all tests of actual cycle OK? */
+                if (cycle_status == 0)
+                        pass_cycles++;
+
+                /* set status LED if no error is occoured since yet */
+                if (status == 0)
+                        led_set (1);
+
+                printf ("%s: cycle %d finished\n", __FUNCTION__, act_cycle);
+
+                /* pause between cycles */
+                sdelay (BURN_IN_CYCLE_DELAY);
+        }
+
+        if (global_vars_write_to_eeprom () != 0) {
+                led_set (0);
+                printf ("%s: error writing global_vars to eeprom\n",
+                        __FUNCTION__);
+                status = 1;
+        }
+
+        if (status == 0) {
+                led_blink ();   /* endless loop!! */
+                return (0);
+        } else {
+                led_set (0);
+                return (1);
+        }
+}
+
+U_BOOT_CMD(
+ 	burn_in,	1,	1,	do_burn_in,
+ 	"burn_in - start burn-in test application on TRAB\n",
+ 	"\n"
+ 	"    -  start burn-in test application\n"
+        "       The burn-in test could took a while to finish!\n"
+        "       The content of the onboard EEPROM is modified!\n"
+);
+
+
+int do_dip (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+        int i, dip;
+
+      	if (argc > 1) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+        if ((dip = read_dip ()) == -1) {
+                return 1;
+        }
+
+        for (i = 0; i < 4; i++) {
+                if ((dip & (1 << i)) == 0)
+                        printf("0");
+                else
+                        printf("1");
+        }
+        printf("\n");
+
+	return 0;
+}
+
+U_BOOT_CMD(
+ 	dip,	1,	1,	do_dip,
+ 	"dip     - read dip switch on TRAB\n",
+ 	"\n"
+ 	"    - read state of dip switch (S1) on TRAB board\n"
+        "      read sequence: 1-2-3-4; ON=1; OFF=0; e.g.: \"0100\"\n"
+);
+
+
+int do_vcc5v (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+        int vcc5v;
+
+        if (argc > 1) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+        if ((vcc5v = read_vcc5v ()) == -1) {
+                return (1);
+        }
+
+        printf ("%d", (vcc5v / 1000));
+        printf (".%d", (vcc5v % 1000) / 100);
+        printf ("%d V\n", (vcc5v % 100) / 10) ;
+
+	return 0;
+}
+
+U_BOOT_CMD(
+ 	vcc5v,	1,	1,	do_vcc5v,
+ 	"vcc5v   - read VCC5V on TRAB\n",
+ 	"\n"
+ 	"    - read actual value of voltage VCC5V\n"
+);
+
+
+int do_contact_temp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+        int contact_temp;
+
+        if (argc > 1) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+        spi_init ();
+        tsc2000_reg_init ();
+
+        contact_temp = tsc2000_contact_temp();
+        printf ("%d degree C * 100\n", contact_temp) ;
+
+	return 0;
+}
+
+U_BOOT_CMD(
+ 	c_temp,	1,	1,	do_contact_temp,
+ 	"c_temp  - read contact temperature on TRAB\n",
+ 	"\n"
+ 	"    -  reads the onboard temperature (=contact temperature)\n"
+);
+
+
+int do_burn_in_status (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+        if (argc > 1) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+        if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_STATUS, 1,
+                                (unsigned char*) &status, 1)) {
+                return (1);
+        }
+        if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_PASS_CYCLES, 1,
+                                (unsigned char*) &pass_cycles, 2)) {
+                return (1);
+        }
+        if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_CYCLE,
+                                1, (unsigned char*) &first_error_cycle, 2)) {
+                return (1);
+        }
+        if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NUM,
+                                1, (unsigned char*) &first_error_num, 1)) {
+                return (1);
+        }
+        if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NAME,
+                               1, first_error_name,
+                               sizeof (first_error_name))) {
+                return (1);
+        }
+
+        if (read_max_cycles () != 0) {
+                return (1);
+        }
+
+        printf ("max_cycles = %d\n", max_cycles);
+        printf ("status = %d\n", status);
+        printf ("pass_cycles = %d\n", pass_cycles);
+        printf ("first_error_cycle = %d\n", first_error_cycle);
+        printf ("first_error_num = %d\n", first_error_num);
+        printf ("first_error_name = %.*s\n",(int) sizeof(first_error_name),
+                first_error_name);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+ 	bis,	1,	1,	do_burn_in_status,
+ 	"bis     - print burn in status on TRAB\n",
+ 	"\n"
+ 	"    -  prints the status variables of the last burn in test\n"
+        "       stored in the onboard EEPROM on TRAB board\n"
+);
+
+static int read_dip (void)
+{
+        unsigned int result = 0;
+        int adc_val;
+        int i;
+
+	/***********************************************************
+	 DIP switch connection (according to wa4-cpu.sp.301.pdf, page 3):
+	   SW1 - AIN4
+	   SW2 - AIN5
+	   SW3 - AIN6
+	   SW4 - AIN7
+
+	   "On" DIP switch position short-circuits the voltage from
+	   the input channel (i.e. '0' conversion result means "on").
+	*************************************************************/
+
+	for (i = 7; i > 3; i--) {
+
+                if ((adc_val = adc_read (i)) == -1) {
+                        printf ("%s: Channel %d could not be read\n",
+                                 __FUNCTION__, i);
+                        return (-1);
+                }
+
+		/*
+		 * Input voltage (switch open) is 1.8 V.
+		 * (Vin_High/VRef)*adc_res = (1,8V/2,5V)*1023) = 736
+		 * Set trigger at halve that value.
+		 */
+		if (adc_val < 368)
+                        result |= (1 << (i-4));
+        }
+        return (result);
+}
+
+
+static int read_vcc5v (void)
+{
+        s32 result;
+
+        /* VCC5V is connected to channel 2 */
+
+        if ((result = adc_read (2)) == -1) {
+                printf ("%s: VCC5V could not be read\n", __FUNCTION__);
+                return (-1);
+        }
+        /*
+         * Calculate voltage value. Split in two parts because there is no
+         * floating point support.  VCC5V is connected over an resistor divider:
+         * VCC5V=ADCval*2,5V/1023*(10K+30K)/10K.
+         */
+        result = result * 10 * 1000 / 1023; /* result in mV */
+
+        return (result);
+}
+
+
+static int test_dip (void)
+{
+        static int first_run = 1;
+        static int first_dip;
+
+        if (first_run) {
+                if ((first_dip = read_dip ()) == -1) {
+                        return (1);
+                }
+                first_run = 0;
+                debug ("%s: first_dip=%d\n", __FUNCTION__, first_dip);
+        }
+        if (first_dip != read_dip ()) {
+                return (1);
+        } else {
+                return (0);
+        }
+}
+
+
+static int test_vcc5v (void)
+{
+        int vcc5v;
+
+        if ((vcc5v = read_vcc5v ()) == -1) {
+                return (1);
+        }
+
+        if ((vcc5v > VCC5V_MAX) || (vcc5v < VCC5V_MIN)) {
+                return (1);
+        } else {
+                return (0);
+        }
+}
+
+
+static int test_rotary_switch (void)
+{
+        static int first_run = 1;
+        static int first_rs;
+
+        if (first_run) {
+                /*
+                 * clear bits in CPLD, because they have random values after
+                 * power-up or reset.
+                 */
+                *CPLD_ROTARY_SWITCH |= (1 << 16) | (1 << 17);
+
+                first_rs = ((*CPLD_ROTARY_SWITCH >> 16) & 0x7);
+                first_run = 0;
+                debug ("%s: first_rs=%d\n", __FUNCTION__, first_rs);
+        }
+
+        if (first_rs != ((*CPLD_ROTARY_SWITCH >> 16) & 0x7)) {
+                return (1);
+        } else {
+                return (0);
+        }
+}
+
+
+static int test_sram (void)
+{
+        return (memory_post_tests (SRAM_ADDR, SRAM_SIZE));
+}
+
+
+static int test_eeprom (void)
+{
+        unsigned char temp[sizeof (EEPROM_TEST_STRING_1)];
+        int result = 0;
+
+        /* write test string 1, read back and verify */
+        if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1,
+                                EEPROM_TEST_STRING_1,
+                                sizeof (EEPROM_TEST_STRING_1))) {
+                return (1);
+        }
+
+        if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1,
+                               temp, sizeof (EEPROM_TEST_STRING_1))) {
+                return (1);
+        }
+
+        if (strcmp (temp, EEPROM_TEST_STRING_1) != 0) {
+                result = 1;
+                printf ("%s: error; read_str = \"%s\"\n", __FUNCTION__, temp);
+        }
+
+        /* write test string 2, read back and verify */
+        if (result == 0) {
+                if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1,
+                                        EEPROM_TEST_STRING_2,
+                                        sizeof (EEPROM_TEST_STRING_2))) {
+                        return (1);
+                }
+
+                if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1,
+                                       temp, sizeof (EEPROM_TEST_STRING_2))) {
+                        return (1);
+                }
+
+                if (strcmp (temp, EEPROM_TEST_STRING_2) != 0) {
+                        result = 1;
+                        printf ("%s: error; read str = \"%s\"\n",
+                                __FUNCTION__, temp);
+                }
+        }
+        return (result);
+}
+
+
+static int test_contact_temp (void)
+{
+        int contact_temp;
+
+        spi_init ();
+        contact_temp = tsc2000_contact_temp ();
+
+        if ((contact_temp < MIN_CONTACT_TEMP)
+            || (contact_temp > MAX_CONTACT_TEMP))
+                return (1);
+        else
+                return (0);
+}
+
+
+static int i2c_write_multiple (uchar chip, uint addr, int alen,
+                               uchar *buffer, int len)
+{
+        int i;
+
+        if (alen != 1) {
+                printf ("%s: addr len other than 1 not supported\n",
+                         __FUNCTION__);
+                return (1);
+        }
+
+        for (i = 0; i < len; i++) {
+                if (i2c_write (chip, addr+i, alen, buffer+i, 1)) {
+                        printf ("%s: could not write to i2c device %d"
+                                 ", addr %d\n", __FUNCTION__, chip, addr);
+                        return (1);
+                }
+#if 0
+                printf ("chip=%#x, addr+i=%#x+%d=%p, alen=%d, *buffer+i="
+                        "%#x+%d=%p=\"%.1s\"\n", chip, addr, i, addr+i,
+                        alen, buffer, i, buffer+i, buffer+i);
+#endif
+
+                udelay (30000);
+        }
+        return (0);
+}
+
+
+static int i2c_read_multiple (uchar chip, uint addr, int alen,
+                               uchar *buffer, int len)
+{
+        int i;
+
+        if (alen != 1) {
+                printf ("%s: addr len other than 1 not supported\n",
+                         __FUNCTION__);
+                return (1);
+        }
+
+        for (i = 0; i < len; i++) {
+                if (i2c_read (chip, addr+i, alen, buffer+i, 1)) {
+                        printf ("%s: could not read from i2c device %#x"
+                                 ", addr %d\n", __FUNCTION__, chip, addr);
+                        return (1);
+                }
+        }
+        return (0);
+}
+
+
+static int adc_read (unsigned int channel)
+{
+        int j = 1000; /* timeout value for wait loop in us */
+        S3C2400_ADC *padc;
+
+        padc = S3C2400_GetBase_ADC();
+        channel &= 0x7;
+
+        adc_init ();
+
+	debug ("%s: adccon %#x\n", __FUNCTION__, padc->ADCCON);
+
+        padc->ADCCON &= ~ADC_STDBM; /* select normal mode */
+	padc->ADCCON &= ~(0x7 << 3); /* clear the channel bits */
+        padc->ADCCON |= ((channel << 3) | ADC_ENABLE_START);
+
+        debug ("%s: reading ch %d, addcon %#x\n", __FUNCTION__,
+		(padc->ADCCON >> 3) & 0x7, padc->ADCCON);
+
+        while (j--) {
+                if ((padc->ADCCON & ADC_ENABLE_START) == 0)
+                        break;
+                udelay (1);
+        }
+
+        if (j == 0) {
+                printf("%s: ADC timeout\n", __FUNCTION__);
+                padc->ADCCON |= ADC_STDBM; /* select standby mode */
+                return -1;
+        }
+
+        padc->ADCCON |= ADC_STDBM; /* select standby mode */
+
+        debug ("%s: return %#x, adccon %#x\n", __FUNCTION__,
+		padc->ADCDAT & 0x3FF, padc->ADCCON);
+
+        return (padc->ADCDAT & 0x3FF);
+}
+
+
+static void adc_init (void)
+{
+        S3C2400_ADC *padc;
+
+        padc = S3C2400_GetBase_ADC();
+
+	padc->ADCCON &= ~(0xff << 6); /* clear prescaler bits */
+	padc->ADCCON |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */
+
+        return;
+}
+
+
+static void led_set (unsigned int state)
+{
+        S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+        led_init ();
+
+        switch (state) {
+        case 0: /* turn LED off */
+                gpio->PADAT |= (1 << 12);
+                break;
+        case 1: /* turn LED on */
+                gpio->PADAT &= ~(1 << 12);
+                break;
+        default:
+        }
+}
+
+static void led_blink (void)
+{
+        led_init ();
+
+        /* blink LED. This function does not return! */
+        while (1) {
+                led_set (1);
+                udelay (1000000 / LED_BLINK_FREQ / 2);
+                led_set (0);
+                udelay (1000000 / LED_BLINK_FREQ / 2);
+        }
+}
+
+
+static void led_init (void)
+{
+        S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+        /* configure GPA12 as output and set to High -> LED off */
+        gpio->PACON &= ~(1 << 12);
+        gpio->PADAT |= (1 << 12);
+}
+
+
+static void sdelay (unsigned long seconds)
+{
+        unsigned long i;
+
+        for (i = 0; i < seconds; i++) {
+                udelay (1000000);
+        }
+}
+
+
+static int global_vars_write_to_eeprom (void)
+{
+        if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_STATUS, 1,
+                                (unsigned char*) &status, 1)) {
+                return (1);
+        }
+        if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_PASS_CYCLES, 1,
+                                (unsigned char*) &pass_cycles, 2)) {
+                return (1);
+        }
+        if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_CYCLE,
+                                1, (unsigned char*) &first_error_cycle, 2)) {
+                return (1);
+        }
+        if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NUM,
+                                1, (unsigned char*) &first_error_num, 1)) {
+                return (1);
+        }
+        if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NAME,
+                                1, first_error_name,
+                                sizeof(first_error_name))) {
+                return (1);
+        }
+        return (0);
+}
+
+static void global_vars_init (void)
+{
+        status                  = 1; /* error */
+        pass_cycles             = 0;
+        first_error_cycle       = 0;
+        first_error_num         = 0;
+        first_error_name[0]     = '\0';
+        act_cycle               = 0;
+        max_cycles              = 0;
+}
+
+
+static void test_function_table_init (void)
+{
+        int i;
+
+  	for (i = 0; i < BIF_MAX; i++)
+		test_function[i].pf = dummy;
+
+        /*
+         * the length of "name" must not exceed 16, including the '\0'
+         * termination. See also the EEPROM address map.
+         */
+        test_function[0].pf = test_dip;
+        test_function[0].name = "dip";
+
+        test_function[1].pf = test_vcc5v;
+        test_function[1].name = "vcc5v";
+
+        test_function[2].pf = test_rotary_switch;
+        test_function[2].name = "rotary_switch";
+
+        test_function[3].pf = test_sram;
+        test_function[3].name = "sram";
+
+        test_function[4].pf = test_eeprom;
+        test_function[4].name = "eeprom";
+
+        test_function[5].pf = test_contact_temp;
+        test_function[5].name = "contact_temp";
+}
+
+
+static int read_max_cycles (void)
+{
+        if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_MAX_CYCLES, 1,
+                               (unsigned char *) &max_cycles, 2) != 0) {
+                return (1);
+        }
+
+        return (0);
+}
+
+static int dummy(void)
+{
+        return (0);
+}
+
+#endif	/* CFG_CMD_BSP */

board/trab/memory.c

@@ -0,0 +1,484 @@
+/*
+ * (C) Copyright 2002-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* Memory test
+ *
+ * General observations:
+ * o The recommended test sequence is to test the data lines: if they are
+ *   broken, nothing else will work properly.  Then test the address
+ *   lines.  Finally, test the cells in the memory now that the test
+ *   program knows that the address and data lines work properly.
+ *   This sequence also helps isolate and identify what is faulty.
+ *
+ * o For the address line test, it is a good idea to use the base
+ *   address of the lowest memory location, which causes a '1' bit to
+ *   walk through a field of zeros on the address lines and the highest
+ *   memory location, which causes a '0' bit to walk through a field of
+ *   '1's on the address line.
+ *
+ * o Floating buses can fool memory tests if the test routine writes
+ *   a value and then reads it back immediately.  The problem is, the
+ *   write will charge the residual capacitance on the data bus so the
+ *   bus retains its state briefely.  When the test program reads the
+ *   value back immediately, the capacitance of the bus can allow it
+ *   to read back what was written, even though the memory circuitry
+ *   is broken.  To avoid this, the test program should write a test
+ *   pattern to the target location, write a different pattern elsewhere
+ *   to charge the residual capacitance in a differnt manner, then read
+ *   the target location back.
+ *
+ * o Always read the target location EXACTLY ONCE and save it in a local
+ *   variable.  The problem with reading the target location more than
+ *   once is that the second and subsequent reads may work properly,
+ *   resulting in a failed test that tells the poor technician that
+ *   "Memory error at 00000000, wrote aaaaaaaa, read aaaaaaaa" which
+ *   doesn't help him one bit and causes puzzled phone calls.  Been there,
+ *   done that.
+ *
+ * Data line test:
+ * ---------------
+ * This tests data lines for shorts and opens by forcing adjacent data
+ * to opposite states. Because the data lines could be routed in an
+ * arbitrary manner the must ensure test patterns ensure that every case
+ * is tested. By using the following series of binary patterns every
+ * combination of adjacent bits is test regardless of routing.
+ *
+ *     ...101010101010101010101010
+ *     ...110011001100110011001100
+ *     ...111100001111000011110000
+ *     ...111111110000000011111111
+ *
+ * Carrying this out, gives us six hex patterns as follows:
+ *
+ *     0xaaaaaaaaaaaaaaaa
+ *     0xcccccccccccccccc
+ *     0xf0f0f0f0f0f0f0f0
+ *     0xff00ff00ff00ff00
+ *     0xffff0000ffff0000
+ *     0xffffffff00000000
+ *
+ * To test for short and opens to other signals on our boards, we
+ * simply test with the 1's complemnt of the paterns as well, resulting
+ * in twelve patterns total.
+ *
+ * After writing a test pattern. a special pattern 0x0123456789ABCDEF is
+ * written to a different address in case the data lines are floating.
+ * Thus, if a byte lane fails, you will see part of the special
+ * pattern in that byte lane when the test runs.  For example, if the
+ * xx__xxxxxxxxxxxx byte line fails, you will see aa23aaaaaaaaaaaa
+ * (for the 'a' test pattern).
+ *
+ * Address line test:
+ * ------------------
+ *  This function performs a test to verify that all the address lines
+ *  hooked up to the RAM work properly.  If there is an address line
+ *  fault, it usually shows up as two different locations in the address
+ *  map (related by the faulty address line) mapping to one physical
+ *  memory storage location.  The artifact that shows up is writing to
+ *  the first location "changes" the second location.
+ *
+ * To test all address lines, we start with the given base address and
+ * xor the address with a '1' bit to flip one address line.  For each
+ * test, we shift the '1' bit left to test the next address line.
+ *
+ * In the actual code, we start with address sizeof(ulong) since our
+ * test pattern we use is a ulong and thus, if we tried to test lower
+ * order address bits, it wouldn't work because our pattern would
+ * overwrite itself.
+ *
+ * Example for a 4 bit address space with the base at 0000:
+ *   0000 <- base
+ *   0001 <- test 1
+ *   0010 <- test 2
+ *   0100 <- test 3
+ *   1000 <- test 4
+ * Example for a 4 bit address space with the base at 0010:
+ *   0010 <- base
+ *   0011 <- test 1
+ *   0000 <- (below the base address, skipped)
+ *   0110 <- test 2
+ *   1010 <- test 3
+ *
+ * The test locations are successively tested to make sure that they are
+ * not "mirrored" onto the base address due to a faulty address line.
+ * Note that the base and each test location are related by one address
+ * line flipped.  Note that the base address need not be all zeros.
+ *
+ * Memory tests 1-4:
+ * -----------------
+ * These tests verify RAM using sequential writes and reads
+ * to/from RAM. There are several test cases that use different patterns to
+ * verify RAM. Each test case fills a region of RAM with one pattern and
+ * then reads the region back and compares its contents with the pattern.
+ * The following patterns are used:
+ *
+ *  1a) zero pattern (0x00000000)
+ *  1b) negative pattern (0xffffffff)
+ *  1c) checkerboard pattern (0x55555555)
+ *  1d) checkerboard pattern (0xaaaaaaaa)
+ *  2)  bit-flip pattern ((1 << (offset % 32))
+ *  3)  address pattern (offset)
+ *  4)  address pattern (~offset)
+ *
+ * Being run in normal mode, the test verifies only small 4Kb
+ * regions of RAM around each 1Mb boundary. For example, for 64Mb
+ * RAM the following areas are verified: 0x00000000-0x00000800,
+ * 0x000ff800-0x00100800, 0x001ff800-0x00200800, ..., 0x03fff800-
+ * 0x04000000. If the test is run in slow-test mode, it verifies
+ * the whole RAM.
+ */
+
+/* #ifdef CONFIG_POST */
+
+#include <post.h>
+#include <watchdog.h>
+
+/* #if CONFIG_POST & CFG_POST_MEMORY */
+
+/*
+ * Define INJECT_*_ERRORS for testing error detection in the presence of
+ * _good_ hardware.
+ */
+#undef  INJECT_DATA_ERRORS
+#undef  INJECT_ADDRESS_ERRORS
+
+#ifdef INJECT_DATA_ERRORS
+#warning "Injecting data line errors for testing purposes"
+#endif
+
+#ifdef INJECT_ADDRESS_ERRORS
+#warning "Injecting address line errors for testing purposes"
+#endif
+
+
+/*
+ * This function performs a double word move from the data at
+ * the source pointer to the location at the destination pointer.
+ * This is helpful for testing memory on processors which have a 64 bit
+ * wide data bus.
+ *
+ * On those PowerPC with FPU, use assembly and a floating point move:
+ * this does a 64 bit move.
+ *
+ * For other processors, let the compiler generate the best code it can.
+ */
+static void move64(unsigned long long *src, unsigned long long *dest)
+{
+#if defined(CONFIG_MPC8260) || defined(CONFIG_MPC824X)
+	asm ("lfd  0, 0(3)\n\t" /* fpr0	  =  *scr	*/
+	 "stfd 0, 0(4)"		/* *dest  =  fpr0	*/
+	 : : : "fr0" );		/* Clobbers fr0		*/
+    return;
+#else
+	*dest = *src;
+#endif
+}
+
+/*
+ * This is 64 bit wide test patterns.  Note that they reside in ROM
+ * (which presumably works) and the tests write them to RAM which may
+ * not work.
+ *
+ * The "otherpattern" is written to drive the data bus to values other
+ * than the test pattern.  This is for detecting floating bus lines.
+ *
+ */
+const static unsigned long long pattern[] = {
+    0xaaaaaaaaaaaaaaaa,
+    0xcccccccccccccccc,
+    0xf0f0f0f0f0f0f0f0,
+    0xff00ff00ff00ff00,
+    0xffff0000ffff0000,
+    0xffffffff00000000,
+    0x00000000ffffffff,
+    0x0000ffff0000ffff,
+    0x00ff00ff00ff00ff,
+    0x0f0f0f0f0f0f0f0f,
+    0x3333333333333333,
+    0x5555555555555555};
+const unsigned long long otherpattern = 0x0123456789abcdef;
+
+
+static int memory_post_dataline(unsigned long long * pmem)
+{
+	unsigned long long temp64;
+	int num_patterns = sizeof(pattern)/ sizeof(pattern[0]);
+	int i;
+	unsigned int hi, lo, pathi, patlo;
+	int ret = 0;
+
+	for ( i = 0; i < num_patterns; i++) {
+		move64((unsigned long long *)&(pattern[i]), pmem++);
+		/*
+		 * Put a different pattern on the data lines: otherwise they
+		 * may float long enough to read back what we wrote.
+		 */
+		move64((unsigned long long *)&otherpattern, pmem--);
+		move64(pmem, &temp64);
+
+#ifdef INJECT_DATA_ERRORS
+		temp64 ^= 0x00008000;
+#endif
+
+		if (temp64 != pattern[i]){
+			pathi = (pattern[i]>>32) & 0xffffffff;
+			patlo = pattern[i] & 0xffffffff;
+
+			hi = (temp64>>32) & 0xffffffff;
+			lo = temp64 & 0xffffffff;
+
+			printf ("Memory (date line) error at %08lx, "
+				  "wrote %08x%08x, read %08x%08x !\n",
+					  (ulong)pmem, pathi, patlo, hi, lo);
+			ret = -1;
+		}
+	}
+	return ret;
+}
+
+static int memory_post_addrline(ulong *testaddr, ulong *base, ulong size)
+{
+	ulong *target;
+	ulong *end;
+	ulong readback;
+	ulong xor;
+	int   ret = 0;
+
+	end = (ulong *)((ulong)base + size);	/* pointer arith! */
+	xor = 0;
+	for(xor = sizeof(ulong); xor > 0; xor <<= 1) {
+		target = (ulong *)((ulong)testaddr ^ xor);
+		if((target >= base) && (target < end)) {
+			*testaddr = ~*target;
+			readback  = *target;
+
+#ifdef INJECT_ADDRESS_ERRORS
+			if(xor == 0x00008000) {
+				readback = *testaddr;
+			}
+#endif
+			if(readback == *testaddr) {
+				printf ("Memory (address line) error at %08lx<->%08lx, "
+				  	"XOR value %08lx !\n",
+					(ulong)testaddr, (ulong)target,
+					xor);
+				ret = -1;
+			}
+		}
+	}
+	return ret;
+}
+
+static int memory_post_test1 (unsigned long start,
+			      unsigned long size,
+			      unsigned long val)
+{
+	unsigned long i;
+	ulong *mem = (ulong *) start;
+	ulong readback;
+	int ret = 0;
+
+	for (i = 0; i < size / sizeof (ulong); i++) {
+		mem[i] = val;
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
+		readback = mem[i];
+		if (readback != val) {
+			printf ("Memory error at %08lx, "
+				  "wrote %08lx, read %08lx !\n",
+					  (ulong)(mem + i), val, readback);
+
+			ret = -1;
+			break;
+		}
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	return ret;
+}
+
+static int memory_post_test2 (unsigned long start, unsigned long size)
+{
+	unsigned long i;
+	ulong *mem = (ulong *) start;
+	ulong readback;
+	int ret = 0;
+
+	for (i = 0; i < size / sizeof (ulong); i++) {
+		mem[i] = 1 << (i % 32);
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
+		readback = mem[i];
+		if (readback != (1 << (i % 32))) {
+			printf ("Memory error at %08lx, "
+				  "wrote %08x, read %08lx !\n",
+					  (ulong)(mem + i), 1 << (i % 32), readback);
+
+			ret = -1;
+			break;
+		}
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	return ret;
+}
+
+static int memory_post_test3 (unsigned long start, unsigned long size)
+{
+	unsigned long i;
+	ulong *mem = (ulong *) start;
+	ulong readback;
+	int ret = 0;
+
+	for (i = 0; i < size / sizeof (ulong); i++) {
+		mem[i] = i;
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
+		readback = mem[i];
+		if (readback != i) {
+			printf ("Memory error at %08lx, "
+				  "wrote %08lx, read %08lx !\n",
+					  (ulong)(mem + i), i, readback);
+
+			ret = -1;
+			break;
+		}
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	return ret;
+}
+
+static int memory_post_test4 (unsigned long start, unsigned long size)
+{
+	unsigned long i;
+	ulong *mem = (ulong *) start;
+	ulong readback;
+	int ret = 0;
+
+	for (i = 0; i < size / sizeof (ulong); i++) {
+		mem[i] = ~i;
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
+		readback = mem[i];
+		if (readback != ~i) {
+			printf ("Memory error at %08lx, "
+				  "wrote %08lx, read %08lx !\n",
+					  (ulong)(mem + i), ~i, readback);
+
+			ret = -1;
+			break;
+		}
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	return ret;
+}
+
+int memory_post_tests (unsigned long start, unsigned long size)
+{
+	int ret = 0;
+
+	if (ret == 0)
+		ret = memory_post_dataline ((long long *)start);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_addrline ((long *)start, (long *)start, size);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_addrline ((long *)(start + size - 8),
+					    (long *)start, size);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_test1 (start, size, 0x00000000);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_test1 (start, size, 0xffffffff);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_test1 (start, size, 0x55555555);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_test1 (start, size, 0xaaaaaaaa);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_test2 (start, size);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_test3 (start, size);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_test4 (start, size);
+	WATCHDOG_RESET ();
+
+	return ret;
+}
+
+#if 0
+int memory_post_test (int flags)
+{
+	int ret = 0;
+	DECLARE_GLOBAL_DATA_PTR;
+	bd_t *bd = gd->bd;
+	unsigned long memsize = (bd->bi_memsize >= 256 << 20 ?
+				 256 << 20 : bd->bi_memsize) - (1 << 20);
+
+
+	if (flags & POST_SLOWTEST) {
+		ret = memory_post_tests (CFG_SDRAM_BASE, memsize);
+	} else {			/* POST_NORMAL */
+
+		unsigned long i;
+
+		for (i = 0; i < (memsize >> 20) && ret == 0; i++) {
+			if (ret == 0)
+				ret = memory_post_tests (i << 20, 0x800);
+			if (ret == 0)
+				ret = memory_post_tests ((i << 20) + 0xff800, 0x800);
+		}
+	}
+
+	return ret;
+}
+#endif 0
+
+/* #endif */ /* CONFIG_POST & CFG_POST_MEMORY */
+/* #endif */ /* CONFIG_POST */

board/trab/trab.c

@@ -105,6 +105,10 @@ int board_init ()
 	gpio->PGUP  = 0x0;
 	gpio->OPENCR= 0x0;
 
+	/* suppress flicker of the VFDs */
+	gpio->MISCCR = 0x40;
+	gpio->PFCON |= (2<<12);
+
 	/* arch number of SAMSUNG-Board */
 	/* MACH_TYPE_SMDK2400 */
 	/* XXX this isn't really correct, but keep it for now */

board/trab/tsc2000.c

@@ -0,0 +1,317 @@
+/*
+ * Functions to access the TSC2000 controller on TRAB board (used for scanning
+ * thermo sensors)
+ *
+ * Copyright (C) 2003 Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * Copyright (C) 2002 DENX Software Engineering, Wolfgang Denk, wd@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <s3c2400.h>
+#include "tsc2000.h"
+
+void spi_init(void)
+{
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+	S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
+	int i;
+
+	/* Configure I/O ports. */
+ 	gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000;
+	gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000;
+	gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000;
+	gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000;
+
+	CLR_CS_TOUCH();
+
+	spi->ch[0].SPPRE = 0x1F; /* Baud-rate ca. 514kHz */
+	spi->ch[0].SPPIN = 0x01; /* SPI-MOSI holds Level after last bit */
+	spi->ch[0].SPCON = 0x1A; /* Polling, Prescaler, Master, CPOL=0,
+                                    CPHA=1 */
+
+	/* Dummy byte ensures clock to be low. */
+	for (i = 0; i < 10; i++) {
+		spi->ch[0].SPTDAT = 0xFF;
+	}
+	spi_wait_transmit_done();
+}
+
+
+static void spi_wait_transmit_done(void)
+{
+	S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
+
+	while (!(spi->ch[0].SPSTA & 0x01)); /* wait until transfer is done */
+}
+
+
+static void tsc2000_write(unsigned short reg, unsigned short data)
+{
+	S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
+	unsigned int command;
+
+	SET_CS_TOUCH();
+	command = reg;
+        spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
+	spi_wait_transmit_done();
+	spi->ch[0].SPTDAT = (command & 0x00FF);
+	spi_wait_transmit_done();
+	spi->ch[0].SPTDAT = (data & 0xFF00) >> 8;
+	spi_wait_transmit_done();
+	spi->ch[0].SPTDAT = (data & 0x00FF);
+	spi_wait_transmit_done();
+
+	CLR_CS_TOUCH();
+}
+
+
+static unsigned short tsc2000_read (unsigned short reg)
+{
+	unsigned short command, data;
+	S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
+
+	SET_CS_TOUCH();
+	command = 0x8000 | reg;
+
+        spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
+	spi_wait_transmit_done();
+	spi->ch[0].SPTDAT = (command & 0x00FF);
+	spi_wait_transmit_done();
+
+        spi->ch[0].SPTDAT = 0xFF;
+	spi_wait_transmit_done();
+	data = spi->ch[0].SPRDAT;
+	spi->ch[0].SPTDAT = 0xFF;
+	spi_wait_transmit_done();
+
+	CLR_CS_TOUCH();
+	return (spi->ch[0].SPRDAT & 0x0FF) | (data << 8);
+}
+
+
+static void tsc2000_set_mux (unsigned int channel)
+{
+        S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	CLR_MUX1_ENABLE; CLR_MUX2_ENABLE;
+	CLR_MUX3_ENABLE; CLR_MUX4_ENABLE;
+	switch (channel) {
+	case 0:
+		CLR_MUX0; CLR_MUX1;
+		SET_MUX1_ENABLE;
+		break;
+	case 1:
+		SET_MUX0; CLR_MUX1;
+		SET_MUX1_ENABLE;
+		break;
+	case 2:
+		CLR_MUX0; SET_MUX1;
+		SET_MUX1_ENABLE;
+		break;
+	case 3:
+		SET_MUX0; SET_MUX1;
+		SET_MUX1_ENABLE;
+		break;
+	case 4:
+		CLR_MUX0; CLR_MUX1;
+		SET_MUX2_ENABLE;
+		break;
+	case 5:
+		SET_MUX0; CLR_MUX1;
+		SET_MUX2_ENABLE;
+		break;
+	case 6:
+		CLR_MUX0; SET_MUX1;
+		SET_MUX2_ENABLE;
+		break;
+	case 7:
+		SET_MUX0; SET_MUX1;
+		SET_MUX2_ENABLE;
+		break;
+	case 8:
+		CLR_MUX0; CLR_MUX1;
+		SET_MUX3_ENABLE;
+		break;
+	case 9:
+		SET_MUX0; CLR_MUX1;
+		SET_MUX3_ENABLE;
+		break;
+	case 10:
+		CLR_MUX0; SET_MUX1;
+		SET_MUX3_ENABLE;
+		break;
+	case 11:
+		SET_MUX0; SET_MUX1;
+		SET_MUX3_ENABLE;
+		break;
+	case 12:
+		CLR_MUX0; CLR_MUX1;
+		SET_MUX4_ENABLE;
+		break;
+	case 13:
+		SET_MUX0; CLR_MUX1;
+		SET_MUX4_ENABLE;
+		break;
+	case 14:
+		CLR_MUX0; SET_MUX1;
+		SET_MUX4_ENABLE;
+		break;
+	case 15:
+		SET_MUX0; SET_MUX1;
+		SET_MUX4_ENABLE;
+		break;
+	default:
+		CLR_MUX0; CLR_MUX1;
+	}
+}
+
+
+static void tsc2000_set_range (unsigned int range)
+{
+        S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	switch (range) {
+	case 1:
+		CLR_SEL_TEMP_V_0; SET_SEL_TEMP_V_1;
+		CLR_SEL_TEMP_V_2; CLR_SEL_TEMP_V_3;
+		break;
+	case 2:
+		CLR_SEL_TEMP_V_0; CLR_SEL_TEMP_V_1;
+		CLR_SEL_TEMP_V_2; SET_SEL_TEMP_V_3;
+		break;
+	case 3:
+		SET_SEL_TEMP_V_0; CLR_SEL_TEMP_V_1;
+		SET_SEL_TEMP_V_2; CLR_SEL_TEMP_V_3;
+		break;
+	}
+}
+
+
+static u16 tsc2000_read_channel (unsigned int channel)
+{
+	u16 res;
+
+	tsc2000_set_mux(channel);
+	udelay(3 * TSC2000_DELAY_BASE);
+
+	tsc2000_write(TSC2000_REG_ADC, 0x2036);
+        adc_wait_conversion_done ();
+        res = tsc2000_read(TSC2000_REG_AUX1);
+	return res;
+}
+
+
+s32 tsc2000_contact_temp (void)
+{
+	long adc_pt1000, offset;
+        long u_pt1000;
+	long contact_temp;
+
+
+        tsc2000_reg_init ();
+	tsc2000_set_range (3);
+
+        adc_pt1000 = tsc2000_read_channel (14);
+        debug ("read channel 14 (pt1000 adc value): %ld\n", adc_pt1000);
+
+        offset = tsc2000_read_channel (15);
+        debug ("read channel 15 (offset): %ld\n", offset);
+
+        /*
+         * Formula for calculating voltage drop on PT1000 resistor: u_pt1000 =
+         * x_range3 * (adc_raw - offset) / 10. Formula to calculate x_range3:
+         * x_range3 = (2500 * (1000000 + err_vref + err_amp3)) / (4095*6). The
+         * error correction Values err_vref and err_amp3 are assumed as 0 in
+         * u-boot, because this could cause only a very small error (< 1%).
+         */
+        u_pt1000 = (101750 * (adc_pt1000 - offset)) / 10;
+        debug ("u_pt1000: %ld\n", u_pt1000);
+
+        if (tsc2000_interpolate(u_pt1000, Pt1000_temp_table,
+                                &contact_temp) == -1) {
+                printf ("%s: error interpolating PT1000 vlaue\n",
+                         __FUNCTION__);
+                return (-1000);
+        }
+        debug ("contact_temp: %ld\n", contact_temp);
+
+	return contact_temp;
+}
+
+
+void tsc2000_reg_init (void)
+{
+        S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	tsc2000_write(TSC2000_REG_ADC, 0x2036);
+	tsc2000_write(TSC2000_REG_REF, 0x0011);
+	tsc2000_write(TSC2000_REG_DACCTL, 0x0000);
+
+	CON_MUX0;
+	CON_MUX1;
+
+	CON_MUX1_ENABLE;
+	CON_MUX2_ENABLE;
+	CON_MUX3_ENABLE;
+	CON_MUX4_ENABLE;
+
+	CON_SEL_TEMP_V_0;
+	CON_SEL_TEMP_V_1;
+	CON_SEL_TEMP_V_2;
+	CON_SEL_TEMP_V_3;
+
+	tsc2000_set_mux(0);
+	tsc2000_set_range(0);
+}
+
+
+static int tsc2000_interpolate(long value, long data[][2], long *result)
+{
+	int i;
+
+	/* the data is sorted and the first element is upper
+	 * limit so we can easily check for out-of-band values
+	 */
+	if (data[0][0] < value || data[1][0] > value)
+		return -1;
+
+	i = 1;
+	while (data[i][0] < value)
+		i++;
+
+	/* To prevent overflow we have to store the intermediate
+	   result in 'long long'.
+	*/
+
+	*result = data[i-1][1] +
+		((unsigned long long)(data[i][1] - data[i-1][1])
+		 * (unsigned long long)(value - data[i-1][0]))
+		/ (data[i][0] - data[i-1][0]);
+
+	return 0;
+}
+
+
+static void adc_wait_conversion_done(void)
+{
+        while (!(tsc2000_read(TSC2000_REG_ADC) & (1 << 14)));
+}

board/trab/tsc2000.h

@@ -0,0 +1,147 @@
+/*
+ * Functions to access the TSC2000 controller on TRAB board (used for scanning
+ * thermo sensors)
+ *
+ * Copyright (C) 2003 Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * Copyright (C) 2002 DENX Software Engineering, Wolfgang Denk, wd@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TSC2000_H_
+#define _TSC2000_H_
+
+#include "Pt1000_temp_data.h"
+
+/* temperature channel multiplexer definitions */
+#define CON_MUX0         	(gpio->PCCON = (gpio->PCCON & 0x0FFFFFCFF) | 0x00000100)
+#define CLR_MUX0         	(gpio->PCDAT &= 0x0FFEF)
+#define SET_MUX0         	(gpio->PCDAT |= 0x00010)
+
+#define CON_MUX1         	(gpio->PCCON = (gpio->PCCON & 0x0FFFFF3FF) | 0x00000400)
+#define CLR_MUX1         	(gpio->PCDAT &= 0x0FFDF)
+#define SET_MUX1         	(gpio->PCDAT |= 0x00020)
+
+#define CON_MUX1_ENABLE  	(gpio->PCCON = (gpio->PCCON & 0x0FFFFCFFF) | 0x00001000)
+#define CLR_MUX1_ENABLE  	(gpio->PCDAT |= 0x00040)
+#define SET_MUX1_ENABLE  	(gpio->PCDAT &= 0x0FFBF)
+
+#define CON_MUX2_ENABLE  	(gpio->PCCON = (gpio->PCCON & 0x0FFFF3FFF) | 0x00004000)
+#define CLR_MUX2_ENABLE  	(gpio->PCDAT |= 0x00080)
+#define SET_MUX2_ENABLE  	(gpio->PCDAT &= 0x0FF7F)
+
+#define CON_MUX3_ENABLE  	(gpio->PCCON = (gpio->PCCON & 0x0FFFCFFFF) | 0x00010000)
+#define CLR_MUX3_ENABLE  	(gpio->PCDAT |= 0x00100)
+#define SET_MUX3_ENABLE  	(gpio->PCDAT &= 0x0FEFF)
+
+#define CON_MUX4_ENABLE  	(gpio->PCCON = (gpio->PCCON & 0x0FFF3FFFF) | 0x00040000)
+#define CLR_MUX4_ENABLE  	(gpio->PCDAT |= 0x00200)
+#define SET_MUX4_ENABLE  	(gpio->PCDAT &= 0x0FDFF)
+
+#define CON_SEL_TEMP_V_0 	(gpio->PCCON = (gpio->PCCON & 0x0FFCFFFFF) | 0x00100000)
+#define CLR_SEL_TEMP_V_0 	(gpio->PCDAT &= 0x0FBFF)
+#define SET_SEL_TEMP_V_0 	(gpio->PCDAT |= 0x00400)
+
+#define CON_SEL_TEMP_V_1 	(gpio->PCCON = (gpio->PCCON & 0x0FF3FFFFF) | 0x00400000)
+#define CLR_SEL_TEMP_V_1 	(gpio->PCDAT &= 0x0F7FF)
+#define SET_SEL_TEMP_V_1 	(gpio->PCDAT |= 0x00800)
+
+#define CON_SEL_TEMP_V_2 	(gpio->PCCON = (gpio->PCCON & 0x0FCFFFFFF) | 0x01000000)
+#define CLR_SEL_TEMP_V_2 	(gpio->PCDAT &= 0x0EFFF)
+#define SET_SEL_TEMP_V_2 	(gpio->PCDAT |= 0x01000)
+
+#define CON_SEL_TEMP_V_3 	(gpio->PCCON = (gpio->PCCON & 0x0F3FFFFFF) | 0x04000000)
+#define CLR_SEL_TEMP_V_3 	(gpio->PCDAT &= 0x0DFFF)
+#define SET_SEL_TEMP_V_3 	(gpio->PCDAT |= 0x02000)
+
+/* TSC2000 register definition */
+#define TSC2000_REG_X		((0 << 11) | (0 << 5))
+#define TSC2000_REG_Y		((0 << 11) | (1 << 5))
+#define TSC2000_REG_Z1		((0 << 11) | (2 << 5))
+#define TSC2000_REG_Z2		((0 << 11) | (3 << 5))
+#define TSC2000_REG_BAT1	((0 << 11) | (5 << 5))
+#define TSC2000_REG_BAT2	((0 << 11) | (6 << 5))
+#define TSC2000_REG_AUX1	((0 << 11) | (7 << 5))
+#define TSC2000_REG_AUX2	((0 << 11) | (8 << 5))
+#define TSC2000_REG_TEMP1	((0 << 11) | (9 << 5))
+#define TSC2000_REG_TEMP2	((0 << 11) | (0xA << 5))
+#define TSC2000_REG_DAC		((0 << 11) | (0xB << 5))
+#define TSC2000_REG_ZERO	((0 << 11) | (0x10 << 5))
+#define TSC2000_REG_ADC		((1 << 11) | (0 << 5))
+#define TSC2000_REG_DACCTL	((1 << 11) | (2 << 5))
+#define TSC2000_REG_REF		((1 << 11) | (3 << 5))
+#define TSC2000_REG_RESET	((1 << 11) | (4 << 5))
+#define TSC2000_REG_CONFIG	((1 << 11) | (5 << 5))
+
+/* bit definition of TSC2000 ADC register */
+#define TC_PSM          (1 << 15)
+#define TC_STS          (1 << 14)
+#define TC_AD3          (1 << 13)
+#define TC_AD2          (1 << 12)
+#define TC_AD1          (1 << 11)
+#define TC_AD0          (1 << 10)
+#define TC_RS1          (1 << 9)
+#define TC_RS0          (1 << 8)
+#define TC_AV1          (1 << 7)
+#define TC_AV0          (1 << 6)
+#define TC_CL1          (1 << 5)
+#define TC_CL0          (1 << 4)
+#define TC_PV2          (1 << 3)
+#define TC_PV1          (1 << 2)
+#define TC_PV0          (1 << 1)
+
+/* default value for TSC2000 ADC register for use with touch functions */
+#define DEFAULT_ADC		(TC_PV1 | TC_AV0 | TC_AV1 | TC_RS0)
+
+#define TSC2000_DELAY_BASE	500
+#define TSC2000_NO_SENSOR	-0x10000
+
+#define ERROR_BATTERY   220     /* must be adjusted, if R68 is changed on
+                                 * TRAB */
+
+static void tsc2000_write(unsigned short, unsigned short);
+static unsigned short tsc2000_read (unsigned short);
+static u16 tsc2000_read_channel (unsigned int);
+static void tsc2000_set_mux (unsigned int);
+static void tsc2000_set_range (unsigned int);
+void tsc2000_reg_init (void);
+s32 tsc2000_contact_temp (void);
+static void spi_wait_transmit_done (void);
+void spi_init(void);
+static int tsc2000_interpolate(long value, long data[][2], long *result);
+static void adc_wait_conversion_done(void);
+
+
+static inline void SET_CS_TOUCH(void)
+{
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	gpio->PDDAT &= 0x5FF;
+}
+
+
+static inline void CLR_CS_TOUCH(void)
+{
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	gpio->PDDAT |= 0x200;
+}
+
+#endif	/* _TSC2000_H_ */

common/cmd_doc.c

@@ -861,8 +861,13 @@ static int find_boot_record(struct NFTLrecord *nftl)
 		memcpy(mh, buf, sizeof(struct NFTLMediaHeader));
 
 		/* Do some sanity checks on it */
-		if (mh->UnitSizeFactor != 0xff) {
-			puts ("Sorry, we don't support UnitSizeFactor "
+		if (mh->UnitSizeFactor == 0) {
+#ifdef NFTL_DEBUG
+			puts ("UnitSizeFactor 0x00 detected.\n"
+			      "This violates the spec but we think we know what it means...\n");
+#endif
+		} else if (mh->UnitSizeFactor != 0xff) {
+			printf ("Sorry, we don't support UnitSizeFactor "
 			      "of != 1 yet.\n");
 			return -1;
 		}
@@ -950,6 +955,8 @@ static void DoC2k_init(struct DiskOnChip* this)
 
 	/* Ident all the chips present. */
 	DoC_ScanChips(this);
+	if ((!this->numchips) || (!this->chips))
+		return;
 
 	nftl = &this->nftl;
 

common/cmd_fat.c

@@ -36,76 +36,179 @@
 
 #include <fat.h>
 
-extern block_dev_desc_t *ide_get_dev (int dev);
+
+
+
+block_dev_desc_t *get_dev (char* ifname, int dev)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_IDE)
+	if (strncmp(ifname,"ide",3)==0) {
+		extern block_dev_desc_t * ide_get_dev(int dev);
+		return(ide_get_dev(dev));
+	}
+#endif
+#if (CONFIG_COMMANDS & CFG_CMD_SCSI)
+	if (strncmp(ifname,"scsi",4)==0) {
+		extern block_dev_desc_t * scsi_get_dev(int dev);
+		return(scsi_get_dev(dev));
+	}
+#endif
+#if ((CONFIG_COMMANDS & CFG_CMD_USB) && defined(CONFIG_USB_STORAGE))
+	if (strncmp(ifname,"usb",3)==0) {
+		extern block_dev_desc_t * usb_stor_get_dev(int dev);
+		return(usb_stor_get_dev(dev));
+	}
+#endif
+#if defined(CONFIG_MMC)
+	if (strncmp(ifname,"mmc",3)==0) {
+		extern block_dev_desc_t *  mmc_get_dev(int dev);
+		return(mmc_get_dev(dev));
+	}
+#endif
+	return NULL;
+}
+
 
 int do_fat_fsload (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	long size;
 	unsigned long offset;
 	unsigned long count;
+	block_dev_desc_t *dev_desc=NULL;
+	int dev=0;
+	int part=1;
+	char *ep;
 
-	if (argc < 3) {
-		printf ("usage:fatload <filename> <addr> [bytes]\n");
+	if (argc < 5) {
+		printf ("usage: fatload <interface> <dev[:part]> <addr> <filename> [bytes]\n");
 		return (0);
 	}
-
-	offset = simple_strtoul (argv[2], NULL, 16);
-	if (argc == 4)
-		count = simple_strtoul (argv[3], NULL, 16);
+	dev = (int)simple_strtoul (argv[2], &ep, 16);
+	dev_desc=get_dev(argv[1],dev);
+	if (dev_desc==NULL) {
+		puts ("\n** Invalid boot device **\n");
+		return 1;
+	}
+	if (*ep) {
+		if (*ep != ':') {
+			puts ("\n** Invalid boot device, use `dev[:part]' **\n");
+			return 1;
+		}
+		part = (int)simple_strtoul(++ep, NULL, 16);
+	}
+	if (fat_register_device(dev_desc,part)!=0) {
+		printf ("\n** Unable to use %s %d:%d for fatload **\n",argv[1],dev,part);
+		return 1;
+	}
+	offset = simple_strtoul (argv[3], NULL, 16);
+	if (argc == 6)
+		count = simple_strtoul (argv[5], NULL, 16);
 	else
 		count = 0;
+	size = file_fat_read (argv[4], (unsigned char *) offset, count);
 
-	size = file_fat_read (argv[1], (unsigned char *) offset, count);
-
-	printf ("%ld bytes read\n", size);
+	if(size==-1)
+		printf("\n** Unable to read \"%s\" from %s %d:%d **\n",argv[4],argv[1],dev,part);
+	else
+		printf ("\n%ld bytes read\n", size);
 
 	return size;
 }
 
+
+
+
 U_BOOT_CMD(
-	fatload,	4,	0,	do_fat_fsload,
+	fatload,	6,	0,	do_fat_fsload,
 	"fatload - load binary file from a dos filesystem\n",
-	"[ off ] [ filename ]\n"
-	"    - load binary file from dos filesystem\n"
-	"      with offset 'off'\n"
+	"<interface> <dev[:part]>  <addr> <filename> [bytes]\n"
+	"    - load binary file 'filename' from 'dev' on 'interface'\n"
+	"      to address 'addr' from dos filesystem\n"
 );
 
 int do_fat_ls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	char *filename = "/";
 	int ret;
+	int dev=0;
+	int part=1;
+	char *ep;
+	block_dev_desc_t *dev_desc=NULL;
 
-	if (argc == 2)
-		ret = file_fat_ls (argv[1]);
+	if (argc < 3) {
+		printf ("usage: fatls <interface> <dev[:part]> [directory]\n");
+		return (0);
+	}
+	dev = (int)simple_strtoul (argv[2], &ep, 16);
+	dev_desc=get_dev(argv[1],dev);
+	if (dev_desc==NULL) {
+		puts ("\n** Invalid boot device **\n");
+		return 1;
+	}
+	if (*ep) {
+		if (*ep != ':') {
+			puts ("\n** Invalid boot device, use `dev[:part]' **\n");
+			return 1;
+		}
+		part = (int)simple_strtoul(++ep, NULL, 16);
+	}
+	if (fat_register_device(dev_desc,part)!=0) {
+		printf ("\n** Unable to use %s %d:%d for fatls **\n",argv[1],dev,part);
+		return 1;
+	}
+	if (argc == 4)
+		ret = file_fat_ls (argv[3]);
 	else
 		ret = file_fat_ls (filename);
 
+	if(ret!=0)
+		printf("No Fat FS detected\n");
 	return (ret);
 }
 
 U_BOOT_CMD(
-	fatls,	2,	1,	do_fat_ls,
+	fatls,	4,	1,	do_fat_ls,
 	"fatls   - list files in a directory (default /)\n",
-	"[ directory ]\n"
-	"    - list files in a directory\n"
+	"<interface> <dev[:part]> [directory]\n"
+	"    - list files from 'dev' on 'interface' in a 'directory'\n"
 );
 
 int do_fat_fsinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-	int ret;
+	int dev=0;
+	int part=1;
+	char *ep;
+	block_dev_desc_t *dev_desc=NULL;
 
-	ret = 0;
-
-	printf ("FAT info: %d\n", file_fat_detectfs ());
-
-	return (ret);
+	if (argc < 2) {
+		printf ("usage: fatinfo <interface> <dev[:part]>\n");
+		return (0);
+	}
+	dev = (int)simple_strtoul (argv[2], &ep, 16);
+	dev_desc=get_dev(argv[1],dev);
+	if (dev_desc==NULL) {
+		puts ("\n** Invalid boot device **\n");
+		return 1;
+	}
+	if (*ep) {
+		if (*ep != ':') {
+			puts ("\n** Invalid boot device, use `dev[:part]' **\n");
+			return 1;
+		}
+		part = (int)simple_strtoul(++ep, NULL, 16);
+	}
+	if (fat_register_device(dev_desc,part)!=0) {
+		printf ("\n** Unable to use %s %d:%d for fatinfo **\n",argv[1],dev,part);
+		return 1;
+	}
+	return (file_fat_detectfs ());
 }
 
 U_BOOT_CMD(
-	fatinfo,	1,	1,	do_fat_fsinfo,
+	fatinfo,	3,	1,	do_fat_fsinfo,
 	"fatinfo - print information about filesystem\n",
-	"\n"
-	"    - print information about filesystem\n"
+	"<interface> <dev[:part]>\n"
+	"    - print information about filesystem from 'dev' on 'interface'\n"
 );
 
 #ifdef NOT_IMPLEMENTED_YET

common/cmd_jffs2.c

@@ -174,7 +174,7 @@ do_jffs2_chpart(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	}
 
 	if (jffs2_part_info(tmp_part)){
-		printf("Partiton changed to %d\n",tmp_part);
+		printf("Partition changed to %d\n",tmp_part);
 		part_num=tmp_part;
 		return 0;
 	}

common/cmd_nand.c

@@ -734,7 +734,9 @@ static void NanD_ScanChips(struct nand_chip *nand)
 
 	/* If there are none at all that we recognise, bail */
 	if (!nand->numchips) {
+#ifdef NAND_DEBUG
 		puts ("No NAND flash chips recognised.\n");
+#endif
 		return;
 	}
 
@@ -1408,7 +1410,7 @@ static inline int nandcheck(unsigned long potential, unsigned long physadr)
 	return 0;
 }
 
-void nand_probe(unsigned long physadr)
+unsigned long nand_probe(unsigned long physadr)
 {
 	struct nand_chip *nand = NULL;
 	int i = 0, ChipID = 1;
@@ -1434,10 +1436,12 @@ void nand_probe(unsigned long physadr)
 
 	for (i=0; i<CFG_MAX_NAND_DEVICE; i++) {
 		if (nand_dev_desc[i].ChipID == NAND_ChipID_UNKNOWN) {
-			nand = nand_dev_desc + i;
+			nand = &nand_dev_desc[i];
 			break;
 		}
 	}
+	if (!nand)
+		return (0);
 
 	memset((char *)nand, 0, sizeof(struct nand_chip));
 
@@ -1449,7 +1453,7 @@ void nand_probe(unsigned long physadr)
 		/* no chips found, clean up and quit */
 		memset((char *)nand, 0, sizeof(struct nand_chip));
 		nand->ChipID = NAND_ChipID_UNKNOWN;
-		return;
+		return (0);
 	}
 
 	nand->ChipID = ChipID;
@@ -1459,8 +1463,10 @@ void nand_probe(unsigned long physadr)
 	nand->data_buf = malloc (nand->oobblock + nand->oobsize);
 	if (!nand->data_buf) {
 		puts ("Cannot allocate memory for data structures.\n");
-		return;
+		return (0);
 	}
+
+	return (nand->totlen);
 }
 
 #ifdef CONFIG_MTD_NAND_ECC

common/cmd_vfd.c

@@ -54,7 +54,7 @@ int do_vfd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		return 1;
 	}
 
-	if (argv[1][0] == '#') {	/* select bitmap by number */
+	if (argv[1][0] == '/') {	/* select bitmap by number */
 		bitmap = simple_strtoul(argv[1]+1, NULL, 10);
 		return (trab_vfd(bitmap));
 	}
@@ -68,8 +68,10 @@ int do_vfd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 U_BOOT_CMD(
  	vfd,	2,	0,	do_vfd,
  	"vfd     - load a bitmap to the VFDs on TRAB\n",
- 	"N\n"
+ 	"/N\n"
  	"    - load bitmap N to the VFDs (N is _decimal_ !!!)\n"
+	"vfd ADDR\n"
+	"    - load bitmap at address ADDR\n"
 );
 #endif	/* CFG_CMD_VFD */
 

common/exports.c

@@ -27,5 +27,9 @@ void jumptable_init (void)
 #if defined(CONFIG_I386) || defined(CONFIG_PPC)
 	gd->jt[XF_install_hdlr] = (void *) irq_install_handler;
 	gd->jt[XF_free_hdlr] = (void *) irq_free_handler;
-#endif
+#endif	/* I386 || PPC */
+#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+	gd->jt[XF_i2c_write] = (void *) i2c_write;
+	gd->jt[XF_i2c_read] = (void *) i2c_read;
+#endif	/* CFG_CMD_I2C */
 }

common/usb_storage.c

@@ -2,8 +2,12 @@
  * (C) Copyright 2001
  * Denis Peter, MPL AG Switzerland
  *
+ * For BBB support (C) Copyright 2003
+ * Gary Jennejohn, DENX Software Engineering <gj@denx.de>
+ *
  * Most of this source has been derived from the Linux USB
- * project.
+ * project. BBB support based on /sys/dev/usb/umass.c from
+ * FreeBSD.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -30,6 +34,13 @@
  * is only tested with a TEAC USB Floppy. Other Massstorages with CBI or CB
  * transport protocoll may work as well.
  */
+/*
+ * New Note:
+ * Support for USB Mass Storage Devices (BBB) has been added. It has
+ * only been tested with USB memory sticks.
+ * Nota bene: if you are using the BBB support with a little-endian
+ * CPU then you MUST define LITTLEENDIAN in the configuration file!
+ */
 
 
 #include <common.h>
@@ -71,6 +82,41 @@ static ccb usb_ccb;
 
 #define US_CBI_ADSC		0
 
+/*
+ * BULK only
+ */
+#define US_BBB_RESET		0xff
+#define US_BBB_GET_MAX_LUN	0xfe
+
+/* Command Block Wrapper */
+typedef struct {
+	__u32		dCBWSignature;
+#	define CBWSIGNATURE	0x43425355
+	__u32		dCBWTag;
+	__u32		dCBWDataTransferLength;
+	__u8		bCBWFlags;
+#	define CBWFLAGS_OUT	0x00
+#	define CBWFLAGS_IN	0x80
+	__u8		bCBWLUN;
+	__u8		bCDBLength;
+#	define CBWCDBLENGTH	16
+	__u8		CBWCDB[CBWCDBLENGTH];
+} umass_bbb_cbw_t;
+#define	UMASS_BBB_CBW_SIZE	31
+static __u32 CBWTag = 0;
+
+/* Command Status Wrapper */
+typedef struct {
+	__u32		dCSWSignature;
+#	define CSWSIGNATURE	0x53425355
+	__u32		dCSWTag;
+	__u32		dCSWDataResidue;
+	__u8		bCSWStatus;
+#	define CSWSTATUS_GOOD	0x0
+#	define CSWSTATUS_FAILED	0x1
+#	define CSWSTATUS_PHASE	0x2
+} umass_bbb_csw_t;
+#define	UMASS_BBB_CSW_SIZE	13
 
 #define USB_MAX_STOR_DEV 5
 static int usb_max_devs; /* number of highest available usb device */
@@ -138,6 +184,9 @@ int usb_stor_scan(int mode)
 	unsigned char i;
 	struct usb_device *dev;
 
+	/* GJ */
+	memset(usb_stor_buf, 0, sizeof(usb_stor_buf));
+
 	if(mode==1) {
 		printf("scanning bus for storage devices...\n");
 	}
@@ -293,6 +342,51 @@ static int us_one_transfer(struct us_data *us, int pipe, char *buf, int length)
 	return 0;
 }
 
+static int usb_stor_BBB_reset(struct us_data *us)
+{
+	int result;
+	unsigned int pipe;
+
+	/*
+	 * Reset recovery (5.3.4 in Universal Serial Bus Mass Storage Class)
+	 *
+	 * For Reset Recovery the host shall issue in the following order:
+	 * a) a Bulk-Only Mass Storage Reset
+	 * b) a Clear Feature HALT to the Bulk-In endpoint
+	 * c) a Clear Feature HALT to the Bulk-Out endpoint
+	 *
+	 * This is done in 3 steps.
+	 *
+	 * If the reset doesn't succeed, the device should be port reset.
+	 *
+	 * This comment stolen from FreeBSD's /sys/dev/usb/umass.c.
+	 */
+	USB_STOR_PRINTF("BBB_reset\n");
+	result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev,0),
+				 US_BBB_RESET, USB_TYPE_CLASS | USB_RECIP_INTERFACE,
+				 0, us->ifnum, 0, 0, USB_CNTL_TIMEOUT*5);
+	if((result < 0) && (us->pusb_dev->status & USB_ST_STALLED))
+	{
+		USB_STOR_PRINTF("RESET:stall\n");
+		return -1;
+	}
+	/* long wait for reset */
+	wait_ms(150);
+	USB_STOR_PRINTF("BBB_reset result %d: status %X reset\n",result,us->pusb_dev->status);
+	pipe = usb_rcvbulkpipe(us->pusb_dev, us->ep_in);
+	result = usb_clear_halt(us->pusb_dev, pipe);
+	/* long wait for reset */
+	wait_ms(150);
+	USB_STOR_PRINTF("BBB_reset result %d: status %X clearing IN endpoint\n",result,us->pusb_dev->status);
+	/* long wait for reset */
+	pipe = usb_sndbulkpipe(us->pusb_dev, us->ep_out);
+	result = usb_clear_halt(us->pusb_dev, pipe);
+	wait_ms(150);
+	USB_STOR_PRINTF("BBB_reset result %d: status %X clearing OUT endpoint\n",result,us->pusb_dev->status);
+	USB_STOR_PRINTF("BBB_reset done\n");
+	return 0;
+}
+
 /* FIXME: this reset function doesn't really reset the port, and it
  * should. Actually it should probably do what it's doing here, and
  * reset the port physically
@@ -320,6 +414,52 @@ static int usb_stor_CB_reset(struct us_data *us)
 	return 0;
 }
 
+/*
+ * Set up the command for a BBB device. Note that the actual SCSI
+ * command is copied into cbw.CBWCDB.
+ */
+int usb_stor_BBB_comdat(ccb *srb, struct us_data *us)
+{
+	int result;
+	int actlen;
+	int dir_in;
+	unsigned int pipe;
+	umass_bbb_cbw_t cbw;
+
+	dir_in = US_DIRECTION(srb->cmd[0]);
+
+#ifdef BBB_COMDAT_TRACE
+	printf("dir %d lun %d cmdlen %d cmd %p datalen %d pdata %p\n", dir_in, srb->lun, srb->cmdlen, srb->cmd, srb->datalen, srb->pdata);
+	if (srb->cmdlen) {
+		for(result = 0;result < srb->cmdlen;result++)
+			printf("cmd[%d] %#x ", result, srb->cmd[result]);
+		printf("\n");
+	}
+#endif
+	/* sanity checks */
+	if (!(srb->cmdlen <= CBWCDBLENGTH)) {
+		USB_STOR_PRINTF("usb_stor_BBB_comdat:cmdlen too large\n");
+		return -1;
+	}
+
+	/* always OUT to the ep */
+	pipe = usb_sndbulkpipe(us->pusb_dev, us->ep_out);
+
+	cbw.dCBWSignature = swap_32(CBWSIGNATURE);
+	cbw.dCBWTag = swap_32(CBWTag++);
+	cbw.dCBWDataTransferLength = swap_32(srb->datalen);
+	cbw.bCBWFlags = (dir_in? CBWFLAGS_IN : CBWFLAGS_OUT);
+	cbw.bCBWLUN = srb->lun;
+	cbw.bCDBLength = srb->cmdlen;
+	/* copy the command data into the CBW command data buffer */
+	/* DST SRC LEN!!! */
+	memcpy(cbw.CBWCDB, srb->cmd, srb->cmdlen);
+	result = usb_bulk_msg(us->pusb_dev, pipe, &cbw, UMASS_BBB_CBW_SIZE, &actlen, USB_CNTL_TIMEOUT*5);
+	if (result < 0)
+		USB_STOR_PRINTF("usb_stor_BBB_comdat:usb_bulk_msg error\n");
+	return result;
+}
+
 /* FIXME: we also need a CBI_command which sets up the completion
  * interrupt, and waits for it
  */
@@ -422,6 +562,134 @@ int usb_stor_CBI_get_status(ccb *srb, struct us_data *us)
 #define USB_TRANSPORT_UNKNOWN_RETRY 5
 #define USB_TRANSPORT_NOT_READY_RETRY 10
 
+/* clear a stall on an endpoint - special for BBB devices */
+int usb_stor_BBB_clear_endpt_stall(struct us_data *us, __u8 endpt)
+{
+	int result;
+
+	/* ENDPOINT_HALT = 0, so set value to 0 */
+	result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev,0),
+				USB_REQ_CLEAR_FEATURE, USB_RECIP_ENDPOINT,
+				0, endpt, 0, 0, USB_CNTL_TIMEOUT*5);
+	return result;
+}
+
+int usb_stor_BBB_transport(ccb *srb, struct us_data *us)
+{
+	int result, retry;
+	int dir_in;
+	int actlen, data_actlen;
+	unsigned int pipe, pipein, pipeout;
+	umass_bbb_csw_t csw;
+#ifdef BBB_XPORT_TRACE
+	unsigned char *ptr;
+	int index;
+#endif
+
+	dir_in = US_DIRECTION(srb->cmd[0]);
+
+	/* COMMAND phase */
+	USB_STOR_PRINTF("COMMAND phase\n");
+	result = usb_stor_BBB_comdat(srb, us);
+	if (result < 0) {
+		USB_STOR_PRINTF("failed to send CBW status %ld\n",
+			us->pusb_dev->status);
+		usb_stor_BBB_reset(us);
+		return USB_STOR_TRANSPORT_FAILED;
+	}
+	wait_ms(5);
+	pipein = usb_rcvbulkpipe(us->pusb_dev, us->ep_in);
+	pipeout = usb_sndbulkpipe(us->pusb_dev, us->ep_out);
+	/* DATA phase + error handling */
+	USB_STOR_PRINTF("DATA phase\n");
+	data_actlen = 0;
+	/* no data, go immediately to the STATUS phase */
+	if (srb->datalen == 0)
+		goto st;
+	if (dir_in)
+		pipe = pipein;
+	else
+		pipe = pipeout;
+	result = usb_bulk_msg(us->pusb_dev, pipe, srb->pdata, srb->datalen, &data_actlen, USB_CNTL_TIMEOUT*5);
+	/* special handling of STALL in DATA phase */
+	if((result < 0) && (us->pusb_dev->status & USB_ST_STALLED)) {
+		USB_STOR_PRINTF("DATA:stall\n");
+		/* clear the STALL on the endpoint */
+		result = usb_stor_BBB_clear_endpt_stall(us, dir_in? us->ep_in : us->ep_out);
+		if (result >= 0)
+			/* continue on to STATUS phase */
+			goto st;
+	}
+	if (result < 0) {
+		USB_STOR_PRINTF("usb_bulk_msg error status %ld\n",
+			us->pusb_dev->status);
+		usb_stor_BBB_reset(us);
+		return USB_STOR_TRANSPORT_FAILED;
+	}
+#ifdef BBB_XPORT_TRACE
+	for (index = 0; index < data_actlen; index++)
+		printf("pdata[%d] %#x ", index, srb->pdata[index]);
+	printf("\n");
+#endif
+	/* STATUS phase + error handling */
+   st:
+	retry = 0;
+   again:
+	USB_STOR_PRINTF("STATUS phase\n");
+	result = usb_bulk_msg(us->pusb_dev, pipein, &csw, UMASS_BBB_CSW_SIZE, &actlen, USB_CNTL_TIMEOUT*5);
+	/* special handling of STALL in STATUS phase */
+	if((result < 0) && (retry < 1) && (us->pusb_dev->status & USB_ST_STALLED)) {
+		USB_STOR_PRINTF("STATUS:stall\n");
+		/* clear the STALL on the endpoint */
+		result = usb_stor_BBB_clear_endpt_stall(us, us->ep_in);
+		if (result >= 0 && (retry++ < 1))
+			/* do a retry */
+			goto again;
+	}
+	if (result < 0) {
+		USB_STOR_PRINTF("usb_bulk_msg error status %ld\n",
+			us->pusb_dev->status);
+		usb_stor_BBB_reset(us);
+		return USB_STOR_TRANSPORT_FAILED;
+	}
+#ifdef BBB_XPORT_TRACE
+	ptr = (unsigned char *)&csw;
+	for (index = 0; index < UMASS_BBB_CSW_SIZE; index++)
+		printf("ptr[%d] %#x ", index, ptr[index]);
+	printf("\n");
+#endif
+	/* misuse pipe to get the residue */
+	pipe = swap_32(csw.dCSWDataResidue);
+	if (pipe == 0 && srb->datalen != 0 && srb->datalen - data_actlen != 0)
+		pipe = srb->datalen - data_actlen;
+	if (CSWSIGNATURE != swap_32(csw.dCSWSignature)) {
+		USB_STOR_PRINTF("!CSWSIGNATURE\n");
+		usb_stor_BBB_reset(us);
+		return USB_STOR_TRANSPORT_FAILED;
+	} else if ((CBWTag - 1) != swap_32(csw.dCSWTag)) {
+		USB_STOR_PRINTF("!Tag\n");
+		usb_stor_BBB_reset(us);
+		return USB_STOR_TRANSPORT_FAILED;
+	} else if (csw.bCSWStatus > CSWSTATUS_PHASE) {
+		USB_STOR_PRINTF(">PHASE\n");
+		usb_stor_BBB_reset(us);
+		return USB_STOR_TRANSPORT_FAILED;
+	} else if (csw.bCSWStatus == CSWSTATUS_PHASE) {
+		USB_STOR_PRINTF("=PHASE\n");
+		usb_stor_BBB_reset(us);
+		return USB_STOR_TRANSPORT_FAILED;
+	} else if (data_actlen > srb->datalen) {
+		USB_STOR_PRINTF("transferred %dB instead of %dB\n",
+			data_actlen, srb->datalen);
+		return USB_STOR_TRANSPORT_FAILED;
+	} else if (csw.bCSWStatus == CSWSTATUS_FAILED) {
+		USB_STOR_PRINTF("FAILED\n");
+		return USB_STOR_TRANSPORT_FAILED;
+	}
+
+	return result;
+}
+
 int usb_stor_CB_transport(ccb *srb, struct us_data *us)
 {
 	int result,status;
@@ -495,29 +763,28 @@ do_retry:
 		return USB_STOR_TRANSPORT_GOOD;
 	/* Check the auto request result */
 	switch(srb->sense_buf[2]) {
-		case 0x01: /* Recovered Error */
-			return USB_STOR_TRANSPORT_GOOD;
-		 	break;
-		case 0x02: /* Not Ready */
-			if(notready++ > USB_TRANSPORT_NOT_READY_RETRY) {
-				printf("cmd 0x%02X returned 0x%02X 0x%02X 0x%02X 0x%02X (NOT READY)\n",
-					srb->cmd[0],srb->sense_buf[0],srb->sense_buf[2],srb->sense_buf[12],srb->sense_buf[13]);
-				return USB_STOR_TRANSPORT_FAILED;
-			}
-			else {
-				wait_ms(100);
-				goto do_retry;
-			}
-			break;
-		default:
-			if(retry++ > USB_TRANSPORT_UNKNOWN_RETRY) {
-				printf("cmd 0x%02X returned 0x%02X 0x%02X 0x%02X 0x%02X\n",
-					srb->cmd[0],srb->sense_buf[0],srb->sense_buf[2],srb->sense_buf[12],srb->sense_buf[13]);
-				return USB_STOR_TRANSPORT_FAILED;
-			}
-			else
-				goto do_retry;
-			break;
+	case 0x01: /* Recovered Error */
+		return USB_STOR_TRANSPORT_GOOD;
+	 	break;
+	case 0x02: /* Not Ready */
+		if(notready++ > USB_TRANSPORT_NOT_READY_RETRY) {
+			printf("cmd 0x%02X returned 0x%02X 0x%02X 0x%02X 0x%02X (NOT READY)\n",
+				srb->cmd[0],srb->sense_buf[0],srb->sense_buf[2],srb->sense_buf[12],srb->sense_buf[13]);
+			return USB_STOR_TRANSPORT_FAILED;
+		} else {
+			wait_ms(100);
+			goto do_retry;
+		}
+		break;
+	default:
+		if(retry++ > USB_TRANSPORT_UNKNOWN_RETRY) {
+			printf("cmd 0x%02X returned 0x%02X 0x%02X 0x%02X 0x%02X\n",
+				srb->cmd[0],srb->sense_buf[0],srb->sense_buf[2],srb->sense_buf[12],srb->sense_buf[13]);
+			return USB_STOR_TRANSPORT_FAILED;
+		} else {
+			goto do_retry;
+		}
+		break;
 	}
 	return USB_STOR_TRANSPORT_FAILED;
 }
@@ -538,7 +805,8 @@ static int usb_inquiry(ccb *srb,struct us_data *ss)
 		USB_STOR_PRINTF("inquiry returns %d\n",i);
 		if(i==0)
 			break;
-	}while(retry--);
+	} while(retry--);
+
 	if(!retry) {
 		printf("error in inquiry\n");
 		return -1;
@@ -567,17 +835,18 @@ static int usb_request_sense(ccb *srb,struct us_data *ss)
 static int usb_test_unit_ready(ccb *srb,struct us_data *ss)
 {
 	int retries=10;
+
 	do {
 		memset(&srb->cmd[0],0,12);
 		srb->cmd[0]=SCSI_TST_U_RDY;
 		srb->cmd[1]=srb->lun<<5;
 		srb->datalen=0;
 		srb->cmdlen=12;
-		if(ss->transport(srb,ss)==USB_STOR_TRANSPORT_GOOD)
-		{
+		if(ss->transport(srb,ss)==USB_STOR_TRANSPORT_GOOD) {
 			return 0;
 		}
 	} while(retries--);
+
 	return -1;
 }
 
@@ -594,7 +863,8 @@ static int usb_read_capacity(ccb *srb,struct us_data *ss)
 		if(ss->transport(srb,ss)==USB_STOR_TRANSPORT_GOOD) {
 			return 0;
 		}
-	}while(retry--);
+	} while(retry--);
+
 	return -1;
 }
 
@@ -654,8 +924,7 @@ unsigned long usb_stor_read(int device, unsigned long blknr, unsigned long blkcn
 		srb->pdata=(unsigned char *)buf_addr;
 		if(blks>USB_MAX_READ_BLK) {
 			smallblks=USB_MAX_READ_BLK;
-		}
-		else {
+		} else {
 			smallblks=(unsigned short) blks;
 		}
 retry_it:
@@ -751,6 +1020,11 @@ int usb_storage_probe(struct usb_device *dev, unsigned int ifnum,struct us_data
 		ss->transport = usb_stor_CB_transport;
 		ss->transport_reset = usb_stor_CB_reset;
 		break;
+	case US_PR_BULK:
+		USB_STOR_PRINTF("Bulk/Bulk/Bulk\n");
+		ss->transport = usb_stor_BBB_transport;
+		ss->transport_reset = usb_stor_BBB_reset;
+		break;
 	default:
 		printf("USB Starage Transport unknown / not yet implemented\n");
 		return 0;
@@ -793,23 +1067,22 @@ int usb_storage_probe(struct usb_device *dev, unsigned int ifnum,struct us_data
 		return 0;
 	}
 	/* set class specific stuff */
-	/* We only handle certain protocols.  Currently, this is
-	 * the only one.
+	/* We only handle certain protocols.  Currently, these are
+	 * the only ones.
 	 */
-	if (ss->subclass != US_SC_UFI) {
+	if (ss->subclass != US_SC_UFI && ss->subclass != US_SC_SCSI) {
 		printf("Sorry, protocol %d not yet supported.\n",ss->subclass);
 		return 0;
 	}
-	if(ss->ep_int) /* we had found an interrupt endpoint, prepare irq pipe */
-	{
+	if(ss->ep_int) { /* we had found an interrupt endpoint, prepare irq pipe */
 		/* set up the IRQ pipe and handler */
 
 		ss->irqinterval = (ss->irqinterval > 0) ? ss->irqinterval : 255;
 		ss->irqpipe = usb_rcvintpipe(ss->pusb_dev, ss->ep_int);
 		ss->irqmaxp = usb_maxpacket(dev, ss->irqpipe);
 		dev->irq_handle=usb_stor_irq;
-		dev->privptr=(void *)ss;
 	}
+	dev->privptr=(void *)ss;
 	return 1;
 }
 
@@ -865,6 +1138,19 @@ int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t
 	if(cap[0]>(0x200000 * 10)) /* greater than 10 GByte */
 		cap[0]>>=16;
 #endif
+#ifdef LITTLEENDIAN
+	cap[0] = ((unsigned long)(
+		(((unsigned long)(cap[0]) & (unsigned long)0x000000ffUL) << 24) |
+		(((unsigned long)(cap[0]) & (unsigned long)0x0000ff00UL) <<  8) |
+		(((unsigned long)(cap[0]) & (unsigned long)0x00ff0000UL) >>  8) |
+		(((unsigned long)(cap[0]) & (unsigned long)0xff000000UL) >> 24) ));
+	cap[1] = ((unsigned long)(
+		(((unsigned long)(cap[1]) & (unsigned long)0x000000ffUL) << 24) |
+		(((unsigned long)(cap[1]) & (unsigned long)0x0000ff00UL) <<  8) |
+		(((unsigned long)(cap[1]) & (unsigned long)0x00ff0000UL) >>  8) |
+		(((unsigned long)(cap[1]) & (unsigned long)0xff000000UL) >> 24) ));
+#endif
+	/* this assumes bigendian! */
 	cap[0]+=1;
 	capacity=&cap[0];
 	blksz=&cap[1];
@@ -881,5 +1167,5 @@ int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t
 	return 1;
 }
 
-#endif
 #endif /* CONFIG_USB_STORAGE */
+#endif /* CFG_CMD_USB */

cpu/arm920t/Makefile

@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(CPU).a
 
 START	= start.o
-OBJS	= serial.o interrupts.o cpu.o speed.o
+OBJS	= serial.o interrupts.o cpu.o speed.o usb_ohci.o
 
 all:	.depend $(START) $(LIB)
 

cpu/arm920t/usb_ohci.h

@@ -0,0 +1,420 @@
+/*
+ * URB OHCI HCD (Host Controller Driver) for USB.
+ *
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
+ *
+ * usb-ohci.h
+ */
+
+
+static int cc_to_error[16] = {
+
+/* mapping of the OHCI CC status to error codes */
+	/* No  Error  */               0,
+	/* CRC Error  */               USB_ST_CRC_ERR,
+	/* Bit Stuff  */               USB_ST_BIT_ERR,
+	/* Data Togg  */               USB_ST_CRC_ERR,
+	/* Stall      */               USB_ST_STALLED,
+	/* DevNotResp */               -1,
+	/* PIDCheck   */               USB_ST_BIT_ERR,
+	/* UnExpPID   */               USB_ST_BIT_ERR,
+	/* DataOver   */               USB_ST_BUF_ERR,
+	/* DataUnder  */               USB_ST_BUF_ERR,
+	/* reservd    */               -1,
+	/* reservd    */               -1,
+	/* BufferOver */               USB_ST_BUF_ERR,
+	/* BuffUnder  */               USB_ST_BUF_ERR,
+	/* Not Access */               -1,
+	/* Not Access */               -1
+};
+
+/* ED States */
+
+#define ED_NEW 		0x00
+#define ED_UNLINK 	0x01
+#define ED_OPER		0x02
+#define ED_DEL		0x04
+#define ED_URB_DEL  	0x08
+
+/* usb_ohci_ed */
+struct ed {
+	__u32 hwINFO;
+	__u32 hwTailP;
+	__u32 hwHeadP;
+	__u32 hwNextED;
+
+	struct ed *ed_prev;
+	__u8 int_period;
+	__u8 int_branch;
+	__u8 int_load;
+	__u8 int_interval;
+	__u8 state;
+	__u8 type;
+	__u16 last_iso;
+	struct ed *ed_rm_list;
+
+	struct usb_device *usb_dev;
+	__u32 unused[3];
+} __attribute((aligned(16)));
+typedef struct ed ed_t;
+
+
+/* TD info field */
+#define TD_CC       0xf0000000
+#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
+#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
+#define TD_EC       0x0C000000
+#define TD_T        0x03000000
+#define TD_T_DATA0  0x02000000
+#define TD_T_DATA1  0x03000000
+#define TD_T_TOGGLE 0x00000000
+#define TD_R        0x00040000
+#define TD_DI       0x00E00000
+#define TD_DI_SET(X) (((X) & 0x07)<< 21)
+#define TD_DP       0x00180000
+#define TD_DP_SETUP 0x00000000
+#define TD_DP_IN    0x00100000
+#define TD_DP_OUT   0x00080000
+
+#define TD_ISO	    0x00010000
+#define TD_DEL      0x00020000
+
+/* CC Codes */
+#define TD_CC_NOERROR      0x00
+#define TD_CC_CRC          0x01
+#define TD_CC_BITSTUFFING  0x02
+#define TD_CC_DATATOGGLEM  0x03
+#define TD_CC_STALL        0x04
+#define TD_DEVNOTRESP      0x05
+#define TD_PIDCHECKFAIL    0x06
+#define TD_UNEXPECTEDPID   0x07
+#define TD_DATAOVERRUN     0x08
+#define TD_DATAUNDERRUN    0x09
+#define TD_BUFFEROVERRUN   0x0C
+#define TD_BUFFERUNDERRUN  0x0D
+#define TD_NOTACCESSED     0x0F
+
+
+#define MAXPSW 1
+
+struct td {
+	__u32 hwINFO;
+  	__u32 hwCBP;		/* Current Buffer Pointer */
+  	__u32 hwNextTD;		/* Next TD Pointer */
+  	__u32 hwBE;		/* Memory Buffer End Pointer */
+
+  	__u16 hwPSW[MAXPSW];
+  	__u8 unused;
+  	__u8 index;
+  	struct ed *ed;
+  	struct td *next_dl_td;
+	struct usb_device *usb_dev;
+	int transfer_len;
+	__u32 data;
+
+	__u32 unused2[2];
+} __attribute((aligned(32)));
+typedef struct td td_t;
+
+#define OHCI_ED_SKIP	(1 << 14)
+
+/*
+ * The HCCA (Host Controller Communications Area) is a 256 byte
+ * structure defined in the OHCI spec. that the host controller is
+ * told the base address of.  It must be 256-byte aligned.
+ */
+
+#define NUM_INTS 32	/* part of the OHCI standard */
+struct ohci_hcca {
+	__u32	int_table[NUM_INTS];	/* Interrupt ED table */
+	__u16	frame_no;		/* current frame number */
+	__u16	pad1;			/* set to 0 on each frame_no change */
+	__u32	done_head;		/* info returned for an interrupt */
+	u8		reserved_for_hc[116];
+} __attribute((aligned(256)));
+
+
+/*
+ * Maximum number of root hub ports.
+ */
+#define MAX_ROOT_PORTS	15	/* maximum OHCI root hub ports */
+
+/*
+ * This is the structure of the OHCI controller's memory mapped I/O
+ * region.  This is Memory Mapped I/O.  You must use the readl() and
+ * writel() macros defined in asm/io.h to access these!!
+ */
+struct ohci_regs {
+	/* control and status registers */
+	__u32	revision;
+	__u32	control;
+	__u32	cmdstatus;
+	__u32	intrstatus;
+	__u32	intrenable;
+	__u32	intrdisable;
+	/* memory pointers */
+	__u32	hcca;
+	__u32	ed_periodcurrent;
+	__u32	ed_controlhead;
+	__u32	ed_controlcurrent;
+	__u32	ed_bulkhead;
+	__u32	ed_bulkcurrent;
+	__u32	donehead;
+	/* frame counters */
+	__u32	fminterval;
+	__u32	fmremaining;
+	__u32	fmnumber;
+	__u32	periodicstart;
+	__u32	lsthresh;
+	/* Root hub ports */
+	struct	ohci_roothub_regs {
+		__u32	a;
+		__u32	b;
+		__u32	status;
+		__u32	portstatus[MAX_ROOT_PORTS];
+	} roothub;
+} __attribute((aligned(32)));
+
+
+/* OHCI CONTROL AND STATUS REGISTER MASKS */
+
+/*
+ * HcControl (control) register masks
+ */
+#define OHCI_CTRL_CBSR	(3 << 0)	/* control/bulk service ratio */
+#define OHCI_CTRL_PLE	(1 << 2)	/* periodic list enable */
+#define OHCI_CTRL_IE	(1 << 3)	/* isochronous enable */
+#define OHCI_CTRL_CLE	(1 << 4)	/* control list enable */
+#define OHCI_CTRL_BLE	(1 << 5)	/* bulk list enable */
+#define OHCI_CTRL_HCFS	(3 << 6)	/* host controller functional state */
+#define OHCI_CTRL_IR	(1 << 8)	/* interrupt routing */
+#define OHCI_CTRL_RWC	(1 << 9)	/* remote wakeup connected */
+#define OHCI_CTRL_RWE	(1 << 10)	/* remote wakeup enable */
+
+/* pre-shifted values for HCFS */
+#	define OHCI_USB_RESET	(0 << 6)
+#	define OHCI_USB_RESUME	(1 << 6)
+#	define OHCI_USB_OPER	(2 << 6)
+#	define OHCI_USB_SUSPEND	(3 << 6)
+
+/*
+ * HcCommandStatus (cmdstatus) register masks
+ */
+#define OHCI_HCR	(1 << 0)	/* host controller reset */
+#define OHCI_CLF  	(1 << 1)	/* control list filled */
+#define OHCI_BLF  	(1 << 2)	/* bulk list filled */
+#define OHCI_OCR  	(1 << 3)	/* ownership change request */
+#define OHCI_SOC  	(3 << 16)	/* scheduling overrun count */
+
+/*
+ * masks used with interrupt registers:
+ * HcInterruptStatus (intrstatus)
+ * HcInterruptEnable (intrenable)
+ * HcInterruptDisable (intrdisable)
+ */
+#define OHCI_INTR_SO	(1 << 0)	/* scheduling overrun */
+#define OHCI_INTR_WDH	(1 << 1)	/* writeback of done_head */
+#define OHCI_INTR_SF	(1 << 2)	/* start frame */
+#define OHCI_INTR_RD	(1 << 3)	/* resume detect */
+#define OHCI_INTR_UE	(1 << 4)	/* unrecoverable error */
+#define OHCI_INTR_FNO	(1 << 5)	/* frame number overflow */
+#define OHCI_INTR_RHSC	(1 << 6)	/* root hub status change */
+#define OHCI_INTR_OC	(1 << 30)	/* ownership change */
+#define OHCI_INTR_MIE	(1 << 31)	/* master interrupt enable */
+
+
+
+/* Virtual Root HUB */
+struct virt_root_hub {
+	int devnum; /* Address of Root Hub endpoint */
+	void *dev;  /* was urb */
+	void *int_addr;
+	int send;
+	int interval;
+};
+
+/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
+
+/* destination of request */
+#define RH_INTERFACE               0x01
+#define RH_ENDPOINT                0x02
+#define RH_OTHER                   0x03
+
+#define RH_CLASS                   0x20
+#define RH_VENDOR                  0x40
+
+/* Requests: bRequest << 8 | bmRequestType */
+#define RH_GET_STATUS           0x0080
+#define RH_CLEAR_FEATURE        0x0100
+#define RH_SET_FEATURE          0x0300
+#define RH_SET_ADDRESS		0x0500
+#define RH_GET_DESCRIPTOR	0x0680
+#define RH_SET_DESCRIPTOR       0x0700
+#define RH_GET_CONFIGURATION	0x0880
+#define RH_SET_CONFIGURATION	0x0900
+#define RH_GET_STATE            0x0280
+#define RH_GET_INTERFACE        0x0A80
+#define RH_SET_INTERFACE        0x0B00
+#define RH_SYNC_FRAME           0x0C80
+/* Our Vendor Specific Request */
+#define RH_SET_EP               0x2000
+
+
+/* Hub port features */
+#define RH_PORT_CONNECTION         0x00
+#define RH_PORT_ENABLE             0x01
+#define RH_PORT_SUSPEND            0x02
+#define RH_PORT_OVER_CURRENT       0x03
+#define RH_PORT_RESET              0x04
+#define RH_PORT_POWER              0x08
+#define RH_PORT_LOW_SPEED          0x09
+
+#define RH_C_PORT_CONNECTION       0x10
+#define RH_C_PORT_ENABLE           0x11
+#define RH_C_PORT_SUSPEND          0x12
+#define RH_C_PORT_OVER_CURRENT     0x13
+#define RH_C_PORT_RESET            0x14
+
+/* Hub features */
+#define RH_C_HUB_LOCAL_POWER       0x00
+#define RH_C_HUB_OVER_CURRENT      0x01
+
+#define RH_DEVICE_REMOTE_WAKEUP    0x00
+#define RH_ENDPOINT_STALL          0x01
+
+#define RH_ACK                     0x01
+#define RH_REQ_ERR                 -1
+#define RH_NACK                    0x00
+
+
+/* OHCI ROOT HUB REGISTER MASKS */
+
+/* roothub.portstatus [i] bits */
+#define RH_PS_CCS            0x00000001   	/* current connect status */
+#define RH_PS_PES            0x00000002   	/* port enable status*/
+#define RH_PS_PSS            0x00000004   	/* port suspend status */
+#define RH_PS_POCI           0x00000008   	/* port over current indicator */
+#define RH_PS_PRS            0x00000010  	/* port reset status */
+#define RH_PS_PPS            0x00000100   	/* port power status */
+#define RH_PS_LSDA           0x00000200    	/* low speed device attached */
+#define RH_PS_CSC            0x00010000 	/* connect status change */
+#define RH_PS_PESC           0x00020000   	/* port enable status change */
+#define RH_PS_PSSC           0x00040000    	/* port suspend status change */
+#define RH_PS_OCIC           0x00080000    	/* over current indicator change */
+#define RH_PS_PRSC           0x00100000   	/* port reset status change */
+
+/* roothub.status bits */
+#define RH_HS_LPS	     0x00000001		/* local power status */
+#define RH_HS_OCI	     0x00000002		/* over current indicator */
+#define RH_HS_DRWE	     0x00008000		/* device remote wakeup enable */
+#define RH_HS_LPSC	     0x00010000		/* local power status change */
+#define RH_HS_OCIC	     0x00020000		/* over current indicator change */
+#define RH_HS_CRWE	     0x80000000		/* clear remote wakeup enable */
+
+/* roothub.b masks */
+#define RH_B_DR		0x0000ffff		/* device removable flags */
+#define RH_B_PPCM	0xffff0000		/* port power control mask */
+
+/* roothub.a masks */
+#define	RH_A_NDP	(0xff << 0)		/* number of downstream ports */
+#define	RH_A_PSM	(1 << 8)		/* power switching mode */
+#define	RH_A_NPS	(1 << 9)		/* no power switching */
+#define	RH_A_DT		(1 << 10)		/* device type (mbz) */
+#define	RH_A_OCPM	(1 << 11)		/* over current protection mode */
+#define	RH_A_NOCP	(1 << 12)		/* no over current protection */
+#define	RH_A_POTPGT	(0xff << 24)		/* power on to power good time */
+
+/* urb */
+#define N_URB_TD 48
+typedef struct
+{
+	ed_t *ed;
+	__u16 length;	/* number of tds associated with this request */
+	__u16 td_cnt;	/* number of tds already serviced */
+	int   state;
+	unsigned long pipe;
+	int actual_length;
+	td_t *td[N_URB_TD];	/* list pointer to all corresponding TDs associated with this request */
+} urb_priv_t;
+#define URB_DEL 1
+
+/*
+ * This is the full ohci controller description
+ *
+ * Note how the "proper" USB information is just
+ * a subset of what the full implementation needs. (Linus)
+ */
+
+
+typedef struct ohci {
+	struct ohci_hcca *hcca;		/* hcca */
+	/*dma_addr_t hcca_dma;*/
+
+	int irq;
+	int disabled;			/* e.g. got a UE, we're hung */
+	int sleeping;
+	unsigned long flags;		/* for HC bugs */
+
+	struct ohci_regs *regs;	/* OHCI controller's memory */
+
+	ed_t *ed_rm_list[2];     /* lists of all endpoints to be removed */
+	ed_t *ed_bulktail;       /* last endpoint of bulk list */
+	ed_t *ed_controltail;    /* last endpoint of control list */
+	int intrstatus;
+	__u32 hc_control;		/* copy of the hc control reg */
+	struct usb_device *dev[32];
+	struct virt_root_hub rh;
+
+	const char	*slot_name;
+} ohci_t;
+
+#define NUM_EDS 8		/* num of preallocated endpoint descriptors */
+
+struct ohci_device {
+	ed_t 	ed[NUM_EDS];
+	int ed_cnt;
+};
+
+/* hcd */
+/* endpoint */
+static int ep_link(ohci_t * ohci, ed_t * ed);
+static int ep_unlink(ohci_t * ohci, ed_t * ed);
+static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe);
+
+/*-------------------------------------------------------------------------*/
+
+/* we need more TDs than EDs */
+#define NUM_TD 64
+
+/* +1 so we can align the storage */
+td_t gtd[NUM_TD+1];
+/* pointers to aligned storage */
+td_t *ptd;
+
+/* TDs ... */
+static inline struct td *
+td_alloc (struct usb_device *usb_dev)
+{
+	int i;
+	struct td	*td;
+
+	td = NULL;
+	for (i = 0; i < NUM_TD; i++)
+	{
+		if (ptd[i].usb_dev == NULL)
+		{
+			td = &ptd[i];
+			td->usb_dev = usb_dev;
+			break;
+		}
+	}
+
+	return td;
+}
+
+static inline void
+ed_free (struct ed *ed)
+{
+	ed->usb_dev = NULL;
+}

cpu/mpc824x/Makefile

@@ -25,14 +25,14 @@ include $(TOPDIR)/config.mk
 
 LIB	= lib$(CPU).a
 
-START	= start.S drivers/i2c/i2c2.o
+START	= start.S
 OBJS	= traps.o cpu.o cpu_init.o interrupts.o speed.o \
-	  drivers/epic/epic1.o drivers/i2c/i2c1.o pci.o bedbug_603e.o
+	  drivers/epic/epic1.o drivers/i2c/i2c.o pci.o bedbug_603e.o
 
 all:	.depend $(START) $(LIB)
 
 $(LIB):	$(OBJS)
-	$(AR) crv $@ $(OBJS) drivers/i2c/i2c2.o
+	$(AR) crv $@ $(OBJS)
 
 bedbug_603e.c:
 	ln -s ../mpc8260/bedbug_603e.c bedbug_603e.c

cpu/mpc824x/drivers/i2c/Makefile

@@ -1,84 +0,0 @@
-##########################################################################
-#
-#       Copyright Motorola, Inc. 1997
-#       ALL RIGHTS RESERVED
-#
-#       You are hereby granted a copyright license to use, modify, and
-#       distribute the SOFTWARE so long as this entire notice is retained
-#       without alteration in any modified and/or redistributed versions,
-#       and that such modified versions are clearly identified as such.
-#       No licenses are granted by implication, estoppel or otherwise under
-#       any patents or trademarks of Motorola, Inc.
-#
-#       The SOFTWARE is provided on an "AS IS" basis and without warranty.
-#       To the maximum extent permitted by applicable law, MOTOROLA DISCLAIMS
-#       ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING IMPLIED
-#       WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
-#       PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
-#       REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS
-#       THEREOF) AND ANY ACCOMPANYING WRITTEN MATERIALS.
-#
-#       To the maximum extent permitted by applicable law, IN NO EVENT SHALL
-#       MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
-#       (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF
-#       BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS
-#       INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OF THE USE OR
-#       INABILITY TO USE THE SOFTWARE.
-#
-############################################################################
-TARGET = libi2c.a
-
-#DEBUG  = -g
-DEBUG   = -DI2CDBG
-LST     = -Hanno -S
-OPTIM   =
-CC      = /risc/tools/pkgs/metaware/bin/hcppc
-CFLAGS  = -Hnocopyr -c -Hsds -Hon=Char_default_unsigned -Hon=Char_is_rep -I../inc -I/risc/tools/pkgs/metaware/inc
-CCobj   = $(CC) $(CFLAGS) $(DEBUG) $(OPTIM)
-PREP    = $(CC) $(CFLAGS) -P
-
-# Assembler used to build the .s files (for the board version)
-
-ASOPT   = -big_si -c
-ASDEBUG = -l -fm
-AS      = /risc/tools/pkgs/metaware/bin/asppc
-
-# Linker to bring .o files together into an executable.
-
-LKOPT	=  -Bbase=0 -q -Qn -r
-LKCMD   =
-LINK    =  /risc/tools/pkgs/metaware/bin/ldppc $(LKCMD) $(LKOPT)
-
-# DOS Utilities
-
-DEL     = rm
-COPY    = cp
-LIST    = ls
-
-OBJECTS = i2c1.o i2c2.o
-
-all: $(TARGET)
-
-objects: $(OBJECTS)
-
-$(TARGET): $(OBJECTS)
-	$(LINK) $(OBJECTS) -o $@
-
-clean:
-	$(DEL) -f *.o *.i *.map *.lst $(TARGET) $(OBJECTS)
-
-.s.o:
-	$(DEL) -f $*.i
-	$(PREP) -Hasmcpp $<
-	$(AS) $(ASOPT) $*.i
-#	$(AS) $(ASOPT) $(ASDEBUG) $*.i > $*.lst
-
-.c.o:
-	$(CCobj) $<
-
-.c.s:
-	$(CCobj) $(LST) $<
-
-i2c1.o: i2c_export.h i2c.h i2c1.c
-
-i2c2.o: i2c.h i2c2.s

cpu/mpc824x/drivers/i2c/Makefile_pc

@@ -1,91 +0,0 @@
-##########################################################################
-#
-#       makefile_pc for use with PC mksnt tools  dink32/drivers/i2c
-#
-#       Copyright Motorola, Inc. 1997
-#       ALL RIGHTS RESERVED
-#
-#       You are hereby granted a copyright license to use, modify, and
-#       distribute the SOFTWARE so long as this entire notice is retained
-#       without alteration in any modified and/or redistributed versions,
-#       and that such modified versions are clearly identified as such.
-#       No licenses are granted by implication, estoppel or otherwise under
-#       any patents or trademarks of Motorola, Inc.
-#
-#       The SOFTWARE is provided on an "AS IS" basis and without warranty.
-#       To the maximum extent permitted by applicable law, MOTOROLA DISCLAIMS
-#       ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING IMPLIED
-#       WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
-#       PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
-#       REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS
-#       THEREOF) AND ANY ACCOMPANYING WRITTEN MATERIALS.
-#
-#       To the maximum extent permitted by applicable law, IN NO EVENT SHALL
-#       MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
-#       (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF
-#       BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS
-#       INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OF THE USE OR
-#       INABILITY TO USE THE SOFTWARE.
-#
-############################################################################
-TARGET = libi2c.a
-
-#DEBUG  = -g
-DEBUG   = -DI2CDBG
-LST     = -Hanno -S
-OPTIM   =
-CC      = m:/old_tools/tools/hcppc/bin/hcppc
-CFLAGS  = -Hnocopyr -c -Hsds -Hon=Char_default_unsigned -Hon=Char_is_rep -I../inc -I/risc/tools/pkgs/metaware/inc
-CCobj   = $(CC) $(CFLAGS) $(DEBUG) $(OPTIM)
-PREP    = $(CC) $(CFLAGS) -P
-
-# Assembler used to build the .s files (for the board version)
-
-ASOPT   = -big_si -c
-ASDEBUG = -l -fm
-AS      = m:/old_tools/tools/hcppc/bin/asppc
-
-# Linker to bring .o files together into an executable.
-
-LKOPT	=  -Bbase=0 -q -Qn -r
-LKCMD   =
-LINK    = m:/old_tools/tools/hcppc/bin/ldppc $(LKCMD) $(LKOPT)
-
-# DOS Utilities
-
-DEL     = rm
-COPY    = cp
-LIST    = ls
-
-OBJECTS = i2c1.o i2c2.o
-
-all: $(TARGET)
-
-objects: $(OBJECTS)
-
-$(TARGET): $(OBJECTS)
-	$(LINK) $(OBJECTS) -o $@
-
-clean:
-	$(DEL) -f *.o *.i *.map *.lst $(TARGET) $(OBJECTS)
-
-.s.o:
-	$(DEL) -f $*.i
-	$(PREP) -Hasmcpp $<
-	$(AS) $(ASOPT) $*.i
-#	$(AS) $(ASOPT) $(ASDEBUG) $*.i > $*.lst
-
-.c.o:
-	$(CCobj) $<
-
-.c.s:
-	$(CCobj) $(LST) $<
-
-i2c1.o: i2c_export.h i2c.h i2c1.c
-	$(CCobj) $<
-
-
-i2c2.o: i2c.h i2c2.s
-	$(DEL) -f $*.i
-	$(PREP) -Hasmcpp $<
-	$(AS) $(ASOPT) $*.i

cpu/mpc824x/drivers/i2c/README

@@ -1,104 +0,0 @@
-CONTENT:
-
-   i2c.h
-   i2c1.c
-   i2c2.s
-
-WHAT ARE THESE FILES:
-
-These files contain MPC8240 (Kahlua) I2C
-driver routines. The driver routines are not
-written for any specific operating system.
-They serves the purpose of code sample, and
-jump-start for using the MPC8240 I2C unit.
-
-For the reason of correctness of C language
-syntax, these files are compiled by Metaware
-C compiler and assembler.
-
-ENDIAN NOTATION:
-
-The algorithm is designed for big-endian mode,
-software is responsible for byte swapping.
-
-USAGE:
-
-1. The host system that is running on MPC8240
-   shall link the files listed here. The memory
-   location of driver routines shall take into
-   account of that driver routines need to run
-   in supervisor mode and they process I2C
-   interrupt.
-
-2. The host system is responsible for configuring
-   the MPC8240 including Embedded Utilities Memory
-   Block. All I2C driver functions require the
-   content of Embedded Utilities Memory Block
-   Base Address Register, EUMBBAR, as the first
-   parameter.
-
-3. Before I2C unit of MPC8240 can be used,
-   initialize I2C unit by calling I2C_Init
-   with the corresponding parameters.
-
-   Note that the I2CFDR register shall be written
-   once during the initialization. If it is written
-   in the midst of transers, or after I2C STOPs or
-   REPEAT STATRs, depending on the data written,
-   a long reset time may be encountered.
-
-4. After I2C unit has been successfully initialized,
-   use the Application level API to send data or
-   receive data upon the desired mode, Master or
-   Slave.
-
-5. If the host system is also using the EPIC unit
-   on MPC8240, the system can register the
-   I2C_ISR with the EPIC including other
-   desired resources.
-
-   If the host system does not using the EPIC unit
-   on MPC8240, I2C_Timer_Event function can
-   be called for each desired time interval.
-
-   In both cases, the host system is free to provide
-   its own timer event handler and interrupt service
-   routine.
-
-6. The I2C driver routines contains a set
-   of utilities, Set and Get, for host system
-   to query and modify the desired I2C registers.
-
-7. It is the host system's responsibility of
-   queueing the I2C I/O request. The host
-   system shall check the I2C_ISR return code
-   for I2C I/O status. If I2C_ISR returns
-   I2CBUFFEMPTY or I2CBUFFFULL, it means
-   I2C unit has completed a I/O request
-   stated by the Application API.
-
-8. If the host system has more than one master
-   mode I2C unit I/O requests but doesn't want
-   to be intervented by being addressed as slave,
-   the host system can use the master mode
-   Application API with stop_flag set to 0 in
-   conjunction with is_cnt flag set to 1.
-   The first API call sets both stop_flag and
-   is_cnt to 0, indicating a START condition
-   shall be generated but when the end of
-   transaction is reached, do not generate a
-   STOP condition. Once the host system is
-   informed that the transaction has been
-   completed, the next Application API call
-   shall set is_cnt flag to 1, indicating a
-   repeated START condition shall be generated.
-   The last Application API call shall set
-   stop_flag
-   to 1.
-
-9. The I2C_Timer_Event function containes
-   a user defined function pointer. It
-   serves the purpose of providing the
-   host system a way to use its own event
-   handler instead of the I2C_ISR provided
-   here.

cpu/mpc824x/drivers/i2c/i2c.c

@@ -0,0 +1,284 @@
+/*
+ * (C) Copyright 2003
+ * Gleb Natapov <gnatapov@mrv.com>
+ * Some bits are taken from linux driver writen by adrian@humboldt.co.uk
+ *
+ * Hardware I2C driver for MPC107 PCI bridge.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#undef I2CDBG
+
+#ifdef CONFIG_HARD_I2C
+#include <i2c.h>
+
+#define TIMEOUT (CFG_HZ/4)
+
+#define I2C_Addr ((unsigned *)(CFG_EUMB_ADDR + 0x3000))
+
+#define I2CADR &I2C_Addr[0]
+#define I2CFDR  &I2C_Addr[1]
+#define I2CCCR  &I2C_Addr[2]
+#define I2CCSR  &I2C_Addr[3]
+#define I2CCDR  &I2C_Addr[4]
+
+#define MPC107_CCR_MEN  0x80
+#define MPC107_CCR_MIEN 0x40
+#define MPC107_CCR_MSTA 0x20
+#define MPC107_CCR_MTX  0x10
+#define MPC107_CCR_TXAK 0x08
+#define MPC107_CCR_RSTA 0x04
+
+#define MPC107_CSR_MCF  0x80
+#define MPC107_CSR_MAAS 0x40
+#define MPC107_CSR_MBB  0x20
+#define MPC107_CSR_MAL  0x10
+#define MPC107_CSR_SRW  0x04
+#define MPC107_CSR_MIF  0x02
+#define MPC107_CSR_RXAK 0x01
+
+#define I2C_READ  1
+#define I2C_WRITE 0
+
+/* taken from linux include/asm-ppc/io.h */
+inline unsigned in_le32 (volatile unsigned *addr)
+{
+	unsigned ret;
+
+	__asm__ __volatile__ ("lwbrx %0,0,%1;\n"
+			      "twi 0,%0,0;\n"
+			      "isync":"=r" (ret): "r" (addr), "m" (*addr));
+	return ret;
+}
+
+inline void out_le32 (volatile unsigned *addr, int val)
+{
+	__asm__ __volatile__ ("stwbrx %1,0,%2; eieio":"=m" (*addr):"r" (val),
+			      "r" (addr));
+}
+
+#define writel(val, addr) out_le32(addr, val)
+#define readl(addr) in_le32(addr)
+
+void i2c_init (int speed, int slaveadd)
+{
+	/* stop I2C controller */
+	writel (0x0, I2CCCR);
+	/* set clock */
+	writel (0x1020, I2CFDR);
+	/* write slave address */
+	writel (slaveadd, I2CADR);
+	/* clear status register */
+	writel (0x0, I2CCSR);
+	/* start I2C controller */
+	writel (MPC107_CCR_MEN, I2CCCR);
+
+	return;
+}
+
+static __inline__ int i2c_wait4bus (void)
+{
+	ulong timeval = get_timer (0);
+
+	while (readl (I2CCSR) & MPC107_CSR_MBB)
+		if (get_timer (timeval) > TIMEOUT)
+			return -1;
+
+	return 0;
+}
+
+static __inline__ int i2c_wait (int write)
+{
+	u32 csr;
+	ulong timeval = get_timer (0);
+
+	do {
+		csr = readl (I2CCSR);
+
+		if (!(csr & MPC107_CSR_MIF))
+			continue;
+
+		writel (0x0, I2CCSR);
+
+		if (csr & MPC107_CSR_MAL) {
+#ifdef I2CDBG
+			printf ("i2c_wait: MAL\n");
+#endif
+			return -1;
+		}
+
+		if (!(csr & MPC107_CSR_MCF)) {
+#ifdef I2CDBG
+			printf ("i2c_wait: unfinished\n");
+#endif
+			return -1;
+		}
+
+		if (write == I2C_WRITE && (csr & MPC107_CSR_RXAK)) {
+#ifdef I2CDBG
+			printf ("i2c_wait: No RXACK\n");
+#endif
+			return -1;
+		}
+
+		return 0;
+	} while (get_timer (timeval) < TIMEOUT);
+
+#ifdef I2CDBG
+	printf ("i2c_wait: timed out\n");
+#endif
+	return -1;
+}
+
+static __inline__ int i2c_write_addr (u8 dev, u8 dir, int rsta)
+{
+	writel (MPC107_CCR_MEN | MPC107_CCR_MSTA | MPC107_CCR_MTX |
+		(rsta ? MPC107_CCR_RSTA : 0), I2CCCR);
+
+	writel ((dev << 1) | dir, I2CCDR);
+
+	if (i2c_wait (I2C_WRITE) < 0)
+		return 0;
+
+	return 1;
+}
+
+static __inline__ int __i2c_write (u8 * data, int length)
+{
+	int i;
+
+	writel (MPC107_CCR_MEN | MPC107_CCR_MSTA | MPC107_CCR_MTX, I2CCCR);
+
+	for (i = 0; i < length; i++) {
+		writel (data[i], I2CCDR);
+
+		if (i2c_wait (I2C_WRITE) < 0)
+			break;
+	}
+
+	return i;
+}
+
+static __inline__ int __i2c_read (u8 * data, int length)
+{
+	int i;
+
+	writel (MPC107_CCR_MEN | MPC107_CCR_MSTA |
+		((length == 1) ? MPC107_CCR_TXAK : 0), I2CCCR);
+
+	/* dummy read */
+	readl (I2CCDR);
+
+	for (i = 0; i < length; i++) {
+		if (i2c_wait (I2C_READ) < 0)
+			break;
+
+		/* Generate ack on last next to last byte */
+		if (i == length - 2)
+			writel (MPC107_CCR_MEN | MPC107_CCR_MSTA |
+				MPC107_CCR_TXAK, I2CCCR);
+
+		/* Generate stop on last byte */
+		if (i == length - 1)
+			writel (MPC107_CCR_MEN | MPC107_CCR_TXAK, I2CCCR);
+
+		data[i] = readl (I2CCDR);
+	}
+
+	return i;
+}
+
+int i2c_read (u8 dev, uint addr, int alen, u8 * data, int length)
+{
+	int i = 0;
+	u8 *a = (u8 *) & addr;
+
+	if (i2c_wait4bus () < 0)
+		goto exit;
+
+	if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
+		goto exit;
+
+	if (__i2c_write (&a[4 - alen], alen) != alen)
+		goto exit;
+
+	if (i2c_write_addr (dev, I2C_READ, 1) == 0)
+		goto exit;
+
+	i = __i2c_read (data, length);
+
+exit:
+	writel (MPC107_CCR_MEN, I2CCCR);
+
+	return !(i == length);
+}
+
+int i2c_write (u8 dev, uint addr, int alen, u8 * data, int length)
+{
+	int i = 0;
+	u8 *a = (u8 *) & addr;
+
+	if (i2c_wait4bus () < 0)
+		goto exit;
+
+	if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
+		goto exit;
+
+	if (__i2c_write (&a[4 - alen], alen) != alen)
+		goto exit;
+
+	i = __i2c_write (data, length);
+
+exit:
+	writel (MPC107_CCR_MEN, I2CCCR);
+
+	return !(i == length);
+}
+
+int i2c_probe (uchar chip)
+{
+	int tmp;
+
+	/*
+	 * Try to read the first location of the chip.  The underlying
+	 * driver doesn't appear to support sending just the chip address
+	 * and looking for an <ACK> back.
+	 */
+	udelay (10000);
+	return i2c_read (chip, 0, 1, (char *) &tmp, 1);
+}
+
+uchar i2c_reg_read (uchar i2c_addr, uchar reg)
+{
+	char buf[1];
+
+	i2c_read (i2c_addr, reg, 1, buf, 1);
+
+	return (buf[0]);
+}
+
+void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val)
+{
+	i2c_write (i2c_addr, reg, 1, &val, 1);
+}
+
+#endif /* CONFIG_HARD_I2C */

cpu/mpc824x/drivers/i2c/i2c.h

@@ -1,309 +0,0 @@
-#ifndef I2C_H
-#define I2C_H
-
-/****************************************************
- *
- * Copyright Motrola 1999
- *
- ****************************************************/
-#define get_eumbbar() CFG_EUMB_ADDR
-
-#define I2CADR    0x00003000
-#define I2CFDR    0x00003004
-#define I2CCR     0x00003008
-#define I2CSR     0x0000300C
-#define I2CDR     0x00003010
-
-typedef enum _i2cstatus
-{
- I2CSUCCESS     = 0x3000,
- I2CADDRESS,
- I2CERROR,
- I2CBUFFFULL,
- I2CBUFFEMPTY,
- I2CXMITERROR,
- I2CRCVERROR,
- I2CBUSBUSY,
- I2CALOSS,
- I2CNOEVENT,
-} I2CStatus;
-
-typedef enum i2c_control
-{
- MEN  = 0x00000080,
- MIEN = 0x00000040,
- MSTA = 0x00000020,
- MTX  = 0x00000010,
- TXAK = 0x00000008,
- RSTA = 0x00000004,
-} I2C_CONTROL;
-
-typedef enum i2c_status
-{
-  MCF   =  0x00000080,
-  MAAS  =  0x00000040,
-  MBB   =  0x00000020,
-  MAL   =  0x00000010,
-  SRW   =  0x00000004,
-  MIF   =  0x00000002,
-  RXAK  =  0x00000001,
-} I2C_STATUS;
-
-typedef struct _i2c_ctrl
-{
-	unsigned int reserved0 : 24;
-	unsigned int men       : 1;
-	unsigned int mien      : 1;
-	unsigned int msta      : 1;
-	unsigned int mtx       : 1;
-	unsigned int txak      : 1;
-	unsigned int rsta      : 1;
-	unsigned int reserved1 : 2;
-} I2C_CTRL;
-
-typedef struct _i2c_stat
-{
-	unsigned int rsrv0    : 24;
-	unsigned int mcf      : 1;
-	unsigned int maas     : 1;
-	unsigned int mbb      : 1;
-	unsigned int mal      : 1;
-	unsigned int rsrv1    : 1;
-	unsigned int srw      : 1;
-	unsigned int mif      : 1;
-	unsigned int rxak     : 1;
-} I2C_STAT;
-
-typedef enum _i2c_mode
-{
-	RCV =  0,
-	XMIT = 1,
-} I2C_MODE;
-
-/******************** App. API ********************
- * The application API is for user level application
- * to use the funcitonality provided by I2C driver
- *
- * Note: Its App.s responsibility to swap the data
- *       byte. In our API, we just transfer whatever
- *       we are given
- **************************************************/
-/**
- * Note:
- *
- * In all following functions,
- * the caller shall pass the configured embedded utility memory
- * block base, EUMBBAR.
- **/
-
-/* Send a buffer of data to the intended rcv_addr.
- * If stop_flag is set, after the whole buffer
- * is sent, generate a STOP signal provided that the
- * receiver doesn't signal the STOP in the middle.
- * I2C is the master performing transmitting. If
- * no STOP signal is generated at the end of current
- * transaction, the master can generate a START signal
- * to another slave addr.
- *
- * return I2CSUCCESS if no error.
- */
-static I2CStatus I2C_put( unsigned int  eumbbar,
-						  unsigned char rcv_addr,    /* receiver's address */
-			      unsigned char *buffer_ptr, /* pointer of data to be sent */
-					      unsigned int  length,      /* number of byte of in the buffer */
-					      unsigned int  stop_flag,   /* 1 - signal STOP when buffer is empty
-									  * 0 - no STOP signal when buffer is empty
-												  */
-						  unsigned int  is_cnt );    /* 1 - this is a restart, don't check MBB
-						      * 0 - this is a new start, check MBB
-													  */
-
-/* Receive a buffer of data from the desired sender_addr
- * If stop_flag is set, when the buffer is full and the
- * sender does not signal STOP, generate a STOP signal.
- * I2C is the master performing receiving. If no STOP signal
- * is generated, the master can generate a START signal
- * to another slave addr.
- *
- * return I2CSUCCESS if no error.
- */
-static I2CStatus I2C_get( unsigned int  eumbbar,
-						  unsigned char sender_addr, /* sender's address */
-					      unsigned char *buffer_ptr, /* pointer of receiving buffer */
-					  unsigned int  length,      /* length of the receiving buffer */
-					      unsigned int  stop_flag,   /* 1 - signal STOP when buffer is full
-									  * 0 - no STOP signal when buffer is full
-												      */
-						  unsigned int  is_cnt );    /* 1 - this is a restart, don't check MBB
-						      * 0 - this is a new start, check MBB
-													  */
-
-#if 0 /* the I2C_write and I2C_read functions are not active */
-/* Send a buffer of data to the requiring master.
- * If stop_flag is set, after the whole buffer is sent,
- * generate a STOP signal provided that the requiring
- * receiver doesn't signal the STOP in the middle.
- * I2C is the slave performing transmitting.
- *
- * return I2CSUCCESS if no error.
- *
- * Note: due to the Kahlua design, slave transmitter
- *       shall not signal STOP since there is no way
- *       for master to detect it, causing I2C bus hung.
- *
- *       For the above reason, the stop_flag is always
- *       set, i.e., 1.
- *
- *       programmer shall use the timer on Kahlua to
- *       control the interval of data byte at the
- *       master side.
- */
-static I2CStatus I2C_write( unsigned int eumbbar,
-						    unsigned char *buffer_ptr, /* pointer of data to be sent */
-						unsigned int  length,      /* number of byte of in the buffer */
-						unsigned int  stop_flag ); /* 1 - signal STOP when buffer is empty
-											* 0 - no STOP signal when buffer is empty
-												    */
-
- /* Receive a buffer of data from the sending master.
- * If stop_flag is set, when the buffer is full and the
- * sender does not signal STOP, generate a STOP signal.
- * I2C is the slave performing receiving.
- *
- * return I2CSUCCESS if no error.
- */
-static I2CStatus I2C_read(unsigned int  eumbbar,
-						  unsigned char *buffer_ptr, /* pointer of receiving buffer */
-					      unsigned int  length,      /* length of the receiving buffer */
-					  unsigned int  stop_flag ); /* 1 - signal STOP when buffer is full
-									  * 0 - no STOP signal when buffer is full
-												      */
-#endif /* of if0 for turning off I2C_read & I2C_write */
-
-/* if interrupt is not used, this is the timer event handler.
- * After each fixed time interval, this function can be called
- * to check the I2C status and call appropriate function to
- * handle the status event.
- */
-static I2CStatus I2C_Timer_Event( unsigned int eumbbar, I2CStatus (*handler)( unsigned int ) );
-
-/********************* Kernel API ************************
- * Kernel APIs are functions I2C driver provides to the
- * O.S.
- *********************************************************/
-
-/******************* device I/O function ***************/
-
-/*  Generate a START signal in the desired mode.
- *  I2C is the master.
- *
- * return I2CSUCCESS if no error.
- *        I2CERROR   if i2c unit is not enabled.
- *        I2CBUSBUSY if bus cannot be granted
- */
-static I2CStatus I2C_Start( unsigned int  eumbbar,
-						    unsigned char slave_addr, /* address of the receiver */
-				I2C_MODE     mode,       /* XMIT(1) - put (write)
-										  * RCV(0)  - get (read)
-													  */
-						    unsigned int is_cnt ); /* 1 - this is a restart, don't check MBB
-													* 0 - this is a new start, check MBB
-						    */
-
-/* Generate a STOP signal to terminate the transaction. */
-static I2CStatus I2C_Stop( unsigned int eumbbar );
-
-/*  Do a one-byte master transmit.
- *
- *  return I2CBUFFEMPTY if this is the last byte.
- *  Otherwise return I2CSUCCESS
- */
-static I2CStatus I2C_Master_Xmit( unsigned int eumbbar );
-
-/*  Do a one-byte master receive.
- *
- *  return I2CBUFFFULL if this is the last byte.
- *  Otherwise return I2CSUCCESS
- */
-static I2CStatus I2C_Master_Rcv( unsigned int eumbbar );
-
-/*  Do a one-byte slave transmit.
- *
- *  return I2CBUFFEMPTY if this is the last byte.
- *  Otherwise return I2CSUCCESS
- *
- */
-static I2CStatus I2C_Slave_Xmit( unsigned int eumbbar );
-
-/* Do a one-byte slave receive.
- *
- *  return I2CBUFFFULL if this is the last byte.
- *  Otherwise return I2CSUCCESS
- */
-static I2CStatus I2C_Slave_Rcv( unsigned int eumbbar  );
-
-/* Process slave address phase.
- *
- * return I2CADDRESS if this is slave receiver's address phase
- * Otherwise return the result of slave xmit one byte.
- */
-static I2CStatus I2C_Slave_Addr( unsigned int eumbbar );
-
-/******************* Device Control Fucntion ****************/
-/*  Initialize I2C unit with desired frequency divider,
- *  driver's slave address w/o interrupt enabled.
- *
- *  This function must be called before I2C unit can
- *  be used.
- */
-static I2CStatus I2C_Init( unsigned int  eumbbar,
-						   unsigned char fdr,       /* frequency divider */
-			       unsigned char addr,      /* driver's address used for receiving */
-					   unsigned int en_int);    /* 1 - enable I2C interrupt
-									 * 0 - disable I2C interrup
-												 */
-
-/* I2C interrupt service routine.
- *
- * return I2CADDRESS if it is receiver's (either master or slave) address phase.
- * return the result of xmit or receive one byte
- */
-static I2CStatus I2C_ISR(unsigned int eumbbar  );
-
-/* Set I2C Status, i.e., write to I2CSR */
-static void I2C_Set_Stat( unsigned int eumbbar, I2C_STAT stat );
-
-/* Query I2C Status, i.e., read I2CSR */
-static I2C_STAT I2C_Get_Stat( unsigned int eumbbar );
-
-/* Change I2C Control bits, i.e., write to I2CCR */
-static void I2C_Set_Ctrl( unsigned int eumbbar, I2C_CTRL ); /* new control value */
-
-/* Query I2C Control bits, i.e., read I2CCR */
-static I2C_CTRL I2C_Get_Ctrl( unsigned int eumbbar );
-
-/* This function performs the work for I2C_do_transaction.  The work is
- * split into this function to enable I2C_do_transaction to first transmit
- * the data address to the I2C slave device without putting the data address
- * into the first byte of the buffer.
- *
- * en_int controls interrupt/polling mode
- * act is the type of transaction
- * i2c_addr is the I2C address of the slave device
- * len is the length of data to send or receive
- * buffer is the address of the data buffer
- * stop = I2C_NO_STOP, don't signal STOP at end of transaction
- *        I2C_STOP, signal STOP at end of transaction
- * retry is the timeout retry value, currently ignored
- * rsta = I2C_NO_RESTART, this is not continuation of existing transaction
- *        I2C_RESTART, this is a continuation of existing transaction
- */
-static I2C_Status I2C_do_buffer( I2C_INTERRUPT_MODE en_int,
-				 I2C_TRANSACTION_MODE act,
-				 unsigned char i2c_addr,
-				 int len,
-				 unsigned char *buffer,
-				 I2C_STOP_MODE stop,
-				 int retry,
-				 I2C_RESTART_MODE rsta);
-#endif

cpu/mpc824x/drivers/i2c/i2c2.S

@@ -1,52 +0,0 @@
-/**************************************
- *
- * copyright @ Motorola, 1999
- *
- **************************************/
-
-#include <config.h>
-#ifdef CONFIG_HARD_I2C
-#include <ppc_asm.tmpl>
-#include <asm/mmu.h>
-/**********************************************************
- * function: load_runtime_reg
- *
- * input:  r3 - value of eumbbar
- *         r4 - register offset in embedded utility space
- *
- * output: r3 - register content
- **********************************************************/
-	.text
-	.align 2
-	.global load_runtime_reg
-load_runtime_reg:
-
-/*	xor r5,r5,r5
- *	or  r5,r5,r3
- *
- *	lwbrx	r3,r4,r5
- */
-	lwbrx r3,r4,r3
-	sync
-
-	bclr 20, 0
-
-/****************************************************************
- * function: store_runtime_reg
- *
- * input: r3 - value of eumbbar
- *        r4 - register offset in embedded utility space
- *        r5 - new value to be stored
- *
- ****************************************************************/
-	.text
-	.align 2
-	.global store_runtime_reg
-store_runtime_reg:
-
-	stwbrx r5,  r4, r3
-	sync
-
-	bclr   20,0
-
-#endif /* CONFIG_HARD_I2C */

cpu/mpc824x/drivers/i2c/i2c_export.h

@@ -1,103 +0,0 @@
-#ifndef I2C_EXPORT_H
-#define I2C_EXPORT_H
-
-/****************************************************
- *
- * Copyright Motrola 1999
- *
- ****************************************************/
-
-/* These are the defined return values for the I2C_do_transaction function.
- * Any non-zero value indicates failure.  Failure modes can be added for
- * more detailed error reporting.
- */
-typedef enum _i2c_status
-{
- I2C_SUCCESS     = 0,
- I2C_ERROR,
-} I2C_Status;
-
-/* These are the defined tasks for I2C_do_transaction.
- * Modes for SLAVE_RCV and SLAVE_XMIT will be added.
- */
-typedef enum _i2c_transaction_mode
-{
-	I2C_MASTER_RCV =  0,
-	I2C_MASTER_XMIT = 1,
-} I2C_TRANSACTION_MODE;
-
-typedef enum _i2c_interrupt_mode
-{
-	I2C_INT_DISABLE =  0,
-	I2C_INT_ENABLE = 1,
-} I2C_INTERRUPT_MODE;
-
-typedef enum _i2c_stop
-{
-	I2C_NO_STOP =  0,
-	I2C_STOP = 1,
-} I2C_STOP_MODE;
-
-typedef enum _i2c_restart
-{
-	I2C_NO_RESTART =  0,
-	I2C_RESTART = 1,
-} I2C_RESTART_MODE;
-
-/******************** App. API ********************
- * The application API is for user level application
- * to use the functionality provided by I2C driver.
- * This is a "generic" I2C interface, it should contain
- * nothing specific to the Kahlua implementation.
- * Only the generic functions are exported by the library.
- *
- * Note: Its App.s responsibility to swap the data
- *       byte. In our API, we just transfer whatever
- *       we are given
- **************************************************/
-
-
-/*  Initialize I2C unit with the following:
- *  driver's slave address
- *  interrupt enabled
- *  optional pointer to application layer print function
- *
- *  These parameters may be added:
- *  desired clock rate
- *  digital filter frequency sampling rate
- *
- *  This function must be called before I2C unit can be used.
- */
-extern I2C_Status I2C_Initialize(
-	unsigned char addr,            /* driver's I2C slave address */
-	I2C_INTERRUPT_MODE en_int,     /* 1 - enable I2C interrupt
-					* 0 - disable I2C interrupt
-					*/
-	int (*app_print_function)(char *,...)); /* pointer to optional "printf"
-						 * provided by application
-						 */
-
-/* Perform the given I2C transaction, only MASTER_XMIT and MASTER_RCV
- * are implemented.  Both are only in polling mode.
- *
- * en_int controls interrupt/polling mode
- * act is the type of transaction
- * addr is the I2C address of the slave device
- * len is the length of data to send or receive
- * buffer is the address of the data buffer
- * stop = I2C_NO_STOP, don't signal STOP at end of transaction
- *        I2C_STOP, signal STOP at end of transaction
- * retry is the timeout retry value, currently ignored
- * rsta = I2C_NO_RESTART, this is not continuation of existing transaction
- *        I2C_RESTART, this is a continuation of existing transaction
- */
-extern I2C_Status I2C_do_transaction( I2C_INTERRUPT_MODE en_int,
-				      I2C_TRANSACTION_MODE act,
-				      unsigned char i2c_addr,
-				      unsigned char data_addr,
-				      int len,
-				      char *buffer,
-				      I2C_STOP_MODE stop,
-				      int retry,
-				      I2C_RESTART_MODE rsta);
-#endif

cpu/mpc824x/start.S

@@ -526,11 +526,26 @@ relocate_code:
 	stwu	r0,-4(r7)
 	bdnz	3b
 
+4:
+#if !defined(CONFIG_BMW)
+/* Unlock the data cache and invalidate locked area */
+	xor	r0, r0, r0
+	mtspr	1011, r0
+	lis	r4, CFG_INIT_RAM_ADDR@h
+	ori	r4, r4, CFG_INIT_RAM_ADDR@l
+	li	r0, 128
+	mtctr	r0
+41:
+	dcbi	r0, r4
+	addi	r4, r4, 32
+	bdnz	41b
+#endif
+
 /*
  * Now flush the cache: note that we must start from a cache aligned
  * address. Otherwise we might miss one cache line.
  */
-4:	cmpwi	r6,0
+	cmpwi	r6,0
 	add	r5,r3,r5
 	beq	7f		/* Always flush prefetch queue in any case */
 	subi	r0,r6,1

cpu/ppc4xx/405gp_enet.c

@@ -83,7 +83,7 @@
 #if defined(CONFIG_405GP) || defined(CONFIG_440) || defined(CONFIG_405EP)
 
 #define EMAC_RESET_TIMEOUT 1000	/* 1000 ms reset timeout */
-#define PHY_AUTONEGOTIATE_TIMEOUT 2000	/* 2000 ms autonegotiate timeout */
+#define PHY_AUTONEGOTIATE_TIMEOUT 4000	/* 4000 ms autonegotiate timeout */
 
 #define NUM_TX_BUFF 1
 /* AS.HARNOIS
@@ -271,18 +271,18 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 		puts ("Waiting for PHY auto negotiation to complete");
 		i = 0;
 		while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
-			if ((i++ % 100) == 0)
-				putc ('.');
-			udelay (10000);		/* 10 ms */
-			miiphy_read (CONFIG_PHY_ADDR, PHY_BMSR, &reg_short);
-
 			/*
 			 * Timeout reached ?
 			 */
-			if (i * 10 > PHY_AUTONEGOTIATE_TIMEOUT) {
+			if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
 				puts (" TIMEOUT !\n");
 				break;
 			}
+
+			if ((i++ % 1000) == 0)
+				putc ('.');
+			udelay (1000);	/* 1 ms */
+			miiphy_read (CONFIG_PHY_ADDR, PHY_BMSR, &reg_short);
 		}
 		puts (" done\n");
 		udelay (500000);	/* another 500 ms (results in faster booting) */

cpu/pxa/mmc.c

@@ -26,11 +26,19 @@
 #include <mmc.h>
 #include <asm/errno.h>
 #include <asm/arch/hardware.h>
+#include <part.h>
 
 #ifdef CONFIG_MMC
 
 extern int
-fat_register_read(int(*block_read)(int device, ulong blknr, ulong blkcnt, uchar *buffer));
+fat_register_device(block_dev_desc_t *dev_desc, int part_no);
+
+static block_dev_desc_t mmc_dev;
+
+block_dev_desc_t * mmc_get_dev(int dev)
+{
+	return ((block_dev_desc_t *)&mmc_dev);
+}
 
 /*
  * FIXME needs to read cid and csd info to determine block size
@@ -379,9 +387,9 @@ mmc_write(uchar *src, ulong dst, int size)
 	return 0;
 }
 
-int
+ulong
 /****************************************************/
-mmc_bread(int dev_num, ulong blknr, ulong blkcnt, uchar *dst)
+mmc_bread(int dev_num, ulong blknr, ulong blkcnt, ulong *dst)
 /****************************************************/
 {
 	int mmc_block_size = MMC_BLOCK_SIZE;
@@ -441,6 +449,21 @@ mmc_init(int verbose)
 			printf("Month = %d\n",cid->month);
 			printf("Year = %d\n",1997 + cid->year);
 		}
+		/* fill in device description */
+		mmc_dev.if_type = IF_TYPE_MMC;
+		mmc_dev.dev = 0;
+		mmc_dev.lun = 0;
+		mmc_dev.type = 0;
+		/* FIXME fill in the correct size (is set to 32MByte) */
+		mmc_dev.blksz = 512;
+		mmc_dev.lba = 0x10000;
+		sprintf(mmc_dev.vendor,"Man %02x%02x%02x Snr %02x%02x%02x",
+				cid->id[0], cid->id[1], cid->id[2],
+				cid->sn[0], cid->sn[1], cid->sn[2]);
+		sprintf(mmc_dev.product,"%s",cid->name);
+		sprintf(mmc_dev.revision,"%x %x",cid->hwrev, cid->fwrev);
+		mmc_dev.removable = 0;
+		mmc_dev.block_read = mmc_bread;
 
 		/* MMC exists, get CSD too */
 		resp = mmc_cmd(MMC_CMD_SET_RCA, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R1);
@@ -458,7 +481,7 @@ mmc_init(int verbose)
 	MMC_CLKRT = 0;	/* 20 MHz */
 	resp = mmc_cmd(7, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R1);
 
-	fat_register_read(mmc_bread);
+	fat_register_device(&mmc_dev,1); /* partitions start counting with 1 */ 
 
 	return rc;
 }

disk/part.c

@@ -33,7 +33,9 @@
 #define PRINTF(fmt,args...)
 #endif
 
-#if (CONFIG_COMMANDS & CFG_CMD_IDE) || (CONFIG_COMMANDS & CFG_CMD_SCSI)
+#if ((CONFIG_COMMANDS & CFG_CMD_IDE)	|| \
+     (CONFIG_COMMANDS & CFG_CMD_SCSI)	|| \
+     (CONFIG_COMMANDS & CFG_CMD_USB)	)
 
 /* ------------------------------------------------------------------------- */
 /*

disk/part_dos.c

@@ -35,7 +35,9 @@
 #include <ide.h>
 #include "part_dos.h"
 
-#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || (CONFIG_COMMANDS & CFG_CMD_SCSI)) && defined(CONFIG_DOS_PARTITION)
+#if ((CONFIG_COMMANDS & CFG_CMD_IDE)	|| \
+     (CONFIG_COMMANDS & CFG_CMD_SCSI)	|| \
+     (CONFIG_COMMANDS & CFG_CMD_USB)	) && defined(CONFIG_DOS_PARTITION)
 
 /* Convert char[4] in little endian format to the host format integer
  */
@@ -65,6 +67,17 @@ static void print_one_part (dos_partition_t *p, int ext_part_sector, int part_nu
 		(is_extended (p->sys_ind) ? " Extd" : ""));
 }
 
+static int test_block_type(unsigned char *buffer)
+{
+	if((buffer[DOS_PART_MAGIC_OFFSET + 0] != 0x55) ||
+	    (buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) ) {
+		return (-1);
+	} /* no DOS Signature at all */
+	if(strncmp(&buffer[DOS_PBR_FSTYPE_OFFSET],"FAT",3)==0)
+		return DOS_PBR; /* is PBR */
+	return DOS_MBR;	    /* Is MBR */
+}
+
 
 int test_part_dos (block_dev_desc_t *dev_desc)
 {
@@ -92,14 +105,18 @@ static void print_partition_extended (block_dev_desc_t *dev_desc, int ext_part_s
 			dev_desc->dev, ext_part_sector);
 		return;
 	}
-	if (buffer[DOS_PART_MAGIC_OFFSET] != 0x55 ||
-		buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) {
+	i=test_block_type(buffer);
+	if(i==-1) {
 		printf ("bad MBR sector signature 0x%02x%02x\n",
 			buffer[DOS_PART_MAGIC_OFFSET],
 			buffer[DOS_PART_MAGIC_OFFSET + 1]);
 		return;
 	}
-
+	if(i==DOS_PBR) {
+		printf ("    1\t\t         0\t%10ld\t%2x\n",
+			dev_desc->lba, buffer[DOS_PBR_MEDIA_TYPE_OFFSET]);
+		return;
+	}
 	/* Print all primary/logical partitions */
 	pt = (dos_partition_t *) (buffer + DOS_PART_TBL_OFFSET);
 	for (i = 0; i < 4; i++, pt++) {

disk/part_dos.h

@@ -34,6 +34,10 @@
 #endif
 #define DOS_PART_TBL_OFFSET	0x1be
 #define DOS_PART_MAGIC_OFFSET	0x1fe
+#define DOS_PBR_FSTYPE_OFFSET	0x36
+#define DOS_PBR_MEDIA_TYPE_OFFSET	0x15
+#define DOS_MBR	0
+#define DOS_PBR	1
 
 typedef struct dos_partition {
 	unsigned char boot_ind;		/* 0x80 - active			*/

drivers/sk98lin/h/ski2c.h

@@ -161,6 +161,8 @@ typedef struct  s_Sensor SK_SENSOR;
 /*
  * Define READ and WRITE Constants.
  */
+#undef	I2C_READ		/* just in case */
+#undef	I2C_WRITE		/* just in case */
 #define I2C_READ	0
 #define I2C_WRITE	1
 #define I2C_BURST	1

drivers/sk98lin/skaddr.c

@@ -218,6 +218,10 @@
  *
  ******************************************************************************/
 
+#include <config.h>
+
+#ifdef CONFIG_SK98
+
 #ifndef	lint
 static const char SysKonnectFileId[] =
 	"@(#) $Id: skaddr.c,v 1.48 2003/02/12 17:09:37 tschilli Exp $ (C) SysKonnect.";
@@ -1872,3 +1876,4 @@ SK_U32	ToPortNumber)		/* Port2 Index */
 }
 #endif	/* __cplusplus */
 
+#endif /* CONFIG_SK98 */

drivers/sk98lin/skcsum.c

@@ -70,6 +70,10 @@
  *
  ******************************************************************************/
 
+#include <config.h>
+
+#ifdef CONFIG_SK98
+
 #ifdef SK_USE_CSUM	/* Check if CSUM is to be used. */
 
 #ifndef lint
@@ -921,3 +925,5 @@ SK_EVPARA	Param)	/* Event dependent parameter. */
 }	/* SkCsEvent */
 
 #endif	/* SK_USE_CSUM */
+
+#endif /* CONFIG_SK98 */

drivers/sk98lin/skge.c

@@ -340,6 +340,10 @@
  *
  ******************************************************************************/
 
+#include <config.h>
+
+#ifdef CONFIG_SK98
+
 #include	"h/skversion.h"
 #if 0
 #include	<linux/module.h>
@@ -4862,6 +4866,8 @@ int	l;
 
 #endif
 
+#endif /* CONFIG_SK98 */
+
 /*
  * Local variables:
  * compile-command: "make"

drivers/sk98lin/skgehwt.c

@@ -73,6 +73,10 @@
  ******************************************************************************/
 
 
+#include <config.h>
+
+#ifdef CONFIG_SK98
+
 /*
 	Event queue and dispatcher
 */
@@ -211,4 +215,6 @@ SK_IOC	Ioc)	/* IoContext */
 	SkTimerDone(pAC,Ioc) ;
 }
 
+#endif /* CONFIG_SK98 */
+
 /* End of file */

drivers/sk98lin/skgeinit.c

@@ -393,6 +393,10 @@
  *
  ******************************************************************************/
 
+#include <config.h>
+
+#ifdef CONFIG_SK98
+
 #include "h/skdrv1st.h"
 #include "h/skdrv2nd.h"
 
@@ -2364,3 +2368,5 @@ int		Port)		/* Port to configure */
 
 	return(0);
 }	/* SkGeInitPort */
+
+#endif /* CONFIG_SK98 */

drivers/sk98lin/skgemib.c

@@ -50,6 +50,10 @@
  *	
  ****************************************************************************/
 
+#include <config.h>
+
+#ifdef CONFIG_SK98
+
 /*
  * PRIVATE OID handler function prototypes
  */
@@ -1054,3 +1058,4 @@ PNMI_STATIC const SK_PNMI_TAB_ENTRY IdTable[] = {
 		SK_PNMI_RO, Vct, 0},
 };
 
+#endif /* CONFIG_SK98 */

drivers/sk98lin/skgepnmi.c

@@ -432,6 +432,10 @@
  ****************************************************************************/
 
 
+#include <config.h>
+
+#ifdef CONFIG_SK98
+
 static const char SysKonnectFileId[] =
 	"@(#) $Id: skgepnmi.c,v 1.102 2002/12/16 14:03:24 tschilli Exp $"
 	" (C) SysKonnect.";
@@ -8303,3 +8307,5 @@ SK_U32		PhysPortIndex)
 	}
 
 } /* CheckVctStatus */
+
+#endif /* CONFIG_SK98 */

drivers/sk98lin/skgesirq.c

@@ -337,6 +337,10 @@
  *
  ******************************************************************************/
 
+#include <config.h>
+
+#ifdef CONFIG_SK98
+
 /*
  *	Special Interrupt handler
  *
@@ -2408,4 +2412,6 @@ SK_U16	IStatus)	/* Interrupt Status */
 }	/* SkPhyIsrLone */
 #endif /* OTHER_PHY */
 
+#endif /* CONFIG_SK98 */
+
 /* End of File */

drivers/sk98lin/ski2c.c

@@ -228,6 +228,10 @@
  ******************************************************************************/
 
 
+#include <config.h>
+
+#ifdef CONFIG_SK98
+
 /*
  *	I2C Protocol
  */
@@ -1497,3 +1501,5 @@ SK_EVPARA	Para)	/* Event specific Parameter */
 }	/* SkI2cEvent*/
 
 #endif	/* !SK_DIAG */
+
+#endif /* CONFIG_SK98 */

drivers/sk98lin/sklm80.c

@@ -98,6 +98,10 @@
  ******************************************************************************/
 
 
+#include <config.h>
+
+#ifdef CONFIG_SK98
+
 /*
 	LM80 functions
 */
@@ -284,3 +288,5 @@ SK_SENSOR	*pSen)	/* Sensor to be read */
 	/* Not completed */
 	return(0);
 }
+
+#endif /* CONFIG_SK98 */

drivers/sk98lin/skproc.c

@@ -70,6 +70,10 @@
  *
  ******************************************************************************/
 
+#include <config.h>
+
+#ifdef CONFIG_SK98
+
 #include <linux/proc_fs.h>
 
 #include "h/skdrv1st.h"
@@ -511,5 +515,4 @@ char * SkNumber(char * str, long long num, int base, int size, int precision
 	return strorg;
 }
 
-
-
+#endif /* CONFIG_SK98 */

drivers/sk98lin/skqueue.c

@@ -87,6 +87,10 @@
  ******************************************************************************/
 
 
+#include <config.h>
+
+#ifdef CONFIG_SK98
+
 /*
 	Event queue and dispatcher
 */
@@ -233,4 +237,6 @@ SK_IOC	Ioc)	/* Io context */
 	return(0) ;
 }
 
+#endif /* CONFIG_SK98 */
+
 /* End of file */

drivers/sk98lin/skrlmt.c

@@ -280,6 +280,10 @@
  *
  ******************************************************************************/
 
+#include <config.h>
+
+#ifdef CONFIG_SK98
+
 #ifndef	lint
 static const char SysKonnectFileId[] =
 	"@(#) $Id: skrlmt.c,v 1.68 2003/01/31 15:26:56 rschmidt Exp $ (C) SysKonnect.";
@@ -3500,3 +3504,5 @@ SK_EVPARA	Para)	/* Event-specific parameter */
 #ifdef __cplusplus
 }
 #endif	/* __cplusplus */
+
+#endif /* CONFIG_SK98 */

drivers/sk98lin/sktimer.c

@@ -72,6 +72,10 @@
  ******************************************************************************/
 
 
+#include <config.h>
+
+#ifdef CONFIG_SK98
+
 /*
 	Event queue and dispatcher
 */
@@ -288,4 +292,6 @@ int	Restart)	/* Do we need to restart the Hardware timer ? */
 	}
 }
 
+#endif /* CONFIG_SK98 */
+
 /* End of file */

drivers/sk98lin/skvpd.c

@@ -160,6 +160,10 @@
  *
  ******************************************************************************/
 
+#include <config.h>
+
+#ifdef CONFIG_SK98
+
 /*
 	Please refer skvpd.txt for infomation how to include this module
  */
@@ -1323,3 +1327,4 @@ char	*msg)	/* error log message */
 	(void)VpdUpdate(pAC, IoC);
 }
 
+#endif /* CONFIG_SK98 */

drivers/sk98lin/skxmac2.c

@@ -410,6 +410,10 @@
  *
  ******************************************************************************/
 
+#include <config.h>
+
+#ifdef CONFIG_SK98
+
 #include "h/skdrv1st.h"
 #include "h/skdrv2nd.h"
 
@@ -4389,4 +4393,6 @@ SK_BOOL	StartTest)	/* flag for start / get result */
 	return(0);
 }	/* SkGmCableDiagStatus */
 
+#endif /* CONFIG_SK98 */
+
 /* End of file */

drivers/sk98lin/uboot_skb.c

@@ -23,6 +23,10 @@
  * MA 02111-1307 USA
  */
 
+#include <config.h>
+
+#ifdef CONFIG_SK98
+
 #include <common.h>
 #include "u-boot_compat.h"
 
@@ -114,3 +118,5 @@ void skb_put(struct sk_buff *skb, unsigned int len)
 {
 	skb->len+=len;
 }
+
+#endif /* CONFIG_SK98 */

examples/Makefile

@@ -69,6 +69,11 @@ ifeq ($(BOARD),oxc)
 SREC   += eepro100_eeprom.srec
 endif
 
+##ifeq ($(BOARD),trab)
+##SREC   += trab_fkt.srec
+##BIN    += trab_fkt.bin
+##endif
+
 OBJS	= $(SREC:.srec=.o)
 
 LIB	= libstubs.a

fs/fat/fat.c

@@ -29,6 +29,7 @@
 #include <config.h>
 #include <fat.h>
 #include <asm/byteorder.h>
+#include <part.h>
 
 #if (CONFIG_COMMANDS & CFG_CMD_FAT)
 
@@ -44,26 +45,70 @@ downcase(char *str)
 	}
 }
 
-int (*dev_block_read)(int device, __u32 blknr, __u32 blkcnt, __u8 *buffer) = 0;
+static  block_dev_desc_t *cur_dev = NULL;
+static unsigned long part_offset = 0;
+static int cur_part = 1;
+
+#define DOS_PART_TBL_OFFSET	0x1be
+#define DOS_PART_MAGIC_OFFSET	0x1fe
+#define DOS_FS_TYPE_OFFSET	0x36
 
 int disk_read (__u32 startblock, __u32 getsize, __u8 * bufptr)
 {
-	/* FIXME we need to determine the start block of the
-	 * partition where the DOS FS resides
-	 */
-	startblock += 32;
-
-	if (dev_block_read) {
-		return dev_block_read (0, startblock, getsize, bufptr);
+	startblock += part_offset;
+	if (cur_dev == NULL)
+		return -1;
+	if (cur_dev->block_read) {
+		return cur_dev->block_read (cur_dev->dev, startblock, getsize, (unsigned long *)bufptr);
 	}
 	return -1;
 }
 
 
 int
-fat_register_read (int (*block_read)(int, __u32, __u32, __u8 *))
+fat_register_device(block_dev_desc_t *dev_desc, int part_no)
 {
-	dev_block_read = block_read;
+	unsigned char buffer[SECTOR_SIZE];
+
+	if (!dev_desc->block_read)
+		return -1;
+	cur_dev=dev_desc;
+	/* check if we have a MBR (on floppies we have only a PBR) */
+	if (dev_desc->block_read (dev_desc->dev, 0, 1, (ulong *) buffer) != 1) {
+		printf ("** Can't read from device %d **\n", dev_desc->dev);
+		return -1;
+	}
+	if (buffer[DOS_PART_MAGIC_OFFSET] != 0x55 ||
+		buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) {
+		/* no signature found */
+		return -1;
+	}
+	if(!strncmp(&buffer[DOS_FS_TYPE_OFFSET],"FAT",3)) {
+		/* ok, we assume we are on a PBR only */
+		cur_part = 1;
+		part_offset=0;
+	}
+	else {
+#if (CONFIG_COMMANDS & CFG_CMD_IDE) || (CONFIG_COMMANDS & CFG_CMD_SCSI)
+		disk_partition_t info;
+		if(!get_partition_info(dev_desc, part_no, &info)) {
+			part_offset = info.start;
+			cur_part = part_no;
+		}
+		else {
+			printf ("** Partition %d not valid on device %d **\n",part_no,dev_desc->dev);
+			return -1;
+		}
+#else
+		/* FIXME we need to determine the start block of the
+		 * partition where the DOS FS resides. This can be done
+		 * by using the get_partition_info routine. For this
+		 * purpose the libpart must be included.
+		 */
+		part_offset=32;
+		cur_part = 1;
+#endif
+	}
 	return 0;
 }
 
@@ -246,25 +291,21 @@ get_cluster(fsdata *mydata, __u32 clustnum, __u8 *buffer, unsigned long size)
 	}
 
 	FAT_DPRINT("gc - clustnum: %d, startsect: %d\n", clustnum, startsect);
-	while (size > 0) {
-		if (size >= FS_BLOCK_SIZE) {
-			if (disk_read(startsect + idx, 1, buffer) < 0) {
-				FAT_DPRINT("Error reading data\n");
-				return -1;
-			}
-		} else {
-			__u8 tmpbuf[FS_BLOCK_SIZE];
-			if (disk_read(startsect + idx, 1, tmpbuf) < 0) {
-				FAT_DPRINT("Error reading data\n");
-				return -1;
-			}
-			memcpy(buffer, tmpbuf, size);
-
-			return 0;
+	if (disk_read(startsect, size/FS_BLOCK_SIZE , buffer) < 0) {
+		FAT_DPRINT("Error reading data\n");
+		return -1;
+	}
+	if(size % FS_BLOCK_SIZE) {
+		__u8 tmpbuf[FS_BLOCK_SIZE];
+		idx= size/FS_BLOCK_SIZE;
+		if (disk_read(startsect + idx, 1, tmpbuf) < 0) {
+			FAT_DPRINT("Error reading data\n");
+			return -1;
 		}
-		buffer += FS_BLOCK_SIZE;
-		size -= FS_BLOCK_SIZE;
-		idx++;
+		buffer += idx*FS_BLOCK_SIZE;
+
+		memcpy(buffer, tmpbuf, size % FS_BLOCK_SIZE);
+		return 0;
 	}
 
 	return 0;
@@ -283,6 +324,8 @@ get_contents(fsdata *mydata, dir_entry *dentptr, __u8 *buffer,
 	unsigned long filesize = FAT2CPU32(dentptr->size), gotsize = 0;
 	unsigned int bytesperclust = mydata->clust_size * SECTOR_SIZE;
 	__u32 curclust = START(dentptr);
+	__u32 endclust, newclust;
+	unsigned long actsize;
 
 	FAT_DPRINT("Filesize: %ld bytes\n", filesize);
 
@@ -290,25 +333,56 @@ get_contents(fsdata *mydata, dir_entry *dentptr, __u8 *buffer,
 
 	FAT_DPRINT("Reading: %ld bytes\n", filesize);
 
+	actsize=bytesperclust;
+	endclust=curclust;
 	do {
-		int getsize = (filesize > bytesperclust) ? bytesperclust :
-			filesize;
-
-		if (get_cluster(mydata, curclust, buffer, getsize) != 0) {
+		/* search for consecutive clusters */
+		while(actsize < filesize) {
+			newclust = get_fatent(mydata, endclust);
+			if((newclust -1)!=endclust)
+				goto getit;
+			if (newclust <= 0x0001 || newclust >= 0xfff0) {
+				FAT_DPRINT("curclust: 0x%x\n", newclust);
+				FAT_DPRINT("Invalid FAT entry\n");
+				return gotsize;
+			}
+			endclust=newclust;
+			actsize+= bytesperclust;
+		}
+		/* actsize >= file size */
+		actsize -= bytesperclust;
+		/* get remaining clusters */
+		if (get_cluster(mydata, curclust, buffer, (int)actsize) != 0) {
 			FAT_ERROR("Error reading cluster\n");
 			return -1;
 		}
-		gotsize += getsize;
-		filesize -= getsize;
-		if (filesize <= 0) return gotsize;
-		buffer += getsize;
-
-		curclust = get_fatent(mydata, curclust);
+		/* get remaining bytes */
+		gotsize += (int)actsize;
+		filesize -= actsize;
+		buffer += actsize;
+		actsize= filesize;
+		if (get_cluster(mydata, endclust, buffer, (int)actsize) != 0) {
+			FAT_ERROR("Error reading cluster\n");
+			return -1;
+		}
+		gotsize+=actsize;
+		return gotsize;
+getit:
+		if (get_cluster(mydata, curclust, buffer, (int)actsize) != 0) {
+			FAT_ERROR("Error reading cluster\n");
+			return -1;
+		}
+		gotsize += (int)actsize;
+		filesize -= actsize;
+		buffer += actsize;
+		curclust = get_fatent(mydata, endclust);
 		if (curclust <= 0x0001 || curclust >= 0xfff0) {
 			FAT_DPRINT("curclust: 0x%x\n", curclust);
 			FAT_ERROR("Invalid FAT entry\n");
 			return gotsize;
 		}
+		actsize=bytesperclust;
+		endclust=curclust;
 	} while (1);
 }
 
@@ -641,7 +715,7 @@ static long
 do_fat_read (const char *filename, void *buffer, unsigned long maxsize,
 	     int dols)
 {
-    __u8 block[FS_BLOCK_SIZE];  /* Block buffer */
+    __u8 block[MAX_CLUSTSIZE];  /* Block buffer */
     char fnamecopy[2048];
     boot_sector bs;
     volume_info volinfo;
@@ -713,7 +787,7 @@ do_fat_read (const char *filename, void *buffer, unsigned long maxsize,
     while (1) {
 	int i;
 
-	if (disk_read (cursect, 1, block) < 0) {
+	if (disk_read (cursect, mydata->clust_size, block) < 0) {
 	    FAT_DPRINT ("Error: reading rootdir block\n");
 	    return -1;
 	}
@@ -786,9 +860,11 @@ do_fat_read (const char *filename, void *buffer, unsigned long maxsize,
 		int doit = 0;
 
 		if (isdir) {
-		    dirs++;
 		    dirc = '/';
-		    doit = 1;
+		    if (s_name[0] != 0) {
+			dirs++;
+			doit = 1;
+		    }
 		} else {
 		    dirc = ' ';
 		    if (s_name[0] != 0) {
@@ -880,8 +956,35 @@ file_fat_detectfs(void)
 	boot_sector	bs;
 	volume_info	volinfo;
 	int		fatsize;
+	char	vol_label[12];
 
-	return read_bootsectandvi(&bs, &volinfo, &fatsize);
+	if(cur_dev==NULL) {
+		printf("No current device\n");
+		return 1;
+	}
+#if (CONFIG_COMMANDS & CFG_CMD_IDE) || (CONFIG_COMMANDS & CFG_CMD_SCSI)
+	printf("Interface:  ");
+	switch(cur_dev->if_type) {
+		case IF_TYPE_IDE :	printf("IDE"); break;
+		case IF_TYPE_SCSI :	printf("SCSI"); break;
+		case IF_TYPE_ATAPI :	printf("ATAPI"); break;
+		case IF_TYPE_USB :	printf("USB"); break;
+		case IF_TYPE_DOC :	printf("DOC"); break;
+		case IF_TYPE_MMC :	printf("MMC"); break;
+		default :		printf("Unknown");
+	}
+	printf("\n  Device %d: ",cur_dev->dev);
+	dev_print(cur_dev);
+#endif
+	if(read_bootsectandvi(&bs, &volinfo, &fatsize)) {
+		printf("\nNo valid FAT fs found\n");
+		return 1;
+	}
+	memcpy (vol_label, volinfo.volume_label, 11);
+	vol_label[11] = '\0';
+	volinfo.fs_type[5]='\0';
+	printf("Partition %d: Filesystem: %s \"%s\"\n",cur_part,volinfo.fs_type,vol_label);
+	return 0;
 }
 
 
@@ -895,6 +998,7 @@ file_fat_ls(const char *dir)
 long
 file_fat_read(const char *filename, void *buffer, unsigned long maxsize)
 {
+	printf("reading %s\n",filename);
 	return do_fat_read(filename, buffer, maxsize, LS_NO);
 }
 

fs/jffs2/jffs2_1pass.c

@@ -1,4 +1,3 @@
-/* vi: set sw=4 ts=4: */
 /*
 -------------------------------------------------------------------------
  * Filename:      jffs2.c
@@ -265,20 +264,56 @@ insert_node(struct b_list *list, u32 offset)
 }
 
 #ifdef CFG_JFFS2_SORT_FRAGMENTS
+/* Sort data entries with the latest version last, so that if there
+ * is overlapping data the latest version will be used.
+ */
 static int compare_inodes(struct b_node *new, struct b_node *old)
 {
 	struct jffs2_raw_inode *jNew = (struct jffs2_raw_inode *)new->offset;
 	struct jffs2_raw_inode *jOld = (struct jffs2_raw_inode *)old->offset;
 
-	return jNew->version < jOld->version;
+	return jNew->version > jOld->version;
 }
 
+/* Sort directory entries so all entries in the same directory
+ * with the same name are grouped together, with the latest version
+ * last. This makes it easy to eliminate all but the latest version
+ * by marking the previous version dead by setting the inode to 0.
+ */
 static int compare_dirents(struct b_node *new, struct b_node *old)
 {
 	struct jffs2_raw_dirent *jNew = (struct jffs2_raw_dirent *)new->offset;
 	struct jffs2_raw_dirent *jOld = (struct jffs2_raw_dirent *)old->offset;
+	int cmp;
 
-	return jNew->version > jOld->version;
+	/* ascending sort by pino */
+	if (jNew->pino != jOld->pino)
+		return jNew->pino > jOld->pino;
+
+	/* pino is the same, so use ascending sort by nsize, so
+	 * we don't do strncmp unless we really must.
+	 */
+	if (jNew->nsize != jOld->nsize)
+		return jNew->nsize > jOld->nsize;
+
+	/* length is also the same, so use ascending sort by name
+	 */
+	cmp = strncmp(jNew->name, jOld->name, jNew->nsize);
+	if (cmp != 0)
+		return cmp > 0;
+
+	/* we have duplicate names in this directory, so use ascending
+	 * sort by version
+	 */
+	if (jNew->version > jOld->version) {
+		/* since jNew is newer, we know jOld is not valid, so
+		 * mark it with inode 0 and it will not be used
+		 */
+		jOld->ino = 0;
+		return 1;
+	}
+	
+	return 0;
 }
 #endif
 
@@ -327,12 +362,31 @@ jffs2_1pass_read_inode(struct b_lists *pL, u32 inode, char *dest)
 	struct b_node *b;
 	struct jffs2_raw_inode *jNode;
 	u32 totalSize = 0;
-	u16 latestVersion = 0;
+	u32 latestVersion = 0;
 	char *lDest;
 	char *src;
 	long ret;
 	int i;
 	u32 counter = 0;
+#ifdef CFG_JFFS2_SORT_FRAGMENTS
+	/* Find file size before loading any data, so fragments that
+	 * start past the end of file can be ignored. A fragment
+	 * that is partially in the file is loaded, so extra data may
+	 * be loaded up to the next 4K boundary above the file size.
+	 * This shouldn't cause trouble when loading kernel images, so
+	 * we will live with it.
+	 */
+	for (b = pL->frag.listHead; b != NULL; b = b->next) {
+		jNode = (struct jffs2_raw_inode *) (b->offset);
+		if ((inode == jNode->ino)) {
+			/* get actual file length from the newest node */
+			if (jNode->version >= latestVersion) {
+				totalSize = jNode->isize;
+				latestVersion = jNode->version;
+			}
+		}
+	}
+#endif
 
 	for (b = pL->frag.listHead; b != NULL; b = b->next) {
 		jNode = (struct jffs2_raw_inode *) (b->offset);
@@ -349,11 +403,14 @@ jffs2_1pass_read_inode(struct b_lists *pL, u32 inode, char *dest)
 			putLabeledWord("read_inode: usercompr = ", jNode->usercompr);
 			putLabeledWord("read_inode: flags = ", jNode->flags);
 #endif
+
+#ifndef CFG_JFFS2_SORT_FRAGMENTS
 			/* get actual file length from the newest node */
 			if (jNode->version >= latestVersion) {
 				totalSize = jNode->isize;
 				latestVersion = jNode->version;
 			}
+#endif
 
 			if(dest) {
 				src = ((char *) jNode) + sizeof(struct jffs2_raw_inode);
@@ -430,15 +487,11 @@ jffs2_1pass_find_inode(struct b_lists * pL, const char *name, u32 pino)
 		if ((pino == jDir->pino) && (len == jDir->nsize) &&
 		    (jDir->ino) &&	/* 0 for unlink */
 		    (!strncmp(jDir->name, name, len))) {	/* a match */
-			if (jDir->version < version) continue;
+			if (jDir->version < version)
+				continue;
 
-		        if(jDir->version == 0) {
-			    	/* Is this legal? */
-				putstr(" ** WARNING ** ");
-				putnstr(jDir->name, jDir->nsize);
-				putstr(" is version 0 (in find, ignoring)\r\n");
-			} else if(jDir->version == version) {
-			    	/* Im pretty sure this isn't ... */
+			if (jDir->version == version && inode != 0) {
+			    	/* I'm pretty sure this isn't legal */
 				putstr(" ** ERROR ** ");
 				putnstr(jDir->name, jDir->nsize);
 				putLabeledWord(" has dup version =", version);
@@ -643,15 +696,11 @@ jffs2_1pass_resolve_inode(struct b_lists * pL, u32 ino)
 	for(b = pL->dir.listHead; b; b = b->next) {
 		jDir = (struct jffs2_raw_dirent *) (b->offset);
 		if (ino == jDir->ino) {
-		    	if(jDir->version < version) continue;
+		    	if (jDir->version < version)
+				continue;
 
-			if(jDir->version == 0) {
-			    	/* Is this legal? */
-				putstr(" ** WARNING ** ");
-				putnstr(jDir->name, jDir->nsize);
-				putstr(" is version 0 (in resolve, ignoring)\r\n");
-			} else if(jDir->version == version) {
-			    	/* Im pretty sure this isn't ... */
+			if (jDir->version == version && jDirFound) {
+			    	/* I'm pretty sure this isn't legal */
 				putstr(" ** ERROR ** ");
 				putnstr(jDir->name, jDir->nsize);
 				putLabeledWord(" has dup version (resolve) = ",
@@ -891,6 +940,11 @@ jffs2_1pass_build_lists(struct part_info * part)
 					printf("OOPS Cleanmarker has bad size "
 						"%d != %d\n", node->totlen,
 						sizeof(struct jffs2_unknown_node));
+			} else if (node->nodetype == JFFS2_NODETYPE_PADDING) {
+				if (node->totlen < sizeof(struct jffs2_unknown_node))
+					printf("OOPS Padding has bad size "
+						"%d < %d\n", node->totlen,
+						sizeof(struct jffs2_unknown_node));
 			} else {
 				printf("Unknown node type: %x len %d "
 					"offset 0x%x\n", node->nodetype,

include/_exports.h

@@ -10,3 +10,7 @@ EXPORT_FUNC(malloc)
 EXPORT_FUNC(free)
 EXPORT_FUNC(udelay)
 EXPORT_FUNC(get_timer)
+#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+EXPORT_FUNC(i2c_write)
+EXPORT_FUNC(i2c_read)
+#endif	/* CFG_CMD_I2C */

include/configs/AdderII.h

@@ -48,10 +48,10 @@
 #define CONFIG_CLOCKS_IN_MHZ	1
 
 /* Monitor Functions */
-#define CONFIG_COMMANDS		( CFG_CMD_FLASH | \
+#define CONFIG_COMMANDS		( CFG_CMD_ENV	| \
+				  CFG_CMD_FLASH | \
 				  CFG_CMD_MEMORY| \
 				  CFG_CMD_NET   | \
-				  CFG_CMD_ENV	| \
 				  CFG_CMD_PING  | \
 				  CFG_CMD_SDRAM )
 

include/configs/IceCube.h

@@ -191,8 +191,8 @@
 /*
  * Various low-level settings
  */
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		0
+#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL		HID0_ICE
 
 #define CFG_BOOTCS_START	CFG_FLASH_BASE
 #define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE

include/configs/MIP405.h

@@ -67,6 +67,7 @@
 			CFG_CMD_DATE	| \
 			CFG_CMD_ELF	| \
 			CFG_CMD_MII	| \
+			CFG_CMD_FAT | \
 			CFG_CMD_PING	| \
 			CFG_CMD_SAVES	| \
 			CFG_CMD_BSP	)
@@ -246,9 +247,10 @@
 /*
  * Init Memory Controller:
  */
-
-#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/
+#define FLASH_MAX_SIZE		0x00800000		/* 8MByte max */
+#define FLASH_BASE_PRELIM	0xFF800000  /* open the flash CS */
+/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
+#define FLASH_SIZE_PRELIM	 3  /* maximal flash FLASH size bank #0	*/
 
 #define CONFIG_BOARD_PRE_INIT
 
@@ -325,7 +327,7 @@
 #undef	CONFIG_IDE_LED	       /* no led for ide supported     */
 #define CONFIG_IDE_RESET       /* reset for ide supported...	*/
 #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
-
+#define CONFIG_SUPPORT_VFAT
 /************************************************************
  * ATAPI support (experimental)
  ************************************************************/

include/configs/P3G4.h

@@ -99,6 +99,7 @@
 #define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
 				 CONFIG_BOOTP_BOOTFILESIZE)
 
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
 
 #define CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_ASKENV)
 

include/configs/PIP405.h

@@ -50,11 +50,13 @@
 			CFG_CMD_PCI	| \
 			CFG_CMD_CACHE	| \
 			CFG_CMD_IRQ	| \
+			CFG_CMD_ECHO	| \
 			CFG_CMD_EEPROM	| \
 			CFG_CMD_I2C	| \
 			CFG_CMD_REGINFO | \
 			CFG_CMD_FDC	| \
 			CFG_CMD_SCSI	| \
+			CFG_CMD_FAT 	| \
 			CFG_CMD_DATE	| \
 			CFG_CMD_ELF	| \
 			CFG_CMD_USB	| \
@@ -141,7 +143,7 @@
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
-
+#define CONFIG_MISC_INIT_R
 /***********************************************************
  * Miscellaneous configurable options
  **********************************************************/
@@ -231,9 +233,12 @@
 /*
  * Init Memory Controller:
  */
+#define FLASH_MAX_SIZE		0x00800000		/* 8MByte max */
+#define FLASH_BASE_PRELIM	0xFF800000  /* open the flash CS */
+/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
+#define FLASH_SIZE_PRELIM	 3  /* maximal flash FLASH size bank #0	*/
 
-#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/
+#define CONFIG_BOARD_PRE_INIT
 
 /* Configuration Port location */
 #define CONFIG_PORT_ADDR	0xF4000000
@@ -299,6 +304,7 @@
 #undef	CONFIG_IDE_LED			/* no led for ide supported	*/
 #define CONFIG_IDE_RESET		/* reset for ide supported...	*/
 #define CONFIG_IDE_RESET_ROUTINE	/* with a special reset function */
+#define CONFIG_SUPPORT_VFAT
 
 /************************************************************
  * ATAPI support (experimental)

include/configs/SL8245.h

@@ -51,6 +51,8 @@
 
 #define CONFIG_BOOTDELAY	5
 
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
 #define CONFIG_COMMANDS		(CONFIG_CMD_DFL | CFG_CMD_PCI)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) 	*/
@@ -68,7 +70,7 @@
 /* Print Buffer Size
  */
 #define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_MAXARGS	8		/* Max number of command args	*/
+#define CFG_MAXARGS	32		/* Max number of command args	*/
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 #define CFG_LOAD_ADDR	0x00400000	/* Default load address		*/
 

include/configs/SXNI855T.h

@@ -145,12 +145,22 @@
 
 #define CONFIG_COMMANDS		(CONFIG_CMD_DFL		| \
 				 CFG_CMD_EEPROM		| \
+				 CFG_CMD_JFFS2		| \
 				 CFG_CMD_NAND		| \
 				 CFG_CMD_DATE)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
+#define CFG_JFFS_CUSTOM_PART
+#define CFG_JFFS2_SORT_FRAGMENTS
+/* JFFS2 location when using NOR flash */
+#define CFG_JFFS2_BASE	(CFG_FLASH_BASE + 0x80000)
+#define CFG_JFFS2_SIZE	(0x780000)
+/* JFFS2 location (in RAM) when using NAND flash */
+#define	CFG_JFFS2_RAMBASE 0x400000
+#define	CFG_JFFS2_RAMSIZE 0x200000	/* NAND boot partition is 2MiB	*/
+
 /* NAND flash support */
 #define CONFIG_MTD_NAND_ECC_JFFS2
 #define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices	*/
@@ -405,13 +415,18 @@
 
 #define CONFIG_RESET_ON_PANIC		/* reset if system panic() */
 
-/* to put environment in EEROM */
-#define	CFG_ENV_IS_IN_EEPROM	1
-#define CFG_ENV_OFFSET		0	/* Start right at beginning of NVRAM */
-#define CFG_ENV_SIZE		1024	/* Use only a part of it*/
-
-#if 1
-#define CONFIG_BOOT_RETRY_TIME	60	/* boot if no command in 60 seconds */
+#define CFG_ENV_IS_IN_FLASH
+#ifdef CFG_ENV_IS_IN_FLASH
+  /* environment is in FLASH */
+  #define CFG_ENV_ADDR		0xF8040000	/* AM29LV641 or AM29LV800BT */
+  #define CFG_ENV_ADDR_REDUND	0xF8050000	/* AM29LV641 or AM29LV800BT */
+  #define CFG_ENV_SECT_SIZE	0x00010000
+  #define CFG_ENV_SIZE		0x00002000
+#else
+  /* environment is in EEPROM */
+  #define CFG_ENV_IS_IN_EEPROM		1
+  #define CFG_ENV_OFFSET		0	/* at beginning of EEPROM */
+  #define CFG_ENV_SIZE		     1024	/* Use only a part of it*/
 #endif
 
 #if 1

include/configs/Sandpoint8240.h

@@ -46,8 +46,39 @@
 #endif
 
 #define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_DRAM_SPEED	100		/* MHz				*/
+#define CONFIG_BAUDRATE		9600
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run net_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$(serverip):$(rootpath)\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs $(bootargs) "				\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
+		":$(hostname):$(netdev):off panic=1\0"			\
+	"net_self=tftp $(kernel_addr) $(bootfile);"			\
+		"tftp $(ramdisk_addr) $(ramdisk);"			\
+		"run ramargs addip;"					\
+		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
+	"net_nfs=tftp $(kernel_addr) $(bootfile);"			\
+		"run nfsargs addip;bootm\0"				\
+	"rootpath=/opt/eldk/ppc_82xx\0"					\
+	"bootfile=/tftpboot/SP8240/uImage\0"				\
+	"ramdisk=/tftpboot/SP8240/uRamdisk\0"				\
+	"kernel_addr=200000\0"						\
+	"ramdisk_addr=400000\0"						\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
 
 #define CONFIG_COMMANDS		( (CONFIG_CMD_DFL & ~CFG_CMD_AUTOSCRIPT) | \
 				  CFG_CMD_ELF    | \
@@ -59,6 +90,7 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any)	*/
 #include <cmd_confdefs.h>
 
+#define CONFIG_DRAM_SPEED	100		/* MHz				*/
 
 /*
  * Miscellaneous configurable options

include/configs/trab.h

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2002
+ * (C) Copyright 2002-2003
  * Gary Jennejohn <gj@denx.de>
  *
  * Configuation settings for the TRAB board.
@@ -40,6 +40,7 @@
 #define CONFIG_S3C2400		1	/* in a SAMSUNG S3C2400 SoC	*/
 #define CONFIG_TRAB		1	/* on a TRAB Board		*/
 #undef CONFIG_TRAB_50MHZ		/* run the CPU at 50 MHz	*/
+#define LITTLEENDIAN		1	/* used by usb_ohci.c		*/
 
 /* input clock of PLL */
 #define CONFIG_SYS_CLK_FREQ	12000000 /* TRAB has 12 MHz input clock */
@@ -67,6 +68,11 @@
 #define CFG_EEPROM_PAGE_WRITE_BITS 3	/* 8 bytes page write mode on 24C04 */
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
 
+/* USB stuff */
+#define CONFIG_USB_OHCI		1
+#define CONFIG_USB_STORAGE	1
+#define CONFIG_DOS_PARTITION	1
+
 /*
  * Size of malloc() pool
  */
@@ -139,6 +145,8 @@
 				 CONFIG_COMMANDS_ADD_HWFLOW	| \
 				 CONFIG_COMMANDS_ADD_VFD	| \
 				 CONFIG_COMMANDS_ADD_EEPROM	| \
+				 CFG_CMD_USB			| \
+				 CFG_CMD_FAT			| \
 				 CONFIG_COMMANDS_I2C		)
 #else
 #define CONFIG_COMMANDS		(CONFIG_CMD_DFL			| \
@@ -147,9 +155,14 @@
 				 CONFIG_COMMANDS_ADD_HWFLOW	| \
 				 CONFIG_COMMANDS_ADD_VFD	| \
 				 CONFIG_COMMANDS_ADD_EEPROM	| \
+				 CFG_CMD_USB			| \
+				 CFG_CMD_FAT			| \
 				 CONFIG_COMMANDS_I2C		)
 #endif
 
+/* moved up */
+#define CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
@@ -164,6 +177,28 @@
 #define CONFIG_BOOTCOMMAND	"run flash_nfs"
 
 #ifndef CONFIG_BIG_FLASH
+#ifdef CFG_HUSH_PARSER
+#define	CONFIG_EXTRA_ENV_SETTINGS	\
+	"nfs_args=setenv bootargs root=/dev/nfs rw " \
+		"nfsroot=$serverip:$rootpath\0" \
+	"rootpath=/opt/eldk/arm_920TDI\0" \
+	"ram_args=setenv bootargs root=/dev/ram rw\0" \
+	"add_net=setenv bootargs $bootargs ethaddr=$ethaddr " \
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
+	"add_misc=setenv bootargs $bootargs console=ttyS0 panic=1\0" \
+	"load=tftp 0xC100000 /tftpboot/TRAB/u-boot.bin\0" \
+	"update=protect off 1:0-8;era 1:0-8;cp.b 0xc100000 0 $filesize;" \
+		"setenv filesize;saveenv\0" \
+	"loadfile=/tftpboot/TRAB/uImage\0" \
+	"loadaddr=c400000\0" \
+	"net_load=tftpboot $loadaddr $loadfile\0" \
+	"net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \
+	"kernel_addr=00040000\0" \
+	"flash_nfs=run nfs_args add_net add_misc;bootm $kernel_addr\0" \
+	"mdm_init1=ATZ\0" \
+	"mdm_init2=ATS0=1\0" \
+	"mdm_flow_control=rts/cts\0"
+#else /* !CFG_HUSH_PARSER */
 #define	CONFIG_EXTRA_ENV_SETTINGS	\
 	"nfs_args=setenv bootargs root=/dev/nfs rw " \
 		"nfsroot=$(serverip):$(rootpath)\0" \
@@ -184,7 +219,29 @@
 	"mdm_init1=ATZ\0" \
 	"mdm_init2=ATS0=1\0" \
 	"mdm_flow_control=rts/cts\0"
+#endif /* CFG_HUSH_PARSER */
 #else	/* CONFIG_BIG_FLASH */
+#ifdef CFG_HUSH_PARSER
+#define	CONFIG_EXTRA_ENV_SETTINGS	\
+	"nfs_args=setenv bootargs root=/dev/nfs rw " \
+		"nfsroot=$serverip:$rootpath\0" \
+	"rootpath=/opt/eldk/arm_920TDI\0" \
+	"ram_args=setenv bootargs root=/dev/ram rw\0" \
+	"add_net=setenv bootargs $bootargs ethaddr=$ethaddr " \
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
+	"add_misc=setenv bootargs $bootargs console=ttyS0 panic=1\0" \
+	"load=tftp 0xC100000 /tftpboot/TRAB/u-boot.bin\0" \
+	"update=protect off 1:0;era 1:0;cp.b 0xc100000 0 $filesize\0" \
+	"loadfile=/tftpboot/TRAB/uImage\0" \
+	"loadaddr=c400000\0" \
+	"net_load=tftpboot $loadaddr $loadfile\0" \
+	"net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \
+	"kernel_addr=00040000\0" \
+	"flash_nfs=run nfs_args add_net add_misc;bootm $kernel_addr\0" \
+	"mdm_init1=ATZ\0" \
+	"mdm_init2=ATS0=1\0" \
+	"mdm_flow_control=rts/cts\0"
+#else /* !CFG_HUSH_PARSER */
 #define	CONFIG_EXTRA_ENV_SETTINGS	\
 	"nfs_args=setenv bootargs root=/dev/nfs rw " \
 		"nfsroot=$(serverip):$(rootpath)\0" \
@@ -204,6 +261,7 @@
 	"mdm_init1=ATZ\0" \
 	"mdm_init2=ATS0=1\0" \
 	"mdm_flow_control=rts/cts\0"
+#endif /* CFG_HUSH_PARSER */
 #endif	/* CONFIG_BIG_FLASH */
 
 #if 0	/* disabled for development */
@@ -223,7 +281,6 @@
  */
 #define	CFG_LONGHELP				/* undef to save memory		*/
 #define	CFG_PROMPT		"TRAB # "	/* Monitor Command Prompt	*/
-/* #define CFG_HUSH_PARSER		1 */	/* use "hush" command parser	*/
 #ifdef	CFG_HUSH_PARSER
 #define CFG_PROMPT_HUSH_PS2	"> "
 #endif
@@ -257,6 +314,11 @@
 
 #define CONFIG_MISC_INIT_R		/* have misc_init_r() function	*/
 
+/*-----------------------------------------------------------------------
+ * burn-in test stuff
+ */
+#define BURN_IN_CYCLE_DELAY	20	/* delay in sec between burn-in test cycles */
+
 /*-----------------------------------------------------------------------
  * Stack sizes
  *

include/exports.h

@@ -18,6 +18,10 @@ void *malloc(size_t);
 void free(void*);
 void udelay(unsigned long);
 unsigned long get_timer(unsigned long);
+#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+int i2c_write (uchar, uint, int , uchar* , int);
+int i2c_read (uchar, uint, int , uchar* , int);
+#endif	/* CFG_CMD_I2C */
 
 void app_startup(char **);
 
@@ -31,7 +35,7 @@ enum {
 	XF_MAX
 };
 
-#define XF_VERSION	1
+#define XF_VERSION	2
 
 #if defined(CONFIG_I386)
 extern gd_t *global_data;

include/fat.h

@@ -204,5 +204,6 @@ int file_fat_detectfs(void);
 int file_fat_ls(const char *dir);
 long file_fat_read(const char *filename, void *buffer, unsigned long maxsize);
 const char *file_getfsname(int idx);
+int fat_register_device(block_dev_desc_t *dev_desc, int part_no);
 
 #endif /* _FAT_H_ */

include/jffs2/jffs2.h

@@ -82,6 +82,7 @@
 #define JFFS2_NODETYPE_DIRENT (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 1)
 #define JFFS2_NODETYPE_INODE (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 2)
 #define JFFS2_NODETYPE_CLEANMARKER (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 3)
+#define JFFS2_NODETYPE_PADDING (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 4)
 
 /* Maybe later... */
 /*#define JFFS2_NODETYPE_CHECKPOINT (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 3) */

include/linux/mtd/nand.h

@@ -193,6 +193,6 @@ struct nand_flash_dev {
 #define NAND_JFFS2_OOB8_FSDALEN		2
 #define NAND_JFFS2_OOB16_FSDALEN	8
 
-void nand_probe(unsigned long physadr);
+unsigned long nand_probe(unsigned long physadr);
 
 #endif /* __LINUX_MTD_NAND_H */

include/part.h

@@ -50,6 +50,7 @@ typedef struct block_dev_desc {
 #define IF_TYPE_ATAPI		3
 #define IF_TYPE_USB		4
 #define IF_TYPE_DOC		5
+#define IF_TYPE_MMC		6
 
 /* Part types */
 #define	PART_TYPE_UNKNOWN	0x00

include/usb.h

@@ -169,7 +169,7 @@ struct usb_device {
  * this is how the lowlevel part communicate with the outer world
  */
 
-#ifdef CONFIG_USB_UHCI
+#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI)
 int usb_lowlevel_init(void);
 int usb_lowlevel_stop(void);
 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len);
@@ -228,6 +228,11 @@ int usb_string(struct usb_device *dev, int index, char *buf, size_t size);
 int usb_set_interface(struct usb_device *dev, int interface, int alternate);
 
 /* big endian -> little endian conversion */
+/* some CPUs are already little endian e.g. the ARM920T */
+#ifdef LITTLEENDIAN
+#define swap_16(x) ((unsigned short)(x))
+#define swap_32(x) ((unsigned long)(x))
+#else
 #define swap_16(x) \
 	((unsigned short)( \
 		(((unsigned short)(x) & (unsigned short)0x00ffU) << 8) | \
@@ -238,6 +243,7 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate);
 		(((unsigned long)(x) & (unsigned long)0x0000ff00UL) <<  8) | \
 		(((unsigned long)(x) & (unsigned long)0x00ff0000UL) >>  8) | \
 		(((unsigned long)(x) & (unsigned long)0xff000000UL) >> 24) ))
+#endif /* LITTLEENDIAN */
 
 /*
  * Calling this entity a "pipe" is glorifying it. A USB pipe

include/version.h

@@ -24,6 +24,6 @@
 #ifndef	__VERSION_H__
 #define	__VERSION_H__
 
-#define	U_BOOT_VERSION	"U-Boot 0.4.8"
+#define	U_BOOT_VERSION	"U-Boot 1.0.0-pre"
 
 #endif	/* __VERSION_H__ */

lib_arm/board.c

@@ -248,6 +248,7 @@ void start_armboot (void)
 #endif /* CONFIG_VFD */
 
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
+	puts ("NAND:");
 	nand_init();		/* go init the NAND */
 #endif
 

lib_ppc/board.c

@@ -865,7 +865,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
 
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
 	WATCHDOG_RESET ();
-	puts ("NAND:  ");
+	puts ("NAND:");
 	nand_init();		/* go init the NAND */
 #endif
 

post/cache_8xx.S

@@ -27,8 +27,7 @@
     defined(CONFIG_MPC850) || \
     defined(CONFIG_MPC855) || \
     defined(CONFIG_MPC860) || \
-    defined(CONFIG_MPC862) || \
-    defined(CONFIG_MPC824X)
+    defined(CONFIG_MPC862)
 
 #include <post.h>
 #include <ppc_asm.tmpl>
@@ -491,6 +490,6 @@ cache_post_test6_data:
 	mtlr	r0
 	blr
 
-#endif /* CONFIG_MPC823 || MPC850 || MPC855 || MPC860 || MPC824X */
+#endif /* CONFIG_MPC823 || MPC850 || MPC855 || MPC860 */
 #endif /* CONFIG_POST & CFG_POST_CACHE */
 #endif /* CONFIG_POST */

post/ether.c

@@ -38,7 +38,7 @@
 #ifdef CONFIG_POST
 
 #include <post.h>
-
+#if CONFIG_POST & CFG_POST_ETHER
 #if defined(CONFIG_8xx)
 #include <commproc.h>
 #elif defined(CONFIG_MPC8260)
@@ -50,8 +50,6 @@
 #include <command.h>
 #include <net.h>
 
-#if CONFIG_POST & CFG_POST_ETHER
-
 #define MIN_PACKET_LENGTH	64
 #define MAX_PACKET_LENGTH	256
 #define TEST_NUM		1