* Update TRAB auto update code

* Make fatload set filesize environment variable
  fix potential buffer overlow problem

* enable basic / medium / high-end configurations for PPChameleonEVB
  board; fix NAND code

* enable TFTP client code to specify to the server the desired
  timeout value (see RFC-2349)

CHANGELOG

@@ -1,7 +1,152 @@
 ======================================================================
-Changes for U-Boot 0.4.7:
+Changes for U-Boot 1.0.0:
 ======================================================================
 
+* Make fatload set filesize environment variable
+
+* enable basic / medium / high-end configurations for PPChameleonEVB
+  board; fix NAND code
+
+* enable TFTP client code to specify to the server the desired
+  timeout value (see RFC-2349)
+
+* Improve SDRAM setup for TRAB board
+
+* Suppress all output with splashscreen configured only if "splashimage"
+  is set
+
+* Fix problems with I2C support for mpc5200
+
+* Adapt TRAB configuration and auto_update to new memory layout
+
+* Add configuration for wtk board
+
+* Add support for the Sharp LQ065T9DR51U LCD display
+
+* Patch by Rune Torgersen, 17 Sep 2003:
+  - Fixes for MPC8266 default config
+  - Allow eth_loopback_test() on 8260 to use a subset of the FCC's
+
+* Patches by Jon Diekema, 17 Sep 2003:
+  - update README (SHOW_BOOT_PROGRESS values for cmd_nand.c and
+    env_common.c)
+  - sbc8260 tweaks
+  - adjust "help" output
+
+* Patches by Anders Larsen, 17 Sep 2003:
+  - fix spelling errors
+  - set GD_FLG_DEVINIT flag only after device function pointers
+    are valid
+  - Allow CFG_ALT_MEMTEST on systems where address zero isn't
+    writeable
+  - enable 3.rd UART (ST-UART) on PXA(XScale) CPUs
+  - trigger watchdog while waiting in serial driver
+
+* Add auto-update code for TRAB board using USB memory sticks,
+  support new configuration with more memory
+
+* disable MPC5200 bus pipelining as workaround for bus contention
+
+* Modify XLB arbiter priorities on MPC5200 so all devices use same
+  priority; configure critical interrupts to be handled like external
+  interrupts
+
+* Make IPB clock on MGT5100/MPC5200 configurable in board config file;
+  go back to 66 MHz for stability
+
+* Patches by Jon Diekema, 15 Sep 2003:
+  - add description for missing CFG_CMD_* entries in the README file
+  - sacsng tweaks
+
+* Patch by Gleb Natapov, 14 Sep 2003:
+  enable watchdog support for all MPC824x boards that have a watchdog
+
+* On MPC5200, restrict FEC to a maximum of 10 Mbps to work around the
+  "Non-octet Aligned Frame" errors we see at 100 Mbps
+
+* Patch by Sharad Gupta, 14 Sep 2003:
+  fix SPR numbers for upper BAT register ([ID]BAT[4-7][UL])
+
+* Patch by llandre, 11 Sep 2003:
+  update configuration for PPChameleonEVB board
+
+* Patch by David Müller, 13 Sep 2003:
+  various changes to VCMA9 board specific files
+
+* Add I2C support for MGT5100 / MPC5200
+
+* Patch by Rune Torgersen, 11 Sep 2003:
+  Changed default memory option on MPC8266ADS to NOT be Page Based
+  Interleave, since this doesn't work very well with the standard
+  16MB DIMM
+
+* Patch by George G. Davis, 12 Sep 2003:
+  fix Makefile settings for sk98 driver
+
+* Patch by Stefan Roese, 12 Sep 2003:
+  - new boards added: DP405, HUB405, PLU405, VOH405
+  - some esd boards updated
+  - cpu/ppc4xx/sdram.c: disable memory controller before setting
+    first values
+  - cpu/ppc4xx/405_pci.c: set vendor id on PPC405EP systems
+
+* Patch by Martin Krause, 11 Sep 2003:
+  add burn-in tests for TRAB board
+
+* Enable instruction cache on MPC5200 board
+
+* Patch by Denis Peter, 11 Sep 2003:
+  - fix USB data pointer assignment for bulk only transfer.
+  - prevent to display erased directories in FAT filesystem.
+
+* Change output format for NAND flash - make it look like for other
+  memory, too
+
+======================================================================
+Changes for U-Boot 0.4.8:
+======================================================================
+
+<<<<<<< CHANGELOG
+<<<<<<< CHANGELOG
+<<<<<<< CHANGELOG
+* Add I2C and RTC support for RMU board
+
+=======
+=======
+=======
+* Patches by Denis Peter, 9 Sep 2003:
+  add FAT support for IDE, SCSI and USB
+
+* Patches by Gleb Natapov, 2 Sep 2003:
+  - cleanup of POST code for unsupported architectures
+  - MPC824x locks way0 of data cache for use as initial RAM;
+    this patch unlocks it after relocation to RAM and invalidates
+    the locked entries.
+
+* Patch by Gleb Natapov, 30 Aug 2003:
+  new I2C driver for mpc107 bridge. Now works from flash.
+
+* Patch by Dave Ellis, 11 Aug 2003:
+  - JFFS2: fix typo in common/cmd_jffs2.c
+  - JFFS2: fix CFG_JFFS2_SORT_FRAGMENTS option
+  - JFFS2: remove node version 0 warning
+  - JFFS2: accept JFFS2 PADDING nodes
+  - SXNI855T: add AM29LV800 support
+  - SXNI855T: move environment from EEPROM to flash
+  - SXNI855T: boot from JFFS2 in NOR or NAND flash
+
+* Patch by Bill Hargen, 11 Aug 2003:
+  fixes for I2C on MPC8240
+  - fix i2c_write routine
+  - fix iprobe command
+  - eliminates use of global variables, plus dead code, cleanup.
+
+* Add support for USB Mass Storage Devices (BBB)
+  (tested with USB memory sticks only)
+
+* Avoid flicker on TRAB's VFD
+
+>>>>>>> 1.130
 * Add support for SK98xx driver
 
 * Add PCI support for SL8245 board
@@ -27,6 +172,10 @@ Changes for U-Boot 0.4.7:
 * Patch by Yuli Barcohen, 7 Aug 2003:
   check BCSR to detect if the board is configured in PCI mode
 
+======================================================================
+Changes for U-Boot 0.4.7:
+======================================================================
+
 * Patch by Raghu Krishnaprasad, 7 Aug 2003:
   add support for Adder II MPC852T module
 
@@ -43,6 +192,7 @@ Changes for U-Boot 0.4.7:
 * Add GCC library to examples/Makefile so GCC utility functions will
   be resolved, too
 
+>>>>>>> 1.118
 * Add I2C and RTC support for RMU board using software I2C driver
   (because of better response to iprobe command); fix problem with
   "reset" command
@@ -51,6 +201,7 @@ Changes for U-Boot 0.4.7:
   Added CONFIG_BOOTP_DNS2 and CONFIG_BOOTP_SEND_HOSTNAME to
   CONFIG_BOOTP_MAKS (see README).
 
+>>>>>>> 1.112
 * Fix ICU862 environment problem
 
 * Fix RAM size detection for RMU board
@@ -263,7 +414,7 @@ Changes for U-Boot 0.4.1:
   - PIC on LWMON board needs delay after power-on
   - Add missing RSR definitions for MPC8xx
   - Improve log buffer handling: guarantee clean reset after power-on
-  - Add support for EXBITGEN board
+  - Add support for EXBITGEN board (aka "genie")
   - Add support for SL8245 board
 
 * Code cleanup:

CREDITS

@@ -302,3 +302,9 @@ W: www.elinos.com
 N: Pantelis Antoniou
 E: panto@intracom.gr
 D: NETVIA board support, ARTOS support.
+
+N: Raghu Krishnaprasad
+E: Raghu.Krishnaprasad@fci.com
+D: Support for Adder-II MPC852T evaluation board
+W: http://www.forcecomputers.com
+

MAINTAINERS

@@ -89,6 +89,7 @@ Wolfgang Denk <wd@denx.de>
 	TQM8255			MPC8255
 
 	CPU86			MPC8260
+	PM825			MPC8250
 	PM826			MPC8260
 	TQM8260			MPC8260
 
@@ -107,6 +108,10 @@ Dave Ellis <DGE@sixnetio.com>
 
 	SXNI855T		MPC8xx
 
+Raghu Krishnaprasad <raghu.krishnaprasad@fci.com>
+
+	ADDERII			MPC852T
+
 Thomas Frieden <ThomasF@hyperion-entertainment.com>
 
 	AmigaOneG3SE		MPC7xx
@@ -195,11 +200,15 @@ Stefan Roese <stefan.roese@esd-electronics.com>
 	CPCI440			PPC440GP
 	CPCIISER4		PPC405GP
 	DASA_SIM		IOP480 (PPC401)
+	DP405			PPC405EP
 	DU405			PPC405GP
+	HUB405			PPC405EP
 	OCRTC			PPC405GP
 	ORSG			PPC405GP
 	PCI405			PPC405GP
+	PLU405			PPC405EP
 	PMC405			PPC405GP
+	VOH405			PPC405EP
 
 Peter De Schrijver <p2@mind.be>
 

MAKEALL

@@ -56,10 +56,11 @@ LIST_4xx="	\
 	ADCIOP		AR405		ASH405          BUBINGA405EP    \
 	CANBT		CPCI405		CPCI4052 	CPCI405AB       \
 	CPCI440         CPCIISER4	CRAYL1  	DASA_SIM	\
-	DU405    	EBONY           ERIC  		EXBITGEN	\
-	MIP405  	MIP405T		ML2		OCRTC		\
-	ORSG		PCI405		PIP405		PMC405          \
-	PPChameleonEVB	W7OLMC		W7OLMG          WALNUT405	\
+	DP405           DU405    	EBONY           ERIC  		\
+	EXBITGEN	HUB405          MIP405  	MIP405T		\
+	ML2		OCRTC		ORSG		PCI405		\
+	PIP405		PLU405          PMC405          PPChameleonEVB	\
+	VOH405          W7OLMC		W7OLMG          WALNUT405	\
 "
 
 #########################################################################

Makefile

@@ -76,6 +76,7 @@ export	CROSS_COMPILE
 
 # The "tools" are needed early, so put this first
 SUBDIRS	= tools \
+	  examples \
 	  lib_generic \
 	  lib_$(ARCH) \
 	  cpu/$(CPU) \
@@ -89,8 +90,7 @@ SUBDIRS	= tools \
 	  drivers \
 	  drivers/sk98lin \
 	  post \
-	  post/cpu \
-	  examples
+	  post/cpu
 
 #########################################################################
 # U-Boot objects....order is important (i.e. start must be first)
@@ -117,6 +117,8 @@ LIBS += drivers/sk98lin/libsk98lin.a
 LIBS += post/libpost.a post/cpu/libcpu.a
 LIBS += common/libcommon.a
 LIBS += lib_generic/libgeneric.a
+# Add GCC lib
+PLATFORM_LIBS += -L $(shell dirname `$(CC) -print-libgcc-file-name`) -lgcc
 
 #########################################################################
 #########################################################################
@@ -468,9 +470,15 @@ v37_config:	unconfig
 	@echo "#define CONFIG_SHARP_LQ084V1DG21" >>include/config.h
 	@./mkconfig $(@:_config=) ppc mpc8xx v37
 
+wtk_config:	unconfig
+	@echo "#define CONFIG_LCD" >include/config.h
+	@echo "#define CONFIG_SHARP_LQ065T9DR51U" >>include/config.h
+	@./mkconfig -a TQM823L ppc mpc8xx tqm8xx
+
 #########################################################################
 ## PPC4xx Systems
 #########################################################################
+xtract_4xx = $(subst _MODEL_BA,,$(subst _MODEL_ME,,$(subst _MODEL_HI,,$(subst _config,,$1))))
 
 ADCIOP_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx adciop esd
@@ -505,6 +513,9 @@ CRAYL1_config:unconfig
 DASA_SIM_config: unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx dasa_sim esd
 
+DP405_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx dp405 esd
+
 DU405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx du405 esd
 
@@ -517,6 +528,9 @@ ERIC_config:unconfig
 EXBITGEN_config:unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx exbitgen
 
+HUB405_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx hub405 esd
+
 MIP405_config:unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx mip405 mpl
 
@@ -538,11 +552,33 @@ PCI405_config:	unconfig
 PIP405_config:unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx pip405 mpl
 
+PLU405_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx plu405 esd
+
 PMC405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx pmc405 esd
 
+PPChameleonEVB_MODEL_BA_config	\
+PPChameleonEVB_MODEL_ME_config	\
+PPChameleonEVB_MODEL_HI_config	\
 PPChameleonEVB_config:	unconfig
-	@./mkconfig $(@:_config=) ppc ppc4xx PPChameleonEVB dave
+	@ >include/config.h
+	@[ -z "$(findstring _MODEL_BA,$@)" ] || \
+		{ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 0" >>include/config.h ; \
+		  echo "... BASIC model" ; \
+		}
+	@[ -z "$(findstring _MODEL_ME,$@)" ] || \
+		{ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 1" >>include/config.h ; \
+		  echo "... MEDIUM model" ; \
+		}
+	@[ -z "$(findstring _MODEL_HI,$@)" ] || \
+		{ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 2" >>include/config.h ; \
+		  echo "... HIGH-END model" ; \
+		}
+	@./mkconfig -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave
+
+VOH405_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx voh405 esd
 
 W7OLMC_config	\
 W7OLMG_config: unconfig
@@ -782,7 +818,7 @@ shannon_config	:	unconfig
 ## ARM92xT Systems
 #########################################################################
 
-xtract_trab = $(subst _big_flash,,$(subst _config,,$1))
+xtract_trab = $(subst _bigram,,$(subst _bigflash,,$(subst _old,,$(subst _config,,$1))))
 
 omap1510inn_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm925t omap1510inn
@@ -797,11 +833,23 @@ smdk2410_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm920t smdk2410
 
 trab_config \
-trab_big_flash_config:	unconfig
+trab_bigram_config \
+trab_bigflash_config \
+trab_old_config:	unconfig
 	@ >include/config.h
-	@[ -z "$(findstring _big_flash,$@)" ] || \
-		{ echo "#define CONFIG_BIG_FLASH" >>include/config.h ; \
-		  echo "... with big flash support" ; \
+	@[ -z "$(findstring _bigram,$@)" ] || \
+		{ echo "#define CONFIG_FLASH_8MB" >>include/config.h ; \
+		  echo "... with 8 MB Flash, 32 MB RAM" ; \
+		}
+	@[ -z "$(findstring _bigflash,$@)" ] || \
+		{ echo "#define CONFIG_RAM_16MB" >>include/config.h ; \
+		  echo "... with 16 MB Flash, 16 MB RAM" ; \
+		  echo "TEXT_BASE = 0x0CF00000" >board/trab/config.tmp ; \
+		}
+	@[ -z "$(findstring _old,$@)" ] || \
+		{ echo "#define CONFIG_OLD_VERSION" >>include/config.h ; \
+		  echo "... with small memory configuration" ; \
+		  echo "TEXT_BASE = 0x0CF00000" >board/trab/config.tmp ; \
 		}
 	@./mkconfig -a $(call xtract_trab,$@) arm arm920t trab
 
@@ -907,6 +955,7 @@ clean:
 	rm -f tools/gdb/astest tools/gdb/gdbcont tools/gdb/gdbsend
 	rm -f tools/env/fw_printenv tools/env/fw_setenv
 	rm -f board/cray/L1/bootscript.c board/cray/L1/bootscript.image
+	rm -f board/trab/trab_fkt board/trab/config.tmp
 
 clobber:	clean
 	find . -type f \

README

@@ -203,6 +203,7 @@ Directory Hierarchy:
 - board/mpl/common	Common files for MPL boards
 - board/mpl/pip405	Files specific to PIP405     boards
 - board/mpl/mip405	Files specific to MIP405     boards
+- board/mpl/vcma9	Files specific to VCMA9      boards
 - board/musenki	Files specific to MUSEKNI    boards
 - board/mvs1	Files specific to MVS1       boards
 - board/nx823   Files specific to NX823      boards
@@ -363,7 +364,7 @@ The following options need to be configured:
 		CONFIG_IMPA7,       CONFIG_LART,       CONFIG_LUBBOCK,
 		CONFIG_INNOVATOROMAP1510,	CONFIG_INNOVATOROMAP1610
 		CONFIG_SHANNON,     CONFIG_SMDK2400,   CONFIG_SMDK2410,
-		CONFIG_TRAB,	    CONFIG_AT91RM9200DK
+		CONFIG_TRAB,	    CONFIG_VCMA9,      CONFIG_AT91RM9200DK
 
 
 - CPU Module Type: (if CONFIG_COGENT is defined)
@@ -572,13 +573,18 @@ The following options need to be configured:
 		#define enables commands:
 		-------------------------
 		CFG_CMD_ASKENV	* ask for env variable
+		CFG_CMD_AUTOSCRIPT Autoscript Support
 		CFG_CMD_BDI	  bdinfo
 		CFG_CMD_BEDBUG	  Include BedBug Debugger
+		CFG_CMD_BMP     * BMP support
 		CFG_CMD_BOOTD	  bootd
 		CFG_CMD_CACHE	  icache, dcache
 		CFG_CMD_CONSOLE	  coninfo
 		CFG_CMD_DATE	* support for RTC, date/time...
 		CFG_CMD_DHCP	  DHCP support
+		CFG_CMD_DIAG    * Diagnostics
+		CFG_CMD_DOC     * Disk-On-Chip Support
+		CFG_CMD_DTT       Digital Therm and Thermostat 
 		CFG_CMD_ECHO	* echo arguments
 		CFG_CMD_EEPROM	* EEPROM read/write support
 		CFG_CMD_ELF	  bootelf, bootvx
@@ -588,27 +594,37 @@ The following options need to be configured:
 		CFG_CMD_FDOS	* Dos diskette Support
 		CFG_CMD_FLASH	  flinfo, erase, protect
 		CFG_CMD_FPGA	  FPGA device initialization support
+		CFG_CMD_HWFLOW  * RTS/CTS hw flow control
 		CFG_CMD_I2C	* I2C serial bus support
 		CFG_CMD_IDE	* IDE harddisk support
 		CFG_CMD_IMI	  iminfo
+		CFG_CMD_IMLS      List all found images
 		CFG_CMD_IMMAP	* IMMR dump support
 		CFG_CMD_IRQ	* irqinfo
+		CFG_CMD_JFFS2   * JFFS2 Support
 		CFG_CMD_KGDB	* kgdb
 		CFG_CMD_LOADB	  loadb
 		CFG_CMD_LOADS	  loads
 		CFG_CMD_MEMORY	  md, mm, nm, mw, cp, cmp, crc, base,
 				  loop, mtest
+		CFG_CMD_MISC      Misc functions like sleep etc
 		CFG_CMD_MMC	  MMC memory mapped support
 		CFG_CMD_MII	  MII utility commands
+		CFG_CMD_NAND    * NAND support
 		CFG_CMD_NET	  bootp, tftpboot, rarpboot
 		CFG_CMD_PCI	* pciinfo
 		CFG_CMD_PCMCIA	* PCMCIA support
+		CFG_CMD_PING    * send ICMP ECHO_REQUEST to network host
+		CFG_CMD_PORTIO    Port I/O
 		CFG_CMD_REGINFO * Register dump
 		CFG_CMD_RUN	  run command in env variable
+		CFG_CMD_SAVES     save S record dump
 		CFG_CMD_SCSI	* SCSI Support
+		CFG_CMD_SDRAM   * print SDRAM configuration information
 		CFG_CMD_SETGETDCR Support for DCR Register access (4xx only)
 		CFG_CMD_SPI	* SPI serial bus support
 		CFG_CMD_USB	* USB support
+		CFG_CMD_VFD     * VFD support (TRAB)
 		CFG_CMD_BSP	* Board SPecific functions
 		-----------------------------------------------
 		CFG_CMD_ALL	all
@@ -1400,7 +1416,13 @@ The following options need to be configured:
    -1	common/cmd_ide.c	Read Error on boot device
    -1	common/cmd_ide.c	Image header has bad magic number
 
-   -1	common/cmd_nvedit.c	Environment not changable, but has bad CRC
+   -1	common/cmd_nand.c	Bad usage of "nand" command
+   -1	common/cmd_nand.c	No boot device
+   -1	common/cmd_nand.c	Unknown Chip ID on boot device
+   -1	common/cmd_nand.c	Read Error on boot device
+   -1	common/cmd_nand.c	Image header has bad magic number
+
+   -1	common/env_common.c     Environment has a bad CRC, using default
 
 
 Modem Support:
@@ -1482,6 +1504,10 @@ Configuration Settings:
 - CFG_ALT_MEMTEST:
 		Enable an alternate, more extensive memory test.
 
+- CFG_MEMTEST_SCRATCH:
+		Scratch address used by the alternate memory test
+		You only need to set this if address zero isn't writeable
+
 - CFG_TFTP_LOADADDR:
 		Default load address for network file downloads
 

board/at91rm9200dk/at91rm9200dk.c

@@ -66,7 +66,7 @@ int dram_init (void)
  * The NAND lives in the CS2* space
  */
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
-extern void nand_probe (ulong physadr);
+extern ulong nand_probe (ulong physadr);
 
 #define AT91_SMARTMEDIA_BASE 0x40000000	/* physical address to access memory on NCS3 */
 void nand_init (void)
@@ -103,10 +103,12 @@ void nand_init (void)
 	*AT91C_PIOB_ODR = AT91C_PIO_PB1;	/* disable output */
 
 	if (*AT91C_PIOB_PDSR & AT91C_PIO_PB1)
-		printf ("No ");
-	printf ("SmartMedia card inserted\n");
+		printf ("  No SmartMedia card inserted\n");
+#ifdef DEBUG
+	printf ("  SmartMedia card inserted\n");
 
 	printf ("Probing at 0x%.8x\n", AT91_SMARTMEDIA_BASE);
-	nand_probe (AT91_SMARTMEDIA_BASE);
+#endif
+	printf ("%4lu MB\n", nand_probe(AT91_SMARTMEDIA_BASE) >> 20);
 }
 #endif

board/at91rm9200dk/flash.c

@@ -160,7 +160,7 @@ ulong flash_init (void)
 		if (i == 0)
 			flashbase = PHYS_FLASH_1;
 		else
-			panic ("configured to many flash banks!\n");
+			panic ("configured too many flash banks!\n");
 
 		sector = 0;
 		start_address = flashbase;

board/cradle/flash.c

@@ -59,7 +59,7 @@ ulong flash_init(void)
 		flashbase = PHYS_FLASH_2;
 		break;
 	 default:
-		panic("configured to many flash banks!\n");
+		panic("configured too many flash banks!\n");
 		break;
       }
       for (j = 0; j < flash_info[i].sector_count; j++)

board/csb226/flash.c

@@ -62,7 +62,7 @@ ulong flash_init(void)
 				flashbase = PHYS_FLASH_1;
 				break;
 			default:
-				panic("configured to many flash banks!\n");
+				panic("configured too many flash banks!\n");
 				break;
 		}
 		for (j = 0; j < flash_info[i].sector_count; j++) {

board/dave/PPChameleonEVB/PPChameleonEVB.c

@@ -255,16 +255,23 @@ int testdram (void)
 /* ------------------------------------------------------------------------- */
 
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
-extern void
+extern ulong
 nand_probe(ulong physadr);
 
 void
 nand_init(void)
 {
+	ulong totlen = 0;
+
+#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) || \
+    (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
 	debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE);
-	nand_probe (CFG_NAND0_BASE);
+	totlen += nand_probe (CFG_NAND0_BASE);
+#endif	/* CONFIG_PPCHAMELEON_MODULE_ME, CONFIG_PPCHAMELEON_MODULE_HI */
 
 	debug ("Probing at 0x%.8x\n", CFG_NAND1_BASE);
-	nand_probe (CFG_NAND1_BASE);
+	totlen += nand_probe (CFG_NAND1_BASE);
+
+	printf ("%4lu MB\n", totlen >>20);
 }
 #endif

board/dnp1110/flash.c

@@ -74,7 +74,7 @@ unsigned long flash_init (void)
 		 flash_get_offsets(PHYS_FLASH_1, &flash_info[i]);
 		break;
 	   default:
-		panic("configured to many flash banks!\n");
+		panic("configured too many flash banks!\n");
 		break;
 	}
 	size += flash_info[i].size;

board/ep7312/flash.c

@@ -50,7 +50,7 @@ ulong flash_init (void)
 		if (i == 0)
 			flashbase = PHYS_FLASH_1;
 		else
-			panic ("configured to many flash banks!\n");
+			panic ("configured too many flash banks!\n");
 		for (j = 0; j < flash_info[i].sector_count; j++) {
 			flash_info[i].start[j] = flashbase + j * MAIN_SECT_SIZE;
 		}

board/esd/ash405/ash405.c

@@ -246,7 +246,6 @@ void nand_init(void)
 {
 	nand_probe(CFG_NAND_BASE);
 	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
-		puts("NAND:  ");
 		print_size(nand_dev_desc[0].totlen, "\n");
 	}
 }

board/esd/common/xilinx_jtag/lenval.c

@@ -0,0 +1,217 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*******************************************************/
+/* file: lenval.c                                      */
+/* abstract:  This file contains routines for using    */
+/*            the lenVal data structure.               */
+/*******************************************************/
+
+#include <common.h>
+#include <asm/processor.h>
+
+#include "lenval.h"
+#include "ports.h"
+
+
+/*****************************************************************************
+ * Function:     value
+ * Description:  Extract the long value from the lenval array.
+ * Parameters:   plvValue    - ptr to lenval.
+ * Returns:      long        - the extracted value.
+ *****************************************************************************/
+long value( lenVal*     plvValue )
+{
+	long    lValue;         /* result to hold the accumulated result */
+	short   sIndex;
+
+	lValue  = 0;
+	for ( sIndex = 0; sIndex < plvValue->len ; ++sIndex )
+	{
+		lValue <<= 8;                       /* shift the accumulated result */
+		lValue |= plvValue->val[ sIndex];   /* get the last byte first */
+	}
+
+	return( lValue );
+}
+
+/*****************************************************************************
+ * Function:     initLenVal
+ * Description:  Initialize the lenval array with the given value.
+ *               Assumes lValue is less than 256.
+ * Parameters:   plv         - ptr to lenval.
+ *               lValue      - the value to set.
+ * Returns:      void.
+ *****************************************************************************/
+void initLenVal( lenVal*    plv,
+                 long       lValue )
+{
+	plv->len    = 1;
+	plv->val[0] = (unsigned char)lValue;
+}
+
+/*****************************************************************************
+ * Function:     EqualLenVal
+ * Description:  Compare two lenval arrays with an optional mask.
+ * Parameters:   plvTdoExpected  - ptr to lenval #1.
+ *               plvTdoCaptured  - ptr to lenval #2.
+ *               plvTdoMask      - optional ptr to mask (=0 if no mask).
+ * Returns:      short   - 0 = mismatch; 1 = equal.
+ *****************************************************************************/
+short EqualLenVal( lenVal*  plvTdoExpected,
+                   lenVal*  plvTdoCaptured,
+                   lenVal*  plvTdoMask )
+{
+	short           sEqual;
+	short           sIndex;
+	unsigned char   ucByteVal1;
+	unsigned char   ucByteVal2;
+	unsigned char   ucByteMask;
+
+	sEqual  = 1;
+	sIndex  = plvTdoExpected->len;
+
+	while ( sEqual && sIndex-- )
+	{
+		ucByteVal1  = plvTdoExpected->val[ sIndex ];
+		ucByteVal2  = plvTdoCaptured->val[ sIndex ];
+		if ( plvTdoMask )
+		{
+			ucByteMask  = plvTdoMask->val[ sIndex ];
+			ucByteVal1  &= ucByteMask;
+			ucByteVal2  &= ucByteMask;
+		}
+		if ( ucByteVal1 != ucByteVal2 )
+		{
+			sEqual  = 0;
+		}
+	}
+
+	return( sEqual );
+}
+
+
+/*****************************************************************************
+ * Function:     RetBit
+ * Description:  return the (byte, bit) of lv (reading from left to right).
+ * Parameters:   plv     - ptr to lenval.
+ *               iByte   - the byte to get the bit from.
+ *               iBit    - the bit number (0=msb)
+ * Returns:      short   - the bit value.
+ *****************************************************************************/
+short RetBit( lenVal*   plv,
+              int       iByte,
+              int       iBit )
+{
+	/* assert( ( iByte >= 0 ) && ( iByte < plv->len ) ); */
+	/* assert( ( iBit >= 0 ) && ( iBit < 8 ) ); */
+	return( (short)( ( plv->val[ iByte ] >> ( 7 - iBit ) ) & 0x1 ) );
+}
+
+/*****************************************************************************
+ * Function:     SetBit
+ * Description:  set the (byte, bit) of lv equal to val
+ * Example:      SetBit("00000000",byte, 1) equals "01000000".
+ * Parameters:   plv     - ptr to lenval.
+ *               iByte   - the byte to get the bit from.
+ *               iBit    - the bit number (0=msb).
+ *               sVal    - the bit value to set.
+ * Returns:      void.
+ *****************************************************************************/
+void SetBit( lenVal*    plv,
+             int        iByte,
+             int        iBit,
+             short      sVal )
+{
+	unsigned char   ucByteVal;
+	unsigned char   ucBitMask;
+
+	ucBitMask   = (unsigned char)(1 << ( 7 - iBit ));
+	ucByteVal   = (unsigned char)(plv->val[ iByte ] & (~ucBitMask));
+
+	if ( sVal )
+	{
+		ucByteVal   |= ucBitMask;
+	}
+	plv->val[ iByte ]   = ucByteVal;
+}
+
+/*****************************************************************************
+ * Function:     AddVal
+ * Description:  add val1 to val2 and store in resVal;
+ *               assumes val1 and val2  are of equal length.
+ * Parameters:   plvResVal   - ptr to result.
+ *               plvVal1     - ptr of addendum.
+ *               plvVal2     - ptr of addendum.
+ * Returns:      void.
+ *****************************************************************************/
+void addVal( lenVal*    plvResVal,
+             lenVal*    plvVal1,
+             lenVal*    plvVal2 )
+{
+	unsigned char   ucCarry;
+	unsigned short  usSum;
+	unsigned short  usVal1;
+	unsigned short  usVal2;
+	short           sIndex;
+
+	plvResVal->len  = plvVal1->len;         /* set up length of result */
+
+	/* start at least significant bit and add bytes    */
+	ucCarry = 0;
+	sIndex  = plvVal1->len;
+	while ( sIndex-- )
+	{
+		usVal1  = plvVal1->val[ sIndex ];   /* i'th byte of val1 */
+		usVal2  = plvVal2->val[ sIndex ];   /* i'th byte of val2 */
+
+		/* add the two bytes plus carry from previous addition */
+		usSum   = (unsigned short)( usVal1 + usVal2 + ucCarry );
+
+		/* set up carry for next byte */
+		ucCarry = (unsigned char)( ( usSum > 255 ) ? 1 : 0 );
+
+		/* set the i'th byte of the result */
+		plvResVal->val[ sIndex ]    = (unsigned char)usSum;
+	}
+}
+
+/*****************************************************************************
+ * Function:     readVal
+ * Description:  read from XSVF numBytes bytes of data into x.
+ * Parameters:   plv         - ptr to lenval in which to put the bytes read.
+ *               sNumBytes   - the number of bytes to read.
+ * Returns:      void.
+ *****************************************************************************/
+void readVal( lenVal*   plv,
+              short     sNumBytes )
+{
+	unsigned char*  pucVal;
+
+	plv->len    = sNumBytes;        /* set the length of the lenVal        */
+	for ( pucVal = plv->val; sNumBytes; --sNumBytes, ++pucVal )
+	{
+		/* read a byte of data into the lenVal */
+		readByte( pucVal );
+	}
+}

board/esd/common/xilinx_jtag/lenval.h

@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*******************************************************/
+/* file: lenval.h                                      */
+/* abstract:  This file contains a description of the  */
+/*            data structure "lenval".                 */
+/*******************************************************/
+
+#ifndef lenval_dot_h
+#define lenval_dot_h
+
+/* the lenVal structure is a byte oriented type used to store an */
+/* arbitrary length binary value. As an example, the hex value   */
+/* 0x0e3d is represented as a lenVal with len=2 (since 2 bytes   */
+/* and val[0]=0e and val[1]=3d.  val[2-MAX_LEN] are undefined    */
+
+/* maximum length (in bytes) of value to read in        */
+/* this needs to be at least 4, and longer than the     */
+/* length of the longest SDR instruction.  If there is, */
+/* only 1 device in the chain, MAX_LEN must be at least */
+/* ceil(27/8) == 4.  For 6 devices in a chain, MAX_LEN  */
+/* must be 5, for 14 devices MAX_LEN must be 6, for 20  */
+/* devices MAX_LEN must be 7, etc..                     */
+/* You can safely set MAX_LEN to a smaller number if you*/
+/* know how many devices will be in your chain.         */
+#define MAX_LEN 7000
+
+
+typedef struct var_len_byte
+{
+	short len;   /* number of chars in this value */
+	unsigned char val[MAX_LEN+1];  /* bytes of data */
+} lenVal;
+
+
+/* return the long representation of a lenVal */
+extern long value(lenVal *x);
+
+/* set lenVal equal to value */
+extern void initLenVal(lenVal *x, long value);
+
+/* check if expected equals actual (taking the mask into account) */
+extern short EqualLenVal(lenVal *expected, lenVal *actual, lenVal *mask);
+
+/* add val1+val2 and put the result in resVal */
+extern void addVal(lenVal *resVal, lenVal *val1, lenVal *val2);
+
+/* return the (byte, bit) of lv (reading from left to right) */
+extern short RetBit(lenVal *lv, int byte, int bit);
+
+/* set the (byte, bit) of lv equal to val (e.g. SetBit("00000000",byte, 1)
+   equals "01000000" */
+extern void SetBit(lenVal *lv, int byte, int bit, short val);
+
+/* read from XSVF numBytes bytes of data into x */
+extern void  readVal(lenVal *x, short numBytes);
+
+#endif

board/esd/common/xilinx_jtag/micro.h

@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*****************************************************************************
+ * File:         micro.h
+ * Description:  This header file contains the function prototype to the
+ *               primary interface function for the XSVF player.
+ * Usage:        FIRST - PORTS.C
+ *               Customize the ports.c function implementations to establish
+ *               the correct protocol for communicating with your JTAG ports
+ *               (setPort() and readTDOBit()) and tune the waitTime() delay
+ *               function.  Also, establish access to the XSVF data source
+ *               in the readByte() function.
+ *               FINALLY - Call xsvfExecute().
+ *****************************************************************************/
+#ifndef XSVF_MICRO_H
+#define XSVF_MICRO_H
+
+/* Legacy error codes for xsvfExecute from original XSVF player v2.0 */
+#define XSVF_LEGACY_SUCCESS 1
+#define XSVF_LEGACY_ERROR   0
+
+/* 4.04 [NEW] Error codes for xsvfExecute. */
+/* Must #define XSVF_SUPPORT_ERRORCODES in micro.c to get these codes */
+#define XSVF_ERROR_NONE         0
+#define XSVF_ERROR_UNKNOWN      1
+#define XSVF_ERROR_TDOMISMATCH  2
+#define XSVF_ERROR_MAXRETRIES   3   /* TDO mismatch after max retries */
+#define XSVF_ERROR_ILLEGALCMD   4
+#define XSVF_ERROR_ILLEGALSTATE 5
+#define XSVF_ERROR_DATAOVERFLOW 6   /* Data > lenVal MAX_LEN buffer size*/
+/* Insert new errors here */
+#define XSVF_ERROR_LAST         7
+
+/*****************************************************************************
+ * Function:     xsvfExecute
+ * Description:  Process, interpret, and apply the XSVF commands.
+ *               See port.c:readByte for source of XSVF data.
+ * Parameters:   none.
+ * Returns:      int - For error codes see above.
+ *****************************************************************************/
+int xsvfExecute(void);
+
+#endif  /* XSVF_MICRO_H */

board/esd/common/xilinx_jtag/ports.c

@@ -0,0 +1,116 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*******************************************************/
+/* file: ports.c                                       */
+/* abstract:  This file contains the routines to       */
+/*            output values on the JTAG ports, to read */
+/*            the TDO bit, and to read a byte of data  */
+/*            from the prom                            */
+/*                                                     */
+/*******************************************************/
+
+#include <common.h>
+#include <asm/processor.h>
+
+#include "ports.h"
+
+static unsigned long output = 0;
+static int filepos = 0;
+static int oldstate = 0;
+static int newstate = 0;
+static int readptr = 0;
+
+extern long filesize;
+extern const unsigned char fpgadata[];
+
+
+/* if in debugging mode, then just set the variables */
+void setPort(short p,short val)
+{
+	if (p==TMS) {
+		if (val) {
+			output |= JTAG_TMS;
+		} else {
+			output &= ~JTAG_TMS;
+		}
+	}
+	if (p==TDI) {
+		if (val) {
+			output |= JTAG_TDI;
+		} else {
+			output &= ~JTAG_TDI;
+		}
+	}
+	if (p==TCK) {
+		if (val) {
+			output |= JTAG_TCK;
+		} else {
+			output &= ~JTAG_TCK;
+		}
+		out32(GPIO0_OR, output);
+	}
+}
+
+
+/* toggle tck LH */
+void pulseClock(void)
+{
+	setPort(TCK,0);  /* set the TCK port to low  */
+	setPort(TCK,1);  /* set the TCK port to high */
+}
+
+
+/* read in a byte of data from the prom */
+void readByte(unsigned char *data)
+{
+	/* pretend reading using a file */
+	*data = fpgadata[readptr++];
+	newstate = (100 * filepos++) / filesize;
+	if (newstate != oldstate) {
+		printf("%4d\r\r\r\r", newstate);
+		oldstate = newstate;
+	}
+}
+
+/* read the TDO bit from port */
+unsigned char readTDOBit(void)
+{
+	unsigned long inputs;
+
+	inputs = in32(GPIO0_IR);
+	if (inputs & JTAG_TDO)
+		return 1;
+	else
+		return 0;
+}
+
+
+/* Wait at least the specified number of microsec.                           */
+/* Use a timer if possible; otherwise estimate the number of instructions    */
+/* necessary to be run based on the microcontroller speed.  For this example */
+/* we pulse the TCK port a number of times based on the processor speed.     */
+void waitTime(long microsec)
+{
+	udelay(microsec); /* esd */
+}

board/esd/common/xilinx_jtag/ports.h

@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*******************************************************/
+/* file: ports.h                                       */
+/* abstract:  This file contains extern declarations   */
+/*            for providing stimulus to the JTAG ports.*/
+/*******************************************************/
+
+#ifndef ports_dot_h
+#define ports_dot_h
+
+/* these constants are used to send the appropriate ports to setPort */
+/* they should be enumerated types, but some of the microcontroller  */
+/* compilers don't like enumerated types */
+#define TCK (short) 0
+#define TMS (short) 1
+#define TDI (short) 2
+
+/*
+ * Use CFG_FPGA_xxx defines from board include file.
+ */
+#define JTAG_TMS   CFG_FPGA_PRG     /* output */
+#define JTAG_TCK   CFG_FPGA_CLK     /* output */
+#define JTAG_TDI   CFG_FPGA_DATA    /* output */
+#define JTAG_TDO   CFG_FPGA_DONE    /* input */
+
+/* set the port "p" (TCK, TMS, or TDI) to val (0 or 1) */
+void setPort(short p, short val);
+
+/* read the TDO bit and store it in val */
+unsigned char readTDOBit(void);
+
+/* make clock go down->up->down*/
+void pulseClock(void);
+
+/* read the next byte of data from the xsvf file */
+void readByte(unsigned char *data);
+
+void waitTime(long microsec);
+
+#endif

board/esd/cpci405/cpci405.c

@@ -433,7 +433,14 @@ int checkboard (void)
 #endif
 
 	if (ctermm2()) {
-		printf("CTERM-M2 - Id=0x%02x)", *(unsigned char *)0xf0000400);
+		unsigned char str[4];
+
+		/*
+		 * Read board-id and save in env-variable
+		 */
+		sprintf(str, "%d", *(unsigned char *)0xf0000400);
+		setenv("boardid", str);
+		printf("CTERM-M2 - Id=%s)", str);
 	} else {
 		if (cpci405_host()) {
 			puts ("PCI Host Version)");
@@ -508,44 +515,144 @@ void ide_set_reset(int on)
 #endif /* CONFIG_IDE_RESET */
 #endif /* CONFIG_CPCI405_VER2 */
 
-#if 0 /* test-only */
-/* ------------------------------------------------------------------------- */
 
-u8 *dhcp_vendorex_prep (u8 * e)
+#ifdef CONFIG_CPCI405AB
+
+#define ONE_WIRE_CLEAR   (*(volatile unsigned short *)0xf0400000 |= 0x0100)
+#define ONE_WIRE_SET     (*(volatile unsigned short *)0xf0400000 &= ~0x0100)
+#define ONE_WIRE_GET     (*(volatile unsigned short *)0xf0400002 & 0x1000)
+
+/*
+ * Generate a 1-wire reset, return 1 if no presence detect was found,
+ * return 0 otherwise.
+ * (NOTE: Does not handle alarm presence from DS2404/DS1994)
+ */
+int OWTouchReset(void)
 {
-	char *ptr;
+	int result;
 
-/* DHCP vendor-class-identifier = 60 */
-	if ((ptr = getenv ("dhcp_vendor-class-identifier"))) {
-		*e++ = 60;
-		*e++ = strlen (ptr);
-		while (*ptr)
-			*e++ = *ptr++;
-	}
-/* my DHCP_CLIENT_IDENTIFIER = 61 */
-	if ((ptr = getenv ("dhcp_client_id"))) {
-		*e++ = 61;
-		*e++ = strlen (ptr);
-		while (*ptr)
-			*e++ = *ptr++;
-	}
+	ONE_WIRE_CLEAR;
+	udelay(480);
+	ONE_WIRE_SET;
+	udelay(70);
 
-	return e;
+	result = ONE_WIRE_GET;
+
+	udelay(410);
+	return result;
 }
 
 
-/* ------------------------------------------------------------------------- */
-
-u8 *dhcp_vendorex_proc (u8 * popt)
+/*
+ * Send 1 a 1-wire write bit.
+ * Provide 10us recovery time.
+ */
+void OWWriteBit(int bit)
 {
-	if (*popt == 61)
-		return (u8 *)-1;
-	if (*popt == 43) {
-		printf("|%s|", popt+4); /* test-only */
-		return (u8 *)-1;
+	if (bit) {
+		/*
+		 * write '1' bit
+		 */
+		ONE_WIRE_CLEAR;
+		udelay(6);
+		ONE_WIRE_SET;
+		udelay(64);
+	} else {
+		/*
+		 * write '0' bit
+		 */
+		ONE_WIRE_CLEAR;
+		udelay(60);
+		ONE_WIRE_SET;
+		udelay(10);
 	}
-	return NULL;
 }
 
-/* ------------------------------------------------------------------------- */
-#endif /* test-only */
+
+/*
+ * Read a bit from the 1-wire bus and return it.
+ * Provide 10us recovery time.
+ */
+int OWReadBit(void)
+{
+	int result;
+
+	ONE_WIRE_CLEAR;
+	udelay(6);
+	ONE_WIRE_SET;
+	udelay(9);
+
+	result = ONE_WIRE_GET;
+
+	udelay(55);
+	return result;
+}
+
+
+void OWWriteByte(int data)
+{
+	int loop;
+
+	for (loop=0; loop<8; loop++) {
+		OWWriteBit(data & 0x01);
+		data >>= 1;
+	}
+}
+
+
+int OWReadByte(void)
+{
+	int loop, result = 0;
+
+	for (loop=0; loop<8; loop++) {
+		result >>= 1;
+		if (OWReadBit()) {
+			result |= 0x80;
+		}
+	}
+
+	return result;
+}
+
+
+int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	volatile unsigned short val;
+	int result;
+	int i;
+	unsigned char ow_id[6];
+	unsigned char str[32];
+	unsigned char ow_crc;
+
+	/*
+	 * Clear 1-wire bit (open drain with pull-up)
+	 */
+	val = *(volatile unsigned short *)0xf0400000;
+	val &= ~0x1000; /* clear 1-wire bit */
+	*(volatile unsigned short *)0xf0400000 = val;
+
+	result = OWTouchReset();
+	if (result != 0) {
+		puts("No 1-wire device detected!\n");
+	}
+
+	OWWriteByte(0x33); /* send read rom command */
+	OWReadByte(); /* skip family code ( == 0x01) */
+	for (i=0; i<6; i++) {
+		ow_id[i] = OWReadByte();
+	}
+	ow_crc = OWReadByte(); /* read crc */
+
+	sprintf(str, "%08X%04X", *(unsigned int *)&ow_id[0], *(unsigned short *)&ow_id[4]);
+	printf("Setting environment variable 'ow_id' to %s\n", str);
+	setenv("ow_id", str);
+
+	return 0;
+}
+U_BOOT_CMD(
+	onewire,	1,	1,	do_onewire,
+	"onewire - Read 1-write ID\n",
+	NULL
+	);
+
+#endif /* CONFIG_CPCI405AB */

board/esd/dp405/Makefile

@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+# Objects for Xilinx JTAG programming (CPLD)
+CPLD    = ../common/xilinx_jtag/lenval.o \
+	  ../common/xilinx_jtag/micro.o \
+	  ../common/xilinx_jtag/ports.o
+
+OBJS	= $(BOARD).o flash.o $(CPLD)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/esd/dp405/config.mk

@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd VOH405 boards
+#
+
+TEXT_BASE = 0xFFFC0000
+#TEXT_BASE = 0x00FC0000

board/esd/dp405/dp405.c

@@ -0,0 +1,143 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+
+
+/* fpga configuration data - not compressed, generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+int filesize = sizeof(fpgadata);
+
+
+int board_pre_init (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(uicer, 0x00000000);       /* disable all ints */
+	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(uicpr, 0xFFFFFF80);       /* set int polarities */
+	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
+	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (epcr, 0xa8400000); /* ebc always driven */
+
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_f (void)
+{
+	return 0;  /* dummy implementation */
+}
+
+
+int misc_init_r (void)
+{
+	/*
+	 * Reset CPLD via GPIO13 (CS4) pin
+	 */
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~(0x80000000 >> 13));
+	udelay(1000); /* wait 1ms */
+	out32(GPIO0_OR, in32(GPIO0_OR) | (0x80000000 >> 13));
+	udelay(1000); /* wait 1ms */
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	unsigned char str[64];
+	int i = getenv_r ("serial#", str, sizeof(str));
+	unsigned char trans[16] = {0x0,0x8,0x4,0xc,0x2,0xa,0x6,0xe,
+                                   0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf};
+	unsigned char id1, id2;
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming DP405");
+	} else {
+		puts(str);
+	}
+
+	id1 = trans[(~(in32(GPIO0_IR) >> 5)) & 0x0000000f];
+	id2 = trans[(~(in32(GPIO0_IR) >> 9)) & 0x0000000f];
+	printf(" (ID=0x%1X%1X)\n", id1, id2);
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	unsigned long val;
+
+	mtdcr(memcfga, mem_mb0cf);
+	val = mfdcr(memcfgd);
+
+#if 0
+	printf("\nmb0cf=%x\n", val); /* test-only */
+	printf("strap=%x\n", mfdcr(strap)); /* test-only */
+#endif
+
+	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: 16 MB - ok\n");
+
+	return (0);
+}

board/esd/dp405/flash.c

@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(ebccfga, pb0cr);
+	pbcr = mfdcr(ebccfgd);
+	mtdcr(ebccfga, pb0cr);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(ebccfgd, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}

board/esd/dp405/u-boot.lds

@@ -0,0 +1,148 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/405gp_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/esd/hub405/Makefile

@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/esd/hub405/config.mk

@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd HUB405 boards
+#
+
+TEXT_BASE = 0xFFFC0000

board/esd/hub405/flash.c

@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(ebccfga, pb0cr);
+	pbcr = mfdcr(ebccfgd);
+	mtdcr(ebccfga, pb0cr);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(ebccfgd, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}

board/esd/hub405/hub405.c

@@ -0,0 +1,166 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+
+/* ------------------------------------------------------------------------- */
+
+
+int board_pre_init (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(uicer, 0x00000000);       /* disable all ints */
+	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(uicpr, 0xFFFFFF9F);       /* set int polarities */
+	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
+	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (epcr, 0xa8400000); /* ebc always driven */
+
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_f (void)
+{
+	return 0;  /* dummy implementation */
+}
+
+
+int misc_init_r (void)
+{
+	volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
+	volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
+	volatile unsigned char *duart2_mcr = (unsigned char *)((ulong)DUART2_BA + 4);
+	volatile unsigned char *duart3_mcr = (unsigned char *)((ulong)DUART3_BA + 4);
+
+	/*
+	 * Reset external DUARTs
+	 */
+	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
+	udelay(10); /* wait 10us */
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Enable interrupts in exar duart mcr[3]
+	 */
+	*duart0_mcr = 0x08;
+	*duart1_mcr = 0x08;
+	*duart2_mcr = 0x08;
+	*duart3_mcr = 0x08;
+
+	/*
+	 * Set NAND-FLASH GPIO signals to default
+	 */
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
+	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	unsigned char str[64];
+	int i = getenv_r ("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming HUB405");
+	} else {
+		puts(str);
+	}
+
+	putc ('\n');
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	unsigned long val;
+
+	mtdcr(memcfga, mem_mb0cf);
+	val = mfdcr(memcfgd);
+
+#if 0
+	printf("\nmb0cf=%x\n", val); /* test-only */
+	printf("strap=%x\n", mfdcr(strap)); /* test-only */
+#endif
+
+	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: 16 MB - ok\n");
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#include <linux/mtd/nand.h>
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+
+void nand_init(void)
+{
+	nand_probe(CFG_NAND_BASE);
+	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
+		print_size(nand_dev_desc[0].totlen, "\n");
+	}
+}
+#endif

board/esd/hub405/u-boot.lds

@@ -0,0 +1,147 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/405gp_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/esd/pci405/cmd_pci405.c

@@ -107,5 +107,10 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 	return 0;
 }
+U_BOOT_CMD(
+	loadpci,	1,	1,	do_loadpci,
+	"loadpci - Wait for pci-image and boot it\n",
+	NULL
+);
 
 #endif

board/esd/plu405/Makefile

@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/esd/plu405/config.mk

@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd PLU405 boards
+#
+
+TEXT_BASE = 0xFFFC0000
+#TEXT_BASE = 0x00FC0000

board/esd/plu405/flash.c

@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(ebccfga, pb0cr);
+	pbcr = mfdcr(ebccfgd);
+	mtdcr(ebccfga, pb0cr);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(ebccfgd, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}

board/esd/plu405/plu405.c

@@ -0,0 +1,268 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+
+/* ------------------------------------------------------------------------- */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
+/* fpga configuration data - gzip compressed and generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+/* Prototypes */
+int gunzip(void *, int, unsigned char *, int *);
+
+
+int board_pre_init (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(uicer, 0x00000000);       /* disable all ints */
+	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(uicpr, 0xFFFFFF99);       /* set int polarities */
+	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
+	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (epcr, 0xa8400000); /* ebc always driven */
+
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_f (void)
+{
+	return 0;  /* dummy implementation */
+}
+
+
+int misc_init_r (void)
+{
+	volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
+	volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
+	unsigned char *dst;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+
+#if 1 /* test-only */
+	dst = malloc(CFG_FPGA_MAX_SIZE);
+	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
+		printf ("GUNZIP ERROR - must RESET board to recover\n");
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i=20; i>0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index=0;index<1000;index++)
+				udelay(1000);
+		}
+		putc ('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index+1]));
+		index += len+3;
+	}
+	putc ('\n');
+
+	free(dst);
+
+	/*
+	 * Reset FPGA via FPGA_DATA pin
+	 */
+	SET_FPGA(FPGA_PRG | FPGA_CLK);
+	udelay(1000); /* wait 1ms */
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Reset external DUARTs
+	 */
+	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
+	udelay(10); /* wait 10us */
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Set NAND-FLASH GPIO signals to default
+	 */
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
+	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
+
+	/*
+	 * Enable interrupts in exar duart mcr[3]
+	 */
+	*duart0_mcr = 0x08;
+	*duart1_mcr = 0x08;
+#endif
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	unsigned char str[64];
+	int i = getenv_r ("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming PLU405");
+	} else {
+		puts(str);
+	}
+
+	putc ('\n');
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	unsigned long val;
+
+	mtdcr(memcfga, mem_mb0cf);
+	val = mfdcr(memcfgd);
+
+#if 0
+	printf("\nmb0cf=%x\n", val); /* test-only */
+	printf("strap=%x\n", mfdcr(strap)); /* test-only */
+#endif
+
+	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: 16 MB - ok\n");
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef CONFIG_IDE_RESET
+void ide_set_reset(int on)
+{
+	volatile unsigned short *fpga_mode =
+		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+
+	/*
+	 * Assert or deassert CompactFlash Reset Pin
+	 */
+	if (on) {		/* assert RESET */
+		*fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
+	} else {		/* release RESET */
+		*fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
+	}
+}
+#endif /* CONFIG_IDE_RESET */
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#include <linux/mtd/nand.h>
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+
+void nand_init(void)
+{
+	nand_probe(CFG_NAND_BASE);
+	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
+		print_size(nand_dev_desc[0].totlen, "\n");
+	}
+}
+#endif

board/esd/plu405/u-boot.lds

@@ -0,0 +1,148 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/405gp_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/esd/pmc405/Makefile

@@ -25,7 +25,12 @@ include $(TOPDIR)/config.mk
 
 LIB	= lib$(BOARD).a
 
-OBJS	= $(BOARD).o strataflash.o
+# Objects for Xilinx JTAG programming (CPLD)
+CPLD    = ../common/xilinx_jtag/lenval.o \
+	  ../common/xilinx_jtag/micro.o \
+	  ../common/xilinx_jtag/ports.o
+
+OBJS	= $(BOARD).o strataflash.o $(CPLD)
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS)

board/esd/pmc405/pmc405.c

@@ -26,11 +26,13 @@
 #include <command.h>
 #include <malloc.h>
 
-/* ------------------------------------------------------------------------- */
 
-
-/* Prototypes */
-int gunzip(void *, int, unsigned char *, int *);
+/* fpga configuration data - not compressed, generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+int filesize = sizeof(fpgadata);
 
 
 int board_pre_init (void)
@@ -74,104 +76,6 @@ int misc_init_f (void)
 
 int misc_init_r (void)
 {
-#if 0 /* test-only */
-	DECLARE_GLOBAL_DATA_PTR;
-	volatile unsigned short *fpga_mode =
-		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
-	volatile unsigned char *duart0_mcr =
-		(unsigned char *)((ulong)DUART0_BA + 4);
-	volatile unsigned char *duart1_mcr =
-		(unsigned char *)((ulong)DUART1_BA + 4);
-	bd_t *bd = gd->bd;
-	char *	tmp;                    /* Temporary char pointer      */
-	unsigned char *dst;
-	ulong len = sizeof(fpgadata);
-	int status;
-	int index;
-	int i;
-	unsigned long cntrl0Reg;
-
-	/*
-	 * Setup GPIO pins (CS6+CS7 as GPIO)
-	 */
-	cntrl0Reg = mfdcr(cntrl0);
-	mtdcr(cntrl0, cntrl0Reg | 0x00300000);
-
-	dst = malloc(CFG_FPGA_MAX_SIZE);
-	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
-		printf ("GUNZIP ERROR - must RESET board to recover\n");
-		do_reset (NULL, 0, 0, NULL);
-	}
-
-	status = fpga_boot(dst, len);
-	if (status != 0) {
-		printf("\nFPGA: Booting failed ");
-		switch (status) {
-		case ERROR_FPGA_PRG_INIT_LOW:
-			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
-			break;
-		case ERROR_FPGA_PRG_INIT_HIGH:
-			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
-			break;
-		case ERROR_FPGA_PRG_DONE:
-			printf("(Timeout: DONE not high after programming FPGA)\n ");
-			break;
-		}
-
-		/* display infos on fpgaimage */
-		index = 15;
-		for (i=0; i<4; i++) {
-			len = dst[index];
-			printf("FPGA: %s\n", &(dst[index+1]));
-			index += len+3;
-		}
-		putc ('\n');
-		/* delayed reboot */
-		for (i=20; i>0; i--) {
-			printf("Rebooting in %2d seconds \r",i);
-			for (index=0;index<1000;index++)
-				udelay(1000);
-		}
-		putc ('\n');
-		do_reset(NULL, 0, 0, NULL);
-	}
-
-	/* restore gpio/cs settings */
-	mtdcr(cntrl0, cntrl0Reg);
-
-	puts("FPGA:  ");
-
-	/* display infos on fpgaimage */
-	index = 15;
-	for (i=0; i<4; i++) {
-		len = dst[index];
-		printf("%s ", &(dst[index+1]));
-		index += len+3;
-	}
-	putc ('\n');
-
-	free(dst);
-
-	/*
-	 * Reset FPGA via FPGA_DATA pin
-	 */
-	SET_FPGA(FPGA_PRG | FPGA_CLK);
-	udelay(1000); /* wait 1ms */
-	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
-	udelay(1000); /* wait 1ms */
-
-	/*
-	 * Enable power on PS/2 interface
-	 */
-	*fpga_mode |= CFG_FPGA_CTRL_PS2_RESET;
-
-	/*
-	 * Enable interrupts in exar duart mcr[3]
-	 */
-	*duart0_mcr = 0x08;
-	*duart1_mcr = 0x08;
-#endif
-
 	return (0);
 }
 
@@ -188,7 +92,7 @@ int checkboard (void)
 	puts ("Board: ");
 
 	if (i == -1) {
-		puts ("### No HW ID - assuming ABG405");
+		puts ("### No HW ID - assuming PMC405");
 	} else {
 		puts(str);
 	}

board/esd/voh405/Makefile

@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/esd/voh405/config.mk

@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd VOH405 boards
+#
+
+TEXT_BASE = 0xFFFC0000
+#TEXT_BASE = 0x00FC0000

board/esd/voh405/flash.c

@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(ebccfga, pb0cr);
+	pbcr = mfdcr(ebccfgd);
+	mtdcr(ebccfga, pb0cr);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(ebccfgd, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}

board/esd/voh405/u-boot.lds

@@ -0,0 +1,148 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/405gp_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/esd/voh405/voh405.c

@@ -0,0 +1,273 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+
+/* ------------------------------------------------------------------------- */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
+/* fpga configuration data - gzip compressed and generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+/* Prototypes */
+int gunzip(void *, int, unsigned char *, int *);
+
+
+int board_pre_init (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(uicer, 0x00000000);       /* disable all ints */
+	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(uicpr, 0xFFFFFFB5);       /* set int polarities */
+	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
+	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (epcr, 0xa8400000); /* ebc always driven */
+
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_f (void)
+{
+	return 0;  /* dummy implementation */
+}
+
+
+int misc_init_r (void)
+{
+	volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
+	volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
+	volatile unsigned short *lcd_reg =
+		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4);
+	unsigned char *dst;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+
+	dst = malloc(CFG_FPGA_MAX_SIZE);
+	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
+		printf ("GUNZIP ERROR - must RESET board to recover\n");
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i=20; i>0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index=0;index<1000;index++)
+				udelay(1000);
+		}
+		putc ('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index+1]));
+		index += len+3;
+	}
+	putc ('\n');
+
+	free(dst);
+
+	/*
+	 * Reset FPGA via FPGA_DATA pin
+	 */
+	SET_FPGA(FPGA_PRG | FPGA_CLK);
+	udelay(1000); /* wait 1ms */
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Reset external DUARTs
+	 */
+	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
+	udelay(10); /* wait 10us */
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Set NAND-FLASH GPIO signals to default
+	 */
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
+	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
+
+	/*
+	 * Enable interrupts in exar duart mcr[3]
+	 */
+	*duart0_mcr = 0x08;
+	*duart1_mcr = 0x08;
+
+	/*
+	 * Set default contrast voltage on epson vga controller
+	 */
+	*lcd_reg = 0x4848;
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	unsigned char str[64];
+	int i = getenv_r ("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming VOH405");
+	} else {
+		puts(str);
+	}
+
+	putc ('\n');
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	unsigned long val;
+
+	mtdcr(memcfga, mem_mb0cf);
+	val = mfdcr(memcfgd);
+
+#if 0
+	printf("\nmb0cf=%x\n", val); /* test-only */
+	printf("strap=%x\n", mfdcr(strap)); /* test-only */
+#endif
+
+	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: 16 MB - ok\n");
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef CONFIG_IDE_RESET
+void ide_set_reset(int on)
+{
+	volatile unsigned short *fpga_mode =
+		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+
+	/*
+	 * Assert or deassert CompactFlash Reset Pin
+	 */
+	if (on) {		/* assert RESET */
+		*fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
+	} else {		/* release RESET */
+		*fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
+	}
+}
+#endif /* CONFIG_IDE_RESET */
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#include <linux/mtd/nand.h>
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+
+void nand_init(void)
+{
+	nand_probe(CFG_NAND_BASE);
+	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
+		print_size(nand_dev_desc[0].totlen, "\n");
+	}
+}
+#endif

board/impa7/flash.c

@@ -53,7 +53,7 @@ ulong flash_init(void)
 	else if (i == 1)
 	  flashbase = PHYS_FLASH_2;
 	else
-	  panic("configured to many flash banks!\n");
+	  panic("configured too many flash banks!\n");
 	for (j = 0; j < flash_info[i].sector_count; j++)
 	{
 	    if (j <= 7)

board/innokom/flash.c

@@ -276,7 +276,7 @@ ulong flash_init(void)
 				flashbase = PHYS_FLASH_1;
 				break;
 			default:
-				panic("configured to many flash banks!\n");
+				panic("configured too many flash banks!\n");
 				break;
 		}
 		for (j = 0; j < flash_info[i].sector_count; j++) {

board/lart/flash.c

@@ -86,7 +86,7 @@ ulong flash_init(void)
 	if (i == 0)
 	  flashbase = PHYS_FLASH_1;
 	else
-	  panic("configured to many flash banks!\n");
+	  panic("configured too many flash banks!\n");
 	for (j = 0; j < flash_info[i].sector_count; j++)
 	{
 	    if (j <= 7)

board/logodl/flash.c

@@ -91,7 +91,7 @@ ulong flash_init(void)
 		flashbase = PHYS_FLASH_2;
 		break;
 	   default:
-		panic("configured to many flash banks!\n");
+		panic("configured too many flash banks!\n");
 		break;
 	}
 	for (j = 0; j < flash_info[i].sector_count; j++)

board/lubbock/flash.c

@@ -76,7 +76,7 @@ unsigned long flash_init (void)
 			flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
 			break;
 		default:
-			panic ("configured to many flash banks!\n");
+			panic ("configured too many flash banks!\n");
 			break;
 		}
 		size += flash_info[i].size;

board/ml2/flash.c

@@ -72,7 +72,7 @@ ulong flash_init(void) {
 		if (i==0)
 			flashbase = CFG_FLASH_BASE;
 		else
-			panic("configured to many flash banks!\n");
+			panic("configured too many flash banks!\n");
 		for (j = 0; j < flash_info[i].sector_count; j++)
 				flash_info[i].start[j]=flashbase + j * SECT_SIZE;
 

board/mpc8260ads/mpc8260ads.c

@@ -238,7 +238,9 @@ int board_pre_init (void)
 
 long int initdram (int board_type)
 {
+#if CONFIG_ADSTYPE == CFG_PQ2FADS
 	vu_long *bcsr = (vu_long *)CFG_BCSR;
+#endif
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 	volatile uchar *ramaddr, c = 0xff;

board/mpc8266ads/mpc8266ads.c

@@ -46,7 +46,7 @@
  *   PSDMR_BUFCMD adds a clock
  *   0            no extra clock
  */
-#define CONFIG_PBI		PSDMR_PBI
+#define CONFIG_PBI		0
 #define PESSIMISTIC_SDRAM	0
 #define EAMUX			0	/* EST requires EAMUX */
 #define BUFCMD			0
@@ -427,7 +427,7 @@ long int initdram(int board_type)
     bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
     sda10 = sdam + 2;
 #else
-    sdam = cols - 6;
+    sdam = cols + banks - 8;
     bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
     sda10 = sdam;
 #endif
@@ -557,9 +557,18 @@ long int initdram(int board_type)
 	printf("SDRAM configuration read from SPD\n");
 	printf("\tSize per side = %dMB\n", sdram_size >> 20);
 	printf("\tOrganization: %d sides, %d banks, %d Columns, %d Rows, Data width = %d bits\n", chipselects, 1<<(banks), cols, rows, data_width);
-	printf("\tRefresh rate = %d, CAS latency = %d\n", psrt, caslatency);
+	printf("\tRefresh rate = %d, CAS latency = %d", psrt, caslatency);
+#if(CONFIG_PBI == 0)	/* bank-based interleaving */
+    printf(", Using Bank Based Interleave\n");
+#else
+    printf(", Using Page Based Interleave\n");
+#endif    
 	printf("\tTotal size: ");
 
+    /* this delay only needed for original 16MB DIMM... 
+     * Not needed for any other memory configuration */
+    if ((sdram_size * chipselects) == (16 *1024 *1024))
+        udelay (250000);
     return (sdram_size * chipselects);
 	/*return (16 * 1024 * 1024);*/
 }
@@ -575,3 +584,4 @@ void pci_init_board(void)
 	pci_mpc8250_init(&hose);
 }
 #endif
+

board/mpl/common/common_util.c

@@ -375,138 +375,6 @@ void show_stdio_dev(void)
 	}
 }
 
-/* ------------------------------------------------------------------------- */
-
-	/* switches the cs0 and the cs1 to the locations.
-	   When boot is TRUE, the the mapping is switched
-	   to the boot configuration, If it is FALSE, the
-	   flash will be switched in the boot area */
-
-#undef SW_CS_DBG
-#ifdef SW_CS_DBG
-#define	SW_CS_PRINTF(fmt,args...)	printf (fmt ,##args)
-#else
-#define SW_CS_PRINTF(fmt,args...)
-#endif
-
-#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405)
-int switch_cs(unsigned char boot)
-{
-	unsigned long pbcr;
-	int mode;
-
-	mode=get_boot_mode();
-	mtdcr(ebccfga, pb0cr);
-	pbcr = mfdcr (ebccfgd);
-	if (mode & BOOT_MPS) {
-		/* Boot width = 8 bit MPS Boot, set up MPS on CS0 */
-		/* we need only to switch if boot from MPS */
-		/* printf(" MPS boot mode detected. ");*/
-		/* printf("cs0 cfg: %lx\n",pbcr); */
-		if(boot) {
-			/* switch to boot configuration */
-			/* this is a 8bit boot, switch cs0 to flash location */
-			SW_CS_PRINTF("switch to boot mode (MPS on High address\n");
-			pbcr&=0x000FFFFF; /*mask base address of the cs0 */
-			pbcr|=(FLASH_BASE0_PRELIM & 0xFFF00000);
-			mtdcr(ebccfga, pb0cr);
-			mtdcr(ebccfgd, pbcr);
-			SW_CS_PRINTF("  new cs0 cfg: %lx\n",pbcr);
-			mtdcr(ebccfga, pb1cr); /* get cs1 config reg (flash) */
-			pbcr = mfdcr(ebccfgd);
-			SW_CS_PRINTF(" old cs1 cfg: %lx\n",pbcr);
-			pbcr&=0x000FFFFF; /*mask base address of the cs1 */
-			pbcr|=(MULTI_PURPOSE_SOCKET_ADDR & 0xFFF00000);
-			mtdcr(ebccfga, pb1cr);
-			mtdcr(ebccfgd, pbcr);
-			SW_CS_PRINTF("  new cs1 cfg: %lx, MPS is on High Address\n",pbcr);
-		}
-		else {
-			/* map flash to boot area, */
-			SW_CS_PRINTF("map Flash to boot area\n");
-			pbcr&=0x000FFFFF; /*mask base address of the cs0 */
-			pbcr|=(MULTI_PURPOSE_SOCKET_ADDR & 0xFFF00000);
-			mtdcr(ebccfga, pb0cr);
-			mtdcr(ebccfgd, pbcr);
-			SW_CS_PRINTF("  new cs0 cfg: %lx\n",pbcr);
-			mtdcr(ebccfga, pb1cr); /* get cs1 config reg (flash) */
-			pbcr = mfdcr(ebccfgd);
-			SW_CS_PRINTF("  cs1 cfg: %lx\n",pbcr);
-			pbcr&=0x000FFFFF; /*mask base address of the cs1 */
-			pbcr|=(FLASH_BASE0_PRELIM & 0xFFF00000);
-			mtdcr(ebccfga, pb1cr);
-			mtdcr(ebccfgd, pbcr);
-			SW_CS_PRINTF("  new cs1 cfg: %lx Flash is on High Address\n",pbcr);
-		}
-		return 1;
-	}
-	else {
-		SW_CS_PRINTF("Normal boot, no switching necessary\n");
-		return 0;
-	}
-
-}
-
-int get_boot_mode(void)
-{
-	unsigned long pbcr;
-	int res = 0;
-	pbcr = mfdcr (strap);
-	if ((pbcr & PSR_ROM_WIDTH_MASK) == 0)
-		/* boot via MPS or MPS mapping */
-		res = BOOT_MPS;
-	if(pbcr & PSR_ROM_LOC)
-		/* boot via PCI.. */
-		res |= BOOT_PCI;
-	 return res;
-}
-
-/* Setup cs0 parameter finally.
-   Map the flash high (in boot area)
-   This code can only be executed from SDRAM (after relocation).
-*/
-void setup_cs_reloc(void)
-{
-	unsigned long pbcr;
-	/* Since we are relocated, we can set-up the CS finaly
-	 * but first of all, switch off PCI mapping (in case it was a PCI boot) */
-	out32r(PMM0MA,0L);
-	icache_enable (); /* we are relocated */
-	/* for PCI Boot, we have to set-up the remaining CS correctly */
-	pbcr = mfdcr (strap);
-	if(pbcr & PSR_ROM_LOC) {
-		/* boot via PCI.. */
-		if ((pbcr & PSR_ROM_WIDTH_MASK) == 0) {
-		/* Boot width = 8 bit MPS Boot, set up MPS on CS0 */
-			#ifdef DEBUG
-			printf("Mapping MPS to CS0 @ 0x%lx\n",(MPS_CR_B & 0xfff00000));
-			#endif
-			mtdcr (ebccfga, pb0ap);
-			mtdcr (ebccfgd, MPS_AP);
-			mtdcr (ebccfga, pb0cr);
-			mtdcr (ebccfgd, MPS_CR_B);
-		}
-		else {
-			/* Flash boot, set up the Flash on CS0 */
-			#ifdef DEBUG
-			printf("Mapping Flash to CS0 @ 0x%lx\n",(FLASH_CR_B & 0xfff00000));
-			#endif
-			mtdcr (ebccfga, pb0ap);
-			mtdcr (ebccfgd, FLASH_AP);
-			mtdcr (ebccfga, pb0cr);
-			mtdcr (ebccfgd, FLASH_CR_B);
-		}
-	}
-	switch_cs(0); /* map Flash High */
-}
-
-
-#elif defined(CONFIG_VCMA9)
-int switch_cs(unsigned char boot)
-{
-    return 0;
-}
-#endif /* CONFIG_VCMA9 */
 
 int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
@@ -625,6 +493,7 @@ void doc_init (void)
 
 #ifdef CONFIG_CONSOLE_EXTRA_INFO
 extern GraphicDevice ctfb;
+extern int get_boot_mode(void);
 
 void video_get_info_str (int line_number, char *info)
 {

board/mpl/common/common_util.h

@@ -31,10 +31,8 @@ typedef struct {
 } backup_t;
 
 void get_backup_values(backup_t *buf);
-int switch_cs(unsigned char boot);
+
 #if defined(CONFIG_PIP405) || defined(CONFIG_MIP405)
-int get_boot_mode(void);
-void setup_cs_reloc(void);
 #define BOOT_MPS	0x01
 #define BOOT_PCI	0x02
 #endif

board/mpl/common/flash.c

@@ -39,6 +39,13 @@
 #include <ppc4xx.h>
 #include <asm/processor.h>
 #include "common_util.h"
+#if defined(CONFIG_MIP405)
+#include "../mip405/mip405.h"
+#endif
+#if defined(CONFIG_PIP405)
+#include "../pip405/pip405.h"
+#endif
+#include <405gp_pci.h>
 
 flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 /*-----------------------------------------------------------------------
@@ -66,23 +73,102 @@ void unlock_intel_sectors(flash_info_t *info,ulong addr,ulong cnt);
 #define TRUE            1
 
 /*-----------------------------------------------------------------------
+ * Some CS switching routines:
+ *
+ * On PIP/MIP405 we have 3 (4) possible boot mode
+ *
+ * - Boot from Flash (Flash CS = CS0, MPS CS = CS1)
+ * - Boot from MPS   (Flash CS = CS1, MPS CS = CS0)
+ * - Boot from PCI with Flash map (Flash CS = CS0, MPS CS = CS1)
+ * - Boot from PCI with MPS map   (Flash CS = CS1, MPS CS = CS0)
+ * The flash init is the first board specific routine which is called
+ * after code relocation (running from SDRAM)
+ * The first thing we do is to map the Flash CS to the Flash area and
+ * the MPS CS to the MPS area. Since the flash size is unknown at this
+ * point, we use the max flash size and the lowest flash address as base.
+ * 
+ * After flash detection we adjust the size of the CS area accordingly.
+ * The board_init_r will fill in wrong values in the board init structure,
+ * but this will be fixed in the misc_init_r routine:
+ * bd->bi_flashstart=0-flash_info[0].size
+ * bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN
+ * bd->bi_flashoffset=0
+ * 
  */
+int get_boot_mode(void)
+{
+	unsigned long pbcr;
+	int res = 0;
+	pbcr = mfdcr (strap);
+	if ((pbcr & PSR_ROM_WIDTH_MASK) == 0)
+		/* boot via MPS or MPS mapping */
+		res = BOOT_MPS;
+	if(pbcr & PSR_ROM_LOC)
+		/* boot via PCI.. */
+		res |= BOOT_PCI;
+	 return res;
+}
+
+/* Map the flash high (in boot area)
+   This code can only be executed from SDRAM (after relocation).
+*/
+void setup_cs_reloc(void)
+{
+	int mode;
+	/* Since we are relocated, we can set-up the CS finaly
+	 * but first of all, switch off PCI mapping (in case it was a PCI boot) */
+	out32r(PMM0MA,0L);
+	icache_enable (); /* we are relocated */
+	/* get boot mode */
+	mode=get_boot_mode();
+	/* we map the flash high in every case */
+	/* first findout on which cs the flash is */
+	if(mode & BOOT_MPS) {
+		/* map flash high on CS1 and MPS on CS0 */
+		mtdcr (ebccfga, pb0ap);
+		mtdcr (ebccfgd, MPS_AP);
+		mtdcr (ebccfga, pb0cr);
+		mtdcr (ebccfgd, MPS_CR);
+		/* we use the default values (max values) for the flash
+		 * because its real size is not yet known */
+		mtdcr (ebccfga, pb1ap);
+		mtdcr (ebccfgd, FLASH_AP);
+		mtdcr (ebccfga, pb1cr);
+		mtdcr (ebccfgd, FLASH_CR_B);
+	}
+	else {
+		/* map flash high on CS0 and MPS on CS1 */
+		mtdcr (ebccfga, pb1ap);
+		mtdcr (ebccfgd, MPS_AP);
+		mtdcr (ebccfga, pb1cr);
+		mtdcr (ebccfgd, MPS_CR);
+		/* we use the default values (max values) for the flash
+		 * because its real size is not yet known */
+		mtdcr (ebccfga, pb0ap);
+		mtdcr (ebccfgd, FLASH_AP);
+		mtdcr (ebccfga, pb0cr);
+		mtdcr (ebccfgd, FLASH_CR_B);
+	}
+}
+
 
 
 unsigned long flash_init (void)
 {
-	unsigned long size_b0, size_b1;
-	int i;
+	unsigned long size_b0, size_b1,flashcr;
+	int mode, i;
+	extern char version_string;
+	char *p=&version_string;
 
 	/* Since we are relocated, we can set-up the CS finally */
 	setup_cs_reloc();
 	/* get and display boot mode */
-	i=get_boot_mode();
-	if(i & BOOT_PCI)
-		printf("(PCI Boot %s Map) ",(i & BOOT_MPS) ?
+	mode=get_boot_mode();
+	if(mode & BOOT_PCI)
+		printf("(PCI Boot %s Map) ",(mode & BOOT_MPS) ?
 			"MPS" : "Flash");
 	else
-		printf("(%s Boot) ",(i & BOOT_MPS) ?
+		printf("(%s Boot) ",(mode & BOOT_MPS) ?
 			"MPS" : "Flash");
 	/* Init: no FLASHes known */
 	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
@@ -91,7 +177,7 @@ unsigned long flash_init (void)
 
 	/* Static FLASH Bank configuration here - FIXME XXX */
 
-	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+	size_b0 = flash_get_size((vu_long *)CFG_MONITOR_BASE, &flash_info[0]);
 
 	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
 		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
@@ -109,8 +195,31 @@ unsigned long flash_init (void)
 	flash_info[0].protect[flash_info[0].sector_count-1] = 1;
 	size_b1 = 0 ;
 	flash_info[0].size = size_b0;
+	/* set up flash cs according to the size */
+	if(mode & BOOT_MPS) {
+		/* flash is on CS1 */
+		mtdcr(ebccfga, pb1cr);
+		flashcr = mfdcr (ebccfgd);
+		/* we map the flash high in every case */
+		flashcr&=0x0001FFFF; /* mask out address bits */
+		flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */
+		flashcr|= (((flash_info[0].size >>21) & 0x07) << 17); /* size addr */
+		mtdcr(ebccfga, pb1cr);
+		mtdcr(ebccfgd, flashcr);
+	}
+	else {
+		/* flash is on CS0 */
+		mtdcr(ebccfga, pb0cr);
+		flashcr = mfdcr (ebccfgd);
+		/* we map the flash high in every case */
+		flashcr&=0x0001FFFF; /* mask out address bits */
+		flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */
+		flashcr|= (((flash_info[0].size >>21) & 0x07) << 17); /* size addr */
+		mtdcr(ebccfga, pb0cr);
+		mtdcr(ebccfgd, flashcr);
+	}
 #if 0
-	/* include this if you want to test if
+	/* enable this if you want to test if
 	   the relocation has be done ok.
 	   This will disable both Chipselects */
 	mtdcr (ebccfga, pb0cr);
@@ -119,6 +228,14 @@ unsigned long flash_init (void)
 	mtdcr (ebccfgd, 0L);
 	printf("CS0 & CS1 switched off for test\n");
 #endif
+	/* patch version_string */
+	for(i=0;i<0x100;i++) {
+		if(*p=='\n') {
+			*p=0;
+			break;
+		}
+		p++;
+	}
 	return (size_b0);
 }
 
@@ -171,6 +288,8 @@ void flash_print_info  (flash_info_t *info)
 				break;
 	case FLASH_INTEL320T:	printf ("TE28F320C3 (32 Mbit, top sector size)\n");
 				break;
+	case FLASH_AM640U:	printf ("AM29LV640U (64 Mbit, uniform sector size)\n");
+				break;
 	default:		printf ("Unknown Chip Type\n");
 				break;
 	}
@@ -211,7 +330,8 @@ void flash_print_info  (flash_info_t *info)
 
 
 /*-----------------------------------------------------------------------
- */
+ 
+*/
 
 /*
  * The following code cannot be run from FLASH!
@@ -220,7 +340,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 {
 	short i;
 	FLASH_WORD_SIZE value;
-	ulong base = (ulong)addr;
+	ulong base;
 	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
 
 	/* Write auto select command: read Manufacturer ID */
@@ -250,7 +370,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		return (0);			/* no or unknown flash	*/
 	}
 	value = addr2[1];			/* device ID		*/
-	/*	printf("Device value %x\n",value); */
+	/*	printf("Device value %x\n",value); 		    */
 	switch (value) {
 	case (FLASH_WORD_SIZE)AMD_ID_F040B:
 		info->flash_id += FLASH_AM040;
@@ -292,12 +412,17 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		info->sector_count = 35;
 		info->size = 0x00200000;
 		break;				/* => 2 MB		*/
-#if 0	/* enable when device IDs are available */
 	case (FLASH_WORD_SIZE)AMD_ID_LV320T:
 		info->flash_id += FLASH_AM320T;
 		info->sector_count = 67;
 		info->size = 0x00400000;
 		break;				/* => 4 MB		*/
+	case (FLASH_WORD_SIZE)AMD_ID_LV640U:
+		info->flash_id += FLASH_AM640U;
+		info->sector_count = 128;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+#if 0	/* enable when device IDs are available */
 
 	case (FLASH_WORD_SIZE)AMD_ID_LV320B:
 		info->flash_id += FLASH_AM320B;
@@ -328,10 +453,12 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		return (0);			/* => no or unknown flash */
 
 	}
-
+	/* base address calculation */
+	base=0-info->size;
 	/* set up sector start address table */
 	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
-	     (info->flash_id  == FLASH_AM040)){
+	     (info->flash_id  == FLASH_AM040) ||
+	     (info->flash_id  == FLASH_AM640U)){
 		for (i = 0; i < info->sector_count; i++)
 			info->start[i] = base + (i * 0x00010000);
 	}

board/mpl/common/isa.c

@@ -32,7 +32,6 @@
 #include "kbd.h"
 #include "video.h"
 
-extern int drv_isa_kbd_init (void);
 
 #undef	ISA_DEBUG
 
@@ -49,6 +48,9 @@ extern int drv_isa_kbd_init (void);
 #define FALSE           0
 #endif
 
+#if defined(CONFIG_PIP405)
+
+extern int drv_isa_kbd_init (void);
 
 /* fdc (logical device 0) */
 const SIO_LOGDEV_TABLE sio_fdc[] = {
@@ -183,7 +185,7 @@ void isa_sio_setup(void)
 		close_cfg_super_IO(0x3F0);
 	}
 }
-
+#endif
 
 /******************************************************************************
  * IRQ Controller
@@ -202,7 +204,7 @@ static struct isa_irq_action isa_irqs[16];
 /*
  * This contains the irq mask for both 8259A irq controllers,
  */
-static unsigned int cached_irq_mask = 0xffff;
+static unsigned int cached_irq_mask = 0xfff9;
 
 #define cached_imr1	(unsigned char)cached_irq_mask
 #define cached_imr2	(unsigned char)(cached_irq_mask>>8)
@@ -387,19 +389,22 @@ int handle_isa_int(void)
 	isr2=in8(ISR_2);
 	isr1=in8(ISR_1);
 	irq=(unsigned char)irqack;
-	if((irq==7)&&((isr1&0x80)==0)) {
+	irq-=32;
+/*	if((irq==7)&&((isr1&0x80)==0)) {
 		PRINTF("IRQ7 detected but not in ISR\n");
 	}
 	else {
-		/* we should handle cascaded interrupts here also */
-		/* printf("ISA Irq %d\n",irq); */
-		isa_irqs[irq].count++;
-	if (isa_irqs[irq].handler != NULL)
-		(*isa_irqs[irq].handler)(isa_irqs[irq].arg);      /* call isr */
-	else
+*/		/* we should handle cascaded interrupts here also */
 	{
-	PRINTF ("bogus interrupt vector 0x%x\n", irq);
-	}
+/*		printf("ISA Irq %d\n",irq); */
+		isa_irqs[irq].count++;
+		if(irq!=2) { /* just swallow the cascade irq 2 */
+			if (isa_irqs[irq].handler != NULL)
+				(*isa_irqs[irq].handler)(isa_irqs[irq].arg);      /* call isr */
+			else {
+				PRINTF ("bogus interrupt vector 0x%x\n", irq);
+			}
+		}
 	}
 	/* issue EOI instruction to clear the IRQ */
 	mask_and_ack_8259A(irq);
@@ -413,13 +418,13 @@ int handle_isa_int(void)
 
 void isa_irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
 {
-  if (isa_irqs[vec].handler != NULL) {
-   printf ("ISA Interrupt vector %d: handler 0x%x replacing 0x%x\n",
-	   vec, (uint)handler, (uint)isa_irqs[vec].handler);
-  }
-  isa_irqs[vec].handler = handler;
-  isa_irqs[vec].arg     = arg;
-  enable_8259A_irq(vec);
+	if (isa_irqs[vec].handler != NULL) {
+		printf ("ISA Interrupt vector %d: handler 0x%x replacing 0x%x\n",
+			vec, (uint)handler, (uint)isa_irqs[vec].handler);
+	}
+	isa_irqs[vec].handler = handler;
+	isa_irqs[vec].arg     = arg;
+	enable_8259A_irq(vec);
 	PRINTF ("Install ISA IRQ %d ==> %p, @ %p mask=%04x\n", vec, handler, &isa_irqs[vec].handler,cached_irq_mask);
 
 }
@@ -427,9 +432,9 @@ void isa_irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
 void isa_irq_free_handler(int vec)
 {
 	disable_8259A_irq(vec);
-  isa_irqs[vec].handler = NULL;
-  isa_irqs[vec].arg     = NULL;
-	printf ("Free ISA IRQ %d mask=%04x\n", vec, cached_irq_mask);
+	isa_irqs[vec].handler = NULL;
+	isa_irqs[vec].arg     = NULL;
+	PRINTF ("Free ISA IRQ %d mask=%04x\n", vec, cached_irq_mask);
 
 }
 
@@ -448,16 +453,42 @@ void isa_init_irq_contr(void)
 	init_8259A();
 	out8(IMR_2,0xFF);
 }
+/*************************************************************************/
 
+void isa_show_irq(void)
+{
+	int vec;
+
+	printf ("\nISA Interrupt-Information:\n");
+	printf ("Nr  Routine   Arg       Count\n");
+
+	for (vec=0; vec<16; vec++) {
+		if (isa_irqs[vec].handler != NULL) {
+			printf ("%02d  %08lx  %08lx  %d\n",
+				vec,
+				(ulong)isa_irqs[vec].handler,
+				(ulong)isa_irqs[vec].arg,
+				isa_irqs[vec].count);
+		}
+	}
+}
+
+int isa_irq_get_count(int vec)
+{
+	return(isa_irqs[vec].count);
+}
 
 /******************************************************************
  * Init the ISA bus and devices.
  */
 
+#if defined(CONFIG_PIP405)
 
 int isa_init(void)
 {
 	isa_sio_setup();
+	isa_init_irq_contr();
 	drv_isa_kbd_init();
 	return 0;
 }
+#endif

board/mpl/common/isa.h

@@ -21,12 +21,12 @@
  * MA 02111-1307 USA
  */
 
-#ifndef _PIP405_ISA_H_
-#define _PIP405_ISA_H_
+#ifndef _ISA_H_
+#define _ISA_H_
 /* Super IO */
 #define SIO_CFG_PORT	0x3F0	/* Config Port Address */
 
-
+#if defined(CONFIG_PIP405)
 /* table fore SIO initialization */
 typedef struct {
 	const uchar index;
@@ -44,10 +44,14 @@ unsigned char read_cfg_super_IO(int address, unsigned char function, unsigned ch
 void write_cfg_super_IO(int address, unsigned char function, unsigned char regaddr, unsigned char data);
 void close_cfg_super_IO(int address);
 void isa_sio_setup(void);
-void isa_sio_setup(void);
+#endif
+
 void isa_irq_install_handler(int vec, interrupt_handler_t *handler, void *arg);
 void isa_irq_free_handler(int vec);
 int handle_isa_int(void);
+void isa_init_irq_contr(void);
+void isa_show_irq(void);
+int isa_irq_get_count(int vec);
 
 
 #endif

board/mpl/common/pci_parts.h

@@ -92,7 +92,7 @@ extern void pci_pip405_write_regs(struct pci_controller *,
 /* PIIX4 ISA Bridge Function 0 */
 static struct pci_pip405_config_entry piix4_isa_bridge_f0[] = {
 	{PCI_CFG_PIIX4_SERIRQ,	0xD0,		1}, /* enable Continous SERIRQ Pin */
-	{PCI_CFG_PIIX4_GENCFG,	0x00010041,	4}, /* enable SERIRQs, ISA, PNP	*/
+	{PCI_CFG_PIIX4_GENCFG,	0x00018041,	4}, /* enable SERIRQs, ISA, PNP, GPI11 */
 	{PCI_CFG_PIIX4_TOM,	0xFE,		1}, /* Top of Memory		*/
 	{PCI_CFG_PIIX4_XBCS,	0x02C4,		2}, /* disable all peri CS	*/
 	{PCI_CFG_PIIX4_RTCCFG,	0x21,		1}, /* enable RTC	   	*/
@@ -106,6 +106,7 @@ static struct pci_pip405_config_entry piix4_isa_bridge_f0[] = {
 
 /* PIIX4 IDE Controller Function 1 */
 static struct pci_pip405_config_entry piix4_ide_cntrl_f1[] = {
+	{PCI_CFG_PIIX4_BMIBA,	0x0001000,	4}, /* set BMI to a valid address */
 	{PCI_COMMAND,		0x0001,		2}, /* enable IO access 	*/
 #if !defined(CONFIG_MIP405T)
 	{PCI_CFG_PIIX4_IDETIM,	0x80008000,	4}, /* enable Both IDE channels	*/
@@ -129,10 +130,10 @@ static struct pci_pip405_config_entry piix4_usb_cntrl_f2[] = {
 
 /* PIIX4 Power Management Function 3 */
 static struct pci_pip405_config_entry piix4_pmm_cntrl_f3[] = {
-	{PCI_COMMAND,		0x0001,		2}, /* enable IO access 	*/
-	{PCI_CFG_PIIX4_PMAB,	0x00004000,	4}, /* set PMBA to "valid" value */
-	{PCI_CFG_PIIX4_PMMISC,	0x01,		1}, /* enable PMBA IO access	*/
+	{PCI_CFG_PIIX4_PMBA,	0x00004000,	4}, /* set PMBA to "valid" value */
 	{PCI_CFG_PIIX4_SMBBA,	0x00005000,	4}, /* set SMBBA to "valid" value */
+	{PCI_CFG_PIIX4_PMMISC,	0x01,		1}, /* enable PMBA IO access	*/
+	{PCI_COMMAND,		0x0001,		2}, /* enable IO access 	*/
 	{ }					    /* end of device table 	*/
 };
 /* PPC405 Dummy only used to prevent autosetup on this host bridge */

board/mpl/common/piix4_pci.h

@@ -143,7 +143,7 @@
 #define	PCI_CFG_PIIX4_LEGSUP	0xC0
 
 /* Function 3 Power Management */
-#define	PCI_CFG_PIIX4_PMAB		0x40
+#define	PCI_CFG_PIIX4_PMBA		0x40
 #define	PCI_CFG_PIIX4_CNTA		0x44
 #define	PCI_CFG_PIIX4_CNTB		0x48
 #define	PCI_CFG_PIIX4_GPICTL	0x4C

board/mpl/mip405/cmd_mip405.c

@@ -54,10 +54,13 @@ int do_mip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return (do_mplcommon(cmdtp, flag, argc, argv));
 }
 U_BOOT_CMD(
-	mip405,	6,	1,	do_mip405,
+	mip405,	8,	1,	do_mip405,
 	"mip405  - MIP405 specific Cmds\n",
 	"flash mem [SrcAddr] - updates U-Boot with image in memory\n"
 	"mip405 flash mps - updates U-Boot with image from MPS\n"
+	"mip405 info      - displays board information\n"
+	"mip405 led <on>  - switches LED on (on=1) or off (on=0)\n"
+	"mip405 mem [cnt] - Memory Test <cnt>-times, <cnt> = -1 loop forever\n"
 );
 
 /* ------------------------------------------------------------------------- */

board/mpl/mip405/init.S

@@ -87,19 +87,15 @@ ext_bus_cntlr_init:
 	mfdcr		r4,ebccfgd
 
 	andi.		r0, r4, 0x2000			/* mask out irrelevant bits */
-	beq			0f						/* jump if 8 bit bus width */
+	beq		0f				/* jump if 8 bit bus width */
 
-	/* setup 16 bit things (Flash Boot)
+	/* setup 16 bit things
    *-----------------------------------------------------------------------
    * Memory Bank 0 (16 Bit Flash) initialization
    *---------------------------------------------------------------------- */
 
 	addi    r4,0,pb0ap
 	mtdcr   ebccfga,r4
-/*	addis   r4,0,0xFF8F */
-/*	ori     r4,r4,0xFE80 */
-/*	addis   r4,0,0x9B01 */
-/*	ori     r4,r4,0x5480 */
 	addis   r4,0,(FLASH_AP_B)@h
 	ori     r4,r4,(FLASH_AP_B)@l
 	mtdcr   ebccfgd,r4
@@ -107,8 +103,6 @@ ext_bus_cntlr_init:
 	addi    r4,0,pb0cr
 	mtdcr   ebccfga,r4
 	/* BS=0x010(4MB),BU=0x3(R/W), */
-/*	addis   r4,0,((FLASH_BASE0_PRELIM & 0xFFF00000) | 0x00050000)@h */
-/*	ori     r4,r4,0xA000          / * BW=0x01(16 bits) */
 	addis   r4,0,(FLASH_CR_B)@h
 	ori     r4,r4,(FLASH_CR_B)@l
 	mtdcr   ebccfgd,r4
@@ -123,21 +117,13 @@ ext_bus_cntlr_init:
 	/* 0x7F8FFE80 slowest boot */
 	addi    r4,0,pb0ap
 	mtdcr   ebccfga,r4
-#if 0
-	addis   r4,0,0x9B01
-	ori     r4,r4,0x5480
-#else
 	addis   r4,0,(MPS_AP_B)@h
 	ori     r4,r4,(MPS_AP_B)@l
-#endif
 	mtdcr   ebccfgd,r4
 
 	addi    r4,0,pb0cr
 	mtdcr   ebccfga,r4
 	/* BS=0x010(4MB),BU=0x3(R/W), */
-/*	addis   r4,0,((FLASH_BASE0_PRELIM & 0xFFF00000) | 0x00050000)@h */
-/*	ori     r4,r4,0x8000          / * BW=0x0( 8 bits) */
-
 	addis   r4,0,(MPS_CR_B)@h
 	ori     r4,r4,(MPS_CR_B)@l
 
@@ -178,18 +164,18 @@ ext_bus_cntlr_init:
   ori     r4,r4,0x0000
   mtdcr   ebccfgd,r4
 
-	addi    r4,0,pb6cr
+  addi    r4,0,pb6cr
   mtdcr   ebccfga,r4
   addis   r4,0,0x0000
   ori     r4,r4,0x0000
   mtdcr   ebccfgd,r4
 
-	addi    r4,0,pb7cr
+  addi    r4,0,pb7cr
   mtdcr   ebccfga,r4
   addis   r4,0,0x0000
   ori     r4,r4,0x0000
   mtdcr   ebccfgd,r4
-	nop				/* pass2 DCR errata #8 */
+  nop				/* pass2 DCR errata #8 */
   blr
 
 /*-----------------------------------------------------------------------------

board/mpl/mip405/mip405.c

@@ -667,9 +667,16 @@ static int test_dram (unsigned long ramsize)
 /* used to check if the time in RTC is valid */
 static unsigned long start;
 static struct rtc_time tm;
+extern flash_info_t flash_info[];	/* info for FLASH chips */
 
 int misc_init_r (void)
 {
+	DECLARE_GLOBAL_DATA_PTR;
+	/* adjust flash start and size as well as the offset */
+	gd->bd->bi_flashstart=0-flash_info[0].size;
+	gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN;
+	gd->bd->bi_flashoffset=0;
+
 	/* check, if RTC is running */
 	rtc_get (&tm);
 	start=get_timer(0);

board/mpl/mip405/mip405.h

@@ -137,13 +137,13 @@ void user_led0(unsigned char on);
 					(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
 
 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define FLASH_BS	2	/* 4 MByte */
+#define FLASH_BS	FLASH_SIZE_PRELIM	/* 4 MByte */
 /* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
 #define FLASH_BU	3	/* R/W */
 /* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
 #define FLASH_BW	1	/* 16Bit */
 /* CR register for Boot */
-#define FLASH_CR_B	((FLASH_BASE0_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
+#define FLASH_CR_B	((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
 /* CR register for non Boot */
 #define FLASH_CR	((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
 
@@ -172,11 +172,12 @@ void user_led0(unsigned char on);
 
 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
 #define MPS_BS		2	/* 4 MByte */
+#define MPS_BS_B		FLASH_SIZE_PRELIM	/* 1 MByte */
 /* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
 #define MPS_BU		3	/* R/W */
 /* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
 #define MPS_BW		0	/* 8Bit */
 /* CR register for Boot */
-#define MPS_CR_B	((FLASH_BASE0_PRELIM & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
+#define MPS_CR_B	((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS_B << 17) + (MPS_BU << 15) + (MPS_BW << 13))
 /* CR register for non Boot */
 #define MPS_CR		((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))

board/mpl/pip405/init.S

@@ -41,17 +41,21 @@
 
 #define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
 
-#include "configs/PIP405.h"
+#include <configs/PIP405.h>
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
 #include <asm/cache.h>
 #include <asm/mmu.h>
+#include "pip405.h"
 
+  .globl ext_bus_cntlr_init
+ ext_bus_cntlr_init:
+  mflr   r4                      /* save link register */
+  mfdcr  r3,strap                /* get strapping reg */
+  andi.  r0, r3, PSR_ROM_LOC     /* mask out irrelevant bits */
+  bnelr                          /* jump back if PCI boot */
 
-	.globl	ext_bus_cntlr_init
-ext_bus_cntlr_init:
-  mflr    r4                      /* save link register */
   bl      ..getAddr
 ..getAddr:
   mflr    r3                      /* get address of ..getAddr */
@@ -82,7 +86,7 @@ ext_bus_cntlr_init:
 	mfdcr		r4,ebccfgd
 
 	andi.		r0, r4, 0x2000			/* mask out irrelevant bits */
-	beq			0f									/* jump if 8 bit bus width */
+	beq		0f				/* jump if 8 bit bus width */
 
 	/* setup 16 bit things
    *-----------------------------------------------------------------------
@@ -90,74 +94,49 @@ ext_bus_cntlr_init:
    *---------------------------------------------------------------------- */
 
 	addi    r4,0,pb0ap
-  mtdcr   ebccfga,r4
-  addis   r4,0,0x9B01
-  ori     r4,r4,0x5480
-  mtdcr   ebccfgd,r4
+	mtdcr   ebccfga,r4
+	addis   r4,0,(FLASH_AP_B)@h
+	ori     r4,r4,(FLASH_AP_B)@l
+	mtdcr   ebccfgd,r4
 
-  addi    r4,0,pb0cr
-  mtdcr   ebccfga,r4
-	/* BS=0x011(8MB),BU=0x3(R/W), */
-  addis   r4,0,((FLASH_BASE0_PRELIM & 0xFFF00000) | 0x00050000)@h
-  ori     r4,r4,0xA000          /* BW=0x01(16 bits) */
-  mtdcr   ebccfgd,r4
-
-  /*-----------------------------------------------------------------------
-   * Memory Bank 1 (Multi Purpose Socket) initialization
-   *----------------------------------------------------------------------*/
-  addi    r4,0,pb1ap
-  mtdcr   ebccfga,r4
-  addis   r4,0,0x0281
-  ori     r4,r4,0x5480
-  mtdcr   ebccfgd,r4
-
-  addi    r4,0,pb1cr
-  mtdcr   ebccfga,r4
-  /* BS=0x011(8MB),BU=0x3(R/W), */
-  addis   r4,0,((MULTI_PURPOSE_SOCKET_ADDR & 0xFFF00000) | 0x00050000)@h
-  ori     r4,r4,0x8000          /* BW=0x0( 8 bits) */
-  mtdcr   ebccfgd,r4
+	addi    r4,0,pb0cr
+	mtdcr   ebccfga,r4
+	/* BS=0x010(4MB),BU=0x3(R/W), */
+	addis   r4,0,(FLASH_CR_B)@h
+	ori     r4,r4,(FLASH_CR_B)@l
+	mtdcr   ebccfgd,r4
 	b				1f
 
 0:
-  /* 8Bit boot mode: */
+	/* 8Bit boot mode: */
 	/*-----------------------------------------------------------------------
-   * Memory Bank 0 Multi Purpose Socket initialization
-   *----------------------------------------------------------------------- */
-
+	* Memory Bank 0 Multi Purpose Socket initialization
+	*----------------------------------------------------------------------- */
+	/* 0x7F8FFE80 slowest boot */
 	addi    r4,0,pb0ap
-  mtdcr   ebccfga,r4
-  addis   r4,0,0x9B01
-  ori     r4,r4,0x5480
-  mtdcr   ebccfgd,r4
+	mtdcr   ebccfga,r4
+	addis   r4,0,(MPS_AP_B)@h
+	ori     r4,r4,(MPS_AP_B)@l
+	mtdcr   ebccfgd,r4
 
-  addi    r4,0,pb0cr
-  mtdcr   ebccfga,r4
-	/* BS=0x011(4MB),BU=0x3(R/W), */
-  addis   r4,0,((FLASH_BASE0_PRELIM & 0xFFF00000) | 0x00050000)@h
-  ori     r4,r4,0x8000          /* BW=0x0( 8 bits) */
-  mtdcr   ebccfgd,r4
+	addi    r4,0,pb0cr
+	mtdcr   ebccfga,r4
+	/* BS=0x010(4MB),BU=0x3(R/W), */
+	addis   r4,0,(MPS_CR_B)@h
+	ori     r4,r4,(MPS_CR_B)@l
+	mtdcr   ebccfgd,r4
 
-  /*-----------------------------------------------------------------------
-   * Memory Bank 1 (Flash) initialization
-   *-----------------------------------------------------------------------*/
-  addi    r4,0,pb1ap
-  mtdcr   ebccfga,r4
-  addis   r4,0,0x0281
-  ori     r4,r4,0x5480
-  mtdcr   ebccfgd,r4
-
-  addi    r4,0,pb1cr
-  mtdcr   ebccfga,r4
-  /* BS=0x011(8MB),BU=0x3(R/W), */
-  addis   r4,0,((MULTI_PURPOSE_SOCKET_ADDR & 0xFFF00000) | 0x00050000)@h
-  ori     r4,r4,0xA000          /* BW=0x0( 8 bits) */
-  mtdcr   ebccfgd,r4
 
 1:
   /*-----------------------------------------------------------------------
    * Memory Bank 2-3-4-5-6 (not used) initialization
    *-----------------------------------------------------------------------*/
+  addi    r4,0,pb1cr
+  mtdcr   ebccfga,r4
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
+  mtdcr   ebccfgd,r4
+
   addi    r4,0,pb2cr
   mtdcr   ebccfga,r4
   addis   r4,0,0x0000
@@ -182,28 +161,18 @@ ext_bus_cntlr_init:
   ori     r4,r4,0x0000
   mtdcr   ebccfgd,r4
 
-	addi    r4,0,pb6cr
+  addi    r4,0,pb6cr
   mtdcr   ebccfga,r4
   addis   r4,0,0x0000
   ori     r4,r4,0x0000
-  mtdcr   ebccfgd,r4
-
-	/*-----------------------------------------------------------------------
-   * Memory Bank 7 (Config Register) initialization
-   *----------------------------------------------------------------------- */
-  addi    r4,0,pb7ap
-  mtdcr   ebccfga,r4
-  addis   r4,0,0x0181	      /* Doc says TWT=3 and Openios TWT=3!! */
-  ori     r4,r4,0x5280          /* disable Ready, BEM=0 */
   mtdcr   ebccfgd,r4
 
   addi    r4,0,pb7cr
   mtdcr   ebccfga,r4
-	/* BS=0x0(1MB),BU=0x3(R/W), */
-  addis   r4,0,((CONFIG_PORT_ADDR & 0xFFF00000) | 0x00010000)@h
-  ori     r4,r4,0x8000            /* BW=0x0(8 bits) */
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
   mtdcr   ebccfgd,r4
-	nop				/* pass2 DCR errata #8 */
+  nop				/* pass2 DCR errata #8 */
   blr
 
 /*-----------------------------------------------------------------------------
@@ -217,3 +186,45 @@ sdram_init:
 
 
   blr
+
+
+#if defined(CONFIG_BOOT_PCI)
+    .section .bootpg,"ax"
+    .globl _start_pci
+/*******************************************
+ */
+
+_start_pci:
+  /* first handle errata #68 / PCI_18 */
+  iccci   r0, r0          /* invalidate I-cache */
+  lis     r31, 0
+  mticcr  r31             /* ICCR = 0 (all uncachable) */
+  isync
+
+  mfccr0  r28             /* set CCR0[24] = 1 */
+  ori     r28, r28, 0x0080
+  mtccr0  r28
+
+  /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */
+  lis     r28, 0xEF40
+  addi    r28, r28, 0x0004
+  stw     r31, 0x0C(r28)  /* clear PMM0PCIHA */
+  lis     r29, 0xFFF8     /* open 512 kByte */
+  addi    r29, r29, 0x0001/* and enable this region */
+  stwbrx  r29, r0, r28    /* write PMM0MA */
+
+  lis     r28, 0xEEC0     /* address of PCIC0_CFGADDR */
+  addi    r29, r28, 4     /* add 4 to r29 -> PCIC0_CFGDATA */
+
+  lis     r31, 0x8000     /* set en bit bus 0 */
+  ori     r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */
+  stwbrx  r31, r0, r28    /* write it */
+
+  lwbrx   r31, r0, r29    /* load XBCS register */
+  oris    r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */
+  stwbrx  r31, r0, r29    /* write back XBCS register */
+
+  nop
+  nop
+  b	_start		/* normal start */
+#endif

board/mpl/pip405/pip405.c

@@ -194,6 +194,11 @@ int board_pre_init (void)
 #ifdef SDRAM_DEBUG
 	DECLARE_GLOBAL_DATA_PTR;
 #endif
+	/* set up the config port */
+	mtdcr (ebccfga, pb7ap);
+	mtdcr (ebccfgd, CONFIG_PORT_AP);
+	mtdcr (ebccfga, pb7cr);
+	mtdcr (ebccfgd, CONFIG_PORT_CR);
 
 	memclk = get_bus_freq (tmemclk);
 	tmemclk = 1000000000 / (memclk / 100);	/* in 10 ps units */
@@ -657,8 +662,20 @@ static int test_dram (unsigned long ramsize)
 }
 
 
+extern flash_info_t flash_info[];	/* info for FLASH chips */
+
 int misc_init_r (void)
 {
+	DECLARE_GLOBAL_DATA_PTR;
+	/* adjust flash start and size as well as the offset */
+	gd->bd->bi_flashstart=0-flash_info[0].size;
+	gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN;
+	gd->bd->bi_flashoffset=0;
+
+	/* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
+	if (mfdcr(strap) & PSR_ROM_LOC)
+	       mtspr(ccr0, (mfspr(ccr0) & ~0x80));
+
 	return (0);
 }
 

board/mpl/pip405/pip405.h

@@ -25,6 +25,7 @@
  * Global routines used for PIP405
  *****************************************************************************/
 
+#ifndef __ASSEMBLY__
 
 extern int  mem_test(unsigned long start, unsigned long ramsize,int mode);
 
@@ -35,13 +36,13 @@ void user_led1(unsigned char on);
 
 
 #define PLD_BASE_ADDRESS		CFG_ISA_IO_BASE_ADDRESS + 0x800
-#define PLD_PART_REG				PLD_BASE_ADDRESS + 0
-#define PLD_VERS_REG				PLD_BASE_ADDRESS + 1
+#define PLD_PART_REG			PLD_BASE_ADDRESS + 0
+#define PLD_VERS_REG			PLD_BASE_ADDRESS + 1
 #define PLD_BOARD_CFG_REG		PLD_BASE_ADDRESS + 2
 #define PLD_LED_USER_REG		PLD_BASE_ADDRESS + 3
 #define PLD_SYS_MAN_REG			PLD_BASE_ADDRESS + 4
 #define PLD_FLASH_COM_REG		PLD_BASE_ADDRESS + 5
-#define PLD_CAN_REG					PLD_BASE_ADDRESS + 6
+#define PLD_CAN_REG			PLD_BASE_ADDRESS + 6
 #define PLD_SER_PWR_REG			PLD_BASE_ADDRESS + 7
 #define PLD_COM_PWR_REG			PLD_BASE_ADDRESS + 8
 #define PLD_NIC_VGA_REG			PLD_BASE_ADDRESS + 9
@@ -50,86 +51,32 @@ void user_led1(unsigned char on);
 #define PIIX4_VENDOR_ID			0x8086
 #define PIIX4_IDE_DEV_ID		0x7111
 
-
-/* timings */
-/* PLD (CS7) */
-#define PLD_BME	0 	/* Burst disable */
-#define PLD_TWE	5	/* 5 * 30ns 120ns Waitstates (access=TWT+1+TH) */
-#define PLD_CSN	1	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
-#define PLD_OEN	1	/* Cycles from CS low to OE low   */
-#define PLD_WBN	1	/* Cycles from CS low to WE low   */
-#define PLD_WBF	1	/* Cycles from WE high to CS high */
-#define PLD_TH	2	/* Number of hold cycles after transfer */
-#define PLD_RE	0	/* Ready disabled */
-#define PLD_SOR	1	/* Sample on Ready disabled */
-#define PLD_BEM	0	/* Byte Write only active on Write cycles */
-#define PLD_PEN	0	/* Parity disable */
-#define PLD_AP 	((PLD_BME << 31) + (PLD_TWE << 23) + (PLD_CSN << 18) + (PLD_OEN << 16) + (PLD_WBN << 14) + \
-					(PLD_WBF << 12) + (PLD_TH << 9) + (PLD_RE << 8) + (PLD_SOR << 7) + (PLD_BEM << 6) + (PLD_PEN << 5))
-
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define PLD_BS	0	/* 1 MByte */
-/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
-#define PLD_BU	3	/* R/W */
-/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
-#define PLD_BW	0	/* 16Bit */
-#define PLD_CR	((PER_PLD_ADDR & 0xfff00000) + (PLD_BS << 17) + (PLD_BU << 15) + (PLD_BW << 13))
-
+#endif
 
 /* timings */
 
-#define PER_BOARD_ADDR (PER_UART1_ADDR+(1024*1024))
-/* Dummy CS to get the board revision */
-#define BOARD_BME	0 	/* Burst disable */
-#define BOARD_TWE	255	/* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */
-#define BOARD_CSN	1	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
-#define BOARD_OEN	1	/* Cycles from CS low to OE low   */
-#define BOARD_WBN	1	/* Cycles from CS low to WE low   */
-#define BOARD_WBF	1	/* Cycles from WE high to CS high */
-#define BOARD_TH	2	/* Number of hold cycles after transfer */
-#define BOARD_RE	0	/* Ready disabled */
-#define BOARD_SOR	1	/* Sample on Ready disabled */
-#define BOARD_BEM	0	/* Byte Write only active on Write cycles */
-#define BOARD_PEN	0	/* Parity disable */
-#define BOARD_AP 	((BOARD_BME << 31) + (BOARD_TWE << 23) + (BOARD_CSN << 18) + (BOARD_OEN << 16) + (BOARD_WBN << 14) + \
-					(BOARD_WBF << 12) + (BOARD_TH << 9) + (BOARD_RE << 8) + (BOARD_SOR << 7) + (BOARD_BEM << 6) + (BOARD_PEN << 5))
+/* CS Config register (CS7) */
+#define CONFIG_PORT_BME	0 	/* Burst disable */
+#define CONFIG_PORT_TWE	255	/* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */
+#define CONFIG_PORT_CSN	1	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
+#define CONFIG_PORT_OEN	1	/* Cycles from CS low to OE low   */
+#define CONFIG_PORT_WBN	1	/* Cycles from CS low to WE low   */
+#define CONFIG_PORT_WBF	1	/* Cycles from WE high to CS high */
+#define CONFIG_PORT_TH	2	/* Number of hold cycles after transfer */
+#define CONFIG_PORT_RE	0	/* Ready disabled */
+#define CONFIG_PORT_SOR	1	/* Sample on Ready disabled */
+#define CONFIG_PORT_BEM	0	/* Byte Write only active on Write cycles */
+#define CONFIG_PORT_PEN	0	/* Parity disable */
+#define CONFIG_PORT_AP 	((CONFIG_PORT_BME << 31) + (CONFIG_PORT_TWE << 23) + (CONFIG_PORT_CSN << 18) + (CONFIG_PORT_OEN << 16) + (CONFIG_PORT_WBN << 14) + \
+				(CONFIG_PORT_WBF << 12) + (CONFIG_PORT_TH << 9) + (CONFIG_PORT_RE << 8) + (CONFIG_PORT_SOR << 7) + (CONFIG_PORT_BEM << 6) + (CONFIG_PORT_PEN << 5))
 
 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define BOARD_BS	0	/* 1 MByte */
+#define CONFIG_PORT_BS	0	/* 1 MByte */
 /* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
-#define BOARD_BU	3	/* R/W */
+#define CONFIG_PORT_BU	3	/* R/W */
 /* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
-#define BOARD_BW	0	/* 16Bit */
-#define BOARD_CR	((PER_BOARD_ADDR & 0xfff00000) + (BOARD_BS << 17) + (BOARD_BU << 15) + (BOARD_BW << 13))
-
-
-/* UART0 CS2 */
-#define UART0_BME	0 	/* Burst disable */
-#define UART0_TWE	7	/* 7 * 30ns 210ns Waitstates (access=TWT+1+TH) */
-#define UART0_CSN	1	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
-#define UART0_OEN	1	/* Cycles from CS low to OE low   */
-#define UART0_WBN	1	/* Cycles from CS low to WE low   */
-#define UART0_WBF	1	/* Cycles from WE high to CS high */
-#define UART0_TH	2	/* Number of hold cycles after transfer */
-#define UART0_RE	0	/* Ready disabled */
-#define UART0_SOR	1	/* Sample on Ready disabled */
-#define UART0_BEM	0	/* Byte Write only active on Write cycles */
-#define UART0_PEN	0	/* Parity disable */
-#define UART0_AP 	((UART0_BME << 31) + (UART0_TWE << 23) + (UART0_CSN << 18) + (UART0_OEN << 16) + (UART0_WBN << 14) + \
-					(UART0_WBF << 12) + (UART0_TH << 9) + (UART0_RE << 8) + (UART0_SOR << 7) + (UART0_BEM << 6) + (UART0_PEN << 5))
-
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define UART0_BS	0	/* 1 MByte */
-/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
-#define UART0_BU	3	/* R/W */
-/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
-#define UART0_BW	0	/* 8Bit */
-#define UART0_CR	((PER_UART0_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13))
-
-/* UART1 CS3 */
-#define UART1_AP UART0_AP /* same timing as UART0 */
-#define UART1_CR	((PER_UART1_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13))
-
+#define CONFIG_PORT_BW	0	/* 16Bit */
+#define CONFIG_PORT_CR	((CONFIG_PORT_ADDR & 0xfff00000) + (CONFIG_PORT_BS << 17) + (CONFIG_PORT_BU << 15) + (CONFIG_PORT_BW << 13))
 
 /* Flash CS0 or CS 1 */
 /* 0x7F8FFE80 slowest timing at all... */
@@ -149,19 +96,19 @@ void user_led1(unsigned char on);
 #define FLASH_PEN	0	/* Parity disable */
 /* Access Parameter Register for non Boot */
 #define FLASH_AP 	((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
-					(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
+				(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
 /* Access Parameter Register for Boot */
 #define FLASH_AP_B 	((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
-					(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
+				(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
 
 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define FLASH_BS	2	/* 4 MByte */
+#define FLASH_BS	FLASH_SIZE_PRELIM	/* 4 MByte */
 /* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
 #define FLASH_BU	3	/* R/W */
 /* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
 #define FLASH_BW	1	/* 16Bit */
 /* CR register for Boot */
-#define FLASH_CR_B	((FLASH_BASE0_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
+#define FLASH_CR_B	((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
 /* CR register for non Boot */
 #define FLASH_CR	((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
 
@@ -183,18 +130,19 @@ void user_led1(unsigned char on);
 #define MPS_PEN		0	/* Parity disable */
 /* Access Parameter Register for non Boot */
 #define MPS_AP 		((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
-					(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
+				(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
 /* Access Parameter Register for Boot */
-#define MPS_AP_B 		((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
-					(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
+#define MPS_AP_B 	((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
+				(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
 
 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
 #define MPS_BS		2	/* 4 MByte */
+#define MPS_BS_B		FLASH_SIZE_PRELIM	/* 1 MByte */
 /* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
 #define MPS_BU		3	/* R/W */
 /* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
 #define MPS_BW		0	/* 8Bit */
 /* CR register for Boot */
-#define MPS_CR_B	((FLASH_BASE0_PRELIM & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
+#define MPS_CR_B	((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
 /* CR register for non Boot */
 #define MPS_CR		((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))

board/mpl/vcma9/cmd_vcma9.c

@@ -41,9 +41,12 @@ static uchar cs8900_chksum(ushort data)
 #endif
 
 extern void print_vcma9_info(void);
-extern int vcma9_cantest(void);
+extern int vcma9_cantest(int);
 extern int vcma9_nandtest(void);
-extern int vcma9_dactest(void);
+extern int vcma9_nanderase(void);
+extern int vcma9_nandread(ulong);
+extern int vcma9_nandwrite(ulong);
+extern int vcma9_dactest(int);
 extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 
 /* ------------------------------------------------------------------------- */
@@ -126,18 +129,53 @@ int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #endif
 #if 0
 	if (strcmp(argv[1], "cantest") == 0) {
-		vcma9_cantest();
+		if (argc >= 3)
+			vcma9_cantest(strcmp(argv[2], "s") ? 0 : 1);
+		else
+			vcma9_cantest(0);
 		return 0;
 	}
 	if (strcmp(argv[1], "nandtest") == 0) {
 		vcma9_nandtest();
 		return 0;
 	}
+	if (strcmp(argv[1], "nanderase") == 0) {
+		vcma9_nanderase();
+		return 0;
+	}
+	if (strcmp(argv[1], "nandread") == 0) {
+		ulong offset = 0;
+
+		if (argc >= 3)
+			offset = simple_strtoul(argv[2], NULL, 16);
+
+		vcma9_nandread(offset);
+		return 0;
+	}
+	if (strcmp(argv[1], "nandwrite") == 0) {
+		ulong offset = 0;
+
+		if (argc >= 3)
+			offset = simple_strtoul(argv[2], NULL, 16);
+
+		vcma9_nandwrite(offset);
+		return 0;
+	}
 	if (strcmp(argv[1], "dactest") == 0) {
-		vcma9_dactest();
+		if (argc >= 3)
+			vcma9_dactest(strcmp(argv[2], "s") ? 0 : 1);
+		else
+		vcma9_dactest(0);
 		return 0;
 	}
 #endif
 
 	return (do_mplcommon(cmdtp, flag, argc, argv));
 }
+
+U_BOOT_CMD(
+	vcma9, 6, 1, do_vcma9,
+	"vcma9   - VCMA9 specific commands\n",
+	"flash mem [SrcAddr]\n    - updates U-Boot with image in memory\n"
+);
+

board/mpl/vcma9/config.mk

@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2002
+# (C) Copyright 2002, 2003
 # David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
 #
 # MPL VCMA9 board with S3C2410X (ARM920T) cpu
@@ -8,17 +8,17 @@
 #
 
 #
-# MPL VCMA9 has 1 bank of 64 MB DRAM
-#
-# 3000'0000 to 3400'0000
+# MPL VCMA9 has 1 bank of minimal 16 MB DRAM
+# from 0x30000000
 #
 # Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
-# optionally with a ramdisk at 3080'0000
+# optionally with a ramdisk at 3040'0000
 #
-# we load ourself to 33F8'0000
+# we load ourself to 30F8'0000
 #
-# download area is 3300'0000
+# download area is 3080'0000
 #
 
 
+#TEXT_BASE = 0x30F80000
 TEXT_BASE = 0x33F80000

board/mpl/vcma9/flash.c

@@ -80,7 +80,7 @@ ulong flash_init(void)
 	if (i == 0)
 	  flashbase = PHYS_FLASH_1;
 	else
-	  panic("configured to many flash banks!\n");
+	  panic("configured too many flash banks!\n");
 	for (j = 0; j < flash_info[i].sector_count; j++)
 	{
 	    if (j <= 3)

board/mpl/vcma9/memsetup.S

@@ -34,7 +34,9 @@
 
 /* some parameters for the board */
 
-#define BWSCON	0x48000000
+#define BWSCON		0x48000000
+#define PLD_BASE	0x2C000000
+#define SDRAM_REG	0x2C000106
 
 /* BWSCON */
 #define DW8		 	(0x0)
@@ -43,6 +45,9 @@
 #define WAIT		 	(0x1<<2)
 #define UBLB		 	(0x1<<3)
 
+/* BANKSIZE */
+#define BURST_EN		(0x1<<7)
+
 #define B1_BWSCON	  	(DW16)
 #define B2_BWSCON	  	(DW32)
 #define B3_BWSCON	  	(DW32)
@@ -130,24 +135,39 @@ memsetup:
 	/* memory control configuration */
 	/* make r0 relative the current location so that it */
 	/* reads SMRDATA out of FLASH rather than memory ! */
-	ldr     r0, =SMRDATA
+	ldr     r0, =CSDATA
 	ldr	r1, _TEXT_BASE
 	sub	r0, r0, r1
 	ldr	r1, =BWSCON	/* Bus Width Status Controller */
-	add     r2, r0, #13*4
+	add     r2, r0, #CSDATA_END-CSDATA
 0:
 	ldr     r3, [r0], #4
 	str     r3, [r1], #4
 	cmp     r2, r0
 	bne     0b
 
+	/* PLD access is now possible */
+	/* r0 == SDRAMDATA */
+	/* r1 == SDRAM controller regs */
+	ldr	r2, =PLD_BASE
+	ldrb	r3, [r2, #SDRAM_REG-PLD_BASE]
+	mov	r4, #SDRAMDATA1_END-SDRAMDATA
+	/* calculate start and end point */
+	mla	r0, r3, r4, r0 
+	add     r2, r0, r4
+0:
+	ldr     r3, [r0], #4
+	str     r3, [r1], #4
+	cmp     r2, r0
+	bne     0b
+	
 	/* everything is fine now */
 	mov	pc, lr
 
 	.ltorg
 /* the literal pools origin */
 
-SMRDATA:
+CSDATA:
     .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
     .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
     .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
@@ -155,9 +175,38 @@ SMRDATA:
     .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
     .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
     .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
+CSDATA_END:
+
+SDRAMDATA:
+/* 4Mx8x4 */
     .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
     .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
     .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
-    .word 0x32
+    .word 0x32 + BURST_EN
+    .word 0x30
+    .word 0x30
+SDRAMDATA1_END:
+
+/* 8Mx8x4 (not implemented yet) */
+    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+    .word 0x32 + BURST_EN
+    .word 0x30
+    .word 0x30
+    
+/* 2Mx8x4 (not implemented yet) */
+    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+    .word 0x32 + BURST_EN
+    .word 0x30
+    .word 0x30
+    
+/* 4Mx8x2 (not implemented yet) */
+    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+    .word 0x32 + BURST_EN
     .word 0x30
     .word 0x30

board/mpl/vcma9/vcma9.c

@@ -130,21 +130,11 @@ int board_init(void)
 	return 0;
 }
 
-int dram_init(void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return 0;
-}
-
 /*
  * NAND flash initialization.
  */
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
-extern void
+extern ulong
 nand_probe(ulong physadr);
 
 
@@ -162,9 +152,16 @@ static inline void NF_Reset(void)
 
 static inline void NF_Init(void)
 {
+#if 0 /* a little bit too optimistic */
 #define TACLS   0
 #define TWRPH0  3
 #define TWRPH1  0
+#else
+#define TACLS   0
+#define TWRPH0  4
+#define TWRPH1  2
+#endif
+
     NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0));
     /*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */
     /* 1  1    1     1,   1      xxx,  r xxx,   r xxx */
@@ -179,8 +176,10 @@ nand_init(void)
 	S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
 
 	NF_Init();
+#ifdef DEBUG
 	printf("NAND flash probing at 0x%.8lX\n", (ulong)nand);
-	nand_probe((ulong)nand);
+#endif
+	printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20);
 }
 #endif
 
@@ -188,41 +187,102 @@ nand_init(void)
  * Get some Board/PLD Info
  */
 
-static uchar Get_PLD_ID(void)
+static u8 Get_PLD_ID(void)
 {
-	return(*(volatile uchar *)PLD_ID_REG);
+	VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
+	
+	return(pld->ID);
 }
 
-static uchar Get_PLD_BOARD(void)
+static u8 Get_PLD_BOARD(void)
 {
-	return(*(volatile uchar *)PLD_BOARD_REG);
+	VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
+	
+	return(pld->BOARD);
 }
 
-static uchar Get_PLD_Version(void)
+static u8 Get_PLD_SDRAM(void)
+{
+	VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
+	
+	return(pld->SDRAM);
+}
+
+static u8 Get_PLD_Version(void)
 {
 	return((Get_PLD_ID() >> 4) & 0x0F);
 }
 
-static uchar Get_PLD_Revision(void)
+static u8 Get_PLD_Revision(void)
 {
 	return(Get_PLD_ID() & 0x0F);
 }
 
+#if 0	/* not used */
 static int Get_Board_Config(void)
 {
-	uchar config = Get_PLD_BOARD() & 0x03;
+	u8 config = Get_PLD_BOARD() & 0x03;
 
 	if (config == 3)
 	    return 1;
 	else
 	    return 0;
 }
+#endif
 
 static uchar Get_Board_PCB(void)
 {
 	return(((Get_PLD_BOARD() >> 4) & 0x03) + 'A');
 }
 
+static u8 Get_SDRAM_ChipNr(void)
+{
+	switch ((Get_PLD_SDRAM() >> 4) & 0x0F) {
+		case 0: return 4;
+		case 1: return 1;
+		case 2: return 2;
+		default: return 0;
+	}
+}
+
+static ulong Get_SDRAM_ChipSize(void)
+{
+	switch (Get_PLD_SDRAM() & 0x0F) {
+		case 0: return 16 * (1024*1024);
+		case 1: return 32 * (1024*1024);
+		case 2: return  8 * (1024*1024);
+		case 3: return  8 * (1024*1024);
+		default: return 0;
+	}	
+}
+static const char * Get_SDRAM_ChipGeom(void)
+{
+	switch (Get_PLD_SDRAM() & 0x0F) {
+		case 0: return "4Mx8x4";
+		case 1: return "8Mx8x4";
+		case 2: return "2Mx8x4";
+		case 3: return "4Mx8x2";
+		default: return "unknown";
+	}
+}
+
+static void Show_VCMA9_Info(char *board_name, char *serial)
+{
+	printf("Board: %s SN: %s  PCB Rev: %c PLD(%d,%d)\n",
+		board_name, serial, Get_Board_PCB(), Get_PLD_Version(), Get_PLD_Revision());
+	printf("SDRAM: %d chips %s\n", Get_SDRAM_ChipNr(), Get_SDRAM_ChipGeom());
+}
+
+int dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = Get_SDRAM_ChipSize() * Get_SDRAM_ChipNr();
+
+	return 0;
+}
+
 /* ------------------------------------------------------------------------- */
 
 /*
@@ -235,8 +295,6 @@ int checkboard(void)
 	int i;
 	backup_t *b = (backup_t *) s;
 
-	puts("Board: ");
-
 	i = getenv_r("serial#", s, 32);
 	if ((i < 0) || strncmp (s, "VCMA9", 5)) {
 		get_backup_values (b);
@@ -244,32 +302,23 @@ int checkboard(void)
 			puts ("### No HW ID - assuming VCMA9");
 		} else {
 			b->serial_name[5] = 0;
-			printf ("%s-%d PCB Rev %c SN: %s", b->serial_name, Get_Board_Config(),
-					Get_Board_PCB(), &b->serial_name[6]);
+			Show_VCMA9_Info(b->serial_name, &b->serial_name[6]);
 		}
 	} else {
 		s[5] = 0;
-		printf ("%s-%d PCB Rev %c SN: %s", s, Get_Board_Config(), Get_Board_PCB(),
-				&s[6]);
+		Show_VCMA9_Info(s, &s[6]);
 	}
-	printf("\n");
+	/*printf("\n");*/
 	return(0);
 }
 
 
-void print_vcma9_rev(void)
-{
-	printf("Board: VCMA9-%d PCB Rev: %c (PLD Ver: %d, Rev: %d)\n",
-		Get_Board_Config(), Get_Board_PCB(),
-		Get_PLD_Version(), Get_PLD_Revision());
-}
-
 extern void mem_test_reloc(void);
 
 int last_stage_init(void)
 {
 	mem_test_reloc();
-	print_vcma9_rev();
+	checkboard();
 	show_stdio_dev();
 	check_env();
 	return 0;
@@ -290,6 +339,15 @@ int overwrite_console(void)
 * Print VCMA9 Info
 ************************************************************************/
 void print_vcma9_info(void)
-{
-    print_vcma9_rev();
+{	
+	unsigned char s[50];
+	int i;
+	
+	if ((i = getenv_r("serial#", s, 32)) < 0) {
+		puts ("### No HW ID - assuming VCMA9");
+		printf("i %d", i*24);
+	} else {
+		s[5] = 0;
+		Show_VCMA9_Info(s, &s[6]);
+	}
 }

board/mpl/vcma9/vcma9.h

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2002
+ * (C) Copyright 2002, 2003
  * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
  *
  * See file CREDITS for list of people who contributed to this
@@ -116,11 +116,19 @@ static inline u32 NF_Read_ECC(void)
 
 #endif
 
+/* VCMA9 PLD regsiters */
+typedef struct {
+	S3C24X0_REG8	ID;
+	S3C24X0_REG8	NIC;
+	S3C24X0_REG8	CAN;
+	S3C24X0_REG8	MISC;
+	S3C24X0_REG8	GPCD;
+	S3C24X0_REG8	BOARD;
+	S3C24X0_REG8	SDRAM;
+} /*__attribute__((__packed__))*/ VCMA9_PLD;
 
-#define PLD_BASE_ADDRESS		0x2C000100
-#define PLD_ID_REG			(PLD_BASE_ADDRESS + 0)
-#define PLD_NIC_REG			(PLD_BASE_ADDRESS + 1)
-#define PLD_CAN_REG			(PLD_BASE_ADDRESS + 2)
-#define PLD_MISC_REG			(PLD_BASE_ADDRESS + 3)
-#define PLD_GPCD_REG			(PLD_BASE_ADDRESS + 4)
-#define PLD_BOARD_REG			(PLD_BASE_ADDRESS + 5)
+#define VCMA9_PLD_BASE	0x2C000100
+static inline VCMA9_PLD * const VCMA9_GetBase_PLD(void)
+{
+	return (VCMA9_PLD * const)VCMA9_PLD_BASE;
+}

board/netvia/netvia.c

@@ -420,16 +420,13 @@ int board_pre_init(void)
 
 #include <linux/mtd/nand.h>
 
-extern void nand_probe(ulong physadr);
+extern ulong nand_probe(ulong physadr);
 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
 
 void nand_init(void)
 {
-	nand_probe(CFG_NAND_BASE);
-	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
-		nand_dev_desc[0].name = "NetVia NAND flash";
-		puts("NAND:  ");
-		print_size(nand_dev_desc[0].totlen, "\n");
-	}
+	unsigned long totlen = nand_probe(CFG_NAND_BASE);
+
+	printf ("%4lu MB\n", totlen >> 20);
 }
 #endif

board/omap1510inn/flash.c

@@ -72,7 +72,7 @@ unsigned long flash_init (void)
 			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
 			break;
 		default:
-			panic ("configured to many flash banks!\n");
+			panic ("configured too many flash banks!\n");
 			break;
 		}
 		size += flash_info[i].size;

board/omap1610inn/flash.c

@@ -96,7 +96,7 @@ unsigned long flash_init (void)
 			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
 			break;
 		default:
-			panic ("configured to many flash banks!\n");
+			panic ("configured too many flash banks!\n");
 			break;
 		}
 		size += flash_info[i].size;

board/sacsng/sacsng.c

@@ -28,11 +28,18 @@
 #include <mpc8260.h>
 #include <i2c.h>
 #include <spi.h>
+#include <command.h>
 
 #ifdef CONFIG_SHOW_BOOT_PROGRESS
 #include <status_led.h>
 #endif
 
+#ifdef CONFIG_ETHER_LOOPBACK_TEST
+extern void eth_loopback_test(void);
+#endif /* CONFIG_ETHER_LOOPBACK_TEST */
+
+extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
 #include "clkinit.h"
 #include "ioconfig.h" /* I/O configuration table */
 
@@ -243,15 +250,15 @@ long int initdram(int board_type)
 
     /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */
     if(caslatency < 2) {
-	printf("CL was %d, forcing to 2\n", caslatency);
+	printf("WARNING: CL was %d, forcing to 2\n", caslatency);
 	caslatency = 2;
     }
     if(rows > 14) {
-	printf("This doesn't look good, rows = %d, should be <= 14\n", rows);
+	printf("WARNING: This doesn't look good, rows = %d, should be <= 14\n", rows);
 	rows = 14;
     }
     if(cols > 11) {
-	printf("This doesn't look good, columns = %d, should be <= 11\n", cols);
+	printf("WARNING: This doesn't look good, columns = %d, should be <= 11\n", cols);
 	cols = 11;
     }
 
@@ -450,6 +457,15 @@ int misc_init_r(void)
     int  sample_128x;  /* Use 128/4 clocking for the ADC/DAC */
     int  right_just;   /* Is the data to the DAC right justified? */
     int  mclk_divide;  /* MCLK Divide */
+    int  quiet;        /* Quiet or minimal output mode */
+
+    quiet = 0;
+    if ((ep = getenv("quiet")) != NULL) {
+	quiet = simple_strtol(ep, NULL, 10);
+    }
+    else {
+	setenv("quiet", "0");
+    }
 
     /*
      * SACSng custom initialization:
@@ -517,8 +533,12 @@ int misc_init_r(void)
 	setenv("Daq128xSampling", "1");
     }
 
-    /* Display the ADC/DAC clocking information */
-    Daq_Display_Clocks();
+    /* 
+     * Display the ADC/DAC clocking information 
+     */
+    if (!quiet) {
+        Daq_Display_Clocks();
+    }
 
     /*
      * Determine the DAC data justification
@@ -552,8 +572,10 @@ int misc_init_r(void)
      * 3) Write the I2C address to register 6
      * 4) Enable address matching by setting the MSB in register 7
      */
-
-    printf("Initializing the ADC...\n");
+    
+    if (!quiet) {
+        printf("Initializing the ADC...\n");
+    }
     udelay(ADC_INITIAL_DELAY);		/* 10uSec per uF of VREF cap */
 
     iopa->pdat &= ~ADC_SDATA1_MASK;     /* release SDATA1 */
@@ -615,7 +637,9 @@ int misc_init_r(void)
      * sending an I2C "start" sequence.  When we bring the I2C back to
      * the normal state, we send an I2C "stop" sequence.
      */
-    printf("Initializing the DAC...\n");
+    if (!quiet) {
+	printf("Initializing the DAC...\n");
+    }
 
     /*
      * Bring the I2C clock and data lines low for initialization
@@ -695,7 +719,16 @@ int misc_init_r(void)
     I2C_DELAY;
     I2C_TRISTATE;
 
-    printf("\n");
+    if (!quiet) {
+        printf("\n");
+    }
+
+#ifdef CONFIG_ETHER_LOOPBACK_TEST
+    /*
+     * Run the Ethernet loopback test
+     */
+    eth_loopback_test ();
+#endif /* CONFIG_ETHER_LOOPBACK_TEST */
 
 #ifdef CONFIG_SHOW_BOOT_PROGRESS
     /*
@@ -758,17 +791,44 @@ static int last_boot_progress;
 
 void show_boot_progress (int status)
 {
-    if(status != -1) {
+    int i,j;
+    if(status > 0) {
 	last_boot_progress = status;
     } else {
-	/*
-	 * Houston, we have a problem.  Blink the last OK status which
-	 * indicates where things failed.
+        /* 
+	 * If a specific failure code is given, flash this code
+	 * else just use the last success code we've seen
 	 */
-	status_led_set(STATUS_LED_RED, STATUS_LED_ON);
-	flash_code(last_boot_progress, 5, 3);
-	udelay(1000000);
-	status_led_set(STATUS_LED_RED, STATUS_LED_BLINKING);
+	if(status < -1)
+	    last_boot_progress = -status;
+	
+	/* 
+	 * Flash this code 5 times
+	 */
+	for(j=0; j<5; j++) {
+	    /*
+	     * Houston, we have a problem.
+	     * Blink the last OK status which indicates where things failed.
+	     */
+	    status_led_set(STATUS_LED_RED, STATUS_LED_ON);
+	    flash_code(last_boot_progress, 5, 3);
+
+	    /* 
+	     * Delay 5 seconds between repetitions, 
+	     * with the fault LED blinking 
+	     */
+	    for(i=0; i<5; i++) {
+	    	status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
+	    	udelay(500000);
+	    	status_led_set(STATUS_LED_RED, STATUS_LED_ON);
+	    	udelay(500000);
+	    }
+	}
+
+	/*
+	 * Reset the board to retry initialization.
+	 */
+	do_reset (NULL, 0, 0, NULL);
     }
 }
 #endif /* CONFIG_SHOW_BOOT_PROGRESS */

board/sc520_cdp/flash.c

@@ -234,7 +234,7 @@ ulong flash_init(void)
 			flashbase = SC520_FLASH_BANK2_BASE;
 			break;
 		default:
-			panic("configured to many flash banks!\n");
+			panic("configured too many flash banks!\n");
 		}
 
 		id = identify_flash(flashbase, 4);

board/sc520_cdp/flash_old.c

@@ -101,7 +101,7 @@ ulong flash_init(void)
 			flashbase = SC520_FLASH_BANK0_BASE;
 			break;
 		default:
-			panic("configured to many flash banks!\n");
+			panic("configured too many flash banks!\n");
 		}
 
 		for (j = 0; j < flash_info[i].sector_count; j++) {

board/sc520_spunk/flash.c

@@ -239,7 +239,7 @@ ulong flash_init(void)
 			flashbase = SC520_FLASH_BANK0_BASE;
 			break;
 		default:
-			panic("configured to many flash banks!\n");
+			panic("configured too many flash banks!\n");
 		}
 
 		id = identify_flash(flashbase, 2);

board/shannon/flash.c

@@ -73,7 +73,7 @@ ulong flash_init(void)
 	if (i == 0)
 	  flashbase = PHYS_FLASH_1;
 	else
-	  panic("configured to many flash banks!\n");
+	  panic("configured too many flash banks!\n");
 	for (j = 0; j < flash_info[i].sector_count; j++)
 	{
 

board/shannon/shannon.c

@@ -60,7 +60,7 @@ int board_init (void)
 	*(unsigned long *)temp = 0x00060006;
 
 	}
-#endif /* CONFIG_INIT_CRITICAL */
+#endif /* CONFIG_INFERNO */
 
 	/* arch number for shannon */
 	gd->bd->bi_arch_number = 97;

board/sixnet/flash.c

@@ -23,6 +23,10 @@
 
 #include <common.h>
 #include <mpc8xx.h>
+/* environment.h defines the various CFG_ENV_... values in terms
+ * of whichever ones are given in the configuration file.
+ */
+#include <environment.h>
 
 flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
@@ -104,6 +108,19 @@ unsigned long flash_init (void)
 		      &flash_info[0]);
 #endif
 
+#ifdef CFG_ENV_ADDR
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+#endif
+
+#ifdef CFG_ENV_ADDR_REDUND
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR_REDUND,
+			CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
+			&flash_info[0]);
+#endif
+
 	return (size_b);
 }
 
@@ -154,6 +171,21 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
 		for( i = 0; i < info->sector_count; i++ )
 			info->start[i] = base + (i * sect_size);
 	}
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
+		 && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM800T) {
+
+		int sect_size;		/* number of bytes/sector */
+
+		sect_size = 0x00010000 * (sizeof(FPW)/2);
+
+		/* set up sector start address table (top boot sector type) */
+		for (i = 0; i < info->sector_count - 3; i++)
+			info->start[i] = base + (i * sect_size);
+		i = info->sector_count - 1;
+		info->start[i--] = base + (info->size - 0x00004000) * (sizeof(FPW)/2);
+		info->start[i--] = base + (info->size - 0x00006000) * (sizeof(FPW)/2);
+		info->start[i--] = base + (info->size - 0x00008000) * (sizeof(FPW)/2);
+	}
 }
 
 /*-----------------------------------------------------------------------
@@ -196,6 +228,9 @@ void flash_print_info (flash_info_t *info)
 	}
 
 	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM800T:
+		fmt = "29LV800B%s (8 Mbit, %s)\n";
+		break;
 	case FLASH_AM640U:
 		fmt = "29LV641D (64 Mbit, uniform sectors)\n";
 		break;
@@ -295,6 +330,12 @@ ulong flash_get_size (FPWV *addr, flash_info_t *info)
 	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
 	if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) {
 
+	case (FPW)AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000 * (sizeof(FPW)/2);
+		break;				/* => 1 or 2 MiB	*/
+
 	case (FPW)AMD_ID_LV640U:	/* 29LV640 and 29LV641 have same ID */
 		info->flash_id += FLASH_AM640U;
 		info->sector_count = 128;
@@ -401,6 +442,7 @@ static void flash_sync_real_protect(flash_info_t *info)
 	break;
 
     case FLASH_AM640U:
+    case FLASH_AM800T:
     default:
 	/* no hardware protect that we support */
 	break;
@@ -438,6 +480,7 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 	case FLASH_28F320C3B:
 	case FLASH_28F640C3B:
 	case FLASH_AM640U:
+	case FLASH_AM800T:
 		break;
 	case FLASH_UNKNOWN:
 	default:
@@ -735,6 +778,7 @@ int flash_real_protect (flash_info_t * info, long sector, int prot)
 		break;
 
 	case FLASH_AM640U:
+	case FLASH_AM800T:
 	default:
 		/* no hardware protect that we support */
 		info->protect[sector] = prot;

board/sixnet/sixnet.c

@@ -24,6 +24,7 @@
 
 #include <common.h>
 #include <config.h>
+#include <jffs2/jffs2.h>
 #include <mpc8xx.h>
 #include <net.h>	/* for eth_init() */
 #include <rtc.h>
@@ -329,11 +330,9 @@ int misc_init_r (void)
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
 void nand_init(void)
 {
-	nand_probe(CFG_DFLASH_BASE);	/* see if any NAND flash present */
-	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
-		puts("NAND:  ");
-		print_size(nand_dev_desc[0].totlen, "\n");
-	}
+	unsigned long totlen = nand_probe(CFG_DFLASH_BASE);
+
+	printf ("%4lu MB\n", totlen >> 20);
 }
 #endif
 
@@ -602,3 +601,70 @@ long int initdram(int board_type)
 
 	return (size_sdram);
 }
+
+#ifdef CFG_JFFS_CUSTOM_PART
+
+static struct part_info part;
+
+#define jffs2_block(i)	\
+	((struct jffs2_unknown_node*)(CFG_JFFS2_BASE + (i) * 65536))
+
+struct part_info* jffs2_part_info(int part_num)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	bd_t *bd = gd->bd;
+	char* s;
+	int i;
+	int bootnor = 0;	/* assume booting from NAND flash */
+
+	if (part_num != 0)
+		return 0;	/* only support one partition */
+
+	if (part.usr_priv == (void*)1)
+		return &part;	/* already have part info */
+
+	memset(&part, 0, sizeof(part));
+
+	if (nand_dev_desc[0].ChipID == NAND_ChipID_UNKNOWN)
+		bootnor = 1;
+	else if (bd->bi_flashsize < 0x800000)
+		bootnor = 0;
+	else for (i = 0; !bootnor && i < 4; ++i) {
+		/* boot from NOR if JFFS2 info in any of
+		 * first 4 erase blocks
+		 */
+
+		if (jffs2_block(i)->magic == JFFS2_MAGIC_BITMASK)
+			bootnor = 1;
+	}
+
+	if (bootnor) {
+		/* no NAND flash or boot in NOR, use NOR flash */
+		part.offset = (unsigned char *)CFG_JFFS2_BASE;
+		part.size = CFG_JFFS2_SIZE;
+	}
+	else {
+		char readcmd[60];
+
+		/* boot info in NAND flash, get and use copy in RAM */
+
+		/* override info from environment if present */
+		s = getenv("fsaddr");
+		part.offset = s ? (void *)simple_strtoul(s, NULL, 16)
+				: (void *)CFG_JFFS2_RAMBASE;
+		s = getenv("fssize");
+		part.size = s ? simple_strtoul(s, NULL, 16)
+			      : CFG_JFFS2_RAMSIZE;
+
+		/* read from nand flash */
+		sprintf(readcmd, "nand read.jffs2 %x 0 %x",
+			(uint32_t)part.offset, part.size);
+		run_command(readcmd, 0);
+	}
+
+	part.erasesize = 0;	/* unused */
+	part.usr_priv=(void*)1;	/* ready */
+
+	return &part;
+}
+#endif /* ifdef CFG_JFFS_CUSTOM_PART */

board/smdk2410/flash.c

@@ -80,7 +80,7 @@ ulong flash_init(void)
 	if (i == 0)
 	  flashbase = PHYS_FLASH_1;
 	else
-	  panic("configured to many flash banks!\n");
+	  panic("configured too many flash banks!\n");
 	for (j = 0; j < flash_info[i].sector_count; j++)
 	{
 	    if (j <= 3)

board/trab/Makefile

@@ -25,12 +25,30 @@ include $(TOPDIR)/config.mk
 
 LIB	= lib$(BOARD).a
 
-OBJS	:= trab.o flash.o vfd.o
+OBJS	:= trab.o flash.o vfd.o cmd_trab.o memory.o tsc2000.o auto_update.o
 SOBJS	:= memsetup.o
 
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LOAD_ADDR = 0xc100000
+
+#########################################################################
+
+all:	$(LIB) trab_fkt.srec trab_fkt.bin
+
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)
 
+trab_fkt.srec:	trab_fkt.o rs485.o tsc2000.o $(LIB)
+	$(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e $(<:.o=) $^ $(LIB) \
+		-L../../examples -lstubs \
+		-L../../lib_generic -lgeneric \
+		-L$(gcclibdir) -lgcc
+	$(OBJCOPY) -O srec $(<:.o=) $@
+
+trab_fkt.bin:	trab_fkt.srec
+	$(OBJCOPY) -O binary $< $@ 2>/dev/null
+
 clean:
 	rm -f $(SOBJS) $(OBJS)
 

board/trab/Pt1000_temp_data.h

@@ -0,0 +1,71 @@
+/*
+ * Data file for tsc2000 driver.
+ * Copyright (C) 2002, 2003 DENX Software Engineering, Wolfgang Denk, wd@denx.de
+ */
+
+#ifndef _PT1000_TEMP_DATA_H
+#define _PT1000_TEMP_DATA_H
+
+long Pt1000_temp_table[][2] = {
+	/* For quick range checking the largest element
+	 * is placed at index 0.
+	 * U, nV    T, C*100
+	 */
+	{ 44000000 , 12165 },
+	{ -10000000 , -2644 },
+	{ -9000000 , -2381 },
+	{ -8000000 , -2118 },
+	{ -7000000 , -1855 },
+	{ -6000000 , -1591 },
+	{ -5000000 , -1327 },
+	{ -4000000 , -1063 },
+	{ -3000000 , -798 },
+	{ -2000000 , -532 },
+	{ -1000000 , -266 },
+	{ 0 , 000 },
+	{ 1000000 , 267 },
+	{ 2000000 , 534 },
+	{ 3000000 , 802 },
+	{ 4000000 , 1070 },
+	{ 5000000 , 1338 },
+	{ 6000000 , 1607 },
+	{ 7000000 , 1876 },
+	{ 8000000 , 2146 },
+	{ 9000000 , 2416 },
+	{ 10000000 , 2687 },
+	{ 11000000 , 2958 },
+	{ 12000000 , 3230 },
+	{ 13000000 , 3502 },
+	{ 14000000 , 3774 },
+	{ 15000000 , 4047 },
+	{ 16000000 , 4321 },
+	{ 17000000 , 4595 },
+	{ 18000000 , 4869 },
+	{ 19000000 , 5144 },
+	{ 20000000 , 5419 },
+	{ 21000000 , 5694 },
+	{ 22000000 , 5971 },
+	{ 23000000 , 6247 },
+	{ 24000000 , 6524 },
+	{ 25000000 , 6802 },
+	{ 26000000 , 7080 },
+	{ 27000000 , 7358 },
+	{ 28000000 , 7637 },
+	{ 29000000 , 7916 },
+	{ 30000000 , 8196 },
+	{ 31000000 , 8476 },
+	{ 32000000 , 8757 },
+	{ 33000000 , 9039 },
+	{ 34000000 , 9320 },
+	{ 35000000 , 9602 },
+	{ 36000000 , 9885 },
+	{ 37000000 , 10168 },
+	{ 38000000 , 10452 },
+	{ 39000000 , 10736 },
+	{ 40000000 , 11021 },
+	{ 41000000 , 11306 },
+	{ 42000000 , 11592 },
+	{ 43000000 , 11879 },
+	{ 44000000 , 12165 },
+};
+#endif /* _PT1000_TEMP_DATA_H */

board/trab/auto_update.c

@@ -0,0 +1,612 @@
+/*
+ * (C) Copyright 2003
+ * Gary Jennejohn, DENX Software Engineering, gj@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <image.h>
+#include <asm/byteorder.h>
+#include <usb.h>
+
+#ifdef CFG_HUSH_PARSER
+#include <hush.h>
+#endif
+
+#ifdef CONFIG_AUTO_UPDATE
+
+#ifndef CONFIG_USB_OHCI
+#error "must define CONFIG_USB_OHCI"
+#endif
+
+#ifndef CONFIG_USB_STORAGE
+#error "must define CONFIG_USB_STORAGE"
+#endif
+
+#ifndef CFG_HUSH_PARSER
+#error "must define CFG_HUSH_PARSER"
+#endif
+
+#if !(CONFIG_COMMANDS & CFG_CMD_FAT)
+#error "must define CFG_CMD_FAT"
+#endif
+
+/*
+ * Check whether a USB memory stick is plugged in.
+ * If one is found:
+ *	1) if prepare.img ist found load it into memory. If it is
+ *		valid then run it.
+ *	2) if preinst.img is found load it into memory. If it is
+ *		valid then run it. Update the EEPROM.
+ *	3) if firmware.img is found load it into memory. If it is valid,
+ *		burn it into FLASH and update the EEPROM.
+ *	4) if kernel.img is found load it into memory. If it is valid,
+ *		burn it into FLASH and update the EEPROM.
+ *	5) if app.img is found load it into memory. If it is valid,
+ *		burn it into FLASH and update the EEPROM.
+ *	6) if disk.img is found load it into memory. If it is valid,
+ *		burn it into FLASH and update the EEPROM.
+ *	7) if postinst.img is found load it into memory. If it is
+ *		valid then run it. Update the EEPROM.
+ */
+
+#undef AU_DEBUG
+
+#undef debug
+#ifdef	AU_DEBUG
+#define debug(fmt,args...)	printf (fmt ,##args)
+#else
+#define debug(fmt,args...)
+#endif	/* AU_DEBUG */
+
+/* possible names of files on the USB stick. */
+#define AU_PREPARE	"prepare.img"
+#define AU_PREINST	"preinst.img"
+#define AU_FIRMWARE	"firmware.img"
+#define AU_KERNEL	"kernel.img"
+#define AU_APP		"app.img"
+#define AU_DISK		"disk.img"
+#define AU_POSTINST	"postinst.img"
+
+struct flash_layout
+{
+	long start;
+	long end;
+};
+
+/* layout of the FLASH. ST = start address, ND = end address. */
+#ifndef CONFIG_FLASH_8MB			/* 16 MB Flash, 32 MB RAM */
+#define AU_FL_FIRMWARE_ST	0x00000000
+#define AU_FL_FIRMWARE_ND	0x0009FFFF
+#define AU_FL_VFD_ST		0x000A0000
+#define AU_FL_VFD_ND		0x000BFFFF
+#define AU_FL_KERNEL_ST		0x000C0000
+#define AU_FL_KERNEL_ND		0x001BFFFF
+#define AU_FL_APP_ST		0x001C0000
+#define AU_FL_APP_ND		0x005BFFFF
+#define AU_FL_DISK_ST		0x005C0000
+#define AU_FL_DISK_ND		0x00FFFFFF
+#else						/*  8 MB Flash, 32 MB RAM */
+#define AU_FL_FIRMWARE_ST	0x00000000
+#define AU_FL_FIRMWARE_ND	0x0005FFFF
+#define AU_FL_KERNEL_ST		0x00060000
+#define AU_FL_KERNEL_ND		0x0013FFFF
+#define AU_FL_APP_ST		0x00140000
+#define AU_FL_APP_ND		0x0067FFFF
+#define AU_FL_DISK_ST		0x00680000
+#define AU_FL_DISK_ND		0x007DFFFF
+#define AU_FL_VFD_ST		0x007E0000
+#define AU_FL_VFD_ND		0x007FFFFF
+#endif	/* CONFIG_FLASH_8MB */
+
+/* a structure with the offsets to values in the EEPROM */
+struct eeprom_layout
+{
+	int time;
+	int size;
+	int dcrc;
+};
+
+/* layout of the EEPROM - offset from the start. All entries are 32 bit. */
+#define AU_EEPROM_TIME_PREINST	64
+#define AU_EEPROM_SIZE_PREINST	68
+#define AU_EEPROM_DCRC_PREINST	72
+#define AU_EEPROM_TIME_FIRMWARE	76
+#define AU_EEPROM_SIZE_FIRMWARE	80
+#define AU_EEPROM_DCRC_FIRMWARE	84
+#define AU_EEPROM_TIME_KERNEL	88
+#define AU_EEPROM_SIZE_KERNEL	92
+#define AU_EEPROM_DCRC_KERNEL	96
+#define AU_EEPROM_TIME_APP	100
+#define AU_EEPROM_SIZE_APP	104
+#define AU_EEPROM_DCRC_APP	108
+#define AU_EEPROM_TIME_DISK	112
+#define AU_EEPROM_SIZE_DISK	116
+#define AU_EEPROM_DCRC_DISK	120
+#define AU_EEPROM_TIME_POSTINST 124
+#define AU_EEPROM_SIZE_POSTINST 128
+#define AU_EEPROM_DCRC_POSTINST 132
+
+static int au_usb_stor_curr_dev; /* current device */
+
+/* index of each file in the following arrays */
+#define IDX_PREPARE	0
+#define IDX_PREINST	1
+#define IDX_FIRMWARE	2
+#define IDX_KERNEL	3
+#define IDX_APP		4
+#define IDX_DISK	5
+#define IDX_POSTINST	6
+/* max. number of files which could interest us */
+#define AU_MAXFILES 7
+/* pointers to file names */
+char *aufile[AU_MAXFILES];
+/* sizes of flash areas for each file */
+long ausize[AU_MAXFILES];
+/* offsets into the EEEPROM */
+struct eeprom_layout auee_off[AU_MAXFILES] = { \
+	{0}, \
+	{AU_EEPROM_TIME_PREINST, AU_EEPROM_SIZE_PREINST, AU_EEPROM_DCRC_PREINST,}, \
+	{AU_EEPROM_TIME_FIRMWARE, AU_EEPROM_SIZE_FIRMWARE, AU_EEPROM_DCRC_FIRMWARE,}, \
+	{AU_EEPROM_TIME_KERNEL, AU_EEPROM_SIZE_KERNEL, AU_EEPROM_DCRC_KERNEL,}, \
+	{AU_EEPROM_TIME_APP, AU_EEPROM_SIZE_APP, AU_EEPROM_DCRC_APP,}, \
+	{AU_EEPROM_TIME_DISK, AU_EEPROM_SIZE_DISK, AU_EEPROM_DCRC_DISK,}, \
+	{AU_EEPROM_TIME_POSTINST, AU_EEPROM_SIZE_POSTINST, AU_EEPROM_DCRC_POSTINST,} \
+	};
+/* array of flash areas start and end addresses */
+struct flash_layout aufl_layout[AU_MAXFILES - 3] = { \
+	{AU_FL_FIRMWARE_ST, AU_FL_FIRMWARE_ND,}, \
+	{AU_FL_KERNEL_ST, AU_FL_KERNEL_ND,}, \
+	{AU_FL_APP_ST, AU_FL_APP_ND,}, \
+	{AU_FL_DISK_ST, AU_FL_DISK_ND,}, \
+};
+/* convert the index into aufile[] to an index into aufl_layout[] */
+#define FIDX_TO_LIDX(idx) ((idx) - 2)
+
+/* where to load files into memory */
+#define LOAD_ADDR ((unsigned char *)0x0C100100)
+/* where to build strings in memory - 256 bytes should be enough */
+#define STRING_ADDR ((char *)0x0C100000)
+/* the app is the largest image */
+#define MAX_LOADSZ ausize[IDX_APP]
+
+/* externals */
+extern int fat_register_device(block_dev_desc_t *, int);
+extern int file_fat_detectfs(void);
+extern long file_fat_read(const char *, void *, unsigned long);
+extern int i2c_read (unsigned char, unsigned int, int , unsigned char* , int);
+extern int i2c_write (uchar, uint, int , uchar* , int);
+#ifdef CONFIG_VFD
+extern int trab_vfd (ulong);
+extern int transfer_pic(unsigned char, unsigned char *, int, int);
+#endif
+/* change char* to void* to shutup the compiler */
+extern int i2c_write_multiple (uchar, uint, int, void *, int);
+extern int i2c_read_multiple (uchar, uint, int, void *, int);
+extern block_dev_desc_t *get_dev (char*, int);
+
+int
+au_check_valid(int idx, long nbytes)
+{
+	image_header_t *hdr;
+	unsigned long checksum;
+	unsigned char buf[4];
+
+	hdr = (image_header_t *)LOAD_ADDR;
+	/* check the easy ones first */
+#undef CHECK_VALID_DEBUG
+#ifdef CHECK_VALID_DEBUG
+	printf("magic %#x %#x ", ntohl(hdr->ih_magic), IH_MAGIC);
+	printf("arch %#x %#x ", hdr->ih_arch, IH_CPU_ARM);
+	printf("size %#x %#lx ", ntohl(hdr->ih_size), nbytes);
+	printf("type %#x %#x ", hdr->ih_type, IH_TYPE_KERNEL);
+#endif
+	if (ntohl(hdr->ih_magic) != IH_MAGIC ||
+	    hdr->ih_arch != IH_CPU_ARM ||
+	    nbytes != (sizeof(*hdr) + ntohl(hdr->ih_size)))
+	{
+		printf ("Image %s bad MAGIC or ARCH or SIZE\n", aufile[idx]);
+		return -1;
+	}
+	/* check the hdr CRC */
+	checksum = ntohl(hdr->ih_hcrc);
+	hdr->ih_hcrc = 0;
+
+	if (crc32 (0, (char *)hdr, sizeof(*hdr)) != checksum) {
+		printf ("Image %s bad header checksum\n", aufile[idx]);
+		return -1;
+	}
+	hdr->ih_hcrc = htonl(checksum);
+	/* check the data CRC */
+	checksum = ntohl(hdr->ih_dcrc);
+
+	if (crc32 (0, (char *)(LOAD_ADDR + sizeof(*hdr)), ntohl(hdr->ih_size))
+		!= checksum)
+	{
+		printf ("Image %s bad data checksum\n", aufile[idx]);
+		return -1;
+	}
+	/* check the type - could do this all in one gigantic if() */
+	if ((idx == IDX_FIRMWARE) && (hdr->ih_type != IH_TYPE_FIRMWARE)) {
+		printf ("Image %s wrong type\n", aufile[idx]);
+		return -1;
+	}
+	if ((idx == IDX_KERNEL) && (hdr->ih_type != IH_TYPE_KERNEL)) {
+		printf ("Image %s wrong type\n", aufile[idx]);
+		return -1;
+	}
+	if ((idx == IDX_DISK || idx == IDX_APP)
+		&& (hdr->ih_type != IH_TYPE_RAMDISK))
+	{
+		printf ("Image %s wrong type\n", aufile[idx]);
+		return -1;
+	}
+	if ((idx == IDX_PREPARE || idx == IDX_PREINST || idx == IDX_POSTINST)
+		&& (hdr->ih_type != IH_TYPE_SCRIPT))
+	{
+		printf ("Image %s wrong type\n", aufile[idx]);
+		return -1;
+	}
+	/* special case for prepare.img */
+	if (idx == IDX_PREPARE)
+		return 0;
+	/* check the size does not exceed space in flash */
+	if ((ausize[idx] != 0) && (ausize[idx] < ntohl(hdr->ih_size))) {
+		printf ("Image %s is bigger than FLASH\n", aufile[idx]);
+		return -1;
+	}
+	/* check the time stamp from the EEPROM */
+	/* read it in */
+	i2c_read_multiple(0x54, auee_off[idx].time, 1, buf, sizeof(buf));
+#ifdef CHECK_VALID_DEBUG
+	printf ("buf[0] %#x buf[1] %#x buf[2] %#x buf[3] %#x "
+		"as int %#x time %#x\n",
+		buf[0], buf[1], buf[2], buf[3],
+		*((unsigned int *)buf), ntohl(hdr->ih_time));
+#endif
+	/* check it */
+	if (*((unsigned int *)buf) >= ntohl(hdr->ih_time)) {
+		printf ("Image %s is too old\n", aufile[idx]);
+		return -1;
+	}
+
+	return 0;
+}
+
+/* power control defines */
+#define CPLD_VFD_BK ((volatile char *)0x04038002)
+#define POWER_OFF (1 << 1)
+
+int
+au_do_update(int idx, long sz, int repeat)
+{
+	image_header_t *hdr;
+	char *addr;
+	long start, end;
+	char *strbuf = STRING_ADDR;
+	int off;
+	uint nbytes;
+
+	hdr = (image_header_t *)LOAD_ADDR;
+
+	/* disable the power switch */
+	*CPLD_VFD_BK |= POWER_OFF;
+
+	/* execute a script */
+	if (hdr->ih_type == IH_TYPE_SCRIPT) {
+		addr = (char *)((char *)hdr + sizeof(*hdr));
+		/* stick a NULL at the end of the script, otherwise */
+		/* parse_string_outer() runs off the end. */
+		addr[ntohl(hdr->ih_size)] = 0;
+		addr += 8;
+		parse_string_outer(addr, FLAG_PARSE_SEMICOLON);
+		return 0;
+	}
+
+	start = aufl_layout[FIDX_TO_LIDX(idx)].start;
+	end = aufl_layout[FIDX_TO_LIDX(idx)].end;
+
+	/* unprotect the address range */
+	/* this assumes that ONLY the firmware is protected! */
+	if (idx == IDX_FIRMWARE) {
+#undef AU_UPDATE_TEST
+#ifdef AU_UPDATE_TEST
+		/* erase it where Linux goes */
+		start = aufl_layout[1].start;
+		end = aufl_layout[1].end;
+#endif
+		debug ("protect off %lx %lx\n", start, end);
+		sprintf(strbuf, "protect off %lx %lx\n", start, end);
+		parse_string_outer(strbuf, FLAG_PARSE_SEMICOLON);
+	}
+
+	/*
+	 * erase the address range. Multiple erases seem to cause
+	 * problems.
+	 */
+	if (repeat == 0) {
+		debug ("erase %lx %lx\n", start, end);
+		sprintf(strbuf, "erase %lx %lx\n", start, end);
+		parse_string_outer(strbuf, FLAG_PARSE_SEMICOLON);
+	}
+	wait_ms(100);
+	/* strip the header - except for the kernel and app */
+	if (idx == IDX_FIRMWARE || idx == IDX_DISK) {
+		addr = (char *)((char *)hdr + sizeof(*hdr));
+#ifdef AU_UPDATE_TEST
+		/* copy it to where Linux goes */
+		if (idx == IDX_FIRMWARE)
+			start = aufl_layout[1].start;
+#endif
+		off = 0;
+		nbytes = ntohl(hdr->ih_size);
+	} else {
+		addr = (char *)hdr;
+		off = sizeof(*hdr);
+		nbytes = sizeof(*hdr) + ntohl(hdr->ih_size);
+	}
+
+	/* copy the data from RAM to FLASH */
+	debug ("cp.b %p %lx %x\n", addr, start, nbytes);
+	sprintf(strbuf, "cp.b %p %lx %x\n", addr, start, nbytes);
+	parse_string_outer(strbuf, FLAG_PARSE_SEMICOLON);
+
+	/* check the dcrc of the copy */
+	if (crc32 (0, (char *)(start + off), ntohl(hdr->ih_size)) != ntohl(hdr->ih_dcrc)) {
+		printf ("Image %s Bad Data Checksum After COPY\n", aufile[idx]);
+		return -1;
+	}
+
+	/* protect the address range */
+	/* this assumes that ONLY the firmware is protected! */
+	if (idx == IDX_FIRMWARE) {
+		debug ("protect on %lx %lx\n", start, end);
+		sprintf(strbuf, "protect on %lx %lx\n", start, end);
+		parse_string_outer(strbuf, FLAG_PARSE_SEMICOLON);
+	}
+	return 0;
+}
+
+int
+au_update_eeprom(int idx)
+{
+	image_header_t *hdr;
+	int off;
+	uint32_t val;
+
+	hdr = (image_header_t *)LOAD_ADDR;
+	/* write the time field into EEPROM */
+	off = auee_off[idx].time;
+	val = ntohl(hdr->ih_time);
+	i2c_write_multiple(0x54, off, 1, &val, sizeof(val));
+	/* write the size field into EEPROM */
+	off = auee_off[idx].size;
+	val = ntohl(hdr->ih_size);
+	i2c_write_multiple(0x54, off, 1, &val, sizeof(val));
+	/* write the dcrc field into EEPROM */
+	off = auee_off[idx].dcrc;
+	val = ntohl(hdr->ih_dcrc);
+	i2c_write_multiple(0x54, off, 1, &val, sizeof(val));
+	/* enable the power switch */
+	*CPLD_VFD_BK &= ~POWER_OFF;
+	return 0;
+}
+
+/*
+ * this is called from board_init() after the hardware has been set up
+ * and is usable. That seems like a good time to do this.
+ * Right now the return value is ignored.
+ */
+int
+do_auto_update(void)
+{
+	block_dev_desc_t *stor_dev;
+	long sz;
+	int i, res, bitmap_first, cnt, old_ctrlc, got_ctrlc;
+	char *env;
+	long start, end;
+
+#undef ERASE_EEPROM
+#ifdef ERASE_EEPROM
+	int arr[18];
+	memset(arr, 0, sizeof(arr));
+	i2c_write_multiple(0x54, 64, 1, arr, sizeof(arr));
+#endif
+	au_usb_stor_curr_dev = -1;
+	/* start USB */
+	if (usb_stop() < 0) {
+		debug ("usb_stop failed\n");
+		return -1;
+	}
+	if (usb_init() < 0) {
+		debug ("usb_init failed\n");
+		return -1;
+	}
+	/*
+	 * check whether a storage device is attached (assume that it's
+	 * a USB memory stick, since nothing else should be attached).
+	 */
+	au_usb_stor_curr_dev = usb_stor_scan(1);
+	if (au_usb_stor_curr_dev == -1) {
+		debug ("No device found. Not initialized?\n");
+		return -1;
+	}
+	/* check whether it has a partition table */
+	stor_dev = get_dev("usb", 0);
+	if (stor_dev == NULL) {
+		debug ("uknown device type\n");
+		return -1;
+	}
+	if (fat_register_device(stor_dev, 1) != 0) {
+		debug ("Unable to use USB %d:%d for fatls\n",
+			au_usb_stor_curr_dev, 1);
+		return -1;
+	}
+	if (file_fat_detectfs() != 0) {
+		debug ("file_fat_detectfs failed\n");
+	}
+
+	/* initialize the array of file names */
+	memset(aufile, 0, sizeof(aufile));
+	aufile[IDX_PREPARE] = AU_PREPARE;
+	aufile[IDX_PREINST] = AU_PREINST;
+	aufile[IDX_FIRMWARE] = AU_FIRMWARE;
+	aufile[IDX_KERNEL] = AU_KERNEL;
+	aufile[IDX_APP] = AU_APP;
+	aufile[IDX_DISK] = AU_DISK;
+	aufile[IDX_POSTINST] = AU_POSTINST;
+	/* initialize the array of flash sizes */
+	memset(ausize, 0, sizeof(ausize));
+	ausize[IDX_FIRMWARE] = (AU_FL_FIRMWARE_ND + 1) - AU_FL_FIRMWARE_ST;
+	ausize[IDX_KERNEL] = (AU_FL_KERNEL_ND + 1) - AU_FL_KERNEL_ST;
+	ausize[IDX_APP] = (AU_FL_APP_ND + 1) - AU_FL_APP_ST;
+	ausize[IDX_DISK] = (AU_FL_DISK_ND + 1) - AU_FL_DISK_ST;
+	/*
+	 * now check whether start and end are defined using environment
+	 * variables.
+	 */
+	start = -1;
+	end = 0;
+	env = getenv("firmware_st");
+	if (env != NULL)
+		start = simple_strtoul(env, NULL, 16);
+	env = getenv("firmware_nd");
+	if (env != NULL)
+		end = simple_strtoul(env, NULL, 16);
+	if (start >= 0 && end && end > start) {
+		ausize[IDX_FIRMWARE] = (end + 1) - start;
+		aufl_layout[0].start = start;
+		aufl_layout[0].end = end;
+	}
+	start = -1;
+	end = 0;
+	env = getenv("kernel_st");
+	if (env != NULL)
+		start = simple_strtoul(env, NULL, 16);
+	env = getenv("kernel_nd");
+	if (env != NULL)
+		end = simple_strtoul(env, NULL, 16);
+	if (start >= 0 && end && end > start) {
+		ausize[IDX_KERNEL] = (end + 1) - start;
+		aufl_layout[1].start = start;
+		aufl_layout[1].end = end;
+	}
+	start = -1;
+	end = 0;
+	env = getenv("app_st");
+	if (env != NULL)
+		start = simple_strtoul(env, NULL, 16);
+	env = getenv("app_nd");
+	if (env != NULL)
+		end = simple_strtoul(env, NULL, 16);
+	if (start >= 0 && end && end > start) {
+		ausize[IDX_APP] = (end + 1) - start;
+		aufl_layout[2].start = start;
+		aufl_layout[2].end = end;
+	}
+	start = -1;
+	end = 0;
+	env = getenv("disk_st");
+	if (env != NULL)
+		start = simple_strtoul(env, NULL, 16);
+	env = getenv("disk_nd");
+	if (env != NULL)
+		end = simple_strtoul(env, NULL, 16);
+	if (start >= 0 && end && end > start) {
+		ausize[IDX_DISK] = (end + 1) - start;
+		aufl_layout[3].start = start;
+		aufl_layout[3].end = end;
+	}
+	/* make sure that we see CTRL-C and save the old state */
+	old_ctrlc = disable_ctrlc(0);
+
+	bitmap_first = 0;
+	/* just loop thru all the possible files */
+	for (i = 0; i < AU_MAXFILES; i++) {
+		sz = file_fat_read(aufile[i], LOAD_ADDR, MAX_LOADSZ);
+		debug ("read %s sz %ld hdr %d\n",
+			aufile[i], sz, sizeof(image_header_t));
+		if (sz <= 0 || sz <= sizeof(image_header_t)) {
+			debug ("%s not found\n", aufile[i]);
+			continue;
+		}
+		if (au_check_valid(i, sz) < 0) {
+			debug ("%s not valid\n", aufile[i]);
+			continue;
+		}
+#ifdef CONFIG_VFD
+		/* now that we have a valid file we can display the */
+		/* bitmap. */
+		if (bitmap_first == 0) {
+			env = getenv("bitmap2");
+			if (env == NULL) {
+				trab_vfd(0);
+			} else {
+				/* not so simple - bitmap2 is supposed to */
+				/* contain the address of the bitmap */
+				env = (char *)simple_strtoul(env, NULL, 16);
+/* NOTE: these are taken from vfd_logo.h. If that file changes then */
+/* these defines MUST also be updated! These may be wrong for bitmap2. */
+#define VFD_LOGO_WIDTH 112
+#define VFD_LOGO_HEIGHT 72
+				/* must call transfer_pic directly */
+				transfer_pic(3, env, VFD_LOGO_HEIGHT, VFD_LOGO_WIDTH);
+			}
+			bitmap_first = 1;
+		}
+#endif
+		/* this is really not a good idea, but it's what the */
+		/* customer wants. */
+		cnt = 0;
+		got_ctrlc = 0;
+		do {
+			res = au_do_update(i, sz, cnt);
+			/* let the user break out of the loop */
+			if (ctrlc() || had_ctrlc()) {
+				clear_ctrlc();
+				if (res < 0)
+					got_ctrlc = 1;
+				break;
+			}
+			cnt++;
+#ifdef AU_TEST_ONLY
+		} while (res < 0 && cnt < 3);
+		if (cnt < 3)
+#else
+		} while (res < 0);
+#endif
+		/*
+		 * it doesn't make sense to update the EEPROM if the
+		 * update was interrupted by the user due to errors.
+		 */
+		if (got_ctrlc == 0)
+			au_update_eeprom(i);
+		else
+			/* enable the power switch */
+			*CPLD_VFD_BK &= ~POWER_OFF;
+	}
+	usb_stop();
+	/* restore the old state */
+	disable_ctrlc(old_ctrlc);
+	return 0;
+}
+#endif /* CONFIG_AUTO_UPDATE */

board/trab/cmd_trab.c

@@ -0,0 +1,821 @@
+/*
+ * (C) Copyright 2003
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <s3c2400.h>
+
+/*
+ * TRAB board specific commands. Especially commands for burn-in and function
+ * test.
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+
+/* limits for valid range of VCC5V in mV  */
+#define VCC5V_MIN       4500
+#define VCC5V_MAX       5500
+
+/*
+ * Test strings for EEPROM test. Length of string 2 must not exceed length of
+ * string 1. Otherwise a buffer overrun could occur!
+ */
+#define EEPROM_TEST_STRING_1    "0987654321 :tset a si siht"
+#define EEPROM_TEST_STRING_2    "this is a test: 1234567890"
+
+/*
+ * min/max limits for valid contact temperature during burn in test (in
+ * degree Centigrade * 100)
+ */
+#define MIN_CONTACT_TEMP        -1000
+#define MAX_CONTACT_TEMP        +9000
+
+/* blinking frequency of status LED */
+#define LED_BLINK_FREQ          5
+
+/* delay time between burn in cycles in seconds */
+#ifndef BURN_IN_CYCLE_DELAY     /* if not defined in include/configs/trab.h */
+#define BURN_IN_CYCLE_DELAY     5
+#endif
+
+/* physical SRAM parameters */
+#define SRAM_ADDR       0x02000000 /* GCS1 */
+#define SRAM_SIZE       0x40000 /* 256 kByte */
+
+/* CPLD-Register for controlling TRAB hardware functions */
+#define CPLD_BUTTONS            ((volatile unsigned long *)0x04020000)
+#define CPLD_FILL_LEVEL         ((volatile unsigned long *)0x04008000)
+#define CPLD_ROTARY_SWITCH      ((volatile unsigned long *)0x04018000)
+#define CPLD_RS485_RE           ((volatile unsigned long *)0x04028000)
+
+/* I2C EEPROM device address */
+#define I2C_EEPROM_DEV_ADDR     0x54
+
+/* EEPROM address map */
+#define EE_ADDR_TEST                    128
+#define EE_ADDR_MAX_CYCLES              256
+#define EE_ADDR_STATUS                  258
+#define EE_ADDR_PASS_CYCLES             259
+#define EE_ADDR_FIRST_ERROR_CYCLE       261
+#define EE_ADDR_FIRST_ERROR_NUM         263
+#define EE_ADDR_FIRST_ERROR_NAME        264
+#define EE_ADDR_ACT_CYCLE               280
+
+/* Bit definitions for ADCCON */
+#define ADC_ENABLE_START     0x1
+#define ADC_READ_START       0x2
+#define ADC_STDBM            0x4
+#define ADC_INP_AIN0         (0x0 << 3)
+#define ADC_INP_AIN1         (0x1 << 3)
+#define ADC_INP_AIN2         (0x2 << 3)
+#define ADC_INP_AIN3         (0x3 << 3)
+#define ADC_INP_AIN4         (0x4 << 3)
+#define ADC_INP_AIN5         (0x5 << 3)
+#define ADC_INP_AIN6         (0x6 << 3)
+#define ADC_INP_AIN7         (0x7 << 3)
+#define ADC_PRSCEN           0x4000
+#define ADC_ECFLG            0x800
+
+/* misc */
+
+/* externals */
+extern int memory_post_tests (unsigned long start, unsigned long size);
+extern int i2c_write (uchar, uint, int , uchar* , int);
+extern int i2c_read (uchar, uint, int , uchar* , int);
+extern void tsc2000_reg_init (void);
+extern s32 tsc2000_contact_temp (void);
+extern void spi_init(void);
+
+/* function declarations */
+int do_dip (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+int do_vcc5v (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+int do_burn_in (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+int do_contact_temp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+int do_burn_in_status (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+int i2c_write_multiple (uchar chip, uint addr, int alen,
+			uchar *buffer, int len);
+int i2c_read_multiple (uchar chip, uint addr, int alen,
+			uchar *buffer, int len);
+
+/* helper functions */
+static void adc_init (void);
+static int adc_read (unsigned int channel);
+static int read_dip (void);
+static int read_vcc5v (void);
+static int test_dip (void);
+static int test_vcc5v (void);
+static int test_rotary_switch (void);
+static int test_sram (void);
+static int test_eeprom (void);
+static int test_contact_temp (void);
+static void led_set (unsigned int);
+static void led_blink (void);
+static void led_init (void);
+static void sdelay (unsigned long seconds); /* delay in seconds */
+static int dummy (void);
+static int read_max_cycles(void);
+static void test_function_table_init (void);
+static void global_vars_init (void);
+static int global_vars_write_to_eeprom (void);
+
+/* globals */
+u16 max_cycles;
+u8 status;
+u16 pass_cycles;
+u16 first_error_cycle;
+u8 first_error_num;
+unsigned char first_error_name[16];
+u16 act_cycle;
+
+typedef struct test_function_s {
+	unsigned char *name;
+        int (*pf)(void);
+} test_function_t;
+
+/* max number of Burn In Functions */
+#define BIF_MAX 6
+
+/* table with burn in functions */
+test_function_t test_function[BIF_MAX];
+
+
+int do_burn_in (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+        int i;
+        int cycle_status;
+
+        if (argc > 1) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+        led_init ();
+        global_vars_init ();
+        test_function_table_init ();
+
+        if (global_vars_write_to_eeprom () != 0) {
+                printf ("%s: error writing global_vars to eeprom\n",
+                        __FUNCTION__);
+                return (1);
+        }
+
+        if (read_max_cycles () != 0) {
+                printf ("%s: error reading max_cycles from eeprom\n",
+                        __FUNCTION__);
+                return (1);
+        }
+
+        if (max_cycles == 0) {
+                printf ("%s: error, burn in max_cycles = 0\n", __FUNCTION__);
+                return (1);
+        }
+
+        status = 0;
+        for (act_cycle = 1; act_cycle <= max_cycles; act_cycle++) {
+
+                cycle_status = 0;
+                for (i = 0; i < BIF_MAX; i++) {
+
+                        /* call test function */
+                        if ((*test_function[i].pf)() != 0) {
+                                printf ("error in %s test\n",
+                                        test_function[i].name);
+
+                                /* is it the first error? */
+                                if (status == 0) {
+                                        status = 1;
+                                        first_error_cycle = act_cycle;
+
+                                        /* do not use error_num 0 */
+                                        first_error_num = i+1;
+                                        strncpy (first_error_name,
+                                                 test_function[i].name,
+                                                 sizeof (first_error_name));
+                                        led_set (0);
+                                }
+                                cycle_status = 1;
+                        }
+                }
+                /* were all tests of actual cycle OK? */
+                if (cycle_status == 0)
+                        pass_cycles++;
+
+                /* set status LED if no error is occoured since yet */
+                if (status == 0)
+                        led_set (1);
+
+                printf ("%s: cycle %d finished\n", __FUNCTION__, act_cycle);
+
+                /* pause between cycles */
+                sdelay (BURN_IN_CYCLE_DELAY);
+        }
+
+        if (global_vars_write_to_eeprom () != 0) {
+                led_set (0);
+                printf ("%s: error writing global_vars to eeprom\n",
+                        __FUNCTION__);
+                status = 1;
+        }
+
+        if (status == 0) {
+                led_blink ();   /* endless loop!! */
+                return (0);
+        } else {
+                led_set (0);
+                return (1);
+        }
+}
+
+U_BOOT_CMD(
+ 	burn_in,	1,	1,	do_burn_in,
+ 	"burn_in - start burn-in test application on TRAB\n",
+ 	"\n"
+ 	"    -  start burn-in test application\n"
+        "       The burn-in test could took a while to finish!\n"
+        "       The content of the onboard EEPROM is modified!\n"
+);
+
+
+int do_dip (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+        int i, dip;
+
+      	if (argc > 1) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+        if ((dip = read_dip ()) == -1) {
+                return 1;
+        }
+
+        for (i = 0; i < 4; i++) {
+                if ((dip & (1 << i)) == 0)
+                        printf("0");
+                else
+                        printf("1");
+        }
+        printf("\n");
+
+	return 0;
+}
+
+U_BOOT_CMD(
+ 	dip,	1,	1,	do_dip,
+ 	"dip     - read dip switch on TRAB\n",
+ 	"\n"
+ 	"    - read state of dip switch (S1) on TRAB board\n"
+        "      read sequence: 1-2-3-4; ON=1; OFF=0; e.g.: \"0100\"\n"
+);
+
+
+int do_vcc5v (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+        int vcc5v;
+
+        if (argc > 1) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+        if ((vcc5v = read_vcc5v ()) == -1) {
+                return (1);
+        }
+
+        printf ("%d", (vcc5v / 1000));
+        printf (".%d", (vcc5v % 1000) / 100);
+        printf ("%d V\n", (vcc5v % 100) / 10) ;
+
+	return 0;
+}
+
+U_BOOT_CMD(
+ 	vcc5v,	1,	1,	do_vcc5v,
+ 	"vcc5v   - read VCC5V on TRAB\n",
+ 	"\n"
+ 	"    - read actual value of voltage VCC5V\n"
+);
+
+
+int do_contact_temp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+        int contact_temp;
+
+        if (argc > 1) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+        spi_init ();
+        tsc2000_reg_init ();
+
+        contact_temp = tsc2000_contact_temp();
+        printf ("%d degree C * 100\n", contact_temp) ;
+
+	return 0;
+}
+
+U_BOOT_CMD(
+ 	c_temp,	1,	1,	do_contact_temp,
+ 	"c_temp  - read contact temperature on TRAB\n",
+ 	"\n"
+ 	"    -  reads the onboard temperature (=contact temperature)\n"
+);
+
+
+int do_burn_in_status (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+        if (argc > 1) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+        if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_STATUS, 1,
+                                (unsigned char*) &status, 1)) {
+                return (1);
+        }
+        if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_PASS_CYCLES, 1,
+                                (unsigned char*) &pass_cycles, 2)) {
+                return (1);
+        }
+        if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_CYCLE,
+                                1, (unsigned char*) &first_error_cycle, 2)) {
+                return (1);
+        }
+        if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NUM,
+                                1, (unsigned char*) &first_error_num, 1)) {
+                return (1);
+        }
+        if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NAME,
+                               1, first_error_name,
+                               sizeof (first_error_name))) {
+                return (1);
+        }
+
+        if (read_max_cycles () != 0) {
+                return (1);
+        }
+
+        printf ("max_cycles = %d\n", max_cycles);
+        printf ("status = %d\n", status);
+        printf ("pass_cycles = %d\n", pass_cycles);
+        printf ("first_error_cycle = %d\n", first_error_cycle);
+        printf ("first_error_num = %d\n", first_error_num);
+        printf ("first_error_name = %.*s\n",(int) sizeof(first_error_name),
+                first_error_name);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+ 	bis,	1,	1,	do_burn_in_status,
+ 	"bis     - print burn in status on TRAB\n",
+ 	"\n"
+ 	"    -  prints the status variables of the last burn in test\n"
+        "       stored in the onboard EEPROM on TRAB board\n"
+);
+
+static int read_dip (void)
+{
+        unsigned int result = 0;
+        int adc_val;
+        int i;
+
+	/***********************************************************
+	 DIP switch connection (according to wa4-cpu.sp.301.pdf, page 3):
+	   SW1 - AIN4
+	   SW2 - AIN5
+	   SW3 - AIN6
+	   SW4 - AIN7
+
+	   "On" DIP switch position short-circuits the voltage from
+	   the input channel (i.e. '0' conversion result means "on").
+	*************************************************************/
+
+	for (i = 7; i > 3; i--) {
+
+                if ((adc_val = adc_read (i)) == -1) {
+                        printf ("%s: Channel %d could not be read\n",
+                                 __FUNCTION__, i);
+                        return (-1);
+                }
+
+		/*
+		 * Input voltage (switch open) is 1.8 V.
+		 * (Vin_High/VRef)*adc_res = (1,8V/2,5V)*1023) = 736
+		 * Set trigger at halve that value.
+		 */
+		if (adc_val < 368)
+                        result |= (1 << (i-4));
+        }
+        return (result);
+}
+
+
+static int read_vcc5v (void)
+{
+        s32 result;
+
+        /* VCC5V is connected to channel 2 */
+
+        if ((result = adc_read (2)) == -1) {
+                printf ("%s: VCC5V could not be read\n", __FUNCTION__);
+                return (-1);
+        }
+        /*
+         * Calculate voltage value. Split in two parts because there is no
+         * floating point support.  VCC5V is connected over an resistor divider:
+         * VCC5V=ADCval*2,5V/1023*(10K+30K)/10K.
+         */
+        result = result * 10 * 1000 / 1023; /* result in mV */
+
+        return (result);
+}
+
+
+static int test_dip (void)
+{
+        static int first_run = 1;
+        static int first_dip;
+
+        if (first_run) {
+                if ((first_dip = read_dip ()) == -1) {
+                        return (1);
+                }
+                first_run = 0;
+                debug ("%s: first_dip=%d\n", __FUNCTION__, first_dip);
+        }
+        if (first_dip != read_dip ()) {
+                return (1);
+        } else {
+                return (0);
+        }
+}
+
+
+static int test_vcc5v (void)
+{
+        int vcc5v;
+
+        if ((vcc5v = read_vcc5v ()) == -1) {
+                return (1);
+        }
+
+        if ((vcc5v > VCC5V_MAX) || (vcc5v < VCC5V_MIN)) {
+                return (1);
+        } else {
+                return (0);
+        }
+}
+
+
+static int test_rotary_switch (void)
+{
+        static int first_run = 1;
+        static int first_rs;
+
+        if (first_run) {
+                /*
+                 * clear bits in CPLD, because they have random values after
+                 * power-up or reset.
+                 */
+                *CPLD_ROTARY_SWITCH |= (1 << 16) | (1 << 17);
+
+                first_rs = ((*CPLD_ROTARY_SWITCH >> 16) & 0x7);
+                first_run = 0;
+                debug ("%s: first_rs=%d\n", __FUNCTION__, first_rs);
+        }
+
+        if (first_rs != ((*CPLD_ROTARY_SWITCH >> 16) & 0x7)) {
+                return (1);
+        } else {
+                return (0);
+        }
+}
+
+
+static int test_sram (void)
+{
+        return (memory_post_tests (SRAM_ADDR, SRAM_SIZE));
+}
+
+
+static int test_eeprom (void)
+{
+        unsigned char temp[sizeof (EEPROM_TEST_STRING_1)];
+        int result = 0;
+
+        /* write test string 1, read back and verify */
+        if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1,
+                                EEPROM_TEST_STRING_1,
+                                sizeof (EEPROM_TEST_STRING_1))) {
+                return (1);
+        }
+
+        if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1,
+                               temp, sizeof (EEPROM_TEST_STRING_1))) {
+                return (1);
+        }
+
+        if (strcmp (temp, EEPROM_TEST_STRING_1) != 0) {
+                result = 1;
+                printf ("%s: error; read_str = \"%s\"\n", __FUNCTION__, temp);
+        }
+
+        /* write test string 2, read back and verify */
+        if (result == 0) {
+                if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1,
+                                        EEPROM_TEST_STRING_2,
+                                        sizeof (EEPROM_TEST_STRING_2))) {
+                        return (1);
+                }
+
+                if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1,
+                                       temp, sizeof (EEPROM_TEST_STRING_2))) {
+                        return (1);
+                }
+
+                if (strcmp (temp, EEPROM_TEST_STRING_2) != 0) {
+                        result = 1;
+                        printf ("%s: error; read str = \"%s\"\n",
+                                __FUNCTION__, temp);
+                }
+        }
+        return (result);
+}
+
+
+static int test_contact_temp (void)
+{
+        int contact_temp;
+
+        spi_init ();
+        contact_temp = tsc2000_contact_temp ();
+
+        if ((contact_temp < MIN_CONTACT_TEMP)
+            || (contact_temp > MAX_CONTACT_TEMP))
+                return (1);
+        else
+                return (0);
+}
+
+
+int i2c_write_multiple (uchar chip, uint addr, int alen,
+			uchar *buffer, int len)
+{
+        int i;
+
+        if (alen != 1) {
+                printf ("%s: addr len other than 1 not supported\n",
+                         __FUNCTION__);
+                return (1);
+        }
+
+        for (i = 0; i < len; i++) {
+                if (i2c_write (chip, addr+i, alen, buffer+i, 1)) {
+                        printf ("%s: could not write to i2c device %d"
+                                 ", addr %d\n", __FUNCTION__, chip, addr);
+                        return (1);
+                }
+#if 0
+                printf ("chip=%#x, addr+i=%#x+%d=%p, alen=%d, *buffer+i="
+                        "%#x+%d=%p=\"%.1s\"\n", chip, addr, i, addr+i,
+                        alen, buffer, i, buffer+i, buffer+i);
+#endif
+
+                udelay (30000);
+        }
+        return (0);
+}
+
+
+int i2c_read_multiple ( uchar chip, uint addr, int alen,
+			uchar *buffer, int len)
+{
+        int i;
+
+        if (alen != 1) {
+                printf ("%s: addr len other than 1 not supported\n",
+                         __FUNCTION__);
+                return (1);
+        }
+
+        for (i = 0; i < len; i++) {
+                if (i2c_read (chip, addr+i, alen, buffer+i, 1)) {
+                        printf ("%s: could not read from i2c device %#x"
+                                 ", addr %d\n", __FUNCTION__, chip, addr);
+                        return (1);
+                }
+        }
+        return (0);
+}
+
+
+static int adc_read (unsigned int channel)
+{
+        int j = 1000; /* timeout value for wait loop in us */
+        S3C2400_ADC *padc;
+
+        padc = S3C2400_GetBase_ADC();
+        channel &= 0x7;
+
+        adc_init ();
+
+	debug ("%s: adccon %#x\n", __FUNCTION__, padc->ADCCON);
+
+        padc->ADCCON &= ~ADC_STDBM; /* select normal mode */
+	padc->ADCCON &= ~(0x7 << 3); /* clear the channel bits */
+        padc->ADCCON |= ((channel << 3) | ADC_ENABLE_START);
+
+        debug ("%s: reading ch %d, addcon %#x\n", __FUNCTION__,
+		(padc->ADCCON >> 3) & 0x7, padc->ADCCON);
+
+        while (j--) {
+                if ((padc->ADCCON & ADC_ENABLE_START) == 0)
+                        break;
+                udelay (1);
+        }
+
+        if (j == 0) {
+                printf("%s: ADC timeout\n", __FUNCTION__);
+                padc->ADCCON |= ADC_STDBM; /* select standby mode */
+                return -1;
+        }
+
+        padc->ADCCON |= ADC_STDBM; /* select standby mode */
+
+        debug ("%s: return %#x, adccon %#x\n", __FUNCTION__,
+		padc->ADCDAT & 0x3FF, padc->ADCCON);
+
+        return (padc->ADCDAT & 0x3FF);
+}
+
+
+static void adc_init (void)
+{
+        S3C2400_ADC *padc;
+
+        padc = S3C2400_GetBase_ADC();
+
+	padc->ADCCON &= ~(0xff << 6); /* clear prescaler bits */
+	padc->ADCCON |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */
+
+        return;
+}
+
+
+static void led_set (unsigned int state)
+{
+        S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+        led_init ();
+
+        switch (state) {
+        case 0: /* turn LED off */
+                gpio->PADAT |= (1 << 12);
+                break;
+        case 1: /* turn LED on */
+                gpio->PADAT &= ~(1 << 12);
+                break;
+        default:
+        }
+}
+
+static void led_blink (void)
+{
+        led_init ();
+
+        /* blink LED. This function does not return! */
+        while (1) {
+                led_set (1);
+                udelay (1000000 / LED_BLINK_FREQ / 2);
+                led_set (0);
+                udelay (1000000 / LED_BLINK_FREQ / 2);
+        }
+}
+
+
+static void led_init (void)
+{
+        S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+        /* configure GPA12 as output and set to High -> LED off */
+        gpio->PACON &= ~(1 << 12);
+        gpio->PADAT |= (1 << 12);
+}
+
+
+static void sdelay (unsigned long seconds)
+{
+        unsigned long i;
+
+        for (i = 0; i < seconds; i++) {
+                udelay (1000000);
+        }
+}
+
+
+static int global_vars_write_to_eeprom (void)
+{
+        if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_STATUS, 1,
+                                (unsigned char*) &status, 1)) {
+                return (1);
+        }
+        if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_PASS_CYCLES, 1,
+                                (unsigned char*) &pass_cycles, 2)) {
+                return (1);
+        }
+        if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_CYCLE,
+                                1, (unsigned char*) &first_error_cycle, 2)) {
+                return (1);
+        }
+        if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NUM,
+                                1, (unsigned char*) &first_error_num, 1)) {
+                return (1);
+        }
+        if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NAME,
+                                1, first_error_name,
+                                sizeof(first_error_name))) {
+                return (1);
+        }
+        return (0);
+}
+
+static void global_vars_init (void)
+{
+        status                  = 1; /* error */
+        pass_cycles             = 0;
+        first_error_cycle       = 0;
+        first_error_num         = 0;
+        first_error_name[0]     = '\0';
+        act_cycle               = 0;
+        max_cycles              = 0;
+}
+
+
+static void test_function_table_init (void)
+{
+        int i;
+
+  	for (i = 0; i < BIF_MAX; i++)
+		test_function[i].pf = dummy;
+
+        /*
+         * the length of "name" must not exceed 16, including the '\0'
+         * termination. See also the EEPROM address map.
+         */
+        test_function[0].pf = test_dip;
+        test_function[0].name = "dip";
+
+        test_function[1].pf = test_vcc5v;
+        test_function[1].name = "vcc5v";
+
+        test_function[2].pf = test_rotary_switch;
+        test_function[2].name = "rotary_switch";
+
+        test_function[3].pf = test_sram;
+        test_function[3].name = "sram";
+
+        test_function[4].pf = test_eeprom;
+        test_function[4].name = "eeprom";
+
+        test_function[5].pf = test_contact_temp;
+        test_function[5].name = "contact_temp";
+}
+
+
+static int read_max_cycles (void)
+{
+        if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_MAX_CYCLES, 1,
+                               (unsigned char *) &max_cycles, 2) != 0) {
+                return (1);
+        }
+
+        return (0);
+}
+
+static int dummy(void)
+{
+        return (0);
+}
+
+#endif	/* CFG_CMD_BSP */

board/trab/config.mk

@@ -8,16 +8,19 @@
 #
 
 #
-# TRAB has 1 bank of 16 MB DRAM
+# TRAB has 1 bank of 16 MB or 32 MB DRAM
 #
 # 0c00'0000 to 0e00'0000
 #
 # Linux-Kernel is expected to be at 0c00'8000, entry 0c00'8000
 #
-# we load ourself to 0cf0'0000
+# we load ourself to 0CF0'0000	/ 0DF0'0000
 #
-# download areas is 0c80'0000
+# download areas is 0C80'0000
 #
 
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
 
-TEXT_BASE = 0x0cf00000
+ifndef TEXT_BASE
+TEXT_BASE = 0x0DF00000
+endif

board/trab/memory.c

@@ -0,0 +1,484 @@
+/*
+ * (C) Copyright 2002-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* Memory test
+ *
+ * General observations:
+ * o The recommended test sequence is to test the data lines: if they are
+ *   broken, nothing else will work properly.  Then test the address
+ *   lines.  Finally, test the cells in the memory now that the test
+ *   program knows that the address and data lines work properly.
+ *   This sequence also helps isolate and identify what is faulty.
+ *
+ * o For the address line test, it is a good idea to use the base
+ *   address of the lowest memory location, which causes a '1' bit to
+ *   walk through a field of zeros on the address lines and the highest
+ *   memory location, which causes a '0' bit to walk through a field of
+ *   '1's on the address line.
+ *
+ * o Floating buses can fool memory tests if the test routine writes
+ *   a value and then reads it back immediately.  The problem is, the
+ *   write will charge the residual capacitance on the data bus so the
+ *   bus retains its state briefely.  When the test program reads the
+ *   value back immediately, the capacitance of the bus can allow it
+ *   to read back what was written, even though the memory circuitry
+ *   is broken.  To avoid this, the test program should write a test
+ *   pattern to the target location, write a different pattern elsewhere
+ *   to charge the residual capacitance in a differnt manner, then read
+ *   the target location back.
+ *
+ * o Always read the target location EXACTLY ONCE and save it in a local
+ *   variable.  The problem with reading the target location more than
+ *   once is that the second and subsequent reads may work properly,
+ *   resulting in a failed test that tells the poor technician that
+ *   "Memory error at 00000000, wrote aaaaaaaa, read aaaaaaaa" which
+ *   doesn't help him one bit and causes puzzled phone calls.  Been there,
+ *   done that.
+ *
+ * Data line test:
+ * ---------------
+ * This tests data lines for shorts and opens by forcing adjacent data
+ * to opposite states. Because the data lines could be routed in an
+ * arbitrary manner the must ensure test patterns ensure that every case
+ * is tested. By using the following series of binary patterns every
+ * combination of adjacent bits is test regardless of routing.
+ *
+ *     ...101010101010101010101010
+ *     ...110011001100110011001100
+ *     ...111100001111000011110000
+ *     ...111111110000000011111111
+ *
+ * Carrying this out, gives us six hex patterns as follows:
+ *
+ *     0xaaaaaaaaaaaaaaaa
+ *     0xcccccccccccccccc
+ *     0xf0f0f0f0f0f0f0f0
+ *     0xff00ff00ff00ff00
+ *     0xffff0000ffff0000
+ *     0xffffffff00000000
+ *
+ * To test for short and opens to other signals on our boards, we
+ * simply test with the 1's complemnt of the paterns as well, resulting
+ * in twelve patterns total.
+ *
+ * After writing a test pattern. a special pattern 0x0123456789ABCDEF is
+ * written to a different address in case the data lines are floating.
+ * Thus, if a byte lane fails, you will see part of the special
+ * pattern in that byte lane when the test runs.  For example, if the
+ * xx__xxxxxxxxxxxx byte line fails, you will see aa23aaaaaaaaaaaa
+ * (for the 'a' test pattern).
+ *
+ * Address line test:
+ * ------------------
+ *  This function performs a test to verify that all the address lines
+ *  hooked up to the RAM work properly.  If there is an address line
+ *  fault, it usually shows up as two different locations in the address
+ *  map (related by the faulty address line) mapping to one physical
+ *  memory storage location.  The artifact that shows up is writing to
+ *  the first location "changes" the second location.
+ *
+ * To test all address lines, we start with the given base address and
+ * xor the address with a '1' bit to flip one address line.  For each
+ * test, we shift the '1' bit left to test the next address line.
+ *
+ * In the actual code, we start with address sizeof(ulong) since our
+ * test pattern we use is a ulong and thus, if we tried to test lower
+ * order address bits, it wouldn't work because our pattern would
+ * overwrite itself.
+ *
+ * Example for a 4 bit address space with the base at 0000:
+ *   0000 <- base
+ *   0001 <- test 1
+ *   0010 <- test 2
+ *   0100 <- test 3
+ *   1000 <- test 4
+ * Example for a 4 bit address space with the base at 0010:
+ *   0010 <- base
+ *   0011 <- test 1
+ *   0000 <- (below the base address, skipped)
+ *   0110 <- test 2
+ *   1010 <- test 3
+ *
+ * The test locations are successively tested to make sure that they are
+ * not "mirrored" onto the base address due to a faulty address line.
+ * Note that the base and each test location are related by one address
+ * line flipped.  Note that the base address need not be all zeros.
+ *
+ * Memory tests 1-4:
+ * -----------------
+ * These tests verify RAM using sequential writes and reads
+ * to/from RAM. There are several test cases that use different patterns to
+ * verify RAM. Each test case fills a region of RAM with one pattern and
+ * then reads the region back and compares its contents with the pattern.
+ * The following patterns are used:
+ *
+ *  1a) zero pattern (0x00000000)
+ *  1b) negative pattern (0xffffffff)
+ *  1c) checkerboard pattern (0x55555555)
+ *  1d) checkerboard pattern (0xaaaaaaaa)
+ *  2)  bit-flip pattern ((1 << (offset % 32))
+ *  3)  address pattern (offset)
+ *  4)  address pattern (~offset)
+ *
+ * Being run in normal mode, the test verifies only small 4Kb
+ * regions of RAM around each 1Mb boundary. For example, for 64Mb
+ * RAM the following areas are verified: 0x00000000-0x00000800,
+ * 0x000ff800-0x00100800, 0x001ff800-0x00200800, ..., 0x03fff800-
+ * 0x04000000. If the test is run in slow-test mode, it verifies
+ * the whole RAM.
+ */
+
+/* #ifdef CONFIG_POST */
+
+#include <post.h>
+#include <watchdog.h>
+
+/* #if CONFIG_POST & CFG_POST_MEMORY */
+
+/*
+ * Define INJECT_*_ERRORS for testing error detection in the presence of
+ * _good_ hardware.
+ */
+#undef  INJECT_DATA_ERRORS
+#undef  INJECT_ADDRESS_ERRORS
+
+#ifdef INJECT_DATA_ERRORS
+#warning "Injecting data line errors for testing purposes"
+#endif
+
+#ifdef INJECT_ADDRESS_ERRORS
+#warning "Injecting address line errors for testing purposes"
+#endif
+
+
+/*
+ * This function performs a double word move from the data at
+ * the source pointer to the location at the destination pointer.
+ * This is helpful for testing memory on processors which have a 64 bit
+ * wide data bus.
+ *
+ * On those PowerPC with FPU, use assembly and a floating point move:
+ * this does a 64 bit move.
+ *
+ * For other processors, let the compiler generate the best code it can.
+ */
+static void move64(unsigned long long *src, unsigned long long *dest)
+{
+#if defined(CONFIG_MPC8260) || defined(CONFIG_MPC824X)
+	asm ("lfd  0, 0(3)\n\t" /* fpr0	  =  *scr	*/
+	 "stfd 0, 0(4)"		/* *dest  =  fpr0	*/
+	 : : : "fr0" );		/* Clobbers fr0		*/
+    return;
+#else
+	*dest = *src;
+#endif
+}
+
+/*
+ * This is 64 bit wide test patterns.  Note that they reside in ROM
+ * (which presumably works) and the tests write them to RAM which may
+ * not work.
+ *
+ * The "otherpattern" is written to drive the data bus to values other
+ * than the test pattern.  This is for detecting floating bus lines.
+ *
+ */
+const static unsigned long long pattern[] = {
+    0xaaaaaaaaaaaaaaaa,
+    0xcccccccccccccccc,
+    0xf0f0f0f0f0f0f0f0,
+    0xff00ff00ff00ff00,
+    0xffff0000ffff0000,
+    0xffffffff00000000,
+    0x00000000ffffffff,
+    0x0000ffff0000ffff,
+    0x00ff00ff00ff00ff,
+    0x0f0f0f0f0f0f0f0f,
+    0x3333333333333333,
+    0x5555555555555555};
+const unsigned long long otherpattern = 0x0123456789abcdef;
+
+
+static int memory_post_dataline(unsigned long long * pmem)
+{
+	unsigned long long temp64;
+	int num_patterns = sizeof(pattern)/ sizeof(pattern[0]);
+	int i;
+	unsigned int hi, lo, pathi, patlo;
+	int ret = 0;
+
+	for ( i = 0; i < num_patterns; i++) {
+		move64((unsigned long long *)&(pattern[i]), pmem++);
+		/*
+		 * Put a different pattern on the data lines: otherwise they
+		 * may float long enough to read back what we wrote.
+		 */
+		move64((unsigned long long *)&otherpattern, pmem--);
+		move64(pmem, &temp64);
+
+#ifdef INJECT_DATA_ERRORS
+		temp64 ^= 0x00008000;
+#endif
+
+		if (temp64 != pattern[i]){
+			pathi = (pattern[i]>>32) & 0xffffffff;
+			patlo = pattern[i] & 0xffffffff;
+
+			hi = (temp64>>32) & 0xffffffff;
+			lo = temp64 & 0xffffffff;
+
+			printf ("Memory (date line) error at %08lx, "
+				  "wrote %08x%08x, read %08x%08x !\n",
+					  (ulong)pmem, pathi, patlo, hi, lo);
+			ret = -1;
+		}
+	}
+	return ret;
+}
+
+static int memory_post_addrline(ulong *testaddr, ulong *base, ulong size)
+{
+	ulong *target;
+	ulong *end;
+	ulong readback;
+	ulong xor;
+	int   ret = 0;
+
+	end = (ulong *)((ulong)base + size);	/* pointer arith! */
+	xor = 0;
+	for(xor = sizeof(ulong); xor > 0; xor <<= 1) {
+		target = (ulong *)((ulong)testaddr ^ xor);
+		if((target >= base) && (target < end)) {
+			*testaddr = ~*target;
+			readback  = *target;
+
+#ifdef INJECT_ADDRESS_ERRORS
+			if(xor == 0x00008000) {
+				readback = *testaddr;
+			}
+#endif
+			if(readback == *testaddr) {
+				printf ("Memory (address line) error at %08lx<->%08lx, "
+				  	"XOR value %08lx !\n",
+					(ulong)testaddr, (ulong)target,
+					xor);
+				ret = -1;
+			}
+		}
+	}
+	return ret;
+}
+
+static int memory_post_test1 (unsigned long start,
+			      unsigned long size,
+			      unsigned long val)
+{
+	unsigned long i;
+	ulong *mem = (ulong *) start;
+	ulong readback;
+	int ret = 0;
+
+	for (i = 0; i < size / sizeof (ulong); i++) {
+		mem[i] = val;
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
+		readback = mem[i];
+		if (readback != val) {
+			printf ("Memory error at %08lx, "
+				  "wrote %08lx, read %08lx !\n",
+					  (ulong)(mem + i), val, readback);
+
+			ret = -1;
+			break;
+		}
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	return ret;
+}
+
+static int memory_post_test2 (unsigned long start, unsigned long size)
+{
+	unsigned long i;
+	ulong *mem = (ulong *) start;
+	ulong readback;
+	int ret = 0;
+
+	for (i = 0; i < size / sizeof (ulong); i++) {
+		mem[i] = 1 << (i % 32);
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
+		readback = mem[i];
+		if (readback != (1 << (i % 32))) {
+			printf ("Memory error at %08lx, "
+				  "wrote %08x, read %08lx !\n",
+					  (ulong)(mem + i), 1 << (i % 32), readback);
+
+			ret = -1;
+			break;
+		}
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	return ret;
+}
+
+static int memory_post_test3 (unsigned long start, unsigned long size)
+{
+	unsigned long i;
+	ulong *mem = (ulong *) start;
+	ulong readback;
+	int ret = 0;
+
+	for (i = 0; i < size / sizeof (ulong); i++) {
+		mem[i] = i;
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
+		readback = mem[i];
+		if (readback != i) {
+			printf ("Memory error at %08lx, "
+				  "wrote %08lx, read %08lx !\n",
+					  (ulong)(mem + i), i, readback);
+
+			ret = -1;
+			break;
+		}
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	return ret;
+}
+
+static int memory_post_test4 (unsigned long start, unsigned long size)
+{
+	unsigned long i;
+	ulong *mem = (ulong *) start;
+	ulong readback;
+	int ret = 0;
+
+	for (i = 0; i < size / sizeof (ulong); i++) {
+		mem[i] = ~i;
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
+		readback = mem[i];
+		if (readback != ~i) {
+			printf ("Memory error at %08lx, "
+				  "wrote %08lx, read %08lx !\n",
+					  (ulong)(mem + i), ~i, readback);
+
+			ret = -1;
+			break;
+		}
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	return ret;
+}
+
+int memory_post_tests (unsigned long start, unsigned long size)
+{
+	int ret = 0;
+
+	if (ret == 0)
+		ret = memory_post_dataline ((long long *)start);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_addrline ((long *)start, (long *)start, size);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_addrline ((long *)(start + size - 8),
+					    (long *)start, size);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_test1 (start, size, 0x00000000);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_test1 (start, size, 0xffffffff);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_test1 (start, size, 0x55555555);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_test1 (start, size, 0xaaaaaaaa);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_test2 (start, size);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_test3 (start, size);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_test4 (start, size);
+	WATCHDOG_RESET ();
+
+	return ret;
+}
+
+#if 0
+int memory_post_test (int flags)
+{
+	int ret = 0;
+	DECLARE_GLOBAL_DATA_PTR;
+	bd_t *bd = gd->bd;
+	unsigned long memsize = (bd->bi_memsize >= 256 << 20 ?
+				 256 << 20 : bd->bi_memsize) - (1 << 20);
+
+
+	if (flags & POST_SLOWTEST) {
+		ret = memory_post_tests (CFG_SDRAM_BASE, memsize);
+	} else {			/* POST_NORMAL */
+
+		unsigned long i;
+
+		for (i = 0; i < (memsize >> 20) && ret == 0; i++) {
+			if (ret == 0)
+				ret = memory_post_tests (i << 20, 0x800);
+			if (ret == 0)
+				ret = memory_post_tests ((i << 20) + 0xff800, 0x800);
+		}
+	}
+
+	return ret;
+}
+#endif 0
+
+/* #endif */ /* CONFIG_POST & CFG_POST_MEMORY */
+/* #endif */ /* CONFIG_POST */

board/trab/memsetup.S

@@ -5,7 +5,7 @@
  *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
  *
  * Modified for the TRAB board by
- * (C) Copyright 2002
+ * (C) Copyright 2002-2003
  * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
  *
  * See file CREDITS for list of people who contributed to this
@@ -101,6 +101,17 @@
 #define B5_Tacp	0x0
 #define B5_PMC	0x0	/* normal */
 
+#ifndef CONFIG_RAM_16MB		/* 32 MB RAM */
+/* Bank6 */
+#define	B6_MT	0x3	/* SDRAM */
+#define	B6_Trcd	0x0	/* 2clk */
+#define	B6_SCAN	0x1	/* 9 bit */
+
+/* Bank7 */
+#define	B7_MT	0x3	/* SDRAM */
+#define	B7_Trcd	0x0	/* 2clk */
+#define	B7_SCAN	0x1	/* 9 bit */
+#else	/* CONFIG_RAM_16MB	=  16 MB RAM */
 /* Bank6 */
 #define	B6_MT	0x3	/* SDRAM */
 #define	B6_Trcd	0x1	/* 2clk */
@@ -110,6 +121,7 @@
 #define	B7_MT	0x3	/* SDRAM */
 #define	B7_Trcd	0x1	/* 2clk */
 #define	B7_SCAN	0x0	/* 8 bit */
+#endif	/* CONFIG_RAM_16MB */
 
 /* refresh parameter */
 #define REFEN	0x1	/* enable refresh */
@@ -161,6 +173,10 @@ SMRDATA:
 	.word	((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) /* GCS6 */
 	.word	((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) /* GCS7 */
 	.word	((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+#ifndef CONFIG_RAM_16MB		/* 32 MB RAM */
+	.word	0x10	/* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 32M/32M */
+#else	/* CONFIG_RAM_16MB	=  16 MB RAM */
 	.word	0x17	/* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 16M/16M */
-	.word	0x30	/* MRSR6, CL=3clk */
-	.word	0x30	/* MRSR7 */
+#endif	/* CONFIG_RAM_16MB */
+	.word	0x20	/* MRSR6, CL=2clk */
+	.word	0x20	/* MRSR7 */

board/trab/rs485.c

@@ -0,0 +1,203 @@
+/*
+ * (C) Copyright 2003
+ * Martin Krause, TQ-Systems GmbH, <martin.krause@tqs.de>
+ *
+ * Based on cpu/arm920t/serial.c, by Gary Jennejohn
+ * (C) Copyright 2002 Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <s3c2400.h>
+#include "rs485.h"
+
+static void rs485_setbrg (void);
+static void rs485_cfgio (void);
+static void set_rs485re(unsigned char rs485re_state);
+static void set_rs485de(unsigned char rs485de_state);
+static void rs485_setbrg (void);
+#ifdef	NOT_USED
+static void trab_rs485_disable_tx(void);
+static void trab_rs485_disable_rx(void);
+#endif
+
+#define UART_NR	S3C24X0_UART1
+
+/* CPLD-Register for controlling TRAB hardware functions */
+#define CPLD_RS485_RE           ((volatile unsigned long *)0x04028000)
+
+static void rs485_setbrg (void)
+{
+	S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
+	int i;
+	unsigned int reg = 0;
+
+	/* value is calculated so : (int)(PCLK/16./baudrate) -1 */
+        /* reg = (33000000 / (16 * gd->baudrate)) - 1; */
+        reg = (33000000 / (16 * 38.400)) - 1;
+
+	/* FIFO enable, Tx/Rx FIFO clear */
+	uart->UFCON = 0x07;
+	uart->UMCON = 0x0;
+	/* Normal,No parity,1 stop,8 bit */
+	uart->ULCON = 0x3;
+	/*
+	 * tx=level,rx=edge,disable timeout int.,enable rx error int.,
+	 * normal,interrupt or polling
+	 */
+	uart->UCON = 0x245;
+	uart->UBRDIV = reg;
+
+	for (i = 0; i < 100; i++);
+}
+
+static void rs485_cfgio (void)
+{
+        S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+        gpio->PFCON &= ~(0x3 << 2);
+        gpio->PFCON |=  (0x2 << 2); /* configure GPF1 as RXD1 */
+
+        gpio->PFCON &= ~(0x3 << 6);
+        gpio->PFCON |=  (0x2 << 6); /* configure GPF3 as TXD1 */
+
+        gpio->PFUP |= (1 << 1); /* disable pullup on GPF1 */
+        gpio->PFUP |= (1 << 3); /* disable pullup on GPF3 */
+
+        gpio->PACON &= ~(1 << 11); /* set GPA11 (RS485_DE) to output */
+}
+
+/*
+ * Initialise the rs485 port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ *
+ */
+int rs485_init (void)
+{
+        rs485_cfgio ();
+        rs485_setbrg ();
+
+	return (0);
+}
+
+/*
+ * Read a single byte from the rs485 port. Returns 1 on success, 0
+ * otherwise. When the function is succesfull, the character read is
+ * written into its argument c.
+ */
+int rs485_getc (void)
+{
+	S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
+
+	/* wait for character to arrive */
+	while (!(uart->UTRSTAT & 0x1));
+
+	return uart->URXH & 0xff;
+}
+
+/*
+ * Output a single byte to the rs485 port.
+ */
+void rs485_putc (const char c)
+{
+	S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
+
+	/* wait for room in the tx FIFO */
+	while (!(uart->UTRSTAT & 0x2));
+
+	uart->UTXH = c;
+
+	/* If \n, also do \r */
+	if (c == '\n')
+		rs485_putc ('\r');
+}
+
+/*
+ * Test whether a character is in the RX buffer
+ */
+int rs485_tstc (void)
+{
+	S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
+
+	return uart->UTRSTAT & 0x1;
+}
+
+void rs485_puts (const char *s)
+{
+	while (*s) {
+		rs485_putc (*s++);
+	}
+}
+
+
+/*
+ * State table:
+ *	RE	DE	Result
+ *	1	1	XMIT
+ *	0	0	RCV
+ *	1	0	Shutdown
+ */
+
+/* function that controls the receiver enable for the rs485 */
+/* rs485re_state reflects the level (0/1) of the RE pin */
+
+static void set_rs485re(unsigned char rs485re_state)
+{
+	if(rs485re_state)
+		*CPLD_RS485_RE = 0x010000;
+	else
+		*CPLD_RS485_RE = 0x0;
+}
+
+/* function that controls the sender enable for the rs485 */
+/* rs485de_state reflects the level (0/1) of the DE pin */
+
+static void set_rs485de(unsigned char rs485de_state)
+{
+        S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+        /* This is on PORT A bit 11 */
+        if(rs485de_state)
+                gpio->PADAT |= (1 << 11);
+        else
+                gpio->PADAT &= ~(1 << 11);
+}
+
+
+void trab_rs485_enable_tx(void)
+{
+	set_rs485de(1);
+	set_rs485re(1);
+}
+
+void trab_rs485_enable_rx(void)
+{
+	set_rs485re(0);
+	set_rs485de(0);
+}
+
+#ifdef	NOT_USED
+static void trab_rs485_disable_tx(void)
+{
+	set_rs485de(0);
+}
+
+static void trab_rs485_disable_rx(void)
+{
+	set_rs485re(1);
+}
+#endif

board/trab/rs485.h

@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2003
+ * Martin Krause, TQ-Systems GmbH, <martin.krause@tqs.de>
+ *
+ * Based on cpu/arm920t/serial.c, by Gary Jennejohn
+ * (C) Copyright 2002 Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef _RS485_H_
+#define _RS485_H_
+
+#include <s3c2400.h>
+
+int rs485_init (void);
+int rs485_getc (void);
+void rs485_putc (const char c);
+int rs485_tstc (void);
+void rs485_puts (const char *s);
+void trab_rs485_enable_tx(void);
+void trab_rs485_enable_rx(void);
+
+#endif	/* _RS485_H_ */