Code cleanup

priority; configure critical interrupts to be handled like external
  interrupts

CHANGELOG

@@ -2,6 +2,44 @@
 Changes for U-Boot 1.0.0:
 ======================================================================
 
+* disable MPC5200 bus pipelining as workaround for bus contention
+
+* Modify XLB arbiter priorities on MPC5200 so all devices use same
+  priority; configure critical interrupts to be handled like external
+  interrupts
+
+* Make IPB clock on MGT5100/MPC5200 configurable in board config file;
+  go back to 66 MHz for stability
+
+* Patches by Jon Diekema, 15 Sep 2003:
+  - add description for missing CFG_CMD_* entries in the README file
+  - sacsng tweaks
+
+* Patch by Gleb Natapov, 14 Sep 2003:
+  enable watchdog support for all MPC824x boards that have a watchdog
+
+* On MPC5200, restrict FEC to a maximum of 10 Mbps to work around the
+  "Non-octet Aligned Frame" errors we see at 100 Mbps
+
+* Patch by Sharad Gupta, 14 Sep 2003:
+  fix SPR numbers for upper BAT register ([ID]BAT[4-7][UL])
+
+* Patch by llandre, 11 Sep 2003:
+  update configuration for PPChameleonEVB board
+
+* Patch by David Müller, 13 Sep 2003:
+  various changes to VCMA9 board specific files
+
+* Add I2C support for MGT5100 / MPC5200
+
+* Patch by Rune Torgersen, 11 Sep 2003:
+  Changed default memory option on MPC8266ADS to NOT be Page Based
+  Interleave, since this doesn't work very well with the standard
+  16MB DIMM
+
+* Patch by George G. Davis, 12 Sep 2003:
+  fix Makefile settings for sk98 driver
+
 * Patch by Stefan Roese, 12 Sep 2003:
   - new boards added: DP405, HUB405, PLU405, VOH405
   - some esd boards updated

README

@@ -203,6 +203,7 @@ Directory Hierarchy:
 - board/mpl/common	Common files for MPL boards
 - board/mpl/pip405	Files specific to PIP405     boards
 - board/mpl/mip405	Files specific to MIP405     boards
+- board/mpl/vcma9	Files specific to VCMA9      boards
 - board/musenki	Files specific to MUSEKNI    boards
 - board/mvs1	Files specific to MVS1       boards
 - board/nx823   Files specific to NX823      boards
@@ -363,7 +364,7 @@ The following options need to be configured:
 		CONFIG_IMPA7,       CONFIG_LART,       CONFIG_LUBBOCK,
 		CONFIG_INNOVATOROMAP1510,	CONFIG_INNOVATOROMAP1610
 		CONFIG_SHANNON,     CONFIG_SMDK2400,   CONFIG_SMDK2410,
-		CONFIG_TRAB,	    CONFIG_AT91RM9200DK
+		CONFIG_TRAB,	    CONFIG_VCMA9,      CONFIG_AT91RM9200DK
 
 
 - CPU Module Type: (if CONFIG_COGENT is defined)
@@ -572,13 +573,18 @@ The following options need to be configured:
 		#define enables commands:
 		-------------------------
 		CFG_CMD_ASKENV	* ask for env variable
+		CFG_CMD_AUTOSCRIPT Autoscript Support
 		CFG_CMD_BDI	  bdinfo
 		CFG_CMD_BEDBUG	  Include BedBug Debugger
+		CFG_CMD_BMP     * BMP support
 		CFG_CMD_BOOTD	  bootd
 		CFG_CMD_CACHE	  icache, dcache
 		CFG_CMD_CONSOLE	  coninfo
 		CFG_CMD_DATE	* support for RTC, date/time...
 		CFG_CMD_DHCP	  DHCP support
+		CFG_CMD_DIAG    * Diagnostics
+		CFG_CMD_DOC     * Disk-On-Chip Support
+		CFG_CMD_DTT       Digital Therm and Thermostat 
 		CFG_CMD_ECHO	* echo arguments
 		CFG_CMD_EEPROM	* EEPROM read/write support
 		CFG_CMD_ELF	  bootelf, bootvx
@@ -588,27 +594,37 @@ The following options need to be configured:
 		CFG_CMD_FDOS	* Dos diskette Support
 		CFG_CMD_FLASH	  flinfo, erase, protect
 		CFG_CMD_FPGA	  FPGA device initialization support
+		CFG_CMD_HWFLOW  * RTS/CTS hw flow control
 		CFG_CMD_I2C	* I2C serial bus support
 		CFG_CMD_IDE	* IDE harddisk support
 		CFG_CMD_IMI	  iminfo
+		CFG_CMD_IMLS      List all found images
 		CFG_CMD_IMMAP	* IMMR dump support
 		CFG_CMD_IRQ	* irqinfo
+		CFG_CMD_JFFS2   * JFFS2 Support
 		CFG_CMD_KGDB	* kgdb
 		CFG_CMD_LOADB	  loadb
 		CFG_CMD_LOADS	  loads
 		CFG_CMD_MEMORY	  md, mm, nm, mw, cp, cmp, crc, base,
 				  loop, mtest
+		CFG_CMD_MISC      Misc functions like sleep etc
 		CFG_CMD_MMC	  MMC memory mapped support
 		CFG_CMD_MII	  MII utility commands
+		CFG_CMD_NAND    * NAND support
 		CFG_CMD_NET	  bootp, tftpboot, rarpboot
 		CFG_CMD_PCI	* pciinfo
 		CFG_CMD_PCMCIA	* PCMCIA support
+		CFG_CMD_PING    * send ICMP ECHO_REQUEST to network host
+		CFG_CMD_PORTIO    Port I/O
 		CFG_CMD_REGINFO * Register dump
 		CFG_CMD_RUN	  run command in env variable
+		CFG_CMD_SAVES     save S record dump
 		CFG_CMD_SCSI	* SCSI Support
+		CFG_CMD_SDRAM   * print SDRAM configuration information
 		CFG_CMD_SETGETDCR Support for DCR Register access (4xx only)
 		CFG_CMD_SPI	* SPI serial bus support
 		CFG_CMD_USB	* USB support
+		CFG_CMD_VFD     * VFD support (TRAB)
 		CFG_CMD_BSP	* Board SPecific functions
 		-----------------------------------------------
 		CFG_CMD_ALL	all

board/mpc8266ads/mpc8266ads.c

@@ -46,7 +46,7 @@
  *   PSDMR_BUFCMD adds a clock
  *   0            no extra clock
  */
-#define CONFIG_PBI		PSDMR_PBI
+#define CONFIG_PBI		0
 #define PESSIMISTIC_SDRAM	0
 #define EAMUX			0	/* EST requires EAMUX */
 #define BUFCMD			0

board/mpl/vcma9/cmd_vcma9.c

@@ -41,9 +41,12 @@ static uchar cs8900_chksum(ushort data)
 #endif
 
 extern void print_vcma9_info(void);
-extern int vcma9_cantest(void);
+extern int vcma9_cantest(int);
 extern int vcma9_nandtest(void);
-extern int vcma9_dactest(void);
+extern int vcma9_nanderase(void);
+extern int vcma9_nandread(ulong);
+extern int vcma9_nandwrite(ulong);
+extern int vcma9_dactest(int);
 extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 
 /* ------------------------------------------------------------------------- */
@@ -126,18 +129,53 @@ int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #endif
 #if 0
 	if (strcmp(argv[1], "cantest") == 0) {
-		vcma9_cantest();
+		if (argc >= 3)
+			vcma9_cantest(strcmp(argv[2], "s") ? 0 : 1);
+		else
+			vcma9_cantest(0);
 		return 0;
 	}
 	if (strcmp(argv[1], "nandtest") == 0) {
 		vcma9_nandtest();
 		return 0;
 	}
+	if (strcmp(argv[1], "nanderase") == 0) {
+		vcma9_nanderase();
+		return 0;
+	}
+	if (strcmp(argv[1], "nandread") == 0) {
+		ulong offset = 0;
+
+		if (argc >= 3)
+			offset = simple_strtoul(argv[2], NULL, 16);
+
+		vcma9_nandread(offset);
+		return 0;
+	}
+	if (strcmp(argv[1], "nandwrite") == 0) {
+		ulong offset = 0;
+
+		if (argc >= 3)
+			offset = simple_strtoul(argv[2], NULL, 16);
+
+		vcma9_nandwrite(offset);
+		return 0;
+	}
 	if (strcmp(argv[1], "dactest") == 0) {
-		vcma9_dactest();
+		if (argc >= 3)
+			vcma9_dactest(strcmp(argv[2], "s") ? 0 : 1);
+		else
+		vcma9_dactest(0);
 		return 0;
 	}
 #endif
 
 	return (do_mplcommon(cmdtp, flag, argc, argv));
 }
+
+U_BOOT_CMD(
+	vcma9, 6, 1, do_vcma9,
+	"vcma9   - VCMA9 specific commands\n",
+	"flash mem [SrcAddr]\n    - updates U-Boot with image in memory\n"
+);
+

board/mpl/vcma9/config.mk

@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2002
+# (C) Copyright 2002, 2003
 # David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
 #
 # MPL VCMA9 board with S3C2410X (ARM920T) cpu
@@ -8,17 +8,17 @@
 #
 
 #
-# MPL VCMA9 has 1 bank of 64 MB DRAM
-#
-# 3000'0000 to 3400'0000
+# MPL VCMA9 has 1 bank of minimal 16 MB DRAM
+# from 0x30000000
 #
 # Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
-# optionally with a ramdisk at 3080'0000
+# optionally with a ramdisk at 3040'0000
 #
-# we load ourself to 33F8'0000
+# we load ourself to 30F8'0000
 #
-# download area is 3300'0000
+# download area is 3080'0000
 #
 
 
+#TEXT_BASE = 0x30F80000
 TEXT_BASE = 0x33F80000

board/mpl/vcma9/memsetup.S

@@ -34,7 +34,9 @@
 
 /* some parameters for the board */
 
-#define BWSCON	0x48000000
+#define BWSCON		0x48000000
+#define PLD_BASE	0x2C000000
+#define SDRAM_REG	0x2C000106
 
 /* BWSCON */
 #define DW8		 	(0x0)
@@ -43,6 +45,9 @@
 #define WAIT		 	(0x1<<2)
 #define UBLB		 	(0x1<<3)
 
+/* BANKSIZE */
+#define BURST_EN		(0x1<<7)
+
 #define B1_BWSCON	  	(DW16)
 #define B2_BWSCON	  	(DW32)
 #define B3_BWSCON	  	(DW32)
@@ -130,24 +135,39 @@ memsetup:
 	/* memory control configuration */
 	/* make r0 relative the current location so that it */
 	/* reads SMRDATA out of FLASH rather than memory ! */
-	ldr     r0, =SMRDATA
+	ldr     r0, =CSDATA
 	ldr	r1, _TEXT_BASE
 	sub	r0, r0, r1
 	ldr	r1, =BWSCON	/* Bus Width Status Controller */
-	add     r2, r0, #13*4
+	add     r2, r0, #CSDATA_END-CSDATA
 0:
 	ldr     r3, [r0], #4
 	str     r3, [r1], #4
 	cmp     r2, r0
 	bne     0b
 
+	/* PLD access is now possible */
+	/* r0 == SDRAMDATA */
+	/* r1 == SDRAM controller regs */
+	ldr	r2, =PLD_BASE
+	ldrb	r3, [r2, #SDRAM_REG-PLD_BASE]
+	mov	r4, #SDRAMDATA1_END-SDRAMDATA
+	/* calculate start and end point */
+	mla	r0, r3, r4, r0 
+	add     r2, r0, r4
+0:
+	ldr     r3, [r0], #4
+	str     r3, [r1], #4
+	cmp     r2, r0
+	bne     0b
+	
 	/* everything is fine now */
 	mov	pc, lr
 
 	.ltorg
 /* the literal pools origin */
 
-SMRDATA:
+CSDATA:
     .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
     .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
     .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
@@ -155,9 +175,38 @@ SMRDATA:
     .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
     .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
     .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
+CSDATA_END:
+
+SDRAMDATA:
+/* 4Mx8x4 */
     .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
     .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
     .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
-    .word 0x32
+    .word 0x32 + BURST_EN
+    .word 0x30
+    .word 0x30
+SDRAMDATA1_END:
+
+/* 8Mx8x4 (not implemented yet) */
+    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+    .word 0x32 + BURST_EN
+    .word 0x30
+    .word 0x30
+    
+/* 2Mx8x4 (not implemented yet) */
+    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+    .word 0x32 + BURST_EN
+    .word 0x30
+    .word 0x30
+    
+/* 4Mx8x2 (not implemented yet) */
+    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+    .word 0x32 + BURST_EN
     .word 0x30
     .word 0x30

board/mpl/vcma9/vcma9.c

@@ -130,16 +130,6 @@ int board_init(void)
 	return 0;
 }
 
-int dram_init(void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return 0;
-}
-
 /*
  * NAND flash initialization.
  */
@@ -162,9 +152,16 @@ static inline void NF_Reset(void)
 
 static inline void NF_Init(void)
 {
+#if 0 /* a little bit too optimistic */
 #define TACLS   0
 #define TWRPH0  3
 #define TWRPH1  0
+#else
+#define TACLS   0
+#define TWRPH0  4
+#define TWRPH1  2
+#endif
+
     NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0));
     /*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */
     /* 1  1    1     1,   1      xxx,  r xxx,   r xxx */
@@ -177,15 +174,12 @@ void
 nand_init(void)
 {
 	S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
-	unsigned totlen;
 
 	NF_Init();
 #ifdef DEBUG
 	printf("NAND flash probing at 0x%.8lX\n", (ulong)nand);
 #endif
-	totlen = nand_probe((ulong)nand) >> 20;
-
-	printf ("%4lu MB\n", totlen >> 20);
+	printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20);
 }
 #endif
 
@@ -193,41 +187,102 @@ nand_init(void)
  * Get some Board/PLD Info
  */
 
-static uchar Get_PLD_ID(void)
+static u8 Get_PLD_ID(void)
 {
-	return(*(volatile uchar *)PLD_ID_REG);
+	VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
+	
+	return(pld->ID);
 }
 
-static uchar Get_PLD_BOARD(void)
+static u8 Get_PLD_BOARD(void)
 {
-	return(*(volatile uchar *)PLD_BOARD_REG);
+	VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
+	
+	return(pld->BOARD);
 }
 
-static uchar Get_PLD_Version(void)
+static u8 Get_PLD_SDRAM(void)
+{
+	VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
+	
+	return(pld->SDRAM);
+}
+
+static u8 Get_PLD_Version(void)
 {
 	return((Get_PLD_ID() >> 4) & 0x0F);
 }
 
-static uchar Get_PLD_Revision(void)
+static u8 Get_PLD_Revision(void)
 {
 	return(Get_PLD_ID() & 0x0F);
 }
 
+#if 0	/* not used */
 static int Get_Board_Config(void)
 {
-	uchar config = Get_PLD_BOARD() & 0x03;
+	u8 config = Get_PLD_BOARD() & 0x03;
 
 	if (config == 3)
 	    return 1;
 	else
 	    return 0;
 }
+#endif
 
 static uchar Get_Board_PCB(void)
 {
 	return(((Get_PLD_BOARD() >> 4) & 0x03) + 'A');
 }
 
+static u8 Get_SDRAM_ChipNr(void)
+{
+	switch ((Get_PLD_SDRAM() >> 4) & 0x0F) {
+		case 0: return 4;
+		case 1: return 1;
+		case 2: return 2;
+		default: return 0;
+	}
+}
+
+static ulong Get_SDRAM_ChipSize(void)
+{
+	switch (Get_PLD_SDRAM() & 0x0F) {
+		case 0: return 16 * (1024*1024);
+		case 1: return 32 * (1024*1024);
+		case 2: return  8 * (1024*1024);
+		case 3: return  8 * (1024*1024);
+		default: return 0;
+	}	
+}
+static const char * Get_SDRAM_ChipGeom(void)
+{
+	switch (Get_PLD_SDRAM() & 0x0F) {
+		case 0: return "4Mx8x4";
+		case 1: return "8Mx8x4";
+		case 2: return "2Mx8x4";
+		case 3: return "4Mx8x2";
+		default: return "unknown";
+	}
+}
+
+static void Show_VCMA9_Info(char *board_name, char *serial)
+{
+	printf("Board: %s SN: %s  PCB Rev: %c PLD(%d,%d)\n",
+		board_name, serial, Get_Board_PCB(), Get_PLD_Version(), Get_PLD_Revision());
+	printf("SDRAM: %d chips %s\n", Get_SDRAM_ChipNr(), Get_SDRAM_ChipGeom());
+}
+
+int dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = Get_SDRAM_ChipSize() * Get_SDRAM_ChipNr();
+
+	return 0;
+}
+
 /* ------------------------------------------------------------------------- */
 
 /*
@@ -240,8 +295,6 @@ int checkboard(void)
 	int i;
 	backup_t *b = (backup_t *) s;
 
-	puts("Board: ");
-
 	i = getenv_r("serial#", s, 32);
 	if ((i < 0) || strncmp (s, "VCMA9", 5)) {
 		get_backup_values (b);
@@ -249,32 +302,23 @@ int checkboard(void)
 			puts ("### No HW ID - assuming VCMA9");
 		} else {
 			b->serial_name[5] = 0;
-			printf ("%s-%d PCB Rev %c SN: %s", b->serial_name, Get_Board_Config(),
-					Get_Board_PCB(), &b->serial_name[6]);
+			Show_VCMA9_Info(b->serial_name, &b->serial_name[6]);
 		}
 	} else {
 		s[5] = 0;
-		printf ("%s-%d PCB Rev %c SN: %s", s, Get_Board_Config(), Get_Board_PCB(),
-				&s[6]);
+		Show_VCMA9_Info(s, &s[6]);
 	}
-	printf("\n");
+	/*printf("\n");*/
 	return(0);
 }
 
 
-void print_vcma9_rev(void)
-{
-	printf("Board: VCMA9-%d PCB Rev: %c (PLD Ver: %d, Rev: %d)\n",
-		Get_Board_Config(), Get_Board_PCB(),
-		Get_PLD_Version(), Get_PLD_Revision());
-}
-
 extern void mem_test_reloc(void);
 
 int last_stage_init(void)
 {
 	mem_test_reloc();
-	print_vcma9_rev();
+	checkboard();
 	show_stdio_dev();
 	check_env();
 	return 0;
@@ -295,6 +339,15 @@ int overwrite_console(void)
 * Print VCMA9 Info
 ************************************************************************/
 void print_vcma9_info(void)
-{
-    print_vcma9_rev();
+{	
+	unsigned char s[50];
+	int i;
+	
+	if ((i = getenv_r("serial#", s, 32)) < 0) {
+		puts ("### No HW ID - assuming VCMA9");
+		printf("i %d", i*24);
+	} else {
+		s[5] = 0;
+		Show_VCMA9_Info(s, &s[6]);
+	}
 }

board/mpl/vcma9/vcma9.h

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2002
+ * (C) Copyright 2002, 2003
  * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
  *
  * See file CREDITS for list of people who contributed to this
@@ -116,11 +116,19 @@ static inline u32 NF_Read_ECC(void)
 
 #endif
 
+/* VCMA9 PLD regsiters */
+typedef struct {
+	S3C24X0_REG8	ID;
+	S3C24X0_REG8	NIC;
+	S3C24X0_REG8	CAN;
+	S3C24X0_REG8	MISC;
+	S3C24X0_REG8	GPCD;
+	S3C24X0_REG8	BOARD;
+	S3C24X0_REG8	SDRAM;
+} /*__attribute__((__packed__))*/ VCMA9_PLD;
 
-#define PLD_BASE_ADDRESS		0x2C000100
-#define PLD_ID_REG			(PLD_BASE_ADDRESS + 0)
-#define PLD_NIC_REG			(PLD_BASE_ADDRESS + 1)
-#define PLD_CAN_REG			(PLD_BASE_ADDRESS + 2)
-#define PLD_MISC_REG			(PLD_BASE_ADDRESS + 3)
-#define PLD_GPCD_REG			(PLD_BASE_ADDRESS + 4)
-#define PLD_BOARD_REG			(PLD_BASE_ADDRESS + 5)
+#define VCMA9_PLD_BASE	0x2C000100
+static inline VCMA9_PLD * const VCMA9_GetBase_PLD(void)
+{
+	return (VCMA9_PLD * const)VCMA9_PLD_BASE;
+}

board/sacsng/sacsng.c

@@ -28,11 +28,18 @@
 #include <mpc8260.h>
 #include <i2c.h>
 #include <spi.h>
+#include <command.h>
 
 #ifdef CONFIG_SHOW_BOOT_PROGRESS
 #include <status_led.h>
 #endif
 
+#ifdef CONFIG_ETHER_LOOPBACK_TEST
+extern void eth_loopback_test(void);
+#endif /* CONFIG_ETHER_LOOPBACK_TEST */
+
+extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
 #include "clkinit.h"
 #include "ioconfig.h" /* I/O configuration table */
 
@@ -243,15 +250,15 @@ long int initdram(int board_type)
 
     /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */
     if(caslatency < 2) {
-	printf("CL was %d, forcing to 2\n", caslatency);
+	printf("WARNING: CL was %d, forcing to 2\n", caslatency);
 	caslatency = 2;
     }
     if(rows > 14) {
-	printf("This doesn't look good, rows = %d, should be <= 14\n", rows);
+	printf("WARNING: This doesn't look good, rows = %d, should be <= 14\n", rows);
 	rows = 14;
     }
     if(cols > 11) {
-	printf("This doesn't look good, columns = %d, should be <= 11\n", cols);
+	printf("WARNING: This doesn't look good, columns = %d, should be <= 11\n", cols);
 	cols = 11;
     }
 
@@ -450,6 +457,15 @@ int misc_init_r(void)
     int  sample_128x;  /* Use 128/4 clocking for the ADC/DAC */
     int  right_just;   /* Is the data to the DAC right justified? */
     int  mclk_divide;  /* MCLK Divide */
+    int  quiet;        /* Quiet or minimal output mode */
+
+    quiet = 0;
+    if ((ep = getenv("quiet")) != NULL) {
+	quiet = simple_strtol(ep, NULL, 10);
+    }
+    else {
+	setenv("quiet", "0");
+    }
 
     /*
      * SACSng custom initialization:
@@ -517,8 +533,12 @@ int misc_init_r(void)
 	setenv("Daq128xSampling", "1");
     }
 
-    /* Display the ADC/DAC clocking information */
-    Daq_Display_Clocks();
+    /* 
+     * Display the ADC/DAC clocking information 
+     */
+    if (!quiet) {
+        Daq_Display_Clocks();
+    }
 
     /*
      * Determine the DAC data justification
@@ -552,8 +572,10 @@ int misc_init_r(void)
      * 3) Write the I2C address to register 6
      * 4) Enable address matching by setting the MSB in register 7
      */
-
-    printf("Initializing the ADC...\n");
+    
+    if (!quiet) {
+        printf("Initializing the ADC...\n");
+    }
     udelay(ADC_INITIAL_DELAY);		/* 10uSec per uF of VREF cap */
 
     iopa->pdat &= ~ADC_SDATA1_MASK;     /* release SDATA1 */
@@ -615,7 +637,9 @@ int misc_init_r(void)
      * sending an I2C "start" sequence.  When we bring the I2C back to
      * the normal state, we send an I2C "stop" sequence.
      */
-    printf("Initializing the DAC...\n");
+    if (!quiet) {
+	printf("Initializing the DAC...\n");
+    }
 
     /*
      * Bring the I2C clock and data lines low for initialization
@@ -695,7 +719,16 @@ int misc_init_r(void)
     I2C_DELAY;
     I2C_TRISTATE;
 
-    printf("\n");
+    if (!quiet) {
+        printf("\n");
+    }
+
+#ifdef CONFIG_ETHER_LOOPBACK_TEST
+    /*
+     * Run the Ethernet loopback test
+     */
+    eth_loopback_test ();
+#endif /* CONFIG_ETHER_LOOPBACK_TEST */
 
 #ifdef CONFIG_SHOW_BOOT_PROGRESS
     /*
@@ -758,17 +791,44 @@ static int last_boot_progress;
 
 void show_boot_progress (int status)
 {
-    if(status != -1) {
+    int i,j;
+    if(status > 0) {
 	last_boot_progress = status;
     } else {
-	/*
-	 * Houston, we have a problem.  Blink the last OK status which
-	 * indicates where things failed.
+        /* 
+	 * If a specific failure code is given, flash this code
+	 * else just use the last success code we've seen
 	 */
-	status_led_set(STATUS_LED_RED, STATUS_LED_ON);
-	flash_code(last_boot_progress, 5, 3);
-	udelay(1000000);
-	status_led_set(STATUS_LED_RED, STATUS_LED_BLINKING);
+	if(status < -1)
+	    last_boot_progress = -status;
+	
+	/* 
+	 * Flash this code 5 times
+	 */
+	for(j=0; j<5; j++) {
+	    /*
+	     * Houston, we have a problem.
+	     * Blink the last OK status which indicates where things failed.
+	     */
+	    status_led_set(STATUS_LED_RED, STATUS_LED_ON);
+	    flash_code(last_boot_progress, 5, 3);
+
+	    /* 
+	     * Delay 5 seconds between repetitions, 
+	     * with the fault LED blinking 
+	     */
+	    for(i=0; i<5; i++) {
+	    	status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
+	    	udelay(500000);
+	    	status_led_set(STATUS_LED_RED, STATUS_LED_ON);
+	    	udelay(500000);
+	    }
+	}
+
+	/*
+	 * Reset the board to retry initialization.
+	 */
+	do_reset (NULL, 0, 0, NULL);
     }
 }
 #endif /* CONFIG_SHOW_BOOT_PROGRESS */

board/sixnet/sixnet.c

@@ -330,7 +330,7 @@ int misc_init_r (void)
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
 void nand_init(void)
 {
-	unsigned long totlen = nand_probe(CFG_NAND_BASE);
+	unsigned long totlen = nand_probe(CFG_DFLASH_BASE);
 
 	printf ("%4lu MB\n", totlen >> 20);
 }

config.mk

@@ -102,7 +102,7 @@ RELFLAGS= $(PLATFORM_RELFLAGS)
 DBGFLAGS= -g #-DDEBUG
 OPTFLAGS= -Os #-fomit-frame-pointer
 ifndef LDSCRIPT
-#LDSCRIPT := board/$(BOARDDIR)/u-boot.lds.debug
+#LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug
 LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
 endif
 OBJCFLAGS += --gap-fill=0xff

cpu/mpc5xxx/Makefile

@@ -27,7 +27,7 @@ LIB	= lib$(CPU).a
 
 START	= start.o
 ASOBJS	= io.o firmware_sc_task_bestcomm.impl.o firmware_sc_task.impl.o
-OBJS	= traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o \
+OBJS	= i2c.o traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o \
 	  loadtask.o fec.o pci_mpc5200.o
 
 all:	.depend $(START) $(ASOBJS) $(LIB)

cpu/mpc5xxx/cpu_init.c

@@ -152,6 +152,7 @@ void cpu_init_f (void)
 	/* enable timebase */
 	*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 13);
 
+#if defined(CFG_IPBSPEED_133)
 	/* Motorola reports IPB should better run at 133 MHz. */
 	*(vu_long *)MPC5XXX_ADDECR |= 1;
 	/* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */
@@ -159,6 +160,10 @@ void cpu_init_f (void)
 	addecr &= ~0x103;
 	addecr |= 0x02;
 	*(vu_long *)MPC5XXX_CDM_CFG = addecr;
+#endif
+	/* Configure the XLB Arbiter */
+	*(vu_long *)MPC5XXX_XLBARB_MPRIEN = 0xff;
+	*(vu_long *)MPC5XXX_XLBARB_MPRIVAL = 0x11111111;
 #endif
 }
 
@@ -175,6 +180,8 @@ int cpu_init_r (void)
 #endif
 	*(vu_long *)MPC5XXX_ICTL_CRIT |= 0x0001ffff;
 	*(vu_long *)MPC5XXX_ICTL_EXT &= ~0x00000f00;
+	/* route critical ints to normal ints */
+	*(vu_long *)MPC5XXX_ICTL_EXT |= 0x00000001;
 
 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_MPC5XXX_FEC)
 	/* load FEC microcode */

cpu/mpc5xxx/fec.c

@@ -387,7 +387,9 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
 			/*
 			 * Force 10Base-T, FDX operation
 			 */
+#if (DEBUG & 0x2)
 			printf("Forcing 10 Mbps ethernet link... ");
+#endif
 			miiphy_read(phyAddr, 0x1, &phyStatus);
 			/*
 			miiphy_write(fec, phyAddr, 0x0, 0x0100);
@@ -822,7 +824,13 @@ int mpc5xxx_fec_initialize(bd_t * bis)
 	fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
 	fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
 #ifdef CONFIG_ICECUBE
+#ifndef CONFIG_FEC_10MBIT
 	fec->xcv_type = MII100;
+#else
+	fec->xcv_type = MII10;
+#endif
+#else
+#error fec->xcv_type not initialized.
 #endif
 
 	dev->priv = (void *)fec;

cpu/mpc5xxx/i2c.c

@@ -0,0 +1,338 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_HARD_I2C
+
+#include <mpc5xxx.h>
+#include <i2c.h>
+
+#ifdef CFG_I2C_MODULE
+#define I2C_BASE	MPC5XXX_I2C2
+#else
+#define I2C_BASE	MPC5XXX_I2C1
+#endif
+
+#define I2C_TIMEOUT	100
+#define I2C_RETRIES	3
+
+static int  mpc_reg_in    (volatile u32 *reg);
+static void mpc_reg_out   (volatile u32 *reg, int val, int mask);
+static int  wait_for_bb   (void);
+static int  wait_for_pin  (int *status);
+static int  do_address    (uchar chip, char rdwr_flag);
+static int  send_bytes    (uchar chip, char *buf, int len);
+static int  receive_bytes (uchar chip, char *buf, int len);
+
+static int mpc_reg_in(volatile u32 *reg)
+{
+	return *reg >> 24;
+	__asm__ __volatile__ ("eieio");
+}
+
+static void mpc_reg_out(volatile u32 *reg, int val, int mask)
+{
+	int tmp;
+
+	if (!mask) {
+		*reg = val << 24;
+	} else {
+		tmp = mpc_reg_in(reg);
+		*reg = ((tmp & ~mask) | (val & mask)) << 24;
+	}
+	__asm__ __volatile__ ("eieio");
+
+	return;
+}
+
+static int wait_for_bb(void)
+{
+	struct mpc5xxx_i2c *regs    = (struct mpc5xxx_i2c *)I2C_BASE;
+	int                 timeout = I2C_TIMEOUT;
+	int                 status;
+
+	status = mpc_reg_in(&regs->msr);
+
+	while (timeout-- && (status & I2C_BB)) {
+#if 1
+		volatile int temp;
+		mpc_reg_out(&regs->mcr, I2C_STA, I2C_STA);
+		temp = mpc_reg_in(&regs->mdr);
+		mpc_reg_out(&regs->mcr, 0, I2C_STA);
+		mpc_reg_out(&regs->mcr, 0, 0);
+		mpc_reg_out(&regs->mcr, I2C_EN, 0);
+#endif
+		udelay(1000);
+		status = mpc_reg_in(&regs->msr);
+	}
+
+	return (status & I2C_BB);
+}
+
+static int wait_for_pin(int *status)
+{
+	struct mpc5xxx_i2c *regs    = (struct mpc5xxx_i2c *)I2C_BASE;
+	int                 timeout = I2C_TIMEOUT;
+
+	*status = mpc_reg_in(&regs->msr);
+
+	while (timeout-- && !(*status & I2C_IF)) {
+		udelay(1000);
+		*status = mpc_reg_in(&regs->msr);
+	}
+
+	if (!(*status & I2C_IF)) {
+		return -1;
+	}
+
+	mpc_reg_out(&regs->msr, 0, I2C_IF);
+
+	return 0;
+}
+
+static int do_address(uchar chip, char rdwr_flag)
+{
+	struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
+	int                 status;
+
+	chip <<= 1;
+
+	if (rdwr_flag) {
+		chip |= 1;
+	}
+
+	mpc_reg_out(&regs->mcr, I2C_TX, I2C_TX);
+	mpc_reg_out(&regs->mdr, chip, 0);
+
+        if (wait_for_pin(&status)) {
+                return -2;
+        }
+
+        if (status & I2C_RXAK) {
+                return -3;
+        }
+
+	return 0;
+}
+
+static int send_bytes(uchar chip, char *buf, int len)
+{
+	struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
+	int                 wrcount;
+	int                 status;
+
+	for (wrcount = 0; wrcount < len; ++wrcount) {
+
+		mpc_reg_out(&regs->mdr, buf[wrcount], 0);
+
+		if (wait_for_pin(&status)) {
+			break;
+		}
+
+		if (status & I2C_RXAK) {
+			break;
+		}
+
+	}
+
+	return !(wrcount == len);
+}
+
+static int receive_bytes(uchar chip, char *buf, int len)
+{
+	struct mpc5xxx_i2c *regs    = (struct mpc5xxx_i2c *)I2C_BASE;
+	int                 dummy   = 1;
+	int                 rdcount = 0;
+	int                 status;
+	int                 i;
+
+	mpc_reg_out(&regs->mcr, 0, I2C_TX);
+
+	for (i = 0; i < len; ++i) {
+		buf[rdcount] = mpc_reg_in(&regs->mdr);
+
+		if (dummy) {
+			dummy = 0;
+		} else {
+			rdcount++;
+		}
+
+
+		if (wait_for_pin(&status)) {
+			return -4;
+		}
+	}
+
+	mpc_reg_out(&regs->mcr, I2C_TXAK, I2C_TXAK);
+	buf[rdcount++] = mpc_reg_in(&regs->mdr);
+
+	if (wait_for_pin(&status)) {
+		return -5;
+	}
+
+	mpc_reg_out(&regs->mcr, 0, I2C_TXAK);
+
+	return 0;
+}
+
+/**************** I2C API ****************/
+
+void i2c_init(int speed, int saddr)
+{
+	struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
+
+	mpc_reg_out(&regs->mcr, 0, 0);
+	mpc_reg_out(&regs->madr, saddr << 1, 0);
+
+	/* Set clock
+	 */
+	mpc_reg_out(&regs->mfdr, speed, 0);
+
+	/* Enable module
+	 */
+	mpc_reg_out(&regs->mcr, I2C_EN, I2C_INIT_MASK);
+	mpc_reg_out(&regs->msr, 0, I2C_IF);
+
+	return;
+}
+
+int i2c_probe(uchar chip)
+{
+	struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
+	int                 i;
+
+	for (i = 0; i < I2C_RETRIES; i++) {
+		mpc_reg_out(&regs->mcr, I2C_STA, I2C_STA);
+
+		if (! do_address(chip, 0)) {
+			mpc_reg_out(&regs->mcr, 0, I2C_STA);
+			break;
+		}
+
+		mpc_reg_out(&regs->mcr, 0, I2C_STA);
+		udelay(500);
+	}
+
+	return (i == I2C_RETRIES);
+}
+
+int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
+{
+	uchar                xaddr[4];
+	struct mpc5xxx_i2c * regs        = (struct mpc5xxx_i2c *)I2C_BASE;
+	int                  ret         = -1;
+
+	xaddr[0] = (addr >> 24) & 0xFF;
+	xaddr[1] = (addr >> 16) & 0xFF;
+	xaddr[2] = (addr >>  8) & 0xFF;
+	xaddr[3] =  addr	& 0xFF;
+
+	if (wait_for_bb()) {
+		printf("i2c_read: bus is busy\n");
+		goto Done;
+	}
+
+	mpc_reg_out(&regs->mcr, I2C_STA, I2C_STA);
+	if (do_address(chip, 0)) {
+		printf("i2c_read: failed to address chip\n");
+		goto Done;
+	}
+
+	if (send_bytes(chip, &xaddr[4-alen], alen)) {
+		printf("i2c_read: send_bytes failed\n");
+		goto Done;
+	}
+
+	mpc_reg_out(&regs->mcr, I2C_RSTA, I2C_RSTA);
+	if (do_address(chip, 1)) {
+		printf("i2c_read: failed to address chip\n");
+		goto Done;
+	}
+
+	if (receive_bytes(chip, buf, len)) {
+		printf("i2c_read: receive_bytes failed\n");
+		goto Done;
+	}
+
+	ret = 0;
+Done:
+	mpc_reg_out(&regs->mcr, 0, I2C_STA);
+	return ret;
+}
+
+int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
+{
+	uchar               xaddr[4];
+	struct mpc5xxx_i2c *regs        = (struct mpc5xxx_i2c *)I2C_BASE;
+	int                 ret         = -1;
+
+	xaddr[0] = (addr >> 24) & 0xFF;
+	xaddr[1] = (addr >> 16) & 0xFF;
+	xaddr[2] = (addr >>  8) & 0xFF;
+	xaddr[3] =  addr	& 0xFF;
+
+        if (wait_for_bb()) {
+		printf("i2c_write: bus is busy\n");
+		goto Done;
+	}
+
+        mpc_reg_out(&regs->mcr, I2C_STA, I2C_STA);
+        if (do_address(chip, 0)) {
+		printf("i2c_write: failed to address chip\n");
+		goto Done;
+	}
+
+	if (send_bytes(chip, &xaddr[4-alen], alen)) {
+		printf("i2c_write: send_bytes failed\n");
+		goto Done;
+	}
+
+	if (send_bytes(chip, buf, len)) {
+		printf("i2c_write: send_bytes failed\n");
+		goto Done;
+	}
+
+	ret = 0;
+Done:
+	mpc_reg_out(&regs->mcr, 0, I2C_STA);
+	return ret;
+}
+
+uchar i2c_reg_read(uchar chip, uchar reg)
+{
+	char buf;
+
+	i2c_read(chip, reg, 1, &buf, 1);
+
+	return buf;
+}
+
+void i2c_reg_write(uchar chip, uchar reg, uchar val)
+{
+	i2c_write(chip, reg, 1, &val, 1);
+
+	return;
+}
+
+#endif	/* CONFIG_HARD_I2C */

cpu/mpc5xxx/pci_mpc5200.c

@@ -48,9 +48,11 @@ static int mpc5200_read_config_dword(struct pci_controller *hose,
 {
 	*(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
 	eieio();
+	udelay(10);
 	*value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
 	eieio();
 	*(volatile u32 *)MPC5XXX_PCI_CAR = 0;
+	udelay(10);
 	return 0;
 }
 
@@ -59,9 +61,11 @@ static int mpc5200_write_config_dword(struct pci_controller *hose,
 {
 	*(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
 	eieio();
+	udelay(10);
 	out_le32((volatile u32 *)CONFIG_PCI_IO_PHYS, value);
 	eieio();
 	*(volatile u32 *)MPC5XXX_PCI_CAR = 0;
+	udelay(10);
 	return 0;
 }
 
@@ -125,8 +129,10 @@ void pci_mpc5xxx_init (struct pci_controller *hose)
 	*(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~((7 << 8) | (3 << 5));
 	*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (3 << 8) | (3 << 5);
 
+#if 0
 	/* Enable piplining */
 	*(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~(1 << 31);
+#endif
 	
 	/* Disable interrupts from PCI controller */
 	*(vu_long *)MPC5XXX_PCI_GSCR &= ~(7 << 12);

cpu/mpc5xxx/start.S

@@ -382,6 +382,14 @@ init_5xxx_core:
 	mtspr	DBAT2L, r0
 	mtspr	DBAT3U, r0
 	mtspr	DBAT3L, r0
+	mtspr	DBAT4U, r0
+	mtspr	DBAT4L, r0
+	mtspr	DBAT5U, r0
+	mtspr	DBAT5L, r0
+	mtspr	DBAT6U, r0
+	mtspr	DBAT6L, r0
+	mtspr	DBAT7U, r0
+	mtspr	DBAT7L, r0
 	mtspr	IBAT0U, r0
 	mtspr	IBAT0L, r0
 	mtspr	IBAT1U, r0
@@ -390,6 +398,14 @@ init_5xxx_core:
 	mtspr	IBAT2L, r0
 	mtspr	IBAT3U, r0
 	mtspr	IBAT3L, r0
+	mtspr	IBAT4U, r0
+	mtspr	IBAT4L, r0
+	mtspr	IBAT5U, r0
+	mtspr	IBAT5L, r0
+	mtspr	IBAT6U, r0
+	mtspr	IBAT6L, r0
+	mtspr	IBAT7U, r0
+	mtspr	IBAT7L, r0
 	SYNC
 
 	/* invalidate all tlb's						*/

cpu/mpc824x/interrupts.c

@@ -27,6 +27,7 @@
 #include <asm/processor.h>
 #include <asm/pci_io.h>
 #include <commproc.h>
+#include <watchdog.h>
 #include "drivers/epic.h"
 
 /****************************************************************************/
@@ -149,15 +150,9 @@ void timer_interrupt (struct pt_regs *regs)
 
 	timestamp++;
 
-#if defined(CONFIG_WATCHDOG)
+#if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG)
 	if ((timestamp % (CFG_HZ / 2)) == 0) {
-#if defined(CONFIG_OXC)
-		{
-			extern void oxc_wdt_reset (void);
-
-			oxc_wdt_reset ();
-		}
-#endif
+		WATCHDOG_RESET ();
 	}
 #endif							/* CONFIG_WATCHDOG */
 #if defined(CONFIG_SHOW_ACTIVITY) && defined(CONFIG_OXC)

drivers/s3c24x0_i2c.c

@@ -56,7 +56,7 @@
 #define I2C_START_STOP	0x20		/* START / STOP */
 #define I2C_TXRX_ENA	0x10		/* I2C Tx/Rx enable */
 
-#define I2C_TIMEOUT 1			/* 1 seconde */
+#define I2C_TIMEOUT 1			/* 1 second */
 
 
 static int GetI2CSDA(void)

drivers/sk98lin/Makefile

@@ -24,6 +24,7 @@
 #
 # Makefile for the SysKonnect SK-98xx device driver.
 #
+include $(TOPDIR)/config.mk
 
 LIB := libsk98lin.a
 

include/asm-ppc/processor.h

@@ -95,14 +95,14 @@
 #define	SPRN_DBAT2U	0x21C	/* Data BAT 2 Upper Register */
 #define	SPRN_DBAT3L	0x21F	/* Data BAT 3 Lower Register */
 #define	SPRN_DBAT3U	0x21E	/* Data BAT 3 Upper Register */
-#define	SPRN_DBAT4L	0x238   /* Data BAT 4 Lower Register */
-#define	SPRN_DBAT4U	0x239   /* Data BAT 4 Upper Register */
-#define	SPRN_DBAT5L	0x23A   /* Data BAT 5 Lower Register */
-#define	SPRN_DBAT5U	0x23B   /* Data BAT 5 Upper Register */
-#define	SPRN_DBAT6L	0x23C   /* Data BAT 6 Lower Register */
-#define	SPRN_DBAT6U	0x23D   /* Data BAT 6 Upper Register */
-#define	SPRN_DBAT7L	0x23E   /* Data BAT 7 Lower Register */
-#define	SPRN_DBAT7U	0x23F   /* Data BAT 7 Lower Register */
+#define	SPRN_DBAT4L	0x239   /* Data BAT 4 Lower Register */
+#define	SPRN_DBAT4U	0x238   /* Data BAT 4 Upper Register */
+#define	SPRN_DBAT5L	0x23B   /* Data BAT 5 Lower Register */
+#define	SPRN_DBAT5U	0x23A   /* Data BAT 5 Upper Register */
+#define	SPRN_DBAT6L	0x23D   /* Data BAT 6 Lower Register */
+#define	SPRN_DBAT6U	0x23C   /* Data BAT 6 Upper Register */
+#define	SPRN_DBAT7L	0x23F   /* Data BAT 7 Lower Register */
+#define	SPRN_DBAT7U	0x23E   /* Data BAT 7 Lower Register */
 #define	SPRN_DBCR	0x3F2	/* Debug Control Regsiter */
 #define	  DBCR_EDM	0x80000000
 #define	  DBCR_IDM	0x40000000
@@ -203,14 +203,14 @@
 #define	SPRN_IBAT2U	0x214	/* Instruction BAT 2 Upper Register */
 #define	SPRN_IBAT3L	0x217	/* Instruction BAT 3 Lower Register */
 #define	SPRN_IBAT3U	0x216	/* Instruction BAT 3 Upper Register */
-#define	SPRN_IBAT4L	0x230   /* Instruction BAT 4 Lower Register */
-#define	SPRN_IBAT4U	0x231   /* Instruction BAT 4 Upper Register */
-#define	SPRN_IBAT5L	0x232   /* Instruction BAT 5 Lower Register */
-#define	SPRN_IBAT5U	0x233   /* Instruction BAT 5 Upper Register */
-#define	SPRN_IBAT6L	0x234   /* Instruction BAT 6 Lower Register */
-#define	SPRN_IBAT6U	0x235   /* Instruction BAT 6 Upper Register */
-#define	SPRN_IBAT7L	0x236   /* Instruction BAT 7 Lower Register */
-#define	SPRN_IBAT7U	0x237   /* Instruction BAT 7 Lower Register */
+#define	SPRN_IBAT4L	0x231   /* Instruction BAT 4 Lower Register */
+#define	SPRN_IBAT4U	0x230   /* Instruction BAT 4 Upper Register */
+#define	SPRN_IBAT5L	0x233   /* Instruction BAT 5 Lower Register */
+#define	SPRN_IBAT5U	0x232   /* Instruction BAT 5 Upper Register */
+#define	SPRN_IBAT6L	0x235   /* Instruction BAT 6 Lower Register */
+#define	SPRN_IBAT6U	0x234   /* Instruction BAT 6 Upper Register */
+#define	SPRN_IBAT7L	0x237   /* Instruction BAT 7 Lower Register */
+#define	SPRN_IBAT7U	0x236   /* Instruction BAT 7 Upper Register */
 #define	SPRN_ICCR	0x3FB	/* Instruction Cache Cacheability Register */
 #define	  ICCR_NOCACHE		0	/* Noncacheable */
 #define	  ICCR_CACHE		1	/* Cacheable */

include/configs/IceCube.h

@@ -83,7 +83,8 @@
 /*
  * Supported commands
  */
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | ADD_PCI_CMD)
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | ADD_PCI_CMD | \
+				 CFG_CMD_I2C | CFG_CMD_EEPROM)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
@@ -95,9 +96,32 @@
 #define CONFIG_BOOTCOMMAND	"bootm 100000"	/* autoboot command */
 #define CONFIG_BOOTARGS		"root=/dev/ram rw"
 
+#if defined(CONFIG_MPC5200)
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CFG_IPBSPEED_133   		/* define for 133MHz speed */
+#endif
 /*
  * I2C configuration
  */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CFG_I2C_MODULE		1	/* If defined then I2C module #2 is used
+					 * otherwise I2C module #1 is used */
+#ifdef CONFIG_MPC5200
+#define CFG_I2C_SPEED		0x3D	/* 86KHz given 133MHz IPBI */
+#else
+#define CFG_I2C_SPEED		0x35	/* 86KHz given 33MHz IPBI */
+#endif
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN		1
+#define CFG_EEPROM_PAGE_WRITE_BITS	3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	35
 
 /*
  * Flash configuration
@@ -161,6 +185,7 @@
  * Ethernet configuration
  */
 #define CONFIG_MPC5XXX_FEC	1
+#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
 
 /*
  * GPIO configuration

include/configs/PPChameleonEVB.h

@@ -55,47 +55,17 @@
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
-#if 0
-#define CONFIG_PREBOOT                                                          \
-        "crc32 f0207004 ffc 0;"                                                 \
-        "if cmp 0 f0207000 1;"                                                  \
-        "then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;"             \
-        "else;echo Old CRC is bad;fi"
-#endif
-
 #undef	CONFIG_BOOTARGS
-#define CONFIG_RAMBOOTCOMMAND							\
-	"setenv bootargs root=/dev/ram rw "	\
-	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname):$(netdev):off;"	\
-	"bootm ffc00000 ffca0000"
-#define CONFIG_NFSBOOTCOMMAND							\
-	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "	\
-	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname):$(netdev):off;"	\
-	"bootm ffc00000"
 
-#define CONFIG_PELK_NOR_KERNEL_NOR_RAMDISK_BOOTCOMMAND				\
-	"setenv ipaddr 192.168.10.203;"						\
-    "setenv serverip 192.168.10.6;"						\
-	"setenv netmask 255.255.255.0;"						\
-	"setenv bootargs root=/dev/ram rw console=ttyS0,9600;"			\
-	"setenv autostart yes;"							\
-	"bootm ffc00000 ffd00000"
-/*
-	"setenv ethaddr 00:50:c2:1e:af:fe;"						\
-	"setenv eth1addr 00:50:c2:1e:af:fd;"						\
-*/
-
-#define CONFIG_BOOTCOMMAND CONFIG_PELK_NOR_KERNEL_NOR_RAMDISK_BOOTCOMMAND
+/* Ethernet stuff */
+#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
+#define CONFIG_ETHADDR	00:50:c2:1e:af:fe
+#define CONFIG_ETH1ADDR	00:50:c2:1e:af:fd
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 
-/* EThernet stuff */
-#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
-#define CONFIG_ETHADDR	00:50:c2:1e:af:fe
-#define CONFIG_ETH1ADDR	00:50:c2:1e:af:fd
-
 #undef CONFIG_EXT_PHY
 
 #define CONFIG_MII		1	/* MII PHY management		*/
@@ -548,18 +518,16 @@
 #if 1 /* test-only */
 #define CONFIG_NO_SERIAL_EEPROM
 /*#undef CONFIG_NO_SERIAL_EEPROM*/
-/*----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------*/
+/*--------------------------------------------------------------------*/
 #ifdef CONFIG_NO_SERIAL_EEPROM
 
 
 /*
-!-------------------------------------------------------------------------------
+!-----------------------------------------------------------------------
 ! Defines for entry options.
 ! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
 !       are plugged in the board will be utilized as non-ECC DIMMs.
-!-------------------------------------------------------------------------------
+!-----------------------------------------------------------------------
 */
 #undef        AUTO_MEMORY_CONFIG
 #define        DIMM_READ_ADDR 0xAB
@@ -678,10 +646,10 @@
 #define PLL_PCIDIV_4               0x00000003
 
 /*
-!-------------------------------------------------------------------------------
+!-----------------------------------------------------------------------
 ! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
 ! assuming a 33.3MHz input clock to the 405EP.
-!-------------------------------------------------------------------------------
+!-----------------------------------------------------------------------
 */
 #define PLLMR0_133_66_66_33  (PLL_CPUDIV_1 | PLL_PLBDIV_1 |  \
                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \

include/configs/VCMA9.h

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2002
+ * (C) Copyright 2002, 2003
  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  * Marius Groeger <mgroeger@sysgo.de>
  * Gary Jennejohn <gj@denx.de>
@@ -160,9 +160,10 @@
 #define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
 #define CFG_MEMTEST_START	0x30000000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x33F80000	/* 63.5 MB in DRAM	*/
+#define CFG_MEMTEST_END		0x30F80000	/* 15.5 MB in DRAM	*/
+
 #define CFG_ALT_MEMTEST
-#define	CFG_LOAD_ADDR		0x33000000	/* default load address	*/
+#define	CFG_LOAD_ADDR		0x30800000	/* default load address	*/
 
 
 #undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
@@ -197,8 +198,6 @@
  */
 #define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
 #define PHYS_SDRAM_1		0x30000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
-
 #define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
 
 #define CFG_FLASH_BASE		PHYS_FLASH_1

include/configs/sacsng.h

@@ -35,10 +35,11 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-/* Enable debug prints */
 #undef DEBUG		      /* General debug */
 #undef DEBUG_BOOTP_EXT	      /* Debug received vendor fields */
 
+#undef CONFIG_LOGBUFFER       /* External logbuffer support */
+
 /*****************************************************************************
  *
  * These settings must match the way _your_ board is set up
@@ -172,6 +173,7 @@
 
 #ifdef	CONFIG_ETHER_ON_FCC
 #define CONFIG_ETHER_INDEX	2	/* which SCC/FCC channel for ethernet */
+#undef  CONFIG_ETHER_LOOPBACK_TEST      /* Ethernet external loopback test */
 #define CONFIG_MII			/* MII PHY management		*/
 #define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
 /*
@@ -318,10 +320,12 @@
  * will be part of the default enviroment compiled into the boot image.
  */
 #define CONFIG_EXTRA_ENV_SETTINGS \
-"serverip=192.168.123.201\0" \
+"quiet=0\0" \
+"serverip=192.168.123.205\0" \
 "ipaddr=192.168.123.203\0" \
 "checkhostname=VR8500\0" \
 "reprog="\
+    "bootp; " \
     "tftpboot 0x140000 /bdi2000/u-boot.bin; " \
     "protect off 60000000 6003FFFF; " \
     "erase 60000000 6003FFFF; " \
@@ -405,7 +409,7 @@
 "adc-12=echo ### ADC-12 ; imd.b e 81 e\0" \
 "adc-34=echo ### ADC-34 ; imd.b f 81 e\0" \
 "dac=echo ### DAC ; imd.b 11 81 5\0" \
-"boot-hook=run ana\0"
+"boot-hook=echo\0"
 
 /* What should the console's baud rate be? */
 #define CONFIG_BAUDRATE		9600
@@ -466,15 +470,16 @@
 
 #define CONFIG_BOOTP_RANDOM_DELAY       /* Randomize the BOOTP retry delay */
 
-#define CONFIG_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up */
-
 /* Add support for a few extra bootp options like:
  *	- File size
- *	- DNS
+ *	- DNS (up to 2 servers)
+ *      - Send hostname to DHCP server 
  */
 #define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
 				 CONFIG_BOOTP_BOOTFILESIZE | \
-				 CONFIG_BOOTP_DNS)
+				 CONFIG_BOOTP_DNS | \
+                                 CONFIG_BOOTP_DNS2 | \
+                                 CONFIG_BOOTP_SEND_HOSTNAME)
 
 /* undef this to save memory */
 #define CFG_LONGHELP
@@ -492,6 +497,11 @@
  */
 #define CONFIG_TIMESTAMP
 
+/* If this variable is defined, an environment variable named "ver" 
+ * is created by U-Boot showing the U-Boot version.
+ */
+#define CONFIG_VERSION_VARIABLE
+
 /* What U-Boot subsytems do you want enabled? */
 #ifdef CONFIG_ETHER_ON_FCC
 # define CONFIG_COMMANDS	(((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
@@ -503,6 +513,8 @@
 				CFG_CMD_SDRAM   | \
 				CFG_CMD_REGINFO | \
 				CFG_CMD_IMMAP	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_PING	| \
 				CFG_CMD_MII	)
 #else
 # define CONFIG_COMMANDS	(((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
@@ -513,12 +525,16 @@
 				CFG_CMD_SPI	| \
 				CFG_CMD_SDRAM   | \
 				CFG_CMD_REGINFO | \
-				CFG_CMD_IMMAP	)
+				CFG_CMD_IMMAP	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_PING	)
 #endif /* CONFIG_ETHER_ON_FCC */
 
 /* Where do the internal registers live? */
 #define CFG_IMMR		0xF0000000
 
+#undef	CONFIG_WATCHDOG			/* disable the watchdog */
+
 /*****************************************************************************
  *
  * You should not have to modify any of the following settings
@@ -532,9 +548,48 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
+
 /*
  * Miscellaneous configurable options
  */
+#define CFG_BOOTM_HEADER_QUIET 1        /* Suppress the image header dump    */
+                                        /* in the bootm command.             */
+#define CFG_BOOTM_PROGESS_QUIET 1       /* Suppress the progress displays,   */
+                                        /* "## <message>" from the bootm cmd */
+#define CFG_BOOTP_CHECK_HOSTNAME 1      /* If checkhostname environment is   */
+                                        /* defined, then the hostname param  */
+                                        /* validated against checkhostname.  */
+#define CFG_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up   */
+#define CFG_BOOTP_SHORT_RANDOM_DELAY 1  /* Use a short random delay value    */
+                                        /* (limited to maximum of 1024 msec) */
+#define CFG_CHK_FOR_ABORT_AT_LEAST_ONCE 1
+                                        /* Check for abort key presses       */
+                                        /* at least once in dependent of the */
+                                        /* CONFIG_BOOTDELAY value.           */
+#define CFG_CONSOLE_INFO_QUIET 1        /* Don't print console @ startup     */
+#define CFG_FAULT_ECHO_LINK_DOWN 1      /* Echo the inverted Ethernet link   */
+                                        /* state to the fault LED.           */
+#define CFG_FAULT_MII_ADDR 0x02         /* MII addr of the PHY to check for  */
+                                        /* the Ethernet link state.          */
+#define CFG_STATUS_FLASH_UNTIL_TFTP_OK 1 /* Keeping the status LED flashing  */
+                                        /* until the TFTP is successful.     */
+#define CFG_STATUS_OFF_AFTER_NETBOOT 1  /* After a successful netboot,       */
+                                        /* turn off the STATUS LEDs.         */
+#define CFG_TFTP_BLINK_STATUS_ON_DATA_IN 1 /* Blink status LED based on      */
+                                        /* incoming data.                    */
+#define CFG_TFTP_BLOCKS_PER_HASH 100    /* For every XX blocks, output a '#' */
+                                        /* to signify that tftp is moving.   */
+#define CFG_TFTP_HASHES_PER_FLASH 200   /* For every '#' hashes,             */
+ 				        /* flash the status LED.             */
+#define CFG_TFTP_HASHES_PER_LINE 65     /* Only output XX '#'s per line      */
+                                        /* during the tftp file transfer.    */
+#define CFG_TFTP_PROGESS_QUIET 1        /* Suppress the progress displays    */
+                                        /* '#'s from the tftp command.       */
+#define CFG_TFTP_STATUS_QUIET 1         /* Suppress the status displays      */
+                                        /* issued during the tftp command.   */
+#define CFG_TFTP_TIMEOUT_COUNT 5        /* How many timeouts TFTP will allow */
+					/* before it gives up.               */
+
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #  define CFG_CBSIZE		1024	/* Console I/O Buffer Size	     */
 #else
@@ -734,12 +789,22 @@
  *-----------------------------------------------------------------------
  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC |\
+			 SYPCR_BMT  |\
+			 SYPCR_PBME |\
+			 SYPCR_LBME |\
+			 SYPCR_SWRI |\
+			 SYPCR_SWP  |\
+                         SYPCR_SWE)
+#else
 #define CFG_SYPCR	(SYPCR_SWTC |\
 			 SYPCR_BMT  |\
 			 SYPCR_PBME |\
 			 SYPCR_LBME |\
 			 SYPCR_SWRI |\
 			 SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
 
 /*-----------------------------------------------------------------------
  * TMCNTSC - Time Counter Status and Control			 4-40

include/mpc5xxx.h

@@ -108,6 +108,9 @@
 
 #define	MPC5XXX_FEC		(CFG_MBAR + 0x3000)
 
+#define MPC5XXX_I2C1		(CFG_MBAR + 0x3D00)
+#define MPC5XXX_I2C2		(CFG_MBAR + 0x3D40)
+
 #if defined(CONFIG_MGT5100)
 #define MPC5XXX_SRAM		(CFG_MBAR + 0x4000)
 #define MPC5XXX_SRAM_SIZE	(8*1024)
@@ -148,6 +151,13 @@
 #define MPC5XXX_CS_DEADCYCLE	(MPC5XXX_LPB + 0x002c)
 #endif
 
+#if defined(CONFIG_MPC5200)
+/* XLB Arbiter registers */
+#define MPC5XXX_XLBARB_CFG		(MPC5XXX_XLBARB + 0x40)
+#define MPC5XXX_XLBARB_MPRIEN	(MPC5XXX_XLBARB + 0x64)
+#define MPC5XXX_XLBARB_MPRIVAL	(MPC5XXX_XLBARB + 0x68)
+#endif
+
 /* GPIO registers */
 #define MPC5XXX_GPS_PORT_CONFIG	(MPC5XXX_GPIO + 0x0000)
 
@@ -197,6 +207,24 @@
 #define MPC5XXX_GPT0_ENABLE		(MPC5XXX_GPT + 0x0)
 #define MPC5XXX_GPT0_COUNTER		(MPC5XXX_GPT + 0x4)
 
+/* I2Cn control register bits */
+#define I2C_EN		0x80
+#define I2C_IEN		0x40
+#define I2C_STA		0x20
+#define I2C_TX		0x10
+#define I2C_TXAK	0x08
+#define I2C_RSTA	0x04
+#define I2C_INIT_MASK	(I2C_EN | I2C_STA | I2C_TX | I2C_RSTA)
+
+/* I2Cn status register bits */
+#define I2C_CF		0x80
+#define I2C_AAS		0x40
+#define I2C_BB		0x20
+#define I2C_AL		0x10
+#define I2C_SRW		0x04
+#define I2C_IF		0x02
+#define I2C_RXAK	0x01
+
 /* Programmable Serial Controller (PSC) status register bits */
 #define PSC_SR_CDE		0x0080
 #define PSC_SR_RXRDY		0x0100
@@ -505,6 +533,14 @@ struct mpc5xxx_sdma {
 	volatile u32 EU37;		/* SDMA + 0xfc */
 };
 
+struct mpc5xxx_i2c {
+	volatile u32 madr;		/* I2Cn + 0x00 */
+	volatile u32 mfdr;		/* I2Cn + 0x04 */
+	volatile u32 mcr;		/* I2Cn + 0x08 */
+	volatile u32 msr;		/* I2Cn + 0x0C */
+	volatile u32 mdr;		/* I2Cn + 0x10 */
+};
+
 /* function prototypes */
 void loadtask(int basetask, int tasks);
 

rtc/s3c24x0_rtc.c

@@ -80,13 +80,15 @@ void rtc_get (struct rtc_time *tmp)
 	SetRTC_Access(RTC_ENABLE);
 
 	/* read RTC registers */
-	sec	= rtc->BCDSEC;
-	min	= rtc->BCDMIN;
-	hour	= rtc->BCDHOUR;
-	mday	= rtc->BCDDATE;
-	wday	= rtc->BCDDAY;
-	mon	= rtc->BCDMON;
-	year	= rtc->BCDYEAR;
+	do {
+		sec	= rtc->BCDSEC;
+		min	= rtc->BCDMIN;
+		hour	= rtc->BCDHOUR;
+		mday	= rtc->BCDDATE;
+		wday	= rtc->BCDDAY;
+		mon	= rtc->BCDMON;
+		year	= rtc->BCDYEAR;
+	} while (sec != rtc->BCDSEC);
 
 	/* read ALARM registers */
 	a_sec	= rtc->ALMSEC;
@@ -170,7 +172,7 @@ void rtc_reset (void)
 	S3C24X0_RTC * const rtc = S3C24X0_GetBase_RTC();
 
 	rtc->RTCCON = (rtc->RTCCON & ~0x06) | 0x08;
-	rtc->RTCCON &= ~0x08;
+	rtc->RTCCON &= ~(0x08|0x01);
 }
 
 /* ------------------------------------------------------------------------- */

tools/mkimage.c

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2002
+ * (C) Copyright 2000-2003
  * DENX Software Engineering
  * Wolfgang Denk, wd@denx.de
  * All rights reserved.
@@ -39,6 +39,10 @@ typedef		unsigned int	uint32_t;
 #define     htonl(a)	SWAP_LONG(a)
 #endif	/* __WIN32__ */
 
+#ifndef	O_BINARY		/* should be define'd on __WIN32__ */
+#define O_BINARY	0
+#endif
+
 #include <image.h>
 
 extern int errno;
@@ -265,11 +269,7 @@ NXTARG:		;
 	if (lflag) {
 		ifd = open(imagefile, O_RDONLY);
 	} else {
-#ifdef __WIN32__
 		ifd = open(imagefile, O_RDWR|O_CREAT|O_TRUNC|O_BINARY, 0666);
-#else
-		ifd = open(imagefile, O_RDWR|O_CREAT|O_TRUNC, 0666);
-#endif
 	}
 
 	if (ifd < 0) {