Work on TRAB's auto_update feature.

Cleanup for submitted patches.

CHANGELOG

@@ -2,6 +2,66 @@
 Changes for U-Boot 1.0.0:
 ======================================================================
 
+* Patch by Rune Torgersen, 17 Sep 2003:
+  - Fixes for MPC8266 default config
+  - Allow eth_loopback_test() on 8260 to use a subset of the FCC's
+
+* Patches by Jon Diekema, 17 Sep 2003:
+  - update README (SHOW_BOOT_PROGRESS values for cmd_nand.c and
+    env_common.c)
+  - sbc8260 tweaks
+  - adjust "help" output
+
+* Patches by Anders Larsen, 17 Sep 2003:
+  - fix spelling errors
+  - set GD_FLG_DEVINIT flag only after device function pointers
+    are valid
+  - Allow CFG_ALT_MEMTEST on systems where address zero isn't
+    writeable
+  - enable 3.rd UART (ST-UART) on PXA(XScale) CPUs
+  - trigger watchdog while waiting in serial driver
+
+* Add auto-update code for TRAB board using USB memory sticks,
+  support new configuration with more memory
+
+* disable MPC5200 bus pipelining as workaround for bus contention
+
+* Modify XLB arbiter priorities on MPC5200 so all devices use same
+  priority; configure critical interrupts to be handled like external
+  interrupts
+
+* Make IPB clock on MGT5100/MPC5200 configurable in board config file;
+  go back to 66 MHz for stability
+
+* Patches by Jon Diekema, 15 Sep 2003:
+  - add description for missing CFG_CMD_* entries in the README file
+  - sacsng tweaks
+
+* Patch by Gleb Natapov, 14 Sep 2003:
+  enable watchdog support for all MPC824x boards that have a watchdog
+
+* On MPC5200, restrict FEC to a maximum of 10 Mbps to work around the
+  "Non-octet Aligned Frame" errors we see at 100 Mbps
+
+* Patch by Sharad Gupta, 14 Sep 2003:
+  fix SPR numbers for upper BAT register ([ID]BAT[4-7][UL])
+
+* Patch by llandre, 11 Sep 2003:
+  update configuration for PPChameleonEVB board
+
+* Patch by David Müller, 13 Sep 2003:
+  various changes to VCMA9 board specific files
+
+* Add I2C support for MGT5100 / MPC5200
+
+* Patch by Rune Torgersen, 11 Sep 2003:
+  Changed default memory option on MPC8266ADS to NOT be Page Based
+  Interleave, since this doesn't work very well with the standard
+  16MB DIMM
+
+* Patch by George G. Davis, 12 Sep 2003:
+  fix Makefile settings for sk98 driver
+
 * Patch by Stefan Roese, 12 Sep 2003:
   - new boards added: DP405, HUB405, PLU405, VOH405
   - some esd boards updated

Makefile

@@ -796,7 +796,7 @@ shannon_config	:	unconfig
 ## ARM92xT Systems
 #########################################################################
 
-xtract_trab = $(subst _big_flash,,$(subst _config,,$1))
+xtract_trab = $(subst _bigram,,$(subst _bigflash,,$(subst _old,,$(subst _config,,$1))))
 
 omap1510inn_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm925t omap1510inn
@@ -811,11 +811,23 @@ smdk2410_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm920t smdk2410
 
 trab_config \
-trab_big_flash_config:	unconfig
+trab_bigram_config \
+trab_bigflash_config \
+trab_old_config:	unconfig
 	@ >include/config.h
-	@[ -z "$(findstring _big_flash,$@)" ] || \
-		{ echo "#define CONFIG_BIG_FLASH" >>include/config.h ; \
-		  echo "... with big flash support" ; \
+	@[ -z "$(findstring _bigram,$@)" ] || \
+		{ echo "#define CONFIG_FLASH_8MB" >>include/config.h ; \
+		  echo "... with 8 MB Flash, 32 MB RAM" ; \
+		}
+	@[ -z "$(findstring _bigflash,$@)" ] || \
+		{ echo "#define CONFIG_RAM_16MB" >>include/config.h ; \
+		  echo "... with 16 MB Flash, 16 MB RAM" ; \
+		  echo "TEXT_BASE = 0x0CF00000" >board/trab/config.tmp ; \
+		}
+	@[ -z "$(findstring _old,$@)" ] || \
+		{ echo "#define CONFIG_OLD_VERSION" >>include/config.h ; \
+		  echo "... with small memory configuration" ; \
+		  echo "TEXT_BASE = 0x0CF00000" >board/trab/config.tmp ; \
 		}
 	@./mkconfig -a $(call xtract_trab,$@) arm arm920t trab
 
@@ -921,7 +933,7 @@ clean:
 	rm -f tools/gdb/astest tools/gdb/gdbcont tools/gdb/gdbsend
 	rm -f tools/env/fw_printenv tools/env/fw_setenv
 	rm -f board/cray/L1/bootscript.c board/cray/L1/bootscript.image
-	rm -f board/trab/trab_fkt
+	rm -f board/trab/trab_fkt board/trab/config.tmp
 
 clobber:	clean
 	find . -type f \

README

@@ -203,6 +203,7 @@ Directory Hierarchy:
 - board/mpl/common	Common files for MPL boards
 - board/mpl/pip405	Files specific to PIP405     boards
 - board/mpl/mip405	Files specific to MIP405     boards
+- board/mpl/vcma9	Files specific to VCMA9      boards
 - board/musenki	Files specific to MUSEKNI    boards
 - board/mvs1	Files specific to MVS1       boards
 - board/nx823   Files specific to NX823      boards
@@ -363,7 +364,7 @@ The following options need to be configured:
 		CONFIG_IMPA7,       CONFIG_LART,       CONFIG_LUBBOCK,
 		CONFIG_INNOVATOROMAP1510,	CONFIG_INNOVATOROMAP1610
 		CONFIG_SHANNON,     CONFIG_SMDK2400,   CONFIG_SMDK2410,
-		CONFIG_TRAB,	    CONFIG_AT91RM9200DK
+		CONFIG_TRAB,	    CONFIG_VCMA9,      CONFIG_AT91RM9200DK
 
 
 - CPU Module Type: (if CONFIG_COGENT is defined)
@@ -572,13 +573,18 @@ The following options need to be configured:
 		#define enables commands:
 		-------------------------
 		CFG_CMD_ASKENV	* ask for env variable
+		CFG_CMD_AUTOSCRIPT Autoscript Support
 		CFG_CMD_BDI	  bdinfo
 		CFG_CMD_BEDBUG	  Include BedBug Debugger
+		CFG_CMD_BMP     * BMP support
 		CFG_CMD_BOOTD	  bootd
 		CFG_CMD_CACHE	  icache, dcache
 		CFG_CMD_CONSOLE	  coninfo
 		CFG_CMD_DATE	* support for RTC, date/time...
 		CFG_CMD_DHCP	  DHCP support
+		CFG_CMD_DIAG    * Diagnostics
+		CFG_CMD_DOC     * Disk-On-Chip Support
+		CFG_CMD_DTT       Digital Therm and Thermostat 
 		CFG_CMD_ECHO	* echo arguments
 		CFG_CMD_EEPROM	* EEPROM read/write support
 		CFG_CMD_ELF	  bootelf, bootvx
@@ -588,27 +594,37 @@ The following options need to be configured:
 		CFG_CMD_FDOS	* Dos diskette Support
 		CFG_CMD_FLASH	  flinfo, erase, protect
 		CFG_CMD_FPGA	  FPGA device initialization support
+		CFG_CMD_HWFLOW  * RTS/CTS hw flow control
 		CFG_CMD_I2C	* I2C serial bus support
 		CFG_CMD_IDE	* IDE harddisk support
 		CFG_CMD_IMI	  iminfo
+		CFG_CMD_IMLS      List all found images
 		CFG_CMD_IMMAP	* IMMR dump support
 		CFG_CMD_IRQ	* irqinfo
+		CFG_CMD_JFFS2   * JFFS2 Support
 		CFG_CMD_KGDB	* kgdb
 		CFG_CMD_LOADB	  loadb
 		CFG_CMD_LOADS	  loads
 		CFG_CMD_MEMORY	  md, mm, nm, mw, cp, cmp, crc, base,
 				  loop, mtest
+		CFG_CMD_MISC      Misc functions like sleep etc
 		CFG_CMD_MMC	  MMC memory mapped support
 		CFG_CMD_MII	  MII utility commands
+		CFG_CMD_NAND    * NAND support
 		CFG_CMD_NET	  bootp, tftpboot, rarpboot
 		CFG_CMD_PCI	* pciinfo
 		CFG_CMD_PCMCIA	* PCMCIA support
+		CFG_CMD_PING    * send ICMP ECHO_REQUEST to network host
+		CFG_CMD_PORTIO    Port I/O
 		CFG_CMD_REGINFO * Register dump
 		CFG_CMD_RUN	  run command in env variable
+		CFG_CMD_SAVES     save S record dump
 		CFG_CMD_SCSI	* SCSI Support
+		CFG_CMD_SDRAM   * print SDRAM configuration information
 		CFG_CMD_SETGETDCR Support for DCR Register access (4xx only)
 		CFG_CMD_SPI	* SPI serial bus support
 		CFG_CMD_USB	* USB support
+		CFG_CMD_VFD     * VFD support (TRAB)
 		CFG_CMD_BSP	* Board SPecific functions
 		-----------------------------------------------
 		CFG_CMD_ALL	all
@@ -1400,7 +1416,13 @@ The following options need to be configured:
    -1	common/cmd_ide.c	Read Error on boot device
    -1	common/cmd_ide.c	Image header has bad magic number
 
-   -1	common/cmd_nvedit.c	Environment not changable, but has bad CRC
+   -1	common/cmd_nand.c	Bad usage of "nand" command
+   -1	common/cmd_nand.c	No boot device
+   -1	common/cmd_nand.c	Unknown Chip ID on boot device
+   -1	common/cmd_nand.c	Read Error on boot device
+   -1	common/cmd_nand.c	Image header has bad magic number
+
+   -1	common/env_common.c     Environment has a bad CRC, using default
 
 
 Modem Support:
@@ -1482,6 +1504,10 @@ Configuration Settings:
 - CFG_ALT_MEMTEST:
 		Enable an alternate, more extensive memory test.
 
+- CFG_MEMTEST_SCRATCH:
+		Scratch address used by the alternate memory test
+		You only need to set this if address zero isn't writeable
+
 - CFG_TFTP_LOADADDR:
 		Default load address for network file downloads
 

board/at91rm9200dk/flash.c

@@ -160,7 +160,7 @@ ulong flash_init (void)
 		if (i == 0)
 			flashbase = PHYS_FLASH_1;
 		else
-			panic ("configured to many flash banks!\n");
+			panic ("configured too many flash banks!\n");
 
 		sector = 0;
 		start_address = flashbase;

board/cradle/flash.c

@@ -59,7 +59,7 @@ ulong flash_init(void)
 		flashbase = PHYS_FLASH_2;
 		break;
 	 default:
-		panic("configured to many flash banks!\n");
+		panic("configured too many flash banks!\n");
 		break;
       }
       for (j = 0; j < flash_info[i].sector_count; j++)

board/csb226/flash.c

@@ -62,7 +62,7 @@ ulong flash_init(void)
 				flashbase = PHYS_FLASH_1;
 				break;
 			default:
-				panic("configured to many flash banks!\n");
+				panic("configured too many flash banks!\n");
 				break;
 		}
 		for (j = 0; j < flash_info[i].sector_count; j++) {

board/dnp1110/flash.c

@@ -74,7 +74,7 @@ unsigned long flash_init (void)
 		 flash_get_offsets(PHYS_FLASH_1, &flash_info[i]);
 		break;
 	   default:
-		panic("configured to many flash banks!\n");
+		panic("configured too many flash banks!\n");
 		break;
 	}
 	size += flash_info[i].size;

board/ep7312/flash.c

@@ -50,7 +50,7 @@ ulong flash_init (void)
 		if (i == 0)
 			flashbase = PHYS_FLASH_1;
 		else
-			panic ("configured to many flash banks!\n");
+			panic ("configured too many flash banks!\n");
 		for (j = 0; j < flash_info[i].sector_count; j++) {
 			flash_info[i].start[j] = flashbase + j * MAIN_SECT_SIZE;
 		}

board/impa7/flash.c

@@ -53,7 +53,7 @@ ulong flash_init(void)
 	else if (i == 1)
 	  flashbase = PHYS_FLASH_2;
 	else
-	  panic("configured to many flash banks!\n");
+	  panic("configured too many flash banks!\n");
 	for (j = 0; j < flash_info[i].sector_count; j++)
 	{
 	    if (j <= 7)

board/innokom/flash.c

@@ -276,7 +276,7 @@ ulong flash_init(void)
 				flashbase = PHYS_FLASH_1;
 				break;
 			default:
-				panic("configured to many flash banks!\n");
+				panic("configured too many flash banks!\n");
 				break;
 		}
 		for (j = 0; j < flash_info[i].sector_count; j++) {

board/lart/flash.c

@@ -86,7 +86,7 @@ ulong flash_init(void)
 	if (i == 0)
 	  flashbase = PHYS_FLASH_1;
 	else
-	  panic("configured to many flash banks!\n");
+	  panic("configured too many flash banks!\n");
 	for (j = 0; j < flash_info[i].sector_count; j++)
 	{
 	    if (j <= 7)

board/logodl/flash.c

@@ -91,7 +91,7 @@ ulong flash_init(void)
 		flashbase = PHYS_FLASH_2;
 		break;
 	   default:
-		panic("configured to many flash banks!\n");
+		panic("configured too many flash banks!\n");
 		break;
 	}
 	for (j = 0; j < flash_info[i].sector_count; j++)

board/lubbock/flash.c

@@ -76,7 +76,7 @@ unsigned long flash_init (void)
 			flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
 			break;
 		default:
-			panic ("configured to many flash banks!\n");
+			panic ("configured too many flash banks!\n");
 			break;
 		}
 		size += flash_info[i].size;

board/ml2/flash.c

@@ -72,7 +72,7 @@ ulong flash_init(void) {
 		if (i==0)
 			flashbase = CFG_FLASH_BASE;
 		else
-			panic("configured to many flash banks!\n");
+			panic("configured too many flash banks!\n");
 		for (j = 0; j < flash_info[i].sector_count; j++)
 				flash_info[i].start[j]=flashbase + j * SECT_SIZE;
 

board/mpc8266ads/mpc8266ads.c

@@ -46,7 +46,7 @@
  *   PSDMR_BUFCMD adds a clock
  *   0            no extra clock
  */
-#define CONFIG_PBI		PSDMR_PBI
+#define CONFIG_PBI		0
 #define PESSIMISTIC_SDRAM	0
 #define EAMUX			0	/* EST requires EAMUX */
 #define BUFCMD			0
@@ -427,7 +427,7 @@ long int initdram(int board_type)
     bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
     sda10 = sdam + 2;
 #else
-    sdam = cols - 6;
+    sdam = cols + banks - 8;
     bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
     sda10 = sdam;
 #endif
@@ -557,9 +557,18 @@ long int initdram(int board_type)
 	printf("SDRAM configuration read from SPD\n");
 	printf("\tSize per side = %dMB\n", sdram_size >> 20);
 	printf("\tOrganization: %d sides, %d banks, %d Columns, %d Rows, Data width = %d bits\n", chipselects, 1<<(banks), cols, rows, data_width);
-	printf("\tRefresh rate = %d, CAS latency = %d\n", psrt, caslatency);
+	printf("\tRefresh rate = %d, CAS latency = %d", psrt, caslatency);
+#if(CONFIG_PBI == 0)	/* bank-based interleaving */
+    printf(", Using Bank Based Interleave\n");
+#else
+    printf(", Using Page Based Interleave\n");
+#endif    
 	printf("\tTotal size: ");
 
+    /* this delay only needed for original 16MB DIMM... 
+     * Not needed for any other memory configuration */
+    if ((sdram_size * chipselects) == (16 *1024 *1024))
+        udelay (250000);
     return (sdram_size * chipselects);
 	/*return (16 * 1024 * 1024);*/
 }
@@ -575,3 +584,4 @@ void pci_init_board(void)
 	pci_mpc8250_init(&hose);
 }
 #endif
+

board/mpl/vcma9/cmd_vcma9.c

@@ -41,9 +41,12 @@ static uchar cs8900_chksum(ushort data)
 #endif
 
 extern void print_vcma9_info(void);
-extern int vcma9_cantest(void);
+extern int vcma9_cantest(int);
 extern int vcma9_nandtest(void);
-extern int vcma9_dactest(void);
+extern int vcma9_nanderase(void);
+extern int vcma9_nandread(ulong);
+extern int vcma9_nandwrite(ulong);
+extern int vcma9_dactest(int);
 extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 
 /* ------------------------------------------------------------------------- */
@@ -126,18 +129,53 @@ int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #endif
 #if 0
 	if (strcmp(argv[1], "cantest") == 0) {
-		vcma9_cantest();
+		if (argc >= 3)
+			vcma9_cantest(strcmp(argv[2], "s") ? 0 : 1);
+		else
+			vcma9_cantest(0);
 		return 0;
 	}
 	if (strcmp(argv[1], "nandtest") == 0) {
 		vcma9_nandtest();
 		return 0;
 	}
+	if (strcmp(argv[1], "nanderase") == 0) {
+		vcma9_nanderase();
+		return 0;
+	}
+	if (strcmp(argv[1], "nandread") == 0) {
+		ulong offset = 0;
+
+		if (argc >= 3)
+			offset = simple_strtoul(argv[2], NULL, 16);
+
+		vcma9_nandread(offset);
+		return 0;
+	}
+	if (strcmp(argv[1], "nandwrite") == 0) {
+		ulong offset = 0;
+
+		if (argc >= 3)
+			offset = simple_strtoul(argv[2], NULL, 16);
+
+		vcma9_nandwrite(offset);
+		return 0;
+	}
 	if (strcmp(argv[1], "dactest") == 0) {
-		vcma9_dactest();
+		if (argc >= 3)
+			vcma9_dactest(strcmp(argv[2], "s") ? 0 : 1);
+		else
+		vcma9_dactest(0);
 		return 0;
 	}
 #endif
 
 	return (do_mplcommon(cmdtp, flag, argc, argv));
 }
+
+U_BOOT_CMD(
+	vcma9, 6, 1, do_vcma9,
+	"vcma9   - VCMA9 specific commands\n",
+	"flash mem [SrcAddr]\n    - updates U-Boot with image in memory\n"
+);
+

board/mpl/vcma9/config.mk

@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2002
+# (C) Copyright 2002, 2003
 # David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
 #
 # MPL VCMA9 board with S3C2410X (ARM920T) cpu
@@ -8,17 +8,17 @@
 #
 
 #
-# MPL VCMA9 has 1 bank of 64 MB DRAM
-#
-# 3000'0000 to 3400'0000
+# MPL VCMA9 has 1 bank of minimal 16 MB DRAM
+# from 0x30000000
 #
 # Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
-# optionally with a ramdisk at 3080'0000
+# optionally with a ramdisk at 3040'0000
 #
-# we load ourself to 33F8'0000
+# we load ourself to 30F8'0000
 #
-# download area is 3300'0000
+# download area is 3080'0000
 #
 
 
+#TEXT_BASE = 0x30F80000
 TEXT_BASE = 0x33F80000

board/mpl/vcma9/flash.c

@@ -80,7 +80,7 @@ ulong flash_init(void)
 	if (i == 0)
 	  flashbase = PHYS_FLASH_1;
 	else
-	  panic("configured to many flash banks!\n");
+	  panic("configured too many flash banks!\n");
 	for (j = 0; j < flash_info[i].sector_count; j++)
 	{
 	    if (j <= 3)

board/mpl/vcma9/memsetup.S

@@ -34,7 +34,9 @@
 
 /* some parameters for the board */
 
-#define BWSCON	0x48000000
+#define BWSCON		0x48000000
+#define PLD_BASE	0x2C000000
+#define SDRAM_REG	0x2C000106
 
 /* BWSCON */
 #define DW8		 	(0x0)
@@ -43,6 +45,9 @@
 #define WAIT		 	(0x1<<2)
 #define UBLB		 	(0x1<<3)
 
+/* BANKSIZE */
+#define BURST_EN		(0x1<<7)
+
 #define B1_BWSCON	  	(DW16)
 #define B2_BWSCON	  	(DW32)
 #define B3_BWSCON	  	(DW32)
@@ -130,24 +135,39 @@ memsetup:
 	/* memory control configuration */
 	/* make r0 relative the current location so that it */
 	/* reads SMRDATA out of FLASH rather than memory ! */
-	ldr     r0, =SMRDATA
+	ldr     r0, =CSDATA
 	ldr	r1, _TEXT_BASE
 	sub	r0, r0, r1
 	ldr	r1, =BWSCON	/* Bus Width Status Controller */
-	add     r2, r0, #13*4
+	add     r2, r0, #CSDATA_END-CSDATA
 0:
 	ldr     r3, [r0], #4
 	str     r3, [r1], #4
 	cmp     r2, r0
 	bne     0b
 
+	/* PLD access is now possible */
+	/* r0 == SDRAMDATA */
+	/* r1 == SDRAM controller regs */
+	ldr	r2, =PLD_BASE
+	ldrb	r3, [r2, #SDRAM_REG-PLD_BASE]
+	mov	r4, #SDRAMDATA1_END-SDRAMDATA
+	/* calculate start and end point */
+	mla	r0, r3, r4, r0 
+	add     r2, r0, r4
+0:
+	ldr     r3, [r0], #4
+	str     r3, [r1], #4
+	cmp     r2, r0
+	bne     0b
+	
 	/* everything is fine now */
 	mov	pc, lr
 
 	.ltorg
 /* the literal pools origin */
 
-SMRDATA:
+CSDATA:
     .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
     .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
     .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
@@ -155,9 +175,38 @@ SMRDATA:
     .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
     .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
     .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
+CSDATA_END:
+
+SDRAMDATA:
+/* 4Mx8x4 */
     .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
     .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
     .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
-    .word 0x32
+    .word 0x32 + BURST_EN
+    .word 0x30
+    .word 0x30
+SDRAMDATA1_END:
+
+/* 8Mx8x4 (not implemented yet) */
+    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+    .word 0x32 + BURST_EN
+    .word 0x30
+    .word 0x30
+    
+/* 2Mx8x4 (not implemented yet) */
+    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+    .word 0x32 + BURST_EN
+    .word 0x30
+    .word 0x30
+    
+/* 4Mx8x2 (not implemented yet) */
+    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+    .word 0x32 + BURST_EN
     .word 0x30
     .word 0x30

board/mpl/vcma9/vcma9.c

@@ -130,16 +130,6 @@ int board_init(void)
 	return 0;
 }
 
-int dram_init(void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return 0;
-}
-
 /*
  * NAND flash initialization.
  */
@@ -162,9 +152,16 @@ static inline void NF_Reset(void)
 
 static inline void NF_Init(void)
 {
+#if 0 /* a little bit too optimistic */
 #define TACLS   0
 #define TWRPH0  3
 #define TWRPH1  0
+#else
+#define TACLS   0
+#define TWRPH0  4
+#define TWRPH1  2
+#endif
+
     NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0));
     /*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */
     /* 1  1    1     1,   1      xxx,  r xxx,   r xxx */
@@ -177,15 +174,12 @@ void
 nand_init(void)
 {
 	S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
-	unsigned totlen;
 
 	NF_Init();
 #ifdef DEBUG
 	printf("NAND flash probing at 0x%.8lX\n", (ulong)nand);
 #endif
-	totlen = nand_probe((ulong)nand) >> 20;
-
-	printf ("%4lu MB\n", totlen >> 20);
+	printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20);
 }
 #endif
 
@@ -193,41 +187,102 @@ nand_init(void)
  * Get some Board/PLD Info
  */
 
-static uchar Get_PLD_ID(void)
+static u8 Get_PLD_ID(void)
 {
-	return(*(volatile uchar *)PLD_ID_REG);
+	VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
+	
+	return(pld->ID);
 }
 
-static uchar Get_PLD_BOARD(void)
+static u8 Get_PLD_BOARD(void)
 {
-	return(*(volatile uchar *)PLD_BOARD_REG);
+	VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
+	
+	return(pld->BOARD);
 }
 
-static uchar Get_PLD_Version(void)
+static u8 Get_PLD_SDRAM(void)
+{
+	VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
+	
+	return(pld->SDRAM);
+}
+
+static u8 Get_PLD_Version(void)
 {
 	return((Get_PLD_ID() >> 4) & 0x0F);
 }
 
-static uchar Get_PLD_Revision(void)
+static u8 Get_PLD_Revision(void)
 {
 	return(Get_PLD_ID() & 0x0F);
 }
 
+#if 0	/* not used */
 static int Get_Board_Config(void)
 {
-	uchar config = Get_PLD_BOARD() & 0x03;
+	u8 config = Get_PLD_BOARD() & 0x03;
 
 	if (config == 3)
 	    return 1;
 	else
 	    return 0;
 }
+#endif
 
 static uchar Get_Board_PCB(void)
 {
 	return(((Get_PLD_BOARD() >> 4) & 0x03) + 'A');
 }
 
+static u8 Get_SDRAM_ChipNr(void)
+{
+	switch ((Get_PLD_SDRAM() >> 4) & 0x0F) {
+		case 0: return 4;
+		case 1: return 1;
+		case 2: return 2;
+		default: return 0;
+	}
+}
+
+static ulong Get_SDRAM_ChipSize(void)
+{
+	switch (Get_PLD_SDRAM() & 0x0F) {
+		case 0: return 16 * (1024*1024);
+		case 1: return 32 * (1024*1024);
+		case 2: return  8 * (1024*1024);
+		case 3: return  8 * (1024*1024);
+		default: return 0;
+	}	
+}
+static const char * Get_SDRAM_ChipGeom(void)
+{
+	switch (Get_PLD_SDRAM() & 0x0F) {
+		case 0: return "4Mx8x4";
+		case 1: return "8Mx8x4";
+		case 2: return "2Mx8x4";
+		case 3: return "4Mx8x2";
+		default: return "unknown";
+	}
+}
+
+static void Show_VCMA9_Info(char *board_name, char *serial)
+{
+	printf("Board: %s SN: %s  PCB Rev: %c PLD(%d,%d)\n",
+		board_name, serial, Get_Board_PCB(), Get_PLD_Version(), Get_PLD_Revision());
+	printf("SDRAM: %d chips %s\n", Get_SDRAM_ChipNr(), Get_SDRAM_ChipGeom());
+}
+
+int dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = Get_SDRAM_ChipSize() * Get_SDRAM_ChipNr();
+
+	return 0;
+}
+
 /* ------------------------------------------------------------------------- */
 
 /*
@@ -240,8 +295,6 @@ int checkboard(void)
 	int i;
 	backup_t *b = (backup_t *) s;
 
-	puts("Board: ");
-
 	i = getenv_r("serial#", s, 32);
 	if ((i < 0) || strncmp (s, "VCMA9", 5)) {
 		get_backup_values (b);
@@ -249,32 +302,23 @@ int checkboard(void)
 			puts ("### No HW ID - assuming VCMA9");
 		} else {
 			b->serial_name[5] = 0;
-			printf ("%s-%d PCB Rev %c SN: %s", b->serial_name, Get_Board_Config(),
-					Get_Board_PCB(), &b->serial_name[6]);
+			Show_VCMA9_Info(b->serial_name, &b->serial_name[6]);
 		}
 	} else {
 		s[5] = 0;
-		printf ("%s-%d PCB Rev %c SN: %s", s, Get_Board_Config(), Get_Board_PCB(),
-				&s[6]);
+		Show_VCMA9_Info(s, &s[6]);
 	}
-	printf("\n");
+	/*printf("\n");*/
 	return(0);
 }
 
 
-void print_vcma9_rev(void)
-{
-	printf("Board: VCMA9-%d PCB Rev: %c (PLD Ver: %d, Rev: %d)\n",
-		Get_Board_Config(), Get_Board_PCB(),
-		Get_PLD_Version(), Get_PLD_Revision());
-}
-
 extern void mem_test_reloc(void);
 
 int last_stage_init(void)
 {
 	mem_test_reloc();
-	print_vcma9_rev();
+	checkboard();
 	show_stdio_dev();
 	check_env();
 	return 0;
@@ -295,6 +339,15 @@ int overwrite_console(void)
 * Print VCMA9 Info
 ************************************************************************/
 void print_vcma9_info(void)
-{
-    print_vcma9_rev();
+{	
+	unsigned char s[50];
+	int i;
+	
+	if ((i = getenv_r("serial#", s, 32)) < 0) {
+		puts ("### No HW ID - assuming VCMA9");
+		printf("i %d", i*24);
+	} else {
+		s[5] = 0;
+		Show_VCMA9_Info(s, &s[6]);
+	}
 }

board/mpl/vcma9/vcma9.h

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2002
+ * (C) Copyright 2002, 2003
  * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
  *
  * See file CREDITS for list of people who contributed to this
@@ -116,11 +116,19 @@ static inline u32 NF_Read_ECC(void)
 
 #endif
 
+/* VCMA9 PLD regsiters */
+typedef struct {
+	S3C24X0_REG8	ID;
+	S3C24X0_REG8	NIC;
+	S3C24X0_REG8	CAN;
+	S3C24X0_REG8	MISC;
+	S3C24X0_REG8	GPCD;
+	S3C24X0_REG8	BOARD;
+	S3C24X0_REG8	SDRAM;
+} /*__attribute__((__packed__))*/ VCMA9_PLD;
 
-#define PLD_BASE_ADDRESS		0x2C000100
-#define PLD_ID_REG			(PLD_BASE_ADDRESS + 0)
-#define PLD_NIC_REG			(PLD_BASE_ADDRESS + 1)
-#define PLD_CAN_REG			(PLD_BASE_ADDRESS + 2)
-#define PLD_MISC_REG			(PLD_BASE_ADDRESS + 3)
-#define PLD_GPCD_REG			(PLD_BASE_ADDRESS + 4)
-#define PLD_BOARD_REG			(PLD_BASE_ADDRESS + 5)
+#define VCMA9_PLD_BASE	0x2C000100
+static inline VCMA9_PLD * const VCMA9_GetBase_PLD(void)
+{
+	return (VCMA9_PLD * const)VCMA9_PLD_BASE;
+}

board/omap1510inn/flash.c

@@ -72,7 +72,7 @@ unsigned long flash_init (void)
 			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
 			break;
 		default:
-			panic ("configured to many flash banks!\n");
+			panic ("configured too many flash banks!\n");
 			break;
 		}
 		size += flash_info[i].size;

board/omap1610inn/flash.c

@@ -96,7 +96,7 @@ unsigned long flash_init (void)
 			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
 			break;
 		default:
-			panic ("configured to many flash banks!\n");
+			panic ("configured too many flash banks!\n");
 			break;
 		}
 		size += flash_info[i].size;

board/sacsng/sacsng.c

@@ -28,11 +28,18 @@
 #include <mpc8260.h>
 #include <i2c.h>
 #include <spi.h>
+#include <command.h>
 
 #ifdef CONFIG_SHOW_BOOT_PROGRESS
 #include <status_led.h>
 #endif
 
+#ifdef CONFIG_ETHER_LOOPBACK_TEST
+extern void eth_loopback_test(void);
+#endif /* CONFIG_ETHER_LOOPBACK_TEST */
+
+extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
 #include "clkinit.h"
 #include "ioconfig.h" /* I/O configuration table */
 
@@ -243,15 +250,15 @@ long int initdram(int board_type)
 
     /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */
     if(caslatency < 2) {
-	printf("CL was %d, forcing to 2\n", caslatency);
+	printf("WARNING: CL was %d, forcing to 2\n", caslatency);
 	caslatency = 2;
     }
     if(rows > 14) {
-	printf("This doesn't look good, rows = %d, should be <= 14\n", rows);
+	printf("WARNING: This doesn't look good, rows = %d, should be <= 14\n", rows);
 	rows = 14;
     }
     if(cols > 11) {
-	printf("This doesn't look good, columns = %d, should be <= 11\n", cols);
+	printf("WARNING: This doesn't look good, columns = %d, should be <= 11\n", cols);
 	cols = 11;
     }
 
@@ -450,6 +457,15 @@ int misc_init_r(void)
     int  sample_128x;  /* Use 128/4 clocking for the ADC/DAC */
     int  right_just;   /* Is the data to the DAC right justified? */
     int  mclk_divide;  /* MCLK Divide */
+    int  quiet;        /* Quiet or minimal output mode */
+
+    quiet = 0;
+    if ((ep = getenv("quiet")) != NULL) {
+	quiet = simple_strtol(ep, NULL, 10);
+    }
+    else {
+	setenv("quiet", "0");
+    }
 
     /*
      * SACSng custom initialization:
@@ -517,8 +533,12 @@ int misc_init_r(void)
 	setenv("Daq128xSampling", "1");
     }
 
-    /* Display the ADC/DAC clocking information */
-    Daq_Display_Clocks();
+    /* 
+     * Display the ADC/DAC clocking information 
+     */
+    if (!quiet) {
+        Daq_Display_Clocks();
+    }
 
     /*
      * Determine the DAC data justification
@@ -552,8 +572,10 @@ int misc_init_r(void)
      * 3) Write the I2C address to register 6
      * 4) Enable address matching by setting the MSB in register 7
      */
-
-    printf("Initializing the ADC...\n");
+    
+    if (!quiet) {
+        printf("Initializing the ADC...\n");
+    }
     udelay(ADC_INITIAL_DELAY);		/* 10uSec per uF of VREF cap */
 
     iopa->pdat &= ~ADC_SDATA1_MASK;     /* release SDATA1 */
@@ -615,7 +637,9 @@ int misc_init_r(void)
      * sending an I2C "start" sequence.  When we bring the I2C back to
      * the normal state, we send an I2C "stop" sequence.
      */
-    printf("Initializing the DAC...\n");
+    if (!quiet) {
+	printf("Initializing the DAC...\n");
+    }
 
     /*
      * Bring the I2C clock and data lines low for initialization
@@ -695,7 +719,16 @@ int misc_init_r(void)
     I2C_DELAY;
     I2C_TRISTATE;
 
-    printf("\n");
+    if (!quiet) {
+        printf("\n");
+    }
+
+#ifdef CONFIG_ETHER_LOOPBACK_TEST
+    /*
+     * Run the Ethernet loopback test
+     */
+    eth_loopback_test ();
+#endif /* CONFIG_ETHER_LOOPBACK_TEST */
 
 #ifdef CONFIG_SHOW_BOOT_PROGRESS
     /*
@@ -758,17 +791,44 @@ static int last_boot_progress;
 
 void show_boot_progress (int status)
 {
-    if(status != -1) {
+    int i,j;
+    if(status > 0) {
 	last_boot_progress = status;
     } else {
-	/*
-	 * Houston, we have a problem.  Blink the last OK status which
-	 * indicates where things failed.
+        /* 
+	 * If a specific failure code is given, flash this code
+	 * else just use the last success code we've seen
 	 */
-	status_led_set(STATUS_LED_RED, STATUS_LED_ON);
-	flash_code(last_boot_progress, 5, 3);
-	udelay(1000000);
-	status_led_set(STATUS_LED_RED, STATUS_LED_BLINKING);
+	if(status < -1)
+	    last_boot_progress = -status;
+	
+	/* 
+	 * Flash this code 5 times
+	 */
+	for(j=0; j<5; j++) {
+	    /*
+	     * Houston, we have a problem.
+	     * Blink the last OK status which indicates where things failed.
+	     */
+	    status_led_set(STATUS_LED_RED, STATUS_LED_ON);
+	    flash_code(last_boot_progress, 5, 3);
+
+	    /* 
+	     * Delay 5 seconds between repetitions, 
+	     * with the fault LED blinking 
+	     */
+	    for(i=0; i<5; i++) {
+	    	status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
+	    	udelay(500000);
+	    	status_led_set(STATUS_LED_RED, STATUS_LED_ON);
+	    	udelay(500000);
+	    }
+	}
+
+	/*
+	 * Reset the board to retry initialization.
+	 */
+	do_reset (NULL, 0, 0, NULL);
     }
 }
 #endif /* CONFIG_SHOW_BOOT_PROGRESS */

board/sc520_cdp/flash.c

@@ -234,7 +234,7 @@ ulong flash_init(void)
 			flashbase = SC520_FLASH_BANK2_BASE;
 			break;
 		default:
-			panic("configured to many flash banks!\n");
+			panic("configured too many flash banks!\n");
 		}
 
 		id = identify_flash(flashbase, 4);

board/sc520_cdp/flash_old.c

@@ -101,7 +101,7 @@ ulong flash_init(void)
 			flashbase = SC520_FLASH_BANK0_BASE;
 			break;
 		default:
-			panic("configured to many flash banks!\n");
+			panic("configured too many flash banks!\n");
 		}
 
 		for (j = 0; j < flash_info[i].sector_count; j++) {

board/sc520_spunk/flash.c

@@ -239,7 +239,7 @@ ulong flash_init(void)
 			flashbase = SC520_FLASH_BANK0_BASE;
 			break;
 		default:
-			panic("configured to many flash banks!\n");
+			panic("configured too many flash banks!\n");
 		}
 
 		id = identify_flash(flashbase, 2);

board/shannon/flash.c

@@ -73,7 +73,7 @@ ulong flash_init(void)
 	if (i == 0)
 	  flashbase = PHYS_FLASH_1;
 	else
-	  panic("configured to many flash banks!\n");
+	  panic("configured too many flash banks!\n");
 	for (j = 0; j < flash_info[i].sector_count; j++)
 	{
 

board/shannon/shannon.c

@@ -60,7 +60,7 @@ int board_init (void)
 	*(unsigned long *)temp = 0x00060006;
 
 	}
-#endif /* CONFIG_INIT_CRITICAL */
+#endif /* CONFIG_INFERNO */
 
 	/* arch number for shannon */
 	gd->bd->bi_arch_number = 97;

board/sixnet/sixnet.c

@@ -330,7 +330,7 @@ int misc_init_r (void)
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
 void nand_init(void)
 {
-	unsigned long totlen = nand_probe(CFG_NAND_BASE);
+	unsigned long totlen = nand_probe(CFG_DFLASH_BASE);
 
 	printf ("%4lu MB\n", totlen >> 20);
 }

board/smdk2410/flash.c

@@ -80,7 +80,7 @@ ulong flash_init(void)
 	if (i == 0)
 	  flashbase = PHYS_FLASH_1;
 	else
-	  panic("configured to many flash banks!\n");
+	  panic("configured too many flash banks!\n");
 	for (j = 0; j < flash_info[i].sector_count; j++)
 	{
 	    if (j <= 3)

board/trab/Makefile

@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= lib$(BOARD).a
 
-OBJS	:= trab.o flash.o vfd.o cmd_trab.o memory.o tsc2000.o
+OBJS	:= trab.o flash.o vfd.o cmd_trab.o memory.o tsc2000.o auto_update.o
 SOBJS	:= memsetup.o
 
 gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)

board/trab/auto_update.c

@@ -0,0 +1,594 @@
+/*
+ * (C) Copyright 2003
+ * Gary Jennejohn, DENX Software Engineering, gj@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <image.h>
+#include <asm/byteorder.h>
+#include <usb.h>
+
+#ifdef CFG_HUSH_PARSER
+#include <hush.h>
+#endif
+
+#ifdef CONFIG_AUTO_UPDATE
+
+#ifndef CONFIG_USB_OHCI
+#error "must define CONFIG_USB_OHCI"
+#endif
+
+#ifndef CONFIG_USB_STORAGE
+#error "must define CONFIG_USB_STORAGE"
+#endif
+
+#ifndef CFG_HUSH_PARSER
+#error "must define CFG_HUSH_PARSER"
+#endif
+
+#if !(CONFIG_COMMANDS & CFG_CMD_FAT)
+#error "must define CFG_CMD_FAT"
+#endif
+
+/*
+ * Check whether a USB memory stick is plugged in.
+ * If one is found:
+ *	1) if prepare.img ist found load it into memory. If it is
+ *		valid then run it.
+ *	2) if preinst.img is found load it into memory. If it is
+ *		valid then run it. Update the EEPROM.
+ *	3) if firmware.img is found load it into memory. If it is valid,
+ *		burn it into FLASH and update the EEPROM.
+ *	4) if kernel.img is found load it into memory. If it is valid,
+ *		burn it into FLASH and update the EEPROM.
+ *	5) if app.img is found load it into memory. If it is valid,
+ *		burn it into FLASH and update the EEPROM.
+ *	6) if disk.img is found load it into memory. If it is valid,
+ *		burn it into FLASH and update the EEPROM.
+ *	7) if postinst.img is found load it into memory. If it is
+ *		valid then run it. Update the EEPROM.
+ */
+
+#undef AU_DEBUG
+
+#undef debug
+#ifdef	AU_DEBUG
+#define debug(fmt,args...)	printf (fmt ,##args)
+#else
+#define debug(fmt,args...)
+#endif	/* AU_DEBUG */
+
+/* possible names of files on the USB stick. */
+#define AU_PREPARE	"prepare.img"
+#define AU_PREINST	"preinst.img"
+#define AU_FIRMWARE	"firmware.img"
+#define AU_KERNEL	"kernel.img"
+#define AU_APP		"app.img"
+#define AU_DISK		"disk.img"
+#define AU_POSTINST	"postinst.img"
+
+struct flash_layout
+{
+	long start;
+	long end;
+};
+
+/* layout of the FLASH. ST = start address, ND = end address. */
+#ifndef CONFIG_FLASH_8MB			/* 16 MB Flash, 32 MB RAM */
+#define AU_FL_FIRMWARE_ST	0x00000000
+#define AU_FL_FIRMWARE_ND	0x0009FFFF
+#define AU_FL_VFD_ST		0x000A0000
+#define AU_FL_VFD_ND		0x000BFFFF
+#define AU_FL_KERNEL_ST		0x000C0000
+#define AU_FL_KERNEL_ND		0x001BFFFF
+#define AU_FL_APP_ST		0x001C0000
+#define AU_FL_APP_ND		0x005BFFFF
+#define AU_FL_DISK_ST		0x005C0000
+#define AU_FL_DISK_ND		0x00FFFFFF
+#else						/*  8 MB Flash, 16 MB RAM */
+#define AU_FL_FIRMWARE_ST	0x00000000
+#define AU_FL_FIRMWARE_ND	0x0003FFFF
+#define AU_FL_KERNEL_ST		0x00040000
+#define AU_FL_KERNEL_ND		0x0011FFFF
+#define AU_FL_APP_ST		0x00120000
+#define AU_FL_APP_ND		0x003FFFFF
+#define AU_FL_DISK_ST		0x00400000
+#define AU_FL_DISK_ND		0x007DFFFF
+#define AU_FL_VFD_ST		0x007E0000
+#define AU_FL_VFD_ND		0x007FFFFF
+#endif	/* CONFIG_FLASH_8MB */
+
+/* a structure with the offsets to values in the EEPROM */
+struct eeprom_layout
+{
+	int time;
+	int size;
+	int dcrc;
+};
+
+/* layout of the EEPROM - offset from the start. All entries are 32 bit. */
+#define AU_EEPROM_TIME_PREINST	64
+#define AU_EEPROM_SIZE_PREINST	68
+#define AU_EEPROM_DCRC_PREINST	72
+#define AU_EEPROM_TIME_FIRMWARE	76
+#define AU_EEPROM_SIZE_FIRMWARE	80
+#define AU_EEPROM_DCRC_FIRMWARE	84
+#define AU_EEPROM_TIME_KERNEL	88
+#define AU_EEPROM_SIZE_KERNEL	92
+#define AU_EEPROM_DCRC_KERNEL	96
+#define AU_EEPROM_TIME_APP	100
+#define AU_EEPROM_SIZE_APP	104
+#define AU_EEPROM_DCRC_APP	108
+#define AU_EEPROM_TIME_DISK	112
+#define AU_EEPROM_SIZE_DISK	116
+#define AU_EEPROM_DCRC_DISK	120
+#define AU_EEPROM_TIME_POSTINST 124
+#define AU_EEPROM_SIZE_POSTINST 128
+#define AU_EEPROM_DCRC_POSTINST 132
+
+static int au_usb_stor_curr_dev; /* current device */
+
+/* index of each file in the following arrays */
+#define IDX_PREPARE	0
+#define IDX_PREINST	1
+#define IDX_FIRMWARE	2
+#define IDX_KERNEL	3
+#define IDX_APP		4
+#define IDX_DISK	5
+#define IDX_POSTINST	6
+/* max. number of files which could interest us */
+#define AU_MAXFILES 7
+/* pointers to file names */
+char *aufile[AU_MAXFILES];
+/* sizes of flash areas for each file */
+long ausize[AU_MAXFILES];
+/* offsets into the EEEPROM */
+struct eeprom_layout auee_off[AU_MAXFILES] = { \
+	{0}, \
+	{AU_EEPROM_TIME_PREINST, AU_EEPROM_SIZE_PREINST, AU_EEPROM_DCRC_PREINST,}, \
+	{AU_EEPROM_TIME_FIRMWARE, AU_EEPROM_SIZE_FIRMWARE, AU_EEPROM_DCRC_FIRMWARE,}, \
+	{AU_EEPROM_TIME_KERNEL, AU_EEPROM_SIZE_KERNEL, AU_EEPROM_DCRC_KERNEL,}, \
+	{AU_EEPROM_TIME_APP, AU_EEPROM_SIZE_APP, AU_EEPROM_DCRC_APP,}, \
+	{AU_EEPROM_TIME_DISK, AU_EEPROM_SIZE_DISK, AU_EEPROM_DCRC_DISK,}, \
+	{AU_EEPROM_TIME_POSTINST, AU_EEPROM_SIZE_POSTINST, AU_EEPROM_DCRC_POSTINST,} \
+	};
+/* array of flash areas start and end addresses */
+struct flash_layout aufl_layout[AU_MAXFILES - 3] = { \
+	{AU_FL_FIRMWARE_ST, AU_FL_FIRMWARE_ND,}, \
+	{AU_FL_KERNEL_ST, AU_FL_KERNEL_ND,}, \
+	{AU_FL_APP_ST, AU_FL_APP_ND,}, \
+	{AU_FL_DISK_ST, AU_FL_DISK_ND,}, \
+};
+/* convert the index into aufile[] to an index into aufl_layout[] */
+#define FIDX_TO_LIDX(idx) ((idx) - 2)
+
+/* where to load files into memory */
+#define LOAD_ADDR ((unsigned char *)0x0C100100)
+/* where to build strings in memory - 256 bytes should be enough */
+#define STRING_ADDR ((char *)0x0C100000)
+/* the disk is the largest image */
+#define MAX_LOADSZ ausize[IDX_DISK]
+
+/* externals */
+extern int fat_register_device(block_dev_desc_t *, int);
+extern int file_fat_detectfs(void);
+extern long file_fat_read(const char *, void *, unsigned long);
+extern int i2c_read (unsigned char, unsigned int, int , unsigned char* , int);
+extern int i2c_write (uchar, uint, int , uchar* , int);
+#ifdef CONFIG_VFD
+extern int trab_vfd (ulong);
+extern int transfer_pic(unsigned char, unsigned char *, int, int);
+#endif
+/* change char* to void* to shutup the compiler */
+extern int i2c_write_multiple (uchar, uint, int, void *, int);
+extern int i2c_read_multiple (uchar, uint, int, void *, int);
+extern block_dev_desc_t *get_dev (char*, int);
+
+int
+au_check_valid(int idx, long nbytes)
+{
+	image_header_t *hdr;
+	unsigned long checksum;
+	unsigned char buf[4];
+
+	hdr = (image_header_t *)LOAD_ADDR;
+	/* check the easy ones first */
+#undef CHECK_VALID_DEBUG
+#ifdef CHECK_VALID_DEBUG
+	printf("magic %#x %#x ", ntohl(hdr->ih_magic), IH_MAGIC);
+	printf("arch %#x %#x ", hdr->ih_arch, IH_CPU_ARM);
+	printf("size %#x %#lx ", ntohl(hdr->ih_size), nbytes);
+	printf("type %#x %#x ", hdr->ih_type, IH_TYPE_KERNEL);
+#endif
+	if (ntohl(hdr->ih_magic) != IH_MAGIC ||
+	    hdr->ih_arch != IH_CPU_ARM ||
+	    nbytes < ntohl(hdr->ih_size))
+	{
+		printf ("Image %s bad MAGIC or ARCH or SIZE\n", aufile[idx]);
+		return -1;
+	}
+	/* check the hdr CRC */
+	checksum = ntohl(hdr->ih_hcrc);
+	hdr->ih_hcrc = 0;
+
+	if (crc32 (0, (char *)hdr, sizeof(*hdr)) != checksum) {
+		printf ("Image %s bad header checksum\n", aufile[idx]);
+		return -1;
+	}
+	hdr->ih_hcrc = htonl(checksum);
+	/* check the data CRC */
+	checksum = ntohl(hdr->ih_dcrc);
+
+	if (crc32 (0, (char *)(LOAD_ADDR + sizeof(*hdr)), ntohl(hdr->ih_size))
+		!= checksum)
+	{
+		printf ("Image %s bad data checksum\n", aufile[idx]);
+		return -1;
+	}
+	/* check the type - could do this all in one gigantic if() */
+	if ((idx == IDX_FIRMWARE) && (hdr->ih_type != IH_TYPE_FIRMWARE)) {
+		printf ("Image %s wrong type\n", aufile[idx]);
+		return -1;
+	}
+	if ((idx == IDX_KERNEL) && (hdr->ih_type != IH_TYPE_KERNEL)) {
+		printf ("Image %s wrong type\n", aufile[idx]);
+		return -1;
+	}
+	if ((idx == IDX_DISK || idx == IDX_APP)
+		&& (hdr->ih_type != IH_TYPE_RAMDISK))
+	{
+		printf ("Image %s wrong type\n", aufile[idx]);
+		return -1;
+	}
+	if ((idx == IDX_PREPARE || idx == IDX_PREINST || idx == IDX_POSTINST)
+		&& (hdr->ih_type != IH_TYPE_SCRIPT))
+	{
+		printf ("Image %s wrong type\n", aufile[idx]);
+		return -1;
+	}
+	/* special case for prepare.img */
+	if (idx == IDX_PREPARE)
+		return 0;
+	/* check the size does not exceed space in flash */
+	if ((ausize[idx] != 0) && (ausize[idx] < ntohl(hdr->ih_size))) {
+		printf ("Image %s is bigger than FLASH\n", aufile[idx]);
+		return -1;
+	}
+	/* check the time stamp from the EEPROM */
+	/* read it in */
+	i2c_read_multiple(0x54, auee_off[idx].time, 1, buf, sizeof(buf));
+#ifdef CHECK_VALID_DEBUG
+	printf ("buf[0] %#x buf[1] %#x buf[2] %#x buf[3] %#x "
+		"as int %#x time %#x\n",
+		buf[0], buf[1], buf[2], buf[3],
+		*((unsigned int *)buf), ntohl(hdr->ih_time));
+#endif
+	/* check it */
+	if (*((unsigned int *)buf) >= ntohl(hdr->ih_time)) {
+		printf ("Image %s is too old\n", aufile[idx]);
+		return -1;
+	}
+
+	return 0;
+}
+
+/* power control defines */
+#define CPLD_VFD_BK ((volatile char *)0x04038002)
+#define POWER_OFF (1 << 1)
+
+int
+au_do_update(int idx, long sz, int repeat)
+{
+	image_header_t *hdr;
+	char *addr;
+	long start, end;
+	char *strbuf = STRING_ADDR;
+	int off;
+	uint nbytes;
+
+	hdr = (image_header_t *)LOAD_ADDR;
+
+	/* disable the power switch */
+	*CPLD_VFD_BK |= POWER_OFF;
+
+	/* execute a script */
+	if (hdr->ih_type == IH_TYPE_SCRIPT) {
+		addr = (char *)((char *)hdr + sizeof(*hdr) + 8);
+		parse_string_outer(addr,
+			FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP);
+		return 0;
+	}
+
+	start = aufl_layout[FIDX_TO_LIDX(idx)].start;
+	end = aufl_layout[FIDX_TO_LIDX(idx)].end;
+
+	/* unprotect the address range */
+	/* this assumes that ONLY the firmware is protected! */
+	if (idx == IDX_FIRMWARE) {
+#undef AU_UPDATE_TEST
+#ifdef AU_UPDATE_TEST
+		/* erase it where Linux goes */
+		start = aufl_layout[1].start;
+		end = aufl_layout[1].end;
+#endif
+		debug ("protect off %lx %lx\n", start, end);
+		sprintf(strbuf, "protect off %lx %lx\n", start, end);
+		parse_string_outer(strbuf,
+			FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP);
+	}
+
+	/*
+	 * erase the address range. Multiple erases seem to cause
+	 * problems.
+	 */
+	if (repeat == 0) {
+		debug ("erase %lx %lx\n", start, end);
+		sprintf(strbuf, "erase %lx %lx\n", start, end);
+		parse_string_outer(strbuf,
+			FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP);
+	}
+	wait_ms(100);
+	/* strip the header - except for the kernel */
+	if (idx == IDX_FIRMWARE || idx == IDX_DISK || idx == IDX_APP) {
+		addr = (char *)((char *)hdr + sizeof(*hdr));
+#ifdef AU_UPDATE_TEST
+		/* copy it to where Linux goes */
+		if (idx == IDX_FIRMWARE)
+			start = aufl_layout[1].start;
+#endif
+		off = 0;
+		nbytes = ntohl(hdr->ih_size);
+	} else {
+		addr = (char *)hdr;
+		off = sizeof(*hdr);
+		nbytes = sizeof(*hdr) + ntohl(hdr->ih_size);
+	}
+
+	/* copy the data from RAM to FLASH */
+	debug ("cp.b %p %lx %x\n", addr, start, nbytes);
+	sprintf(strbuf, "cp.b %p %lx %x\n", addr, start, nbytes);
+	parse_string_outer(strbuf,
+		FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP);
+
+	/* check the dcrc of the copy */
+	if (crc32 (0, (char *)(start + off), ntohl(hdr->ih_size)) != ntohl(hdr->ih_dcrc)) {
+		printf ("Image %s Bad Data Checksum After COPY\n", aufile[idx]);
+		return -1;
+	}
+
+	/* protect the address range */
+	/* this assumes that ONLY the firmware is protected! */
+	if (idx == IDX_FIRMWARE) {
+		debug ("protect on %lx %lx\n", start, end);
+		sprintf(strbuf, "protect on %lx %lx\n", start, end);
+		parse_string_outer(strbuf,
+			FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP);
+	}
+	return 0;
+}
+
+int
+au_update_eeprom(int idx)
+{
+	image_header_t *hdr;
+	int off;
+	uint32_t val;
+
+	hdr = (image_header_t *)LOAD_ADDR;
+	/* write the time field into EEPROM */
+	off = auee_off[idx].time;
+	val = ntohl(hdr->ih_time);
+	i2c_write_multiple(0x54, off, 1, &val, sizeof(val));
+	/* write the size field into EEPROM */
+	off = auee_off[idx].size;
+	val = ntohl(hdr->ih_size);
+	i2c_write_multiple(0x54, off, 1, &val, sizeof(val));
+	/* write the dcrc field into EEPROM */
+	off = auee_off[idx].dcrc;
+	val = ntohl(hdr->ih_dcrc);
+	i2c_write_multiple(0x54, off, 1, &val, sizeof(val));
+	/* enable the power switch */
+	*CPLD_VFD_BK &= ~POWER_OFF;
+	return 0;
+}
+
+/*
+ * this is called from board_init() after the hardware has been set up
+ * and is usable. That seems like a good time to do this.
+ * Right now the return value is ignored.
+ */
+int
+do_auto_update(void)
+{
+	block_dev_desc_t *stor_dev;
+	long sz;
+	int i, res, bitmap_first, cnt, old_ctrlc, got_ctrlc;
+	char *env;
+	long start, end;
+
+#undef ERASE_EEPROM
+#ifdef ERASE_EEPROM
+	int arr[18];
+	memset(arr, 0, sizeof(arr));
+	i2c_write_multiple(0x54, 64, 1, arr, sizeof(arr));
+#endif
+	au_usb_stor_curr_dev = -1;
+	/* start USB */
+	if (usb_stop() < 0) {
+		debug ("usb_stop failed\n");
+		return -1;
+	}
+	if (usb_init() < 0) {
+		debug ("usb_init failed\n");
+		return -1;
+	}
+	/*
+	 * check whether a storage device is attached (assume that it's
+	 * a USB memory stick, since nothing else should be attached).
+	 */
+	au_usb_stor_curr_dev = usb_stor_scan(1);
+	if (au_usb_stor_curr_dev == -1) {
+		debug ("No device found. Not initialized?\n");
+		return -1;
+	}
+	/* check whether it has a partition table */
+	stor_dev = get_dev("usb", 0);
+	if (stor_dev == NULL) {
+		debug ("uknown device type\n");
+		return -1;
+	}
+	if (fat_register_device(stor_dev, 1) != 0) {
+		debug ("Unable to use USB %d:%d for fatls\n",
+			au_usb_stor_curr_dev, 1);
+		return -1;
+	}
+	if (file_fat_detectfs() != 0) {
+		debug ("file_fat_detectfs failed\n");
+	}
+
+	/* initialize the array of file names */
+	memset(aufile, 0, sizeof(aufile));
+	aufile[IDX_PREPARE] = AU_PREPARE;
+	aufile[IDX_PREINST] = AU_PREINST;
+	aufile[IDX_FIRMWARE] = AU_FIRMWARE;
+	aufile[IDX_KERNEL] = AU_KERNEL;
+	aufile[IDX_APP] = AU_APP;
+	aufile[IDX_DISK] = AU_DISK;
+	aufile[IDX_POSTINST] = AU_POSTINST;
+	/* initialize the array of flash sizes */
+	memset(ausize, 0, sizeof(ausize));
+	ausize[IDX_FIRMWARE] = (AU_FL_FIRMWARE_ND + 1) - AU_FL_FIRMWARE_ST;
+	ausize[IDX_KERNEL] = (AU_FL_KERNEL_ND + 1) - AU_FL_KERNEL_ST;
+	ausize[IDX_APP] = (AU_FL_APP_ND + 1) - AU_FL_APP_ST;
+	ausize[IDX_DISK] = (AU_FL_DISK_ND + 1) - AU_FL_DISK_ST;
+	/*
+	 * now check whether start and end are defined using environment
+	 * variables.
+	 */
+	start = end = 0;
+	env = getenv("firmware_st");
+	if (env != NULL)
+		start = simple_strtoul(env, NULL, 16);
+	env = getenv("firmware_nd");
+	if (env != NULL)
+		end = simple_strtoul(env, NULL, 16);
+	if (start && end && end > start)
+		ausize[IDX_FIRMWARE] = (end + 1) - start;
+	start = end = 0;
+	env = getenv("kernel_st");
+	if (env != NULL)
+		start = simple_strtoul(env, NULL, 16);
+	env = getenv("kernel_nd");
+	if (env != NULL)
+		end = simple_strtoul(env, NULL, 16);
+	if (start && end && end > start)
+		ausize[IDX_KERNEL] = (end + 1) - start;
+	start = end = 0;
+	env = getenv("app_st");
+	if (env != NULL)
+		start = simple_strtoul(env, NULL, 16);
+	env = getenv("app_nd");
+	if (env != NULL)
+		end = simple_strtoul(env, NULL, 16);
+	if (start && end && end > start)
+		ausize[IDX_APP] = (end + 1) - start;
+	start = end = 0;
+	env = getenv("disk_st");
+	if (env != NULL)
+		start = simple_strtoul(env, NULL, 16);
+	env = getenv("disk_nd");
+	if (env != NULL)
+		end = simple_strtoul(env, NULL, 16);
+	if (start && end && end > start)
+		ausize[IDX_DISK] = (end + 1) - start;
+	/* make sure that we see CTRL-C and save the old state */
+	old_ctrlc = disable_ctrlc(0);
+
+	bitmap_first = 0;
+	/* just loop thru all the possible files */
+	for (i = 0; i < AU_MAXFILES; i++) {
+		sz = file_fat_read(aufile[i], LOAD_ADDR, MAX_LOADSZ);
+		debug ("read %s sz %ld hdr %d\n",
+			aufile[i], sz, sizeof(image_header_t));
+		if (sz <= 0 || sz <= sizeof(image_header_t)) {
+			debug ("%s not found\n", aufile[i]);
+			continue;
+		}
+		if (au_check_valid(i, sz) < 0) {
+			debug ("%s not valid\n", aufile[i]);
+			continue;
+		}
+#ifdef CONFIG_VFD
+		/* now that we have a valid file we can display the */
+		/* bitmap. */
+		if (bitmap_first == 0) {
+			env = getenv("bitmap2");
+			if (env == NULL) {
+				trab_vfd(0);
+			} else {
+				/* not so simple - bitmap2 is supposed to */
+				/* contain the address of the bitmap */
+				env = (char *)simple_strtoul(env, NULL, 16);
+/* NOTE: these are taken from vfd_logo.h. If that file changes then */
+/* these defines MUST also be updated! These may be wrong for bitmap2. */
+#define VFD_LOGO_WIDTH 112
+#define VFD_LOGO_HEIGHT 72
+				/* must call transfer_pic directly */
+				transfer_pic(3, env, VFD_LOGO_HEIGHT, VFD_LOGO_WIDTH);
+			}
+			bitmap_first = 1;
+		}
+#endif
+		/* this is really not a good idea, but it's what the */
+		/* customer wants. */
+		cnt = 0;
+		got_ctrlc = 0;
+		do {
+			res = au_do_update(i, sz, cnt);
+			/* let the user break out of the loop */
+			if (ctrlc() || had_ctrlc()) {
+				clear_ctrlc();
+				if (res < 0)
+					got_ctrlc = 1;
+				break;
+			}
+			cnt++;
+#ifdef AU_TEST_ONLY
+		} while (res < 0 && cnt < 3);
+		if (cnt < 3)
+#else
+		} while (res < 0);
+#endif
+		/*
+		 * it doesn't make sense to update the EEPROM if the
+		 * update was interrupted by the user due to errors.
+		 */
+		if (got_ctrlc == 0)
+			au_update_eeprom(i);
+	}
+	usb_stop();
+	/* restore the old state */
+	disable_ctrlc(old_ctrlc);
+	return 0;
+}
+#endif /* CONFIG_AUTO_UPDATE */

board/trab/cmd_trab.c

@@ -111,6 +111,10 @@ int do_vcc5v (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 int do_burn_in (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 int do_contact_temp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 int do_burn_in_status (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+int i2c_write_multiple (uchar chip, uint addr, int alen,
+			uchar *buffer, int len);
+int i2c_read_multiple (uchar chip, uint addr, int alen,
+			uchar *buffer, int len);
 
 /* helper functions */
 static void adc_init (void);
@@ -123,10 +127,6 @@ static int test_rotary_switch (void);
 static int test_sram (void);
 static int test_eeprom (void);
 static int test_contact_temp (void);
-static int i2c_write_multiple (uchar chip, uint addr, int alen,
-                               uchar *buffer, int len);
-static int i2c_read_multiple (uchar chip, uint addr, int alen,
-                              uchar *buffer, int len);
 static void led_set (unsigned int);
 static void led_blink (void);
 static void led_init (void);
@@ -579,8 +579,8 @@ static int test_contact_temp (void)
 }
 
 
-static int i2c_write_multiple (uchar chip, uint addr, int alen,
-                               uchar *buffer, int len)
+int i2c_write_multiple (uchar chip, uint addr, int alen,
+			uchar *buffer, int len)
 {
         int i;
 
@@ -608,8 +608,8 @@ static int i2c_write_multiple (uchar chip, uint addr, int alen,
 }
 
 
-static int i2c_read_multiple (uchar chip, uint addr, int alen,
-                               uchar *buffer, int len)
+int i2c_read_multiple ( uchar chip, uint addr, int alen,
+			uchar *buffer, int len)
 {
         int i;
 

board/trab/config.mk

@@ -8,16 +8,19 @@
 #
 
 #
-# TRAB has 1 bank of 16 MB DRAM
+# TRAB has 1 bank of 16 MB or 32 MB DRAM
 #
 # 0c00'0000 to 0e00'0000
 #
 # Linux-Kernel is expected to be at 0c00'8000, entry 0c00'8000
 #
-# we load ourself to 0cf0'0000
+# we load ourself to 0CF0'0000	/ 0DF0'0000
 #
-# download areas is 0c80'0000
+# download areas is 0C80'0000
 #
 
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
 
-TEXT_BASE = 0x0cf00000
+ifndef TEXT_BASE
+TEXT_BASE = 0x0DF00000
+endif

board/trab/memsetup.S

@@ -5,7 +5,7 @@
  *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
  *
  * Modified for the TRAB board by
- * (C) Copyright 2002
+ * (C) Copyright 2002-2003
  * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
  *
  * See file CREDITS for list of people who contributed to this
@@ -101,6 +101,17 @@
 #define B5_Tacp	0x0
 #define B5_PMC	0x0	/* normal */
 
+#ifndef CONFIG_RAM_16MB		/* 32 MB RAM */
+/* Bank6 */
+#define	B6_MT	0x3	/* SDRAM */
+#define	B6_Trcd	0x1	/* 3clk */
+#define	B6_SCAN	0x1	/* 9 bit */
+
+/* Bank7 */
+#define	B7_MT	0x3	/* SDRAM */
+#define	B7_Trcd	0x1	/* 3clk */
+#define	B7_SCAN	0x1	/* 9 bit */
+#else	/* CONFIG_RAM_16MB	=  16 MB RAM */
 /* Bank6 */
 #define	B6_MT	0x3	/* SDRAM */
 #define	B6_Trcd	0x1	/* 2clk */
@@ -110,6 +121,7 @@
 #define	B7_MT	0x3	/* SDRAM */
 #define	B7_Trcd	0x1	/* 2clk */
 #define	B7_SCAN	0x0	/* 8 bit */
+#endif	/* CONFIG_RAM_16MB */
 
 /* refresh parameter */
 #define REFEN	0x1	/* enable refresh */
@@ -161,6 +173,10 @@ SMRDATA:
 	.word	((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) /* GCS6 */
 	.word	((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) /* GCS7 */
 	.word	((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+#ifndef CONFIG_RAM_16MB		/* 32 MB RAM */
+	.word	0x10	/* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 32M/32M */
+#else	/* CONFIG_RAM_16MB	=  16 MB RAM */
 	.word	0x17	/* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 16M/16M */
+#endif	/* CONFIG_RAM_16MB */
 	.word	0x30	/* MRSR6, CL=3clk */
 	.word	0x30	/* MRSR7 */

board/trab/trab.c

@@ -169,6 +169,12 @@ int misc_init_r (void)
 	uchar *str;
 	int i;
 
+#ifdef CONFIG_AUTO_UPDATE
+	extern int do_auto_update(void);
+	/* this has priority over all else */
+	do_auto_update();
+#endif
+
 	for (i = 0; i < KEYBD_KEY_NUM; ++i) {
 		keybd_env[i] = '0' + ((kbd_data >> i) & 1);
 	}

common/cmd_immap.c

@@ -634,7 +634,7 @@ U_BOOT_CMD(
 
 U_BOOT_CMD(
 	iopset,	5,	0,	do_iopset,
-	"iopset - set I/O Port registers\n",
+	"iopset  - set I/O Port registers\n",
 	"PORT PIN CMD VALUE\nPORT: A-D, PIN: 0-31, CMD: [dat|dir|odr|sor], VALUE: 0|1"
 );
 

common/cmd_mem.c

@@ -555,7 +555,11 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	vu_long	temp;
 	vu_long	anti_pattern;
 	vu_long	num_words;
+#if defined(CFG_MEMTEST_SCRATCH)
+	vu_long *dummy = (vu_long*)CFG_MEMTEST_SCRATCH;
+#else
 	vu_long *dummy = NULL;
+#endif
 	int	j;
 	int iterations = 1;
 

common/cmd_spi.c

@@ -133,7 +133,7 @@ int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 U_BOOT_CMD(
 	sspi,	5,	1,	do_spi,
-	"sspi     - SPI utility commands\n",
+	"sspi    - SPI utility commands\n",
 	"<device> <bit_len> <dout> - Send <bit_len> bits from <dout> out the SPI\n"
 	"<device>  - Identifies the chip select of the device\n"
 	"<bit_len> - Number of bits to send (base 10)\n"

common/console.c

@@ -436,6 +436,8 @@ int console_init_r (void)
 		console_setfile (stdin, inputdev);
 	}
 
+	gd->flags |= GD_FLG_DEVINIT;	/* device initialization completed */
+
 #ifndef CFG_CONSOLE_INFO_QUIET
 	/* Print information */
 	printf ("In:    ");
@@ -480,6 +482,8 @@ int console_init_r (void)
 /* Called after the relocation - use desired console functions */
 int console_init_r (void)
 {
+	DECLARE_GLOBAL_DATA_PTR;
+
 	device_t *inputdev = NULL, *outputdev = NULL;
 	int i, items = ListNumItems (devlist);
 
@@ -514,6 +518,8 @@ int console_init_r (void)
 		console_setfile (stdin, inputdev);
 	}
 
+	gd->flags |= GD_FLG_DEVINIT;	/* device initialization completed */
+
 #ifndef CFG_CONSOLE_INFO_QUIET
 	/* Print information */
 	printf ("In:    ");

common/devices.c

@@ -158,9 +158,9 @@ int device_deregister(char *devname)
 
 int devices_init (void)
 {
+#ifndef CONFIG_ARM     /* already relocated for current ARM implementation */
 	DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef CONFIG_ARM     /* already relocated for current ARM implementation */
 	ulong relocation_offset = gd->reloc_off;
 	int i;
 
@@ -195,8 +195,6 @@ int devices_init (void)
 #endif
 	drv_system_init ();
 
-	gd-> flags |= GD_FLG_DEVINIT;	/* device initialization done */
-
 	return (0);
 }
 

common/usb.c

@@ -595,7 +595,7 @@ struct usb_device * usb_alloc_new_device(void)
 	int i;
 	USB_PRINTF("New Device %d\n",dev_index);
 	if(dev_index==USB_MAX_DEVICE) {
-		printf("ERROR, to many USB Devices max=%d\n",USB_MAX_DEVICE);
+		printf("ERROR, too many USB Devices, max=%d\n",USB_MAX_DEVICE);
 		return NULL;
 	}
 	usb_dev[dev_index].devnum=dev_index+1; /* default Address is 0, real addresses start with 1 */

common/usb_storage.c

@@ -188,7 +188,7 @@ int usb_stor_scan(int mode)
 	memset(usb_stor_buf, 0, sizeof(usb_stor_buf));
 
 	if(mode==1) {
-		printf("scanning bus for storage devices...\n");
+		printf("       scanning bus for storage devices...\n");
 	}
 	usb_disable_asynch(1); /* asynch transfer not allowed */
 

config.mk

@@ -102,7 +102,7 @@ RELFLAGS= $(PLATFORM_RELFLAGS)
 DBGFLAGS= -g #-DDEBUG
 OPTFLAGS= -Os #-fomit-frame-pointer
 ifndef LDSCRIPT
-#LDSCRIPT := board/$(BOARDDIR)/u-boot.lds.debug
+#LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug
 LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
 endif
 OBJCFLAGS += --gap-fill=0xff

cpu/arm720t/start.S

@@ -71,9 +71,6 @@ _fiq:			.word fiq
  *************************************************************************
  */
 
-/*
- * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
- */
 _TEXT_BASE:
 	.word	TEXT_BASE
 

cpu/arm920t/serial.c

@@ -30,7 +30,7 @@
 
 #elif CONFIG_SERIAL2
 # if defined(CONFIG_TRAB)
-#  #error "TRAB supports only CONFIG_SERIAL1"
+#  error "TRAB supports only CONFIG_SERIAL1"
 # endif
 #define UART_NR	S3C24X0_UART1
 

cpu/arm920t/start.S

@@ -72,9 +72,6 @@ _fiq:			.word fiq
  *************************************************************************
  */
 
-/*
- * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
- */
 _TEXT_BASE:
 	.word	TEXT_BASE
 

cpu/arm920t/usb_ohci.c

@@ -1199,7 +1199,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 	/* ohci_dump_status(&gohci); */
 	
 	/* allow more time for a BULK device to react - some are slow */
-#define BULK_TO	 2000	/* timeout in milliseconds */
+#define BULK_TO	 5000	/* timeout in milliseconds */
 	if (usb_pipetype (pipe) == PIPE_BULK)
 		timeout = BULK_TO;
 	else

cpu/arm925t/start.S

@@ -81,9 +81,6 @@ _fiq:			.word fiq
  *************************************************************************
  */
 
-/*
- * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
- */
 _TEXT_BASE:
 	.word	TEXT_BASE
 

cpu/arm926ejs/start.S

@@ -90,9 +90,6 @@ _fiq:
  *************************************************************************
  */
 
-/*
- * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
- */
 _TEXT_BASE:
 	.word	TEXT_BASE
 

cpu/at91rm9200/start.S

@@ -71,9 +71,6 @@ _fiq:			.word fiq
  *************************************************************************
  */
 
-/*
- * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
- */
 _TEXT_BASE:
 	.word	TEXT_BASE
 

cpu/mpc5xxx/Makefile

@@ -27,7 +27,7 @@ LIB	= lib$(CPU).a
 
 START	= start.o
 ASOBJS	= io.o firmware_sc_task_bestcomm.impl.o firmware_sc_task.impl.o
-OBJS	= traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o \
+OBJS	= i2c.o traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o \
 	  loadtask.o fec.o pci_mpc5200.o
 
 all:	.depend $(START) $(ASOBJS) $(LIB)

cpu/mpc5xxx/cpu_init.c

@@ -152,6 +152,7 @@ void cpu_init_f (void)
 	/* enable timebase */
 	*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 13);
 
+#if defined(CFG_IPBSPEED_133)
 	/* Motorola reports IPB should better run at 133 MHz. */
 	*(vu_long *)MPC5XXX_ADDECR |= 1;
 	/* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */
@@ -159,6 +160,10 @@ void cpu_init_f (void)
 	addecr &= ~0x103;
 	addecr |= 0x02;
 	*(vu_long *)MPC5XXX_CDM_CFG = addecr;
+#endif
+	/* Configure the XLB Arbiter */
+	*(vu_long *)MPC5XXX_XLBARB_MPRIEN = 0xff;
+	*(vu_long *)MPC5XXX_XLBARB_MPRIVAL = 0x11111111;
 #endif
 }
 
@@ -175,6 +180,8 @@ int cpu_init_r (void)
 #endif
 	*(vu_long *)MPC5XXX_ICTL_CRIT |= 0x0001ffff;
 	*(vu_long *)MPC5XXX_ICTL_EXT &= ~0x00000f00;
+	/* route critical ints to normal ints */
+	*(vu_long *)MPC5XXX_ICTL_EXT |= 0x00000001;
 
 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_MPC5XXX_FEC)
 	/* load FEC microcode */

cpu/mpc5xxx/fec.c

@@ -387,7 +387,9 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
 			/*
 			 * Force 10Base-T, FDX operation
 			 */
+#if (DEBUG & 0x2)
 			printf("Forcing 10 Mbps ethernet link... ");
+#endif
 			miiphy_read(phyAddr, 0x1, &phyStatus);
 			/*
 			miiphy_write(fec, phyAddr, 0x0, 0x0100);
@@ -822,7 +824,13 @@ int mpc5xxx_fec_initialize(bd_t * bis)
 	fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
 	fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
 #ifdef CONFIG_ICECUBE
+#ifndef CONFIG_FEC_10MBIT
 	fec->xcv_type = MII100;
+#else
+	fec->xcv_type = MII10;
+#endif
+#else
+#error fec->xcv_type not initialized.
 #endif
 
 	dev->priv = (void *)fec;

cpu/mpc5xxx/i2c.c

@@ -0,0 +1,338 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_HARD_I2C
+
+#include <mpc5xxx.h>
+#include <i2c.h>
+
+#ifdef CFG_I2C_MODULE
+#define I2C_BASE	MPC5XXX_I2C2
+#else
+#define I2C_BASE	MPC5XXX_I2C1
+#endif
+
+#define I2C_TIMEOUT	100
+#define I2C_RETRIES	3
+
+static int  mpc_reg_in    (volatile u32 *reg);
+static void mpc_reg_out   (volatile u32 *reg, int val, int mask);
+static int  wait_for_bb   (void);
+static int  wait_for_pin  (int *status);
+static int  do_address    (uchar chip, char rdwr_flag);
+static int  send_bytes    (uchar chip, char *buf, int len);
+static int  receive_bytes (uchar chip, char *buf, int len);
+
+static int mpc_reg_in(volatile u32 *reg)
+{
+	return *reg >> 24;
+	__asm__ __volatile__ ("eieio");
+}
+
+static void mpc_reg_out(volatile u32 *reg, int val, int mask)
+{
+	int tmp;
+
+	if (!mask) {
+		*reg = val << 24;
+	} else {
+		tmp = mpc_reg_in(reg);
+		*reg = ((tmp & ~mask) | (val & mask)) << 24;
+	}
+	__asm__ __volatile__ ("eieio");
+
+	return;
+}
+
+static int wait_for_bb(void)
+{
+	struct mpc5xxx_i2c *regs    = (struct mpc5xxx_i2c *)I2C_BASE;
+	int                 timeout = I2C_TIMEOUT;
+	int                 status;
+
+	status = mpc_reg_in(&regs->msr);
+
+	while (timeout-- && (status & I2C_BB)) {
+#if 1
+		volatile int temp;
+		mpc_reg_out(&regs->mcr, I2C_STA, I2C_STA);
+		temp = mpc_reg_in(&regs->mdr);
+		mpc_reg_out(&regs->mcr, 0, I2C_STA);
+		mpc_reg_out(&regs->mcr, 0, 0);
+		mpc_reg_out(&regs->mcr, I2C_EN, 0);
+#endif
+		udelay(1000);
+		status = mpc_reg_in(&regs->msr);
+	}
+
+	return (status & I2C_BB);
+}
+
+static int wait_for_pin(int *status)
+{
+	struct mpc5xxx_i2c *regs    = (struct mpc5xxx_i2c *)I2C_BASE;
+	int                 timeout = I2C_TIMEOUT;
+
+	*status = mpc_reg_in(&regs->msr);
+
+	while (timeout-- && !(*status & I2C_IF)) {
+		udelay(1000);
+		*status = mpc_reg_in(&regs->msr);
+	}
+
+	if (!(*status & I2C_IF)) {
+		return -1;
+	}
+
+	mpc_reg_out(&regs->msr, 0, I2C_IF);
+
+	return 0;
+}
+
+static int do_address(uchar chip, char rdwr_flag)
+{
+	struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
+	int                 status;
+
+	chip <<= 1;
+
+	if (rdwr_flag) {
+		chip |= 1;
+	}
+
+	mpc_reg_out(&regs->mcr, I2C_TX, I2C_TX);
+	mpc_reg_out(&regs->mdr, chip, 0);
+
+        if (wait_for_pin(&status)) {
+                return -2;
+        }
+
+        if (status & I2C_RXAK) {
+                return -3;
+        }
+
+	return 0;
+}
+
+static int send_bytes(uchar chip, char *buf, int len)
+{
+	struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
+	int                 wrcount;
+	int                 status;
+
+	for (wrcount = 0; wrcount < len; ++wrcount) {
+
+		mpc_reg_out(&regs->mdr, buf[wrcount], 0);
+
+		if (wait_for_pin(&status)) {
+			break;
+		}
+
+		if (status & I2C_RXAK) {
+			break;
+		}
+
+	}
+
+	return !(wrcount == len);
+}
+
+static int receive_bytes(uchar chip, char *buf, int len)
+{
+	struct mpc5xxx_i2c *regs    = (struct mpc5xxx_i2c *)I2C_BASE;
+	int                 dummy   = 1;
+	int                 rdcount = 0;
+	int                 status;
+	int                 i;
+
+	mpc_reg_out(&regs->mcr, 0, I2C_TX);
+
+	for (i = 0; i < len; ++i) {
+		buf[rdcount] = mpc_reg_in(&regs->mdr);
+
+		if (dummy) {
+			dummy = 0;
+		} else {
+			rdcount++;
+		}
+
+
+		if (wait_for_pin(&status)) {
+			return -4;
+		}
+	}
+
+	mpc_reg_out(&regs->mcr, I2C_TXAK, I2C_TXAK);
+	buf[rdcount++] = mpc_reg_in(&regs->mdr);
+
+	if (wait_for_pin(&status)) {
+		return -5;
+	}
+
+	mpc_reg_out(&regs->mcr, 0, I2C_TXAK);
+
+	return 0;
+}
+
+/**************** I2C API ****************/
+
+void i2c_init(int speed, int saddr)
+{
+	struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
+
+	mpc_reg_out(&regs->mcr, 0, 0);
+	mpc_reg_out(&regs->madr, saddr << 1, 0);
+
+	/* Set clock
+	 */
+	mpc_reg_out(&regs->mfdr, speed, 0);
+
+	/* Enable module
+	 */
+	mpc_reg_out(&regs->mcr, I2C_EN, I2C_INIT_MASK);
+	mpc_reg_out(&regs->msr, 0, I2C_IF);
+
+	return;
+}
+
+int i2c_probe(uchar chip)
+{
+	struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
+	int                 i;
+
+	for (i = 0; i < I2C_RETRIES; i++) {
+		mpc_reg_out(&regs->mcr, I2C_STA, I2C_STA);
+
+		if (! do_address(chip, 0)) {
+			mpc_reg_out(&regs->mcr, 0, I2C_STA);
+			break;
+		}
+
+		mpc_reg_out(&regs->mcr, 0, I2C_STA);
+		udelay(500);
+	}
+
+	return (i == I2C_RETRIES);
+}
+
+int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
+{
+	uchar                xaddr[4];
+	struct mpc5xxx_i2c * regs        = (struct mpc5xxx_i2c *)I2C_BASE;
+	int                  ret         = -1;
+
+	xaddr[0] = (addr >> 24) & 0xFF;
+	xaddr[1] = (addr >> 16) & 0xFF;
+	xaddr[2] = (addr >>  8) & 0xFF;
+	xaddr[3] =  addr	& 0xFF;
+
+	if (wait_for_bb()) {
+		printf("i2c_read: bus is busy\n");
+		goto Done;
+	}
+
+	mpc_reg_out(&regs->mcr, I2C_STA, I2C_STA);
+	if (do_address(chip, 0)) {
+		printf("i2c_read: failed to address chip\n");
+		goto Done;
+	}
+
+	if (send_bytes(chip, &xaddr[4-alen], alen)) {
+		printf("i2c_read: send_bytes failed\n");
+		goto Done;
+	}
+
+	mpc_reg_out(&regs->mcr, I2C_RSTA, I2C_RSTA);
+	if (do_address(chip, 1)) {
+		printf("i2c_read: failed to address chip\n");
+		goto Done;
+	}
+
+	if (receive_bytes(chip, buf, len)) {
+		printf("i2c_read: receive_bytes failed\n");
+		goto Done;
+	}
+
+	ret = 0;
+Done:
+	mpc_reg_out(&regs->mcr, 0, I2C_STA);
+	return ret;
+}
+
+int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
+{
+	uchar               xaddr[4];
+	struct mpc5xxx_i2c *regs        = (struct mpc5xxx_i2c *)I2C_BASE;
+	int                 ret         = -1;
+
+	xaddr[0] = (addr >> 24) & 0xFF;
+	xaddr[1] = (addr >> 16) & 0xFF;
+	xaddr[2] = (addr >>  8) & 0xFF;
+	xaddr[3] =  addr	& 0xFF;
+
+        if (wait_for_bb()) {
+		printf("i2c_write: bus is busy\n");
+		goto Done;
+	}
+
+        mpc_reg_out(&regs->mcr, I2C_STA, I2C_STA);
+        if (do_address(chip, 0)) {
+		printf("i2c_write: failed to address chip\n");
+		goto Done;
+	}
+
+	if (send_bytes(chip, &xaddr[4-alen], alen)) {
+		printf("i2c_write: send_bytes failed\n");
+		goto Done;
+	}
+
+	if (send_bytes(chip, buf, len)) {
+		printf("i2c_write: send_bytes failed\n");
+		goto Done;
+	}
+
+	ret = 0;
+Done:
+	mpc_reg_out(&regs->mcr, 0, I2C_STA);
+	return ret;
+}
+
+uchar i2c_reg_read(uchar chip, uchar reg)
+{
+	char buf;
+
+	i2c_read(chip, reg, 1, &buf, 1);
+
+	return buf;
+}
+
+void i2c_reg_write(uchar chip, uchar reg, uchar val)
+{
+	i2c_write(chip, reg, 1, &val, 1);
+
+	return;
+}
+
+#endif	/* CONFIG_HARD_I2C */

cpu/mpc5xxx/pci_mpc5200.c

@@ -48,9 +48,11 @@ static int mpc5200_read_config_dword(struct pci_controller *hose,
 {
 	*(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
 	eieio();
+	udelay(10);
 	*value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
 	eieio();
 	*(volatile u32 *)MPC5XXX_PCI_CAR = 0;
+	udelay(10);
 	return 0;
 }
 
@@ -59,9 +61,11 @@ static int mpc5200_write_config_dword(struct pci_controller *hose,
 {
 	*(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
 	eieio();
+	udelay(10);
 	out_le32((volatile u32 *)CONFIG_PCI_IO_PHYS, value);
 	eieio();
 	*(volatile u32 *)MPC5XXX_PCI_CAR = 0;
+	udelay(10);
 	return 0;
 }
 
@@ -125,8 +129,10 @@ void pci_mpc5xxx_init (struct pci_controller *hose)
 	*(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~((7 << 8) | (3 << 5));
 	*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (3 << 8) | (3 << 5);
 
+#if 0
 	/* Enable piplining */
 	*(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~(1 << 31);
+#endif
 	
 	/* Disable interrupts from PCI controller */
 	*(vu_long *)MPC5XXX_PCI_GSCR &= ~(7 << 12);

cpu/mpc5xxx/start.S

@@ -382,6 +382,14 @@ init_5xxx_core:
 	mtspr	DBAT2L, r0
 	mtspr	DBAT3U, r0
 	mtspr	DBAT3L, r0
+	mtspr	DBAT4U, r0
+	mtspr	DBAT4L, r0
+	mtspr	DBAT5U, r0
+	mtspr	DBAT5L, r0
+	mtspr	DBAT6U, r0
+	mtspr	DBAT6L, r0
+	mtspr	DBAT7U, r0
+	mtspr	DBAT7L, r0
 	mtspr	IBAT0U, r0
 	mtspr	IBAT0L, r0
 	mtspr	IBAT1U, r0
@@ -390,6 +398,14 @@ init_5xxx_core:
 	mtspr	IBAT2L, r0
 	mtspr	IBAT3U, r0
 	mtspr	IBAT3L, r0
+	mtspr	IBAT4U, r0
+	mtspr	IBAT4L, r0
+	mtspr	IBAT5U, r0
+	mtspr	IBAT5L, r0
+	mtspr	IBAT6U, r0
+	mtspr	IBAT6L, r0
+	mtspr	IBAT7U, r0
+	mtspr	IBAT7L, r0
 	SYNC
 
 	/* invalidate all tlb's						*/

cpu/mpc824x/interrupts.c

@@ -27,6 +27,7 @@
 #include <asm/processor.h>
 #include <asm/pci_io.h>
 #include <commproc.h>
+#include <watchdog.h>
 #include "drivers/epic.h"
 
 /****************************************************************************/
@@ -149,15 +150,9 @@ void timer_interrupt (struct pt_regs *regs)
 
 	timestamp++;
 
-#if defined(CONFIG_WATCHDOG)
+#if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG)
 	if ((timestamp % (CFG_HZ / 2)) == 0) {
-#if defined(CONFIG_OXC)
-		{
-			extern void oxc_wdt_reset (void);
-
-			oxc_wdt_reset ();
-		}
-#endif
+		WATCHDOG_RESET ();
 	}
 #endif							/* CONFIG_WATCHDOG */
 #if defined(CONFIG_SHOW_ACTIVITY) && defined(CONFIG_OXC)

cpu/mpc8260/ether_fcc.c

@@ -650,6 +650,15 @@ eth_loopback_test (void)
 	/* 28.9 - (1-2): ioports have been set up already */
 
 #if defined(CONFIG_HYMOD)
+	/*
+	 * Attention: this is board-specific
+	 * 0, FCC1 
+	 * 1, FCC2 
+	 * 2, FCC3 
+         */
+#       define FCC_START_LOOP 0
+#       define FCC_END_LOOP   2
+
 	/*
 	 * Attention: this is board-specific
 	 * - FCC1 Rx-CLK is CLK10
@@ -665,13 +674,30 @@ eth_loopback_test (void)
 	immr->im_cpmux.cmx_fcr = CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11|\
 	    CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14|\
 	    CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16;
+#elif defined(CONFIG_SBC8260) || defined(CONFIG_SACSng)
+	/*
+	 * Attention: this is board-specific
+	 * 1, FCC2 
+         */
+#       define FCC_START_LOOP 1
+#       define FCC_END_LOOP   1
+
+	/*
+	 * Attention: this is board-specific
+	 * - FCC2 Rx-CLK is CLK13
+	 * - FCC2 Tx-CLK is CLK14
+	 */
+
+	/* 28.9 - (3): connect FCC's tx and rx clocks */
+	immr->im_cpmux.cmx_uar = 0;
+	immr->im_cpmux.cmx_fcr = CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14;
 #else
 #error "eth_loopback_test not supported on your board"
 #endif
 
 	puts ("Initialise FCC channels:");
 
-	for (c = 0; c < 3; c++) {
+	for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) {
 		elbt_chan *ecp = &elbt_chans[c];
 		volatile fcc_t *fcp = &immr->im_fcc[c];
 		volatile fcc_enet_t *fpp;
@@ -853,7 +879,7 @@ eth_loopback_test (void)
 	do {
 		nclosed = 0;
 
-		for (c = 0; c < 3; c++) {
+		for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) {
 			volatile fcc_t *fcp = &immr->im_fcc[c];
 			elbt_chan *ecp = &elbt_chans[c];
 			int i;
@@ -1082,7 +1108,7 @@ eth_loopback_test (void)
 			}
 		}
 
-	} while (nclosed < 3);
+	} while (nclosed < (FCC_END_LOOP - FCC_START_LOOP + 1));
 
 	runtime = get_timer (runtime);
 	if (runtime <= ELBT_CLSWAIT) {
@@ -1099,7 +1125,7 @@ eth_loopback_test (void)
 	 * now print stats
 	 */
 
-	for (c = 0; c < 3; c++) {
+	for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) {
 		elbt_chan *ecp = &elbt_chans[c];
 		uint rxpps, txpps, nerr;
 
@@ -1131,17 +1157,17 @@ eth_loopback_test (void)
 	}
 
 	puts ("Receive Error Counts:\n");
-	for (c = 0; c < 3; c++)
+	for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++)
 		bases[c] = (uchar *)&elbt_chans[c].rxeacc;
 	print_desc (rxeacc_descs, rxeacc_ndesc, bases, 3);
 
 	puts ("\nTransmit Error Counts:\n");
-	for (c = 0; c < 3; c++)
+	for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++)
 		bases[c] = (uchar *)&elbt_chans[c].txeacc;
 	print_desc (txeacc_descs, txeacc_ndesc, bases, 3);
 
 	puts ("\nRMON(-like) Counters:\n");
-	for (c = 0; c < 3; c++)
+	for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++)
 		bases[c] = (uchar *)&immr->im_dprambase[elbt_chans[c].proff];
 	print_desc (epram_descs, epram_ndesc, bases, 3);
 }

cpu/pxa/cpu.c

@@ -83,7 +83,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	extern void reset_cpu (ulong addr);
 
-	printf ("reseting ...\n");
+	printf ("resetting ...\n");
 
 	udelay (50000);				/* wait 50 ms */
 	disable_interrupts ();

cpu/pxa/serial.c

@@ -29,6 +29,7 @@
  */
 
 #include <common.h>
+#include <watchdog.h>
 #include <asm/arch/pxa-regs.h>
 
 void serial_setbrg (void)
@@ -38,7 +39,7 @@ void serial_setbrg (void)
 	unsigned int quot = 0;
 
 	if (gd->baudrate == 1200)
-		quot = 192;
+		quot = 768;
 	else if (gd->baudrate == 9600)
 		quot = 96;
 	else if (gd->baudrate == 19200)
@@ -53,7 +54,6 @@ void serial_setbrg (void)
 		hang ();
 
 #ifdef CONFIG_FFUART
-
 	CKEN |= CKEN6_FFUART;
 
 	FFIER = 0;					/* Disable for now */
@@ -82,9 +82,21 @@ void serial_setbrg (void)
 	BTIER = IER_UUE;			/* Enable BFUART */
 
 #elif defined(CONFIG_STUART)
-#error "Bad: not implemented yet!"
+	CKEN |= CKEN5_STUART;
+
+	STIER = 0;
+	STFCR = 0;
+
+	/* set baud rate */
+	STLCR = LCR_DLAB;
+	STDLL = quot & 0xff;
+	STDLH = quot >> 8;
+	STLCR = LCR_WLS0 | LCR_WLS1;
+
+	STIER = IER_UUE;			/* Enable STUART */
+
 #else
-#error "Bad: you didn't configured serial ..."
+#error "Bad: you didn't configure serial ..."
 #endif
 }
 
@@ -109,13 +121,17 @@ void serial_putc (const char c)
 {
 #ifdef CONFIG_FFUART
 	/* wait for room in the tx FIFO on FFUART */
-	while ((FFLSR & LSR_TEMT) == 0);
-
+	while ((FFLSR & LSR_TEMT) == 0)
+		WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
 	FFTHR = c;
 #elif defined(CONFIG_BTUART)
-	while ((BTLSR & LSR_TEMT ) == 0 );
+	while ((BTLSR & LSR_TEMT ) == 0 )
+		WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
 	BTTHR = c;
 #elif defined(CONFIG_STUART)
+	while ((STLSR & LSR_TEMT ) == 0 )
+		WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
+	STTHR = c;
 #endif
 
 	/* If \n, also do \r */
@@ -135,6 +151,7 @@ int serial_tstc (void)
 #elif defined(CONFIG_BTUART)
 	return BTLSR & LSR_DR;
 #elif defined(CONFIG_STUART)
+	return STLSR & LSR_DR;
 #endif
 }
 
@@ -146,14 +163,17 @@ int serial_tstc (void)
 int serial_getc (void)
 {
 #ifdef CONFIG_FFUART
-	while (!(FFLSR & LSR_DR));
-
+	while (!(FFLSR & LSR_DR))
+		WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
 	return (char) FFRBR & 0xff;
 #elif defined(CONFIG_BTUART)
-	while (!(BTLSR & LSR_DR));
-
+	while (!(BTLSR & LSR_DR))
+		WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
 	return (char) BTRBR & 0xff;
 #elif defined(CONFIG_STUART)
+	while (!(STLSR & LSR_DR))
+		WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
+	return (char) STRBR & 0xff;
 #endif
 }
 

cpu/pxa/start.S

@@ -61,9 +61,6 @@ _fiq:			.word fiq
  * - jump to second stage
  */
 
-/*
- * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
- */
 _TEXT_BASE:
 	.word	TEXT_BASE
 

cpu/sa1100/start.S

@@ -73,9 +73,6 @@ _fiq:			.word fiq
  *************************************************************************
  */
 
-/*
- * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
- */
 _TEXT_BASE:
 	.word	TEXT_BASE
 

drivers/s3c24x0_i2c.c

@@ -56,7 +56,7 @@
 #define I2C_START_STOP	0x20		/* START / STOP */
 #define I2C_TXRX_ENA	0x10		/* I2C Tx/Rx enable */
 
-#define I2C_TIMEOUT 1			/* 1 seconde */
+#define I2C_TIMEOUT 1			/* 1 second */
 
 
 static int GetI2CSDA(void)

drivers/sk98lin/Makefile

@@ -24,6 +24,7 @@
 #
 # Makefile for the SysKonnect SK-98xx device driver.
 #
+include $(TOPDIR)/config.mk
 
 LIB := libsk98lin.a
 

include/asm-ppc/processor.h

@@ -95,14 +95,14 @@
 #define	SPRN_DBAT2U	0x21C	/* Data BAT 2 Upper Register */
 #define	SPRN_DBAT3L	0x21F	/* Data BAT 3 Lower Register */
 #define	SPRN_DBAT3U	0x21E	/* Data BAT 3 Upper Register */
-#define	SPRN_DBAT4L	0x238   /* Data BAT 4 Lower Register */
-#define	SPRN_DBAT4U	0x239   /* Data BAT 4 Upper Register */
-#define	SPRN_DBAT5L	0x23A   /* Data BAT 5 Lower Register */
-#define	SPRN_DBAT5U	0x23B   /* Data BAT 5 Upper Register */
-#define	SPRN_DBAT6L	0x23C   /* Data BAT 6 Lower Register */
-#define	SPRN_DBAT6U	0x23D   /* Data BAT 6 Upper Register */
-#define	SPRN_DBAT7L	0x23E   /* Data BAT 7 Lower Register */
-#define	SPRN_DBAT7U	0x23F   /* Data BAT 7 Lower Register */
+#define	SPRN_DBAT4L	0x239   /* Data BAT 4 Lower Register */
+#define	SPRN_DBAT4U	0x238   /* Data BAT 4 Upper Register */
+#define	SPRN_DBAT5L	0x23B   /* Data BAT 5 Lower Register */
+#define	SPRN_DBAT5U	0x23A   /* Data BAT 5 Upper Register */
+#define	SPRN_DBAT6L	0x23D   /* Data BAT 6 Lower Register */
+#define	SPRN_DBAT6U	0x23C   /* Data BAT 6 Upper Register */
+#define	SPRN_DBAT7L	0x23F   /* Data BAT 7 Lower Register */
+#define	SPRN_DBAT7U	0x23E   /* Data BAT 7 Lower Register */
 #define	SPRN_DBCR	0x3F2	/* Debug Control Regsiter */
 #define	  DBCR_EDM	0x80000000
 #define	  DBCR_IDM	0x40000000
@@ -203,14 +203,14 @@
 #define	SPRN_IBAT2U	0x214	/* Instruction BAT 2 Upper Register */
 #define	SPRN_IBAT3L	0x217	/* Instruction BAT 3 Lower Register */
 #define	SPRN_IBAT3U	0x216	/* Instruction BAT 3 Upper Register */
-#define	SPRN_IBAT4L	0x230   /* Instruction BAT 4 Lower Register */
-#define	SPRN_IBAT4U	0x231   /* Instruction BAT 4 Upper Register */
-#define	SPRN_IBAT5L	0x232   /* Instruction BAT 5 Lower Register */
-#define	SPRN_IBAT5U	0x233   /* Instruction BAT 5 Upper Register */
-#define	SPRN_IBAT6L	0x234   /* Instruction BAT 6 Lower Register */
-#define	SPRN_IBAT6U	0x235   /* Instruction BAT 6 Upper Register */
-#define	SPRN_IBAT7L	0x236   /* Instruction BAT 7 Lower Register */
-#define	SPRN_IBAT7U	0x237   /* Instruction BAT 7 Lower Register */
+#define	SPRN_IBAT4L	0x231   /* Instruction BAT 4 Lower Register */
+#define	SPRN_IBAT4U	0x230   /* Instruction BAT 4 Upper Register */
+#define	SPRN_IBAT5L	0x233   /* Instruction BAT 5 Lower Register */
+#define	SPRN_IBAT5U	0x232   /* Instruction BAT 5 Upper Register */
+#define	SPRN_IBAT6L	0x235   /* Instruction BAT 6 Lower Register */
+#define	SPRN_IBAT6U	0x234   /* Instruction BAT 6 Upper Register */
+#define	SPRN_IBAT7L	0x237   /* Instruction BAT 7 Lower Register */
+#define	SPRN_IBAT7U	0x236   /* Instruction BAT 7 Upper Register */
 #define	SPRN_ICCR	0x3FB	/* Instruction Cache Cacheability Register */
 #define	  ICCR_NOCACHE		0	/* Noncacheable */
 #define	  ICCR_CACHE		1	/* Cacheable */

include/configs/IceCube.h

@@ -71,6 +71,7 @@
 #define CONFIG_NET_MULTI	1
 #define CONFIG_EEPRO100		1
 #define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
+#define CONFIG_NS8382X		1
 
 #define ADD_PCI_CMD 		CFG_CMD_PCI
 
@@ -83,7 +84,8 @@
 /*
  * Supported commands
  */
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | ADD_PCI_CMD)
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | ADD_PCI_CMD | \
+				 CFG_CMD_I2C | CFG_CMD_EEPROM)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
@@ -95,9 +97,32 @@
 #define CONFIG_BOOTCOMMAND	"bootm 100000"	/* autoboot command */
 #define CONFIG_BOOTARGS		"root=/dev/ram rw"
 
+#if defined(CONFIG_MPC5200)
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CFG_IPBSPEED_133   		/* define for 133MHz speed */
+#endif
 /*
  * I2C configuration
  */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CFG_I2C_MODULE		1	/* If defined then I2C module #2 is used
+					 * otherwise I2C module #1 is used */
+#ifdef CONFIG_MPC5200
+#define CFG_I2C_SPEED		0x3D	/* 86KHz given 133MHz IPBI */
+#else
+#define CFG_I2C_SPEED		0x35	/* 86KHz given 33MHz IPBI */
+#endif
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN		1
+#define CFG_EEPROM_PAGE_WRITE_BITS	3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	35
 
 /*
  * Flash configuration
@@ -161,6 +186,7 @@
  * Ethernet configuration
  */
 #define CONFIG_MPC5XXX_FEC	1
+#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
 
 /*
  * GPIO configuration

include/configs/MPC8266ADS.h

@@ -508,7 +508,8 @@
 #define CFG_MPTPR		0x00001900
 #define CFG_PSRT		0x00000021
 
-#define CFG_RESET_ADDRESS	0x04400000
+/* This address must not exist */
+#define CFG_RESET_ADDRESS	0xFCFFFF00
 
 /* PCI Memory map (if different from default map */
 #define CFG_PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE		/* Local base */

include/configs/PPChameleonEVB.h

@@ -55,47 +55,17 @@
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
-#if 0
-#define CONFIG_PREBOOT                                                          \
-        "crc32 f0207004 ffc 0;"                                                 \
-        "if cmp 0 f0207000 1;"                                                  \
-        "then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;"             \
-        "else;echo Old CRC is bad;fi"
-#endif
-
 #undef	CONFIG_BOOTARGS
-#define CONFIG_RAMBOOTCOMMAND							\
-	"setenv bootargs root=/dev/ram rw "	\
-	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname):$(netdev):off;"	\
-	"bootm ffc00000 ffca0000"
-#define CONFIG_NFSBOOTCOMMAND							\
-	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "	\
-	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname):$(netdev):off;"	\
-	"bootm ffc00000"
 
-#define CONFIG_PELK_NOR_KERNEL_NOR_RAMDISK_BOOTCOMMAND				\
-	"setenv ipaddr 192.168.10.203;"						\
-    "setenv serverip 192.168.10.6;"						\
-	"setenv netmask 255.255.255.0;"						\
-	"setenv bootargs root=/dev/ram rw console=ttyS0,9600;"			\
-	"setenv autostart yes;"							\
-	"bootm ffc00000 ffd00000"
-/*
-	"setenv ethaddr 00:50:c2:1e:af:fe;"						\
-	"setenv eth1addr 00:50:c2:1e:af:fd;"						\
-*/
-
-#define CONFIG_BOOTCOMMAND CONFIG_PELK_NOR_KERNEL_NOR_RAMDISK_BOOTCOMMAND
+/* Ethernet stuff */
+#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
+#define CONFIG_ETHADDR	00:50:c2:1e:af:fe
+#define CONFIG_ETH1ADDR	00:50:c2:1e:af:fd
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 
-/* EThernet stuff */
-#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
-#define CONFIG_ETHADDR	00:50:c2:1e:af:fe
-#define CONFIG_ETH1ADDR	00:50:c2:1e:af:fd
-
 #undef CONFIG_EXT_PHY
 
 #define CONFIG_MII		1	/* MII PHY management		*/
@@ -548,18 +518,16 @@
 #if 1 /* test-only */
 #define CONFIG_NO_SERIAL_EEPROM
 /*#undef CONFIG_NO_SERIAL_EEPROM*/
-/*----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------*/
+/*--------------------------------------------------------------------*/
 #ifdef CONFIG_NO_SERIAL_EEPROM
 
 
 /*
-!-------------------------------------------------------------------------------
+!-----------------------------------------------------------------------
 ! Defines for entry options.
 ! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
 !       are plugged in the board will be utilized as non-ECC DIMMs.
-!-------------------------------------------------------------------------------
+!-----------------------------------------------------------------------
 */
 #undef        AUTO_MEMORY_CONFIG
 #define        DIMM_READ_ADDR 0xAB
@@ -678,10 +646,10 @@
 #define PLL_PCIDIV_4               0x00000003
 
 /*
-!-------------------------------------------------------------------------------
+!-----------------------------------------------------------------------
 ! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
 ! assuming a 33.3MHz input clock to the 405EP.
-!-------------------------------------------------------------------------------
+!-----------------------------------------------------------------------
 */
 #define PLLMR0_133_66_66_33  (PLL_CPUDIV_1 | PLL_PLBDIV_1 |  \
                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \

include/configs/VCMA9.h

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2002
+ * (C) Copyright 2002, 2003
  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  * Marius Groeger <mgroeger@sysgo.de>
  * Gary Jennejohn <gj@denx.de>
@@ -160,9 +160,10 @@
 #define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
 #define CFG_MEMTEST_START	0x30000000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x33F80000	/* 63.5 MB in DRAM	*/
+#define CFG_MEMTEST_END		0x30F80000	/* 15.5 MB in DRAM	*/
+
 #define CFG_ALT_MEMTEST
-#define	CFG_LOAD_ADDR		0x33000000	/* default load address	*/
+#define	CFG_LOAD_ADDR		0x30800000	/* default load address	*/
 
 
 #undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
@@ -197,8 +198,6 @@
  */
 #define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
 #define PHYS_SDRAM_1		0x30000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
-
 #define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
 
 #define CFG_FLASH_BASE		PHYS_FLASH_1

include/configs/sacsng.h

@@ -35,10 +35,11 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-/* Enable debug prints */
 #undef DEBUG		      /* General debug */
 #undef DEBUG_BOOTP_EXT	      /* Debug received vendor fields */
 
+#undef CONFIG_LOGBUFFER       /* External logbuffer support */
+
 /*****************************************************************************
  *
  * These settings must match the way _your_ board is set up
@@ -172,6 +173,7 @@
 
 #ifdef	CONFIG_ETHER_ON_FCC
 #define CONFIG_ETHER_INDEX	2	/* which SCC/FCC channel for ethernet */
+#undef  CONFIG_ETHER_LOOPBACK_TEST      /* Ethernet external loopback test */
 #define CONFIG_MII			/* MII PHY management		*/
 #define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
 /*
@@ -318,10 +320,12 @@
  * will be part of the default enviroment compiled into the boot image.
  */
 #define CONFIG_EXTRA_ENV_SETTINGS \
-"serverip=192.168.123.201\0" \
+"quiet=0\0" \
+"serverip=192.168.123.205\0" \
 "ipaddr=192.168.123.203\0" \
 "checkhostname=VR8500\0" \
 "reprog="\
+    "bootp; " \
     "tftpboot 0x140000 /bdi2000/u-boot.bin; " \
     "protect off 60000000 6003FFFF; " \
     "erase 60000000 6003FFFF; " \
@@ -405,7 +409,7 @@
 "adc-12=echo ### ADC-12 ; imd.b e 81 e\0" \
 "adc-34=echo ### ADC-34 ; imd.b f 81 e\0" \
 "dac=echo ### DAC ; imd.b 11 81 5\0" \
-"boot-hook=run ana\0"
+"boot-hook=echo\0"
 
 /* What should the console's baud rate be? */
 #define CONFIG_BAUDRATE		9600
@@ -466,15 +470,16 @@
 
 #define CONFIG_BOOTP_RANDOM_DELAY       /* Randomize the BOOTP retry delay */
 
-#define CONFIG_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up */
-
 /* Add support for a few extra bootp options like:
  *	- File size
- *	- DNS
+ *	- DNS (up to 2 servers)
+ *      - Send hostname to DHCP server 
  */
 #define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
 				 CONFIG_BOOTP_BOOTFILESIZE | \
-				 CONFIG_BOOTP_DNS)
+				 CONFIG_BOOTP_DNS | \
+                                 CONFIG_BOOTP_DNS2 | \
+                                 CONFIG_BOOTP_SEND_HOSTNAME)
 
 /* undef this to save memory */
 #define CFG_LONGHELP
@@ -492,6 +497,11 @@
  */
 #define CONFIG_TIMESTAMP
 
+/* If this variable is defined, an environment variable named "ver" 
+ * is created by U-Boot showing the U-Boot version.
+ */
+#define CONFIG_VERSION_VARIABLE
+
 /* What U-Boot subsytems do you want enabled? */
 #ifdef CONFIG_ETHER_ON_FCC
 # define CONFIG_COMMANDS	(((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
@@ -503,6 +513,8 @@
 				CFG_CMD_SDRAM   | \
 				CFG_CMD_REGINFO | \
 				CFG_CMD_IMMAP	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_PING	| \
 				CFG_CMD_MII	)
 #else
 # define CONFIG_COMMANDS	(((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
@@ -513,12 +525,16 @@
 				CFG_CMD_SPI	| \
 				CFG_CMD_SDRAM   | \
 				CFG_CMD_REGINFO | \
-				CFG_CMD_IMMAP	)
+				CFG_CMD_IMMAP	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_PING	)
 #endif /* CONFIG_ETHER_ON_FCC */
 
 /* Where do the internal registers live? */
 #define CFG_IMMR		0xF0000000
 
+#undef	CONFIG_WATCHDOG			/* disable the watchdog */
+
 /*****************************************************************************
  *
  * You should not have to modify any of the following settings
@@ -532,9 +548,48 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
+
 /*
  * Miscellaneous configurable options
  */
+#define CFG_BOOTM_HEADER_QUIET 1        /* Suppress the image header dump    */
+                                        /* in the bootm command.             */
+#define CFG_BOOTM_PROGESS_QUIET 1       /* Suppress the progress displays,   */
+                                        /* "## <message>" from the bootm cmd */
+#define CFG_BOOTP_CHECK_HOSTNAME 1      /* If checkhostname environment is   */
+                                        /* defined, then the hostname param  */
+                                        /* validated against checkhostname.  */
+#define CFG_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up   */
+#define CFG_BOOTP_SHORT_RANDOM_DELAY 1  /* Use a short random delay value    */
+                                        /* (limited to maximum of 1024 msec) */
+#define CFG_CHK_FOR_ABORT_AT_LEAST_ONCE 1
+                                        /* Check for abort key presses       */
+                                        /* at least once in dependent of the */
+                                        /* CONFIG_BOOTDELAY value.           */
+#define CFG_CONSOLE_INFO_QUIET 1        /* Don't print console @ startup     */
+#define CFG_FAULT_ECHO_LINK_DOWN 1      /* Echo the inverted Ethernet link   */
+                                        /* state to the fault LED.           */
+#define CFG_FAULT_MII_ADDR 0x02         /* MII addr of the PHY to check for  */
+                                        /* the Ethernet link state.          */
+#define CFG_STATUS_FLASH_UNTIL_TFTP_OK 1 /* Keeping the status LED flashing  */
+                                        /* until the TFTP is successful.     */
+#define CFG_STATUS_OFF_AFTER_NETBOOT 1  /* After a successful netboot,       */
+                                        /* turn off the STATUS LEDs.         */
+#define CFG_TFTP_BLINK_STATUS_ON_DATA_IN 1 /* Blink status LED based on      */
+                                        /* incoming data.                    */
+#define CFG_TFTP_BLOCKS_PER_HASH 100    /* For every XX blocks, output a '#' */
+                                        /* to signify that tftp is moving.   */
+#define CFG_TFTP_HASHES_PER_FLASH 200   /* For every '#' hashes,             */
+ 				        /* flash the status LED.             */
+#define CFG_TFTP_HASHES_PER_LINE 65     /* Only output XX '#'s per line      */
+                                        /* during the tftp file transfer.    */
+#define CFG_TFTP_PROGESS_QUIET 1        /* Suppress the progress displays    */
+                                        /* '#'s from the tftp command.       */
+#define CFG_TFTP_STATUS_QUIET 1         /* Suppress the status displays      */
+                                        /* issued during the tftp command.   */
+#define CFG_TFTP_TIMEOUT_COUNT 5        /* How many timeouts TFTP will allow */
+					/* before it gives up.               */
+
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #  define CFG_CBSIZE		1024	/* Console I/O Buffer Size	     */
 #else
@@ -734,12 +789,22 @@
  *-----------------------------------------------------------------------
  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC |\
+			 SYPCR_BMT  |\
+			 SYPCR_PBME |\
+			 SYPCR_LBME |\
+			 SYPCR_SWRI |\
+			 SYPCR_SWP  |\
+                         SYPCR_SWE)
+#else
 #define CFG_SYPCR	(SYPCR_SWTC |\
 			 SYPCR_BMT  |\
 			 SYPCR_PBME |\
 			 SYPCR_LBME |\
 			 SYPCR_SWRI |\
 			 SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
 
 /*-----------------------------------------------------------------------
  * TMCNTSC - Time Counter Status and Control			 4-40

include/configs/sbc8260.h

@@ -196,6 +196,7 @@
 
 #ifdef	CONFIG_ETHER_ON_FCC
 #define CONFIG_ETHER_INDEX	2	/* which SCC/FCC channel for ethernet */
+#undef	CONFIG_ETHER_LOOPBACK_TEST	/* Ethernet external loopback test */
 #define CONFIG_MII			/* MII PHY management		*/
 #define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
 /*
@@ -351,38 +352,39 @@
  *
  */
 #define CONFIG_EXTRA_ENV_SETTINGS \
-	"serverip=192.168.123.201\0" \
-	"ipaddr=192.168.123.203\0" \
+	"serverip=192.168.123.205\0\0" \
+	"ipaddr=192.168.123.213\0" \
 	"reprog="\
-		"tftpboot 0x140000 /bdi2000/u-boot.bin; " \
-		"protect off 1:0; " \
-		"erase 1:0; " \
-		"cp.b 140000 40000000 $(filesize); " \
+		"bootp;" \
+		"tftpboot 0x140000 /bdi2000/u-boot.bin;" \
+		"protect off 1:0;" \
+		"erase 1:0;" \
+		"cp.b 140000 40000000 $(filesize);" \
 		"protect on 1:0\0" \
 	"zapenv="\
-		"protect off 1:1; " \
-		"erase 1:1; " \
+		"protect off 1:1;" \
+		"erase 1:1;" \
 		"protect on 1:1\0" \
 	"root-on-initrd="\
 		"setenv bootcmd "\
-		"version\\;" \
-		"echo\\;" \
-		"bootp\\;" \
+		"version;" \
+		"echo;" \
+		"bootp;" \
 		"setenv bootargs root=/dev/ram0 rw " \
-		"ip=\\$(ipaddr):\\$(serverip):\\$(gatewayip):\\$(netmask):\\$(hostname)::off\\;" \
-		"run boot-hook\\;" \
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+		"run boot-hook;" \
 		"bootm\0" \
 	"root-on-nfs="\
 		"setenv bootcmd "\
-		"version\\;" \
-		"echo\\;" \
-		"bootp\\;" \
+		"version;" \
+		"echo;" \
+		"bootp;" \
 		"setenv bootargs root=/dev/nfs rw " \
-		"nfsroot=\\$(serverip):\\$(rootpath) " \
-		"ip=\\$(ipaddr):\\$(serverip):\\$(gatewayip):\\$(netmask):\\$(hostname)::off\\;" \
-		"run boot-hook\\;" \
+		"nfsroot=$(serverip):$(rootpath) " \
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+		"run boot-hook;" \
 		"bootm\0" \
-	"boot-hook=echo boot-hook\0"
+	"boot-hook=echo\0"
 
 /* Define a command string that is automatically executed when no character
  * is read on the console interface withing "Boot Delay" after reset.
@@ -412,11 +414,14 @@
 
 /* Add support for a few extra bootp options like:
  *	- File size
- *	- DNS
+ *	- DNS (up to 2 servers)
+ *	- Send hostname to DHCP server
  */
 #define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
 				 CONFIG_BOOTP_BOOTFILESIZE | \
-				 CONFIG_BOOTP_DNS)
+				 CONFIG_BOOTP_DNS  | \
+				 CONFIG_BOOTP_DNS2 | \
+				 CONFIG_BOOTP_SEND_HOSTNAME)
 
 /* undef this to save memory */
 #define CFG_LONGHELP
@@ -434,28 +439,37 @@
  */
 #define CONFIG_TIMESTAMP
 
+/* If this variable is defined, an environment variable named "ver"
+ * is created by U-Boot showing the U-Boot version.
+ */
+#define CONFIG_VERSION_VARIABLE
+
 /* What U-Boot subsytems do you want enabled? */
 #ifdef CONFIG_ETHER_ON_FCC
 # define CONFIG_COMMANDS	(((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
-				CFG_CMD_ELF	| \
 				CFG_CMD_ASKENV	| \
 				CFG_CMD_ECHO	| \
+				CFG_CMD_ELF	| \
 				CFG_CMD_I2C	| \
-				CFG_CMD_SDRAM   | \
-				CFG_CMD_REGINFO | \
 				CFG_CMD_IMMAP	| \
-				CFG_CMD_MII	)
+				CFG_CMD_MII	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_REGINFO | \
+				CFG_CMD_SDRAM   )
 #else
 # define CONFIG_COMMANDS	(((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
-				CFG_CMD_ELF	| \
 				CFG_CMD_ASKENV	| \
 				CFG_CMD_ECHO	| \
+				CFG_CMD_ELF	| \
 				CFG_CMD_I2C	| \
-				CFG_CMD_SDRAM   | \
+				CFG_CMD_IMMAP	| \
+				CFG_CMD_PING	| \
 				CFG_CMD_REGINFO | \
-				CFG_CMD_IMMAP	)
+				CFG_CMD_SDRAM   )
 #endif /* CONFIG_ETHER_ON_FCC */
 
+#undef CONFIG_WATCHDOG				/* disable the watchdog */
+
 /* Where do the internal registers live? */
 #define CFG_IMMR		0xF0000000
 
@@ -670,12 +684,22 @@
  *-----------------------------------------------------------------------
  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC |\
+			 SYPCR_BMT  |\
+			 SYPCR_PBME |\
+			 SYPCR_LBME |\
+			 SYPCR_SWRI |\
+			 SYPCR_SWP  |\
+			 SYPCR_SWE)
+#else
 #define CFG_SYPCR	(SYPCR_SWTC |\
 			 SYPCR_BMT  |\
 			 SYPCR_PBME |\
 			 SYPCR_LBME |\
 			 SYPCR_SWRI |\
 			 SYPCR_SWP)
+#endif	/* CONFIG_WATCHDOG */
 
 /*-----------------------------------------------------------------------
  * TMCNTSC - Time Counter Status and Control			 4-40

include/configs/trab.h

@@ -26,6 +26,11 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#ifdef CONFIG_OLD_VERSION		/* Old configuration:		*/
+#define	CONFIG_RAM_16MB			/*	16 MB SDRAM		*/
+#define CONFIG_FLASH_8MB		/*	 8 MB Flash		*/
+#endif
+
 /*
  * If we are developing, we might want to start armboot from ram
  * so we MUST NOT initialize critical regs like mem-timing ...
@@ -42,6 +47,9 @@
 #undef CONFIG_TRAB_50MHZ		/* run the CPU at 50 MHz	*/
 #define LITTLEENDIAN		1	/* used by usb_ohci.c		*/
 
+/* automatic software updates (see board/trab/auto_update.c) */
+#define CONFIG_AUTO_UPDATE	1
+
 /* input clock of PLL */
 #define CONFIG_SYS_CLK_FREQ	12000000 /* TRAB has 12 MHz input clock */
 
@@ -176,7 +184,7 @@
 #define CONFIG_SERVERIP		192.168.3.1
 #define CONFIG_BOOTCOMMAND	"run flash_nfs"
 
-#ifndef CONFIG_BIG_FLASH
+#ifndef CONFIG_FLASH_8MB	/* current config: 16 MB flash */
 #ifdef CFG_HUSH_PARSER
 #define	CONFIG_EXTRA_ENV_SETTINGS	\
 	"nfs_args=setenv bootargs root=/dev/nfs rw " \
@@ -186,14 +194,15 @@
 	"add_net=setenv bootargs $bootargs ethaddr=$ethaddr " \
 		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
 	"add_misc=setenv bootargs $bootargs console=ttyS0 panic=1\0" \
-	"load=tftp 0xC100000 /tftpboot/TRAB/u-boot.bin\0" \
-	"update=protect off 1:0-8;era 1:0-8;cp.b 0xc100000 0 $filesize;" \
-		"setenv filesize;saveenv\0" \
+	"u-boot=/tftpboot/TRAB/u-boot.bin\0" \
+	"load=tftp C100000 ${u-boot}\0" \
+	"update=protect off 0 5FFFF;era 0 5FFFF;" \
+		"cp.b C100000 0 $filesize\0" \
 	"loadfile=/tftpboot/TRAB/uImage\0" \
 	"loadaddr=c400000\0" \
 	"net_load=tftpboot $loadaddr $loadfile\0" \
 	"net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \
-	"kernel_addr=00040000\0" \
+	"kernel_addr=000C0000\0" \
 	"flash_nfs=run nfs_args add_net add_misc;bootm $kernel_addr\0" \
 	"mdm_init1=ATZ\0" \
 	"mdm_init2=ATS0=1\0" \
@@ -207,20 +216,21 @@
 	"add_net=setenv bootargs $(bootargs) ethaddr=$(ethaddr) " \
 		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off\0" \
 	"add_misc=setenv bootargs $(bootargs) console=ttyS0 panic=1\0" \
-	"load=tftp 0xC100000 /tftpboot/TRAB/u-boot.bin\0" \
-	"update=protect off 1:0-8;era 1:0-8;cp.b 0xc100000 0 $(filesize);" \
-		"setenv filesize;saveenv\0" \
+	"u-boot=/tftpboot/TRAB/u-boot.bin\0" \
+	"load=tftp C100000 $(u-boot)\0" \
+	"update=protect off 0 5FFFF;era 0 5FFFF;" \
+		"cp.b C100000 0 $(filesize)\0" \
 	"loadfile=/tftpboot/TRAB/uImage\0" \
 	"loadaddr=c400000\0" \
 	"net_load=tftpboot $(loadaddr) $(loadfile)\0" \
 	"net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \
-	"kernel_addr=00040000\0" \
+	"kernel_addr=000C0000\0" \
 	"flash_nfs=run nfs_args add_net add_misc;bootm $(kernel_addr)\0" \
 	"mdm_init1=ATZ\0" \
 	"mdm_init2=ATS0=1\0" \
 	"mdm_flow_control=rts/cts\0"
-#endif /* CFG_HUSH_PARSER */
-#else	/* CONFIG_BIG_FLASH */
+#endif	/* CFG_HUSH_PARSER */
+#else	/* CONFIG_FLASH_8MB 	 => 8 MB flash */
 #ifdef CFG_HUSH_PARSER
 #define	CONFIG_EXTRA_ENV_SETTINGS	\
 	"nfs_args=setenv bootargs root=/dev/nfs rw " \
@@ -230,13 +240,16 @@
 	"add_net=setenv bootargs $bootargs ethaddr=$ethaddr " \
 		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
 	"add_misc=setenv bootargs $bootargs console=ttyS0 panic=1\0" \
-	"load=tftp 0xC100000 /tftpboot/TRAB/u-boot.bin\0" \
-	"update=protect off 1:0;era 1:0;cp.b 0xc100000 0 $filesize\0" \
+	"u-boot=/tftpboot/TRAB/u-boot.bin-old\0" \
+	"load=tftp C100000 ${u-boot}\0" \
+	"update=protect off 0 3FFFF;era 0 3FFFF;" \
+		"cp.b C100000 0 $filesize;" \
+		"setenv filesize;saveenv\0" \
 	"loadfile=/tftpboot/TRAB/uImage\0" \
-	"loadaddr=c400000\0" \
+	"loadaddr=C400000\0" \
 	"net_load=tftpboot $loadaddr $loadfile\0" \
 	"net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \
-	"kernel_addr=00040000\0" \
+	"kernel_addr=000C0000\0" \
 	"flash_nfs=run nfs_args add_net add_misc;bootm $kernel_addr\0" \
 	"mdm_init1=ATZ\0" \
 	"mdm_init2=ATS0=1\0" \
@@ -250,19 +263,22 @@
 	"add_net=setenv bootargs $(bootargs) ethaddr=$(ethaddr) " \
 		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off\0" \
 	"add_misc=setenv bootargs $(bootargs) console=ttyS0 panic=1\0" \
-	"load=tftp 0xC100000 /tftpboot/TRAB/u-boot.bin\0" \
-	"update=protect off 1:0;era 1:0;cp.b 0xc100000 0 $(filesize)\0" \
+	"u-boot=/tftpboot/TRAB/u-boot.bin-old\0" \
+	"load=tftp C100000 $(u-boot)\0" \
+	"update=protect off 0 3FFFF;era 0 3FFFF;" \
+		"cp.b C100000 0 $(filesize);" \
+		"setenv filesize;saveenv\0" \
 	"loadfile=/tftpboot/TRAB/uImage\0" \
-	"loadaddr=c400000\0" \
+	"loadaddr=C400000\0" \
 	"net_load=tftpboot $(loadaddr) $(loadfile)\0" \
 	"net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \
-	"kernel_addr=00040000\0" \
+	"kernel_addr=000C0000\0" \
 	"flash_nfs=run nfs_args add_net add_misc;bootm $(kernel_addr)\0" \
 	"mdm_init1=ATZ\0" \
 	"mdm_init2=ATS0=1\0" \
 	"mdm_flow_control=rts/cts\0"
 #endif /* CFG_HUSH_PARSER */
-#endif	/* CONFIG_BIG_FLASH */
+#endif	/* CONFIG_FLASH_8MB */
 
 #if 0	/* disabled for development */
 #define	CONFIG_AUTOBOOT_KEYED		/* Enable password protection	*/
@@ -290,12 +306,12 @@
 #define	CFG_MAXARGS		16		/* max number of command args	*/
 #define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0c000000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0d000000	/* 16 MB in DRAM	*/
+#define CFG_MEMTEST_START	0x0C000000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0D000000	/* 16 MB in DRAM	*/
 
 #undef CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define	CFG_LOAD_ADDR		0x0cf00000	/* default load address	*/
+#define	CFG_LOAD_ADDR		0x0CF00000	/* default load address	*/
 
 #ifdef CONFIG_TRAB_50MHZ
 /* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
@@ -334,27 +350,27 @@
  * Physical Memory Map
  */
 #define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x0c000000	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1		0x0C000000	/* SDRAM Bank #1 */
+#ifndef CONFIG_RAM_16MB
+#define PHYS_SDRAM_1_SIZE	0x02000000	/* 32 MB */
+#else
 #define PHYS_SDRAM_1_SIZE	0x01000000	/* 16 MB */
+#endif
 
 #define CFG_FLASH_BASE		0x00000000	/* Flash Bank #1 */
 
 /* The following #defines are needed to get flash environment right */
 #define	CFG_MONITOR_BASE	CFG_FLASH_BASE
-#ifndef CONFIG_BIG_FLASH
 #define	CFG_MONITOR_LEN		(256 << 10)
-#else
-#define	CFG_MONITOR_LEN		(128 << 10)
-#endif
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
 #define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#ifndef CONFIG_BIG_FLASH
-#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
-#else
+#ifndef CONFIG_FLASH_8MB
 #define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
+#else
+#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
 #endif
 
 /* timeout values are in ticks */
@@ -364,14 +380,14 @@
 #define	CFG_ENV_IS_IN_FLASH	1
 
 /* Address and size of Primary Environment Sector	*/
-#ifndef CONFIG_BIG_FLASH
+#ifndef CONFIG_FLASH_8MB
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x60000)
+#define CFG_ENV_SIZE		0x4000
+#define CFG_ENV_SECT_SIZE	0x20000
+#else
 #define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x4000)
 #define CFG_ENV_SIZE		0x4000
 #define CFG_ENV_SECT_SIZE	0x4000
-#else
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x20000)
-#define CFG_ENV_SIZE		0x4000
-#define CFG_ENV_SECT_SIZE	0x20000
 #endif
 
 /* Address and size of Redundant Environment Sector	*/

include/miiphy.h

@@ -1,38 +1,38 @@
 /*----------------------------------------------------------------------------+
 |
-|       This source code has been made available to you by IBM on an AS-IS
-|       basis.  Anyone receiving this source is licensed under IBM
-|       copyrights to use it in any way he or she deems fit, including
-|       copying it, modifying it, compiling it, and redistributing it either
-|       with or without modifications.  No license under IBM patents or
-|       patent applications is to be implied by the copyright license.
+|	This source code has been made available to you by IBM on an AS-IS
+|	basis.	Anyone receiving this source is licensed under IBM
+|	copyrights to use it in any way he or she deems fit, including
+|	copying it, modifying it, compiling it, and redistributing it either
+|	with or without modifications.	No license under IBM patents or
+|	patent applications is to be implied by the copyright license.
 |
-|       Any user of this software should understand that IBM cannot provide
-|       technical support for this software and will not be responsible for
-|       any consequences resulting from the use of this software.
+|	Any user of this software should understand that IBM cannot provide
+|	technical support for this software and will not be responsible for
+|	any consequences resulting from the use of this software.
 |
-|       Any person who transfers this source code or any derivative work
-|       must include the IBM copyright notice, this paragraph, and the
-|       preceding two paragraphs in the transferred software.
+|	Any person who transfers this source code or any derivative work
+|	must include the IBM copyright notice, this paragraph, and the
+|	preceding two paragraphs in the transferred software.
 |
-|       COPYRIGHT   I B M   CORPORATION 1999
-|       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+|	COPYRIGHT   I B M   CORPORATION 1999
+|	LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
 +----------------------------------------------------------------------------*/
 /*----------------------------------------------------------------------------+
 |
-|  File Name:   miiphy.h
+|  File Name:	miiphy.h
 |
-|  Function:    Include file defining PHY registers.
+|  Function:	Include file defining PHY registers.
 |
-|  Author:      Mark Wisner
+|  Author:	Mark Wisner
 |
 |  Change Activity-
 |
-|  Date        Description of Change                                       BY
-|  ---------   ---------------------                                       ---
-|  04-May-99   Created                                                     MKW
-|  07-Jul-99   Added full duplex support                                   MKW
-|  08-Sep-01   Tweaks                                                      gvb
+|  Date	       Description of Change					BY
+|  ---------   ---------------------					---
+|  04-May-99   Created							MKW
+|  07-Jul-99   Added full duplex support				MKW
+|  08-Sep-01   Tweaks							gvb
 |
 +----------------------------------------------------------------------------*/
 #ifndef _miiphy_h_
@@ -49,35 +49,35 @@ int  miiphy_duplex(unsigned char addr);
 
 
 /* phy seed setup */
-#define AUTO     99
-#define _100BASET 100
-#define _10BASET  10
-#define HALF   22
-#define FULL   44
+#define AUTO			99
+#define _100BASET		100
+#define _10BASET		10
+#define HALF			22
+#define FULL			44
 
 /* phy register offsets */
-#define PHY_BMCR 		0x00
+#define PHY_BMCR		0x00
 #define PHY_BMSR		0x01
-#define PHY_PHYIDR1 	0x02
-#define PHY_PHYIDR2	0x03
+#define PHY_PHYIDR1		0x02
+#define PHY_PHYIDR2		0x03
 #define PHY_ANAR		0x04
-#define PHY_ANLPAR	0x05
+#define PHY_ANLPAR		0x05
 #define PHY_ANER		0x06
-#define PHY_ANNPTR	0x07
-#define PHY_PHYSTS	0x10
-#define PHY_MIPSCR	0x11
-#define PHY_MIPGSR	0x12
-#define PHY_DCR		0x13
+#define PHY_ANNPTR		0x07
+#define PHY_PHYSTS		0x10
+#define PHY_MIPSCR		0x11
+#define PHY_MIPGSR		0x12
+#define PHY_DCR			0x13
 #define PHY_FCSCR		0x14
 #define PHY_RECR		0x15
 #define PHY_PCSR		0x16
-#define PHY_LBR		0x17
-#define PHY_10BTSCR	0x18
-#define PHY_PHYCTRL	0x19
+#define PHY_LBR			0x17
+#define PHY_10BTSCR		0x18
+#define PHY_PHYCTRL		0x19
 
 /* PHY BMCR */
-#define PHY_BMCR_RESET  	0x8000
-#define PHY_BMCR_LOOP  	 	0x4000
+#define PHY_BMCR_RESET		0x8000
+#define PHY_BMCR_LOOP		0x4000
 #define PHY_BMCR_100MB		0x2000
 #define PHY_BMCR_AUTON		0x1000
 #define PHY_BMCR_POWD		0x0800
@@ -103,11 +103,11 @@ int  miiphy_duplex(unsigned char addr);
 /*phy ANLPAR */
 #define PHY_ANLPAR_NP		0x8000
 #define PHY_ANLPAR_ACK		0x4000
-#define PHY_ANLPAR_RF         0x2000
-#define PHY_ANLPAR_T4         0x0200
-#define PHY_ANLPAR_TXFD       0x0100
-#define PHY_ANLPAR_TX         0x0080
+#define PHY_ANLPAR_RF		0x2000
+#define PHY_ANLPAR_T4		0x0200
+#define PHY_ANLPAR_TXFD		0x0100
+#define PHY_ANLPAR_TX		0x0080
 #define PHY_ANLPAR_10FD		0x0040
-#define PHY_ANLPAR_10         0x0020
-#define PHY_ANLPAR_100        0x0380        /* we can run at 100 */
+#define PHY_ANLPAR_10		0x0020
+#define PHY_ANLPAR_100		0x0380	    /* we can run at 100 */
 #endif

include/mpc5xxx.h

@@ -108,6 +108,9 @@
 
 #define	MPC5XXX_FEC		(CFG_MBAR + 0x3000)
 
+#define MPC5XXX_I2C1		(CFG_MBAR + 0x3D00)
+#define MPC5XXX_I2C2		(CFG_MBAR + 0x3D40)
+
 #if defined(CONFIG_MGT5100)
 #define MPC5XXX_SRAM		(CFG_MBAR + 0x4000)
 #define MPC5XXX_SRAM_SIZE	(8*1024)
@@ -148,6 +151,13 @@
 #define MPC5XXX_CS_DEADCYCLE	(MPC5XXX_LPB + 0x002c)
 #endif
 
+#if defined(CONFIG_MPC5200)
+/* XLB Arbiter registers */
+#define MPC5XXX_XLBARB_CFG		(MPC5XXX_XLBARB + 0x40)
+#define MPC5XXX_XLBARB_MPRIEN	(MPC5XXX_XLBARB + 0x64)
+#define MPC5XXX_XLBARB_MPRIVAL	(MPC5XXX_XLBARB + 0x68)
+#endif
+
 /* GPIO registers */
 #define MPC5XXX_GPS_PORT_CONFIG	(MPC5XXX_GPIO + 0x0000)
 
@@ -197,6 +207,24 @@
 #define MPC5XXX_GPT0_ENABLE		(MPC5XXX_GPT + 0x0)
 #define MPC5XXX_GPT0_COUNTER		(MPC5XXX_GPT + 0x4)
 
+/* I2Cn control register bits */
+#define I2C_EN		0x80
+#define I2C_IEN		0x40
+#define I2C_STA		0x20
+#define I2C_TX		0x10
+#define I2C_TXAK	0x08
+#define I2C_RSTA	0x04
+#define I2C_INIT_MASK	(I2C_EN | I2C_STA | I2C_TX | I2C_RSTA)
+
+/* I2Cn status register bits */
+#define I2C_CF		0x80
+#define I2C_AAS		0x40
+#define I2C_BB		0x20
+#define I2C_AL		0x10
+#define I2C_SRW		0x04
+#define I2C_IF		0x02
+#define I2C_RXAK	0x01
+
 /* Programmable Serial Controller (PSC) status register bits */
 #define PSC_SR_CDE		0x0080
 #define PSC_SR_RXRDY		0x0100
@@ -505,6 +533,14 @@ struct mpc5xxx_sdma {
 	volatile u32 EU37;		/* SDMA + 0xfc */
 };
 
+struct mpc5xxx_i2c {
+	volatile u32 madr;		/* I2Cn + 0x00 */
+	volatile u32 mfdr;		/* I2Cn + 0x04 */
+	volatile u32 mcr;		/* I2Cn + 0x08 */
+	volatile u32 msr;		/* I2Cn + 0x0C */
+	volatile u32 mdr;		/* I2Cn + 0x10 */
+};
+
 /* function prototypes */
 void loadtask(int basetask, int tasks);
 

lib_arm/board.c

@@ -157,7 +157,7 @@ static void display_flash_config (ulong size)
 /*
  * Breath some life into the board...
  *
- * Initialize an SMC for serial comms, and carry out some hardware
+ * Initialize a serial port as console, and carry out some hardware
  * tests.
  *
  * The first part of initialization is running from Flash memory;
@@ -285,7 +285,7 @@ void start_armboot (void)
 		}
 	}
 
-	devices_init ();      /* get the devices list going. */
+	devices_init ();	/* get the devices list going. */
 
 	jumptable_init ();
 

rtc/s3c24x0_rtc.c

@@ -80,13 +80,15 @@ void rtc_get (struct rtc_time *tmp)
 	SetRTC_Access(RTC_ENABLE);
 
 	/* read RTC registers */
-	sec	= rtc->BCDSEC;
-	min	= rtc->BCDMIN;
-	hour	= rtc->BCDHOUR;
-	mday	= rtc->BCDDATE;
-	wday	= rtc->BCDDAY;
-	mon	= rtc->BCDMON;
-	year	= rtc->BCDYEAR;
+	do {
+		sec	= rtc->BCDSEC;
+		min	= rtc->BCDMIN;
+		hour	= rtc->BCDHOUR;
+		mday	= rtc->BCDDATE;
+		wday	= rtc->BCDDAY;
+		mon	= rtc->BCDMON;
+		year	= rtc->BCDYEAR;
+	} while (sec != rtc->BCDSEC);
 
 	/* read ALARM registers */
 	a_sec	= rtc->ALMSEC;
@@ -170,7 +172,7 @@ void rtc_reset (void)
 	S3C24X0_RTC * const rtc = S3C24X0_GetBase_RTC();
 
 	rtc->RTCCON = (rtc->RTCCON & ~0x06) | 0x08;
-	rtc->RTCCON &= ~0x08;
+	rtc->RTCCON &= ~(0x08|0x01);
 }
 
 /* ------------------------------------------------------------------------- */

tools/mkimage.c

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2002
+ * (C) Copyright 2000-2003
  * DENX Software Engineering
  * Wolfgang Denk, wd@denx.de
  * All rights reserved.
@@ -39,6 +39,10 @@ typedef		unsigned int	uint32_t;
 #define     htonl(a)	SWAP_LONG(a)
 #endif	/* __WIN32__ */
 
+#ifndef	O_BINARY		/* should be define'd on __WIN32__ */
+#define O_BINARY	0
+#endif
+
 #include <image.h>
 
 extern int errno;
@@ -265,11 +269,7 @@ NXTARG:		;
 	if (lflag) {
 		ifd = open(imagefile, O_RDONLY);
 	} else {
-#ifdef __WIN32__
 		ifd = open(imagefile, O_RDWR|O_CREAT|O_TRUNC|O_BINARY, 0666);
-#else
-		ifd = open(imagefile, O_RDWR|O_CREAT|O_TRUNC, 0666);
-#endif
 	}
 
 	if (ifd < 0) {