*** empty log message ***

CREDITS

@@ -18,14 +18,14 @@ N: Dr. Bruno Achauer
 E: bruno@exet-ag.de
 D: Support for NetBSD (both as host and target system)
 
-N: Guillaume Alexandre
-E: guillaume.alexandre@gespac.ch
-D: Add PCIPPC6 configuration
-
 N: Swen Anderson
 E: sand@peppercon.de
 D: ERIC Support
 
+N: Guillaume Alexandre
+E: guillaume.alexandre@gespac.ch
+D: Add PCIPPC6 configuration
+
 N: Pantelis Antoniou
 E: panto@intracom.gr
 D: NETVIA board support, ARTOS support.
@@ -75,7 +75,7 @@ E: clark@esteem.com
 D: ESTEEM192E support
 
 N: Magnus Damm
-E: damm@opensource.se
+E: eramdam@kieray1.p.y.ki.era.ericsson.se
 D: 8xxrom
 
 N: Arun Dharankar
@@ -182,37 +182,19 @@ N: Brad Kemp
 E: Brad.Kemp@seranoa.com
 D: Port to Windriver ppmc8260 board
 
-N: Sangmoon Kim
-E: dogoil@etinsys.com
-D: Support for debris board
-
 N: Thomas Koeller
 E: tkoeller@gmx.net
 D: Port to Motorola Sandpoint 3 (MPC8240)
 
-N: Raghu Krishnaprasad
-E: Raghu.Krishnaprasad@fci.com
-D: Support for Adder-II MPC852T evaluation board
-W: http://www.forcecomputers.com
-
-N: Bernhard Kuhn
-E: bkuhn@metrowerks.com
-D Support for Coldfire CPU; Support for Motorola M5272C3 and M5282EVB boards
-
 N: Thomas Lange
-E: thomas@corelatus.se
-D: Support for GTH and dbau1x00 boards; lots of PCMCIA fixes
+E: thomas@corelatus.com
+D: Support for GTH board; lots of PCMCIA fixes
 
 N: The LEOX team
 E: team@leox.org
 D: Support for LEOX boards, DS164x RTC
 W: http://www.leox.org
 
-N: Stephan Linz
-E: linz@li-pro.net
-D: Support for Nios Stratix Development Kit (DK-1S10)
-W: http://www.li-pro.net
-
 N: Raymond Lo
 E: lo@routefree.com
 D: Support for DOS partitions
@@ -237,10 +219,6 @@ N: David M
 E: d.mueller@elsoft.ch
 D: Support for Samsung ARM920T SMDK2410 eval board
 
-N: Scott McNutt
-E: smcnutt@psyent.com
-D: Support for Altera Nios-32 CPU, for Nios Cyclone Development Kit (DK-1C20)
-
 N: Rolf Offermanns
 E: rof@sysgo.de
 D: Initial support for SSV-DNP1110, SMC91111 driver
@@ -276,10 +254,6 @@ N: Neil Russell
 E: caret@c-side.com
 D: Author of LiMon-1.4.2, which contributed some ideas
 
-N: Travis B. Sawyer
-E: travis.sawyer@sandburst.com
-D: Support for IBM PPC440GX, XES XPedite1000 440GX PrPMC board.
-
 N: Paolo Scaffardi
 E: arsenio@tin.it
 D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots more
@@ -325,6 +299,6 @@ E: azu@sysgo.de
 D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
 W: www.elinos.com
 
-N: Xianghua Xiao
-E: x.xiao@motorola.com
-D: Support for Motorola 85xx(PowerQUICC III) chip, MPC8540ADS and MPC8560ADS boards.
+N: Pantelis Antoniou
+E: panto@intracom.gr
+D: NETVIA board support, ARTOS support.

MAINTAINERS

@@ -25,10 +25,6 @@ Pantelis Antoniou <panto@intracom.gr>
 
 	NETVIA			MPC8xx
 
-Yuli Barcohen <yuli@arabellasw.com>
-
-	ZPC1900			MPC8265
-
 Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
 
 	sacsng			MPC8260
@@ -56,8 +52,6 @@ Wolfgang Denk <wd@denx.de>
 	FPS850L			MPC850
 	FPS860L			MPC860
 	ICU862			MPC862
-	IceCube_5100		MGT5100
-	IceCube_5200		MPC5200
 	IP860			MPC860
 	IVML24			MPC860
 	IVML24_128		MPC860
@@ -78,6 +72,7 @@ Wolfgang Denk <wd@denx.de>
 	TQM855L			MPC855
 	TQM860L			MPC860
 	TQM860L_FEC		MPC860
+	TTTech			MPC823
 	c2mon			MPC855
 	hermes			MPC860
 	lwmon			MPC823
@@ -93,12 +88,9 @@ Wolfgang Denk <wd@denx.de>
 	TQM8255			MPC8255
 
 	CPU86			MPC8260
-	PM825			MPC8250
 	PM826			MPC8260
 	TQM8260			MPC8260
 
-	P3G4			MPC7410
-
 	PCIPPC2			MPC750
 	PCIPPC6			MPC750
 
@@ -135,10 +127,6 @@ Howard Gray <mvsensor@matrix-vision.de>
 
 	MVS1			MPC823
 
-Bill Hargen <Bill_Hargen@Jabil.com>
-
-	BUBINGA405EP		PPC405EP
-
 Klaus Heydeck <heydeck@kieback-peter.de>
 
 	KUP4K			MPC855
@@ -154,19 +142,11 @@ Brad Kemp <Brad.Kemp@seranoa.com>
 
 	ppmc8260		MPC8260
 
-Sangmoon Kim <dogoil@etinsys.com>
-
-	debris			MPC8245
-
-Raghu Krishnaprasad <raghu.krishnaprasad@fci.com>
-
-	ADDERII			MPC852T
-
 Nye Liu <nyet@zumanetworks.com>
 
 	ZUMA			MPC7xx_74xx
 
-Thomas Lange <thomas@corelatus.se>
+Thomas Lange <thomas@corelatus.com>
 
 	GTH			MPC860
 
@@ -180,8 +160,7 @@ Eran Man <eran@nbase.co.il>
 
 Reinhard Meyer <r.meyer@emk-elektronik.de>
 
-	TOP860			MPC860T
-	TOP5200			MPC5200
+	TOP860			MPC860
 
 Scott McNutt <smcnutt@artesyncp.com>
 
@@ -213,15 +192,11 @@ Stefan Roese <stefan.roese@esd-electronics.com>
 	CPCI440			PPC440GP
 	CPCIISER4		PPC405GP
 	DASA_SIM		IOP480 (PPC401)
-	DP405			PPC405EP
 	DU405			PPC405GP
-	HUB405			PPC405EP
 	OCRTC			PPC405GP
 	ORSG			PPC405GP
 	PCI405			PPC405GP
-	PLU405			PPC405EP
 	PMC405			PPC405GP
-	VOH405			PPC405EP
 
 Peter De Schrijver <p2@mind.be>
 
@@ -245,11 +220,6 @@ John Zhan <zhanz@sinovee.com>
 
 	svm_sc8xx		MPC8xx
 
-Xianghua Xiao <x.xiao@motorola.com>
-
-	MPC8540ADS		MPC8540
-	MPC8560ADS		MPC8560
-
 -------------------------------------------------------------------------
 
 Unknown / orphaned boards:
@@ -299,17 +269,12 @@ Kyle Harris <kharris@nexus-tech.net>
 
 	lubbock			xscale
 	cradle			xscale
-	ixdp425			xscale
 
 Gary Jennejohn <gj@denx.de>
 
 	smdk2400		ARM920T
 	trab			ARM920T
 
-Kshitij Gupta <kshitij@ti.com>
-	omap1510inn		ARM925T
-	omap1610inn		ARM926EJS
-
 David Müller <d.mueller@elsoft.ch>
 
 	smdk2410		ARM920T
@@ -352,24 +317,6 @@ Wolfgang Denk <wd@denx.de>
 	incaip			MIPS32 4Kc
 	purple			MIPS64 5Kc
 
-Thomas Lange <thomas@corelatus.se>
-	dbau1x00		MIPS32 Au1000
-
-#########################################################################
-# Nios-32 Systems:							#
-#									#
-# Maintainer Name, Email Address					#
-#	Board			CPU					#
-#########################################################################
-
-Stephan Linz <linz@li-pro.net>
-
-	DK1S10			Nios-32
-
-Scott McNutt <smcnutt@psyent.com>
-
-	DK1C20			Nios-32
-
 #########################################################################
 # End of MAINTAINERS list						#
 #########################################################################

MAKEALL

@@ -1,7 +1,5 @@
 #!/bin/sh
 
-: ${JOBS:=}
-
 if [ "${CROSS_COMPILE}" ] ; then
 	MAKE="make CROSS_COMPILE=${CROSS_COMPILE}"
 else
@@ -20,35 +18,25 @@ LIST_5xx="	\
 	cmi_mpc5xx							\
 "
 
-#########################################################################
-## MPC5xxx Systems
-#########################################################################
-
-LIST_5xxx="	\
-	IceCube_5100	IceCube_5200	EVAL5200	\
-"
-
 #########################################################################
 ## MPC8xx Systems
 #########################################################################
 
 LIST_8xx="	\
-	AdderII		ADS860		AMX860		c2mon		\
-	CCM		cogent_mpc8xx	DUET_ADS	ESTEEM192E	\
-	ETX094		ELPT860		FADS823		FADS850SAR	\
-	FADS860T	FLAGADM		FPS850L		GEN860T		\
-	GEN860T_SC	GENIETV		GTH		hermes		\
-	IAD210		ICU862_100MHz	IP860		IVML24		\
-	IVML24_128	IVML24_256	IVMS8		IVMS8_128	\
-	IVMS8_256	KUP4K           LANTEC	        lwmon   	\
-	MBX		MBX860T		MHPC		MPC86xADS	\
-	MVS1		NETVIA		NETVIA_V2	NX823		\
-	pcu_e		QS823		QS850		QS860T		\
-	R360MPI		RBC823		rmu		RPXClassic	\
-	RPXlite		RRvision	SM850		SPD823TS	\
-	svm_sc8xx	SXNI855T	TOP860		TQM823L		\
-	TQM823L_LCD	TQM850L		TQM855L		TQM860L		\
-	v37								\
+	ADS860		AMX860		c2mon		CCM		\
+	cogent_mpc8xx	ESTEEM192E	ETX094		ELPT860		\
+	FADS823		FADS850SAR	FADS860T	FLAGADM		\
+	FPS850L		GEN860T		GEN860T_SC	GENIETV		\
+	GTH		hermes		IAD210		ICU862_100MHz	\
+	IP860		IVML24		IVML24_128	IVML24_256	\
+	IVMS8		IVMS8_128	IVMS8_256	KUP4K           \
+	LANTEC	        lwmon   	MBX		MBX860T		\
+	MHPC		MVS1		NETVIA		NETVIA_V2	\
+	NX823		pcu_e		R360MPI		RBC823		\
+	rmu		RPXClassic	RPXlite		RRvision	\
+	SM850		SPD823TS	svm_sc8xx	SXNI855T	\
+	TOP860		TQM823L		TQM823L_LCD	TQM850L		\
+	TQM855L		TQM860L		TTTech		v37		\
 "
 
 #########################################################################
@@ -57,14 +45,12 @@ LIST_8xx="	\
 
 LIST_4xx="	\
 	ADCIOP		AR405		ASH405          BUBINGA405EP    \
-	CANBT		CPCI405		CPCI4052 	CPCI405AB       \
-	CPCI440         CPCIISER4	CRAYL1  	DASA_SIM	\
-	DP405           DU405    	EBONY           ERIC  		\
-	EXBITGEN	HUB405          MIP405  	MIP405T		\
-	ML2		OCRTC		ORSG		PCI405		\
-	PIP405		PLU405          PMC405          PPChameleonEVB	\
-	VOH405          W7OLMC		W7OLMG          WALNUT405	\
-	XPEDITE1K							\
+        CANBT		CPCI405		CPCI4052 	CPCI405AB       \
+        CPCI440         CPCIISER4	CRAYL1  	DASA_SIM	\
+        DU405    	EBONY           ERIC  		EXBITGEN	\
+	MIP405  	MIP405T		ML2		OCRTC		\
+	ORSG		PCI405		PIP405		PMC405          \
+	W7OLMC		W7OLMG          WALNUT405			\
 "
 
 #########################################################################
@@ -72,10 +58,9 @@ LIST_4xx="	\
 #########################################################################
 
 LIST_824x="	\
-	A3000           BMW		CPC45		CU824		\
-	debris		MOUSSE          MUSENKI    	MVBLUE		\
-	OXC		PN62		Sandpoint8240   Sandpoint8245	\
-	SL8245		utx8245						\
+        A3000           BMW		CPC45		CU824		\
+	MOUSSE          MUSENKI    	OXC		PN62		\
+	Sandpoint8240   Sandpoint8245	SL8245		utx8245		\
 "
 
 #########################################################################
@@ -87,15 +72,7 @@ LIST_8260="	\
 	gw8260		hymod		IPHASE4539	MPC8260ADS	\
 	MPC8266ADS	PM826		ppmc8260	RPXsuper	\
 	rsdproto	sacsng		sbc8260		SCM		\
-	TQM8260_AC	TQM8260_AD	TQM8260_AE	ZPC1900		\
-"
-
-#########################################################################
-## MPC85xx Systems (includes 8540, 8560 etc.)
-#########################################################################
-
-LIST_85xx="	\
-	MPC8540ADS	MPC8560ADS					\
+	TQM8260								\
 "
 
 #########################################################################
@@ -103,18 +80,15 @@ LIST_85xx="	\
 #########################################################################
 
 LIST_74xx="	\
-	DB64360		DB64460		EVB64260	P3G4		\
-	PCIPPC2		PCIPPC6		ZUMA				\
+	EVB64260	PCIPPC2		PCIPPC6		ZUMA		\
 "
 
 LIST_7xx="	\
 	BAB7xx		ELPPC						\
 "
 
-LIST_ppc="${LIST_5xx}  ${LIST_5xxx} \
-	  ${LIST_8xx}  \
+LIST_ppc="${LIST_5xx}  ${LIST_8xx}  \
 	  ${LIST_824x} ${LIST_8260} \
-	  ${LIST_85xx}	\
 	  ${LIST_4xx}		    \
 	  ${LIST_74xx} ${LIST_7xx}"
 
@@ -134,11 +108,7 @@ LIST_ARM7="ep7312 impa7"
 ## ARM9 Systems
 #########################################################################
 
-LIST_ARM9="	\
-	at91rm9200dk	omap1510inn	omap1610inn			\
-	smdk2400	smdk2410	trab				\
-	VCMA9								\
-"
+LIST_ARM9="at91rm9200dk smdk2400 smdk2410 trab VCMA9"
 
 #########################################################################
 ## Xscale Systems
@@ -146,22 +116,18 @@ LIST_ARM9="	\
 
 LIST_pxa="cradle csb226 innokom lubbock wepep250"
 
-LIST_ixp="ixdp425"
 
-
-LIST_arm="${LIST_SA} ${LIST_ARM7} ${LIST_ARM9} ${LIST_pxa} ${LIST_ixp}"
+LIST_arm="${LIST_SA} ${LIST_ARM7} ${LIST_ARM9} ${LIST_pxa}"
 
 #########################################################################
-## MIPS Systems
+## MIPS 4Kc Systems
 #########################################################################
 
 LIST_mips4kc="incaip"
 
 LIST_mips5kc="purple"
 
-LIST_au1x00="dbau1000 dbau1100 dbau1500"
-
-LIST_mips="${LIST_mips4kc} ${LIST_mips5kc} ${LIST_au1x00}"
+LIST_mips="${LIST_mips4kc} ${LIST_mips5kc}"
 
 #########################################################################
 ## i386 Systems
@@ -171,15 +137,6 @@ LIST_I486="sc520_cdp sc520_spunk sc520_spunk_rel"
 
 LIST_x86="${LIST_I486}"
 
-#########################################################################
-## NIOS Systems
-#########################################################################
-
-LIST_nios="	\
-	DK1C20 DK1C20_standard_32					\
-	DK1S10 DK1S10_standard_32 DK1S10_mtx_ldk_20			\
-"
-
 #-----------------------------------------------------------------------
 
 #----- for now, just run PPC by default -----
@@ -192,7 +149,7 @@ build_target() {
 
 	${MAKE} distclean >/dev/null
 	${MAKE} ${target}_config
-	${MAKE} ${JOBS} all 2>&1 >LOG/$target.MAKELOG | tee LOG/$target.ERR
+	${MAKE} all 2>&1 >LOG/$target.MAKELOG | tee LOG/$target.ERR
 	${CROSS_COMPILE:-ppc_8xx-}size u-boot | tee -a LOG/$target.MAKELOG
 }
 
@@ -202,11 +159,7 @@ build_target() {
 for arg in $@
 do
 	case "$arg" in
-	ppc|5xx|5xxx|8xx|824x|8260|85xx|4xx|7xx|74xx| \
-	arm|SA|ARM7|ARM9|pxa|ixp| \
-	mips| \
-	nios| \
-	x86|I486)
+	5xx|8xx|824x|8260|4xx|7xx|74xx|SA|ARM7|ARM9|ppc|arm|pxa|mips|I486|x86)
 			for target in `eval echo '$LIST_'${arg}`
 			do
 				build_target ${target}

Makefile

@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000-2004
+# (C) Copyright 2000, 2001, 2002
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -69,64 +69,60 @@ endif
 ifeq ($(ARCH),mips)
 CROSS_COMPILE = mips_4KC-
 endif
-ifeq ($(ARCH),nios)
-CROSS_COMPILE = nios-elf-
-endif
-ifeq ($(ARCH),m68k)
-CROSS_COMPILE = m68k-elf-
-endif
 endif
 endif
 
 export	CROSS_COMPILE
 
+# The "tools" are needed early, so put this first
+SUBDIRS	= tools \
+	  lib_generic \
+	  lib_$(ARCH) \
+	  cpu/$(CPU) \
+	  board/$(BOARDDIR) \
+	  common \
+	  disk \
+	  fs \
+	  net \
+	  rtc \
+	  dtt \
+	  drivers \
+	  post \
+	  post/cpu \
+	  examples
+
 #########################################################################
 # U-Boot objects....order is important (i.e. start must be first)
 
-OBJS  = cpu/$(CPU)/start.o
+OBJS  =	cpu/$(CPU)/start.o
 ifeq ($(CPU),i386)
-OBJS += cpu/$(CPU)/start16.o
-OBJS += cpu/$(CPU)/reset.o
+OBJS +=	cpu/$(CPU)/start16.o
+OBJS +=	cpu/$(CPU)/reset.o
 endif
 ifeq ($(CPU),ppc4xx)
-OBJS += cpu/$(CPU)/resetvec.o
-endif
-ifeq ($(CPU),mpc85xx)
-OBJS += cpu/$(CPU)/resetvec.o
+OBJS +=	cpu/$(CPU)/resetvec.o
 endif
 
-LIBS  = lib_generic/libgeneric.a
-LIBS += board/$(BOARDDIR)/lib$(BOARD).a
+LIBS  =	board/$(BOARDDIR)/lib$(BOARD).a
 LIBS += cpu/$(CPU)/lib$(CPU).a
 LIBS += lib_$(ARCH)/lib$(ARCH).a
-LIBS += fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a fs/jffs2/libjffs2.a
+LIBS += fs/jffs2/libjffs2.a fs/fdos/libfdos.a fs/fat/libfat.a
 LIBS += net/libnet.a
 LIBS += disk/libdisk.a
 LIBS += rtc/librtc.a
 LIBS += dtt/libdtt.a
 LIBS += drivers/libdrivers.a
-LIBS += drivers/sk98lin/libsk98lin.a
 LIBS += post/libpost.a post/cpu/libcpu.a
 LIBS += common/libcommon.a
-.PHONY : $(LIBS)
-
-# Add GCC lib
-PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
-
-# The "tools" are needed early, so put this first
-# Don't include stuff already done in $(LIBS)
-SUBDIRS	= tools \
-	  examples \
-	  post \
-	  post/cpu
-.PHONY : $(SUBDIRS)
+LIBS += lib_generic/libgeneric.a
 
-#########################################################################
 #########################################################################
 
-ALL = u-boot.srec u-boot.bin System.map
+all:		u-boot.srec u-boot.bin System.map
 
-all:		$(ALL)
+install:	all
+		-cp u-boot.bin /tftpboot/u-boot.bin
+		-cp u-boot.bin /net/denx/tftpboot/u-boot.bin
 
 u-boot.srec:	u-boot
 		$(OBJCOPY) ${OBJCFLAGS} -O srec $< $@
@@ -134,30 +130,16 @@ u-boot.srec:	u-boot
 u-boot.bin:	u-boot
 		$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
 
-u-boot.img:	u-boot.bin
-		./tools/mkimage -A $(ARCH) -T firmware -C none \
-		-a $(TEXT_BASE) -e 0 \
-		-n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' include/version.h | \
-			sed -e 's/"[	 ]*$$/ for $(BOARD) board"/') \
-		-d $< $@
-
 u-boot.dis:	u-boot
 		$(OBJDUMP) -d $< > $@
 
-u-boot:		depend $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT)
-		UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed  -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
-		$(LD) $(LDFLAGS) $$UNDEF_SYM $(OBJS) \
-			--start-group $(LIBS) $(PLATFORM_LIBS) --end-group \
+u-boot:		depend subdirs $(OBJS) $(LIBS) $(LDSCRIPT)
+		$(LD) $(LDFLAGS) $(OBJS) \
+			--start-group $(LIBS) --end-group \
 			-Map u-boot.map -o u-boot
 
-$(LIBS):
-		$(MAKE) -C `dirname $@`
-
-$(SUBDIRS):
-		$(MAKE) -C $@ all
-
-gdbtools:
-		$(MAKE) -C tools/gdb || exit 1
+subdirs:
+		@for dir in $(SUBDIRS) ; do $(MAKE) -C $$dir || exit 1 ; done
 
 depend dep:
 		@for dir in $(SUBDIRS) ; do $(MAKE) -C $$dir .depend ; done
@@ -198,71 +180,16 @@ unconfig:
 cmi_mpc5xx_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc5xx cmi
 
-PATI_config:unconfig
-	@./mkconfig $(@:_config=) ppc mpc5xx pati mpl
-
-#########################################################################
-## MPC5xxx Systems
-#########################################################################
-MPC5200LITE_config		\
-MPC5200LITE_LOWBOOT_config	\
-MPC5200LITE_LOWBOOT08_config	\
-icecube_5200_DDR_LOWBOOT_config	\
-icecube_5200_DDR_config		\
-IceCube_5200_DDR_config		\
-icecube_5200_config		\
-IceCube_5200_config		\
-IceCube_5100_config:		unconfig
-	@ >include/config.h
-	@[ -z "$(findstring LOWBOOT,$@)" ] || \
-		{ echo "TEXT_BASE = 0xFF000000" >board/icecube/config.tmp ; \
-		  echo "... with LOWBOOT configuration" ; \
-		}
-	@[ -z "$(findstring LOWBOOT08,$@)" ] || \
-		{ echo "TEXT_BASE = 0xFF800000" >board/icecube/config.tmp ; \
-		  echo "... with 8 MB flash only" ; \
-		}
-	@[ -z "$(findstring DDR,$@)" ] || \
-		{ echo "#define CONFIG_MPC5200_DDR"	>>include/config.h ; \
-		  echo "... DDR memory revision" ; \
-		}
-	@[ -z "$(findstring 5200,$@)" ] || \
-		{ echo "#define CONFIG_MPC5200"		>>include/config.h ; \
-		  echo "... with MPC5200 processor" ; \
-		}
-	@[ -z "$(findstring 5100,$@)" ] || \
-		{ echo "#define CONFIG_MGT5100"		>>include/config.h ; \
-		  echo "... with MGT5100 processor" ; \
-		}
-	@./mkconfig -a IceCube ppc mpc5xxx icecube
-
-MINI5200_config	\
-EVAL5200_config	\
-TOP5200_config:	unconfig
-	@ echo "#define CONFIG_$(@:_config=) 1"	>include/config.h
-	@./mkconfig -a TOP5200 ppc mpc5xxx top5200 emk
-
 #########################################################################
 ## MPC8xx Systems
 #########################################################################
 
-AdderII_config:	unconfig
-	@./mkconfig $(@:_config=) ppc mpc8xx adderII
-
-ADS860_config     \
-DUET_ADS_config   \
-FADS823_config    \
-FADS850SAR_config \
-MPC86xADS_config  \
-FADS860T_config:	unconfig
+ADS860_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx fads
 
 AMX860_config	:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx amx860 westel
 
-bms2003_config	:	unconfig
-	@./mkconfig $(@:_config=) ppc mpc8xx tqm8xx
-
 c2mon_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx c2mon
 
@@ -281,6 +208,11 @@ ESTEEM192E_config:	unconfig
 ETX094_config	:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx etx094
 
+FADS823_config	\
+FADS850SAR_config \
+FADS860T_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc8xx fads
+
 FLAGADM_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx flagadm
 
@@ -391,15 +323,6 @@ NX823_config:		unconfig
 pcu_e_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx pcu_e siemens
 
-QS850_config:	unconfig
-	@./mkconfig $(@:_config=) ppc mpc8xx qs850 snmc
-
-QS823_config:	unconfig
-	@./mkconfig $(@:_config=) ppc mpc8xx qs850 snmc
-
-QS860T_config:	unconfig
-	@./mkconfig $(@:_config=) ppc mpc8xx qs860t snmc
-
 R360MPI_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx r360mpi
 
@@ -444,11 +367,10 @@ TOP860_config:		unconfig
 # All boards can come with 50 MHz (default), 66MHz, 80MHz or 100 MHz clock,
 # but only 855 and 860 boards may come with FEC
 # and 823 boards may have LCD support
-xtract_8xx = $(subst _66MHz,,$(subst _80MHz,,$(subst _100MHz,,$(subst _133MHz,,$(subst _LCD,,$(subst _config,,$1))))))
+xtract_8xx = $(subst _66MHz,,$(subst _80MHz,,$(subst _100MHz,,$(subst _LCD,,$(subst _config,,$1)))))
 
 FPS850L_config		\
 FPS860L_config		\
-NSCU_config		\
 TQM823L_config		\
 TQM823L_66MHz_config	\
 TQM823L_80MHz_config	\
@@ -467,23 +389,7 @@ TQM860L_80MHz_config	\
 TQM862L_config		\
 TQM862L_66MHz_config	\
 TQM862L_80MHz_config	\
-TQM823M_config		\
-TQM823M_66MHz_config	\
-TQM823M_80MHz_config	\
-TQM850M_config		\
-TQM850M_66MHz_config	\
-TQM850M_80MHz_config	\
-TQM855M_config		\
-TQM855M_66MHz_config	\
-TQM855M_80MHz_config	\
-TQM860M_config		\
-TQM860M_66MHz_config	\
-TQM860M_80MHz_config	\
-TQM862M_config		\
-TQM862M_66MHz_config	\
-TQM862M_80MHz_config	\
-TQM862M_100MHz_config	\
-TQM866M_config:		unconfig
+TQM862M_100MHz_config:	unconfig
 	@ >include/config.h
 	@[ -z "$(findstring _66MHz,$@)" ] || \
 		{ echo "#define CONFIG_66MHz"		>>include/config.h ; \
@@ -497,13 +403,9 @@ TQM866M_config:		unconfig
 		{ echo "#define CONFIG_100MHz"		>>include/config.h ; \
 		  echo "... with 100MHz system clock" ; \
 		}
-	@[ -z "$(findstring _133MHz,$@)" ] || \
-		{ echo "#define CONFIG_133MHz"		>>include/config.h ; \
-		  echo "... with 133MHz system clock" ; \
-		}
 	@[ -z "$(findstring _LCD,$@)" ] || \
 		{ echo "#define CONFIG_LCD"		>>include/config.h ; \
-		  echo "#define CONFIG_NEC_NL6448BC20"	>>include/config.h ; \
+		  echo "#define CONFIG_NEC_NL6648BC20"	>>include/config.h ; \
 		  echo "... with LCD display" ; \
 		}
 	@./mkconfig -a $(call xtract_8xx,$@) ppc mpc8xx tqm8xx
@@ -518,15 +420,9 @@ v37_config:	unconfig
 	@echo "#define CONFIG_SHARP_LQ084V1DG21" >>include/config.h
 	@./mkconfig $(@:_config=) ppc mpc8xx v37
 
-wtk_config:	unconfig
-	@echo "#define CONFIG_LCD" >include/config.h
-	@echo "#define CONFIG_SHARP_LQ065T9DR51U" >>include/config.h
-	@./mkconfig -a TQM823L ppc mpc8xx tqm8xx
-
 #########################################################################
 ## PPC4xx Systems
 #########################################################################
-xtract_4xx = $(subst _MODEL_BA,,$(subst _MODEL_ME,,$(subst _MODEL_HI,,$(subst _config,,$1))))
 
 ADCIOP_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx adciop esd
@@ -561,9 +457,6 @@ CRAYL1_config:unconfig
 DASA_SIM_config: unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx dasa_sim esd
 
-DP405_config:	unconfig
-	@./mkconfig $(@:_config=) ppc ppc4xx dp405 esd
-
 DU405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx du405 esd
 
@@ -576,9 +469,6 @@ ERIC_config:unconfig
 EXBITGEN_config:unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx exbitgen
 
-HUB405_config:	unconfig
-	@./mkconfig $(@:_config=) ppc ppc4xx hub405 esd
-
 MIP405_config:unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx mip405 mpl
 
@@ -600,34 +490,9 @@ PCI405_config:	unconfig
 PIP405_config:unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx pip405 mpl
 
-PLU405_config:	unconfig
-	@./mkconfig $(@:_config=) ppc ppc4xx plu405 esd
-
 PMC405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx pmc405 esd
 
-PPChameleonEVB_MODEL_BA_config	\
-PPChameleonEVB_MODEL_ME_config	\
-PPChameleonEVB_MODEL_HI_config	\
-PPChameleonEVB_config:	unconfig
-	@ >include/config.h
-	@[ -z "$(findstring _MODEL_BA,$@)" ] || \
-		{ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 0" >>include/config.h ; \
-		  echo "... BASIC model" ; \
-		}
-	@[ -z "$(findstring _MODEL_ME,$@)" ] || \
-		{ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 1" >>include/config.h ; \
-		  echo "... MEDIUM model" ; \
-		}
-	@[ -z "$(findstring _MODEL_HI,$@)" ] || \
-		{ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 2" >>include/config.h ; \
-		  echo "... HIGH-END model" ; \
-		}
-	@./mkconfig -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave
-
-VOH405_config:	unconfig
-	@./mkconfig $(@:_config=) ppc ppc4xx voh405 esd
-
 W7OLMC_config	\
 W7OLMG_config: unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx w7o
@@ -635,9 +500,6 @@ W7OLMG_config: unconfig
 WALNUT405_config:unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx walnut405
 
-XPEDITE1K_config:unconfig
-	@./mkconfig $(@:_config=) ppc ppc4xx xpedite1k
-
 #########################################################################
 ## MPC824x Systems
 #########################################################################
@@ -671,9 +533,6 @@ MOUSSE_config: unconfig
 MUSENKI_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x musenki
 
-MVBLUE_config:	unconfig
-	@./mkconfig $(@:_config=) ppc mpc824x mvblue
-
 OXC_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x oxc
 
@@ -696,9 +555,6 @@ utx8245_config: unconfig
 ## MPC8260 Systems
 #########################################################################
 
-atc_config:	unconfig
-	@./mkconfig $(@:_config=) ppc mpc8260 atc
-
 cogent_mpc8260_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 cogent
 
@@ -778,75 +634,36 @@ sbc8260_config:	unconfig
 SCM_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 SCM siemens
 
-TQM8255_AA_config \
-TQM8260_AA_config \
-TQM8260_AB_config \
-TQM8260_AC_config \
-TQM8260_AD_config \
-TQM8260_AE_config \
-TQM8260_AF_config \
-TQM8260_AG_config \
-TQM8260_AH_config \
-TQM8265_AA_config:  unconfig
-	@case "$@" in \
-	TQM8255_AA_config) CTYPE=MPC8255; CFREQ=300; CACHE=no;  BMODE=8260;;  \
-	TQM8260_AA_config) CTYPE=MPC8260; CFREQ=200; CACHE=no;  BMODE=8260;; \
-	TQM8260_AB_config) CTYPE=MPC8260; CFREQ=200; CACHE=yes; BMODE=60x;;  \
-	TQM8260_AC_config) CTYPE=MPC8260; CFREQ=200; CACHE=yes; BMODE=60x;;  \
-	TQM8260_AD_config) CTYPE=MPC8260; CFREQ=300; CACHE=no;  BMODE=60x;;  \
-	TQM8260_AE_config) CTYPE=MPC8260; CFREQ=266; CACHE=no;  BMODE=8260;; \
-	TQM8260_AF_config) CTYPE=MPC8260; CFREQ=300; CACHE=no;  BMODE=60x;;  \
-	TQM8260_AG_config) CTYPE=MPC8260; CFREQ=300; CACHE=no;  BMODE=8260;; \
-	TQM8260_AH_config) CTYPE=MPC8260; CFREQ=300; CACHE=yes; BMODE=60x;;  \
-	TQM8265_AA_config) CTYPE=MPC8265; CFREQ=300; CACHE=no;  BMODE=60x;;  \
-	esac; \
-	>include/config.h ; \
-	if [ "$${CTYPE}" != "MPC8260" ] ; then \
-		echo "#define CONFIG_$${CTYPE}"	>>include/config.h ; \
-	fi; \
-	echo "#define CONFIG_$${CFREQ}MHz"	>>include/config.h ; \
-	echo "... with $${CFREQ}MHz system clock" ; \
-	if [ "$${CACHE}" == "yes" ] ; then \
+TQM8255_config	\
+TQM8260_config	\
+TQM8260_L2_config	\
+TQM8255_266MHz_config	\
+TQM8260_266MHz_config	\
+TQM8260_L2_266MHz_config \
+TQM8255_300MHz_config	\
+TQM8260_300MHz_config:	unconfig
+	@ >include/config.h
+	@if [ "$(findstring _L2_,$@)" ] ; then \
 		echo "#define CONFIG_L2_CACHE"	>>include/config.h ; \
-		echo "... with L2 Cache support" ; \
+		echo "... with L2 Cache support (60x Bus Mode)" ; \
 	else \
 		echo "#undef CONFIG_L2_CACHE"	>>include/config.h ; \
 		echo "... without L2 Cache support" ; \
-	fi; \
-	if [ "$${BMODE}" == "60x" ] ; then \
-		echo "#define CONFIG_BUSMODE_60x" >>include/config.h ; \
-		echo "... with 60x Bus Mode" ; \
-	else \
-		echo "#undef CONFIG_BUSMODE_60x"  >>include/config.h ; \
-		echo "... without 60x Bus Mode" ; \
 	fi
+	@[ -z "$(findstring _266MHz,$@)" ] || \
+		{ echo "#define CONFIG_266MHz"	>>include/config.h ; \
+		  echo "... with 266MHz system clock" ; \
+		}
+	@[ -z "$(findstring _300MHz,$@)" ] || \
+		{ echo "#define CONFIG_300MHz"	>>include/config.h ; \
+		  echo "... with 300MHz system clock" ; \
+		}
+	@[ -z "$(findstring TQM8255_,$@)" ] || \
+		{ echo "#define CONFIG_MPC8255"	>>include/config.h ; }
 	@./mkconfig -a TQM8260 ppc mpc8260 tqm8260
 
-ZPC1900_config: unconfig
-	@./mkconfig $(@:_config=) ppc mpc8260 zpc1900
-
-#========================================================================
-# M68K
-#========================================================================
-#########################################################################
-## Coldfire
-#########################################################################
-
-M5272C3_config :		unconfig
-	@./mkconfig $(@:_config=) m68k coldfire m5272c3
-
-M5282EVB_config :		unconfig
-	@./mkconfig $(@:_config=) m68k coldfire m5282evb
-
-#########################################################################
-## MPC85xx Systems
-#########################################################################
-
-MPC8540ADS_config:      unconfig
-	@./mkconfig $(@:_config=) ppc mpc85xx mpc8540ads
-
-MPC8560ADS_config:      unconfig
-	@./mkconfig $(@:_config=) ppc mpc85xx mpc8560ads
+atc_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc8260 atc
 
 #########################################################################
 ## 74xx/7xx Systems
@@ -855,34 +672,22 @@ MPC8560ADS_config:      unconfig
 AmigaOneG3SE_config:	unconfig
 	@./mkconfig $(@:_config=) ppc 74xx_7xx AmigaOneG3SE MAI
 
-BAB7xx_config: unconfig
-	@./mkconfig $(@:_config=) ppc 74xx_7xx bab7xx eltec
-
-DB64360_config:  unconfig
-	@./mkconfig DB64360 ppc 74xx_7xx db64360 Marvell
-
-DB64460_config:  unconfig
-	@./mkconfig DB64460 ppc 74xx_7xx db64460 Marvell
-
-debris_config: unconfig
-	@./mkconfig $(@:_config=) ppc mpc824x debris etin
-
-ELPPC_config: unconfig
-	@./mkconfig $(@:_config=) ppc 74xx_7xx elppc eltec
-
 EVB64260_config	\
 EVB64260_750CX_config:	unconfig
 	@./mkconfig EVB64260 ppc 74xx_7xx evb64260
 
-P3G4_config: unconfig
+ZUMA_config:	unconfig
 	@./mkconfig $(@:_config=) ppc 74xx_7xx evb64260
 
 PCIPPC2_config \
 PCIPPC6_config: unconfig
 	@./mkconfig $(@:_config=) ppc 74xx_7xx pcippc2
 
-ZUMA_config:	unconfig
-	@./mkconfig $(@:_config=) ppc 74xx_7xx evb64260
+BAB7xx_config: unconfig
+	@./mkconfig $(@:_config=) ppc 74xx_7xx bab7xx eltec
+
+ELPPC_config: unconfig
+	@./mkconfig $(@:_config=) ppc 74xx_7xx elppc eltec
 
 #========================================================================
 # ARM
@@ -904,16 +709,10 @@ shannon_config	:	unconfig
 	@./mkconfig $(@:_config=) arm sa1100 shannon
 
 #########################################################################
-## ARM92xT Systems
+## ARM920T Systems
 #########################################################################
 
-xtract_trab = $(subst _bigram,,$(subst _bigflash,,$(subst _old,,$(subst _config,,$1))))
-
-omap1510inn_config :	unconfig
-	@./mkconfig $(@:_config=) arm arm925t omap1510inn
-
-omap1610inn_config :	unconfig
-	@./mkconfig $(@:_config=) arm arm926ejs omap1610inn
+xtract_trab = $(subst _big_flash,,$(subst _config,,$1))
 
 smdk2400_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm920t smdk2400
@@ -921,28 +720,12 @@ smdk2400_config	:	unconfig
 smdk2410_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm920t smdk2410
 
-# TRAB default configuration:	8 MB Flash, 32 MB RAM
 trab_config \
-trab_bigram_config \
-trab_bigflash_config \
-trab_old_config:	unconfig
+trab_big_flash_config:	unconfig
 	@ >include/config.h
-	@[ -z "$(findstring _bigram,$@)" ] || \
-		{ echo "#define CONFIG_FLASH_8MB"  >>include/config.h ; \
-		  echo "#define CONFIG_RAM_32MB"   >>include/config.h ; \
-		  echo "... with 8 MB Flash, 32 MB RAM" ; \
-		}
-	@[ -z "$(findstring _bigflash,$@)" ] || \
-		{ echo "#define CONFIG_FLASH_16MB" >>include/config.h ; \
-		  echo "#define CONFIG_RAM_16MB"   >>include/config.h ; \
-		  echo "... with 16 MB Flash, 16 MB RAM" ; \
-		  echo "TEXT_BASE = 0x0CF40000" >board/trab/config.tmp ; \
-		}
-	@[ -z "$(findstring _old,$@)" ] || \
-		{ echo "#define CONFIG_FLASH_8MB"  >>include/config.h ; \
-		  echo "#define CONFIG_RAM_16MB"   >>include/config.h ; \
-		  echo "... with 8 MB Flash, 16 MB RAM" ; \
-		  echo "TEXT_BASE = 0x0CF40000" >board/trab/config.tmp ; \
+	@[ -z "$(findstring _big_flash,$@)" ] || \
+		{ echo "#define CONFIG_BIG_FLASH" >>include/config.h ; \
+		  echo "... with big flash support" ; \
 		}
 	@./mkconfig -a $(call xtract_trab,$@) arm arm920t trab
 
@@ -972,9 +755,6 @@ csb226_config	:	unconfig
 innokom_config	:	unconfig
 	@./mkconfig $(@:_config=) arm pxa innokom
 
-ixdp425_config	:	unconfig
-	@./mkconfig $(@:_config=) arm ixp ixdp425
-
 lubbock_config	:	unconfig
 	@./mkconfig $(@:_config=) arm pxa lubbock
 
@@ -1006,104 +786,12 @@ sc520_spunk_rel_config	:	unconfig
 ## MIPS32 4Kc
 #########################################################################
 
-xtract_incaip = $(subst _100MHz,,$(subst _133MHz,,$(subst _150MHz,,$(subst _config,,$1))))
-
-incaip_100MHz_config	\
-incaip_133MHz_config	\
-incaip_150MHz_config	\
-incaip_config: unconfig
-	@ >include/config.h
-	@[ -z "$(findstring _100MHz,$@)" ] || \
-		{ echo "#define CPU_CLOCK_RATE 100000000" >>include/config.h ; \
-		  echo "... with 100MHz system clock" ; \
-		}
-	@[ -z "$(findstring _133MHz,$@)" ] || \
-		{ echo "#define CPU_CLOCK_RATE 133000000" >>include/config.h ; \
-		  echo "... with 133MHz system clock" ; \
-		}
-	@[ -z "$(findstring _150MHz,$@)" ] || \
-		{ echo "#define CPU_CLOCK_RATE 150000000" >>include/config.h ; \
-		  echo "... with 150MHz system clock" ; \
-		}
-	@./mkconfig -a $(call xtract_incaip,$@) mips mips incaip
-
-tb0229_config: unconfig
-	@./mkconfig $(@:_config=) mips mips tb0229
-
-#########################################################################
-## MIPS64 5Kc
-#########################################################################
+incaip_config :		unconfig
+	@./mkconfig $(@:_config=) mips mips incaip
 
 purple_config :		unconfig
 	@./mkconfig $(@:_config=) mips mips purple
 
-#========================================================================
-# Nios
-#========================================================================
-#########################################################################
-## Nios32
-#########################################################################
-
-DK1C20_safe_32_config		\
-DK1C20_standard_32_config	\
-DK1C20_config:	unconfig
-	@ >include/config.h
-	@[ -z "$(findstring _safe_32,$@)" ] || \
-		{ echo "#define CONFIG_NIOS_SAFE_32 1" >>include/config.h ; \
-		  echo "... NIOS 'safe_32' configuration" ; \
-		}
-	@[ -z "$(findstring _standard_32,$@)" ] || \
-		{ echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \
-		  echo "... NIOS 'standard_32' configuration" ; \
-		}
-	@[ -z "$(findstring DK1C20_config,$@)" ] || \
-		{ echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \
-		  echo "... NIOS 'standard_32' configuration (DEFAULT)" ; \
-		}
-	@./mkconfig -a DK1C20 nios nios dk1c20 altera
-
-DK1S10_safe_32_config		\
-DK1S10_standard_32_config	\
-DK1S10_mtx_ldk_20_config	\
-DK1S10_config:	unconfig
-	@ >include/config.h
-	@[ -z "$(findstring _safe_32,$@)" ] || \
-		{ echo "#define CONFIG_NIOS_SAFE_32 1" >>include/config.h ; \
-		  echo "... NIOS 'safe_32' configuration" ; \
-		}
-	@[ -z "$(findstring _standard_32,$@)" ] || \
-		{ echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \
-		  echo "... NIOS 'standard_32' configuration" ; \
-		}
-	@[ -z "$(findstring _mtx_ldk_20,$@)" ] || \
-		{ echo "#define CONFIG_NIOS_MTX_LDK_20 1" >>include/config.h ; \
-		  echo "... NIOS 'mtx_ldk_20' configuration" ; \
-		}
-	@[ -z "$(findstring DK1S10_config,$@)" ] || \
-		{ echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \
-		  echo "... NIOS 'standard_32' configuration (DEFAULT)" ; \
-		}
-	@./mkconfig -a DK1S10 nios nios dk1s10 altera
-
-
-#########################################################################
-## MIPS32 AU1X00
-#########################################################################
-dbau1000_config		: 	unconfig
-	@ >include/config.h
-	@echo "#define CONFIG_DBAU1000 1" >>include/config.h
-	@./mkconfig -a dbau1x00 mips mips dbau1x00
-
-dbau1100_config		: 	unconfig
-	@ >include/config.h
-	@echo "#define CONFIG_DBAU1100 1" >>include/config.h
-	@./mkconfig -a dbau1x00 mips mips dbau1x00
-
-dbau1500_config		: 	unconfig
-	@ >include/config.h
-	@echo "#define CONFIG_DBAU1500 1" >>include/config.h
-	@./mkconfig -a dbau1x00 mips mips dbau1x00
-
 #########################################################################
 #########################################################################
 
@@ -1121,7 +809,6 @@ clean:
 	rm -f tools/gdb/astest tools/gdb/gdbcont tools/gdb/gdbsend
 	rm -f tools/env/fw_printenv tools/env/fw_setenv
 	rm -f board/cray/L1/bootscript.c board/cray/L1/bootscript.image
-	rm -f board/trab/trab_fkt board/*/config.tmp
 
 clobber:	clean
 	find . -type f \
@@ -1130,7 +817,7 @@ clobber:	clean
 		| xargs rm -f
 	rm -f $(OBJS) *.bak tags TAGS
 	rm -fr *.*~
-	rm -f u-boot u-boot.map $(ALL)
+	rm -f u-boot u-boot.bin u-boot.srec u-boot.map System.map
 	rm -f tools/crc32.c tools/environment.c tools/env/crc32.c
 	rm -f tools/inca-swap-bytes cpu/mpc824x/bedbug_603e.c
 	rm -f include/asm/proc include/asm/arch include/asm

board/LEOX/elpt860/elpt860.c

@@ -33,7 +33,7 @@
 /*
 ** Note 1: In this file, you have to provide the following functions:
 ** ------
-**              int             board_early_init_f(void)
+**              int             board_pre_init(void)
 **              int             checkboard(void)
 **              long int        initdram(int board_type)
 ** called from 'board_init_f()' into 'common/board.c'
@@ -53,87 +53,89 @@ static long int dram_size (long int, long int *, long int);
 
 #define	_NOT_USED_	0xFFFFFFFF
 
-const uint init_sdram_table[] = {
-	/*
-	 * Single Read. (Offset 0 in UPMA RAM)
-	 */
-	0x0FFCCC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04,
-	0xFFFFFC04,		/* last */
-	/*
-	 * SDRAM Initialization (offset 5 in UPMA RAM)
-	 *
-	 * This is no UPM entry point. The following definition uses
-	 * the remaining space to establish an initialization
-	 * sequence, which is executed by a RUN command.
-	 *
-	 */
-	0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,	/* last */
-	/*
-	 * Burst Read. (Offset 8 in UPMA RAM)
-	 */
-	0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
-	0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
-	0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
-	0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04,	/* last */
-	/*
-	 * Single Write. (Offset 18 in UPMA RAM)
-	 */
-	0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,
-	0xFFFFFC04, 0xFFFFFC04, 0x0FFFFC04, 0xFFFFFC04,	/* last */
-	/*
-	 * Burst Write. (Offset 20 in UPMA RAM)
-	 */
-	0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
-	0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
-	0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC34, 0x0FAC0C34,
-	0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05,	/* last */
+const uint init_sdram_table[] =
+{
+  /*
+   * Single Read. (Offset 0 in UPMA RAM)
+   */
+  0x0FFCCC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04,
+  0xFFFFFC04, /* last */
+  /*
+   * SDRAM Initialization (offset 5 in UPMA RAM)
+   *
+   * This is no UPM entry point. The following definition uses
+   * the remaining space to establish an initialization
+   * sequence, which is executed by a RUN command.
+   *
+   */
+  0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,  /* last */
+  /*
+   * Burst Read. (Offset 8 in UPMA RAM)
+   */
+  0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+  0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+  0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
+  0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, /* last */
+  /*
+   * Single Write. (Offset 18 in UPMA RAM)
+   */
+  0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,
+  0xFFFFFC04, 0xFFFFFC04, 0x0FFFFC04, 0xFFFFFC04, /* last */
+  /*
+   * Burst Write. (Offset 20 in UPMA RAM)
+   */
+  0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+  0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
+  0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC34, 0x0FAC0C34,
+  0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05, /* last */
 };
 
-const uint sdram_table[] = {
-	/*
-	 * Single Read. (Offset 0 in UPMA RAM)
-	 */
-	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
-	0xFF0FFC00,		/* last */
-	/*
-	 * SDRAM Initialization (offset 5 in UPMA RAM)
-	 *
-	 * This is no UPM entry point. The following definition uses
-	 * the remaining space to establish an initialization
-	 * sequence, which is executed by a RUN command.
-	 *
-	 */
-	0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC05,	/* last */
-	/*
-	 * Burst Read. (Offset 8 in UPMA RAM)
-	 */
-	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
-	0xF00FFC00, 0xF00FFC00, 0xF00FFC00, 0xFF0FFC00,
-	0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
-	0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04,	/* last */
-	/*
-	 * Single Write. (Offset 18 in UPMA RAM)
-	 */
-	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF0C00,
-	0xFF0FFC04, 0x0FFCCC04, 0xFFAFFC05,	/* last */
-	_NOT_USED_,
-	/*
-	 * Burst Write. (Offset 20 in UPMA RAM)
-	 */
-	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC00, 0x00AF0C00,
-	0xF00FFC00, 0xF00FFC00, 0xF00FFC04, 0x0FFCCC04,
-	0xFFAFFC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
-	0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04,	/* last */
-	/*
-	 * Refresh  (Offset 30 in UPMA RAM)
-	 */
-	0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
-	0xFFFFFC05, 0xFFFFFC04, 0xFFFFFC05, _NOT_USED_,
-	0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04,	/* last */
-	/*
-	 * Exception. (Offset 3c in UPMA RAM)
-	 */
-	0x0FFFFC34, 0x0FAC0C34, 0xFFFFFC05, 0xFFAFFC04,	/* last */
+const uint sdram_table[] =
+{
+  /*
+   * Single Read. (Offset 0 in UPMA RAM)
+   */
+  0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
+  0xFF0FFC00, /* last */
+  /*
+   * SDRAM Initialization (offset 5 in UPMA RAM)
+   *
+   * This is no UPM entry point. The following definition uses
+   * the remaining space to establish an initialization
+   * sequence, which is executed by a RUN command.
+   *
+   */
+  0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC05, /* last */
+  /*
+   * Burst Read. (Offset 8 in UPMA RAM)
+   */
+  0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
+  0xF00FFC00, 0xF00FFC00, 0xF00FFC00, 0xFF0FFC00,
+  0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
+  0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
+  /*
+   * Single Write. (Offset 18 in UPMA RAM)
+   */
+  0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF0C00,
+  0xFF0FFC04, 0x0FFCCC04, 0xFFAFFC05, /* last */
+  _NOT_USED_,
+  /*
+   * Burst Write. (Offset 20 in UPMA RAM)
+   */
+  0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC00, 0x00AF0C00,
+  0xF00FFC00, 0xF00FFC00, 0xF00FFC04, 0x0FFCCC04,
+  0xFFAFFC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
+  0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
+  /*
+   * Refresh  (Offset 30 in UPMA RAM)
+   */
+  0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+  0xFFFFFC05, 0xFFFFFC04, 0xFFFFFC05, _NOT_USED_,
+  0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
+  /*
+   * Exception. (Offset 3c in UPMA RAM)
+   */
+  0x0FFFFC34, 0x0FAC0C34, 0xFFFFFC05, 0xFFAFFC04, /* last */
 };
 
 /* ------------------------------------------------------------------------- */
@@ -145,18 +147,19 @@ const uint sdram_table[] = {
 /*
  * Very early board init code (fpga boot, etc.)
  */
-int board_early_init_f (void)
+int
+board_pre_init (void)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+  volatile immap_t *immr = (immap_t *) CFG_IMMR;
 
-	/*
-	 * Light up the red led on ELPT860 pcb (DS1) (PCDAT)
-	 */
-	immr->im_ioport.iop_pcdat &= ~CFG_DS1;	/* PCDAT (DS1 = 0)                */
-	immr->im_ioport.iop_pcpar &= ~CFG_DS1;	/* PCPAR (0=general purpose I/O)  */
-	immr->im_ioport.iop_pcdir |= CFG_DS1;	/* PCDIR (I/O: 0=input, 1=output) */
+  /*
+   * Light up the red led on ELPT860 pcb (DS1) (PCDAT)
+   */
+  immr->im_ioport.iop_pcdat &= ~CFG_DS1;   /* PCDAT (DS1 = 0)                */
+  immr->im_ioport.iop_pcpar &= ~CFG_DS1;   /* PCPAR (0=general purpose I/O)  */
+  immr->im_ioport.iop_pcdir |=  CFG_DS1;   /* PCDIR (I/O: 0=input, 1=output) */
 
-	return (0);		/* success */
+  return ( 0 );    /* success */
 }
 
 /*
@@ -167,143 +170,150 @@ int board_early_init_f (void)
  * Return 1 if no second DRAM bank, otherwise returns 0
  */
 
-int checkboard (void)
+int
+checkboard (void)
 {
-	unsigned char *s = getenv ("serial#");
+    unsigned char *s = getenv("serial#");
 
-	if (!s || strncmp (s, "ELPT860", 7))
-		printf ("### No HW ID - assuming ELPT860\n");
+    if ( !s || strncmp(s, "ELPT860", 7) )
+      printf ("### No HW ID - assuming ELPT860\n");
 
-	return (0);		/* success */
+    return ( 0 );    /* success */
 }
 
 /* ------------------------------------------------------------------------- */
 
-long int initdram (int board_type)
+long int
+initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	long int size8, size9;
-	long int size_b0 = 0;
+    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile memctl8xx_t *memctl = &immap->im_memctl;
+    long int              size8, size9;
+    long int              size_b0 = 0;
 
-	/*
-	 * This sequence initializes SDRAM chips on ELPT860 board
-	 */
-	upmconfig (UPMA, (uint *) init_sdram_table,
-		   sizeof (init_sdram_table) / sizeof (uint));
+    /*
+     * This sequence initializes SDRAM chips on ELPT860 board
+     */
+    upmconfig(UPMA, (uint *)init_sdram_table,
+	      sizeof(init_sdram_table)/sizeof(uint));
 
-	memctl->memc_mptpr = 0x0200;
-	memctl->memc_mamr = 0x18002111;
+    memctl->memc_mptpr = 0x0200;
+    memctl->memc_mamr  = 0x18002111;
 
-	memctl->memc_mar = 0x00000088;
-	memctl->memc_mcr = 0x80002000;	/* CS1: SDRAM bank 0 */
+    memctl->memc_mar   = 0x00000088;
+    memctl->memc_mcr   = 0x80002000;	/* CS1: SDRAM bank 0 */
 
-	upmconfig (UPMA, (uint *) sdram_table,
-		   sizeof (sdram_table) / sizeof (uint));
+    upmconfig(UPMA, (uint *)sdram_table,
+	      sizeof(sdram_table)/sizeof(uint));
 
-	/*
-	 * Preliminary prescaler for refresh (depends on number of
-	 * banks): This value is selected for four cycles every 62.4 us
-	 * with two SDRAM banks or four cycles every 31.2 us with one
-	 * bank. It will be adjusted after memory sizing.
-	 */
-	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+    /*
+     * Preliminary prescaler for refresh (depends on number of
+     * banks): This value is selected for four cycles every 62.4 us
+     * with two SDRAM banks or four cycles every 31.2 us with one
+     * bank. It will be adjusted after memory sizing.
+     */
+    memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
 
-	/*
-	 * The following value is used as an address (i.e. opcode) for
-	 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
-	 * the port size is 32bit the SDRAM does NOT "see" the lower two
-	 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
-	 * MICRON SDRAMs:
-	 * ->    0 00 010 0 010
-	 *       |  |   | |   +- Burst Length = 4
-	 *       |  |   | +----- Burst Type   = Sequential
-	 *       |  |   +------- CAS Latency  = 2
-	 *       |  +----------- Operating Mode = Standard
-	 *       +-------------- Write Burst Mode = Programmed Burst Length
-	 */
-	memctl->memc_mar = 0x00000088;
+    /*
+     * The following value is used as an address (i.e. opcode) for
+     * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
+     * the port size is 32bit the SDRAM does NOT "see" the lower two
+     * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
+     * MICRON SDRAMs:
+     * ->    0 00 010 0 010
+     *       |  |   | |   +- Burst Length = 4
+     *       |  |   | +----- Burst Type   = Sequential
+     *       |  |   +------- CAS Latency  = 2
+     *       |  +----------- Operating Mode = Standard
+     *       +-------------- Write Burst Mode = Programmed Burst Length
+     */
+    memctl->memc_mar   = 0x00000088;
 
-	/*
-	 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
-	 * preliminary addresses - these have to be modified after the
-	 * SDRAM size has been determined.
-	 */
-	memctl->memc_or1 = CFG_OR1_PRELIM;
-	memctl->memc_br1 = CFG_BR1_PRELIM;
+    /*
+     * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
+     * preliminary addresses - these have to be modified after the
+     * SDRAM size has been determined.
+     */
+    memctl->memc_or1   = CFG_OR1_PRELIM;
+    memctl->memc_br1   = CFG_BR1_PRELIM;
 
-	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+    memctl->memc_mamr  = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
 
-	udelay (200);
+    udelay (200);
 
-	/* perform SDRAM initializsation sequence */
+    /* perform SDRAM initializsation sequence */
 
-	memctl->memc_mcr = 0x80002105;	/* CS1: SDRAM bank 0 */
-	udelay (1);
-	memctl->memc_mcr = 0x80002230;	/* CS1: SDRAM bank 0 - execute twice */
-	udelay (1);
+    memctl->memc_mcr   = 0x80002105;	/* CS1: SDRAM bank 0 */
+    udelay (1);
+    memctl->memc_mcr   = 0x80002230;	/* CS1: SDRAM bank 0 - execute twice */
+    udelay (1);
 
-	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+    memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
 
+    udelay (1000);
+
+    /*
+     * Check Bank 0 Memory Size for re-configuration
+     *
+     * try 8 column mode
+     */
+    size8 = dram_size (CFG_MAMR_8COL,
+		       (ulong *) SDRAM_BASE1_PRELIM,
+		       SDRAM_MAX_SIZE);
+
+    udelay (1000);
+
+    /*
+     * try 9 column mode
+     */
+    size9 = dram_size (CFG_MAMR_9COL,
+		       (ulong *) SDRAM_BASE1_PRELIM,
+		       SDRAM_MAX_SIZE);
+
+    if ( size8 < size9 )    /* leave configuration at 9 columns	*/
+      {
+	size_b0 = size9;
+	/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
+      }
+    else                  /* back to 8 columns			*/
+      {
+	size_b0 = size8;
+	memctl->memc_mamr = CFG_MAMR_8COL;
+	udelay (500);
+	/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
+      }
+
+    udelay (1000);
+
+    /*
+     * Adjust refresh rate depending on SDRAM type, both banks
+     * For types > 128 MBit leave it at the current (fast) rate
+     */
+    if ( size_b0 < 0x02000000 )
+      {
+	/* reduce to 15.6 us (62.4 us / quad) */
+	memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
 	udelay (1000);
+      }
 
-	/*
-	 * Check Bank 0 Memory Size for re-configuration
-	 *
-	 * try 8 column mode
-	 */
-	size8 = dram_size (CFG_MAMR_8COL,
-			   (ulong *) SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
+    /*
+     * Final mapping: map bigger bank first
+     */
+    memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+    memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 
-	udelay (1000);
+    {
+      unsigned long reg;
 
-	/*
-	 * try 9 column mode
-	 */
-	size9 = dram_size (CFG_MAMR_9COL,
-			   (ulong *) SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
+      /* adjust refresh rate depending on SDRAM type, one bank */
+      reg = memctl->memc_mptpr;
+      reg >>= 1;	/* reduce to CFG_MPTPR_1BK_8K / _4K */
+      memctl->memc_mptpr = reg;
+    }
 
-	if (size8 < size9) {	/* leave configuration at 9 columns       */
-		size_b0 = size9;
-		/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
-	} else {		/* back to 8 columns                      */
+    udelay(10000);
 
-		size_b0 = size8;
-		memctl->memc_mamr = CFG_MAMR_8COL;
-		udelay (500);
-		/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
-	}
-
-	udelay (1000);
-
-	/*
-	 * Adjust refresh rate depending on SDRAM type, both banks
-	 * For types > 128 MBit leave it at the current (fast) rate
-	 */
-	if (size_b0 < 0x02000000) {
-		/* reduce to 15.6 us (62.4 us / quad) */
-		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
-		udelay (1000);
-	}
-
-	/*
-	 * Final mapping: map bigger bank first
-	 */
-	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
-	memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-
-	{
-		unsigned long reg;
-
-		/* adjust refresh rate depending on SDRAM type, one bank */
-		reg = memctl->memc_mptpr;
-		reg >>= 1;	/* reduce to CFG_MPTPR_1BK_8K / _4K */
-		memctl->memc_mptpr = reg;
-	}
-
-	udelay (10000);
-
-	return (size_b0);
+    return (size_b0);
 }
 
 /* ------------------------------------------------------------------------- */
@@ -317,14 +327,54 @@ long int initdram (int board_type)
  */
 
 static long int
-dram_size (long int mamr_value, long int *base, long int maxsize)
+dram_size (long int   mamr_value,
+	   long int  *base,
+	   long int   maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
+  volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+  volatile memctl8xx_t *memctl = &immap->im_memctl;
+  volatile long int    *addr;
+  ulong                 cnt, val;
+  ulong                 save[32];    /* to make test non-destructive */
+  unsigned char         i = 0;
 
-	memctl->memc_mamr = mamr_value;
+  memctl->memc_mamr = mamr_value;
 
-	return (get_ram_size (base, maxsize));
+  for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1)
+    {
+      addr = base + cnt;    /* pointer arith! */
+
+      save[i++] = *addr;
+      *addr     = ~cnt;
+    }
+
+  /* write 0 to base address */
+  addr    = base;
+  save[i] = *addr;
+  *addr   = 0;
+
+  /* check at base address */
+  if ( (val = *addr) != 0 )
+    {
+      *addr = save[i];
+
+      return (0);
+    }
+
+  for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1)
+    {
+      addr = base + cnt;    /* pointer arith! */
+
+      val   = *addr;
+      *addr = save[--i];
+
+      if ( val != (~cnt) )
+	{
+	  return (cnt * sizeof(long));
+	}
+    }
+
+  return (maxsize);
 }
 
 /* ------------------------------------------------------------------------- */
@@ -334,15 +384,16 @@ dram_size (long int mamr_value, long int *base, long int maxsize)
 
 #define CFG_LBKs    (CFG_PA2 | CFG_PA1)
 
-void reset_phy (void)
+void
+reset_phy (void)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+  volatile immap_t *immr = (immap_t *) CFG_IMMR;
 
-	/*
-	 * Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect
-	 *                                          and no AUI loopback
-	 */
-	immr->im_ioport.iop_padat &= ~CFG_LBKs;	/* PADAT (LBK eth 1&2 = 0)        */
-	immr->im_ioport.iop_papar &= ~CFG_LBKs;	/* PAPAR (0=general purpose I/O)  */
-	immr->im_ioport.iop_padir |= CFG_LBKs;	/* PADIR (I/O: 0=input, 1=output) */
+  /*
+   * Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect
+   *                                          and no AUI loopback
+   */
+  immr->im_ioport.iop_padat &= ~CFG_LBKs;  /* PADAT (LBK eth 1&2 = 0)        */
+  immr->im_ioport.iop_papar &= ~CFG_LBKs;  /* PAPAR (0=general purpose I/O)  */
+  immr->im_ioport.iop_padir |=  CFG_LBKs;  /* PADIR (I/O: 0=input, 1=output) */
 }

board/MAI/AmigaOneG3SE/articiaS.c

@@ -675,7 +675,7 @@ static __inline__ void set_msr (unsigned long msr)
 	asm volatile ("mtmsr %0"::"r" (msr));
 }
 
-int board_early_init_f (void)
+int board_pre_init (void)
 {
 	unsigned char c_value = 0;
 	unsigned long msr;

board/MAI/AmigaOneG3SE/cmd_boota.c

@@ -121,8 +121,8 @@ int do_boota (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	return 0;
 }
 #if defined(CONFIG_AMIGAONEG3SE) && (CONFIG_COMMANDS & CFG_CMD_BSP)
-U_BOOT_CMD(
-	boota,   3,      1,      do_boota,
+cmd_tbl_t U_BOOT_CMD(BOOTA) = MK_CMD_ENTRY(
+	"boota",   3,      1,      do_boota,
 	"boota   - boot an Amiga kernel\n",
 	"address disk"
 );

board/MAI/bios_emulator/scitech/src/x86emu/makefile.cross

@@ -63,7 +63,7 @@ $(TARGETDEBUGLIB): $(DEBUGOBJS)
 	$(AR) rv $(TARGETDEBUGLIB) $(DEBUGOBJS)
 
 INCS   = -I. -Ix86emu -I../../include
-CFLAGS = -D__DRIVER__ -DFORCE_POST -D_CEXPORT= -DNO_LONG_LONG -Dprintk=printf -fsigned-char  -fomit-frame-pointer -fPIC -ffixed-r14 -meabi
+CFLAGS = -D__DRIVER__ -DFORCE_POST -D_CEXPORT= -DNO_LONG_LONG -Dprintk=printf -fsigned-char  -fomit-frame-pointer -mrelocatable -ffixed-r14 -meabi -mrelocatable -ffixed-r14 -meabi
 CDEBUGFLAGS = -DDEBUG
 
 .c.o:

board/MAI/bios_emulator/scitech/src/x86emu/makefile.uboot

@@ -61,7 +61,7 @@ $(TARGETDEBUGLIB): $(DEBUGOBJS)
 	$(AR) rv $(TARGETDEBUGLIB) $(DEBUGOBJS)
 
 INCS   = -I. -Ix86emu -I../../include
-CFLAGS = -D__DRIVER__ -DFORCE_POST -D_CEXPORT= -DNO_LONG_LONG -Dprintk=printf -fsigned-char  -fomit-frame-pointer -fPIC -ffixed-r14 -meabi
+CFLAGS = -D__DRIVER__ -DFORCE_POST -D_CEXPORT= -DNO_LONG_LONG -Dprintk=printf -fsigned-char  -fomit-frame-pointer -mrelocatable -ffixed-r14 -meabi -mrelocatable -ffixed-r14 -meabi
 CDEBUGFLAGS = -DDEBUG
 
 .c.o:

board/MAI/menu/cmd_menu.c

@@ -8,8 +8,8 @@ int do_menu( cmd_tbl_t *cmdtp, /*bd_t *bd,*/ int flag, int argc, char *argv[] )
 }
 
 #if defined(CONFIG_AMIGAONEG3SE) && (CONFIG_COMMANDS & CFG_CMD_BSP)
-U_BOOT_CMD(
-	menu,   1,      1,      do_menu,
+cmd_tbl_t U_BOOT_CMD(MENU) = MK_CMD_ENTRY(
+	"menu",   1,      1,      do_menu,
 	"menu    - display BIOS setup menu\n",
 	""
 );

board/Marvell/common/bootseq.txt

@@ -1,94 +0,0 @@
-(cpu/mpc7xxx/start.S)
-
-start:
-    b boot_cold
-
-start_warm:
-    b boot_warm
-
-
-boot_cold:
-boot_warm:
-    clear bats
-    init l2 (if enabled)
-    init altivec (if enabled)
-    invalidate l2 (if enabled)
-    setup bats (from defines in config_EVB)
-    enable_addr_trans: (if MMU enabled)
-	enable MSR_IR and MSR_DR
-    jump to in_flash
-
-in_flash:
-    enable l1 dcache
-    gal_low_init: (board/evb64260/sdram_init.S)
-	config SDRAM (CFG, TIMING, DECODE)
-	init scratch regs (810 + 814)
-
-	detect DIMM0 (bank 0 only)
-	config SDRAM_PARA0 to 256/512Mbit
-	bl sdram_op_mode
-	detect bank0 width
-	    write scratch reg 810
-	config SDRAM_PARA0 with results
-	config SDRAM_PARA1 with results
-
-	detect DIMM1 (bank 2 only)
-	config SDRAM_PARA2 to 256/512Mbit
-	detect bank2 width
-	    write scratch reg 814
-	config SDRAM_PARA2 with results
-	config SDRAM_PARA3 with results
-
-	setup device bus timings/width
-	setup boot device timings/width
-
-	setup CPU_CONF (0x0)
-	setup cpu master control register 0x160
-	setup PCI0 TIMEOUT
-	setup PCI1 TIMEOUT
-	setup PCI0 BAR
-	setup PCI1 BAR
-
-	setup MPP control 0-3
-	setup GPP level control
-	setup Serial ports multiplex
-
-    setup stack pointer (r1)
-    setup GOT
-    call cpu_init_f
-    	debug leds
-    board_init_f: (common/board.c)
-	board_early_init_f:
-	    remap gt regs?
-	    map PCI mem/io
-	    map device space
-	    clear out interupts
-	init_timebase
-	env_init
-	serial_init
-	console_init_f
-	display_options
-	initdram: (board/evb64260/evb64260.c)
-	    detect memory
-	    for each bank:
-		dram_size()
-		setup PCI slave memory mappings
-		setup SCS
-   	setup monitor
-	alloc board info struct
-	init bd struct
-	relocate_code: (cpu/mpc7xxx/start.S)
-	    copy,got,clearbss
-	    board_init_r(bd, dest_addr) (common/board.c)
-		setup bd function pointers
-		trap_init
-		flash_init: (board/evb64260/flash.c)
-		setup bd flash info
-		cpu_init_r: (cpu/mpc7xxx/cpu_init.c)
-		    nothing
-		mem_malloc_init
-		malloc_bin_reloc
-		spi_init (r or f)??? (CFG_ENV_IS_IN_EEPROM)
-		env_relocated
-		misc_init_r(bd): (board/evb64260/evb64260.c)
-		    mpsc_init2

board/Marvell/common/ecctest.c

@@ -1,133 +0,0 @@
-indent: Standard input:49: Warning:old style assignment ambiguity in "=*".  Assuming "= *"
-
-/*
- * (C) Copyright 2001
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifdef ECC_TEST
-static inline void ecc_off (void)
-{
-	*(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) &= ~0x00200000;
-}
-
-static inline void ecc_on (void)
-{
-	*(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) |= 0x00200000;
-}
-
-static int putshex (const char *buf, int len)
-{
-	int i;
-
-	for (i = 0; i < len; i++) {
-		printf ("%02x", buf[i]);
-	}
-	return 0;
-}
-
-static int char_memcpy (void *d, const void *s, int len)
-{
-	int i;
-	char *cd = d;
-	const char *cs = s;
-
-	for (i = 0; i < len; i++) {
-		*(cd++) = *(cs++);
-	}
-	return 0;
-}
-
-static int memory_test (char *buf)
-{
-	const char src[][16] = {
-		{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-		{0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-		 0x01, 0x01, 0x01, 0x01, 0x01, 0x01},
-		{0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
-		 0x02, 0x02, 0x02, 0x02, 0x02, 0x02},
-		{0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04,
-		 0x04, 0x04, 0x04, 0x04, 0x04, 0x04},
-		{0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
-		 0x08, 0x08, 0x08, 0x08, 0x08, 0x08},
-		{0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
-		 0x10, 0x10, 0x10, 0x10, 0x10, 0x10},
-		{0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-		 0x20, 0x20, 0x20, 0x20, 0x20, 0x20},
-		{0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
-		 0x40, 0x40, 0x40, 0x40, 0x40, 0x40},
-		{0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-		 0x80, 0x80, 0x80, 0x80, 0x80, 0x80},
-		{0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55,
-		 0x55, 0x55, 0x55, 0x55, 0x55, 0x55},
-		{0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
-		 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa},
-		{0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-	};
-	const int foo[] = { 0 };
-	int i, j, a;
-
-	printf ("\ntest @ %d %p\n", foo[0], buf);
-	for (i = 0; i < 12; i++) {
-		for (a = 0; a < 8; a++) {
-			const char *s = src[i] + a;
-			int align = (unsigned) (s) & 0x7;
-
-			/* ecc_off(); */
-			memcpy (buf, s, 8);
-			/* ecc_on(); */
-			putshex (s, 8);
-			if (memcmp (buf, s, 8)) {
-				putc ('\n');
-				putshex (buf, 8);
-				printf (" [FAIL] (%p) align=%d\n", s, align);
-				for (j = 0; j < 8; j++) {
-					s[j] == buf[j] ? puts ("  ") :
-						printf ("%02x",
-							(s[j]) ^ (buf[j]));
-				}
-				putc ('\n');
-			} else {
-				printf (" [PASS] (%p) align=%d\n", s, align);
-			}
-			/* ecc_off(); */
-			char_memcpy (buf, s, 8);
-			/* ecc_on(); */
-			putshex (s, 8);
-			if (memcmp (buf, s, 8)) {
-				putc ('\n');
-				putshex (buf, 8);
-				printf (" [FAIL] (%p) align=%d\n", s, align);
-				for (j = 0; j < 8; j++) {
-					s[j] == buf[j] ? puts ("  ") :
-						printf ("%02x",
-							(s[j]) ^ (buf[j]));
-				}
-				putc ('\n');
-			} else {
-				printf (" [PASS] (%p) align=%d\n", s, align);
-			}
-		}
-	}
-
-	return 0;
-}
-#endif

board/Marvell/common/i2c.c

@@ -1,532 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Hacked for the DB64360 board by Ingo.Assmus@keymile.com
- * extra improvments by Brain Waite
- */
-#include <common.h>
-#include <mpc8xx.h>
-#include <malloc.h>
-#include "../include/mv_gen_reg.h"
-#include "../include/core.h"
-
-#define MAX_I2C_RETRYS	    10
-#define I2C_DELAY	    1000	/* Should be at least the # of MHz of Tclk */
-#undef	DEBUG_I2C
-/*#define DEBUG_I2C*/
-
-#ifdef DEBUG_I2C
-#define DP(x) x
-#else
-#define DP(x)
-#endif
-
-/* Assuming that there is only one master on the bus (us) */
-
-static void i2c_init (int speed, int slaveaddr)
-{
-	unsigned int n, m, freq, margin, power;
-	unsigned int actualN = 0, actualM = 0;
-	unsigned int control, status;
-	unsigned int minMargin = 0xffffffff;
-	unsigned int tclk = CFG_TCLK;
-	unsigned int i2cFreq = speed;	/* 100000 max. Fast mode not supported */
-
-	DP (puts ("i2c_init\n"));
-/* gtI2cMasterInit */
-	for (n = 0; n < 8; n++) {
-		for (m = 0; m < 16; m++) {
-			power = 2 << n;	/* power = 2^(n+1) */
-			freq = tclk / (10 * (m + 1) * power);
-			if (i2cFreq > freq)
-				margin = i2cFreq - freq;
-			else
-				margin = freq - i2cFreq;
-			if (margin < minMargin) {
-				minMargin = margin;
-				actualN = n;
-				actualM = m;
-			}
-		}
-	}
-
-	DP (puts ("setup i2c bus\n"));
-
-	/* Setup bus */
-/* gtI2cReset */
-	GT_REG_WRITE (I2C_SOFT_RESET, 0);
-
-	DP (puts ("udelay...\n"));
-
-	udelay (I2C_DELAY);
-
-	DP (puts ("set baudrate\n"));
-
-	GT_REG_WRITE (I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN);
-	GT_REG_WRITE (I2C_CONTROL, (0x1 << 2) | (0x1 << 6));
-
-	udelay (I2C_DELAY * 10);
-
-	DP (puts ("read control, baudrate\n"));
-
-	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-	GT_REG_READ (I2C_CONTROL, &control);
-}
-
-static uchar i2c_start (void)
-{				/* DB64360 checked -> ok */
-	unsigned int control, status;
-	int count = 0;
-
-	DP (puts ("i2c_start\n"));
-
-	/* Set the start bit */
-
-/* gtI2cGenerateStartBit() */
-
-	GT_REG_READ (I2C_CONTROL, &control);
-	control |= (0x1 << 5);	/* generate the I2C_START_BIT */
-	GT_REG_WRITE (I2C_CONTROL, control);
-
-	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-
-	count = 0;
-	while ((status & 0xff) != 0x08) {
-		udelay (I2C_DELAY);
-		if (count > 20) {
-			GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
-			return (status);
-		}
-		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-		count++;
-	}
-
-	return (0);
-}
-
-static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit)
-{
-	unsigned int status, data, bits = 7;
-	int count = 0;
-
-	DP (puts ("i2c_select_device\n"));
-
-	/* Output slave address */
-
-	if (ten_bit) {
-		bits = 10;
-	}
-
-	data = (dev_addr << 1);
-	/* set the read bit */
-	data |= read;
-	GT_REG_WRITE (I2C_DATA, data);
-	/* assert the address */
-	RESET_REG_BITS (I2C_CONTROL, BIT3);
-
-	udelay (I2C_DELAY);
-
-	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-	count = 0;
-	while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) {
-		udelay (I2C_DELAY);
-		if (count > 20) {
-			GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
-			return (status);
-		}
-		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-		count++;
-	}
-
-	if (bits == 10) {
-		printf ("10 bit I2C addressing not yet implemented\n");
-		return (0xff);
-	}
-
-	return (0);
-}
-
-static uchar i2c_get_data (uchar * return_data, int len)
-{
-
-	unsigned int data, status;
-	int count = 0;
-
-	DP (puts ("i2c_get_data\n"));
-
-	while (len) {
-
-		/* Get and return the data */
-
-		RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
-
-		udelay (I2C_DELAY * 5);
-
-		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-		count++;
-		while ((status & 0xff) != 0x50) {
-			udelay (I2C_DELAY);
-			if (count > 2) {
-				GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
-				return 0;
-			}
-			GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-			count++;
-		}
-		GT_REG_READ (I2C_DATA, &data);
-		len--;
-		*return_data = (uchar) data;
-		return_data++;
-	}
-	RESET_REG_BITS (I2C_CONTROL, BIT2 | BIT3);
-	while ((status & 0xff) != 0x58) {
-		udelay (I2C_DELAY);
-		if (count > 200) {
-			GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
-			return (status);
-		}
-		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-		count++;
-	}
-	GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/* stop */
-
-	return (0);
-}
-
-static uchar i2c_write_data (unsigned int *data, int len)
-{
-	unsigned int status;
-	int count = 0;
-	unsigned int temp;
-	unsigned int *temp_ptr = data;
-
-	DP (puts ("i2c_write_data\n"));
-
-	while (len) {
-		temp = (unsigned int) (*temp_ptr);
-		GT_REG_WRITE (I2C_DATA, temp);
-		RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
-
-		udelay (I2C_DELAY);
-
-		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-		count++;
-		while ((status & 0xff) != 0x28) {
-			udelay (I2C_DELAY);
-			if (count > 20) {
-				GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
-				return (status);
-			}
-			GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-			count++;
-		}
-		len--;
-		temp_ptr++;
-	}
-/* 11-14-2002 Paul Marchese */
-/* Can't have the write issuing a stop command */
-/* it's wrong to have a stop bit in read stream or write stream */
-/* since we don't know if it's really the end of the command */
-/* or whether we have just send the device address + offset */
-/* we will push issuing the stop command off to the original */
-/* calling function */
-	/* set the interrupt bit in the control register */
-	GT_REG_WRITE (I2C_CONTROL, (0x1 << 3));
-	udelay (I2C_DELAY * 10);
-	return (0);
-}
-
-/* 11-14-2002 Paul Marchese */
-/* created this function to get the i2c_write() */
-/* function working properly. */
-/* function to write bytes out on the i2c bus */
-/* this is identical to the function i2c_write_data() */
-/* except that it requires a buffer that is an */
-/* unsigned character array.  You can't use */
-/* i2c_write_data() to send an array of unsigned characters */
-/* since the byte of interest ends up on the wrong end of the bus */
-/* aah, the joys of big endian versus little endian! */
-/* */
-/* returns 0 = success */
-/*         anything other than zero is failure */
-static uchar i2c_write_byte (unsigned char *data, int len)
-{
-	unsigned int status;
-	int count = 0;
-	unsigned int temp;
-	unsigned char *temp_ptr = data;
-
-	DP (puts ("i2c_write_byte\n"));
-
-	while (len) {
-		/* Set and assert the data */
-		temp = *temp_ptr;
-		GT_REG_WRITE (I2C_DATA, temp);
-		RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
-
-		udelay (I2C_DELAY);
-
-		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-		count++;
-		while ((status & 0xff) != 0x28) {
-			udelay (I2C_DELAY);
-			if (count > 20) {
-				GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
-				return (status);
-			}
-			GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-			count++;
-		}
-		len--;
-		temp_ptr++;
-	}
-/* Can't have the write issuing a stop command */
-/* it's wrong to have a stop bit in read stream or write stream */
-/* since we don't know if it's really the end of the command */
-/* or whether we have just send the device address + offset */
-/* we will push issuing the stop command off to the original */
-/* calling function */
-/*	GT_REG_WRITE(I2C_CONTROL, (0x1 << 3) | (0x1 << 4));
-	GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); */
-	/* set the interrupt bit in the control register */
-	GT_REG_WRITE (I2C_CONTROL, (0x1 << 3));
-	udelay (I2C_DELAY * 10);
-
-	return (0);
-}
-
-static uchar
-i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit,
-		    int alen)
-{
-	uchar status;
-	unsigned int table[2];
-
-/* initialize the table of address offset bytes */
-/* utilized for 2 byte address offsets */
-/* NOTE: the order is high byte first! */
-	table[1] = offset & 0xff;	/* low byte */
-	table[0] = offset / 0x100;	/* high byte */
-
-	DP (puts ("i2c_set_dev_offset\n"));
-
-	status = i2c_select_device (dev_addr, 0, ten_bit);
-	if (status) {
-#ifdef DEBUG_I2C
-		printf ("Failed to select device setting offset: 0x%02x\n",
-			status);
-#endif
-		return status;
-	}
-/* check the address offset length */
-	if (alen == 0)
-		/* no address offset */
-		return (0);
-	else if (alen == 1) {
-		/* 1 byte address offset */
-		status = i2c_write_data (&offset, 1);
-		if (status) {
-#ifdef DEBUG_I2C
-			printf ("Failed to write data: 0x%02x\n", status);
-#endif
-			return status;
-		}
-	} else if (alen == 2) {
-		/* 2 bytes address offset */
-		status = i2c_write_data (table, 2);
-		if (status) {
-#ifdef DEBUG_I2C
-			printf ("Failed to write data: 0x%02x\n", status);
-#endif
-			return status;
-		}
-	} else {
-		/* address offset unknown or not supported */
-		printf ("Address length offset %d is not supported\n", alen);
-		return 1;
-	}
-	return 0;		/* sucessful completion */
-}
-
-uchar
-i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
-	  int len)
-{
-	uchar status = 0;
-	unsigned int i2cFreq = CFG_I2C_SPEED;
-
-	DP (puts ("i2c_read\n"));
-
-	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
-
-	status = i2c_start ();
-
-	if (status) {
-#ifdef DEBUG_I2C
-		printf ("Transaction start failed: 0x%02x\n", status);
-#endif
-		return status;
-	}
-
-	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
-	if (status) {
-#ifdef DEBUG_I2C
-		printf ("Failed to set slave address & offset: 0x%02x\n",
-			status);
-#endif
-		return status;
-	}
-
-	i2c_init (i2cFreq, 0);	/* set the i2c frequency again */
-
-	status = i2c_start ();
-	if (status) {
-#ifdef DEBUG_I2C
-		printf ("Transaction restart failed: 0x%02x\n", status);
-#endif
-		return status;
-	}
-
-	status = i2c_select_device (dev_addr, 1, 0);	/* send the slave address */
-	if (status) {
-#ifdef DEBUG_I2C
-		printf ("Address not acknowledged: 0x%02x\n", status);
-#endif
-		return status;
-	}
-
-	status = i2c_get_data (data, len);
-	if (status) {
-#ifdef DEBUG_I2C
-		printf ("Data not recieved: 0x%02x\n", status);
-#endif
-		return status;
-	}
-
-	return 0;
-}
-
-/* 11-14-2002 Paul Marchese */
-/* Function to set the I2C stop bit */
-void i2c_stop (void)
-{
-	GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));
-}
-
-/* 11-14-2002 Paul Marchese */
-/* I2C write function */
-/* dev_addr = device address */
-/* offset = address offset */
-/* alen = length in bytes of the address offset */
-/* data = pointer to buffer to read data into */
-/* len = # of bytes to read */
-/* */
-/* returns 0 = succesful */
-/*         anything but zero is failure */
-uchar
-i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data,
-	   int len)
-{
-	uchar status = 0;
-	unsigned int i2cFreq = CFG_I2C_SPEED;
-
-	DP (puts ("i2c_write\n"));
-
-	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
-
-	status = i2c_start ();	/* send a start bit */
-
-	if (status) {
-#ifdef DEBUG_I2C
-		printf ("Transaction start failed: 0x%02x\n", status);
-#endif
-		return status;
-	}
-
-	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
-	if (status) {
-#ifdef DEBUG_I2C
-		printf ("Failed to set slave address & offset: 0x%02x\n",
-			status);
-#endif
-		return status;
-	}
-
-
-	status = i2c_write_byte (data, len);	/* write the data */
-	if (status) {
-#ifdef DEBUG_I2C
-		printf ("Data not written: 0x%02x\n", status);
-#endif
-		return status;
-	}
-	/* issue a stop bit */
-	i2c_stop ();
-	return 0;
-}
-
-/* 11-14-2002 Paul Marchese */
-/* function to determine if an I2C device is present */
-/* chip = device address of chip to check for */
-/* */
-/* returns 0 = sucessful, the device exists */
-/*         anything other than zero is failure, no device */
-int i2c_probe (uchar chip)
-{
-
-	/* We are just looking for an <ACK> back. */
-	/* To see if the device/chip is there */
-
-#ifdef DEBUG_I2C
-	unsigned int i2c_status;
-#endif
-	uchar status = 0;
-	unsigned int i2cFreq = CFG_I2C_SPEED;
-
-	DP (puts ("i2c_probe\n"));
-
-	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
-
-	status = i2c_start ();	/* send a start bit */
-
-	if (status) {
-#ifdef DEBUG_I2C
-		printf ("Transaction start failed: 0x%02x\n", status);
-#endif
-		return (int) status;
-	}
-
-	status = i2c_set_dev_offset (chip, 0, 0, 0);	/* send the slave address + no offset */
-	if (status) {
-#ifdef DEBUG_I2C
-		printf ("Failed to set slave address: 0x%02x\n", status);
-#endif
-		return (int) status;
-	}
-#ifdef DEBUG_I2C
-	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &i2c_status);
-	printf ("address %#x returned %#x\n", chip, i2c_status);
-#endif
-	/* issue a stop bit */
-	i2c_stop ();
-	return 0;		/* successful completion */
-}

board/Marvell/common/intel_flash.c

@@ -1,269 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Hacked for the marvell db64360 eval board by
- * Ingo Assmus <ingo.assmus@keymile.com>
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include "../include/mv_gen_reg.h"
-#include "../include/memory.h"
-#include "intel_flash.h"
-
-
-/*-----------------------------------------------------------------------
- * Protection Flags:
- */
-#define FLAG_PROTECT_SET	0x01
-#define FLAG_PROTECT_CLEAR	0x02
-
-static void bank_reset (flash_info_t * info, int sect)
-{
-	bank_addr_t addrw, eaddrw;
-
-	addrw = (bank_addr_t) info->start[sect];
-	eaddrw = BANK_ADDR_NEXT_WORD (addrw);
-
-	while (addrw < eaddrw) {
-#ifdef FLASH_DEBUG
-		printf ("  writing reset cmd to addr 0x%08lx\n",
-			(unsigned long) addrw);
-#endif
-		*addrw = BANK_CMD_RST;
-		addrw++;
-	}
-}
-
-static void bank_erase_init (flash_info_t * info, int sect)
-{
-	bank_addr_t addrw, saddrw, eaddrw;
-	int flag;
-
-#ifdef FLASH_DEBUG
-	printf ("0x%08x BANK_CMD_PROG\n", BANK_CMD_PROG);
-	printf ("0x%08x BANK_CMD_ERASE1\n", BANK_CMD_ERASE1);
-	printf ("0x%08x BANK_CMD_ERASE2\n", BANK_CMD_ERASE2);
-	printf ("0x%08x BANK_CMD_CLR_STAT\n", BANK_CMD_CLR_STAT);
-	printf ("0x%08x BANK_CMD_RST\n", BANK_CMD_RST);
-	printf ("0x%08x BANK_STAT_RDY\n", BANK_STAT_RDY);
-	printf ("0x%08x BANK_STAT_ERR\n", BANK_STAT_ERR);
-#endif
-
-	saddrw = (bank_addr_t) info->start[sect];
-	eaddrw = BANK_ADDR_NEXT_WORD (saddrw);
-
-#ifdef FLASH_DEBUG
-	printf ("erasing sector %d, start addr = 0x%08lx "
-		"(bank next word addr = 0x%08lx)\n", sect,
-		(unsigned long) saddrw, (unsigned long) eaddrw);
-#endif
-
-	/* Disable intrs which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	for (addrw = saddrw; addrw < eaddrw; addrw++) {
-#ifdef FLASH_DEBUG
-		printf ("  writing erase cmd to addr 0x%08lx\n",
-			(unsigned long) addrw);
-#endif
-		*addrw = BANK_CMD_ERASE1;
-		*addrw = BANK_CMD_ERASE2;
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts ();
-}
-
-static int bank_erase_poll (flash_info_t * info, int sect)
-{
-	bank_addr_t addrw, saddrw, eaddrw;
-	int sectdone, haderr;
-
-	saddrw = (bank_addr_t) info->start[sect];
-	eaddrw = BANK_ADDR_NEXT_WORD (saddrw);
-
-	sectdone = 1;
-	haderr = 0;
-
-	for (addrw = saddrw; addrw < eaddrw; addrw++) {
-		bank_word_t stat = *addrw;
-
-#ifdef FLASH_DEBUG
-		printf ("  checking status at addr "
-			"0x%08x [0x%08x]\n", (unsigned long) addrw, stat);
-#endif
-		if ((stat & BANK_STAT_RDY) != BANK_STAT_RDY)
-			sectdone = 0;
-		else if ((stat & BANK_STAT_ERR) != 0) {
-			printf (" failed on sector %d "
-				"(stat = 0x%08x) at "
-				"address 0x%p\n", sect, stat, addrw);
-			*addrw = BANK_CMD_CLR_STAT;
-			haderr = 1;
-		}
-	}
-
-	if (haderr)
-		return (-1);
-	else
-		return (sectdone);
-}
-
-int write_word_intel (bank_addr_t addr, bank_word_t value)
-{
-	bank_word_t stat;
-	ulong start;
-	int flag, retval;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	*addr = BANK_CMD_PROG;
-
-	*addr = value;
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts ();
-
-	retval = 0;
-
-	/* data polling for D7 */
-	start = get_timer (0);
-	do {
-		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
-			retval = 1;
-			goto done;
-		}
-		stat = *addr;
-	} while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY);
-
-	if ((stat & BANK_STAT_ERR) != 0) {
-		printf ("flash program failed (stat = 0x%08lx) "
-			"at address 0x%08lx\n", (ulong) stat, (ulong) addr);
-		*addr = BANK_CMD_CLR_STAT;
-		retval = 3;
-	}
-
-      done:
-	/* reset to read mode */
-	*addr = BANK_CMD_RST;
-
-	return (retval);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase_intel (flash_info_t * info, int s_first, int s_last)
-{
-	int prot, sect, haderr;
-	ulong start, now, last;
-
-#ifdef FLASH_DEBUG
-	printf ("\nflash_erase: erase %d sectors (%d to %d incl.) from\n"
-		"  Bank # %d: ", s_last - s_first + 1, s_first, s_last,
-		(info - flash_info) + 1);
-	flash_print_info (info);
-#endif
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sector%s will not be erased!\n", prot, (prot > 1 ? "s" : ""));
-	}
-
-	start = get_timer (0);
-	last = 0;
-	haderr = 0;
-
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			ulong estart;
-			int sectdone;
-
-			bank_erase_init (info, sect);
-
-			/* wait at least 80us - let's wait 1 ms */
-			udelay (1000);
-
-			estart = get_timer (start);
-
-			do {
-				now = get_timer (start);
-
-				if (now - estart > CFG_FLASH_ERASE_TOUT) {
-					printf ("Timeout (sect %d)\n", sect);
-					haderr = 1;
-					break;
-				}
-#ifndef FLASH_DEBUG
-				/* show that we're waiting */
-				if ((now - last) > 1000) {	/* every second */
-					putc ('.');
-					last = now;
-				}
-#endif
-
-				sectdone = bank_erase_poll (info, sect);
-
-				if (sectdone < 0) {
-					haderr = 1;
-					break;
-				}
-
-			} while (!sectdone);
-
-			if (haderr)
-				break;
-		}
-	}
-
-	if (haderr > 0)
-		printf (" failed\n");
-	else
-		printf (" done\n");
-
-	/* reset to read mode */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			bank_reset (info, sect);
-		}
-	}
-	return haderr;
-}

board/Marvell/common/intel_flash.h

@@ -1,186 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Hacked for the marvell db64360 eval board by
- * Ingo Assmus <ingo.assmus@keymile.com>
- */
-
-/*************** DEFINES for Intel StrataFlash FLASH chip ********************/
-
-/*
- * acceptable chips types are:
- *
- *	28F320J5, 28F640J5, 28F320J3A, 28F640J3A and 28F128J3A
- */
-
-/* register addresses, valid only following an CHIP_CMD_RD_ID command */
-#define CHIP_ADDR_REG_MAN	0x000000	/* manufacturer's id */
-#define CHIP_ADDR_REG_DEV	0x000001	/* device id */
-#define CHIP_ADDR_REG_CFGM	0x000003	/* master lock config */
-#define CHIP_ADDR_REG_CFG(b)	(((b)<<16)|2)	/* lock config for block b */
-
-/* Commands */
-#define CHIP_CMD_RST		0xFF		/* reset flash */
-#define CHIP_CMD_RD_ID		0x90		/* read the id and lock bits */
-#define CHIP_CMD_RD_QUERY	0x98		/* read device capabilities */
-#define CHIP_CMD_RD_STAT	0x70		/* read the status register */
-#define CHIP_CMD_CLR_STAT	0x50		/* clear the staus register */
-#define CHIP_CMD_WR_BUF		0xE8		/* clear the staus register */
-#define CHIP_CMD_PROG		0x40		/* program word command */
-#define CHIP_CMD_ERASE1		0x20		/* 1st word for block erase */
-#define CHIP_CMD_ERASE2		0xD0		/* 2nd word for block erase */
-#define CHIP_CMD_ERASE_SUSP	0xB0		/* suspend block erase */
-#define CHIP_CMD_LOCK		0x60		/* 1st word for all lock cmds */
-#define CHIP_CMD_SET_LOCK_BLK	0x01		/* 2nd wrd set block lock bit */
-#define CHIP_CMD_SET_LOCK_MSTR	0xF1		/* 2nd wrd set master lck bit */
-#define CHIP_CMD_CLR_LOCK_BLK	0xD0		/* 2nd wrd clear blk lck bit */
-
-/* status register bits */
-#define CHIP_STAT_DPS		0x02		/* Device Protect Status */
-#define CHIP_STAT_VPPS		0x08		/* VPP Status */
-#define CHIP_STAT_PSLBS		0x10		/* Program+Set Lock Bit Stat */
-#define CHIP_STAT_ECLBS		0x20		/* Erase+Clr Lock Bit Stat */
-#define CHIP_STAT_ESS		0x40		/* Erase Suspend Status */
-#define CHIP_STAT_RDY		0x80		/* WSM Mach Status, 1=rdy */
-
-#define CHIP_STAT_ERR		(CHIP_STAT_VPPS | CHIP_STAT_DPS | \
-				    CHIP_STAT_ECLBS | CHIP_STAT_PSLBS)
-
-/* ID and Lock Configuration */
-#define CHIP_RD_ID_LOCK		0x01		/* Bit 0 of each byte */
-#define CHIP_RD_ID_MAN		0x89		/* Manufacturer code = 0x89 */
-#define CHIP_RD_ID_DEV		CFG_FLASH_ID
-
-/* dimensions */
-#define CHIP_WIDTH		2		/* chips are in 16 bit mode */
-#define CHIP_WSHIFT		1		/* (log2 of CHIP_WIDTH) */
-#define CHIP_NBLOCKS		128
-#define CHIP_BLKSZ		(128 * 1024)	/* of 128Kbytes each */
-#define CHIP_SIZE		(CHIP_BLKSZ * CHIP_NBLOCKS)
-
-/********************** DEFINES for Hymod Flash ******************************/
-
-/*
- * The hymod board has 2 x 28F320J5 chips running in
- * 16 bit mode, for a 32 bit wide bank.
- */
-
-typedef unsigned short bank_word_t;		/* 8/16/32/64bit unsigned int */
-typedef volatile bank_word_t *bank_addr_t;
-typedef unsigned long bank_size_t;		/* want this big - >= 32 bit */
-
-#define BANK_CHIP_WIDTH		1		/* each bank is 1 chip wide */
-#define BANK_CHIP_WSHIFT	0		/* (log2 of BANK_CHIP_WIDTH) */
-
-#define BANK_WIDTH		(CHIP_WIDTH * BANK_CHIP_WIDTH)
-#define BANK_WSHIFT		(CHIP_WSHIFT + BANK_CHIP_WSHIFT)
-#define BANK_NBLOCKS		CHIP_NBLOCKS
-#define BANK_BLKSZ		(CHIP_BLKSZ * BANK_CHIP_WIDTH)
-#define BANK_SIZE		(CHIP_SIZE * BANK_CHIP_WIDTH)
-
-#define MAX_BANKS		1		/* only one bank possible */
-
-/* align bank addresses and sizes to bank word boundaries */
-#define BANK_ADDR_WORD_ALIGN(a)	((bank_addr_t)((bank_size_t)(a) \
-				    & ~(BANK_WIDTH - 1)))
-#define BANK_SIZE_WORD_ALIGN(s)	((bank_size_t)BANK_ADDR_WORD_ALIGN( \
-				    (bank_size_t)(s) + (BANK_WIDTH - 1)))
-
-/* align bank addresses and sizes to bank block boundaries */
-#define BANK_ADDR_BLK_ALIGN(a)	((bank_addr_t)((bank_size_t)(a) \
-				    & ~(BANK_BLKSZ - 1)))
-#define BANK_SIZE_BLK_ALIGN(s)	((bank_size_t)BANK_ADDR_BLK_ALIGN( \
-				    (bank_size_t)(s) + (BANK_BLKSZ - 1)))
-
-/* align bank addresses and sizes to bank boundaries */
-#define BANK_ADDR_BANK_ALIGN(a)	((bank_addr_t)((bank_size_t)(a) \
-				    & ~(BANK_SIZE - 1)))
-#define BANK_SIZE_BANK_ALIGN(s)	((bank_size_t)BANK_ADDR_BANK_ALIGN( \
-				    (bank_size_t)(s) + (BANK_SIZE - 1)))
-
-/* add an offset to a bank address */
-#define BANK_ADDR_OFFSET(a, o)	(bank_addr_t)((bank_size_t)(a) + \
-				    (bank_size_t)(o))
-
-/* get base address of bank b, given flash base address a */
-#define BANK_ADDR_BASE(a, b)	BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
-				    (bank_size_t)(b) * BANK_SIZE)
-
-/* adjust a bank address to start of next word, block or bank */
-#define BANK_ADDR_NEXT_WORD(a)	BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \
-				    BANK_WIDTH)
-#define BANK_ADDR_NEXT_BLK(a)	BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \
-				    BANK_BLKSZ)
-#define BANK_ADDR_NEXT_BANK(a)	BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
-				    BANK_SIZE)
-
-/* get bank address of chip register r given a bank base address a */
-#define BANK_ADDR_REG(a, r)	BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
-				    ((bank_size_t)(r) << BANK_WSHIFT))
-
-/* make a bank address for each chip register address */
-
-#define BANK_ADDR_REG_MAN(a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_MAN)
-#define BANK_ADDR_REG_DEV(a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_DEV)
-#define BANK_ADDR_REG_CFGM(a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_CFGM)
-#define BANK_ADDR_REG_CFG(b,a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG(b))
-
-/*
- * replicate a chip cmd/stat/rd value into each byte position within a word
- * so that multiple chips are accessed in a single word i/o operation
- *
- * this must be as wide as the bank_word_t type, and take into account the
- * chip width and bank layout
- */
-
-#define BANK_FILL_WORD(o)	((bank_word_t)(o))
-
-/* make a bank word value for each chip cmd/stat/rd value */
-
-/* Commands */
-#define BANK_CMD_RST		BANK_FILL_WORD(CHIP_CMD_RST)
-#define BANK_CMD_RD_ID		BANK_FILL_WORD(CHIP_CMD_RD_ID)
-#define BANK_CMD_RD_STAT	BANK_FILL_WORD(CHIP_CMD_RD_STAT)
-#define BANK_CMD_CLR_STAT	BANK_FILL_WORD(CHIP_CMD_CLR_STAT)
-#define BANK_CMD_ERASE1		BANK_FILL_WORD(CHIP_CMD_ERASE1)
-#define BANK_CMD_ERASE2		BANK_FILL_WORD(CHIP_CMD_ERASE2)
-#define BANK_CMD_PROG		BANK_FILL_WORD(CHIP_CMD_PROG)
-#define BANK_CMD_LOCK		BANK_FILL_WORD(CHIP_CMD_LOCK)
-#define BANK_CMD_SET_LOCK_BLK	BANK_FILL_WORD(CHIP_CMD_SET_LOCK_BLK)
-#define BANK_CMD_SET_LOCK_MSTR	BANK_FILL_WORD(CHIP_CMD_SET_LOCK_MSTR)
-#define BANK_CMD_CLR_LOCK_BLK	BANK_FILL_WORD(CHIP_CMD_CLR_LOCK_BLK)
-
-/* status register bits */
-#define BANK_STAT_DPS		BANK_FILL_WORD(CHIP_STAT_DPS)
-#define BANK_STAT_PSS		BANK_FILL_WORD(CHIP_STAT_PSS)
-#define BANK_STAT_VPPS		BANK_FILL_WORD(CHIP_STAT_VPPS)
-#define BANK_STAT_PSLBS		BANK_FILL_WORD(CHIP_STAT_PSLBS)
-#define BANK_STAT_ECLBS		BANK_FILL_WORD(CHIP_STAT_ECLBS)
-#define BANK_STAT_ESS		BANK_FILL_WORD(CHIP_STAT_ESS)
-#define BANK_STAT_RDY		BANK_FILL_WORD(CHIP_STAT_RDY)
-
-#define BANK_STAT_ERR		BANK_FILL_WORD(CHIP_STAT_ERR)
-
-/* ID and Lock Configuration */
-#define BANK_RD_ID_LOCK		BANK_FILL_WORD(CHIP_RD_ID_LOCK)
-#define BANK_RD_ID_MAN		BANK_FILL_WORD(CHIP_RD_ID_MAN)
-#define BANK_RD_ID_DEV		BANK_FILL_WORD(CHIP_RD_ID_DEV)

board/Marvell/common/misc.S

@@ -1,235 +0,0 @@
-#include <config.h>
-#include <74xx_7xx.h>
-#include "version.h"
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-#include "../include/mv_gen_reg.h"
-
-#ifdef CONFIG_ECC
-	/* Galileo specific asm code for initializing ECC */
-	.globl board_relocate_rom
-board_relocate_rom:
-	mflr	r7
-	/* update the location of the GT registers */
-	lis	r11, CFG_GT_REGS@h
-	/* if we're using ECC, we must use the DMA engine to copy ourselves */
-	bl	start_idma_transfer_0
-	bl	wait_for_idma_0
-	bl	stop_idma_engine_0
-
-	mtlr	r7
-	blr
-
-	.globl board_init_ecc
-board_init_ecc:
-	mflr	r7
-	/* NOTE: r10 still contains the location we've been relocated to
-	 * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */
-
-	/* now that we're running from ram, init the rest of main memory
-	 * for ECC use */
-	lis	r8, CFG_MONITOR_LEN@h
-	ori	r8, r8, CFG_MONITOR_LEN@l
-
-	divw	r3, r10, r8
-
-	/* set up the counter, and init the starting address */
-	mtctr	r3
-	li	r12, 0
-
-	/* bytes per transfer */
-	mr	r5, r8
-about_to_init_ecc:
-1:	mr	r3, r12
-	mr	r4, r12
-	bl	start_idma_transfer_0
-	bl	wait_for_idma_0
-	bl	stop_idma_engine_0
-	add	r12, r12, r8
-	bdnz	1b
-
-	mtlr	r7
-	blr
-
-	/* r3:	dest addr
-	 * r4:	source addr
-	 * r5:	byte count
-	 * r11: gt regbase
-	 * trashes:	 r6, r5
-	 */
-start_idma_transfer_0:
-	/* set the byte count, including the OWN bit */
-	mr	r6, r11
-	ori	r6, r6, CHANNEL0_DMA_BYTE_COUNT
-	stwbrx	r5, 0, (r6)
-
-	/* set the source address */
-	mr	r6, r11
-	ori	r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS
-	stwbrx	r4, 0, (r6)
-
-	/* set the dest address */
-	mr	r6, r11
-	ori	r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS
-	stwbrx	r3, 0, (r6)
-
-	/* set the next record pointer */
-	li	r5, 0
-	mr	r6, r11
-	ori	r6, r6, CHANNEL0NEXT_RECORD_POINTER
-	stwbrx	r5, 0, (r6)
-
-	/* set the low control register */
-	/* bit 9 is NON chained mode, bit 31 is new style descriptors.
-	   bit 12 is channel enable */
-	ori	r5, r5, (1 << 12) | (1 << 12) | (1 << 11)
-	/* 15 shifted by 16 (oris) == bit 31 */
-	oris	r5, r5, (1 << 15)
-	mr	r6, r11
-	ori	r6, r6, CHANNEL0CONTROL
-	stwbrx	r5, 0, (r6)
-
-	blr
-
-	/* this waits for the bytecount to return to zero, indicating
-	 * that the trasfer is complete */
-wait_for_idma_0:
-	mr	r5, r11
-	lis	r6, 0xff
-	ori	r6, r6, 0xffff
-	ori	r5, r5, CHANNEL0_DMA_BYTE_COUNT
-1:	lwbrx	r4, 0, (r5)
-	and.	r4, r4, r6
-	bne	1b
-
-	blr
-
-	/* this turns off channel 0 of the idma engine */
-stop_idma_engine_0:
-	/* shut off the DMA engine */
-	li	r5, 0
-	mr	r6, r11
-	ori	r6, r6, CHANNEL0CONTROL
-	stwbrx	r5, 0, (r6)
-
-	blr
-#endif
-
-#ifdef CFG_BOARD_ASM_INIT
-	/* NOTE: trashes r3-r7 */
-	.globl board_asm_init
-board_asm_init:
-	/* just move the GT registers to where they belong */
-	lis	r3, CFG_DFL_GT_REGS@h
-	ori	r3, r3, CFG_DFL_GT_REGS@l
-	lis	r4, CFG_GT_REGS@h
-	ori	r4, r4, CFG_GT_REGS@l
-	li	r5, INTERNAL_SPACE_DECODE
-
-	/* test to see if we've already moved */
-	lwbrx	r6, r5, r4
-	andi.	r6, r6, 0xffff
-	/* check loading of R7 is: 0x0F80 should: 0xf800: DONE */
-/*	rlwinm	r7, r4, 8, 16, 31
-	rlwinm	r7, r4, 12, 16, 31	*/ /* original */
-	rlwinm	r7, r4, 16, 16, 31
-	/* -----------------------------------------------------*/
-	cmp	cr0, r7, r6
-	beqlr
-
-	/* nope, have to move the registers */
-	lwbrx	r6, r5, r3
-	andis.	r6, r6, 0xffff
-	or	r6, r6, r7
-	stwbrx	r6, r5, r3
-
-	/* now, poll for the change */
-1:	lwbrx	r7, r5, r4
-	cmp	cr0, r7, r6
-	bne	1b
-
-	/* done! */
-	blr
-#endif
-
-/* For use of the debug LEDs */
-	.global led_on0_relocated
-led_on0_relocated:
-	xor	r21, r21, r21
-	xor	r18, r18, r18
-	lis	r18, 0xFC80
-	ori	r18, r18, 0x8000
-	stw	r21, 0x0(r18)
-/*	  stw	  r18, 0x0(r18) */
-	sync
-	blr
-
-	.global led_off0_relocated
-led_off0_relocated:
-	xor	r21, r21, r21
-	xor	r18, r18, r18
-	lis	r18, 0xFC81
-	ori	r18, r18, 0x4000
-	stw	r21, 0x0(r18)
-/*	  stw	  r18, 0x0(r18) */
-	sync
-	blr
-
-	.global led_on0
-led_on0:
-	xor	r18, r18, r18
-	lis	r18, 0x1c80
-	ori	r18, r18, 0x8000
-	stw	r18, 0x0(r18)
-	sync
-	blr
-
-	.global led_off0
-led_off0:
-	xor	r18, r18, r18
-	lis	r18, 0x1c81
-	ori	r18, r18, 0x4000
-	stw	r18, 0x0(r18)
-	sync
-	blr
-
-	.global led_on1
-led_on1:
-	xor	r18, r18, r18
-	lis	r18, 0x1c80
-	ori	r18, r18, 0xc000
-	stw	r18, 0x0(r18)
-	sync
-	blr
-
-	.global led_off1
-led_off1:
-	xor	r18, r18, r18
-	lis	r18, 0x1c81
-	ori	r18, r18, 0x8000
-	stw	r18, 0x0(r18)
-	sync
-	blr
-
-	.global led_on2
-led_on2:
-	xor	r18, r18, r18
-	lis	r18, 0x1c81
-	ori	r18, r18, 0x0000
-	stw	r18, 0x0(r18)
-	sync
-	blr
-
-	.global led_off2
-led_off2:
-	xor	r18, r18, r18
-	lis	r18, 0x1c81
-	ori	r18, r18, 0xc000
-	stw	r18, 0x0(r18)
-	sync
-	blr

board/Marvell/common/ns16550.c

@@ -1,66 +0,0 @@
-/*
- * COM1 NS16550 support
- * originally from linux source (arch/ppc/boot/ns16550.c)
- * modified to use CFG_ISA_MEM and new defines
- *
- * further modified by Josh Huber <huber@mclx.com> to support
- * the DUART on the Galileo Eval board. (db64360)
- */
-
-#include <config.h>
-#include "ns16550.h"
-
-#ifdef ZUMA_NTL
-/* no 16550 device */
-#else
-const NS16550_t COM_PORTS[] = { (NS16550_t) (CFG_DUART_IO + 0),
-	(NS16550_t) (CFG_DUART_IO + 0x20)
-};
-
-volatile struct NS16550 *NS16550_init (int chan, int baud_divisor)
-{
-	volatile struct NS16550 *com_port;
-
-	com_port = (struct NS16550 *) COM_PORTS[chan];
-	com_port->ier = 0x00;
-	com_port->lcr = LCR_BKSE;	/* Access baud rate */
-	com_port->dll = baud_divisor & 0xff;	/* 9600 baud */
-	com_port->dlm = (baud_divisor >> 8) & 0xff;
-	com_port->lcr = LCR_8N1;	/* 8 data, 1 stop, no parity */
-	com_port->mcr = MCR_DTR | MCR_RTS;	/* RTS/DTR */
-
-	/* Clear & enable FIFOs */
-	com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;
-	return (com_port);
-}
-
-void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor)
-{
-	com_port->ier = 0x00;
-	com_port->lcr = LCR_BKSE;	/* Access baud rate */
-	com_port->dll = baud_divisor & 0xff;	/* 9600 baud */
-	com_port->dlm = (baud_divisor >> 8) & 0xff;
-	com_port->lcr = LCR_8N1;	/* 8 data, 1 stop, no parity */
-	com_port->mcr = MCR_DTR | MCR_RTS;	/* RTS/DTR */
-
-	/* Clear & enable FIFOs */
-	com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;
-}
-
-void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c)
-{
-	while ((com_port->lsr & LSR_THRE) == 0);
-	com_port->thr = c;
-}
-
-unsigned char NS16550_getc (volatile struct NS16550 *com_port)
-{
-	while ((com_port->lsr & LSR_DR) == 0);
-	return (com_port->rbr);
-}
-
-int NS16550_tstc (volatile struct NS16550 *com_port)
-{
-	return ((com_port->lsr & LSR_DR) != 0);
-}
-#endif

board/Marvell/common/ns16550.h

@@ -1,102 +0,0 @@
-/*
- * NS16550 Serial Port
- * originally from linux source (arch/ppc/boot/ns16550.h)
- * modified slightly to
- * have addresses as offsets from CFG_ISA_BASE
- * added a few more definitions
- * added prototypes for ns16550.c
- * reduced no of com ports to 2
- * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
- *
- * further modified to support the DUART in the Galileo eval board
- * modifications (c) Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- */
-
-#ifndef __NS16550_H__
-#define __NS16550_H__
-
-/* the padding is necessary because on the galileo board the UART is
-   wired in with the 3 address lines shifted over by 2 bits */
-struct NS16550
-{
-	unsigned char rbr;  /* 0 = 0-3*/
-	int pad1:24;
-
-	unsigned char ier;  /* 1 = 4-7*/
-	int pad2:24;
-
-	unsigned char fcr;  /* 2 = 8-b*/
-	int pad3:24;
-
-	unsigned char lcr;  /* 3 = c-f*/
-	int pad4:24;
-
-	unsigned char mcr;  /* 4 = 10-13*/
-	int pad5:24;
-
-	unsigned char lsr;  /* 5 = 14-17*/
-	int pad6:24;
-
-	unsigned char msr;  /* 6 =18-1b*/
-	int pad7:24;
-
-	unsigned char scr;  /* 7 =1c-1f*/
-	int pad8:24;
-} __attribute__ ((packed));
-
-/* aliases */
-#define thr rbr
-#define iir fcr
-#define dll rbr
-#define dlm ier
-
-#define FCR_FIFO_EN     0x01    /*fifo enable*/
-#define FCR_RXSR        0x02    /*reciever soft reset*/
-#define FCR_TXSR        0x04    /*transmitter soft reset*/
-
-
-#define MCR_DTR         0x01
-#define MCR_RTS         0x02
-#define MCR_DMA_EN      0x04
-#define MCR_TX_DFR      0x08
-
-
-#define LCR_WLS_MSK 0x03    /* character length slect mask*/
-#define LCR_WLS_5   0x00    /* 5 bit character length */
-#define LCR_WLS_6   0x01    /* 6 bit character length */
-#define LCR_WLS_7   0x02    /* 7 bit character length */
-#define LCR_WLS_8   0x03    /* 8 bit character length */
-#define LCR_STB     0x04    /* Number of stop Bits, off = 1, on = 1.5 or 2) */
-#define LCR_PEN     0x08    /* Parity eneble*/
-#define LCR_EPS     0x10    /* Even Parity Select*/
-#define LCR_STKP    0x20    /* Stick Parity*/
-#define LCR_SBRK    0x40    /* Set Break*/
-#define LCR_BKSE    0x80    /* Bank select enable*/
-
-#define LSR_DR      0x01    /* Data ready */
-#define LSR_OE      0x02    /* Overrun */
-#define LSR_PE      0x04    /* Parity error */
-#define LSR_FE      0x08    /* Framing error */
-#define LSR_BI      0x10    /* Break */
-#define LSR_THRE    0x20    /* Xmit holding register empty */
-#define LSR_TEMT    0x40    /* Xmitter empty */
-#define LSR_ERR     0x80    /* Error */
-
-/* useful defaults for LCR*/
-#define LCR_8N1     0x03
-
-
-#define COM1 0x03F8
-#define COM2 0x02F8
-
-volatile struct NS16550 * NS16550_init(int chan, int baud_divisor);
-void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c);
-unsigned char NS16550_getc(volatile struct NS16550 *com_port);
-int NS16550_tstc(volatile struct NS16550 *com_port);
-void NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor);
-
-typedef struct NS16550 *NS16550_t;
-
-extern const NS16550_t COM_PORTS[];
-
-#endif

board/Marvell/common/ppc_error_no.h

@@ -1,164 +0,0 @@
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * BK Id: SCCS/s.errno.h 1.9 06/05/01 21:45:21 paulus
- */
-#ifndef _MV_PPC_ERRNO_H
-#define _MV_PPC_ERRNO_H
-
-#define	EPERM		 1	/* Operation not permitted */
-#define	ENOENT		 2	/* No such file or directory */
-#define	ESRCH		 3	/* No such process */
-#define	EINTR		 4	/* Interrupted system call */
-#define	EIO		 5	/* I/O error */
-#define	ENXIO		 6	/* No such device or address */
-#define	E2BIG		 7	/* Arg list too long */
-#define	ENOEXEC		 8	/* Exec format error */
-#define	EBADF		 9	/* Bad file number */
-#define	ECHILD		10	/* No child processes */
-#define	EAGAIN		11	/* Try again */
-#define	ENOMEM		12	/* Out of memory */
-#define	EACCES		13	/* Permission denied */
-#define	EFAULT		14	/* Bad address */
-#define	ENOTBLK		15	/* Block device required */
-#define	EBUSY		16	/* Device or resource busy */
-#define	EEXIST		17	/* File exists */
-#define	EXDEV		18	/* Cross-device link */
-#define	ENODEV		19	/* No such device */
-#define	ENOTDIR		20	/* Not a directory */
-#define	EISDIR		21	/* Is a directory */
-#define	EINVAL		22	/* Invalid argument */
-#define	ENFILE		23	/* File table overflow */
-#define	EMFILE		24	/* Too many open files */
-#define	ENOTTY		25	/* Not a typewriter */
-#define	ETXTBSY		26	/* Text file busy */
-#define	EFBIG		27	/* File too large */
-#define	ENOSPC		28	/* No space left on device */
-#define	ESPIPE		29	/* Illegal seek */
-#define	EROFS		30	/* Read-only file system */
-#define	EMLINK		31	/* Too many links */
-#define	EPIPE		32	/* Broken pipe */
-#define	EDOM		33	/* Math argument out of domain of func */
-#define	ERANGE		34	/* Math result not representable */
-#define	EDEADLK		35	/* Resource deadlock would occur */
-#define	ENAMETOOLONG	36	/* File name too long */
-#define	ENOLCK		37	/* No record locks available */
-#define	ENOSYS		38	/* Function not implemented */
-#define	ENOTEMPTY	39	/* Directory not empty */
-#define	ELOOP		40	/* Too many symbolic links encountered */
-#define	EWOULDBLOCK	EAGAIN	/* Operation would block */
-#define	ENOMSG		42	/* No message of desired type */
-#define	EIDRM		43	/* Identifier removed */
-#define	ECHRNG		44	/* Channel number out of range */
-#define	EL2NSYNC	45	/* Level 2 not synchronized */
-#define	EL3HLT		46	/* Level 3 halted */
-#define	EL3RST		47	/* Level 3 reset */
-#define	ELNRNG		48	/* Link number out of range */
-#define	EUNATCH		49	/* Protocol driver not attached */
-#define	ENOCSI		50	/* No CSI structure available */
-#define	EL2HLT		51	/* Level 2 halted */
-#define	EBADE		52	/* Invalid exchange */
-#define	EBADR		53	/* Invalid request descriptor */
-#define	EXFULL		54	/* Exchange full */
-#define	ENOANO		55	/* No anode */
-#define	EBADRQC		56	/* Invalid request code */
-#define	EBADSLT		57	/* Invalid slot */
-#define	EDEADLOCK	58	/* File locking deadlock error */
-#define	EBFONT		59	/* Bad font file format */
-#define	ENOSTR		60	/* Device not a stream */
-#define	ENODATA		61	/* No data available */
-#define	ETIME		62	/* Timer expired */
-#define	ENOSR		63	/* Out of streams resources */
-#define	ENONET		64	/* Machine is not on the network */
-#define	ENOPKG		65	/* Package not installed */
-#define	EREMOTE		66	/* Object is remote */
-#define	ENOLINK		67	/* Link has been severed */
-#define	EADV		68	/* Advertise error */
-#define	ESRMNT		69	/* Srmount error */
-#define	ECOMM		70	/* Communication error on send */
-#define	EPROTO		71	/* Protocol error */
-#define	EMULTIHOP	72	/* Multihop attempted */
-#define	EDOTDOT		73	/* RFS specific error */
-#define	EBADMSG		74	/* Not a data message */
-#define	EOVERFLOW	75	/* Value too large for defined data type */
-#define	ENOTUNIQ	76	/* Name not unique on network */
-#define	EBADFD		77	/* File descriptor in bad state */
-#define	EREMCHG		78	/* Remote address changed */
-#define	ELIBACC		79	/* Can not access a needed shared library */
-#define	ELIBBAD		80	/* Accessing a corrupted shared library */
-#define	ELIBSCN		81	/* .lib section in a.out corrupted */
-#define	ELIBMAX		82	/* Attempting to link in too many shared libraries */
-#define	ELIBEXEC	83	/* Cannot exec a shared library directly */
-#define	EILSEQ		84	/* Illegal byte sequence */
-#define	ERESTART	85	/* Interrupted system call should be restarted */
-#define	ESTRPIPE	86	/* Streams pipe error */
-#define	EUSERS		87	/* Too many users */
-#define	ENOTSOCK	88	/* Socket operation on non-socket */
-#define	EDESTADDRREQ	89	/* Destination address required */
-#define	EMSGSIZE	90	/* Message too long */
-#define	EPROTOTYPE	91	/* Protocol wrong type for socket */
-#define	ENOPROTOOPT	92	/* Protocol not available */
-#define	EPROTONOSUPPORT	93	/* Protocol not supported */
-#define	ESOCKTNOSUPPORT	94	/* Socket type not supported */
-#define	EOPNOTSUPP	95	/* Operation not supported on transport endpoint */
-#define	EPFNOSUPPORT	96	/* Protocol family not supported */
-#define	EAFNOSUPPORT	97	/* Address family not supported by protocol */
-#define	EADDRINUSE	98	/* Address already in use */
-#define	EADDRNOTAVAIL	99	/* Cannot assign requested address */
-#define	ENETDOWN	100	/* Network is down */
-#define	ENETUNREACH	101	/* Network is unreachable */
-#define	ENETRESET	102	/* Network dropped connection because of reset */
-#define	ECONNABORTED	103	/* Software caused connection abort */
-#define	ECONNRESET	104	/* Connection reset by peer */
-#define	ENOBUFS		105	/* No buffer space available */
-#define	EISCONN		106	/* Transport endpoint is already connected */
-#define	ENOTCONN	107	/* Transport endpoint is not connected */
-#define	ESHUTDOWN	108	/* Cannot send after transport endpoint shutdown */
-#define	ETOOMANYREFS	109	/* Too many references: cannot splice */
-#define	ETIMEDOUT	110	/* Connection timed out */
-#define	ECONNREFUSED	111	/* Connection refused */
-#define	EHOSTDOWN	112	/* Host is down */
-#define	EHOSTUNREACH	113	/* No route to host */
-#define	EALREADY	114	/* Operation already in progress */
-#define	EINPROGRESS	115	/* Operation now in progress */
-#define	ESTALE		116	/* Stale NFS file handle */
-#define	EUCLEAN		117	/* Structure needs cleaning */
-#define	ENOTNAM		118	/* Not a XENIX named type file */
-#define	ENAVAIL		119	/* No XENIX semaphores available */
-#define	EISNAM		120	/* Is a named type file */
-#define	EREMOTEIO	121	/* Remote I/O error */
-#define	EDQUOT		122	/* Quota exceeded */
-
-#define	ENOMEDIUM	123	/* No medium found */
-#define	EMEDIUMTYPE	124	/* Wrong medium type */
-
-/* Should never be seen by user programs */
-#define ERESTARTSYS	512
-#define ERESTARTNOINTR	513
-#define ERESTARTNOHAND	514	/* restart if no handler.. */
-#define ENOIOCTLCMD	515	/* No ioctl command */
-
-#define _LAST_ERRNO	515
-
-#endif

board/Marvell/common/serial.c

@@ -1,178 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * modified for marvell db64360 eval board by
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * serial.c - serial support for the gal ev board
- */
-
-/* supports both the 16650 duart and the MPSC */
-
-#include <common.h>
-#include <command.h>
-#include "../include/memory.h"
-#include "serial.h"
-
-#ifdef CONFIG_DB64360
-#include "../db64360/mpsc.h"
-#endif
-
-#ifdef CONFIG_DB64460
-#include "../db64460/mpsc.h"
-#endif
-
-#include "ns16550.h"
-
-#ifdef CONFIG_MPSC
-
-
-int serial_init (void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2)
-	int clock_divisor = 230400 / gd->baudrate;
-#endif
-
-	mpsc_init (gd->baudrate);
-
-	/* init the DUART chans so that KGDB in the kernel can use them */
-#ifdef CFG_INIT_CHAN1
-	NS16550_reinit (COM_PORTS[0], clock_divisor);
-#endif
-#ifdef CFG_INIT_CHAN2
-	NS16550_reinit (COM_PORTS[1], clock_divisor);
-#endif
-	return (0);
-}
-
-void serial_putc (const char c)
-{
-	if (c == '\n')
-		mpsc_putchar ('\r');
-
-	mpsc_putchar (c);
-}
-
-int serial_getc (void)
-{
-	return mpsc_getchar ();
-}
-
-int serial_tstc (void)
-{
-	return mpsc_test_char ();
-}
-
-void serial_setbrg (void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
-}
-
-#else  /* ! CONFIG_MPSC */
-
-int serial_init (void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	int clock_divisor = 230400 / gd->baudrate;
-
-#ifdef CFG_INIT_CHAN1
-	(void) NS16550_init (0, clock_divisor);
-#endif
-#ifdef CFG_INIT_CHAN2
-	(void) NS16550_init (1, clock_divisor);
-#endif
-	return (0);
-}
-
-void serial_putc (const char c)
-{
-	if (c == '\n')
-		NS16550_putc (COM_PORTS[CFG_DUART_CHAN], '\r');
-
-	NS16550_putc (COM_PORTS[CFG_DUART_CHAN], c);
-}
-
-int serial_getc (void)
-{
-	return NS16550_getc (COM_PORTS[CFG_DUART_CHAN]);
-}
-
-int serial_tstc (void)
-{
-	return NS16550_tstc (COM_PORTS[CFG_DUART_CHAN]);
-}
-
-void serial_setbrg (void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	int clock_divisor = 230400 / gd->baudrate;
-
-#ifdef CFG_INIT_CHAN1
-	NS16550_reinit (COM_PORTS[0], clock_divisor);
-#endif
-#ifdef CFG_INIT_CHAN2
-	NS16550_reinit (COM_PORTS[1], clock_divisor);
-#endif
-}
-
-#endif /* CONFIG_MPSC */
-
-void serial_puts (const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-void kgdb_serial_init (void)
-{
-}
-
-void putDebugChar (int c)
-{
-	serial_putc (c);
-}
-
-void putDebugStr (const char *str)
-{
-	serial_puts (str);
-}
-
-int getDebugChar (void)
-{
-	return serial_getc ();
-}
-
-void kgdb_interruptible (int yes)
-{
-	return;
-}
-#endif /* CFG_CMD_KGDB */

board/Marvell/common/serial.h

@@ -1,89 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * modified for marvell db64360 eval board by
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* serial.h - mostly useful for DUART serial_init in serial.c */
-
-#ifndef __SERIAL_H__
-#define __SERIAL_H__
-
-#if 0
-
-#define B230400         1
-#define B115200         2
-#define B57600          4
-#define B38400          82
-#define B19200          163
-#define B9600           24
-#define B4800           651
-#define B2400           1302
-#define B1200           2604
-#define B600            5208
-#define B300            10417
-#define B150            20833
-#define B110            28409
-#define BDEFAULT        B115200
-
-				/* this stuff is important to initialize
-				the DUART channels */
-
-#define	Scale		0x01L		/* distance between port addresses */
-#define	COM1		0x000003f8		/* Keyboard */
-#define COM2		0x000002f8		/* Host */
-
-
-/* Port Definitions relative to base COM port addresses */
-#define DataIn	(0x00*Scale)	/* data input port */
-#define DataOut	(0x00*Scale)	/* data output port */
-#define BaudLsb	(0x00*Scale)	/* baud rate divisor least significant byte */
-#define BaudMsb	(0x01*Scale)	/* baud rate divisor most significant byte */
-#define	Ier	(0x01*Scale)	/* interrupt enable register */
-#define	Iir	(0x02*Scale)	/* interrupt identification register */
-#define	Lcr	(0x03*Scale)	/* line control register */
-#define	Mcr	(0x04*Scale)	/* modem control register */
-#define	Lsr	(0x05*Scale)	/* line status register */
-#define	Msr	(0x06*Scale)	/* modem status register */
-
-/* Bit Definitions for above ports */
-#define LcrDlab	0x80	/* b7:	 enable baud rate divisor registers */
-#define	LcrDflt	0x03	/* b6-0: no parity, 1 stop, 8 data */
-
-#define	McrRts	0x02	/* b1:	request to send (I am ready to xmit) */
-#define	McrDtr	0x01	/* b0:	data terminal ready (I am alive ready to rcv) */
-#define	McrDflt	(McrRts|McrDtr)
-
-#define LsrTxD	0x6000	/* b5: transmit holding register empty (i.e. xmit OK!)*/
-			/* b6: transmitter empty */
-#define LsrRxD	0x0100	/* b0: received data ready (i.e. got a byte!) */
-
-#define	MsrRi	0x0040	/* b6: ring indicator (other guy is ready to rcv) */
-#define	MsrDsr	0x0020	/* b5: data set ready (other guy is alive ready to rcv */
-#define	MsrCts	0x0010	/* b4: clear to send (other guy is ready to rcv) */
-
-#define IerRda	0xf	/* b0: Enable received data available interrupt */
-
-#endif
-
-#endif /* __SERIAL_H__ */

board/Marvell/db64360/64360.h

@@ -1,52 +0,0 @@
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * main board support/init for the Galileo Eval board DB64360.
- */
-
-#ifndef __64360_H__
-#define __64360_H__
-
-/* CPU Configuration bits */
-#define CPU_CONF_ADDR_MISS_EN	(1 << 8)
-#define	CPU_CONF_SINGLE_CPU	(1 << 11)
-#define	CPU_CONF_ENDIANESS	(1 << 12)
-#define CPU_CONF_PIPELINE	(1 << 13)
-#define CPU_CONF_STOP_RETRY	(1 << 17)
-#define CPU_CONF_MULTI_DECODE	(1 << 18)
-#define CPU_CONF_DP_VALID	(1 << 19)
-#define CPU_CONF_PERR_PROP	(1 << 22)
-#define CPU_CONF_AACK_DELAY_2	(1 << 25)
-#define CPU_CONF_AP_VALID	(1 << 26)
-#define CPU_CONF_REMAP_WR_DIS	(1 << 27)
-
-/* CPU Master Control bits */
-#define CPU_MAST_CTL_ARB_EN	(1 << 8)
-#define CPU_MAST_CTL_MASK_BR_1	(1 << 9)
-#define CPU_MAST_CTL_M_WR_TRIG	(1 << 10)
-#define CPU_MAST_CTL_M_RD_TRIG	(1 << 11)
-#define CPU_MAST_CTL_CLEAN_BLK	(1 << 12)
-#define CPU_MAST_CTL_FLUSH_BLK	(1 << 13)
-
-#endif /* __64360_H__ */

board/Marvell/db64360/Makefile

@@ -1,44 +0,0 @@
-#
-# (C) Copyright 2001
-# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= lib$(BOARD).a
-
-SOBJS	= ../common/misc.o
-
-OBJS	= $(BOARD).o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \
-	  mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \
-	  sdram_init.o ../common/intel_flash.o
-
-$(LIB):	.depend $(OBJS) $(SOBJS)
-	$(AR) crv $@ $(OBJS) $(SOBJS)
-
-#########################################################################
-
-.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
-		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-
-sinclude .depend
-
-#########################################################################

board/Marvell/db64360/config.mk

@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2001
-# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# EVB64360 boards
-#
-
-TEXT_BASE = 0xfff00000

board/Marvell/db64360/db64360.c

@@ -1,936 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com
- */
-
-/*
- * db64360.c - main board support/init for the Galileo Eval board.
- */
-
-#include <common.h>
-#include <74xx_7xx.h>
-#include "../include/memory.h"
-#include "../include/pci.h"
-#include "../include/mv_gen_reg.h"
-#include <net.h>
-
-#include "eth.h"
-#include "mpsc.h"
-#include "i2c.h"
-#include "64360.h"
-#include "mv_regs.h"
-
-#undef	DEBUG
-/*#define	DEBUG */
-
-#define	MAP_PCI
-
-#ifdef DEBUG
-#define DP(x) x
-#else
-#define DP(x)
-#endif
-
-extern void flush_data_cache (void);
-extern void invalidate_l1_instruction_cache (void);
-
-/* ------------------------------------------------------------------------- */
-
-/* this is the current GT register space location */
-/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
-
-/* Unfortunately, we cant change it while we are in flash, so we initialize it
- * to the "final" value. This means that any debug_led calls before
- * board_early_init_f wont work right (like in cpu_init_f).
- * See also my_remap_gt_regs below. (NTL)
- */
-
-void board_prebootm_init (void);
-unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
-int display_mem_map (void);
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * This is a version of the GT register space remapping function that
- * doesn't touch globals (meaning, it's ok to run from flash.)
- *
- * Unfortunately, this has the side effect that a writable
- * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
- */
-
-void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
-{
-	u32 temp;
-
-	/* check and see if it's already moved */
-
-/* original ppcboot 1.1.6 source
-
-	temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
-	if ((temp & 0xffff) == new_loc >> 20)
-		return;
-
-	temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
-		0xffff0000) | (new_loc >> 20);
-
-	out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
-
-	while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
-original ppcboot 1.1.6 source end */
-
-	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
-	if ((temp & 0xffff) == new_loc >> 16)
-		return;
-
-	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
-		0xffff0000) | (new_loc >> 16);
-
-	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
-
-	while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
-}
-
-#ifdef CONFIG_PCI
-
-static void gt_pci_config (void)
-{
-	unsigned int stat;
-	unsigned int val = 0x00fff864;	/* DINK32: BusNum 23:16,  DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
-
-	/* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
-	 * config registers by writing ones to the bus and device.
-	 * We then update the Virtual register with the correct value for the bus and device.
-	 */
-	if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
-		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
-
-		GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
-
-		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
-		GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
-			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
-
-	}
-	if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
-		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
-		GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
-
-		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
-		GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
-			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
-	}
-
-	/* Enable master */
-	PCI_MASTER_ENABLE (0, SELF);
-	PCI_MASTER_ENABLE (1, SELF);
-
-	/* Enable PCI0/1 Mem0 and IO 0 disable all others */
-	GT_REG_READ (BASE_ADDR_ENABLE, &stat);
-	stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
-									     <<
-									     18);
-	stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
-	GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
-
-	/* ronen- add write to pci remap registers for 64460.
-	   in 64360 when writing to pci base go and overide remap automaticaly,
-	   in 64460 it doesn't */
-	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16);
-
-	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16);
-
-	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16);
-
-	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16);
-
-	/* PCI interface settings */
-	/* Timeout set to retry forever */
-	GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
-	GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
-
-	/* ronen - enable only CS0 and Internal reg!! */
-	GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
-	GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
-
-/*ronen update the pci internal registers base address.*/
-#ifdef MAP_PCI
-	for (stat = 0; stat <= PCI_HOST1; stat++)
-		pciWriteConfigReg (stat,
-				   PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
-				   SELF, CFG_GT_REGS);
-#endif
-
-}
-#endif
-
-/* Setup CPU interface paramaters */
-static void gt_cpu_config (void)
-{
-	cpu_t cpu = get_cpu_type ();
-	ulong tmp;
-
-	/* cpu configuration register */
-	tmp = GTREGREAD (CPU_CONFIGURATION);
-
-	/* set the SINGLE_CPU bit  see MV64360 P.399 */
-#ifndef CFG_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
-	tmp |= CPU_CONF_SINGLE_CPU;
-#endif
-
-	tmp &= ~CPU_CONF_AACK_DELAY_2;
-
-	tmp |= CPU_CONF_DP_VALID;
-	tmp |= CPU_CONF_AP_VALID;
-
-	tmp |= CPU_CONF_PIPELINE;
-
-	GT_REG_WRITE (CPU_CONFIGURATION, tmp);	/* Marvell (VXWorks) writes 0x20220FF */
-
-	/* CPU master control register */
-	tmp = GTREGREAD (CPU_MASTER_CONTROL);
-
-	tmp |= CPU_MAST_CTL_ARB_EN;
-
-	if ((cpu == CPU_7400) ||
-	    (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
-
-		tmp |= CPU_MAST_CTL_CLEAN_BLK;
-		tmp |= CPU_MAST_CTL_FLUSH_BLK;
-
-	} else {
-		/* cleanblock must be cleared for CPUs
-		 * that do not support this command (603e, 750)
-		 * see Res#1 */
-		tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
-		tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
-	}
-	GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
-}
-
-/*
- * board_early_init_f.
- *
- * set up gal. device mappings, etc.
- */
-int board_early_init_f (void)
-{
-	uchar sram_boot = 0;
-
-	/*
-	 * set up the GT the way the kernel wants it
-	 * the call to move the GT register space will obviously
-	 * fail if it has already been done, but we're going to assume
-	 * that if it's not at the power-on location, it's where we put
-	 * it last time. (huber)
-	 */
-
-	my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
-
-	/* No PCI in first release of Port To_do: enable it. */
-#ifdef CONFIG_PCI
-	gt_pci_config ();
-#endif
-	/* mask all external interrupt sources */
-	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
-	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
-	/* new in MV6436x */
-	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
-	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
-	/* --------------------- */
-	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
-	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
-	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
-	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
-	/* does not exist in MV6436x
-	   GT_REG_WRITE(CPU_INT_0_MASK, 0);
-	   GT_REG_WRITE(CPU_INT_1_MASK, 0);
-	   GT_REG_WRITE(CPU_INT_2_MASK, 0);
-	   GT_REG_WRITE(CPU_INT_3_MASK, 0);
-	   --------------------- */
-
-
-	/* ----- DEVICE BUS SETTINGS ------ */
-
-	/*
-	 * EVB
-	 * 0 - SRAM   ????
-	 * 1 - RTC      ????
-	 * 2 - UART     ????
-	 * 3 - Flash    checked 32Bit Intel Strata
-	 * boot - BootCS checked 8Bit 29LV040B
-	 *
-	 * Zuma
-	 * 0 - Flash
-	 * boot - BootCS
-	 */
-
-	/*
-	 * the dual 7450 module requires burst access to the boot
-	 * device, so the serial rom copies the boot device to the
-	 * on-board sram on the eval board, and updates the correct
-	 * registers to boot from the sram. (device0)
-	 */
-	if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE)
-		sram_boot = 1;
-	if (!sram_boot)
-		memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
-
-	memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE);
-	memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE);
-	memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE);
-
-
-	/* configure device timing */
-#ifdef CFG_DEV0_PAR		/* set port parameters for SRAM device module access */
-	if (!sram_boot)
-		GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR);
-#endif
-
-#ifdef CFG_DEV1_PAR		/* set port parameters for RTC device module access */
-	GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR);
-#endif
-#ifdef CFG_DEV2_PAR		/* set port parameters for DUART device module access */
-	GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);
-#endif
-
-#ifdef CFG_32BIT_BOOT_PAR	/* set port parameters for Flash device module access */
-	/* detect if we are booting from the 32 bit flash */
-	if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
-		/* 32 bit boot flash */
-		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR);
-		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
-			      CFG_32BIT_BOOT_PAR);
-	} else {
-		/* 8 bit boot flash */
-		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR);
-		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
-	}
-#else
-	/* 8 bit boot flash only */
-/*	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/
-#endif
-
-
-	gt_cpu_config ();
-
-	/* MPP setup */
-	GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0);
-	GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1);
-	GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2);
-	GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3);
-
-	GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
-	DEBUG_LED0_ON ();
-	DEBUG_LED1_ON ();
-	DEBUG_LED2_ON ();
-
-	return 0;
-}
-
-/* various things to do after relocation */
-
-int misc_init_r ()
-{
-	icache_enable ();
-#ifdef CFG_L2
-	l2cache_enable ();
-#endif
-#ifdef CONFIG_MPSC
-
-	mpsc_sdma_init ();
-	mpsc_init2 ();
-#endif
-
-#if 0
-	/* disable the dcache and MMU */
-	dcache_lock ();
-#endif
-	return 0;
-}
-
-void after_reloc (ulong dest_addr, gd_t * gd)
-{
-	/* check to see if we booted from the sram.  If so, move things
-	 * back to the way they should be. (we're running from main
-	 * memory at this point now */
-	if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) {
-		memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
-		memoryMapDeviceSpace (BOOT_DEVICE, CFG_DFL_BOOTCS_BASE, _8M);
-	}
-	display_mem_map ();
-	/* now, jump to the main ppcboot board init code */
-	board_init_r (gd, dest_addr);
-	/* NOTREACHED */
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- *
- * right now, assume borad type. (there is just one...after all)
- */
-
-int checkboard (void)
-{
-	int l_type = 0;
-
-	printf ("BOARD: %s\n", CFG_BOARD_NAME);
-	return (l_type);
-}
-
-/* utility functions */
-void debug_led (int led, int mode)
-{
-	volatile int *addr = 0;
-	int dummy;
-
-	if (mode == 1) {
-		switch (led) {
-		case 0:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
-					0x08000);
-			break;
-
-		case 1:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
-					0x0c000);
-			break;
-
-		case 2:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
-					0x10000);
-			break;
-		}
-	} else if (mode == 0) {
-		switch (led) {
-		case 0:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
-					0x14000);
-			break;
-
-		case 1:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
-					0x18000);
-			break;
-
-		case 2:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
-					0x1c000);
-			break;
-		}
-	}
-
-	dummy = *addr;
-}
-
-int display_mem_map (void)
-{
-	int i, j;
-	unsigned int base, size, width;
-
-	/* SDRAM */
-	printf ("SD (DDR) RAM\n");
-	for (i = 0; i <= BANK3; i++) {
-		base = memoryGetBankBaseAddress (i);
-		size = memoryGetBankSize (i);
-		if (size != 0) {
-			printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
-				i, base, size >> 20);
-		}
-	}
-
-	/* CPU's PCI windows */
-	for (i = 0; i <= PCI_HOST1; i++) {
-		printf ("\nCPU's PCI %d windows\n", i);
-		base = pciGetSpaceBase (i, PCI_IO);
-		size = pciGetSpaceSize (i, PCI_IO);
-		printf ("      IO: base - 0x%08x\tsize - %dM bytes\n", base,
-			size >> 20);
-		for (j = 0;
-		     j <=
-		     PCI_REGION0
-		     /*ronen currently only first PCI MEM is used 3 */ ;
-		     j++) {
-			base = pciGetSpaceBase (i, j);
-			size = pciGetSpaceSize (i, j);
-			printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
-		}
-	}
-
-	/* Devices */
-	printf ("\nDEVICES\n");
-	for (i = 0; i <= DEVICE3; i++) {
-		base = memoryGetDeviceBaseAddress (i);
-		size = memoryGetDeviceSize (i);
-		width = memoryGetDeviceWidth (i) * 8;
-		printf ("DEV %d:  base - 0x%08x  size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
-		if (i == 0)
-			printf ("\t- EXT SRAM (actual - 1M)\n");
-		else if (i == 1)
-			printf ("\t- RTC\n");
-		else if (i == 2)
-			printf ("\t- UART\n");
-		else
-			printf ("\t- LARGE FLASH\n");
-	}
-
-	/* Bootrom */
-	base = memoryGetDeviceBaseAddress (BOOT_DEVICE);	/* Boot */
-	size = memoryGetDeviceSize (BOOT_DEVICE);
-	width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
-	printf (" BOOT:  base - 0x%08x  size - %dM bytes\twidth - %d bits\n",
-		base, size >> 20, width);
-	return (0);
-}
-
-/* DRAM check routines copied from gw8260 */
-
-#if defined (CFG_DRAM_TEST)
-
-/*********************************************************************/
-/* NAME:  move64() -  moves a double word (64-bit)		     */
-/*								     */
-/* DESCRIPTION:							     */
-/*   this function performs a double word move from the data at	     */
-/*   the source pointer to the location at the destination pointer.  */
-/*								     */
-/* INPUTS:							     */
-/*   unsigned long long *src  - pointer to data to move		     */
-/*								     */
-/* OUTPUTS:							     */
-/*   unsigned long long *dest - pointer to locate to move data	     */
-/*								     */
-/* RETURNS:							     */
-/*   None							     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*   May cloober fr0.						     */
-/*								     */
-/*********************************************************************/
-static void move64 (unsigned long long *src, unsigned long long *dest)
-{
-	asm ("lfd  0, 0(3)\n\t"	/* fpr0   =  *scr       */
-	     "stfd 0, 0(4)"	/* *dest  =  fpr0       */
-      : : : "fr0");		/* Clobbers fr0         */
-	return;
-}
-
-
-#if defined (CFG_DRAM_TEST_DATA)
-
-unsigned long long pattern[] = {
-	0xaaaaaaaaaaaaaaaa,
-	0xcccccccccccccccc,
-	0xf0f0f0f0f0f0f0f0,
-	0xff00ff00ff00ff00,
-	0xffff0000ffff0000,
-	0xffffffff00000000,
-	0x00000000ffffffff,
-	0x0000ffff0000ffff,
-	0x00ff00ff00ff00ff,
-	0x0f0f0f0f0f0f0f0f,
-	0x3333333333333333,
-	0x5555555555555555
-};
-
-/*********************************************************************/
-/* NAME:  mem_test_data() -  test data lines for shorts and opens    */
-/*								     */
-/* DESCRIPTION:							     */
-/*   Tests data lines for shorts and opens by forcing adjacent data  */
-/*   to opposite states. Because the data lines could be routed in   */
-/*   an arbitrary manner the must ensure test patterns ensure that   */
-/*   every case is tested. By using the following series of binary   */
-/*   patterns every combination of adjacent bits is test regardless  */
-/*   of routing.						     */
-/*								     */
-/*     ...101010101010101010101010				     */
-/*     ...110011001100110011001100				     */
-/*     ...111100001111000011110000				     */
-/*     ...111111110000000011111111				     */
-/*								     */
-/*   Carrying this out, gives us six hex patterns as follows:	     */
-/*								     */
-/*     0xaaaaaaaaaaaaaaaa					     */
-/*     0xcccccccccccccccc					     */
-/*     0xf0f0f0f0f0f0f0f0					     */
-/*     0xff00ff00ff00ff00					     */
-/*     0xffff0000ffff0000					     */
-/*     0xffffffff00000000					     */
-/*								     */
-/*   The number test patterns will always be given by:		     */
-/*								     */
-/*   log(base 2)(number data bits) = log2 (64) = 6		     */
-/*								     */
-/*   To test for short and opens to other signals on our boards. we  */
-/*   simply							     */
-/*   test with the 1's complemnt of the paterns as well.	     */
-/*								     */
-/* OUTPUTS:							     */
-/*   Displays failing test pattern				     */
-/*								     */
-/* RETURNS:							     */
-/*   0 -  Passed test						     */
-/*   1 -  Failed test						     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*  Assumes only one one SDRAM bank				     */
-/*								     */
-/*********************************************************************/
-int mem_test_data (void)
-{
-	unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
-	unsigned long long temp64;
-	int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
-	int i;
-	unsigned int hi, lo;
-
-	for (i = 0; i < num_patterns; i++) {
-		move64 (&(pattern[i]), pmem);
-		move64 (pmem, &temp64);
-
-		/* hi = (temp64>>32) & 0xffffffff;          */
-		/* lo = temp64 & 0xffffffff;                */
-		/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
-
-		hi = (pattern[i] >> 32) & 0xffffffff;
-		lo = pattern[i] & 0xffffffff;
-		/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo);  */
-
-		if (temp64 != pattern[i]) {
-			printf ("\n   Data Test Failed, pattern 0x%08x%08x",
-				hi, lo);
-			return 1;
-		}
-	}
-
-	return 0;
-}
-#endif /* CFG_DRAM_TEST_DATA */
-
-#if defined (CFG_DRAM_TEST_ADDRESS)
-/*********************************************************************/
-/* NAME:  mem_test_address() -	test address lines		     */
-/*								     */
-/* DESCRIPTION:							     */
-/*   This function performs a test to verify that each word im	     */
-/*   memory is uniquly addressable. The test sequence is as follows: */
-/*								     */
-/*   1) write the address of each word to each word.		     */
-/*   2) verify that each location equals its address		     */
-/*								     */
-/* OUTPUTS:							     */
-/*   Displays failing test pattern and address			     */
-/*								     */
-/* RETURNS:							     */
-/*   0 -  Passed test						     */
-/*   1 -  Failed test						     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*								     */
-/*								     */
-/*********************************************************************/
-int mem_test_address (void)
-{
-	volatile unsigned int *pmem =
-		(volatile unsigned int *) CFG_MEMTEST_START;
-	const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4;
-	unsigned int i;
-
-	/* write address to each location */
-	for (i = 0; i < size; i++) {
-		pmem[i] = i;
-	}
-
-	/* verify each loaction */
-	for (i = 0; i < size; i++) {
-		if (pmem[i] != i) {
-			printf ("\n   Address Test Failed at 0x%x", i);
-			return 1;
-		}
-	}
-	return 0;
-}
-#endif /* CFG_DRAM_TEST_ADDRESS */
-
-#if defined (CFG_DRAM_TEST_WALK)
-/*********************************************************************/
-/* NAME:   mem_march() -  memory march				     */
-/*								     */
-/* DESCRIPTION:							     */
-/*   Marches up through memory. At each location verifies rmask if   */
-/*   read = 1. At each location write wmask if	write = 1. Displays  */
-/*   failing address and pattern.				     */
-/*								     */
-/* INPUTS:							     */
-/*   volatile unsigned long long * base - start address of test	     */
-/*   unsigned int size - number of dwords(64-bit) to test	     */
-/*   unsigned long long rmask - read verify mask		     */
-/*   unsigned long long wmask - wrtie verify mask		     */
-/*   short read - verifies rmask if read = 1			     */
-/*   short write  - writes wmask if write = 1			     */
-/*								     */
-/* OUTPUTS:							     */
-/*   Displays failing test pattern and address			     */
-/*								     */
-/* RETURNS:							     */
-/*   0 -  Passed test						     */
-/*   1 -  Failed test						     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*								     */
-/*								     */
-/*********************************************************************/
-int mem_march (volatile unsigned long long *base,
-	       unsigned int size,
-	       unsigned long long rmask,
-	       unsigned long long wmask, short read, short write)
-{
-	unsigned int i;
-	unsigned long long temp;
-	unsigned int hitemp, lotemp, himask, lomask;
-
-	for (i = 0; i < size; i++) {
-		if (read != 0) {
-			/* temp = base[i]; */
-			move64 ((unsigned long long *) &(base[i]), &temp);
-			if (rmask != temp) {
-				hitemp = (temp >> 32) & 0xffffffff;
-				lotemp = temp & 0xffffffff;
-				himask = (rmask >> 32) & 0xffffffff;
-				lomask = rmask & 0xffffffff;
-
-				printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
-				return 1;
-			}
-		}
-		if (write != 0) {
-			/*  base[i] = wmask; */
-			move64 (&wmask, (unsigned long long *) &(base[i]));
-		}
-	}
-	return 0;
-}
-#endif /* CFG_DRAM_TEST_WALK */
-
-/*********************************************************************/
-/* NAME:   mem_test_walk() -  a simple walking ones test	     */
-/*								     */
-/* DESCRIPTION:							     */
-/*   Performs a walking ones through entire physical memory. The     */
-/*   test uses as series of memory marches, mem_march(), to verify   */
-/*   and write the test patterns to memory. The test sequence is as  */
-/*   follows:							     */
-/*     1) march writing 0000...0001				     */
-/*     2) march verifying 0000...0001  , writing  0000...0010	     */
-/*     3) repeat step 2 shifting masks left 1 bit each time unitl    */
-/*	   the write mask equals 1000...0000			     */
-/*     4) march verifying 1000...0000				     */
-/*   The test fails if any of the memory marches return a failure.   */
-/*								     */
-/* OUTPUTS:							     */
-/*   Displays which pass on the memory test is executing	     */
-/*								     */
-/* RETURNS:							     */
-/*   0 -  Passed test						     */
-/*   1 -  Failed test						     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*								     */
-/*								     */
-/*********************************************************************/
-int mem_test_walk (void)
-{
-	unsigned long long mask;
-	volatile unsigned long long *pmem =
-		(volatile unsigned long long *) CFG_MEMTEST_START;
-	const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8;
-
-	unsigned int i;
-
-	mask = 0x01;
-
-	printf ("Initial Pass");
-	mem_march (pmem, size, 0x0, 0x1, 0, 1);
-
-	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
-	printf ("		");
-	printf ("         ");
-	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
-
-	for (i = 0; i < 63; i++) {
-		printf ("Pass %2d", i + 2);
-		if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
-			/*printf("mask: 0x%x, pass: %d, ", mask, i); */
-			return 1;
-		}
-		mask = mask << 1;
-		printf ("\b\b\b\b\b\b\b");
-	}
-
-	printf ("Last Pass");
-	if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
-		/* printf("mask: 0x%x", mask); */
-		return 1;
-	}
-	printf ("\b\b\b\b\b\b\b\b\b");
-	printf ("	     ");
-	printf ("\b\b\b\b\b\b\b\b\b");
-
-	return 0;
-}
-
-/*********************************************************************/
-/* NAME:    testdram() -  calls any enabled memory tests	     */
-/*								     */
-/* DESCRIPTION:							     */
-/*   Runs memory tests if the environment test variables are set to  */
-/*   'y'.							     */
-/*								     */
-/* INPUTS:							     */
-/*   testdramdata    - If set to 'y', data test is run.		     */
-/*   testdramaddress - If set to 'y', address test is run.	     */
-/*   testdramwalk    - If set to 'y', walking ones test is run	     */
-/*								     */
-/* OUTPUTS:							     */
-/*   None							     */
-/*								     */
-/* RETURNS:							     */
-/*   0 -  Passed test						     */
-/*   1 -  Failed test						     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*								     */
-/*								     */
-/*********************************************************************/
-int testdram (void)
-{
-	char *s;
-	int rundata, runaddress, runwalk;
-
-	s = getenv ("testdramdata");
-	rundata = (s && (*s == 'y')) ? 1 : 0;
-	s = getenv ("testdramaddress");
-	runaddress = (s && (*s == 'y')) ? 1 : 0;
-	s = getenv ("testdramwalk");
-	runwalk = (s && (*s == 'y')) ? 1 : 0;
-
-/*    rundata = 1; */
-/*    runaddress = 0; */
-/*    runwalk = 0; */
-
-	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
-		printf ("Testing RAM from 0x%08x to 0x%08x ...  (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END);
-	}
-#ifdef CFG_DRAM_TEST_DATA
-	if (rundata == 1) {
-		printf ("Test DATA ...  ");
-		if (mem_test_data () == 1) {
-			printf ("failed \n");
-			return 1;
-		} else
-			printf ("ok \n");
-	}
-#endif
-#ifdef CFG_DRAM_TEST_ADDRESS
-	if (runaddress == 1) {
-		printf ("Test ADDRESS ...  ");
-		if (mem_test_address () == 1) {
-			printf ("failed \n");
-			return 1;
-		} else
-			printf ("ok \n");
-	}
-#endif
-#ifdef CFG_DRAM_TEST_WALK
-	if (runwalk == 1) {
-		printf ("Test WALKING ONEs ...  ");
-		if (mem_test_walk () == 1) {
-			printf ("failed \n");
-			return 1;
-		} else
-			printf ("ok \n");
-	}
-#endif
-	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
-		printf ("passed\n");
-	}
-	return 0;
-
-}
-#endif /* CFG_DRAM_TEST */
-
-/* ronen - the below functions are used by the bootm function           */
-/*  - we map the base register to fbe00000 (same mapping as in the LSP) */
-/*  - we turn off the RX gig dmas - to prevent the dma from overunning  */
-/*    the kernel data areas.                                            */
-/*  - we diable and invalidate the icache and dcache.                   */
-void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
-{
-	u32 temp;
-
-	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
-	if ((temp & 0xffff) == new_loc >> 16)
-		return;
-
-	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
-		0xffff0000) | (new_loc >> 16);
-
-	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
-
-	while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
-							new_loc |
-							(INTERNAL_SPACE_DECODE)))))
-	       != temp);
-
-}
-
-void board_prebootm_init ()
-{
-
-/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
-		GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
-
-/* Stop GigE Rx DMA engines */
-	GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
-	GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00);
-/* MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0x0000ff00); */
-
-/* Relocate MV64360 internal regs */
-	my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM);
-
-	icache_disable ();
-	invalidate_l1_instruction_cache ();
-	flush_data_cache ();
-	dcache_disable ();
-}

board/Marvell/db64360/eth.h

@@ -1,43 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * eth.h - header file for the polled mode GT ethernet driver
- */
-
-#ifndef __EVB64360_ETH_H__
-#define __EVB64360_ETH_H__
-
-#include <asm/types.h>
-#include <asm/io.h>
-#include <asm/byteorder.h>
-#include <common.h>
-
-
-int db64360_eth0_poll(void);
-int db64360_eth0_transmit(unsigned int s, volatile char *p);
-void db64360_eth0_disable(void);
-bool network_start(bd_t *bis);
-
-
-#endif /* __EVB64360_ETH_H__ */

board/Marvell/db64360/mpsc.h

@@ -1,156 +0,0 @@
-/*
- * (C) Copyright 2001
- * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*************************************************************************
- * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
- *
-  ************************************************************************/
-
-
-/*
- * mpsc.h - header file for MPSC in uart mode (console driver)
- */
-
-#ifndef __MPSC_H__
-#define __MPSC_H__
-
-/* include actual Galileo defines */
-#include "../include/mv_gen_reg.h"
-
-/* driver related defines */
-
-int mpsc_init(int baud);
-void mpsc_sdma_init(void);
-void mpsc_init2(void);
-int galbrg_set_baudrate(int channel, int rate);
-
-int mpsc_putchar_early(char ch);
-char mpsc_getchar_debug(void);
-int mpsc_test_char_debug(void);
-
-int mpsc_test_char_sdma(void);
-
-extern int (*mpsc_putchar)(char ch);
-extern char (*mpsc_getchar)(void);
-extern int (*mpsc_test_char)(void);
-
-#define CHANNEL CONFIG_MPSC_PORT
-
-#define TX_DESC     5
-#define RX_DESC     20
-
-#define DESC_FIRST  0x00010000
-#define DESC_LAST   0x00020000
-#define DESC_OWNER_BIT  0x80000000
-
-#define TX_DEMAND   0x00800000
-#define TX_STOP     0x00010000
-#define RX_ENABLE   0x00000080
-
-#define SDMA_RX_ABORT 		  (1 << 15)
-#define SDMA_TX_ABORT 		  (1 << 31)
-#define MPSC_TX_ABORT 		  (1 << 7)
-#define MPSC_RX_ABORT             (1 << 23)
-#define MPSC_ENTER_HUNT           (1 << 31)
-
-/* MPSC defines */
-
-#define GALMPSC_CONNECT            0x1
-#define GALMPSC_DISCONNECT         0x0
-
-#define GALMPSC_UART               0x1
-
-#define GALMPSC_STOP_BITS_1        0x0
-#define GALMPSC_STOP_BITS_2        0x1
-#define GALMPSC_CHAR_LENGTH_8      0x3
-#define GALMPSC_CHAR_LENGTH_7      0x2
-
-#define GALMPSC_PARITY_ODD         0x0
-#define GALMPSC_PARITY_EVEN        0x2
-#define GALMPSC_PARITY_MARK        0x3
-#define GALMPSC_PARITY_SPACE       0x1
-#define GALMPSC_PARITY_NONE        -1
-
-#define GALMPSC_SERIAL_MULTIPLEX   SERIAL_PORT_MULTIPLEX           /* 0xf010 */
-#define GALMPSC_ROUTING_REGISTER   MAIN_ROUTING_REGISTER           /* 0xb400 */
-#define GALMPSC_RxC_ROUTE          RECEIVE_CLOCK_ROUTING_REGISTER  /* 0xb404 */
-#define GALMPSC_TxC_ROUTE          TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
-#define GALMPSC_MCONF_LOW          MPSC0_MAIN_CONFIGURATION_LOW    /* 0x8000 */
-#define GALMPSC_MCONF_HIGH         MPSC0_MAIN_CONFIGURATION_HIGH   /* 0x8004 */
-#define GALMPSC_PROTOCONF_REG      MPSC0_PROTOCOL_CONFIGURATION    /* 0x8008 */
-
-#define GALMPSC_REG_GAP            0x1000
-
-#define GALMPSC_MCONF_CHREG_BASE   CHANNEL0_REGISTER1  /* 0x800c */
-#define GALMPSC_CHANNELREG_1       CHANNEL0_REGISTER1  /* 0x800c */
-#define GALMPSC_CHANNELREG_2       CHANNEL0_REGISTER2  /* 0x8010 */
-#define GALMPSC_CHANNELREG_3       CHANNEL0_REGISTER3  /* 0x8014 */
-#define GALMPSC_CHANNELREG_4       CHANNEL0_REGISTER4  /* 0x8018 */
-#define GALMPSC_CHANNELREG_5       CHANNEL0_REGISTER5  /* 0x801c */
-#define GALMPSC_CHANNELREG_6       CHANNEL0_REGISTER6  /* 0x8020 */
-#define GALMPSC_CHANNELREG_7       CHANNEL0_REGISTER7  /* 0x8024 */
-#define GALMPSC_CHANNELREG_8       CHANNEL0_REGISTER8  /* 0x8028 */
-#define GALMPSC_CHANNELREG_9       CHANNEL0_REGISTER9  /* 0x802c */
-#define GALMPSC_CHANNELREG_10      CHANNEL0_REGISTER10 /* 0x8030 */
-#define GALMPSC_CHANNELREG_11      CHANNEL0_REGISTER11 /* 0x8034 */
-
-#define GALSDMA_COMMAND_FIRST     (1 << 16)
-#define GALSDMA_COMMAND_LAST      (1 << 17)
-#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
-#define GALSDMA_COMMAND_AUTO      (1 << 30)
-#define GALSDMA_COMMAND_OWNER     (1 << 31)
-
-#define GALSDMA_RX                 0
-#define GALSDMA_TX                 1
-
-/* CHANNEL2 should be CHANNEL1, according to documentation,
- * but to work with the current GTREGS file...
- */
-#define GALSDMA_0_CONF_REG         CHANNEL0_CONFIGURATION_REGISTER   /* 0x4000 */
-#define GALSDMA_1_CONF_REG         CHANNEL2_CONFIGURATION_REGISTER   /* 0x6000 */
-#define GALSDMA_0_COM_REG          CHANNEL0_COMMAND_REGISTER         /* 0x4008 */
-#define GALSDMA_1_COM_REG          CHANNEL2_COMMAND_REGISTER         /* 0x6008 */
-#define GALSDMA_0_CUR_RX_PTR       CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x4810 */
-#define GALSDMA_0_CUR_TX_PTR       CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x4c10 */
-#define GALSDMA_0_FIR_TX_PTR       CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER    /* 0x4c14 */
-#define GALSDMA_1_CUR_RX_PTR       CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x6810 */
-#define GALSDMA_1_CUR_TX_PTR       CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x6c10 */
-#define GALSDMA_1_FIR_TX_PTR       CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER    /* 0x6c14 */
-#define GALSDMA_REG_DIFF           0x2000
-
-/* WRONG in gt64260R.h */
-#define GALSDMA_INT_CAUSE          0xb800   /* SDMA_CAUSE */
-#define GALSDMA_INT_MASK           0xb880   /* SDMA_MASK  */
-#define GALMPSC_0_INT_CAUSE        0xb804
-#define GALMPSC_0_INT_MASK         0xb884
-
-#define GALSDMA_MODE_UART          0
-#define GALSDMA_MODE_BISYNC        1
-#define GALSDMA_MODE_HDLC          2
-#define GALSDMA_MODE_TRANSPARENT   3
-
-#define GALBRG_0_CONFREG           BRG0_CONFIGURATION_REGISTER  /*  0xb200  */
-#define GALBRG_REG_GAP             0x0008
-#define GALBRG_0_BTREG             BRG0_BAUDE_TUNING_REGISTER   /*  0xb204  */
-
-#endif /* __MPSC_H__ */

board/Marvell/db64360/mv_eth.h

@@ -1,844 +0,0 @@
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * based on - Driver for MV64360X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * mv_eth.h - header file for the polled mode GT ethernet driver
- */
-
-#ifndef __DB64360_ETH_H__
-#define __DB64360_ETH_H__
-
-#include <asm/types.h>
-#include <asm/io.h>
-#include <asm/byteorder.h>
-#include <common.h>
-#include <net.h>
-#include "mv_regs.h"
-#include "../common/ppc_error_no.h"
-
-
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-*  The first part is the high level driver of the gigE ethernet ports.	 *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-
-/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
-#ifndef MAX_SKB_FRAGS
-#define MAX_SKB_FRAGS 0
-#endif
-
-/* Port attributes */
-/*#define MAX_RX_QUEUE_NUM	8*/
-/*#define MAX_TX_QUEUE_NUM	8*/
-#define MAX_RX_QUEUE_NUM	1
-#define MAX_TX_QUEUE_NUM	1
-
-
-/* Use one TX queue and one RX queue */
-#define MV64360_TX_QUEUE_NUM 1
-#define MV64360_RX_QUEUE_NUM 1
-
-/*
- * Number of RX / TX descriptors on RX / TX rings.
- * Note that allocating RX descriptors is done by allocating the RX
- * ring AND a preallocated RX buffers (skb's) for each descriptor.
- * The TX descriptors only allocates the TX descriptors ring,
- * with no pre allocated TX buffers (skb's are allocated by higher layers.
- */
-
-/* Default TX ring size is 10 descriptors */
-#ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE
-#define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE
-#else
-#define MV64360_TX_QUEUE_SIZE 4
-#endif
-
-/* Default RX ring size is 4 descriptors */
-#ifdef	CONFIG_MV64360_ETH_RXQUEUE_SIZE
-#define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE
-#else
-#define MV64360_RX_QUEUE_SIZE 4
-#endif
-
-#ifdef CONFIG_RX_BUFFER_SIZE
-#define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
-#else
-#define MV64360_RX_BUFFER_SIZE 1600
-#endif
-
-#ifdef CONFIG_TX_BUFFER_SIZE
-#define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
-#else
-#define MV64360_TX_BUFFER_SIZE 1600
-#endif
-
-
-/*
- *	Network device statistics. Akin to the 2.0 ether stats but
- *	with byte counters.
- */
-
-struct net_device_stats
-{
-	unsigned long	rx_packets;		/* total packets received	*/
-	unsigned long	tx_packets;		/* total packets transmitted	*/
-	unsigned long	rx_bytes;		/* total bytes received		*/
-	unsigned long	tx_bytes;		/* total bytes transmitted	*/
-	unsigned long	rx_errors;		/* bad packets received		*/
-	unsigned long	tx_errors;		/* packet transmit problems	*/
-	unsigned long	rx_dropped;		/* no space in linux buffers	*/
-	unsigned long	tx_dropped;		/* no space available in linux	*/
-	unsigned long	multicast;		/* multicast packets received	*/
-	unsigned long	collisions;
-
-	/* detailed rx_errors: */
-	unsigned long	rx_length_errors;
-	unsigned long	rx_over_errors;		/* receiver ring buff overflow	*/
-	unsigned long	rx_crc_errors;		/* recved pkt with crc error	*/
-	unsigned long	rx_frame_errors;	/* recv'd frame alignment error */
-	unsigned long	rx_fifo_errors;		/* recv'r fifo overrun		*/
-	unsigned long	rx_missed_errors;	/* receiver missed packet	*/
-
-	/* detailed tx_errors */
-	unsigned long	tx_aborted_errors;
-	unsigned long	tx_carrier_errors;
-	unsigned long	tx_fifo_errors;
-	unsigned long	tx_heartbeat_errors;
-	unsigned long	tx_window_errors;
-
-	/* for cslip etc */
-	unsigned long	rx_compressed;
-	unsigned long	tx_compressed;
-};
-
-
-/* Private data structure used for ethernet device */
-struct mv64360_eth_priv {
-    unsigned int port_num;
-    struct net_device_stats *stats;
-
-/* to buffer area aligned */
-    char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1];	/*pointers to alligned tx buffs in memory space */
-    char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1];	/*pointers to allinged rx buffs in memory space */
-
-    /* Size of Tx Ring per queue */
-    unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
-
-
-    /* Size of Rx Ring per queue */
-    unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
-
-    /* Magic Number for Ethernet running */
-    unsigned int eth_running;
-
-};
-
-
-int mv64360_eth_init (struct eth_device *dev);
-int mv64360_eth_stop (struct eth_device *dev);
-int mv64360_eth_start_xmit (struct eth_device*, volatile void* packet, int length);
-/*	return db64360_eth0_poll(); */
-
-int mv64360_eth_open (struct eth_device *dev);
-
-
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-*  The second part is the low level driver of the gigE ethernet ports.	 *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-
-
-/********************************************************************************
- * Header File for : MV-643xx network interface header
- *
- * DESCRIPTION:
- *	 This header file contains macros typedefs and function declaration for
- *	 the Marvell Gig Bit Ethernet Controller.
- *
- * DEPENDENCIES:
- *	 None.
- *
- *******************************************************************************/
-
-
-#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
-#ifdef CONFIG_MV64360_SRAM_CACHEABLE
-/* In case SRAM is cacheable but not cache coherent */
-#define D_CACHE_FLUSH_LINE(addr, offset)       \
-{		    \
-  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
-}
-#else
-/* In case SRAM is cache coherent or non-cacheable */
-#define D_CACHE_FLUSH_LINE(addr, offset) ;
-#endif
-#else
-#ifdef CONFIG_NOT_COHERENT_CACHE
-/* In case of descriptors on DDR but not cache coherent */
-#define D_CACHE_FLUSH_LINE(addr, offset)       \
-{		    \
-  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
-}
-#else
-/* In case of descriptors on DDR and cache coherent */
-#define D_CACHE_FLUSH_LINE(addr, offset) ;
-#endif /* CONFIG_NOT_COHERENT_CACHE */
-#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
-
-
-#define CPU_PIPE_FLUSH		   \
-{		  \
-  __asm__ __volatile__ ("eieio");	  \
-}
-
-
-/* defines  */
-
-/* Default port configuration value */
-#define PORT_CONFIG_VALUE			\
-	     ETH_UNICAST_NORMAL_MODE		|   \
-	     ETH_DEFAULT_RX_QUEUE_0		|   \
-	     ETH_DEFAULT_RX_ARP_QUEUE_0		|   \
-	     ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP	|   \
-	     ETH_RECEIVE_BC_IF_IP		|   \
-	     ETH_RECEIVE_BC_IF_ARP		|   \
-	     ETH_CAPTURE_TCP_FRAMES_DIS		|   \
-	     ETH_CAPTURE_UDP_FRAMES_DIS		|   \
-	     ETH_DEFAULT_RX_TCP_QUEUE_0		|   \
-	     ETH_DEFAULT_RX_UDP_QUEUE_0		|   \
-	     ETH_DEFAULT_RX_BPDU_QUEUE_0
-
-/* Default port extend configuration value */
-#define PORT_CONFIG_EXTEND_VALUE		\
-	     ETH_SPAN_BPDU_PACKETS_AS_NORMAL	|   \
-	     ETH_PARTITION_DISABLE
-
-
-/* Default sdma control value */
-#ifdef CONFIG_NOT_COHERENT_CACHE
-#define PORT_SDMA_CONFIG_VALUE				\
-			 ETH_RX_BURST_SIZE_16_64BIT	|	\
-			 GT_ETH_IPG_INT_RX(0)			|	\
-			 ETH_TX_BURST_SIZE_16_64BIT;
-#else
-#define PORT_SDMA_CONFIG_VALUE			\
-			 ETH_RX_BURST_SIZE_4_64BIT	|	\
-			 GT_ETH_IPG_INT_RX(0)			|	\
-			 ETH_TX_BURST_SIZE_4_64BIT;
-#endif
-
-#define GT_ETH_IPG_INT_RX(value)		\
-	    ((value & 0x3fff) << 8)
-
-/* Default port serial control value */
-#define PORT_SERIAL_CONTROL_VALUE			    \
-			ETH_FORCE_LINK_PASS			|	\
-			ETH_ENABLE_AUTO_NEG_FOR_DUPLX		|	\
-			ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL	|	\
-			ETH_ADV_SYMMETRIC_FLOW_CTRL		|	\
-			ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX	|	\
-			ETH_FORCE_BP_MODE_NO_JAM		|	\
-			BIT9					|	\
-			ETH_DO_NOT_FORCE_LINK_FAIL		|	\
-			ETH_RETRANSMIT_16_ETTEMPTS		|	\
-			ETH_ENABLE_AUTO_NEG_SPEED_GMII		|	\
-			ETH_DTE_ADV_0				|	\
-			ETH_DISABLE_AUTO_NEG_BYPASS		|	\
-			ETH_AUTO_NEG_NO_CHANGE			|	\
-			ETH_MAX_RX_PACKET_1552BYTE		|	\
-			ETH_CLR_EXT_LOOPBACK			|	\
-			ETH_SET_FULL_DUPLEX_MODE		|	\
-			ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
-
-#define RX_BUFFER_MAX_SIZE  0xFFFF
-#define TX_BUFFER_MAX_SIZE  0xFFFF   /* Buffer are limited to 64k */
-
-#define RX_BUFFER_MIN_SIZE  0x8
-#define TX_BUFFER_MIN_SIZE  0x8
-
-/* Tx WRR confoguration macros */
-#define PORT_MAX_TRAN_UNIT	    0x24    /* MTU register (default) 9KByte */
-#define PORT_MAX_TOKEN_BUCKET_SIZE  0x_fFFF  /* PMTBS register (default)      */
-#define PORT_TOKEN_RATE		    1023    /* PTTBRC register (default)     */
-
-/* MAC accepet/reject macros */
-#define ACCEPT_MAC_ADDR	    0
-#define REJECT_MAC_ADDR	    1
-
-/* Size of a Tx/Rx descriptor used in chain list data structure */
-#define RX_DESC_ALIGNED_SIZE		0x20
-#define TX_DESC_ALIGNED_SIZE		0x20
-
-/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
-#define TX_BUF_OFFSET_IN_DESC	    0x18
-/* Buffer offset from buffer pointer */
-#define RX_BUF_OFFSET				0x2
-
-/* Gap define */
-#define ETH_BAR_GAP					0x8
-#define ETH_SIZE_REG_GAP				0x8
-#define ETH_HIGH_ADDR_REMAP_REG_GAP			0x4
-#define ETH_PORT_ACCESS_CTRL_GAP			0x4
-
-/* Gigabit Ethernet Unit Global Registers */
-
-/* MIB Counters register definitions */
-#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW   0x0
-#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH  0x4
-#define ETH_MIB_BAD_OCTETS_RECEIVED	   0x8
-#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR  0xc
-#define ETH_MIB_GOOD_FRAMES_RECEIVED	   0x10
-#define ETH_MIB_BAD_FRAMES_RECEIVED	   0x14
-#define ETH_MIB_BROADCAST_FRAMES_RECEIVED  0x18
-#define ETH_MIB_MULTICAST_FRAMES_RECEIVED  0x1c
-#define ETH_MIB_FRAMES_64_OCTETS	   0x20
-#define ETH_MIB_FRAMES_65_TO_127_OCTETS	   0x24
-#define ETH_MIB_FRAMES_128_TO_255_OCTETS   0x28
-#define ETH_MIB_FRAMES_256_TO_511_OCTETS   0x2c
-#define ETH_MIB_FRAMES_512_TO_1023_OCTETS  0x30
-#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS  0x34
-#define ETH_MIB_GOOD_OCTETS_SENT_LOW	   0x38
-#define ETH_MIB_GOOD_OCTETS_SENT_HIGH	   0x3c
-#define ETH_MIB_GOOD_FRAMES_SENT	   0x40
-#define ETH_MIB_EXCESSIVE_COLLISION	   0x44
-#define ETH_MIB_MULTICAST_FRAMES_SENT	   0x48
-#define ETH_MIB_BROADCAST_FRAMES_SENT	   0x4c
-#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
-#define ETH_MIB_FC_SENT			   0x54
-#define ETH_MIB_GOOD_FC_RECEIVED	   0x58
-#define ETH_MIB_BAD_FC_RECEIVED		   0x5c
-#define ETH_MIB_UNDERSIZE_RECEIVED	   0x60
-#define ETH_MIB_FRAGMENTS_RECEIVED	   0x64
-#define ETH_MIB_OVERSIZE_RECEIVED	   0x68
-#define ETH_MIB_JABBER_RECEIVED		   0x6c
-#define ETH_MIB_MAC_RECEIVE_ERROR	   0x70
-#define ETH_MIB_BAD_CRC_EVENT		   0x74
-#define ETH_MIB_COLLISION		   0x78
-#define ETH_MIB_LATE_COLLISION		   0x7c
-
-/* Port serial status reg (PSR) */
-#define ETH_INTERFACE_GMII_MII				0
-#define ETH_INTERFACE_PCM				BIT0
-#define ETH_LINK_IS_DOWN				0
-#define ETH_LINK_IS_UP					BIT1
-#define ETH_PORT_AT_HALF_DUPLEX				0
-#define ETH_PORT_AT_FULL_DUPLEX				BIT2
-#define ETH_RX_FLOW_CTRL_DISABLED			0
-#define ETH_RX_FLOW_CTRL_ENBALED			BIT3
-#define ETH_GMII_SPEED_100_10				0
-#define ETH_GMII_SPEED_1000				BIT4
-#define ETH_MII_SPEED_10				0
-#define ETH_MII_SPEED_100				BIT5
-#define ETH_NO_TX					0
-#define ETH_TX_IN_PROGRESS				BIT7
-#define ETH_BYPASS_NO_ACTIVE				0
-#define ETH_BYPASS_ACTIVE				BIT8
-#define ETH_PORT_NOT_AT_PARTITION_STATE			0
-#define ETH_PORT_AT_PARTITION_STATE			BIT9
-#define ETH_PORT_TX_FIFO_NOT_EMPTY			0
-#define ETH_PORT_TX_FIFO_EMPTY				BIT10
-
-
-/* These macros describes the Port configuration reg (Px_cR) bits */
-#define ETH_UNICAST_NORMAL_MODE				0
-#define ETH_UNICAST_PROMISCUOUS_MODE			BIT0
-#define ETH_DEFAULT_RX_QUEUE_0				0
-#define ETH_DEFAULT_RX_QUEUE_1				BIT1
-#define ETH_DEFAULT_RX_QUEUE_2				BIT2
-#define ETH_DEFAULT_RX_QUEUE_3				(BIT2 | BIT1)
-#define ETH_DEFAULT_RX_QUEUE_4				BIT3
-#define ETH_DEFAULT_RX_QUEUE_5				(BIT3 | BIT1)
-#define ETH_DEFAULT_RX_QUEUE_6				(BIT3 | BIT2)
-#define ETH_DEFAULT_RX_QUEUE_7				(BIT3 | BIT2 | BIT1)
-#define ETH_DEFAULT_RX_ARP_QUEUE_0			0
-#define ETH_DEFAULT_RX_ARP_QUEUE_1			BIT4
-#define ETH_DEFAULT_RX_ARP_QUEUE_2			BIT5
-#define ETH_DEFAULT_RX_ARP_QUEUE_3			(BIT5 | BIT4)
-#define ETH_DEFAULT_RX_ARP_QUEUE_4			BIT6
-#define ETH_DEFAULT_RX_ARP_QUEUE_5			(BIT6 | BIT4)
-#define ETH_DEFAULT_RX_ARP_QUEUE_6			(BIT6 | BIT5)
-#define ETH_DEFAULT_RX_ARP_QUEUE_7			(BIT6 | BIT5 | BIT4)
-#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP			0
-#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP			BIT7
-#define ETH_RECEIVE_BC_IF_IP				0
-#define ETH_REJECT_BC_IF_IP				BIT8
-#define ETH_RECEIVE_BC_IF_ARP				0
-#define ETH_REJECT_BC_IF_ARP				BIT9
-#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY		BIT12
-#define ETH_CAPTURE_TCP_FRAMES_DIS			0
-#define ETH_CAPTURE_TCP_FRAMES_EN			BIT14
-#define ETH_CAPTURE_UDP_FRAMES_DIS			0
-#define ETH_CAPTURE_UDP_FRAMES_EN			BIT15
-#define ETH_DEFAULT_RX_TCP_QUEUE_0			0
-#define ETH_DEFAULT_RX_TCP_QUEUE_1			BIT16
-#define ETH_DEFAULT_RX_TCP_QUEUE_2			BIT17
-#define ETH_DEFAULT_RX_TCP_QUEUE_3			(BIT17 | BIT16)
-#define ETH_DEFAULT_RX_TCP_QUEUE_4			BIT18
-#define ETH_DEFAULT_RX_TCP_QUEUE_5			(BIT18 | BIT16)
-#define ETH_DEFAULT_RX_TCP_QUEUE_6			(BIT18 | BIT17)
-#define ETH_DEFAULT_RX_TCP_QUEUE_7			(BIT18 | BIT17 | BIT16)
-#define ETH_DEFAULT_RX_UDP_QUEUE_0			0
-#define ETH_DEFAULT_RX_UDP_QUEUE_1			BIT19
-#define ETH_DEFAULT_RX_UDP_QUEUE_2			BIT20
-#define ETH_DEFAULT_RX_UDP_QUEUE_3			(BIT20 | BIT19)
-#define ETH_DEFAULT_RX_UDP_QUEUE_4			(BIT21
-#define ETH_DEFAULT_RX_UDP_QUEUE_5			(BIT21 | BIT19)
-#define ETH_DEFAULT_RX_UDP_QUEUE_6			(BIT21 | BIT20)
-#define ETH_DEFAULT_RX_UDP_QUEUE_7			(BIT21 | BIT20 | BIT19)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_0			 0
-#define ETH_DEFAULT_RX_BPDU_QUEUE_1			BIT22
-#define ETH_DEFAULT_RX_BPDU_QUEUE_2			BIT23
-#define ETH_DEFAULT_RX_BPDU_QUEUE_3			(BIT23 | BIT22)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_4			BIT24
-#define ETH_DEFAULT_RX_BPDU_QUEUE_5			(BIT24 | BIT22)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_6			(BIT24 | BIT23)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_7			(BIT24 | BIT23 | BIT22)
-
-
-/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
-#define ETH_CLASSIFY_EN					BIT0
-#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL			0
-#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7		BIT1
-#define ETH_PARTITION_DISABLE				0
-#define ETH_PARTITION_ENABLE				BIT2
-
-
-/* Tx/Rx queue command reg (RQCR/TQCR)*/
-#define ETH_QUEUE_0_ENABLE				BIT0
-#define ETH_QUEUE_1_ENABLE				BIT1
-#define ETH_QUEUE_2_ENABLE				BIT2
-#define ETH_QUEUE_3_ENABLE				BIT3
-#define ETH_QUEUE_4_ENABLE				BIT4
-#define ETH_QUEUE_5_ENABLE				BIT5
-#define ETH_QUEUE_6_ENABLE				BIT6
-#define ETH_QUEUE_7_ENABLE				BIT7
-#define ETH_QUEUE_0_DISABLE				BIT8
-#define ETH_QUEUE_1_DISABLE				BIT9
-#define ETH_QUEUE_2_DISABLE				BIT10
-#define ETH_QUEUE_3_DISABLE				BIT11
-#define ETH_QUEUE_4_DISABLE				BIT12
-#define ETH_QUEUE_5_DISABLE				BIT13
-#define ETH_QUEUE_6_DISABLE				BIT14
-#define ETH_QUEUE_7_DISABLE				BIT15
-
-
-/* These macros describes the Port Sdma configuration reg (SDCR) bits */
-#define ETH_RIFB					BIT0
-#define ETH_RX_BURST_SIZE_1_64BIT			0
-#define ETH_RX_BURST_SIZE_2_64BIT			BIT1
-#define ETH_RX_BURST_SIZE_4_64BIT			BIT2
-#define ETH_RX_BURST_SIZE_8_64BIT			(BIT2 | BIT1)
-#define ETH_RX_BURST_SIZE_16_64BIT			BIT3
-#define ETH_BLM_RX_NO_SWAP				BIT4
-#define ETH_BLM_RX_BYTE_SWAP				0
-#define ETH_BLM_TX_NO_SWAP				BIT5
-#define ETH_BLM_TX_BYTE_SWAP				0
-#define ETH_DESCRIPTORS_BYTE_SWAP			BIT6
-#define ETH_DESCRIPTORS_NO_SWAP				0
-#define ETH_TX_BURST_SIZE_1_64BIT			0
-#define ETH_TX_BURST_SIZE_2_64BIT			BIT22
-#define ETH_TX_BURST_SIZE_4_64BIT			BIT23
-#define ETH_TX_BURST_SIZE_8_64BIT			(BIT23 | BIT22)
-#define ETH_TX_BURST_SIZE_16_64BIT			BIT24
-
-
-/* These macros describes the Port serial control reg (PSCR) bits */
-#define ETH_SERIAL_PORT_DISABLE				0
-#define ETH_SERIAL_PORT_ENABLE				BIT0
-#define ETH_FORCE_LINK_PASS				BIT1
-#define ETH_DO_NOT_FORCE_LINK_PASS			0
-#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX			0
-#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX			BIT2
-#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL		0
-#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL		BIT3
-#define ETH_ADV_NO_FLOW_CTRL				0
-#define ETH_ADV_SYMMETRIC_FLOW_CTRL			BIT4
-#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX		0
-#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS			BIT5
-#define ETH_FORCE_BP_MODE_NO_JAM			0
-#define ETH_FORCE_BP_MODE_JAM_TX			BIT7
-#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR		BIT8
-#define ETH_FORCE_LINK_FAIL				0
-#define ETH_DO_NOT_FORCE_LINK_FAIL			BIT10
-#define ETH_RETRANSMIT_16_ETTEMPTS			0
-#define ETH_RETRANSMIT_FOREVER				BIT11
-#define ETH_DISABLE_AUTO_NEG_SPEED_GMII			BIT13
-#define ETH_ENABLE_AUTO_NEG_SPEED_GMII			0
-#define ETH_DTE_ADV_0					0
-#define ETH_DTE_ADV_1					BIT14
-#define ETH_DISABLE_AUTO_NEG_BYPASS			0
-#define ETH_ENABLE_AUTO_NEG_BYPASS			BIT15
-#define ETH_AUTO_NEG_NO_CHANGE				0
-#define ETH_RESTART_AUTO_NEG				BIT16
-#define ETH_MAX_RX_PACKET_1518BYTE			0
-#define ETH_MAX_RX_PACKET_1522BYTE			BIT17
-#define ETH_MAX_RX_PACKET_1552BYTE			BIT18
-#define ETH_MAX_RX_PACKET_9022BYTE			(BIT18 | BIT17)
-#define ETH_MAX_RX_PACKET_9192BYTE			BIT19
-#define ETH_MAX_RX_PACKET_9700BYTE			(BIT19 | BIT17)
-#define ETH_SET_EXT_LOOPBACK				BIT20
-#define ETH_CLR_EXT_LOOPBACK				0
-#define ETH_SET_FULL_DUPLEX_MODE			BIT21
-#define ETH_SET_HALF_DUPLEX_MODE			0
-#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	BIT22
-#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	0
-#define ETH_SET_GMII_SPEED_TO_10_100			0
-#define ETH_SET_GMII_SPEED_TO_1000			BIT23
-#define ETH_SET_MII_SPEED_TO_10				0
-#define ETH_SET_MII_SPEED_TO_100			BIT24
-
-
-/* SMI reg */
-#define ETH_SMI_BUSY		BIT28	/* 0 - Write, 1 - Read		*/
-#define ETH_SMI_READ_VALID	BIT27	/* 0 - Write, 1 - Read		*/
-#define ETH_SMI_OPCODE_WRITE	0	/* Completion of Read operation */
-#define ETH_SMI_OPCODE_READ	BIT26	/* Operation is in progress		*/
-
-/* SDMA command status fields macros */
-
-/* Tx & Rx descriptors status */
-#define ETH_ERROR_SUMMARY		    (BIT0)
-
-/* Tx & Rx descriptors command */
-#define ETH_BUFFER_OWNED_BY_DMA		    (BIT31)
-
-/* Tx descriptors status */
-#define ETH_LC_ERROR			    (0	  )
-#define ETH_UR_ERROR			    (BIT1 )
-#define ETH_RL_ERROR			    (BIT2 )
-#define ETH_LLC_SNAP_FORMAT		    (BIT9 )
-
-/* Rx descriptors status */
-#define ETH_CRC_ERROR			    (0	  )
-#define ETH_OVERRUN_ERROR		    (BIT1 )
-#define ETH_MAX_FRAME_LENGTH_ERROR	    (BIT2 )
-#define ETH_RESOURCE_ERROR		    ((BIT2 | BIT1))
-#define ETH_VLAN_TAGGED			    (BIT19)
-#define ETH_BPDU_FRAME			    (BIT20)
-#define ETH_TCP_FRAME_OVER_IP_V_4	    (0	  )
-#define ETH_UDP_FRAME_OVER_IP_V_4	    (BIT21)
-#define ETH_OTHER_FRAME_TYPE		    (BIT22)
-#define ETH_LAYER_2_IS_ETH_V_2		    (BIT23)
-#define ETH_FRAME_TYPE_IP_V_4		    (BIT24)
-#define ETH_FRAME_HEADER_OK		    (BIT25)
-#define ETH_RX_LAST_DESC		    (BIT26)
-#define ETH_RX_FIRST_DESC		    (BIT27)
-#define ETH_UNKNOWN_DESTINATION_ADDR	    (BIT28)
-#define ETH_RX_ENABLE_INTERRUPT		    (BIT29)
-#define ETH_LAYER_4_CHECKSUM_OK		    (BIT30)
-
-/* Rx descriptors byte count */
-#define ETH_FRAME_FRAGMENTED		    (BIT2)
-
-/* Tx descriptors command */
-#define ETH_LAYER_4_CHECKSUM_FIRST_DESC		(BIT10)
-#define ETH_FRAME_SET_TO_VLAN		    (BIT15)
-#define ETH_TCP_FRAME			    (0	  )
-#define ETH_UDP_FRAME			    (BIT16)
-#define ETH_GEN_TCP_UDP_CHECKSUM	    (BIT17)
-#define ETH_GEN_IP_V_4_CHECKSUM		    (BIT18)
-#define ETH_ZERO_PADDING		    (BIT19)
-#define ETH_TX_LAST_DESC		    (BIT20)
-#define ETH_TX_FIRST_DESC		    (BIT21)
-#define ETH_GEN_CRC			    (BIT22)
-#define ETH_TX_ENABLE_INTERRUPT		    (BIT23)
-#define ETH_AUTO_MODE			    (BIT30)
-
-/* Address decode parameters */
-/* Ethernet Base Address Register bits */
-#define EBAR_TARGET_DRAM					0x00000000
-#define EBAR_TARGET_DEVICE					0x00000001
-#define EBAR_TARGET_CBS						0x00000002
-#define EBAR_TARGET_PCI0					0x00000003
-#define EBAR_TARGET_PCI1					0x00000004
-#define EBAR_TARGET_CUNIT					0x00000005
-#define EBAR_TARGET_AUNIT					0x00000006
-#define EBAR_TARGET_GUNIT					0x00000007
-
-/* Window attributes */
-#define EBAR_ATTR_DRAM_CS0					0x00000E00
-#define EBAR_ATTR_DRAM_CS1					0x00000D00
-#define EBAR_ATTR_DRAM_CS2					0x00000B00
-#define EBAR_ATTR_DRAM_CS3					0x00000700
-
-/* DRAM Target interface */
-#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY	0x00000000
-#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT	0x00001000
-#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB	0x00002000
-
-/* Device Bus Target interface */
-#define EBAR_ATTR_DEVICE_DEVCS0				0x00001E00
-#define EBAR_ATTR_DEVICE_DEVCS1				0x00001D00
-#define EBAR_ATTR_DEVICE_DEVCS2				0x00001B00
-#define EBAR_ATTR_DEVICE_DEVCS3				0x00001700
-#define EBAR_ATTR_DEVICE_BOOTCS3			0x00000F00
-
-/* PCI Target interface */
-#define EBAR_ATTR_PCI_BYTE_SWAP				0x00000000
-#define EBAR_ATTR_PCI_NO_SWAP				0x00000100
-#define EBAR_ATTR_PCI_BYTE_WORD_SWAP		0x00000200
-#define EBAR_ATTR_PCI_WORD_SWAP				0x00000300
-#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT	0x00000000
-#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT		0x00000400
-#define EBAR_ATTR_PCI_IO_SPACE				0x00000000
-#define EBAR_ATTR_PCI_MEMORY_SPACE			0x00000800
-#define EBAR_ATTR_PCI_REQ64_FORCE			0x00000000
-#define EBAR_ATTR_PCI_REQ64_SIZE			0x00001000
-
-/* CPU 60x bus or internal SRAM interface */
-#define EBAR_ATTR_CBS_SRAM_BLOCK0			0x00000000
-#define EBAR_ATTR_CBS_SRAM_BLOCK1			0x00000100
-#define EBAR_ATTR_CBS_SRAM					0x00000000
-#define EBAR_ATTR_CBS_CPU_BUS				0x00000800
-
-/* Window access control */
-#define EWIN_ACCESS_NOT_ALLOWED 0
-#define EWIN_ACCESS_READ_ONLY	BIT0
-#define EWIN_ACCESS_FULL	(BIT1 | BIT0)
-#define EWIN0_ACCESS_MASK		0x0003
-#define EWIN1_ACCESS_MASK		0x000C
-#define EWIN2_ACCESS_MASK		0x0030
-#define EWIN3_ACCESS_MASK		0x00C0
-
-/* typedefs */
-
-typedef enum _eth_port
-{
-    ETH_0 = 0,
-	ETH_1 = 1,
-	ETH_2 = 2
-}ETH_PORT;
-
-typedef enum _eth_func_ret_status
-{
-    ETH_OK,			/* Returned as expected.		    */
-    ETH_ERROR,			/* Fundamental error.			    */
-    ETH_RETRY,			/* Could not process request. Try later.    */
-    ETH_END_OF_JOB,		/* Ring has nothing to process.		    */
-    ETH_QUEUE_FULL,		/* Ring resource error.			    */
-    ETH_QUEUE_LAST_RESOURCE	/* Ring resources about to exhaust.	    */
-}ETH_FUNC_RET_STATUS;
-
-typedef enum _eth_queue
-{
-	ETH_Q0 = 0,
-	ETH_Q1 = 1,
-	ETH_Q2 = 2,
-	ETH_Q3 = 3,
-	ETH_Q4 = 4,
-	ETH_Q5 = 5,
-	ETH_Q6 = 6,
-    ETH_Q7 = 7
-} ETH_QUEUE;
-
-typedef enum _addr_win
-{
-	ETH_WIN0,
-	ETH_WIN1,
-	ETH_WIN2,
-	ETH_WIN3,
-	ETH_WIN4,
-    ETH_WIN5
-} ETH_ADDR_WIN;
-
-typedef enum _eth_target
-{
-	ETH_TARGET_DRAM	 ,
-	ETH_TARGET_DEVICE,
-	ETH_TARGET_CBS	 ,
-	ETH_TARGET_PCI0	 ,
-	ETH_TARGET_PCI1
-}ETH_TARGET;
-
-typedef struct _eth_rx_desc
-{
-	unsigned short	byte_cnt	   ;	/* Descriptor buffer byte count	    */
-	unsigned short	buf_size	   ;	/* Buffer size			    */
-	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
-	unsigned int	next_desc_ptr;	  /* Next descriptor pointer	      */
-	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
-    unsigned int    return_info ;    /* User resource return information */
-} ETH_RX_DESC;
-
-
-typedef struct _eth_tx_desc
-{
-    unsigned short  byte_cnt	   ;	/* Descriptor buffer byte count	    */
-    unsigned short  l4i_chk	   ;	/* CPU provided TCP Checksum	    */
-    unsigned int    cmd_sts	   ;	/* Descriptor command status	    */
-    unsigned int    next_desc_ptr;    /* Next descriptor pointer	  */
-    unsigned int    buf_ptr	   ;	/* Descriptor buffer pointer	    */
-    unsigned int    return_info ;    /* User resource return information */
-} ETH_TX_DESC;
-
-/* Unified struct for Rx and Tx operations. The user is not required to */
-/* be familier with neither Tx nor Rx descriptors.			 */
-typedef struct _pkt_info
-{
-	unsigned short	byte_cnt   ;	/* Descriptor buffer byte count	    */
-	unsigned short	l4i_chk	   ;	/* Tx CPU provided TCP Checksum	    */
-	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
-	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
-    unsigned int    return_info ;    /* User resource return information */
-} PKT_INFO;
-
-
-typedef struct _eth_win_param
-{
-    ETH_ADDR_WIN win;	/* Window number. See ETH_ADDR_WIN enum */
-    ETH_TARGET	target;	   /* System targets. See ETH_TARGET enum */
-    unsigned short attributes;	/* BAR attributes. See above macros. */
-    unsigned int base_addr; /* Window base address in unsigned int form */
-    unsigned int high_addr; /* Window high address in unsigned int form */
-    unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
-    bool enable; /* Enable/disable access to the window. */
-    unsigned short access_ctrl; /* Access ctrl register. see above macros */
-} ETH_WIN_PARAM;
-
-
-/* Ethernet port specific infomation */
-
-typedef struct _eth_port_ctrl
-{
-    ETH_PORT  port_num; /* User Ethernet port number */
-    int port_phy_addr;	/* User phy address of Ethrnet port */
-    unsigned char port_mac_addr[6]; /* User defined port MAC address. */
-    unsigned int  port_config; /* User port configuration value */
-    unsigned int  port_config_extend; /* User port config extend value */
-    unsigned int  port_sdma_config; /* User port SDMA config value */
-    unsigned int  port_serial_control; /* User port serial control value */
-    unsigned int  port_tx_queue_command; /* Port active Tx queues summary */
-    unsigned int  port_rx_queue_command; /* Port active Rx queues summary */
-
-    /* User function to cast virtual address to CPU bus address */
-    unsigned int  (*port_virt_to_phys)(unsigned int addr);
-    /* User scratch pad for user specific data structures */
-    void *port_private;
-
-    bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
-    bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
-
-    /* Tx/Rx rings managment indexes fields. For driver use */
-
-    /* Next available Rx resource */
-    volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
-    /* Returning Rx resource */
-    volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
-
-    /* Next available Tx resource */
-    volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
-    /* Returning Tx resource */
-    volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
-    /* An extra Tx index to support transmit of multiple buffers per packet */
-    volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
-
-    /* Tx/Rx rings size and base variables fields. For driver use */
-
-    volatile ETH_RX_DESC	*p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
-    unsigned int		 rx_desc_area_size[MAX_RX_QUEUE_NUM];
-    char			*p_rx_buffer_base[MAX_RX_QUEUE_NUM];
-
-    volatile ETH_TX_DESC	*p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
-    unsigned int		 tx_desc_area_size[MAX_TX_QUEUE_NUM];
-    char			*p_tx_buffer_base[MAX_TX_QUEUE_NUM];
-
-} ETH_PORT_INFO;
-
-
-/* ethernet.h API list */
-
-/* Port operation control routines */
-static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
-static void eth_port_reset(ETH_PORT	eth_port_num);
-static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
-
-
-/* Port MAC address routines */
-static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
-				  unsigned char *p_addr,
-				  ETH_QUEUE queue);
-#if 0	/* FIXME */
-static void eth_port_mc_addr	(ETH_PORT eth_port_num,
-				 unsigned char *p_addr,
-				 ETH_QUEUE queue,
-				 int option);
-#endif
-
-/* PHY and MIB routines */
-static bool ethernet_phy_reset(ETH_PORT eth_port_num);
-
-static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
-				   unsigned int phy_reg,
-				   unsigned int value);
-
-static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
-				  unsigned int phy_reg,
-				  unsigned int* value);
-
-static void eth_clear_mib_counters(ETH_PORT	eth_port_num);
-
-/* Port data flow control routines */
-static ETH_FUNC_RET_STATUS eth_port_send    (ETH_PORT_INFO *p_eth_port_ctrl,
-					     ETH_QUEUE tx_queue,
-					     PKT_INFO *p_pkt_info);
-static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
-					      ETH_QUEUE tx_queue,
-					      PKT_INFO *p_pkt_info);
-static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
-					     ETH_QUEUE rx_queue,
-					     PKT_INFO *p_pkt_info);
-static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
-					      ETH_QUEUE rx_queue,
-					      PKT_INFO *p_pkt_info);
-
-
-static bool ether_init_tx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
-				    ETH_QUEUE	tx_queue,
-				    int				tx_desc_num,
-				    int				tx_buff_size,
-				    unsigned int	tx_desc_base_addr,
-				    unsigned int	tx_buff_base_addr);
-
-static bool ether_init_rx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
-				    ETH_QUEUE	rx_queue,
-				    int				rx_desc_num,
-				    int				rx_buff_size,
-				    unsigned int	rx_desc_base_addr,
-				    unsigned int	rx_buff_base_addr);
-
-#endif /* MV64360_ETH_ */

board/Marvell/db64360/pci.c

@@ -1,940 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-/* PCI.c - PCI functions */
-
-
-#include <common.h>
-#include <pci.h>
-
-#include "../include/pci.h"
-
-#undef DEBUG
-#undef IDE_SET_NATIVE_MODE
-static unsigned int local_buses[] = { 0, 0 };
-
-static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
-	{0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
-	{0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
-};
-
-
-#ifdef DEBUG
-static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
-static void gt_pci_bus_mode_display (PCI_HOST host)
-{
-	unsigned int mode;
-
-
-	mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
-	switch (mode) {
-	case 0:
-		printf ("PCI %d bus mode: Conventional PCI\n", host);
-		break;
-	case 1:
-		printf ("PCI %d bus mode: 66 Mhz PCIX\n", host);
-		break;
-	case 2:
-		printf ("PCI %d bus mode: 100 Mhz PCIX\n", host);
-		break;
-	case 3:
-		printf ("PCI %d bus mode: 133 Mhz PCIX\n", host);
-		break;
-	default:
-		printf ("Unknown BUS %d\n", mode);
-	}
-}
-#endif
-
-static const unsigned int pci_p2p_configuration_reg[] = {
-	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
-};
-
-static const unsigned int pci_configuration_address[] = {
-	PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
-};
-
-static const unsigned int pci_configuration_data[] = {
-	PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
-	PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
-};
-
-static const unsigned int pci_error_cause_reg[] = {
-	PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
-};
-
-static const unsigned int pci_arbiter_control[] = {
-	PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
-};
-
-static const unsigned int pci_address_space_en[] = {
-	PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
-};
-
-static const unsigned int pci_snoop_control_base_0_low[] = {
-	PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
-};
-static const unsigned int pci_snoop_control_top_0[] = {
-	PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
-};
-
-static const unsigned int pci_access_control_base_0_low[] = {
-	PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
-};
-static const unsigned int pci_access_control_top_0[] = {
-	PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
-};
-
-static const unsigned int pci_scs_bank_size[2][4] = {
-	{PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
-	 PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
-	{PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
-	 PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
-};
-
-static const unsigned int pci_p2p_configuration[] = {
-	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
-};
-
-
-/********************************************************************
-* pciWriteConfigReg - Write to a PCI configuration register
-*                    - Make sure the GT is configured as a master before writing
-*                      to another device on the PCI.
-*                    - The function takes care of Big/Little endian conversion.
-*
-*
-* Inputs:   unsigned int regOffset: The register offset as it apears in the GT spec
-*                   (or any other PCI device spec)
-*           pciDevNum: The device number needs to be addressed.
-*
-*  Configuration Address 0xCF8:
-*
-*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
-*  |congif|Reserved|  Bus |Device|Function|Register|00|
-*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
-*
-*********************************************************************/
-void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
-			unsigned int pciDevNum, unsigned int data)
-{
-	volatile unsigned int DataForAddrReg;
-	unsigned int functionNum;
-	unsigned int busNum = 0;
-	unsigned int addr;
-
-	if (pciDevNum > 32)	/* illegal device Number */
-		return;
-	if (pciDevNum == SELF) {	/* configure our configuration space. */
-		pciDevNum =
-			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
-			0x1f;
-		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
-			0xff0000;
-	}
-	functionNum = regOffset & 0x00000700;
-	pciDevNum = pciDevNum << 11;
-	regOffset = regOffset & 0xfc;
-	DataForAddrReg =
-		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
-	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
-	GT_REG_READ (pci_configuration_address[host], &addr);
-	if (addr != DataForAddrReg)
-		return;
-	GT_REG_WRITE (pci_configuration_data[host], data);
-}
-
-/********************************************************************
-* pciReadConfigReg  - Read from a PCI0 configuration register
-*                    - Make sure the GT is configured as a master before reading
-*                     from another device on the PCI.
-*                   - The function takes care of Big/Little endian conversion.
-* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
-*                        spec)
-*           pciDevNum: The device number needs to be addressed.
-* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
-*                 cause register to make sure the data is valid
-*
-*  Configuration Address 0xCF8:
-*
-*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
-*  |congif|Reserved|  Bus |Device|Function|Register|00|
-*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
-*
-*********************************************************************/
-unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
-			       unsigned int pciDevNum)
-{
-	volatile unsigned int DataForAddrReg;
-	unsigned int data;
-	unsigned int functionNum;
-	unsigned int busNum = 0;
-
-	if (pciDevNum > 32)	/* illegal device Number */
-		return 0xffffffff;
-	if (pciDevNum == SELF) {	/* configure our configuration space. */
-		pciDevNum =
-			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
-			0x1f;
-		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
-			0xff0000;
-	}
-	functionNum = regOffset & 0x00000700;
-	pciDevNum = pciDevNum << 11;
-	regOffset = regOffset & 0xfc;
-	DataForAddrReg =
-		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
-	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
-	GT_REG_READ (pci_configuration_address[host], &data);
-	if (data != DataForAddrReg)
-		return 0xffffffff;
-	GT_REG_READ (pci_configuration_data[host], &data);
-	return data;
-}
-
-/********************************************************************
-* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
-*                               the agent is placed on another Bus. For more
-*                               information read P2P in the PCI spec.
-*
-* Inputs:   unsigned int regOffset - The register offset as it apears in the
-*           GT spec (or any other PCI device spec).
-*           unsigned int pciDevNum - The device number needs to be addressed.
-*           unsigned int busNum - On which bus does the Target agent connect
-*                                 to.
-*           unsigned int data - data to be written.
-*
-*  Configuration Address 0xCF8:
-*
-*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
-*  |congif|Reserved|  Bus |Device|Function|Register|01|
-*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
-*
-*  The configuration Address is configure as type-I (bits[1:0] = '01') due to
-*   PCI spec referring to P2P.
-*
-*********************************************************************/
-void pciOverBridgeWriteConfigReg (PCI_HOST host,
-				  unsigned int regOffset,
-				  unsigned int pciDevNum,
-				  unsigned int busNum, unsigned int data)
-{
-	unsigned int DataForReg;
-	unsigned int functionNum;
-
-	functionNum = regOffset & 0x00000700;
-	pciDevNum = pciDevNum << 11;
-	regOffset = regOffset & 0xff;
-	busNum = busNum << 16;
-	if (pciDevNum == SELF) {	/* This board */
-		DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
-	} else {
-		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
-			BIT31 | BIT0;
-	}
-	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
-	GT_REG_WRITE (pci_configuration_data[host], data);
-}
-
-
-/********************************************************************
-* pciOverBridgeReadConfigReg  - Read from a PCIn configuration register where
-*                               the agent target locate on another PCI bus.
-*                             - Make sure the GT is configured as a master
-*                               before reading from another device on the PCI.
-*                             - The function takes care of Big/Little endian
-*                               conversion.
-* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
-*                        spec). (configuration register offset.)
-*           pciDevNum: The device number needs to be addressed.
-*           busNum: the Bus number where the agent is place.
-* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
-*                 cause register to make sure the data is valid
-*
-*  Configuration Address 0xCF8:
-*
-*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
-*  |congif|Reserved|  Bus |Device|Function|Register|01|
-*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
-*
-*********************************************************************/
-unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
-					 unsigned int regOffset,
-					 unsigned int pciDevNum,
-					 unsigned int busNum)
-{
-	unsigned int DataForReg;
-	unsigned int data;
-	unsigned int functionNum;
-
-	functionNum = regOffset & 0x00000700;
-	pciDevNum = pciDevNum << 11;
-	regOffset = regOffset & 0xff;
-	busNum = busNum << 16;
-	if (pciDevNum == SELF) {	/* This board */
-		DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
-	} else {		/* agent on another bus */
-
-		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
-			BIT0 | BIT31;
-	}
-	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
-	GT_REG_READ (pci_configuration_data[host], &data);
-	return data;
-}
-
-
-/********************************************************************
-* pciGetRegOffset - Gets the register offset for this region config.
-*
-* INPUT:   Bus, Region - The bus and region we ask for its base address.
-* OUTPUT:   N/A
-* RETURNS: PCI register base address
-*********************************************************************/
-static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
-{
-	switch (host) {
-	case PCI_HOST0:
-		switch (region) {
-		case PCI_IO:
-			return PCI_0I_O_LOW_DECODE_ADDRESS;
-		case PCI_REGION0:
-			return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
-		case PCI_REGION1:
-			return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
-		case PCI_REGION2:
-			return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
-		case PCI_REGION3:
-			return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
-		}
-	case PCI_HOST1:
-		switch (region) {
-		case PCI_IO:
-			return PCI_1I_O_LOW_DECODE_ADDRESS;
-		case PCI_REGION0:
-			return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
-		case PCI_REGION1:
-			return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
-		case PCI_REGION2:
-			return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
-		case PCI_REGION3:
-			return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
-		}
-	}
-	return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
-}
-
-static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
-{
-	switch (host) {
-	case PCI_HOST0:
-		switch (region) {
-		case PCI_IO:
-			return PCI_0I_O_ADDRESS_REMAP;
-		case PCI_REGION0:
-			return PCI_0MEMORY0_ADDRESS_REMAP;
-		case PCI_REGION1:
-			return PCI_0MEMORY1_ADDRESS_REMAP;
-		case PCI_REGION2:
-			return PCI_0MEMORY2_ADDRESS_REMAP;
-		case PCI_REGION3:
-			return PCI_0MEMORY3_ADDRESS_REMAP;
-		}
-	case PCI_HOST1:
-		switch (region) {
-		case PCI_IO:
-			return PCI_1I_O_ADDRESS_REMAP;
-		case PCI_REGION0:
-			return PCI_1MEMORY0_ADDRESS_REMAP;
-		case PCI_REGION1:
-			return PCI_1MEMORY1_ADDRESS_REMAP;
-		case PCI_REGION2:
-			return PCI_1MEMORY2_ADDRESS_REMAP;
-		case PCI_REGION3:
-			return PCI_1MEMORY3_ADDRESS_REMAP;
-		}
-	}
-	return PCI_0MEMORY0_ADDRESS_REMAP;
-}
-
-/********************************************************************
-* pciGetBaseAddress - Gets the base address of a PCI.
-*           - If the PCI size is 0 then this base address has no meaning!!!
-*
-*
-* INPUT:   Bus, Region - The bus and region we ask for its base address.
-* OUTPUT:   N/A
-* RETURNS: PCI base address.
-*********************************************************************/
-unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
-{
-	unsigned int regBase;
-	unsigned int regEnd;
-	unsigned int regOffset = pciGetRegOffset (host, region);
-
-	GT_REG_READ (regOffset, &regBase);
-	GT_REG_READ (regOffset + 8, &regEnd);
-
-	if (regEnd <= regBase)
-		return 0xffffffff;	/* ERROR !!! */
-
-	regBase = regBase << 16;
-	return regBase;
-}
-
-bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
-		  unsigned int bankBase, unsigned int bankLength)
-{
-	unsigned int low = 0xfff;
-	unsigned int high = 0x0;
-	unsigned int regOffset = pciGetRegOffset (host, region);
-	unsigned int remapOffset = pciGetRemapOffset (host, region);
-
-	if (bankLength != 0) {
-		low = (bankBase >> 16) & 0xffff;
-		high = ((bankBase + bankLength) >> 16) - 1;
-	}
-
-	GT_REG_WRITE (regOffset, low | (1 << 24));	/* no swapping */
-	GT_REG_WRITE (regOffset + 8, high);
-
-	if (bankLength != 0) {	/* must do AFTER writing maps */
-		GT_REG_WRITE (remapOffset, remapBase >> 16);	/* sorry, 32 bits only.
-								   dont support upper 32
-								   in this driver */
-	}
-	return true;
-}
-
-unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
-{
-	unsigned int low;
-	unsigned int regOffset = pciGetRegOffset (host, region);
-
-	GT_REG_READ (regOffset, &low);
-	return (low & 0xffff) << 16;
-}
-
-unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
-{
-	unsigned int low, high;
-	unsigned int regOffset = pciGetRegOffset (host, region);
-
-	GT_REG_READ (regOffset, &low);
-	GT_REG_READ (regOffset + 8, &high);
-	return ((high & 0xffff) + 1) << 16;
-}
-
-
-/* ronen - 7/Dec/03*/
-/********************************************************************
-* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
-* Inputs: one of the PCI BAR
-*********************************************************************/
-void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
-{
-	RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
-}
-
-void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
-{
-	SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
-}
-
-/********************************************************************
-* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
-*
-* Inputs: base and size of PCI SCS
-*********************************************************************/
-void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
-		       unsigned int pciDramBase, unsigned int pciDramSize)
-{
-	/*ronen different function for 3rd bank. */
-	unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
-
-	pciDramBase = pciDramBase & 0xfffff000;
-	pciDramBase = pciDramBase | (pciReadConfigReg (host,
-						       PCI_SCS_0_BASE_ADDRESS
-						       + offset,
-						       SELF) & 0x00000fff);
-	pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
-			   pciDramBase);
-	if (pciDramSize == 0)
-		pciDramSize++;
-	GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
-	gtPciEnableInternalBAR (host, bank);
-}
-
-/********************************************************************
-* pciSetRegionFeatures - This function modifys one of the 8 regions with
-*                         feature bits given as an input.
-*                       - Be advised to check the spec before modifying them.
-* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
-*         unsigned int features - See file: pci.h there are defintion for those
-*                                 region features.
-*         unsigned int baseAddress - The region base Address.
-*         unsigned int topAddress - The region top Address.
-* Returns: false if one of the parameters is erroneous true otherwise.
-*********************************************************************/
-bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
-			   unsigned int features, unsigned int baseAddress,
-			   unsigned int regionLength)
-{
-	unsigned int accessLow;
-	unsigned int accessHigh;
-	unsigned int accessTop = baseAddress + regionLength;
-
-	if (regionLength == 0) {	/* close the region. */
-		pciDisableAccessRegion (host, region);
-		return true;
-	}
-	/* base Address is store is bits [11:0] */
-	accessLow = (baseAddress & 0xfff00000) >> 20;
-	/* All the features are update according to the defines in pci.h (to be on
-	   the safe side we disable bits: [11:0] */
-	accessLow = accessLow | (features & 0xfffff000);
-	/* write to the Low Access Region register */
-	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
-		      accessLow);
-
-	accessHigh = (accessTop & 0xfff00000) >> 20;
-
-	/* write to the High Access Region register */
-	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
-		      accessHigh - 1);
-	return true;
-}
-
-/********************************************************************
-* pciDisableAccessRegion - Disable The given Region by writing MAX size
-*                           to its low Address and MIN size to its high Address.
-*
-* Inputs:   PCI_ACCESS_REGIONS region - The region we to be Disabled.
-* Returns:  N/A.
-*********************************************************************/
-void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
-{
-	/* writing back the registers default values. */
-	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
-		      0x01001fff);
-	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
-}
-
-/********************************************************************
-* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
-*
-* Inputs:   N/A
-* Returns:  true.
-*********************************************************************/
-bool pciArbiterEnable (PCI_HOST host)
-{
-	unsigned int regData;
-
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
-	return true;
-}
-
-/********************************************************************
-* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
-*
-* Inputs:   N/A
-* Returns:  true
-*********************************************************************/
-bool pciArbiterDisable (PCI_HOST host)
-{
-	unsigned int regData;
-
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
-	return true;
-}
-
-/********************************************************************
-* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
-*
-* Inputs:   PCI_AGENT_PRIO internalAgent - priotity for internal agent.
-*           PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
-*           PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
-*           PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
-*           PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
-*           PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
-*           PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
-* Returns:  true
-*********************************************************************/
-bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
-				  PCI_AGENT_PRIO externalAgent0,
-				  PCI_AGENT_PRIO externalAgent1,
-				  PCI_AGENT_PRIO externalAgent2,
-				  PCI_AGENT_PRIO externalAgent3,
-				  PCI_AGENT_PRIO externalAgent4,
-				  PCI_AGENT_PRIO externalAgent5)
-{
-	unsigned int regData;
-	unsigned int writeData;
-
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	writeData = (internalAgent << 7) + (externalAgent0 << 8) +
-		(externalAgent1 << 9) + (externalAgent2 << 10) +
-		(externalAgent3 << 11) + (externalAgent4 << 12) +
-		(externalAgent5 << 13);
-	regData = (regData & 0xffffc07f) | writeData;
-	GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
-	return true;
-}
-
-/********************************************************************
-* pciParkingDisable - Park on last option disable, with this function you can
-*                      disable the park on last mechanism for each agent.
-*                      disabling this option for all agents results parking
-*                      on the internal master.
-*
-* Inputs: PCI_AGENT_PARK internalAgent -  parking Disable for internal agent.
-*         PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
-*         PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
-*         PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
-*         PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
-*         PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
-*         PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
-* Returns:  true
-*********************************************************************/
-bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
-			PCI_AGENT_PARK externalAgent0,
-			PCI_AGENT_PARK externalAgent1,
-			PCI_AGENT_PARK externalAgent2,
-			PCI_AGENT_PARK externalAgent3,
-			PCI_AGENT_PARK externalAgent4,
-			PCI_AGENT_PARK externalAgent5)
-{
-	unsigned int regData;
-	unsigned int writeData;
-
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	writeData = (internalAgent << 14) + (externalAgent0 << 15) +
-		(externalAgent1 << 16) + (externalAgent2 << 17) +
-		(externalAgent3 << 18) + (externalAgent4 << 19) +
-		(externalAgent5 << 20);
-	regData = (regData & ~(0x7f << 14)) | writeData;
-	GT_REG_WRITE (pci_arbiter_control[host], regData);
-	return true;
-}
-
-/********************************************************************
-* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
-*                       respond to grant assertion within a window specified in
-*                       the input value: 'brokenValue'.
-*
-* Inputs: unsigned char brokenValue -  A value which limits the Master to hold the
-*                       grant without asserting frame.
-* Returns:  Error for illegal broken value otherwise true.
-*********************************************************************/
-bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
-{
-	unsigned int data;
-	unsigned int regData;
-
-	if (brokenValue > 0xf)
-		return false;	/* brokenValue must be 4 bit */
-	data = brokenValue << 3;
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	regData = (regData & 0xffffff87) | data;
-	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
-	return true;
-}
-
-/********************************************************************
-* pciDisableBrokenAgentDetection - This function disable the Broken agent
-*                           Detection mechanism.
-*                           NOTE: This operation may cause a dead lock on the
-*                           pci0 arbitration.
-*
-* Inputs:   N/A
-* Returns:  true.
-*********************************************************************/
-bool pciDisableBrokenAgentDetection (PCI_HOST host)
-{
-	unsigned int regData;
-
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	regData = regData & 0xfffffffd;
-	GT_REG_WRITE (pci_arbiter_control[host], regData);
-	return true;
-}
-
-/********************************************************************
-* pciP2PConfig - This function set the PCI_n P2P configurate.
-*                 For more information on the P2P read PCI spec.
-*
-* Inputs:  unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
-*                                      Boundry.
-*          unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
-*                                      Boundry.
-*          unsigned int busNum - The CPI bus number to which the PCI interface
-*                                      is connected.
-*          unsigned int devNum - The PCI interface's device number.
-*
-* Returns:  true.
-*********************************************************************/
-bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
-		   unsigned int SecondBusHigh,
-		   unsigned int busNum, unsigned int devNum)
-{
-	unsigned int regData;
-
-	regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
-		((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
-	GT_REG_WRITE (pci_p2p_configuration[host], regData);
-	return true;
-}
-
-/********************************************************************
-* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
-*                          supports Cache Coherency in the PCI_n interface.
-* Inputs: region - One of the four regions.
-*         snoopType - There is four optional Types:
-*                        1. No Snoop.
-*                        2. Snoop to WT region.
-*                        3. Snoop to WB region.
-*                        4. Snoop & Invalidate to WB region.
-*         baseAddress - Base Address of this region.
-*         regionLength - Region length.
-* Returns: false if one of the parameters is wrong otherwise return true.
-*********************************************************************/
-bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
-			    PCI_SNOOP_TYPE snoopType,
-			    unsigned int baseAddress,
-			    unsigned int regionLength)
-{
-	unsigned int snoopXbaseAddress;
-	unsigned int snoopXtopAddress;
-	unsigned int data;
-	unsigned int snoopHigh = baseAddress + regionLength;
-
-	if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
-		return false;
-	snoopXbaseAddress =
-		pci_snoop_control_base_0_low[host] + 0x10 * region;
-	snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
-	if (regionLength == 0) {	/* closing the region */
-		GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
-		GT_REG_WRITE (snoopXtopAddress, 0);
-		return true;
-	}
-	baseAddress = baseAddress & 0xfff00000;	/* Granularity of 1MByte */
-	data = (baseAddress >> 20) | snoopType << 12;
-	GT_REG_WRITE (snoopXbaseAddress, data);
-	snoopHigh = (snoopHigh & 0xfff00000) >> 20;
-	GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
-	return true;
-}
-
-static int gt_read_config_dword (struct pci_controller *hose,
-				 pci_dev_t dev, int offset, u32 * value)
-{
-	int bus = PCI_BUS (dev);
-
-	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
-		*value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
-					   PCI_DEV (dev));
-	} else {
-		*value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
-						     cfg_addr, offset,
-						     PCI_DEV (dev), bus);
-	}
-
-	return 0;
-}
-
-static int gt_write_config_dword (struct pci_controller *hose,
-				  pci_dev_t dev, int offset, u32 value)
-{
-	int bus = PCI_BUS (dev);
-
-	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
-		pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
-				   PCI_DEV (dev), value);
-	} else {
-		pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
-					     offset, PCI_DEV (dev), bus,
-					     value);
-	}
-	return 0;
-}
-
-
-static void gt_setup_ide (struct pci_controller *hose,
-			  pci_dev_t dev, struct pci_config_table *entry)
-{
-	static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
-	u32 bar_response, bar_value;
-	int bar;
-
-	for (bar = 0; bar < 6; bar++) {
-		/*ronen different function for 3rd bank. */
-		unsigned int offset =
-			(bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
-
-		pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
-					0x0);
-		pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
-				       &bar_response);
-
-		pciauto_region_allocate (bar_response &
-					 PCI_BASE_ADDRESS_SPACE_IO ? hose->
-					 pci_io : hose->pci_mem, ide_bar[bar],
-					 &bar_value);
-
-		pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
-					bar_value);
-	}
-}
-
-
-/* TODO BJW: Change this for DB64360. This was pulled from the EV64260  */
-/* and is curently not called *. */
-#if 0
-static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
-{
-	unsigned char pin, irq;
-
-	pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
-
-	if (pin == 1) {		/* only allow INT A */
-		irq = pci_irq_swizzle[(PCI_HOST) hose->
-				      cfg_addr][PCI_DEV (dev)];
-		if (irq)
-			pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
-	}
-}
-#endif
-
-struct pci_config_table gt_config_table[] = {
-	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
-	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
-
-	{}
-};
-
-struct pci_controller pci0_hose = {
-/*    fixup_irq: gt_fixup_irq, */
-	config_table:gt_config_table,
-};
-
-struct pci_controller pci1_hose = {
-/*    fixup_irq: gt_fixup_irq, */
-	config_table:gt_config_table,
-};
-
-void pci_init_board (void)
-{
-	unsigned int command;
-
-#ifdef DEBUG
-	gt_pci_bus_mode_display (PCI_HOST0);
-#endif
-
-	pci0_hose.first_busno = 0;
-	pci0_hose.last_busno = 0xff;
-	local_buses[0] = pci0_hose.first_busno;
-
-	/* PCI memory space */
-	pci_set_region (pci0_hose.regions + 0,
-			CFG_PCI0_0_MEM_SPACE,
-			CFG_PCI0_0_MEM_SPACE,
-			CFG_PCI0_MEM_SIZE, PCI_REGION_MEM);
-
-	/* PCI I/O space */
-	pci_set_region (pci0_hose.regions + 1,
-			CFG_PCI0_IO_SPACE_PCI,
-			CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO);
-
-	pci_set_ops (&pci0_hose,
-		     pci_hose_read_config_byte_via_dword,
-		     pci_hose_read_config_word_via_dword,
-		     gt_read_config_dword,
-		     pci_hose_write_config_byte_via_dword,
-		     pci_hose_write_config_word_via_dword,
-		     gt_write_config_dword);
-	pci0_hose.region_count = 2;
-
-	pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
-
-	pci_register_hose (&pci0_hose);
-	pciArbiterEnable (PCI_HOST0);
-	pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
-	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
-	command |= PCI_COMMAND_MASTER;
-	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
-	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
-	command |= PCI_COMMAND_MEMORY;
-	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
-
-	pci0_hose.last_busno = pci_hose_scan (&pci0_hose);
-
-#ifdef DEBUG
-	gt_pci_bus_mode_display (PCI_HOST1);
-#endif
-	pci1_hose.first_busno = pci0_hose.last_busno + 1;
-	pci1_hose.last_busno = 0xff;
-	pci1_hose.current_busno = pci1_hose.first_busno;
-	local_buses[1] = pci1_hose.first_busno;
-
-	/* PCI memory space */
-	pci_set_region (pci1_hose.regions + 0,
-			CFG_PCI1_0_MEM_SPACE,
-			CFG_PCI1_0_MEM_SPACE,
-			CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
-
-	/* PCI I/O space */
-	pci_set_region (pci1_hose.regions + 1,
-			CFG_PCI1_IO_SPACE_PCI,
-			CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
-
-	pci_set_ops (&pci1_hose,
-		     pci_hose_read_config_byte_via_dword,
-		     pci_hose_read_config_word_via_dword,
-		     gt_read_config_dword,
-		     pci_hose_write_config_byte_via_dword,
-		     pci_hose_write_config_word_via_dword,
-		     gt_write_config_dword);
-
-	pci1_hose.region_count = 2;
-
-	pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
-
-	pci_register_hose (&pci1_hose);
-
-	pciArbiterEnable (PCI_HOST1);
-	pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
-
-	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
-	command |= PCI_COMMAND_MASTER;
-	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
-
-	pci1_hose.last_busno = pci_hose_scan (&pci1_hose);
-
-	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
-	command |= PCI_COMMAND_MEMORY;
-	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
-
-}

board/Marvell/db64360/u-boot.lds

@@ -1,135 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
- */
-
-OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .interp : { *(.interp) }
-  .hash          : { *(.hash)		}
-  .dynsym        : { *(.dynsym)		}
-  .dynstr        : { *(.dynstr)		}
-  .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
-  .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
-  .rel.got       : { *(.rel.got)		}
-  .rela.got      : { *(.rela.got)		}
-  .rel.ctors     : { *(.rel.ctors)	}
-  .rela.ctors    : { *(.rela.ctors)	}
-  .rel.dtors     : { *(.rel.dtors)	}
-  .rela.dtors    : { *(.rela.dtors)	}
-  .rel.bss       : { *(.rel.bss)		}
-  .rela.bss      : { *(.rela.bss)		}
-  .rel.plt       : { *(.rel.plt)		}
-  .rela.plt      : { *(.rela.plt)		}
-  .init          : { *(.init)	}
-  .plt : { *(.plt) }
-  .text      :
-  {
-    cpu/74xx_7xx/start.o	(.text)
-
-/* store the environment in a seperate sector in the boot flash */
-/*    . = env_offset; */
-/*    common/environment.o(.text) */
-
-    *(.text)
-    *(.fixup)
-    *(.got1)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(.rodata)
-    *(.rodata1)
-    *(.rodata.str1.4)
-  }
-  .fini      : { *(.fini)    } =0
-  .ctors     : { *(.ctors)   }
-  .dtors     : { *(.dtors)   }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x00FF) & 0xFFFFFF00;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    *(.got)
-    _GOT2_TABLE_ = .;
-    *(.got2)
-    _FIXUP_TABLE_ = .;
-    *(.fixup)
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data)
-    *(.data1)
-    *(.sdata)
-    *(.sdata2)
-    *(.dynamic)
-    CONSTRUCTORS
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss       :
-  {
-   *(.sbss) *(.scommon)
-   *(.dynbss)
-   *(.bss)
-   *(COMMON)
-  }
-  _end = . ;
-  PROVIDE (end = .);
-}

board/Marvell/db64460/64460.h

@@ -1,52 +0,0 @@
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * main board support/init for the Galileo Eval board DB64460.
- */
-
-#ifndef __64460_H__
-#define __64460_H__
-
-/* CPU Configuration bits */
-#define CPU_CONF_ADDR_MISS_EN	(1 << 8)
-#define	CPU_CONF_SINGLE_CPU	(1 << 11)
-#define	CPU_CONF_ENDIANESS	(1 << 12)
-#define CPU_CONF_PIPELINE	(1 << 13)
-#define CPU_CONF_STOP_RETRY	(1 << 17)
-#define CPU_CONF_MULTI_DECODE	(1 << 18)
-#define CPU_CONF_DP_VALID	(1 << 19)
-#define CPU_CONF_PERR_PROP	(1 << 22)
-#define CPU_CONF_AACK_DELAY_2	(1 << 25)
-#define CPU_CONF_AP_VALID	(1 << 26)
-#define CPU_CONF_REMAP_WR_DIS	(1 << 27)
-
-/* CPU Master Control bits */
-#define CPU_MAST_CTL_ARB_EN	(1 << 8)
-#define CPU_MAST_CTL_MASK_BR_1	(1 << 9)
-#define CPU_MAST_CTL_M_WR_TRIG	(1 << 10)
-#define CPU_MAST_CTL_M_RD_TRIG	(1 << 11)
-#define CPU_MAST_CTL_CLEAN_BLK	(1 << 12)
-#define CPU_MAST_CTL_FLUSH_BLK	(1 << 13)
-
-#endif /* __64460_H__ */

board/Marvell/db64460/Makefile

@@ -1,44 +0,0 @@
-#
-# (C) Copyright 2001
-# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= lib$(BOARD).a
-
-SOBJS	= ../common/misc.o
-
-OBJS	= $(BOARD).o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \
-	  mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \
-	  sdram_init.o ../common/intel_flash.o
-
-$(LIB):	.depend $(OBJS) $(SOBJS)
-	$(AR) crv $@ $(OBJS) $(SOBJS)
-
-#########################################################################
-
-.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
-		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-
-sinclude .depend
-
-#########################################################################

board/Marvell/db64460/config.mk

@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2001
-# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# EVB64460 boards
-#
-
-TEXT_BASE = 0xfff00000

board/Marvell/db64460/db64460.c

@@ -1,936 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * modifications for the DB64460 eval board based by Ingo.Assmus@keymile.com
- */
-
-/*
- * db64460.c - main board support/init for the Galileo Eval board.
- */
-
-#include <common.h>
-#include <74xx_7xx.h>
-#include "../include/memory.h"
-#include "../include/pci.h"
-#include "../include/mv_gen_reg.h"
-#include <net.h>
-
-#include "eth.h"
-#include "mpsc.h"
-#include "i2c.h"
-#include "64460.h"
-#include "mv_regs.h"
-
-#undef	DEBUG
-/*#define	DEBUG */
-
-#define	MAP_PCI
-
-#ifdef DEBUG
-#define DP(x) x
-#else
-#define DP(x)
-#endif
-
-extern void flush_data_cache (void);
-extern void invalidate_l1_instruction_cache (void);
-
-/* ------------------------------------------------------------------------- */
-
-/* this is the current GT register space location */
-/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
-
-/* Unfortunately, we cant change it while we are in flash, so we initialize it
- * to the "final" value. This means that any debug_led calls before
- * board_early_init_f wont work right (like in cpu_init_f).
- * See also my_remap_gt_regs below. (NTL)
- */
-
-void board_prebootm_init (void);
-unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
-int display_mem_map (void);
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * This is a version of the GT register space remapping function that
- * doesn't touch globals (meaning, it's ok to run from flash.)
- *
- * Unfortunately, this has the side effect that a writable
- * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
- */
-
-void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
-{
-	u32 temp;
-
-	/* check and see if it's already moved */
-
-/* original ppcboot 1.1.6 source
-
-	temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
-	if ((temp & 0xffff) == new_loc >> 20)
-		return;
-
-	temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
-		0xffff0000) | (new_loc >> 20);
-
-	out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
-
-	while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
-original ppcboot 1.1.6 source end */
-
-	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
-	if ((temp & 0xffff) == new_loc >> 16)
-		return;
-
-	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
-		0xffff0000) | (new_loc >> 16);
-
-	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
-
-	while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
-}
-
-#ifdef CONFIG_PCI
-
-static void gt_pci_config (void)
-{
-	unsigned int stat;
-	unsigned int val = 0x00fff864;	/* DINK32: BusNum 23:16,  DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
-
-	/* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
-	 * config registers by writing ones to the bus and device.
-	 * We then update the Virtual register with the correct value for the bus and device.
-	 */
-	if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
-		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
-
-		GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
-
-		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
-		GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
-			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
-
-	}
-	if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
-		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
-		GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
-
-		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
-		GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
-			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
-	}
-
-	/* Enable master */
-	PCI_MASTER_ENABLE (0, SELF);
-	PCI_MASTER_ENABLE (1, SELF);
-
-	/* Enable PCI0/1 Mem0 and IO 0 disable all others */
-	GT_REG_READ (BASE_ADDR_ENABLE, &stat);
-	stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
-									     <<
-									     18);
-	stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
-	GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
-
-	/* ronen- add write to pci remap registers for 64460.
-	   in 64360 when writing to pci base go and overide remap automaticaly,
-	   in 64460 it doesn't */
-	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16);
-
-	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16);
-
-	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16);
-
-	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16);
-
-	/* PCI interface settings */
-	/* Timeout set to retry forever */
-	GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
-	GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
-
-	/* ronen - enable only CS0 and Internal reg!! */
-	GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
-	GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
-
-/*ronen update the pci internal registers base address.*/
-#ifdef MAP_PCI
-	for (stat = 0; stat <= PCI_HOST1; stat++)
-		pciWriteConfigReg (stat,
-				   PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
-				   SELF, CFG_GT_REGS);
-#endif
-
-}
-#endif
-
-/* Setup CPU interface paramaters */
-static void gt_cpu_config (void)
-{
-	cpu_t cpu = get_cpu_type ();
-	ulong tmp;
-
-	/* cpu configuration register */
-	tmp = GTREGREAD (CPU_CONFIGURATION);
-
-	/* set the SINGLE_CPU bit  see MV64460 P.399 */
-#ifndef CFG_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
-	tmp |= CPU_CONF_SINGLE_CPU;
-#endif
-
-	tmp &= ~CPU_CONF_AACK_DELAY_2;
-
-	tmp |= CPU_CONF_DP_VALID;
-	tmp |= CPU_CONF_AP_VALID;
-
-	tmp |= CPU_CONF_PIPELINE;
-
-	GT_REG_WRITE (CPU_CONFIGURATION, tmp);	/* Marvell (VXWorks) writes 0x20220FF */
-
-	/* CPU master control register */
-	tmp = GTREGREAD (CPU_MASTER_CONTROL);
-
-	tmp |= CPU_MAST_CTL_ARB_EN;
-
-	if ((cpu == CPU_7400) ||
-	    (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
-
-		tmp |= CPU_MAST_CTL_CLEAN_BLK;
-		tmp |= CPU_MAST_CTL_FLUSH_BLK;
-
-	} else {
-		/* cleanblock must be cleared for CPUs
-		 * that do not support this command (603e, 750)
-		 * see Res#1 */
-		tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
-		tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
-	}
-	GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
-}
-
-/*
- * board_early_init_f.
- *
- * set up gal. device mappings, etc.
- */
-int board_early_init_f (void)
-{
-	uchar sram_boot = 0;
-
-	/*
-	 * set up the GT the way the kernel wants it
-	 * the call to move the GT register space will obviously
-	 * fail if it has already been done, but we're going to assume
-	 * that if it's not at the power-on location, it's where we put
-	 * it last time. (huber)
-	 */
-
-	my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
-
-	/* No PCI in first release of Port To_do: enable it. */
-#ifdef CONFIG_PCI
-	gt_pci_config ();
-#endif
-	/* mask all external interrupt sources */
-	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
-	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
-	/* new in MV6446x */
-	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
-	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
-	/* --------------------- */
-	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
-	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
-	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
-	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
-	/* does not exist in MV6446x
-	   GT_REG_WRITE(CPU_INT_0_MASK, 0);
-	   GT_REG_WRITE(CPU_INT_1_MASK, 0);
-	   GT_REG_WRITE(CPU_INT_2_MASK, 0);
-	   GT_REG_WRITE(CPU_INT_3_MASK, 0);
-	   --------------------- */
-
-
-	/* ----- DEVICE BUS SETTINGS ------ */
-
-	/*
-	 * EVB
-	 * 0 - SRAM   ????
-	 * 1 - RTC      ????
-	 * 2 - UART     ????
-	 * 3 - Flash    checked 32Bit Intel Strata
-	 * boot - BootCS checked 8Bit 29LV040B
-	 *
-	 * Zuma
-	 * 0 - Flash
-	 * boot - BootCS
-	 */
-
-	/*
-	 * the dual 7450 module requires burst access to the boot
-	 * device, so the serial rom copies the boot device to the
-	 * on-board sram on the eval board, and updates the correct
-	 * registers to boot from the sram. (device0)
-	 */
-	if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE)
-		sram_boot = 1;
-	if (!sram_boot)
-		memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
-
-	memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE);
-	memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE);
-	memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE);
-
-
-	/* configure device timing */
-#ifdef CFG_DEV0_PAR		/* set port parameters for SRAM device module access */
-	if (!sram_boot)
-		GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR);
-#endif
-
-#ifdef CFG_DEV1_PAR		/* set port parameters for RTC device module access */
-	GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR);
-#endif
-#ifdef CFG_DEV2_PAR		/* set port parameters for DUART device module access */
-	GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);
-#endif
-
-#ifdef CFG_32BIT_BOOT_PAR	/* set port parameters for Flash device module access */
-	/* detect if we are booting from the 32 bit flash */
-	if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
-		/* 32 bit boot flash */
-		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR);
-		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
-			      CFG_32BIT_BOOT_PAR);
-	} else {
-		/* 8 bit boot flash */
-		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR);
-		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
-	}
-#else
-	/* 8 bit boot flash only */
-/*	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/
-#endif
-
-
-	gt_cpu_config ();
-
-	/* MPP setup */
-	GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0);
-	GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1);
-	GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2);
-	GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3);
-
-	GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
-	DEBUG_LED0_ON ();
-	DEBUG_LED1_ON ();
-	DEBUG_LED2_ON ();
-
-	return 0;
-}
-
-/* various things to do after relocation */
-
-int misc_init_r ()
-{
-	icache_enable ();
-#ifdef CFG_L2
-	l2cache_enable ();
-#endif
-#ifdef CONFIG_MPSC
-
-	mpsc_sdma_init ();
-	mpsc_init2 ();
-#endif
-
-#if 0
-	/* disable the dcache and MMU */
-	dcache_lock ();
-#endif
-	return 0;
-}
-
-void after_reloc (ulong dest_addr, gd_t * gd)
-{
-	/* check to see if we booted from the sram.  If so, move things
-	 * back to the way they should be. (we're running from main
-	 * memory at this point now */
-	if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) {
-		memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
-		memoryMapDeviceSpace (BOOT_DEVICE, CFG_DFL_BOOTCS_BASE, _8M);
-	}
-	display_mem_map ();
-	/* now, jump to the main ppcboot board init code */
-	board_init_r (gd, dest_addr);
-	/* NOTREACHED */
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- *
- * right now, assume borad type. (there is just one...after all)
- */
-
-int checkboard (void)
-{
-	int l_type = 0;
-
-	printf ("BOARD: %s\n", CFG_BOARD_NAME);
-	return (l_type);
-}
-
-/* utility functions */
-void debug_led (int led, int mode)
-{
-	volatile int *addr = 0;
-	int dummy;
-
-	if (mode == 1) {
-		switch (led) {
-		case 0:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
-					0x08000);
-			break;
-
-		case 1:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
-					0x0c000);
-			break;
-
-		case 2:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
-					0x10000);
-			break;
-		}
-	} else if (mode == 0) {
-		switch (led) {
-		case 0:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
-					0x14000);
-			break;
-
-		case 1:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
-					0x18000);
-			break;
-
-		case 2:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
-					0x1c000);
-			break;
-		}
-	}
-
-	dummy = *addr;
-}
-
-int display_mem_map (void)
-{
-	int i, j;
-	unsigned int base, size, width;
-
-	/* SDRAM */
-	printf ("SD (DDR) RAM\n");
-	for (i = 0; i <= BANK3; i++) {
-		base = memoryGetBankBaseAddress (i);
-		size = memoryGetBankSize (i);
-		if (size != 0) {
-			printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
-				i, base, size >> 20);
-		}
-	}
-
-	/* CPU's PCI windows */
-	for (i = 0; i <= PCI_HOST1; i++) {
-		printf ("\nCPU's PCI %d windows\n", i);
-		base = pciGetSpaceBase (i, PCI_IO);
-		size = pciGetSpaceSize (i, PCI_IO);
-		printf ("      IO: base - 0x%08x\tsize - %dM bytes\n", base,
-			size >> 20);
-		for (j = 0;
-		     j <=
-		     PCI_REGION0
-		     /*ronen currently only first PCI MEM is used 3 */ ;
-		     j++) {
-			base = pciGetSpaceBase (i, j);
-			size = pciGetSpaceSize (i, j);
-			printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
-		}
-	}
-
-	/* Devices */
-	printf ("\nDEVICES\n");
-	for (i = 0; i <= DEVICE3; i++) {
-		base = memoryGetDeviceBaseAddress (i);
-		size = memoryGetDeviceSize (i);
-		width = memoryGetDeviceWidth (i) * 8;
-		printf ("DEV %d:  base - 0x%08x  size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
-		if (i == 0)
-			printf ("\t- EXT SRAM (actual - 1M)\n");
-		else if (i == 1)
-			printf ("\t- RTC\n");
-		else if (i == 2)
-			printf ("\t- UART\n");
-		else
-			printf ("\t- LARGE FLASH\n");
-	}
-
-	/* Bootrom */
-	base = memoryGetDeviceBaseAddress (BOOT_DEVICE);	/* Boot */
-	size = memoryGetDeviceSize (BOOT_DEVICE);
-	width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
-	printf (" BOOT:  base - 0x%08x  size - %dM bytes\twidth - %d bits\n",
-		base, size >> 20, width);
-	return (0);
-}
-
-/* DRAM check routines copied from gw8260 */
-
-#if defined (CFG_DRAM_TEST)
-
-/*********************************************************************/
-/* NAME:  move64() -  moves a double word (64-bit)		     */
-/*								     */
-/* DESCRIPTION:							     */
-/*   this function performs a double word move from the data at	     */
-/*   the source pointer to the location at the destination pointer.  */
-/*								     */
-/* INPUTS:							     */
-/*   unsigned long long *src  - pointer to data to move		     */
-/*								     */
-/* OUTPUTS:							     */
-/*   unsigned long long *dest - pointer to locate to move data	     */
-/*								     */
-/* RETURNS:							     */
-/*   None							     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*   May cloober fr0.						     */
-/*								     */
-/*********************************************************************/
-static void move64 (unsigned long long *src, unsigned long long *dest)
-{
-	asm ("lfd  0, 0(3)\n\t"	/* fpr0   =  *scr       */
-	     "stfd 0, 0(4)"	/* *dest  =  fpr0       */
-      : : : "fr0");		/* Clobbers fr0         */
-	return;
-}
-
-
-#if defined (CFG_DRAM_TEST_DATA)
-
-unsigned long long pattern[] = {
-	0xaaaaaaaaaaaaaaaa,
-	0xcccccccccccccccc,
-	0xf0f0f0f0f0f0f0f0,
-	0xff00ff00ff00ff00,
-	0xffff0000ffff0000,
-	0xffffffff00000000,
-	0x00000000ffffffff,
-	0x0000ffff0000ffff,
-	0x00ff00ff00ff00ff,
-	0x0f0f0f0f0f0f0f0f,
-	0x3333333333333333,
-	0x5555555555555555
-};
-
-/*********************************************************************/
-/* NAME:  mem_test_data() -  test data lines for shorts and opens    */
-/*								     */
-/* DESCRIPTION:							     */
-/*   Tests data lines for shorts and opens by forcing adjacent data  */
-/*   to opposite states. Because the data lines could be routed in   */
-/*   an arbitrary manner the must ensure test patterns ensure that   */
-/*   every case is tested. By using the following series of binary   */
-/*   patterns every combination of adjacent bits is test regardless  */
-/*   of routing.						     */
-/*								     */
-/*     ...101010101010101010101010				     */
-/*     ...110011001100110011001100				     */
-/*     ...111100001111000011110000				     */
-/*     ...111111110000000011111111				     */
-/*								     */
-/*   Carrying this out, gives us six hex patterns as follows:	     */
-/*								     */
-/*     0xaaaaaaaaaaaaaaaa					     */
-/*     0xcccccccccccccccc					     */
-/*     0xf0f0f0f0f0f0f0f0					     */
-/*     0xff00ff00ff00ff00					     */
-/*     0xffff0000ffff0000					     */
-/*     0xffffffff00000000					     */
-/*								     */
-/*   The number test patterns will always be given by:		     */
-/*								     */
-/*   log(base 2)(number data bits) = log2 (64) = 6		     */
-/*								     */
-/*   To test for short and opens to other signals on our boards. we  */
-/*   simply							     */
-/*   test with the 1's complemnt of the paterns as well.	     */
-/*								     */
-/* OUTPUTS:							     */
-/*   Displays failing test pattern				     */
-/*								     */
-/* RETURNS:							     */
-/*   0 -  Passed test						     */
-/*   1 -  Failed test						     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*  Assumes only one one SDRAM bank				     */
-/*								     */
-/*********************************************************************/
-int mem_test_data (void)
-{
-	unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
-	unsigned long long temp64;
-	int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
-	int i;
-	unsigned int hi, lo;
-
-	for (i = 0; i < num_patterns; i++) {
-		move64 (&(pattern[i]), pmem);
-		move64 (pmem, &temp64);
-
-		/* hi = (temp64>>32) & 0xffffffff;          */
-		/* lo = temp64 & 0xffffffff;                */
-		/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
-
-		hi = (pattern[i] >> 32) & 0xffffffff;
-		lo = pattern[i] & 0xffffffff;
-		/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo);  */
-
-		if (temp64 != pattern[i]) {
-			printf ("\n   Data Test Failed, pattern 0x%08x%08x",
-				hi, lo);
-			return 1;
-		}
-	}
-
-	return 0;
-}
-#endif /* CFG_DRAM_TEST_DATA */
-
-#if defined (CFG_DRAM_TEST_ADDRESS)
-/*********************************************************************/
-/* NAME:  mem_test_address() -	test address lines		     */
-/*								     */
-/* DESCRIPTION:							     */
-/*   This function performs a test to verify that each word im	     */
-/*   memory is uniquly addressable. The test sequence is as follows: */
-/*								     */
-/*   1) write the address of each word to each word.		     */
-/*   2) verify that each location equals its address		     */
-/*								     */
-/* OUTPUTS:							     */
-/*   Displays failing test pattern and address			     */
-/*								     */
-/* RETURNS:							     */
-/*   0 -  Passed test						     */
-/*   1 -  Failed test						     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*								     */
-/*								     */
-/*********************************************************************/
-int mem_test_address (void)
-{
-	volatile unsigned int *pmem =
-		(volatile unsigned int *) CFG_MEMTEST_START;
-	const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4;
-	unsigned int i;
-
-	/* write address to each location */
-	for (i = 0; i < size; i++) {
-		pmem[i] = i;
-	}
-
-	/* verify each loaction */
-	for (i = 0; i < size; i++) {
-		if (pmem[i] != i) {
-			printf ("\n   Address Test Failed at 0x%x", i);
-			return 1;
-		}
-	}
-	return 0;
-}
-#endif /* CFG_DRAM_TEST_ADDRESS */
-
-#if defined (CFG_DRAM_TEST_WALK)
-/*********************************************************************/
-/* NAME:   mem_march() -  memory march				     */
-/*								     */
-/* DESCRIPTION:							     */
-/*   Marches up through memory. At each location verifies rmask if   */
-/*   read = 1. At each location write wmask if	write = 1. Displays  */
-/*   failing address and pattern.				     */
-/*								     */
-/* INPUTS:							     */
-/*   volatile unsigned long long * base - start address of test	     */
-/*   unsigned int size - number of dwords(64-bit) to test	     */
-/*   unsigned long long rmask - read verify mask		     */
-/*   unsigned long long wmask - wrtie verify mask		     */
-/*   short read - verifies rmask if read = 1			     */
-/*   short write  - writes wmask if write = 1			     */
-/*								     */
-/* OUTPUTS:							     */
-/*   Displays failing test pattern and address			     */
-/*								     */
-/* RETURNS:							     */
-/*   0 -  Passed test						     */
-/*   1 -  Failed test						     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*								     */
-/*								     */
-/*********************************************************************/
-int mem_march (volatile unsigned long long *base,
-	       unsigned int size,
-	       unsigned long long rmask,
-	       unsigned long long wmask, short read, short write)
-{
-	unsigned int i;
-	unsigned long long temp;
-	unsigned int hitemp, lotemp, himask, lomask;
-
-	for (i = 0; i < size; i++) {
-		if (read != 0) {
-			/* temp = base[i]; */
-			move64 ((unsigned long long *) &(base[i]), &temp);
-			if (rmask != temp) {
-				hitemp = (temp >> 32) & 0xffffffff;
-				lotemp = temp & 0xffffffff;
-				himask = (rmask >> 32) & 0xffffffff;
-				lomask = rmask & 0xffffffff;
-
-				printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
-				return 1;
-			}
-		}
-		if (write != 0) {
-			/*  base[i] = wmask; */
-			move64 (&wmask, (unsigned long long *) &(base[i]));
-		}
-	}
-	return 0;
-}
-#endif /* CFG_DRAM_TEST_WALK */
-
-/*********************************************************************/
-/* NAME:   mem_test_walk() -  a simple walking ones test	     */
-/*								     */
-/* DESCRIPTION:							     */
-/*   Performs a walking ones through entire physical memory. The     */
-/*   test uses as series of memory marches, mem_march(), to verify   */
-/*   and write the test patterns to memory. The test sequence is as  */
-/*   follows:							     */
-/*     1) march writing 0000...0001				     */
-/*     2) march verifying 0000...0001  , writing  0000...0010	     */
-/*     3) repeat step 2 shifting masks left 1 bit each time unitl    */
-/*	   the write mask equals 1000...0000			     */
-/*     4) march verifying 1000...0000				     */
-/*   The test fails if any of the memory marches return a failure.   */
-/*								     */
-/* OUTPUTS:							     */
-/*   Displays which pass on the memory test is executing	     */
-/*								     */
-/* RETURNS:							     */
-/*   0 -  Passed test						     */
-/*   1 -  Failed test						     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*								     */
-/*								     */
-/*********************************************************************/
-int mem_test_walk (void)
-{
-	unsigned long long mask;
-	volatile unsigned long long *pmem =
-		(volatile unsigned long long *) CFG_MEMTEST_START;
-	const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8;
-
-	unsigned int i;
-
-	mask = 0x01;
-
-	printf ("Initial Pass");
-	mem_march (pmem, size, 0x0, 0x1, 0, 1);
-
-	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
-	printf ("		");
-	printf ("         ");
-	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
-
-	for (i = 0; i < 63; i++) {
-		printf ("Pass %2d", i + 2);
-		if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
-			/*printf("mask: 0x%x, pass: %d, ", mask, i); */
-			return 1;
-		}
-		mask = mask << 1;
-		printf ("\b\b\b\b\b\b\b");
-	}
-
-	printf ("Last Pass");
-	if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
-		/* printf("mask: 0x%x", mask); */
-		return 1;
-	}
-	printf ("\b\b\b\b\b\b\b\b\b");
-	printf ("	     ");
-	printf ("\b\b\b\b\b\b\b\b\b");
-
-	return 0;
-}
-
-/*********************************************************************/
-/* NAME:    testdram() -  calls any enabled memory tests	     */
-/*								     */
-/* DESCRIPTION:							     */
-/*   Runs memory tests if the environment test variables are set to  */
-/*   'y'.							     */
-/*								     */
-/* INPUTS:							     */
-/*   testdramdata    - If set to 'y', data test is run.		     */
-/*   testdramaddress - If set to 'y', address test is run.	     */
-/*   testdramwalk    - If set to 'y', walking ones test is run	     */
-/*								     */
-/* OUTPUTS:							     */
-/*   None							     */
-/*								     */
-/* RETURNS:							     */
-/*   0 -  Passed test						     */
-/*   1 -  Failed test						     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*								     */
-/*								     */
-/*********************************************************************/
-int testdram (void)
-{
-	char *s;
-	int rundata, runaddress, runwalk;
-
-	s = getenv ("testdramdata");
-	rundata = (s && (*s == 'y')) ? 1 : 0;
-	s = getenv ("testdramaddress");
-	runaddress = (s && (*s == 'y')) ? 1 : 0;
-	s = getenv ("testdramwalk");
-	runwalk = (s && (*s == 'y')) ? 1 : 0;
-
-/*    rundata = 1; */
-/*    runaddress = 0; */
-/*    runwalk = 0; */
-
-	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
-		printf ("Testing RAM from 0x%08x to 0x%08x ...  (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END);
-	}
-#ifdef CFG_DRAM_TEST_DATA
-	if (rundata == 1) {
-		printf ("Test DATA ...  ");
-		if (mem_test_data () == 1) {
-			printf ("failed \n");
-			return 1;
-		} else
-			printf ("ok \n");
-	}
-#endif
-#ifdef CFG_DRAM_TEST_ADDRESS
-	if (runaddress == 1) {
-		printf ("Test ADDRESS ...  ");
-		if (mem_test_address () == 1) {
-			printf ("failed \n");
-			return 1;
-		} else
-			printf ("ok \n");
-	}
-#endif
-#ifdef CFG_DRAM_TEST_WALK
-	if (runwalk == 1) {
-		printf ("Test WALKING ONEs ...  ");
-		if (mem_test_walk () == 1) {
-			printf ("failed \n");
-			return 1;
-		} else
-			printf ("ok \n");
-	}
-#endif
-	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
-		printf ("passed\n");
-	}
-	return 0;
-
-}
-#endif /* CFG_DRAM_TEST */
-
-/* ronen - the below functions are used by the bootm function           */
-/*  - we map the base register to fbe00000 (same mapping as in the LSP) */
-/*  - we turn off the RX gig dmas - to prevent the dma from overunning  */
-/*    the kernel data areas.                                            */
-/*  - we diable and invalidate the icache and dcache.                   */
-void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
-{
-	u32 temp;
-
-	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
-	if ((temp & 0xffff) == new_loc >> 16)
-		return;
-
-	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
-		0xffff0000) | (new_loc >> 16);
-
-	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
-
-	while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
-							new_loc |
-							(INTERNAL_SPACE_DECODE)))))
-	       != temp);
-
-}
-
-void board_prebootm_init ()
-{
-
-/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
-		GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
-
-/* Stop GigE Rx DMA engines */
-	GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
-	GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00);
-	GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00);
-
-/* Relocate MV64460 internal regs */
-	my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM);
-
-	icache_disable ();
-	invalidate_l1_instruction_cache ();
-	flush_data_cache ();
-	dcache_disable ();
-}

board/Marvell/db64460/eth.h

@@ -1,41 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * eth.h - header file for the polled mode GT ethernet driver
- */
-
-#ifndef __EVB64460_ETH_H__
-#define __EVB64460_ETH_H__
-
-#include <asm/types.h>
-#include <asm/io.h>
-#include <asm/byteorder.h>
-#include <common.h>
-
-int db64460_eth0_poll(void);
-int db64460_eth0_transmit(unsigned int s, volatile char *p);
-void db64460_eth0_disable(void);
-bool network_start(bd_t *bis);
-
-#endif /* __EVB64460_ETH_H__ */

board/Marvell/db64460/mpsc.h

@@ -1,156 +0,0 @@
-/*
- * (C) Copyright 2001
- * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*************************************************************************
- * changes for Marvell DB64460 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
- *
-  ************************************************************************/
-
-
-/*
- * mpsc.h - header file for MPSC in uart mode (console driver)
- */
-
-#ifndef __MPSC_H__
-#define __MPSC_H__
-
-/* include actual Galileo defines */
-#include "../include/mv_gen_reg.h"
-
-/* driver related defines */
-
-int mpsc_init(int baud);
-void mpsc_sdma_init(void);
-void mpsc_init2(void);
-int galbrg_set_baudrate(int channel, int rate);
-
-int mpsc_putchar_early(char ch);
-char mpsc_getchar_debug(void);
-int mpsc_test_char_debug(void);
-
-int mpsc_test_char_sdma(void);
-
-extern int (*mpsc_putchar)(char ch);
-extern char (*mpsc_getchar)(void);
-extern int (*mpsc_test_char)(void);
-
-#define CHANNEL CONFIG_MPSC_PORT
-
-#define TX_DESC     5
-#define RX_DESC     20
-
-#define DESC_FIRST  0x00010000
-#define DESC_LAST   0x00020000
-#define DESC_OWNER_BIT  0x80000000
-
-#define TX_DEMAND   0x00800000
-#define TX_STOP     0x00010000
-#define RX_ENABLE   0x00000080
-
-#define SDMA_RX_ABORT 		  (1 << 15)
-#define SDMA_TX_ABORT 		  (1 << 31)
-#define MPSC_TX_ABORT 		  (1 << 7)
-#define MPSC_RX_ABORT             (1 << 23)
-#define MPSC_ENTER_HUNT           (1 << 31)
-
-/* MPSC defines */
-
-#define GALMPSC_CONNECT            0x1
-#define GALMPSC_DISCONNECT         0x0
-
-#define GALMPSC_UART               0x1
-
-#define GALMPSC_STOP_BITS_1        0x0
-#define GALMPSC_STOP_BITS_2        0x1
-#define GALMPSC_CHAR_LENGTH_8      0x3
-#define GALMPSC_CHAR_LENGTH_7      0x2
-
-#define GALMPSC_PARITY_ODD         0x0
-#define GALMPSC_PARITY_EVEN        0x2
-#define GALMPSC_PARITY_MARK        0x3
-#define GALMPSC_PARITY_SPACE       0x1
-#define GALMPSC_PARITY_NONE        -1
-
-#define GALMPSC_SERIAL_MULTIPLEX   SERIAL_PORT_MULTIPLEX           /* 0xf010 */
-#define GALMPSC_ROUTING_REGISTER   MAIN_ROUTING_REGISTER           /* 0xb400 */
-#define GALMPSC_RxC_ROUTE          RECEIVE_CLOCK_ROUTING_REGISTER  /* 0xb404 */
-#define GALMPSC_TxC_ROUTE          TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
-#define GALMPSC_MCONF_LOW          MPSC0_MAIN_CONFIGURATION_LOW    /* 0x8000 */
-#define GALMPSC_MCONF_HIGH         MPSC0_MAIN_CONFIGURATION_HIGH   /* 0x8004 */
-#define GALMPSC_PROTOCONF_REG      MPSC0_PROTOCOL_CONFIGURATION    /* 0x8008 */
-
-#define GALMPSC_REG_GAP            0x1000
-
-#define GALMPSC_MCONF_CHREG_BASE   CHANNEL0_REGISTER1  /* 0x800c */
-#define GALMPSC_CHANNELREG_1       CHANNEL0_REGISTER1  /* 0x800c */
-#define GALMPSC_CHANNELREG_2       CHANNEL0_REGISTER2  /* 0x8010 */
-#define GALMPSC_CHANNELREG_3       CHANNEL0_REGISTER3  /* 0x8014 */
-#define GALMPSC_CHANNELREG_4       CHANNEL0_REGISTER4  /* 0x8018 */
-#define GALMPSC_CHANNELREG_5       CHANNEL0_REGISTER5  /* 0x801c */
-#define GALMPSC_CHANNELREG_6       CHANNEL0_REGISTER6  /* 0x8020 */
-#define GALMPSC_CHANNELREG_7       CHANNEL0_REGISTER7  /* 0x8024 */
-#define GALMPSC_CHANNELREG_8       CHANNEL0_REGISTER8  /* 0x8028 */
-#define GALMPSC_CHANNELREG_9       CHANNEL0_REGISTER9  /* 0x802c */
-#define GALMPSC_CHANNELREG_10      CHANNEL0_REGISTER10 /* 0x8030 */
-#define GALMPSC_CHANNELREG_11      CHANNEL0_REGISTER11 /* 0x8034 */
-
-#define GALSDMA_COMMAND_FIRST     (1 << 16)
-#define GALSDMA_COMMAND_LAST      (1 << 17)
-#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
-#define GALSDMA_COMMAND_AUTO      (1 << 30)
-#define GALSDMA_COMMAND_OWNER     (1 << 31)
-
-#define GALSDMA_RX                 0
-#define GALSDMA_TX                 1
-
-/* CHANNEL2 should be CHANNEL1, according to documentation,
- * but to work with the current GTREGS file...
- */
-#define GALSDMA_0_CONF_REG         CHANNEL0_CONFIGURATION_REGISTER   /* 0x4000 */
-#define GALSDMA_1_CONF_REG         CHANNEL2_CONFIGURATION_REGISTER   /* 0x6000 */
-#define GALSDMA_0_COM_REG          CHANNEL0_COMMAND_REGISTER         /* 0x4008 */
-#define GALSDMA_1_COM_REG          CHANNEL2_COMMAND_REGISTER         /* 0x6008 */
-#define GALSDMA_0_CUR_RX_PTR       CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x4810 */
-#define GALSDMA_0_CUR_TX_PTR       CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x4c10 */
-#define GALSDMA_0_FIR_TX_PTR       CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER    /* 0x4c14 */
-#define GALSDMA_1_CUR_RX_PTR       CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x6810 */
-#define GALSDMA_1_CUR_TX_PTR       CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x6c10 */
-#define GALSDMA_1_FIR_TX_PTR       CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER    /* 0x6c14 */
-#define GALSDMA_REG_DIFF           0x2000
-
-/* WRONG in gt64260R.h */
-#define GALSDMA_INT_CAUSE          0xb800   /* SDMA_CAUSE */
-#define GALSDMA_INT_MASK           0xb880   /* SDMA_MASK  */
-#define GALMPSC_0_INT_CAUSE        0xb804
-#define GALMPSC_0_INT_MASK         0xb884
-
-#define GALSDMA_MODE_UART          0
-#define GALSDMA_MODE_BISYNC        1
-#define GALSDMA_MODE_HDLC          2
-#define GALSDMA_MODE_TRANSPARENT   3
-
-#define GALBRG_0_CONFREG           BRG0_CONFIGURATION_REGISTER  /*  0xb200  */
-#define GALBRG_REG_GAP             0x0008
-#define GALBRG_0_BTREG             BRG0_BAUDE_TUNING_REGISTER   /*  0xb204  */
-
-#endif /* __MPSC_H__ */

board/Marvell/db64460/mv_eth.h

@@ -1,840 +0,0 @@
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * based on - Driver for MV64460X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * mv_eth.h - header file for the polled mode GT ethernet driver
- */
-
-#ifndef __DB64460_ETH_H__
-#define __DB64460_ETH_H__
-
-#include <asm/types.h>
-#include <asm/io.h>
-#include <asm/byteorder.h>
-#include <common.h>
-#include <net.h>
-#include "mv_regs.h"
-#include "../common/ppc_error_no.h"
-
-
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-*  The first part is the high level driver of the gigE ethernet ports.	 *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-
-/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
-#ifndef MAX_SKB_FRAGS
-#define MAX_SKB_FRAGS 0
-#endif
-
-/* Port attributes */
-/*#define MAX_RX_QUEUE_NUM	8*/
-/*#define MAX_TX_QUEUE_NUM	8*/
-#define MAX_RX_QUEUE_NUM	1
-#define MAX_TX_QUEUE_NUM	1
-
-
-/* Use one TX queue and one RX queue */
-#define MV64460_TX_QUEUE_NUM 1
-#define MV64460_RX_QUEUE_NUM 1
-
-/*
- * Number of RX / TX descriptors on RX / TX rings.
- * Note that allocating RX descriptors is done by allocating the RX
- * ring AND a preallocated RX buffers (skb's) for each descriptor.
- * The TX descriptors only allocates the TX descriptors ring,
- * with no pre allocated TX buffers (skb's are allocated by higher layers.
- */
-
-/* Default TX ring size is 10 descriptors */
-#ifdef CONFIG_MV64460_ETH_TXQUEUE_SIZE
-#define MV64460_TX_QUEUE_SIZE CONFIG_MV64460_ETH_TXQUEUE_SIZE
-#else
-#define MV64460_TX_QUEUE_SIZE 4
-#endif
-
-/* Default RX ring size is 4 descriptors */
-#ifdef	CONFIG_MV64460_ETH_RXQUEUE_SIZE
-#define MV64460_RX_QUEUE_SIZE CONFIG_MV64460_ETH_RXQUEUE_SIZE
-#else
-#define MV64460_RX_QUEUE_SIZE 4
-#endif
-
-#ifdef CONFIG_RX_BUFFER_SIZE
-#define MV64460_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
-#else
-#define MV64460_RX_BUFFER_SIZE 1600
-#endif
-
-#ifdef CONFIG_TX_BUFFER_SIZE
-#define MV64460_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
-#else
-#define MV64460_TX_BUFFER_SIZE 1600
-#endif
-
-/*
- *	Network device statistics. Akin to the 2.0 ether stats but
- *	with byte counters.
- */
-
-struct net_device_stats
-{
-	unsigned long	rx_packets;		/* total packets received	*/
-	unsigned long	tx_packets;		/* total packets transmitted	*/
-	unsigned long	rx_bytes;		/* total bytes received		*/
-	unsigned long	tx_bytes;		/* total bytes transmitted	*/
-	unsigned long	rx_errors;		/* bad packets received		*/
-	unsigned long	tx_errors;		/* packet transmit problems	*/
-	unsigned long	rx_dropped;		/* no space in linux buffers	*/
-	unsigned long	tx_dropped;		/* no space available in linux	*/
-	unsigned long	multicast;		/* multicast packets received	*/
-	unsigned long	collisions;
-
-	/* detailed rx_errors: */
-	unsigned long	rx_length_errors;
-	unsigned long	rx_over_errors;		/* receiver ring buff overflow	*/
-	unsigned long	rx_crc_errors;		/* recved pkt with crc error	*/
-	unsigned long	rx_frame_errors;	/* recv'd frame alignment error */
-	unsigned long	rx_fifo_errors;		/* recv'r fifo overrun		*/
-	unsigned long	rx_missed_errors;	/* receiver missed packet	*/
-
-	/* detailed tx_errors */
-	unsigned long	tx_aborted_errors;
-	unsigned long	tx_carrier_errors;
-	unsigned long	tx_fifo_errors;
-	unsigned long	tx_heartbeat_errors;
-	unsigned long	tx_window_errors;
-
-	/* for cslip etc */
-	unsigned long	rx_compressed;
-	unsigned long	tx_compressed;
-};
-
-
-/* Private data structure used for ethernet device */
-struct mv64460_eth_priv {
-    unsigned int port_num;
-    struct net_device_stats *stats;
-
-/* to buffer area aligned */
-    char * p_eth_tx_buffer[MV64460_TX_QUEUE_SIZE+1];	/*pointers to alligned tx buffs in memory space */
-    char * p_eth_rx_buffer[MV64460_RX_QUEUE_SIZE+1];	/*pointers to allinged rx buffs in memory space */
-
-    /* Size of Tx Ring per queue */
-    unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
-
-
-    /* Size of Rx Ring per queue */
-    unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
-
-    /* Magic Number for Ethernet running */
-    unsigned int eth_running;
-
-};
-
-int mv64460_eth_init (struct eth_device *dev);
-int mv64460_eth_stop (struct eth_device *dev);
-int mv64460_eth_start_xmit (struct eth_device*, volatile void* packet, int length);
-/*	return db64460_eth0_poll(); */
-
-int mv64460_eth_open (struct eth_device *dev);
-
-
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-*  The second part is the low level driver of the gigE ethernet ports.	 *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-
-
-/********************************************************************************
- * Header File for : MV-643xx network interface header
- *
- * DESCRIPTION:
- *	 This header file contains macros typedefs and function declaration for
- *	 the Marvell Gig Bit Ethernet Controller.
- *
- * DEPENDENCIES:
- *	 None.
- *
- *******************************************************************************/
-
-
-#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
-#ifdef CONFIG_MV64460_SRAM_CACHEABLE
-/* In case SRAM is cacheable but not cache coherent */
-#define D_CACHE_FLUSH_LINE(addr, offset)       \
-{		    \
-  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
-}
-#else
-/* In case SRAM is cache coherent or non-cacheable */
-#define D_CACHE_FLUSH_LINE(addr, offset) ;
-#endif
-#else
-#ifdef CONFIG_NOT_COHERENT_CACHE
-/* In case of descriptors on DDR but not cache coherent */
-#define D_CACHE_FLUSH_LINE(addr, offset)       \
-{		    \
-  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
-}
-#else
-/* In case of descriptors on DDR and cache coherent */
-#define D_CACHE_FLUSH_LINE(addr, offset) ;
-#endif /* CONFIG_NOT_COHERENT_CACHE */
-#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
-
-
-#define CPU_PIPE_FLUSH		   \
-{		  \
-  __asm__ __volatile__ ("eieio");	  \
-}
-
-
-/* defines  */
-
-/* Default port configuration value */
-#define PORT_CONFIG_VALUE			\
-	     ETH_UNICAST_NORMAL_MODE		|   \
-	     ETH_DEFAULT_RX_QUEUE_0		|   \
-	     ETH_DEFAULT_RX_ARP_QUEUE_0		|   \
-	     ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP	|   \
-	     ETH_RECEIVE_BC_IF_IP		|   \
-	     ETH_RECEIVE_BC_IF_ARP		|   \
-	     ETH_CAPTURE_TCP_FRAMES_DIS		|   \
-	     ETH_CAPTURE_UDP_FRAMES_DIS		|   \
-	     ETH_DEFAULT_RX_TCP_QUEUE_0		|   \
-	     ETH_DEFAULT_RX_UDP_QUEUE_0		|   \
-	     ETH_DEFAULT_RX_BPDU_QUEUE_0
-
-/* Default port extend configuration value */
-#define PORT_CONFIG_EXTEND_VALUE		\
-	     ETH_SPAN_BPDU_PACKETS_AS_NORMAL	|   \
-	     ETH_PARTITION_DISABLE
-
-
-/* Default sdma control value */
-#ifdef CONFIG_NOT_COHERENT_CACHE
-#define PORT_SDMA_CONFIG_VALUE				\
-			 ETH_RX_BURST_SIZE_16_64BIT	|	\
-			 GT_ETH_IPG_INT_RX(0)			|	\
-			 ETH_TX_BURST_SIZE_16_64BIT;
-#else
-#define PORT_SDMA_CONFIG_VALUE			\
-			 ETH_RX_BURST_SIZE_4_64BIT	|	\
-			 GT_ETH_IPG_INT_RX(0)			|	\
-			 ETH_TX_BURST_SIZE_4_64BIT;
-#endif
-
-#define GT_ETH_IPG_INT_RX(value)		\
-	    ((value & 0x3fff) << 8)
-
-/* Default port serial control value */
-#define PORT_SERIAL_CONTROL_VALUE			    \
-			ETH_FORCE_LINK_PASS			|	\
-			ETH_ENABLE_AUTO_NEG_FOR_DUPLX		|	\
-			ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL	|	\
-			ETH_ADV_SYMMETRIC_FLOW_CTRL		|	\
-			ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX	|	\
-			ETH_FORCE_BP_MODE_NO_JAM		|	\
-			BIT9					|	\
-			ETH_DO_NOT_FORCE_LINK_FAIL		|	\
-			ETH_RETRANSMIT_16_ETTEMPTS		|	\
-			ETH_ENABLE_AUTO_NEG_SPEED_GMII		|	\
-			ETH_DTE_ADV_0				|	\
-			ETH_DISABLE_AUTO_NEG_BYPASS		|	\
-			ETH_AUTO_NEG_NO_CHANGE			|	\
-			ETH_MAX_RX_PACKET_1552BYTE		|	\
-			ETH_CLR_EXT_LOOPBACK			|	\
-			ETH_SET_FULL_DUPLEX_MODE		|	\
-			ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
-
-#define RX_BUFFER_MAX_SIZE  0xFFFF
-#define TX_BUFFER_MAX_SIZE  0xFFFF   /* Buffer are limited to 64k */
-
-#define RX_BUFFER_MIN_SIZE  0x8
-#define TX_BUFFER_MIN_SIZE  0x8
-
-/* Tx WRR confoguration macros */
-#define PORT_MAX_TRAN_UNIT	    0x24    /* MTU register (default) 9KByte */
-#define PORT_MAX_TOKEN_BUCKET_SIZE  0x_fFFF  /* PMTBS register (default)      */
-#define PORT_TOKEN_RATE		    1023    /* PTTBRC register (default)     */
-
-/* MAC accepet/reject macros */
-#define ACCEPT_MAC_ADDR	    0
-#define REJECT_MAC_ADDR	    1
-
-/* Size of a Tx/Rx descriptor used in chain list data structure */
-#define RX_DESC_ALIGNED_SIZE		0x20
-#define TX_DESC_ALIGNED_SIZE		0x20
-
-/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
-#define TX_BUF_OFFSET_IN_DESC	    0x18
-/* Buffer offset from buffer pointer */
-#define RX_BUF_OFFSET				0x2
-
-/* Gap define */
-#define ETH_BAR_GAP					0x8
-#define ETH_SIZE_REG_GAP				0x8
-#define ETH_HIGH_ADDR_REMAP_REG_GAP			0x4
-#define ETH_PORT_ACCESS_CTRL_GAP			0x4
-
-/* Gigabit Ethernet Unit Global Registers */
-
-/* MIB Counters register definitions */
-#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW   0x0
-#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH  0x4
-#define ETH_MIB_BAD_OCTETS_RECEIVED	   0x8
-#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR  0xc
-#define ETH_MIB_GOOD_FRAMES_RECEIVED	   0x10
-#define ETH_MIB_BAD_FRAMES_RECEIVED	   0x14
-#define ETH_MIB_BROADCAST_FRAMES_RECEIVED  0x18
-#define ETH_MIB_MULTICAST_FRAMES_RECEIVED  0x1c
-#define ETH_MIB_FRAMES_64_OCTETS	   0x20
-#define ETH_MIB_FRAMES_65_TO_127_OCTETS	   0x24
-#define ETH_MIB_FRAMES_128_TO_255_OCTETS   0x28
-#define ETH_MIB_FRAMES_256_TO_511_OCTETS   0x2c
-#define ETH_MIB_FRAMES_512_TO_1023_OCTETS  0x30
-#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS  0x34
-#define ETH_MIB_GOOD_OCTETS_SENT_LOW	   0x38
-#define ETH_MIB_GOOD_OCTETS_SENT_HIGH	   0x3c
-#define ETH_MIB_GOOD_FRAMES_SENT	   0x40
-#define ETH_MIB_EXCESSIVE_COLLISION	   0x44
-#define ETH_MIB_MULTICAST_FRAMES_SENT	   0x48
-#define ETH_MIB_BROADCAST_FRAMES_SENT	   0x4c
-#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
-#define ETH_MIB_FC_SENT			   0x54
-#define ETH_MIB_GOOD_FC_RECEIVED	   0x58
-#define ETH_MIB_BAD_FC_RECEIVED		   0x5c
-#define ETH_MIB_UNDERSIZE_RECEIVED	   0x60
-#define ETH_MIB_FRAGMENTS_RECEIVED	   0x64
-#define ETH_MIB_OVERSIZE_RECEIVED	   0x68
-#define ETH_MIB_JABBER_RECEIVED		   0x6c
-#define ETH_MIB_MAC_RECEIVE_ERROR	   0x70
-#define ETH_MIB_BAD_CRC_EVENT		   0x74
-#define ETH_MIB_COLLISION		   0x78
-#define ETH_MIB_LATE_COLLISION		   0x7c
-
-/* Port serial status reg (PSR) */
-#define ETH_INTERFACE_GMII_MII				0
-#define ETH_INTERFACE_PCM				BIT0
-#define ETH_LINK_IS_DOWN				0
-#define ETH_LINK_IS_UP					BIT1
-#define ETH_PORT_AT_HALF_DUPLEX				0
-#define ETH_PORT_AT_FULL_DUPLEX				BIT2
-#define ETH_RX_FLOW_CTRL_DISABLED			0
-#define ETH_RX_FLOW_CTRL_ENBALED			BIT3
-#define ETH_GMII_SPEED_100_10				0
-#define ETH_GMII_SPEED_1000				BIT4
-#define ETH_MII_SPEED_10				0
-#define ETH_MII_SPEED_100				BIT5
-#define ETH_NO_TX					0
-#define ETH_TX_IN_PROGRESS				BIT7
-#define ETH_BYPASS_NO_ACTIVE				0
-#define ETH_BYPASS_ACTIVE				BIT8
-#define ETH_PORT_NOT_AT_PARTITION_STATE			0
-#define ETH_PORT_AT_PARTITION_STATE			BIT9
-#define ETH_PORT_TX_FIFO_NOT_EMPTY			0
-#define ETH_PORT_TX_FIFO_EMPTY				BIT10
-
-
-/* These macros describes the Port configuration reg (Px_cR) bits */
-#define ETH_UNICAST_NORMAL_MODE				0
-#define ETH_UNICAST_PROMISCUOUS_MODE			BIT0
-#define ETH_DEFAULT_RX_QUEUE_0				0
-#define ETH_DEFAULT_RX_QUEUE_1				BIT1
-#define ETH_DEFAULT_RX_QUEUE_2				BIT2
-#define ETH_DEFAULT_RX_QUEUE_3				(BIT2 | BIT1)
-#define ETH_DEFAULT_RX_QUEUE_4				BIT3
-#define ETH_DEFAULT_RX_QUEUE_5				(BIT3 | BIT1)
-#define ETH_DEFAULT_RX_QUEUE_6				(BIT3 | BIT2)
-#define ETH_DEFAULT_RX_QUEUE_7				(BIT3 | BIT2 | BIT1)
-#define ETH_DEFAULT_RX_ARP_QUEUE_0			0
-#define ETH_DEFAULT_RX_ARP_QUEUE_1			BIT4
-#define ETH_DEFAULT_RX_ARP_QUEUE_2			BIT5
-#define ETH_DEFAULT_RX_ARP_QUEUE_3			(BIT5 | BIT4)
-#define ETH_DEFAULT_RX_ARP_QUEUE_4			BIT6
-#define ETH_DEFAULT_RX_ARP_QUEUE_5			(BIT6 | BIT4)
-#define ETH_DEFAULT_RX_ARP_QUEUE_6			(BIT6 | BIT5)
-#define ETH_DEFAULT_RX_ARP_QUEUE_7			(BIT6 | BIT5 | BIT4)
-#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP			0
-#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP			BIT7
-#define ETH_RECEIVE_BC_IF_IP				0
-#define ETH_REJECT_BC_IF_IP				BIT8
-#define ETH_RECEIVE_BC_IF_ARP				0
-#define ETH_REJECT_BC_IF_ARP				BIT9
-#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY		BIT12
-#define ETH_CAPTURE_TCP_FRAMES_DIS			0
-#define ETH_CAPTURE_TCP_FRAMES_EN			BIT14
-#define ETH_CAPTURE_UDP_FRAMES_DIS			0
-#define ETH_CAPTURE_UDP_FRAMES_EN			BIT15
-#define ETH_DEFAULT_RX_TCP_QUEUE_0			0
-#define ETH_DEFAULT_RX_TCP_QUEUE_1			BIT16
-#define ETH_DEFAULT_RX_TCP_QUEUE_2			BIT17
-#define ETH_DEFAULT_RX_TCP_QUEUE_3			(BIT17 | BIT16)
-#define ETH_DEFAULT_RX_TCP_QUEUE_4			BIT18
-#define ETH_DEFAULT_RX_TCP_QUEUE_5			(BIT18 | BIT16)
-#define ETH_DEFAULT_RX_TCP_QUEUE_6			(BIT18 | BIT17)
-#define ETH_DEFAULT_RX_TCP_QUEUE_7			(BIT18 | BIT17 | BIT16)
-#define ETH_DEFAULT_RX_UDP_QUEUE_0			0
-#define ETH_DEFAULT_RX_UDP_QUEUE_1			BIT19
-#define ETH_DEFAULT_RX_UDP_QUEUE_2			BIT20
-#define ETH_DEFAULT_RX_UDP_QUEUE_3			(BIT20 | BIT19)
-#define ETH_DEFAULT_RX_UDP_QUEUE_4			(BIT21
-#define ETH_DEFAULT_RX_UDP_QUEUE_5			(BIT21 | BIT19)
-#define ETH_DEFAULT_RX_UDP_QUEUE_6			(BIT21 | BIT20)
-#define ETH_DEFAULT_RX_UDP_QUEUE_7			(BIT21 | BIT20 | BIT19)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_0			 0
-#define ETH_DEFAULT_RX_BPDU_QUEUE_1			BIT22
-#define ETH_DEFAULT_RX_BPDU_QUEUE_2			BIT23
-#define ETH_DEFAULT_RX_BPDU_QUEUE_3			(BIT23 | BIT22)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_4			BIT24
-#define ETH_DEFAULT_RX_BPDU_QUEUE_5			(BIT24 | BIT22)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_6			(BIT24 | BIT23)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_7			(BIT24 | BIT23 | BIT22)
-
-
-/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
-#define ETH_CLASSIFY_EN					BIT0
-#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL			0
-#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7		BIT1
-#define ETH_PARTITION_DISABLE				0
-#define ETH_PARTITION_ENABLE				BIT2
-
-
-/* Tx/Rx queue command reg (RQCR/TQCR)*/
-#define ETH_QUEUE_0_ENABLE				BIT0
-#define ETH_QUEUE_1_ENABLE				BIT1
-#define ETH_QUEUE_2_ENABLE				BIT2
-#define ETH_QUEUE_3_ENABLE				BIT3
-#define ETH_QUEUE_4_ENABLE				BIT4
-#define ETH_QUEUE_5_ENABLE				BIT5
-#define ETH_QUEUE_6_ENABLE				BIT6
-#define ETH_QUEUE_7_ENABLE				BIT7
-#define ETH_QUEUE_0_DISABLE				BIT8
-#define ETH_QUEUE_1_DISABLE				BIT9
-#define ETH_QUEUE_2_DISABLE				BIT10
-#define ETH_QUEUE_3_DISABLE				BIT11
-#define ETH_QUEUE_4_DISABLE				BIT12
-#define ETH_QUEUE_5_DISABLE				BIT13
-#define ETH_QUEUE_6_DISABLE				BIT14
-#define ETH_QUEUE_7_DISABLE				BIT15
-
-/* These macros describes the Port Sdma configuration reg (SDCR) bits */
-#define ETH_RIFB					BIT0
-#define ETH_RX_BURST_SIZE_1_64BIT			0
-#define ETH_RX_BURST_SIZE_2_64BIT			BIT1
-#define ETH_RX_BURST_SIZE_4_64BIT			BIT2
-#define ETH_RX_BURST_SIZE_8_64BIT			(BIT2 | BIT1)
-#define ETH_RX_BURST_SIZE_16_64BIT			BIT3
-#define ETH_BLM_RX_NO_SWAP				BIT4
-#define ETH_BLM_RX_BYTE_SWAP				0
-#define ETH_BLM_TX_NO_SWAP				BIT5
-#define ETH_BLM_TX_BYTE_SWAP				0
-#define ETH_DESCRIPTORS_BYTE_SWAP			BIT6
-#define ETH_DESCRIPTORS_NO_SWAP				0
-#define ETH_TX_BURST_SIZE_1_64BIT			0
-#define ETH_TX_BURST_SIZE_2_64BIT			BIT22
-#define ETH_TX_BURST_SIZE_4_64BIT			BIT23
-#define ETH_TX_BURST_SIZE_8_64BIT			(BIT23 | BIT22)
-#define ETH_TX_BURST_SIZE_16_64BIT			BIT24
-
-/* These macros describes the Port serial control reg (PSCR) bits */
-#define ETH_SERIAL_PORT_DISABLE				0
-#define ETH_SERIAL_PORT_ENABLE				BIT0
-#define ETH_FORCE_LINK_PASS				BIT1
-#define ETH_DO_NOT_FORCE_LINK_PASS			0
-#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX			0
-#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX			BIT2
-#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL		0
-#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL		BIT3
-#define ETH_ADV_NO_FLOW_CTRL				0
-#define ETH_ADV_SYMMETRIC_FLOW_CTRL			BIT4
-#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX		0
-#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS			BIT5
-#define ETH_FORCE_BP_MODE_NO_JAM			0
-#define ETH_FORCE_BP_MODE_JAM_TX			BIT7
-#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR		BIT8
-#define ETH_FORCE_LINK_FAIL				0
-#define ETH_DO_NOT_FORCE_LINK_FAIL			BIT10
-#define ETH_RETRANSMIT_16_ETTEMPTS			0
-#define ETH_RETRANSMIT_FOREVER				BIT11
-#define ETH_DISABLE_AUTO_NEG_SPEED_GMII			BIT13
-#define ETH_ENABLE_AUTO_NEG_SPEED_GMII			0
-#define ETH_DTE_ADV_0					0
-#define ETH_DTE_ADV_1					BIT14
-#define ETH_DISABLE_AUTO_NEG_BYPASS			0
-#define ETH_ENABLE_AUTO_NEG_BYPASS			BIT15
-#define ETH_AUTO_NEG_NO_CHANGE				0
-#define ETH_RESTART_AUTO_NEG				BIT16
-#define ETH_MAX_RX_PACKET_1518BYTE			0
-#define ETH_MAX_RX_PACKET_1522BYTE			BIT17
-#define ETH_MAX_RX_PACKET_1552BYTE			BIT18
-#define ETH_MAX_RX_PACKET_9022BYTE			(BIT18 | BIT17)
-#define ETH_MAX_RX_PACKET_9192BYTE			BIT19
-#define ETH_MAX_RX_PACKET_9700BYTE			(BIT19 | BIT17)
-#define ETH_SET_EXT_LOOPBACK				BIT20
-#define ETH_CLR_EXT_LOOPBACK				0
-#define ETH_SET_FULL_DUPLEX_MODE			BIT21
-#define ETH_SET_HALF_DUPLEX_MODE			0
-#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	BIT22
-#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	0
-#define ETH_SET_GMII_SPEED_TO_10_100			0
-#define ETH_SET_GMII_SPEED_TO_1000			BIT23
-#define ETH_SET_MII_SPEED_TO_10				0
-#define ETH_SET_MII_SPEED_TO_100			BIT24
-
-
-/* SMI reg */
-#define ETH_SMI_BUSY		BIT28	/* 0 - Write, 1 - Read		*/
-#define ETH_SMI_READ_VALID	BIT27	/* 0 - Write, 1 - Read		*/
-#define ETH_SMI_OPCODE_WRITE	0	/* Completion of Read operation */
-#define ETH_SMI_OPCODE_READ	BIT26	/* Operation is in progress		*/
-
-/* SDMA command status fields macros */
-
-/* Tx & Rx descriptors status */
-#define ETH_ERROR_SUMMARY		    (BIT0)
-
-/* Tx & Rx descriptors command */
-#define ETH_BUFFER_OWNED_BY_DMA		    (BIT31)
-
-/* Tx descriptors status */
-#define ETH_LC_ERROR			    (0	  )
-#define ETH_UR_ERROR			    (BIT1 )
-#define ETH_RL_ERROR			    (BIT2 )
-#define ETH_LLC_SNAP_FORMAT		    (BIT9 )
-
-/* Rx descriptors status */
-#define ETH_CRC_ERROR			    (0	  )
-#define ETH_OVERRUN_ERROR		    (BIT1 )
-#define ETH_MAX_FRAME_LENGTH_ERROR	    (BIT2 )
-#define ETH_RESOURCE_ERROR		    ((BIT2 | BIT1))
-#define ETH_VLAN_TAGGED			    (BIT19)
-#define ETH_BPDU_FRAME			    (BIT20)
-#define ETH_TCP_FRAME_OVER_IP_V_4	    (0	  )
-#define ETH_UDP_FRAME_OVER_IP_V_4	    (BIT21)
-#define ETH_OTHER_FRAME_TYPE		    (BIT22)
-#define ETH_LAYER_2_IS_ETH_V_2		    (BIT23)
-#define ETH_FRAME_TYPE_IP_V_4		    (BIT24)
-#define ETH_FRAME_HEADER_OK		    (BIT25)
-#define ETH_RX_LAST_DESC		    (BIT26)
-#define ETH_RX_FIRST_DESC		    (BIT27)
-#define ETH_UNKNOWN_DESTINATION_ADDR	    (BIT28)
-#define ETH_RX_ENABLE_INTERRUPT		    (BIT29)
-#define ETH_LAYER_4_CHECKSUM_OK		    (BIT30)
-
-/* Rx descriptors byte count */
-#define ETH_FRAME_FRAGMENTED		    (BIT2)
-
-/* Tx descriptors command */
-#define ETH_LAYER_4_CHECKSUM_FIRST_DESC		(BIT10)
-#define ETH_FRAME_SET_TO_VLAN		    (BIT15)
-#define ETH_TCP_FRAME			    (0	  )
-#define ETH_UDP_FRAME			    (BIT16)
-#define ETH_GEN_TCP_UDP_CHECKSUM	    (BIT17)
-#define ETH_GEN_IP_V_4_CHECKSUM		    (BIT18)
-#define ETH_ZERO_PADDING		    (BIT19)
-#define ETH_TX_LAST_DESC		    (BIT20)
-#define ETH_TX_FIRST_DESC		    (BIT21)
-#define ETH_GEN_CRC			    (BIT22)
-#define ETH_TX_ENABLE_INTERRUPT		    (BIT23)
-#define ETH_AUTO_MODE			    (BIT30)
-
-/* Address decode parameters */
-/* Ethernet Base Address Register bits */
-#define EBAR_TARGET_DRAM					0x00000000
-#define EBAR_TARGET_DEVICE					0x00000001
-#define EBAR_TARGET_CBS						0x00000002
-#define EBAR_TARGET_PCI0					0x00000003
-#define EBAR_TARGET_PCI1					0x00000004
-#define EBAR_TARGET_CUNIT					0x00000005
-#define EBAR_TARGET_AUNIT					0x00000006
-#define EBAR_TARGET_GUNIT					0x00000007
-
-/* Window attributes */
-#define EBAR_ATTR_DRAM_CS0					0x00000E00
-#define EBAR_ATTR_DRAM_CS1					0x00000D00
-#define EBAR_ATTR_DRAM_CS2					0x00000B00
-#define EBAR_ATTR_DRAM_CS3					0x00000700
-
-/* DRAM Target interface */
-#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY	0x00000000
-#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT	0x00001000
-#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB	0x00002000
-
-/* Device Bus Target interface */
-#define EBAR_ATTR_DEVICE_DEVCS0				0x00001E00
-#define EBAR_ATTR_DEVICE_DEVCS1				0x00001D00
-#define EBAR_ATTR_DEVICE_DEVCS2				0x00001B00
-#define EBAR_ATTR_DEVICE_DEVCS3				0x00001700
-#define EBAR_ATTR_DEVICE_BOOTCS3			0x00000F00
-
-/* PCI Target interface */
-#define EBAR_ATTR_PCI_BYTE_SWAP				0x00000000
-#define EBAR_ATTR_PCI_NO_SWAP				0x00000100
-#define EBAR_ATTR_PCI_BYTE_WORD_SWAP		0x00000200
-#define EBAR_ATTR_PCI_WORD_SWAP				0x00000300
-#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT	0x00000000
-#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT		0x00000400
-#define EBAR_ATTR_PCI_IO_SPACE				0x00000000
-#define EBAR_ATTR_PCI_MEMORY_SPACE			0x00000800
-#define EBAR_ATTR_PCI_REQ64_FORCE			0x00000000
-#define EBAR_ATTR_PCI_REQ64_SIZE			0x00001000
-
-/* CPU 60x bus or internal SRAM interface */
-#define EBAR_ATTR_CBS_SRAM_BLOCK0			0x00000000
-#define EBAR_ATTR_CBS_SRAM_BLOCK1			0x00000100
-#define EBAR_ATTR_CBS_SRAM					0x00000000
-#define EBAR_ATTR_CBS_CPU_BUS				0x00000800
-
-/* Window access control */
-#define EWIN_ACCESS_NOT_ALLOWED 0
-#define EWIN_ACCESS_READ_ONLY	BIT0
-#define EWIN_ACCESS_FULL	(BIT1 | BIT0)
-#define EWIN0_ACCESS_MASK		0x0003
-#define EWIN1_ACCESS_MASK		0x000C
-#define EWIN2_ACCESS_MASK		0x0030
-#define EWIN3_ACCESS_MASK		0x00C0
-
-/* typedefs */
-
-typedef enum _eth_port
-{
-    ETH_0 = 0,
-	ETH_1 = 1,
-	ETH_2 = 2
-}ETH_PORT;
-
-typedef enum _eth_func_ret_status
-{
-    ETH_OK,			/* Returned as expected.		    */
-    ETH_ERROR,			/* Fundamental error.			    */
-    ETH_RETRY,			/* Could not process request. Try later.    */
-    ETH_END_OF_JOB,		/* Ring has nothing to process.		    */
-    ETH_QUEUE_FULL,		/* Ring resource error.			    */
-    ETH_QUEUE_LAST_RESOURCE	/* Ring resources about to exhaust.	    */
-}ETH_FUNC_RET_STATUS;
-
-typedef enum _eth_queue
-{
-	ETH_Q0 = 0,
-	ETH_Q1 = 1,
-	ETH_Q2 = 2,
-	ETH_Q3 = 3,
-	ETH_Q4 = 4,
-	ETH_Q5 = 5,
-	ETH_Q6 = 6,
-    ETH_Q7 = 7
-} ETH_QUEUE;
-
-typedef enum _addr_win
-{
-	ETH_WIN0,
-	ETH_WIN1,
-	ETH_WIN2,
-	ETH_WIN3,
-	ETH_WIN4,
-    ETH_WIN5
-} ETH_ADDR_WIN;
-
-typedef enum _eth_target
-{
-	ETH_TARGET_DRAM	 ,
-	ETH_TARGET_DEVICE,
-	ETH_TARGET_CBS	 ,
-	ETH_TARGET_PCI0	 ,
-	ETH_TARGET_PCI1
-}ETH_TARGET;
-
-typedef struct _eth_rx_desc
-{
-	unsigned short	byte_cnt	   ;	/* Descriptor buffer byte count	    */
-	unsigned short	buf_size	   ;	/* Buffer size			    */
-	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
-	unsigned int	next_desc_ptr;	  /* Next descriptor pointer	      */
-	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
-    unsigned int    return_info ;    /* User resource return information */
-} ETH_RX_DESC;
-
-
-typedef struct _eth_tx_desc
-{
-    unsigned short  byte_cnt	   ;	/* Descriptor buffer byte count	    */
-    unsigned short  l4i_chk	   ;	/* CPU provided TCP Checksum	    */
-    unsigned int    cmd_sts	   ;	/* Descriptor command status	    */
-    unsigned int    next_desc_ptr;    /* Next descriptor pointer	  */
-    unsigned int    buf_ptr	   ;	/* Descriptor buffer pointer	    */
-    unsigned int    return_info ;    /* User resource return information */
-} ETH_TX_DESC;
-
-/* Unified struct for Rx and Tx operations. The user is not required to */
-/* be familier with neither Tx nor Rx descriptors.			 */
-typedef struct _pkt_info
-{
-	unsigned short	byte_cnt   ;	/* Descriptor buffer byte count	    */
-	unsigned short	l4i_chk	   ;	/* Tx CPU provided TCP Checksum	    */
-	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
-	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
-    unsigned int    return_info ;    /* User resource return information */
-} PKT_INFO;
-
-
-typedef struct _eth_win_param
-{
-    ETH_ADDR_WIN win;	/* Window number. See ETH_ADDR_WIN enum */
-    ETH_TARGET	target;	   /* System targets. See ETH_TARGET enum */
-    unsigned short attributes;	/* BAR attributes. See above macros. */
-    unsigned int base_addr; /* Window base address in unsigned int form */
-    unsigned int high_addr; /* Window high address in unsigned int form */
-    unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
-    bool enable; /* Enable/disable access to the window. */
-    unsigned short access_ctrl; /* Access ctrl register. see above macros */
-} ETH_WIN_PARAM;
-
-
-/* Ethernet port specific infomation */
-
-typedef struct _eth_port_ctrl
-{
-    ETH_PORT  port_num; /* User Ethernet port number */
-    int port_phy_addr;	/* User phy address of Ethrnet port */
-    unsigned char port_mac_addr[6]; /* User defined port MAC address. */
-    unsigned int  port_config; /* User port configuration value */
-    unsigned int  port_config_extend; /* User port config extend value */
-    unsigned int  port_sdma_config; /* User port SDMA config value */
-    unsigned int  port_serial_control; /* User port serial control value */
-    unsigned int  port_tx_queue_command; /* Port active Tx queues summary */
-    unsigned int  port_rx_queue_command; /* Port active Rx queues summary */
-
-    /* User function to cast virtual address to CPU bus address */
-    unsigned int  (*port_virt_to_phys)(unsigned int addr);
-    /* User scratch pad for user specific data structures */
-    void *port_private;
-
-    bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
-    bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
-
-    /* Tx/Rx rings managment indexes fields. For driver use */
-
-    /* Next available Rx resource */
-    volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
-    /* Returning Rx resource */
-    volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
-
-    /* Next available Tx resource */
-    volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
-    /* Returning Tx resource */
-    volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
-    /* An extra Tx index to support transmit of multiple buffers per packet */
-    volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
-
-    /* Tx/Rx rings size and base variables fields. For driver use */
-
-    volatile ETH_RX_DESC	*p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
-    unsigned int		 rx_desc_area_size[MAX_RX_QUEUE_NUM];
-    char			*p_rx_buffer_base[MAX_RX_QUEUE_NUM];
-
-    volatile ETH_TX_DESC	*p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
-    unsigned int		 tx_desc_area_size[MAX_TX_QUEUE_NUM];
-    char			*p_tx_buffer_base[MAX_TX_QUEUE_NUM];
-
-} ETH_PORT_INFO;
-
-
-/* ethernet.h API list */
-
-/* Port operation control routines */
-static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
-static void eth_port_reset(ETH_PORT	eth_port_num);
-static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
-
-
-/* Port MAC address routines */
-static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
-				  unsigned char *p_addr,
-				  ETH_QUEUE queue);
-#if 0	/* FIXME */
-static void eth_port_mc_addr	(ETH_PORT eth_port_num,
-				 unsigned char *p_addr,
-				 ETH_QUEUE queue,
-				 int option);
-#endif
-
-/* PHY and MIB routines */
-static bool ethernet_phy_reset(ETH_PORT eth_port_num);
-
-static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
-				   unsigned int phy_reg,
-				   unsigned int value);
-
-static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
-				  unsigned int phy_reg,
-				  unsigned int* value);
-
-static void eth_clear_mib_counters(ETH_PORT	eth_port_num);
-
-/* Port data flow control routines */
-static ETH_FUNC_RET_STATUS eth_port_send    (ETH_PORT_INFO *p_eth_port_ctrl,
-					     ETH_QUEUE tx_queue,
-					     PKT_INFO *p_pkt_info);
-static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
-					      ETH_QUEUE tx_queue,
-					      PKT_INFO *p_pkt_info);
-static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
-					     ETH_QUEUE rx_queue,
-					     PKT_INFO *p_pkt_info);
-static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
-					      ETH_QUEUE rx_queue,
-					      PKT_INFO *p_pkt_info);
-
-
-static bool ether_init_tx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
-				    ETH_QUEUE	tx_queue,
-				    int				tx_desc_num,
-				    int				tx_buff_size,
-				    unsigned int	tx_desc_base_addr,
-				    unsigned int	tx_buff_base_addr);
-
-static bool ether_init_rx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
-				    ETH_QUEUE	rx_queue,
-				    int				rx_desc_num,
-				    int				rx_buff_size,
-				    unsigned int	rx_desc_base_addr,
-				    unsigned int	rx_buff_base_addr);
-
-#endif /* MV64460_ETH_ */

board/Marvell/db64460/pci.c

@@ -1,940 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-/* PCI.c - PCI functions */
-
-
-#include <common.h>
-#include <pci.h>
-
-#include "../include/pci.h"
-
-#undef DEBUG
-#undef IDE_SET_NATIVE_MODE
-static unsigned int local_buses[] = { 0, 0 };
-
-static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
-	{0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
-	{0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
-};
-
-
-#ifdef DEBUG
-static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
-static void gt_pci_bus_mode_display (PCI_HOST host)
-{
-	unsigned int mode;
-
-
-	mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
-	switch (mode) {
-	case 0:
-		printf ("PCI %d bus mode: Conventional PCI\n", host);
-		break;
-	case 1:
-		printf ("PCI %d bus mode: 66 Mhz PCIX\n", host);
-		break;
-	case 2:
-		printf ("PCI %d bus mode: 100 Mhz PCIX\n", host);
-		break;
-	case 3:
-		printf ("PCI %d bus mode: 133 Mhz PCIX\n", host);
-		break;
-	default:
-		printf ("Unknown BUS %d\n", mode);
-	}
-}
-#endif
-
-static const unsigned int pci_p2p_configuration_reg[] = {
-	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
-};
-
-static const unsigned int pci_configuration_address[] = {
-	PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
-};
-
-static const unsigned int pci_configuration_data[] = {
-	PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
-	PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
-};
-
-static const unsigned int pci_error_cause_reg[] = {
-	PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
-};
-
-static const unsigned int pci_arbiter_control[] = {
-	PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
-};
-
-static const unsigned int pci_address_space_en[] = {
-	PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
-};
-
-static const unsigned int pci_snoop_control_base_0_low[] = {
-	PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
-};
-static const unsigned int pci_snoop_control_top_0[] = {
-	PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
-};
-
-static const unsigned int pci_access_control_base_0_low[] = {
-	PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
-};
-static const unsigned int pci_access_control_top_0[] = {
-	PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
-};
-
-static const unsigned int pci_scs_bank_size[2][4] = {
-	{PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
-	 PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
-	{PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
-	 PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
-};
-
-static const unsigned int pci_p2p_configuration[] = {
-	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
-};
-
-
-/********************************************************************
-* pciWriteConfigReg - Write to a PCI configuration register
-*                    - Make sure the GT is configured as a master before writing
-*                      to another device on the PCI.
-*                    - The function takes care of Big/Little endian conversion.
-*
-*
-* Inputs:   unsigned int regOffset: The register offset as it apears in the GT spec
-*                   (or any other PCI device spec)
-*           pciDevNum: The device number needs to be addressed.
-*
-*  Configuration Address 0xCF8:
-*
-*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
-*  |congif|Reserved|  Bus |Device|Function|Register|00|
-*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
-*
-*********************************************************************/
-void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
-			unsigned int pciDevNum, unsigned int data)
-{
-	volatile unsigned int DataForAddrReg;
-	unsigned int functionNum;
-	unsigned int busNum = 0;
-	unsigned int addr;
-
-	if (pciDevNum > 32)	/* illegal device Number */
-		return;
-	if (pciDevNum == SELF) {	/* configure our configuration space. */
-		pciDevNum =
-			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
-			0x1f;
-		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
-			0xff0000;
-	}
-	functionNum = regOffset & 0x00000700;
-	pciDevNum = pciDevNum << 11;
-	regOffset = regOffset & 0xfc;
-	DataForAddrReg =
-		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
-	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
-	GT_REG_READ (pci_configuration_address[host], &addr);
-	if (addr != DataForAddrReg)
-		return;
-	GT_REG_WRITE (pci_configuration_data[host], data);
-}
-
-/********************************************************************
-* pciReadConfigReg  - Read from a PCI0 configuration register
-*                    - Make sure the GT is configured as a master before reading
-*                     from another device on the PCI.
-*                   - The function takes care of Big/Little endian conversion.
-* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
-*                        spec)
-*           pciDevNum: The device number needs to be addressed.
-* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
-*                 cause register to make sure the data is valid
-*
-*  Configuration Address 0xCF8:
-*
-*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
-*  |congif|Reserved|  Bus |Device|Function|Register|00|
-*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
-*
-*********************************************************************/
-unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
-			       unsigned int pciDevNum)
-{
-	volatile unsigned int DataForAddrReg;
-	unsigned int data;
-	unsigned int functionNum;
-	unsigned int busNum = 0;
-
-	if (pciDevNum > 32)	/* illegal device Number */
-		return 0xffffffff;
-	if (pciDevNum == SELF) {	/* configure our configuration space. */
-		pciDevNum =
-			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
-			0x1f;
-		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
-			0xff0000;
-	}
-	functionNum = regOffset & 0x00000700;
-	pciDevNum = pciDevNum << 11;
-	regOffset = regOffset & 0xfc;
-	DataForAddrReg =
-		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
-	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
-	GT_REG_READ (pci_configuration_address[host], &data);
-	if (data != DataForAddrReg)
-		return 0xffffffff;
-	GT_REG_READ (pci_configuration_data[host], &data);
-	return data;
-}
-
-/********************************************************************
-* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
-*                               the agent is placed on another Bus. For more
-*                               information read P2P in the PCI spec.
-*
-* Inputs:   unsigned int regOffset - The register offset as it apears in the
-*           GT spec (or any other PCI device spec).
-*           unsigned int pciDevNum - The device number needs to be addressed.
-*           unsigned int busNum - On which bus does the Target agent connect
-*                                 to.
-*           unsigned int data - data to be written.
-*
-*  Configuration Address 0xCF8:
-*
-*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
-*  |congif|Reserved|  Bus |Device|Function|Register|01|
-*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
-*
-*  The configuration Address is configure as type-I (bits[1:0] = '01') due to
-*   PCI spec referring to P2P.
-*
-*********************************************************************/
-void pciOverBridgeWriteConfigReg (PCI_HOST host,
-				  unsigned int regOffset,
-				  unsigned int pciDevNum,
-				  unsigned int busNum, unsigned int data)
-{
-	unsigned int DataForReg;
-	unsigned int functionNum;
-
-	functionNum = regOffset & 0x00000700;
-	pciDevNum = pciDevNum << 11;
-	regOffset = regOffset & 0xff;
-	busNum = busNum << 16;
-	if (pciDevNum == SELF) {	/* This board */
-		DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
-	} else {
-		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
-			BIT31 | BIT0;
-	}
-	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
-	GT_REG_WRITE (pci_configuration_data[host], data);
-}
-
-
-/********************************************************************
-* pciOverBridgeReadConfigReg  - Read from a PCIn configuration register where
-*                               the agent target locate on another PCI bus.
-*                             - Make sure the GT is configured as a master
-*                               before reading from another device on the PCI.
-*                             - The function takes care of Big/Little endian
-*                               conversion.
-* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
-*                        spec). (configuration register offset.)
-*           pciDevNum: The device number needs to be addressed.
-*           busNum: the Bus number where the agent is place.
-* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
-*                 cause register to make sure the data is valid
-*
-*  Configuration Address 0xCF8:
-*
-*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
-*  |congif|Reserved|  Bus |Device|Function|Register|01|
-*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
-*
-*********************************************************************/
-unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
-					 unsigned int regOffset,
-					 unsigned int pciDevNum,
-					 unsigned int busNum)
-{
-	unsigned int DataForReg;
-	unsigned int data;
-	unsigned int functionNum;
-
-	functionNum = regOffset & 0x00000700;
-	pciDevNum = pciDevNum << 11;
-	regOffset = regOffset & 0xff;
-	busNum = busNum << 16;
-	if (pciDevNum == SELF) {	/* This board */
-		DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
-	} else {		/* agent on another bus */
-
-		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
-			BIT0 | BIT31;
-	}
-	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
-	GT_REG_READ (pci_configuration_data[host], &data);
-	return data;
-}
-
-
-/********************************************************************
-* pciGetRegOffset - Gets the register offset for this region config.
-*
-* INPUT:   Bus, Region - The bus and region we ask for its base address.
-* OUTPUT:   N/A
-* RETURNS: PCI register base address
-*********************************************************************/
-static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
-{
-	switch (host) {
-	case PCI_HOST0:
-		switch (region) {
-		case PCI_IO:
-			return PCI_0I_O_LOW_DECODE_ADDRESS;
-		case PCI_REGION0:
-			return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
-		case PCI_REGION1:
-			return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
-		case PCI_REGION2:
-			return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
-		case PCI_REGION3:
-			return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
-		}
-	case PCI_HOST1:
-		switch (region) {
-		case PCI_IO:
-			return PCI_1I_O_LOW_DECODE_ADDRESS;
-		case PCI_REGION0:
-			return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
-		case PCI_REGION1:
-			return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
-		case PCI_REGION2:
-			return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
-		case PCI_REGION3:
-			return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
-		}
-	}
-	return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
-}
-
-static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
-{
-	switch (host) {
-	case PCI_HOST0:
-		switch (region) {
-		case PCI_IO:
-			return PCI_0I_O_ADDRESS_REMAP;
-		case PCI_REGION0:
-			return PCI_0MEMORY0_ADDRESS_REMAP;
-		case PCI_REGION1:
-			return PCI_0MEMORY1_ADDRESS_REMAP;
-		case PCI_REGION2:
-			return PCI_0MEMORY2_ADDRESS_REMAP;
-		case PCI_REGION3:
-			return PCI_0MEMORY3_ADDRESS_REMAP;
-		}
-	case PCI_HOST1:
-		switch (region) {
-		case PCI_IO:
-			return PCI_1I_O_ADDRESS_REMAP;
-		case PCI_REGION0:
-			return PCI_1MEMORY0_ADDRESS_REMAP;
-		case PCI_REGION1:
-			return PCI_1MEMORY1_ADDRESS_REMAP;
-		case PCI_REGION2:
-			return PCI_1MEMORY2_ADDRESS_REMAP;
-		case PCI_REGION3:
-			return PCI_1MEMORY3_ADDRESS_REMAP;
-		}
-	}
-	return PCI_0MEMORY0_ADDRESS_REMAP;
-}
-
-/********************************************************************
-* pciGetBaseAddress - Gets the base address of a PCI.
-*           - If the PCI size is 0 then this base address has no meaning!!!
-*
-*
-* INPUT:   Bus, Region - The bus and region we ask for its base address.
-* OUTPUT:   N/A
-* RETURNS: PCI base address.
-*********************************************************************/
-unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
-{
-	unsigned int regBase;
-	unsigned int regEnd;
-	unsigned int regOffset = pciGetRegOffset (host, region);
-
-	GT_REG_READ (regOffset, &regBase);
-	GT_REG_READ (regOffset + 8, &regEnd);
-
-	if (regEnd <= regBase)
-		return 0xffffffff;	/* ERROR !!! */
-
-	regBase = regBase << 16;
-	return regBase;
-}
-
-bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
-		  unsigned int bankBase, unsigned int bankLength)
-{
-	unsigned int low = 0xfff;
-	unsigned int high = 0x0;
-	unsigned int regOffset = pciGetRegOffset (host, region);
-	unsigned int remapOffset = pciGetRemapOffset (host, region);
-
-	if (bankLength != 0) {
-		low = (bankBase >> 16) & 0xffff;
-		high = ((bankBase + bankLength) >> 16) - 1;
-	}
-
-	GT_REG_WRITE (regOffset, low | (1 << 24));	/* no swapping */
-	GT_REG_WRITE (regOffset + 8, high);
-
-	if (bankLength != 0) {	/* must do AFTER writing maps */
-		GT_REG_WRITE (remapOffset, remapBase >> 16);	/* sorry, 32 bits only.
-								   dont support upper 32
-								   in this driver */
-	}
-	return true;
-}
-
-unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
-{
-	unsigned int low;
-	unsigned int regOffset = pciGetRegOffset (host, region);
-
-	GT_REG_READ (regOffset, &low);
-	return (low & 0xffff) << 16;
-}
-
-unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
-{
-	unsigned int low, high;
-	unsigned int regOffset = pciGetRegOffset (host, region);
-
-	GT_REG_READ (regOffset, &low);
-	GT_REG_READ (regOffset + 8, &high);
-	return ((high & 0xffff) + 1) << 16;
-}
-
-
-/* ronen - 7/Dec/03*/
-/********************************************************************
-* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
-* Inputs: one of the PCI BAR
-*********************************************************************/
-void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
-{
-	RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
-}
-
-void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
-{
-	SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
-}
-
-/********************************************************************
-* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
-*
-* Inputs: base and size of PCI SCS
-*********************************************************************/
-void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
-		       unsigned int pciDramBase, unsigned int pciDramSize)
-{
-	/*ronen different function for 3rd bank. */
-	unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
-
-	pciDramBase = pciDramBase & 0xfffff000;
-	pciDramBase = pciDramBase | (pciReadConfigReg (host,
-						       PCI_SCS_0_BASE_ADDRESS
-						       + offset,
-						       SELF) & 0x00000fff);
-	pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
-			   pciDramBase);
-	if (pciDramSize == 0)
-		pciDramSize++;
-	GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
-	gtPciEnableInternalBAR (host, bank);
-}
-
-/********************************************************************
-* pciSetRegionFeatures - This function modifys one of the 8 regions with
-*                         feature bits given as an input.
-*                       - Be advised to check the spec before modifying them.
-* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
-*         unsigned int features - See file: pci.h there are defintion for those
-*                                 region features.
-*         unsigned int baseAddress - The region base Address.
-*         unsigned int topAddress - The region top Address.
-* Returns: false if one of the parameters is erroneous true otherwise.
-*********************************************************************/
-bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
-			   unsigned int features, unsigned int baseAddress,
-			   unsigned int regionLength)
-{
-	unsigned int accessLow;
-	unsigned int accessHigh;
-	unsigned int accessTop = baseAddress + regionLength;
-
-	if (regionLength == 0) {	/* close the region. */
-		pciDisableAccessRegion (host, region);
-		return true;
-	}
-	/* base Address is store is bits [11:0] */
-	accessLow = (baseAddress & 0xfff00000) >> 20;
-	/* All the features are update according to the defines in pci.h (to be on
-	   the safe side we disable bits: [11:0] */
-	accessLow = accessLow | (features & 0xfffff000);
-	/* write to the Low Access Region register */
-	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
-		      accessLow);
-
-	accessHigh = (accessTop & 0xfff00000) >> 20;
-
-	/* write to the High Access Region register */
-	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
-		      accessHigh - 1);
-	return true;
-}
-
-/********************************************************************
-* pciDisableAccessRegion - Disable The given Region by writing MAX size
-*                           to its low Address and MIN size to its high Address.
-*
-* Inputs:   PCI_ACCESS_REGIONS region - The region we to be Disabled.
-* Returns:  N/A.
-*********************************************************************/
-void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
-{
-	/* writing back the registers default values. */
-	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
-		      0x01001fff);
-	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
-}
-
-/********************************************************************
-* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
-*
-* Inputs:   N/A
-* Returns:  true.
-*********************************************************************/
-bool pciArbiterEnable (PCI_HOST host)
-{
-	unsigned int regData;
-
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
-	return true;
-}
-
-/********************************************************************
-* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
-*
-* Inputs:   N/A
-* Returns:  true
-*********************************************************************/
-bool pciArbiterDisable (PCI_HOST host)
-{
-	unsigned int regData;
-
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
-	return true;
-}
-
-/********************************************************************
-* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
-*
-* Inputs:   PCI_AGENT_PRIO internalAgent - priotity for internal agent.
-*           PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
-*           PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
-*           PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
-*           PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
-*           PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
-*           PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
-* Returns:  true
-*********************************************************************/
-bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
-				  PCI_AGENT_PRIO externalAgent0,
-				  PCI_AGENT_PRIO externalAgent1,
-				  PCI_AGENT_PRIO externalAgent2,
-				  PCI_AGENT_PRIO externalAgent3,
-				  PCI_AGENT_PRIO externalAgent4,
-				  PCI_AGENT_PRIO externalAgent5)
-{
-	unsigned int regData;
-	unsigned int writeData;
-
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	writeData = (internalAgent << 7) + (externalAgent0 << 8) +
-		(externalAgent1 << 9) + (externalAgent2 << 10) +
-		(externalAgent3 << 11) + (externalAgent4 << 12) +
-		(externalAgent5 << 13);
-	regData = (regData & 0xffffc07f) | writeData;
-	GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
-	return true;
-}
-
-/********************************************************************
-* pciParkingDisable - Park on last option disable, with this function you can
-*                      disable the park on last mechanism for each agent.
-*                      disabling this option for all agents results parking
-*                      on the internal master.
-*
-* Inputs: PCI_AGENT_PARK internalAgent -  parking Disable for internal agent.
-*         PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
-*         PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
-*         PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
-*         PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
-*         PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
-*         PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
-* Returns:  true
-*********************************************************************/
-bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
-			PCI_AGENT_PARK externalAgent0,
-			PCI_AGENT_PARK externalAgent1,
-			PCI_AGENT_PARK externalAgent2,
-			PCI_AGENT_PARK externalAgent3,
-			PCI_AGENT_PARK externalAgent4,
-			PCI_AGENT_PARK externalAgent5)
-{
-	unsigned int regData;
-	unsigned int writeData;
-
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	writeData = (internalAgent << 14) + (externalAgent0 << 15) +
-		(externalAgent1 << 16) + (externalAgent2 << 17) +
-		(externalAgent3 << 18) + (externalAgent4 << 19) +
-		(externalAgent5 << 20);
-	regData = (regData & ~(0x7f << 14)) | writeData;
-	GT_REG_WRITE (pci_arbiter_control[host], regData);
-	return true;
-}
-
-/********************************************************************
-* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
-*                       respond to grant assertion within a window specified in
-*                       the input value: 'brokenValue'.
-*
-* Inputs: unsigned char brokenValue -  A value which limits the Master to hold the
-*                       grant without asserting frame.
-* Returns:  Error for illegal broken value otherwise true.
-*********************************************************************/
-bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
-{
-	unsigned int data;
-	unsigned int regData;
-
-	if (brokenValue > 0xf)
-		return false;	/* brokenValue must be 4 bit */
-	data = brokenValue << 3;
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	regData = (regData & 0xffffff87) | data;
-	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
-	return true;
-}
-
-/********************************************************************
-* pciDisableBrokenAgentDetection - This function disable the Broken agent
-*                           Detection mechanism.
-*                           NOTE: This operation may cause a dead lock on the
-*                           pci0 arbitration.
-*
-* Inputs:   N/A
-* Returns:  true.
-*********************************************************************/
-bool pciDisableBrokenAgentDetection (PCI_HOST host)
-{
-	unsigned int regData;
-
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	regData = regData & 0xfffffffd;
-	GT_REG_WRITE (pci_arbiter_control[host], regData);
-	return true;
-}
-
-/********************************************************************
-* pciP2PConfig - This function set the PCI_n P2P configurate.
-*                 For more information on the P2P read PCI spec.
-*
-* Inputs:  unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
-*                                      Boundry.
-*          unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
-*                                      Boundry.
-*          unsigned int busNum - The CPI bus number to which the PCI interface
-*                                      is connected.
-*          unsigned int devNum - The PCI interface's device number.
-*
-* Returns:  true.
-*********************************************************************/
-bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
-		   unsigned int SecondBusHigh,
-		   unsigned int busNum, unsigned int devNum)
-{
-	unsigned int regData;
-
-	regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
-		((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
-	GT_REG_WRITE (pci_p2p_configuration[host], regData);
-	return true;
-}
-
-/********************************************************************
-* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
-*                          supports Cache Coherency in the PCI_n interface.
-* Inputs: region - One of the four regions.
-*         snoopType - There is four optional Types:
-*                        1. No Snoop.
-*                        2. Snoop to WT region.
-*                        3. Snoop to WB region.
-*                        4. Snoop & Invalidate to WB region.
-*         baseAddress - Base Address of this region.
-*         regionLength - Region length.
-* Returns: false if one of the parameters is wrong otherwise return true.
-*********************************************************************/
-bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
-			    PCI_SNOOP_TYPE snoopType,
-			    unsigned int baseAddress,
-			    unsigned int regionLength)
-{
-	unsigned int snoopXbaseAddress;
-	unsigned int snoopXtopAddress;
-	unsigned int data;
-	unsigned int snoopHigh = baseAddress + regionLength;
-
-	if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
-		return false;
-	snoopXbaseAddress =
-		pci_snoop_control_base_0_low[host] + 0x10 * region;
-	snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
-	if (regionLength == 0) {	/* closing the region */
-		GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
-		GT_REG_WRITE (snoopXtopAddress, 0);
-		return true;
-	}
-	baseAddress = baseAddress & 0xfff00000;	/* Granularity of 1MByte */
-	data = (baseAddress >> 20) | snoopType << 12;
-	GT_REG_WRITE (snoopXbaseAddress, data);
-	snoopHigh = (snoopHigh & 0xfff00000) >> 20;
-	GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
-	return true;
-}
-
-static int gt_read_config_dword (struct pci_controller *hose,
-				 pci_dev_t dev, int offset, u32 * value)
-{
-	int bus = PCI_BUS (dev);
-
-	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
-		*value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
-					   PCI_DEV (dev));
-	} else {
-		*value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
-						     cfg_addr, offset,
-						     PCI_DEV (dev), bus);
-	}
-
-	return 0;
-}
-
-static int gt_write_config_dword (struct pci_controller *hose,
-				  pci_dev_t dev, int offset, u32 value)
-{
-	int bus = PCI_BUS (dev);
-
-	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
-		pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
-				   PCI_DEV (dev), value);
-	} else {
-		pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
-					     offset, PCI_DEV (dev), bus,
-					     value);
-	}
-	return 0;
-}
-
-
-static void gt_setup_ide (struct pci_controller *hose,
-			  pci_dev_t dev, struct pci_config_table *entry)
-{
-	static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
-	u32 bar_response, bar_value;
-	int bar;
-
-	for (bar = 0; bar < 6; bar++) {
-		/*ronen different function for 3rd bank. */
-		unsigned int offset =
-			(bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
-
-		pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
-					0x0);
-		pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
-				       &bar_response);
-
-		pciauto_region_allocate (bar_response &
-					 PCI_BASE_ADDRESS_SPACE_IO ? hose->
-					 pci_io : hose->pci_mem, ide_bar[bar],
-					 &bar_value);
-
-		pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
-					bar_value);
-	}
-}
-
-
-/* TODO BJW: Change this for DB64360. This was pulled from the EV64260  */
-/* and is curently not called *. */
-#if 0
-static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
-{
-	unsigned char pin, irq;
-
-	pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
-
-	if (pin == 1) {		/* only allow INT A */
-		irq = pci_irq_swizzle[(PCI_HOST) hose->
-				      cfg_addr][PCI_DEV (dev)];
-		if (irq)
-			pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
-	}
-}
-#endif
-
-struct pci_config_table gt_config_table[] = {
-	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
-	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
-
-	{}
-};
-
-struct pci_controller pci0_hose = {
-/*    fixup_irq: gt_fixup_irq, */
-	config_table:gt_config_table,
-};
-
-struct pci_controller pci1_hose = {
-/*    fixup_irq: gt_fixup_irq, */
-	config_table:gt_config_table,
-};
-
-void pci_init_board (void)
-{
-	unsigned int command;
-
-#ifdef DEBUG
-	gt_pci_bus_mode_display (PCI_HOST0);
-#endif
-
-	pci0_hose.first_busno = 0;
-	pci0_hose.last_busno = 0xff;
-	local_buses[0] = pci0_hose.first_busno;
-
-	/* PCI memory space */
-	pci_set_region (pci0_hose.regions + 0,
-			CFG_PCI0_0_MEM_SPACE,
-			CFG_PCI0_0_MEM_SPACE,
-			CFG_PCI0_MEM_SIZE, PCI_REGION_MEM);
-
-	/* PCI I/O space */
-	pci_set_region (pci0_hose.regions + 1,
-			CFG_PCI0_IO_SPACE_PCI,
-			CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO);
-
-	pci_set_ops (&pci0_hose,
-		     pci_hose_read_config_byte_via_dword,
-		     pci_hose_read_config_word_via_dword,
-		     gt_read_config_dword,
-		     pci_hose_write_config_byte_via_dword,
-		     pci_hose_write_config_word_via_dword,
-		     gt_write_config_dword);
-	pci0_hose.region_count = 2;
-
-	pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
-
-	pci_register_hose (&pci0_hose);
-	pciArbiterEnable (PCI_HOST0);
-	pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
-	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
-	command |= PCI_COMMAND_MASTER;
-	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
-	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
-	command |= PCI_COMMAND_MEMORY;
-	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
-
-	pci0_hose.last_busno = pci_hose_scan (&pci0_hose);
-
-#ifdef DEBUG
-	gt_pci_bus_mode_display (PCI_HOST1);
-#endif
-	pci1_hose.first_busno = pci0_hose.last_busno + 1;
-	pci1_hose.last_busno = 0xff;
-	pci1_hose.current_busno = pci1_hose.first_busno;
-	local_buses[1] = pci1_hose.first_busno;
-
-	/* PCI memory space */
-	pci_set_region (pci1_hose.regions + 0,
-			CFG_PCI1_0_MEM_SPACE,
-			CFG_PCI1_0_MEM_SPACE,
-			CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
-
-	/* PCI I/O space */
-	pci_set_region (pci1_hose.regions + 1,
-			CFG_PCI1_IO_SPACE_PCI,
-			CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
-
-	pci_set_ops (&pci1_hose,
-		     pci_hose_read_config_byte_via_dword,
-		     pci_hose_read_config_word_via_dword,
-		     gt_read_config_dword,
-		     pci_hose_write_config_byte_via_dword,
-		     pci_hose_write_config_word_via_dword,
-		     gt_write_config_dword);
-
-	pci1_hose.region_count = 2;
-
-	pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
-
-	pci_register_hose (&pci1_hose);
-
-	pciArbiterEnable (PCI_HOST1);
-	pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
-
-	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
-	command |= PCI_COMMAND_MASTER;
-	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
-
-	pci1_hose.last_busno = pci_hose_scan (&pci1_hose);
-
-	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
-	command |= PCI_COMMAND_MEMORY;
-	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
-
-}

board/Marvell/db64460/u-boot.lds

@@ -1,135 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
- */
-
-OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .interp : { *(.interp) }
-  .hash          : { *(.hash)		}
-  .dynsym        : { *(.dynsym)		}
-  .dynstr        : { *(.dynstr)		}
-  .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
-  .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
-  .rel.got       : { *(.rel.got)		}
-  .rela.got      : { *(.rela.got)		}
-  .rel.ctors     : { *(.rel.ctors)	}
-  .rela.ctors    : { *(.rela.ctors)	}
-  .rel.dtors     : { *(.rel.dtors)	}
-  .rela.dtors    : { *(.rela.dtors)	}
-  .rel.bss       : { *(.rel.bss)		}
-  .rela.bss      : { *(.rela.bss)		}
-  .rel.plt       : { *(.rel.plt)		}
-  .rela.plt      : { *(.rela.plt)		}
-  .init          : { *(.init)	}
-  .plt : { *(.plt) }
-  .text      :
-  {
-    cpu/74xx_7xx/start.o	(.text)
-
-/* store the environment in a seperate sector in the boot flash */
-/*    . = env_offset; */
-/*    common/environment.o(.text) */
-
-    *(.text)
-    *(.fixup)
-    *(.got1)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(.rodata)
-    *(.rodata1)
-    *(.rodata.str1.4)
-  }
-  .fini      : { *(.fini)    } =0
-  .ctors     : { *(.ctors)   }
-  .dtors     : { *(.dtors)   }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x00FF) & 0xFFFFFF00;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    *(.got)
-    _GOT2_TABLE_ = .;
-    *(.got2)
-    _FIXUP_TABLE_ = .;
-    *(.fixup)
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data)
-    *(.data1)
-    *(.sdata)
-    *(.sdata2)
-    *(.dynamic)
-    CONSTRUCTORS
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss       :
-  {
-   *(.sbss) *(.scommon)
-   *(.dynbss)
-   *(.bss)
-   *(COMMON)
-  }
-  _end = . ;
-  PROVIDE (end = .);
-}

board/Marvell/include/core.h

@@ -1,238 +0,0 @@
-/* Core.h - Basic core logic functions and definitions */
-
-/* Copyright Galileo Technology. */
-
-/*
-DESCRIPTION
-This header file contains simple read/write macros for addressing
-the SDRAM, devices, GT`s internal registers and PCI (using the PCI`s address
-space). The macros take care of Big/Little endian conversions.
-*/
-
-#ifndef __INCcoreh
-#define __INCcoreh
-
-#include "mv_gen_reg.h"
-
-extern unsigned int INTERNAL_REG_BASE_ADDR;
-
-/****************************************/
-/*	    GENERAL Definitions			*/
-/****************************************/
-
-#define NO_BIT		0x00000000
-#define BIT0		0x00000001
-#define BIT1		0x00000002
-#define BIT2		0x00000004
-#define BIT3		0x00000008
-#define BIT4		0x00000010
-#define BIT5		0x00000020
-#define BIT6		0x00000040
-#define BIT7		0x00000080
-#define BIT8		0x00000100
-#define BIT9		0x00000200
-#define BIT10		0x00000400
-#define BIT11		0x00000800
-#define BIT12		0x00001000
-#define BIT13		0x00002000
-#define BIT14		0x00004000
-#define BIT15		0x00008000
-#define BIT16		0x00010000
-#define BIT17		0x00020000
-#define BIT18		0x00040000
-#define BIT19		0x00080000
-#define BIT20		0x00100000
-#define BIT21		0x00200000
-#define BIT22		0x00400000
-#define BIT23		0x00800000
-#define BIT24		0x01000000
-#define BIT25		0x02000000
-#define BIT26		0x04000000
-#define BIT27		0x08000000
-#define BIT28		0x10000000
-#define BIT29		0x20000000
-#define BIT30		0x40000000
-#define BIT31		0x80000000
-
-#define _1K		0x00000400
-#define _2K		0x00000800
-#define _4K		0x00001000
-#define _8K		0x00002000
-#define _16K		0x00004000
-#define _32K		0x00008000
-#define _64K		0x00010000
-#define _128K		0x00020000
-#define _256K		0x00040000
-#define _512K		0x00080000
-
-#define _1M		0x00100000
-#define _2M		0x00200000
-#define _3M		0x00300000
-#define _4M		0x00400000
-#define _5M		0x00500000
-#define _6M		0x00600000
-#define _7M		0x00700000
-#define _8M		0x00800000
-#define _9M		0x00900000
-#define _10M		0x00a00000
-#define _11M		0x00b00000
-#define _12M		0x00c00000
-#define _13M		0x00d00000
-#define _14M		0x00e00000
-#define _15M		0x00f00000
-#define _16M		0x01000000
-
-#define _32M		0x02000000
-#define _64M		0x04000000
-#define _128M		0x08000000
-#define _256M		0x10000000
-#define _512M		0x20000000
-
-#define _1G		0x40000000
-#define _2G		0x80000000
-
-typedef enum _bool{false,true} bool;
-
-/* Little to Big endian conversion macros */
-
-#ifdef LE /* Little Endian */
-#define SHORT_SWAP(X) (X)
-#define WORD_SWAP(X) (X)
-#define LONG_SWAP(X) ((l64)(X))
-
-#else	 /* Big Endian */
-#define SHORT_SWAP(X) ((X <<8 ) | (X >> 8))
-
-#define WORD_SWAP(X) (((X)&0xff)<<24)+	    \
-		    (((X)&0xff00)<<8)+	    \
-		    (((X)&0xff0000)>>8)+    \
-		    (((X)&0xff000000)>>24)
-
-#define LONG_SWAP(X) ( (l64) (((X)&0xffULL)<<56)+		\
-			    (((X)&0xff00ULL)<<40)+		\
-			    (((X)&0xff0000ULL)<<24)+		\
-			    (((X)&0xff000000ULL)<<8)+		\
-			    (((X)&0xff00000000ULL)>>8)+		\
-			    (((X)&0xff0000000000ULL)>>24)+	\
-			    (((X)&0xff000000000000ULL)>>40)+	\
-			    (((X)&0xff00000000000000ULL)>>56))
-
-#endif
-
-#ifndef NULL
-#define NULL 0
-#endif
-
-/* Those two definitions were defined to be compatible with MIPS */
-#define NONE_CACHEABLE		0x00000000
-#define CACHEABLE			0x00000000
-
-/* 750 cache line */
-#define CACHE_LINE_SIZE 32
-#define CACHELINE_MASK_BITS (CACHE_LINE_SIZE - 1)
-#define CACHELINE_ROUNDUP(A) (((A)+CACHELINE_MASK_BITS) & ~CACHELINE_MASK_BITS)
-
-/* Read/Write to/from GT`s internal registers */
-#define GT_REG_READ(offset, pData)					    \
-*pData = ( *((volatile unsigned int *)(NONE_CACHEABLE |			    \
-		INTERNAL_REG_BASE_ADDR | (offset))) ) ;						     \
-*pData = WORD_SWAP(*pData)
-
-#define GTREGREAD(offset)						    \
-	 (WORD_SWAP( *((volatile unsigned int *)(NONE_CACHEABLE |	     \
-		   INTERNAL_REG_BASE_ADDR | (offset))) ))
-
-#define GT_REG_WRITE(offset, data)					    \
-*((unsigned int *)( INTERNAL_REG_BASE_ADDR | (offset))) =		    \
-		    WORD_SWAP(data)
-
-/* Write 32/16/8 bit */
-#define WRITE_CHAR(address, data)					    \
-	*((unsigned char *)(address)) = data
-#define WRITE_SHORT(address, data)					    \
-	*((unsigned short *)(address)) = data
-#define WRITE_WORD(address, data)					    \
-	*((unsigned int *)(address)) = data
-
-#define GT_WRITE_CHAR(address, data)	 WRITE_CHAR(address, data)
-
-/* Write 32/16/8 bit NonCacheable */
-/*
-#define GT_WRITE_CHAR(address, data)					       \
-	(*((unsigned char *)NONE_CACHEABLE(address))) = data
-#define GT_WRITE_SHORT(address, data)					       \
-	(*((unsigned short *)NONE_CACHEABLE(address))) = data
-#define GT_WRITE_WORD(address, data)					       \
-	(*((unsigned int *)NONE_CACHEABLE(address))) = data
-*/
- /*#define GT_WRITE_CHAR(address, data)	  ((*((volatile unsigned char *)NONE_CACHEABLE((address)))) = ((unsigned char)(data)))1 */
-
- /*#define GT_WRITE_SHORT(address, data)   ((*((volatile unsigned short *)NONE_CACHEABLE((address)))) = ((unsigned short)(data)))1 */
-
- /*#define GT_WRITE_WORD(address, data)	 ((*((volatile unsigned int *)NONE_CACHEABLE((address)))) = ((unsigned int)(data)))1 */
-
-
-/* Read 32/16/8 bits - returns data in variable. */
-#define READ_CHAR(address, pData)					    \
-	*pData = *((volatile unsigned char *)(address))
-
-#define READ_SHORT(address, pData)					    \
-	*pData = *((volatile unsigned short *)(address))
-
-#define READ_WORD(address, pData)					    \
-	*pData = *((volatile unsigned int *)(address))
-
-/* Read 32/16/8 bit - returns data direct. */
-#define READCHAR(address)						    \
-	*((volatile unsigned char *)((address) | NONE_CACHEABLE))
-
-#define READSHORT(address)						    \
-	*((volatile unsigned short *)((address) | NONE_CACHEABLE))
-
-#define READWORD(address)						    \
-	*((volatile unsigned int *)((address) | NONE_CACHEABLE))
-
-/* Those two Macros were defined to be compatible with MIPS */
-#define VIRTUAL_TO_PHY(x)    (((unsigned int)x) & 0xffffffff)
-#define PHY_TO_VIRTUAL(x)    (((unsigned int)x) | NONE_CACHEABLE)
-
-/*  SET_REG_BITS(regOffset,bits) -
-   gets register offset and bits: a 32bit value. It set to logic '1' in the
-   internal register the bits which given as an input example:
-   SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
-   '1' in register 0x840 while the other bits stays as is. */
-#define SET_REG_BITS(regOffset,bits) \
-	*(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR |  \
-	regOffset) |= (unsigned int)WORD_SWAP(bits)
-
-/*  RESET_REG_BITS(regOffset,bits) -
-   gets register offset and bits: a 32bit value. It set to logic '0' in the
-   internal register the bits which given as an input example:
-   RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
-   '0' in register 0x840 while the other bits stays as is. */
-#define RESET_REG_BITS(regOffset,bits) \
-	*(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR   \
-	| regOffset) &= ~( (unsigned int)WORD_SWAP(bits) )
-/* gets register offset and bits: a 32bit value. It set to logic '1' in the
-   internal register the bits which given as an input example:
-   GT_SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
-   '1' in register 0x840 while the other bits stays as is. */
- /*#define GT_SET_REG_BITS(regOffset,bits)	((*((volatile unsigned int*)(NONE_CACHEABLE(INTERNAL_REG_BASE_ADDR) | (regOffset)))) |= ((unsigned int)WORD_SWAP(bits)))1 */
- /*#define GT_SET_REG_BITS(regOffset,bits) RESET_REG_BITS(regOffset,bits)1 */
-#define GT_SET_REG_BITS(regOffset,bits) SET_REG_BITS(regOffset,bits)
-/* gets register offset and bits: a 32bit value. It set to logic '0' in the
-   internal register the bits which given as an input example:
-   GT_RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to
-   logic '0' in register 0x840 while the other bits stays as is. */
- /*#define GT_RESET_REG_BITS(regOffset,bits)	((*((volatile unsigned int*)(NONE_CACHEABLE(INTERNAL_REG_BASE_ADDR) |  (regOffset)))) &= ~((unsigned int)WORD_SWAP(bits)))1 */
-#define GT_RESET_REG_BITS(regOffset,bits) RESET_REG_BITS(regOffset,bits)
-
-
-#define DEBUG_LED0_ON()	       WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x8000,0)
-#define DEBUG_LED1_ON()	       WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0xc000,0)
-#define DEBUG_LED2_ON()	       WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x10000,0)
-#define DEBUG_LED0_OFF()      WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x14000,0)
-#define DEBUG_LED1_OFF()      WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x18000,0)
-#define DEBUG_LED2_OFF()      WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x1c000,0)
-
-#endif /* __INCcoreh */

board/Marvell/include/memory.h

@@ -1,173 +0,0 @@
-/* Memory.h - Memory mappings and remapping functions declarations */
-
-/* Copyright - Galileo technology. */
-
-#ifndef __INCmemoryh
-#define __INCmemoryh
-
-/* includes */
-
-#include "core.h"
-
-/* defines */
-
-#define DONT_MODIFY	0xffffffff
-#define PARITY_SUPPORT	0x40000000
-#define MINIMUM_MEM_BANK_SIZE		0x10000
-#define MINIMUM_DEVICE_WINDOW_SIZE	0x10000
-#define MINIMUM_PCI_WINDOW_SIZE		0x10000
-#define MINIMUM_ACCESS_WIN_SIZE		0x10000
-
-#define _8BIT		0x00000000
-#define _16BIT		0x00100000
-#define _32BIT		0x00200000
-#define _64BIT		0x00300000
-
-/* typedefs */
-
- typedef struct deviceParam
-{						/* boundary values  */
-    unsigned int    turnOff;			/* 0x0 - 0xf	    */
-    unsigned int    acc2First;			/* 0x0 - 0x1f	    */
-    unsigned int    acc2Next;		/* 0x0 - 0x1f	    */
-    unsigned int    ale2Wr;			/* 0x0 - 0xf	    */
-    unsigned int    wrLow;			/* 0x0 - 0xf	    */
-    unsigned int    wrHigh;			/* 0x0 - 0xf	    */
-    unsigned int    badrSkew;		/* 0x0 - 0x2	   */
-    unsigned int    DPEn;			/* 0x0 - 0x1	   */
-    unsigned int    deviceWidth;	/* in Bytes  */
-} DEVICE_PARAM;
-
-
-typedef enum __memBank{BANK0,BANK1,BANK2,BANK3} MEMORY_BANK;
-typedef enum __memDevice{DEVICE0,DEVICE1,DEVICE2,DEVICE3,BOOT_DEVICE} DEVICE;
-
-/*typedef enum __memoryProtectRegion{MEM_REGION0,MEM_REGION1,MEM_REGION2,	\
-				   MEM_REGION3,MEM_REGION4,MEM_REGION5,	      \
-				   MEM_REGION6,MEM_REGION7}		      \
-				   MEMORY_PROTECT_REGION;*/
-/* There are four possible windows that can be defined as protected */
-typedef enum _memoryProtectWindow{MEM_WINDOW0,MEM_WINDOW1,MEM_WINDOW2,
-				  MEM_WINDOW3
-				 } MEMORY_PROTECT_WINDOW;
-/* When defining a protected window , this paramter indicates whether it
-   is accessible or not */
-typedef enum __memoryAccess{MEM_ACCESS_ALLOWED,MEM_ACCESS_FORBIDEN}	      \
-			    MEMORY_ACCESS;
-typedef enum __memoryWrite{MEM_WRITE_ALLOWED,MEM_WRITE_FORBIDEN}	      \
-			   MEMORY_ACCESS_WRITE;
-typedef enum __memoryCacheProtect{MEM_CACHE_ALLOWED,MEM_CACHE_FORBIDEN}	      \
-				  MEMORY_CACHE_PROTECT;
-typedef enum __memorySnoopType{MEM_NO_SNOOP,MEM_SNOOP_WT,MEM_SNOOP_WB}	      \
-			       MEMORY_SNOOP_TYPE;
-typedef enum __memorySnoopRegion{MEM_SNOOP_REGION0,MEM_SNOOP_REGION1,	      \
-				 MEM_SNOOP_REGION2,MEM_SNOOP_REGION3}	      \
-				 MEMORY_SNOOP_REGION;
-
-/* There are 21 memory windows dedicated for the varios interfaces (PCI,
-   devCS (devices), CS(DDR), interenal registers and SRAM) used by the CPU's
-   address decoding mechanism. */
-typedef enum _memoryWindow {CS_0_WINDOW = BIT0, CS_1_WINDOW = BIT1,
-			    CS_2_WINDOW = BIT2, CS_3_WINDOW = BIT3,
-			    DEVCS_0_WINDOW = BIT4, DEVCS_1_WINDOW = BIT5,
-			    DEVCS_2_WINDOW = BIT6, DEVCS_3_WINDOW = BIT7,
-			    BOOT_CS_WINDOW = BIT8, PCI_0_IO_WINDOW = BIT9,
-			    PCI_0_MEM0_WINDOW = BIT10,
-			    PCI_0_MEM1_WINDOW = BIT11,
-			    PCI_0_MEM2_WINDOW = BIT12,
-			    PCI_0_MEM3_WINDOW = BIT13, PCI_1_IO_WINDOW = BIT14,
-			    PCI_1_MEM0_WINDOW = BIT15, PCI_1_MEM1_WINDOW =BIT16,
-			    PCI_1_MEM2_WINDOW = BIT17, PCI_1_MEM3_WINDOW =BIT18,
-			    INTEGRATED_SRAM_WINDOW = BIT19,
-			    INTERNAL_SPACE_WINDOW = BIT20,
-			    ALL_WINDOWS = 0X1FFFFF
-			   } MEMORY_WINDOW;
-
-typedef enum _memoryWindowStatus {MEM_WINDOW_ENABLED,MEM_WINDOW_DISABLED
-				 } MEMORY_WINDOW_STATUS;
-
-
-typedef enum _pciMemWindow{PCI_0_IO,PCI_0_MEM0,PCI_0_MEM1,PCI_0_MEM2,PCI_0_MEM3
-#ifdef INCLUDE_PCI_1
-			  ,PCI_1_IO,PCI_1_MEM0,PCI_1_MEM1,PCI_1_MEM2,PCI_1_MEM3
-#endif /* INCLUDE_PCI_1 */
-			  } PCI_MEM_WINDOW;
-
-
-/* -------------------------------------------------------------------------------------------------*/
-
-/* functions */
-unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank);
-unsigned int memoryGetDeviceBaseAddress(DEVICE device);
-/* New at MV6436x */
-unsigned int MemoryGetPciBaseAddr(PCI_MEM_WINDOW pciWindow);
-unsigned int memoryGetBankSize(MEMORY_BANK bank);
-unsigned int memoryGetDeviceSize(DEVICE device);
-unsigned int memoryGetDeviceWidth(DEVICE device);
-/* New at MV6436x */
-unsigned int gtMemoryGetPciWindowSize(PCI_MEM_WINDOW pciWindow);
-
-/* when given base Address and size Set new WINDOW for SCS_X. (X = 0,1,2 or 3*/
-bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength);
-/* Set a new base and size for one of the memory banks (CS0 - CS3) */
-bool gtMemorySetMemoryBank(MEMORY_BANK bank, unsigned int bankBase,
-			   unsigned int bankSize);
-bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength);
-
-/* Change the Internal Register Base Address to a new given Address. */
-bool memoryMapInternalRegistersSpace(unsigned int internalRegBase);
-/* returns internal Register Space Base Address. */
-unsigned int memoryGetInternalRegistersSpace(void);
-
-/* Returns the integrated SRAM Base Address. */
-unsigned int memoryGetInternalSramBaseAddr(void);
-/* -------------------------------------------------------------------------------------------------*/
-
-/* Set new base address for the integrated SRAM. */
-void memorySetInternalSramBaseAddr(unsigned int sramBaseAddress);
-/* -------------------------------------------------------------------------------------------------*/
-
-/* Delete a protection feature to a given space. */
-void memoryDisableProtectRegion(MEMORY_PROTECT_WINDOW window);
-/* -------------------------------------------------------------------------------------------------*/
-
-/* Writes a new remap value to the remap register */
-unsigned int memorySetPciRemapValue(PCI_MEM_WINDOW memoryWindow,
-				      unsigned int remapValueHigh,
-				      unsigned int remapValueLow);
-/* -------------------------------------------------------------------------------------------------*/
-
-/* Configurate the protection feature to a given space. */
-bool memorySetProtectRegion(MEMORY_PROTECT_WINDOW window,
-			      MEMORY_ACCESS gtMemoryAccess,
-			      MEMORY_ACCESS_WRITE gtMemoryWrite,
-			      MEMORY_CACHE_PROTECT cacheProtection,
-			      unsigned int baseAddress,
-			      unsigned int size);
-
-/* Configurate the protection feature to a given space. */
-/*bool memorySetProtectRegion(MEMORY_PROTECT_REGION region,
-			    MEMORY_ACCESS memoryAccess,
-			    MEMORY_ACCESS_WRITE memoryWrite,
-			    MEMORY_CACHE_PROTECT cacheProtection,
-			    unsigned int baseAddress,
-			    unsigned int regionLength); */
-/* Configurate the snoop feature to a given space. */
-bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
-			      MEMORY_SNOOP_TYPE snoopType,
-			      unsigned int baseAddress,
-			      unsigned int regionLength);
-
-bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue);
-bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
-bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
-/* Set a new base and size for one of the PCI windows. */
-bool memorySetPciWindow(PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase,
-			  unsigned int pciWindowSize);
-
-/* Disable or enable one of the 21 windows dedicated for the CPU's
-   address decoding mechanism */
-void MemoryDisableWindow(MEMORY_WINDOW window);
-void MemoryEnableWindow (MEMORY_WINDOW window);
-MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus(MEMORY_WINDOW window);
-#endif	/* __INCmemoryh */

board/Marvell/include/pci.h

@@ -1,293 +0,0 @@
-/* PCI.h - PCI functions header file */
-
-/* Copyright - Galileo technology. */
-
-#ifndef __INCpcih
-#define __INCpcih
-
-/* includes */
-
-#include"core.h"
-#include"memory.h"
-
-/* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */
-#define PCI_MAX_DEVICES 22
-
-
-/* Macros */
-
-/* The next Macros configurate the initiator board (SELF) or any any agent on
-   the PCI to become: MASTER, response to MEMORY transactions , response to
-   IO transactions or TWO both MEMORY_IO transactions. Those configuration
-   are for both PCI0 and PCI1. */
-
-#define PCI_MEMORY_ENABLE(host, deviceNumber) pciWriteConfigReg(host,	       \
-	  PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE |		     \
-	  pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
-
-#define PCI_IO_ENABLE(host, deviceNumber) pciWriteConfigReg(host,	       \
-	  PCI_STATUS_AND_COMMAND,deviceNumber,I_O_ENABLE |		     \
-	  pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
-
-#define PCI_SLAVE_ENABLE(host, deviceNumber) pciWriteConfigReg(host,	       \
-	  PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | I_O_ENABLE |   \
-	  pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
-
-#define PCI_DISABLE(host, deviceNumber) pciWriteConfigReg(host,		       \
-	  PCI_STATUS_AND_COMMAND,deviceNumber,0xfffffff8  &		     \
-	  pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber))
-
-#define PCI_MASTER_ENABLE(host,deviceNumber) pciWriteConfigReg(host,	       \
-	  PCI_STATUS_AND_COMMAND,deviceNumber,MASTER_ENABLE |		     \
-	  pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) )
-
-#define PCI_MASTER_DISABLE(deviceNumber) pciWriteConfigReg(host,	      \
-	  PCI_STATUS_AND_COMMAND,deviceNumber,~MASTER_ENABLE &		     \
-	  pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) )
-
-#define		MASTER_ENABLE			BIT2
-#define		MEMORY_ENABLE			BIT1
-#define		I_O_ENABLE			BIT0
-#define	    SELF		    32
-
-/* Agent on the PCI bus may have up to 6 BARS. */
-#define	    BAR0		    0x10
-#define	    BAR1		    0x14
-#define	    BAR2		    0x18
-#define	    BAR3		    0x1c
-#define	    BAR4		    0x20
-#define	    BAR5		    0x24
-#define		BAR_SEL_MEM_IO			BIT0
-#define		BAR_MEM_TYPE_32_BIT		NO_BIT
-#define		BAR_MEM_TYPE_BELOW_1M		       BIT1
-#define		BAR_MEM_TYPE_64_BIT			      BIT2
-#define		BAR_MEM_TYPE_RESERVED		      (BIT1 | BIT2)
-#define		BAR_MEM_TYPE_MASK		      (BIT1 | BIT2)
-#define		BAR_PREFETCHABLE				      BIT3
-#define		BAR_CONFIG_MASK			(BIT0 | BIT1 | BIT2 | BIT3)
-
-/* Defines for the access regions. */
-#define	    PREFETCH_ENABLE		    BIT12
-#define	    PREFETCH_DISABLE		    NO_BIT
-#define	    DELAYED_READ_ENABLE		    BIT13
-/* #define     CACHING_ENABLE		       BIT14 */
-/* aggressive prefetch: PCI slave prefetch two burst in advance*/
-#define	    AGGRESSIVE_PREFETCH		     BIT16
-/* read line aggresive prefetch: PCI slave prefetch two burst in advance*/
-#define	    READ_LINE_AGGRESSIVE_PREFETCH   BIT17
-/* read multiple aggresive prefetch: PCI slave prefetch two burst in advance*/
-#define	    READ_MULTI_AGGRESSIVE_PREFETCH  BIT18
-#define	    MAX_BURST_4			    NO_BIT
-#define	    MAX_BURST_8			    BIT20  /* Bits[21:20] = 01 */
-#define	    MAX_BURST_16		    BIT21  /* Bits[21:20] = 10 */
-#define	    PCI_BYTE_SWAP		    NO_BIT /* Bits[25:24] = 00 */
-#define	    PCI_NO_SWAP			    BIT24  /* Bits[25:24] = 01 */
-#define	    PCI_BYTE_AND_WORD_SWAP	    BIT25  /* Bits[25:24] = 10 */
-#define	    PCI_WORD_SWAP		   (BIT24 | BIT25) /* Bits[25:24] = 11 */
-#define	    PCI_ACCESS_PROTECT		    BIT28
-#define	    PCI_WRITE_PROTECT		    BIT29
-
-/* typedefs */
-
-typedef enum __pciAccessRegions{REGION0,REGION1,REGION2,REGION3,REGION4,REGION5,
-				REGION6,REGION7} PCI_ACCESS_REGIONS;
-
-typedef enum __pciAgentPrio{LOW_AGENT_PRIO,HI_AGENT_PRIO} PCI_AGENT_PRIO;
-typedef enum __pciAgentPark{PARK_ON_AGENT,DONT_PARK_ON_AGENT} PCI_AGENT_PARK;
-
-typedef enum __pciSnoopType{PCI_NO_SNOOP,PCI_SNOOP_WT,PCI_SNOOP_WB}
-			    PCI_SNOOP_TYPE;
-typedef enum __pciSnoopRegion{PCI_SNOOP_REGION0,PCI_SNOOP_REGION1,
-			      PCI_SNOOP_REGION2,PCI_SNOOP_REGION3}
-			      PCI_SNOOP_REGION;
-
-typedef enum __memPciHost{PCI_HOST0,PCI_HOST1} PCI_HOST;
-typedef enum __memPciRegion{PCI_REGION0,PCI_REGION1,
-			 PCI_REGION2,PCI_REGION3,
-			 PCI_IO}
-			 PCI_REGION;
-
-/*ronen 7/Dec/03 */
-typedef enum __pci_bar_windows{PCI_CS0_BAR, PCI_CS1_BAR, PCI_CS2_BAR,
-			       PCI_CS3_BAR, PCI_DEV_CS0_BAR, PCI_DEV_CS1_BAR,
-			       PCI_DEV_CS2_BAR, PCI_DEV_CS3_BAR, PCI_BOOT_CS_BAR,
-			       PCI_MEM_INT_REG_BAR, PCI_IO_INT_REG_BAR,
-			       PCI_P2P_MEM0_BAR, PCI_P2P_MEM1_BAR,
-			       PCI_P2P_IO_BAR, PCI_CPU_BAR, PCI_INT_SRAM_BAR,
-			       PCI_LAST_BAR} PCI_INTERNAL_BAR;
-
-typedef struct pciBar {
-    unsigned int detectBase;
-    unsigned int base;
-    unsigned int size;
-    unsigned int type;
-} PCI_BAR;
-
-typedef struct pciDevice {
-    PCI_HOST	     host;
-    char	    type[40];
-    unsigned int    deviceNum;
-    unsigned int    venID;
-    unsigned int    deviceID;
-    PCI_BAR bar[6];
-} PCI_DEVICE;
-
-typedef struct pciSelfBars {
-    unsigned int    SCS0Base;
-    unsigned int    SCS0Size;
-    unsigned int    SCS1Base;
-    unsigned int    SCS1Size;
-    unsigned int    SCS2Base;
-    unsigned int    SCS2Size;
-    unsigned int    SCS3Base;
-    unsigned int    SCS3Size;
-    unsigned int    internalMemBase;
-    unsigned int    internalIOBase;
-    unsigned int    CS0Base;
-    unsigned int    CS0Size;
-    unsigned int    CS1Base;
-    unsigned int    CS1Size;
-    unsigned int    CS2Base;
-    unsigned int    CS2Size;
-    unsigned int    CS3Base;
-    unsigned int    CS3Size;
-    unsigned int    CSBootBase;
-    unsigned int    CSBootSize;
-    unsigned int    P2PMem0Base;
-    unsigned int    P2PMem0Size;
-    unsigned int    P2PMem1Base;
-    unsigned int    P2PMem1Size;
-    unsigned int    P2PIOBase;
-    unsigned int    P2PIOSize;
-    unsigned int    CPUBase;
-    unsigned int    CPUSize;
-} PCI_SELF_BARS;
-
-/* read/write configuration registers on local PCI bus. */
-void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset,
-		       unsigned int pciDevNum, unsigned int data);
-unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
-			       unsigned int pciDevNum);
-
-/* read/write configuration registers on another PCI bus. */
-void pciOverBridgeWriteConfigReg(PCI_HOST host,
-				 unsigned int regOffset,
-				 unsigned int pciDevNum,
-				 unsigned int busNum,unsigned int data);
-unsigned int pciOverBridgeReadConfigReg(PCI_HOST host,
-					unsigned int regOffset,
-					unsigned int pciDevNum,
-					unsigned int busNum);
-
-/* Performs full scane on both PCI and returns all detail possible on the
-   agents which exist on the bus. */
-void pciScanDevices(PCI_HOST host, PCI_DEVICE *pci0Detect,
-		    unsigned int numberOfElment);
-
-/*	Master`s memory space	*/
-bool pciMapSpace(PCI_HOST host, PCI_REGION region,
-		unsigned int remapBase,
-		unsigned int deviceBase,
-		unsigned int deviceLength);
-unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region);
-unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region);
-
-/*	Slave`s memory space   */
-void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank,
-		      unsigned int pci0Dram0Base, unsigned int pci0Dram0Size);
-
-#if 0 /* GARBAGE routines - dont use till they get cleaned up */
-void pci0ScanSelfBars(PCI_SELF_BARS *pci0SelfBars);
-void pci1ScanSelfBars(PCI_SELF_BARS *pci1SelfBars);
-void pci0MapInternalRegSpace(unsigned int pci0InternalBase);
-void pci1MapInternalRegSpace(unsigned int pci1InternalBase);
-void pci0MapInternalRegIOSpace(unsigned int pci0InternalBase);
-void pci1MapInternalRegIOSpace(unsigned int pci1InternalBase);
-void pci0MapDevice0MemorySpace(unsigned int pci0Dev0Base,
-			       unsigned int pci0Dev0Length);
-void pci1MapDevice0MemorySpace(unsigned int pci1Dev0Base,
-			       unsigned int pci1Dev0Length);
-void pci0MapDevice1MemorySpace(unsigned int pci0Dev1Base,
-			       unsigned int pci0Dev1Length);
-void pci1MapDevice1MemorySpace(unsigned int pci1Dev1Base,
-			       unsigned int pci1Dev1Length);
-void pci0MapDevice2MemorySpace(unsigned int pci0Dev2Base,
-			       unsigned int pci0Dev2Length);
-void pci1MapDevice2MemorySpace(unsigned int pci1Dev2Base,
-			       unsigned int pci1Dev2Length);
-void pci0MapDevice3MemorySpace(unsigned int pci0Dev3Base,
-			       unsigned int pci0Dev3Length);
-void pci1MapDevice3MemorySpace(unsigned int pci1Dev3Base,
-			       unsigned int pci1Dev3Length);
-void pci0MapBootDeviceMemorySpace(unsigned int pci0DevBootBase,
-				  unsigned int pci0DevBootLength);
-void pci1MapBootDeviceMemorySpace(unsigned int pci1DevBootBase,
-				  unsigned int pci1DevBootLength);
-void pci0MapP2pMem0Space(unsigned int pci0P2pMem0Base,
-			 unsigned int pci0P2pMem0Length);
-void pci1MapP2pMem0Space(unsigned int pci1P2pMem0Base,
-			 unsigned int pci1P2pMem0Length);
-void pci0MapP2pMem1Space(unsigned int pci0P2pMem1Base,
-			 unsigned int pci0P2pMem1Length);
-void pci1MapP2pMem1Space(unsigned int pci1P2pMem1Base,
-			 unsigned int pci1P2pMem1Length);
-void pci0MapP2pIoSpace(unsigned int pci0P2pIoBase,
-		       unsigned int pci0P2pIoLength);
-void pci1MapP2pIoSpace(unsigned int pci1P2pIoBase,
-		       unsigned int pci1P2pIoLength);
-
-void pci0MapCPUspace(unsigned int pci0CpuBase, unsigned int pci0CpuLengs);
-void pci1MapCPUspace(unsigned int pci1CpuBase, unsigned int pci1CpuLengs);
-#endif
-
-/* PCI region options */
-
-bool  pciSetRegionFeatures(PCI_HOST host, PCI_ACCESS_REGIONS region,
-	unsigned int features, unsigned int baseAddress,
-	unsigned int regionLength);
-
-void  pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region);
-
-/* PCI arbiter */
-
-bool pciArbiterEnable(PCI_HOST host);
-bool pciArbiterDisable(PCI_HOST host);
-bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent,
-				  PCI_AGENT_PRIO externalAgent0,
-				  PCI_AGENT_PRIO externalAgent1,
-				  PCI_AGENT_PRIO externalAgent2,
-				  PCI_AGENT_PRIO externalAgent3,
-				  PCI_AGENT_PRIO externalAgent4,
-				  PCI_AGENT_PRIO externalAgent5);
-bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent,
-				  PCI_AGENT_PRIO externalAgent0,
-				  PCI_AGENT_PRIO externalAgent1,
-				  PCI_AGENT_PRIO externalAgent2,
-				  PCI_AGENT_PRIO externalAgent3,
-				  PCI_AGENT_PRIO externalAgent4,
-				  PCI_AGENT_PRIO externalAgent5);
-bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent,
-			PCI_AGENT_PARK externalAgent0,
-			PCI_AGENT_PARK externalAgent1,
-			PCI_AGENT_PARK externalAgent2,
-			PCI_AGENT_PARK externalAgent3,
-			PCI_AGENT_PARK externalAgent4,
-			PCI_AGENT_PARK externalAgent5);
-bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue);
-bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue);
-
-/* PCI-to-PCI (P2P) */
-
-bool pciP2PConfig(PCI_HOST host,
-		  unsigned int SecondBusLow,unsigned int SecondBusHigh,
-		  unsigned int busNum,unsigned int devNum);
-/* PCI Cache-coherency */
-
-bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region,
-			    PCI_SNOOP_TYPE snoopType,
-			    unsigned int baseAddress,
-			    unsigned int regionLength);
-
-PCI_DEVICE * pciFindDevice(unsigned short ven, unsigned short dev);
-
-#endif /* __INCpcih */

board/RPXClassic/RPXClassic.c

@@ -220,10 +220,42 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize
 {
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	volatile long int *addr;
+	ulong cnt, val;
+	ulong save[32];			/* to make test non-destructive */
+	unsigned char i = 0;
 
 	memctl->memc_mamr = mamr_value;
 
-	return (get_ram_size(base, maxsize));
+	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
+		addr = base + cnt;	/* pointer arith! */
+
+		save[i++] = *addr;
+		*addr = ~cnt;
+	}
+
+	/* write 0 to base address */
+	addr = base;
+	save[i] = *addr;
+	*addr = 0;
+
+	/* check at base address */
+	if ((val = *addr) != 0) {
+		*addr = save[i];
+		return (0);
+	}
+
+	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+		addr = base + cnt;		/* pointer arith! */
+
+		val = *addr;
+		*addr = save[--i];
+
+		if (val != (~cnt)) {
+			return (cnt * sizeof (long));
+		}
+	}
+	return (maxsize);
 }
 /*-----------------------------------------------------------------------------
  * aschex_to_byte --

board/RPXlite/RPXlite.c

@@ -40,19 +40,20 @@ static long int dram_size (long int, long int *, long int);
 
 #define	_NOT_USED_	0xFFFFCC25
 
-const uint sdram_table[] = {
+const uint sdram_table[] =
+{
 	/*
 	 * Single Read. (Offset 00h in UPMA RAM)
 	 */
 	0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08,
-	0x3FBFCC27,		/* last */
+	0x3FBFCC27, /* last */
 	_NOT_USED_, _NOT_USED_, _NOT_USED_,
 
 	/*
 	 * Burst Read. (Offset 08h in UPMA RAM)
 	 */
 	0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88,
-	0x3FBFCC27,		/* last */
+	0x3FBFCC27, /* last */
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 	_NOT_USED_, _NOT_USED_, _NOT_USED_,
@@ -61,14 +62,14 @@ const uint sdram_table[] = {
 	 * Single Write. (Offset 18h in UPMA RAM)
 	 */
 	0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00,
-	0x3FFFCC27,		/* last */
+	0x3FFFCC27, /* last */
 	_NOT_USED_, _NOT_USED_, _NOT_USED_,
 
 	/*
 	 * Burst Write. (Offset 20h in UPMA RAM)
 	 */
 	0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C,
-	0x0CFFCC00, 0x33FFCC27,	/* last */
+	0x0CFFCC00, 0x33FFCC27, /* last */
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 	_NOT_USED_, _NOT_USED_,
@@ -77,7 +78,7 @@ const uint sdram_table[] = {
 	 * Refresh. (Offset 30h in UPMA RAM)
 	 */
 	0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24,
-	0x3FFFCC27,		/* last */
+	0x3FFFCC27, /* last */
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 	_NOT_USED_, _NOT_USED_, _NOT_USED_,
 
@@ -96,51 +97,49 @@ const uint sdram_table[] = {
 
 int checkboard (void)
 {
-	puts ("Board: RPXlite\n");
-	return (0);
+	puts ("Board: RPXlite\n") ;
+	return (0) ;
 }
 
 /* ------------------------------------------------------------------------- */
 
 long int initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	long int size10;
+    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile memctl8xx_t *memctl = &immap->im_memctl;
+    long int size10 ;
 
-	upmconfig (UPMA, (uint *) sdram_table,
-		   sizeof (sdram_table) / sizeof (uint));
+    upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
 
 	/* Refresh clock prescalar */
-	memctl->memc_mptpr = CFG_MPTPR;
+    memctl->memc_mptpr = CFG_MPTPR ;
 
-	memctl->memc_mar = 0x00000000;
+    memctl->memc_mar  = 0x00000000;
 
 	/* Map controller banks 1 to the SDRAM bank */
-	memctl->memc_or1 = CFG_OR1_PRELIM;
-	memctl->memc_br1 = CFG_BR1_PRELIM;
+    memctl->memc_or1 = CFG_OR1_PRELIM;
+    memctl->memc_br1 = CFG_BR1_PRELIM;
 
-	memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE));	/* no refresh yet */
+    memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */
 
-	udelay (200);
+    udelay(200);
 
-	/* perform SDRAM initializsation sequence */
+    /* perform SDRAM initializsation sequence */
 
-	memctl->memc_mcr = 0x80002230;	/* SDRAM bank 0 - refresh twice */
-	udelay (1);
+	memctl->memc_mcr  = 0x80002230 ; /* SDRAM bank 0 - refresh twice */
+    udelay(1);
 
-	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+    memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
 
-	udelay (1000);
+    udelay (1000);
 
 	/* Check Bank 0 Memory Size
 	 * try 10 column mode
 	 */
 
-	size10 = dram_size (CFG_MAMR_10COL, (ulong *) SDRAM_BASE_PRELIM,
-			    SDRAM_MAX_SIZE);
+	size10 = dram_size (CFG_MAMR_10COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE) ;
 
-	return (size10);
+    return (size10);
 }
 
 /* ------------------------------------------------------------------------- */
@@ -153,13 +152,44 @@ long int initdram (int board_type)
  * - short between data lines
  */
 
-static long int dram_size (long int mamr_value, long int *base,
-			   long int maxsize)
+static long int dram_size (long int mamr_value, long int *base, long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
+    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile memctl8xx_t *memctl = &immap->im_memctl;
+    volatile long int	 *addr;
+    ulong		  cnt, val;
+    ulong		  save[32];	/* to make test non-destructive */
+    unsigned char	  i = 0;
 
-	memctl->memc_mamr = mamr_value;
+    memctl->memc_mamr = mamr_value;
 
-	return (get_ram_size (base, maxsize));
+    for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
+	addr = base + cnt;	/* pointer arith! */
+
+	save[i++] = *addr;
+	*addr = ~cnt;
+    }
+
+    /* write 0 to base address */
+    addr = base;
+    save[i] = *addr;
+    *addr = 0;
+
+    /* check at base address */
+    if ((val = *addr) != 0) {
+	*addr = save[i];
+	return (0);
+    }
+
+    for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
+	addr = base + cnt;	/* pointer arith! */
+
+	val = *addr;
+	*addr = save[--i];
+
+	if (val != (~cnt)) {
+	    return (cnt * sizeof(long));
+	}
+    }
+    return (maxsize);
 }

board/RRvision/RRvision.c

@@ -229,8 +229,40 @@ static long int dram_size (long int mamr_value, long int *base,
 {
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	volatile long int *addr;
+	ulong cnt, val;
+	ulong save[32];			/* to make test non-destructive */
+	unsigned char i = 0;
 
 	memctl->memc_mamr = mamr_value;
 
-	return (get_ram_size(base, maxsize));
+	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
+		addr = base + cnt;	/* pointer arith! */
+
+		save[i++] = *addr;
+		*addr = ~cnt;
+	}
+
+	/* write 0 to base address */
+	addr = base;
+	save[i] = *addr;
+	*addr = 0;
+
+	/* check at base address */
+	if ((val = *addr) != 0) {
+		*addr = save[i];
+		return (0);
+	}
+
+	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+		addr = base + cnt;	/* pointer arith! */
+
+		val = *addr;
+		*addr = save[--i];
+
+		if (val != (~cnt)) {
+			return (cnt * sizeof (long));
+		}
+	}
+	return (maxsize);
 }

board/RRvision/video_ad7179.h

@@ -1,68 +0,0 @@
-/*
- * (C) Copyright 2003 Wolfgang Grandegger <wg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#define VIDEO_ENCODER_NAME	"Analog Devices AD7179"
-
-#define VIDEO_ENCODER_I2C_RATE	100000	/* Max rate is 100Khz	*/
-#define VIDEO_ENCODER_CB_Y_CR_Y		/* Use CB Y CR Y format...	*/
-
-#define VIDEO_MODE_YUYV		/* The only mode supported by this encoder	*/
-#undef	VIDEO_MODE_RGB
-#define VIDEO_MODE_BPP		16
-
-#ifdef	VIDEO_MODE_PAL
-#define VIDEO_ACTIVE_COLS	720
-#define VIDEO_ACTIVE_ROWS	576
-#define VIDEO_VISIBLE_COLS	640
-#define VIDEO_VISIBLE_ROWS	480
-#else
-#error "NTSC mode is not supported"
-#endif
-
-static unsigned char video_encoder_data[] = {
-				0x05, /* Mode Register 0 */
-				0x11, /* Mode Register 1 */
-				0x20, /* Mode Register 2 */
-				0x0C, /* Mode Register 3 */
-				0x01, /* Mode Register 4 */
-				0x00, /* Reserved */
-				0x00, /* Reserved */
-				0x04, /* Timing Register 0 */
-				0x00, /* Timing Register 1 */
-				0xCB, /* Subcarrier Frequency Register 0 */
-				0x0A, /* Subcarrier Frequency Register 1 */
-				0x09, /* Subcarrier Frequency Register 2 */
-				0x2A, /* Subcarrier Frequency Register 3 */
-				0x00, /* Subcarrier Phase */
-				0x00, /* Closed Captioning Ext Reg 0 */
-				0x00, /* Closed Captioning Ext Reg 1 */
-				0x00, /* Closed Captioning Reg 0 */
-				0x00, /* Closed Captioning Reg 1 */
-				0x00, /* Pedestal Control Reg 0 */
-				0x00, /* Pedestal Control Reg 1 */
-				0x00, /* Pedestal Control Reg 2 */
-				0x00, /* Pedestal Control Reg 3 */
-				0x00, /* CGMS_WSS Reg 0 */
-				0x00, /* CGMS_WSS Reg 0 */
-				0x00, /* CGMS_WSS Reg 0 */
-				0x00  /* Teletext Req. Control Reg */
-} ;

board/a3000/a3000.c

@@ -2,9 +2,6 @@
  * (C) Copyright 2001
  * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
  *
- * Modified during 2003 by
- * Ken Chou, kchou@ieee.org
- *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -40,65 +37,101 @@ int checkboard (void)
 
 long int initdram (int board_type)
 {
-	long size;
-	long new_bank0_end;
-	long mear1;
-	long emear1;
+	int              i, cnt;
+	volatile uchar * base= CFG_SDRAM_BASE;
+	volatile ulong * addr;
+	ulong            save[32];
+	ulong            val, ret  = 0;
 
-	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+	for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
+		addr = (volatile ulong *)base + cnt;
+		save[i++] = *addr;
+		*addr = ~cnt;
+	}
 
-	new_bank0_end = size - 1;
-	mear1 = mpc824x_mpc107_getreg(MEAR1);
-	emear1 = mpc824x_mpc107_getreg(EMEAR1);
-	mear1 = (mear1  & 0xFFFFFF00) |
-		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
-	emear1 = (emear1 & 0xFFFFFF00) |
-		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
-	mpc824x_mpc107_setreg(MEAR1, mear1);
-	mpc824x_mpc107_setreg(EMEAR1, emear1);
+	addr = (volatile ulong *)base;
+	save[i] = *addr;
+	*addr = 0;
 
-	return (size);
+	if (*addr != 0) {
+		*addr = save[i];
+		goto Done;
+	}
+
+	for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
+		addr = (volatile ulong *)base + cnt;
+		val = *addr;
+		*addr = save[--i];
+		if (val != ~cnt) {
+			ulong new_bank0_end = cnt * sizeof(long) - 1;
+			ulong mear1  = mpc824x_mpc107_getreg(MEAR1);
+			ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
+			mear1 =  (mear1  & 0xFFFFFF00) |
+			  ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+			emear1 = (emear1 & 0xFFFFFF00) |
+			  ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+			mpc824x_mpc107_setreg(MEAR1,  mear1);
+			mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+			ret = cnt * sizeof(long);
+			goto Done;
+		}
+	}
+
+	ret = CFG_MAX_RAM_SIZE;
+Done:
+	return ret;
 }
 
 /*
  * Initialize PCI Devices
  */
+#if 1
 #ifndef CONFIG_PCI_PNP
 static struct pci_config_table pci_a3000_config_table[] = {
-	/* vendor, device, class */
-	/* bus, dev, func */
-	{ PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815, PCI_ANY_ID,
-	  PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,	/* dp83815 eth0 divice */
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	  0x0, 0x0, 0x0, /* unknown eth0 divice */
 	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
 				       PCI_ENET0_MEMADDR,
 				       PCI_COMMAND_IO |
 				       PCI_COMMAND_MEMORY |
 				       PCI_COMMAND_MASTER }},
 	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-	  PCI_ANY_ID, 0x14, PCI_ANY_ID,		/* PCI slot1 */
+	  0x0, 0x0, 0x0, /* unknown eth1 device */
 	  pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
 				       PCI_ENET1_MEMADDR,
 				       PCI_COMMAND_IO |
 				       PCI_COMMAND_MEMORY |
 				       PCI_COMMAND_MASTER }},
 	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-	  PCI_ANY_ID, 0x15, PCI_ANY_ID, 	/* PCI slot2 */
+	  0x0, 0x0, 0x0, /* unknown eth1 device */
 	  pci_cfgfunc_config_device, { PCI_ENET2_IOADDR,
 				       PCI_ENET2_MEMADDR,
 				       PCI_COMMAND_IO |
 				       PCI_COMMAND_MEMORY |
 				       PCI_COMMAND_MASTER }},
-	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-	  PCI_ANY_ID, 0x16, PCI_ANY_ID,		/* PCI slot3 */
-	  pci_cfgfunc_config_device, { PCI_ENET3_IOADDR,
-				       PCI_ENET3_MEMADDR,
-				       PCI_COMMAND_IO |
-				       PCI_COMMAND_MEMORY |
-				       PCI_COMMAND_MASTER }},
 	{ }
 };
 #endif
 
+#else
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_a3000_config_table[] = {
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
+				       PCI_ENET1_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ }
+};
+#endif
+
+#endif
+
 struct pci_controller hose = {
 #ifndef CONFIG_PCI_PNP
 	config_table: pci_a3000_config_table,

board/adderII/Makefile

@@ -1,40 +0,0 @@
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= lib$(BOARD).a
-
-OBJS	= $(BOARD).o flash.o
-
-$(LIB):	.depend $(OBJS)
-	$(AR) crv $@ $(OBJS)
-
-#########################################################################
-
-.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
-		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-
-sinclude .depend
-
-#########################################################################

board/adderII/adderII.c

@@ -1,189 +0,0 @@
-/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <config.h>
-#include <mpc8xx.h>
-
-/*
- * Check Board Identity:
- */
-
-int checkboard( void )
-{
-	puts("Board: ");
-	puts("AdderII(MPC852T)\n" );
-
-  	return 0;
-}
-
-#if defined( CONFIG_SDRAM_50MHZ )
-
-/******************************************************************************
-** for chip Samsung K4S643232F - T70
-** this table is for 32-50MHz operation
-*******************************************************************************/
-
-#define SDRAM_MPTPRVALUE 	0x0200
-
-#define SDRAM_MAMRVALUE0 	0x00802114   /* refresh at 32MHz */
-#define SDRAM_MAMRVALUE1 	0x00802118
-
-#define SDRAM_OR1VALUE   	0xff800e00
-#define SDRAM_BR1VALUE   	0x00000081
-
-#define SDRAM_MARVALUE		94
-
-#define SDRAM_MCRVALUE0  	0x80808105
-#define SDRAM_MCRVALUE1  	0x80808130
-
-const uint sdram_table[] = {
-
-	/* single read   (offset 0x00 in upm ram) */
-       	0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00,
-       	0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04,
-
-	/* burst read    (offset 0x08 in upm ram) */
-       	0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00,
-       	0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44,
-       	0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35,
-       	0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35,
-
-	/* single write  (offset 0x18 in upm ram) */
-       	0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47,
-       	0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-
-	/* burst write   (offset 0x20 in upm ram) */
-       	0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
-       	0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04,
-       	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-       	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-
-	/* refresh       (offset 0x30 in upm ram) */
-       	0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-       	0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04,
-       	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-
-	/* exception     (offset 0x3C in upm ram) */
-       	0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-};
-
-#else
-#error SDRAM not correctly configured
-#endif
-
-int _initsdram (uint base, uint noMbytes)
-{
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-	if (noMbytes != 8) {
-		return -1;
-	}
-
-	upmconfig (UPMA, (uint *) sdram_table,
-		   sizeof (sdram_table) / sizeof (uint));
-
-	memctl->memc_mptpr = SDRAM_MPTPRVALUE;
-
-	/* Configure the refresh (mostly).  This needs to be
-	 * based upon processor clock speed and optimized to provide
-	 * the highest level of performance.  For multiple banks,
-	 * this time has to be divided by the number of banks.
-	 * Although it is not clear anywhere, it appears the
-	 * refresh steps through the chip selects for this UPM
-	 * on each refresh cycle.
-	 * We have to be careful changing
-	 * UPM registers after we ask it to run these commands.
-	 */
-
-	memctl->memc_mamr = (SDRAM_MAMRVALUE0 | (SDRAM_MARVALUE << 24));
-	memctl->memc_mar = 0x0;
-	udelay (200);
-
-	/* Now run the precharge/nop/mrs commands.
-	 */
-	memctl->memc_mcr = 0x80002115;
-	udelay (200);
-
-	/* Run 8 refresh cycles */
-	memctl->memc_mcr = 0x80002380;
-	udelay (200);
-
-	memctl->memc_mar = 0x88;
-	udelay (200);
-
-	memctl->memc_mcr = 0x80002116;
-	udelay (200);
-
-	memctl->memc_or1 = SDRAM_OR1VALUE;
-	memctl->memc_br1 = SDRAM_BR1VALUE | base;
-
-	return 0;
-}
-
-void _sdramdisable( void )
-{
-	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-	memctl->memc_br1 = 0x00000000;
-
-	/* maybe we should turn off upma here or something */
-}
-
-int initsdram (uint base, uint * noMbytes)
-{
-	uint m = 8;
-
-	*noMbytes = m;
-
-	if (!_initsdram (base, m)) {
-		return 0;
-	} else {
-		_sdramdisable ();
-		return -1;
-	}
-}
-
-long int initdram (int board_type)
-{
-	/* AdderII: has 8MB SDRAM */
-	uint sdramsz;
-	uint m = 0;
-
-	if (!initsdram (0x00000000, &sdramsz)) {
-		m += sdramsz;
-	} else {
-		return -1;
-	}
-	return (m << 20);
-}
-
-int testdram (void)
-{
-	/* TODO: XXX XXX XXX not an actual SDRAM test */
-	printf ("Test: 8MB SDRAM\n");
-
-	return (0);
-}

board/adderII/adderII.h

@@ -1,43 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/****************************************************************************
- * FLASH Memory Map as used by FADS Monitor:
- *
- *                          Start Address    Length
- * +-----------------------+ 0xFE00_0000     Start of Flash -----------------
- * | MON8xx code           | 0xFE00_0100     Reset Vector
- * +-----------------------+ 0xFE0?_????
- * | (unused)              |
- * +-----------------------+
- * | 			   |
- * +-----------------------+
- * | 			   |
- * +-----------------------+
- * | 			   |
- * +-----------------------+
- * | 			   |
- * +=======================+
- * | 			   |
- * | ...                   |
- *****************************************************************************/

board/adderII/config.mk

@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# AdderII board ( Analogue-Micro )
-#
-
-TEXT_BASE = 0xFE000000

board/adderII/flash.c

@@ -1,501 +0,0 @@
-/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-/******************************************************************************
-** Notes: AM29LV320DB - 90EI ( 32 Mbit device )
-** Sectors - Eight 8 Kb sector
-** 	   - Sixty three 64 Kb sector
-** Bottom boot sector
-******************************************************************************/
-#include <common.h>
-#include <mpc8xx.h>
-
-
-/******************************************************************************
-**	Defines
-******************************************************************************/
-#ifdef CONFIG_ADDERII
-
-#define ADDR0	0x0555
-#define ADDR1	0x02AA
-#define FLASH_WORD_SIZE unsigned short
-
-#endif
-
-#if defined( CFG_ENV_IS_IN_FLASH )
-# ifndef  CFG_ENV_ADDR
-#  define CFG_ENV_ADDR  ( CFG_FLASH_BASE + CFG_ENV_OFFSET )
-# endif
-# ifndef  CFG_ENV_SIZE
-#  define CFG_ENV_SIZE  CFG_ENV_SECT_SIZE
-# endif
-# ifndef  CFG_ENV_SECT_SIZE
-#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
-# endif
-#endif
-
-/******************************************************************************
-**	Global Parameters
-******************************************************************************/
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
-
-/******************************************************************************
-**	Function Prototypes
-******************************************************************************/
-static ulong flash_get_size( vu_long *addr, flash_info_t *info );
-
-static int write_word( flash_info_t *info, ulong dest, ulong data );
-
-static void flash_get_offsets( ulong base, flash_info_t *info );
-
-int wait_for_DQ7( flash_info_t *info, int sect );
-
-/******************************************************************************
-** Function :	flash_init
-** Param    :   void
-** Notes    :   Initializes the Flash Chip
-******************************************************************************/
-ulong flash_init (void)
-{
-	ulong size_b0 = -1;
-	int i;
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-	/* Set Flash to unknown */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	/* Get the Flash Bank Size */
-
-	size_b0 = flash_get_size ((vu_long *) (CFG_FLASH_BASE),
-				  &flash_info[0]);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-		printf ("## UNKNOWN Flash on Bank 0 - Size = 0x%08lx = %ldMB\n",
-			size_b0, size_b0 >> 20);
-	}
-
-	/* Remap Flash according to size detected  */
-	memctl->memc_or0 = 0xFF800774;
-	memctl->memc_br0 = CFG_BR0_PRELIM;
-
-	/* Setup Flash Sector Offsets */
-
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
-
-	/* Monitor Protection ON - default */
-
-#if ( CFG_MONITOR_BASE >= CFG_FLASH_BASE  )
-	flash_protect (FLAG_PROTECT_SET, CFG_MONITOR_BASE,
-		       (CFG_MONITOR_BASE + monitor_flash_len - 1),
-		       &flash_info[0]);
-#endif
-
-	/* Protect Environment Variables */
-#ifdef CFG_ENV_IS_IN_FLASH
-	flash_protect (FLAG_PROTECT_SET, CFG_ENV_ADDR,
-		       (CFG_ENV_ADDR + CFG_ENV_SIZE - 1), &flash_info[0]);
-#endif
-
-	return size_b0;
-}
-
-/******************************************************************************
-** Function : flash_get_offsets
-** Param    : ulong base, flash_into_t *info
-** Notes    :
-******************************************************************************/
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
-	return;
-}
-
-
-/******************************************************************************
-** Function : flash_print_info
-** Param    : flash_info_t
-** Notes    :
-******************************************************************************/
-void flash_print_info (flash_info_t * info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("Missing or unknown flash type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:
-		printf ("AMD ");
-		break;
-	case FLASH_MAN_FUJ:
-		printf ("FUJITSU ");
-		break;
-	case FLASH_MAN_BM:
-		printf ("BRIGHT MICRO ");
-		break;
-	default:
-		printf ("Unknown Vendor ");
-		break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AM320B:
-		printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
-		break;
-	case FLASH_AM320T:
-		printf ("AM29LV320T (32 Mbit, top boot sector)\n");
-		break;
-	default:
-		printf ("Unknown Chip Type\n");
-		break;
-
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n", info->size >> 20,
-		info->sector_count);
-	printf ("  Sector Start Addresses:");
-
-	for (i = 0; i < info->sector_count; ++i) {
-		if ((i % 5) == 0) {
-			printf ("\n   ");
-		}
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     ");
-	}
-	printf ("\n");
-	return;
-}
-
-/******************************************************************************
-** Function : flash_get_size
-** Param    : vu_long *addr, flash_info_t *info
-** Notes    :
-******************************************************************************/
-static ulong flash_get_size (vu_long * addr, flash_info_t * info)
-{
-	short i;
-	FLASH_WORD_SIZE manu_id, dev_id;
-	ulong base = (ulong) addr;
-	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
-
-	/* Write Auto Select Command and read Manufacturer's ID and Dev ID */
-
-	addr2[ADDR0] = (FLASH_WORD_SIZE) 0xAAAAAAAA;
-	addr2[ADDR1] = (FLASH_WORD_SIZE) 0x55555555;
-	addr2[ADDR0] = (FLASH_WORD_SIZE) 0x90909090;
-
-	manu_id = addr2[0];
-
-	switch (manu_id) {
-	case (FLASH_WORD_SIZE) AMD_MANUFACT:
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		break;
-	}
-
-	/* Read Device Id */
-	dev_id = addr2[1];
-
-	switch (dev_id) {
-	case (FLASH_WORD_SIZE) AMD_ID_LV320B:
-		info->flash_id += FLASH_AM320B;
-		info->sector_count = 71;	/* 8 - boot sec + 63 normal */
-		info->size = 0x400000;	/* 4MByte */
-		break;
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		break;
-	}
-
-	/* Set up sector start Addresses */
-
-	if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block
-		 ** Eight 8 Kb Boot sectors
-		 ** Sixty Three 64Kb sectors
-		 */
-		for (i = 0; i < 8; i++) {
-			info->start[i] = base + (i * 0x00002000);
-		}
-		for (i = 8; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00010000) - 0x00070000;
-		}
-	}
-
-	/* Reset To read mode */
-
-	if (info->flash_id != FLASH_UNKNOWN) {
-		addr = (ulong *) info->start[0];
-		*addr = 0xF0F0F0F0;
-	}
-	return (info->size);
-}
-
-/*******************************************************************************
-** Function : flash_erase
-** Param    : flash_info_t *info, int s_first, int s_last
-** Notes    :
-******************************************************************************/
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
-	volatile FLASH_WORD_SIZE *addr2;
-	int flag, prot, sect, l_sect;
-	int i;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("Can't erase unknown flash type - aborted\n");
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-	l_sect = -1;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last; sect++) {
-
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
-
-			if ((info->flash_id & FLASH_VENDMASK) ==
-			    FLASH_MAN_SST) {
-				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
-				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
-				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
-				addr2[0] = (FLASH_WORD_SIZE) 0x00500050;	/* block erase */
-				for (i = 0; i < 50; i++)
-					udelay (1000);	/* wait 1 ms */
-			} else {
-				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
-				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
-				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
-				addr2[0] = (FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
-			}
-			l_sect = sect;
-			/*
-			 * Wait for each sector to complete, it's more
-			 * reliable.  According to AMD Spec, you must
-			 * issue all erase commands within a specified
-			 * timeout.  This has been seen to fail, especially
-			 * if printf()s are included (for debug)!!
-			 */
-			wait_for_DQ7 (info, sect);
-		}
-	}
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts ();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay (1000);
-
-	/* reset to read mode */
-	addr = (FLASH_WORD_SIZE *) info->start[0];
-	addr[0] = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
-
-	printf (" done\n");
-	return 0;
-}
-
-int wait_for_DQ7 (flash_info_t * info, int sect)
-{
-	ulong start, now, last;
-	volatile FLASH_WORD_SIZE *addr =
-		(FLASH_WORD_SIZE *) (info->start[sect]);
-
-	start = get_timer (0);
-	last = start;
-	while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
-	       (FLASH_WORD_SIZE) 0x00800080) {
-		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
-			printf ("Timeout\n");
-			return -1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {
-			putc ('.');
-			last = now;
-		}
-	}
-	return 0;
-}
-
-
-/******************************************************************************
-** Function : write_buff
-** Param    : flash_info_t *info, uchar *src, ulong addr, ulong cnt
-** Notes    :
-******************************************************************************/
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-
-	/* get lower word aligned address */
-	wp = (addr & ~3);
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i = 0, cp = wp; i < l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *) cp);
-		}
-		for (; i < 4 && cnt > 0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt == 0 && i < 4; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *) cp);
-		}
-
-		if ((rc = write_word (info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-		for (i = 0; i < 4; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_word (info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i < 4; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *) cp);
-	}
-
-	return (write_word (info, wp, data));
-}
-
-
-/******************************************************************************
-** Function : write_word
-** Param    : flash_info_t *info, ulong dest, ulong data
-** Notes    :
-******************************************************************************/
-static int write_word (flash_info_t * info, ulong dest, ulong data)
-{
-	volatile FLASH_WORD_SIZE *addr2 =
-		(FLASH_WORD_SIZE *) (info->start[0]);
-	volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
-	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
-	ulong start;
-	int i;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((volatile FLASH_WORD_SIZE *) dest) &
-	     (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
-		return (2);
-	}
-
-	for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
-		int flag;
-
-		/* Disable interrupts which might cause a timeout here */
-		flag = disable_interrupts ();
-
-		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
-		addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
-		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
-
-		dest2[i] = data2[i];
-
-		/* re-enable interrupts if necessary */
-		if (flag)
-			enable_interrupts ();
-
-		/* data polling for D7 */
-		start = get_timer (0);
-		while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
-		       (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
-			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
-				return (1);
-			}
-		}
-	}
-
-	return (0);
-}

board/adderII/u-boot.lds

@@ -1,146 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .interp : { *(.interp) }
-  .hash          : { *(.hash)		}
-  .dynsym        : { *(.dynsym)		}
-  .dynstr        : { *(.dynstr)		}
-  .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
-  .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
-  .rel.got       : { *(.rel.got)		}
-  .rela.got      : { *(.rela.got)		}
-  .rel.ctors     : { *(.rel.ctors)	}
-  .rela.ctors    : { *(.rela.ctors)	}
-  .rel.dtors     : { *(.rel.dtors)	}
-  .rela.dtors    : { *(.rela.dtors)	}
-  .rel.bss       : { *(.rel.bss)		}
-  .rela.bss      : { *(.rela.bss)		}
-  .rel.plt       : { *(.rel.plt)		}
-  .rela.plt      : { *(.rela.plt)		}
-  .init          : { *(.init)	}
-  .plt : { *(.plt) }
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
-
-    cpu/mpc8xx/start.o	(.text)
-/*
-    cpu/mpc8xx/start.o	(.text)
-    common/dlmalloc.o	(.text)
-    lib_ppc/ppcstring.o	(.text)
-    lib_generic/vsprintf.o	(.text)
-    lib_generic/crc32.o		(.text)
-    lib_generic/zlib.o		(.text)
-
-    . = env_offset;
-    common/environment.o(.text)
-*/
-
-    *(.text)
-    *(.fixup)
-    *(.got1)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(.rodata)
-    *(.rodata1)
-    *(.rodata.str1.4)
-  }
-  .fini      : { *(.fini)    } =0
-  .ctors     : { *(.ctors)   }
-  .dtors     : { *(.dtors)   }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    *(.got)
-    _GOT2_TABLE_ = .;
-    *(.got2)
-    _FIXUP_TABLE_ = .;
-    *(.fixup)
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data)
-    *(.data1)
-    *(.sdata)
-    *(.sdata2)
-    *(.dynamic)
-    CONSTRUCTORS
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss       :
-  {
-   *(.sbss) *(.scommon)
-   *(.dynbss)
-   *(.bss)
-   *(COMMON)
-  }
-  . = ALIGN(256 * 1024);
-  .ppcenv	:
-  {
-    common/environment.o (.ppcenv)
-  }
-  _end = . ;
-  PROVIDE (end = .);
-}

board/altera/common/flash.c

@@ -1,196 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include <nios.h>
-
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
-
-/*--------------------------------------------------------------------*/
-void flash_print_info (flash_info_t * info)
-{
-	int i, k;
-	unsigned long size;
-	int erased;
-	volatile unsigned char *flash;
-
-	printf ("  Size: %ld KB in %d Sectors\n",
-		info->size >> 10, info->sector_count);
-	printf ("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; ++i) {
-
-		/* Check if whole sector is erased */
-		if (i != (info->sector_count - 1))
-			size = info->start[i + 1] - info->start[i];
-		else
-			size = info->start[0] + info->size - info->start[i];
-		erased = 1;
-		flash = (volatile unsigned char *) info->start[i];
-		for (k = 0; k < size; k++) {
-			if (*flash++ != 0xff) {
-				erased = 0;
-				break;
-			}
-		}
-
-		/* Print the info */
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s%s", info->start[i], erased ? " E" : "  ",
-			info->protect[i] ? "RO " : "   ");
-	}
-	printf ("\n");
-}
-
-/*-------------------------------------------------------------------*/
-
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CFG_FLASH_WORD_SIZE *addr2;
-	int prot, sect;
-	unsigned oldpri;
-	ulong start;
-
-	/* Some sanity checking */
-	if ((s_first < 0) || (s_first > s_last)) {
-		printf ("- no sectors to erase\n");
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-#ifdef DEBUG
-	for (sect = s_first; sect <= s_last; sect++) {
-		printf("- Erase: Sect: %i @ 0x%08x\n", sect,  info->start[sect]);
-	}
-#endif
-
-	/* NOTE: disabling interrupts on Nios can be very bad since it
-	 * also disables the LO_LIMIT exception. It's better here to
-	 * set the interrupt priority to 3 & restore it when we're done.
-	 */
-	oldpri = ipri (3);
-
-	/* It's ok to erase multiple sectors provided we don't delay more
-	 * than 50 usec between cmds ... at which point the erase time-out
-	 * occurs. So don't go and put printf() calls in the loop ... it
-	 * won't be very helpful ;-)
-	 */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
-			*addr = 0xaa;
-			*addr = 0x55;
-			*addr = 0x80;
-			*addr = 0xaa;
-			*addr = 0x55;
-			*addr2 = 0x30;
-			/* Now just wait for 0xff & provide some user
-			 * feedback while we wait. Here we have to grant
-			 * timer interrupts. Otherwise get_timer() can't
-			 * work right. */
-			ipri(oldpri);
-			start = get_timer (0);
-			while (*addr2 != 0xff) {
-				udelay (1000 * 1000);
-				putc ('.');
-				if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
-					printf ("timeout\n");
-					return 1;
-				}
-			}
-			oldpri = ipri (3); /* disallow non important irqs again */
-		}
-	}
-
-	printf ("\n");
-
-	/* Restore interrupt priority */
-	ipri (oldpri);
-
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-
-	vu_char *cmd = (vu_char *) info->start[0];
-	vu_char *dst = (vu_char *) addr;
-	unsigned char b;
-	unsigned oldpri;
-	ulong start;
-
-	while (cnt) {
-		/* Check for sufficient erase */
-		b = *src;
-		if ((*dst & b) != b) {
-			printf ("%02x : %02x\n", *dst, b);
-			return (2);
-		}
-
-		/* Disable interrupts other than window underflow
-		 * (interrupt priority 2)
-		 */
-		oldpri = ipri (3);
-		*cmd = 0xaa;
-		*cmd = 0x55;
-		*cmd = 0xa0;
-		*dst = b;
-
-		/* Verify write */
-		start = get_timer (0);
-		while (*dst != b) {
-			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
-				ipri (oldpri);
-				return 1;
-			}
-		}
-		dst++;
-		src++;
-		cnt--;
-		ipri (oldpri);
-	}
-
-	return (0);
-}

board/altera/common/sevenseg.c

@@ -1,220 +0,0 @@
-/*
- * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
- * Stephan Linz <linz@li-pro.net>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * common/sevenseg.c
- *
- * NIOS PIO based seven segment led support functions
- */
-
-#include <common.h>
-#include <nios-io.h>
-
-#ifdef	CONFIG_SEVENSEG
-
-#define SEVENDEG_MASK_DP	((SEVENSEG_DIGIT_DP << 8) | SEVENSEG_DIGIT_DP)
-
-#ifdef	SEVENSEG_WRONLY	/* emulate read access */
-#if (SEVENSEG_ACTIVE == 0)
-static unsigned int sevenseg_portval = ~0;
-#else
-static unsigned int sevenseg_portval = 0;
-#endif
-#endif
-
-static int sevenseg_init_done = 0;
-
-static inline void __sevenseg_set_masked (unsigned int mask, int value)
-{
-	nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;
-
-#ifdef	SEVENSEG_WRONLY	/* emulate read access */
-
-#if (SEVENSEG_ACTIVE == 0)
-	if (value)
-		sevenseg_portval &= ~mask;
-	else
-		sevenseg_portval |= mask;
-#else
-	if (value)
-		sevenseg_portval |= mask;
-	else
-		sevenseg_portval &= ~mask;
-#endif
-
-	piop->data = sevenseg_portval;
-
-#else	/* !SEVENSEG_WRONLY */
-
-#if (SEVENSEG_ACTIVE == 0)
-	if (value)
-		piop->data &= ~mask;
-	else
-		piop->data |= mask;
-#else
-	if (value)
-		piop->data |= mask;
-	else
-		piop->data &= ~mask;
-#endif
-
-#endif	/* SEVENSEG_WRONLY */
-}
-
-static inline void __sevenseg_toggle_masked (unsigned int mask)
-{
-	nios_pio_t *piop = (nios_pio_t*)SEVENSEG_BASE;
-
-#ifdef	SEVENSEG_WRONLY	/* emulate read access */
-
-	sevenseg_portval ^= mask;
-	piop->data = sevenseg_portval;
-
-#else	/* !SEVENSEG_WRONLY */
-
-	piop->data ^= mask;
-
-#endif	/* SEVENSEG_WRONLY */
-}
-
-static inline void __sevenseg_set (unsigned int value)
-{
-	nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;
-
-#ifdef	SEVENSEG_WRONLY	/* emulate read access */
-
-#if (SEVENSEG_ACTIVE == 0)
-	sevenseg_portval = (sevenseg_portval &   SEVENDEG_MASK_DP)
-		         | ((~value)         & (~SEVENDEG_MASK_DP));
-#else
-	sevenseg_portval = (sevenseg_portval & SEVENDEG_MASK_DP)
-		         | (value);
-#endif
-
-	piop->data = sevenseg_portval;
-
-#else	/* !SEVENSEG_WRONLY */
-
-#if (SEVENSEG_ACTIVE == 0)
-	piop->data = (piop->data &   SEVENDEG_MASK_DP)
-		   | ((~value)   & (~SEVENDEG_MASK_DP));
-#else
-	piop->data = (piop->data & SEVENDEG_MASK_DP)
-		   | (value);
-#endif
-
-#endif	/* SEVENSEG_WRONLY */
-}
-
-static inline void __sevenseg_init (void)
-{
-	nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;
-
-	__sevenseg_set(0);
-
-#ifndef	SEVENSEG_WRONLY	/* setup direction */
-
-	piop->direction |= mask;
-
-#endif	/* SEVENSEG_WRONLY */
-}
-
-
-void sevenseg_set(int value)
-{
-	unsigned char	digits[] = {
-		SEVENSEG_DIGITS_0,
-		SEVENSEG_DIGITS_1,
-		SEVENSEG_DIGITS_2,
-		SEVENSEG_DIGITS_3,
-		SEVENSEG_DIGITS_4,
-		SEVENSEG_DIGITS_5,
-		SEVENSEG_DIGITS_6,
-		SEVENSEG_DIGITS_7,
-		SEVENSEG_DIGITS_8,
-		SEVENSEG_DIGITS_9,
-		SEVENSEG_DIGITS_A,
-		SEVENSEG_DIGITS_B,
-		SEVENSEG_DIGITS_C,
-		SEVENSEG_DIGITS_D,
-		SEVENSEG_DIGITS_E,
-		SEVENSEG_DIGITS_F
-	};
-
-	if (!sevenseg_init_done) {
-		__sevenseg_init();
-		sevenseg_init_done++;
-	}
-
-	switch (value & SEVENSEG_MASK_CTRL) {
-
-		case SEVENSEG_RAW:
-			__sevenseg_set( (
-				(digits[((value & SEVENSEG_MASK_VAL) >>  4)] << 8) |
-				digits[((value & SEVENSEG_MASK_VAL) & 0xf)] ) );
-			return;
-			break;	/* paranoia */
-
-		case SEVENSEG_OFF:
-			__sevenseg_set(0);
-			__sevenseg_set_masked(SEVENDEG_MASK_DP, 0);
-			return;
-			break;	/* paranoia */
-
-		case SEVENSEG_SET_DPL:
-			__sevenseg_set_masked(SEVENSEG_DIGIT_DP, 1);
-			return;
-			break;	/* paranoia */
-
-		case SEVENSEG_SET_DPH:
-			__sevenseg_set_masked((SEVENSEG_DIGIT_DP << 8), 1);
-			return;
-			break;	/* paranoia */
-
-		case SEVENSEG_RES_DPL:
-			__sevenseg_set_masked(SEVENSEG_DIGIT_DP, 0);
-			return;
-			break;	/* paranoia */
-
-		case SEVENSEG_RES_DPH:
-			__sevenseg_set_masked((SEVENSEG_DIGIT_DP << 8), 0);
-			return;
-			break;	/* paranoia */
-
-		case SEVENSEG_TOG_DPL:
-			__sevenseg_toggle_masked(SEVENSEG_DIGIT_DP);
-			return;
-			break;	/* paranoia */
-
-		case SEVENSEG_TOG_DPH:
-			__sevenseg_toggle_masked((SEVENSEG_DIGIT_DP << 8));
-			return;
-			break;	/* paranoia */
-
-		case SEVENSEG_LO:
-		case SEVENSEG_HI:
-		case SEVENSEG_STR:
-		default:
-			break;
-	}
-}
-
-#endif	/* CONFIG_SEVENSEG */

board/altera/common/sevenseg.h

@@ -1,142 +0,0 @@
-/*
- * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
- * Stephan Linz <linz@li-pro.net>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * common/sevenseg.h
- *
- * NIOS PIO based seven segment led support functions
- */
-
-#ifndef __DK1S10_SEVENSEG_H__
-#define __DK1S10_SEVENSEG_H__
-
-#ifdef	CONFIG_SEVENSEG
-
-/*
- *  15                    8 7      0
- * |-----------------------|--------|
- * |   controll value      |  value |
- * ----------------------------------
- */
-#define	SEVENSEG_RAW		(int)(0)	/* write out byte value (hex) */
-#define	SEVENSEG_OFF		(int)( 1 << 8)	/* display switch off */
-#define	SEVENSEG_SET_DPL	(int)( 2 << 8)	/* set dp low  nibble */
-#define	SEVENSEG_SET_DPH	(int)( 3 << 8)	/* set dp high nibble */
-#define	SEVENSEG_RES_DPL	(int)( 4 << 8)	/* reset dp low  nibble */
-#define	SEVENSEG_RES_DPH	(int)( 5 << 8)	/* reset dp high nibble */
-#define	SEVENSEG_TOG_DPL	(int)( 6 << 8)	/* toggle dp low  nibble */
-#define	SEVENSEG_TOG_DPH	(int)( 7 << 8)	/* toggle dp high nibble */
-#define	SEVENSEG_LO		(int)( 8 << 8)	/* write out low nibble only */
-#define	SEVENSEG_HI		(int)( 9 << 8)	/* write out high nibble only */
-#define	SEVENSEG_STR		(int)(10 << 8)	/* write out a string */
-
-#define	SEVENSEG_MASK_VAL	(0xff)		/* only used by SEVENSEG_RAW */
-#define	SEVENSEG_MASK_CTRL	(~SEVENSEG_MASK_VAL)
-
-#ifdef	SEVENSEG_DIGIT_HI_LO_EQUAL
-
-#define	SEVENSEG_DIGITS_0	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_B	\
-				|	SEVENSEG_DIGIT_C	\
-				|	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_E	\
-				|	SEVENSEG_DIGIT_F	)
-#define	SEVENSEG_DIGITS_1	(	SEVENSEG_DIGIT_B	\
-				|	SEVENSEG_DIGIT_C	)
-#define	SEVENSEG_DIGITS_2	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_B	\
-				|	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_E	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_3	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_B	\
-				|	SEVENSEG_DIGIT_C	\
-				|	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_4	(	SEVENSEG_DIGIT_B	\
-				|	SEVENSEG_DIGIT_C	\
-				|	SEVENSEG_DIGIT_F	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_5	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_C	\
-				|	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_F	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_6	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_C	\
-				|	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_E	\
-				|	SEVENSEG_DIGIT_F	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_7	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_B	\
-				|	SEVENSEG_DIGIT_C	)
-#define	SEVENSEG_DIGITS_8	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_B	\
-				|	SEVENSEG_DIGIT_C	\
-				|	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_E	\
-				|	SEVENSEG_DIGIT_F	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_9	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_B	\
-				|	SEVENSEG_DIGIT_C	\
-				|	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_F	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_A	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_B	\
-				|	SEVENSEG_DIGIT_C	\
-				|	SEVENSEG_DIGIT_E	\
-				|	SEVENSEG_DIGIT_F	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_B	(	SEVENSEG_DIGIT_C	\
-				|	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_E	\
-				|	SEVENSEG_DIGIT_F	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_C	(	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_E	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_D	(	SEVENSEG_DIGIT_B	\
-				|	SEVENSEG_DIGIT_C	\
-				|	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_E	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_E	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_E	\
-				|	SEVENSEG_DIGIT_F	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_F	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_E	\
-				|	SEVENSEG_DIGIT_F	\
-				|	SEVENSEG_DIGIT_G	)
-
-#else	/* !SEVENSEG_DIGIT_HI_LO_EQUAL */
-#error SEVENSEG: different pin asssignments not supported
-#endif
-
-void sevenseg_set(int value);
-
-#endif	/* CONFIG_SEVENSEG */
-
-#endif	/* __DK1S10_SEVENSEG_H__ */

board/altera/dk1c20/Makefile

@@ -1,48 +0,0 @@
-#
-# (C) Copyright 2001-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= lib$(BOARD).a
-
-OBJS	:= $(BOARD).o flash.o misc.o
-
-SOBJS  = vectors.o
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(AR) crv $@ $^
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
-		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-
--include .depend
-
-#########################################################################

board/altera/dk1c20/config.mk

@@ -1,29 +0,0 @@
-#
-# (C) Copyright 2003
-# Psyent Corporation
-# Scott McNutt <smcnutt@psyent.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0x018c0000
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif

board/altera/dk1c20/dk1c20.c

@@ -1,52 +0,0 @@
-/*
- * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#if	defined(CONFIG_SEVENSEG)
-#include "../common/sevenseg.h"
-#endif
-
-void _default_hdlr (void)
-{
-	printf ("default_hdlr\n");
-}
-
-int board_early_init_f (void)
-{
-#if	defined(CONFIG_SEVENSEG)
-	/* init seven segment led display and switch off */
-	sevenseg_set(SEVENSEG_OFF);
-#endif
-	return 0;
-}
-
-int checkboard (void)
-{
-	puts ("Board: Altera Nios 1C20 Development Kit\n");
-	return 0;
-}
-
-long int initdram (int board_type)
-{
-	return (0);
-}

board/altera/dk1c20/flash.c

@@ -1,62 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include <nios.h>
-
-/*
- * include common flash code (for altera boards)
- */
-#include "../common/flash.c"
-
-/*----------------------------------------------------------------------*/
-#define BANKSZ		CFG_FLASH_SIZE
-#define SECTSZ		(64 * 1024)
-#define USERFLASH	(2 * 1024 * 1024)	/* bottom 2 MB for user	*/
-
-/*----------------------------------------------------------------------*/
-unsigned long flash_init (void)
-{
-	int i;
-	unsigned long addr;
-	flash_info_t *fli = &flash_info[0];
-
-	fli->size = BANKSZ;
-	fli->sector_count = CFG_MAX_FLASH_SECT;
-	fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D;
-
-	addr = CFG_FLASH_BASE;
-	for (i = 0; i < fli->sector_count; ++i) {
-		fli->start[i] = addr;
-		addr += SECTSZ;
-
-		/* Protect all but 2 MByte user area */
-		if (addr < (CFG_FLASH_BASE + USERFLASH))
-			fli->protect[i] = 0;
-		else
-			fli->protect[i] = 1;
-	}
-
-	return (BANKSZ);
-}

board/altera/dk1c20/misc.c

@@ -1,33 +0,0 @@
-/*
- * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
- * Stephan Linz <linz@li-pro.net>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * board/altera/dk1s10/misc.c
- *
- * miscellaneous board interfaces / drivers
- */
-
-#include <common.h>
-
-#if	defined(CONFIG_SEVENSEG)
-#include "../common/sevenseg.h"
-#include "../common/sevenseg.c"
-#endif

board/altera/dk1c20/u-boot.lds

@@ -1,69 +0,0 @@
-/*
- * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-OUTPUT_FORMAT("elf32-nios")
-OUTPUT_ARCH(nios)
-ENTRY(_start)
-
-SECTIONS
-{
-	.text :
-	{
-	  cpu/nios/start.o (.text)
-	  *(.text)
-	}
-	__text_end = .;
-
-	. = ALIGN(4);
-	.rodata :
-	{
-		*(.rodata)
-	}
-	__rodata_end = .;
-
-	. = ALIGN(4);
-	.data :
-	{
-		*(.data)
-	}
-	. = ALIGN(4);
-	__data_end = .;
-
-	__u_boot_cmd_start = .;
-	.u_boot_cmd :
-	{
-		*(.u_boot_cmd)
-	}
-	. = ALIGN(4);
-	__u_boot_cmd_end = .;
-
-	__bss_start = .;
-	. = ALIGN(4);
-	.bss :
-	{
-		*(.bss)
-	}
-	. = ALIGN(4);
-	__bss_end = .;
-}

board/altera/dk1c20/vectors.S

@@ -1,122 +0,0 @@
-/*
- * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-/*************************************************************************
- * Exception Vector Table
- *
- * This could have gone in the cpu soure tree, but the whole point of
- * Nios is customization -- and polluting the cpu source tree with
- * board-specific ifdef's really defeats the purpose, no? With this in
- * the board-specific tree, each board has the freedom to organize
- * vectors/traps, etc anyway it wants. The init code copies this table
- * to the proper location.
- *
- * Each board can do what it likes here. But there are four "standard"
- * handlers availble:
- *
- *	_cwp_lolimit	-Handles register window underflows.
- *	_cwp_hilimit	-Handles register window overflows.
- *	_timebase_int	-Increments the timebase.
- *	_def_xhandler	-Default exception handler.
- *
- * _timebase_int handles a Nios Timer interrupt and increments the
- * timestamp used for the get_timer(), reset_timer(), etc. routines. It
- * expects the timer to be configured like the standard-32 low priority
- * timer.
- *
- * _def_xhandler dispatches exceptions/traps via the external_interrupt()
- * routine. This lets you use the irq_install_handler() and handle your
- * interrupts/traps with code written in C.
- ************************************************************************/
-
-	.data
-	.global _vectors
-	.align	4
-_vectors:
-
-	.long	_def_xhandler@h		/* Vector 0  - NMI */
-	.long	_cwp_lolimit@h		/* Vector 1  -  underflow */
-	.long	_cwp_hilimit@h		/* Vector 2  - overflow	*/
-
-	.long	_def_xhandler@h		/* Vector 3 - GNUPro debug */
-	.long	_def_xhandler@h		/* Vector 4 - GNUPro debug */
-	.long	_def_xhandler@h		/* Vector 5 - GNUPro debug */
-	.long	_def_xhandler@h		/* Vector 6 - future reserved */
-	.long	_def_xhandler@h		/* Vector 7 - future reserved */
-	.long	_def_xhandler@h		/* Vector 8 - future reserved */
-	.long	_def_xhandler@h		/* Vector 9 - future reserved */
-	.long	_def_xhandler@h		/* Vector 10 - future reserved */
-	.long	_def_xhandler@h		/* Vector 11 - future reserved */
-	.long	_def_xhandler@h		/* Vector 12 - future reserved */
-	.long	_def_xhandler@h		/* Vector 13 - future reserved */
-	.long	_def_xhandler@h		/* Vector 14 - future reserved */
-	.long	_def_xhandler@h		/* Vector 15 - future reserved */
-	.long	_def_xhandler@h		/* Vector 16 */
-	.long	_def_xhandler@h		/* Vector 17 */
-	.long	_def_xhandler@h		/* Vector 18 */
-	.long	_def_xhandler@h		/* Vector 19 */
-	.long	_def_xhandler@h		/* Vector 20 */
-	.long	_def_xhandler@h		/* Vector 21 */
-	.long	_def_xhandler@h		/* Vector 22 */
-	.long	_def_xhandler@h		/* Vector 23 */
-	.long	_def_xhandler@h		/* Vector 24 */
-	.long	_def_xhandler@h		/* Vector 25 */
-	.long	_def_xhandler@h		/* Vector 26 */
-	.long	_def_xhandler@h		/* Vector 27 */
-	.long	_def_xhandler@h		/* Vector 28 */
-	.long	_def_xhandler@h		/* Vector 29 */
-	.long	_def_xhandler@h		/* Vector 30 */
-	.long	_def_xhandler@h		/* Vector 31 */
-	.long	_def_xhandler@h		/* Vector 32 */
-	.long	_def_xhandler@h		/* Vector 33 */
-	.long	_def_xhandler@h		/* Vector 34 */
-	.long	_def_xhandler@h		/* Vector 35 */
-	.long	_def_xhandler@h		/* Vector 36 */
-	.long	_def_xhandler@h		/* Vector 37 */
-	.long	_def_xhandler@h		/* Vector 38 */
-	.long	_def_xhandler@h		/* Vector 39 */
-	.long	_def_xhandler@h		/* Vector 40 */
-	.long	_def_xhandler@h		/* Vector 41 */
-	.long	_def_xhandler@h		/* Vector 42 */
-	.long	_def_xhandler@h		/* Vector 43 */
-	.long	_def_xhandler@h		/* Vector 44 */
-	.long	_def_xhandler@h		/* Vector 45 */
-	.long	_def_xhandler@h		/* Vector 46 */
-	.long	_def_xhandler@h		/* Vector 47 */
-	.long	_def_xhandler@h		/* Vector 48 */
-	.long	_def_xhandler@h		/* Vector 49 */
-	.long	_timebase_int@h		/* Vector 50 - lopri timer*/
-	.long	_def_xhandler@h		/* Vector 51 */
-	.long	_def_xhandler@h		/* Vector 52 */
-	.long	_def_xhandler@h		/* Vector 53 */
-	.long	_def_xhandler@h		/* Vector 54 */
-	.long	_def_xhandler@h		/* Vector 55 */
-	.long	_def_xhandler@h		/* Vector 56 */
-	.long	_def_xhandler@h		/* Vector 57 */
-	.long	_def_xhandler@h		/* Vector 58 */
-	.long	_def_xhandler@h		/* Vector 59 */
-	.long	_def_xhandler@h		/* Vector 60 */
-	.long	_def_xhandler@h		/* Vector 61 */
-	.long	_def_xhandler@h		/* Vector 62 */
-	.long	_def_xhandler@h		/* Vector 63 */

board/altera/dk1s10/Makefile

@@ -1,48 +0,0 @@
-#
-# (C) Copyright 2001-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= lib$(BOARD).a
-
-OBJS	:= $(BOARD).o flash.o misc.o
-
-SOBJS  = vectors.o
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(AR) crv $@ $^
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
-		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-
--include .depend
-
-#########################################################################

board/altera/dk1s10/config.mk

@@ -1,29 +0,0 @@
-#
-# (C) Copyright 2003
-# Psyent Corporation
-# Scott McNutt <smcnutt@psyent.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0x018c0000
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif

board/altera/dk1s10/dk1s10.c

@@ -1,60 +0,0 @@
-/*
- * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#if	defined(CONFIG_SEVENSEG)
-#include "../common/sevenseg.h"
-#endif
-
-void _default_hdlr (void)
-{
-	printf ("default_hdlr\n");
-}
-
-int board_early_init_f (void)
-{
-#if	defined(CONFIG_SEVENSEG)
-	/* init seven segment led display and switch off */
-	sevenseg_set(SEVENSEG_OFF);
-#endif
-	return 0;
-}
-
-int checkboard (void)
-{
-	puts ("Board: Altera Nios 1S10 Development Kit\n");
-#if     defined(CONFIG_NIOS_SAFE_32)
-	puts ("Conf.: Altera Safe 32 (safe_32)\n");
-#elif   defined(CONFIG_NIOS_STANDARD_32)
-	puts ("Conf.: Altera Standard 32 (standard_32)\n");
-#elif   defined(CONFIG_NIOS_MTX_LDK_20)
-	puts ("Conf.: Microtronix LDK 2.0 (LDK2)\n");
-#endif
-
-	return 0;
-}
-
-long int initdram (int board_type)
-{
-	return (0);
-}

board/altera/dk1s10/flash.c

@@ -1,62 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include <nios.h>
-
-/*
- * include common flash code (for altera boards)
- */
-#include "../common/flash.c"
-
-/*---------------------------------------------------------------------*/
-#define BANKSZ	(8 * 1024 * 1024)
-#define SECTSZ	(64 * 1024)
-#define USERFLASH (2 * 1024 * 1024)	/* bottom 2 MB for user */
-
-/*---------------------------------------------------------------------*/
-unsigned long flash_init (void)
-{
-	int i;
-	unsigned long addr;
-	flash_info_t *fli = &flash_info[0];
-
-	fli->size = BANKSZ;
-	fli->sector_count = CFG_MAX_FLASH_SECT;
-	fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D;
-
-	addr = CFG_FLASH_BASE;
-	for (i = 0; i < fli->sector_count; ++i) {
-		fli->start[i] = addr;
-		addr += SECTSZ;
-
-		/* Protect all but 2 MByte user area */
-		if (addr < (CFG_FLASH_BASE + USERFLASH))
-			fli->protect[i] = 0;
-		else
-			fli->protect[i] = 1;
-	}
-
-	return (BANKSZ);
-}

board/altera/dk1s10/misc.c

@@ -1,33 +0,0 @@
-/*
- * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
- * Stephan Linz <linz@li-pro.net>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * board/altera/dk1s10/misc.c
- *
- * miscellaneous board interfaces / drivers
- */
-
-#include <common.h>
-
-#if	defined(CONFIG_SEVENSEG)
-#include "../common/sevenseg.h"
-#include "../common/sevenseg.c"
-#endif

board/altera/dk1s10/u-boot.lds

@@ -1,69 +0,0 @@
-/*
- * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-OUTPUT_FORMAT("elf32-nios")
-OUTPUT_ARCH(nios)
-ENTRY(_start)
-
-SECTIONS
-{
-	.text :
-	{
-	  cpu/nios/start.o (.text)
-	  *(.text)
-	}
-	__text_end = .;
-
-	. = ALIGN(4);
-	.rodata :
-	{
-		*(.rodata)
-	}
-	__rodata_end = .;
-
-	. = ALIGN(4);
-	.data :
-	{
-		*(.data)
-	}
-	. = ALIGN(4);
-	__data_end = .;
-
-	__u_boot_cmd_start = .;
-	.u_boot_cmd :
-	{
-		*(.u_boot_cmd)
-	}
-	. = ALIGN(4);
-	__u_boot_cmd_end = .;
-
-	__bss_start = .;
-	. = ALIGN(4);
-	.bss :
-	{
-		*(.bss)
-	}
-	. = ALIGN(4);
-	__bss_end = .;
-}

board/altera/dk1s10/vectors.S

@@ -1,139 +0,0 @@
-/*
- * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- * Stephan Linz <linz@li-pro.net>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-
-
-/*************************************************************************
- * Exception Vector Table
- *
- * This could have gone in the cpu soure tree, but the whole point of
- * Nios is customization -- and polluting the cpu source tree with
- * board-specific ifdef's really defeats the purpose, no? With this in
- * the board-specific tree, each board has the freedom to organize
- * vectors/traps, etc anyway it wants. The init code copies this table
- * to the proper location.
- *
- * Each board can do what it likes here. But there are four "standard"
- * handlers availble:
- *
- *	_cwp_lolimit	-Handles register window underflows.
- *	_cwp_hilimit	-Handles register window overflows.
- *	_timebase_int	-Increments the timebase.
- *	_def_xhandler	-Default exception handler.
- *
- * _timebase_int handles a Nios Timer interrupt and increments the
- * timestamp used for the get_timer(), reset_timer(), etc. routines. It
- * expects the timer to be configured like the standard-32 low priority
- * timer.
- *
- * _def_xhandler dispatches exceptions/traps via the external_interrupt()
- * routine. This lets you use the irq_install_handler() and handle your
- * interrupts/traps with code written in C.
- ************************************************************************/
-
-	.data
-	.global _vectors
-	.align	4
-_vectors:
-
-#if	defined(CFG_NIOS_CPU_OCI_BASE)
-	/* OCI does the reset job */
-	.long	_def_xhandler@h		/* Vector 0  - NMI / Reset */
-#else
-	/* there is no OCI, so we have to do a direct reset jump here */
-	.long	CFG_NIOS_CPU_RST_VECT	/* Vector 0  - Reset to GERMS */
-#endif
-	.long	_cwp_lolimit@h		/* Vector 1  - underflow */
-	.long	_cwp_hilimit@h		/* Vector 2  - overflow	*/
-
-	.long	_def_xhandler@h		/* Vector 3 - GNUPro debug */
-	.long	_def_xhandler@h		/* Vector 4 - GNUPro debug */
-	.long	_def_xhandler@h		/* Vector 5 - GNUPro debug */
-	.long	_def_xhandler@h		/* Vector 6 - future reserved */
-	.long	_def_xhandler@h		/* Vector 7 - future reserved */
-	.long	_def_xhandler@h		/* Vector 8 - future reserved */
-	.long	_def_xhandler@h		/* Vector 9 - future reserved */
-	.long	_def_xhandler@h		/* Vector 10 - future reserved */
-	.long	_def_xhandler@h		/* Vector 11 - future reserved */
-	.long	_def_xhandler@h		/* Vector 12 - future reserved */
-	.long	_def_xhandler@h		/* Vector 13 - future reserved */
-	.long	_def_xhandler@h		/* Vector 14 - future reserved */
-	.long	_def_xhandler@h		/* Vector 15 - future reserved */
-#if	(CFG_NIOS_TMRIRQ == 16)
-	.long	_timebase_int@h		/* Vector 16 - lopri timer*/
-#else
-	.long	_def_xhandler@h		/* Vector 16 */
-#endif
-	.long	_def_xhandler@h		/* Vector 17 */
-	.long	_def_xhandler@h		/* Vector 18 */
-	.long	_def_xhandler@h		/* Vector 19 */
-	.long	_def_xhandler@h		/* Vector 20 */
-	.long	_def_xhandler@h		/* Vector 21 */
-	.long	_def_xhandler@h		/* Vector 22 */
-	.long	_def_xhandler@h		/* Vector 23 */
-	.long	_def_xhandler@h		/* Vector 24 */
-	.long	_def_xhandler@h		/* Vector 25 */
-	.long	_def_xhandler@h		/* Vector 26 */
-	.long	_def_xhandler@h		/* Vector 27 */
-	.long	_def_xhandler@h		/* Vector 28 */
-	.long	_def_xhandler@h		/* Vector 29 */
-	.long	_def_xhandler@h		/* Vector 30 */
-	.long	_def_xhandler@h		/* Vector 31 */
-	.long	_def_xhandler@h		/* Vector 32 */
-	.long	_def_xhandler@h		/* Vector 33 */
-	.long	_def_xhandler@h		/* Vector 34 */
-	.long	_def_xhandler@h		/* Vector 35 */
-	.long	_def_xhandler@h		/* Vector 36 */
-	.long	_def_xhandler@h		/* Vector 37 */
-	.long	_def_xhandler@h		/* Vector 38 */
-	.long	_def_xhandler@h		/* Vector 39 */
-	.long	_def_xhandler@h		/* Vector 40 */
-	.long	_def_xhandler@h		/* Vector 41 */
-	.long	_def_xhandler@h		/* Vector 42 */
-	.long	_def_xhandler@h		/* Vector 43 */
-	.long	_def_xhandler@h		/* Vector 44 */
-	.long	_def_xhandler@h		/* Vector 45 */
-	.long	_def_xhandler@h		/* Vector 46 */
-	.long	_def_xhandler@h		/* Vector 47 */
-	.long	_def_xhandler@h		/* Vector 48 */
-	.long	_def_xhandler@h		/* Vector 49 */
-#if	(CFG_NIOS_TMRIRQ == 50)
-	.long	_timebase_int@h		/* Vector 50 - lopri timer*/
-#else
-	.long	_def_xhandler@h		/* Vector 50 */
-#endif
-	.long	_def_xhandler@h		/* Vector 51 */
-	.long	_def_xhandler@h		/* Vector 52 */
-	.long	_def_xhandler@h		/* Vector 53 */
-	.long	_def_xhandler@h		/* Vector 54 */
-	.long	_def_xhandler@h		/* Vector 55 */
-	.long	_def_xhandler@h		/* Vector 56 */
-	.long	_def_xhandler@h		/* Vector 57 */
-	.long	_def_xhandler@h		/* Vector 58 */
-	.long	_def_xhandler@h		/* Vector 59 */
-	.long	_def_xhandler@h		/* Vector 60 */
-	.long	_def_xhandler@h		/* Vector 61 */
-	.long	_def_xhandler@h		/* Vector 62 */
-	.long	_def_xhandler@h		/* Vector 63 */

board/at91rm9200dk/at91rm9200dk.c

@@ -66,7 +66,7 @@ int dram_init (void)
  * The NAND lives in the CS2* space
  */
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
-extern ulong nand_probe (ulong physadr);
+extern void nand_probe (ulong physadr);
 
 #define AT91_SMARTMEDIA_BASE 0x40000000	/* physical address to access memory on NCS3 */
 void nand_init (void)
@@ -103,12 +103,10 @@ void nand_init (void)
 	*AT91C_PIOB_ODR = AT91C_PIO_PB1;	/* disable output */
 
 	if (*AT91C_PIOB_PDSR & AT91C_PIO_PB1)
-		printf ("  No SmartMedia card inserted\n");
-#ifdef DEBUG
-	printf ("  SmartMedia card inserted\n");
+		printf ("No ");
+	printf ("SmartMedia card inserted\n");
 
 	printf ("Probing at 0x%.8x\n", AT91_SMARTMEDIA_BASE);
-#endif
-	printf ("%4lu MB\n", nand_probe(AT91_SMARTMEDIA_BASE) >> 20);
+	nand_probe (AT91_SMARTMEDIA_BASE);
 }
 #endif

board/at91rm9200dk/config.mk

@@ -1 +1 @@
-TEXT_BASE = 0x21f80000
+TEXT_BASE = 0x21f00000

board/at91rm9200dk/flash.c

@@ -160,7 +160,7 @@ ulong flash_init (void)
 		if (i == 0)
 			flashbase = PHYS_FLASH_1;
 		else
-			panic ("configured too many flash banks!\n");
+			panic ("configured to many flash banks!\n");
 
 		sector = 0;
 		start_address = flashbase;

board/at91rm9200dk/u-boot.lds

@@ -45,12 +45,14 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }
 
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+	armboot_end_data = .;
 
 	. = ALIGN(4);
-	__bss_start = .;
 	.bss : { *(.bss) }
-	_end = .;
+
+	armboot_end = .;
 }

board/atc/atc.c

@@ -92,20 +92,20 @@ const iop_conf_t iop_conf_tab[4][32] = {
 	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
 	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
 	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
-	/* PB17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_DV */
-	/* PB16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_ER */
-	/* PB15 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_ER */
-	/* PB14 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_EN */
-	/* PB13 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII COL */
-	/* PB12 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII CRS */
-	/* PB11 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD */
-	/* PB10 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD */
-	/* PB9  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD */
-	/* PB8  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD */
-	/* PB7  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD */
-	/* PB6  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD */
-	/* PB5  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD */
-	/* PB4  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD */
+	/* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
+	/* PB16 */ {   0,   0,   0,   0,   0,   0   }, /* PB16 */
+	/* PB15 */ {   0,   0,   0,   0,   0,   0   }, /* PB15 */
+	/* PB14 */ {   0,   0,   0,   0,   0,   0   }, /* PB14 */
+	/* PB13 */ {   0,   0,   0,   0,   0,   0   }, /* PB13 */
+	/* PB12 */ {   0,   0,   0,   0,   0,   0   }, /* PB12 */
+	/* PB11 */ {   0,   0,   0,   0,   0,   0   }, /* PB11 */
+	/* PB10 */ {   0,   0,   0,   0,   0,   0   }, /* PB10 */
+	/* PB9  */ {   0,   0,   0,   0,   0,   0   }, /* PB9 */
+	/* PB8  */ {   0,   0,   0,   0,   0,   0   }, /* PB8 */
+	/* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
+	/* PB6  */ {   0,   0,   0,   0,   0,   0   }, /* PB6 */
+	/* PB5  */ {   0,   0,   0,   0,   0,   0   }, /* PB5 */
+	/* PB4  */ {   0,   0,   0,   0,   0,   0   }, /* PB4 */
 	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* PB3 */
 	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* PB2 */
 	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* PB1 */
@@ -128,8 +128,8 @@ const iop_conf_t iop_conf_tab[4][32] = {
 	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII TX_CLK */
 	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK */
 	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII TX_CLK */
-	/* PC17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_CLK */
-	/* PC16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII TX_CLK */
+	/* PC17 */ {   0,   0,   0,   0,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   0,   0,   0,   0,   0   }, /* PC16 */
 #if 0
 	/* PC15 */ {   0,   0,   0,   0,   0,   0   }, /* PC15 */
 #else
@@ -269,10 +269,13 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 			  ulong orx, volatile uchar * base)
 {
 	volatile uchar c = 0xff;
+	ulong cnt, val;
+	volatile ulong *addr;
 	volatile uint *sdmr_ptr;
 	volatile uint *orx_ptr;
-	ulong maxsize, size;
 	int i;
+	ulong save[32];		/* to make test non-destructive */
+	ulong maxsize;
 
 	/* We must be able to test a location outsize the maximum legal size
 	 * to find out THAT we are outside; but this address still has to be
@@ -322,11 +325,41 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
 	*base = c;
 
-	size = get_ram_size((long *)base, maxsize);
+	/*
+	 * Check memory range for valid RAM. A simple memory test determines
+	 * the actually available RAM size between addresses `base' and
+	 * `base + maxsize'. Some (not all) hardware errors are detected:
+	 * - short between address lines
+	 * - short between data lines
+	 */
+	i = 0;
+	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
+		addr = (volatile ulong *) base + cnt;	/* pointer arith! */
+		save[i++] = *addr;
+		*addr = ~cnt;
+	}
 
-	*orx_ptr = orx | ~(size - 1);
+	addr = (volatile ulong *) base;
+	save[i] = *addr;
+	*addr = 0;
 
-	return (size);
+	if ((val = *addr) != 0) {
+		*addr = save[i];
+		return (0);
+	}
+
+	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+		addr = (volatile ulong *) base + cnt;	/* pointer arith! */
+		val = *addr;
+		*addr = save[--i];
+		if (val != ~cnt) {
+			/* Write the actual size to ORx
+			 */
+			*orx_ptr = orx | ~(cnt * sizeof (long) - 1);
+			return (cnt * sizeof (long));
+		}
+	}
+	return (maxsize);
 }
 
 int misc_init_r(void)

board/bmw/bmw.c

@@ -27,6 +27,7 @@
 #include <command.h>
 #include <malloc.h>
 #include <devices.h>
+#include <syscall.h>
 #include <net.h>
 #include <version.h>
 #include <dtt.h>

board/bubinga405ep/bubinga405ep.c

@@ -23,10 +23,11 @@
 long int spd_sdram (void);
 
 #include <common.h>
+#include "bubinga405ep.h"
 #include <asm/processor.h>
 
 
-int board_early_init_f (void)
+int board_pre_init (void)
 {
 	mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
 	mtdcr (uicer, 0x00000000);      /* disable all ints */
@@ -79,12 +80,20 @@ int board_early_init_f (void)
 int checkboard (void)
 {
 	unsigned char *s = getenv ("serial#");
+	unsigned char *e;
 
-	puts ("Board: IBM 405EP Eval Board");
+	puts ("Board: ");
 
-	if (s != NULL) {
-		puts (", serial# ");
-		puts (s);
+	if (!s || strncmp (s, "BUBINGA405EP", 9)) {
+		puts ("### No HW ID - assuming WALNUT405");
+	} else {
+		for (e = s; *e; ++e) {
+			if (*e == ' ')
+				break;
+		}
+		for (; s < e; ++s) {
+			putc (*s);
+		}
 	}
 	putc ('\n');
 

board/bubinga405ep/flash.c

@@ -77,144 +77,138 @@ unsigned long flash_init (void)
 	unsigned long base_b0, base_b1;
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
 	/* Static FLASH Bank configuration here - FIXME XXX */
 
-	size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
 
 	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
 		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-			size_b0, size_b0 << 20);
+			size_b0, size_b0<<20);
 	}
 
 	/* Only one bank */
-	if (CFG_MAX_FLASH_BANKS == 1) {
-		/* Setup offsets */
-		flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
+	if (CFG_MAX_FLASH_BANKS == 1)
+	  {
+	    /* Setup offsets */
+	    flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
 
-		/* Monitor protection ON by default */
-		(void) flash_protect (FLAG_PROTECT_SET,
-				      FLASH_BASE0_PRELIM,
-				      FLASH_BASE0_PRELIM + CFG_MONITOR_LEN - 1,
-				      &flash_info[0]);
-		/* Also protect sector containing initial power-up instruction */
-		(void) flash_protect (FLAG_PROTECT_SET,
-				      0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]);
-		size_b1 = 0;
-		flash_info[0].size = size_b0;
-	}
+	    /* Monitor protection ON by default */
+	    (void)flash_protect(FLAG_PROTECT_SET,
+				FLASH_BASE0_PRELIM,
+				FLASH_BASE0_PRELIM+CFG_MONITOR_LEN-1,
+				&flash_info[0]);
+	    size_b1 = 0 ;
+	    flash_info[0].size = size_b0;
+	  }
 
 	/* 2 banks */
-	else {
-		size_b1 = flash_get_size ((vu_long *) FLASH_BASE1_PRELIM, &flash_info[1]);
+	else
+	  {
+	    size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
 
-		/* Re-do sizing to get full correct info */
+	    /* Re-do sizing to get full correct info */
 
-		if (size_b1) {
-			mtdcr (ebccfga, pb0cr);
-			pbcr = mfdcr (ebccfgd);
-			mtdcr (ebccfga, pb0cr);
-			base_b1 = -size_b1;
-			pbcr = (pbcr & 0x0001ffff) | base_b1 |
-				(((size_b1 / 1024 / 1024) - 1) << 17);
-			mtdcr (ebccfgd, pbcr);
-			/*          printf("pb1cr = %x\n", pbcr); */
-		}
+	    if (size_b1)
+	      {
+		mtdcr(ebccfga, pb0cr);
+		pbcr = mfdcr(ebccfgd);
+		mtdcr(ebccfga, pb0cr);
+		base_b1 = -size_b1;
+		pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17);
+		mtdcr(ebccfgd, pbcr);
+		/*          printf("pb1cr = %x\n", pbcr); */
+	      }
 
-		if (size_b0) {
-			mtdcr (ebccfga, pb1cr);
-			pbcr = mfdcr (ebccfgd);
-			mtdcr (ebccfga, pb1cr);
-			base_b0 = base_b1 - size_b0;
-			pbcr = (pbcr & 0x0001ffff) | base_b0 |
-				(((size_b0 / 1024 / 1024) - 1) << 17);
-			mtdcr (ebccfgd, pbcr);
-			/*            printf("pb0cr = %x\n", pbcr); */
-		}
+	    if (size_b0)
+	      {
+		mtdcr(ebccfga, pb1cr);
+		pbcr = mfdcr(ebccfgd);
+		mtdcr(ebccfga, pb1cr);
+		base_b0 = base_b1 - size_b0;
+		pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
+		mtdcr(ebccfgd, pbcr);
+		/*            printf("pb0cr = %x\n", pbcr); */
+	      }
 
-		size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
+	    size_b0 = flash_get_size((vu_long *)base_b0, &flash_info[0]);
 
-		flash_get_offsets (base_b0, &flash_info[0]);
+	    flash_get_offsets (base_b0, &flash_info[0]);
 
-		/* monitor protection ON by default */
-		(void) flash_protect (FLAG_PROTECT_SET,
-				      base_b0 + size_b0 - CFG_MONITOR_LEN,
-				      base_b0 + size_b0 - 1, &flash_info[0]);
-		/* Also protect sector containing initial power-up instruction */
-		/* (flash_protect() checks address range - other call ignored) */
-		(void) flash_protect (FLAG_PROTECT_SET,
-				      0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]);
-		(void) flash_protect (FLAG_PROTECT_SET,
-				      0xFFFFFFFC, 0xFFFFFFFF, &flash_info[1]);
+	    /* monitor protection ON by default */
+	    (void)flash_protect(FLAG_PROTECT_SET,
+				base_b0+size_b0-CFG_MONITOR_LEN,
+				base_b0+size_b0-1,
+				&flash_info[0]);
 
-		if (size_b1) {
-			/* Re-do sizing to get full correct info */
-			size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
+	    if (size_b1) {
+	      /* Re-do sizing to get full correct info */
+	      size_b1 = flash_get_size((vu_long *)base_b1, &flash_info[1]);
 
-			flash_get_offsets (base_b1, &flash_info[1]);
+	      flash_get_offsets (base_b1, &flash_info[1]);
 
-			/* monitor protection ON by default */
-			(void) flash_protect (FLAG_PROTECT_SET,
-					      base_b1 + size_b1 - CFG_MONITOR_LEN,
-					      base_b1 + size_b1 - 1,
-					      &flash_info[1]);
-			/* monitor protection OFF by default (one is enough) */
-			(void) flash_protect (FLAG_PROTECT_CLEAR,
-					      base_b0 + size_b0 - CFG_MONITOR_LEN,
-					      base_b0 + size_b0 - 1,
-					      &flash_info[0]);
-		} else {
-			flash_info[1].flash_id = FLASH_UNKNOWN;
-			flash_info[1].sector_count = -1;
-		}
+	      /* monitor protection ON by default */
+	      (void)flash_protect(FLAG_PROTECT_SET,
+				  base_b1+size_b1-CFG_MONITOR_LEN,
+				  base_b1+size_b1-1,
+				  &flash_info[1]);
+	      /* monitor protection OFF by default (one is enough) */
+	      (void)flash_protect(FLAG_PROTECT_CLEAR,
+				  base_b0+size_b0-CFG_MONITOR_LEN,
+				  base_b0+size_b0-1,
+				  &flash_info[0]);
+	    } else {
+	      flash_info[1].flash_id = FLASH_UNKNOWN;
+	      flash_info[1].sector_count = -1;
+	    }
 
-		flash_info[0].size = size_b0;
-		flash_info[1].size = size_b1;
-	}			/* else 2 banks */
+	    flash_info[0].size = size_b0;
+	    flash_info[1].size = size_b1;
+	  }/* else 2 banks */
 	return (size_b0 + size_b1);
 }
 
 
 /*-----------------------------------------------------------------------
  */
-static void flash_get_offsets (ulong base, flash_info_t * info)
+static void flash_get_offsets (ulong base, flash_info_t *info)
 {
 	int i;
 
 	/* set up sector start address table */
 	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
-	    (info->flash_id == FLASH_AM040)) {
-		for (i = 0; i < info->sector_count; i++)
-			info->start[i] = base + (i * 0x00010000);
+	    (info->flash_id  == FLASH_AM040)){
+	    for (i = 0; i < info->sector_count; i++)
+		info->start[i] = base + (i * 0x00010000);
 	} else {
-		if (info->flash_id & FLASH_BTYPE) {
-			/* set sector offsets for bottom boot block type        */
-			info->start[0] = base + 0x00000000;
-			info->start[1] = base + 0x00004000;
-			info->start[2] = base + 0x00006000;
-			info->start[3] = base + 0x00008000;
-			for (i = 4; i < info->sector_count; i++) {
-				info->start[i] = base + (i * 0x00010000) - 0x00030000;
-			}
-		} else {
-			/* set sector offsets for top boot block type           */
-			i = info->sector_count - 1;
-			info->start[i--] = base + info->size - 0x00004000;
-			info->start[i--] = base + info->size - 0x00006000;
-			info->start[i--] = base + info->size - 0x00008000;
-			for (; i >= 0; i--) {
-				info->start[i] = base + i * 0x00010000;
-			}
+	    if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
 		}
+	    } else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	    }
 	}
 }
 
 /*-----------------------------------------------------------------------
  */
-void flash_print_info (flash_info_t * info)
+void flash_print_info  (flash_info_t *info)
 {
 	int i;
 	int k;
@@ -265,35 +259,39 @@ void flash_print_info (flash_info_t * info)
 		info->size >> 10, info->sector_count);
 
 	printf ("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; ++i) {
+	for (i=0; i<info->sector_count; ++i) {
 		/*
 		 * Check if whole sector is erased
 		 */
-		if (i != (info->sector_count - 1))
-			size = info->start[i + 1] - info->start[i];
+		if (i != (info->sector_count-1))
+		  size = info->start[i+1] - info->start[i];
 		else
-			size = info->start[0] + info->size - info->start[i];
+		  size = info->start[0] + info->size - info->start[i];
 		erased = 1;
-		flash = (volatile unsigned long *) info->start[i];
-		size = size >> 2;	/* divide by 4 for longword access */
-		for (k = 0; k < size; k++) {
-			if (*flash++ != 0xffffffff) {
-				erased = 0;
-				break;
-			}
-		}
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;        /* divide by 4 for longword access */
+		for (k=0; k<size; k++)
+		  {
+		    if (*flash++ != 0xffffffff)
+		      {
+			erased = 0;
+			break;
+		      }
+		  }
 
 		if ((i % 5) == 0)
 			printf ("\n   ");
-#if 0				/* test-only */
+#if 0 /* test-only */
 		printf (" %08lX%s",
-			info->start[i], info->protect[i] ? " (RO)" : "     "
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
 #else
 		printf (" %08lX%s%s",
 			info->start[i],
-			erased ? " E" : "  ", info->protect[i] ? "RO " : "   "
+			erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   "
 #endif
-			);
+		);
 	}
 	printf ("\n");
 	return;
@@ -309,17 +307,17 @@ void flash_print_info (flash_info_t * info)
 /*
  * The following code cannot be run from FLASH!
  */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info)
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 {
 	short i;
 	FLASH_WORD_SIZE value;
-	ulong base = (ulong) addr;
-	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
+	ulong base = (ulong)addr;
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
 
 	/* Write auto select command: read Manufacturer ID */
-	addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
-	addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
-	addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090;
+	addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+	addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+	addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
 
 #ifdef CONFIG_ADCIOP
 	value = addr2[2];
@@ -328,126 +326,126 @@ static ulong flash_get_size (vu_long * addr, flash_info_t * info)
 #endif
 
 	switch (value) {
-	case (FLASH_WORD_SIZE) AMD_MANUFACT:
+	case (FLASH_WORD_SIZE)AMD_MANUFACT:
 		info->flash_id = FLASH_MAN_AMD;
 		break;
-	case (FLASH_WORD_SIZE) FUJ_MANUFACT:
+	case (FLASH_WORD_SIZE)FUJ_MANUFACT:
 		info->flash_id = FLASH_MAN_FUJ;
 		break;
-	case (FLASH_WORD_SIZE) SST_MANUFACT:
+	case (FLASH_WORD_SIZE)SST_MANUFACT:
 		info->flash_id = FLASH_MAN_SST;
 		break;
 	default:
 		info->flash_id = FLASH_UNKNOWN;
 		info->sector_count = 0;
 		info->size = 0;
-		return (0);	/* no or unknown flash  */
+		return (0);			/* no or unknown flash	*/
 	}
 
 #ifdef CONFIG_ADCIOP
-	value = addr2[0];	/* device ID            */
+	value = addr2[0];			/* device ID		*/
 	/*        printf("\ndev_code=%x\n", value); */
 #else
-	value = addr2[1];	/* device ID            */
+	value = addr2[1];			/* device ID		*/
 #endif
 
 	switch (value) {
-	case (FLASH_WORD_SIZE) AMD_ID_F040B:
+	case (FLASH_WORD_SIZE)AMD_ID_F040B:
 		info->flash_id += FLASH_AM040;
 		info->sector_count = 8;
-		info->size = 0x0080000;	/* => 512 ko */
+		info->size = 0x0080000; /* => 512 ko */
 		break;
-	case (FLASH_WORD_SIZE) AMD_ID_LV400T:
+	case (FLASH_WORD_SIZE)AMD_ID_LV400T:
 		info->flash_id += FLASH_AM400T;
 		info->sector_count = 11;
 		info->size = 0x00080000;
-		break;		/* => 0.5 MB            */
+		break;				/* => 0.5 MB		*/
 
-	case (FLASH_WORD_SIZE) AMD_ID_LV400B:
+	case (FLASH_WORD_SIZE)AMD_ID_LV400B:
 		info->flash_id += FLASH_AM400B;
 		info->sector_count = 11;
 		info->size = 0x00080000;
-		break;		/* => 0.5 MB            */
+		break;				/* => 0.5 MB		*/
 
-	case (FLASH_WORD_SIZE) AMD_ID_LV800T:
+	case (FLASH_WORD_SIZE)AMD_ID_LV800T:
 		info->flash_id += FLASH_AM800T;
 		info->sector_count = 19;
 		info->size = 0x00100000;
-		break;		/* => 1 MB              */
+		break;				/* => 1 MB		*/
 
-	case (FLASH_WORD_SIZE) AMD_ID_LV800B:
+	case (FLASH_WORD_SIZE)AMD_ID_LV800B:
 		info->flash_id += FLASH_AM800B;
 		info->sector_count = 19;
 		info->size = 0x00100000;
-		break;		/* => 1 MB              */
+		break;				/* => 1 MB		*/
 
-	case (FLASH_WORD_SIZE) AMD_ID_LV160T:
+	case (FLASH_WORD_SIZE)AMD_ID_LV160T:
 		info->flash_id += FLASH_AM160T;
 		info->sector_count = 35;
 		info->size = 0x00200000;
-		break;		/* => 2 MB              */
+		break;				/* => 2 MB		*/
 
-	case (FLASH_WORD_SIZE) AMD_ID_LV160B:
+	case (FLASH_WORD_SIZE)AMD_ID_LV160B:
 		info->flash_id += FLASH_AM160B;
 		info->sector_count = 35;
 		info->size = 0x00200000;
-		break;		/* => 2 MB              */
-#if 0				/* enable when device IDs are available */
-	case (FLASH_WORD_SIZE) AMD_ID_LV320T:
+		break;				/* => 2 MB		*/
+#if 0	/* enable when device IDs are available */
+	case (FLASH_WORD_SIZE)AMD_ID_LV320T:
 		info->flash_id += FLASH_AM320T;
 		info->sector_count = 67;
 		info->size = 0x00400000;
-		break;		/* => 4 MB              */
+		break;				/* => 4 MB		*/
 
-	case (FLASH_WORD_SIZE) AMD_ID_LV320B:
+	case (FLASH_WORD_SIZE)AMD_ID_LV320B:
 		info->flash_id += FLASH_AM320B;
 		info->sector_count = 67;
 		info->size = 0x00400000;
-		break;		/* => 4 MB              */
+		break;				/* => 4 MB		*/
 #endif
-	case (FLASH_WORD_SIZE) SST_ID_xF800A:
+	case (FLASH_WORD_SIZE)SST_ID_xF800A:
 		info->flash_id += FLASH_SST800A;
 		info->sector_count = 16;
 		info->size = 0x00100000;
-		break;		/* => 1 MB              */
+		break;				/* => 1 MB		*/
 
-	case (FLASH_WORD_SIZE) SST_ID_xF160A:
+	case (FLASH_WORD_SIZE)SST_ID_xF160A:
 		info->flash_id += FLASH_SST160A;
 		info->sector_count = 32;
 		info->size = 0x00200000;
-		break;		/* => 2 MB              */
+		break;				/* => 2 MB		*/
 
 	default:
 		info->flash_id = FLASH_UNKNOWN;
-		return (0);	/* => no or unknown flash */
+		return (0);			/* => no or unknown flash */
 
 	}
 
 	/* set up sector start address table */
 	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
-	    (info->flash_id == FLASH_AM040)) {
-		for (i = 0; i < info->sector_count; i++)
-			info->start[i] = base + (i * 0x00010000);
+	    (info->flash_id  == FLASH_AM040)){
+	    for (i = 0; i < info->sector_count; i++)
+		info->start[i] = base + (i * 0x00010000);
 	} else {
-		if (info->flash_id & FLASH_BTYPE) {
-			/* set sector offsets for bottom boot block type        */
-			info->start[0] = base + 0x00000000;
-			info->start[1] = base + 0x00004000;
-			info->start[2] = base + 0x00006000;
-			info->start[3] = base + 0x00008000;
-			for (i = 4; i < info->sector_count; i++) {
-				info->start[i] = base + (i * 0x00010000) - 0x00030000;
-			}
-		} else {
-			/* set sector offsets for top boot block type           */
-			i = info->sector_count - 1;
-			info->start[i--] = base + info->size - 0x00004000;
-			info->start[i--] = base + info->size - 0x00006000;
-			info->start[i--] = base + info->size - 0x00008000;
-			for (; i >= 0; i--) {
-				info->start[i] = base + i * 0x00010000;
-			}
+	    if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
 		}
+	    } else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	    }
 	}
 
 	/* check for protected sectors */
@@ -455,14 +453,14 @@ static ulong flash_get_size (vu_long * addr, flash_info_t * info)
 		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
 		/* D0 = 1 if protected */
 #ifdef CONFIG_ADCIOP
-		addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
+		addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
 		info->protect[i] = addr2[4] & 1;
 #else
-		addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
+		addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
 		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
-			info->protect[i] = 0;
+		  info->protect[i] = 0;
 		else
-			info->protect[i] = addr2[2] & 1;
+		  info->protect[i] = addr2[2] & 1;
 #endif
 	}
 
@@ -470,52 +468,52 @@ static ulong flash_get_size (vu_long * addr, flash_info_t * info)
 	 * Prevent writes to uninitialized FLASH.
 	 */
 	if (info->flash_id != FLASH_UNKNOWN) {
-#if 0				/* test-only */
+#if 0 /* test-only */
 #ifdef CONFIG_ADCIOP
-		addr2 = (volatile unsigned char *) info->start[0];
+		addr2 = (volatile unsigned char *)info->start[0];
 		addr2[ADDR0] = 0xAA;
 		addr2[ADDR1] = 0x55;
-		addr2[ADDR0] = 0xF0;	/* reset bank */
+		addr2[ADDR0] = 0xF0;  /* reset bank */
 #else
-		addr2 = (FLASH_WORD_SIZE *) info->start[0];
-		*addr2 = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+		addr2 = (FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
 #endif
-#else  /* test-only */
-		addr2 = (FLASH_WORD_SIZE *) info->start[0];
-		*addr2 = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+#else /* test-only */
+		addr2 = (FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
 #endif /* test-only */
 	}
 
 	return (info->size);
 }
 
-int wait_for_DQ7 (flash_info_t * info, int sect)
+int wait_for_DQ7(flash_info_t *info, int sect)
 {
 	ulong start, now, last;
-	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[sect]);
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
 
 	start = get_timer (0);
-	last = 0;
-	while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != (FLASH_WORD_SIZE) 0x00800080) {
-		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
-			printf ("Timeout\n");
-			return -1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			putc ('.');
-			last = now;
-		}
+    last  = start;
+    while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
+	if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	    printf ("Timeout\n");
+	    return -1;
 	}
+	/* show that we're waiting */
+	if ((now - last) > 1000) {  /* every second */
+	    putc ('.');
+	    last = now;
+	}
+    }
 	return 0;
 }
 
 /*-----------------------------------------------------------------------
  */
 
-int flash_erase (flash_info_t * info, int s_first, int s_last)
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
 {
-	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
 	volatile FLASH_WORD_SIZE *addr2;
 	int flag, prot, sect, l_sect;
 	int i;
@@ -535,14 +533,15 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 	}
 
 	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
+	for (sect=s_first; sect<=s_last; ++sect) {
 		if (info->protect[sect]) {
 			prot++;
 		}
 	}
 
 	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
 	} else {
 		printf ("\n");
 	}
@@ -550,46 +549,46 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 	l_sect = -1;
 
 	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
+	flag = disable_interrupts();
 
 	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last; sect++) {
+	for (sect = s_first; sect<=s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
-			addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
-			printf ("Erasing sector %p\n", addr2);	/* CLH */
+		    addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
+		    printf("Erasing sector %p\n", addr2);	/* CLH */
 
-			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
-				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
-				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
-				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
-				addr2[0] = (FLASH_WORD_SIZE) 0x00500050;	/* block erase */
-				for (i = 0; i < 50; i++)
-					udelay (1000);	/* wait 1 ms */
-			} else {
-				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
-				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
-				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
-				addr2[0] = (FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
-			}
-			l_sect = sect;
-			/*
-			 * Wait for each sector to complete, it's more
-			 * reliable.  According to AMD Spec, you must
-			 * issue all erase commands within a specified
-			 * timeout.  This has been seen to fail, especially
-			 * if printf()s are included (for debug)!!
-			 */
-			wait_for_DQ7 (info, sect);
+		    if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+			addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+			addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+			addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+			addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+			addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+			addr2[0] = (FLASH_WORD_SIZE)0x00500050;  /* block erase */
+			for (i=0; i<50; i++)
+				udelay(1000);  /* wait 1 ms */
+		    } else {
+			addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+			addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+			addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+			addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+			addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+			addr2[0] = (FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+		    }
+		    l_sect = sect;
+		    /*
+		     * Wait for each sector to complete, it's more
+		     * reliable.  According to AMD Spec, you must
+		     * issue all erase commands within a specified
+		     * timeout.  This has been seen to fail, especially
+		     * if printf()s are included (for debug)!!
+		     */
+		    wait_for_DQ7(info, sect);
 		}
 	}
 
 	/* re-enable interrupts if necessary */
 	if (flag)
-		enable_interrupts ();
+		enable_interrupts();
 
 	/* wait at least 80us - let's wait 1 ms */
 	udelay (1000);
@@ -600,13 +599,13 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 	 */
 	if (l_sect < 0)
 		goto DONE;
-	wait_for_DQ7 (info, l_sect);
+	wait_for_DQ7(info, l_sect);
 
-      DONE:
+DONE:
 #endif
 	/* reset to read mode */
-	addr = (FLASH_WORD_SIZE *) info->start[0];
-	addr[0] = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+	addr = (FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
 
 	printf (" done\n");
 	return 0;
@@ -619,7 +618,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
  * 2 - Flash not erased
  */
 
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 {
 	ulong cp, wp, data;
 	int i, l, rc;
@@ -631,19 +630,19 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 	 */
 	if ((l = addr - wp) != 0) {
 		data = 0;
-		for (i = 0, cp = wp; i < l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *) cp);
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
 		}
-		for (; i < 4 && cnt > 0; ++i) {
+		for (; i<4 && cnt>0; ++i) {
 			data = (data << 8) | *src++;
 			--cnt;
 			++cp;
 		}
-		for (; cnt == 0 && i < 4; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *) cp);
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
 		}
 
-		if ((rc = write_word (info, wp, data)) != 0) {
+		if ((rc = write_word(info, wp, data)) != 0) {
 			return (rc);
 		}
 		wp += 4;
@@ -654,13 +653,13 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 	 */
 	while (cnt >= 4) {
 		data = 0;
-		for (i = 0; i < 4; ++i) {
+		for (i=0; i<4; ++i) {
 			data = (data << 8) | *src++;
 		}
-		if ((rc = write_word (info, wp, data)) != 0) {
+		if ((rc = write_word(info, wp, data)) != 0) {
 			return (rc);
 		}
-		wp += 4;
+		wp  += 4;
 		cnt -= 4;
 	}
 
@@ -672,15 +671,15 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 	 * handle unaligned tail bytes
 	 */
 	data = 0;
-	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
 		data = (data << 8) | *src++;
 		--cnt;
 	}
-	for (; i < 4; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *) cp);
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
 	}
 
-	return (write_word (info, wp, data));
+	return (write_word(info, wp, data));
 }
 
 /*-----------------------------------------------------------------------
@@ -699,7 +698,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data)
 
 	/* Check if Flash is (sufficiently) erased */
 	if ((*((volatile FLASH_WORD_SIZE *) dest) &
-	     (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
+	    (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
 		return (2);
 	}
 

board/c2mon/c2mon.c

@@ -227,8 +227,40 @@ static long int dram_size (long int mamr_value, long int *base,
 {
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	volatile long int *addr;
+	ulong cnt, val;
+	ulong save[32];			/* to make test non-destructive */
+	unsigned char i = 0;
 
 	memctl->memc_mamr = mamr_value;
 
-	return (get_ram_size(base, maxsize));
+	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
+		addr = base + cnt;	/* pointer arith! */
+
+		save[i++] = *addr;
+		*addr = ~cnt;
+	}
+
+	/* write 0 to base address */
+	addr = base;
+	save[i] = *addr;
+	*addr = 0;
+
+	/* check at base address */
+	if ((val = *addr) != 0) {
+		*addr = save[i];
+		return (0);
+	}
+
+	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+		addr = base + cnt;	/* pointer arith! */
+
+		val = *addr;
+		*addr = save[--i];
+
+		if (val != (~cnt)) {
+			return (cnt * sizeof (long));
+		}
+	}
+	return (maxsize);
 }

board/cogent/lcd.c

@@ -229,17 +229,3 @@ lcd_heartbeat(void)
     if (++rotator_index >= (sizeof rotchars / sizeof rotchars[0]))
 	rotator_index = 0;
 }
-
-#ifdef CONFIG_SHOW_ACTIVITY
-void board_show_activity (ulong timestamp)
-{
-#ifdef CONFIG_STATUS_LED
-	if ((timestamp % (CFG_HZ / 2) == 0)
-		lcd_heartbeat ();
-#endif
-}
-
-void show_activity(int arg)
-{
-}
-#endif

board/cpc45/cpc45.c

@@ -32,7 +32,7 @@ extern void Plx9030Init(void);
 	/* We have to clear the initial data area here. Couldn't have done it
 	 * earlier because DRAM had not been initialized.
 	 */
-int board_early_init_f(void)
+int board_pre_init(void)
 {
 
 	/* enable DUAL UART Mode on CPC45 */
@@ -60,24 +60,51 @@ int checkboard(void)
 
 long int initdram(int board_type)
 {
-	long size;
-	long new_bank0_end;
-	long mear1;
-	long emear1;
+	int              i, cnt;
+	volatile uchar * base      = CFG_SDRAM_BASE;
+	volatile ulong * addr;
+	ulong            save[32];
+	ulong            val, ret  = 0;
 
-	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+	for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
 
-	new_bank0_end = size - 1;
-	mear1 = mpc824x_mpc107_getreg(MEAR1);
-	emear1 = mpc824x_mpc107_getreg(EMEAR1);
-	mear1 = (mear1  & 0xFFFFFF00) |
-		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
-	emear1 = (emear1 & 0xFFFFFF00) |
-		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
-	mpc824x_mpc107_setreg(MEAR1, mear1);
-	mpc824x_mpc107_setreg(EMEAR1, emear1);
+		addr = (volatile ulong *)base + cnt;
+		save[i++] = *addr;
+		*addr = ~cnt;
+	}
 
-	return (size);
+	addr = (volatile ulong *)base;
+	save[i] = *addr;
+	*addr = 0;
+
+	if (*addr != 0) {
+		*addr = save[i];
+		goto Done;
+	}
+
+	for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
+		addr = (volatile ulong *)base + cnt;
+		val = *addr;
+		*addr = save[--i];
+		if (val != ~cnt) {
+			ulong new_bank0_end = cnt * sizeof(long) - 1;
+			ulong mear1  = mpc824x_mpc107_getreg(MEAR1);
+			ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
+			mear1 =  (mear1  & 0xFFFFFF00) |
+			  ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+			emear1 = (emear1 & 0xFFFFFF00) |
+			  ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+			mpc824x_mpc107_setreg(MEAR1,  mear1);
+			mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+			ret = cnt * sizeof(long);
+			goto Done;
+		}
+	}
+
+	ret = CFG_MAX_RAM_SIZE;
+Done:
+	return ret;
 }
 
 /*

board/cpu86/cpu86.c

@@ -213,10 +213,13 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 			  ulong orx, volatile uchar * base)
 {
 	volatile uchar c = 0xff;
+	ulong cnt, val;
+	volatile ulong *addr;
 	volatile uint *sdmr_ptr;
 	volatile uint *orx_ptr;
-	ulong maxsize, size;
 	int i;
+	ulong save[32];		/* to make test non-destructive */
+	ulong maxsize;
 
 	/* We must be able to test a location outsize the maximum legal size
 	 * to find out THAT we are outside; but this address still has to be
@@ -266,11 +269,41 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
 	*base = c;
 
-	size = get_ram_size((long *)base, maxsize);
+	/*
+	 * Check memory range for valid RAM. A simple memory test determines
+	 * the actually available RAM size between addresses `base' and
+	 * `base + maxsize'. Some (not all) hardware errors are detected:
+	 * - short between address lines
+	 * - short between data lines
+	 */
+	i = 0;
+	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
+		addr = (volatile ulong *) base + cnt;	/* pointer arith! */
+		save[i++] = *addr;
+		*addr = ~cnt;
+	}
 
-	*orx_ptr = orx | ~(size - 1);
+	addr = (volatile ulong *) base;
+	save[i] = *addr;
+	*addr = 0;
 
-	return (size);
+	if ((val = *addr) != 0) {
+		*addr = save[i];
+		return (0);
+	}
+
+	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+		addr = (volatile ulong *) base + cnt;	/* pointer arith! */
+		val = *addr;
+		*addr = save[--i];
+		if (val != ~cnt) {
+			/* Write the actual size to ORx
+			 */
+			*orx_ptr = orx | ~(cnt * sizeof (long) - 1);
+			return (cnt * sizeof (long));
+		}
+	}
+	return (maxsize);
 }
 
 long int initdram (int board_type)

board/cradle/config.mk

@@ -1,2 +1,2 @@
-TEXT_BASE = 0xa0f80000
+TEXT_BASE = 0xa0f08000
 #TEXT_BASE = 0

board/cradle/cradle.c

@@ -170,7 +170,7 @@ init_sio (int led, unsigned long base)
 
 int
 /**********************************************************/
-board_late_init (void)
+board_post_init (void)
 /**********************************************************/
 {
 	return (0);

board/cradle/flash.c

@@ -59,7 +59,7 @@ ulong flash_init(void)
 		flashbase = PHYS_FLASH_2;
 		break;
 	 default:
-		panic("configured too many flash banks!\n");
+		panic("configured to many flash banks!\n");
 		break;
       }
       for (j = 0; j < flash_info[i].sector_count; j++)

board/cradle/u-boot.lds

@@ -44,12 +44,17 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }
 
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
+   __u_boot_cmd_start = .;
+   .u_boot_cmd : { *(.u_boot_cmd) }
+   __u_boot_cmd_end = .;
+
+	armboot_end_data = .;
 
 	. = ALIGN(4);
-	__bss_start = .;
+	bss_start = .;
 	.bss : { *(.bss) }
-	_end = .;
+	bss_end = .;
+
+	armboot_end = .;
+
 }

board/cray/L1/L1.c

@@ -109,7 +109,7 @@ extern char bootscript[];
 static void init_sdram (void);
 
 /* ------------------------------------------------------------------------- */
-int board_early_init_f (void)
+int board_pre_init (void)
 {
 	/* Running from ROM: global data is still READONLY */
 	init_sdram ();