Renamed UC100 => uc100

Cleanup: avoid trigraph warning in fs/ext2/ext2fs.c; rename UC100 -> uc100
Add support for UC100 board
2026-06-02 17:56:44 +03:00 · 2004-12-19 10:09:07 +00:00 · 2004-12-19 09:58:11 +00:00 · 2004-12-18 22:35:43 +00:00 · 2004-12-17 09:13:49 +00:00 · 2004-12-16 21:44:03 +00:00
526 changed files with 87909 additions and 11596 deletions
--- a/259
+++ b/259
@@ -2,6 +2,265 @@
 Changes since U-Boot 1.1.1:
 ======================================================================

+* Cleanup:
+  - avoid trigraph warning in fs/ext2/ext2fs.c
+  - rename UC100 -> uc100
+
+* Add support for UC100 board
+
+* Patch by Stefan Roese, 16 Dez 2004:
+  - ext2fs support added
+  - Tundra universe support added
+  - Coldfire MCF5249 support added (no preloader needed!)
+  - MCF5249 board TASREG added
+  - PPC boards added: APC405, CPCI405DT, CPCI750, G2000, HH405,
+    VOM405, WUH405
+  - some esd boards updated
+  - memory commands "mdc" and "mwc" added for cyclic read/write
+    (CONFIG_MX_CYCLIC, see README for further description)
+
+* Add support for INKA4X0 board
+
+* Patch by Steven Scholz, 12 Dec 2004:
+  Fix typo in AT91 memory setup.
+
+* Patch by Martin Krause, 27 Oct 2004:
+  - add support for "STK52xx" board (including PS/2 multiplexer)
+  - add hardware detection for TQM5200
+
+* Clean up CMC PU2 flash driver
+
+* Update MAINTAINERS file
+
+* Fix bug in MPC823 LCD driver
+
+* Fix udelay() on AT91RM9200 for delays < 1 ms.
+
+* Enable long help on CMC PU2 board;
+  fix reset issue;
+  increase CPU speed from 179 to 207 MHz.
+
+* Fix smc91111 ethernet driver for Xaeniax board (need to handle
+  unaligned tail part specially).
+
+* Update for AT91RM9200DK and CMC_PU2 boards:
+  - Enable booting directly from flash
+  - fix CMC_PU2 flash driver
+
+* Fix mkimage usage message
+
+* Map SRAM on NC650 board
+
+* Work around for Ethernet problems on Xaeniax board
+
+* Patch by TsiChung Liew, 23 Sep 2004:
+  - add support for MPC8220 CPU
+  - Add support for Alaska and Yukon boards
+
+* Fix configuration for ERIC board (needs more room)
+
+* Adjust MIPS compiler options at run-time depending on tools version
+  ("-march=4kc -mtune=4kc -Wa,-mips_allow_branch_to_undefined" for new,
+  "-mcpu=4kc" for old tools)
+
+* Add passing of the command line and memory size information to  the
+  kernel on xaeniax board.
+
+* Enable NAND flash support for NC650 board.
+
+* Patch by Thomas Lange 07 Oct 2004:
+  Updated README for DBAu1x00 boards to match current status
+
+* Patch by Philippe Robin, 28 Sept 2004:
+  Fix Flash support for Versatile.
+
+* Patch by Roger Blofeld, 16 Sep 2004:
+  Fix timeout for DHCP command retry
+
+* Patch by Pantelis Antoniou, 14 Sep 2004:
+  Fix early serial hang when CONFIG_SERIAL_MULTI is defined.
+
+* Patch by Pantelis Antoniou, 14 Sep 2004:
+  Kick watchdog when bz-decompressing
+
+* Fix CFG_HZ problems on AT91RM9200 systems
+  [Remember: CFG_HZ should be 1000 on ALL systems!]
+
+* Patch by Gridish Shlomi, 30 Aug 2004:
+  - Add support to revA version of PQ27 and PQ27E.
+  - Reverted MPC8260ADS baudrate back to original 115200
+
+* Patch by Hojin, 17 Sep 2004:
+  Fix typo in cfi_flash.c
+
+* Patch by Mark Jonas, 09 September 2004:
+  mtest's data line test (with CFG_ALT_MEMTEST set) returned a wrong
+  error message
+
+* Patch by Mark Jonas, 31 August 2004:
+  Added option CFG_XLB_PIPELINING to enable XLB pipelining. This
+  improves FTP performance for MPC5200 systems. Enabled for IceCube
+  by default.
+
+* Patch by Michael Bendzick, 30 Aug 2004:
+  - Improve platform.S code for omap1510inn that detects whether code
+    is running from SDRAM or not. Patch allows SDRAM to be configured
+    if code is running out of SRAM at 0x20000000.
+
+* Patch by Frederick Klatt, 30 Aug 2004:
+  Add support for the Wind River SBC8540/SBC8560 boards
+
+* Configure SX1 board to use drivers/cfi_flash.c
+
+* Patches by Michael Bendzick, 30 Aug 2004:
+  - Configure omap1510inn board to use drivers/cfi_flash.c
+  - Make drivers/cfi_flash.c protect environment and redundant
+    environment.
+
+* Patch by Steven Scholz, 23 Jun 2004:
+  - Add script (tools/img2brec.sh) to programm U-Boot into
+    (Synch)Flash using the Bootstrap Mode of the MC9328MX1/L
+
+* Patches by Scott McNutt, 24 Aug 2004:
+  - Add support for Altera Nios-II processors.
+  - Add support for Psyent PCI-5441 board.
+  - Add support for Psyent PK1C20 board.
+
+* Patches by Jon Loeliger, 24 Aug 2004:
+  - Add support for the MPC8541 and MPC8555 CDS boards
+  - Cleanup eth?addr handling: make dependent on CONFIG_ETH?ADDR
+  - Convert MPC85xxADS to use common CFI flash driver
+  - Fix PCI window on MPC85xx; remove unneeded PCI initialization
+    from board_early_init_f()
+  - Provide SW workaround for PCI initialization on 85xx CDS
+
+* Patches by George G. Davis, 24 Aug 2004:
+  - Enable ramdisk/initrd tagged param support for omap1610h2_config
+  - Remove static network setup defaults from mx1ads_config
+  - update ARM boards to use constants from mach-types.h
+
+* Patch by Gary Jennejohn, 04 Oct 2004:
+  - fix I2C on at91rm9200
+  - add support for Ricoh RS5C372A RTC
+
+* Patch by Gary Jennejohn, 01 Oct 2004:
+  - add support for CMC PU2 board
+  - add support for I2C on at91rm9200
+
+* Patch by Gary Jennejohn, 28 Sep 2004:
+  fix baudrate handling on at91rm9200
+
+* Patch by Yuli Barcohen, 22 Aug 2004:
+  - remove ZPC.1900 board-specific flash driver;
+    switch the port to generic CFI driver;
+  - port clean-up
+
+* Patch by Hinko Kocevar, 21 Aug 2004:
+  Add calc_fbsize() function used with VIDEOLFB_TAG on TRAB
+
+* Clean up tools/bmp_logo.c to not add trailing white space
+
+* Patch by Hinko Kocevar, 21 Aug 2004:
+  - Group common framebuffer functions in common/lcd.c
+  - Group common framebuffer macros and #defines in include/lcd.h
+  - Provide calc_fbsize() for video ATAG
+
+* Patch by Sam Song, 21 August 2004:
+  - Fix a typo in README
+  - Align "(RO)" output for "flinfo" after "protect on"
+  - Add RESET support for RPXlite_DW board; adjust CPU:BUS frequency
+    ratio 1:1 when core frequency less than 50MHz
+
+* Patches by Hinko Kocevar, 21 Aug 2004:
+  - fix some "use of label at end of compound statement" warnings
+  - Define type of LCD panel on lubbock board if CONFIG_LCD is used
+
+* Patch by Steven Scholz, 16 Aug 2004:
+  - Introducing the concept of SoCs "./cpu/$(CPU)/$(SOC)"
+  - creating subdirs for SoCs ./cpu/arm920t/imx and ./cpu/arm920t/s3c24x0
+  - moving SoC specific code out of cpu/arm920t/ into cpu/arm920t/$(SOC)/
+  - moving drivers/s3c24x0_i2c.c and drivers/serial_imx.c out of drivers/
+    into cpu/arm920t/$(SOC)/
+
+* Patches by Sean Chang, 09 Aug 2004:
+  - Added support for both 8 and 16 bit mode access to System ACE CF
+    through MPU.
+  - Fixed missing System ACE CF device during get FAT partition info
+    in fat_register_device function.
+  - Enabled System ACE CF support on ML300.
+
+* Patch by Sean Chang, 09 Aug 2004:
+  Synch defines for saveenv and do_saveenv functions so they get
+  compiled under the same statement.
+
+* Patch by Sean Chang, 09 Aug 2004:
+  - Added I2C support for ML300.
+  - Added support for ML300 to read out its environment information
+    stored on the EEPROM.
+  - Added support to use board specific parameters as part of
+    U-Boot's environment information.
+  - Updated MLD files to support configuration for new features
+    above.
+
+* Patches by Travis Sawyer, 05 Aug 2004:
+  - Remove incorrect bridge settings for eth group 6
+  - Add call to setup bridge in ppc_440x_eth_initialize
+  - Fix ppc_440x_eth_init to reset the phy only if its the
+    first time through, otherwise, just check the phy for the
+    autonegotiated speed/duplex.  This allows the use of netconsole
+  - only print the speed/duplex the first time the phy is reset.
+
+* Patch by Shlomo Kut, 29 Mar 2004:
+  Add support for MKS Instruments "Quantum" board
+
+* Fix build problem with Cogent boards;
+  avoid using <asm/byteorder.h> when using the host compiler
+
+* Patch by Ganapathi C, 04 Aug 2004:
+  Fix NFS timeout issue
+
+* Patch by Yuli Barcohen, 19 Jul 2004:
+  - Fix host tools building in Cygwin environment
+  - Fix header files search order for host tools
+
+* Patch by Tom Armistead, 19 Jul 2004:
+  Fix kgdb.S support for 74xx_75x cpu
+
+* Patch by Jon Loeliger, 15 Jul 2004:
+  Fix MPC85xx I2C driver
+
+* Fix problems with CDROM drive as slave device on Lite5200 IDE bus.
+
+* Patch by Stephen Williams, 15 July 2004
+  Set the PCI class code for JSE board as part of PCI interface setup
+
+* Patch by Michael Bendzick, 15 Jul 2004:
+  Fix problem with writes with odd sizes in drivers/cfi_flash.c when
+  CFG_FLASH_USE_BUFFER_WRITE is set
+
+* Patch by Yuli Barcohen, 13 Jul 2004:
+  Allow clock setting on MPC866/MPC885 series chips according to
+  environment variable `cpuclk'
+
+* Patch by Yuli Barcohen, 20 Apr 2004:
+  Remove unnecessary redefine of CPM_DATAONLY_SIZE for MPC826x
+
+* Patch by Vincent Dubey, 24 Sep 2004:
+  Add support for xaeniax board
+
+* Add comment about non-GPL character of standalone applications to
+  COPYING file
+
+* Fix FEC ethernet problem on NSCU board.
+
+* Patch by Gary Jennejohn, 09 Sep 2004:
+  allow to use USART1 as console port on at91rm9200dk boards
+
+* Patch by Stefan Roese, 16 Sep 2004:
+  Update AR405 board.
+
+* Fix SysClk handling for PPChameleon and CATcenter boards
+
 * Patch by Detlev Zundel, 08 Sep 2004:
  Update etags build target

--- a/11
+++ b/11
@@ -1,3 +1,14 @@
+  NOTE! This copyright does *not* cover the so-called "standalone"
+applications that use U-Boot services by means of the jump table
+provided by U-Boot exactly for this purpose - this is merely
+considered normal use of U-Boot, and does *not* fall under the
+heading of "derived work". Also note that the GPL below is
+copyrighted by the Free Software Foundation, but the instance of code
+that it refers to (the U-Boot source code) is copyrighted by me and
+others who actually wrote it. -- Wolfgang Denk
+
+=======================================================================
+
 		    GNU GENERAL PUBLIC LICENSE
 		       Version 2, June 1991

--- a/9
+++ b/9
@@ -223,6 +223,10 @@ N: Sangmoon Kim
 E: dogoil@etinsys.com
 D: Support for debris board

+N: Frederick W. Klatt
+E: fred.klatt@windriver.com
+D: Support for Wind River SBC8540/SBC8560 boards
+
 N: Thomas Koeller
 E: tkoeller@gmx.net
 D: Port to Motorola Sandpoint 3 (MPC8240)
@@ -286,7 +290,10 @@ D: Support for Samsung ARM920T SMDK2410 eval board

 N: Scott McNutt
 E: smcnutt@psyent.com
-D: Support for Altera Nios-32 CPU, for Nios Cyclone Development Kit (DK-1C20)
+D: Support for Altera Nios-32 CPU
+D: Support for Altera Nios-II CPU
+D: Support for Nios Cyclone Development Kit (DK-1C20)
+W: http://www.psyent.com

 N: Rolf Offermanns
 E: rof@sysgo.de
--- a/40
+++ b/40
@@ -25,6 +25,10 @@ Pantelis Antoniou <panto@intracom.gr>

 	NETVIA			MPC8xx

+Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+
+	CPCI750			PPC750FX/GX
+
 Yuli Barcohen <yuli@arabellasw.com>

 	Adder			MPC87x/MPC852T
@@ -209,6 +213,13 @@ Frank Panno <fpanno@delphintech.com>

 	ep8260			MPC8260

+Peter Pearse <peter.pearse@arm.com>
+
+	Integrator/AP		CM 926EJ-S, CM7x0T, CM9x0T
+	Integrator/CP		CM 926EJ-S  CM920T, CM940T, CM922T-XA10
+	Versatile/AB		ARM926EJ-S
+	Versatile/PB		ARM926EJ-S
+
 Denis Peter <d.peter@mpl.ch>

 	MIP405			PPC4xx
@@ -217,17 +228,21 @@ Denis Peter <d.peter@mpl.ch>
 Stefan Roese <stefan.roese@esd-electronics.com>

 	ADCIOP			IOP480 (PPC401)
+	APC405			PPC405GP
 	AR405			PPC405GP
 	ASH405			PPC405EP
 	CANBT			PPC405CR
 	CPCI405			PPC405GP
 	CPCI4052		PPC405GP
 	CPCI405AB		PPC405GP
+	CPCI405DT		PPC405GP
 	CPCI440			PPC440GP
 	CPCIISER4		PPC405GP
 	DASA_SIM		IOP480 (PPC401)
 	DP405			PPC405EP
 	DU405			PPC405GP
+	G2000			PPC405EP
+	HH405			PPC405EP
 	HUB405			PPC405EP
 	OCRTC			PPC405GP
 	ORSG			PPC405GP
@@ -235,6 +250,8 @@ Stefan Roese <stefan.roese@esd-electronics.com>
 	PLU405			PPC405EP
 	PMC405			PPC405GP
 	VOH405			PPC405EP
+	VOM405			PPC405EP
+	WUH405			PPC405EP

 Travis Sawyer (travis.sawyer@sandburst.com>

@@ -430,6 +447,18 @@ Scott McNutt <smcnutt@psyent.com>

 	DK1C20			Nios-32

+#########################################################################
+# Nios-II Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board			CPU					#
+#########################################################################
+
+Scott McNutt <smcnutt@psyent.com>
+
+	PCI5441			Nios-II
+	PK1C20			Nios-II
+
 #########################################################################
 # MicroBlaze Systems:							#
 #									#
@@ -441,6 +470,17 @@ Yasushi Shoji <yashi@atmark-techno.com>

 	SUZAKU			MicroBlaze

+#########################################################################
+# Coldfire Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board			CPU					#
+#########################################################################
+
+Stefan Roese <stefan.roese@esd-electronics.com>
+
+	TASREG			MCF5249
+
 #########################################################################
 # End of MAINTAINERS list						#
 #########################################################################
--- a/76
+++ b/76
@@ -34,23 +34,25 @@ LIST_5xxx="	\
 #########################################################################

 LIST_8xx="	\
-	Adder87x	GENIETV		MBX860T		RBC823		\
-	AdderII		GTH		MHPC		rmu		\
-	ADS860		hermes		MPC86xADS	RPXClassic	\
-	AMX860		IAD210		MPC885ADS	RPXlite		\
-	c2mon		ICU862_100MHz	MVS1		RPXlite_DW	\
-	CCM		IP860		NETPHONE	RRvision	\
-	cogent_mpc8xx	IVML24		NETTA		SM850		\
-	ELPT860		IVML24_128	NETTA2		SPD823TS	\
-	ESTEEM192E	IVML24_256	NETTA_ISDN	svm_sc8xx	\
-	ETX094		IVMS8		NETVIA		SXNI855T	\
-	FADS823		IVMS8_128	NETVIA_V2	TOP860		\
-	FADS850SAR	IVMS8_256	NX823		TQM823L		\
-	FADS860T	KUP4K		pcu_e		TQM823L_LCD	\
-	FLAGADM		KUP4X		QS823		TQM850L		\
-	FPS850L		LANTEC		QS850		TQM855L		\
-	GEN860T		lwmon		QS860T		TQM860L		\
-	GEN860T_SC	MBX		R360MPI		v37		\
+	Adder87x	GENIETV		MBX860T		R360MPI		\
+	AdderII		GTH		MHPC		RBC823		\
+	ADS860		hermes		MPC86xADS	rmu		\
+	AMX860		IAD210		MPC885ADS	RPXClassic	\
+	c2mon		ICU862_100MHz	MVS1		RPXlite		\
+	CCM		IP860		NETPHONE	RPXlite_DW	\
+	cogent_mpc8xx	IVML24		NETTA		RRvision	\
+	ELPT860		IVML24_128	NETTA2		SM850		\
+	ESTEEM192E	IVML24_256	NETTA_ISDN	SPD823TS	\
+	ETX094		IVMS8		NETVIA		svm_sc8xx	\
+	FADS823		IVMS8_128	NETVIA_V2	SXNI855T	\
+	FADS850SAR	IVMS8_256	NX823		TOP860		\
+	FADS860T	KUP4K		pcu_e		TQM823L		\
+	FLAGADM		KUP4X		QS823		TQM823L_LCD	\
+	FPS850L		LANTEC		QS850		TQM850L		\
+	GEN860T		lwmon		QS860T		TQM855L		\
+	GEN860T_SC	MBX		quantum		TQM860L		\
+							uc100		\
+							v37		\
 "

 #########################################################################
@@ -67,7 +69,15 @@ LIST_4xx="	\
 	ml300		OCOTEA		OCRTC		ORSG		\
 	PCI405		PIP405		PLU405		PMC405		\
 	PPChameleonEVB	VOH405		W7OLMC		W7OLMG		\
-	WALNUT405	XPEDITE1K					\
+	WALNUT405	WUH405          XPEDITE1K			\
+"
+
+#########################################################################
+## MPC8220 Systems
+#########################################################################
+
+LIST_8220="	\
+	Alaska8220	Yukon8220					\
 "

 #########################################################################
@@ -99,7 +109,8 @@ LIST_8260="	\
 #########################################################################

 LIST_85xx="	\
-	MPC8540ADS	MPC8560ADS	sbc8560		stxgp3		\
+	MPC8540ADS	MPC8541CDS	MPC8555CDS	MPC8560ADS	\
+	sbc8540		sbc8560		stxgp3				\
 "

 #########################################################################
@@ -112,7 +123,7 @@ LIST_74xx="	\
 "

 LIST_7xx="	\
-	BAB7xx		ELPPC						\
+	BAB7xx		CPCI750		ELPPC				\
 "

 LIST_ppc="${LIST_5xx}  ${LIST_5xxx} \
@@ -139,17 +150,22 @@ LIST_ARM7="B2 ep7312 evb4510 impa7 modnet50"
 #########################################################################

 LIST_ARM9="	\
-	at91rm9200dk	integratorcp	integratorap 	lpd7a400	\
-	mx1ads		mx1fs2		omap1510inn	omap1610h2	\
-	omap1610inn	omap730p2	scb9328		smdk2400	\
-	smdk2410	trab		VCMA9		versatile	\
+	at91rm9200dk	cmc_pu2		integratorcp	integratorap 	\
+	lpd7a400	mx1ads		mx1fs2		omap1510inn	\
+	omap1610h2	omap1610inn	omap730p2	scb9328		\
+	smdk2400	smdk2410	trab		VCMA9		\
+	versatile							\
 "

 #########################################################################
 ## Xscale Systems
 #########################################################################

-LIST_pxa="cerf250 cradle csb226 innokom lubbock wepep250 xm250 xsengine"
+LIST_pxa="	\
+	cerf250		cradle		csb226		innokom		\
+	lubbock		wepep250	xaeniax		xm250		\
+	xsengine							\
+"

 LIST_ixp="ixdp425"

@@ -187,6 +203,12 @@ LIST_nios="	\
 	DK1S10 DK1S10_standard_32 DK1S10_mtx_ldk_20			\
 "

+#########################################################################
+## Nios-II Systems
+#########################################################################
+
+LIST_nios2="PCI5441 PK1C20"
+
 #########################################################################
 ## MicroBlaze Systems
 #########################################################################
@@ -215,11 +237,11 @@ build_target() {
 for arg in $@
 do
 	case "$arg" in
-	ppc|5xx|5xxx|8xx|824x|8260|85xx|4xx|7xx|74xx| \
+	ppc|5xx|5xxx|8xx|8220|824x|8260|85xx|4xx|7xx|74xx| \
 	arm|SA|ARM7|ARM9|pxa|ixp| \
 	microblaze| \
 	mips| \
-	nios| \
+	nios|nios2| \
 	x86|I486)
 			for target in `eval echo '$LIST_'${arg}`
 			do
--- a/136
+++ b/136
@@ -45,7 +45,7 @@ export	TOPDIR
 ifeq (include/config.mk,$(wildcard include/config.mk))
 # load ARCH, BOARD, and CPU configuration
 include include/config.mk
-export	ARCH CPU BOARD VENDOR
+export	ARCH CPU BOARD VENDOR SOC
 # load other configuration
 include $(TOPDIR)/config.mk

@@ -72,6 +72,9 @@ endif
 ifeq ($(ARCH),nios)
 CROSS_COMPILE = nios-elf-
 endif
+ifeq ($(ARCH),nios2)
+CROSS_COMPILE = nios2-elf-
+endif
 ifeq ($(ARCH),m68k)
 CROSS_COMPILE = m68k-elf-
 endif
@@ -101,9 +104,12 @@ endif
 LIBS  = lib_generic/libgeneric.a
 LIBS += board/$(BOARDDIR)/lib$(BOARD).a
 LIBS += cpu/$(CPU)/lib$(CPU).a
+ifdef SOC
+LIBS += cpu/$(CPU)/$(SOC)/lib$(SOC).a
+endif
 LIBS += lib_$(ARCH)/lib$(ARCH).a
 LIBS += fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a fs/jffs2/libjffs2.a \
-	fs/reiserfs/libreiserfs.a
+	fs/reiserfs/libreiserfs.a fs/ext2/libext2fs.a
 LIBS += net/libnet.a
 LIBS += disk/libdisk.a
 LIBS += rtc/librtc.a
@@ -252,6 +258,9 @@ icecube_5100_config:			unconfig
 		}
 	@./mkconfig -a IceCube ppc mpc5xxx icecube

+inka4x0_config:		unconfig
+	@./mkconfig inka4x0 ppc mpc5xxx inka4x0
+
 PM520_config \
 PM520_DDR_config \
 PM520_ROMBOOT_config \
@@ -301,6 +310,7 @@ Total5200_Rev2_lowboot_config:	unconfig
 		}
 	@./mkconfig -a Total5200 ppc mpc5xxx total5200

+TQM5200_auto_config		\
 TQM5200_AA_config	\
 TQM5200_AB_config	\
 TQM5200_AC_config	\
@@ -325,6 +335,10 @@ MiniFAP_config:	unconfig
 		  echo "... with 4 MB Flash, 128 MB SDRAM" ; \
 		  echo "... with Graphics Controller"; \
 		}
+	@[ -z "$(findstring auto,$@)" ] || \
+		{ echo "#define CONFIG_CS_AUTOCONF"	>>include/config.h ; \
+		  echo "... with automatic CS configuration" ; \
+		}
 	@./mkconfig -a TQM5200 ppc mpc5xxx tqm5200

 #########################################################################
@@ -553,6 +567,9 @@ QS823_config:	unconfig
 QS860T_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx qs860t snmc

+quantum_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc8xx quantum
+
 R360MPI_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx r360mpi

@@ -650,6 +667,9 @@ TTTech_config:	unconfig
 	@echo "#define CONFIG_SHARP_LQ104V7DS01" >>include/config.h
 	@./mkconfig -a TQM823L ppc mpc8xx tqm8xx

+uc100_config	:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc8xx uc100
+
 v37_config:	unconfig
 	@echo "#define CONFIG_LCD" >include/config.h
 	@echo "#define CONFIG_SHARP_LQ084V1DG21" >>include/config.h
@@ -668,6 +688,9 @@ xtract_4xx = $(subst _25,,$(subst _33,,$(subst _BA,,$(subst _ME,,$(subst _HI,,$(
 ADCIOP_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx adciop esd

+APC405_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx apc405 esd
+
 AR405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx ar405 esd

@@ -680,13 +703,24 @@ BUBINGA405EP_config:	unconfig
 CANBT_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx canbt esd

-CATcenter_config:	unconfig
+CATcenter_config	\
+CATcenter_25_config	\
+CATcenter_33_config:	unconfig
 	@ echo "/* CATcenter uses PPChameleon Model ME */"  > include/config.h
 	@ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 1" >> include/config.h
+	@[ -z "$(findstring _25,$@)" ] || \
+		{ echo "#define CONFIG_PPCHAMELEON_CLK_25" >>include/config.h ; \
+		  echo "SysClk = 25MHz" ; \
+		}
+	@[ -z "$(findstring _33,$@)" ] || \
+		{ echo "#define CONFIG_PPCHAMELEON_CLK_33" >>include/config.h ; \
+		  echo "SysClk = 33MHz" ; \
+		}
 	@./mkconfig -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave

 CPCI405_config	\
 CPCI4052_config	\
+CPCI405DT_config	\
 CPCI405AB_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx cpci405 esd
 	@echo "BOARD_REVISION = $(@:_config=)"	>>include/config.mk
@@ -724,6 +758,12 @@ ERIC_config:	unconfig
 EXBITGEN_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx exbitgen

+G2000_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx g2000
+
+HH405_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx hh405 esd
+
 HUB405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx hub405 esd

@@ -771,31 +811,34 @@ PPChameleonEVB_BA_33_config	\
 PPChameleonEVB_ME_33_config	\
 PPChameleonEVB_HI_33_config:	unconfig
 	@ >include/config.h
-	@[ -z "$(findstring _MODEL_BA,$@)" ] || \
+	@[ -z "$(findstring EVB_BA,$@)" ] || \
 		{ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 0" >>include/config.h ; \
 		  echo "... BASIC model" ; \
 		}
-	@[ -z "$(findstring _MODEL_ME,$@)" ] || \
+	@[ -z "$(findstring EVB_ME,$@)" ] || \
 		{ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 1" >>include/config.h ; \
 		  echo "... MEDIUM model" ; \
 		}
-	@[ -z "$(findstring _MODEL_HI,$@)" ] || \
+	@[ -z "$(findstring EVB_HI,$@)" ] || \
 		{ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 2" >>include/config.h ; \
 		  echo "... HIGH-END model" ; \
 		}
 	@[ -z "$(findstring _25,$@)" ] || \
 		{ echo "#define CONFIG_PPCHAMELEON_CLK_25" >>include/config.h ; \
-		  echo " SysClk = 25MHz" ; \
+		  echo "SysClk = 25MHz" ; \
 		}
 	@[ -z "$(findstring _33,$@)" ] || \
 		{ echo "#define CONFIG_PPCHAMELEON_CLK_33" >>include/config.h ; \
-		  echo " SysClk = 33MHz" ; \
+		  echo "SysClk = 33MHz" ; \
 		}
 	@./mkconfig -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave

 VOH405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx voh405 esd

+VOM405_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx vom405 esd
+
 W7OLMC_config	\
 W7OLMG_config: unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx w7o
@@ -803,9 +846,21 @@ W7OLMG_config: unconfig
 WALNUT405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx walnut405

+WUH405_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx wuh405 esd
+
 XPEDITE1K_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx xpedite1k

+#########################################################################
+## MPC8220 Systems
+#########################################################################
+Alaska8220_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc8220 alaska
+
+Yukon8220_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc8220 yukon
+
 #########################################################################
 ## MPC824x Systems
 #########################################################################
@@ -1061,6 +1116,9 @@ M5272C3_config :		unconfig
 M5282EVB_config :		unconfig
 	@./mkconfig $(@:_config=) m68k mcf52x2 m5282evb

+TASREG_config :		unconfig
+	@./mkconfig $(@:_config=) m68k mcf52x2 tasreg esd
+
 #########################################################################
 ## MPC85xx Systems
 #########################################################################
@@ -1071,14 +1129,29 @@ MPC8540ADS_config:	unconfig
 MPC8560ADS_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc85xx mpc8560ads

-stxgp3_config:		unconfig
-	@./mkconfig $(@:_config=) ppc mpc85xx stxgp3
+MPC8541CDS_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc85xx mpc8541cds cds
+
+MPC8555CDS_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc85xx mpc8555cds cds
+
+sbc8540_config \
+sbc8540_33_config \
+sbc8540_66_config:	unconfig
+	@if [ "$(findstring _66_,$@)" ] ; then \
+		echo "#define CONFIG_PCI_66"	>>include/config.h ; \
+		echo "... 66 MHz PCI" ; \
+	else \
+		>include/config.h ; \
+		echo "... 33 MHz PCI" ; \
+	fi
+	@./mkconfig -a SBC8540 ppc mpc85xx sbc8560

 sbc8560_config \
 sbc8560_33_config \
 sbc8560_66_config:      unconfig
 	@if [ "$(findstring _66_,$@)" ] ; then \
-		echo "#define CONFIG_PCI_66"  >>include/config.h ; \
+		echo "#define CONFIG_PCI_66"	>>include/config.h ; \
 		echo "... 66 MHz PCI" ; \
 	else \
 		>include/config.h ; \
@@ -1086,6 +1159,9 @@ sbc8560_66_config:      unconfig
 	fi
 	@./mkconfig -a sbc8560 ppc mpc85xx sbc8560

+stxgp3_config:		unconfig
+	@./mkconfig $(@:_config=) ppc mpc85xx stxgp3
+
 #########################################################################
 ## 74xx/7xx Systems
 #########################################################################
@@ -1096,6 +1172,9 @@ AmigaOneG3SE_config:	unconfig
 BAB7xx_config: unconfig
 	@./mkconfig $(@:_config=) ppc 74xx_7xx bab7xx eltec

+CPCI750_config:        unconfig
+	@./mkconfig CPCI750 ppc 74xx_7xx cpci750 esd
+
 DB64360_config:  unconfig
 	@./mkconfig DB64360 ppc 74xx_7xx db64360 Marvell

@@ -1151,21 +1230,21 @@ xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,,$(subst _cs_autoboot,,$

 xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))

-integratorcp_config :	unconfig
-	@./mkconfig $(@:_config=) arm arm926ejs integratorcp
-
 integratorap_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm926ejs integratorap

+integratorcp_config :	unconfig
+	@./mkconfig $(@:_config=) arm arm926ejs integratorcp
+
 lpd7a400_config \
 lpd7a404_config:	unconfig
 	@./mkconfig $(@:_config=) arm lh7a40x lpd7a40x

 mx1ads_config	:	unconfig
-	@./mkconfig $(@:_config=) arm arm920t mx1ads
+	@./mkconfig $(@:_config=) arm arm920t mx1ads NULL imx

 mx1fs2_config	:	unconfig
-	@./mkconfig $(@:_config=) arm arm920t mx1fs2
+	@./mkconfig $(@:_config=) arm arm920t mx1fs2 NULL imx

 omap1510inn_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm925t omap1510inn
@@ -1206,13 +1285,13 @@ omap730p2_cs3boot_config :	unconfig
 	@./mkconfig -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2

 scb9328_config	:	unconfig
-	@./mkconfig $(@:_config=) arm arm920t scb9328
+	@./mkconfig $(@:_config=) arm arm920t scb9328 NULL imx

 smdk2400_config	:	unconfig
-	@./mkconfig $(@:_config=) arm arm920t smdk2400
+	@./mkconfig $(@:_config=) arm arm920t smdk2400 NULL s3c24x0

 smdk2410_config	:	unconfig
-	@./mkconfig $(@:_config=) arm arm920t smdk2410
+	@./mkconfig $(@:_config=) arm arm920t smdk2410 NULL s3c24x0

 SX1_config :		unconfig
 	@./mkconfig $(@:_config=) arm arm925t sx1
@@ -1240,10 +1319,10 @@ trab_old_config:	unconfig
 		  echo "... with 8 MB Flash, 16 MB RAM" ; \
 		  echo "TEXT_BASE = 0x0CF40000" >board/trab/config.tmp ; \
 		}
-	@./mkconfig -a $(call xtract_trab,$@) arm arm920t trab
+	@./mkconfig -a $(call xtract_trab,$@) arm arm920t trab NULL s3c24x0

 VCMA9_config	:	unconfig
-	@./mkconfig $(@:_config=) arm arm920t vcma9 mpl
+	@./mkconfig $(@:_config=) arm arm920t vcma9 mpl s3c24x0

 versatile_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm926ejs versatile
@@ -1278,6 +1357,9 @@ evb4510_config :	unconfig
 at91rm9200dk_config	:	unconfig
 	@./mkconfig $(@:_config=) arm at91rm9200 at91rm9200dk

+cmc_pu2_config	:	unconfig
+	@./mkconfig $(@:_config=) arm at91rm9200 cmc_pu2
+
 #########################################################################
 ## XScale Systems
 #########################################################################
@@ -1306,6 +1388,9 @@ logodl_config	:	unconfig
 wepep250_config	:	unconfig
 	@./mkconfig $(@:_config=) arm pxa wepep250

+xaeniax_config	:	unconfig
+	@./mkconfig $(@:_config=) arm pxa xaeniax
+
 xm250_config	:	unconfig
 	@./mkconfig $(@:_config=) arm pxa xm250

@@ -1449,6 +1534,15 @@ ADNPESC1_config: unconfig
 		}
 	@./mkconfig -a ADNPESC1 nios nios adnpesc1 ssv

+#########################################################################
+## Nios-II
+#########################################################################
+
+PK1C20_config : unconfig
+	@./mkconfig  PK1C20 nios2 nios2 pk1c20 psyent
+
+PCI5441_config : unconfig
+	@./mkconfig  PCI5441 nios2 nios2 pci5441 psyent

 #========================================================================
 # MicroBlaze
--- a/80
+++ b/80
@@ -25,9 +25,10 @@ Summary:
 ========

 This directory contains the source code for U-Boot, a boot loader for
-Embedded boards based on PowerPC and ARM processors, which can be
-installed in a boot ROM and used to initialize and test the hardware
-or to download and run application code.
+Embedded boards based on PowerPC, ARM, MIPS and several other
+processors, which can be installed in a boot ROM and used to
+initialize and test the hardware or to download and run application
+code.

 The development of U-Boot is closely related to Linux: some parts of
 the source code originate in the Linux source tree, we have some
@@ -122,23 +123,27 @@ Directory Hierarchy:
 - board		Board dependent files
 - common	Misc architecture independent functions
 - cpu		CPU specific files
-  - 74xx_7xx	Files specific to Motorola MPC74xx and 7xx CPUs
+  - 74xx_7xx	Files specific to Freescale MPC74xx and 7xx CPUs
  - arm720t	Files specific to ARM 720 CPUs
  - arm920t	Files specific to ARM 920 CPUs
+    - imx	Files specific to Freescale MC9328 i.MX CPUs
+    - s3c24x0	Files specific to Samsung S3C24X0 CPUs
  - arm925t	Files specific to ARM 925 CPUs
  - arm926ejs	Files specific to ARM 926 CPUs
  - at91rm9200	Files specific to Atmel AT91RM9200 CPUs
  - i386	Files specific to i386 CPUs
  - ixp		Files specific to Intel XScale IXP CPUs
-  - mcf52x2	Files specific to Motorola ColdFire MCF52x2 CPUs
+  - mcf52x2	Files specific to Freescale ColdFire MCF52x2 CPUs
  - mips	Files specific to MIPS CPUs
-  - mpc5xx	Files specific to Motorola MPC5xx  CPUs
-  - mpc5xxx	Files specific to Motorola MPC5xxx CPUs
-  - mpc8xx	Files specific to Motorola MPC8xx  CPUs
-  - mpc824x	Files specific to Motorola MPC824x CPUs
-  - mpc8260	Files specific to Motorola MPC8260 CPUs
-  - mpc85xx	Files specific to Motorola MPC85xx CPUs
+  - mpc5xx	Files specific to Freescale MPC5xx  CPUs
+  - mpc5xxx	Files specific to Freescale MPC5xxx CPUs
+  - mpc8xx	Files specific to Freescale MPC8xx  CPUs
+  - mpc8220	Files specific to Freescale MPC8220 CPUs
+  - mpc824x	Files specific to Freescale MPC824x CPUs
+  - mpc8260	Files specific to Freescale MPC8260 CPUs
+  - mpc85xx	Files specific to Freescale MPC85xx CPUs
  - nios	Files specific to Altera NIOS CPUs
+  - nios2	Files specific to Altera Nios-II CPUs
  - ppc4xx	Files specific to IBM PowerPC 4xx CPUs
  - pxa		Files specific to Intel XScale PXA CPUs
  - s3c44b0	Files specific to Samsung S3C44B0 CPUs
@@ -225,6 +230,7 @@ The following options need to be configured:
 		-------------------
 		CONFIG_MPC823,	CONFIG_MPC850,	CONFIG_MPC855,	CONFIG_MPC860
 	or	CONFIG_MPC5xx
+	or	CONFIG_MPC8220
 	or	CONFIG_MPC824X, CONFIG_MPC8260
 	or	CONFIG_MPC85xx
 	or	CONFIG_IOP480
@@ -244,6 +250,10 @@ The following options need to be configured:
 		----------------------
 		CONFIG_MICROBLAZE

+		Nios-2 based CPUs:
+		----------------------
+		CONFIG_NIOS2
+

 - Board Type:	Define exactly one of

@@ -304,6 +314,11 @@ The following options need to be configured:

 		CONFIG_SUZAKU

+		Nios-2 based boards:
+		------------------------
+
+		CONFIG_PCI5441 CONFIG_PK1C20
+

 - CPU Module Type: (if CONFIG_COGENT is defined)
 		Define exactly one of
@@ -339,16 +354,17 @@ The following options need to be configured:
 		CONFIG_MPC8240, CONFIG_MPC8245

 - 8xx CPU Options: (if using an MPC8xx cpu)
-		Define one or more of
-		CONFIG_8xx_GCLK_FREQ	- if get_gclk_freq() cannot work
+		CONFIG_8xx_GCLK_FREQ	- deprecated: CPU clock if
+					  get_gclk_freq() cannot work
 					  e.g. if there is no 32KHz
 					  reference PIT/RTC clock
+		CONFIG_8xx_OSCLK	- PLL input clock (either EXTCLK
+					  or XTAL/EXTAL)

- 859/866 CPU options: (if using a MPC859 or MPC866 CPU):
-		CFG_866_OSCCLK
-		CFG_866_CPUCLK_MIN
-		CFG_866_CPUCLK_MAX
-		CFG_866_CPUCLK_DEFAULT
+- 859/866/885 CPU options: (if using a MPC859 or MPC866 or MPC885 CPU):
+		CFG_8xx_CPUCLK_MIN
+		CFG_8xx_CPUCLK_MAX
+		CONFIG_8xx_CPUCLK_DEFAULT
 			See doc/README.MPC866

 		CFG_MEASURE_CPUCLK
@@ -358,7 +374,7 @@ The following options need to be configured:
 		values. Mostly useful for board bringup to make sure
 		the PLL is locked at the intended frequency. Note
 		that this requires a (stable) reference clock (32 kHz
-		RTC clock),
+		RTC clock or CFG_8XX_XIN)

 - Linux Kernel Interface:
 		CONFIG_CLOCKS_IN_MHZ
@@ -784,7 +800,7 @@ The following options need to be configured:
 		supported (PIP405, MIP405, MPC5200); define
 		CONFIG_USB_UHCI to enable it.
 		define CONFIG_USB_KEYBOARD to enable the USB Keyboard
-		end define CONFIG_USB_STORAGE to enable the USB
+		and define CONFIG_USB_STORAGE to enable the USB
 		storage devices.
 		Note:
 		Supported are USB Keyboards and USB Floppy drives
@@ -819,7 +835,7 @@ The following options need to be configured:
 		function struct part_info* jffs2_part_info(int part_num)

 		If you define only one JFFS2 partition you may also want to
-		#define CFG_JFFS_SINGLE_PART    1
+		#define CFG_JFFS_SINGLE_PART	1
 		to disable the command chpart. This is the default when you
 		have not defined a custom partition

@@ -1961,9 +1977,9 @@ Low Level (hardware related) configuration options:
 		source code. It is used to make hardware dependant
 		initializations.

- CFG_IMMR:	Physical address of the Internal Memory Mapped
-		Register; DO NOT CHANGE! (11-4)
-		[MPC8xx systems only]
+- CFG_IMMR:	Physical address of the Internal Memory.
+		DO NOT CHANGE unless you know exactly what you're
+		doing! (11-4) [MPC8xx/82xx systems only]

 - CFG_INIT_RAM_ADDR:

@@ -2097,6 +2113,20 @@ Low Level (hardware related) configuration options:
 		Add the "loopw" memory command. This only takes effect if
 		the memory commands are activated globally (CFG_CMD_MEM).

+- CONFIG_MX_CYCLIC
+		Add the "mdc" and "mwc" memory commands. These are cyclic
+		"md/mw" commands.
+		Examples:
+
+		=> mdc.b 10 4 500
+		This command will print 4 bytes (10,11,12,13) each 500 ms.
+
+		=> mwc.l 100 12345678 10
+		This command will write 12345678 to address 100 all 10 ms.
+
+		This only takes effect if the memory commands are activated
+		globally (CFG_CMD_MEM).
+
 Building the Software:
 ======================

@@ -2126,6 +2156,7 @@ configurations; the following names are supported:

 	ADCIOP_config		FPS860L_config		omap730p2_config
 	ADS860_config		GEN860T_config		pcu_e_config
+	Alaska8220_config
 	AR405_config		GENIETV_config		PIP405_config
 	at91rm9200dk_config	GTH_config		QS823_config
 	CANBT_config		hermes_config		QS850_config
@@ -2147,6 +2178,7 @@ configurations; the following names are supported:
 	FADS860T_config		omap1610inn_config	TQM855L_config
 	FPS850L_config		omap5912osk_config	TQM860L_config
 							WALNUT405_config
+							Yukon8220_config
 							ZPC1900_config

 Note: for some board special configuration names may exist; check if
--- a/board/alaska/Makefile
+++ b/board/alaska/Makefile
@@ -0,0 +1,45 @@
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o flash.o extserial.o serial.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/alaska/alaska.c
+++ b/board/alaska/alaska.c
@@ -0,0 +1,153 @@
+/*
+ * (C) Copyright 2004, Freescale Inc.
+ * TsiChung Liew, Tsi-Chung.Liew@freescale.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8220.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+
+void setupBat (ulong size)
+{
+	ulong batu, batl;
+	int blocksize = 0;
+
+	/* Flash 0 */
+#if defined (CFG_AMD_BOOT)
+	batu = CFG_FLASH0_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
+#else
+	batu = CFG_FLASH0_BASE | (BL_16M << 2) | BPP_RW | BPP_RX;
+#endif
+	batl = CFG_FLASH0_BASE | 0x22;
+	write_bat (IBAT0, batu, batl);
+	write_bat (DBAT0, batu, batl);
+
+	/* Flash 1 */
+#if defined (CFG_AMD_BOOT)
+	batu = CFG_FLASH1_BASE | (BL_16M << 2) | BPP_RW | BPP_RX;
+#else
+	batu = CFG_FLASH1_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
+#endif
+	batl = CFG_FLASH1_BASE | 0x22;
+	write_bat (IBAT1, batu, batl);
+	write_bat (DBAT1, batu, batl);
+
+	/* CPLD */
+	batu = CFG_CPLD_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
+	batl = CFG_CPLD_BASE | 0x22;
+	write_bat (IBAT2, 0, 0);
+	write_bat (DBAT2, batu, batl);
+
+	/* FPGA */
+	batu = CFG_FPGA_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
+	batl = CFG_FPGA_BASE | 0x22;
+	write_bat (IBAT3, 0, 0);
+	write_bat (DBAT3, batu, batl);
+
+	/* MBAR - Data only */
+	batu = CFG_MBAR | BPP_RW | BPP_RX;
+	batl = CFG_MBAR | 0x22;
+	mtspr (IBAT4L, 0);
+	mtspr (IBAT4U, 0);
+	mtspr (DBAT4L, batl);
+	mtspr (DBAT4U, batu);
+
+	/* MBAR - SRAM */
+	batu = CFG_SRAM_BASE | BPP_RW | BPP_RX;
+	batl = CFG_SRAM_BASE | 0x42;
+	mtspr (IBAT5L, batl);
+	mtspr (IBAT5U, batu);
+	mtspr (DBAT5L, batl);
+	mtspr (DBAT5U, batu);
+
+	if (size <= 0x800000)	/* 8MB */
+		blocksize = BL_8M << 2;
+	else if (size <= 0x1000000)	/* 16MB */
+		blocksize = BL_16M << 2;
+	else if (size <= 0x2000000)	/* 32MB */
+		blocksize = BL_32M << 2;
+	else if (size <= 0x4000000)	/* 64MB */
+		blocksize = BL_64M << 2;
+	else if (size <= 0x8000000)	/* 128MB */
+		blocksize = BL_128M << 2;
+	else if (size <= 0x10000000)	/* 256MB */
+		blocksize = BL_256M << 2;
+
+	/* Memory */
+	batu = CFG_SDRAM_BASE | blocksize | BPP_RW | BPP_RX;
+	batl = CFG_SDRAM_BASE | 0x42;
+	mtspr (IBAT6L, batl);
+	mtspr (IBAT6U, batu);
+	mtspr (DBAT6L, batl);
+	mtspr (DBAT6U, batu);
+
+	/* memory size is less than 256MB */
+	if (size <= 0x10000000) {
+		/* Nothing */
+		batu = 0;
+		batl = 0;
+	} else {
+		size -= 0x10000000;
+		if (size <= 0x800000)	/* 8MB */
+			blocksize = BL_8M << 2;
+		else if (size <= 0x1000000)	/* 16MB */
+			blocksize = BL_16M << 2;
+		else if (size <= 0x2000000)	/* 32MB */
+			blocksize = BL_32M << 2;
+		else if (size <= 0x4000000)	/* 64MB */
+			blocksize = BL_64M << 2;
+		else if (size <= 0x8000000)	/* 128MB */
+			blocksize = BL_128M << 2;
+		else if (size <= 0x10000000)	/* 256MB */
+			blocksize = BL_256M << 2;
+
+		batu = (CFG_SDRAM_BASE +
+			0x10000000) | blocksize | BPP_RW | BPP_RX;
+		batl = (CFG_SDRAM_BASE + 0x10000000) | 0x42;
+	}
+
+	mtspr (IBAT7L, batl);
+	mtspr (IBAT7U, batu);
+	mtspr (DBAT7L, batl);
+	mtspr (DBAT7U, batu);
+}
+
+long int initdram (int board_type)
+{
+	ulong size;
+
+	size = dramSetup ();
+
+/* if iCache ad dCache is defined */
+#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
+/*    setupBat(size);*/
+#endif
+
+	return size;
+}
+
+int checkboard (void)
+{
+	puts ("Board: Alaska MPC8220 Evaluation Board\n");
+
+	return 0;
+}
--- a/board/alaska/config.mk
+++ b/board/alaska/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# alaska board
+#
+
+TEXT_BASE = 0xfff00000
+# TEXT_BASE = 0x00100000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
--- a/board/alaska/extserial.c
+++ b/board/alaska/extserial.c
@@ -0,0 +1,110 @@
+/*
+ * (C) Copyright 2004, Freescale, Inc
+ * TsiChung Liew, Tsi-Chung.Liew@freescale.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * Minimal serial functions needed to use one of the PSC ports
+ * as serial console interface.
+ */
+
+#include <common.h>
+#include <mpc8220.h>
+
+#if defined (CONFIG_EXTUART_CONSOLE)
+#   include <ns16550.h>
+
+#   define PADSERIAL_BAUD_115200   0x40
+#   define PADSERIAL_BAUD_57600    0x20
+#   define PADSERIAL_BAUD_9600     0
+#   define PADCARD_FREQ            18432000
+
+const NS16550_t com_port = (NS16550_t) CFG_NS16550_COM1;
+
+int ext_serial_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	volatile u8 *dipswitch = (volatile u8 *) (CFG_CPLD_BASE + 0x1002);
+	int baud_divisor;
+
+	/* Find out the baud rate speed on debug card dip switches */
+	if (*dipswitch & PADSERIAL_BAUD_115200)
+		gd->baudrate = 115200;
+	else if (*dipswitch & PADSERIAL_BAUD_57600)
+		gd->baudrate = 57600;
+	else
+		gd->baudrate = 9600;
+
+	/* Debug card frequency */
+	baud_divisor = PADCARD_FREQ / (16 * gd->baudrate);
+
+	NS16550_init (com_port, baud_divisor);
+
+	return (0);
+}
+
+void ext_serial_putc (const char c)
+{
+	if (c == '\n')
+		NS16550_putc (com_port, '\r');
+
+	NS16550_putc (com_port, c);
+}
+
+void ext_serial_puts (const char *s)
+{
+	while (*s) {
+		serial_putc (*s++);
+	}
+}
+
+int ext_serial_getc (void)
+{
+	return NS16550_getc (com_port);
+}
+
+int ext_serial_tstc (void)
+{
+	return NS16550_tstc (com_port);
+}
+
+void ext_serial_setbrg (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	volatile u8 *dipswitch = (volatile u8 *) (CFG_CPLD_BASE + 0x1002);
+	int baud_divisor;
+
+	/* Find out the baud rate speed on debug card dip switches */
+	if (*dipswitch & PADSERIAL_BAUD_115200)
+		gd->baudrate = 115200;
+	else if (*dipswitch & PADSERIAL_BAUD_57600)
+		gd->baudrate = 57600;
+	else
+		gd->baudrate = 9600;
+
+	/* Debug card frequency */
+	baud_divisor = PADCARD_FREQ / (16 * gd->baudrate);
+
+	NS16550_reinit (com_port, baud_divisor);
+}
+#endif /* CONFIG_EXTUART_CONSOLE */
--- a/board/alaska/flash.c
+++ b/board/alaska/flash.c
@@ -0,0 +1,807 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH8
+
+typedef unsigned char FLASH_PORT_WIDTH;
+typedef volatile unsigned char FLASH_PORT_WIDTHV;
+
+#define SWAP(x)         (x)
+
+/* Intel-compatible flash ID */
+#define INTEL_COMPAT    0x89
+#define INTEL_ALT       0xB0
+
+/* Intel-compatible flash commands */
+#define INTEL_PROGRAM   0x10
+#define INTEL_ERASE     0x20
+#define INTEL_CLEAR     0x50
+#define INTEL_LOCKBIT   0x60
+#define INTEL_PROTECT   0x01
+#define INTEL_STATUS    0x70
+#define INTEL_READID    0x90
+#define INTEL_CONFIRM   0xD0
+#define INTEL_RESET     0xFF
+
+/* Intel-compatible flash status bits */
+#define INTEL_FINISHED  0x80
+#define INTEL_OK        0x80
+
+#define FPW             FLASH_PORT_WIDTH
+#define FPWV            FLASH_PORT_WIDTHV
+
+#define FLASH_CYCLE1    0x0555
+#define FLASH_CYCLE2    0x02aa
+
+#define WR_BLOCK        0x20
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static int write_data_block (flash_info_t * info, ulong src, ulong dest);
+static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+	ulong fsize = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		memset (&flash_info[i], 0, sizeof (flash_info_t));
+
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) CFG_FLASH1_BASE,
+					&flash_info[i]);
+			flash_get_offsets (CFG_FLASH1_BASE, &flash_info[i]);
+			break;
+		case 1:
+			flash_get_size ((FPW *) CFG_FLASH1_BASE,
+					&flash_info[i]);
+			fsize = CFG_FLASH1_BASE + flash_info[i - 1].size;
+			flash_get_offsets (fsize, &flash_info[i]);
+			break;
+		case 2:
+			flash_get_size ((FPW *) CFG_FLASH0_BASE,
+					&flash_info[i]);
+			flash_get_offsets (CFG_FLASH0_BASE, &flash_info[i]);
+			break;
+		case 3:
+			flash_get_size ((FPW *) CFG_FLASH0_BASE,
+					&flash_info[i]);
+			fsize = CFG_FLASH0_BASE + flash_info[i - 1].size;
+			flash_get_offsets (fsize, &flash_info[i]);
+			break;
+		default:
+			panic ("configured to many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+#if defined (CFG_AMD_BOOT)
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_MONITOR_BASE,
+		       CFG_MONITOR_BASE + monitor_flash_len - 1,
+		       &flash_info[2]);
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_INTEL_BASE,
+		       CFG_INTEL_BASE + monitor_flash_len - 1,
+		       &flash_info[1]);
+#else
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_MONITOR_BASE,
+		       CFG_MONITOR_BASE + monitor_flash_len - 1,
+		       &flash_info[3]);
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_AMD_BASE,
+		       CFG_AMD_BASE + monitor_flash_len - 1, &flash_info[0]);
+#endif
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV1_ADDR,
+		       CFG_ENV1_ADDR + CFG_ENV1_SIZE - 1, &flash_info[1]);
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[3]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return;
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_AMD_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_INTEL_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+
+	case FLASH_AM040:
+		printf ("AMD29F040B\n");
+		break;
+
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+	FPWV value;
+	static int amd = 0;
+
+	/* Write auto select command: read Manufacturer ID */
+	/* Write auto select command sequence and test FLASH answer */
+	addr[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* for AMD, Intel ignores this */
+	__asm__ ("sync");
+	addr[FLASH_CYCLE2] = (FPW) 0x00550055;	/* for AMD, Intel ignores this */
+	__asm__ ("sync");
+	addr[FLASH_CYCLE1] = (FPW) 0x00900090;	/* selects Intel or AMD */
+	__asm__ ("sync");
+
+	udelay (100);
+
+	switch (addr[0] & 0xff) {
+
+	case (uchar) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		value = addr[1];
+		break;
+
+	case (uchar) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		value = addr[2];
+		break;
+
+	default:
+		printf ("unknown\n");
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);	/* no or unknown flash  */
+	}
+
+	switch (value) {
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;	/* => 16 MB     */
+		break;
+
+	case (FPW) AMD_ID_LV040B:
+		info->flash_id += FLASH_AM040;
+		if (amd == 0) {
+			info->sector_count = 7;
+			info->size = 0x00070000;	/* => 448 KB     */
+			amd = 1;
+		} else {
+			/* for Environment settings */
+			info->sector_count = 1;
+			info->size = PHYS_AMD_SECT_SIZE;	/* => 64 KB     */
+			amd = 0;
+		}
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	if (value == (FPW) INTEL_ID_28F128J3A)
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+	else
+		addr[0] = (FPW) 0x00F000F0;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0, intel = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN)
+			printf ("- missing\n");
+		else
+			printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		type = (info->flash_id & FLASH_VENDMASK);
+		if ((type != FLASH_MAN_AMD)) {
+			printf ("Can't erase unknown flash type %08lx - aborted\n",
+				info->flash_id);
+			return 1;
+		}
+	}
+
+	if (type == FLASH_MAN_INTEL)
+		intel = 1;
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			start = get_timer (0);
+
+			if (intel) {
+				*addr = (FPW) 0x00500050;	/* clear status register */
+				*addr = (FPW) 0x00200020;	/* erase setup */
+				*addr = (FPW) 0x00D000D0;	/* erase confirm */
+			} else {
+				FPWV *base;	/* first address in bank */
+
+				base = (FPWV *) (CFG_AMD_BASE);
+				base[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* unlock */
+				base[FLASH_CYCLE2] = (FPW) 0x00550055;	/* unlock */
+				base[FLASH_CYCLE1] = (FPW) 0x00800080;	/* erase mode */
+				base[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* unlock */
+				base[FLASH_CYCLE2] = (FPW) 0x00550055;	/* unlock */
+				*addr = (FPW) 0x00300030;	/* erase sector */
+			}
+
+			while (((status =
+				 *addr) & (FPW) 0x00800080) !=
+			       (FPW) 0x00800080) {
+				if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					if (intel) {
+						*addr = (FPW) 0x00B000B0;	/* suspend erase     */
+						*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+					} else
+						*addr = (FPW) 0x00F000F0;	/* reset to read mode */
+
+					rcode = 1;
+					break;
+				}
+			}
+
+			if (intel) {
+				*addr = (FPW) 0x00500050;	/* clear status register cmd.   */
+				*addr = (FPW) 0x00FF00FF;	/* resest to read mode          */
+			} else
+				*addr = (FPW) 0x00F000F0;	/* reset to read mode */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+	    {
+		FPW data = 0;	/* 16 or 32 bit word, matches flash bus width */
+		int bytes;	/* number of bytes to program in current word */
+		int left;	/* number of bytes left to program */
+		int i, res;
+
+		for (left = cnt, res = 0;
+		     left > 0 && res == 0;
+		     addr += sizeof (data), left -=
+		     sizeof (data) - bytes) {
+
+			bytes = addr & (sizeof (data) - 1);
+			addr &= ~(sizeof (data) - 1);
+
+			/* combine source and destination data so can program
+			 * an entire word of 16 or 32 bits
+			 */
+			for (i = 0; i < sizeof (data); i++) {
+				data <<= 8;
+				if (i < bytes || i - bytes >= left)
+					data += *((uchar *) addr + i);
+				else
+					data += *src++;
+			}
+
+			res = write_word_amd (info, (FPWV *) addr,
+					      data);
+		}
+		return res;
+	    }		/* case FLASH_MAN_AMD */
+
+	case FLASH_MAN_INTEL:
+	    {
+		ulong cp, wp;
+		FPW data;
+		int count, i, l, rc, port_width;
+
+		/* get lower word aligned address */
+		wp = addr;
+		port_width = 1;
+
+		/*
+		 * handle unaligned start bytes
+		 */
+		if ((l = addr - wp) != 0) {
+			data = 0;
+			for (i = 0, cp = wp; i < l; ++i, ++cp) {
+				data = (data << 8) | (*(uchar *) cp);
+			}
+
+			for (; i < port_width && cnt > 0; ++i) {
+				data = (data << 8) | *src++;
+				--cnt;
+				++cp;
+			}
+
+			for (; cnt == 0 && i < port_width; ++i, ++cp)
+				data = (data << 8) | (*(uchar *) cp);
+
+			if ((rc =
+			     write_data (info, wp, SWAP (data))) != 0)
+				return (rc);
+			wp += port_width;
+		}
+
+		if (cnt > WR_BLOCK) {
+			/*
+			 * handle word aligned part
+			 */
+			count = 0;
+			while (cnt >= WR_BLOCK) {
+
+				if ((rc =
+				     write_data_block (info,
+						       (ulong) src,
+						       wp)) != 0)
+					return (rc);
+
+				wp += WR_BLOCK;
+				src += WR_BLOCK;
+				cnt -= WR_BLOCK;
+
+				if (count++ > 0x800) {
+					spin_wheel ();
+					count = 0;
+				}
+			}
+		}
+
+		if (cnt < WR_BLOCK) {
+			/*
+			 * handle word aligned part
+			 */
+			count = 0;
+			while (cnt >= port_width) {
+				data = 0;
+				for (i = 0; i < port_width; ++i)
+					data = (data << 8) | *src++;
+
+				if ((rc =
+				     write_data (info, wp,
+						 SWAP (data))) != 0)
+					return (rc);
+
+				wp += port_width;
+				cnt -= port_width;
+				if (count++ > 0x800) {
+					spin_wheel ();
+					count = 0;
+				}
+			}
+		}
+
+		if (cnt == 0)
+			return (0);
+
+		/*
+		 * handle unaligned tail bytes
+		 */
+		data = 0;
+		for (i = 0, cp = wp; i < port_width && cnt > 0;
+		     ++i, ++cp) {
+			data = (data << 8) | *src++;
+			--cnt;
+		}
+
+		for (; i < port_width; ++i, ++cp)
+			data = (data << 8) | (*(uchar *) cp);
+
+		return (write_data (info, wp, SWAP (data)));
+	    }		/* case FLASH_MAN_INTEL */
+
+	}			/* switch */
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	start = get_timer (0);
+
+	/* wait while polling the status register */
+	while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data_block (flash_info_t * info, ulong src, ulong dest)
+{
+	FPWV *srcaddr = (FPWV *) src;
+	FPWV *dstaddr = (FPWV *) dest;
+	ulong start;
+	int flag, i;
+
+	/* Check if Flash is (sufficiently) erased */
+	for (i = 0; i < WR_BLOCK; i++)
+		if ((*dstaddr++ & 0xff) != 0xff) {
+			printf ("not erased at %08lx (%lx)\n",
+				(ulong) dstaddr, *dstaddr);
+			return (2);
+		}
+
+	dstaddr = (FPWV *) dest;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*dstaddr = (FPW) 0x00e800e8;	/* write block setup */
+
+	/* arm simple, non interrupt dependent timer */
+	start = get_timer (0);
+
+	/* wait while polling the status register */
+	while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			*dstaddr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*dstaddr = (FPW) 0x001f001f;	/* write 32 to buffer */
+	for (i = 0; i < WR_BLOCK; i++)
+		*dstaddr++ = *srcaddr++;
+
+	dstaddr -= 1;
+	*dstaddr = (FPW) 0x00d000d0;	/* write 32 to buffer */
+
+	/* arm simple, non interrupt dependent timer */
+	start = get_timer (0);
+
+	/* wait while polling the status register */
+	while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			*dstaddr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*dstaddr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data)
+{
+	ulong start;
+	int flag;
+	int res = 0;		/* result, assume success */
+	FPWV *base;		/* first address in flash bank */
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+	base = (FPWV *) (CFG_AMD_BASE);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	base[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* unlock */
+	base[FLASH_CYCLE2] = (FPW) 0x00550055;	/* unlock */
+	base[FLASH_CYCLE1] = (FPW) 0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data */
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	start = get_timer (0);
+
+	/* data polling for D7 */
+	while (res == 0
+	       && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			*dest = (FPW) 0x00F000F0;	/* reset bank */
+			res = 1;
+		}
+	}
+
+	return (res);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Set/Clear sector's lock bit, returns:
+ * 0 - OK
+ * 1 - Error (timeout, voltage problems, etc.)
+ */
+int flash_real_protect (flash_info_t * info, long sector, int prot)
+{
+	ulong start;
+	int i;
+	int rc = 0;
+	FPWV *addr = (FPWV *) (info->start[sector]);
+	int flag = disable_interrupts ();
+
+	/*
+	 * 29F040B AMD flash does not support software protection/unprotection,
+	 * the only way to protect the AMD flash is marked it as prot bit.
+	 * This flash only support hardware protection, by supply or not supply
+	 * 12vpp to the flash
+	 */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
+		info->protect[sector] = prot;
+
+		return 0;
+	}
+
+	*addr = INTEL_CLEAR;	/* Clear status register    */
+	if (prot) {		/* Set sector lock bit      */
+		*addr = INTEL_LOCKBIT;	/* Sector lock bit          */
+		*addr = INTEL_PROTECT;	/* set                      */
+	} else {		/* Clear sector lock bit    */
+		*addr = INTEL_LOCKBIT;	/* All sectors lock bits    */
+		*addr = INTEL_CONFIRM;	/* clear                    */
+	}
+
+	start = get_timer (0);
+
+	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
+		if (get_timer (start) > CFG_FLASH_UNLOCK_TOUT) {
+			printf ("Flash lock bit operation timed out\n");
+			rc = 1;
+			break;
+		}
+	}
+
+	if (*addr != INTEL_OK) {
+		printf ("Flash lock bit operation failed at %08X, CSR=%08X\n",
+			(uint) addr, (uint) * addr);
+		rc = 1;
+	}
+
+	if (!rc)
+		info->protect[sector] = prot;
+
+	/*
+	 * Clear lock bit command clears all sectors lock bits, so
+	 * we have to restore lock bits of protected sectors.
+	 */
+	if (!prot) {
+		for (i = 0; i < info->sector_count; i++) {
+			if (info->protect[i]) {
+				start = get_timer (0);
+				addr = (FPWV *) (info->start[i]);
+				*addr = INTEL_LOCKBIT;	/* Sector lock bit  */
+				*addr = INTEL_PROTECT;	/* set              */
+				while ((*addr & INTEL_FINISHED) !=
+				       INTEL_FINISHED) {
+					if (get_timer (start) >
+					    CFG_FLASH_UNLOCK_TOUT) {
+						printf ("Flash lock bit operation timed out\n");
+						rc = 1;
+						break;
+					}
+				}
+			}
+		}
+	}
+
+	if (flag)
+		enable_interrupts ();
+
+	*addr = INTEL_RESET;	/* Reset to read array mode */
+
+	return rc;
+}
--- a/board/alaska/serial.c
+++ b/board/alaska/serial.c
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2004, Freescale, Inc
+ * TsiChung Liew, Tsi-Chung.Liew@freescale.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * Minimal serial functions needed to use one of the PSC ports
+ * as serial console interface.
+ */
+
+#include <common.h>
+#include <mpc8220.h>
+
+int serial_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+#if defined (CONFIG_EXTUART_CONSOLE)
+	volatile uchar *cpld = (volatile uchar *) CFG_CPLD_BASE;
+#endif
+
+	/* Check CPLD Switch 2 whether is external or internal */
+#if defined (CONFIG_EXTUART_CONSOLE)
+	if ((*cpld & 0x02) == 0x02) {
+		gd->bExtUart = 1;
+		return ext_serial_init ();
+	} else
+#endif
+	{
+#if defined(CONFIG_PSC_CONSOLE)
+		gd->bExtUart = 0;
+		return psc_serial_init ();
+#endif
+	}
+
+	return (0);
+}
+
+void serial_putc (const char c)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	if (gd->bExtUart) {
+#if defined (CONFIG_EXTUART_CONSOLE)
+		ext_serial_putc (c);
+#endif
+	} else {
+#if defined(CONFIG_PSC_CONSOLE)
+		psc_serial_putc (c);
+#endif
+	}
+}
+
+void serial_puts (const char *s)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	if (gd->bExtUart) {
+#if defined (CONFIG_EXTUART_CONSOLE)
+		ext_serial_puts (s);
+#endif
+	} else {
+#if defined(CONFIG_PSC_CONSOLE)
+		psc_serial_puts (s);
+#endif
+	}
+}
+
+int serial_getc (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	if (gd->bExtUart) {
+#if defined (CONFIG_EXTUART_CONSOLE)
+		return ext_serial_getc ();
+#endif
+	} else {
+#if defined(CONFIG_PSC_CONSOLE)
+		return psc_serial_getc ();
+#endif
+	}
+}
+
+int serial_tstc (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	if (gd->bExtUart) {
+#if defined (CONFIG_EXTUART_CONSOLE)
+		return ext_serial_tstc ();
+#endif
+	} else {
+#if defined(CONFIG_PSC_CONSOLE)
+		return psc_serial_tstc ();
+#endif
+	}
+}
+
+void serial_setbrg (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	if (gd->bExtUart) {
+#if defined (CONFIG_EXTUART_CONSOLE)
+		ext_serial_setbrg ();
+#endif
+	} else {
+#if defined(CONFIG_PSC_CONSOLE)
+		psc_serial_setbrg ();
+#endif
+	}
+}
--- a/board/alaska/u-boot.lds
+++ b/board/alaska/u-boot.lds
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8220/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
--- a/board/assabet/assabet.c
+++ b/board/assabet/assabet.c
@@ -101,7 +101,7 @@ board_init(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;

-	gd->bd->bi_arch_number = 25;	/* Intel Assabet Board */
+	gd->bd->bi_arch_number = MACH_TYPE_ASSABET;
 	gd->bd->bi_boot_params = 0xc0000100;

 	neponset_init();
--- a/board/at91rm9200dk/Makefile
+++ b/board/at91rm9200dk/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a

 OBJS	:= at91rm9200dk.o at45.o dm9161.o flash.o
-SOBJS	:=
+SOBJS	:= memsetup.o

 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)
--- a/board/at91rm9200dk/at91rm9200dk.c
+++ b/board/at91rm9200dk/at91rm9200dk.c
@@ -45,7 +45,7 @@ int board_init (void)
 	/* so we do _nothing_ here */

 	/* arch number of AT91RM9200DK-Board */
-	gd->bd->bi_arch_number = 251;
+	gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200;
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

--- a/board/at91rm9200dk/config.mk
+++ b/board/at91rm9200dk/config.mk
@@ -1 +1 @@
-TEXT_BASE = 0x21f80000
+TEXT_BASE = 0x21f00000
--- a/board/at91rm9200dk/memsetup.S
+++ b/board/at91rm9200dk/memsetup.S
@@ -0,0 +1,200 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *		       Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the at91rm9200dk board by
+ * (C) Copyright 2004
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#ifdef CONFIG_BOOTBINFUNC
+/*
+ * some parameters for the board
+ *
+ * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in
+ * turn is based on the boot.bin code from ATMEL
+ *
+ */
+
+/* flash */
+#define MC_PUIA 0xFFFFFF10
+#define MC_PUIA_VAL 0x00000000
+#define MC_PUP 0xFFFFFF50
+#define MC_PUP_VAL 0x00000000
+#define MC_PUER 0xFFFFFF54
+#define MC_PUER_VAL 0x00000000
+#define MC_ASR 0xFFFFFF04
+#define MC_ASR_VAL 0x00000000
+#define MC_AASR 0xFFFFFF08
+#define MC_AASR_VAL 0x00000000
+#define EBI_CFGR 0xFFFFFF64
+#define EBI_CFGR_VAL 0x00000000
+#define SMC2_CSR 0xFFFFFF70
+#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
+
+/* clocks */
+#define PLLAR 0xFFFFFC28
+#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
+#define PLLBR 0xFFFFFC2C
+#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
+#define MCKR 0xFFFFFC30
+#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
+
+/* sdram */
+#define PIOC_ASR 0xFFFFF870
+#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define PIOC_BSR 0xFFFFF874
+#define PIOC_BSR_VAL 0x00000000
+#define PIOC_PDR 0xFFFFF804
+#define PIOC_PDR_VAL 0xFFFF0000
+#define EBI_CSA 0xFFFFFF60
+#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
+#define SDRC_CR 0xFFFFFF98
+#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */
+#define SDRAM 0x20000000 /* address of the SDRAM */
+#define SDRAM1 0x20000080 /* address of the SDRAM */
+#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
+#define SDRC_MR 0xFFFFFF90
+#define SDRC_MR_VAL 0x00000002 /* Precharge All */
+#define SDRC_MR_VAL1 0x00000004 /* refresh */
+#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
+#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
+#define SDRC_TR 0xFFFFFF94
+#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
+
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+.globl lowlevelinit
+lowlevelinit:
+	/* memory control configuration */
+	/* this isn't very elegant, but	 what the heck */
+	ldr	r0, =SMRDATA
+	ldr	r1, _TEXT_BASE
+	sub	r0, r0, r1
+	add	r2, r0, #80
+0:
+	/* the address */
+	ldr	r1, [r0], #4
+	/* the value */
+	ldr	r3, [r0], #4
+	str	r3, [r1]
+	cmp	r2, r0
+	bne	0b
+	/* delay - this is all done by guess */
+	ldr	r0, =0x00010000
+1:
+	subs	r0, r0, #1
+	bhi	1b
+	ldr	r0, =SMRDATA1
+	ldr	r1, _TEXT_BASE
+	sub	r0, r0, r1
+	add	r2, r0, #176
+2:
+	/* the address */
+	ldr	r1, [r0], #4
+	/* the value */
+	ldr	r3, [r0], #4
+	str	r3, [r1]
+	cmp	r2, r0
+	bne	2b
+
+	/* everything is fine now */
+	mov	pc, lr
+
+	.ltorg
+
+SMRDATA:
+	.word MC_PUIA
+	.word MC_PUIA_VAL
+	.word MC_PUP
+	.word MC_PUP_VAL
+	.word MC_PUER
+	.word MC_PUER_VAL
+	.word MC_ASR
+	.word MC_ASR_VAL
+	.word MC_AASR
+	.word MC_AASR_VAL
+	.word EBI_CFGR
+	.word EBI_CFGR_VAL
+	.word SMC2_CSR
+	.word SMC2_CSR_VAL
+	.word PLLAR
+	.word PLLAR_VAL
+	.word PLLBR
+	.word PLLBR_VAL
+	.word MCKR
+	.word MCKR_VAL
+	/* SMRDATA is 80 bytes long */
+	/* here there's a delay of 100 */
+SMRDATA1:
+	.word PIOC_ASR
+	.word PIOC_ASR_VAL
+	.word PIOC_BSR
+	.word PIOC_BSR_VAL
+	.word PIOC_PDR
+	.word PIOC_PDR_VAL
+	.word EBI_CSA
+	.word EBI_CSA_VAL
+	.word SDRC_CR
+	.word SDRC_CR_VAL
+	.word SDRC_MR
+	.word SDRC_MR_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRC_MR
+	.word SDRC_MR_VAL1
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRC_MR
+	.word SDRC_MR_VAL2
+	.word SDRAM1
+	.word SDRAM_VAL
+	.word SDRC_TR
+	.word SDRC_TR_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRC_MR
+	.word SDRC_MR_VAL3
+	.word SDRAM
+	.word SDRAM_VAL
+	/* SMRDATA1 is 176 bytes long */
+#endif /* CONFIG_BOOTBINFUNC */
--- a/board/cds/common/cadmus.c
+++ b/board/cds/common/cadmus.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+
+
+/*
+ * CADMUS Board System Registers
+ */
+#ifndef CFG_CADMUS_BASE_REG
+#define CFG_CADMUS_BASE_REG	(CADMUS_BASE_ADDR + 0x4000)
+#endif
+
+typedef struct cadmus_reg {
+    u_char cm_ver;		/* Board version */
+    u_char cm_csr;		/* General control/status */
+    u_char cm_rst;		/* Reset control */
+    u_char cm_hsclk;		/* High speed clock */
+    u_char cm_hsxclk;		/* High speed clock extended */
+    u_char cm_led;		/* LED data */
+    u_char cm_pci;		/* PCI control/status */
+    u_char cm_dma;		/* DMA control */
+    u_char cm_reserved[248];	/* Total 256 bytes */
+} cadmus_reg_t;
+
+
+unsigned int
+get_board_version(void)
+{
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
+
+	return cadmus->cm_ver;
+}
+
+
+unsigned long
+get_clock_freq(void)
+{
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
+
+	uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */
+
+	if (pci1_speed == 0) {
+		return 33000000;
+	} else if (pci1_speed == 1) {
+		return 66000000;
+	} else {
+		/* Really, unknown. Be safe? */
+		return 33000000;
+	}
+}
+
+
+unsigned int
+get_pci_slot(void)
+{
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
+
+	/*
+	 * PCI slot in USER bits CSR[6:7] by convention.
+	 */
+	return ((cadmus->cm_csr >> 6) & 0x3) + 1;
+}
+
+
+unsigned int
+get_pci_dual(void)
+{
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
+
+	/*
+	 * PCI DUAL in CM_PCI[3]
+	 */
+	return cadmus->cm_pci & 0x10;
+}
--- a/board/cds/common/cadmus.h
+++ b/board/cds/common/cadmus.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CADMUS_H_
+#define __CADMUS_H_
+
+
+/*
+ * CADMUS Board System Register interface.
+ */
+
+/*
+ * Returns board version register.
+ */
+extern unsigned int get_board_version(void);
+
+/*
+ * Returns either 33000000 or 66000000 as the SYS_CLK_FREQ.
+ */
+extern unsigned long get_clock_freq(void);
+
+
+/*
+ * Returns 1 - 4, as found in the USER CSR[6:7] bits.
+ */
+extern unsigned int get_pci_slot(void);
+
+
+/*
+ * Returns PCI DUAL as found in CM_PCI[3].
+ */
+extern unsigned int get_pci_dual(void);
+
+
+#endif	/* __CADMUS_H_ */
--- a/board/cds/common/eeprom.c
+++ b/board/cds/common/eeprom.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <i2c.h>
+
+#include "eeprom.h"
+
+
+typedef struct {
+	char idee_pcbid[4];		/* "CCID" for CDC v1.X */
+	u8 idee_major;
+	u8 idee_minor;
+	char idee_serial[10];
+	char idee_errata[2];
+	char idee_date[8];		/* yyyymmdd */
+	/* The rest of the EEPROM space is reserved */
+} id_eeprom_t;
+
+
+unsigned int
+get_cpu_board_revision(void)
+{
+	uint major = 0;
+	uint minor = 0;
+
+	id_eeprom_t id_eeprom;
+
+	i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2,
+		 (uchar *) &id_eeprom, sizeof(id_eeprom));
+
+	major = id_eeprom.idee_major;
+	minor = id_eeprom.idee_minor;
+
+	if (major == 0xff && minor == 0xff) {
+		major = minor = 0;
+	}
+
+	return MPC85XX_CPU_BOARD_REV(major,minor);
+}
--- a/board/cds/common/eeprom.h
+++ b/board/cds/common/eeprom.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __EEPROM_H_
+#define __EEPROM_H_
+
+
+/*
+ * EEPROM Board System Register interface.
+ */
+
+
+/*
+ * CPU Board Revision
+ */
+#define MPC85XX_CPU_BOARD_REV(maj, min)	((((maj)&0xff) << 8) | ((min) & 0xff))
+#define MPC85XX_CPU_BOARD_MAJOR(rev)	(((rev) >> 8) & 0xff)
+#define MPC85XX_CPU_BOARD_MINOR(rev)	((rev) & 0xff)
+
+#define MPC85XX_CPU_BOARD_REV_UNKNOWN	MPC85XX_CPU_BOARD_REV(0,0)
+#define MPC85XX_CPU_BOARD_REV_1_0	MPC85XX_CPU_BOARD_REV(1,0)
+#define MPC85XX_CPU_BOARD_REV_1_1	MPC85XX_CPU_BOARD_REV(1,1)
+
+/*
+ * Returns CPU board revision register as a 16-bit value with
+ * the Major in the high byte, and Minor in the low byte.
+ */
+extern unsigned int get_cpu_board_revision(void);
+
+
+#endif	/* __CADMUS_H_ */
--- a/board/cds/mpc8541cds/Makefile
+++ b/board/cds/mpc8541cds/Makefile
@@ -0,0 +1,51 @@
+#
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o \
+	   ../common/cadmus.o \
+	   ../common/eeprom.o
+
+SOBJS	:= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/cds/mpc8541cds/config.mk
+++ b/board/cds/mpc8541cds/config.mk
@@ -0,0 +1,30 @@
+#
+# Copyright 2004 Freescale Semiconductor.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8541cds board
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8541=1
--- a/board/cds/mpc8541cds/init.S
+++ b/board/cds/mpc8541cds/init.S
@@ -0,0 +1,255 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2002,2003, Motorola Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define	entry_start \
+	mflr	r1 	;	\
+	bl	0f 	;
+
+#define	entry_end \
+0:	mflr	r0	;	\
+	mtlr	r1	;	\
+	blr		;
+
+
+	.section	.bootpg, "ax"
+	.globl	tlb1_entry
+tlb1_entry:
+	entry_start
+
+	/*
+	 * Number of TLB0 and TLB1 entries in the following table
+	 */
+	.long 13
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+	/*
+	 * TLB0		4K	Non-cacheable, guarded
+	 * 0xff700000	4K	Initial CCSRBAR mapping
+	 *
+	 * This ends up at a TLB0 Index==0 entry, and must not collide
+	 * with other TLB0 Entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+	/*
+	 * TLB0		16K	Cacheable, non-guarded
+	 * 0xd001_0000	16K	Temporary Global data for initialization
+	 *
+	 * Use four 4K TLB0 entries.  These entries must be cacheable
+	 * as they provide the bootstrap memory before the memory
+	 * controler and real memory have been configured.
+	 *
+	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+	 * and must not collide with other TLB0 entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+
+	/*
+	 * TLB 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	.long TLB1_MAS0(1, 0, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 1:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	.long TLB1_MAS0(1, 1, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	.long TLB1_MAS0(1, 2, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0xa0000000	256M	PCI2 MEM First half
+	 */
+	.long TLB1_MAS0(1, 3, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xb0000000	256M	PCI2 MEM Second half
+	 */
+	.long TLB1_MAS0(1, 4, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 * 0xe300_0000	16M	PCI2 IO
+	 */
+	.long TLB1_MAS0(1, 5, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 6:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	.long TLB1_MAS0(1, 6, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 7:	1M	Non-cacheable, guarded
+	 * 0xf8000000	1M	CADMUS registers
+	 */
+	.long TLB1_MAS0(1, 7, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1)
+
+	entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
+ * 0xe300_0000     0xe3ff_ffff     PCI2 IO                 16M
+ * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
+ * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
+ * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
+ * 0xff80_0000     0xffff_ffff     FLASH (boot bank)       8M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * The defines below are 1-off of the actual LAWAR0 usage.
+ * So LAWAR3 define uses the LAWAR4 register in the ECM.
+ */
+
+#define LAWBAR0 0
+#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
+#define LAWAR2 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
+#define LAWAR3 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff)
+#define LAWAR4 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR5 	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+	.section .bootpg, "ax"
+	.globl	law_entry
+
+law_entry:
+	entry_start
+	.long 6
+	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+	.long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5
+	entry_end
--- a/board/cds/mpc8541cds/mpc8541cds.c
+++ b/board/cds/mpc8541cds/mpc8541cds.c
@@ -0,0 +1,349 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <spd.h>
+
+#include "../common/cadmus.h"
+#include "../common/eeprom.h"
+
+#if defined(CONFIG_DDR_ECC)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+extern long int spd_sdram(void);
+
+void local_bus_init(void);
+void sdram_init(void);
+
+int board_early_init_f (void)
+{
+	return 0;
+}
+
+int checkboard (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+
+	/* PCI slot in USER bits CSR[6:7] by convention. */
+	uint pci_slot = get_pci_slot ();
+
+	uint pci_dual = get_pci_dual ();	/* PCI DUAL in CM_PCI[3] */
+	uint pci1_32 = gur->pordevsr & 0x10000;	/* PORDEVSR[15] */
+	uint pci1_clk_sel = gur->porpllsr & 0x8000;	/* PORPLLSR[16] */
+	uint pci2_clk_sel = gur->porpllsr & 0x4000;	/* PORPLLSR[17] */
+
+	uint pci1_speed = get_clock_freq ();	/* PCI PSPEED in [4:5] */
+
+	uint cpu_board_rev = get_cpu_board_revision ();
+
+	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
+		get_board_version (), pci_slot);
+
+	printf ("CPU Board Revision %d.%d (0x%04x)\n",
+		MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
+		MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
+
+	printf ("    PCI1: %d bit, %s MHz, %s\n",
+		(pci1_32) ? 32 : 64,
+		(pci1_speed == 33000000) ? "33" :
+		(pci1_speed == 66000000) ? "66" : "unknown",
+		pci1_clk_sel ? "sync" : "async");
+
+	if (pci_dual) {
+		printf ("    PCI2: 32 bit, 66 MHz, %s\n",
+			pci2_clk_sel ? "sync" : "async");
+	} else {
+		printf ("    PCI2: disabled\n");
+	}
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init ();
+
+	return 0;
+}
+
+long int
+initdram(int board_type)
+{
+	long dram_size = 0;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+
+	puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+	{
+		/*
+		 * Work around to stabilize DDR DLL MSYNC_IN.
+		 * Errata DDR9 seems to have been fixed.
+		 * This is now the workaround for Errata DDR11:
+		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
+		 */
+
+		volatile ccsr_gur_t *gur= &immap->im_gur;
+
+		gur->ddrdllcr = 0x81000000;
+		asm("sync;isync;msync");
+		udelay(200);
+	}
+#endif
+	dram_size = spd_sdram();
+
+#if defined(CONFIG_DDR_ECC)
+	/*
+	 * Initialize and enable DDR ECC.
+	 */
+	ddr_enable_ecc(dram_size);
+#endif
+	/*
+	 * SDRAM Initialization
+	 */
+	sdram_init();
+
+	puts("    DDR: ");
+	return dram_size;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+
+	uint clkdiv;
+	uint lbc_hz;
+	sys_info_t sysinfo;
+	uint temp_lbcdll;
+
+	/*
+	 * Errata LBC11.
+	 * Fix Local Bus clock glitch when DLL is enabled.
+	 *
+	 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
+	 * If localbus freq is > 133Mhz, DLL can be safely enabled.
+	 * Between 66 and 133, the DLL is enabled with an override workaround.
+	 */
+
+	get_sys_info(&sysinfo);
+	clkdiv = lbc->lcrr & 0x0f;
+	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+	if (lbc_hz < 66) {
+		lbc->lcrr |= 0x80000000;	/* DLL Bypass */
+
+	} else if (lbc_hz >= 133) {
+		lbc->lcrr &= (~0x80000000);		/* DLL Enabled */
+
+	} else {
+		lbc->lcrr &= (~0x8000000);	/* DLL Enabled */
+		udelay(200);
+
+		/*
+		 * Sample LBC DLL ctrl reg, upshift it to set the
+		 * override bits.
+		 */
+		temp_lbcdll = gur->lbcdllcr;
+		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
+		asm("sync;isync;msync");
+	}
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void
+sdram_init(void)
+{
+#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
+
+	uint idx;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+	uint cpu_board_rev;
+	uint lsdmr_common;
+
+	puts("    SDRAM: ");
+
+	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+	/*
+	 * Setup SDRAM Base and Option Registers
+	 */
+	lbc->or2 = CFG_OR2_PRELIM;
+	asm("msync");
+
+	lbc->br2 = CFG_BR2_PRELIM;
+	asm("msync");
+
+	lbc->lbcr = CFG_LBC_LBCR;
+	asm("msync");
+
+
+	lbc->lsrt = CFG_LBC_LSRT;
+	lbc->mrtpr = CFG_LBC_MRTPR;
+	asm("msync");
+
+	/*
+	 * Determine which address lines to use baed on CPU board rev.
+	 */
+	cpu_board_rev = get_cpu_board_revision();
+	lsdmr_common = CFG_LBC_LSDMR_COMMON;
+	if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
+		lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
+	} else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
+		lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
+	} else {
+		/*
+		 * Assume something unable to identify itself is
+		 * really old, and likely has lines 16/17 mapped.
+		 */
+		lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
+	}
+
+	/*
+	 * Issue PRECHARGE ALL command.
+	 */
+	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue 8 AUTO REFRESH commands.
+	 */
+	for (idx = 0; idx < 8; idx++) {
+		lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
+		asm("sync;msync");
+		*sdram_addr = 0xff;
+		ppcDcbf((unsigned long) sdram_addr);
+		udelay(100);
+	}
+
+	/*
+	 * Issue 8 MODE-set command.
+	 */
+	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue NORMAL OP command.
+	 */
+	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(200);    /* Overkill. Must wait > 200 bus cycles */
+
+#endif	/* enable SDRAM init */
+}
+
+#if defined(CFG_DRAM_TEST)
+int
+testdram(void)
+{
+	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *p;
+
+	printf("Testing DRAM from 0x%08x to 0x%08x\n",
+	       CFG_MEMTEST_START,
+	       CFG_MEMTEST_END);
+
+	printf("DRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("DRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("DRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("DRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("DRAM test passed.\n");
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_PCI)
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc85xxcds_config_table[] = {
+    { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+      PCI_IDSEL_NUMBER, PCI_ANY_ID,
+      pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				   PCI_ENET0_MEMADDR,
+				   PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+      } },
+    { }
+};
+#endif
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_mpc85xxcds_config_table,
+#endif
+};
+
+#endif	/* CONFIG_PCI */
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+	extern void pci_mpc85xx_init(struct pci_controller *hose);
+
+	pci_mpc85xx_init(&hose);
+#endif
+}
--- a/board/cds/mpc8541cds/u-boot.lds
+++ b/board/cds/mpc8541cds/u-boot.lds
@@ -0,0 +1,147 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/mpc85xx/start.o	(.bootpg)
+    board/cds/mpc8541cds/init.o (.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc85xx/start.o	(.text)
+    board/cds/mpc8541cds/init.o (.text)
+    cpu/mpc85xx/traps.o (.text)
+    cpu/mpc85xx/interrupts.o (.text)
+    cpu/mpc85xx/cpu_init.o (.text)
+    cpu/mpc85xx/cpu.o (.text)
+    cpu/mpc85xx/tsec.o (.text)
+    cpu/mpc85xx/speed.o (.text)
+    cpu/mpc85xx/pci.o (.text)
+    common/dlmalloc.o (.text)
+    lib_generic/crc32.o (.text)
+    lib_ppc/extable.o (.text)
+    lib_generic/zlib.o (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   }
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
--- a/board/cds/mpc8555cds/Makefile
+++ b/board/cds/mpc8555cds/Makefile
@@ -0,0 +1,51 @@
+#
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o \
+	   ../common/cadmus.o \
+	   ../common/eeprom.o
+
+SOBJS	:= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/cds/mpc8555cds/config.mk
+++ b/board/cds/mpc8555cds/config.mk
@@ -0,0 +1,30 @@
+#
+# Copyright 2004 Freescale Semiconductor.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8555cds board
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8555=1
--- a/board/cds/mpc8555cds/init.S
+++ b/board/cds/mpc8555cds/init.S
@@ -0,0 +1,255 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2002,2003, Motorola Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define	entry_start \
+	mflr	r1 	;	\
+	bl	0f 	;
+
+#define	entry_end \
+0:	mflr	r0	;	\
+	mtlr	r1	;	\
+	blr		;
+
+
+	.section	.bootpg, "ax"
+	.globl	tlb1_entry
+tlb1_entry:
+	entry_start
+
+	/*
+	 * Number of TLB0 and TLB1 entries in the following table
+	 */
+	.long 13
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+	/*
+	 * TLB0		4K	Non-cacheable, guarded
+	 * 0xff700000	4K	Initial CCSRBAR mapping
+	 *
+	 * This ends up at a TLB0 Index==0 entry, and must not collide
+	 * with other TLB0 Entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+	/*
+	 * TLB0		16K	Cacheable, non-guarded
+	 * 0xd001_0000	16K	Temporary Global data for initialization
+	 *
+	 * Use four 4K TLB0 entries.  These entries must be cacheable
+	 * as they provide the bootstrap memory before the memory
+	 * controler and real memory have been configured.
+	 *
+	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+	 * and must not collide with other TLB0 entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+
+	/*
+	 * TLB 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	.long TLB1_MAS0(1, 0, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 1:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	.long TLB1_MAS0(1, 1, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	.long TLB1_MAS0(1, 2, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0xa0000000	256M	PCI2 MEM First half
+	 */
+	.long TLB1_MAS0(1, 3, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xb0000000	256M	PCI2 MEM Second half
+	 */
+	.long TLB1_MAS0(1, 4, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 * 0xe300_0000	16M	PCI2 IO
+	 */
+	.long TLB1_MAS0(1, 5, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 6:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	.long TLB1_MAS0(1, 6, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 7:	1M	Non-cacheable, guarded
+	 * 0xf8000000	1M	CADMUS registers
+	 */
+	.long TLB1_MAS0(1, 7, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1)
+
+	entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
+ * 0xe300_0000     0xe3ff_ffff     PCI2 IO                 16M
+ * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
+ * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
+ * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
+ * 0xff80_0000     0xffff_ffff     FLASH (boot bank)       8M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * The defines below are 1-off of the actual LAWAR0 usage.
+ * So LAWAR3 define uses the LAWAR4 register in the ECM.
+ */
+
+#define LAWBAR0 0
+#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
+#define LAWAR2 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
+#define LAWAR3 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff)
+#define LAWAR4 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR5 	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+	.section .bootpg, "ax"
+	.globl	law_entry
+
+law_entry:
+	entry_start
+	.long 6
+	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+	.long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5
+	entry_end
--- a/board/cds/mpc8555cds/mpc8555cds.c
+++ b/board/cds/mpc8555cds/mpc8555cds.c
@@ -0,0 +1,346 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <spd.h>
+
+#include "../common/cadmus.h"
+#include "../common/eeprom.h"
+
+#if defined(CONFIG_DDR_ECC)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+extern long int spd_sdram(void);
+
+void local_bus_init(void);
+void sdram_init(void);
+
+int board_early_init_f (void)
+{
+	return 0;
+}
+
+int checkboard (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+
+	/* PCI slot in USER bits CSR[6:7] by convention. */
+	uint pci_slot = get_pci_slot ();
+
+	uint pci_dual = get_pci_dual ();	/* PCI DUAL in CM_PCI[3] */
+	uint pci1_32 = gur->pordevsr & 0x10000;	/* PORDEVSR[15] */
+	uint pci1_clk_sel = gur->porpllsr & 0x8000;	/* PORPLLSR[16] */
+	uint pci2_clk_sel = gur->porpllsr & 0x4000;	/* PORPLLSR[17] */
+
+	uint pci1_speed = get_clock_freq ();	/* PCI PSPEED in [4:5] */
+
+	uint cpu_board_rev = get_cpu_board_revision ();
+
+	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
+		get_board_version (), pci_slot);
+
+	printf ("CPU Board Revision %d.%d (0x%04x)\n",
+		MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
+		MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
+
+	printf ("    PCI1: %d bit, %s MHz, %s\n",
+		(pci1_32) ? 32 : 64,
+		(pci1_speed == 33000000) ? "33" :
+		(pci1_speed == 66000000) ? "66" : "unknown",
+		pci1_clk_sel ? "sync" : "async");
+
+	if (pci_dual) {
+		printf ("    PCI2: 32 bit, 66 MHz, %s\n",
+			pci2_clk_sel ? "sync" : "async");
+	} else {
+		printf ("    PCI2: disabled\n");
+	}
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init ();
+
+	return 0;
+}
+
+long int
+initdram(int board_type)
+{
+	long dram_size = 0;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+
+	puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+	{
+		/*
+		 * Work around to stabilize DDR DLL MSYNC_IN.
+		 * Errata DDR9 seems to have been fixed.
+		 * This is now the workaround for Errata DDR11:
+		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
+		 */
+
+		volatile ccsr_gur_t *gur= &immap->im_gur;
+
+		gur->ddrdllcr = 0x81000000;
+		asm("sync;isync;msync");
+		udelay(200);
+	}
+#endif
+	dram_size = spd_sdram();
+
+#if defined(CONFIG_DDR_ECC)
+	/*
+	 * Initialize and enable DDR ECC.
+	 */
+	ddr_enable_ecc(dram_size);
+#endif
+	/*
+	 * SDRAM Initialization
+	 */
+	sdram_init();
+
+	puts("    DDR: ");
+	return dram_size;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+
+	uint clkdiv;
+	uint lbc_hz;
+	sys_info_t sysinfo;
+	uint temp_lbcdll;
+
+	/*
+	 * Errata LBC11.
+	 * Fix Local Bus clock glitch when DLL is enabled.
+	 *
+	 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
+	 * If localbus freq is > 133Mhz, DLL can be safely enabled.
+	 * Between 66 and 133, the DLL is enabled with an override workaround.
+	 */
+
+	get_sys_info(&sysinfo);
+	clkdiv = lbc->lcrr & 0x0f;
+	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+	if (lbc_hz < 66) {
+		lbc->lcrr |= 0x80000000;	/* DLL Bypass */
+
+	} else if (lbc_hz >= 133) {
+		lbc->lcrr &= (~0x80000000);		/* DLL Enabled */
+
+	} else {
+		lbc->lcrr &= (~0x8000000);	/* DLL Enabled */
+		udelay(200);
+
+		/*
+		 * Sample LBC DLL ctrl reg, upshift it to set the
+		 * override bits.
+		 */
+		temp_lbcdll = gur->lbcdllcr;
+		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
+		asm("sync;isync;msync");
+	}
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void
+sdram_init(void)
+{
+#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
+
+	uint idx;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+	uint cpu_board_rev;
+	uint lsdmr_common;
+
+	puts("    SDRAM: ");
+
+	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+	/*
+	 * Setup SDRAM Base and Option Registers
+	 */
+	lbc->or2 = CFG_OR2_PRELIM;
+	asm("msync");
+
+	lbc->br2 = CFG_BR2_PRELIM;
+	asm("msync");
+
+	lbc->lbcr = CFG_LBC_LBCR;
+	asm("msync");
+
+	lbc->lsrt = CFG_LBC_LSRT;
+	lbc->mrtpr = CFG_LBC_MRTPR;
+	asm("msync");
+
+	/*
+	 * Determine which address lines to use baed on CPU board rev.
+	 */
+	cpu_board_rev = get_cpu_board_revision();
+	lsdmr_common = CFG_LBC_LSDMR_COMMON;
+	if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
+		lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
+	} else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
+		lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
+	} else {
+		/*
+		 * Assume something unable to identify itself is
+		 * really old, and likely has lines 16/17 mapped.
+		 */
+		lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
+	}
+
+	/*
+	 * Issue PRECHARGE ALL command.
+	 */
+	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue 8 AUTO REFRESH commands.
+	 */
+	for (idx = 0; idx < 8; idx++) {
+		lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
+		asm("sync;msync");
+		*sdram_addr = 0xff;
+		ppcDcbf((unsigned long) sdram_addr);
+		udelay(100);
+	}
+
+	/*
+	 * Issue 8 MODE-set command.
+	 */
+	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue NORMAL OP command.
+	 */
+	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(200);    /* Overkill. Must wait > 200 bus cycles */
+
+#endif	/* enable SDRAM init */
+}
+
+#if defined(CFG_DRAM_TEST)
+int
+testdram(void)
+{
+	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *p;
+
+	printf("Testing DRAM from 0x%08x to 0x%08x\n",
+	       CFG_MEMTEST_START,
+	       CFG_MEMTEST_END);
+
+	printf("DRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("DRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("DRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("DRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("DRAM test passed.\n");
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_PCI)
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc85xxcds_config_table[] = {
+    { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+      PCI_IDSEL_NUMBER, PCI_ANY_ID,
+      pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				   PCI_ENET0_MEMADDR,
+				   PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+      } },
+    { }
+};
+#endif
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_mpc85xxcds_config_table,
+#endif
+};
+
+#endif	/* CONFIG_PCI */
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+	extern void pci_mpc85xx_init(struct pci_controller *hose);
+
+	pci_mpc85xx_init(&hose);
+#endif
+}
--- a/board/cds/mpc8555cds/u-boot.lds
+++ b/board/cds/mpc8555cds/u-boot.lds
@@ -0,0 +1,147 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/mpc85xx/start.o	(.bootpg)
+    board/cds/mpc8555cds/init.o (.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc85xx/start.o	(.text)
+    board/cds/mpc8555cds/init.o (.text)
+    cpu/mpc85xx/traps.o (.text)
+    cpu/mpc85xx/interrupts.o (.text)
+    cpu/mpc85xx/cpu_init.o (.text)
+    cpu/mpc85xx/cpu.o (.text)
+    cpu/mpc85xx/tsec.o (.text)
+    cpu/mpc85xx/speed.o (.text)
+    cpu/mpc85xx/pci.o (.text)
+    common/dlmalloc.o (.text)
+    lib_generic/crc32.o (.text)
+    lib_ppc/extable.o (.text)
+    lib_generic/zlib.o (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   }
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
--- a/board/cerf250/cerf250.c
+++ b/board/cerf250/cerf250.c
@@ -42,7 +42,7 @@ int board_init (void)
 	/* so we do _nothing_ here */

 	/* arch number of cerf PXA Board */
-	gd->bd->bi_arch_number = 139;
+	gd->bd->bi_arch_number = MACH_TYPE_PXA_CERF;

 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0xa0000100;
--- a/board/cmc_pu2/Makefile
+++ b/board/cmc_pu2/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= cmc_pu2.o at45.o dm9161.o flash.o
+SOBJS	:= memsetup.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/cmc_pu2/at45.c
+++ b/board/cmc_pu2/at45.c
@@ -0,0 +1,621 @@
+/* Driver for ATMEL DataFlash support
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/hardware.h>
+
+#ifdef CONFIG_HAS_DATAFLASH
+#include <dataflash.h>
+
+#define AT91C_SPI_CLK	10000000	/* Max Value = 10MHz to be compliant to
+the Continuous Array Read function */
+
+/* AC Characteristics */
+/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
+#define DATAFLASH_TCSS	(0xC << 16)
+#define DATAFLASH_TCHS	(0x1 << 24)
+
+#define AT91C_TIMEOUT_WRDY			200000
+#define AT91C_SPI_PCS0_SERIAL_DATAFLASH		0xE     /* Chip Select 0 : NPCS0 %1110 */
+#define AT91C_SPI_PCS3_DATAFLASH_CARD		0x7     /* Chip Select 3 : NPCS3 %0111 */
+
+void AT91F_SpiInit(void) {
+
+/*-------------------------------------------------------------------*/
+/*	SPI DataFlash Init								*/
+/*-------------------------------------------------------------------*/
+	/* Configure PIOs */
+	AT91C_BASE_PIOA->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 |
+				   AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK;
+	AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 |
+				   AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK;
+	/* Enable CLock */
+	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI;
+
+	/* Reset the SPI */
+	AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST;
+
+	/* Configure SPI in Master Mode with No CS selected !!! */
+	AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS;
+
+	/* Configure CS0 and CS3 */
+	*(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT &
+	DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
+
+	*(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT &
+	DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
+
+}
+
+void AT91F_SpiEnable(int cs) {
+	switch(cs) {
+	case 0:	/* Configure SPI CS0 for Serial DataFlash AT45DBxx */
+		AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
+		AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) & AT91C_SPI_PCS);
+		break;
+	case 3:	/* Configure SPI CS3 for Serial DataFlash Card */
+		/* Set up PIO SDC_TYPE to switch on DataFlash Card and not MMC/SDCard */
+		AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB7;	/* Set in PIO mode */
+		AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB7;	/* Configure in output */
+		/* Clear Output */
+		AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7;
+		/* Configure PCS */
+		AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
+		AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS);
+		break;
+	}
+
+	/* SPI_Enable */
+	AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN;
+}
+
+/*----------------------------------------------------------------------------*/
+/* \fn    AT91F_SpiWrite						      */
+/* \brief Set the PDC registers for a transfert				      */
+/*----------------------------------------------------------------------------*/
+unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc )
+{
+	unsigned int timeout;
+
+	pDesc->state = BUSY;
+
+	AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
+
+	/* Initialize the Transmit and Receive Pointer */
+	AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ;
+	AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ;
+
+	/* Intialize the Transmit and Receive Counters */
+	AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size;
+	AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size;
+
+	if ( pDesc->tx_data_size != 0 ) {
+		/* Initialize the Next Transmit and Next Receive Pointer */
+		AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ;
+		AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ;
+
+		/* Intialize the Next Transmit and Next Receive Counters */
+		AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ;
+		AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ;
+	}
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked();
+	timeout = 0;
+
+	AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN;
+	while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) && ((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT));
+	AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
+	pDesc->state = IDLE;
+
+	if (timeout >= CFG_SPI_WRITE_TOUT){
+		printf("Error Timeout\n\r");
+		return DATAFLASH_ERROR;
+	}
+
+	return DATAFLASH_OK;
+}
+
+
+/*----------------------------------------------------------------------*/
+/* \fn    AT91F_DataFlashSendCommand					*/
+/* \brief Generic function to send a command to the dataflash		*/
+/*----------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashSendCommand(
+	AT91PS_DataFlash pDataFlash,
+	unsigned char OpCode,
+	unsigned int CmdSize,
+	unsigned int DataflashAddress)
+{
+    unsigned int adr;
+
+	if ( (pDataFlash->pDataFlashDesc->state) != IDLE)
+		return DATAFLASH_BUSY;
+
+	/* process the address to obtain page address and byte address */
+	adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << pDataFlash->pDevice->page_offset) + (DataflashAddress % (pDataFlash->pDevice->pages_size));
+
+	/* fill the  command  buffer */
+	pDataFlash->pDataFlashDesc->command[0] = OpCode;
+	if (pDataFlash->pDevice->pages_number >= 16384) {
+		pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x0F000000) >> 24);
+		pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x00FF0000) >> 16);
+		pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((adr & 0x0000FF00) >> 8);
+		pDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF);
+	} else {
+		pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16);
+		pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8);
+		pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF) ;
+		pDataFlash->pDataFlashDesc->command[4] = 0;
+	}
+	pDataFlash->pDataFlashDesc->command[5] = 0;
+	pDataFlash->pDataFlashDesc->command[6] = 0;
+	pDataFlash->pDataFlashDesc->command[7] = 0;
+
+	/* Initialize the SpiData structure for the spi write fuction */
+	pDataFlash->pDataFlashDesc->tx_cmd_pt   =  pDataFlash->pDataFlashDesc->command ;
+	pDataFlash->pDataFlashDesc->tx_cmd_size =  CmdSize ;
+	pDataFlash->pDataFlashDesc->rx_cmd_pt   =  pDataFlash->pDataFlashDesc->command ;
+	pDataFlash->pDataFlashDesc->rx_cmd_size =  CmdSize ;
+
+	/* send the command and read the data */
+	return AT91F_SpiWrite (pDataFlash->pDataFlashDesc);
+}
+
+
+/*----------------------------------------------------------------------*/
+/* \fn    AT91F_DataFlashGetStatus					*/
+/* \brief Read the status register of the dataflash			*/
+/*----------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc)
+{
+	AT91S_DataFlashStatus status;
+
+	/* if a transfert is in progress ==> return 0 */
+	if( (pDesc->state) != IDLE)
+		return DATAFLASH_BUSY;
+
+	/* first send the read status command (D7H) */
+	pDesc->command[0] = DB_STATUS;
+	pDesc->command[1] = 0;
+
+	pDesc->DataFlash_state  = GET_STATUS;
+	pDesc->tx_data_size 	= 0 ;	/* Transmit the command and receive response */
+	pDesc->tx_cmd_pt 		= pDesc->command ;
+	pDesc->rx_cmd_pt 		= pDesc->command ;
+	pDesc->rx_cmd_size 		= 2 ;
+	pDesc->tx_cmd_size 		= 2 ;
+	status = AT91F_SpiWrite (pDesc);
+
+	pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1);
+
+	return status;
+}
+
+
+/*----------------------------------------------------------------------*/
+/* \fn    AT91F_DataFlashWaitReady					*/
+/* \brief wait for dataflash ready (bit7 of the status register == 1)	*/
+/*----------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc pDataFlashDesc, unsigned int timeout)
+{
+	pDataFlashDesc->DataFlash_state = IDLE;
+
+	do {
+		AT91F_DataFlashGetStatus(pDataFlashDesc);
+		timeout--;
+	} while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && (timeout > 0) );
+
+	if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80)
+		return DATAFLASH_ERROR;
+
+	return DATAFLASH_OK;
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_DataFlashContinuousRead 				*/
+/* Object              : Continuous stream Read 				*/
+/* Input Parameters    : DataFlash Service					*/
+/*						: <src> = dataflash address	*/
+/*                     : <*dataBuffer> = data buffer pointer			*/
+/*                     : <sizeToRead> = data buffer size			*/
+/* Return value		: State of the dataflash				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
+	AT91PS_DataFlash pDataFlash,
+	int src,
+	unsigned char *dataBuffer,
+	int sizeToRead )
+{
+	AT91S_DataFlashStatus status;
+	/* Test the size to read in the device */
+	if ( (src + sizeToRead) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number)))
+		return DATAFLASH_MEMORY_OVERFLOW;
+
+	pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer;
+	pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead;
+	pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer;
+	pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead;
+
+	status = AT91F_DataFlashSendCommand (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src);
+	/* Send the command to the dataflash */
+	return(status);
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_DataFlashPagePgmBuf				*/
+/* Object              : Main memory page program through buffer 1 or buffer 2	*/
+/* Input Parameters    : DataFlash Service					*/
+/*						: <*src> = Source buffer	*/
+/*                     : <dest> = dataflash destination address			*/
+/*                     : <SizeToWrite> = data buffer size			*/
+/* Return value		: State of the dataflash				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(
+	AT91PS_DataFlash pDataFlash,
+	unsigned char *src,
+	unsigned int dest,
+	unsigned int SizeToWrite)
+{
+	int cmdsize;
+	pDataFlash->pDataFlashDesc->tx_data_pt = src ;
+	pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ;
+	pDataFlash->pDataFlashDesc->rx_data_pt = src;
+	pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite;
+
+	cmdsize = 4;
+	/* Send the command to the dataflash */
+	if (pDataFlash->pDevice->pages_number >= 16384)
+		cmdsize = 5;
+	return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1, cmdsize, dest));
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_MainMemoryToBufferTransfert			*/
+/* Object              : Read a page in the SRAM Buffer 1 or 2			*/
+/* Input Parameters    : DataFlash Service					*/
+/*                     : Page concerned						*/
+/*                     : 							*/
+/* Return value		: State of the dataflash				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert(
+	AT91PS_DataFlash pDataFlash,
+	unsigned char BufferCommand,
+	unsigned int page)
+{
+	int cmdsize;
+	/* Test if the buffer command is legal */
+	if ((BufferCommand != DB_PAGE_2_BUF1_TRF) && (BufferCommand != DB_PAGE_2_BUF2_TRF))
+		return DATAFLASH_BAD_COMMAND;
+
+	/* no data to transmit or receive */
+	pDataFlash->pDataFlashDesc->tx_data_size = 0;
+	cmdsize = 4;
+	if (pDataFlash->pDevice->pages_number >= 16384)
+		cmdsize = 5;
+	return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, page*pDataFlash->pDevice->pages_size));
+}
+
+
+/*----------------------------------------------------------------------------- */
+/* Function Name       : AT91F_DataFlashWriteBuffer				*/
+/* Object              : Write data to the internal sram buffer 1 or 2		*/
+/* Input Parameters    : DataFlash Service					*/
+/*			: <BufferCommand> = command to write buffer1 or buffer2	*/
+/*                     : <*dataBuffer> = data buffer to write			*/
+/*                     : <bufferAddress> = address in the internal buffer	*/
+/*                     : <SizeToWrite> = data buffer size			*/
+/* Return value		: State of the dataflash				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer (
+	AT91PS_DataFlash pDataFlash,
+	unsigned char BufferCommand,
+	unsigned char *dataBuffer,
+	unsigned int bufferAddress,
+	int SizeToWrite )
+{
+	int cmdsize;
+	/* Test if the buffer command is legal */
+	if ((BufferCommand != DB_BUF1_WRITE) && (BufferCommand != DB_BUF2_WRITE))
+		return DATAFLASH_BAD_COMMAND;
+
+	/* buffer address must be lower than page size */
+	if (bufferAddress > pDataFlash->pDevice->pages_size)
+		return DATAFLASH_BAD_ADDRESS;
+
+	if ( (pDataFlash->pDataFlashDesc->state)  != IDLE)
+		return DATAFLASH_BUSY;
+
+	/* Send first Write Command */
+	pDataFlash->pDataFlashDesc->command[0] = BufferCommand;
+	pDataFlash->pDataFlashDesc->command[1] = 0;
+	if (pDataFlash->pDevice->pages_number >= 16384) {
+	    	pDataFlash->pDataFlashDesc->command[2] = 0;
+	    	pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(((unsigned int)(bufferAddress &  pDataFlash->pDevice->byte_mask)) >> 8) ;
+	    	pDataFlash->pDataFlashDesc->command[4] = (unsigned char)((unsigned int)bufferAddress  & 0x00FF) ;
+		cmdsize = 5;
+	} else {
+	    	pDataFlash->pDataFlashDesc->command[2] = (unsigned char)(((unsigned int)(bufferAddress &  pDataFlash->pDevice->byte_mask)) >> 8) ;
+	    	pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress  & 0x00FF) ;
+	    	pDataFlash->pDataFlashDesc->command[4] = 0;
+		cmdsize = 4;
+	}
+
+	pDataFlash->pDataFlashDesc->tx_cmd_pt 	 = pDataFlash->pDataFlashDesc->command ;
+	pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize ;
+	pDataFlash->pDataFlashDesc->rx_cmd_pt 	 = pDataFlash->pDataFlashDesc->command ;
+	pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize ;
+
+	pDataFlash->pDataFlashDesc->rx_data_pt 	= dataBuffer ;
+	pDataFlash->pDataFlashDesc->tx_data_pt 	= dataBuffer ;
+	pDataFlash->pDataFlashDesc->rx_data_size 	= SizeToWrite ;
+	pDataFlash->pDataFlashDesc->tx_data_size 	= SizeToWrite ;
+
+	return AT91F_SpiWrite(pDataFlash->pDataFlashDesc);
+}
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_PageErase                                        */
+/* Object              : Erase a page 						*/
+/* Input Parameters    : DataFlash Service					*/
+/*                     : Page concerned						*/
+/*                     : 							*/
+/* Return value		: State of the dataflash				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_PageErase(
+	AT91PS_DataFlash pDataFlash,
+	unsigned int page)
+{
+	int cmdsize;
+	/* Test if the buffer command is legal */
+	/* no data to transmit or receive */
+    	pDataFlash->pDataFlashDesc->tx_data_size = 0;
+
+	cmdsize = 4;
+	if (pDataFlash->pDevice->pages_number >= 16384)
+		cmdsize = 5;
+	return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize, page*pDataFlash->pDevice->pages_size));
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_BlockErase                                       */
+/* Object              : Erase a Block 						*/
+/* Input Parameters    : DataFlash Service					*/
+/*                     : Page concerned						*/
+/*                     : 							*/
+/* Return value		: State of the dataflash				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_BlockErase(
+	AT91PS_DataFlash pDataFlash,
+	unsigned int block)
+{
+	int cmdsize;
+	/* Test if the buffer command is legal */
+	/* no data to transmit or receive */
+    	pDataFlash->pDataFlashDesc->tx_data_size = 0;
+	cmdsize = 4;
+	if (pDataFlash->pDevice->pages_number >= 16384)
+		cmdsize = 5;
+	return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize, block*8*pDataFlash->pDevice->pages_size));
+}
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_WriteBufferToMain				*/
+/* Object              : Write buffer to the main memory			*/
+/* Input Parameters    : DataFlash Service					*/
+/*		: <BufferCommand> = command to send to buffer1 or buffer2	*/
+/*                     : <dest> = main memory address				*/
+/* Return value		: State of the dataflash				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_WriteBufferToMain (
+	AT91PS_DataFlash pDataFlash,
+	unsigned char BufferCommand,
+	unsigned int dest )
+{
+	int cmdsize;
+	/* Test if the buffer command is correct */
+	if ((BufferCommand != DB_BUF1_PAGE_PGM) &&
+	    (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) &&
+	    (BufferCommand != DB_BUF2_PAGE_PGM) &&
+	    (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) )
+		return DATAFLASH_BAD_COMMAND;
+
+	/* no data to transmit or receive */
+	pDataFlash->pDataFlashDesc->tx_data_size = 0;
+
+	cmdsize = 4;
+	if (pDataFlash->pDevice->pages_number >= 16384)
+		cmdsize = 5;
+	/* Send the command to the dataflash */
+	return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, dest));
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_PartialPageWrite					*/
+/* Object              : Erase partielly a page					*/
+/* Input Parameters    : <page> = page number					*/
+/*			: <AdrInpage> = adr to begin the fading			*/
+/*                     : <length> = Number of bytes to erase			*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_PartialPageWrite (
+	AT91PS_DataFlash pDataFlash,
+	unsigned char *src,
+	unsigned int dest,
+	unsigned int size)
+{
+	unsigned int page;
+	unsigned int AdrInPage;
+
+	page = dest / (pDataFlash->pDevice->pages_size);
+	AdrInPage = dest % (pDataFlash->pDevice->pages_size);
+
+	/* Read the contents of the page in the Sram Buffer */
+	AT91F_MainMemoryToBufferTransfert(pDataFlash, DB_PAGE_2_BUF1_TRF, page);
+	AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+	/*Update the SRAM buffer */
+	AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size);
+
+	AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+
+	/* Erase page if a 128 Mbits device */
+	if (pDataFlash->pDevice->pages_number >= 16384) {
+		AT91F_PageErase(pDataFlash, page);
+		/* Rewrite the modified Sram Buffer in the main memory */
+		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+	}
+
+	/* Rewrite the modified Sram Buffer in the main memory */
+	return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, (page*pDataFlash->pDevice->pages_size)));
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_DataFlashWrite					*/
+/* Object              :							*/
+/* Input Parameters    : <*src> = Source buffer					*/
+/*                     : <dest> = dataflash adress				*/
+/*                     : <size> = data buffer size				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashWrite(
+	AT91PS_DataFlash pDataFlash,
+	unsigned char *src,
+	int dest,
+	int size )
+{
+	unsigned int length;
+	unsigned int page;
+	unsigned int status;
+
+	AT91F_SpiEnable(pDataFlash->pDevice->cs);
+
+	if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number)))
+		return DATAFLASH_MEMORY_OVERFLOW;
+
+	/* If destination does not fit a page start address */
+	if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size)))  != 0 ) {
+		length = pDataFlash->pDevice->pages_size - (dest % ((unsigned int)(pDataFlash->pDevice->pages_size)));
+
+		if (size < length)
+			length = size;
+
+		if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length))
+			return DATAFLASH_ERROR;
+
+		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+
+		/* Update size, source and destination pointers */
+		size -= length;
+		dest += length;
+		src += length;
+	}
+
+	while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) {
+		/* program dataflash page */
+		page = (unsigned int)dest / (pDataFlash->pDevice->pages_size);
+
+		status = AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, 0, pDataFlash->pDevice->pages_size);
+		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+
+		status = AT91F_PageErase(pDataFlash, page);
+		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+		if (!status)
+			return DATAFLASH_ERROR;
+
+		status = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest);
+		if(!status)
+			return DATAFLASH_ERROR;
+
+		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+
+		/* Update size, source and destination pointers */
+		size -= pDataFlash->pDevice->pages_size ;
+		dest += pDataFlash->pDevice->pages_size ;
+		src  += pDataFlash->pDevice->pages_size ;
+	}
+
+	/* If still some bytes to read */
+	if ( size > 0 ) {
+		/* program dataflash page */
+		if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) )
+			return DATAFLASH_ERROR;
+
+		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+	}
+	return DATAFLASH_OK;
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_DataFlashRead 					*/
+/* Object              : Read a block in dataflash				*/
+/* Input Parameters    : 							*/
+/* Return value		: 							*/
+/*------------------------------------------------------------------------------*/
+int AT91F_DataFlashRead(
+	AT91PS_DataFlash pDataFlash,
+	unsigned long addr,
+	unsigned long size,
+	char *buffer)
+{
+	unsigned long SizeToRead;
+
+	AT91F_SpiEnable(pDataFlash->pDevice->cs);
+
+	if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
+		return -1;
+
+	while (size) {
+		SizeToRead = (size < 0x8000)? size:0x8000;
+
+		if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
+			return -1;
+
+		if (AT91F_DataFlashContinuousRead (pDataFlash, addr, buffer, SizeToRead) != DATAFLASH_OK)
+			return -1;
+
+		size -= SizeToRead;
+		addr += SizeToRead;
+		buffer += SizeToRead;
+	}
+
+	return DATAFLASH_OK;
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_DataflashProbe 					*/
+/* Object              : 							*/
+/* Input Parameters    : 							*/
+/* Return value	       : Dataflash status register				*/
+/*------------------------------------------------------------------------------*/
+int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc)
+{
+	AT91F_SpiEnable(cs);
+	AT91F_DataFlashGetStatus(pDesc);
+	return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C);
+}
+
+#endif
--- a/board/cmc_pu2/cmc_pu2.c
+++ b/board/cmc_pu2/cmc_pu2.c
@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Modified for CMC_PU2 (removed Smart Media support) by Gary Jennejohn
+ * (2004) garyj@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mach-types.h>
+#include <asm/arch/AT91RM9200.h>
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* Enable Ctrlc */
+	console_init_f ();
+
+	/* Correct IRDA resistor problem */
+	/* Set PA23_TXD in Output */
+	(AT91PS_PIO) AT91C_BASE_PIOA->PIO_OER = AT91C_PA23_TXD2;
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* arch number of CMC_PU2-Board */
+	/* gd->bd->bi_arch_number = MACH_TYPE_CMC_PU2; */
+	gd->bd->bi_arch_number = 251;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
--- a/board/cmc_pu2/config.mk
+++ b/board/cmc_pu2/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x20f00000
--- a/board/cmc_pu2/dm9161.c
+++ b/board/cmc_pu2/dm9161.c
@@ -0,0 +1,243 @@
+/*
+ * (C) Copyright 2003
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <at91rm9200_net.h>
+#include <net.h>
+#include <dm9161.h>
+
+#ifdef CONFIG_DRIVER_ETHER
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+
+/*
+ * Name:
+ *	dm9161_IsPhyConnected
+ * Description:
+ *	Reads the 2 PHY ID registers
+ * Arguments:
+ *	p_mac - pointer to AT91S_EMAC struct
+ * Return value:
+ *	TRUE - if id read successfully
+ *	FALSE- if error
+ */
+static unsigned int dm9161_IsPhyConnected (AT91PS_EMAC p_mac)
+{
+	unsigned short Id1, Id2;
+
+	at91rm9200_EmacEnableMDIO (p_mac);
+	at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID1, &Id1);
+	at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID2, &Id2);
+	at91rm9200_EmacDisableMDIO (p_mac);
+
+	if ((Id1 == (DM9161_PHYID1_OUI >> 6)) &&
+		((Id2 >> 10) == (DM9161_PHYID1_OUI & DM9161_LSB_MASK)))
+		return TRUE;
+
+	return FALSE;
+}
+
+/*
+ * Name:
+ *	dm9161_GetLinkSpeed
+ * Description:
+ *	Link parallel detection status of MAC is checked and set in the
+ *	MAC configuration registers
+ * Arguments:
+ *	p_mac - pointer to MAC
+ * Return value:
+ *	TRUE - if link status set succesfully
+ *	FALSE - if link status not set
+ */
+static UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac)
+{
+	unsigned short stat1, stat2;
+
+	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &stat1))
+		return FALSE;
+
+	if (!(stat1 & DM9161_LINK_STATUS))	/* link status up? */
+		return FALSE;
+
+	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_DSCSR, &stat2))
+		return FALSE;
+
+	if ((stat1 & DM9161_100BASE_TX_FD) && (stat2 & DM9161_100FDX)) {
+		/*set Emac for 100BaseTX and Full Duplex  */
+		p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
+		return TRUE;
+	}
+
+	if ((stat1 & DM9161_10BASE_T_FD) && (stat2 & DM9161_10FDX)) {
+		/*set MII for 10BaseT and Full Duplex  */
+		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+				| AT91C_EMAC_FD;
+		return TRUE;
+	}
+
+	if ((stat1 & DM9161_100BASE_T4_HD) && (stat2 & DM9161_100HDX)) {
+		/*set MII for 100BaseTX and Half Duplex  */
+		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+				| AT91C_EMAC_SPD;
+		return TRUE;
+	}
+
+	if ((stat1 & DM9161_10BASE_T_HD) && (stat2 & DM9161_10HDX)) {
+		/*set MII for 10BaseT and Half Duplex  */
+		p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
+		return TRUE;
+	}
+	return FALSE;
+}
+
+
+/*
+ * Name:
+ *	dm9161_InitPhy
+ * Description:
+ *	MAC starts checking its link by using parallel detection and
+ *	Autonegotiation and the same is set in the MAC configuration registers
+ * Arguments:
+ *	p_mac - pointer to struct AT91S_EMAC
+ * Return value:
+ *	TRUE - if link status set succesfully
+ *	FALSE - if link status not set
+ */
+static UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac)
+{
+	UCHAR ret = TRUE;
+	unsigned short IntValue;
+
+	at91rm9200_EmacEnableMDIO (p_mac);
+
+	if (!dm9161_GetLinkSpeed (p_mac)) {
+		/* Try another time */
+		ret = dm9161_GetLinkSpeed (p_mac);
+	}
+
+	/* Disable PHY Interrupts */
+	at91rm9200_EmacReadPhy (p_mac, DM9161_MDINTR, &IntValue);
+	/* clear FDX, SPD, Link, INTR masks */
+	IntValue &= ~(DM9161_FDX_MASK | DM9161_SPD_MASK |
+		      DM9161_LINK_MASK | DM9161_INTR_MASK);
+	at91rm9200_EmacWritePhy (p_mac, DM9161_MDINTR, &IntValue);
+	at91rm9200_EmacDisableMDIO (p_mac);
+
+	return (ret);
+}
+
+
+/*
+ * Name:
+ *	dm9161_AutoNegotiate
+ * Description:
+ *	MAC Autonegotiates with the partner status of same is set in the
+ *	MAC configuration registers
+ * Arguments:
+ *	dev - pointer to struct net_device
+ * Return value:
+ *	TRUE - if link status set successfully
+ *	FALSE - if link status not set
+ */
+static UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
+{
+	unsigned short value;
+	unsigned short PhyAnar;
+	unsigned short PhyAnalpar;
+
+	/* Set dm9161 control register */
+	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
+		return FALSE;
+	value &= ~DM9161_AUTONEG;	/* remove autonegotiation enable */
+	value |= DM9161_ISOLATE;	/* Electrically isolate PHY */
+	if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
+		return FALSE;
+
+	/* Set the Auto_negotiation Advertisement Register */
+	/* MII advertising for Next page, 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */
+	PhyAnar = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX |
+		  DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3;
+	if (!at91rm9200_EmacWritePhy (p_mac, DM9161_ANAR, &PhyAnar))
+		return FALSE;
+
+	/* Read the Control Register     */
+	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
+		return FALSE;
+
+	value |= DM9161_SPEED_SELECT | DM9161_AUTONEG | DM9161_DUPLEX_MODE;
+	if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
+		return FALSE;
+	/* Restart Auto_negotiation  */
+	value |= DM9161_RESTART_AUTONEG;
+	if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
+		return FALSE;
+
+	/*check AutoNegotiate complete */
+	udelay (10000);
+	at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &value);
+	if (!(value & DM9161_AUTONEG_COMP))
+		return FALSE;
+
+	/* Get the AutoNeg Link partner base page */
+	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_ANLPAR, &PhyAnalpar))
+		return FALSE;
+
+	if ((PhyAnar & DM9161_TX_FDX) && (PhyAnalpar & DM9161_TX_FDX)) {
+		/*set MII for 100BaseTX and Full Duplex  */
+		p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
+		return TRUE;
+	}
+
+	if ((PhyAnar & DM9161_10_FDX) && (PhyAnalpar & DM9161_10_FDX)) {
+		/*set MII for 10BaseT and Full Duplex  */
+		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+				| AT91C_EMAC_FD;
+		return TRUE;
+	}
+	return FALSE;
+}
+
+
+/*
+ * Name:
+ *	at91rm92000_GetPhyInterface
+ * Description:
+ *	Initialise the interface functions to the PHY
+ * Arguments:
+ *	None
+ * Return value:
+ *	None
+ */
+void at91rm92000_GetPhyInterface(AT91PS_PhyOps p_phyops)
+{
+	p_phyops->Init = dm9161_InitPhy;
+	p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
+	p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
+	p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
+}
+
+#endif	/* CONFIG_COMMANDS & CFG_CMD_NET */
+
+#endif	/* CONFIG_DRIVER_ETHER */
--- a/board/cmc_pu2/flash.c
+++ b/board/cmc_pu2/flash.c
@@ -0,0 +1,471 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * Modified for the CMC PU2 by (C) Copyright 2004 Gary Jennejohn
+ * garyj@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#ifndef	CFG_ENV_ADDR
+#define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+#endif
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*
+ * CPU to flash interface is 32-bit, so make declaration accordingly
+ */
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+
+#define FPW  FLASH_PORT_WIDTH
+#define FPWV FLASH_PORT_WIDTHV
+
+#define FLASH_CYCLE1	0x0555
+#define FLASH_CYCLE2	0x02AA
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPWV *addr, flash_info_t *info);
+static void flash_reset(flash_info_t *info);
+static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
+static flash_info_t *flash_get_info(ulong base);
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size = 0;
+	ulong flashbase = CFG_FLASH_BASE;
+
+	/* Init: no FLASHes known */
+	memset(&flash_info[0], 0, sizeof(flash_info_t));
+
+	flash_info[0].size =
+		flash_get_size((FPW *)flashbase, &flash_info[0]);
+
+	size = flash_info[0].size;
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      flash_get_info(CFG_MONITOR_BASE));
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+		      flash_get_info(CFG_ENV_ADDR));
+#endif
+
+	return size ? size : 1;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t *info)
+{
+	FPWV *base = (FPWV *)(info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+		*base = (FPW)0x00FF;	/* Intel Read Mode */
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+		*base = (FPW)0x00F0;	/* AMD Read Mode */
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static flash_info_t *flash_get_info(ulong base)
+{
+	int i;
+	flash_info_t * info;
+
+	info = NULL;
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
+		info = & flash_info[i];
+		if (info->size && info->start[0] <= base &&
+		    base <= info->start[0] + info->size - 1)
+			break;
+	}
+
+	return i == CFG_MAX_FLASH_BANKS ? 0 : info;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_S29GL064M:
+		printf ("S29GL064M-R6 (64Mbit, uniform sector size)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20,
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size (FPWV *addr, flash_info_t *info)
+{
+	int i;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	/* Write auto select command sequence and test FLASH answer */
+	addr[FLASH_CYCLE1] = (FPW)0x00AA;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE2] = (FPW)0x0055;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE1] = (FPW)0x0090;	/* selects Intel or AMD */
+
+	/* The manufacturer codes are only 1 byte, so just use 1 byte.
+	 * This works for any bus width and any FLASH device width.
+	 */
+	udelay(100);
+	switch (addr[0] & 0xff) {
+
+	case (uchar)AMD_MANUFACT:
+		debug ("Manufacturer: AMD (Spansion)\n");
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	case (uchar)INTEL_MANUFACT:
+		debug ("Manufacturer: Intel (not supported yet)\n");
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
+	if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) {
+
+	case AMD_ID_MIRROR:
+		debug ("Mirror Bit flash: addr[14] = %08X  addr[15] = %08X\n",
+			addr[14], addr[15]);
+
+		switch(addr[14] & 0xffff) {
+		case (AMD_ID_GL064M_2 & 0xffff):
+			if (addr[15] != (AMD_ID_GL064M_3 & 0xffff)) {
+				printf ("Chip: S29GLxxxM -> unknown\n");
+				info->flash_id = FLASH_UNKNOWN;
+				info->sector_count = 0;
+				info->size = 0;
+			} else {
+				debug ("Chip: S29GL064M-R6\n");
+				info->flash_id += FLASH_S29GL064M;
+				info->sector_count = 128;
+				info->size = 0x00800000;
+				for (i = 0; i < info->sector_count; i++) {
+					info->start[i] = base;
+					base += 0x10000;
+				}
+			}
+			break;	/* => 16 MB	*/
+		default:
+			printf ("Chip: *** unknown ***\n");
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			break;
+		}
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+	}
+
+	/* Put FLASH back in read mode */
+	flash_reset(info);
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	FPWV *addr = (FPWV *)(info->start[0]);
+	int flag, prot, sect, ssect, l_sect;
+	ulong start, now, last;
+
+	debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/*
+	 * Start erase on unprotected sectors.
+	 * Since the flash can erase multiple sectors with one command
+	 * we take advantage of that by doing the erase in chunks of
+	 * 3 sectors.
+	 */
+	for (sect = s_first; sect <= s_last; ) {
+		l_sect = -1;
+
+		addr[FLASH_CYCLE1] = 0x00AA;
+		addr[FLASH_CYCLE2] = 0x0055;
+		addr[FLASH_CYCLE1] = 0x0080;
+		addr[FLASH_CYCLE1] = 0x00AA;
+		addr[FLASH_CYCLE2] = 0x0055;
+
+		/* do the erase in chunks of at most 3 sectors */
+		for (ssect = 0; ssect < 3; ssect++) {
+			if ((sect + ssect) > s_last)
+				break;
+			if (info->protect[sect + ssect] == 0) {	/* not protected */
+				addr = (FPWV *)(info->start[sect + ssect]);
+				addr[0] = 0x0030;
+				l_sect = sect + ssect;
+			}
+		}
+		/* wait at least 80us - let's wait 1 ms */
+		udelay (1000);
+
+		/*
+		 * We wait for the last triggered sector
+		 */
+		if (l_sect < 0)
+			goto DONE;
+
+		start = get_timer (0);
+		last  = start;
+		addr = (FPWV *)(info->start[l_sect]);
+		while ((addr[0] & 0x0080) != 0x0080) {
+			if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+				return 1;
+			}
+			/* show that we're waiting */
+			if ((now - last) > 1000) {	/* every second */
+				putc ('.');
+				last = now;
+			}
+		}
+		addr = (FPWV *)info->start[0];
+		addr[0] = 0x00F0;	/* reset bank */
+		sect += ssect;
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+DONE:
+	/* reset to read mode */
+	addr = (FPWV *)info->start[0];
+	addr[0] = 0x00F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong wp, data;
+	int rc;
+
+	if (addr & 1) {
+		printf ("unaligned destination not supported\n");
+		return ERR_ALIGN;
+	};
+
+	if ((int) src & 1) {
+		printf ("unaligned source not supported\n");
+		return ERR_ALIGN;
+	};
+
+	wp = addr;
+
+	while (cnt >= 2) {
+		data = *((FPWV *)src);
+		if ((rc = write_word_amd(info, (FPW *)wp, data)) != 0) {
+			return (rc);
+		}
+		src += 2;
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	if (cnt == 1) {
+		data = (*((volatile u8 *) src)) | (*((volatile u8 *) (wp + 1))
+				<< 8);
+		if ((rc = write_word_amd(info, (FPW *)wp, data)) != 0) {
+			return (rc);
+		}
+		src += 1;
+		wp += 1;
+		cnt -= 1;
+	}
+
+	return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
+{
+	ulong start;
+	int flag;
+	FPWV *base;		/* first address in flash bank	*/
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+	base = (FPWV *)(info->start[0]);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[FLASH_CYCLE1] = (FPW)0x00AA;	/* unlock */
+	base[FLASH_CYCLE2] = (FPW)0x0055;	/* unlock */
+	base[FLASH_CYCLE1] = (FPW)0x00A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data	*/
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer (0);
+
+	/* data polling for D7 */
+	while ((*dest & (FPW)0x0080) != (data & (FPW)0x0080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*dest = (FPW)0x00F0;	/* reset bank */
+			return (1);
+		}
+	}
+	return (0);
+}
--- a/board/cmc_pu2/memsetup.S
+++ b/board/cmc_pu2/memsetup.S
@@ -0,0 +1,205 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *		       Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the at91rm9200dk board by
+ * (C) Copyright 2004
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#ifdef CONFIG_BOOTBINFUNC
+/*
+ * some parameters for the board
+ *
+ * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in
+ * turn is based on the boot.bin code from ATMEL
+ *
+ */
+
+/* flash */
+#define MC_PUIA 0xFFFFFF10
+#define MC_PUIA_VAL 0x00000000
+#define MC_PUP 0xFFFFFF50
+#define MC_PUP_VAL 0x00000000
+#define MC_PUER 0xFFFFFF54
+#define MC_PUER_VAL 0x00000000
+#define MC_ASR 0xFFFFFF04
+#define MC_ASR_VAL 0x00000000
+#define MC_AASR 0xFFFFFF08
+#define MC_AASR_VAL 0x00000000
+#define EBI_CFGR 0xFFFFFF64
+#define EBI_CFGR_VAL 0x00000000
+#define SMC2_CSR 0xFFFFFF70
+#define SMC2_CSR_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */
+
+/* clocks */
+#define PLLAR 0xFFFFFC28
+#define PLLAR_VAL 0x202CBE04 /* 207.360 MHz for PCK */
+#define PLLBR 0xFFFFFC2C
+#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
+#define MCKR 0xFFFFFC30
+#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */
+
+/* sdram */
+#define PIOC_ASR 0xFFFFF870
+#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define PIOC_BSR 0xFFFFF874
+#define PIOC_BSR_VAL 0x00000000
+#define PIOC_PDR 0xFFFFF804
+#define PIOC_PDR_VAL 0xFFFF0000
+#define EBI_CSA 0xFFFFFF60
+#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
+#define SDRC_CR 0xFFFFFF98
+#define SDRC_CR_VAL 0x3399c1d4 /* set up the SDRAM */
+#define SDRAM 0x20000000 /* address of the SDRAM */
+#define SDRAM1 0x20000080 /* address of the SDRAM */
+#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
+#define SDRC_MR 0xFFFFFF90
+#define SDRC_MR_VAL 0x00000002 /* Precharge All */
+#define SDRC_MR_VAL1 0x00000004 /* refresh */
+#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
+#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
+#define SDRC_TR 0xFFFFFF94
+#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
+
+
+_MTEXT_BASE:
+#undef START_FROM_MEM
+#ifdef START_FROM_MEM
+	.word	TEXT_BASE-PHYS_FLASH_1
+#else
+	.word	TEXT_BASE
+#endif
+
+.globl lowlevelinit
+lowlevelinit:
+	/* memory control configuration */
+	/* this isn't very elegant, but	 what the heck */
+	ldr	r0, =SMRDATA
+	ldr	r1, _MTEXT_BASE
+	sub	r0, r0, r1
+	add	r2, r0, #80
+0:
+	/* the address */
+	ldr	r1, [r0], #4
+	/* the value */
+	ldr	r3, [r0], #4
+	str	r3, [r1]
+	cmp	r2, r0
+	bne	0b
+	/* delay - this is all done by guess */
+	ldr	r0, =0x00010000
+1:
+	subs	r0, r0, #1
+	bhi	1b
+	ldr	r0, =SMRDATA1
+	ldr	r1, _MTEXT_BASE
+	sub	r0, r0, r1
+	add	r2, r0, #176
+2:
+	/* the address */
+	ldr	r1, [r0], #4
+	/* the value */
+	ldr	r3, [r0], #4
+	str	r3, [r1]
+	cmp	r2, r0
+	bne	2b
+
+	/* everything is fine now */
+	mov	pc, lr
+
+	.ltorg
+
+SMRDATA:
+	.word MC_PUIA
+	.word MC_PUIA_VAL
+	.word MC_PUP
+	.word MC_PUP_VAL
+	.word MC_PUER
+	.word MC_PUER_VAL
+	.word MC_ASR
+	.word MC_ASR_VAL
+	.word MC_AASR
+	.word MC_AASR_VAL
+	.word EBI_CFGR
+	.word EBI_CFGR_VAL
+	.word SMC2_CSR
+	.word SMC2_CSR_VAL
+	.word PLLAR
+	.word PLLAR_VAL
+	.word PLLBR
+	.word PLLBR_VAL
+	.word MCKR
+	.word MCKR_VAL
+	/* SMRDATA is 80 bytes long */
+	/* here there's a delay of 100 */
+SMRDATA1:
+	.word PIOC_ASR
+	.word PIOC_ASR_VAL
+	.word PIOC_BSR
+	.word PIOC_BSR_VAL
+	.word PIOC_PDR
+	.word PIOC_PDR_VAL
+	.word EBI_CSA
+	.word EBI_CSA_VAL
+	.word SDRC_CR
+	.word SDRC_CR_VAL
+	.word SDRC_MR
+	.word SDRC_MR_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRC_MR
+	.word SDRC_MR_VAL1
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRC_MR
+	.word SDRC_MR_VAL2
+	.word SDRAM1
+	.word SDRAM_VAL
+	.word SDRC_TR
+	.word SDRC_TR_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRC_MR
+	.word SDRC_MR_VAL3
+	.word SDRAM
+	.word SDRAM_VAL
+	/* SMRDATA1 is 176 bytes long */
+#endif /* CONFIG_BOOTBINFUNC */
--- a/board/cmc_pu2/u-boot.lds
+++ b/board/cmc_pu2/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/at91rm9200/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
--- a/board/cogent/mb.h
+++ b/board/cogent/mb.h
@@ -54,7 +54,7 @@
 * i.e. they are 8 bytes apart. For big endian addressing, the 8 bit register
 * will be at byte 7 (the address + 7). For little endian addressing, the
 * register will be at byte 0 (the address + 0). To learn the endianess
- * we must include <asm/byteorder.h>
+ * we must include <endian.h>
 *
 * Take the CMA102 and CMA111 motherboards as examples...
 *
@@ -230,16 +230,20 @@

 #ifndef __ASSEMBLY__

-#include <asm/byteorder.h>
+#ifdef USE_HOSTCC
+#include <endian.h>		/* avoid using private kernel header files */
+#else
+#include <asm/byteorder.h>	/* use U-Boot provided headers */
+#endif

 /* a single CMA10x motherboard i/o register */
 typedef
    struct {
-#if defined(__LITTLE_ENDIAN)
+#if __BYTE_ORDER == __LITTLE_ENDIAN
 	unsigned char value;
 #endif
 	unsigned char filler[7];
-#if defined(__BIG_ENDIAN)
+#if __BYTE_ORDER == __BIG_ENDIAN
 	unsigned char value;
 #endif
    }
@@ -357,7 +361,7 @@ cma_mb_dipsw;
 /* V360EPC PCI Bridge */
 typedef
    struct {
-#if defined(__LITTLE_ENDIAN)
+#if __BYTE_ORDER == __LITTLE_ENDIAN
 	unsigned short v3_pci_vendor;		/* 0x00 */
 	unsigned short v3_pci_device;
 	unsigned short v3_pci_cmd;		/* 0x04 */
@@ -436,7 +440,7 @@ typedef
 	unsigned long  reserved8:24;
 	unsigned long  reserved9[7];		/* 0xe4 */
 #endif
-#if defined(__BIG_ENDIAN)
+#if __BYTE_ORDER == __BIG_ENDIAN
 	unsigned short v3_pci_device;		/* 0x00 */
 	unsigned short v3_pci_vendor;
 	unsigned short v3_pci_stat;		/* 0x04 */
--- a/board/cradle/cradle.c
+++ b/board/cradle/cradle.c
@@ -186,7 +186,7 @@ board_init (void)
 	led_code (0xf, YELLOW);

 	/* arch number of HHP Cradle */
-	gd->bd->bi_arch_number = 174;
+	gd->bd->bi_arch_number = MACH_TYPE_HHP_CRADLE;

 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0xa0000100;
--- a/board/cradle/flash.c
+++ b/board/cradle/flash.c
@@ -30,338 +30,330 @@
 #define FLASH_BANK_SIZE 0x400000
 #define MAIN_SECT_SIZE  0x20000

-flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];


 /*-----------------------------------------------------------------------
 */

-ulong flash_init(void)
+ulong flash_init (void)
 {
-   int i, j;
-   ulong size = 0;
+	int i, j;
+	ulong size = 0;

-   for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
-   {
-      ulong flashbase = 0;
-      flash_info[i].flash_id =
-	  (INTEL_MANUFACT & FLASH_VENDMASK) |
-	  (INTEL_ID_28F128J3 & FLASH_TYPEMASK);
-      flash_info[i].size = FLASH_BANK_SIZE;
-      flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-      memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
-      switch (i)
-      {
-	 case 0:
-		flashbase = PHYS_FLASH_1;
-		break;
-	 case 1:
-		flashbase = PHYS_FLASH_2;
-		break;
-	 default:
-		panic("configured too many flash banks!\n");
-		break;
-      }
-      for (j = 0; j < flash_info[i].sector_count; j++)
-      {
-	 flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE;
-      }
-      size += flash_info[i].size;
-   }
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;

-   /* Protect monitor and environment sectors
-    */
-   flash_protect(FLAG_PROTECT_SET,
-		  CFG_FLASH_BASE,
-		  CFG_FLASH_BASE + monitor_flash_len - 1,
-		  &flash_info[0]);
+		flash_info[i].flash_id =
+			(INTEL_MANUFACT & FLASH_VENDMASK) |
+			(INTEL_ID_28F128J3 & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		switch (i) {
+		case 0:
+			flashbase = PHYS_FLASH_1;
+			break;
+		case 1:
+			flashbase = PHYS_FLASH_2;
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] =
+				flashbase + j * MAIN_SECT_SIZE;
+		}
+		size += flash_info[i].size;
+	}

-   flash_protect(FLAG_PROTECT_SET,
-		  CFG_ENV_ADDR,
-		  CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
-		  &flash_info[0]);
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_FLASH_BASE,
+		       CFG_FLASH_BASE + monitor_flash_len - 1,
+		       &flash_info[0]);

-   return size;
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
 }

 /*-----------------------------------------------------------------------
 */
-void flash_print_info  (flash_info_t *info)
+void flash_print_info (flash_info_t * info)
 {
-   int i, j;
+	int i, j;

-   for (j=0; j<CFG_MAX_FLASH_BANKS; j++)
-   {
-      switch (info->flash_id & FLASH_VENDMASK)
-      {
-	 case (INTEL_MANUFACT & FLASH_VENDMASK):
-		printf("Intel: ");
-		break;
-	 default:
-		printf("Unknown Vendor ");
-		break;
-      }
+	for (j = 0; j < CFG_MAX_FLASH_BANKS; j++) {
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case (INTEL_MANUFACT & FLASH_VENDMASK):
+			printf ("Intel: ");
+			break;
+		default:
+			printf ("Unknown Vendor ");
+			break;
+		}

-      switch (info->flash_id & FLASH_TYPEMASK)
-      {
-	 case (INTEL_ID_28F320J3A & FLASH_TYPEMASK):
-		printf("28F320J3A (32Mbit)\n");
-		break;
-	 case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
-		printf("28F128J3 (128Mbit)\n");
-		break;
-	 default:
-		printf("Unknown Chip Type\n");
-		goto Done;
-		break;
-      }
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		case (INTEL_ID_28F320J3A & FLASH_TYPEMASK):
+			printf ("28F320J3A (32Mbit)\n");
+			break;
+		case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
+			printf ("28F128J3 (128Mbit)\n");
+			break;
+		default:
+			printf ("Unknown Chip Type\n");
+			goto Done;
+			break;
+		}

-      printf("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
+		printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);

-      printf("  Sector Start Addresses:");
-      for (i = 0; i < info->sector_count; i++)
-      {
-	 if ((i % 5) == 0)
-	 {
-	    printf ("\n   ");
-	 }
-	 printf (" %08lX%s", info->start[i],
-			info->protect[i] ? " (RO)" : "     ");
-      }
-      printf ("\n");
-      info++;
-   }
+		printf ("  Sector Start Addresses:");
+		for (i = 0; i < info->sector_count; i++) {
+			if ((i % 5) == 0) {
+				printf ("\n   ");
+			}
+			printf (" %08lX%s", info->start[i],
+				info->protect[i] ? " (RO)" : "     ");
+		}
+		printf ("\n");
+		info++;
+	}

-Done:
+Done:	;
 }

 /*-----------------------------------------------------------------------
 */

-int        flash_erase (flash_info_t *info, int s_first, int s_last)
+int flash_erase (flash_info_t * info, int s_first, int s_last)
 {
-   int flag, prot, sect;
-   int rc = ERR_OK;
+	int flag, prot, sect;
+	int rc = ERR_OK;

-   if (info->flash_id == FLASH_UNKNOWN)
-	return ERR_UNKNOWN_FLASH_TYPE;
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;

-   if ((s_first < 0) || (s_first > s_last)) {
-	return ERR_INVAL;
-   }
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}

-   if ((info->flash_id & FLASH_VENDMASK) !=
-	(INTEL_MANUFACT & FLASH_VENDMASK)) {
-	return ERR_UNKNOWN_FLASH_VENDOR;
-   }
+	if ((info->flash_id & FLASH_VENDMASK) !=
+	    (INTEL_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}

-   prot = 0;
-   for (sect=s_first; sect<=s_last; ++sect) {
-      if (info->protect[sect]) {
-	    prot++;
-      }
-   }
-   if (prot)
-	return ERR_PROTECTED;
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot)
+		return ERR_PROTECTED;

-   /*
-    * Disable interrupts which might cause a timeout
-    * here. Remember that our exception vectors are
-    * at address 0 in the flash, and we don't want a
-    * (ticker) exception to happen while the flash
-    * chip is in programming mode.
-    */
-   flag = disable_interrupts();
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	flag = disable_interrupts ();

-   /* Start erase on unprotected sectors */
-   for (sect = s_first; sect<=s_last && !ctrlc(); sect++) {
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {

-      printf("Erasing sector %2d ... ", sect);
+		printf ("Erasing sector %2d ... ", sect);

-      /* arm simple, non interrupt dependent timer */
-      reset_timer_masked();
+		/* arm simple, non interrupt dependent timer */
+		reset_timer_masked ();

-      if (info->protect[sect] == 0) {        /* not protected */
-	  vu_short *addr = (vu_short *)(info->start[sect]);
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_short *addr = (vu_short *) (info->start[sect]);

-	  *addr = 0x20;        /* erase setup */
-	  *addr = 0xD0;        /* erase confirm */
+			*addr = 0x20;	/* erase setup */
+			*addr = 0xD0;	/* erase confirm */

-	  while ((*addr & 0x80) != 0x80) {
-	     if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) {
-		*addr = 0xB0; /* suspend erase */
-		*addr = 0xFF;        /* reset to read mode */
-		rc = ERR_TIMOUT;
-		goto outahere;
-	     }
-	  }
+			while ((*addr & 0x80) != 0x80) {
+				if (get_timer_masked () >
+				    CFG_FLASH_ERASE_TOUT) {
+					*addr = 0xB0;	/* suspend erase */
+					*addr = 0xFF;	/* reset to read mode */
+					rc = ERR_TIMOUT;
+					goto outahere;
+				}
+			}

-	  /* clear status register command */
-	  *addr = 0x50;
-	  /* reset to read mode */
-	  *addr = 0xFF;
-      }
-      printf("ok.\n");
-   }
-   if (ctrlc())
-      printf("User Interrupt!\n");
+			/* clear status register command */
+			*addr = 0x50;
+			/* reset to read mode */
+			*addr = 0xFF;
+		}
+		printf ("ok.\n");
+	}
+	if (ctrlc ())
+		printf ("User Interrupt!\n");

 outahere:

-   /* allow flash to settle - wait 10 ms */
-   udelay_masked(10000);
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked (10000);

-   if (flag)
-      enable_interrupts();
+	if (flag)
+		enable_interrupts ();

-   return rc;
+	return rc;
 }

 /*-----------------------------------------------------------------------
 * Copy memory to flash
 */

-static int write_word (flash_info_t *info, ulong dest, ushort data)
+static int write_word (flash_info_t * info, ulong dest, ushort data)
 {
-   vu_short *addr = (vu_short *)dest, val;
-   int rc = ERR_OK;
-   int flag;
+	vu_short *addr = (vu_short *) dest, val;
+	int rc = ERR_OK;
+	int flag;

-   /* Check if Flash is (sufficiently) erased
-    */
-   if ((*addr & data) != data)
-      return ERR_NOT_ERASED;
+	/* Check if Flash is (sufficiently) erased
+	 */
+	if ((*addr & data) != data)
+		return ERR_NOT_ERASED;

-   /*
-    * Disable interrupts which might cause a timeout
-    * here. Remember that our exception vectors are
-    * at address 0 in the flash, and we don't want a
-    * (ticker) exception to happen while the flash
-    * chip is in programming mode.
-    */
-   flag = disable_interrupts();
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	flag = disable_interrupts ();

-   /* clear status register command */
-   *addr = 0x50;
+	/* clear status register command */
+	*addr = 0x50;

-   /* program set-up command */
-   *addr = 0x40;
+	/* program set-up command */
+	*addr = 0x40;

-   /* latch address/data */
-   *addr = data;
+	/* latch address/data */
+	*addr = data;

-   /* arm simple, non interrupt dependent timer */
-   reset_timer_masked();
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();

-   /* wait while polling the status register */
-   while(((val = *addr) & 0x80) != 0x80)
-   {
-      if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) {
-	  rc = ERR_TIMOUT;
-	  /* suspend program command */
-	  *addr = 0xB0;
-	  goto outahere;
-      }
-   }
+	/* wait while polling the status register */
+	while (((val = *addr) & 0x80) != 0x80) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			rc = ERR_TIMOUT;
+			/* suspend program command */
+			*addr = 0xB0;
+			goto outahere;
+		}
+	}

-   if(val & 0x1A) {        /* check for error */
-      printf("\nFlash write error %02x at address %08lx\n",
-	       (int)val, (unsigned long)dest);
-      if(val & (1<<3)) {
-	 printf("Voltage range error.\n");
-	 rc = ERR_PROG_ERROR;
-	 goto outahere;
-      }
-      if(val & (1<<1)) {
-	 printf("Device protect error.\n");
-	 rc = ERR_PROTECTED;
-	 goto outahere;
-      }
-      if(val & (1<<4)) {
-	 printf("Programming error.\n");
-	 rc = ERR_PROG_ERROR;
-	 goto outahere;
-      }
-      rc = ERR_PROG_ERROR;
-      goto outahere;
-   }
+	if (val & 0x1A) {	/* check for error */
+		printf ("\nFlash write error %02x at address %08lx\n",
+			(int) val, (unsigned long) dest);
+		if (val & (1 << 3)) {
+			printf ("Voltage range error.\n");
+			rc = ERR_PROG_ERROR;
+			goto outahere;
+		}
+		if (val & (1 << 1)) {
+			printf ("Device protect error.\n");
+			rc = ERR_PROTECTED;
+			goto outahere;
+		}
+		if (val & (1 << 4)) {
+			printf ("Programming error.\n");
+			rc = ERR_PROG_ERROR;
+			goto outahere;
+		}
+		rc = ERR_PROG_ERROR;
+		goto outahere;
+	}

 outahere:
-   /* read array command */
-   *addr = 0xFF;
+	/* read array command */
+	*addr = 0xFF;

-   if (flag)
-      enable_interrupts();
+	if (flag)
+		enable_interrupts ();

-   return rc;
+	return rc;
 }

 /*-----------------------------------------------------------------------
 * Copy memory to flash.
 */

-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 {
-   ulong cp, wp;
-   ushort data;
-   int l;
-   int i, rc;
+	ulong cp, wp;
+	ushort data;
+	int l;
+	int i, rc;

-   wp = (addr & ~1);        /* get lower word aligned address */
+	wp = (addr & ~1);	/* get lower word aligned address */

-   /*
-    * handle unaligned start bytes
-    */
-   if ((l = addr - wp) != 0)
-   {
-      data = 0;
-      for (i=0, cp=wp; i<l; ++i, ++cp) {
-	   data = (data >> 8) | (*(uchar *)cp << 8);
-      }
-      for (; i<2 && cnt>0; ++i) {
-	 data = (data >> 8) | (*src++ << 8);
-	 --cnt;
-	 ++cp;
-      }
-      for (; cnt==0 && i<2; ++i, ++cp) {
-	 data = (data >> 8) | (*(uchar *)cp << 8);
-      }
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+		for (; i < 2 && cnt > 0; ++i) {
+			data = (data >> 8) | (*src++ << 8);
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 2; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}

-      if ((rc = write_word(info, wp, data)) != 0) {
-	 return (rc);
-      }
-      wp += 2;
-   }
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+	}

-   /*
-    * handle word aligned part
-    */
-   while (cnt >= 2) {
-      data = *((vu_short*)src);
-      if ((rc = write_word(info, wp, data)) != 0) {
-	  return (rc);
-      }
-      src += 2;
-      wp  += 2;
-      cnt -= 2;
-   }
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 2) {
+		data = *((vu_short *) src);
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 2;
+		wp += 2;
+		cnt -= 2;
+	}

-   if (cnt == 0) {
-      return ERR_OK;
-   }
+	if (cnt == 0) {
+		return ERR_OK;
+	}

-   /*
-    * handle unaligned tail bytes
-    */
-   data = 0;
-   for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
-      data = (data >> 8) | (*src++ << 8);
-      --cnt;
-   }
-   for (; i<2; ++i, ++cp) {
-      data = (data >> 8) | (*(uchar *)cp << 8);
-   }
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 8);
+		--cnt;
+	}
+	for (; i < 2; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *) cp << 8);
+	}

-   return write_word(info, wp, data);
+	return write_word (info, wp, data);
 }
--- a/board/csb226/csb226.c
+++ b/board/csb226/csb226.c
@@ -71,7 +71,7 @@ int board_init (void)
 	/* so we do _nothing_ here */

 	/* arch number of CSB226 board */
-	gd->bd->bi_arch_number = 216;
+	gd->bd->bi_arch_number = MACH_TYPE_CSB226;

 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0xa0000100;
--- a/board/dave/B2/B2.c
+++ b/board/dave/B2/B2.c
@@ -109,7 +109,7 @@ int board_init (void)
    PDATF = temp;

 	/* arch number MACH_TYPE_MBA44B0 */
-	gd->bd->bi_arch_number = 178;
+	gd->bd->bi_arch_number = MACH_TYPE_S3C44B0;

 	/* location of boot parameters */
 	gd->bd->bi_boot_params = 0x0c000100;
--- a/board/dbau1x00/README
+++ b/board/dbau1x00/README
@@ -1,30 +1,40 @@
-By Thomas.Lange@corelatus.se 2003-10-06
+By Thomas.Lange@corelatus.se 2004-Oct-05
 ----------------------------------------
-DbAu1000 is a development board from AMD containing
-an Alchemy AU1000 with mips32 core.
+DbAu1xx0 are development boards from AMD containing
+an Alchemy AU1xx0 series cpu with mips32 core.
+Existing cpu:s are Au1000, Au1100, Au1500 and Au1550

 Limitations & comments
 ----------------------
-I assume that you set board to BIG endian!
-Little endian not tested, most probably broken.
+Support was originally big endian only.
+I have not tested, but several u-boot users report working
+configurations in little endian mode.

 I named the board dbau1x00, to allow
 support for all three development boards
-some day ( dbau1000, dbau1100 and dbau1500 ).
+( dbau1000, dbau1100 and dbau1500 ).
+Now there is a new board called dbau1550 also, which
+should be supported RSN.

-I only have a dbau1000, so all testing is limited
-to this board!
+I only have a dbau1000, so my testing is limited
+to this board.

 The board has two different flash banks, that can
 be selected via dip switch. This makes it possible
 to test new bootloaders without thrashing the YAMON
-boot loader deliviered with board.
+boot loader delivered with board.
+
+NOTE! When you switch between the two boot flashes, the
+base addresses will be swapped.
+Have this in mind when you compile u-boot. TEXT_BASE has
+to match the address where u-boot is located when you
+actually launch.

 Ethernet only supported for mac0.

-Pcmcia only supported for slot 0, only 3.3V.
+PCMCIA only supported for slot 0, only 3.3V.

-Pcmcia IDE tested with Sandisk Compact Flash and
+PCMCIA IDE tested with Sandisk Compact Flash and
 IBM microdrive.

 ###################################
@@ -32,7 +42,7 @@ IBM microdrive.
 ###################################
 If you partition a disk on another system (e.g. laptop),
 all bytes will be swapped on 16bit level when using
-PCMCIA!!!!
+PCMCIA and running cpu in big endian mode!!!!

 This is probably due to an error in Au1000 chip.

--- a/board/dnp1110/dnp1110.c
+++ b/board/dnp1110/dnp1110.c
@@ -39,7 +39,7 @@ int board_init (void)
 	/* so we do _nothing_ here */

 	/* arch number of DNP1110-Board */
-	gd->bd->bi_arch_number = 255;
+	gd->bd->bi_arch_number = MACH_TYPE_DNP1110;

    /* flash vpp on */
    PPDR |= 0x80;	/* assumes LCD controller is off */
--- a/board/ep7312/ep7312.c
+++ b/board/ep7312/ep7312.c
@@ -40,7 +40,7 @@ int board_init (void)
 	IO_LEDFLSH = 0x40;

 	/* arch number MACH_TYPE_EDB7312 */
-	gd->bd->bi_arch_number = 131;
+	gd->bd->bi_arch_number = MACH_TYPE_EDB7312;

 	/* location of boot parameters */
 	gd->bd->bi_boot_params = 0xc0020100;
--- a/board/ep7312/flash.c
+++ b/board/ep7312/flash.c
@@ -109,7 +109,7 @@ void flash_print_info (flash_info_t * info)
 	}
 	printf ("\n");

-  Done:
+Done:	;
 }

 /*-----------------------------------------------------------------------
--- a/board/eric/config.mk
+++ b/board/eric/config.mk
@@ -26,5 +26,4 @@
 #

 #TEXT_BASE = 0xFFF80000
-#TEXT_BASE = 0xFFFC0000
-TEXT_BASE = 0xFFFE0000
+TEXT_BASE = 0xFFFC0000
--- a/board/esd/adciop/Makefile
+++ b/board/esd/adciop/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk

 LIB	= lib$(BOARD).a

-OBJS	= $(BOARD).o flash.o ../common/pci.o
+OBJS	= $(BOARD).o flash.o ../common/misc.o ../common/pci.o

 $(LIB):	$(OBJS)
 	$(AR) crv $@ $(OBJS)
--- a/board/esd/apc405/Makefile
+++ b/board/esd/apc405/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o strataflash.o ../common/misc.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- a/board/esd/apc405/apc405.c
+++ b/board/esd/apc405/apc405.c
@@ -0,0 +1,315 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+
+/* ------------------------------------------------------------------------- */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+extern void lxt971_no_sleep(void);
+
+/* fpga configuration data - gzip compressed and generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+/* Prototypes */
+int gunzip(void *, int, unsigned char *, unsigned long *);
+
+
+#ifdef CONFIG_LCD_USED
+/* logo bitmap data - gzip compressed and generated by bin2c */
+unsigned char logo_bmp[] =
+{
+#include CFG_LCD_LOGO_NAME
+};
+
+/*
+ * include common lcd code (for esd boards)
+ */
+#include "../common/lcd.c"
+
+#include "../common/"CFG_LCD_HEADER_NAME
+#endif /* CONFIG_LCD_USED */
+
+
+int board_early_init_f (void)
+{
+	/*
+	 * First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
+	 */
+	out32(GPIO0_ODR, 0x00000000);        /* no open drain pins      */
+	out32(GPIO0_TCR, CFG_FPGA_PRG);      /* setup for output        */
+	out32(GPIO0_OR,  CFG_FPGA_PRG);      /* set output pins to high */
+	out32(GPIO0_OR, 0);                  /* pull prg low            */
+
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(uicer, 0x00000000);       /* disable all ints */
+	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
+	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
+	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+#if 1 /* test-only */
+	mtebc (epcr, 0xa8400000); /* ebc always driven */
+#else
+	mtebc (epcr, 0x28400000); /* ebc in high-z */
+#endif
+
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_f (void)
+{
+	return 0;  /* dummy implementation */
+}
+
+
+int misc_init_r (void)
+{
+	volatile unsigned short *fpga_mode =
+		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+	volatile unsigned char *duart0_mcr =
+		(unsigned char *)((ulong)DUART0_BA + 4);
+	volatile unsigned char *duart1_mcr =
+		(unsigned char *)((ulong)DUART1_BA + 4);
+	volatile unsigned short *fuji_lcdbl_pwm =
+		(unsigned short *)((ulong)0xf0100200 + 0xa0);
+	unsigned char *dst;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+	unsigned long cntrl0Reg;
+
+	/*
+	 * Setup GPIO pins (CS6+CS7 as GPIO)
+	 */
+	cntrl0Reg = mfdcr(cntrl0);
+	mtdcr(cntrl0, cntrl0Reg | 0x00300000);
+
+	dst = malloc(CFG_FPGA_MAX_SIZE);
+	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+		printf ("GUNZIP ERROR - must RESET board to recover\n");
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i=20; i>0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index=0;index<1000;index++)
+				udelay(1000);
+		}
+		putc ('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	/* restore gpio/cs settings */
+	mtdcr(cntrl0, cntrl0Reg);
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index+1]));
+		index += len+3;
+	}
+	putc ('\n');
+
+	free(dst);
+
+	/*
+	 * Reset FPGA via FPGA_DATA pin
+	 */
+	SET_FPGA(FPGA_PRG | FPGA_CLK);
+	udelay(1000); /* wait 1ms */
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Enable power on PS/2 interface (with reset)
+	 */
+	*fpga_mode |= CFG_FPGA_CTRL_PS2_RESET;
+	for (i=0;i<100;i++)
+		udelay(1000);
+	udelay(1000);
+	*fpga_mode &= ~CFG_FPGA_CTRL_PS2_RESET;
+
+	/*
+	 * Enable interrupts in exar duart mcr[3]
+	 */
+	*duart0_mcr = 0x08;
+	*duart1_mcr = 0x08;
+
+	/*
+	 * Init lcd interface and display logo
+	 */
+	lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
+		 regs_13806_640_480_16bpp,
+		 sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
+		 logo_bmp, sizeof(logo_bmp));
+
+	/*
+	 * Enable microcontroller and setup backlight PWM controller
+	 */
+	*fpga_mode |= 0x001c;
+	*fuji_lcdbl_pwm = 0x00ff;
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	unsigned char str[64];
+	int i = getenv_r ("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming APC405");
+	} else {
+		puts(str);
+	}
+
+	putc ('\n');
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	unsigned long val;
+
+	mtdcr(memcfga, mem_mb0cf);
+	val = mfdcr(memcfgd);
+
+#if 0
+	printf("\nmb0cf=%x\n", val); /* test-only */
+	printf("strap=%x\n", mfdcr(strap)); /* test-only */
+#endif
+
+	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: 16 MB - ok\n");
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef CONFIG_IDE_RESET
+
+void ide_set_reset(int on)
+{
+	volatile unsigned short *fpga_mode =
+		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+
+	/*
+	 * Assert or deassert CompactFlash Reset Pin
+	 */
+	if (on) {		/* assert RESET */
+		*fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
+	} else {		/* release RESET */
+		*fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
+	}
+}
+
+#endif /* CONFIG_IDE_RESET */
+
+/* ------------------------------------------------------------------------- */
--- a/board/esd/apc405/config.mk
+++ b/board/esd/apc405/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ABG405 boards
+#
+
+TEXT_BASE = 0xFFF80000
--- a/board/esd/apc405/fpgadata.c
+++ b/board/esd/apc405/fpgadata.c
--- a/board/esd/apc405/logo_640_480_24bpp.c
+++ b/board/esd/apc405/logo_640_480_24bpp.c
@@ -0,0 +1,235 @@
+  0x1f,0x8b,0x08,0x08,0x85,0xd1,0x0f,0x40,0x00,0x03,0x61,0x62,0x67,0x5f,0x6c,0x6f,
+  0x67,0x6f,0x5f,0x36,0x34,0x30,0x5f,0x34,0x38,0x30,0x2e,0x62,0x6d,0x70,0x00,0xed,
+  0xd9,0xcb,0x91,0x25,0x3b,0x15,0x05,0xd0,0x02,0x03,0x08,0x86,0x98,0x80,0x05,0x18,
+  0xc0,0x1c,0x9f,0x30,0x05,0x53,0x18,0x60,0x08,0x9e,0x14,0x8f,0xe6,0x17,0x74,0xd5,
+  0xad,0xca,0x94,0xce,0x2f,0x33,0xd7,0x8a,0x7c,0x13,0x78,0x71,0xb4,0x25,0xdd,0xd6,
+  0x8e,0x86,0x3f,0xfe,0xe9,0x0f,0xbf,0xfd,0xcd,0xdb,0x3f,0xfd,0xe1,0x97,0x7f,0x7e,
+  0xff,0xcb,0x3f,0x7f,0xfe,0xf5,0xdb,0xdb,0xdf,0x7f,0xf5,0xf6,0xf6,0xab,0xb7,0xdf,
+  0xfd,0xf8,0xcf,0xdf,0x7e,0xf9,0xef,0xff,0xf6,0xcb,0xbf,0xf2,0xb7,0x7f,0xfd,0x6b,
+  0x3f,0xfc,0xf9,0x2f,0x7f,0xf9,0x2b,0x00,0x50,0xeb,0x0d,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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+  0x63,0xd7,0xe6,0xbc,0x4a,0x18,0x3b,0x0d,0x38,0xa6,0xf2,0xb5,0x9c,0xd6,0x3b,0xed,
+  0xb5,0x38,0xed,0x40,0xea,0xef,0xb7,0xce,0x5a,0xad,0x84,0x97,0xd1,0xa9,0x81,0xdf,
+  0x4e,0x8e,0x9a,0xb6,0x36,0xe7,0x8b,0x60,0xc0,0x01,0x95,0x0f,0xe6,0xc0,0xba,0x69,
+  0x2f,0xc4,0x81,0x67,0x52,0x7c,0xbf,0x45,0xd6,0x6a,0x25,0xbc,0x8c,0x4e,0x0d,0xfc,
+  0x76,0x72,0xd4,0xb4,0xb5,0x39,0x05,0xc1,0xe0,0xee,0xca,0x5e,0xcb,0x81,0x5d,0xd3,
+  0xde,0x86,0x5d,0x5f,0x92,0x51,0x61,0x3e,0x84,0x3b,0x5f,0x04,0xe1,0xf5,0x71,0xb2,
+  0x91,0xbe,0x99,0x1c,0x35,0x6d,0x6d,0x4e,0x41,0x30,0x78,0x80,0xb2,0xd7,0x72,0x5a,
+  0xcb,0xb4,0xf7,0x60,0xe3,0x97,0x61,0x4e,0x92,0xcf,0xc2,0x9d,0x2f,0x82,0xf0,0xfa,
+  0x38,0xd9,0x48,0xdf,0x4c,0x8e,0x9a,0xb6,0x36,0xa7,0x20,0x18,0x3c,0x43,0xcd,0x83,
+  0x39,0xad,0x65,0xda,0x4b,0xb0,0xfd,0x8b,0x35,0x21,0xc3,0xeb,0x70,0xe7,0x8b,0x20,
+  0xbc,0x3e,0x4e,0x36,0xd2,0x37,0x93,0xa3,0xa6,0xad,0xcd,0x29,0x08,0x06,0x8f,0x51,
+  0xf0,0x60,0x4e,0xeb,0x97,0x51,0x61,0x66,0x1e,0xd1,0x29,0x13,0x32,0xbc,0x0e,0x77,
+  0xb2,0x0b,0x32,0xba,0xe3,0xd4,0xcc,0x6f,0x87,0x47,0x4d,0x5b,0x9b,0x53,0x10,0x0c,
+  0x1e,0xa3,0xe0,0xb5,0x1c,0x58,0x2e,0xa3,0xc2,0x74,0x1d,0x54,0x94,0xf6,0x00,0x5f,
+  0x86,0x3b,0xd9,0x05,0x19,0xdd,0x71,0x6a,0xe6,0xb7,0xc3,0xa3,0xa6,0xad,0xcd,0x29,
+  0x08,0x06,0x4f,0x92,0xfd,0x60,0x16,0xd7,0xca,0x91,0x9c,0xa3,0xc2,0x5c,0x28,0x5b,
+  0x6c,0xe6,0x0a,0x67,0xbb,0x20,0xa3,0x3b,0x4e,0xcd,0xfc,0x76,0x78,0xd4,0xb4,0xb5,
+  0x39,0x05,0xc1,0xe0,0x49,0x0a,0xde,0xcc,0xca,0x4e,0x39,0x12,0x72,0x54,0x98,0xc6,
+  0x78,0x51,0xda,0x03,0x7c,0x19,0xee,0x4c,0x17,0x64,0x74,0xc7,0xc9,0x46,0xfa,0x66,
+  0x78,0xd4,0xb4,0xb5,0x39,0x05,0xc1,0xe0,0x61,0x6e,0x53,0x28,0x07,0x43,0xce,0x49,
+  0xd2,0x9e,0x30,0x44,0xef,0xea,0xdf,0x85,0x3b,0xd3,0x05,0x19,0xdd,0x71,0xb2,0x91,
+  0xbe,0x19,0x1e,0x35,0x6d,0x6d,0x4e,0x41,0x30,0x78,0x9e,0xd4,0x37,0xb3,0xb2,0xef,
+  0x8e,0x84,0x1c,0x15,0xa6,0x3d,0xe1,0xbe,0xc6,0xa5,0x0f,0x84,0x3b,0xd3,0x05,0x19,
+  0xdd,0x71,0xb2,0x91,0xbe,0x19,0x1e,0x35,0x6d,0x6d,0x4e,0x41,0x30,0x78,0xa4,0xbc,
+  0x67,0xb3,0xb8,0xef,0x8e,0x24,0x1c,0x15,0xe6,0x72,0xf1,0xa2,0xd2,0x56,0x38,0xd5,
+  0x05,0x19,0xc5,0x71,0xbe,0x94,0xbe,0x9a,0x1f,0x35,0x6d,0x6d,0x4e,0x41,0x30,0x78,
+  0xa4,0xbc,0x97,0xb3,0xb2,0x4d,0x0e,0xc6,0x1b,0x15,0xa6,0x37,0xe1,0xbe,0xc6,0xa5,
+  0x0f,0x84,0x3b,0xd3,0x05,0x19,0xc5,0x71,0xbe,0x94,0x5e,0xce,0x5f,0x1b,0xf5,0xe9,
+  0xb4,0xc0,0x51,0xe1,0xd3,0xe0,0x91,0xf2,0x1e,0xcf,0xca,0xbe,0x3b,0x12,0x6f,0x4e,
+  0x92,0x09,0x21,0x37,0x75,0xad,0x7b,0x2c,0x5c,0x8e,0xec,0x00,0xb1,0x5b,0x08,0x3f,
+  0x99,0x8c,0x39,0xf0,0x78,0x49,0x8f,0x67,0x65,0xdf,0x1d,0x89,0x37,0x27,0xc9,0x84,
+  0x90,0x9b,0xba,0xd6,0x3d,0x9c,0x2f,0x41,0xef,0xea,0x67,0x5d,0x2b,0x18,0x3c,0x5b,
+  0xf8,0xfb,0x59,0xd9,0x77,0x47,0xb2,0x8d,0x0a,0x33,0x21,0xe4,0x8e,0xae,0x75,0x0f,
+  0xe7,0x6b,0x2d,0x8e,0x8c,0xd5,0xcf,0x1a,0x9b,0x2d,0xe2,0x7a,0xe1,0x7e,0x62,0xdf,
+  0xcf,0xe2,0xbe,0x3b,0x12,0x6c,0x54,0x98,0x8b,0x26,0xdc,0xcf,0x59,0xa1,0xb7,0x35,
+  0xc2,0x57,0x5f,0x30,0x36,0xdb,0xf6,0xdd,0xc2,0x5d,0xc5,0x3e,0xa1,0x95,0x6d,0x72,
+  0x24,0xd5,0xa8,0x30,0x17,0x4d,0xb8,0x9f,0xb3,0x42,0x6f,0x6b,0x84,0xaf,0x1e,0x9b,
+  0x76,0x6c,0x30,0x78,0xbc,0xc0,0x57,0xb4,0xb2,0x4d,0x8e,0xa4,0x9a,0x93,0xe4,0xba,
+  0x09,0xf7,0x73,0x56,0xe8,0x2d,0x8e,0xf0,0xd5,0x63,0xa3,0x4e,0xce,0x06,0x8f,0x17,
+  0xf5,0x90,0x56,0xb6,0xc9,0x91,0x48,0x73,0x92,0xb4,0xc7,0xdb,0x7c,0x09,0xbb,0xd6,
+  0x3d,0x9c,0xaf,0xb5,0x38,0xc2,0x57,0x0f,0x8f,0x3a,0x36,0x18,0x70,0xc1,0xbe,0x9b,
+  0x96,0x27,0xef,0xcc,0x1b,0x13,0x86,0x44,0x2d,0xd2,0xd8,0x1d,0xb1,0x4b,0x27,0x45,
+  0x1d,0x1b,0x0c,0x88,0x78,0x4e,0x8b,0x0b,0xe5,0xc8,0x1f,0xf0,0x39,0x49,0xe6,0x9f,
+  0x55,0x52,0xda,0x22,0x8d,0xc5,0x11,0xb8,0xf4,0x6d,0x72,0x9e,0xcd,0x06,0x6c,0x3f,
+  0xa7,0xd3,0x6a,0x65,0x4e,0x92,0xe1,0x07,0x95,0x17,0xb5,0x48,0x63,0x77,0x04,0x2e,
+  0x9d,0x9a,0xb3,0x2c,0xea,0x42,0x30,0xe0,0x87,0x9d,0x17,0x75,0x5a,0xad,0xcc,0x49,
+  0xd2,0x78,0x44,0x9b,0x3d,0xd8,0xb5,0xee,0xc9,0x94,0x7d,0xf5,0x11,0xb8,0x74,0x52,
+  0xc2,0xca,0xb4,0x3b,0xd9,0x80,0x8d,0x77,0x75,0x5a,0xad,0x74,0x95,0xdd,0xc0,0x2f,
+  0xf5,0xc7,0x90,0xb1,0xee,0xc9,0x94,0x7d,0x0d,0x12,0xb8,0x74,0x52,0xc2,0x9a,0xc0,
+  0x9b,0xa9,0x80,0xff,0x58,0x7b,0x5a,0xa7,0xd5,0x4a,0x7b,0xeb,0xcd,0xf9,0x52,0x7f,
+  0x09,0x19,0xeb,0x9e,0x4c,0xd9,0xd7,0x23,0x81,0x4b,0x87,0x67,0x2b,0x8b,0x1d,0x18,
+  0x0c,0x58,0x7a,0x5d,0xa7,0xd5,0x4a,0x7b,0xeb,0xcd,0xf9,0x52,0x7f,0x06,0x19,0xeb,
+  0x9e,0x4c,0xd9,0xd7,0x23,0x51,0x4b,0x87,0x07,0xab,0x49,0x9e,0x11,0x0c,0x58,0x7a,
+  0x5d,0xa7,0x35,0x4b,0x7b,0xf1,0x4d,0xf8,0x52,0x7f,0x03,0x49,0xeb,0x52,0x4a,0xe7,
+  0xc2,0x3c,0x67,0x1f,0xd8,0x69,0xe5,0xd2,0xde,0x7d,0x13,0xbe,0xa4,0xdb,0xcf,0x5b,
+  0x97,0x1e,0x9a,0x17,0xe6,0x39,0xfe,0xc0,0x4e,0x2b,0x97,0xf6,0xee,0x6b,0xff,0x32,
+  0xee,0xbd,0x60,0x69,0x00,0xfe,0xeb,0xc8,0x03,0x3b,0xad,0x5f,0xda,0xeb,0xaf,0xfd,
+  0x0b,0xbc,0xee,0xb2,0xa5,0x01,0xf8,0xc9,0x91,0x37,0x76,0x5a,0xc5,0xb4,0x37,0x60,
+  0xe3,0x17,0x7b,0xd7,0x95,0xab,0x03,0xf0,0xd1,0xd7,0x6f,0xec,0xb4,0x96,0x69,0x2f,
+  0xc1,0xae,0x2f,0xf0,0x96,0x5b,0x02,0x00,0xf0,0xd1,0x17,0x6f,0xec,0xb4,0xa2,0x69,
+  0xef,0xc1,0x96,0x2f,0xea,0x7e,0xbb,0x02,0x00,0xf0,0xca,0xab,0x67,0x76,0x5a,0xd7,
+  0xb4,0x57,0xe1,0xb4,0x03,0x39,0x78,0xb3,0x8d,0x01,0x00,0x58,0x30,0xb0,0x6e,0xda,
+  0x0b,0x71,0xd4,0x69,0x14,0x1c,0x17,0x00,0x2d,0xa6,0x95,0x4e,0x7b,0x27,0x4e,0x38,
+  0x84,0xca,0xbb,0x03,0xa0,0xc5,0xb4,0xea,0x69,0x6f,0xc6,0xc6,0xbd,0xb7,0xdc,0x1d,
+  0x00,0x2d,0xa6,0x75,0x50,0x7b,0x45,0xb6,0xec,0xba,0xeb,0xe2,0x00,0xe8,0x32,0xad,
+  0x89,0xda,0x8b,0xf2,0x12,0x8d,0x76,0xad,0xb4,0x00,0x7c,0x74,0xd7,0x86,0xba,0x31,
+  0x17,0x01,0x00,0xc5,0x94,0x2f,0x00,0x14,0x53,0xbe,0x00,0x50,0xcc,0xff,0x05,0x00,
+  0x00,0xc5,0x94,0x2f,0xc0,0xa3,0x78,0xcc,0x27,0x08,0x2c,0x5f,0x57,0x06,0x70,0x15,
+  0xde,0xf3,0x5e,0xca,0x17,0xe0,0xc9,0x3c,0xec,0x2d,0x94,0x2f,0x00,0xff,0xe2,0x79,
+  0xaf,0x11,0xdb,0xbc,0x6e,0x07,0xe0,0x1e,0xbc,0xf3,0xa9,0x94,0x2f,0x00,0x5f,0xf3,
+  0xe0,0x87,0x53,0xbe,0x00,0x1c,0xe4,0xf1,0x0f,0xa1,0x79,0x01,0x58,0xa0,0x0b,0x96,
+  0x85,0x37,0xaf,0x33,0x07,0x78,0x1a,0x8d,0x70,0x8a,0xda,0x05,0x20,0x8a,0x82,0x38,
+  0xc2,0xdf,0x79,0x01,0x48,0xa5,0x32,0x7e,0xa2,0x79,0x01,0x28,0xa3,0x3b,0xde,0xd2,
+  0x9a,0xf7,0x39,0x07,0x08,0xc0,0xb2,0xa7,0xb5,0x49,0x5e,0xe7,0xde,0xef,0xac,0x00,
+  0x28,0x70,0xfb,0x5a,0xd1,0xbc,0x00,0x8c,0x75,0xcb,0xc6,0x51,0xbb,0x00,0x5c,0xc5,
+  0x0d,0x3a,0xc8,0x5f,0x78,0x01,0xb8,0x81,0xc9,0xdd,0x94,0x5d,0xb5,0x3a,0x17,0x80,
+  0x76,0xed,0xcd,0x55,0xd6,0xb6,0x6a,0x17,0x80,0xb1,0xea,0xdb,0x50,0xf3,0x02,0xc0,
+  0x47,0xed,0xa5,0xa9,0x73,0x01,0x78,0xb2,0xf6,0x26,0x55,0xb5,0x00,0xd0,0xde,0xb6,
+  0x3a,0x17,0x00,0x3e,0xa5,0x5e,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xea,0xfc,0x03,0x26,
+  0x84,0x0a,0xd6,0x36,0x10,0x0e,0x00,
--- a/board/esd/apc405/strataflash.c
+++ b/board/esd/apc405/strataflash.c
@@ -0,0 +1,789 @@
+/*
+ * (C) Copyright 2002
+ * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#undef  DEBUG_FLASH
+/*
+ * This file implements a Common Flash Interface (CFI) driver for ppcboot.
+ * The width of the port and the width of the chips are determined at initialization.
+ * These widths are used to calculate the address for access CFI data structures.
+ * It has been tested on an Intel Strataflash implementation.
+ *
+ * References
+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
+ *
+ * TODO
+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
+ * Add support for other command sets Use the PRI and ALT to determine command set
+ * Verify erase and program timeouts.
+ */
+
+#define FLASH_CMD_CFI			0x98
+#define FLASH_CMD_READ_ID		0x90
+#define FLASH_CMD_RESET			0xff
+#define FLASH_CMD_BLOCK_ERASE		0x20
+#define FLASH_CMD_ERASE_CONFIRM		0xD0
+#define FLASH_CMD_WRITE			0x40
+#define FLASH_CMD_PROTECT		0x60
+#define FLASH_CMD_PROTECT_SET		0x01
+#define FLASH_CMD_PROTECT_CLEAR		0xD0
+#define FLASH_CMD_CLEAR_STATUS		0x50
+#define FLASH_CMD_WRITE_TO_BUFFER       0xE8
+#define FLASH_CMD_WRITE_BUFFER_CONFIRM  0xD0
+
+#define FLASH_STATUS_DONE		0x80
+#define FLASH_STATUS_ESS		0x40
+#define FLASH_STATUS_ECLBS		0x20
+#define FLASH_STATUS_PSLBS		0x10
+#define FLASH_STATUS_VPENS		0x08
+#define FLASH_STATUS_PSS		0x04
+#define FLASH_STATUS_DPS		0x02
+#define FLASH_STATUS_R			0x01
+#define FLASH_STATUS_PROTECT		0x01
+
+#define FLASH_OFFSET_CFI		0x55
+#define FLASH_OFFSET_CFI_RESP		0x10
+#define FLASH_OFFSET_WTOUT		0x1F
+#define FLASH_OFFSET_WBTOUT             0x20
+#define FLASH_OFFSET_ETOUT		0x21
+#define FLASH_OFFSET_CETOUT             0x22
+#define FLASH_OFFSET_WMAX_TOUT		0x23
+#define FLASH_OFFSET_WBMAX_TOUT         0x24
+#define FLASH_OFFSET_EMAX_TOUT		0x25
+#define FLASH_OFFSET_CEMAX_TOUT         0x26
+#define FLASH_OFFSET_SIZE		0x27
+#define FLASH_OFFSET_INTERFACE          0x28
+#define FLASH_OFFSET_BUFFER_SIZE        0x2A
+#define FLASH_OFFSET_NUM_ERASE_REGIONS	0x2C
+#define FLASH_OFFSET_ERASE_REGIONS	0x2D
+#define FLASH_OFFSET_PROTECT		0x02
+#define FLASH_OFFSET_USER_PROTECTION    0x85
+#define FLASH_OFFSET_INTEL_PROTECTION   0x81
+
+#define FLASH_MAN_CFI			0x01000000
+
+typedef union {
+	unsigned char c;
+	unsigned short w;
+	unsigned long l;
+} cfiword_t;
+
+typedef union {
+	unsigned char * cp;
+	unsigned short *wp;
+	unsigned long *lp;
+} cfiptr_t;
+
+#define NUM_ERASE_REGIONS 4
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c);
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf);
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_detect_cfi(flash_info_t * info);
+static ulong flash_get_size (ulong base, int banknum);
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
+#endif
+/*-----------------------------------------------------------------------
+ * create an address based on the offset and the port width
+ */
+inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset)
+{
+	return ((uchar *)(info->start[sect] + (offset * info->portwidth)));
+}
+/*-----------------------------------------------------------------------
+ * read a character at a port width address
+ */
+inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
+{
+	uchar *cp;
+	cp = flash_make_addr(info, 0, offset);
+	return (cp[info->portwidth - 1]);
+}
+
+/*-----------------------------------------------------------------------
+ * read a short word by swapping for ppc format.
+ */
+ushort flash_read_ushort(flash_info_t * info, int sect,  uchar offset)
+{
+    uchar * addr;
+
+    addr = flash_make_addr(info, sect, offset);
+    return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ * read a long word by picking the least significant byte of each maiximum
+ * port size word. Swap for ppc format.
+ */
+ulong flash_read_long(flash_info_t * info, int sect,  uchar offset)
+{
+    uchar * addr;
+
+    addr = flash_make_addr(info, sect, offset);
+    return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) |
+	    (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size;
+	int i;
+	unsigned long  address;
+
+
+	/* The flash is positioned back to back, with the demultiplexing of the chip
+	 * based on the A24 address line.
+	 *
+	 */
+
+	address = CFG_FLASH_BASE;
+	size = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		size += flash_info[i].size = flash_get_size(address, i);
+		address += CFG_FLASH_INCREMENT;
+		if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i,
+				flash_info[0].size, flash_info[i].size<<20);
+		}
+	}
+
+#if 0 /* test-only */
+	/* Monitor protection ON by default */
+#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
+	for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+CFG_MONITOR_LEN-1; i++)
+		(void)flash_real_protect(&flash_info[0], i, 1);
+#endif
+#else
+	/* monitor protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+		       - CFG_MONITOR_LEN,
+		       - 1, &flash_info[1]);
+#endif
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int rcode = 0;
+	int prot;
+	int sect;
+
+	if( info->flash_id != FLASH_MAN_CFI) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) { /* not protected */
+			flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
+
+			if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) {
+				rcode = 1;
+			} else
+				printf(".");
+		}
+	}
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id != FLASH_MAN_CFI) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	printf("CFI conformant FLASH (%d x %d)",
+	       (info->portwidth	 << 3 ), (info->chipwidth  << 3 ));
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+	printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
+	       info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+#ifdef CFG_FLASH_EMPTY_INFO
+		int k;
+		int size;
+		int erased;
+		volatile unsigned long *flash;
+
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count-1))
+		  size = info->start[i+1] - info->start[i];
+		else
+		  size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;        /* divide by 4 for longword access */
+		for (k=0; k<size; k++)
+		  {
+		    if (*flash++ != 0xffffffff)
+		      {
+			erased = 0;
+			break;
+		      }
+		  }
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		/* print empty and read-only info */
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   ");
+#else
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+#endif
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong wp;
+	ulong cp;
+	int aln;
+	cfiword_t cword;
+	int i, rc;
+
+	/* get lower aligned address */
+	wp = (addr & ~(info->portwidth - 1));
+
+	/* handle unaligned start */
+	if((aln = addr - wp) != 0) {
+		cword.l = 0;
+		cp = wp;
+		for(i=0;i<aln; ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *)cp));
+
+		for(; (i< info->portwidth) && (cnt > 0) ; i++) {
+			flash_add_byte(info, &cword, *src++);
+			cnt--;
+			cp++;
+		}
+		for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *)cp));
+		if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp = cp;
+	}
+
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+	while(cnt >= info->portwidth) {
+		i = info->buffer_size > cnt? cnt: info->buffer_size;
+		if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
+			return rc;
+		wp += i;
+		src += i;
+		cnt -=i;
+	}
+#else
+	/* handle the aligned part */
+	while(cnt >= info->portwidth) {
+		cword.l = 0;
+		for(i = 0; i < info->portwidth; i++) {
+			flash_add_byte(info, &cword, *src++);
+		}
+		if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp += info->portwidth;
+		cnt -= info->portwidth;
+	}
+#endif /* CFG_FLASH_USE_BUFFER_WRITE */
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	cword.l = 0;
+	for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) {
+		flash_add_byte(info, &cword, *src++);
+		--cnt;
+	}
+	for (; i<info->portwidth; ++i, ++cp) {
+		flash_add_byte(info, & cword, (*(uchar *)cp));
+	}
+
+	return flash_write_cfiword(info, wp, cword);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	int retcode = 0;
+
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
+	if(prot)
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
+	else
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
+
+	if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
+					 prot?"protect":"unprotect")) == 0) {
+
+		info->protect[sector] = prot;
+		/* Intel's unprotect unprotects all locking */
+		if(prot == 0) {
+			int i;
+			for(i = 0 ; i<info->sector_count; i++) {
+				if(info->protect[i])
+					flash_real_protect(info, i, 1);
+			}
+		}
+	}
+
+	return retcode;
+}
+/*-----------------------------------------------------------------------
+ *  wait for XSR.7 to be set. Time out with an error if it does not.
+ *  This routine does not set the flash to read-array mode.
+ */
+static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+	ulong start;
+
+	/* Wait for command completion */
+	start = get_timer (0);
+	while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
+		if (get_timer(start) > info->erase_blk_tout) {
+			printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]);
+			flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+			return ERR_TIMOUT;
+		}
+	}
+	return ERR_OK;
+}
+/*-----------------------------------------------------------------------
+ * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
+ * This routine sets the flash to read-array mode.
+ */
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+	int retcode;
+	retcode = flash_status_check(info, sector, tout, prompt);
+	if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) {
+		retcode = ERR_INVAL;
+		printf("Flash %s error at address %lx\n", prompt,info->start[sector]);
+		if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){
+			printf("Command Sequence Error.\n");
+		} else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){
+			printf("Block Erase Error.\n");
+			retcode = ERR_NOT_ERASED;
+		} else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
+			printf("Locking Error\n");
+		}
+		if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){
+			printf("Block locked.\n");
+			retcode = ERR_PROTECTED;
+		}
+		if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
+			printf("Vpp Low Error.\n");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+	return retcode;
+}
+/*-----------------------------------------------------------------------
+ */
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c)
+{
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cword->c = c;
+		break;
+	case FLASH_CFI_16BIT:
+		cword->w = (cword->w << 8) | c;
+		break;
+	case FLASH_CFI_32BIT:
+		cword->l = (cword->l << 8) | c;
+	}
+}
+
+
+/*-----------------------------------------------------------------------
+ * make a proper sized command based on the port and chip widths
+ */
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf)
+{
+	int i;
+	uchar *cp = (uchar *)cmdbuf;
+	for(i=0; i< info->portwidth; i++)
+		*cp++ = ((i+1) % info->chipwidth) ? '\0':cmd;
+}
+
+/*
+ * Write a proper sized command to the correct address
+ */
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+
+	volatile cfiptr_t addr;
+	cfiword_t cword;
+	addr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		*addr.cp = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		*addr.wp = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		*addr.lp = cword.l;
+		break;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = (cptr.cp[0] == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = (cptr.wp[0] == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = (cptr.lp[0] == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+/*-----------------------------------------------------------------------
+ */
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = ((cptr.lp[0] & cword.l) == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ * detect if flash is compatible with the Common Flash Interface (CFI)
+ * http://www.jedec.org/download/search/jesd68.pdf
+ *
+*/
+static int flash_detect_cfi(flash_info_t * info)
+{
+
+	for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT;
+	    info->portwidth <<= 1) {
+		for(info->chipwidth =FLASH_CFI_BY8;
+		    info->chipwidth <= info->portwidth;
+		    info->chipwidth <<= 1) {
+			flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+			flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
+			if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
+			   flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
+			   flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y'))
+				return 1;
+		}
+	}
+	return 0;
+}
+/*
+ * The following code cannot be run from FLASH!
+ *
+ */
+static ulong flash_get_size (ulong base, int banknum)
+{
+	flash_info_t * info = &flash_info[banknum];
+	int i, j;
+	int sect_cnt;
+	unsigned long sector;
+	unsigned long tmp;
+	int size_ratio;
+	uchar num_erase_regions;
+	int  erase_region_size;
+	int  erase_region_count;
+
+	info->start[0] = base;
+
+	if(flash_detect_cfi(info)){
+#ifdef DEBUG_FLASH
+		printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
+#endif
+		size_ratio = info->portwidth / info->chipwidth;
+		num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
+#ifdef DEBUG_FLASH
+		printf("found %d erase regions\n", num_erase_regions);
+#endif
+		sect_cnt = 0;
+		sector = base;
+		for(i = 0 ; i < num_erase_regions; i++) {
+			if(i > NUM_ERASE_REGIONS) {
+				printf("%d erase regions found, only %d used\n",
+				       num_erase_regions, NUM_ERASE_REGIONS);
+				break;
+			}
+			tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS);
+			erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128;
+			tmp >>= 16;
+			erase_region_count = (tmp & 0xffff) +1;
+			for(j = 0; j< erase_region_count; j++) {
+				info->start[sect_cnt] = sector;
+				sector += (erase_region_size * size_ratio);
+				info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT);
+				sect_cnt++;
+			}
+		}
+
+		info->sector_count = sect_cnt;
+		/* multiply the size by the number of chips */
+		info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio;
+		info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
+		info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
+		info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
+		info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000;
+		info->flash_id = FLASH_MAN_CFI;
+	}
+
+	flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+	return(info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
+{
+
+	cfiptr_t ctladdr;
+	cfiptr_t cptr;
+	int flag;
+
+	ctladdr.cp = flash_make_addr(info, 0, 0);
+	cptr.cp = (uchar *)dest;
+
+
+	/* Check if Flash is (sufficiently) erased */
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		flag = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		flag = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		flag = ((cptr.lp[0] & cword.l)	== cword.l);
+		break;
+	default:
+		return 2;
+	}
+	if(!flag)
+		return 2;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
+
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cptr.cp[0] = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		cptr.wp[0] = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		cptr.lp[0] = cword.l;
+		break;
+	}
+
+	/* re-enable interrupts if necessary */
+	if(flag)
+		enable_interrupts();
+
+	return flash_full_status_check(info, 0, info->write_tout, "write");
+}
+
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+
+/* loop through the sectors from the highest address
+ * when the passed address is greater or equal to the sector address
+ * we have a match
+ */
+static int find_sector(flash_info_t *info, ulong addr)
+{
+	int sector;
+	for(sector = info->sector_count - 1; sector >= 0; sector--) {
+		if(addr >= info->start[sector])
+			break;
+	}
+	return sector;
+}
+
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len)
+{
+
+	int sector;
+	int cnt;
+	int retcode;
+	volatile cfiptr_t src;
+	volatile cfiptr_t dst;
+
+	src.cp = cp;
+	dst.cp = (uchar *)dest;
+	sector = find_sector(info, dest);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
+	if((retcode = flash_status_check(info, sector, info->buffer_write_tout,
+					 "write to buffer")) == ERR_OK) {
+		switch(info->portwidth) {
+		case FLASH_CFI_8BIT:
+			cnt = len;
+			break;
+		case FLASH_CFI_16BIT:
+			cnt = len >> 1;
+			break;
+		case FLASH_CFI_32BIT:
+			cnt = len >> 2;
+			break;
+		default:
+			return ERR_INVAL;
+			break;
+		}
+		flash_write_cmd(info, sector, 0, (uchar)cnt-1);
+		while(cnt-- > 0) {
+			switch(info->portwidth) {
+			case FLASH_CFI_8BIT:
+				*dst.cp++ = *src.cp++;
+				break;
+			case FLASH_CFI_16BIT:
+				*dst.wp++ = *src.wp++;
+				break;
+			case FLASH_CFI_32BIT:
+				*dst.lp++ = *src.lp++;
+				break;
+			default:
+				return ERR_INVAL;
+				break;
+			}
+		}
+		flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM);
+		retcode = flash_full_status_check(info, sector, info->buffer_write_tout,
+					     "buffer write");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	return retcode;
+}
+#endif /* CFG_USE_FLASH_BUFFER_WRITE */
--- a/board/esd/apc405/u-boot.lds
+++ b/board/esd/apc405/u-boot.lds
@@ -0,0 +1,148 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/405gp_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
--- a/board/esd/ar405/Makefile
+++ b/board/esd/ar405/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk

 LIB	= lib$(BOARD).a

-OBJS	= $(BOARD).o flash.o
+OBJS	= $(BOARD).o flash.o ../common/misc.o

 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS)
--- a/board/esd/ar405/ar405.c
+++ b/board/esd/ar405/ar405.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2001
+ * (C) Copyright 2001-2004
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * See file CREDITS for list of people who contributed to this
@@ -28,6 +28,7 @@

 /*cmd_boot.c*/
 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+extern void lxt971_no_sleep(void);

 /* ------------------------------------------------------------------------- */

@@ -40,6 +41,10 @@ const unsigned char fpgadata[] = {
 #include "fpgadata.c"
 };

+const unsigned char fpgadata_xl30[] = {
+#include "fpgadata_xl30.c"
+};
+
 /*
 * include common fpga code (for esd boards)
 */
@@ -64,45 +69,52 @@ int board_early_init_f (void)
 	/*
 	 * Boot onboard FPGA
 	 */
+	/* first try 40er image */
+	gd->board_type = 40;
 	status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
 	if (status != 0) {
-		/* booting FPGA failed */
+		/* try xl30er image */
+		gd->board_type = 30;
+		status = fpga_boot ((unsigned char *) fpgadata_xl30, sizeof (fpgadata_xl30));
+		if (status != 0) {
+			/* booting FPGA failed */
 #ifndef FPGA_DEBUG
-		/* set up serial port with default baudrate */
-		(void) get_clocks ();
-		gd->baudrate = CONFIG_BAUDRATE;
-		serial_init ();
-		console_init_f ();
+			/* set up serial port with default baudrate */
+			(void) get_clocks ();
+			gd->baudrate = CONFIG_BAUDRATE;
+			serial_init ();
+			console_init_f ();
 #endif
-		printf ("\nFPGA: Booting failed ");
-		switch (status) {
-		case ERROR_FPGA_PRG_INIT_LOW:
-			printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
-			break;
-		case ERROR_FPGA_PRG_INIT_HIGH:
-			printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
-			break;
-		case ERROR_FPGA_PRG_DONE:
-			printf ("(Timeout: DONE not high after programming FPGA)\n ");
-			break;
-		}
+			printf ("\nFPGA: Booting failed ");
+			switch (status) {
+			case ERROR_FPGA_PRG_INIT_LOW:
+				printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+				break;
+			case ERROR_FPGA_PRG_INIT_HIGH:
+				printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+				break;
+			case ERROR_FPGA_PRG_DONE:
+				printf ("(Timeout: DONE not high after programming FPGA)\n ");
+				break;
+			}

-		/* display infos on fpgaimage */
-		index = 15;
-		for (i = 0; i < 4; i++) {
-			len = fpgadata[index];
-			printf ("FPGA: %s\n", &(fpgadata[index + 1]));
-			index += len + 3;
+			/* display infos on fpgaimage */
+			index = 15;
+			for (i = 0; i < 4; i++) {
+				len = fpgadata[index];
+				printf ("FPGA: %s\n", &(fpgadata[index + 1]));
+				index += len + 3;
+			}
+			putc ('\n');
+			/* delayed reboot */
+			for (i = 20; i > 0; i--) {
+				printf ("Rebooting in %2d seconds \r", i);
+				for (index = 0; index < 1000; index++)
+					udelay (1000);
+			}
+			putc ('\n');
+			do_reset (NULL, 0, 0, NULL);
 		}
-		putc ('\n');
-		/* delayed reboot */
-		for (i = 20; i > 0; i--) {
-			printf ("Rebooting in %2d seconds \r", i);
-			for (index = 0; index < 1000; index++)
-				udelay (1000);
-		}
-		putc ('\n');
-		do_reset (NULL, 0, 0, NULL);
 	}

 	/*
@@ -139,32 +151,44 @@ int board_early_init_f (void)

 int checkboard (void)
 {
+	DECLARE_GLOBAL_DATA_PTR;
+
 	int index;
 	int len;
 	unsigned char str[64];
 	int i = getenv_r ("serial#", str, sizeof (str));
+	const unsigned char *fpga;

 	puts ("Board: ");

-	if (!i || strncmp (str, "AR405", 5)) {
-		puts ("### No HW ID - assuming AR405\n");
-		return (0);
+	if (i == -1) {
+		puts ("### No HW ID - assuming AR405");
+	} else {
+		puts(str);
 	}

-	puts (str);
-
 	puts ("\nFPGA:  ");

 	/* display infos on fpgaimage */
+	if (gd->board_type == 30) {
+		fpga = fpgadata_xl30;
+	} else {
+		fpga = fpgadata;
+	}
 	index = 15;
 	for (i = 0; i < 4; i++) {
-		len = fpgadata[index];
-		printf ("%s ", &(fpgadata[index + 1]));
+		len = fpga[index];
+		printf ("%s ", &(fpga[index + 1]));
 		index += len + 3;
 	}

 	putc ('\n');

+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+
 	return 0;
 }

@@ -172,7 +196,12 @@ int checkboard (void)

 long int initdram (int board_type)
 {
-	return (16 * 1024 * 1024);
+	unsigned long val;
+
+	mtdcr(memcfga, mem_mb0cf);
+	val = mfdcr(memcfgd);
+
+	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
 }

 /* ------------------------------------------------------------------------- */
@@ -185,4 +214,225 @@ int testdram (void)
 	return (0);
 }

-/* ------------------------------------------------------------------------- */
+
+#if 1 /* test-only: some internal test routines... */
+/*
+ * Some test routines
+ */
+int do_digtest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	volatile uchar *digen = (volatile uchar *)0xf03000b4;
+	volatile ushort *digout = (volatile ushort *)0xf03000b0;
+	volatile ushort *digin = (volatile ushort *)0xf03000a0;
+	int i;
+	int k;
+	int start;
+	int end;
+
+	if (argc != 3) {
+		puts("Usage: digtest n_start n_end (digtest 0 7)\n");
+		return 0;
+	}
+
+	start = simple_strtol (argv[1], NULL, 10);
+	end = simple_strtol (argv[2], NULL, 10);
+
+	/*
+	 * Enable digital outputs
+	 */
+	*digen = 0x08;
+
+	printf("\nStarting digital In-/Out Test from I/O %d to %d (Cntrl-C to abort)...\n",
+	       start, end);
+
+	/*
+	 * Set outputs one by one
+	 */
+	for (;;) {
+		for (i=start; i<=end; i++) {
+			*digout = 0x0001 << i;
+			for (k=0; k<200; k++)
+				udelay(1000);
+
+			if (*digin != (0x0001 << i)) {
+				printf("ERROR: OUT=0x%04X, IN=0x%04X\n", 0x0001 << i, *digin);
+				return 0;
+			}
+
+			/* Abort if ctrl-c was pressed */
+			if (ctrlc()) {
+				puts("\nAbort\n");
+				return 0;
+			}
+		}
+	}
+
+	return 0;
+}
+U_BOOT_CMD(
+	digtest,	3,	1,	do_digtest,
+	"digtest - Test digital in-/output\n",
+	NULL
+	);
+
+
+#define ERROR_DELTA     256
+
+struct io {
+	volatile short val;
+	short dummy;
+};
+
+int do_anatest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	volatile short val;
+	int i;
+	int volt;
+	struct io *out;
+	struct io *in;
+
+	out = (struct io *)0xf0300090;
+	in = (struct io *)0xf0300000;
+
+	i = simple_strtol (argv[1], NULL, 10);
+
+	volt = 0;
+	printf("Setting Channel %d to %dV...\n", i, volt);
+	out[i].val = (volt * 0x7fff) / 10;
+	udelay(10000);
+	val = in[i*2].val;
+	printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
+	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
+	    (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
+		printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
+		       ((volt * 0x7fff) / 40) + ERROR_DELTA);
+		return -1;
+	}
+	val = in[i*2+1].val;
+	printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
+	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
+	    (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
+		printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
+		       ((volt * 0x7fff) / 40) + ERROR_DELTA);
+		return -1;
+	}
+
+	volt = 5;
+	printf("Setting Channel %d to %dV...\n", i, volt);
+	out[i].val = (volt * 0x7fff) / 10;
+	udelay(10000);
+	val = in[i*2].val;
+	printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
+	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
+	    (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
+		printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
+		       ((volt * 0x7fff) / 40) + ERROR_DELTA);
+		return -1;
+	}
+	val = in[i*2+1].val;
+	printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
+	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
+	    (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
+		printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
+		       ((volt * 0x7fff) / 40) + ERROR_DELTA);
+		return -1;
+	}
+
+	volt = 10;
+	printf("Setting Channel %d to %dV...\n", i, volt);
+	out[i].val = (volt * 0x7fff) / 10;
+	udelay(10000);
+	val = in[i*2].val;
+	printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
+	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
+	    (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
+		printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
+		       ((volt * 0x7fff) / 40) + ERROR_DELTA);
+		return -1;
+	}
+	val = in[i*2+1].val;
+	printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
+	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
+	    (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
+		printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
+		       ((volt * 0x7fff) / 40) + ERROR_DELTA);
+		return -1;
+	}
+
+	printf("Channel %d OK!\n", i);
+
+	return 0;
+}
+U_BOOT_CMD(
+	anatest,	2,	1,	do_anatest,
+	"anatest - Test analog in-/output\n",
+	NULL
+	);
+
+
+int counter = 0;
+
+void cyclicInt(void *ptr)
+{
+	*(ushort *)0xf03000e8 = 0x0800; /* ack int */
+	counter++;
+}
+
+
+int do_inctest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	volatile uchar *digout = (volatile uchar *)0xf03000b4;
+	volatile ulong *incin;
+	int i;
+
+	incin = (volatile ulong *)0xf0300040;
+
+	/*
+	 * Clear inc counter
+	 */
+	incin[0] = 0;
+	incin[1] = 0;
+	incin[2] = 0;
+	incin[3] = 0;
+
+	incin = (volatile ulong *)0xf0300050;
+
+	/*
+	 * Inc a little
+	 */
+	for (i=0; i<10000; i++) {
+		switch (i & 0x03) {
+		case 0:
+			*digout = 0x02;
+			break;
+		case 1:
+			*digout = 0x03;
+			break;
+		case 2:
+			*digout = 0x01;
+			break;
+		case 3:
+			*digout = 0x00;
+			break;
+		}
+		udelay(10);
+	}
+
+	printf("Inc 0 = %ld\n", incin[0]);
+	printf("Inc 1 = %ld\n", incin[1]);
+	printf("Inc 2 = %ld\n", incin[2]);
+	printf("Inc 3 = %ld\n", incin[3]);
+
+	*(ushort *)0xf03000e0 = 0x0c80-1; /* set counter */
+	*(ushort *)0xf03000ec |= 0x0800; /* enable int */
+	irq_install_handler (30, (interrupt_handler_t *) cyclicInt, NULL);
+	printf("counter=%d\n", counter);
+
+	return 0;
+}
+U_BOOT_CMD(
+	inctest,	3,	1,	do_inctest,
+	"inctest - Test incremental encoder inputs\n",
+	NULL
+	);
+#endif
--- a/board/esd/ar405/config.mk
+++ b/board/esd/ar405/config.mk
@@ -26,4 +26,5 @@
 #

 #TEXT_BASE = 0xFFFE0000
-TEXT_BASE = 0xFFFD0000
+#TEXT_BASE = 0xFFFD0000
+TEXT_BASE = 0xFFFC0000
--- a/board/esd/ar405/flash.c
+++ b/board/esd/ar405/flash.c
@@ -33,18 +33,19 @@
 /*-----------------------------------------------------------------------
 * Functions
 */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static void flash_get_offsets (ulong base, flash_info_t *info);
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);

 /*-----------------------------------------------------------------------
 */

 unsigned long flash_init (void)
 {
-	unsigned long size_b0, size_b1;
+	unsigned long size_b0;
 	int i;
 	uint pbcr;
-	unsigned long base_b0, base_b1;
+	unsigned long base_b0;
+	int size_val = 0;

 	/* Init: no FLASHes known */
 	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
@@ -53,74 +54,48 @@ unsigned long flash_init (void)

 	/* Static FLASH Bank configuration here - FIXME XXX */

-	base_b0 = FLASH_BASE0_PRELIM;
-	size_b0 = flash_get_size((vu_long *)base_b0, &flash_info[0]);
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);

 	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
 		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
 			size_b0, size_b0<<20);
 	}

-	base_b1 = FLASH_BASE1_PRELIM;
-	size_b1 = flash_get_size((vu_long *)base_b1, &flash_info[1]);
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);

 	/* Re-do sizing to get full correct info */
+	mtdcr(ebccfga, pb0cr);
+	pbcr = mfdcr(ebccfgd);
+	mtdcr(ebccfga, pb0cr);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(ebccfgd, pbcr);

-	if (size_b1)
-	  {
-	    mtdcr(ebccfga, pb0cr);
-	    pbcr = mfdcr(ebccfgd);
-	    mtdcr(ebccfga, pb0cr);
-	    base_b1 = -size_b1;
-	    pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17);
-	    mtdcr(ebccfgd, pbcr);
-	    /*          printf("pb1cr = %x\n", pbcr); */
-	  }
-
-	if (size_b0)
-	  {
-	    mtdcr(ebccfga, pb1cr);
-	    pbcr = mfdcr(ebccfgd);
-	    mtdcr(ebccfga, pb1cr);
-	    base_b0 = base_b1 - size_b0;
-	    pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
-	    mtdcr(ebccfgd, pbcr);
-	    /*            printf("pb0cr = %x\n", pbcr); */
-	  }
-
-	size_b0 = flash_get_size((vu_long *)base_b0, &flash_info[0]);
-
-	flash_get_offsets (base_b0, &flash_info[0]);
-
-	/* monitor protection ON by default */
+	/* Monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
-			    base_b0+size_b0-monitor_flash_len,
-			    base_b0+size_b0-1,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
 			    &flash_info[0]);

-	if (size_b1) {
-		/* Re-do sizing to get full correct info */
-		size_b1 = flash_get_size((vu_long *)base_b1, &flash_info[1]);
-
-		flash_get_offsets (base_b1, &flash_info[1]);
-
-		/* monitor protection ON by default */
-		(void)flash_protect(FLAG_PROTECT_SET,
-				    base_b1+size_b1-monitor_flash_len,
-				    base_b1+size_b1-1,
-				    &flash_info[1]);
-		/* monitor protection OFF by default (one is enough) */
-		(void)flash_protect(FLAG_PROTECT_CLEAR,
-				    base_b0+size_b0-monitor_flash_len,
-				    base_b0+size_b0-1,
-				    &flash_info[0]);
-	} else {
-		flash_info[1].flash_id = FLASH_UNKNOWN;
-		flash_info[1].sector_count = -1;
-	}
-
 	flash_info[0].size = size_b0;
-	flash_info[1].size = size_b1;

-	return (size_b0 + size_b1);
+	return (size_b0);
 }
--- a/board/esd/ar405/fpgadata_xl30.c
+++ b/board/esd/ar405/fpgadata_xl30.c
--- a/board/esd/ar405/u-boot.lds
+++ b/board/esd/ar405/u-boot.lds
@@ -83,7 +83,10 @@ SECTIONS
    common/lists.o		(.text)
    common/main.o		(.text)

-    . = env_offset;
+/*
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.ppcenv)
+*/
    common/environment.o	(.text)

    *(.text)
--- a/board/esd/ash405/Makefile
+++ b/board/esd/ash405/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk

 LIB	= lib$(BOARD).a

-OBJS	= $(BOARD).o flash.o
+OBJS	= $(BOARD).o flash.o ../common/misc.o

 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS)
--- a/board/esd/canbt/Makefile
+++ b/board/esd/canbt/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk

 LIB	= lib$(BOARD).a

-OBJS	= $(BOARD).o flash.o
+OBJS	= $(BOARD).o flash.o ../common/misc.o

 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS)
--- a/board/esd/common/auto_update.c
+++ b/board/esd/common/auto_update.c
@@ -0,0 +1,537 @@
+/*
+ * (C) Copyright 2003-2004
+ * Gary Jennejohn, DENX Software Engineering, gj@denx.de.
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <image.h>
+#include <asm/byteorder.h>
+#include <linux/mtd/nand.h>
+#include <fat.h>
+
+#include "auto_update.h"
+
+#ifdef CONFIG_AUTO_UPDATE
+
+#if !(CONFIG_COMMANDS & CFG_CMD_FAT)
+#error "must define CFG_CMD_FAT"
+#endif
+
+extern au_image_t au_image[];
+extern int N_AU_IMAGES;
+
+#define AU_DEBUG
+#undef AU_DEBUG
+
+#undef debug
+#ifdef	AU_DEBUG
+#define debug(fmt,args...)	printf (fmt ,##args)
+#else
+#define debug(fmt,args...)
+#endif	/* AU_DEBUG */
+
+
+#define LOAD_ADDR ((unsigned char *)0x100000)   /* where to load files into memory */
+#define MAX_LOADSZ 0x1e00000
+
+/* externals */
+extern int fat_register_device(block_dev_desc_t *, int);
+extern int file_fat_detectfs(void);
+extern long file_fat_read(const char *, void *, unsigned long);
+long do_fat_read (const char *filename, void *buffer, unsigned long maxsize, int dols);
+#ifdef CONFIG_VFD
+extern int trab_vfd (ulong);
+extern int transfer_pic(unsigned char, unsigned char *, int, int);
+#endif
+extern int flash_sect_erase(ulong, ulong);
+extern int flash_sect_protect (int, ulong, ulong);
+extern int flash_write (uchar *, ulong, ulong);
+/* change char* to void* to shutup the compiler */
+extern block_dev_desc_t *get_dev (char*, int);
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+/* references to names in cmd_nand.c */
+#define NANDRW_READ	0x01
+#define NANDRW_WRITE	0x00
+#define NANDRW_JFFS2	0x02
+#define NANDRW_JFFS2_SKIP	0x04
+extern struct nand_chip nand_dev_desc[];
+extern int nand_rw(struct nand_chip* nand, int cmd, size_t start, size_t len,
+		   size_t * retlen, u_char * buf);
+extern int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean);
+#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
+
+extern block_dev_desc_t ide_dev_desc[CFG_IDE_MAXDEVICE];
+
+
+int au_check_cksum_valid(int i, long nbytes)
+{
+	image_header_t *hdr;
+	unsigned long checksum;
+
+	hdr = (image_header_t *)LOAD_ADDR;
+
+	if ((au_image[i].type == AU_FIRMWARE) && (au_image[i].size != ntohl(hdr->ih_size))) {
+		printf ("Image %s has wrong size\n", au_image[i].name);
+		return -1;
+	}
+
+	if (nbytes != (sizeof(*hdr) + ntohl(hdr->ih_size))) {
+		printf ("Image %s bad total SIZE\n", au_image[i].name);
+		return -1;
+	}
+	/* check the data CRC */
+	checksum = ntohl(hdr->ih_dcrc);
+
+	if (crc32 (0, (char *)(LOAD_ADDR + sizeof(*hdr)), ntohl(hdr->ih_size))
+		!= checksum) {
+		printf ("Image %s bad data checksum\n", au_image[i].name);
+		return -1;
+	}
+	return 0;
+}
+
+
+int au_check_header_valid(int i, long nbytes)
+{
+	image_header_t *hdr;
+	unsigned long checksum;
+
+	hdr = (image_header_t *)LOAD_ADDR;
+	/* check the easy ones first */
+#undef CHECK_VALID_DEBUG
+#ifdef CHECK_VALID_DEBUG
+	printf("magic %#x %#x ", ntohl(hdr->ih_magic), IH_MAGIC);
+	printf("arch %#x %#x ", hdr->ih_arch, IH_CPU_PPC);
+	printf("size %#x %#lx ", ntohl(hdr->ih_size), nbytes);
+	printf("type %#x %#x ", hdr->ih_type, IH_TYPE_KERNEL);
+#endif
+	if (nbytes < sizeof(*hdr))
+	{
+		printf ("Image %s bad header SIZE\n", au_image[i].name);
+		return -1;
+	}
+	if (ntohl(hdr->ih_magic) != IH_MAGIC || hdr->ih_arch != IH_CPU_PPC)
+	{
+		printf ("Image %s bad MAGIC or ARCH\n", au_image[i].name);
+		return -1;
+	}
+	/* check the hdr CRC */
+	checksum = ntohl(hdr->ih_hcrc);
+	hdr->ih_hcrc = 0;
+
+	if (crc32 (0, (char *)hdr, sizeof(*hdr)) != checksum) {
+		printf ("Image %s bad header checksum\n", au_image[i].name);
+		return -1;
+	}
+	hdr->ih_hcrc = htonl(checksum);
+
+	/* check the type - could do this all in one gigantic if() */
+	if ((au_image[i].type == AU_FIRMWARE) && (hdr->ih_type != IH_TYPE_FIRMWARE)) {
+		printf ("Image %s wrong type\n", au_image[i].name);
+		return -1;
+	}
+	if ((au_image[i].type == AU_SCRIPT) && (hdr->ih_type != IH_TYPE_SCRIPT)) {
+		printf ("Image %s wrong type\n", au_image[i].name);
+		return -1;
+	}
+
+	/* recycle checksum */
+	checksum = ntohl(hdr->ih_size);
+
+#if 0 /* test-only */
+	/* for kernel and app the image header must also fit into flash */
+	if (idx != IDX_DISK)
+		checksum += sizeof(*hdr);
+	/* check the size does not exceed space in flash. HUSH scripts */
+	/* all have ausize[] set to 0 */
+	if ((ausize[idx] != 0) && (ausize[idx] < checksum)) {
+		printf ("Image %s is bigger than FLASH\n", au_image[i].name);
+		return -1;
+	}
+#endif
+
+	return 0;
+}
+
+
+int au_do_update(int i, long sz)
+{
+	image_header_t *hdr;
+	char *addr;
+	long start, end;
+	int off, rc;
+	uint nbytes;
+	int k;
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+	int total;
+#endif
+
+	hdr = (image_header_t *)LOAD_ADDR;
+
+	switch (au_image[i].type) {
+	case AU_SCRIPT:
+		printf("Executing script %s\n", au_image[i].name);
+
+		/* execute a script */
+		if (hdr->ih_type == IH_TYPE_SCRIPT) {
+			addr = (char *)((char *)hdr + sizeof(*hdr));
+			/* stick a NULL at the end of the script, otherwise */
+			/* parse_string_outer() runs off the end. */
+			addr[ntohl(hdr->ih_size)] = 0;
+			addr += 8;
+
+			/*
+			 * Replace cr/lf with ;
+			 */
+			k = 0;
+			while (addr[k] != 0) {
+				if ((addr[k] == 10) || (addr[k] == 13)) {
+					addr[k] = ';';
+				}
+				k++;
+			}
+
+			run_command(addr, 0);
+			return 0;
+		}
+
+		break;
+
+	case AU_FIRMWARE:
+	case AU_NOR:
+	case AU_NAND:
+		start = au_image[i].start;
+		end = au_image[i].start + au_image[i].size - 1;
+
+		/* unprotect the address range */
+		/* this assumes that ONLY the firmware is protected! */
+		if (au_image[i].type == AU_FIRMWARE) {
+			flash_sect_protect(0, start, end);
+		}
+
+		/*
+		 * erase the address range.
+		 */
+		if (au_image[i].type != AU_NAND) {
+			printf("Updating NOR FLASH with image %s\n", au_image[i].name);
+			debug ("flash_sect_erase(%lx, %lx);\n", start, end);
+			flash_sect_erase(start, end);
+		} else {
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+			printf("Updating NAND FLASH with image %s\n", au_image[i].name);
+			debug ("nand_erase(%lx, %lx);\n", start, end);
+			rc = nand_erase (nand_dev_desc, start, end - start + 1, 0);
+			debug ("nand_erase returned %x\n", rc);
+#endif
+		}
+
+		udelay(10000);
+
+		/* strip the header - except for the kernel and ramdisk */
+		if (au_image[i].type != AU_FIRMWARE) {
+			addr = (char *)hdr;
+			off = sizeof(*hdr);
+			nbytes = sizeof(*hdr) + ntohl(hdr->ih_size);
+		} else {
+			addr = (char *)((char *)hdr + sizeof(*hdr));
+			off = 0;
+			nbytes = ntohl(hdr->ih_size);
+		}
+
+		/*
+		 * copy the data from RAM to FLASH
+		 */
+		if (au_image[i].type != AU_NAND) {
+			debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes);
+			rc = flash_write(addr, start, nbytes);
+		} else {
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+			debug ("nand_rw(%p, %lx %x)\n", addr, start, nbytes);
+			rc = nand_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2,
+				     start, nbytes, &total, addr);
+			debug ("nand_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes);
+#endif
+		}
+		if (rc != 0) {
+			printf("Flashing failed due to error %d\n", rc);
+			return -1;
+		}
+
+		/*
+		 * check the dcrc of the copy
+		 */
+		if (au_image[i].type != AU_NAND) {
+			rc = crc32 (0, (char *)(start + off), ntohl(hdr->ih_size));
+		} else {
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+			rc = nand_rw(nand_dev_desc, NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP,
+				     start, nbytes, &total, addr);
+			rc = crc32 (0, (char *)(addr + off), ntohl(hdr->ih_size));
+#endif
+		}
+		if (rc != ntohl(hdr->ih_dcrc)) {
+			printf ("Image %s Bad Data Checksum After COPY\n", au_image[i].name);
+			return -1;
+		}
+
+		/* protect the address range */
+		/* this assumes that ONLY the firmware is protected! */
+		if (au_image[i].type == AU_FIRMWARE) {
+			flash_sect_protect(1, start, end);
+		}
+
+		break;
+
+	default:
+		printf("Wrong image type selected!\n");
+	}
+
+	return 0;
+}
+
+
+static void process_macros (const char *input, char *output)
+{
+	char c, prev;
+	const char *varname_start = NULL;
+	int inputcnt  = strlen (input);
+	int outputcnt = CFG_CBSIZE;
+	int state = 0;	/* 0 = waiting for '$'	*/
+			/* 1 = waiting for '(' or '{' */
+			/* 2 = waiting for ')' or '}' */
+			/* 3 = waiting for '''  */
+#ifdef DEBUG_PARSER
+	char *output_start = output;
+
+	printf ("[PROCESS_MACROS] INPUT len %d: \"%s\"\n", strlen(input), input);
+#endif
+
+	prev = '\0';			/* previous character	*/
+
+	while (inputcnt && outputcnt) {
+	    c = *input++;
+	    inputcnt--;
+
+	    if (state!=3) {
+	    /* remove one level of escape characters */
+	    if ((c == '\\') && (prev != '\\')) {
+		if (inputcnt-- == 0)
+			break;
+		prev = c;
+		c = *input++;
+	    }
+	    }
+
+	    switch (state) {
+	    case 0:			/* Waiting for (unescaped) $	*/
+		if ((c == '\'') && (prev != '\\')) {
+			state = 3;
+			break;
+		}
+		if ((c == '$') && (prev != '\\')) {
+			state++;
+		} else {
+			*(output++) = c;
+			outputcnt--;
+		}
+		break;
+	    case 1:			/* Waiting for (	*/
+		if (c == '(' || c == '{') {
+			state++;
+			varname_start = input;
+		} else {
+			state = 0;
+			*(output++) = '$';
+			outputcnt--;
+
+			if (outputcnt) {
+				*(output++) = c;
+				outputcnt--;
+			}
+		}
+		break;
+	    case 2:			/* Waiting for )	*/
+		if (c == ')' || c == '}') {
+			int i;
+			char envname[CFG_CBSIZE], *envval;
+			int envcnt = input-varname_start-1; /* Varname # of chars */
+
+			/* Get the varname */
+			for (i = 0; i < envcnt; i++) {
+				envname[i] = varname_start[i];
+			}
+			envname[i] = 0;
+
+			/* Get its value */
+			envval = getenv (envname);
+
+			/* Copy into the line if it exists */
+			if (envval != NULL)
+				while ((*envval) && outputcnt) {
+					*(output++) = *(envval++);
+					outputcnt--;
+				}
+			/* Look for another '$' */
+			state = 0;
+		}
+		break;
+	    case 3:			/* Waiting for '	*/
+		if ((c == '\'') && (prev != '\\')) {
+			state = 0;
+		} else {
+			*(output++) = c;
+			outputcnt--;
+		}
+		break;
+	    }
+	    prev = c;
+	}
+
+	if (outputcnt)
+		*output = 0;
+
+#ifdef DEBUG_PARSER
+	printf ("[PROCESS_MACROS] OUTPUT len %d: \"%s\"\n",
+		strlen(output_start), output_start);
+#endif
+}
+
+
+/*
+ * this is called from board_init() after the hardware has been set up
+ * and is usable. That seems like a good time to do this.
+ * Right now the return value is ignored.
+ */
+int do_auto_update(void)
+{
+	block_dev_desc_t *stor_dev;
+	long sz;
+	int i, res, cnt, old_ctrlc, got_ctrlc;
+	char buffer[32];
+	char str[80];
+
+	/*
+	 * Check whether a CompactFlash is inserted
+	 */
+	if (ide_dev_desc[0].type == DEV_TYPE_UNKNOWN) {
+		return -1;       /* no disk detected! */
+	}
+
+	/* check whether it has a partition table */
+	stor_dev = get_dev("ide", 0);
+	if (stor_dev == NULL) {
+		debug ("Uknown device type\n");
+		return -1;
+	}
+	if (fat_register_device(stor_dev, 1) != 0) {
+		debug ("Unable to register ide disk 0:1 for fatls\n");
+		return -1;
+	}
+
+	/*
+	 * Check if magic file is present
+	 */
+	if (do_fat_read(AU_MAGIC_FILE, buffer, sizeof(buffer), LS_NO) <= 0) {
+		return -1;
+	}
+
+#ifdef CONFIG_AUTO_UPDATE_SHOW
+	board_auto_update_show(1);
+#endif
+	puts("\nAutoUpdate Disk detected! Trying to update system...\n");
+
+	/* make sure that we see CTRL-C and save the old state */
+	old_ctrlc = disable_ctrlc(0);
+
+	/* just loop thru all the possible files */
+	for (i = 0; i < N_AU_IMAGES; i++) {
+		/*
+		 * Try to expand the environment var in the fname
+		 */
+		process_macros(au_image[i].name, str);
+		strcpy(au_image[i].name, str);
+
+		printf("Reading %s ...", au_image[i].name);
+		/* just read the header */
+		sz = do_fat_read(au_image[i].name, LOAD_ADDR, sizeof(image_header_t), LS_NO);
+		debug ("read %s sz %ld hdr %d\n",
+			au_image[i].name, sz, sizeof(image_header_t));
+		if (sz <= 0 || sz < sizeof(image_header_t)) {
+			puts(" not found\n");
+			continue;
+		}
+		if (au_check_header_valid(i, sz) < 0) {
+			puts(" header not valid\n");
+			continue;
+		}
+		sz = do_fat_read(au_image[i].name, LOAD_ADDR, MAX_LOADSZ, LS_NO);
+		debug ("read %s sz %ld hdr %d\n",
+			au_image[i].name, sz, sizeof(image_header_t));
+		if (sz <= 0 || sz <= sizeof(image_header_t)) {
+			puts(" not found\n");
+			continue;
+		}
+		if (au_check_cksum_valid(i, sz) < 0) {
+			puts(" checksum not valid\n");
+			continue;
+		}
+		puts(" done\n");
+
+		do {
+			res = au_do_update(i, sz);
+			/* let the user break out of the loop */
+			if (ctrlc() || had_ctrlc()) {
+				clear_ctrlc();
+				if (res < 0)
+					got_ctrlc = 1;
+				break;
+			}
+			cnt++;
+		} while (res < 0);
+	}
+
+	/* restore the old state */
+	disable_ctrlc(old_ctrlc);
+
+	puts("AutoUpdate finished\n\n");
+#ifdef CONFIG_AUTO_UPDATE_SHOW
+	board_auto_update_show(0);
+#endif
+
+	return 0;
+}
+
+
+int auto_update(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	do_auto_update();
+
+	return 0;
+}
+U_BOOT_CMD(
+	autoupd,	1,	1,	auto_update,
+	"autoupd - Automatically update images\n",
+	NULL
+);
+#endif /* CONFIG_AUTO_UPDATE */
--- a/board/esd/common/auto_update.h
+++ b/board/esd/common/auto_update.h
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _AUTO_UPDATE_H_
+#define _AUTO_UPDATE_H_
+
+#define MBR_MAGIC       0x07081967
+#define MBR_MAGIC_ADDR  0x100           /* offset 0x100 should be free space */
+
+#define AU_MAGIC_FILE   "__auto_update"
+
+#define AU_SCRIPT       1
+#define AU_FIRMWARE     2
+#define AU_NOR          3
+#define AU_NAND         4
+
+struct au_image_s {
+	char name[80];
+	ulong start;
+	ulong size;
+	int type;
+};
+
+typedef struct au_image_s au_image_t;
+
+int do_auto_update(void);
+#ifdef CONFIG_AUTO_UPDATE_SHOW
+void board_auto_update_show(int au_active);
+#endif
+
+#endif /* #ifndef _AUTO_UPDATE_H_ */
--- a/board/esd/common/flash.c
+++ b/board/esd/common/flash.c
@@ -117,6 +117,7 @@ void flash_print_info  (flash_info_t *info)
 	case FLASH_MAN_AMD:	printf ("AMD ");		break;
 	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
 	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_EXCEL:	printf ("Excel Semiconductor "); break;
 	default:		printf ("Unknown Vendor ");	break;
 	}

@@ -151,6 +152,10 @@ void flash_print_info  (flash_info_t *info)
 				break;
 	case FLASH_SST160A:	printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
 				break;
+	case FLASH_SST320:	printf ("SST39LF/VF320 (32 Mbit, uniform sector size)\n");
+				break;
+	case FLASH_SST640:	printf ("SST39LF/VF640 (64 Mbit, uniform sector size)\n");
+				break;
 	default:		printf ("Unknown Chip Type\n");
 				break;
 	}
@@ -235,6 +240,9 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 	case (CFG_FLASH_WORD_SIZE)SST_MANUFACT:
 		info->flash_id = FLASH_MAN_SST;
 		break;
+	case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT:
+		info->flash_id = FLASH_MAN_EXCEL;
+		break;
 	default:
 		info->flash_id = FLASH_UNKNOWN;
 		info->sector_count = 0;
@@ -316,6 +324,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		info->sector_count = 128;
 		info->size = 0x00800000;  break;	/* => 8 MB	*/

+#if !(defined(CONFIG_ADCIOP) || defined(CONFIG_DASA_SIM))
 	case (CFG_FLASH_WORD_SIZE)SST_ID_xF800A:
 		info->flash_id += FLASH_SST800A;
 		info->sector_count = 16;
@@ -323,11 +332,28 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		break;				/* => 1 MB		*/

 	case (CFG_FLASH_WORD_SIZE)SST_ID_xF160A:
+	case (CFG_FLASH_WORD_SIZE)SST_ID_xF1601:
+	case (CFG_FLASH_WORD_SIZE)SST_ID_xF1602:
 		info->flash_id += FLASH_SST160A;
 		info->sector_count = 32;
 		info->size = 0x00200000;
 		break;				/* => 2 MB		*/

+	case (CFG_FLASH_WORD_SIZE)SST_ID_xF3201:
+	case (CFG_FLASH_WORD_SIZE)SST_ID_xF3202:
+		info->flash_id += FLASH_SST320;
+		info->sector_count = 64;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)SST_ID_xF6401:
+	case (CFG_FLASH_WORD_SIZE)SST_ID_xF6402:
+		info->flash_id += FLASH_SST640;
+		info->sector_count = 128;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+#endif
+
 	default:
 		info->flash_id = FLASH_UNKNOWN;
 		return (0);			/* => no or unknown flash */
@@ -397,7 +423,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
 		/* D0 = 1 if protected */
 		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
-		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+		if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD)
 		  info->protect[i] = 0;
 		else
 		  info->protect[i] = addr2[CFG_FLASH_READ2] & 1;
@@ -610,10 +636,10 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
 	int i;

 	/* Check if Flash is (sufficiently) erased */
-	if ((*((volatile CFG_FLASH_WORD_SIZE *)dest) &
-	     (CFG_FLASH_WORD_SIZE)data) != (CFG_FLASH_WORD_SIZE)data) {
+	if ((*((vu_long *)dest) & data) != data) {
 		return (2);
 	}
+
 	/* Disable interrupts which might cause a timeout here */
 	flag = disable_interrupts();

--- a/board/esd/common/fpga.c
+++ b/board/esd/common/fpga.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2001-2003
+ * (C) Copyright 2001-2004
 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
@@ -54,19 +54,42 @@
 #define ERROR_FPGA_PRG_INIT_HIGH -2        /* Timeout after PRG* deasserted */
 #define ERROR_FPGA_PRG_DONE      -3        /* Timeout after programming     */

-#define SET_FPGA(data)         out32(GPIO0_OR, data)
+#ifndef SET_FPGA
+# define SET_FPGA(data)         out32(GPIO0_OR, data)
+#endif

-#define FPGA_WRITE_1 {                                                    \
-	SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set clock to 0 */  \
-	SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set data to 1  */  \
-	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);  /* set clock to 1 */  \
-	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1  */
+#ifdef FPGA_PROG_ACTIVE_HIGH
+# define FPGA_PRG_LOW           FPGA_PRG
+# define FPGA_PRG_HIGH          0
+#else
+# define FPGA_PRG_LOW           0
+# define FPGA_PRG_HIGH          FPGA_PRG
+#endif
+
+#define FPGA_CLK_LOW            0
+#define FPGA_CLK_HIGH           FPGA_CLK
+
+#define FPGA_DATA_LOW           0
+#define FPGA_DATA_HIGH          FPGA_DATA
+
+#define FPGA_WRITE_1 {                                                                   \
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW  | FPGA_DATA_HIGH);  /* set clock to 0 */  \
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW  | FPGA_DATA_HIGH);  /* set data to 1  */  \
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);  /* set clock to 1 */  \
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1  */

 #define FPGA_WRITE_0 {                                                    \
-	SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set clock to 0 */  \
-	SET_FPGA(FPGA_PRG);                         /* set data to 0  */  \
-	SET_FPGA(FPGA_PRG | FPGA_CLK);              /* set clock to 1 */  \
-	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1  */
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW  | FPGA_DATA_HIGH);  /* set clock to 0 */  \
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW  | FPGA_DATA_LOW);   /* set data to 0  */  \
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_LOW);   /* set clock to 1 */  \
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1  */
+
+#ifndef FPGA_DONE_STATE
+# define FPGA_DONE_STATE (in32(GPIO0_IR) & FPGA_DONE)
+#endif
+#ifndef FPGA_INIT_STATE
+# define FPGA_INIT_STATE (in32(GPIO0_IR) & FPGA_INIT)
+#endif


 static int fpga_boot(unsigned char *fpgadata, int size)
@@ -115,21 +138,23 @@ static int fpga_boot(unsigned char *fpgadata, int size)
  /*
   * Setup port pins for fpga programming
   */
+#ifndef CONFIG_M5249
  out32(GPIO0_ODR, 0x00000000);                                      /* no open drain pins */
  out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* setup for output */
-  out32(GPIO0_OR, in32(GPIO0_OR) | FPGA_PRG | FPGA_CLK | FPGA_DATA);   /* set pins to high */
+#endif
+  SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);            /* set pins to high */

-  DBG("%s, ",((in32(GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
-  DBG("%s\n",((in32(GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT" );
+  DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
+  DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );

  /*
   * Init fpga by asserting and deasserting PROGRAM*
   */
-  SET_FPGA(FPGA_CLK | FPGA_DATA);
+  SET_FPGA(FPGA_PRG_LOW  | FPGA_CLK_HIGH | FPGA_DATA_HIGH);             /* set prog active */

  /* Wait for FPGA init line low */
  count = 0;
-  while (in32(GPIO0_IR) & FPGA_INIT)
+  while (FPGA_INIT_STATE)
    {
      udelay(1000); /* wait 1ms */
      /* Check for timeout - 100us max, so use 3ms */
@@ -140,15 +165,15 @@ static int fpga_boot(unsigned char *fpgadata, int size)
 	}
    }

-  DBG("%s, ",((in32(GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
-  DBG("%s\n",((in32(GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT" );
+  DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
+  DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );

  /* deassert PROGRAM* */
-  SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+  SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);           /* set prog inactive */

  /* Wait for FPGA end of init period .  */
  count = 0;
-  while (!(in32(GPIO0_IR) & FPGA_INIT))
+  while (!(FPGA_INIT_STATE))
    {
      udelay(1000); /* wait 1ms */
      /* Check for timeout */
@@ -159,8 +184,8 @@ static int fpga_boot(unsigned char *fpgadata, int size)
 	}
    }

-  DBG("%s, ",((in32(GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
-  DBG("%s\n",((in32(GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT" );
+  DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
+  DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );

  DBG("write configuration data into fpga\n");
  /* write configuration-data into fpga... */
@@ -232,8 +257,8 @@ static int fpga_boot(unsigned char *fpgadata, int size)
    }
 #endif

-  DBG("%s, ",((in32(GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
-  DBG("%s\n",((in32(GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT" );
+  DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
+  DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );

  /*
   * Check if fpga's DONE signal - correctly booted ?
@@ -241,7 +266,7 @@ static int fpga_boot(unsigned char *fpgadata, int size)

  /* Wait for FPGA end of programming period .  */
  count = 0;
-  while (!(in32(GPIO0_IR) & FPGA_DONE))
+  while (!(FPGA_DONE_STATE))
    {
      udelay(1000); /* wait 1ms */
      /* Check for timeout */
--- a/board/esd/common/lcd.c
+++ b/board/esd/common/lcd.c
@@ -0,0 +1,230 @@
+/*
+ * (C) Copyright 2003-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "lcd.h"
+
+
+int palette_index;
+int palette_value;
+
+
+#ifdef CFG_LCD_ENDIAN
+void lcd_setup(int lcd, int config)
+{
+	if (lcd == 0) {
+		/*
+		 * Set endianess and reset lcd controller 0 (small)
+		 */
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD0_RST); /* set reset to low */
+		udelay(10); /* wait 10us */
+		if (config == 1) {
+			out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
+		} else {
+			out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
+		}
+		udelay(10); /* wait 10us */
+		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD0_RST); /* set reset to high */
+	} else {
+		/*
+		 * Set endianess and reset lcd controller 1 (big)
+		 */
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD1_RST); /* set reset to low */
+		udelay(10); /* wait 10us */
+		if (config == 1) {
+			out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
+		} else {
+			out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
+		}
+		udelay(10); /* wait 10us */
+		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD1_RST); /* set reset to high */
+	}
+
+	/*
+	 * CFG_LCD_ENDIAN may also be FPGA_RESET, so set inactive
+	 */
+	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* set reset high again */
+}
+#endif /* #ifdef CFG_LCD_ENDIAN */
+
+
+void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
+	      uchar *logo_bmp, ulong len)
+{
+	int i;
+	ushort s1dReg;
+	uchar s1dValue;
+	uchar *ptr;
+	ushort *ptr2;
+	ushort val;
+	unsigned char *dst;
+	int x, y;
+	int width, height, bpp, colors, line_size;
+	int header_size;
+	unsigned char *bmp;
+	unsigned char r, g, b;
+	BITMAPINFOHEADER *bm_info;
+	int reg_byte_swap;
+
+	/*
+	 * Detect epson
+	 */
+	if (lcd_reg[0] == 0x1c) {
+		/*
+		 * Big epson detected
+		 */
+		reg_byte_swap = FALSE;
+		palette_index = 0x1e2;
+		palette_value = 0x1e4;
+		puts("LCD:   S1D13806");
+	} else if (lcd_reg[1] == 0x1c) {
+		/*
+		 * Big epson detected (with register swap bug)
+		 */
+		reg_byte_swap = TRUE;
+		palette_index = 0x1e3;
+		palette_value = 0x1e5;
+		puts("LCD:   S1D13806S");
+	} else if (lcd_reg[0] == 0x18) {
+		/*
+		 * Small epson detected (704)
+		 */
+		reg_byte_swap = FALSE;
+		palette_index = 0x15;
+		palette_value = 0x17;
+		puts("LCD:   S1D13704");
+	} else if (lcd_reg[0x10000] == 0x24) {
+		/*
+		 * Small epson detected (705)
+		 */
+		reg_byte_swap = FALSE;
+		palette_index = 0x15;
+		palette_value = 0x17;
+		lcd_reg += 0x10000; /* add offset for 705 regs */
+		puts("LCD:   S1D13705");
+	} else {
+		puts("LCD:   No controller detected!\n");
+		return;
+	}
+
+	for (i = 0; i<reg_count; i++) {
+		s1dReg = regs[i].Index;
+		if (reg_byte_swap) {
+			if ((s1dReg & 0x0001) == 0)
+				s1dReg |= 0x0001;
+			else
+				s1dReg &= ~0x0001;
+		}
+		s1dValue = regs[i].Value;
+		lcd_reg[s1dReg] = s1dValue;
+	}
+
+	/*
+	 * Decompress bmp image
+	 */
+	dst = malloc(CFG_LCD_LOGO_MAX_SIZE);
+	if (gunzip(dst, CFG_LCD_LOGO_MAX_SIZE, (uchar *)logo_bmp, &len) != 0) {
+		return;
+	}
+
+	/*
+	 * Check for bmp mark 'BM'
+	 */
+	if (*(ushort *)dst != 0x424d) {
+		printf("LCD: Unknown image format!\n");
+		free(dst);
+		return;
+	}
+
+	/*
+	 * Get image info from bmp-header
+	 */
+	bm_info = (BITMAPINFOHEADER *)(dst + 14);
+	bpp = LOAD_SHORT(bm_info->biBitCount);
+	width = LOAD_LONG(bm_info->biWidth);
+	height = LOAD_LONG(bm_info->biHeight);
+	switch (bpp) {
+	case 1:
+		colors = 1;
+		line_size = width >> 3;
+		break;
+	case 4:
+		colors = 16;
+		line_size = width >> 1;
+		break;
+	case 8:
+		colors = 256;
+		line_size = width;
+		break;
+	case 24:
+		colors = 0;
+		line_size = width * 3;
+		break;
+	default:
+		printf("LCD: Unknown bpp (%d) im image!\n", bpp);
+		free(dst);
+		return;
+	}
+	printf(" (%d*%d, %dbpp)\n", width, height, bpp);
+
+	/*
+	 * Write color palette
+	 */
+	if (colors <= 256) {
+		ptr = (unsigned char *)(dst + 14 + 40);
+		for (i=0; i<colors; i++) {
+			b = *ptr++;
+			g = *ptr++;
+			r = *ptr++;
+			ptr++;
+			S1D_WRITE_PALETTE(lcd_reg, i, r, g, b);
+		}
+	}
+
+	/*
+	 * Write bitmap data into framebuffer
+	 */
+	ptr = lcd_mem;
+	ptr2 = (ushort *)lcd_mem;
+	header_size = 14 + 40 + 4*colors;          /* skip bmp header */
+	for (y=0; y<height; y++) {
+		bmp = &dst[(height-1-y)*line_size + header_size];
+		if (bpp == 24) {
+			for (x=0; x<width; x++) {
+				/*
+				 * Generate epson 16bpp fb-format from 24bpp image
+				 */
+				b = *bmp++ >> 3;
+				g = *bmp++ >> 2;
+				r = *bmp++ >> 3;
+				val = ((r & 0x1f) << 11) | ((g & 0x3f) << 5) | (b & 0x1f);
+				*ptr2++ = val;
+			}
+		} else {
+			for (x=0; x<line_size; x++) {
+				*ptr++ = *bmp++;
+			}
+		}
+	}
+
+	free(dst);
+}
--- a/board/esd/common/lcd.h
+++ b/board/esd/common/lcd.h
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2003-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Neutralize little endians.
+ */
+#define SWAP_LONG(data) ((unsigned long)                                  \
+		         (((unsigned long)(data) >> 24)                 | \
+			  ((unsigned long)(data)  << 24)                | \
+			  (((unsigned long)(data) >> 8) & 0x0000ff00 )  | \
+			   (((unsigned long)(data) << 8) & 0x00ff0000 )))
+#define SWAP_SHORT(data) ((unsigned short)                                \
+			  (((unsigned short)(data) >> 8 )  |              \
+			   ((unsigned short)(data) << 8 )))
+#define LOAD_LONG(data)   SWAP_LONG(data)
+#define LOAD_SHORT(data)  SWAP_SHORT(data)
+
+#ifndef FALSE
+#define FALSE 0
+#define TRUE (!FALSE)
+#endif
+
+#define S1D_WRITE_PALETTE(p,i,r,g,b)  \
+  {  \
+  ((volatile uchar*)(p))[palette_index] = (uchar)(i); \
+  ((volatile uchar*)(p))[palette_value] = (uchar)(r); \
+  ((volatile uchar*)(p))[palette_value] = (uchar)(g); \
+  ((volatile uchar*)(p))[palette_value] = (uchar)(b); \
+  }
+
+typedef struct
+{
+    ushort Index;
+    uchar  Value;
+} S1D_REGS;
+
+typedef struct                       /**** BMP file info structure ****/
+{
+	unsigned int   biSize;           /* Size of info header */
+	int            biWidth;          /* Width of image */
+	int            biHeight;         /* Height of image */
+	unsigned short biPlanes;         /* Number of color planes */
+	unsigned short biBitCount;       /* Number of bits per pixel */
+	unsigned int   biCompression;    /* Type of compression to use */
+	unsigned int   biSizeImage;      /* Size of image data */
+	int            biXPelsPerMeter;  /* X pixels per meter */
+	int            biYPelsPerMeter;  /* Y pixels per meter */
+	unsigned int   biClrUsed;        /* Number of colors used */
+	unsigned int   biClrImportant;   /* Number of important colors */
+} BITMAPINFOHEADER;
--- a/board/esd/common/misc.c
+++ b/board/esd/common/misc.c
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_LXT971_NO_SLEEP
+#include <miiphy.h>
+#endif
+
+
+#ifdef CONFIG_LXT971_NO_SLEEP
+void lxt971_no_sleep(void)
+{
+	unsigned short reg;
+
+	miiphy_read(CONFIG_PHY_ADDR, 0x10, &reg);
+	reg &= ~0x0040;                  /* disable sleep mode */
+	miiphy_write(CONFIG_PHY_ADDR, 0x10, reg);
+}
+#endif /* CONFIG_LXT971_NO_SLEEP */
--- a/board/esd/common/s1d13704_320_240_4bpp.h
+++ b/board/esd/common/s1d13704_320_240_4bpp.h
@@ -0,0 +1,53 @@
+/*
+ *
+ *  Generic Header information generated by 13704CFG.EXE (Build 10)
+ *
+ *  Copyright (c) 2000,2001 Epson Research and Development, Inc.
+ *  All rights reserved.
+ *
+ *  Panel: 320x240x4bpp 78Hz Mono 4-Bit STN, Disabled (PCLK=6.666MHz)
+ *
+ *  This file defines the configuration environment and registers,
+ *  which can be used by any software, such as display drivers.
+ *
+ *  PLEASE NOTE: If you FTP this file to a non-Windows platform, make
+ *               sure you transfer this file using ASCII, not BINARY
+ *               mode.
+ *
+ */
+
+static S1D_REGS regs_13704_320_240_4bpp[] =
+{
+	{ 0x00,             0x00 },       /* Revision Code Register */
+	{ 0x01,             0x04 }, /*00*/      /* Mode Register 0 Register */
+	{ 0x02,             0xA4 }, /*a0*/      /* Mode Register 1 Register */
+	{ 0x03,             0x83 }, /*03*/      /* Mode Register 2 Register - bit7 is LUT bypass */
+	{ 0x04,             0x27 },       /* Horizontal Panel Size Register */
+	{ 0x05,             0xEF },       /* Vertical Panel Size Register (LSB) */
+	{ 0x06,             0x00 },       /* Vertical Panel Size Register (MSB) */
+	{ 0x07,             0x00 },       /* FPLINE Start Position Register */
+	{ 0x08,             0x00 },       /* Horizontal Non-Display Period Register */
+	{ 0x09,             0x00 },       /* FPFRAME Start Position Register */
+	{ 0x0A,             0x02 },       /* Vertical Non-Display Period Register */
+	{ 0x0B,             0x00 },       /* MOD Rate Register */
+	{ 0x0C,             0x00 },       /* Screen 1 Start Address Register (LSB) */
+	{ 0x0D,             0x00 },       /* Screen 1 Start Address Register (MSB) */
+	{ 0x0E,             0x00 },       /* Not Used */
+	{ 0x0F,             0x00 },       /* Screen 2 Start Address Register (LSB) */
+	{ 0x10,             0x00 },       /* Screen 2 Start Address Register (MSB) */
+	{ 0x11,             0x00 },       /* Not Used */
+	{ 0x12,             0x00 },       /* Memory Address Offset Register */
+	{ 0x13,             0xFF },       /* Screen 1 Vertical Size Register (LSB) */
+	{ 0x14,             0x03 },       /* Screen 1 Vertical Size Register (MSB) */
+	{ 0x15,             0x00 },       /* Look-Up Table Address Register */
+	{ 0x16,             0x00 },       /* Look-Up Table Bank Select Register */
+	{ 0x17,             0x00 },       /* Look-Up Table Data Register */
+	{ 0x18,             0x01 },       /* GPIO Configuration Control Register */
+	{ 0x19,             0x01 },       /* GPIO Status/Control Register */
+	{ 0x1A,             0x00 },       /* Scratch Pad Register */
+	{ 0x1B,             0x00 },       /* SwivelView Mode Register */
+	{ 0x1C,             0xA0 },       /* Line Byte Count Register */
+	{ 0x1D,             0x00 },       /* Not Used */
+	{ 0x1E,             0x00 },       /* Not Used */
+	{ 0x1F,             0x00 },       /* Not Used */
+};
--- a/board/esd/common/s1d13705_320_240_8bpp.h
+++ b/board/esd/common/s1d13705_320_240_8bpp.h
@@ -0,0 +1,53 @@
+/*
+ *
+ *  Generic Header information generated by 13704CFG.EXE (Build 10)
+ *
+ *  Copyright (c) 2000,2001 Epson Research and Development, Inc.
+ *  All rights reserved.
+ *
+ *  Panel: 320x240x8bpp 78Hz Mono 8-Bit STN, Disabled (PCLK=6.666MHz)
+ *
+ *  This file defines the configuration environment and registers,
+ *  which can be used by any software, such as display drivers.
+ *
+ *  PLEASE NOTE: If you FTP this file to a non-Windows platform, make
+ *               sure you transfer this file using ASCII, not BINARY
+ *               mode.
+ *
+ */
+
+static S1D_REGS regs_13705_320_240_8bpp[] =
+{
+	{ 0x00,             0x00 },       /* Revision Code Register */
+	{ 0x01,             0x23 },       /* Mode Register 0 Register */
+	{ 0x02,             0xE0 },       /* Mode Register 1 Register */
+	{ 0x03,             0x03 },       /* Mode Register 2 Register - bit7 is LUT bypass */
+	{ 0x04,             0x27 },       /* Horizontal Panel Size Register */
+	{ 0x05,             0xEF },       /* Vertical Panel Size Register (LSB) */
+	{ 0x06,             0x00 },       /* Vertical Panel Size Register (MSB) */
+	{ 0x07,             0x00 },       /* FPLINE Start Position Register */
+	{ 0x08,             0x00 },       /* Horizontal Non-Display Period Register */
+	{ 0x09,             0x01 },       /* FPFRAME Start Position Register */
+	{ 0x0A,             0x02 },       /* Vertical Non-Display Period Register */
+	{ 0x0B,             0x00 },       /* MOD Rate Register */
+	{ 0x0C,             0x00 },       /* Screen 1 Start Address Register (LSB) */
+	{ 0x0D,             0x00 },       /* Screen 1 Start Address Register (MSB) */
+	{ 0x0E,             0x00 },       /* Not Used */
+	{ 0x0F,             0x00 },       /* Screen 2 Start Address Register (LSB) */
+	{ 0x10,             0x00 },       /* Screen 2 Start Address Register (MSB) */
+	{ 0x11,             0x00 },       /* Not Used */
+	{ 0x12,             0x00 },       /* Memory Address Offset Register */
+	{ 0x13,             0xFF },       /* Screen 1 Vertical Size Register (LSB) */
+	{ 0x14,             0x03 },       /* Screen 1 Vertical Size Register (MSB) */
+	{ 0x15,             0x00 },       /* Look-Up Table Address Register */
+	{ 0x16,             0x00 },       /* Look-Up Table Bank Select Register */
+	{ 0x17,             0x00 },       /* Look-Up Table Data Register */
+	{ 0x18,             0x01 },       /* GPIO Configuration Control Register */
+	{ 0x19,             0x01 },       /* GPIO Status/Control Register */
+	{ 0x1A,             0x00 },       /* Scratch Pad Register */
+	{ 0x1B,             0x00 },       /* SwivelView Mode Register */
+	{ 0x1C,             0xFF },       /* Line Byte Count Register */
+	{ 0x1D,             0x00 },       /* Not Used */
+	{ 0x1E,             0x00 },       /* Not Used */
+	{ 0x1F,             0x00 },       /* Not Used */
+};
--- a/board/esd/common/s1d13806_1024_768_8bpp.h
+++ b/board/esd/common/s1d13806_1024_768_8bpp.h
@@ -0,0 +1,125 @@
+/*
+ *
+ *  File generated by S1D13806CFG.EXE
+ *
+ *  Copyright (c) 2000,2001 Epson Research and Development, Inc.
+ *  All rights reserved.
+ *
+ *  PLEASE NOTE: If you FTP this file to a non-Windows platform, make
+ *               sure you transfer this file using ASCII, not BINARY mode.
+ *
+ * Panel:  (active)   1024x768 34Hz TFT Single 12-bit (PCLK=BUSCLK=33.333MHz)
+ * Memory: Embedded SDRAM (MCLK=CLKI=49.100MHz) (BUSCLK=33.333MHz)
+ *
+ */
+
+static S1D_REGS regs_13806_1024_768_8bpp[] =
+{
+	{0x0001,0x00},   /* Miscellaneous Register */
+	{0x01FC,0x00},   /* Display Mode Register */
+	{0x0004,0x00},   /* General IO Pins Configuration Register 0 */
+	{0x0005,0x00},   /* General IO Pins Configuration Register 1 */
+	{0x0008,0x00},   /* General IO Pins Control Register 0 */
+	{0x0009,0x00},   /* General IO Pins Control Register 1 */
+	{0x0010,0x00},   /* Memory Clock Configuration Register */
+	{0x0014,0x01},   /* LCD Pixel Clock Configuration Register */
+	{0x0018,0x00},   /* CRT/TV Pixel Clock Configuration Register */
+	{0x001C,0x02},   /* MediaPlug Clock Configuration Register */
+	{0x001E,0x01},   /* CPU To Memory Wait State Select Register */
+	{0x0021,0x03},   /* DRAM Refresh Rate Register */
+	{0x002A,0x00},   /* DRAM Timings Control Register 0 */
+	{0x002B,0x01},   /* DRAM Timings Control Register 1 */
+	{0x0020,0x80},   /* Memory Configuration Register */
+	{0x0030,0x55},   /* Panel Type Register */
+	{0x0031,0x00},   /* MOD Rate Register */
+	{0x0032,0x7F},   /* LCD Horizontal Display Width Register */
+	{0x0034,0x12},   /* LCD Horizontal Non-Display Period Register */
+	{0x0035,0x01},   /* TFT FPLINE Start Position Register */
+	{0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
+	{0x0038,0xFF},   /* LCD Vertical Display Height Register 0 */
+	{0x0039,0x02},   /* LCD Vertical Display Height Register 1 */
+	{0x003A,0x2C},   /* LCD Vertical Non-Display Period Register */
+	{0x003B,0x0A},   /* TFT FPFRAME Start Position Register */
+	{0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
+	{0x0040,0x03},   /* LCD Display Mode Register */
+	{0x0041,0x00},   /* LCD Miscellaneous Register */
+	{0x0042,0x00},   /* LCD Display Start Address Register 0 */
+	{0x0043,0x00},   /* LCD Display Start Address Register 1 */
+	{0x0044,0x00},   /* LCD Display Start Address Register 2 */
+	{0x0046,0x00},   /* LCD Memory Address Offset Register 0 */
+	{0x0047,0x02},   /* LCD Memory Address Offset Register 1 */
+	{0x0048,0x00},   /* LCD Pixel Panning Register */
+	{0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
+	{0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
+	{0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
+	{0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
+	{0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
+	{0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
+	{0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
+	{0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
+	{0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
+	{0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
+	{0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
+	{0x005B,0x10},   /* TV Output Control Register */
+	{0x0060,0x03},   /* CRT/TV Display Mode Register */
+	{0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
+	{0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
+	{0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
+	{0x0066,0x40},   /* CRT/TV Memory Address Offset Register 0 */
+	{0x0067,0x01},   /* CRT/TV Memory Address Offset Register 1 */
+	{0x0068,0x00},   /* CRT/TV Pixel Panning Register */
+	{0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
+	{0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
+	{0x0070,0x00},   /* LCD Ink/Cursor Control Register */
+	{0x0071,0x01},   /* LCD Ink/Cursor Start Address Register */
+	{0x0072,0x00},   /* LCD Cursor X Position Register 0 */
+	{0x0073,0x00},   /* LCD Cursor X Position Register 1 */
+	{0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
+	{0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
+	{0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
+	{0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
+	{0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
+	{0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
+	{0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
+	{0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
+	{0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
+	{0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
+	{0x0081,0x01},   /* CRT/TV Ink/Cursor Start Address Register */
+	{0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
+	{0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
+	{0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
+	{0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
+	{0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
+	{0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
+	{0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
+	{0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
+	{0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
+	{0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
+	{0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
+	{0x0100,0x00},   /* BitBlt Control Register 0 */
+	{0x0101,0x00},   /* BitBlt Control Register 1 */
+	{0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
+	{0x0103,0x00},   /* BitBlt Operation Register */
+	{0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
+	{0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
+	{0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
+	{0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
+	{0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
+	{0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
+	{0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
+	{0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
+	{0x0110,0x00},   /* BitBlt Width Register 0 */
+	{0x0111,0x00},   /* BitBlt Width Register 1 */
+	{0x0112,0x00},   /* BitBlt Height Register 0 */
+	{0x0113,0x00},   /* BitBlt Height Register 1 */
+	{0x0114,0x00},   /* BitBlt Background Color Register 0 */
+	{0x0115,0x00},   /* BitBlt Background Color Register 1 */
+	{0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
+	{0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
+	{0x01E0,0x00},   /* Look-Up Table Mode Register */
+	{0x01E2,0x00},   /* Look-Up Table Address Register */
+	{0x01F0,0x10},   /* Power Save Configuration Register */
+	{0x01F1,0x00},   /* Power Save Status Register */
+	{0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
+	{0x01FC,0x01},   /* Display Mode Register */
+};
--- a/board/esd/common/s1d13806_320_240_4bpp.h
+++ b/board/esd/common/s1d13806_320_240_4bpp.h
@@ -0,0 +1,125 @@
+/*
+ *
+ *  File generated by S1D13806CFG.EXE
+ *
+ *  Copyright (c) 2000,2001 Epson Research and Development, Inc.
+ *  All rights reserved.
+ *
+ *  PLEASE NOTE: If you FTP this file to a non-Windows platform, make
+ *               sure you transfer this file using ASCII, not BINARY mode.
+ *
+ * Panel:  (active)   320x240 62Hz STN Single 4-bit (PCLK=CLKI2/4=6.250MHz)
+ * Memory: Embedded SDRAM (MCLK=CLKI=49.500MHz) (BUSCLK=33.333MHz)
+ *
+ */
+
+static S1D_REGS regs_13806_320_240_4bpp[] =
+{
+	{0x0001,0x00},   /* Miscellaneous Register */
+	{0x01FC,0x00},   /* Display Mode Register */
+	{0x0004,0x08},   /* General IO Pins Configuration Register 0 */
+	{0x0005,0x08},   /* General IO Pins Configuration Register 1 */
+	{0x0008,0x08},   /* General IO Pins Control Register 0 */
+	{0x0009,0x00},   /* General IO Pins Control Register 1 */
+	{0x0010,0x00},   /* Memory Clock Configuration Register */
+	{0x0014,0x32},   /* LCD Pixel Clock Configuration Register */
+	{0x0018,0x00},   /* CRT/TV Pixel Clock Configuration Register */
+	{0x001C,0x02},   /* MediaPlug Clock Configuration Register */
+	{0x001E,0x01},   /* CPU To Memory Wait State Select Register */
+	{0x0021,0x03},   /* DRAM Refresh Rate Register */
+	{0x002A,0x00},   /* DRAM Timings Control Register 0 */
+	{0x002B,0x01},   /* DRAM Timings Control Register 1 */
+	{0x0020,0x80},   /* Memory Configuration Register */
+	{0x0030,0x00},   /* Panel Type Register */
+	{0x0031,0x00},   /* MOD Rate Register */
+	{0x0032,0x27},   /* LCD Horizontal Display Width Register */
+	{0x0034,0x03},   /* LCD Horizontal Non-Display Period Register */
+	{0x0035,0x01},   /* TFT FPLINE Start Position Register */
+	{0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
+	{0x0038,0xEF},   /* LCD Vertical Display Height Register 0 */
+	{0x0039,0x00},   /* LCD Vertical Display Height Register 1 */
+	{0x003A,0x2C},   /* LCD Vertical Non-Display Period Register */
+	{0x003B,0x0A},   /* TFT FPFRAME Start Position Register */
+	{0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
+	{0x0040,0x02},   /* LCD Display Mode Register */
+	{0x0041,0x00},   /* LCD Miscellaneous Register */
+	{0x0042,0x00},   /* LCD Display Start Address Register 0 */
+	{0x0043,0x00},   /* LCD Display Start Address Register 1 */
+	{0x0044,0x00},   /* LCD Display Start Address Register 2 */
+	{0x0046,0x50},   /* LCD Memory Address Offset Register 0 */
+	{0x0047,0x00},   /* LCD Memory Address Offset Register 1 */
+	{0x0048,0x00},   /* LCD Pixel Panning Register */
+	{0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
+	{0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
+	{0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
+	{0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
+	{0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
+	{0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
+	{0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
+	{0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
+	{0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
+	{0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
+	{0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
+	{0x005B,0x10},   /* TV Output Control Register */
+	{0x0060,0x03},   /* CRT/TV Display Mode Register */
+	{0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
+	{0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
+	{0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
+	{0x0066,0x40},   /* CRT/TV Memory Address Offset Register 0 */
+	{0x0067,0x01},   /* CRT/TV Memory Address Offset Register 1 */
+	{0x0068,0x00},   /* CRT/TV Pixel Panning Register */
+	{0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
+	{0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
+	{0x0070,0x00},   /* LCD Ink/Cursor Control Register */
+	{0x0071,0x01},   /* LCD Ink/Cursor Start Address Register */
+	{0x0072,0x00},   /* LCD Cursor X Position Register 0 */
+	{0x0073,0x00},   /* LCD Cursor X Position Register 1 */
+	{0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
+	{0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
+	{0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
+	{0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
+	{0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
+	{0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
+	{0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
+	{0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
+	{0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
+	{0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
+	{0x0081,0x01},   /* CRT/TV Ink/Cursor Start Address Register */
+	{0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
+	{0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
+	{0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
+	{0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
+	{0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
+	{0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
+	{0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
+	{0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
+	{0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
+	{0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
+	{0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
+	{0x0100,0x00},   /* BitBlt Control Register 0 */
+	{0x0101,0x00},   /* BitBlt Control Register 1 */
+	{0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
+	{0x0103,0x00},   /* BitBlt Operation Register */
+	{0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
+	{0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
+	{0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
+	{0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
+	{0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
+	{0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
+	{0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
+	{0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
+	{0x0110,0x00},   /* BitBlt Width Register 0 */
+	{0x0111,0x00},   /* BitBlt Width Register 1 */
+	{0x0112,0x00},   /* BitBlt Height Register 0 */
+	{0x0113,0x00},   /* BitBlt Height Register 1 */
+	{0x0114,0x00},   /* BitBlt Background Color Register 0 */
+	{0x0115,0x00},   /* BitBlt Background Color Register 1 */
+	{0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
+	{0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
+	{0x01E0,0x00},   /* Look-Up Table Mode Register */
+	{0x01E2,0x00},   /* Look-Up Table Address Register */
+	{0x01F0,0x10},   /* Power Save Configuration Register */
+	{0x01F1,0x00},   /* Power Save Status Register */
+	{0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
+	{0x01FC,0x01},   /* Display Mode Register */
+};
--- a/board/esd/common/s1d13806_640_480_16bpp.h
+++ b/board/esd/common/s1d13806_640_480_16bpp.h
@@ -0,0 +1,125 @@
+/*
+ *
+ *  File generated by S1D13806CFG.EXE
+ *
+ *  Copyright (c) 2000,2001 Epson Research and Development, Inc.
+ *  All rights reserved.
+ *
+ *  PLEASE NOTE: If you FTP this file to a non-Windows platform, make
+ *               sure you transfer this file using ASCII, not BINARY mode.
+ *
+ * Panel:  (active)   640x480 59Hz TFT Single 18-bit (PCLK=CLKI2=25.000MHz)
+ * Memory: Embedded SDRAM (MCLK=CLKI=49.152MHz) (BUSCLK=33.333MHz)
+ *
+ */
+
+static S1D_REGS regs_13806_640_480_16bpp[] =
+{
+	{0x0001,0x00},   /* Miscellaneous Register */
+	{0x01FC,0x00},   /* Display Mode Register */
+	{0x0004,0x18},   /* General IO Pins Configuration Register 0 */
+	{0x0005,0x00},   /* General IO Pins Configuration Register 1 */
+	{0x0008,0x18},   /* General IO Pins Control Register 0 */
+	{0x0009,0x00},   /* General IO Pins Control Register 1 */
+	{0x0010,0x00},   /* Memory Clock Configuration Register */
+	{0x0014,0x02},   /* LCD Pixel Clock Configuration Register */
+	{0x0018,0x02},   /* CRT/TV Pixel Clock Configuration Register */
+	{0x001C,0x02},   /* MediaPlug Clock Configuration Register */
+	{0x001E,0x01},   /* CPU To Memory Wait State Select Register */
+	{0x0021,0x03},   /* DRAM Refresh Rate Register */
+	{0x002A,0x00},   /* DRAM Timings Control Register 0 */
+	{0x002B,0x01},   /* DRAM Timings Control Register 1 */
+	{0x0020,0x80},   /* Memory Configuration Register */
+	{0x0030,0x25},   /* Panel Type Register */
+	{0x0031,0x00},   /* MOD Rate Register */
+	{0x0032,0x4F},   /* LCD Horizontal Display Width Register */
+	{0x0034,0x13},   /* LCD Horizontal Non-Display Period Register */
+	{0x0035,0x00},   /* TFT FPLINE Start Position Register */
+	{0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
+	{0x0038,0xDF},   /* LCD Vertical Display Height Register 0 */
+	{0x0039,0x01},   /* LCD Vertical Display Height Register 1 */
+	{0x003A,0x24},   /* LCD Vertical Non-Display Period Register */
+	{0x003B,0x00},   /* TFT FPFRAME Start Position Register */
+	{0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
+	{0x0040,0x05},   /* LCD Display Mode Register */
+	{0x0041,0x00},   /* LCD Miscellaneous Register */
+	{0x0042,0x00},   /* LCD Display Start Address Register 0 */
+	{0x0043,0x00},   /* LCD Display Start Address Register 1 */
+	{0x0044,0x00},   /* LCD Display Start Address Register 2 */
+	{0x0046,0x80},   /* LCD Memory Address Offset Register 0 */
+	{0x0047,0x02},   /* LCD Memory Address Offset Register 1 */
+	{0x0048,0x00},   /* LCD Pixel Panning Register */
+	{0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
+	{0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
+	{0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
+	{0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
+	{0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
+	{0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
+	{0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
+	{0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
+	{0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
+	{0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
+	{0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
+	{0x005B,0x10},   /* TV Output Control Register */
+	{0x0060,0x05},   /* CRT/TV Display Mode Register */
+	{0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
+	{0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
+	{0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
+	{0x0066,0x80},   /* CRT/TV Memory Address Offset Register 0 */
+	{0x0067,0x02},   /* CRT/TV Memory Address Offset Register 1 */
+	{0x0068,0x00},   /* CRT/TV Pixel Panning Register */
+	{0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
+	{0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
+	{0x0070,0x00},   /* LCD Ink/Cursor Control Register */
+	{0x0071,0x01},   /* LCD Ink/Cursor Start Address Register */
+	{0x0072,0x00},   /* LCD Cursor X Position Register 0 */
+	{0x0073,0x00},   /* LCD Cursor X Position Register 1 */
+	{0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
+	{0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
+	{0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
+	{0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
+	{0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
+	{0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
+	{0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
+	{0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
+	{0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
+	{0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
+	{0x0081,0x01},   /* CRT/TV Ink/Cursor Start Address Register */
+	{0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
+	{0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
+	{0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
+	{0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
+	{0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
+	{0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
+	{0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
+	{0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
+	{0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
+	{0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
+	{0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
+	{0x0100,0x00},   /* BitBlt Control Register 0 */
+	{0x0101,0x00},   /* BitBlt Control Register 1 */
+	{0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
+	{0x0103,0x00},   /* BitBlt Operation Register */
+	{0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
+	{0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
+	{0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
+	{0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
+	{0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
+	{0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
+	{0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
+	{0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
+	{0x0110,0x00},   /* BitBlt Width Register 0 */
+	{0x0111,0x00},   /* BitBlt Width Register 1 */
+	{0x0112,0x00},   /* BitBlt Height Register 0 */
+	{0x0113,0x00},   /* BitBlt Height Register 1 */
+	{0x0114,0x00},   /* BitBlt Background Color Register 0 */
+	{0x0115,0x00},   /* BitBlt Background Color Register 1 */
+	{0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
+	{0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
+	{0x01E0,0x00},   /* Look-Up Table Mode Register */
+	{0x01E2,0x00},   /* Look-Up Table Address Register */
+	{0x01F0,0x10},   /* Power Save Configuration Register */
+	{0x01F1,0x00},   /* Power Save Status Register */
+	{0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
+	{0x01FC,0x01},   /* Display Mode Register */
+};
--- a/board/esd/common/s1d13806_640_480_8bpp.h
+++ b/board/esd/common/s1d13806_640_480_8bpp.h
@@ -0,0 +1,125 @@
+/*
+ *
+ *  File generated by S1D13806CFG.EXE
+ *
+ *  Copyright (c) 2000,2001 Epson Research and Development, Inc.
+ *  All rights reserved.
+ *
+ *  PLEASE NOTE: If you FTP this file to a non-Windows platform, make
+ *               sure you transfer this file using ASCII, not BINARY mode.
+ *
+ * Panel:  (active)   640x480 59Hz TFT Single 18-bit (PCLK=CLKI2=25.000MHz)
+ * Memory: Embedded SDRAM (MCLK=CLKI=49.152MHz) (BUSCLK=33.333MHz)
+ *
+ */
+
+static S1D_REGS regs_13806_640_320_16bpp[] =
+{
+	{0x0001,0x00},   /* Miscellaneous Register */
+	{0x01FC,0x00},   /* Display Mode Register */
+	{0x0004,0x18},   /* General IO Pins Configuration Register 0 */
+	{0x0005,0x00},   /* General IO Pins Configuration Register 1 */
+	{0x0008,0x18},   /* General IO Pins Control Register 0 */
+	{0x0009,0x00},   /* General IO Pins Control Register 1 */
+	{0x0010,0x00},   /* Memory Clock Configuration Register */
+	{0x0014,0x02},   /* LCD Pixel Clock Configuration Register */
+	{0x0018,0x02},   /* CRT/TV Pixel Clock Configuration Register */
+	{0x001C,0x02},   /* MediaPlug Clock Configuration Register */
+	{0x001E,0x01},   /* CPU To Memory Wait State Select Register */
+	{0x0021,0x03},   /* DRAM Refresh Rate Register */
+	{0x002A,0x00},   /* DRAM Timings Control Register 0 */
+	{0x002B,0x01},   /* DRAM Timings Control Register 1 */
+	{0x0020,0x80},   /* Memory Configuration Register */
+	{0x0030,0x25},   /* Panel Type Register */
+	{0x0031,0x00},   /* MOD Rate Register */
+	{0x0032,0x4F},   /* LCD Horizontal Display Width Register */
+	{0x0034,0x13},   /* LCD Horizontal Non-Display Period Register */
+	{0x0035,0x00},   /* TFT FPLINE Start Position Register */
+	{0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
+	{0x0038,0xDF},   /* LCD Vertical Display Height Register 0 */
+	{0x0039,0x01},   /* LCD Vertical Display Height Register 1 */
+	{0x003A,0x24},   /* LCD Vertical Non-Display Period Register */
+	{0x003B,0x00},   /* TFT FPFRAME Start Position Register */
+	{0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
+	{0x0040,0x03},   /* LCD Display Mode Register (8bpp) */
+	{0x0041,0x00},   /* LCD Miscellaneous Register */
+	{0x0042,0x00},   /* LCD Display Start Address Register 0 */
+	{0x0043,0x00},   /* LCD Display Start Address Register 1 */
+	{0x0044,0x00},   /* LCD Display Start Address Register 2 */
+	{0x0046,0x80},   /* LCD Memory Address Offset Register 0 */
+	{0x0047,0x02},   /* LCD Memory Address Offset Register 1 */
+	{0x0048,0x00},   /* LCD Pixel Panning Register */
+	{0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
+	{0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
+	{0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
+	{0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
+	{0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
+	{0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
+	{0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
+	{0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
+	{0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
+	{0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
+	{0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
+	{0x005B,0x10},   /* TV Output Control Register */
+	{0x0060,0x05},   /* CRT/TV Display Mode Register */
+	{0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
+	{0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
+	{0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
+	{0x0066,0x80},   /* CRT/TV Memory Address Offset Register 0 */
+	{0x0067,0x02},   /* CRT/TV Memory Address Offset Register 1 */
+	{0x0068,0x00},   /* CRT/TV Pixel Panning Register */
+	{0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
+	{0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
+	{0x0070,0x00},   /* LCD Ink/Cursor Control Register */
+	{0x0071,0x01},   /* LCD Ink/Cursor Start Address Register */
+	{0x0072,0x00},   /* LCD Cursor X Position Register 0 */
+	{0x0073,0x00},   /* LCD Cursor X Position Register 1 */
+	{0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
+	{0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
+	{0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
+	{0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
+	{0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
+	{0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
+	{0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
+	{0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
+	{0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
+	{0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
+	{0x0081,0x01},   /* CRT/TV Ink/Cursor Start Address Register */
+	{0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
+	{0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
+	{0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
+	{0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
+	{0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
+	{0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
+	{0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
+	{0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
+	{0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
+	{0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
+	{0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
+	{0x0100,0x00},   /* BitBlt Control Register 0 */
+	{0x0101,0x00},   /* BitBlt Control Register 1 */
+	{0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
+	{0x0103,0x00},   /* BitBlt Operation Register */
+	{0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
+	{0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
+	{0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
+	{0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
+	{0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
+	{0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
+	{0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
+	{0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
+	{0x0110,0x00},   /* BitBlt Width Register 0 */
+	{0x0111,0x00},   /* BitBlt Width Register 1 */
+	{0x0112,0x00},   /* BitBlt Height Register 0 */
+	{0x0113,0x00},   /* BitBlt Height Register 1 */
+	{0x0114,0x00},   /* BitBlt Background Color Register 0 */
+	{0x0115,0x00},   /* BitBlt Background Color Register 1 */
+	{0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
+	{0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
+	{0x01E0,0x00},   /* Look-Up Table Mode Register */
+	{0x01E2,0x00},   /* Look-Up Table Address Register */
+	{0x01F0,0x10},   /* Power Save Configuration Register */
+	{0x01F1,0x00},   /* Power Save Status Register */
+	{0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
+	{0x01FC,0x01},   /* Display Mode Register */
+};
--- a/board/esd/cpci405/Makefile
+++ b/board/esd/cpci405/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk

 LIB	= lib$(BOARD).a

-OBJS	= $(BOARD).o flash.o
+OBJS	= $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o

 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS)
--- a/board/esd/cpci405/config.mk
+++ b/board/esd/cpci405/config.mk
@@ -28,9 +28,13 @@
 ifeq ($(BOARD_REVISION),CPCI4052)
 TEXT_BASE = 0xFFFC0000
 else
+ifeq ($(BOARD_REVISION),CPCI405DT)
+TEXT_BASE = 0xFFFC0000
+else
 ifeq ($(BOARD_REVISION),CPCI405AB)
 TEXT_BASE = 0xFFFC0000
 else
 TEXT_BASE = 0xFFFD0000
 endif
 endif
+endif
--- a/board/esd/cpci405/cpci405.c
+++ b/board/esd/cpci405/cpci405.c
@@ -25,6 +25,7 @@
 #include <asm/processor.h>
 #include <command.h>
 #include <malloc.h>
+#include <net.h>

 /* ------------------------------------------------------------------------- */
 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);       /*cmd_boot.c*/
@@ -52,9 +53,43 @@ const unsigned char fpgadata[] =
 #include "../common/fpga.c"


+#include "../common/auto_update.h"
+
+#ifdef CONFIG_CPCI405AB
+au_image_t au_image[] = {
+	{"cpci405ab/preinst.img", 0, -1, AU_SCRIPT},
+	{"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR},
+	{"cpci405ab/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
+	{"cpci405ab/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
+	{"cpci405ab/postinst.img", 0, 0, AU_SCRIPT},
+};
+#else
+#ifdef CONFIG_CPCI405_VER2
+au_image_t au_image[] = {
+	{"cpci4052/preinst.img", 0, -1, AU_SCRIPT},
+	{"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR},
+	{"cpci4052/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
+	{"cpci4052/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
+	{"cpci4052/postinst.img", 0, 0, AU_SCRIPT},
+};
+#else
+au_image_t au_image[] = {
+	{"cpci405/preinst.img", 0, -1, AU_SCRIPT},
+	{"cpci405/pImage", 0xffc00000, 0x000c0000, AU_NOR},
+	{"cpci405/pImage.initrd", 0xffcc0000, 0x00310000, AU_NOR},
+	{"cpci405/u-boot.img", 0xfffd0000, 0x00030000, AU_FIRMWARE},
+	{"cpci405/postinst.img", 0, 0, AU_SCRIPT},
+};
+#endif
+#endif
+
+int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
+
+
 /* Prototypes */
 int cpci405_version(void);
 int gunzip(void *, int, unsigned char *, unsigned long *);
+void lxt971_no_sleep(void);


 int board_early_init_f (void)
@@ -234,12 +269,14 @@ int misc_init_f (void)
 int misc_init_r (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
-
-	bd_t *bd = gd->bd;
-	char *	tmp;                    /* Temporary char pointer      */
 	unsigned long cntrl0Reg;

+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
 #ifdef CONFIG_CPCI405_VER2
+	{
 	unsigned char *dst;
 	ulong len = sizeof(fpgadata);
 	int status;
@@ -348,9 +385,11 @@ int misc_init_r (void)
 		puts("*** CPCI-405 Version 1.x detected!\n");
 		puts("*** Please use correct U-Boot version (CPCI405 instead of CPCI4052)!\n\n");
 	}
+	}

 #else /* CONFIG_CPCI405_VER2 */

+#if 0 /* test-only: code-plug now not relavant for ip-address any more */
 	/*
 	 * Generate last byte of ip-addr from code-plug @ 0xf0000400
 	 */
@@ -371,6 +410,7 @@ int misc_init_r (void)
 			setenv("ipaddr", str);
 		}
 	}
+#endif

 	if (cpci405_version() >= 2) {
 		puts("\n*** U-Boot Version does not match Board Version!\n");
@@ -386,11 +426,6 @@ int misc_init_r (void)
 	cntrl0Reg = mfdcr(cntrl0);
 	mtdcr(cntrl0, cntrl0Reg | 0x00001000);

-	/*
-	 * Write ethernet addr in NVRAM for VxWorks
-	 */
-	tmp = (char *)CFG_NVRAM_BASE_ADDR + CFG_NVRAM_VXWORKS_OFFS;
-	memcpy( (char *)tmp, (char *)&bd->bi_enetaddr[0], 6 );
 	return (0);
 }

@@ -463,6 +498,11 @@ int checkboard (void)

 	putc ('\n');

+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+
 	return 0;
 }

@@ -518,9 +558,12 @@ void ide_set_reset(int on)

 #ifdef CONFIG_CPCI405AB

-#define ONE_WIRE_CLEAR   (*(volatile unsigned short *)0xf0400000 |= 0x0100)
-#define ONE_WIRE_SET     (*(volatile unsigned short *)0xf0400000 &= ~0x0100)
-#define ONE_WIRE_GET     (*(volatile unsigned short *)0xf0400002 & 0x1000)
+#define ONE_WIRE_CLEAR   (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
+			  |= CFG_FPGA_MODE_1WIRE_DIR)
+#define ONE_WIRE_SET     (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
+			  &= ~CFG_FPGA_MODE_1WIRE_DIR)
+#define ONE_WIRE_GET     (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \
+			  & CFG_FPGA_MODE_1WIRE)

 /*
 * Generate a 1-wire reset, return 1 if no presence detect was found,
@@ -655,4 +698,102 @@ U_BOOT_CMD(
 	NULL
 	);

+
+#define CFG_I2C_EEPROM_ADDR_2	0x51	/* EEPROM CAT28WC32		*/
+#define CFG_ENV_SIZE_2	0x800	/* 2048 bytes may be used for env vars*/
+
+/*
+ * Write backplane ip-address...
+ */
+int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	bd_t *bd = gd->bd;
+	char *buf;
+	ulong crc;
+	char str[32];
+	char *ptr;
+	IPaddr_t ipaddr;
+
+	buf = malloc(CFG_ENV_SIZE_2);
+	if (eeprom_read(CFG_I2C_EEPROM_ADDR_2, 0, buf, CFG_ENV_SIZE_2)) {
+		puts("\nError reading backplane EEPROM!\n");
+	} else {
+		crc = crc32(0, buf+4, CFG_ENV_SIZE_2-4);
+		if (crc != *(ulong *)buf) {
+			printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(ulong *)buf);
+			return -1;
+		}
+
+		/*
+		 * Find bp_ip
+		 */
+		ptr = strstr(buf+4, "bp_ip=");
+		if (ptr == NULL) {
+			printf("ERROR: bp_ip not found!\n");
+			return -1;
+		}
+		ptr += 6;
+		ipaddr = string_to_ip(ptr);
+
+		/*
+		 * Update whole ip-addr
+		 */
+		bd->bi_ip_addr = ipaddr;
+		sprintf(str, "%ld.%ld.%ld.%ld",
+			(bd->bi_ip_addr & 0xff000000) >> 24,
+			(bd->bi_ip_addr & 0x00ff0000) >> 16,
+			(bd->bi_ip_addr & 0x0000ff00) >> 8,
+			(bd->bi_ip_addr & 0x000000ff));
+		setenv("ipaddr", str);
+		printf("Updated ip_addr from bp_eeprom to %s!\n", str);
+	}
+
+	free(buf);
+
+	return 0;
+}
+U_BOOT_CMD(
+	getbpip,	1,	1,	do_get_bpip,
+	"getbpip - Update IP-Address with Backplane IP-Address\n",
+	NULL
+	);
+
+/*
+ * Set and print backplane ip...
+ */
+int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	char *buf;
+	unsigned char str[32];
+	ulong crc;
+
+	if (argc < 2) {
+		puts("ERROR!\n");
+		return -1;
+	}
+
+	printf("Setting bp_ip to %s\n", argv[1]);
+	buf = malloc(CFG_ENV_SIZE_2);
+	memset(buf, 0, CFG_ENV_SIZE_2);
+	sprintf(str, "bp_ip=%s", argv[1]);
+	strcpy(buf+4, str);
+	crc = crc32(0, buf+4, CFG_ENV_SIZE_2-4);
+	*(ulong *)buf = crc;
+
+	if (eeprom_write(CFG_I2C_EEPROM_ADDR_2, 0, buf, CFG_ENV_SIZE_2)) {
+		puts("\nError writing backplane EEPROM!\n");
+	}
+
+	free(buf);
+
+	return 0;
+}
+U_BOOT_CMD(
+	setbpip,	2,	1,	do_set_bpip,
+	"setbpip - Write Backplane IP-Address\n",
+	NULL
+	);
+
 #endif /* CONFIG_CPCI405AB */
--- a/board/esd/cpci405/fpgadata_cpci405ab.c
+++ b/board/esd/cpci405/fpgadata_cpci405ab.c
--- a/board/esd/cpci440/Makefile
+++ b/board/esd/cpci440/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk

 LIB	= lib$(BOARD).a

-OBJS	= $(BOARD).o strataflash.o
+OBJS	= $(BOARD).o strataflash.o ../common/misc.o
 SOBJS	= init.o

 $(LIB):	$(OBJS) $(SOBJS)
--- a/board/esd/cpci440/config.mk
+++ b/board/esd/cpci440/config.mk
@@ -31,6 +31,7 @@ ifeq ($(ramsym),1)
 TEXT_BASE = 0x07FD0000
 else
 TEXT_BASE = 0xFFFC0000
+#TEXT_BASE = 0x01fc0000
 endif

 PLATFORM_CPPFLAGS += -DCONFIG_440=1
--- a/board/esd/cpci440/cpci440.c
+++ b/board/esd/cpci440/cpci440.c
@@ -26,6 +26,9 @@
 #include <asm/processor.h>


+extern void lxt971_no_sleep(void);
+
+
 long int fixed_sdram( void );

 int board_early_init_f (void)
@@ -77,6 +80,12 @@ int checkboard (void)
 	printf("\tPLB: %lu MHz\n", sysinfo.freqPLB/1000000);
 	printf("\tOPB: %lu MHz\n", sysinfo.freqOPB/1000000);
 	printf("\tEPB: %lu MHz\n", sysinfo.freqEPB/1000000);
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+
 	return (0);
 }

@@ -101,6 +110,7 @@ long int fixed_sdram( void )
 {
 	uint    reg;

+#if 1 /* test-only */
 	/*--------------------------------------------------------------------
 	 * Setup some default
 	 *------------------------------------------------------------------*/
@@ -136,4 +146,7 @@ long int fixed_sdram( void )
 	}

 	return( 64 * 1024 * 1024 );      /* 64 MB                           */
+#else
+	return( 32 * 1024 * 1024 );      /* 64 MB                           */
+#endif
 }
--- a/board/esd/cpci440/u-boot.lds
+++ b/board/esd/cpci440/u-boot.lds
@@ -28,11 +28,13 @@ SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/
 SECTIONS
 {
  .resetvec 0xFFFFFFFC :
+/*  .resetvec 0x01FFFFFC :*/
  {
    *(.resetvec)
  } = 0xffff

  .bootpg 0xFFFFF000 :
+/*  .bootpg 0x01FFF000 :*/
  {
    cpu/ppc4xx/start.o	(.bootpg)
  } = 0xffff
--- a/board/esd/cpci750/64360.h
+++ b/board/esd/cpci750/64360.h
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ * for cpci750 Reinhard Arlt
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * main board support/init for the cpci750.
+ */
+
+#ifndef __64360_H__
+#define __64360_H__
+
+/* CPU Configuration bits */
+#define CPU_CONF_ADDR_MISS_EN	(1 << 8)
+#define	CPU_CONF_SINGLE_CPU	(1 << 11)
+#define	CPU_CONF_ENDIANESS	(1 << 12)
+#define CPU_CONF_PIPELINE	(1 << 13)
+#define CPU_CONF_STOP_RETRY	(1 << 17)
+#define CPU_CONF_MULTI_DECODE	(1 << 18)
+#define CPU_CONF_DP_VALID	(1 << 19)
+#define CPU_CONF_PERR_PROP	(1 << 22)
+#define CPU_CONF_AACK_DELAY_2	(1 << 25)
+#define CPU_CONF_AP_VALID	(1 << 26)
+#define CPU_CONF_REMAP_WR_DIS	(1 << 27)
+
+/* CPU Master Control bits */
+#define CPU_MAST_CTL_ARB_EN	(1 << 8)
+#define CPU_MAST_CTL_MASK_BR_1	(1 << 9)
+#define CPU_MAST_CTL_M_WR_TRIG	(1 << 10)
+#define CPU_MAST_CTL_M_RD_TRIG	(1 << 11)
+#define CPU_MAST_CTL_CLEAN_BLK	(1 << 12)
+#define CPU_MAST_CTL_FLUSH_BLK	(1 << 13)
+
+#endif /* __64360_H__ */
--- a/board/esd/cpci750/Makefile
+++ b/board/esd/cpci750/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2001
+# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+SOBJS	= misc.o
+
+OBJS	= $(BOARD).o serial.o ../../Marvell/common/memory.o pci.o \
+	  mv_eth.o  mpsc.o i2c.o \
+	  sdram_init.o strataflash.o ide.o
+
+$(LIB):	.depend $(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- a/board/esd/cpci750/config.mk
+++ b/board/esd/cpci750/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2004
+# Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# cpci750 board
+#
+
+TEXT_BASE = 0xfff00000
--- a/board/esd/cpci750/cpci750.c
+++ b/board/esd/cpci750/cpci750.c
@@ -0,0 +1,885 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com
+ * modifications for the cpci750 by reinhard.arlt@esd-electronics.com
+ */
+
+/*
+ * cpci750.c - main board support/init for the esd cpci750.
+ */
+
+#include <common.h>
+#include <74xx_7xx.h>
+#include "../../Marvell/include/memory.h"
+#include "../../Marvell/include/pci.h"
+#include "../../Marvell/include/mv_gen_reg.h"
+#include <net.h>
+
+#include "eth.h"
+#include "mpsc.h"
+#include "i2c.h"
+#include "64360.h"
+#include "mv_regs.h"
+
+#undef	DEBUG
+/*#define	DEBUG */
+
+#ifdef CONFIG_PCI
+#define	MAP_PCI
+#endif /* of CONFIG_PCI */
+
+#ifdef DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+extern void flush_data_cache (void);
+extern void invalidate_l1_instruction_cache (void);
+
+/* ------------------------------------------------------------------------- */
+
+/* this is the current GT register space location */
+/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
+
+/* Unfortunately, we cant change it while we are in flash, so we initialize it
+ * to the "final" value. This means that any debug_led calls before
+ * board_early_init_f wont work right (like in cpu_init_f).
+ * See also my_remap_gt_regs below. (NTL)
+ */
+
+void board_prebootm_init (void);
+unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
+int display_mem_map (void);
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * This is a version of the GT register space remapping function that
+ * doesn't touch globals (meaning, it's ok to run from flash.)
+ *
+ * Unfortunately, this has the side effect that a writable
+ * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
+ */
+
+void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
+{
+	u32 temp;
+
+	/* check and see if it's already moved */
+
+/* original ppcboot 1.1.6 source
+
+	temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 20)
+		return;
+
+	temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 20);
+
+	out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
+original ppcboot 1.1.6 source end */
+
+	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 16)
+		return;
+
+	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 16);
+
+	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
+}
+
+#ifdef CONFIG_PCI
+
+static void gt_pci_config (void)
+{
+	unsigned int stat;
+	unsigned int val = 0x00fff864;	/* DINK32: BusNum 23:16,  DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
+
+	/* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
+	 * config registers by writing ones to the bus and device.
+	 * We then update the Virtual register with the correct value for the bus and device.
+	 */
+	if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
+		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
+
+		GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
+
+		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
+		GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
+			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
+
+	}
+	if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
+		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
+		GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
+
+		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
+		GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
+			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
+	}
+
+	/* Enable master */
+	PCI_MASTER_ENABLE (0, SELF);
+	PCI_MASTER_ENABLE (1, SELF);
+
+	/* Enable PCI0/1 Mem0 and IO 0 disable all others */
+	GT_REG_READ (BASE_ADDR_ENABLE, &stat);
+	stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
+									     <<
+									     18);
+	stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
+	GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
+
+	/* ronen- add write to pci remap registers for 64460.
+	   in 64360 when writing to pci base go and overide remap automaticaly,
+	   in 64460 it doesn't */
+	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_SPACE >> 16);
+	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_SPACE_PCI >> 16);
+	GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_SPACE >> 16);
+	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_SPACE_PCI >> 16);
+	GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16);
+
+	/* PCI interface settings */
+	/* Timeout set to retry forever */
+	GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
+	GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
+
+	/* ronen - enable only CS0 and Internal reg!! */
+	GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
+	GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
+
+/*ronen update the pci internal registers base address.*/
+#ifdef MAP_PCI
+	for (stat = 0; stat <= PCI_HOST1; stat++)
+		pciWriteConfigReg (stat,
+				   PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
+				   SELF, CFG_GT_REGS);
+#endif
+
+}
+#endif
+
+/* Setup CPU interface paramaters */
+static void gt_cpu_config (void)
+{
+	cpu_t cpu = get_cpu_type ();
+	ulong tmp;
+
+	/* cpu configuration register */
+	tmp = GTREGREAD (CPU_CONFIGURATION);
+
+	/* set the SINGLE_CPU bit  see MV64360 P.399 */
+#ifndef CFG_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
+	tmp |= CPU_CONF_SINGLE_CPU;
+#endif
+
+	tmp &= ~CPU_CONF_AACK_DELAY_2;
+
+	tmp |= CPU_CONF_DP_VALID;
+	tmp |= CPU_CONF_AP_VALID;
+
+	tmp |= CPU_CONF_PIPELINE;
+
+	GT_REG_WRITE (CPU_CONFIGURATION, tmp);	/* Marvell (VXWorks) writes 0x20220FF */
+
+	/* CPU master control register */
+	tmp = GTREGREAD (CPU_MASTER_CONTROL);
+
+	tmp |= CPU_MAST_CTL_ARB_EN;
+
+	if ((cpu == CPU_7400) ||
+	    (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
+
+		tmp |= CPU_MAST_CTL_CLEAN_BLK;
+		tmp |= CPU_MAST_CTL_FLUSH_BLK;
+
+	} else {
+		/* cleanblock must be cleared for CPUs
+		 * that do not support this command (603e, 750)
+		 * see Res#1 */
+		tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
+		tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
+	}
+	GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
+}
+
+/*
+ * board_early_init_f.
+ *
+ * set up gal. device mappings, etc.
+ */
+int board_early_init_f (void)
+{
+
+	/*
+	 * set up the GT the way the kernel wants it
+	 * the call to move the GT register space will obviously
+	 * fail if it has already been done, but we're going to assume
+	 * that if it's not at the power-on location, it's where we put
+	 * it last time. (huber)
+	 */
+
+	my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
+
+	/* No PCI in first release of Port To_do: enable it. */
+#ifdef CONFIG_PCI
+	gt_pci_config ();
+#endif
+	/* mask all external interrupt sources */
+	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
+	/* new in MV6436x */
+	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
+	/* --------------------- */
+	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
+	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
+	/* does not exist in MV6436x
+	   GT_REG_WRITE(CPU_INT_0_MASK, 0);
+	   GT_REG_WRITE(CPU_INT_1_MASK, 0);
+	   GT_REG_WRITE(CPU_INT_2_MASK, 0);
+	   GT_REG_WRITE(CPU_INT_3_MASK, 0);
+	   --------------------- */
+
+
+	/* ----- DEVICE BUS SETTINGS ------ */
+
+	/*
+	 * EVB
+	 * 0 - SRAM   ????
+	 * 1 - RTC      ????
+	 * 2 - UART     ????
+	 * 3 - Flash    checked 32Bit Intel Strata
+	 * boot - BootCS checked 8Bit 29LV040B
+	 *
+	 */
+
+	/*
+	 * the dual 7450 module requires burst access to the boot
+	 * device, so the serial rom copies the boot device to the
+	 * on-board sram on the eval board, and updates the correct
+	 * registers to boot from the sram. (device0)
+	 */
+
+	memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
+	memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE);
+	memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE);
+	memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE);
+
+
+	/* configure device timing */
+	GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR);
+	GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR);
+	GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);
+	GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_DEV3_PAR);
+
+#ifdef CFG_32BIT_BOOT_PAR	/* set port parameters for Flash device module access */
+	/* detect if we are booting from the 32 bit flash */
+	if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
+		/* 32 bit boot flash */
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
+			      CFG_32BIT_BOOT_PAR);
+	} else {
+		/* 8 bit boot flash */
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
+	}
+#else
+	/* 8 bit boot flash only */
+/*	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/
+#endif
+
+
+	gt_cpu_config ();
+
+	/* MPP setup */
+	GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0);
+	GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1);
+	GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2);
+	GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3);
+
+	GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
+	DEBUG_LED0_ON ();
+	DEBUG_LED1_ON ();
+	DEBUG_LED2_ON ();
+
+	return 0;
+}
+
+/* various things to do after relocation */
+
+int misc_init_r ()
+{
+	icache_enable ();
+#ifdef CFG_L2
+	l2cache_enable ();
+#endif
+#ifdef CONFIG_MPSC
+
+	mpsc_sdma_init ();
+	mpsc_init2 ();
+#endif
+
+#if 0
+	/* disable the dcache and MMU */
+	dcache_lock ();
+#endif
+	return 0;
+}
+
+void after_reloc (ulong dest_addr, gd_t * gd)
+{
+
+  memoryMapDeviceSpace (BOOT_DEVICE, CFG_BOOT_SPACE, CFG_BOOT_SIZE);
+
+  display_mem_map ();
+  /* now, jump to the main ppcboot board init code */
+  board_init_r (gd, dest_addr);
+  /* NOTREACHED */
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ *
+ * right now, assume borad type. (there is just one...after all)
+ */
+
+int checkboard (void)
+{
+	int l_type = 0;
+
+	printf ("BOARD: %s\n", CFG_BOARD_NAME);
+	return (l_type);
+}
+
+/* utility functions */
+void debug_led (int led, int mode)
+{
+}
+
+int display_mem_map (void)
+{
+	int i, j;
+	unsigned int base, size, width;
+
+	/* SDRAM */
+	printf ("SD (DDR) RAM\n");
+	for (i = 0; i <= BANK3; i++) {
+		base = memoryGetBankBaseAddress (i);
+		size = memoryGetBankSize (i);
+		if (size != 0) {
+			printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
+				i, base, size >> 20);
+		}
+	}
+#ifdef CONFIG_PCI
+	/* CPU's PCI windows */
+	for (i = 0; i <= PCI_HOST1; i++) {
+		printf ("\nCPU's PCI %d windows\n", i);
+		base = pciGetSpaceBase (i, PCI_IO);
+		size = pciGetSpaceSize (i, PCI_IO);
+		printf ("      IO: base - 0x%08x\tsize - %dM bytes\n", base,
+			size >> 20);
+		for (j = 0;
+		     j <=
+		     PCI_REGION0
+		     /*ronen currently only first PCI MEM is used 3 */ ;
+		     j++) {
+			base = pciGetSpaceBase (i, j);
+			size = pciGetSpaceSize (i, j);
+			printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
+		}
+	}
+#endif /* of CONFIG_PCI */
+	/* Devices */
+	printf ("\nDEVICES\n");
+	for (i = 0; i <= DEVICE3; i++) {
+		base = memoryGetDeviceBaseAddress (i);
+		size = memoryGetDeviceSize (i);
+		width = memoryGetDeviceWidth (i) * 8;
+		printf ("DEV %d:  base - 0x%08x  size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
+		if (i == 0)
+			printf ("\t- FLASH\n");
+		else if (i == 1)
+			printf ("\t- FLASH\n");
+		else if (i == 2)
+			printf ("\t- FLASH\n");
+		else
+			printf ("\t- RTC/REGS/CAN\n");
+	}
+
+	/* Bootrom */
+	base = memoryGetDeviceBaseAddress (BOOT_DEVICE);	/* Boot */
+	size = memoryGetDeviceSize (BOOT_DEVICE);
+	width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
+	printf (" BOOT:  base - 0x%08x  size - %dM bytes\twidth - %d bits\t- FLASH\n",
+		base, size >> 20, width);
+	return (0);
+}
+
+/* DRAM check routines copied from gw8260 */
+
+#if defined (CFG_DRAM_TEST)
+
+/*********************************************************************/
+/* NAME:  move64() -  moves a double word (64-bit)		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   this function performs a double word move from the data at	     */
+/*   the source pointer to the location at the destination pointer.  */
+/*								     */
+/* INPUTS:							     */
+/*   unsigned long long *src  - pointer to data to move		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   unsigned long long *dest - pointer to locate to move data	     */
+/*								     */
+/* RETURNS:							     */
+/*   None							     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*   May cloober fr0.						     */
+/*								     */
+/*********************************************************************/
+static void move64 (unsigned long long *src, unsigned long long *dest)
+{
+	asm ("lfd  0, 0(3)\n\t"	/* fpr0   =  *scr       */
+	     "stfd 0, 0(4)"	/* *dest  =  fpr0       */
+      : : : "fr0");		/* Clobbers fr0         */
+	return;
+}
+
+
+#if defined (CFG_DRAM_TEST_DATA)
+
+unsigned long long pattern[] = {
+	0xaaaaaaaaaaaaaaaa,
+	0xcccccccccccccccc,
+	0xf0f0f0f0f0f0f0f0,
+	0xff00ff00ff00ff00,
+	0xffff0000ffff0000,
+	0xffffffff00000000,
+	0x00000000ffffffff,
+	0x0000ffff0000ffff,
+	0x00ff00ff00ff00ff,
+	0x0f0f0f0f0f0f0f0f,
+	0x3333333333333333,
+	0x5555555555555555
+};
+
+/*********************************************************************/
+/* NAME:  mem_test_data() -  test data lines for shorts and opens    */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Tests data lines for shorts and opens by forcing adjacent data  */
+/*   to opposite states. Because the data lines could be routed in   */
+/*   an arbitrary manner the must ensure test patterns ensure that   */
+/*   every case is tested. By using the following series of binary   */
+/*   patterns every combination of adjacent bits is test regardless  */
+/*   of routing.						     */
+/*								     */
+/*     ...101010101010101010101010				     */
+/*     ...110011001100110011001100				     */
+/*     ...111100001111000011110000				     */
+/*     ...111111110000000011111111				     */
+/*								     */
+/*   Carrying this out, gives us six hex patterns as follows:	     */
+/*								     */
+/*     0xaaaaaaaaaaaaaaaa					     */
+/*     0xcccccccccccccccc					     */
+/*     0xf0f0f0f0f0f0f0f0					     */
+/*     0xff00ff00ff00ff00					     */
+/*     0xffff0000ffff0000					     */
+/*     0xffffffff00000000					     */
+/*								     */
+/*   The number test patterns will always be given by:		     */
+/*								     */
+/*   log(base 2)(number data bits) = log2 (64) = 6		     */
+/*								     */
+/*   To test for short and opens to other signals on our boards. we  */
+/*   simply							     */
+/*   test with the 1's complemnt of the paterns as well.	     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern				     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*  Assumes only one one SDRAM bank				     */
+/*								     */
+/*********************************************************************/
+int mem_test_data (void)
+{
+	unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
+	unsigned long long temp64;
+	int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
+	int i;
+	unsigned int hi, lo;
+
+	for (i = 0; i < num_patterns; i++) {
+		move64 (&(pattern[i]), pmem);
+		move64 (pmem, &temp64);
+
+		/* hi = (temp64>>32) & 0xffffffff;          */
+		/* lo = temp64 & 0xffffffff;                */
+		/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
+
+		hi = (pattern[i] >> 32) & 0xffffffff;
+		lo = pattern[i] & 0xffffffff;
+		/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo);  */
+
+		if (temp64 != pattern[i]) {
+			printf ("\n   Data Test Failed, pattern 0x%08x%08x",
+				hi, lo);
+			return 1;
+		}
+	}
+
+	return 0;
+}
+#endif /* CFG_DRAM_TEST_DATA */
+
+#if defined (CFG_DRAM_TEST_ADDRESS)
+/*********************************************************************/
+/* NAME:  mem_test_address() -	test address lines		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   This function performs a test to verify that each word im	     */
+/*   memory is uniquly addressable. The test sequence is as follows: */
+/*								     */
+/*   1) write the address of each word to each word.		     */
+/*   2) verify that each location equals its address		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern and address			     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_test_address (void)
+{
+	volatile unsigned int *pmem =
+		(volatile unsigned int *) CFG_MEMTEST_START;
+	const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4;
+	unsigned int i;
+
+	/* write address to each location */
+	for (i = 0; i < size; i++) {
+		pmem[i] = i;
+	}
+
+	/* verify each loaction */
+	for (i = 0; i < size; i++) {
+		if (pmem[i] != i) {
+			printf ("\n   Address Test Failed at 0x%x", i);
+			return 1;
+		}
+	}
+	return 0;
+}
+#endif /* CFG_DRAM_TEST_ADDRESS */
+
+#if defined (CFG_DRAM_TEST_WALK)
+/*********************************************************************/
+/* NAME:   mem_march() -  memory march				     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Marches up through memory. At each location verifies rmask if   */
+/*   read = 1. At each location write wmask if	write = 1. Displays  */
+/*   failing address and pattern.				     */
+/*								     */
+/* INPUTS:							     */
+/*   volatile unsigned long long * base - start address of test	     */
+/*   unsigned int size - number of dwords(64-bit) to test	     */
+/*   unsigned long long rmask - read verify mask		     */
+/*   unsigned long long wmask - wrtie verify mask		     */
+/*   short read - verifies rmask if read = 1			     */
+/*   short write  - writes wmask if write = 1			     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern and address			     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_march (volatile unsigned long long *base,
+	       unsigned int size,
+	       unsigned long long rmask,
+	       unsigned long long wmask, short read, short write)
+{
+	unsigned int i;
+	unsigned long long temp;
+	unsigned int hitemp, lotemp, himask, lomask;
+
+	for (i = 0; i < size; i++) {
+		if (read != 0) {
+			/* temp = base[i]; */
+			move64 ((unsigned long long *) &(base[i]), &temp);
+			if (rmask != temp) {
+				hitemp = (temp >> 32) & 0xffffffff;
+				lotemp = temp & 0xffffffff;
+				himask = (rmask >> 32) & 0xffffffff;
+				lomask = rmask & 0xffffffff;
+
+				printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
+				return 1;
+			}
+		}
+		if (write != 0) {
+			/*  base[i] = wmask; */
+			move64 (&wmask, (unsigned long long *) &(base[i]));
+		}
+	}
+	return 0;
+}
+#endif /* CFG_DRAM_TEST_WALK */
+
+/*********************************************************************/
+/* NAME:   mem_test_walk() -  a simple walking ones test	     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Performs a walking ones through entire physical memory. The     */
+/*   test uses as series of memory marches, mem_march(), to verify   */
+/*   and write the test patterns to memory. The test sequence is as  */
+/*   follows:							     */
+/*     1) march writing 0000...0001				     */
+/*     2) march verifying 0000...0001  , writing  0000...0010	     */
+/*     3) repeat step 2 shifting masks left 1 bit each time unitl    */
+/*	   the write mask equals 1000...0000			     */
+/*     4) march verifying 1000...0000				     */
+/*   The test fails if any of the memory marches return a failure.   */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays which pass on the memory test is executing	     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_test_walk (void)
+{
+	unsigned long long mask;
+	volatile unsigned long long *pmem =
+		(volatile unsigned long long *) CFG_MEMTEST_START;
+	const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8;
+
+	unsigned int i;
+
+	mask = 0x01;
+
+	printf ("Initial Pass");
+	mem_march (pmem, size, 0x0, 0x1, 0, 1);
+
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+	printf ("		");
+	printf ("         ");
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+
+	for (i = 0; i < 63; i++) {
+		printf ("Pass %2d", i + 2);
+		if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
+			/*printf("mask: 0x%x, pass: %d, ", mask, i); */
+			return 1;
+		}
+		mask = mask << 1;
+		printf ("\b\b\b\b\b\b\b");
+	}
+
+	printf ("Last Pass");
+	if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
+		/* printf("mask: 0x%x", mask); */
+		return 1;
+	}
+	printf ("\b\b\b\b\b\b\b\b\b");
+	printf ("	     ");
+	printf ("\b\b\b\b\b\b\b\b\b");
+
+	return 0;
+}
+
+/*********************************************************************/
+/* NAME:    testdram() -  calls any enabled memory tests	     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Runs memory tests if the environment test variables are set to  */
+/*   'y'.							     */
+/*								     */
+/* INPUTS:							     */
+/*   testdramdata    - If set to 'y', data test is run.		     */
+/*   testdramaddress - If set to 'y', address test is run.	     */
+/*   testdramwalk    - If set to 'y', walking ones test is run	     */
+/*								     */
+/* OUTPUTS:							     */
+/*   None							     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int testdram (void)
+{
+	char *s;
+	int rundata    = 0;
+	int runaddress = 0;
+	int runwalk    = 0;
+
+#ifdef CFG_DRAM_TEST_DATA
+	s = getenv ("testdramdata");
+	rundata = (s && (*s == 'y')) ? 1 : 0;
+#endif
+#ifdef CFG_DRAM_TEST_ADDRESS
+	s = getenv ("testdramaddress");
+	runaddress = (s && (*s == 'y')) ? 1 : 0;
+#endif
+#ifdef CFG_DRAM_TEST_WALK
+	s = getenv ("testdramwalk");
+	runwalk = (s && (*s == 'y')) ? 1 : 0;
+#endif
+
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
+		printf ("Testing RAM from 0x%08x to 0x%08x ...  (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END);
+	}
+#ifdef CFG_DRAM_TEST_DATA
+	if (rundata == 1) {
+		printf ("Test DATA ...  ");
+		if (mem_test_data () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+#ifdef CFG_DRAM_TEST_ADDRESS
+	if (runaddress == 1) {
+		printf ("Test ADDRESS ...  ");
+		if (mem_test_address () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+#ifdef CFG_DRAM_TEST_WALK
+	if (runwalk == 1) {
+		printf ("Test WALKING ONEs ...  ");
+		if (mem_test_walk () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
+		printf ("passed\n");
+	}
+	return 0;
+
+}
+#endif /* CFG_DRAM_TEST */
+
+/* ronen - the below functions are used by the bootm function           */
+/*  - we map the base register to fbe00000 (same mapping as in the LSP) */
+/*  - we turn off the RX gig dmas - to prevent the dma from overunning  */
+/*    the kernel data areas.                                            */
+/*  - we diable and invalidate the icache and dcache.                   */
+void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
+{
+	u32 temp;
+
+	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 16)
+		return;
+
+	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 16);
+
+	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
+							new_loc |
+							(INTERNAL_SPACE_DECODE)))))
+	       != temp);
+
+}
+
+void board_prebootm_init ()
+{
+
+/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
+		GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
+
+/* Stop GigE Rx DMA engines */
+	GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
+/*	GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00); */
+/*      GV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00); */
+
+/* Relocate MV64360 internal regs */
+	my_remap_gt_regs_bootm (CFG_GT_REGS, CFG_DFL_GT_REGS);
+
+	icache_disable ();
+	invalidate_l1_instruction_cache ();
+	flush_data_cache ();
+	dcache_disable ();
+}
--- a/board/esd/cpci750/eth.h
+++ b/board/esd/cpci750/eth.h
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * eth.h - header file for the polled mode GT ethernet driver
+ */
+
+#ifndef __EVB64360_ETH_H__
+#define __EVB64360_ETH_H__
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+#include <common.h>
+
+
+int db64360_eth0_poll(void);
+int db64360_eth0_transmit(unsigned int s, volatile char *p);
+void db64360_eth0_disable(void);
+bool network_start(bd_t *bis);
+
+
+#endif /* __EVB64360_ETH_H__ */
--- a/board/esd/cpci750/i2c.c
+++ b/board/esd/cpci750/i2c.c
@@ -0,0 +1,487 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Hacked for the DB64360 board by Ingo.Assmus@keymile.com
+ * extra improvments by Brain Waite
+ * for cpci750 by reinhard.arlt@esd-electronics.com
+ */
+#include <common.h>
+#include <mpc8xx.h>
+#include <malloc.h>
+#include "../../Marvell/include/mv_gen_reg.h"
+#include "../../Marvell/include/core.h"
+
+#define I2C_DELAY	    100
+#undef	DEBUG_I2C
+
+#ifdef DEBUG_I2C
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+/* Assuming that there is only one master on the bus (us) */
+
+static void i2c_init (int speed, int slaveaddr)
+{
+	unsigned int n, m, freq, margin, power;
+	unsigned int actualN = 0, actualM = 0;
+	unsigned int minMargin = 0xffffffff;
+	unsigned int tclk = CFG_TCLK;
+	unsigned int i2cFreq = speed;	/* 100000 max. Fast mode not supported */
+
+	DP (puts ("i2c_init\n"));
+/* gtI2cMasterInit */
+	for (n = 0; n < 8; n++) {
+		for (m = 0; m < 16; m++) {
+			power = 2 << n;	/* power = 2^(n+1) */
+			freq = tclk / (10 * (m + 1) * power);
+			if (i2cFreq > freq)
+				margin = i2cFreq - freq;
+			else
+				margin = freq - i2cFreq;
+			if (margin < minMargin) {
+				minMargin = margin;
+				actualN = n;
+				actualM = m;
+			}
+		}
+	}
+
+	DP (puts ("setup i2c bus\n"));
+
+	/* Setup bus */
+	/* gtI2cReset */
+	GT_REG_WRITE (I2C_SOFT_RESET, 0);
+	asm(" sync");
+	GT_REG_WRITE (I2C_CONTROL, 0);
+	asm(" sync");
+
+	DP (puts ("set baudrate\n"));
+
+	GT_REG_WRITE (I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN);
+	asm(" sync");
+
+	DP (puts ("udelay...\n"));
+
+	udelay (I2C_DELAY);
+
+	GT_REG_WRITE (I2C_CONTROL, (0x1 << 2) | (0x1 << 6));
+	asm(" sync");
+}
+
+
+static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit)
+{
+	unsigned int status, data, bits = 7;
+	unsigned int control;
+	int count = 0;
+
+	DP (puts ("i2c_select_device\n"));
+
+	/* Output slave address */
+
+	if (ten_bit) {
+		bits = 10;
+	}
+
+	GT_REG_READ (I2C_CONTROL, &control);
+	control |=  (0x1 << 2);
+	GT_REG_WRITE (I2C_CONTROL, control);
+	asm(" sync");
+
+	GT_REG_READ (I2C_CONTROL, &control);
+	control |= (0x1 << 5);	/* generate the I2C_START_BIT */
+	GT_REG_WRITE (I2C_CONTROL, control);
+	asm(" sync");
+	RESET_REG_BITS (I2C_CONTROL, (0x01 << 3));
+	asm(" sync");
+
+	GT_REG_READ (I2C_CONTROL, &status);
+	while ((status & 0x08) != 0x08) {
+		GT_REG_READ (I2C_CONTROL, &status);
+		}
+
+
+	count = 0;
+
+	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+	while (((status & 0xff) != 0x08) && ((status & 0xff) != 0x10)){
+		if (count > 200) {
+#ifdef DEBUG_I2C
+			printf ("Failed to set startbit: 0x%02x\n", status);
+#endif
+			GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+			asm(" sync");
+			return (status);
+		}
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+	}
+
+	DP (puts ("i2c_select_device:write addr byte\n"));
+
+	/* assert the address */
+
+	data = (dev_addr << 1);
+	/* set the read bit */
+	data |= read;
+	GT_REG_WRITE (I2C_DATA, data);
+	asm(" sync");
+	RESET_REG_BITS (I2C_CONTROL, BIT3);
+	asm(" sync");
+
+	GT_REG_READ (I2C_CONTROL, &status);
+	while ((status & 0x08) != 0x08) {
+		GT_REG_READ (I2C_CONTROL, &status);
+		}
+
+	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+	count = 0;
+	while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) {
+		if (count > 200) {
+#ifdef DEBUG_I2C
+			printf ("Failed to write address: 0x%02x\n", status);
+#endif
+			GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+			return (status);
+		}
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		asm(" sync");
+		count++;
+	}
+
+	if (bits == 10) {
+		printf ("10 bit I2C addressing not yet implemented\n");
+		return (0xff);
+	}
+
+	return (0);
+}
+
+static uchar i2c_get_data (uchar * return_data, int len)
+{
+
+	unsigned int data, status;
+	int count = 0;
+
+	DP (puts ("i2c_get_data\n"));
+
+	while (len) {
+
+		RESET_REG_BITS (I2C_CONTROL, BIT3);
+		asm(" sync");
+
+		/* Get and return the data */
+
+		GT_REG_READ (I2C_CONTROL, &status);
+		while ((status & 0x08) != 0x08) {
+			GT_REG_READ (I2C_CONTROL, &status);
+			}
+
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+		while ((status & 0xff) != 0x50) {
+			if (count > 20) {
+#ifdef DEBUG_I2C
+				printf ("Failed to get data len status: 0x%02x\n", status);
+#endif
+				GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+				asm(" sync");
+				return 0;
+			}
+			GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+			count++;
+		}
+		GT_REG_READ (I2C_DATA, &data);
+		len--;
+		*return_data = (uchar) data;
+		return_data++;
+
+	}
+	RESET_REG_BITS (I2C_CONTROL, BIT2 | BIT3);
+	asm(" sync");
+	count = 0;
+
+	GT_REG_READ (I2C_CONTROL, &status);
+	while ((status & 0x08) != 0x08) {
+		GT_REG_READ (I2C_CONTROL, &status);
+		}
+
+	while ((status & 0xff) != 0x58) {
+		if (count > 2000) {
+			GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+			return (status);
+		}
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+	}
+	GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/* stop */
+	asm(" sync");
+	RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
+	asm(" sync");
+
+	return (0);
+}
+
+
+static uchar i2c_write_data (unsigned int *data, int len)
+{
+	unsigned int status;
+	int count;
+	unsigned int temp;
+	unsigned int *temp_ptr = data;
+
+	DP (puts ("i2c_write_data\n"));
+
+	while (len) {
+		count = 0;
+		temp = (unsigned int) (*temp_ptr);
+		GT_REG_WRITE (I2C_DATA, temp);
+		asm(" sync");
+		RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
+		asm(" sync");
+
+		GT_REG_READ (I2C_CONTROL, &status);
+		while ((status & 0x08) != 0x08) {
+			GT_REG_READ (I2C_CONTROL, &status);
+			}
+
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+		while ((status & 0xff) != 0x28) {
+			if (count > 200) {
+				GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+				asm(" sync");
+				return (status);
+			}
+			GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+			count++;
+		}
+		len--;
+		temp_ptr++;
+	}
+	return (0);
+}
+
+
+static uchar i2c_write_byte (unsigned char *data, int len)
+{
+	unsigned int status;
+	int count;
+	unsigned int temp;
+	unsigned char *temp_ptr = data;
+
+	DP (puts ("i2c_write_byte\n"));
+
+	while (len) {
+		count = 0;
+		/* Set and assert the data */
+		temp = *temp_ptr;
+		GT_REG_WRITE (I2C_DATA, temp);
+		asm(" sync");
+		RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
+		asm(" sync");
+
+
+		GT_REG_READ (I2C_CONTROL, &status);
+		while ((status & 0x08) != 0x08) {
+			GT_REG_READ (I2C_CONTROL, &status);
+			}
+
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+		while ((status & 0xff) != 0x28) {
+			if (count > 200) {
+				GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+				asm(" sync");
+				return (status);
+			}
+			GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+			count++;
+		}
+		len--;
+		temp_ptr++;
+	}
+	return (0);
+}
+
+static uchar
+i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit,
+		    int alen)
+{
+	uchar status;
+	unsigned int table[2];
+
+	table[1] = (offset     ) & 0x0ff;	/* low byte */
+	table[0] = (offset >> 8) & 0x0ff;	/* high byte */
+
+	DP (puts ("i2c_set_dev_offset\n"));
+
+	status = i2c_select_device (dev_addr, 0, ten_bit);
+	if (status) {
+#ifdef DEBUG_I2C
+22		printf ("Failed to select device setting offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+/* check the address offset length */
+	if (alen == 0)
+		/* no address offset */
+		return (0);
+	else if (alen == 1) {
+		/* 1 byte address offset */
+		status = i2c_write_data (&offset, 1);
+		if (status) {
+#ifdef DEBUG_I2C
+			printf ("Failed to write data: 0x%02x\n", status);
+#endif
+			return status;
+		}
+	} else if (alen == 2) {
+		/* 2 bytes address offset */
+		status = i2c_write_data (table, 2);
+		if (status) {
+#ifdef DEBUG_I2C
+			printf ("Failed to write data: 0x%02x\n", status);
+#endif
+			return status;
+		}
+	} else {
+		/* address offset unknown or not supported */
+		printf ("Address length offset %d is not supported\n", alen);
+		return 1;
+	}
+	return 0;		/* sucessful completion */
+}
+
+uchar
+i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
+	  int len)
+{
+	uchar status = 0;
+	unsigned int i2cFreq = CFG_I2C_SPEED;
+
+	DP (puts ("i2c_read\n"));
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
+
+	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address & offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+
+	status = i2c_select_device (dev_addr, 1, 0);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to select device for data read: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+
+	status = i2c_get_data (data, len);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Data not read: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	return 0;
+}
+
+
+void i2c_stop (void)
+{
+	GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));
+	asm(" sync");
+}
+
+
+uchar
+i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data,
+	   int len)
+{
+	uchar status = 0;
+	unsigned int i2cFreq = CFG_I2C_SPEED;
+
+	DP (puts ("i2c_write\n"));
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
+
+	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address & offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+		}
+
+
+	status = i2c_write_byte (data, len);	/* write the data */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Data not written: 0x%02x\n", status);
+#endif
+		return status;
+		}
+	/* issue a stop bit */
+	i2c_stop ();
+	return 0;
+}
+
+
+int i2c_probe (uchar chip)
+{
+
+#ifdef DEBUG_I2C
+	unsigned int i2c_status;
+#endif
+	uchar status = 0;
+	unsigned int i2cFreq = CFG_I2C_SPEED;
+
+	DP (puts ("i2c_probe\n"));
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
+
+	status = i2c_set_dev_offset (chip, 0, 0, 0);	/* send the slave address + no offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address: 0x%02x\n", status);
+#endif
+		return (int) status;
+	}
+#ifdef DEBUG_I2C
+	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &i2c_status);
+	printf ("address %#x returned %#x\n", chip, i2c_status);
+#endif
+	/* issue a stop bit */
+	i2c_stop ();
+	return 0;		/* successful completion */
+}
--- a/board/esd/cpci750/i2c.h
+++ b/board/esd/cpci750/i2c.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Hacked for the DB64360 board by Ingo.Assmus@keymile.com
+ */
+
+#ifndef __I2C_H__
+#define __I2C_H__
+
+/* function declarations */
+uchar i2c_read(uchar, unsigned int, int, uchar*, int);
+
+#endif
--- a/board/esd/cpci750/ide.c
+++ b/board/esd/cpci750/ide.c
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+/* ide.c - ide support functions */
+
+
+#include <common.h>
+#ifdef CFG_CMD_IDE
+#include <ata.h>
+#include <ide.h>
+#include <pci.h>
+
+extern ulong ide_bus_offset[CFG_IDE_MAXBUS];
+
+int ide_preinit (void)
+{
+	int status;
+	pci_dev_t devbusfn;
+	int l;
+
+	status = 1;
+	for (l = 0; l < CFG_IDE_MAXBUS; l++) {
+		ide_bus_offset[l] = -ATA_STATUS;
+	}
+	devbusfn = pci_find_device (0x1103, 0x0004, 0);
+	if (devbusfn != -1) {
+		status = 0;
+
+		pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
+				       (u32 *) & ide_bus_offset[0]);
+		ide_bus_offset[0] &= 0xfffffffe;
+		ide_bus_offset[0] += CFG_PCI0_IO_SPACE;
+		pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2,
+				       (u32 *) & ide_bus_offset[1]);
+		ide_bus_offset[1] &= 0xfffffffe;
+		ide_bus_offset[1] += CFG_PCI0_IO_SPACE;
+	}
+	return (status);
+}
+
+void ide_set_reset (int flag) {
+	return;
+}
+
+#endif /* of CONFIG_CMDS_IDE */
--- a/board/esd/cpci750/local.h
+++ b/board/esd/cpci750/local.h
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * include/local.h - local configuration options, board specific
+ */
+
+#ifndef __LOCAL_H
+#define __LOCAL_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+/* This tells PPCBoot that the config options are compiled in */
+/* #undef ENV_IS_EMBEDDED */
+/* Don't touch this! PPCBOOT figures this out  based on other
+ * magic. */
+
+/* Uncomment and define any of the below options */
+
+/* #define CONFIG_750CX */ /* The 750CX doesn't support as many things in L2CR */
+#define CONFIG_750FX       /* The 750FX doesn't support as many things in L2CR like 750CX*/
+
+/* These want string arguments */
+/* #define CONFIG_BOOTARGS */
+/* #define CONFIG_BOOTCOMMAND */
+/* #define CONFIG_RAMBOOTCOMMAND */
+/* #define CONFIG_NFSBOOTCOMMAND */
+/* #define CFG_AUTOLOAD */
+/* #define CONFIG_PREBOOT */
+
+/* These don't */
+
+/* #define CONFIG_BOOTDELAY  */
+/* #define CONFIG_BAUDRATE */
+/* #define CONFIG_LOADS_ECHO */
+/* #define CONFIG_ETHADDR */
+/* #define CONFIG_ETH2ADDR */
+/* #define CONFIG_ETH3ADDR */
+/* #define CONFIG_IPADDR */
+/* #define CONFIG_SERVERIP */
+/* #define CONFIG_ROOTPATH */
+/* #define CONFIG_GATEWAYIP */
+/* #define CONFIG_NETMASK */
+/* #define CONFIG_HOSTNAME */
+/* #define CONFIG_BOOTFILE */
+/* #define CONFIG_LOADADDR */
+
+/* these hardware addresses are pretty bogus, please change them to
+   suit your needs */
+
+/* first ethernet */
+/* #define CONFIG_ETHADDR          86:06:2d:7e:c6:53 */
+#define CONFIG_ETHADDR          64:36:00:00:00:01
+
+/* next two ethernet hwaddrs */
+#define CONFIG_ETH1ADDR		86:06:2d:7e:c6:54
+#define CONFIG_ETH2ADDR		86:06:2d:7e:c6:55
+
+#define CONFIG_ENV_OVERWRITE
+#endif	/* __CONFIG_H */
--- a/board/esd/cpci750/misc.S
+++ b/board/esd/cpci750/misc.S
@@ -0,0 +1,245 @@
+#include <config.h>
+#include <74xx_7xx.h>
+#include "version.h"
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#include "../../Marvell/include/mv_gen_reg.h"
+
+#ifdef CONFIG_ECC
+	/* Galileo specific asm code for initializing ECC */
+	.globl board_relocate_rom
+board_relocate_rom:
+	mflr	r7
+	/* update the location of the GT registers */
+	lis	r11, CFG_GT_REGS@h
+	/* if we're using ECC, we must use the DMA engine to copy ourselves */
+	bl	start_idma_transfer_0
+	bl	wait_for_idma_0
+	bl	stop_idma_engine_0
+
+	mtlr	r7
+	blr
+
+	.globl board_init_ecc
+board_init_ecc:
+	mflr	r7
+	/* NOTE: r10 still contains the location we've been relocated to
+	 * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */
+
+	/* now that we're running from ram, init the rest of main memory
+	 * for ECC use */
+	lis	r8, CFG_MONITOR_LEN@h
+	ori	r8, r8, CFG_MONITOR_LEN@l
+
+	divw	r3, r10, r8
+
+	/* set up the counter, and init the starting address */
+	mtctr	r3
+	li	r12, 0
+
+	/* bytes per transfer */
+	mr	r5, r8
+about_to_init_ecc:
+1:	mr	r3, r12
+	mr	r4, r12
+	bl	start_idma_transfer_0
+	bl	wait_for_idma_0
+	bl	stop_idma_engine_0
+	add	r12, r12, r8
+	bdnz	1b
+
+	mtlr	r7
+	blr
+
+	/* r3:	dest addr
+	 * r4:	source addr
+	 * r5:	byte count
+	 * r11: gt regbase
+	 * trashes:	 r6, r5
+	 */
+start_idma_transfer_0:
+	/* set the byte count, including the OWN bit */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_BYTE_COUNT
+	stwbrx	r5, 0, (r6)
+
+	/* set the source address */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS
+	stwbrx	r4, 0, (r6)
+
+	/* set the dest address */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS
+	stwbrx	r3, 0, (r6)
+
+	/* set the next record pointer */
+	li	r5, 0
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0NEXT_RECORD_POINTER
+	stwbrx	r5, 0, (r6)
+
+	/* set the low control register */
+	/* bit 9 is NON chained mode, bit 31 is new style descriptors.
+	   bit 12 is channel enable */
+	ori	r5, r5, (1 << 12) | (1 << 12) | (1 << 11)
+	/* 15 shifted by 16 (oris) == bit 31 */
+	oris	r5, r5, (1 << 15)
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0CONTROL
+	stwbrx	r5, 0, (r6)
+
+	blr
+
+	/* this waits for the bytecount to return to zero, indicating
+	 * that the trasfer is complete */
+wait_for_idma_0:
+	mr	r5, r11
+	lis	r6, 0xff
+	ori	r6, r6, 0xffff
+	ori	r5, r5, CHANNEL0_DMA_BYTE_COUNT
+1:	lwbrx	r4, 0, (r5)
+	and.	r4, r4, r6
+	bne	1b
+
+	blr
+
+	/* this turns off channel 0 of the idma engine */
+stop_idma_engine_0:
+	/* shut off the DMA engine */
+	li	r5, 0
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0CONTROL
+	stwbrx	r5, 0, (r6)
+
+	blr
+#endif
+
+#ifdef CFG_BOARD_ASM_INIT
+	/* NOTE: trashes r3-r7 */
+	.globl board_asm_init
+board_asm_init:
+	/* just move the GT registers to where they belong */
+	lis	r3, CFG_DFL_GT_REGS@h
+	ori	r3, r3, CFG_DFL_GT_REGS@l
+	lis	r4, CFG_GT_REGS@h
+	ori	r4, r4, CFG_GT_REGS@l
+	li	r5, INTERNAL_SPACE_DECODE
+
+	/* test to see if we've already moved */
+	lwbrx	r6, r5, r4
+	andi.	r6, r6, 0xffff
+	/* check loading of R7 is: 0x0F80 should: 0xf800: DONE */
+/*	rlwinm	r7, r4, 8, 16, 31
+	rlwinm	r7, r4, 12, 16, 31	*/ /* original */
+	rlwinm	r7, r4, 16, 16, 31
+	/* -----------------------------------------------------*/
+	cmp	cr0, r7, r6
+	beqlr
+
+	/* nope, have to move the registers */
+	lwbrx	r6, r5, r3
+	andis.	r6, r6, 0xffff
+	or	r6, r6, r7
+	stwbrx	r6, r5, r3
+
+	/* now, poll for the change */
+1:	lwbrx	r7, r5, r4
+	cmp	cr0, r7, r6
+	bne	1b
+
+	lis	r3, CFG_INT_SRAM_BASE@h
+	ori	r3, r3, CFG_INT_SRAM_BASE@l
+	rlwinm  r3, r3, 16, 16, 31
+	lis	r4, CFG_GT_REGS@h
+	ori	r4, r4, CFG_GT_REGS@l
+	li	r5, INTEGRATED_SRAM_BASE_ADDR
+	stwbrx  r3, r5, r4
+
+2:	lwbrx	r6, r5, r4
+	cmp	cr0, r3, r6
+	bne	2b
+
+	/* done! */
+	blr
+#endif
+
+/* For use of the debug LEDs */
+	.global led_on0_relocated
+led_on0_relocated:
+	xor	r21, r21, r21
+	xor	r18, r18, r18
+	lis	r18, 0xFC80
+	ori	r18, r18, 0x8000
+/*	stw	r21, 0x0(r18)   */
+	sync
+	blr
+
+	.global led_off0_relocated
+led_off0_relocated:
+	xor	r21, r21, r21
+	xor	r18, r18, r18
+	lis	r18, 0xFC81
+	ori	r18, r18, 0x4000
+/*	stw	r21, 0x0(r18)   */
+	sync
+	blr
+
+	.global led_on0
+led_on0:
+	xor	r18, r18, r18
+	lis	r18, 0x1c80
+	ori	r18, r18, 0x8000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
+
+	.global led_off0
+led_off0:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0x4000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
+
+	.global led_on1
+led_on1:
+	xor	r18, r18, r18
+	lis	r18, 0x1c80
+	ori	r18, r18, 0xc000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
+
+	.global led_off1
+led_off1:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0x8000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
+
+	.global led_on2
+led_on2:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0x0000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
+
+	.global led_off2
+led_off2:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0xc000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
--- a/board/esd/cpci750/mpsc.c
+++ b/board/esd/cpci750/mpsc.c
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
wdenk	bff96b0e6b	Renamed UC100 => uc100	2004-12-19 10:09:07 +00:00
wdenk	ec0aee7b68	Cleanup: avoid trigraph warning in fs/ext2/ext2fs.c; rename UC100 -> uc100	2004-12-19 09:58:11 +00:00
wdenk	f7d1572bf5	Add support for UC100 board	2004-12-18 22:35:43 +00:00
stroese	8e6b47a89b	One more code cleanup.	2004-12-17 09:13:49 +00:00
wdenk	efe2a4d5cf	Code cleanup.	2004-12-16 21:44:03 +00:00
stroese	bea8e84b52	PCI405 board update	2004-12-16 19:10:22 +00:00
stroese	917b8cc41c	AR405 board update	2004-12-16 19:00:32 +00:00
stroese	8cba1907b8	Patch by Stefan Roese, 16 Dez 2004	2004-12-16 18:47:58 +00:00
stroese	7b46664147	CONFIG_MX_CYCLIC description added	2004-12-16 18:46:55 +00:00
stroese	c419d1d6d0	some new esd boards added	2004-12-16 18:44:40 +00:00
stroese	0621f6f9d3	esd common update	2004-12-16 18:43:13 +00:00
stroese	cd5396fa12	VOH405 board update	2004-12-16 18:41:27 +00:00
stroese	4510a7b736	PMC405 board update	2004-12-16 18:40:02 +00:00
stroese	12537cc5a9	PLU405 board update	2004-12-16 18:39:03 +00:00
stroese	c2642d14c9	PCI405 board update	2004-12-16 18:38:22 +00:00
stroese	25215ee2b0	OCRTC board update	2004-12-16 18:37:41 +00:00
stroese	31193c2cca	HUB405 board update	2004-12-16 18:37:08 +00:00
stroese	ab379df353	DU405 board update	2004-12-16 18:36:28 +00:00
stroese	f2dfe44fd6	DP405 board update	2004-12-16 18:35:58 +00:00
stroese	20aacbf018	CPCIISER4 board update	2004-12-16 18:35:14 +00:00
stroese	7acd6c2168	CPCI440 board update	2004-12-16 18:34:28 +00:00
stroese	c491b442cc	CANBT board update	2004-12-16 18:33:45 +00:00
stroese	86cf82e07f	ASH405 board update	2004-12-16 18:33:12 +00:00
stroese	8d3efe4e9a	AR405 board update	2004-12-16 18:30:36 +00:00
stroese	e399e4c670	ADCIOP board update	2004-12-16 18:27:51 +00:00
stroese	87663b1cbc	CPCI405 board update	2004-12-16 18:27:05 +00:00
stroese	6cfb1f0da6	WUH405 board support added	2004-12-16 18:25:40 +00:00
stroese	809ac5e7b0	VOM405 board support added	2004-12-16 18:24:54 +00:00
stroese	8d8f894b51	TASREG board support added	2004-12-16 18:24:06 +00:00
stroese	1f54ce6df8	HH405 board support added	2004-12-16 18:23:14 +00:00
stroese	771e05be07	CPCI750 board support added	2004-12-16 18:21:17 +00:00
stroese	1bc0f14143	APC405 board support added	2004-12-16 18:20:14 +00:00
stroese	aee2fa27d9	G2000 board support added	2004-12-16 18:17:50 +00:00
stroese	5e746fce05	PMC405 board support added	2004-12-16 18:15:52 +00:00
stroese	b39392a98b	CPU speed calculation updated (fixed a rounding problem)	2004-12-16 18:13:53 +00:00
stroese	0912e483eb	CPCI750 board support added	2004-12-16 18:10:54 +00:00
stroese	8c725b9364	Coldfire MCF5249 support added	2004-12-16 18:09:49 +00:00
stroese	a20b27a36b	esd config files updated	2004-12-16 18:05:42 +00:00
stroese	44acc8d334	new 405ep defines added	2004-12-16 18:03:44 +00:00
stroese	4d535b51e1	new SST and EXCEL devices add	2004-12-16 18:01:48 +00:00
stroese	3d936fd992	- ext2fs support added - Tundra universe support added	2004-12-16 17:59:53 +00:00
stroese	20cc00ddac	"static" from "do_fat_read" removed	2004-12-16 17:57:26 +00:00
stroese	cd42deebd2	Coldfire MCF5249 support added	2004-12-16 17:56:09 +00:00
stroese	e2c22d780e	I2C added	2004-12-16 17:55:22 +00:00
stroese	b7eaad8134	use same spacing for "NAND:" puts	2004-12-16 17:53:17 +00:00
stroese	946c2185dd	CPCI750 board support added	2004-12-16 17:49:38 +00:00
stroese	6bb992ba9d	added CONFIG_PCI_CONFIG_HOST_BRIDGE to enable host bridge configuration	2004-12-16 17:48:41 +00:00
stroese	a842a6d23c	added ".i" same as ".jffs2s" for compatibility with older units (CFG_NAND_SKIP_BAD_DOT_I)	2004-12-16 17:45:46 +00:00
stroese	4aaf29b2f5	memory commands "mdc" and "mwc" added for cyclic read/write	2004-12-16 17:42:39 +00:00
stroese	fa838874cf	remove "static" from "ide_dev_desc" to use it from external code	2004-12-16 17:40:30 +00:00
stroese	1cdf5d92cf	code cleanup: use CFG_VXWORKS_MAC_PTR instead of multiple board defines	2004-12-16 17:37:54 +00:00
stroese	1740618202	- ext2fs support added - Tundra universe support added	2004-12-16 17:35:57 +00:00
stroese	256e4be814	Tundra universe support added	2004-12-16 17:33:38 +00:00
stroese	bcd0be5cf1	ext2fs support added	2004-12-16 17:33:10 +00:00
stroese	2b9187127f	ext2fs support added	2004-12-16 17:26:24 +00:00
wdenk	138ff60c1e	Add support for INKA4X0 board	2004-12-16 15:52:40 +00:00
wdenk	45ea3fca4a	Cleanup for CMC_PU2 board	2004-12-14 23:28:24 +00:00
wdenk	96085e347d	Fix problem introduced by previous patch.	2004-12-13 09:49:01 +00:00
wdenk	689aec1b05	Patch by Steven Scholz, 12 Dec 2004: Fix typo in AT91 memory setup.	2004-12-13 00:18:44 +00:00
wdenk	7e6bf358d8	Patch by Martin Krause, 27 Oct 2004: - add support for "STK52xx" board (including PS/2 multiplexer) - add hardware detection for TQM5200	2004-12-12 22:06:17 +00:00
wdenk	25d6712a81	* Clean up CMC PU2 flash driver * Update MAINTAINERS file * Fix bug in MPC823 LCD driver	2004-12-10 11:40:40 +00:00
wdenk	ed54e62125	* Fix udelay() on AT91RM9200 for delays < 1 ms. * Enable long help on CMC PU2 board; fix reset issue; increase CPU speed from 179 to 207 MHz.	2004-11-24 23:35:19 +00:00
wdenk	bb310d462b	Fix smc91111 ethernet driver for Xaeniax board (need to handle unaligned tail part specially).	2004-11-22 22:20:07 +00:00
wdenk	9d5028c2f7	* Update for AT91RM9200DK and CMC_PU2 boards: - Enable booting directly from flash - fix CMC_PU2 flash driver * Fix mkimage usage message	2004-11-21 00:06:33 +00:00
wdenk	cacfab588a	Map SRAM on NC650 board	2004-11-17 20:44:20 +00:00
wdenk	1f6d4258c2	Work around for Ethernet problems on Xaeniax board	2004-11-02 13:00:33 +00:00
wdenk	983fda8391	Patch by TsiChung Liew, 23 Sep 2004: - add support for MPC8220 CPU - Add support for Alaska and Yukon boards	2004-10-28 00:09:35 +00:00
wdenk	e3c9b9f928	* Fix configuration for ERIC board (needs more room) * Adjust MIPS compiler options at run-time depending on tools version ("-march=4kc -mtune=4kc -Wa,-mips_allow_branch_to_undefined" for new, "-mcpu=4kc" for old tools)	2004-10-24 23:54:40 +00:00
wdenk	14699a22cf	Add passing of the command line and memory size information to the kernel on xaeniax board.	2004-10-19 22:17:51 +00:00
wdenk	e86e5a0748	Code cleanup for GCC-3.3.x compilers	2004-10-17 21:12:06 +00:00
wdenk	8b74bf31fe	Cleanup	2004-10-11 23:10:30 +00:00
wdenk	4cfaf55e5c	* Enable NAND flash support for NC650 board. * Patch by Thomas Lange 07 Oct 2004: Updated README for DBAu1x00 boards to match current status	2004-10-11 23:03:10 +00:00
wdenk	d407bf52b5	* Patch by Philippe Robin, 28 Sept 2004: Fix Flash support for Versatile. * Patch by Roger Blofeld, 16 Sep 2004: Fix timeout for DHCP command retry	2004-10-11 22:51:13 +00:00
wdenk	2ee665339b	* Patch by Pantelis Antoniou, 14 Sep 2004: Fix early serial hang when CONFIG_SERIAL_MULTI is defined. * Patch by Pantelis Antoniou, 14 Sep 2004: Kick watchdog when bz-decompressing	2004-10-11 22:43:02 +00:00
wdenk	9455b7f39c	Fix CFG_HZ problems on AT91RM9200 systems [Remember: CFG_HZ should be 1000 on ALL systems!]	2004-10-11 22:25:49 +00:00
wdenk	e1599e83d6	* Patch by Gridish Shlomi, 30 Aug 2004: - Add support to revA version of PQ27 and PQ27E. - Reverted MPC8260ADS baudrate back to original 115200 * Patch by Hojin, 17 Sep 2004: Fix typo in cfi_flash.c * Patch by Mark Jonas, 09 September 2004: mtest's data line test (with CFG_ALT_MEMTEST set) returned a wrong error message * Patch by Mark Jonas, 31 August 2004: Added option CFG_XLB_PIPELINING to enable XLB pipelining. This improves FTP performance for MPC5200 systems. Enabled for IceCube by default.	2004-10-10 23:27:33 +00:00
wdenk	c15f3120ec	* Patch by Michael Bendzick, 30 Aug 2004: - Improve platform.S code for omap1510inn that detects whether code is running from SDRAM or not. Patch allows SDRAM to be configured if code is running out of SRAM at 0x20000000. * Patch by Frederick Klatt, 30 Aug 2004: Add support for the Wind River SBC8540/SBC8560 boards	2004-10-10 22:44:24 +00:00
wdenk	656658dd15	* Configure SX1 board to use drivers/cfi_flash.c * Patches by Michael Bendzick, 30 Aug 2004: - Configure omap1510inn board to use drivers/cfi_flash.c - Make drivers/cfi_flash.c protect environment and redundant environment. * Patch by Steven Scholz, 23 Jun 2004: - Add script (tools/img2brec.sh) to programm U-Boot into (Synch)Flash using the Bootstrap Mode of the MC9328MX1/L	2004-10-10 22:16:06 +00:00
wdenk	5c952cf024	Patches by Scott McNutt, 24 Aug 2004: - Add support for Altera Nios-II processors. - Add support for Psyent PCI-5441 board. - Add support for Psyent PK1C20 board.	2004-10-10 21:27:30 +00:00
wdenk	03f5c55021	Patches by Jon Loeliger, 24 Aug 2004: - Add support for the MPC8541 and MPC8555 CDS boards - Cleanup eth?addr handling: make dependent on CONFIG_ETH?ADDR	2004-10-10 21:21:55 +00:00
wdenk	cf33678e51	* Patch by Jon Loeliger, 24 Aug 2004: - Fix PCI window on MPC85xx; remove unneeded PCI initialization from board_early_init_f() - Provide SW workaround for PCI initialization on 85xx CDS - Convert MPC85xxADS to use common CFI flash driver * Cleanup: avoid compiler warnings * Add CMC PU2 board to MAKEALL script	2004-10-10 20:23:57 +00:00
wdenk	08b6aa6154	Patches by George G. Davis, 24 Aug 2004: - Enable ramdisk/initrd tagged param support for omap1610h2_config - Remove static network setup defaults from mx1ads_config	2004-10-10 18:49:14 +00:00
wdenk	731215ebde	Patch by George G. Davis, 24 Aug 2004: - update ARM boards to use constants from mach-types.h	2004-10-10 18:41:04 +00:00
wdenk	b65085130a	Code Cleanup Patch by Gary Jennejohn, 04 Oct 2004: - fix I2C on at91rm9200 - add support for Ricoh RS5C372A RTC	2004-10-10 18:03:33 +00:00
wdenk	2cbe571a56	* Patch by Gary Jennejohn, 01 Oct 2004: - add support for CMC PU2 board - add support for I2C on at91rm9200 * Patch by Gary Jennejohn, 28 Sep 2004: fix baudrate handling on at91rm9200	2004-10-10 17:05:18 +00:00
wdenk	659883c298	Patch by Yuli Barcohen, 22 Aug 2004: - remove ZPC.1900 board-specific flash driver; switch the port to generic CFI driver; - port clean-up	2004-10-09 23:33:42 +00:00
wdenk	f325e18beb	Patch by Hinko Kocevar, 21 Aug 2004: Add calc_fbsize() function used with VIDEOLFB_TAG on TRAB	2004-10-09 23:28:40 +00:00
wdenk	8655b6f860	* Clean up tools/bmp_logo.c to not add trailing white space * Patch by Hinko Kocevar, 21 Aug 2004: - Group common framebuffer functions in common/lcd.c - Group common framebuffer macros and #defines in include/lcd.h - Provide calc_fbsize() for video ATAG	2004-10-09 23:25:58 +00:00
wdenk	30d56fae23	Patch by Sam Song, 21 August 2004: - Fix a typo in README - Align "(RO)" output for "flinfo" after "protect on" - Add RESET support for RPXlite_DW board; adjust CPU:BUS frequency ratio 1:1 when core frequency less than 50MHz	2004-10-09 22:44:59 +00:00
wdenk	63cfcbb4e2	Patches by himba, 21 Aug 2004: - fix some "use of label at end of compound statement" warnings - Define type of LCD panel on lubbock board if CONFIG_LCD is used	2004-10-09 22:32:26 +00:00
wdenk	1d9f410500	Patch by Steven Scholz, 16 Aug 2004: - Introducing the concept of SoCs "./cpu/$(CPU)/$(SOC)" - creating subdirs for SoCs ./cpu/arm920t/imx and ./cpu/arm920t/s3c24x0 - moving SoC specific code out of cpu/arm920t/ into cpu/arm920t/$(SOC)/ - moving drivers/s3c24x0_i2c.c and drivers/serial_imx.c out of drivers/ into cpu/arm920t/$(SOC)/	2004-10-09 22:21:29 +00:00
wdenk	3e01d75ff2	Patch by Andreas Engel, 16 Aug 2004: parameter type cleanup for NetSetTimeout()	2004-10-09 21:56:21 +00:00
wdenk	a5bbcc3c53	* Patches by Sean Chang, 09 Aug 2004: - Added support for both 8 and 16 bit mode access to System ACE CF through MPU. - Fixed missing System ACE CF device during get FAT partition info in fat_register_device function. - Enabled System ACE CF support on ML300. * Patch by Sean Chang, 09 Aug 2004: Synch defines for saveenv and do_saveenv functions so they get compiled under the same statement.	2004-09-29 22:55:14 +00:00
wdenk	a06752e36b	* Patch by Sean Chang, 9 Aug 2004: - Added I2C support for ML300. - Added support for ML300 to read out its environment information stored on the EEPROM. - Added support to use board specific parameters as part of U-Boot's environment information. - Updated MLD files to support configuration for new features above. * Patches by Travis Sawyer, 5 Aug 2004: - Remove incorrect bridge settings for eth group 6 - Add call to setup bridge in ppc_440x_eth_initialize - Fix ppc_440x_eth_init to reset the phy only if its the first time through, otherwise, just check the phy for the autonegotiated speed/duplex. This allows the use of netconsole - only print the speed/duplex the first time the phy is reset.	2004-09-29 22:43:59 +00:00
wdenk	da93ed8147	* Patch by Shlomo Kut, 29 Mar 2004: Add support for MKS Instruments "Quantum" board * Fix build problem with Cogent boards; avoid using <asm/byteorder.h> when using the host compiler	2004-09-29 11:02:56 +00:00
wdenk	a5725fabc0	* Patch by Ganapathi C, 04 Aug 2004: Fix NFS timeout issue	2004-09-28 21:51:42 +00:00
wdenk	e1a3f6b39b	* Patch by Yuli Barcohen, 19 Jul 2004: - Fix host tools building in Cygwin environment - Fix header files search order for host tools * Patch by Tom Armistead, 19 Jul 2004: Fix kgdb.S support for 74xx_75x cpu	2004-09-28 21:39:45 +00:00
wdenk	c65fdc74aa	* Patch by Jon Loeliger, 15 Jul 2004: Fix MPC85xx I2C driver	2004-09-28 21:26:26 +00:00
wdenk	64f70bede3	Fix problems with CDROM drive as slave device on Lite5200 IDE bus.	2004-09-28 20:34:50 +00:00
wdenk	cce625e557	* Patch by Stephen Williams, 15 July 2004 Set the PCI class code for JSE board as part of PCI interface setup * Patch by Michael Bendzick, 15 Jul 2004: Fix problem with writes with odd sizes in drivers/cfi_flash.c when CFG_FLASH_USE_BUFFER_WRITE is set	2004-09-28 19:00:19 +00:00
wdenk	66ca92a5ba	* Patch by Yuli Barcohen, 13 Jul 2004: Allow clock setting on MPC866/MPC885 series chips according to environment variable `cpuclk' * Patch by Yuli Barcohen, 20 Apr 2004: Remove unnecessary redefine of CPM_DATAONLY_SIZE for MPC826x	2004-09-28 17:59:53 +00:00
wdenk	4ec3a7f0fd	Patch by Vincent Dubey, 24 Sep 2004: Add support for xaeniax board	2004-09-28 16:44:41 +00:00
wdenk	79536a6eb0	* Add comment about non-GPL character of standalone applications to COPYING file * Fix FEC ethernet problem on NSCU board.	2004-09-27 20:20:11 +00:00
wdenk	4734cb78d8	Patch by Gary Jennejohn, 09 Sep 2004: allow to use USART1 as console port on at91rm9200dk boards	2004-09-21 23:33:32 +00:00
wdenk	a9c37d561d	Fix [noeol] problem in board/esd/ar405/fpgadata_xl30.c	2004-09-16 12:57:35 +00:00
stroese	c354839349	Patch by Stefan Roese, 16 Sep 2004	2004-09-16 12:37:13 +00:00
stroese	8b1ccd8693	Update AR405 board.	2004-09-16 12:34:51 +00:00
stroese	e623a1a394	esd misc file esd common routines added.	2004-09-16 12:33:54 +00:00
wdenk	1d6f97209e	Fix SysClk handling for PPChameleon and CATcenter boards	2004-09-09 17:44:35 +00:00